1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClassStorage<135, 1296, 2329, 1070, 16, 979> X86MCRegisterClassStorage;
12
13static const MVT::SimpleValueType X86VTLists[] = {
14 /* 0 */ MVT::i8, MVT::Other,
15 /* 2 */ MVT::i16, MVT::Other,
16 /* 4 */ MVT::i32, MVT::Other,
17 /* 6 */ MVT::i64, MVT::Other,
18 /* 8 */ MVT::f16, MVT::Other,
19 /* 10 */ MVT::f80, MVT::f64, MVT::f32, MVT::Other,
20 /* 14 */ MVT::f64, MVT::Other,
21 /* 16 */ MVT::f80, MVT::Other,
22 /* 18 */ MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::v8bf16, MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::f128, MVT::Other,
23 /* 28 */ MVT::v1i1, MVT::Other,
24 /* 30 */ MVT::v2i1, MVT::Other,
25 /* 32 */ MVT::v4i1, MVT::Other,
26 /* 34 */ MVT::v8i1, MVT::Other,
27 /* 36 */ MVT::v16i1, MVT::Other,
28 /* 38 */ MVT::v32i1, MVT::Other,
29 /* 40 */ MVT::v64i1, MVT::Other,
30 /* 42 */ MVT::v8f32, MVT::v4f64, MVT::v16f16, MVT::v16bf16, MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::Other,
31 /* 51 */ MVT::v16f32, MVT::v8f64, MVT::v32f16, MVT::v32bf16, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
32 /* 60 */ MVT::v16f32, MVT::v8f64, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
33 /* 67 */ MVT::x86mmx, MVT::Other,
34 /* 69 */ MVT::Untyped, MVT::Other,
35 /* 71 */ MVT::x86amx, MVT::Other,
36};
37
38#ifdef __GNUC__
39#pragma GCC diagnostic push
40#pragma GCC diagnostic ignored "-Woverlength-strings"
41#endif
42static constexpr char X86SubRegIndexStrings[] = {
43 /* 0 */ "sub_mask_0\000"
44 /* 11 */ "sub_mask_1\000"
45 /* 22 */ "sub_16bit_hi\000"
46 /* 35 */ "sub_8bit_hi\000"
47 /* 47 */ "sub_xmm\000"
48 /* 55 */ "sub_ymm\000"
49 /* 63 */ "sub_32bit\000"
50 /* 73 */ "sub_16bit\000"
51 /* 83 */ "sub_8bit\000"
52 /* 92 */ "sub_8bit_hi_phony\000"
53};
54#ifdef __GNUC__
55#pragma GCC diagnostic pop
56#endif
57
58
59static constexpr uint32_t X86SubRegIndexNameOffsets[] = {
60 83,
61 35,
62 92,
63 73,
64 22,
65 63,
66 0,
67 11,
68 47,
69 55,
70};
71
72static const TargetRegisterInfo::SubRegCoveredBits X86SubRegIdxRangeTable[] = {
73 { .Offset: 4294967295, .Size: 4294967295 },
74 { .Offset: 0, .Size: 8 }, // sub_8bit
75 { .Offset: 8, .Size: 8 }, // sub_8bit_hi
76 { .Offset: 8, .Size: 8 }, // sub_8bit_hi_phony
77 { .Offset: 0, .Size: 16 }, // sub_16bit
78 { .Offset: 16, .Size: 16 }, // sub_16bit_hi
79 { .Offset: 0, .Size: 32 }, // sub_32bit
80 { .Offset: 0, .Size: 4294967295 }, // sub_mask_0
81 { .Offset: 4294967295, .Size: 4294967295 }, // sub_mask_1
82 { .Offset: 0, .Size: 128 }, // sub_xmm
83 { .Offset: 0, .Size: 256 }, // sub_ymm
84 { .Offset: 4294967295, .Size: 4294967295 },
85 { .Offset: 0, .Size: 8 }, // sub_8bit
86 { .Offset: 8, .Size: 8 }, // sub_8bit_hi
87 { .Offset: 8, .Size: 8 }, // sub_8bit_hi_phony
88 { .Offset: 0, .Size: 16 }, // sub_16bit
89 { .Offset: 16, .Size: 16 }, // sub_16bit_hi
90 { .Offset: 0, .Size: 32 }, // sub_32bit
91 { .Offset: 0, .Size: 4294967295 }, // sub_mask_0
92 { .Offset: 4294967295, .Size: 4294967295 }, // sub_mask_1
93 { .Offset: 0, .Size: 128 }, // sub_xmm
94 { .Offset: 0, .Size: 256 }, // sub_ymm
95 { .Offset: 4294967295, .Size: 4294967295 },
96 { .Offset: 0, .Size: 8 }, // sub_8bit
97 { .Offset: 8, .Size: 8 }, // sub_8bit_hi
98 { .Offset: 8, .Size: 8 }, // sub_8bit_hi_phony
99 { .Offset: 0, .Size: 16 }, // sub_16bit
100 { .Offset: 16, .Size: 16 }, // sub_16bit_hi
101 { .Offset: 0, .Size: 32 }, // sub_32bit
102 { .Offset: 0, .Size: 4294967295 }, // sub_mask_0
103 { .Offset: 4294967295, .Size: 4294967295 }, // sub_mask_1
104 { .Offset: 0, .Size: 128 }, // sub_xmm
105 { .Offset: 0, .Size: 256 }, // sub_ymm
106};
107
108
109static const LaneBitmask X86SubRegIndexLaneMaskTable[] = {
110 LaneBitmask::getAll(),
111 LaneBitmask(0x0000000000000001), // sub_8bit
112 LaneBitmask(0x0000000000000002), // sub_8bit_hi
113 LaneBitmask(0x0000000000000004), // sub_8bit_hi_phony
114 LaneBitmask(0x0000000000000007), // sub_16bit
115 LaneBitmask(0x0000000000000008), // sub_16bit_hi
116 LaneBitmask(0x000000000000000F), // sub_32bit
117 LaneBitmask(0x0000000000000010), // sub_mask_0
118 LaneBitmask(0x0000000000000020), // sub_mask_1
119 LaneBitmask(0x0000000000000040), // sub_xmm
120 LaneBitmask(0x0000000000000040), // sub_ymm
121 };
122
123
124
125static const TargetRegisterInfo::RegClassInfo X86RegClassInfos[] = {
126 // Mode = 0 (DefaultMode)
127 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8
128 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GRH8
129 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_NOREX2
130 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_NOREX
131 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_H
132 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_L
133 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GRH16
134 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16
135 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_NOREX2
136 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_NOREX
137 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 28 }, // VK1
138 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 36 }, // VK16
139 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 30 }, // VK2
140 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 32 }, // VK4
141 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 34 }, // VK8
142 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 36 }, // VK16WM
143 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 28 }, // VK1WM
144 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 30 }, // VK2WM
145 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 32 }, // VK4WM
146 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 34 }, // VK8WM
147 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // SEGMENT_REG
148 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_ABCD
149 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // FPCCR
150 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 8 }, // FR16X
151 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 8 }, // FR16
152 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK16PAIR
153 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK1PAIR
154 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK2PAIR
155 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK4PAIR
156 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK8PAIR
157 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK1PAIR_with_sub_mask_0_in_VK1WM
158 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP
159 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS
160 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
161 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // FR32X
162 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32
163 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOSP
164 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
165 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // DEBUG_REG
166 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // FR32
167 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2
168 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2_NOSP
169 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
170 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX
171 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 38 }, // VK32
172 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX_NOSP
173 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // RFP32
174 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 38 }, // VK32WM
175 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD
176 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_TC
177 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_TC
178 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_AD
179 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef
180 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP
181 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BSI
182 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_CB
183 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DC
184 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DIBP
185 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_SIDI
186 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
187 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // CCR
188 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // DFCCR
189 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_BSI
190 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_AD_and_GR32_ArgRef
191 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef_and_GR32_CB
192 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_DIBP
193 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_TC
194 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BSI_and_GR32_SIDI
195 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DIBP_and_GR32_SIDI
196 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
197 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_with_sub_32bit
198 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 14 }, // RFP64
199 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64
200 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 14 }, // FR64X
201 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_8bit
202 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOSP
203 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2
204 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // CONTROL_REG
205 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 14 }, // FR64
206 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX2
207 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP
208 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe
209 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC
210 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX
211 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64
212 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_with_sub_8bit
213 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TC
214 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_with_sub_8bit
215 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_TCW64
216 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX
217 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 40 }, // VK64
218 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 67 }, // VR64
219 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TC
220 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TCW64
221 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_NOSP
222 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TC
223 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_and_GR64_TC_with_sub_8bit
224 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 40 }, // VK64WM
225 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
226 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
227 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TCW64
228 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
229 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TCW64
230 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ABCD
231 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_TC
232 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
233 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_AD
234 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef
235 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS_RBP
236 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef
237 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP
238 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI
239 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_CB
240 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP
241 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_SIDI
242 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_A
243 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef_and_GR64_TC
244 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS
245 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
246 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
247 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
248 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
249 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
250 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
251 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
252 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 10 }, // RST
253 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 16 }, // RFP80
254 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 16 }, // RFP80_7
255 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*X86VTLists+*/.VTListOffset: 18 }, // VR128X
256 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*X86VTLists+*/.VTListOffset: 18 }, // VR128
257 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*X86VTLists+*/.VTListOffset: 42 }, // VR256X
258 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*X86VTLists+*/.VTListOffset: 42 }, // VR256
259 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*X86VTLists+*/.VTListOffset: 51 }, // VR512
260 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*X86VTLists+*/.VTListOffset: 60 }, // VR512_0_15
261 { .RegSize: 8192, .SpillSize: 8192, .SpillAlignment: 8192, /*X86VTLists+*/.VTListOffset: 71 }, // TILE
262 // Mode = 1 (X86_64)
263 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8
264 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GRH8
265 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_NOREX2
266 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_NOREX
267 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_H
268 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_L
269 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GRH16
270 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16
271 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_NOREX2
272 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_NOREX
273 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 28 }, // VK1
274 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 36 }, // VK16
275 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 30 }, // VK2
276 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 32 }, // VK4
277 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 34 }, // VK8
278 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 36 }, // VK16WM
279 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 28 }, // VK1WM
280 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 30 }, // VK2WM
281 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 32 }, // VK4WM
282 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 34 }, // VK8WM
283 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // SEGMENT_REG
284 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_ABCD
285 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // FPCCR
286 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 8 }, // FR16X
287 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 8 }, // FR16
288 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK16PAIR
289 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK1PAIR
290 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK2PAIR
291 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK4PAIR
292 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK8PAIR
293 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK1PAIR_with_sub_mask_0_in_VK1WM
294 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP
295 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS
296 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
297 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // FR32X
298 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32
299 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOSP
300 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
301 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // DEBUG_REG
302 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // FR32
303 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2
304 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2_NOSP
305 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
306 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX
307 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 38 }, // VK32
308 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX_NOSP
309 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // RFP32
310 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 38 }, // VK32WM
311 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD
312 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_TC
313 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_TC
314 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_AD
315 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef
316 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP
317 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BSI
318 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_CB
319 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DC
320 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DIBP
321 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_SIDI
322 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
323 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // CCR
324 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // DFCCR
325 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_BSI
326 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_AD_and_GR32_ArgRef
327 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef_and_GR32_CB
328 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_DIBP
329 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_TC
330 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BSI_and_GR32_SIDI
331 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DIBP_and_GR32_SIDI
332 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
333 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_with_sub_32bit
334 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 14 }, // RFP64
335 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64
336 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 14 }, // FR64X
337 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_8bit
338 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOSP
339 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2
340 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // CONTROL_REG
341 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 14 }, // FR64
342 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX2
343 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP
344 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe
345 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC
346 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX
347 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64
348 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_with_sub_8bit
349 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TC
350 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_with_sub_8bit
351 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_TCW64
352 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX
353 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 40 }, // VK64
354 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 67 }, // VR64
355 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TC
356 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TCW64
357 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_NOSP
358 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TC
359 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_and_GR64_TC_with_sub_8bit
360 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 40 }, // VK64WM
361 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
362 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
363 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TCW64
364 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
365 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TCW64
366 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ABCD
367 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_TC
368 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
369 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_AD
370 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef
371 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS_RBP
372 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef
373 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP
374 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI
375 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_CB
376 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP
377 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_SIDI
378 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_A
379 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef_and_GR64_TC
380 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS
381 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
382 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
383 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
384 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
385 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
386 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
387 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
388 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 10 }, // RST
389 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 16 }, // RFP80
390 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 16 }, // RFP80_7
391 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*X86VTLists+*/.VTListOffset: 18 }, // VR128X
392 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*X86VTLists+*/.VTListOffset: 18 }, // VR128
393 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*X86VTLists+*/.VTListOffset: 42 }, // VR256X
394 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*X86VTLists+*/.VTListOffset: 42 }, // VR256
395 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*X86VTLists+*/.VTListOffset: 51 }, // VR512
396 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*X86VTLists+*/.VTListOffset: 60 }, // VR512_0_15
397 { .RegSize: 8192, .SpillSize: 8192, .SpillAlignment: 8192, /*X86VTLists+*/.VTListOffset: 71 }, // TILE
398 // Mode = 2 (X86_64_X32)
399 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8
400 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GRH8
401 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_NOREX2
402 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_NOREX
403 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_H
404 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_L
405 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GRH16
406 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16
407 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_NOREX2
408 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_NOREX
409 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 28 }, // VK1
410 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 36 }, // VK16
411 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 30 }, // VK2
412 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 32 }, // VK4
413 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 34 }, // VK8
414 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 36 }, // VK16WM
415 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 28 }, // VK1WM
416 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 30 }, // VK2WM
417 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 32 }, // VK4WM
418 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 34 }, // VK8WM
419 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // SEGMENT_REG
420 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_ABCD
421 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // FPCCR
422 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 8 }, // FR16X
423 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 8 }, // FR16
424 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK16PAIR
425 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK1PAIR
426 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK2PAIR
427 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK4PAIR
428 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK8PAIR
429 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK1PAIR_with_sub_mask_0_in_VK1WM
430 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP
431 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS
432 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
433 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // FR32X
434 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32
435 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOSP
436 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
437 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // DEBUG_REG
438 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // FR32
439 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2
440 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2_NOSP
441 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
442 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX
443 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 38 }, // VK32
444 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX_NOSP
445 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // RFP32
446 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 38 }, // VK32WM
447 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD
448 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_TC
449 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_TC
450 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_AD
451 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef
452 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP
453 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BSI
454 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_CB
455 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DC
456 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DIBP
457 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_SIDI
458 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
459 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // CCR
460 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // DFCCR
461 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_BSI
462 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_AD_and_GR32_ArgRef
463 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef_and_GR32_CB
464 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_DIBP
465 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_TC
466 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BSI_and_GR32_SIDI
467 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DIBP_and_GR32_SIDI
468 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
469 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_with_sub_32bit
470 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 14 }, // RFP64
471 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64
472 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 14 }, // FR64X
473 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_8bit
474 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOSP
475 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2
476 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // CONTROL_REG
477 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 14 }, // FR64
478 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX2
479 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP
480 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe
481 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC
482 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX
483 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64
484 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_with_sub_8bit
485 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TC
486 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_with_sub_8bit
487 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_TCW64
488 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX
489 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 40 }, // VK64
490 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 67 }, // VR64
491 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TC
492 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TCW64
493 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_NOSP
494 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TC
495 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_and_GR64_TC_with_sub_8bit
496 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 40 }, // VK64WM
497 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
498 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
499 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TCW64
500 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
501 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TCW64
502 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ABCD
503 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_TC
504 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
505 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_AD
506 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef
507 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS_RBP
508 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef
509 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP
510 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI
511 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_CB
512 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP
513 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_SIDI
514 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_A
515 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef_and_GR64_TC
516 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS
517 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
518 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
519 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
520 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
521 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
522 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
523 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
524 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 10 }, // RST
525 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 16 }, // RFP80
526 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 16 }, // RFP80_7
527 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*X86VTLists+*/.VTListOffset: 18 }, // VR128X
528 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*X86VTLists+*/.VTListOffset: 18 }, // VR128
529 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*X86VTLists+*/.VTListOffset: 42 }, // VR256X
530 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*X86VTLists+*/.VTListOffset: 42 }, // VR256
531 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*X86VTLists+*/.VTListOffset: 51 }, // VR512
532 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*X86VTLists+*/.VTListOffset: 60 }, // VR512_0_15
533 { .RegSize: 8192, .SpillSize: 8192, .SpillAlignment: 8192, /*X86VTLists+*/.VTListOffset: 71 }, // TILE
534};
535
536static inline unsigned GR8AltOrderSelect(const MachineFunction &MF, bool Rev) {
537 return MF.getSubtarget<X86Subtarget>().is64Bit();
538 }
539
540static ArrayRef<MCPhysReg> GR8GetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
541 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R16B, X86::R17B, X86::R18B, X86::R19B, X86::R22B, X86::R23B, X86::R24B, X86::R25B, X86::R26B, X86::R27B, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::R20B, X86::R21B, X86::R28B, X86::R29B, X86::R30B, X86::R31B };
542 const ArrayRef<MCPhysReg> Order[] = {
543 RC.getRegisters(),
544 ArrayRef(AltOrder1)
545 };
546 const unsigned Select = GR8AltOrderSelect(MF, Rev);
547 assert(Select < 2);
548 return Order[Select];
549}
550
551static inline unsigned GR8_NOREX2AltOrderSelect(const MachineFunction &MF, bool Rev) {
552 return MF.getSubtarget<X86Subtarget>().is64Bit();
553 }
554
555static ArrayRef<MCPhysReg> GR8_NOREX2GetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
556 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B };
557 const ArrayRef<MCPhysReg> Order[] = {
558 RC.getRegisters(),
559 ArrayRef(AltOrder1)
560 };
561 const unsigned Select = GR8_NOREX2AltOrderSelect(MF, Rev);
562 assert(Select < 2);
563 return Order[Select];
564}
565
566static inline unsigned GR8_NOREXAltOrderSelect(const MachineFunction &MF, bool Rev) {
567 return MF.getSubtarget<X86Subtarget>().is64Bit();
568 }
569
570static ArrayRef<MCPhysReg> GR8_NOREXGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
571 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL };
572 const ArrayRef<MCPhysReg> Order[] = {
573 RC.getRegisters(),
574 ArrayRef(AltOrder1)
575 };
576 const unsigned Select = GR8_NOREXAltOrderSelect(MF, Rev);
577 assert(Select < 2);
578 return Order[Select];
579}
580
581static inline unsigned FR32XAltOrderSelect(const MachineFunction &MF, bool Rev) {
582 return Rev;
583 }
584
585static ArrayRef<MCPhysReg> FR32XGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
586 static const MCPhysReg AltOrder1[] = { X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 };
587 const ArrayRef<MCPhysReg> Order[] = {
588 RC.getRegisters(),
589 ArrayRef(AltOrder1)
590 };
591 const unsigned Select = FR32XAltOrderSelect(MF, Rev);
592 assert(Select < 2);
593 return Order[Select];
594}
595
596static inline unsigned FR64XAltOrderSelect(const MachineFunction &MF, bool Rev) {
597 return Rev;
598 }
599
600static ArrayRef<MCPhysReg> FR64XGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
601 static const MCPhysReg AltOrder1[] = { X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 };
602 const ArrayRef<MCPhysReg> Order[] = {
603 RC.getRegisters(),
604 ArrayRef(AltOrder1)
605 };
606 const unsigned Select = FR64XAltOrderSelect(MF, Rev);
607 assert(Select < 2);
608 return Order[Select];
609}
610
611static inline unsigned VR128XAltOrderSelect(const MachineFunction &MF, bool Rev) {
612 return Rev;
613 }
614
615static ArrayRef<MCPhysReg> VR128XGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
616 static const MCPhysReg AltOrder1[] = { X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 };
617 const ArrayRef<MCPhysReg> Order[] = {
618 RC.getRegisters(),
619 ArrayRef(AltOrder1)
620 };
621 const unsigned Select = VR128XAltOrderSelect(MF, Rev);
622 assert(Select < 2);
623 return Order[Select];
624}
625
626static inline unsigned VR256XAltOrderSelect(const MachineFunction &MF, bool Rev) {
627 return Rev;
628 }
629
630static ArrayRef<MCPhysReg> VR256XGetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
631 static const MCPhysReg AltOrder1[] = { X86::YMM16, X86::YMM17, X86::YMM18, X86::YMM19, X86::YMM20, X86::YMM21, X86::YMM22, X86::YMM23, X86::YMM24, X86::YMM25, X86::YMM26, X86::YMM27, X86::YMM28, X86::YMM29, X86::YMM30, X86::YMM31, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15 };
632 const ArrayRef<MCPhysReg> Order[] = {
633 RC.getRegisters(),
634 ArrayRef(AltOrder1)
635 };
636 const unsigned Select = VR256XAltOrderSelect(MF, Rev);
637 assert(Select < 2);
638 return Order[Select];
639}
640
641static const uint8_t X86CostPerUseTable[] = {
6420, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
643
644
645static const bool X86InAllocatableClassTable[] = {
646false, true, true, true, true, true, true, false, true, true, true, true, true, true, false, true, true, false, true, true, true, true, true, true, true, true, true, true, false, false, false, true, true, true, false, false, true, false, true, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, true, false, true, true, true, false, true, true, false, true, true, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, };
647
648
649static const TargetRegisterInfoDesc X86RegInfoDesc = { // Extra Descriptors
650.CostPerUse: X86CostPerUseTable, .NumCosts: 1, .InAllocatableClass: X86InAllocatableClassTable};
651
652unsigned X86GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
653 static const uint8_t Rows[1][10] = {
654 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
655 };
656
657 --IdxA; assert(IdxA < 10); (void) IdxA;
658 --IdxB; assert(IdxB < 10);
659 return Rows[0][IdxB];
660}
661
662unsigned X86GenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
663 static const uint8_t Table[10][10] = {
664 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
665 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
666 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
667 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
668 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
669 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
670 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
671 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
672 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
673 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
674 };
675
676 --IdxA; assert(IdxA < 10);
677 --IdxB; assert(IdxB < 10);
678 return Table[IdxA][IdxB];
679 }
680
681 struct MaskRolOp {
682 LaneBitmask Mask;
683 uint8_t RotateLeft;
684 };
685 static const MaskRolOp LaneMaskComposeSequences[] = {
686 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
687 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
688 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
689 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 6
690 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 4 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 8
691 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 5 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 10
692 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 6 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 12
693 };
694 static const uint8_t CompositeSequences[] = {
695 0, // to sub_8bit
696 2, // to sub_8bit_hi
697 4, // to sub_8bit_hi_phony
698 0, // to sub_16bit
699 6, // to sub_16bit_hi
700 0, // to sub_32bit
701 8, // to sub_mask_0
702 10, // to sub_mask_1
703 12, // to sub_xmm
704 0 // to sub_ymm
705 };
706
707LaneBitmask X86GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
708 --IdxA; assert(IdxA < 10 && "Subregister index out of bounds");
709 LaneBitmask Result;
710 for (const MaskRolOp *Ops =
711 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
712 Ops->Mask.any(); ++Ops) {
713 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
714 if (unsigned S = Ops->RotateLeft)
715 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
716 else
717 Result |= LaneBitmask(M);
718 }
719 return Result;
720}
721
722LaneBitmask X86GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
723 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
724 --IdxA; assert(IdxA < 10 && "Subregister index out of bounds");
725 LaneBitmask Result;
726 for (const MaskRolOp *Ops =
727 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
728 Ops->Mask.any(); ++Ops) {
729 LaneBitmask::Type M = LaneMask.getAsInteger();
730 if (unsigned S = Ops->RotateLeft)
731 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
732 else
733 Result |= LaneBitmask(M);
734 }
735 return Result;
736}
737
738const TargetRegisterClass *X86GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
739 static constexpr uint8_t Table[135][10] = {
740 { // GR8
741 0, // sub_8bit
742 0, // sub_8bit_hi
743 0, // sub_8bit_hi_phony
744 0, // sub_16bit
745 0, // sub_16bit_hi
746 0, // sub_32bit
747 0, // sub_mask_0
748 0, // sub_mask_1
749 0, // sub_xmm
750 0, // sub_ymm
751 },
752 { // GRH8
753 0, // sub_8bit
754 0, // sub_8bit_hi
755 0, // sub_8bit_hi_phony
756 0, // sub_16bit
757 0, // sub_16bit_hi
758 0, // sub_32bit
759 0, // sub_mask_0
760 0, // sub_mask_1
761 0, // sub_xmm
762 0, // sub_ymm
763 },
764 { // GR8_NOREX2
765 0, // sub_8bit
766 0, // sub_8bit_hi
767 0, // sub_8bit_hi_phony
768 0, // sub_16bit
769 0, // sub_16bit_hi
770 0, // sub_32bit
771 0, // sub_mask_0
772 0, // sub_mask_1
773 0, // sub_xmm
774 0, // sub_ymm
775 },
776 { // GR8_NOREX
777 0, // sub_8bit
778 0, // sub_8bit_hi
779 0, // sub_8bit_hi_phony
780 0, // sub_16bit
781 0, // sub_16bit_hi
782 0, // sub_32bit
783 0, // sub_mask_0
784 0, // sub_mask_1
785 0, // sub_xmm
786 0, // sub_ymm
787 },
788 { // GR8_ABCD_H
789 0, // sub_8bit
790 0, // sub_8bit_hi
791 0, // sub_8bit_hi_phony
792 0, // sub_16bit
793 0, // sub_16bit_hi
794 0, // sub_32bit
795 0, // sub_mask_0
796 0, // sub_mask_1
797 0, // sub_xmm
798 0, // sub_ymm
799 },
800 { // GR8_ABCD_L
801 0, // sub_8bit
802 0, // sub_8bit_hi
803 0, // sub_8bit_hi_phony
804 0, // sub_16bit
805 0, // sub_16bit_hi
806 0, // sub_32bit
807 0, // sub_mask_0
808 0, // sub_mask_1
809 0, // sub_xmm
810 0, // sub_ymm
811 },
812 { // GRH16
813 0, // sub_8bit
814 0, // sub_8bit_hi
815 0, // sub_8bit_hi_phony
816 0, // sub_16bit
817 0, // sub_16bit_hi
818 0, // sub_32bit
819 0, // sub_mask_0
820 0, // sub_mask_1
821 0, // sub_xmm
822 0, // sub_ymm
823 },
824 { // GR16
825 8, // sub_8bit -> GR16
826 22, // sub_8bit_hi -> GR16_ABCD
827 0, // sub_8bit_hi_phony
828 0, // sub_16bit
829 0, // sub_16bit_hi
830 0, // sub_32bit
831 0, // sub_mask_0
832 0, // sub_mask_1
833 0, // sub_xmm
834 0, // sub_ymm
835 },
836 { // GR16_NOREX2
837 9, // sub_8bit -> GR16_NOREX2
838 22, // sub_8bit_hi -> GR16_ABCD
839 0, // sub_8bit_hi_phony
840 0, // sub_16bit
841 0, // sub_16bit_hi
842 0, // sub_32bit
843 0, // sub_mask_0
844 0, // sub_mask_1
845 0, // sub_xmm
846 0, // sub_ymm
847 },
848 { // GR16_NOREX
849 10, // sub_8bit -> GR16_NOREX
850 22, // sub_8bit_hi -> GR16_ABCD
851 0, // sub_8bit_hi_phony
852 0, // sub_16bit
853 0, // sub_16bit_hi
854 0, // sub_32bit
855 0, // sub_mask_0
856 0, // sub_mask_1
857 0, // sub_xmm
858 0, // sub_ymm
859 },
860 { // VK1
861 0, // sub_8bit
862 0, // sub_8bit_hi
863 0, // sub_8bit_hi_phony
864 0, // sub_16bit
865 0, // sub_16bit_hi
866 0, // sub_32bit
867 0, // sub_mask_0
868 0, // sub_mask_1
869 0, // sub_xmm
870 0, // sub_ymm
871 },
872 { // VK16
873 0, // sub_8bit
874 0, // sub_8bit_hi
875 0, // sub_8bit_hi_phony
876 0, // sub_16bit
877 0, // sub_16bit_hi
878 0, // sub_32bit
879 0, // sub_mask_0
880 0, // sub_mask_1
881 0, // sub_xmm
882 0, // sub_ymm
883 },
884 { // VK2
885 0, // sub_8bit
886 0, // sub_8bit_hi
887 0, // sub_8bit_hi_phony
888 0, // sub_16bit
889 0, // sub_16bit_hi
890 0, // sub_32bit
891 0, // sub_mask_0
892 0, // sub_mask_1
893 0, // sub_xmm
894 0, // sub_ymm
895 },
896 { // VK4
897 0, // sub_8bit
898 0, // sub_8bit_hi
899 0, // sub_8bit_hi_phony
900 0, // sub_16bit
901 0, // sub_16bit_hi
902 0, // sub_32bit
903 0, // sub_mask_0
904 0, // sub_mask_1
905 0, // sub_xmm
906 0, // sub_ymm
907 },
908 { // VK8
909 0, // sub_8bit
910 0, // sub_8bit_hi
911 0, // sub_8bit_hi_phony
912 0, // sub_16bit
913 0, // sub_16bit_hi
914 0, // sub_32bit
915 0, // sub_mask_0
916 0, // sub_mask_1
917 0, // sub_xmm
918 0, // sub_ymm
919 },
920 { // VK16WM
921 0, // sub_8bit
922 0, // sub_8bit_hi
923 0, // sub_8bit_hi_phony
924 0, // sub_16bit
925 0, // sub_16bit_hi
926 0, // sub_32bit
927 0, // sub_mask_0
928 0, // sub_mask_1
929 0, // sub_xmm
930 0, // sub_ymm
931 },
932 { // VK1WM
933 0, // sub_8bit
934 0, // sub_8bit_hi
935 0, // sub_8bit_hi_phony
936 0, // sub_16bit
937 0, // sub_16bit_hi
938 0, // sub_32bit
939 0, // sub_mask_0
940 0, // sub_mask_1
941 0, // sub_xmm
942 0, // sub_ymm
943 },
944 { // VK2WM
945 0, // sub_8bit
946 0, // sub_8bit_hi
947 0, // sub_8bit_hi_phony
948 0, // sub_16bit
949 0, // sub_16bit_hi
950 0, // sub_32bit
951 0, // sub_mask_0
952 0, // sub_mask_1
953 0, // sub_xmm
954 0, // sub_ymm
955 },
956 { // VK4WM
957 0, // sub_8bit
958 0, // sub_8bit_hi
959 0, // sub_8bit_hi_phony
960 0, // sub_16bit
961 0, // sub_16bit_hi
962 0, // sub_32bit
963 0, // sub_mask_0
964 0, // sub_mask_1
965 0, // sub_xmm
966 0, // sub_ymm
967 },
968 { // VK8WM
969 0, // sub_8bit
970 0, // sub_8bit_hi
971 0, // sub_8bit_hi_phony
972 0, // sub_16bit
973 0, // sub_16bit_hi
974 0, // sub_32bit
975 0, // sub_mask_0
976 0, // sub_mask_1
977 0, // sub_xmm
978 0, // sub_ymm
979 },
980 { // SEGMENT_REG
981 0, // sub_8bit
982 0, // sub_8bit_hi
983 0, // sub_8bit_hi_phony
984 0, // sub_16bit
985 0, // sub_16bit_hi
986 0, // sub_32bit
987 0, // sub_mask_0
988 0, // sub_mask_1
989 0, // sub_xmm
990 0, // sub_ymm
991 },
992 { // GR16_ABCD
993 22, // sub_8bit -> GR16_ABCD
994 22, // sub_8bit_hi -> GR16_ABCD
995 0, // sub_8bit_hi_phony
996 0, // sub_16bit
997 0, // sub_16bit_hi
998 0, // sub_32bit
999 0, // sub_mask_0
1000 0, // sub_mask_1
1001 0, // sub_xmm
1002 0, // sub_ymm
1003 },
1004 { // FPCCR
1005 0, // sub_8bit
1006 0, // sub_8bit_hi
1007 0, // sub_8bit_hi_phony
1008 0, // sub_16bit
1009 0, // sub_16bit_hi
1010 0, // sub_32bit
1011 0, // sub_mask_0
1012 0, // sub_mask_1
1013 0, // sub_xmm
1014 0, // sub_ymm
1015 },
1016 { // FR16X
1017 0, // sub_8bit
1018 0, // sub_8bit_hi
1019 0, // sub_8bit_hi_phony
1020 0, // sub_16bit
1021 0, // sub_16bit_hi
1022 0, // sub_32bit
1023 0, // sub_mask_0
1024 0, // sub_mask_1
1025 0, // sub_xmm
1026 0, // sub_ymm
1027 },
1028 { // FR16
1029 0, // sub_8bit
1030 0, // sub_8bit_hi
1031 0, // sub_8bit_hi_phony
1032 0, // sub_16bit
1033 0, // sub_16bit_hi
1034 0, // sub_32bit
1035 0, // sub_mask_0
1036 0, // sub_mask_1
1037 0, // sub_xmm
1038 0, // sub_ymm
1039 },
1040 { // VK16PAIR
1041 0, // sub_8bit
1042 0, // sub_8bit_hi
1043 0, // sub_8bit_hi_phony
1044 0, // sub_16bit
1045 0, // sub_16bit_hi
1046 0, // sub_32bit
1047 26, // sub_mask_0 -> VK16PAIR
1048 26, // sub_mask_1 -> VK16PAIR
1049 0, // sub_xmm
1050 0, // sub_ymm
1051 },
1052 { // VK1PAIR
1053 0, // sub_8bit
1054 0, // sub_8bit_hi
1055 0, // sub_8bit_hi_phony
1056 0, // sub_16bit
1057 0, // sub_16bit_hi
1058 0, // sub_32bit
1059 27, // sub_mask_0 -> VK1PAIR
1060 27, // sub_mask_1 -> VK1PAIR
1061 0, // sub_xmm
1062 0, // sub_ymm
1063 },
1064 { // VK2PAIR
1065 0, // sub_8bit
1066 0, // sub_8bit_hi
1067 0, // sub_8bit_hi_phony
1068 0, // sub_16bit
1069 0, // sub_16bit_hi
1070 0, // sub_32bit
1071 28, // sub_mask_0 -> VK2PAIR
1072 28, // sub_mask_1 -> VK2PAIR
1073 0, // sub_xmm
1074 0, // sub_ymm
1075 },
1076 { // VK4PAIR
1077 0, // sub_8bit
1078 0, // sub_8bit_hi
1079 0, // sub_8bit_hi_phony
1080 0, // sub_16bit
1081 0, // sub_16bit_hi
1082 0, // sub_32bit
1083 29, // sub_mask_0 -> VK4PAIR
1084 29, // sub_mask_1 -> VK4PAIR
1085 0, // sub_xmm
1086 0, // sub_ymm
1087 },
1088 { // VK8PAIR
1089 0, // sub_8bit
1090 0, // sub_8bit_hi
1091 0, // sub_8bit_hi_phony
1092 0, // sub_16bit
1093 0, // sub_16bit_hi
1094 0, // sub_32bit
1095 30, // sub_mask_0 -> VK8PAIR
1096 30, // sub_mask_1 -> VK8PAIR
1097 0, // sub_xmm
1098 0, // sub_ymm
1099 },
1100 { // VK1PAIR_with_sub_mask_0_in_VK1WM
1101 0, // sub_8bit
1102 0, // sub_8bit_hi
1103 0, // sub_8bit_hi_phony
1104 0, // sub_16bit
1105 0, // sub_16bit_hi
1106 0, // sub_32bit
1107 31, // sub_mask_0 -> VK1PAIR_with_sub_mask_0_in_VK1WM
1108 31, // sub_mask_1 -> VK1PAIR_with_sub_mask_0_in_VK1WM
1109 0, // sub_xmm
1110 0, // sub_ymm
1111 },
1112 { // LOW32_ADDR_ACCESS_RBP
1113 34, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
1114 49, // sub_8bit_hi -> GR32_ABCD
1115 0, // sub_8bit_hi_phony
1116 32, // sub_16bit -> LOW32_ADDR_ACCESS_RBP
1117 32, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP
1118 60, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
1119 0, // sub_mask_0
1120 0, // sub_mask_1
1121 0, // sub_xmm
1122 0, // sub_ymm
1123 },
1124 { // LOW32_ADDR_ACCESS
1125 36, // sub_8bit -> GR32
1126 49, // sub_8bit_hi -> GR32_ABCD
1127 0, // sub_8bit_hi_phony
1128 33, // sub_16bit -> LOW32_ADDR_ACCESS
1129 33, // sub_16bit_hi -> LOW32_ADDR_ACCESS
1130 71, // sub_32bit -> LOW32_ADDR_ACCESS_with_sub_32bit
1131 0, // sub_mask_0
1132 0, // sub_mask_1
1133 0, // sub_xmm
1134 0, // sub_ymm
1135 },
1136 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
1137 34, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
1138 49, // sub_8bit_hi -> GR32_ABCD
1139 0, // sub_8bit_hi_phony
1140 34, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
1141 34, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
1142 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
1143 0, // sub_mask_0
1144 0, // sub_mask_1
1145 0, // sub_xmm
1146 0, // sub_ymm
1147 },
1148 { // FR32X
1149 0, // sub_8bit
1150 0, // sub_8bit_hi
1151 0, // sub_8bit_hi_phony
1152 0, // sub_16bit
1153 0, // sub_16bit_hi
1154 0, // sub_32bit
1155 0, // sub_mask_0
1156 0, // sub_mask_1
1157 0, // sub_xmm
1158 0, // sub_ymm
1159 },
1160 { // GR32
1161 36, // sub_8bit -> GR32
1162 49, // sub_8bit_hi -> GR32_ABCD
1163 0, // sub_8bit_hi_phony
1164 36, // sub_16bit -> GR32
1165 36, // sub_16bit_hi -> GR32
1166 0, // sub_32bit
1167 0, // sub_mask_0
1168 0, // sub_mask_1
1169 0, // sub_xmm
1170 0, // sub_ymm
1171 },
1172 { // GR32_NOSP
1173 37, // sub_8bit -> GR32_NOSP
1174 49, // sub_8bit_hi -> GR32_ABCD
1175 0, // sub_8bit_hi_phony
1176 37, // sub_16bit -> GR32_NOSP
1177 37, // sub_16bit_hi -> GR32_NOSP
1178 0, // sub_32bit
1179 0, // sub_mask_0
1180 0, // sub_mask_1
1181 0, // sub_xmm
1182 0, // sub_ymm
1183 },
1184 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
1185 38, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
1186 49, // sub_8bit_hi -> GR32_ABCD
1187 0, // sub_8bit_hi_phony
1188 38, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
1189 38, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
1190 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
1191 0, // sub_mask_0
1192 0, // sub_mask_1
1193 0, // sub_xmm
1194 0, // sub_ymm
1195 },
1196 { // DEBUG_REG
1197 0, // sub_8bit
1198 0, // sub_8bit_hi
1199 0, // sub_8bit_hi_phony
1200 0, // sub_16bit
1201 0, // sub_16bit_hi
1202 0, // sub_32bit
1203 0, // sub_mask_0
1204 0, // sub_mask_1
1205 0, // sub_xmm
1206 0, // sub_ymm
1207 },
1208 { // FR32
1209 0, // sub_8bit
1210 0, // sub_8bit_hi
1211 0, // sub_8bit_hi_phony
1212 0, // sub_16bit
1213 0, // sub_16bit_hi
1214 0, // sub_32bit
1215 0, // sub_mask_0
1216 0, // sub_mask_1
1217 0, // sub_xmm
1218 0, // sub_ymm
1219 },
1220 { // GR32_NOREX2
1221 41, // sub_8bit -> GR32_NOREX2
1222 49, // sub_8bit_hi -> GR32_ABCD
1223 0, // sub_8bit_hi_phony
1224 41, // sub_16bit -> GR32_NOREX2
1225 41, // sub_16bit_hi -> GR32_NOREX2
1226 0, // sub_32bit
1227 0, // sub_mask_0
1228 0, // sub_mask_1
1229 0, // sub_xmm
1230 0, // sub_ymm
1231 },
1232 { // GR32_NOREX2_NOSP
1233 42, // sub_8bit -> GR32_NOREX2_NOSP
1234 49, // sub_8bit_hi -> GR32_ABCD
1235 0, // sub_8bit_hi_phony
1236 42, // sub_16bit -> GR32_NOREX2_NOSP
1237 42, // sub_16bit_hi -> GR32_NOREX2_NOSP
1238 0, // sub_32bit
1239 0, // sub_mask_0
1240 0, // sub_mask_1
1241 0, // sub_xmm
1242 0, // sub_ymm
1243 },
1244 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
1245 43, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
1246 49, // sub_8bit_hi -> GR32_ABCD
1247 0, // sub_8bit_hi_phony
1248 43, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
1249 43, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
1250 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
1251 0, // sub_mask_0
1252 0, // sub_mask_1
1253 0, // sub_xmm
1254 0, // sub_ymm
1255 },
1256 { // GR32_NOREX
1257 44, // sub_8bit -> GR32_NOREX
1258 49, // sub_8bit_hi -> GR32_ABCD
1259 0, // sub_8bit_hi_phony
1260 44, // sub_16bit -> GR32_NOREX
1261 44, // sub_16bit_hi -> GR32_NOREX
1262 0, // sub_32bit
1263 0, // sub_mask_0
1264 0, // sub_mask_1
1265 0, // sub_xmm
1266 0, // sub_ymm
1267 },
1268 { // VK32
1269 0, // sub_8bit
1270 0, // sub_8bit_hi
1271 0, // sub_8bit_hi_phony
1272 0, // sub_16bit
1273 0, // sub_16bit_hi
1274 0, // sub_32bit
1275 0, // sub_mask_0
1276 0, // sub_mask_1
1277 0, // sub_xmm
1278 0, // sub_ymm
1279 },
1280 { // GR32_NOREX_NOSP
1281 46, // sub_8bit -> GR32_NOREX_NOSP
1282 49, // sub_8bit_hi -> GR32_ABCD
1283 0, // sub_8bit_hi_phony
1284 46, // sub_16bit -> GR32_NOREX_NOSP
1285 46, // sub_16bit_hi -> GR32_NOREX_NOSP
1286 0, // sub_32bit
1287 0, // sub_mask_0
1288 0, // sub_mask_1
1289 0, // sub_xmm
1290 0, // sub_ymm
1291 },
1292 { // RFP32
1293 0, // sub_8bit
1294 0, // sub_8bit_hi
1295 0, // sub_8bit_hi_phony
1296 0, // sub_16bit
1297 0, // sub_16bit_hi
1298 0, // sub_32bit
1299 0, // sub_mask_0
1300 0, // sub_mask_1
1301 0, // sub_xmm
1302 0, // sub_ymm
1303 },
1304 { // VK32WM
1305 0, // sub_8bit
1306 0, // sub_8bit_hi
1307 0, // sub_8bit_hi_phony
1308 0, // sub_16bit
1309 0, // sub_16bit_hi
1310 0, // sub_32bit
1311 0, // sub_mask_0
1312 0, // sub_mask_1
1313 0, // sub_xmm
1314 0, // sub_ymm
1315 },
1316 { // GR32_ABCD
1317 49, // sub_8bit -> GR32_ABCD
1318 49, // sub_8bit_hi -> GR32_ABCD
1319 0, // sub_8bit_hi_phony
1320 49, // sub_16bit -> GR32_ABCD
1321 49, // sub_16bit_hi -> GR32_ABCD
1322 0, // sub_32bit
1323 0, // sub_mask_0
1324 0, // sub_mask_1
1325 0, // sub_xmm
1326 0, // sub_ymm
1327 },
1328 { // GR32_TC
1329 50, // sub_8bit -> GR32_TC
1330 51, // sub_8bit_hi -> GR32_ABCD_and_GR32_TC
1331 0, // sub_8bit_hi_phony
1332 50, // sub_16bit -> GR32_TC
1333 50, // sub_16bit_hi -> GR32_TC
1334 0, // sub_32bit
1335 0, // sub_mask_0
1336 0, // sub_mask_1
1337 0, // sub_xmm
1338 0, // sub_ymm
1339 },
1340 { // GR32_ABCD_and_GR32_TC
1341 51, // sub_8bit -> GR32_ABCD_and_GR32_TC
1342 51, // sub_8bit_hi -> GR32_ABCD_and_GR32_TC
1343 0, // sub_8bit_hi_phony
1344 51, // sub_16bit -> GR32_ABCD_and_GR32_TC
1345 51, // sub_16bit_hi -> GR32_ABCD_and_GR32_TC
1346 0, // sub_32bit
1347 0, // sub_mask_0
1348 0, // sub_mask_1
1349 0, // sub_xmm
1350 0, // sub_ymm
1351 },
1352 { // GR32_AD
1353 52, // sub_8bit -> GR32_AD
1354 52, // sub_8bit_hi -> GR32_AD
1355 0, // sub_8bit_hi_phony
1356 52, // sub_16bit -> GR32_AD
1357 52, // sub_16bit_hi -> GR32_AD
1358 0, // sub_32bit
1359 0, // sub_mask_0
1360 0, // sub_mask_1
1361 0, // sub_xmm
1362 0, // sub_ymm
1363 },
1364 { // GR32_ArgRef
1365 53, // sub_8bit -> GR32_ArgRef
1366 53, // sub_8bit_hi -> GR32_ArgRef
1367 0, // sub_8bit_hi_phony
1368 53, // sub_16bit -> GR32_ArgRef
1369 53, // sub_16bit_hi -> GR32_ArgRef
1370 0, // sub_32bit
1371 0, // sub_mask_0
1372 0, // sub_mask_1
1373 0, // sub_xmm
1374 0, // sub_ymm
1375 },
1376 { // GR32_BPSP
1377 54, // sub_8bit -> GR32_BPSP
1378 0, // sub_8bit_hi
1379 54, // sub_8bit_hi_phony -> GR32_BPSP
1380 54, // sub_16bit -> GR32_BPSP
1381 54, // sub_16bit_hi -> GR32_BPSP
1382 0, // sub_32bit
1383 0, // sub_mask_0
1384 0, // sub_mask_1
1385 0, // sub_xmm
1386 0, // sub_ymm
1387 },
1388 { // GR32_BSI
1389 55, // sub_8bit -> GR32_BSI
1390 63, // sub_8bit_hi -> GR32_ABCD_and_GR32_BSI
1391 0, // sub_8bit_hi_phony
1392 55, // sub_16bit -> GR32_BSI
1393 55, // sub_16bit_hi -> GR32_BSI
1394 0, // sub_32bit
1395 0, // sub_mask_0
1396 0, // sub_mask_1
1397 0, // sub_xmm
1398 0, // sub_ymm
1399 },
1400 { // GR32_CB
1401 56, // sub_8bit -> GR32_CB
1402 56, // sub_8bit_hi -> GR32_CB
1403 0, // sub_8bit_hi_phony
1404 56, // sub_16bit -> GR32_CB
1405 56, // sub_16bit_hi -> GR32_CB
1406 0, // sub_32bit
1407 0, // sub_mask_0
1408 0, // sub_mask_1
1409 0, // sub_xmm
1410 0, // sub_ymm
1411 },
1412 { // GR32_DC
1413 57, // sub_8bit -> GR32_DC
1414 57, // sub_8bit_hi -> GR32_DC
1415 0, // sub_8bit_hi_phony
1416 57, // sub_16bit -> GR32_DC
1417 57, // sub_16bit_hi -> GR32_DC
1418 0, // sub_32bit
1419 0, // sub_mask_0
1420 0, // sub_mask_1
1421 0, // sub_xmm
1422 0, // sub_ymm
1423 },
1424 { // GR32_DIBP
1425 58, // sub_8bit -> GR32_DIBP
1426 0, // sub_8bit_hi
1427 58, // sub_8bit_hi_phony -> GR32_DIBP
1428 58, // sub_16bit -> GR32_DIBP
1429 58, // sub_16bit_hi -> GR32_DIBP
1430 0, // sub_32bit
1431 0, // sub_mask_0
1432 0, // sub_mask_1
1433 0, // sub_xmm
1434 0, // sub_ymm
1435 },
1436 { // GR32_SIDI
1437 59, // sub_8bit -> GR32_SIDI
1438 0, // sub_8bit_hi
1439 59, // sub_8bit_hi_phony -> GR32_SIDI
1440 59, // sub_16bit -> GR32_SIDI
1441 59, // sub_16bit_hi -> GR32_SIDI
1442 0, // sub_32bit
1443 0, // sub_mask_0
1444 0, // sub_mask_1
1445 0, // sub_xmm
1446 0, // sub_ymm
1447 },
1448 { // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
1449 70, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
1450 0, // sub_8bit_hi
1451 0, // sub_8bit_hi_phony
1452 60, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
1453 60, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
1454 60, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
1455 0, // sub_mask_0
1456 0, // sub_mask_1
1457 0, // sub_xmm
1458 0, // sub_ymm
1459 },
1460 { // CCR
1461 0, // sub_8bit
1462 0, // sub_8bit_hi
1463 0, // sub_8bit_hi_phony
1464 0, // sub_16bit
1465 0, // sub_16bit_hi
1466 0, // sub_32bit
1467 0, // sub_mask_0
1468 0, // sub_mask_1
1469 0, // sub_xmm
1470 0, // sub_ymm
1471 },
1472 { // DFCCR
1473 0, // sub_8bit
1474 0, // sub_8bit_hi
1475 0, // sub_8bit_hi_phony
1476 0, // sub_16bit
1477 0, // sub_16bit_hi
1478 0, // sub_32bit
1479 0, // sub_mask_0
1480 0, // sub_mask_1
1481 0, // sub_xmm
1482 0, // sub_ymm
1483 },
1484 { // GR32_ABCD_and_GR32_BSI
1485 63, // sub_8bit -> GR32_ABCD_and_GR32_BSI
1486 63, // sub_8bit_hi -> GR32_ABCD_and_GR32_BSI
1487 0, // sub_8bit_hi_phony
1488 63, // sub_16bit -> GR32_ABCD_and_GR32_BSI
1489 63, // sub_16bit_hi -> GR32_ABCD_and_GR32_BSI
1490 0, // sub_32bit
1491 0, // sub_mask_0
1492 0, // sub_mask_1
1493 0, // sub_xmm
1494 0, // sub_ymm
1495 },
1496 { // GR32_AD_and_GR32_ArgRef
1497 64, // sub_8bit -> GR32_AD_and_GR32_ArgRef
1498 64, // sub_8bit_hi -> GR32_AD_and_GR32_ArgRef
1499 0, // sub_8bit_hi_phony
1500 64, // sub_16bit -> GR32_AD_and_GR32_ArgRef
1501 64, // sub_16bit_hi -> GR32_AD_and_GR32_ArgRef
1502 0, // sub_32bit
1503 0, // sub_mask_0
1504 0, // sub_mask_1
1505 0, // sub_xmm
1506 0, // sub_ymm
1507 },
1508 { // GR32_ArgRef_and_GR32_CB
1509 65, // sub_8bit -> GR32_ArgRef_and_GR32_CB
1510 65, // sub_8bit_hi -> GR32_ArgRef_and_GR32_CB
1511 0, // sub_8bit_hi_phony
1512 65, // sub_16bit -> GR32_ArgRef_and_GR32_CB
1513 65, // sub_16bit_hi -> GR32_ArgRef_and_GR32_CB
1514 0, // sub_32bit
1515 0, // sub_mask_0
1516 0, // sub_mask_1
1517 0, // sub_xmm
1518 0, // sub_ymm
1519 },
1520 { // GR32_BPSP_and_GR32_DIBP
1521 66, // sub_8bit -> GR32_BPSP_and_GR32_DIBP
1522 0, // sub_8bit_hi
1523 66, // sub_8bit_hi_phony -> GR32_BPSP_and_GR32_DIBP
1524 66, // sub_16bit -> GR32_BPSP_and_GR32_DIBP
1525 66, // sub_16bit_hi -> GR32_BPSP_and_GR32_DIBP
1526 0, // sub_32bit
1527 0, // sub_mask_0
1528 0, // sub_mask_1
1529 0, // sub_xmm
1530 0, // sub_ymm
1531 },
1532 { // GR32_BPSP_and_GR32_TC
1533 67, // sub_8bit -> GR32_BPSP_and_GR32_TC
1534 0, // sub_8bit_hi
1535 67, // sub_8bit_hi_phony -> GR32_BPSP_and_GR32_TC
1536 67, // sub_16bit -> GR32_BPSP_and_GR32_TC
1537 67, // sub_16bit_hi -> GR32_BPSP_and_GR32_TC
1538 0, // sub_32bit
1539 0, // sub_mask_0
1540 0, // sub_mask_1
1541 0, // sub_xmm
1542 0, // sub_ymm
1543 },
1544 { // GR32_BSI_and_GR32_SIDI
1545 68, // sub_8bit -> GR32_BSI_and_GR32_SIDI
1546 0, // sub_8bit_hi
1547 68, // sub_8bit_hi_phony -> GR32_BSI_and_GR32_SIDI
1548 68, // sub_16bit -> GR32_BSI_and_GR32_SIDI
1549 68, // sub_16bit_hi -> GR32_BSI_and_GR32_SIDI
1550 0, // sub_32bit
1551 0, // sub_mask_0
1552 0, // sub_mask_1
1553 0, // sub_xmm
1554 0, // sub_ymm
1555 },
1556 { // GR32_DIBP_and_GR32_SIDI
1557 69, // sub_8bit -> GR32_DIBP_and_GR32_SIDI
1558 0, // sub_8bit_hi
1559 69, // sub_8bit_hi_phony -> GR32_DIBP_and_GR32_SIDI
1560 69, // sub_16bit -> GR32_DIBP_and_GR32_SIDI
1561 69, // sub_16bit_hi -> GR32_DIBP_and_GR32_SIDI
1562 0, // sub_32bit
1563 0, // sub_mask_0
1564 0, // sub_mask_1
1565 0, // sub_xmm
1566 0, // sub_ymm
1567 },
1568 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
1569 70, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
1570 0, // sub_8bit_hi
1571 70, // sub_8bit_hi_phony -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
1572 70, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
1573 70, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
1574 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
1575 0, // sub_mask_0
1576 0, // sub_mask_1
1577 0, // sub_xmm
1578 0, // sub_ymm
1579 },
1580 { // LOW32_ADDR_ACCESS_with_sub_32bit
1581 0, // sub_8bit
1582 0, // sub_8bit_hi
1583 0, // sub_8bit_hi_phony
1584 71, // sub_16bit -> LOW32_ADDR_ACCESS_with_sub_32bit
1585 71, // sub_16bit_hi -> LOW32_ADDR_ACCESS_with_sub_32bit
1586 71, // sub_32bit -> LOW32_ADDR_ACCESS_with_sub_32bit
1587 0, // sub_mask_0
1588 0, // sub_mask_1
1589 0, // sub_xmm
1590 0, // sub_ymm
1591 },
1592 { // RFP64
1593 0, // sub_8bit
1594 0, // sub_8bit_hi
1595 0, // sub_8bit_hi_phony
1596 0, // sub_16bit
1597 0, // sub_16bit_hi
1598 0, // sub_32bit
1599 0, // sub_mask_0
1600 0, // sub_mask_1
1601 0, // sub_xmm
1602 0, // sub_ymm
1603 },
1604 { // GR64
1605 75, // sub_8bit -> GR64_with_sub_8bit
1606 104, // sub_8bit_hi -> GR64_ABCD
1607 0, // sub_8bit_hi_phony
1608 73, // sub_16bit -> GR64
1609 73, // sub_16bit_hi -> GR64
1610 73, // sub_32bit -> GR64
1611 0, // sub_mask_0
1612 0, // sub_mask_1
1613 0, // sub_xmm
1614 0, // sub_ymm
1615 },
1616 { // FR64X
1617 0, // sub_8bit
1618 0, // sub_8bit_hi
1619 0, // sub_8bit_hi_phony
1620 0, // sub_16bit
1621 0, // sub_16bit_hi
1622 0, // sub_32bit
1623 0, // sub_mask_0
1624 0, // sub_mask_1
1625 0, // sub_xmm
1626 0, // sub_ymm
1627 },
1628 { // GR64_with_sub_8bit
1629 75, // sub_8bit -> GR64_with_sub_8bit
1630 104, // sub_8bit_hi -> GR64_ABCD
1631 0, // sub_8bit_hi_phony
1632 75, // sub_16bit -> GR64_with_sub_8bit
1633 75, // sub_16bit_hi -> GR64_with_sub_8bit
1634 75, // sub_32bit -> GR64_with_sub_8bit
1635 0, // sub_mask_0
1636 0, // sub_mask_1
1637 0, // sub_xmm
1638 0, // sub_ymm
1639 },
1640 { // GR64_NOSP
1641 76, // sub_8bit -> GR64_NOSP
1642 104, // sub_8bit_hi -> GR64_ABCD
1643 0, // sub_8bit_hi_phony
1644 76, // sub_16bit -> GR64_NOSP
1645 76, // sub_16bit_hi -> GR64_NOSP
1646 76, // sub_32bit -> GR64_NOSP
1647 0, // sub_mask_0
1648 0, // sub_mask_1
1649 0, // sub_xmm
1650 0, // sub_ymm
1651 },
1652 { // GR64_NOREX2
1653 80, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX2
1654 104, // sub_8bit_hi -> GR64_ABCD
1655 0, // sub_8bit_hi_phony
1656 77, // sub_16bit -> GR64_NOREX2
1657 77, // sub_16bit_hi -> GR64_NOREX2
1658 77, // sub_32bit -> GR64_NOREX2
1659 0, // sub_mask_0
1660 0, // sub_mask_1
1661 0, // sub_xmm
1662 0, // sub_ymm
1663 },
1664 { // CONTROL_REG
1665 0, // sub_8bit
1666 0, // sub_8bit_hi
1667 0, // sub_8bit_hi_phony
1668 0, // sub_16bit
1669 0, // sub_16bit_hi
1670 0, // sub_32bit
1671 0, // sub_mask_0
1672 0, // sub_mask_1
1673 0, // sub_xmm
1674 0, // sub_ymm
1675 },
1676 { // FR64
1677 0, // sub_8bit
1678 0, // sub_8bit_hi
1679 0, // sub_8bit_hi_phony
1680 0, // sub_16bit
1681 0, // sub_16bit_hi
1682 0, // sub_32bit
1683 0, // sub_mask_0
1684 0, // sub_mask_1
1685 0, // sub_xmm
1686 0, // sub_ymm
1687 },
1688 { // GR64_with_sub_16bit_in_GR16_NOREX2
1689 80, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX2
1690 104, // sub_8bit_hi -> GR64_ABCD
1691 0, // sub_8bit_hi_phony
1692 80, // sub_16bit -> GR64_with_sub_16bit_in_GR16_NOREX2
1693 80, // sub_16bit_hi -> GR64_with_sub_16bit_in_GR16_NOREX2
1694 80, // sub_32bit -> GR64_with_sub_16bit_in_GR16_NOREX2
1695 0, // sub_mask_0
1696 0, // sub_mask_1
1697 0, // sub_xmm
1698 0, // sub_ymm
1699 },
1700 { // GR64_NOREX2_NOSP
1701 81, // sub_8bit -> GR64_NOREX2_NOSP
1702 104, // sub_8bit_hi -> GR64_ABCD
1703 0, // sub_8bit_hi_phony
1704 81, // sub_16bit -> GR64_NOREX2_NOSP
1705 81, // sub_16bit_hi -> GR64_NOREX2_NOSP
1706 81, // sub_32bit -> GR64_NOREX2_NOSP
1707 0, // sub_mask_0
1708 0, // sub_mask_1
1709 0, // sub_xmm
1710 0, // sub_ymm
1711 },
1712 { // GR64PLTSafe
1713 82, // sub_8bit -> GR64PLTSafe
1714 104, // sub_8bit_hi -> GR64_ABCD
1715 0, // sub_8bit_hi_phony
1716 82, // sub_16bit -> GR64PLTSafe
1717 82, // sub_16bit_hi -> GR64PLTSafe
1718 82, // sub_32bit -> GR64PLTSafe
1719 0, // sub_mask_0
1720 0, // sub_mask_1
1721 0, // sub_xmm
1722 0, // sub_ymm
1723 },
1724 { // GR64_TC
1725 86, // sub_8bit -> GR64_TC_with_sub_8bit
1726 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
1727 0, // sub_8bit_hi_phony
1728 83, // sub_16bit -> GR64_TC
1729 83, // sub_16bit_hi -> GR64_TC
1730 83, // sub_32bit -> GR64_TC
1731 0, // sub_mask_0
1732 0, // sub_mask_1
1733 0, // sub_xmm
1734 0, // sub_ymm
1735 },
1736 { // GR64_NOREX
1737 90, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX
1738 104, // sub_8bit_hi -> GR64_ABCD
1739 0, // sub_8bit_hi_phony
1740 84, // sub_16bit -> GR64_NOREX
1741 84, // sub_16bit_hi -> GR64_NOREX
1742 84, // sub_32bit -> GR64_NOREX
1743 0, // sub_mask_0
1744 0, // sub_mask_1
1745 0, // sub_xmm
1746 0, // sub_ymm
1747 },
1748 { // GR64_TCW64
1749 88, // sub_8bit -> GR64_TCW64_with_sub_8bit
1750 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
1751 0, // sub_8bit_hi_phony
1752 85, // sub_16bit -> GR64_TCW64
1753 85, // sub_16bit_hi -> GR64_TCW64
1754 85, // sub_32bit -> GR64_TCW64
1755 0, // sub_mask_0
1756 0, // sub_mask_1
1757 0, // sub_xmm
1758 0, // sub_ymm
1759 },
1760 { // GR64_TC_with_sub_8bit
1761 86, // sub_8bit -> GR64_TC_with_sub_8bit
1762 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
1763 0, // sub_8bit_hi_phony
1764 86, // sub_16bit -> GR64_TC_with_sub_8bit
1765 86, // sub_16bit_hi -> GR64_TC_with_sub_8bit
1766 86, // sub_32bit -> GR64_TC_with_sub_8bit
1767 0, // sub_mask_0
1768 0, // sub_mask_1
1769 0, // sub_xmm
1770 0, // sub_ymm
1771 },
1772 { // GR64_NOREX2_NOSP_and_GR64_TC
1773 87, // sub_8bit -> GR64_NOREX2_NOSP_and_GR64_TC
1774 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
1775 0, // sub_8bit_hi_phony
1776 87, // sub_16bit -> GR64_NOREX2_NOSP_and_GR64_TC
1777 87, // sub_16bit_hi -> GR64_NOREX2_NOSP_and_GR64_TC
1778 87, // sub_32bit -> GR64_NOREX2_NOSP_and_GR64_TC
1779 0, // sub_mask_0
1780 0, // sub_mask_1
1781 0, // sub_xmm
1782 0, // sub_ymm
1783 },
1784 { // GR64_TCW64_with_sub_8bit
1785 88, // sub_8bit -> GR64_TCW64_with_sub_8bit
1786 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
1787 0, // sub_8bit_hi_phony
1788 88, // sub_16bit -> GR64_TCW64_with_sub_8bit
1789 88, // sub_16bit_hi -> GR64_TCW64_with_sub_8bit
1790 88, // sub_32bit -> GR64_TCW64_with_sub_8bit
1791 0, // sub_mask_0
1792 0, // sub_mask_1
1793 0, // sub_xmm
1794 0, // sub_ymm
1795 },
1796 { // GR64_TC_and_GR64_TCW64
1797 97, // sub_8bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
1798 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
1799 0, // sub_8bit_hi_phony
1800 89, // sub_16bit -> GR64_TC_and_GR64_TCW64
1801 89, // sub_16bit_hi -> GR64_TC_and_GR64_TCW64
1802 89, // sub_32bit -> GR64_TC_and_GR64_TCW64
1803 0, // sub_mask_0
1804 0, // sub_mask_1
1805 0, // sub_xmm
1806 0, // sub_ymm
1807 },
1808 { // GR64_with_sub_16bit_in_GR16_NOREX
1809 90, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX
1810 104, // sub_8bit_hi -> GR64_ABCD
1811 0, // sub_8bit_hi_phony
1812 90, // sub_16bit -> GR64_with_sub_16bit_in_GR16_NOREX
1813 90, // sub_16bit_hi -> GR64_with_sub_16bit_in_GR16_NOREX
1814 90, // sub_32bit -> GR64_with_sub_16bit_in_GR16_NOREX
1815 0, // sub_mask_0
1816 0, // sub_mask_1
1817 0, // sub_xmm
1818 0, // sub_ymm
1819 },
1820 { // VK64
1821 0, // sub_8bit
1822 0, // sub_8bit_hi
1823 0, // sub_8bit_hi_phony
1824 0, // sub_16bit
1825 0, // sub_16bit_hi
1826 0, // sub_32bit
1827 0, // sub_mask_0
1828 0, // sub_mask_1
1829 0, // sub_xmm
1830 0, // sub_ymm
1831 },
1832 { // VR64
1833 0, // sub_8bit
1834 0, // sub_8bit_hi
1835 0, // sub_8bit_hi_phony
1836 0, // sub_16bit
1837 0, // sub_16bit_hi
1838 0, // sub_32bit
1839 0, // sub_mask_0
1840 0, // sub_mask_1
1841 0, // sub_xmm
1842 0, // sub_ymm
1843 },
1844 { // GR64PLTSafe_and_GR64_TC
1845 93, // sub_8bit -> GR64PLTSafe_and_GR64_TC
1846 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
1847 0, // sub_8bit_hi_phony
1848 93, // sub_16bit -> GR64PLTSafe_and_GR64_TC
1849 93, // sub_16bit_hi -> GR64PLTSafe_and_GR64_TC
1850 93, // sub_32bit -> GR64PLTSafe_and_GR64_TC
1851 0, // sub_mask_0
1852 0, // sub_mask_1
1853 0, // sub_xmm
1854 0, // sub_ymm
1855 },
1856 { // GR64_NOREX2_NOSP_and_GR64_TCW64
1857 94, // sub_8bit -> GR64_NOREX2_NOSP_and_GR64_TCW64
1858 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
1859 0, // sub_8bit_hi_phony
1860 94, // sub_16bit -> GR64_NOREX2_NOSP_and_GR64_TCW64
1861 94, // sub_16bit_hi -> GR64_NOREX2_NOSP_and_GR64_TCW64
1862 94, // sub_32bit -> GR64_NOREX2_NOSP_and_GR64_TCW64
1863 0, // sub_mask_0
1864 0, // sub_mask_1
1865 0, // sub_xmm
1866 0, // sub_ymm
1867 },
1868 { // GR64_NOREX_NOSP
1869 95, // sub_8bit -> GR64_NOREX_NOSP
1870 104, // sub_8bit_hi -> GR64_ABCD
1871 0, // sub_8bit_hi_phony
1872 95, // sub_16bit -> GR64_NOREX_NOSP
1873 95, // sub_16bit_hi -> GR64_NOREX_NOSP
1874 95, // sub_32bit -> GR64_NOREX_NOSP
1875 0, // sub_mask_0
1876 0, // sub_mask_1
1877 0, // sub_xmm
1878 0, // sub_ymm
1879 },
1880 { // GR64_NOREX_and_GR64_TC
1881 100, // sub_8bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
1882 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
1883 0, // sub_8bit_hi_phony
1884 96, // sub_16bit -> GR64_NOREX_and_GR64_TC
1885 96, // sub_16bit_hi -> GR64_NOREX_and_GR64_TC
1886 96, // sub_32bit -> GR64_NOREX_and_GR64_TC
1887 0, // sub_mask_0
1888 0, // sub_mask_1
1889 0, // sub_xmm
1890 0, // sub_ymm
1891 },
1892 { // GR64_TCW64_and_GR64_TC_with_sub_8bit
1893 97, // sub_8bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
1894 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
1895 0, // sub_8bit_hi_phony
1896 97, // sub_16bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
1897 97, // sub_16bit_hi -> GR64_TCW64_and_GR64_TC_with_sub_8bit
1898 97, // sub_32bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
1899 0, // sub_mask_0
1900 0, // sub_mask_1
1901 0, // sub_xmm
1902 0, // sub_ymm
1903 },
1904 { // VK64WM
1905 0, // sub_8bit
1906 0, // sub_8bit_hi
1907 0, // sub_8bit_hi_phony
1908 0, // sub_16bit
1909 0, // sub_16bit_hi
1910 0, // sub_32bit
1911 0, // sub_mask_0
1912 0, // sub_mask_1
1913 0, // sub_xmm
1914 0, // sub_ymm
1915 },
1916 { // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
1917 99, // sub_8bit -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
1918 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
1919 0, // sub_8bit_hi_phony
1920 99, // sub_16bit -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
1921 99, // sub_16bit_hi -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
1922 99, // sub_32bit -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
1923 0, // sub_mask_0
1924 0, // sub_mask_1
1925 0, // sub_xmm
1926 0, // sub_ymm
1927 },
1928 { // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
1929 100, // sub_8bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
1930 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
1931 0, // sub_8bit_hi_phony
1932 100, // sub_16bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
1933 100, // sub_16bit_hi -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
1934 100, // sub_32bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
1935 0, // sub_mask_0
1936 0, // sub_mask_1
1937 0, // sub_xmm
1938 0, // sub_ymm
1939 },
1940 { // GR64PLTSafe_and_GR64_TCW64
1941 101, // sub_8bit -> GR64PLTSafe_and_GR64_TCW64
1942 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
1943 0, // sub_8bit_hi_phony
1944 101, // sub_16bit -> GR64PLTSafe_and_GR64_TCW64
1945 101, // sub_16bit_hi -> GR64PLTSafe_and_GR64_TCW64
1946 101, // sub_32bit -> GR64PLTSafe_and_GR64_TCW64
1947 0, // sub_mask_0
1948 0, // sub_mask_1
1949 0, // sub_xmm
1950 0, // sub_ymm
1951 },
1952 { // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
1953 102, // sub_8bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
1954 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
1955 0, // sub_8bit_hi_phony
1956 102, // sub_16bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
1957 102, // sub_16bit_hi -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
1958 102, // sub_32bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
1959 0, // sub_mask_0
1960 0, // sub_mask_1
1961 0, // sub_xmm
1962 0, // sub_ymm
1963 },
1964 { // GR64_NOREX_and_GR64_TCW64
1965 105, // sub_8bit -> GR64_with_sub_32bit_in_GR32_TC
1966 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
1967 0, // sub_8bit_hi_phony
1968 103, // sub_16bit -> GR64_NOREX_and_GR64_TCW64
1969 103, // sub_16bit_hi -> GR64_NOREX_and_GR64_TCW64
1970 103, // sub_32bit -> GR64_NOREX_and_GR64_TCW64
1971 0, // sub_mask_0
1972 0, // sub_mask_1
1973 0, // sub_xmm
1974 0, // sub_ymm
1975 },
1976 { // GR64_ABCD
1977 104, // sub_8bit -> GR64_ABCD
1978 104, // sub_8bit_hi -> GR64_ABCD
1979 0, // sub_8bit_hi_phony
1980 104, // sub_16bit -> GR64_ABCD
1981 104, // sub_16bit_hi -> GR64_ABCD
1982 104, // sub_32bit -> GR64_ABCD
1983 0, // sub_mask_0
1984 0, // sub_mask_1
1985 0, // sub_xmm
1986 0, // sub_ymm
1987 },
1988 { // GR64_with_sub_32bit_in_GR32_TC
1989 105, // sub_8bit -> GR64_with_sub_32bit_in_GR32_TC
1990 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
1991 0, // sub_8bit_hi_phony
1992 105, // sub_16bit -> GR64_with_sub_32bit_in_GR32_TC
1993 105, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_TC
1994 105, // sub_32bit -> GR64_with_sub_32bit_in_GR32_TC
1995 0, // sub_mask_0
1996 0, // sub_mask_1
1997 0, // sub_xmm
1998 0, // sub_ymm
1999 },
2000 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
2001 106, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
2002 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
2003 0, // sub_8bit_hi_phony
2004 106, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
2005 106, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
2006 106, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
2007 0, // sub_mask_0
2008 0, // sub_mask_1
2009 0, // sub_xmm
2010 0, // sub_ymm
2011 },
2012 { // GR64_AD
2013 107, // sub_8bit -> GR64_AD
2014 107, // sub_8bit_hi -> GR64_AD
2015 0, // sub_8bit_hi_phony
2016 107, // sub_16bit -> GR64_AD
2017 107, // sub_16bit_hi -> GR64_AD
2018 107, // sub_32bit -> GR64_AD
2019 0, // sub_mask_0
2020 0, // sub_mask_1
2021 0, // sub_xmm
2022 0, // sub_ymm
2023 },
2024 { // GR64_ArgRef
2025 108, // sub_8bit -> GR64_ArgRef
2026 0, // sub_8bit_hi
2027 108, // sub_8bit_hi_phony -> GR64_ArgRef
2028 108, // sub_16bit -> GR64_ArgRef
2029 108, // sub_16bit_hi -> GR64_ArgRef
2030 108, // sub_32bit -> GR64_ArgRef
2031 0, // sub_mask_0
2032 0, // sub_mask_1
2033 0, // sub_xmm
2034 0, // sub_ymm
2035 },
2036 { // GR64_and_LOW32_ADDR_ACCESS_RBP
2037 122, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
2038 0, // sub_8bit_hi
2039 0, // sub_8bit_hi_phony
2040 109, // sub_16bit -> GR64_and_LOW32_ADDR_ACCESS_RBP
2041 109, // sub_16bit_hi -> GR64_and_LOW32_ADDR_ACCESS_RBP
2042 109, // sub_32bit -> GR64_and_LOW32_ADDR_ACCESS_RBP
2043 0, // sub_mask_0
2044 0, // sub_mask_1
2045 0, // sub_xmm
2046 0, // sub_ymm
2047 },
2048 { // GR64_with_sub_32bit_in_GR32_ArgRef
2049 110, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ArgRef
2050 110, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef
2051 0, // sub_8bit_hi_phony
2052 110, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ArgRef
2053 110, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef
2054 110, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ArgRef
2055 0, // sub_mask_0
2056 0, // sub_mask_1
2057 0, // sub_xmm
2058 0, // sub_ymm
2059 },
2060 { // GR64_with_sub_32bit_in_GR32_BPSP
2061 111, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP
2062 0, // sub_8bit_hi
2063 111, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BPSP
2064 111, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP
2065 111, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BPSP
2066 111, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP
2067 0, // sub_mask_0
2068 0, // sub_mask_1
2069 0, // sub_xmm
2070 0, // sub_ymm
2071 },
2072 { // GR64_with_sub_32bit_in_GR32_BSI
2073 112, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BSI
2074 119, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
2075 0, // sub_8bit_hi_phony
2076 112, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BSI
2077 112, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BSI
2078 112, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BSI
2079 0, // sub_mask_0
2080 0, // sub_mask_1
2081 0, // sub_xmm
2082 0, // sub_ymm
2083 },
2084 { // GR64_with_sub_32bit_in_GR32_CB
2085 113, // sub_8bit -> GR64_with_sub_32bit_in_GR32_CB
2086 113, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_CB
2087 0, // sub_8bit_hi_phony
2088 113, // sub_16bit -> GR64_with_sub_32bit_in_GR32_CB
2089 113, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_CB
2090 113, // sub_32bit -> GR64_with_sub_32bit_in_GR32_CB
2091 0, // sub_mask_0
2092 0, // sub_mask_1
2093 0, // sub_xmm
2094 0, // sub_ymm
2095 },
2096 { // GR64_with_sub_32bit_in_GR32_DIBP
2097 114, // sub_8bit -> GR64_with_sub_32bit_in_GR32_DIBP
2098 0, // sub_8bit_hi
2099 114, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_DIBP
2100 114, // sub_16bit -> GR64_with_sub_32bit_in_GR32_DIBP
2101 114, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_DIBP
2102 114, // sub_32bit -> GR64_with_sub_32bit_in_GR32_DIBP
2103 0, // sub_mask_0
2104 0, // sub_mask_1
2105 0, // sub_xmm
2106 0, // sub_ymm
2107 },
2108 { // GR64_with_sub_32bit_in_GR32_SIDI
2109 115, // sub_8bit -> GR64_with_sub_32bit_in_GR32_SIDI
2110 0, // sub_8bit_hi
2111 115, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_SIDI
2112 115, // sub_16bit -> GR64_with_sub_32bit_in_GR32_SIDI
2113 115, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_SIDI
2114 115, // sub_32bit -> GR64_with_sub_32bit_in_GR32_SIDI
2115 0, // sub_mask_0
2116 0, // sub_mask_1
2117 0, // sub_xmm
2118 0, // sub_ymm
2119 },
2120 { // GR64_A
2121 116, // sub_8bit -> GR64_A
2122 116, // sub_8bit_hi -> GR64_A
2123 0, // sub_8bit_hi_phony
2124 116, // sub_16bit -> GR64_A
2125 116, // sub_16bit_hi -> GR64_A
2126 116, // sub_32bit -> GR64_A
2127 0, // sub_mask_0
2128 0, // sub_mask_1
2129 0, // sub_xmm
2130 0, // sub_ymm
2131 },
2132 { // GR64_ArgRef_and_GR64_TC
2133 117, // sub_8bit -> GR64_ArgRef_and_GR64_TC
2134 0, // sub_8bit_hi
2135 117, // sub_8bit_hi_phony -> GR64_ArgRef_and_GR64_TC
2136 117, // sub_16bit -> GR64_ArgRef_and_GR64_TC
2137 117, // sub_16bit_hi -> GR64_ArgRef_and_GR64_TC
2138 117, // sub_32bit -> GR64_ArgRef_and_GR64_TC
2139 0, // sub_mask_0
2140 0, // sub_mask_1
2141 0, // sub_xmm
2142 0, // sub_ymm
2143 },
2144 { // GR64_and_LOW32_ADDR_ACCESS
2145 0, // sub_8bit
2146 0, // sub_8bit_hi
2147 0, // sub_8bit_hi_phony
2148 118, // sub_16bit -> GR64_and_LOW32_ADDR_ACCESS
2149 118, // sub_16bit_hi -> GR64_and_LOW32_ADDR_ACCESS
2150 118, // sub_32bit -> GR64_and_LOW32_ADDR_ACCESS
2151 0, // sub_mask_0
2152 0, // sub_mask_1
2153 0, // sub_xmm
2154 0, // sub_ymm
2155 },
2156 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
2157 119, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
2158 119, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
2159 0, // sub_8bit_hi_phony
2160 119, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
2161 119, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
2162 119, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
2163 0, // sub_mask_0
2164 0, // sub_mask_1
2165 0, // sub_xmm
2166 0, // sub_ymm
2167 },
2168 { // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
2169 120, // sub_8bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
2170 120, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
2171 0, // sub_8bit_hi_phony
2172 120, // sub_16bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
2173 120, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
2174 120, // sub_32bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
2175 0, // sub_mask_0
2176 0, // sub_mask_1
2177 0, // sub_xmm
2178 0, // sub_ymm
2179 },
2180 { // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
2181 121, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
2182 121, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
2183 0, // sub_8bit_hi_phony
2184 121, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
2185 121, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
2186 121, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
2187 0, // sub_mask_0
2188 0, // sub_mask_1
2189 0, // sub_xmm
2190 0, // sub_ymm
2191 },
2192 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
2193 122, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
2194 0, // sub_8bit_hi
2195 122, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
2196 122, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
2197 122, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
2198 122, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
2199 0, // sub_mask_0
2200 0, // sub_mask_1
2201 0, // sub_xmm
2202 0, // sub_ymm
2203 },
2204 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
2205 123, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
2206 0, // sub_8bit_hi
2207 123, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
2208 123, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
2209 123, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
2210 123, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
2211 0, // sub_mask_0
2212 0, // sub_mask_1
2213 0, // sub_xmm
2214 0, // sub_ymm
2215 },
2216 { // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
2217 124, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
2218 0, // sub_8bit_hi
2219 124, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
2220 124, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
2221 124, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
2222 124, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
2223 0, // sub_mask_0
2224 0, // sub_mask_1
2225 0, // sub_xmm
2226 0, // sub_ymm
2227 },
2228 { // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
2229 125, // sub_8bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
2230 0, // sub_8bit_hi
2231 125, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
2232 125, // sub_16bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
2233 125, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
2234 125, // sub_32bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
2235 0, // sub_mask_0
2236 0, // sub_mask_1
2237 0, // sub_xmm
2238 0, // sub_ymm
2239 },
2240 { // RST
2241 0, // sub_8bit
2242 0, // sub_8bit_hi
2243 0, // sub_8bit_hi_phony
2244 0, // sub_16bit
2245 0, // sub_16bit_hi
2246 0, // sub_32bit
2247 0, // sub_mask_0
2248 0, // sub_mask_1
2249 0, // sub_xmm
2250 0, // sub_ymm
2251 },
2252 { // RFP80
2253 0, // sub_8bit
2254 0, // sub_8bit_hi
2255 0, // sub_8bit_hi_phony
2256 0, // sub_16bit
2257 0, // sub_16bit_hi
2258 0, // sub_32bit
2259 0, // sub_mask_0
2260 0, // sub_mask_1
2261 0, // sub_xmm
2262 0, // sub_ymm
2263 },
2264 { // RFP80_7
2265 0, // sub_8bit
2266 0, // sub_8bit_hi
2267 0, // sub_8bit_hi_phony
2268 0, // sub_16bit
2269 0, // sub_16bit_hi
2270 0, // sub_32bit
2271 0, // sub_mask_0
2272 0, // sub_mask_1
2273 0, // sub_xmm
2274 0, // sub_ymm
2275 },
2276 { // VR128X
2277 0, // sub_8bit
2278 0, // sub_8bit_hi
2279 0, // sub_8bit_hi_phony
2280 0, // sub_16bit
2281 0, // sub_16bit_hi
2282 0, // sub_32bit
2283 0, // sub_mask_0
2284 0, // sub_mask_1
2285 0, // sub_xmm
2286 0, // sub_ymm
2287 },
2288 { // VR128
2289 0, // sub_8bit
2290 0, // sub_8bit_hi
2291 0, // sub_8bit_hi_phony
2292 0, // sub_16bit
2293 0, // sub_16bit_hi
2294 0, // sub_32bit
2295 0, // sub_mask_0
2296 0, // sub_mask_1
2297 0, // sub_xmm
2298 0, // sub_ymm
2299 },
2300 { // VR256X
2301 0, // sub_8bit
2302 0, // sub_8bit_hi
2303 0, // sub_8bit_hi_phony
2304 0, // sub_16bit
2305 0, // sub_16bit_hi
2306 0, // sub_32bit
2307 0, // sub_mask_0
2308 0, // sub_mask_1
2309 131, // sub_xmm -> VR256X
2310 0, // sub_ymm
2311 },
2312 { // VR256
2313 0, // sub_8bit
2314 0, // sub_8bit_hi
2315 0, // sub_8bit_hi_phony
2316 0, // sub_16bit
2317 0, // sub_16bit_hi
2318 0, // sub_32bit
2319 0, // sub_mask_0
2320 0, // sub_mask_1
2321 132, // sub_xmm -> VR256
2322 0, // sub_ymm
2323 },
2324 { // VR512
2325 0, // sub_8bit
2326 0, // sub_8bit_hi
2327 0, // sub_8bit_hi_phony
2328 0, // sub_16bit
2329 0, // sub_16bit_hi
2330 0, // sub_32bit
2331 0, // sub_mask_0
2332 0, // sub_mask_1
2333 133, // sub_xmm -> VR512
2334 133, // sub_ymm -> VR512
2335 },
2336 { // VR512_0_15
2337 0, // sub_8bit
2338 0, // sub_8bit_hi
2339 0, // sub_8bit_hi_phony
2340 0, // sub_16bit
2341 0, // sub_16bit_hi
2342 0, // sub_32bit
2343 0, // sub_mask_0
2344 0, // sub_mask_1
2345 134, // sub_xmm -> VR512_0_15
2346 134, // sub_ymm -> VR512_0_15
2347 },
2348 { // TILE
2349 0, // sub_8bit
2350 0, // sub_8bit_hi
2351 0, // sub_8bit_hi_phony
2352 0, // sub_16bit
2353 0, // sub_16bit_hi
2354 0, // sub_32bit
2355 0, // sub_mask_0
2356 0, // sub_mask_1
2357 0, // sub_xmm
2358 0, // sub_ymm
2359 },
2360
2361 };
2362 assert(RC && "Missing regclass");
2363 if (!Idx) return RC;
2364 --Idx;
2365 assert(Idx < 10 && "Bad subreg");
2366 unsigned TV = Table[RC->getID()][Idx];
2367 return TV ? getRegClass(i: TV - 1) : nullptr;
2368}const TargetRegisterClass *X86GenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
2369 static constexpr uint8_t Table[135][10] = {
2370 { // GR8
2371 0, // GR8:sub_8bit
2372 0, // GR8:sub_8bit_hi
2373 0, // GR8:sub_8bit_hi_phony
2374 0, // GR8:sub_16bit
2375 0, // GR8:sub_16bit_hi
2376 0, // GR8:sub_32bit
2377 0, // GR8:sub_mask_0
2378 0, // GR8:sub_mask_1
2379 0, // GR8:sub_xmm
2380 0, // GR8:sub_ymm
2381 },
2382 { // GRH8
2383 0, // GRH8:sub_8bit
2384 0, // GRH8:sub_8bit_hi
2385 0, // GRH8:sub_8bit_hi_phony
2386 0, // GRH8:sub_16bit
2387 0, // GRH8:sub_16bit_hi
2388 0, // GRH8:sub_32bit
2389 0, // GRH8:sub_mask_0
2390 0, // GRH8:sub_mask_1
2391 0, // GRH8:sub_xmm
2392 0, // GRH8:sub_ymm
2393 },
2394 { // GR8_NOREX2
2395 0, // GR8_NOREX2:sub_8bit
2396 0, // GR8_NOREX2:sub_8bit_hi
2397 0, // GR8_NOREX2:sub_8bit_hi_phony
2398 0, // GR8_NOREX2:sub_16bit
2399 0, // GR8_NOREX2:sub_16bit_hi
2400 0, // GR8_NOREX2:sub_32bit
2401 0, // GR8_NOREX2:sub_mask_0
2402 0, // GR8_NOREX2:sub_mask_1
2403 0, // GR8_NOREX2:sub_xmm
2404 0, // GR8_NOREX2:sub_ymm
2405 },
2406 { // GR8_NOREX
2407 0, // GR8_NOREX:sub_8bit
2408 0, // GR8_NOREX:sub_8bit_hi
2409 0, // GR8_NOREX:sub_8bit_hi_phony
2410 0, // GR8_NOREX:sub_16bit
2411 0, // GR8_NOREX:sub_16bit_hi
2412 0, // GR8_NOREX:sub_32bit
2413 0, // GR8_NOREX:sub_mask_0
2414 0, // GR8_NOREX:sub_mask_1
2415 0, // GR8_NOREX:sub_xmm
2416 0, // GR8_NOREX:sub_ymm
2417 },
2418 { // GR8_ABCD_H
2419 0, // GR8_ABCD_H:sub_8bit
2420 0, // GR8_ABCD_H:sub_8bit_hi
2421 0, // GR8_ABCD_H:sub_8bit_hi_phony
2422 0, // GR8_ABCD_H:sub_16bit
2423 0, // GR8_ABCD_H:sub_16bit_hi
2424 0, // GR8_ABCD_H:sub_32bit
2425 0, // GR8_ABCD_H:sub_mask_0
2426 0, // GR8_ABCD_H:sub_mask_1
2427 0, // GR8_ABCD_H:sub_xmm
2428 0, // GR8_ABCD_H:sub_ymm
2429 },
2430 { // GR8_ABCD_L
2431 0, // GR8_ABCD_L:sub_8bit
2432 0, // GR8_ABCD_L:sub_8bit_hi
2433 0, // GR8_ABCD_L:sub_8bit_hi_phony
2434 0, // GR8_ABCD_L:sub_16bit
2435 0, // GR8_ABCD_L:sub_16bit_hi
2436 0, // GR8_ABCD_L:sub_32bit
2437 0, // GR8_ABCD_L:sub_mask_0
2438 0, // GR8_ABCD_L:sub_mask_1
2439 0, // GR8_ABCD_L:sub_xmm
2440 0, // GR8_ABCD_L:sub_ymm
2441 },
2442 { // GRH16
2443 0, // GRH16:sub_8bit
2444 0, // GRH16:sub_8bit_hi
2445 0, // GRH16:sub_8bit_hi_phony
2446 0, // GRH16:sub_16bit
2447 0, // GRH16:sub_16bit_hi
2448 0, // GRH16:sub_32bit
2449 0, // GRH16:sub_mask_0
2450 0, // GRH16:sub_mask_1
2451 0, // GRH16:sub_xmm
2452 0, // GRH16:sub_ymm
2453 },
2454 { // GR16
2455 1, // GR16:sub_8bit -> GR8
2456 5, // GR16:sub_8bit_hi -> GR8_ABCD_H
2457 0, // GR16:sub_8bit_hi_phony
2458 0, // GR16:sub_16bit
2459 0, // GR16:sub_16bit_hi
2460 0, // GR16:sub_32bit
2461 0, // GR16:sub_mask_0
2462 0, // GR16:sub_mask_1
2463 0, // GR16:sub_xmm
2464 0, // GR16:sub_ymm
2465 },
2466 { // GR16_NOREX2
2467 3, // GR16_NOREX2:sub_8bit -> GR8_NOREX2
2468 5, // GR16_NOREX2:sub_8bit_hi -> GR8_ABCD_H
2469 0, // GR16_NOREX2:sub_8bit_hi_phony
2470 0, // GR16_NOREX2:sub_16bit
2471 0, // GR16_NOREX2:sub_16bit_hi
2472 0, // GR16_NOREX2:sub_32bit
2473 0, // GR16_NOREX2:sub_mask_0
2474 0, // GR16_NOREX2:sub_mask_1
2475 0, // GR16_NOREX2:sub_xmm
2476 0, // GR16_NOREX2:sub_ymm
2477 },
2478 { // GR16_NOREX
2479 3, // GR16_NOREX:sub_8bit -> GR8_NOREX2
2480 5, // GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
2481 0, // GR16_NOREX:sub_8bit_hi_phony
2482 0, // GR16_NOREX:sub_16bit
2483 0, // GR16_NOREX:sub_16bit_hi
2484 0, // GR16_NOREX:sub_32bit
2485 0, // GR16_NOREX:sub_mask_0
2486 0, // GR16_NOREX:sub_mask_1
2487 0, // GR16_NOREX:sub_xmm
2488 0, // GR16_NOREX:sub_ymm
2489 },
2490 { // VK1
2491 0, // VK1:sub_8bit
2492 0, // VK1:sub_8bit_hi
2493 0, // VK1:sub_8bit_hi_phony
2494 0, // VK1:sub_16bit
2495 0, // VK1:sub_16bit_hi
2496 0, // VK1:sub_32bit
2497 0, // VK1:sub_mask_0
2498 0, // VK1:sub_mask_1
2499 0, // VK1:sub_xmm
2500 0, // VK1:sub_ymm
2501 },
2502 { // VK16
2503 0, // VK16:sub_8bit
2504 0, // VK16:sub_8bit_hi
2505 0, // VK16:sub_8bit_hi_phony
2506 0, // VK16:sub_16bit
2507 0, // VK16:sub_16bit_hi
2508 0, // VK16:sub_32bit
2509 0, // VK16:sub_mask_0
2510 0, // VK16:sub_mask_1
2511 0, // VK16:sub_xmm
2512 0, // VK16:sub_ymm
2513 },
2514 { // VK2
2515 0, // VK2:sub_8bit
2516 0, // VK2:sub_8bit_hi
2517 0, // VK2:sub_8bit_hi_phony
2518 0, // VK2:sub_16bit
2519 0, // VK2:sub_16bit_hi
2520 0, // VK2:sub_32bit
2521 0, // VK2:sub_mask_0
2522 0, // VK2:sub_mask_1
2523 0, // VK2:sub_xmm
2524 0, // VK2:sub_ymm
2525 },
2526 { // VK4
2527 0, // VK4:sub_8bit
2528 0, // VK4:sub_8bit_hi
2529 0, // VK4:sub_8bit_hi_phony
2530 0, // VK4:sub_16bit
2531 0, // VK4:sub_16bit_hi
2532 0, // VK4:sub_32bit
2533 0, // VK4:sub_mask_0
2534 0, // VK4:sub_mask_1
2535 0, // VK4:sub_xmm
2536 0, // VK4:sub_ymm
2537 },
2538 { // VK8
2539 0, // VK8:sub_8bit
2540 0, // VK8:sub_8bit_hi
2541 0, // VK8:sub_8bit_hi_phony
2542 0, // VK8:sub_16bit
2543 0, // VK8:sub_16bit_hi
2544 0, // VK8:sub_32bit
2545 0, // VK8:sub_mask_0
2546 0, // VK8:sub_mask_1
2547 0, // VK8:sub_xmm
2548 0, // VK8:sub_ymm
2549 },
2550 { // VK16WM
2551 0, // VK16WM:sub_8bit
2552 0, // VK16WM:sub_8bit_hi
2553 0, // VK16WM:sub_8bit_hi_phony
2554 0, // VK16WM:sub_16bit
2555 0, // VK16WM:sub_16bit_hi
2556 0, // VK16WM:sub_32bit
2557 0, // VK16WM:sub_mask_0
2558 0, // VK16WM:sub_mask_1
2559 0, // VK16WM:sub_xmm
2560 0, // VK16WM:sub_ymm
2561 },
2562 { // VK1WM
2563 0, // VK1WM:sub_8bit
2564 0, // VK1WM:sub_8bit_hi
2565 0, // VK1WM:sub_8bit_hi_phony
2566 0, // VK1WM:sub_16bit
2567 0, // VK1WM:sub_16bit_hi
2568 0, // VK1WM:sub_32bit
2569 0, // VK1WM:sub_mask_0
2570 0, // VK1WM:sub_mask_1
2571 0, // VK1WM:sub_xmm
2572 0, // VK1WM:sub_ymm
2573 },
2574 { // VK2WM
2575 0, // VK2WM:sub_8bit
2576 0, // VK2WM:sub_8bit_hi
2577 0, // VK2WM:sub_8bit_hi_phony
2578 0, // VK2WM:sub_16bit
2579 0, // VK2WM:sub_16bit_hi
2580 0, // VK2WM:sub_32bit
2581 0, // VK2WM:sub_mask_0
2582 0, // VK2WM:sub_mask_1
2583 0, // VK2WM:sub_xmm
2584 0, // VK2WM:sub_ymm
2585 },
2586 { // VK4WM
2587 0, // VK4WM:sub_8bit
2588 0, // VK4WM:sub_8bit_hi
2589 0, // VK4WM:sub_8bit_hi_phony
2590 0, // VK4WM:sub_16bit
2591 0, // VK4WM:sub_16bit_hi
2592 0, // VK4WM:sub_32bit
2593 0, // VK4WM:sub_mask_0
2594 0, // VK4WM:sub_mask_1
2595 0, // VK4WM:sub_xmm
2596 0, // VK4WM:sub_ymm
2597 },
2598 { // VK8WM
2599 0, // VK8WM:sub_8bit
2600 0, // VK8WM:sub_8bit_hi
2601 0, // VK8WM:sub_8bit_hi_phony
2602 0, // VK8WM:sub_16bit
2603 0, // VK8WM:sub_16bit_hi
2604 0, // VK8WM:sub_32bit
2605 0, // VK8WM:sub_mask_0
2606 0, // VK8WM:sub_mask_1
2607 0, // VK8WM:sub_xmm
2608 0, // VK8WM:sub_ymm
2609 },
2610 { // SEGMENT_REG
2611 0, // SEGMENT_REG:sub_8bit
2612 0, // SEGMENT_REG:sub_8bit_hi
2613 0, // SEGMENT_REG:sub_8bit_hi_phony
2614 0, // SEGMENT_REG:sub_16bit
2615 0, // SEGMENT_REG:sub_16bit_hi
2616 0, // SEGMENT_REG:sub_32bit
2617 0, // SEGMENT_REG:sub_mask_0
2618 0, // SEGMENT_REG:sub_mask_1
2619 0, // SEGMENT_REG:sub_xmm
2620 0, // SEGMENT_REG:sub_ymm
2621 },
2622 { // GR16_ABCD
2623 6, // GR16_ABCD:sub_8bit -> GR8_ABCD_L
2624 5, // GR16_ABCD:sub_8bit_hi -> GR8_ABCD_H
2625 0, // GR16_ABCD:sub_8bit_hi_phony
2626 0, // GR16_ABCD:sub_16bit
2627 0, // GR16_ABCD:sub_16bit_hi
2628 0, // GR16_ABCD:sub_32bit
2629 0, // GR16_ABCD:sub_mask_0
2630 0, // GR16_ABCD:sub_mask_1
2631 0, // GR16_ABCD:sub_xmm
2632 0, // GR16_ABCD:sub_ymm
2633 },
2634 { // FPCCR
2635 0, // FPCCR:sub_8bit
2636 0, // FPCCR:sub_8bit_hi
2637 0, // FPCCR:sub_8bit_hi_phony
2638 0, // FPCCR:sub_16bit
2639 0, // FPCCR:sub_16bit_hi
2640 0, // FPCCR:sub_32bit
2641 0, // FPCCR:sub_mask_0
2642 0, // FPCCR:sub_mask_1
2643 0, // FPCCR:sub_xmm
2644 0, // FPCCR:sub_ymm
2645 },
2646 { // FR16X
2647 0, // FR16X:sub_8bit
2648 0, // FR16X:sub_8bit_hi
2649 0, // FR16X:sub_8bit_hi_phony
2650 0, // FR16X:sub_16bit
2651 0, // FR16X:sub_16bit_hi
2652 0, // FR16X:sub_32bit
2653 0, // FR16X:sub_mask_0
2654 0, // FR16X:sub_mask_1
2655 0, // FR16X:sub_xmm
2656 0, // FR16X:sub_ymm
2657 },
2658 { // FR16
2659 0, // FR16:sub_8bit
2660 0, // FR16:sub_8bit_hi
2661 0, // FR16:sub_8bit_hi_phony
2662 0, // FR16:sub_16bit
2663 0, // FR16:sub_16bit_hi
2664 0, // FR16:sub_32bit
2665 0, // FR16:sub_mask_0
2666 0, // FR16:sub_mask_1
2667 0, // FR16:sub_xmm
2668 0, // FR16:sub_ymm
2669 },
2670 { // VK16PAIR
2671 0, // VK16PAIR:sub_8bit
2672 0, // VK16PAIR:sub_8bit_hi
2673 0, // VK16PAIR:sub_8bit_hi_phony
2674 0, // VK16PAIR:sub_16bit
2675 0, // VK16PAIR:sub_16bit_hi
2676 0, // VK16PAIR:sub_32bit
2677 91, // VK16PAIR:sub_mask_0 -> VK64
2678 98, // VK16PAIR:sub_mask_1 -> VK64WM
2679 0, // VK16PAIR:sub_xmm
2680 0, // VK16PAIR:sub_ymm
2681 },
2682 { // VK1PAIR
2683 0, // VK1PAIR:sub_8bit
2684 0, // VK1PAIR:sub_8bit_hi
2685 0, // VK1PAIR:sub_8bit_hi_phony
2686 0, // VK1PAIR:sub_16bit
2687 0, // VK1PAIR:sub_16bit_hi
2688 0, // VK1PAIR:sub_32bit
2689 91, // VK1PAIR:sub_mask_0 -> VK64
2690 98, // VK1PAIR:sub_mask_1 -> VK64WM
2691 0, // VK1PAIR:sub_xmm
2692 0, // VK1PAIR:sub_ymm
2693 },
2694 { // VK2PAIR
2695 0, // VK2PAIR:sub_8bit
2696 0, // VK2PAIR:sub_8bit_hi
2697 0, // VK2PAIR:sub_8bit_hi_phony
2698 0, // VK2PAIR:sub_16bit
2699 0, // VK2PAIR:sub_16bit_hi
2700 0, // VK2PAIR:sub_32bit
2701 91, // VK2PAIR:sub_mask_0 -> VK64
2702 98, // VK2PAIR:sub_mask_1 -> VK64WM
2703 0, // VK2PAIR:sub_xmm
2704 0, // VK2PAIR:sub_ymm
2705 },
2706 { // VK4PAIR
2707 0, // VK4PAIR:sub_8bit
2708 0, // VK4PAIR:sub_8bit_hi
2709 0, // VK4PAIR:sub_8bit_hi_phony
2710 0, // VK4PAIR:sub_16bit
2711 0, // VK4PAIR:sub_16bit_hi
2712 0, // VK4PAIR:sub_32bit
2713 91, // VK4PAIR:sub_mask_0 -> VK64
2714 98, // VK4PAIR:sub_mask_1 -> VK64WM
2715 0, // VK4PAIR:sub_xmm
2716 0, // VK4PAIR:sub_ymm
2717 },
2718 { // VK8PAIR
2719 0, // VK8PAIR:sub_8bit
2720 0, // VK8PAIR:sub_8bit_hi
2721 0, // VK8PAIR:sub_8bit_hi_phony
2722 0, // VK8PAIR:sub_16bit
2723 0, // VK8PAIR:sub_16bit_hi
2724 0, // VK8PAIR:sub_32bit
2725 91, // VK8PAIR:sub_mask_0 -> VK64
2726 98, // VK8PAIR:sub_mask_1 -> VK64WM
2727 0, // VK8PAIR:sub_xmm
2728 0, // VK8PAIR:sub_ymm
2729 },
2730 { // VK1PAIR_with_sub_mask_0_in_VK1WM
2731 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_8bit
2732 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_8bit_hi
2733 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_8bit_hi_phony
2734 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_16bit
2735 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_16bit_hi
2736 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_32bit
2737 98, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_mask_0 -> VK64WM
2738 98, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_mask_1 -> VK64WM
2739 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_xmm
2740 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_ymm
2741 },
2742 { // LOW32_ADDR_ACCESS_RBP
2743 1, // LOW32_ADDR_ACCESS_RBP:sub_8bit -> GR8
2744 5, // LOW32_ADDR_ACCESS_RBP:sub_8bit_hi -> GR8_ABCD_H
2745 0, // LOW32_ADDR_ACCESS_RBP:sub_8bit_hi_phony
2746 8, // LOW32_ADDR_ACCESS_RBP:sub_16bit -> GR16
2747 0, // LOW32_ADDR_ACCESS_RBP:sub_16bit_hi
2748 66, // LOW32_ADDR_ACCESS_RBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
2749 0, // LOW32_ADDR_ACCESS_RBP:sub_mask_0
2750 0, // LOW32_ADDR_ACCESS_RBP:sub_mask_1
2751 0, // LOW32_ADDR_ACCESS_RBP:sub_xmm
2752 0, // LOW32_ADDR_ACCESS_RBP:sub_ymm
2753 },
2754 { // LOW32_ADDR_ACCESS
2755 1, // LOW32_ADDR_ACCESS:sub_8bit -> GR8
2756 5, // LOW32_ADDR_ACCESS:sub_8bit_hi -> GR8_ABCD_H
2757 0, // LOW32_ADDR_ACCESS:sub_8bit_hi_phony
2758 8, // LOW32_ADDR_ACCESS:sub_16bit -> GR16
2759 0, // LOW32_ADDR_ACCESS:sub_16bit_hi
2760 0, // LOW32_ADDR_ACCESS:sub_32bit
2761 0, // LOW32_ADDR_ACCESS:sub_mask_0
2762 0, // LOW32_ADDR_ACCESS:sub_mask_1
2763 0, // LOW32_ADDR_ACCESS:sub_xmm
2764 0, // LOW32_ADDR_ACCESS:sub_ymm
2765 },
2766 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
2767 1, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit -> GR8
2768 5, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
2769 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit_hi_phony
2770 8, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_16bit -> GR16
2771 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_16bit_hi
2772 66, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
2773 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_mask_0
2774 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_mask_1
2775 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_xmm
2776 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_ymm
2777 },
2778 { // FR32X
2779 0, // FR32X:sub_8bit
2780 0, // FR32X:sub_8bit_hi
2781 0, // FR32X:sub_8bit_hi_phony
2782 0, // FR32X:sub_16bit
2783 0, // FR32X:sub_16bit_hi
2784 0, // FR32X:sub_32bit
2785 0, // FR32X:sub_mask_0
2786 0, // FR32X:sub_mask_1
2787 0, // FR32X:sub_xmm
2788 0, // FR32X:sub_ymm
2789 },
2790 { // GR32
2791 1, // GR32:sub_8bit -> GR8
2792 5, // GR32:sub_8bit_hi -> GR8_ABCD_H
2793 0, // GR32:sub_8bit_hi_phony
2794 8, // GR32:sub_16bit -> GR16
2795 0, // GR32:sub_16bit_hi
2796 0, // GR32:sub_32bit
2797 0, // GR32:sub_mask_0
2798 0, // GR32:sub_mask_1
2799 0, // GR32:sub_xmm
2800 0, // GR32:sub_ymm
2801 },
2802 { // GR32_NOSP
2803 1, // GR32_NOSP:sub_8bit -> GR8
2804 5, // GR32_NOSP:sub_8bit_hi -> GR8_ABCD_H
2805 0, // GR32_NOSP:sub_8bit_hi_phony
2806 8, // GR32_NOSP:sub_16bit -> GR16
2807 0, // GR32_NOSP:sub_16bit_hi
2808 0, // GR32_NOSP:sub_32bit
2809 0, // GR32_NOSP:sub_mask_0
2810 0, // GR32_NOSP:sub_mask_1
2811 0, // GR32_NOSP:sub_xmm
2812 0, // GR32_NOSP:sub_ymm
2813 },
2814 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
2815 3, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_8bit -> GR8_NOREX2
2816 5, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi -> GR8_ABCD_H
2817 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi_phony
2818 9, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_16bit -> GR16_NOREX2
2819 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_16bit_hi
2820 66, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_32bit -> GR32_BPSP_and_GR32_DIBP
2821 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_mask_0
2822 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_mask_1
2823 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_xmm
2824 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_ymm
2825 },
2826 { // DEBUG_REG
2827 0, // DEBUG_REG:sub_8bit
2828 0, // DEBUG_REG:sub_8bit_hi
2829 0, // DEBUG_REG:sub_8bit_hi_phony
2830 0, // DEBUG_REG:sub_16bit
2831 0, // DEBUG_REG:sub_16bit_hi
2832 0, // DEBUG_REG:sub_32bit
2833 0, // DEBUG_REG:sub_mask_0
2834 0, // DEBUG_REG:sub_mask_1
2835 0, // DEBUG_REG:sub_xmm
2836 0, // DEBUG_REG:sub_ymm
2837 },
2838 { // FR32
2839 0, // FR32:sub_8bit
2840 0, // FR32:sub_8bit_hi
2841 0, // FR32:sub_8bit_hi_phony
2842 0, // FR32:sub_16bit
2843 0, // FR32:sub_16bit_hi
2844 0, // FR32:sub_32bit
2845 0, // FR32:sub_mask_0
2846 0, // FR32:sub_mask_1
2847 0, // FR32:sub_xmm
2848 0, // FR32:sub_ymm
2849 },
2850 { // GR32_NOREX2
2851 3, // GR32_NOREX2:sub_8bit -> GR8_NOREX2
2852 5, // GR32_NOREX2:sub_8bit_hi -> GR8_ABCD_H
2853 0, // GR32_NOREX2:sub_8bit_hi_phony
2854 9, // GR32_NOREX2:sub_16bit -> GR16_NOREX2
2855 0, // GR32_NOREX2:sub_16bit_hi
2856 0, // GR32_NOREX2:sub_32bit
2857 0, // GR32_NOREX2:sub_mask_0
2858 0, // GR32_NOREX2:sub_mask_1
2859 0, // GR32_NOREX2:sub_xmm
2860 0, // GR32_NOREX2:sub_ymm
2861 },
2862 { // GR32_NOREX2_NOSP
2863 3, // GR32_NOREX2_NOSP:sub_8bit -> GR8_NOREX2
2864 5, // GR32_NOREX2_NOSP:sub_8bit_hi -> GR8_ABCD_H
2865 0, // GR32_NOREX2_NOSP:sub_8bit_hi_phony
2866 9, // GR32_NOREX2_NOSP:sub_16bit -> GR16_NOREX2
2867 0, // GR32_NOREX2_NOSP:sub_16bit_hi
2868 0, // GR32_NOREX2_NOSP:sub_32bit
2869 0, // GR32_NOREX2_NOSP:sub_mask_0
2870 0, // GR32_NOREX2_NOSP:sub_mask_1
2871 0, // GR32_NOREX2_NOSP:sub_xmm
2872 0, // GR32_NOREX2_NOSP:sub_ymm
2873 },
2874 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
2875 3, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8_NOREX2
2876 5, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
2877 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
2878 10, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
2879 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
2880 66, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_BPSP_and_GR32_DIBP
2881 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_mask_0
2882 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_mask_1
2883 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_xmm
2884 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_ymm
2885 },
2886 { // GR32_NOREX
2887 3, // GR32_NOREX:sub_8bit -> GR8_NOREX2
2888 5, // GR32_NOREX:sub_8bit_hi -> GR8_ABCD_H
2889 0, // GR32_NOREX:sub_8bit_hi_phony
2890 10, // GR32_NOREX:sub_16bit -> GR16_NOREX
2891 0, // GR32_NOREX:sub_16bit_hi
2892 0, // GR32_NOREX:sub_32bit
2893 0, // GR32_NOREX:sub_mask_0
2894 0, // GR32_NOREX:sub_mask_1
2895 0, // GR32_NOREX:sub_xmm
2896 0, // GR32_NOREX:sub_ymm
2897 },
2898 { // VK32
2899 0, // VK32:sub_8bit
2900 0, // VK32:sub_8bit_hi
2901 0, // VK32:sub_8bit_hi_phony
2902 0, // VK32:sub_16bit
2903 0, // VK32:sub_16bit_hi
2904 0, // VK32:sub_32bit
2905 0, // VK32:sub_mask_0
2906 0, // VK32:sub_mask_1
2907 0, // VK32:sub_xmm
2908 0, // VK32:sub_ymm
2909 },
2910 { // GR32_NOREX_NOSP
2911 3, // GR32_NOREX_NOSP:sub_8bit -> GR8_NOREX2
2912 5, // GR32_NOREX_NOSP:sub_8bit_hi -> GR8_ABCD_H
2913 0, // GR32_NOREX_NOSP:sub_8bit_hi_phony
2914 10, // GR32_NOREX_NOSP:sub_16bit -> GR16_NOREX
2915 0, // GR32_NOREX_NOSP:sub_16bit_hi
2916 0, // GR32_NOREX_NOSP:sub_32bit
2917 0, // GR32_NOREX_NOSP:sub_mask_0
2918 0, // GR32_NOREX_NOSP:sub_mask_1
2919 0, // GR32_NOREX_NOSP:sub_xmm
2920 0, // GR32_NOREX_NOSP:sub_ymm
2921 },
2922 { // RFP32
2923 0, // RFP32:sub_8bit
2924 0, // RFP32:sub_8bit_hi
2925 0, // RFP32:sub_8bit_hi_phony
2926 0, // RFP32:sub_16bit
2927 0, // RFP32:sub_16bit_hi
2928 0, // RFP32:sub_32bit
2929 0, // RFP32:sub_mask_0
2930 0, // RFP32:sub_mask_1
2931 0, // RFP32:sub_xmm
2932 0, // RFP32:sub_ymm
2933 },
2934 { // VK32WM
2935 0, // VK32WM:sub_8bit
2936 0, // VK32WM:sub_8bit_hi
2937 0, // VK32WM:sub_8bit_hi_phony
2938 0, // VK32WM:sub_16bit
2939 0, // VK32WM:sub_16bit_hi
2940 0, // VK32WM:sub_32bit
2941 0, // VK32WM:sub_mask_0
2942 0, // VK32WM:sub_mask_1
2943 0, // VK32WM:sub_xmm
2944 0, // VK32WM:sub_ymm
2945 },
2946 { // GR32_ABCD
2947 6, // GR32_ABCD:sub_8bit -> GR8_ABCD_L
2948 5, // GR32_ABCD:sub_8bit_hi -> GR8_ABCD_H
2949 0, // GR32_ABCD:sub_8bit_hi_phony
2950 22, // GR32_ABCD:sub_16bit -> GR16_ABCD
2951 0, // GR32_ABCD:sub_16bit_hi
2952 0, // GR32_ABCD:sub_32bit
2953 0, // GR32_ABCD:sub_mask_0
2954 0, // GR32_ABCD:sub_mask_1
2955 0, // GR32_ABCD:sub_xmm
2956 0, // GR32_ABCD:sub_ymm
2957 },
2958 { // GR32_TC
2959 3, // GR32_TC:sub_8bit -> GR8_NOREX2
2960 5, // GR32_TC:sub_8bit_hi -> GR8_ABCD_H
2961 0, // GR32_TC:sub_8bit_hi_phony
2962 10, // GR32_TC:sub_16bit -> GR16_NOREX
2963 0, // GR32_TC:sub_16bit_hi
2964 0, // GR32_TC:sub_32bit
2965 0, // GR32_TC:sub_mask_0
2966 0, // GR32_TC:sub_mask_1
2967 0, // GR32_TC:sub_xmm
2968 0, // GR32_TC:sub_ymm
2969 },
2970 { // GR32_ABCD_and_GR32_TC
2971 6, // GR32_ABCD_and_GR32_TC:sub_8bit -> GR8_ABCD_L
2972 5, // GR32_ABCD_and_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
2973 0, // GR32_ABCD_and_GR32_TC:sub_8bit_hi_phony
2974 22, // GR32_ABCD_and_GR32_TC:sub_16bit -> GR16_ABCD
2975 0, // GR32_ABCD_and_GR32_TC:sub_16bit_hi
2976 0, // GR32_ABCD_and_GR32_TC:sub_32bit
2977 0, // GR32_ABCD_and_GR32_TC:sub_mask_0
2978 0, // GR32_ABCD_and_GR32_TC:sub_mask_1
2979 0, // GR32_ABCD_and_GR32_TC:sub_xmm
2980 0, // GR32_ABCD_and_GR32_TC:sub_ymm
2981 },
2982 { // GR32_AD
2983 6, // GR32_AD:sub_8bit -> GR8_ABCD_L
2984 5, // GR32_AD:sub_8bit_hi -> GR8_ABCD_H
2985 0, // GR32_AD:sub_8bit_hi_phony
2986 22, // GR32_AD:sub_16bit -> GR16_ABCD
2987 0, // GR32_AD:sub_16bit_hi
2988 0, // GR32_AD:sub_32bit
2989 0, // GR32_AD:sub_mask_0
2990 0, // GR32_AD:sub_mask_1
2991 0, // GR32_AD:sub_xmm
2992 0, // GR32_AD:sub_ymm
2993 },
2994 { // GR32_ArgRef
2995 6, // GR32_ArgRef:sub_8bit -> GR8_ABCD_L
2996 5, // GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
2997 0, // GR32_ArgRef:sub_8bit_hi_phony
2998 22, // GR32_ArgRef:sub_16bit -> GR16_ABCD
2999 0, // GR32_ArgRef:sub_16bit_hi
3000 0, // GR32_ArgRef:sub_32bit
3001 0, // GR32_ArgRef:sub_mask_0
3002 0, // GR32_ArgRef:sub_mask_1
3003 0, // GR32_ArgRef:sub_xmm
3004 0, // GR32_ArgRef:sub_ymm
3005 },
3006 { // GR32_BPSP
3007 3, // GR32_BPSP:sub_8bit -> GR8_NOREX2
3008 0, // GR32_BPSP:sub_8bit_hi
3009 0, // GR32_BPSP:sub_8bit_hi_phony
3010 10, // GR32_BPSP:sub_16bit -> GR16_NOREX
3011 0, // GR32_BPSP:sub_16bit_hi
3012 0, // GR32_BPSP:sub_32bit
3013 0, // GR32_BPSP:sub_mask_0
3014 0, // GR32_BPSP:sub_mask_1
3015 0, // GR32_BPSP:sub_xmm
3016 0, // GR32_BPSP:sub_ymm
3017 },
3018 { // GR32_BSI
3019 3, // GR32_BSI:sub_8bit -> GR8_NOREX2
3020 5, // GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
3021 0, // GR32_BSI:sub_8bit_hi_phony
3022 10, // GR32_BSI:sub_16bit -> GR16_NOREX
3023 0, // GR32_BSI:sub_16bit_hi
3024 0, // GR32_BSI:sub_32bit
3025 0, // GR32_BSI:sub_mask_0
3026 0, // GR32_BSI:sub_mask_1
3027 0, // GR32_BSI:sub_xmm
3028 0, // GR32_BSI:sub_ymm
3029 },
3030 { // GR32_CB
3031 6, // GR32_CB:sub_8bit -> GR8_ABCD_L
3032 5, // GR32_CB:sub_8bit_hi -> GR8_ABCD_H
3033 0, // GR32_CB:sub_8bit_hi_phony
3034 22, // GR32_CB:sub_16bit -> GR16_ABCD
3035 0, // GR32_CB:sub_16bit_hi
3036 0, // GR32_CB:sub_32bit
3037 0, // GR32_CB:sub_mask_0
3038 0, // GR32_CB:sub_mask_1
3039 0, // GR32_CB:sub_xmm
3040 0, // GR32_CB:sub_ymm
3041 },
3042 { // GR32_DC
3043 6, // GR32_DC:sub_8bit -> GR8_ABCD_L
3044 5, // GR32_DC:sub_8bit_hi -> GR8_ABCD_H
3045 0, // GR32_DC:sub_8bit_hi_phony
3046 22, // GR32_DC:sub_16bit -> GR16_ABCD
3047 0, // GR32_DC:sub_16bit_hi
3048 0, // GR32_DC:sub_32bit
3049 0, // GR32_DC:sub_mask_0
3050 0, // GR32_DC:sub_mask_1
3051 0, // GR32_DC:sub_xmm
3052 0, // GR32_DC:sub_ymm
3053 },
3054 { // GR32_DIBP
3055 3, // GR32_DIBP:sub_8bit -> GR8_NOREX2
3056 0, // GR32_DIBP:sub_8bit_hi
3057 0, // GR32_DIBP:sub_8bit_hi_phony
3058 10, // GR32_DIBP:sub_16bit -> GR16_NOREX
3059 0, // GR32_DIBP:sub_16bit_hi
3060 0, // GR32_DIBP:sub_32bit
3061 0, // GR32_DIBP:sub_mask_0
3062 0, // GR32_DIBP:sub_mask_1
3063 0, // GR32_DIBP:sub_xmm
3064 0, // GR32_DIBP:sub_ymm
3065 },
3066 { // GR32_SIDI
3067 3, // GR32_SIDI:sub_8bit -> GR8_NOREX2
3068 0, // GR32_SIDI:sub_8bit_hi
3069 0, // GR32_SIDI:sub_8bit_hi_phony
3070 10, // GR32_SIDI:sub_16bit -> GR16_NOREX
3071 0, // GR32_SIDI:sub_16bit_hi
3072 0, // GR32_SIDI:sub_32bit
3073 0, // GR32_SIDI:sub_mask_0
3074 0, // GR32_SIDI:sub_mask_1
3075 0, // GR32_SIDI:sub_xmm
3076 0, // GR32_SIDI:sub_ymm
3077 },
3078 { // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
3079 3, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit -> GR8_NOREX2
3080 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit_hi
3081 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit_hi_phony
3082 10, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_16bit -> GR16_NOREX
3083 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_16bit_hi
3084 66, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
3085 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_mask_0
3086 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_mask_1
3087 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_xmm
3088 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_ymm
3089 },
3090 { // CCR
3091 0, // CCR:sub_8bit
3092 0, // CCR:sub_8bit_hi
3093 0, // CCR:sub_8bit_hi_phony
3094 0, // CCR:sub_16bit
3095 0, // CCR:sub_16bit_hi
3096 0, // CCR:sub_32bit
3097 0, // CCR:sub_mask_0
3098 0, // CCR:sub_mask_1
3099 0, // CCR:sub_xmm
3100 0, // CCR:sub_ymm
3101 },
3102 { // DFCCR
3103 0, // DFCCR:sub_8bit
3104 0, // DFCCR:sub_8bit_hi
3105 0, // DFCCR:sub_8bit_hi_phony
3106 0, // DFCCR:sub_16bit
3107 0, // DFCCR:sub_16bit_hi
3108 0, // DFCCR:sub_32bit
3109 0, // DFCCR:sub_mask_0
3110 0, // DFCCR:sub_mask_1
3111 0, // DFCCR:sub_xmm
3112 0, // DFCCR:sub_ymm
3113 },
3114 { // GR32_ABCD_and_GR32_BSI
3115 6, // GR32_ABCD_and_GR32_BSI:sub_8bit -> GR8_ABCD_L
3116 5, // GR32_ABCD_and_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
3117 0, // GR32_ABCD_and_GR32_BSI:sub_8bit_hi_phony
3118 22, // GR32_ABCD_and_GR32_BSI:sub_16bit -> GR16_ABCD
3119 0, // GR32_ABCD_and_GR32_BSI:sub_16bit_hi
3120 0, // GR32_ABCD_and_GR32_BSI:sub_32bit
3121 0, // GR32_ABCD_and_GR32_BSI:sub_mask_0
3122 0, // GR32_ABCD_and_GR32_BSI:sub_mask_1
3123 0, // GR32_ABCD_and_GR32_BSI:sub_xmm
3124 0, // GR32_ABCD_and_GR32_BSI:sub_ymm
3125 },
3126 { // GR32_AD_and_GR32_ArgRef
3127 6, // GR32_AD_and_GR32_ArgRef:sub_8bit -> GR8_ABCD_L
3128 5, // GR32_AD_and_GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
3129 0, // GR32_AD_and_GR32_ArgRef:sub_8bit_hi_phony
3130 22, // GR32_AD_and_GR32_ArgRef:sub_16bit -> GR16_ABCD
3131 0, // GR32_AD_and_GR32_ArgRef:sub_16bit_hi
3132 0, // GR32_AD_and_GR32_ArgRef:sub_32bit
3133 0, // GR32_AD_and_GR32_ArgRef:sub_mask_0
3134 0, // GR32_AD_and_GR32_ArgRef:sub_mask_1
3135 0, // GR32_AD_and_GR32_ArgRef:sub_xmm
3136 0, // GR32_AD_and_GR32_ArgRef:sub_ymm
3137 },
3138 { // GR32_ArgRef_and_GR32_CB
3139 6, // GR32_ArgRef_and_GR32_CB:sub_8bit -> GR8_ABCD_L
3140 5, // GR32_ArgRef_and_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
3141 0, // GR32_ArgRef_and_GR32_CB:sub_8bit_hi_phony
3142 22, // GR32_ArgRef_and_GR32_CB:sub_16bit -> GR16_ABCD
3143 0, // GR32_ArgRef_and_GR32_CB:sub_16bit_hi
3144 0, // GR32_ArgRef_and_GR32_CB:sub_32bit
3145 0, // GR32_ArgRef_and_GR32_CB:sub_mask_0
3146 0, // GR32_ArgRef_and_GR32_CB:sub_mask_1
3147 0, // GR32_ArgRef_and_GR32_CB:sub_xmm
3148 0, // GR32_ArgRef_and_GR32_CB:sub_ymm
3149 },
3150 { // GR32_BPSP_and_GR32_DIBP
3151 3, // GR32_BPSP_and_GR32_DIBP:sub_8bit -> GR8_NOREX2
3152 0, // GR32_BPSP_and_GR32_DIBP:sub_8bit_hi
3153 0, // GR32_BPSP_and_GR32_DIBP:sub_8bit_hi_phony
3154 10, // GR32_BPSP_and_GR32_DIBP:sub_16bit -> GR16_NOREX
3155 0, // GR32_BPSP_and_GR32_DIBP:sub_16bit_hi
3156 0, // GR32_BPSP_and_GR32_DIBP:sub_32bit
3157 0, // GR32_BPSP_and_GR32_DIBP:sub_mask_0
3158 0, // GR32_BPSP_and_GR32_DIBP:sub_mask_1
3159 0, // GR32_BPSP_and_GR32_DIBP:sub_xmm
3160 0, // GR32_BPSP_and_GR32_DIBP:sub_ymm
3161 },
3162 { // GR32_BPSP_and_GR32_TC
3163 3, // GR32_BPSP_and_GR32_TC:sub_8bit -> GR8_NOREX2
3164 0, // GR32_BPSP_and_GR32_TC:sub_8bit_hi
3165 0, // GR32_BPSP_and_GR32_TC:sub_8bit_hi_phony
3166 10, // GR32_BPSP_and_GR32_TC:sub_16bit -> GR16_NOREX
3167 0, // GR32_BPSP_and_GR32_TC:sub_16bit_hi
3168 0, // GR32_BPSP_and_GR32_TC:sub_32bit
3169 0, // GR32_BPSP_and_GR32_TC:sub_mask_0
3170 0, // GR32_BPSP_and_GR32_TC:sub_mask_1
3171 0, // GR32_BPSP_and_GR32_TC:sub_xmm
3172 0, // GR32_BPSP_and_GR32_TC:sub_ymm
3173 },
3174 { // GR32_BSI_and_GR32_SIDI
3175 3, // GR32_BSI_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
3176 0, // GR32_BSI_and_GR32_SIDI:sub_8bit_hi
3177 0, // GR32_BSI_and_GR32_SIDI:sub_8bit_hi_phony
3178 10, // GR32_BSI_and_GR32_SIDI:sub_16bit -> GR16_NOREX
3179 0, // GR32_BSI_and_GR32_SIDI:sub_16bit_hi
3180 0, // GR32_BSI_and_GR32_SIDI:sub_32bit
3181 0, // GR32_BSI_and_GR32_SIDI:sub_mask_0
3182 0, // GR32_BSI_and_GR32_SIDI:sub_mask_1
3183 0, // GR32_BSI_and_GR32_SIDI:sub_xmm
3184 0, // GR32_BSI_and_GR32_SIDI:sub_ymm
3185 },
3186 { // GR32_DIBP_and_GR32_SIDI
3187 3, // GR32_DIBP_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
3188 0, // GR32_DIBP_and_GR32_SIDI:sub_8bit_hi
3189 0, // GR32_DIBP_and_GR32_SIDI:sub_8bit_hi_phony
3190 10, // GR32_DIBP_and_GR32_SIDI:sub_16bit -> GR16_NOREX
3191 0, // GR32_DIBP_and_GR32_SIDI:sub_16bit_hi
3192 0, // GR32_DIBP_and_GR32_SIDI:sub_32bit
3193 0, // GR32_DIBP_and_GR32_SIDI:sub_mask_0
3194 0, // GR32_DIBP_and_GR32_SIDI:sub_mask_1
3195 0, // GR32_DIBP_and_GR32_SIDI:sub_xmm
3196 0, // GR32_DIBP_and_GR32_SIDI:sub_ymm
3197 },
3198 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
3199 3, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit -> GR8_NOREX2
3200 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit_hi
3201 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit_hi_phony
3202 10, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_16bit -> GR16_NOREX
3203 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_16bit_hi
3204 66, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
3205 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_mask_0
3206 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_mask_1
3207 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_xmm
3208 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_ymm
3209 },
3210 { // LOW32_ADDR_ACCESS_with_sub_32bit
3211 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit
3212 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit_hi
3213 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit_hi_phony
3214 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_16bit
3215 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_16bit_hi
3216 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_32bit
3217 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_mask_0
3218 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_mask_1
3219 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_xmm
3220 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_ymm
3221 },
3222 { // RFP64
3223 0, // RFP64:sub_8bit
3224 0, // RFP64:sub_8bit_hi
3225 0, // RFP64:sub_8bit_hi_phony
3226 0, // RFP64:sub_16bit
3227 0, // RFP64:sub_16bit_hi
3228 0, // RFP64:sub_32bit
3229 0, // RFP64:sub_mask_0
3230 0, // RFP64:sub_mask_1
3231 0, // RFP64:sub_xmm
3232 0, // RFP64:sub_ymm
3233 },
3234 { // GR64
3235 1, // GR64:sub_8bit -> GR8
3236 5, // GR64:sub_8bit_hi -> GR8_ABCD_H
3237 0, // GR64:sub_8bit_hi_phony
3238 8, // GR64:sub_16bit -> GR16
3239 0, // GR64:sub_16bit_hi
3240 36, // GR64:sub_32bit -> GR32
3241 0, // GR64:sub_mask_0
3242 0, // GR64:sub_mask_1
3243 0, // GR64:sub_xmm
3244 0, // GR64:sub_ymm
3245 },
3246 { // FR64X
3247 0, // FR64X:sub_8bit
3248 0, // FR64X:sub_8bit_hi
3249 0, // FR64X:sub_8bit_hi_phony
3250 0, // FR64X:sub_16bit
3251 0, // FR64X:sub_16bit_hi
3252 0, // FR64X:sub_32bit
3253 0, // FR64X:sub_mask_0
3254 0, // FR64X:sub_mask_1
3255 0, // FR64X:sub_xmm
3256 0, // FR64X:sub_ymm
3257 },
3258 { // GR64_with_sub_8bit
3259 1, // GR64_with_sub_8bit:sub_8bit -> GR8
3260 5, // GR64_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
3261 0, // GR64_with_sub_8bit:sub_8bit_hi_phony
3262 8, // GR64_with_sub_8bit:sub_16bit -> GR16
3263 0, // GR64_with_sub_8bit:sub_16bit_hi
3264 36, // GR64_with_sub_8bit:sub_32bit -> GR32
3265 0, // GR64_with_sub_8bit:sub_mask_0
3266 0, // GR64_with_sub_8bit:sub_mask_1
3267 0, // GR64_with_sub_8bit:sub_xmm
3268 0, // GR64_with_sub_8bit:sub_ymm
3269 },
3270 { // GR64_NOSP
3271 1, // GR64_NOSP:sub_8bit -> GR8
3272 5, // GR64_NOSP:sub_8bit_hi -> GR8_ABCD_H
3273 0, // GR64_NOSP:sub_8bit_hi_phony
3274 8, // GR64_NOSP:sub_16bit -> GR16
3275 0, // GR64_NOSP:sub_16bit_hi
3276 37, // GR64_NOSP:sub_32bit -> GR32_NOSP
3277 0, // GR64_NOSP:sub_mask_0
3278 0, // GR64_NOSP:sub_mask_1
3279 0, // GR64_NOSP:sub_xmm
3280 0, // GR64_NOSP:sub_ymm
3281 },
3282 { // GR64_NOREX2
3283 3, // GR64_NOREX2:sub_8bit -> GR8_NOREX2
3284 5, // GR64_NOREX2:sub_8bit_hi -> GR8_ABCD_H
3285 0, // GR64_NOREX2:sub_8bit_hi_phony
3286 9, // GR64_NOREX2:sub_16bit -> GR16_NOREX2
3287 0, // GR64_NOREX2:sub_16bit_hi
3288 41, // GR64_NOREX2:sub_32bit -> GR32_NOREX2
3289 0, // GR64_NOREX2:sub_mask_0
3290 0, // GR64_NOREX2:sub_mask_1
3291 0, // GR64_NOREX2:sub_xmm
3292 0, // GR64_NOREX2:sub_ymm
3293 },
3294 { // CONTROL_REG
3295 0, // CONTROL_REG:sub_8bit
3296 0, // CONTROL_REG:sub_8bit_hi
3297 0, // CONTROL_REG:sub_8bit_hi_phony
3298 0, // CONTROL_REG:sub_16bit
3299 0, // CONTROL_REG:sub_16bit_hi
3300 0, // CONTROL_REG:sub_32bit
3301 0, // CONTROL_REG:sub_mask_0
3302 0, // CONTROL_REG:sub_mask_1
3303 0, // CONTROL_REG:sub_xmm
3304 0, // CONTROL_REG:sub_ymm
3305 },
3306 { // FR64
3307 0, // FR64:sub_8bit
3308 0, // FR64:sub_8bit_hi
3309 0, // FR64:sub_8bit_hi_phony
3310 0, // FR64:sub_16bit
3311 0, // FR64:sub_16bit_hi
3312 0, // FR64:sub_32bit
3313 0, // FR64:sub_mask_0
3314 0, // FR64:sub_mask_1
3315 0, // FR64:sub_xmm
3316 0, // FR64:sub_ymm
3317 },
3318 { // GR64_with_sub_16bit_in_GR16_NOREX2
3319 3, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_8bit -> GR8_NOREX2
3320 5, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi -> GR8_ABCD_H
3321 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi_phony
3322 9, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_16bit -> GR16_NOREX2
3323 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_16bit_hi
3324 41, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_32bit -> GR32_NOREX2
3325 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_mask_0
3326 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_mask_1
3327 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_xmm
3328 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_ymm
3329 },
3330 { // GR64_NOREX2_NOSP
3331 3, // GR64_NOREX2_NOSP:sub_8bit -> GR8_NOREX2
3332 5, // GR64_NOREX2_NOSP:sub_8bit_hi -> GR8_ABCD_H
3333 0, // GR64_NOREX2_NOSP:sub_8bit_hi_phony
3334 9, // GR64_NOREX2_NOSP:sub_16bit -> GR16_NOREX2
3335 0, // GR64_NOREX2_NOSP:sub_16bit_hi
3336 42, // GR64_NOREX2_NOSP:sub_32bit -> GR32_NOREX2_NOSP
3337 0, // GR64_NOREX2_NOSP:sub_mask_0
3338 0, // GR64_NOREX2_NOSP:sub_mask_1
3339 0, // GR64_NOREX2_NOSP:sub_xmm
3340 0, // GR64_NOREX2_NOSP:sub_ymm
3341 },
3342 { // GR64PLTSafe
3343 3, // GR64PLTSafe:sub_8bit -> GR8_NOREX2
3344 5, // GR64PLTSafe:sub_8bit_hi -> GR8_ABCD_H
3345 0, // GR64PLTSafe:sub_8bit_hi_phony
3346 9, // GR64PLTSafe:sub_16bit -> GR16_NOREX2
3347 0, // GR64PLTSafe:sub_16bit_hi
3348 42, // GR64PLTSafe:sub_32bit -> GR32_NOREX2_NOSP
3349 0, // GR64PLTSafe:sub_mask_0
3350 0, // GR64PLTSafe:sub_mask_1
3351 0, // GR64PLTSafe:sub_xmm
3352 0, // GR64PLTSafe:sub_ymm
3353 },
3354 { // GR64_TC
3355 3, // GR64_TC:sub_8bit -> GR8_NOREX2
3356 5, // GR64_TC:sub_8bit_hi -> GR8_ABCD_H
3357 0, // GR64_TC:sub_8bit_hi_phony
3358 9, // GR64_TC:sub_16bit -> GR16_NOREX2
3359 0, // GR64_TC:sub_16bit_hi
3360 41, // GR64_TC:sub_32bit -> GR32_NOREX2
3361 0, // GR64_TC:sub_mask_0
3362 0, // GR64_TC:sub_mask_1
3363 0, // GR64_TC:sub_xmm
3364 0, // GR64_TC:sub_ymm
3365 },
3366 { // GR64_NOREX
3367 3, // GR64_NOREX:sub_8bit -> GR8_NOREX2
3368 5, // GR64_NOREX:sub_8bit_hi -> GR8_ABCD_H
3369 0, // GR64_NOREX:sub_8bit_hi_phony
3370 10, // GR64_NOREX:sub_16bit -> GR16_NOREX
3371 0, // GR64_NOREX:sub_16bit_hi
3372 44, // GR64_NOREX:sub_32bit -> GR32_NOREX
3373 0, // GR64_NOREX:sub_mask_0
3374 0, // GR64_NOREX:sub_mask_1
3375 0, // GR64_NOREX:sub_xmm
3376 0, // GR64_NOREX:sub_ymm
3377 },
3378 { // GR64_TCW64
3379 3, // GR64_TCW64:sub_8bit -> GR8_NOREX2
3380 5, // GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
3381 0, // GR64_TCW64:sub_8bit_hi_phony
3382 9, // GR64_TCW64:sub_16bit -> GR16_NOREX2
3383 0, // GR64_TCW64:sub_16bit_hi
3384 41, // GR64_TCW64:sub_32bit -> GR32_NOREX2
3385 0, // GR64_TCW64:sub_mask_0
3386 0, // GR64_TCW64:sub_mask_1
3387 0, // GR64_TCW64:sub_xmm
3388 0, // GR64_TCW64:sub_ymm
3389 },
3390 { // GR64_TC_with_sub_8bit
3391 3, // GR64_TC_with_sub_8bit:sub_8bit -> GR8_NOREX2
3392 5, // GR64_TC_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
3393 0, // GR64_TC_with_sub_8bit:sub_8bit_hi_phony
3394 9, // GR64_TC_with_sub_8bit:sub_16bit -> GR16_NOREX2
3395 0, // GR64_TC_with_sub_8bit:sub_16bit_hi
3396 41, // GR64_TC_with_sub_8bit:sub_32bit -> GR32_NOREX2
3397 0, // GR64_TC_with_sub_8bit:sub_mask_0
3398 0, // GR64_TC_with_sub_8bit:sub_mask_1
3399 0, // GR64_TC_with_sub_8bit:sub_xmm
3400 0, // GR64_TC_with_sub_8bit:sub_ymm
3401 },
3402 { // GR64_NOREX2_NOSP_and_GR64_TC
3403 3, // GR64_NOREX2_NOSP_and_GR64_TC:sub_8bit -> GR8_NOREX2
3404 5, // GR64_NOREX2_NOSP_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
3405 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_8bit_hi_phony
3406 9, // GR64_NOREX2_NOSP_and_GR64_TC:sub_16bit -> GR16_NOREX2
3407 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_16bit_hi
3408 42, // GR64_NOREX2_NOSP_and_GR64_TC:sub_32bit -> GR32_NOREX2_NOSP
3409 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_mask_0
3410 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_mask_1
3411 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_xmm
3412 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_ymm
3413 },
3414 { // GR64_TCW64_with_sub_8bit
3415 3, // GR64_TCW64_with_sub_8bit:sub_8bit -> GR8_NOREX2
3416 5, // GR64_TCW64_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
3417 0, // GR64_TCW64_with_sub_8bit:sub_8bit_hi_phony
3418 9, // GR64_TCW64_with_sub_8bit:sub_16bit -> GR16_NOREX2
3419 0, // GR64_TCW64_with_sub_8bit:sub_16bit_hi
3420 41, // GR64_TCW64_with_sub_8bit:sub_32bit -> GR32_NOREX2
3421 0, // GR64_TCW64_with_sub_8bit:sub_mask_0
3422 0, // GR64_TCW64_with_sub_8bit:sub_mask_1
3423 0, // GR64_TCW64_with_sub_8bit:sub_xmm
3424 0, // GR64_TCW64_with_sub_8bit:sub_ymm
3425 },
3426 { // GR64_TC_and_GR64_TCW64
3427 3, // GR64_TC_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
3428 5, // GR64_TC_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
3429 0, // GR64_TC_and_GR64_TCW64:sub_8bit_hi_phony
3430 9, // GR64_TC_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
3431 0, // GR64_TC_and_GR64_TCW64:sub_16bit_hi
3432 41, // GR64_TC_and_GR64_TCW64:sub_32bit -> GR32_NOREX2
3433 0, // GR64_TC_and_GR64_TCW64:sub_mask_0
3434 0, // GR64_TC_and_GR64_TCW64:sub_mask_1
3435 0, // GR64_TC_and_GR64_TCW64:sub_xmm
3436 0, // GR64_TC_and_GR64_TCW64:sub_ymm
3437 },
3438 { // GR64_with_sub_16bit_in_GR16_NOREX
3439 3, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8_NOREX2
3440 5, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
3441 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
3442 10, // GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
3443 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
3444 44, // GR64_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_NOREX
3445 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_0
3446 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_1
3447 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_xmm
3448 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_ymm
3449 },
3450 { // VK64
3451 0, // VK64:sub_8bit
3452 0, // VK64:sub_8bit_hi
3453 0, // VK64:sub_8bit_hi_phony
3454 0, // VK64:sub_16bit
3455 0, // VK64:sub_16bit_hi
3456 0, // VK64:sub_32bit
3457 0, // VK64:sub_mask_0
3458 0, // VK64:sub_mask_1
3459 0, // VK64:sub_xmm
3460 0, // VK64:sub_ymm
3461 },
3462 { // VR64
3463 0, // VR64:sub_8bit
3464 0, // VR64:sub_8bit_hi
3465 0, // VR64:sub_8bit_hi_phony
3466 0, // VR64:sub_16bit
3467 0, // VR64:sub_16bit_hi
3468 0, // VR64:sub_32bit
3469 0, // VR64:sub_mask_0
3470 0, // VR64:sub_mask_1
3471 0, // VR64:sub_xmm
3472 0, // VR64:sub_ymm
3473 },
3474 { // GR64PLTSafe_and_GR64_TC
3475 3, // GR64PLTSafe_and_GR64_TC:sub_8bit -> GR8_NOREX2
3476 5, // GR64PLTSafe_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
3477 0, // GR64PLTSafe_and_GR64_TC:sub_8bit_hi_phony
3478 9, // GR64PLTSafe_and_GR64_TC:sub_16bit -> GR16_NOREX2
3479 0, // GR64PLTSafe_and_GR64_TC:sub_16bit_hi
3480 42, // GR64PLTSafe_and_GR64_TC:sub_32bit -> GR32_NOREX2_NOSP
3481 0, // GR64PLTSafe_and_GR64_TC:sub_mask_0
3482 0, // GR64PLTSafe_and_GR64_TC:sub_mask_1
3483 0, // GR64PLTSafe_and_GR64_TC:sub_xmm
3484 0, // GR64PLTSafe_and_GR64_TC:sub_ymm
3485 },
3486 { // GR64_NOREX2_NOSP_and_GR64_TCW64
3487 3, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
3488 5, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
3489 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi_phony
3490 9, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
3491 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit_hi
3492 42, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_32bit -> GR32_NOREX2_NOSP
3493 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_0
3494 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_1
3495 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_xmm
3496 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_ymm
3497 },
3498 { // GR64_NOREX_NOSP
3499 3, // GR64_NOREX_NOSP:sub_8bit -> GR8_NOREX2
3500 5, // GR64_NOREX_NOSP:sub_8bit_hi -> GR8_ABCD_H
3501 0, // GR64_NOREX_NOSP:sub_8bit_hi_phony
3502 10, // GR64_NOREX_NOSP:sub_16bit -> GR16_NOREX
3503 0, // GR64_NOREX_NOSP:sub_16bit_hi
3504 46, // GR64_NOREX_NOSP:sub_32bit -> GR32_NOREX_NOSP
3505 0, // GR64_NOREX_NOSP:sub_mask_0
3506 0, // GR64_NOREX_NOSP:sub_mask_1
3507 0, // GR64_NOREX_NOSP:sub_xmm
3508 0, // GR64_NOREX_NOSP:sub_ymm
3509 },
3510 { // GR64_NOREX_and_GR64_TC
3511 3, // GR64_NOREX_and_GR64_TC:sub_8bit -> GR8_NOREX2
3512 5, // GR64_NOREX_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
3513 0, // GR64_NOREX_and_GR64_TC:sub_8bit_hi_phony
3514 10, // GR64_NOREX_and_GR64_TC:sub_16bit -> GR16_NOREX
3515 0, // GR64_NOREX_and_GR64_TC:sub_16bit_hi
3516 44, // GR64_NOREX_and_GR64_TC:sub_32bit -> GR32_NOREX
3517 0, // GR64_NOREX_and_GR64_TC:sub_mask_0
3518 0, // GR64_NOREX_and_GR64_TC:sub_mask_1
3519 0, // GR64_NOREX_and_GR64_TC:sub_xmm
3520 0, // GR64_NOREX_and_GR64_TC:sub_ymm
3521 },
3522 { // GR64_TCW64_and_GR64_TC_with_sub_8bit
3523 3, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit -> GR8_NOREX2
3524 5, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
3525 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit_hi_phony
3526 9, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_16bit -> GR16_NOREX2
3527 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_16bit_hi
3528 41, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_32bit -> GR32_NOREX2
3529 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_mask_0
3530 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_mask_1
3531 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_xmm
3532 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_ymm
3533 },
3534 { // VK64WM
3535 0, // VK64WM:sub_8bit
3536 0, // VK64WM:sub_8bit_hi
3537 0, // VK64WM:sub_8bit_hi_phony
3538 0, // VK64WM:sub_16bit
3539 0, // VK64WM:sub_16bit_hi
3540 0, // VK64WM:sub_32bit
3541 0, // VK64WM:sub_mask_0
3542 0, // VK64WM:sub_mask_1
3543 0, // VK64WM:sub_xmm
3544 0, // VK64WM:sub_ymm
3545 },
3546 { // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
3547 3, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
3548 5, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
3549 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi_phony
3550 9, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
3551 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit_hi
3552 42, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_32bit -> GR32_NOREX2_NOSP
3553 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_0
3554 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_1
3555 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_xmm
3556 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_ymm
3557 },
3558 { // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
3559 3, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8_NOREX2
3560 5, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
3561 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
3562 10, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
3563 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
3564 44, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_NOREX
3565 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_0
3566 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_1
3567 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_xmm
3568 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_ymm
3569 },
3570 { // GR64PLTSafe_and_GR64_TCW64
3571 3, // GR64PLTSafe_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
3572 5, // GR64PLTSafe_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
3573 0, // GR64PLTSafe_and_GR64_TCW64:sub_8bit_hi_phony
3574 9, // GR64PLTSafe_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
3575 0, // GR64PLTSafe_and_GR64_TCW64:sub_16bit_hi
3576 42, // GR64PLTSafe_and_GR64_TCW64:sub_32bit -> GR32_NOREX2_NOSP
3577 0, // GR64PLTSafe_and_GR64_TCW64:sub_mask_0
3578 0, // GR64PLTSafe_and_GR64_TCW64:sub_mask_1
3579 0, // GR64PLTSafe_and_GR64_TCW64:sub_xmm
3580 0, // GR64PLTSafe_and_GR64_TCW64:sub_ymm
3581 },
3582 { // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
3583 3, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit -> GR8_NOREX2
3584 5, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
3585 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit_hi_phony
3586 10, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_16bit -> GR16_NOREX
3587 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_16bit_hi
3588 46, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_32bit -> GR32_NOREX_NOSP
3589 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_mask_0
3590 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_mask_1
3591 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_xmm
3592 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_ymm
3593 },
3594 { // GR64_NOREX_and_GR64_TCW64
3595 3, // GR64_NOREX_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
3596 5, // GR64_NOREX_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
3597 0, // GR64_NOREX_and_GR64_TCW64:sub_8bit_hi_phony
3598 10, // GR64_NOREX_and_GR64_TCW64:sub_16bit -> GR16_NOREX
3599 0, // GR64_NOREX_and_GR64_TCW64:sub_16bit_hi
3600 50, // GR64_NOREX_and_GR64_TCW64:sub_32bit -> GR32_TC
3601 0, // GR64_NOREX_and_GR64_TCW64:sub_mask_0
3602 0, // GR64_NOREX_and_GR64_TCW64:sub_mask_1
3603 0, // GR64_NOREX_and_GR64_TCW64:sub_xmm
3604 0, // GR64_NOREX_and_GR64_TCW64:sub_ymm
3605 },
3606 { // GR64_ABCD
3607 6, // GR64_ABCD:sub_8bit -> GR8_ABCD_L
3608 5, // GR64_ABCD:sub_8bit_hi -> GR8_ABCD_H
3609 0, // GR64_ABCD:sub_8bit_hi_phony
3610 22, // GR64_ABCD:sub_16bit -> GR16_ABCD
3611 0, // GR64_ABCD:sub_16bit_hi
3612 49, // GR64_ABCD:sub_32bit -> GR32_ABCD
3613 0, // GR64_ABCD:sub_mask_0
3614 0, // GR64_ABCD:sub_mask_1
3615 0, // GR64_ABCD:sub_xmm
3616 0, // GR64_ABCD:sub_ymm
3617 },
3618 { // GR64_with_sub_32bit_in_GR32_TC
3619 3, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit -> GR8_NOREX2
3620 5, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
3621 0, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit_hi_phony
3622 10, // GR64_with_sub_32bit_in_GR32_TC:sub_16bit -> GR16_NOREX
3623 0, // GR64_with_sub_32bit_in_GR32_TC:sub_16bit_hi
3624 50, // GR64_with_sub_32bit_in_GR32_TC:sub_32bit -> GR32_TC
3625 0, // GR64_with_sub_32bit_in_GR32_TC:sub_mask_0
3626 0, // GR64_with_sub_32bit_in_GR32_TC:sub_mask_1
3627 0, // GR64_with_sub_32bit_in_GR32_TC:sub_xmm
3628 0, // GR64_with_sub_32bit_in_GR32_TC:sub_ymm
3629 },
3630 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
3631 6, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit -> GR8_ABCD_L
3632 5, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
3633 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit_hi_phony
3634 22, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_16bit -> GR16_ABCD
3635 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_16bit_hi
3636 51, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_32bit -> GR32_ABCD_and_GR32_TC
3637 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_mask_0
3638 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_mask_1
3639 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_xmm
3640 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_ymm
3641 },
3642 { // GR64_AD
3643 6, // GR64_AD:sub_8bit -> GR8_ABCD_L
3644 5, // GR64_AD:sub_8bit_hi -> GR8_ABCD_H
3645 0, // GR64_AD:sub_8bit_hi_phony
3646 22, // GR64_AD:sub_16bit -> GR16_ABCD
3647 0, // GR64_AD:sub_16bit_hi
3648 52, // GR64_AD:sub_32bit -> GR32_AD
3649 0, // GR64_AD:sub_mask_0
3650 0, // GR64_AD:sub_mask_1
3651 0, // GR64_AD:sub_xmm
3652 0, // GR64_AD:sub_ymm
3653 },
3654 { // GR64_ArgRef
3655 3, // GR64_ArgRef:sub_8bit -> GR8_NOREX2
3656 0, // GR64_ArgRef:sub_8bit_hi
3657 0, // GR64_ArgRef:sub_8bit_hi_phony
3658 9, // GR64_ArgRef:sub_16bit -> GR16_NOREX2
3659 0, // GR64_ArgRef:sub_16bit_hi
3660 42, // GR64_ArgRef:sub_32bit -> GR32_NOREX2_NOSP
3661 0, // GR64_ArgRef:sub_mask_0
3662 0, // GR64_ArgRef:sub_mask_1
3663 0, // GR64_ArgRef:sub_xmm
3664 0, // GR64_ArgRef:sub_ymm
3665 },
3666 { // GR64_and_LOW32_ADDR_ACCESS_RBP
3667 3, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit -> GR8_NOREX2
3668 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit_hi
3669 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit_hi_phony
3670 10, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_16bit -> GR16_NOREX
3671 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_16bit_hi
3672 66, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
3673 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_mask_0
3674 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_mask_1
3675 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_xmm
3676 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_ymm
3677 },
3678 { // GR64_with_sub_32bit_in_GR32_ArgRef
3679 6, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_8bit -> GR8_ABCD_L
3680 5, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
3681 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_8bit_hi_phony
3682 22, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_16bit -> GR16_ABCD
3683 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_16bit_hi
3684 53, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_32bit -> GR32_ArgRef
3685 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_mask_0
3686 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_mask_1
3687 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_xmm
3688 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_ymm
3689 },
3690 { // GR64_with_sub_32bit_in_GR32_BPSP
3691 3, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit -> GR8_NOREX2
3692 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit_hi
3693 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit_hi_phony
3694 10, // GR64_with_sub_32bit_in_GR32_BPSP:sub_16bit -> GR16_NOREX
3695 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_16bit_hi
3696 54, // GR64_with_sub_32bit_in_GR32_BPSP:sub_32bit -> GR32_BPSP
3697 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_mask_0
3698 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_mask_1
3699 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_xmm
3700 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_ymm
3701 },
3702 { // GR64_with_sub_32bit_in_GR32_BSI
3703 3, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit -> GR8_NOREX2
3704 5, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
3705 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit_hi_phony
3706 10, // GR64_with_sub_32bit_in_GR32_BSI:sub_16bit -> GR16_NOREX
3707 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_16bit_hi
3708 55, // GR64_with_sub_32bit_in_GR32_BSI:sub_32bit -> GR32_BSI
3709 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_mask_0
3710 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_mask_1
3711 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_xmm
3712 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_ymm
3713 },
3714 { // GR64_with_sub_32bit_in_GR32_CB
3715 6, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit -> GR8_ABCD_L
3716 5, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
3717 0, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit_hi_phony
3718 22, // GR64_with_sub_32bit_in_GR32_CB:sub_16bit -> GR16_ABCD
3719 0, // GR64_with_sub_32bit_in_GR32_CB:sub_16bit_hi
3720 56, // GR64_with_sub_32bit_in_GR32_CB:sub_32bit -> GR32_CB
3721 0, // GR64_with_sub_32bit_in_GR32_CB:sub_mask_0
3722 0, // GR64_with_sub_32bit_in_GR32_CB:sub_mask_1
3723 0, // GR64_with_sub_32bit_in_GR32_CB:sub_xmm
3724 0, // GR64_with_sub_32bit_in_GR32_CB:sub_ymm
3725 },
3726 { // GR64_with_sub_32bit_in_GR32_DIBP
3727 3, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit -> GR8_NOREX2
3728 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit_hi
3729 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit_hi_phony
3730 10, // GR64_with_sub_32bit_in_GR32_DIBP:sub_16bit -> GR16_NOREX
3731 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_16bit_hi
3732 58, // GR64_with_sub_32bit_in_GR32_DIBP:sub_32bit -> GR32_DIBP
3733 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_mask_0
3734 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_mask_1
3735 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_xmm
3736 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_ymm
3737 },
3738 { // GR64_with_sub_32bit_in_GR32_SIDI
3739 3, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit -> GR8_NOREX2
3740 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit_hi
3741 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit_hi_phony
3742 10, // GR64_with_sub_32bit_in_GR32_SIDI:sub_16bit -> GR16_NOREX
3743 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_16bit_hi
3744 59, // GR64_with_sub_32bit_in_GR32_SIDI:sub_32bit -> GR32_SIDI
3745 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_mask_0
3746 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_mask_1
3747 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_xmm
3748 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_ymm
3749 },
3750 { // GR64_A
3751 6, // GR64_A:sub_8bit -> GR8_ABCD_L
3752 5, // GR64_A:sub_8bit_hi -> GR8_ABCD_H
3753 0, // GR64_A:sub_8bit_hi_phony
3754 22, // GR64_A:sub_16bit -> GR16_ABCD
3755 0, // GR64_A:sub_16bit_hi
3756 52, // GR64_A:sub_32bit -> GR32_AD
3757 0, // GR64_A:sub_mask_0
3758 0, // GR64_A:sub_mask_1
3759 0, // GR64_A:sub_xmm
3760 0, // GR64_A:sub_ymm
3761 },
3762 { // GR64_ArgRef_and_GR64_TC
3763 3, // GR64_ArgRef_and_GR64_TC:sub_8bit -> GR8_NOREX2
3764 0, // GR64_ArgRef_and_GR64_TC:sub_8bit_hi
3765 0, // GR64_ArgRef_and_GR64_TC:sub_8bit_hi_phony
3766 9, // GR64_ArgRef_and_GR64_TC:sub_16bit -> GR16_NOREX2
3767 0, // GR64_ArgRef_and_GR64_TC:sub_16bit_hi
3768 42, // GR64_ArgRef_and_GR64_TC:sub_32bit -> GR32_NOREX2_NOSP
3769 0, // GR64_ArgRef_and_GR64_TC:sub_mask_0
3770 0, // GR64_ArgRef_and_GR64_TC:sub_mask_1
3771 0, // GR64_ArgRef_and_GR64_TC:sub_xmm
3772 0, // GR64_ArgRef_and_GR64_TC:sub_ymm
3773 },
3774 { // GR64_and_LOW32_ADDR_ACCESS
3775 0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit
3776 0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit_hi
3777 0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit_hi_phony
3778 0, // GR64_and_LOW32_ADDR_ACCESS:sub_16bit
3779 0, // GR64_and_LOW32_ADDR_ACCESS:sub_16bit_hi
3780 0, // GR64_and_LOW32_ADDR_ACCESS:sub_32bit
3781 0, // GR64_and_LOW32_ADDR_ACCESS:sub_mask_0
3782 0, // GR64_and_LOW32_ADDR_ACCESS:sub_mask_1
3783 0, // GR64_and_LOW32_ADDR_ACCESS:sub_xmm
3784 0, // GR64_and_LOW32_ADDR_ACCESS:sub_ymm
3785 },
3786 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
3787 6, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit -> GR8_ABCD_L
3788 5, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
3789 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit_hi_phony
3790 22, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_16bit -> GR16_ABCD
3791 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_16bit_hi
3792 63, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_32bit -> GR32_ABCD_and_GR32_BSI
3793 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_mask_0
3794 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_mask_1
3795 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_xmm
3796 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_ymm
3797 },
3798 { // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
3799 6, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_8bit -> GR8_ABCD_L
3800 5, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
3801 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_8bit_hi_phony
3802 22, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_16bit -> GR16_ABCD
3803 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_16bit_hi
3804 64, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_32bit -> GR32_AD_and_GR32_ArgRef
3805 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_mask_0
3806 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_mask_1
3807 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_xmm
3808 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_ymm
3809 },
3810 { // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
3811 6, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_8bit -> GR8_ABCD_L
3812 5, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
3813 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_8bit_hi_phony
3814 22, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_16bit -> GR16_ABCD
3815 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_16bit_hi
3816 65, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_32bit -> GR32_ArgRef_and_GR32_CB
3817 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_mask_0
3818 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_mask_1
3819 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_xmm
3820 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_ymm
3821 },
3822 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
3823 3, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit -> GR8_NOREX2
3824 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit_hi
3825 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit_hi_phony
3826 10, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_16bit -> GR16_NOREX
3827 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_16bit_hi
3828 66, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
3829 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_mask_0
3830 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_mask_1
3831 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_xmm
3832 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_ymm
3833 },
3834 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
3835 3, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit -> GR8_NOREX2
3836 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit_hi
3837 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit_hi_phony
3838 10, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_16bit -> GR16_NOREX
3839 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_16bit_hi
3840 67, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_32bit -> GR32_BPSP_and_GR32_TC
3841 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_mask_0
3842 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_mask_1
3843 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_xmm
3844 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_ymm
3845 },
3846 { // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
3847 3, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
3848 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit_hi
3849 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit_hi_phony
3850 10, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_16bit -> GR16_NOREX
3851 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_16bit_hi
3852 68, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_32bit -> GR32_BSI_and_GR32_SIDI
3853 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_mask_0
3854 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_mask_1
3855 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_xmm
3856 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_ymm
3857 },
3858 { // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
3859 3, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
3860 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit_hi
3861 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit_hi_phony
3862 10, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_16bit -> GR16_NOREX
3863 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_16bit_hi
3864 69, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_32bit -> GR32_DIBP_and_GR32_SIDI
3865 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_mask_0
3866 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_mask_1
3867 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_xmm
3868 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_ymm
3869 },
3870 { // RST
3871 0, // RST:sub_8bit
3872 0, // RST:sub_8bit_hi
3873 0, // RST:sub_8bit_hi_phony
3874 0, // RST:sub_16bit
3875 0, // RST:sub_16bit_hi
3876 0, // RST:sub_32bit
3877 0, // RST:sub_mask_0
3878 0, // RST:sub_mask_1
3879 0, // RST:sub_xmm
3880 0, // RST:sub_ymm
3881 },
3882 { // RFP80
3883 0, // RFP80:sub_8bit
3884 0, // RFP80:sub_8bit_hi
3885 0, // RFP80:sub_8bit_hi_phony
3886 0, // RFP80:sub_16bit
3887 0, // RFP80:sub_16bit_hi
3888 0, // RFP80:sub_32bit
3889 0, // RFP80:sub_mask_0
3890 0, // RFP80:sub_mask_1
3891 0, // RFP80:sub_xmm
3892 0, // RFP80:sub_ymm
3893 },
3894 { // RFP80_7
3895 0, // RFP80_7:sub_8bit
3896 0, // RFP80_7:sub_8bit_hi
3897 0, // RFP80_7:sub_8bit_hi_phony
3898 0, // RFP80_7:sub_16bit
3899 0, // RFP80_7:sub_16bit_hi
3900 0, // RFP80_7:sub_32bit
3901 0, // RFP80_7:sub_mask_0
3902 0, // RFP80_7:sub_mask_1
3903 0, // RFP80_7:sub_xmm
3904 0, // RFP80_7:sub_ymm
3905 },
3906 { // VR128X
3907 0, // VR128X:sub_8bit
3908 0, // VR128X:sub_8bit_hi
3909 0, // VR128X:sub_8bit_hi_phony
3910 0, // VR128X:sub_16bit
3911 0, // VR128X:sub_16bit_hi
3912 0, // VR128X:sub_32bit
3913 0, // VR128X:sub_mask_0
3914 0, // VR128X:sub_mask_1
3915 0, // VR128X:sub_xmm
3916 0, // VR128X:sub_ymm
3917 },
3918 { // VR128
3919 0, // VR128:sub_8bit
3920 0, // VR128:sub_8bit_hi
3921 0, // VR128:sub_8bit_hi_phony
3922 0, // VR128:sub_16bit
3923 0, // VR128:sub_16bit_hi
3924 0, // VR128:sub_32bit
3925 0, // VR128:sub_mask_0
3926 0, // VR128:sub_mask_1
3927 0, // VR128:sub_xmm
3928 0, // VR128:sub_ymm
3929 },
3930 { // VR256X
3931 0, // VR256X:sub_8bit
3932 0, // VR256X:sub_8bit_hi
3933 0, // VR256X:sub_8bit_hi_phony
3934 0, // VR256X:sub_16bit
3935 0, // VR256X:sub_16bit_hi
3936 0, // VR256X:sub_32bit
3937 0, // VR256X:sub_mask_0
3938 0, // VR256X:sub_mask_1
3939 24, // VR256X:sub_xmm -> FR16X
3940 0, // VR256X:sub_ymm
3941 },
3942 { // VR256
3943 0, // VR256:sub_8bit
3944 0, // VR256:sub_8bit_hi
3945 0, // VR256:sub_8bit_hi_phony
3946 0, // VR256:sub_16bit
3947 0, // VR256:sub_16bit_hi
3948 0, // VR256:sub_32bit
3949 0, // VR256:sub_mask_0
3950 0, // VR256:sub_mask_1
3951 25, // VR256:sub_xmm -> FR16
3952 0, // VR256:sub_ymm
3953 },
3954 { // VR512
3955 0, // VR512:sub_8bit
3956 0, // VR512:sub_8bit_hi
3957 0, // VR512:sub_8bit_hi_phony
3958 0, // VR512:sub_16bit
3959 0, // VR512:sub_16bit_hi
3960 0, // VR512:sub_32bit
3961 0, // VR512:sub_mask_0
3962 0, // VR512:sub_mask_1
3963 24, // VR512:sub_xmm -> FR16X
3964 131, // VR512:sub_ymm -> VR256X
3965 },
3966 { // VR512_0_15
3967 0, // VR512_0_15:sub_8bit
3968 0, // VR512_0_15:sub_8bit_hi
3969 0, // VR512_0_15:sub_8bit_hi_phony
3970 0, // VR512_0_15:sub_16bit
3971 0, // VR512_0_15:sub_16bit_hi
3972 0, // VR512_0_15:sub_32bit
3973 0, // VR512_0_15:sub_mask_0
3974 0, // VR512_0_15:sub_mask_1
3975 25, // VR512_0_15:sub_xmm -> FR16
3976 132, // VR512_0_15:sub_ymm -> VR256
3977 },
3978 { // TILE
3979 0, // TILE:sub_8bit
3980 0, // TILE:sub_8bit_hi
3981 0, // TILE:sub_8bit_hi_phony
3982 0, // TILE:sub_16bit
3983 0, // TILE:sub_16bit_hi
3984 0, // TILE:sub_32bit
3985 0, // TILE:sub_mask_0
3986 0, // TILE:sub_mask_1
3987 0, // TILE:sub_xmm
3988 0, // TILE:sub_ymm
3989 },
3990
3991 };
3992 assert(RC && "Missing regclass");
3993 if (!Idx) return RC;
3994 --Idx;
3995 assert(Idx < 10 && "Bad subreg");
3996 unsigned TV = Table[RC->getID()][Idx];
3997 return TV ? getRegClass(i: TV - 1) : nullptr;
3998}/// Get the weight in units of pressure for this register class.
3999const RegClassWeight &X86GenRegisterInfo::
4000getRegClassWeight(const TargetRegisterClass *RC) const {
4001 static const RegClassWeight RCWeightTable[] = {
4002 {.RegWeight: 1, .WeightLimit: 36}, // GR8
4003 {.RegWeight: 0, .WeightLimit: 0}, // GRH8
4004 {.RegWeight: 1, .WeightLimit: 20}, // GR8_NOREX2
4005 {.RegWeight: 1, .WeightLimit: 8}, // GR8_NOREX
4006 {.RegWeight: 1, .WeightLimit: 4}, // GR8_ABCD_H
4007 {.RegWeight: 1, .WeightLimit: 4}, // GR8_ABCD_L
4008 {.RegWeight: 0, .WeightLimit: 0}, // GRH16
4009 {.RegWeight: 2, .WeightLimit: 64}, // GR16
4010 {.RegWeight: 2, .WeightLimit: 32}, // GR16_NOREX2
4011 {.RegWeight: 2, .WeightLimit: 16}, // GR16_NOREX
4012 {.RegWeight: 1, .WeightLimit: 8}, // VK1
4013 {.RegWeight: 1, .WeightLimit: 8}, // VK16
4014 {.RegWeight: 1, .WeightLimit: 8}, // VK2
4015 {.RegWeight: 1, .WeightLimit: 8}, // VK4
4016 {.RegWeight: 1, .WeightLimit: 8}, // VK8
4017 {.RegWeight: 1, .WeightLimit: 7}, // VK16WM
4018 {.RegWeight: 1, .WeightLimit: 7}, // VK1WM
4019 {.RegWeight: 1, .WeightLimit: 7}, // VK2WM
4020 {.RegWeight: 1, .WeightLimit: 7}, // VK4WM
4021 {.RegWeight: 1, .WeightLimit: 7}, // VK8WM
4022 {.RegWeight: 1, .WeightLimit: 6}, // SEGMENT_REG
4023 {.RegWeight: 2, .WeightLimit: 8}, // GR16_ABCD
4024 {.RegWeight: 0, .WeightLimit: 0}, // FPCCR
4025 {.RegWeight: 1, .WeightLimit: 32}, // FR16X
4026 {.RegWeight: 1, .WeightLimit: 16}, // FR16
4027 {.RegWeight: 2, .WeightLimit: 8}, // VK16PAIR
4028 {.RegWeight: 2, .WeightLimit: 8}, // VK1PAIR
4029 {.RegWeight: 2, .WeightLimit: 8}, // VK2PAIR
4030 {.RegWeight: 2, .WeightLimit: 8}, // VK4PAIR
4031 {.RegWeight: 2, .WeightLimit: 8}, // VK8PAIR
4032 {.RegWeight: 2, .WeightLimit: 6}, // VK1PAIR_with_sub_mask_0_in_VK1WM
4033 {.RegWeight: 2, .WeightLimit: 66}, // LOW32_ADDR_ACCESS_RBP
4034 {.RegWeight: 2, .WeightLimit: 66}, // LOW32_ADDR_ACCESS
4035 {.RegWeight: 2, .WeightLimit: 64}, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
4036 {.RegWeight: 1, .WeightLimit: 32}, // FR32X
4037 {.RegWeight: 2, .WeightLimit: 64}, // GR32
4038 {.RegWeight: 2, .WeightLimit: 62}, // GR32_NOSP
4039 {.RegWeight: 2, .WeightLimit: 32}, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
4040 {.RegWeight: 1, .WeightLimit: 16}, // DEBUG_REG
4041 {.RegWeight: 1, .WeightLimit: 16}, // FR32
4042 {.RegWeight: 2, .WeightLimit: 32}, // GR32_NOREX2
4043 {.RegWeight: 2, .WeightLimit: 30}, // GR32_NOREX2_NOSP
4044 {.RegWeight: 2, .WeightLimit: 16}, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
4045 {.RegWeight: 2, .WeightLimit: 16}, // GR32_NOREX
4046 {.RegWeight: 1, .WeightLimit: 8}, // VK32
4047 {.RegWeight: 2, .WeightLimit: 14}, // GR32_NOREX_NOSP
4048 {.RegWeight: 1, .WeightLimit: 7}, // RFP32
4049 {.RegWeight: 1, .WeightLimit: 7}, // VK32WM
4050 {.RegWeight: 2, .WeightLimit: 8}, // GR32_ABCD
4051 {.RegWeight: 2, .WeightLimit: 8}, // GR32_TC
4052 {.RegWeight: 2, .WeightLimit: 6}, // GR32_ABCD_and_GR32_TC
4053 {.RegWeight: 2, .WeightLimit: 4}, // GR32_AD
4054 {.RegWeight: 2, .WeightLimit: 4}, // GR32_ArgRef
4055 {.RegWeight: 2, .WeightLimit: 4}, // GR32_BPSP
4056 {.RegWeight: 2, .WeightLimit: 4}, // GR32_BSI
4057 {.RegWeight: 2, .WeightLimit: 4}, // GR32_CB
4058 {.RegWeight: 2, .WeightLimit: 4}, // GR32_DC
4059 {.RegWeight: 2, .WeightLimit: 4}, // GR32_DIBP
4060 {.RegWeight: 2, .WeightLimit: 4}, // GR32_SIDI
4061 {.RegWeight: 2, .WeightLimit: 4}, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
4062 {.RegWeight: 0, .WeightLimit: 0}, // CCR
4063 {.RegWeight: 0, .WeightLimit: 0}, // DFCCR
4064 {.RegWeight: 2, .WeightLimit: 2}, // GR32_ABCD_and_GR32_BSI
4065 {.RegWeight: 2, .WeightLimit: 2}, // GR32_AD_and_GR32_ArgRef
4066 {.RegWeight: 2, .WeightLimit: 2}, // GR32_ArgRef_and_GR32_CB
4067 {.RegWeight: 2, .WeightLimit: 2}, // GR32_BPSP_and_GR32_DIBP
4068 {.RegWeight: 2, .WeightLimit: 2}, // GR32_BPSP_and_GR32_TC
4069 {.RegWeight: 2, .WeightLimit: 2}, // GR32_BSI_and_GR32_SIDI
4070 {.RegWeight: 2, .WeightLimit: 2}, // GR32_DIBP_and_GR32_SIDI
4071 {.RegWeight: 2, .WeightLimit: 2}, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
4072 {.RegWeight: 2, .WeightLimit: 2}, // LOW32_ADDR_ACCESS_with_sub_32bit
4073 {.RegWeight: 1, .WeightLimit: 7}, // RFP64
4074 {.RegWeight: 2, .WeightLimit: 66}, // GR64
4075 {.RegWeight: 1, .WeightLimit: 32}, // FR64X
4076 {.RegWeight: 2, .WeightLimit: 64}, // GR64_with_sub_8bit
4077 {.RegWeight: 2, .WeightLimit: 62}, // GR64_NOSP
4078 {.RegWeight: 2, .WeightLimit: 34}, // GR64_NOREX2
4079 {.RegWeight: 1, .WeightLimit: 16}, // CONTROL_REG
4080 {.RegWeight: 1, .WeightLimit: 16}, // FR64
4081 {.RegWeight: 2, .WeightLimit: 32}, // GR64_with_sub_16bit_in_GR16_NOREX2
4082 {.RegWeight: 2, .WeightLimit: 30}, // GR64_NOREX2_NOSP
4083 {.RegWeight: 2, .WeightLimit: 26}, // GR64PLTSafe
4084 {.RegWeight: 2, .WeightLimit: 20}, // GR64_TC
4085 {.RegWeight: 2, .WeightLimit: 18}, // GR64_NOREX
4086 {.RegWeight: 2, .WeightLimit: 18}, // GR64_TCW64
4087 {.RegWeight: 2, .WeightLimit: 18}, // GR64_TC_with_sub_8bit
4088 {.RegWeight: 2, .WeightLimit: 16}, // GR64_NOREX2_NOSP_and_GR64_TC
4089 {.RegWeight: 2, .WeightLimit: 16}, // GR64_TCW64_with_sub_8bit
4090 {.RegWeight: 2, .WeightLimit: 16}, // GR64_TC_and_GR64_TCW64
4091 {.RegWeight: 2, .WeightLimit: 16}, // GR64_with_sub_16bit_in_GR16_NOREX
4092 {.RegWeight: 1, .WeightLimit: 8}, // VK64
4093 {.RegWeight: 1, .WeightLimit: 8}, // VR64
4094 {.RegWeight: 2, .WeightLimit: 14}, // GR64PLTSafe_and_GR64_TC
4095 {.RegWeight: 2, .WeightLimit: 14}, // GR64_NOREX2_NOSP_and_GR64_TCW64
4096 {.RegWeight: 2, .WeightLimit: 14}, // GR64_NOREX_NOSP
4097 {.RegWeight: 2, .WeightLimit: 14}, // GR64_NOREX_and_GR64_TC
4098 {.RegWeight: 2, .WeightLimit: 14}, // GR64_TCW64_and_GR64_TC_with_sub_8bit
4099 {.RegWeight: 1, .WeightLimit: 7}, // VK64WM
4100 {.RegWeight: 2, .WeightLimit: 12}, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
4101 {.RegWeight: 2, .WeightLimit: 12}, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
4102 {.RegWeight: 2, .WeightLimit: 10}, // GR64PLTSafe_and_GR64_TCW64
4103 {.RegWeight: 2, .WeightLimit: 10}, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
4104 {.RegWeight: 2, .WeightLimit: 10}, // GR64_NOREX_and_GR64_TCW64
4105 {.RegWeight: 2, .WeightLimit: 8}, // GR64_ABCD
4106 {.RegWeight: 2, .WeightLimit: 8}, // GR64_with_sub_32bit_in_GR32_TC
4107 {.RegWeight: 2, .WeightLimit: 6}, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
4108 {.RegWeight: 2, .WeightLimit: 4}, // GR64_AD
4109 {.RegWeight: 2, .WeightLimit: 4}, // GR64_ArgRef
4110 {.RegWeight: 2, .WeightLimit: 4}, // GR64_and_LOW32_ADDR_ACCESS_RBP
4111 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_ArgRef
4112 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_BPSP
4113 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_BSI
4114 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_CB
4115 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_DIBP
4116 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_SIDI
4117 {.RegWeight: 2, .WeightLimit: 2}, // GR64_A
4118 {.RegWeight: 2, .WeightLimit: 2}, // GR64_ArgRef_and_GR64_TC
4119 {.RegWeight: 2, .WeightLimit: 2}, // GR64_and_LOW32_ADDR_ACCESS
4120 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
4121 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
4122 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
4123 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
4124 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
4125 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
4126 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
4127 {.RegWeight: 0, .WeightLimit: 0}, // RST
4128 {.RegWeight: 1, .WeightLimit: 7}, // RFP80
4129 {.RegWeight: 0, .WeightLimit: 0}, // RFP80_7
4130 {.RegWeight: 1, .WeightLimit: 32}, // VR128X
4131 {.RegWeight: 1, .WeightLimit: 16}, // VR128
4132 {.RegWeight: 1, .WeightLimit: 32}, // VR256X
4133 {.RegWeight: 1, .WeightLimit: 16}, // VR256
4134 {.RegWeight: 1, .WeightLimit: 32}, // VR512
4135 {.RegWeight: 1, .WeightLimit: 16}, // VR512_0_15
4136 {.RegWeight: 1, .WeightLimit: 8}, // TILE
4137 };
4138 return RCWeightTable[RC->getID()];
4139}
4140
4141/// Get the weight in units of pressure for this register unit.
4142unsigned X86GenRegisterInfo::
4143getRegUnitWeight(MCRegUnit RegUnit) const {
4144 assert(static_cast<unsigned>(RegUnit) < 221 && "invalid register unit");
4145 // All register units have unit weight.
4146 return 1;
4147}
4148
4149
4150// Get the number of dimensions of register pressure.
4151unsigned X86GenRegisterInfo::getNumRegPressureSets() const {
4152 return 36;
4153}
4154
4155// Get the name of this register unit pressure set.
4156const char *X86GenRegisterInfo::
4157getRegPressureSetName(unsigned Idx) const {
4158 static const char *PressureNameTable[] = {
4159 "SEGMENT_REG",
4160 "GR32_BPSP",
4161 "LOW32_ADDR_ACCESS_with_sub_32bit",
4162 "GR32_BSI",
4163 "GR32_SIDI",
4164 "GR32_DIBP_with_GR32_SIDI",
4165 "GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit",
4166 "RFP32",
4167 "GR8_ABCD_H_with_GR32_BSI",
4168 "GR8_ABCD_L_with_GR32_BSI",
4169 "VK1",
4170 "VR64",
4171 "TILE",
4172 "GR8_NOREX",
4173 "GR32_TC",
4174 "GR32_BPSP_with_GR32_TC",
4175 "FR16",
4176 "DEBUG_REG",
4177 "CONTROL_REG",
4178 "GR64_NOREX",
4179 "GR64_TCW64",
4180 "GR32_BPSP_with_GR64_TCW64",
4181 "GR64_TC_with_GR64_TCW64",
4182 "GR64_TC",
4183 "FR16X",
4184 "GR64PLTSafe_with_GR64_TC",
4185 "GR8",
4186 "GR8_with_GR32_DIBP",
4187 "GR8_with_GR32_BSI",
4188 "GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit",
4189 "GR8_with_GR64_NOREX",
4190 "GR8_with_GR64_TCW64",
4191 "GR8_with_GR64_TC",
4192 "GR8_with_GR64PLTSafe",
4193 "GR8_with_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2",
4194 "GR16",
4195 };
4196 return PressureNameTable[Idx];
4197}
4198
4199// Get the register unit pressure limit for this dimension.
4200// This limit must be adjusted dynamically for reserved registers.
4201unsigned X86GenRegisterInfo::
4202getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
4203 static const uint8_t PressureLimitTable[] = {
4204 6, // 0: SEGMENT_REG
4205 6, // 1: GR32_BPSP
4206 6, // 2: LOW32_ADDR_ACCESS_with_sub_32bit
4207 6, // 3: GR32_BSI
4208 6, // 4: GR32_SIDI
4209 6, // 5: GR32_DIBP_with_GR32_SIDI
4210 6, // 6: GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit
4211 7, // 7: RFP32
4212 7, // 8: GR8_ABCD_H_with_GR32_BSI
4213 7, // 9: GR8_ABCD_L_with_GR32_BSI
4214 8, // 10: VK1
4215 8, // 11: VR64
4216 8, // 12: TILE
4217 10, // 13: GR8_NOREX
4218 12, // 14: GR32_TC
4219 12, // 15: GR32_BPSP_with_GR32_TC
4220 16, // 16: FR16
4221 16, // 17: DEBUG_REG
4222 16, // 18: CONTROL_REG
4223 18, // 19: GR64_NOREX
4224 20, // 20: GR64_TCW64
4225 20, // 21: GR32_BPSP_with_GR64_TCW64
4226 22, // 22: GR64_TC_with_GR64_TCW64
4227 26, // 23: GR64_TC
4228 32, // 24: FR16X
4229 34, // 25: GR64PLTSafe_with_GR64_TC
4230 38, // 26: GR8
4231 38, // 27: GR8_with_GR32_DIBP
4232 38, // 28: GR8_with_GR32_BSI
4233 39, // 29: GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit
4234 42, // 30: GR8_with_GR64_NOREX
4235 43, // 31: GR8_with_GR64_TCW64
4236 44, // 32: GR8_with_GR64_TC
4237 45, // 33: GR8_with_GR64PLTSafe
4238 48, // 34: GR8_with_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
4239 66, // 35: GR16
4240 };
4241 return PressureLimitTable[Idx];
4242}
4243
4244/// Table of pressure sets per register class or unit.
4245static const int RCSetsTable[] = {
4246 /* 0 */ 0, -1,
4247 /* 2 */ 7, -1,
4248 /* 4 */ 10, -1,
4249 /* 6 */ 11, -1,
4250 /* 8 */ 12, -1,
4251 /* 10 */ 17, -1,
4252 /* 12 */ 18, -1,
4253 /* 14 */ 16, 24, -1,
4254 /* 17 */ 25, 35, -1,
4255 /* 20 */ 19, 23, 25, 30, 35, -1,
4256 /* 26 */ 2, 6, 15, 19, 21, 23, 25, 29, 30, 35, -1,
4257 /* 37 */ 20, 21, 22, 23, 25, 31, 35, -1,
4258 /* 45 */ 22, 23, 25, 32, 35, -1,
4259 /* 51 */ 19, 22, 23, 25, 30, 32, 35, -1,
4260 /* 59 */ 20, 21, 22, 23, 25, 31, 32, 35, -1,
4261 /* 68 */ 14, 15, 19, 20, 21, 22, 23, 25, 30, 31, 32, 35, -1,
4262 /* 81 */ 2, 6, 14, 15, 19, 20, 21, 22, 23, 25, 29, 30, 31, 32, 35, -1,
4263 /* 97 */ 25, 34, 35, -1,
4264 /* 101 */ 19, 23, 25, 30, 34, 35, -1,
4265 /* 108 */ 1, 2, 15, 19, 21, 23, 25, 26, 30, 34, 35, -1,
4266 /* 120 */ 20, 21, 22, 23, 25, 31, 34, 35, -1,
4267 /* 129 */ 22, 23, 25, 32, 34, 35, -1,
4268 /* 136 */ 19, 22, 23, 25, 30, 32, 34, 35, -1,
4269 /* 145 */ 20, 21, 22, 23, 25, 31, 32, 34, 35, -1,
4270 /* 155 */ 1, 2, 14, 15, 19, 20, 21, 22, 23, 25, 26, 30, 31, 32, 34, 35, -1,
4271 /* 172 */ 25, 33, 34, 35, -1,
4272 /* 177 */ 19, 23, 25, 30, 33, 34, 35, -1,
4273 /* 185 */ 1, 5, 6, 19, 23, 25, 27, 30, 33, 34, 35, -1,
4274 /* 197 */ 1, 2, 5, 6, 15, 19, 21, 23, 25, 26, 27, 29, 30, 33, 34, 35, -1,
4275 /* 214 */ 22, 23, 25, 32, 33, 34, 35, -1,
4276 /* 222 */ 3, 4, 8, 9, 13, 19, 23, 25, 28, 30, 32, 33, 34, 35, -1,
4277 /* 237 */ 4, 5, 19, 22, 23, 25, 28, 30, 32, 33, 34, 35, -1,
4278 /* 250 */ 3, 4, 5, 8, 9, 13, 19, 22, 23, 25, 28, 30, 32, 33, 34, 35, -1,
4279 /* 267 */ 1, 4, 5, 6, 19, 22, 23, 25, 27, 28, 30, 32, 33, 34, 35, -1,
4280 /* 283 */ 20, 21, 22, 23, 25, 31, 32, 33, 34, 35, -1,
4281 /* 294 */ 3, 13, 14, 19, 20, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
4282 /* 312 */ 8, 13, 14, 19, 20, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
4283 /* 330 */ 3, 4, 8, 9, 13, 14, 19, 20, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
4284 /* 351 */ 1, 2, 5, 6, 15, 19, 21, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
4285 /* 371 */ 1, 4, 5, 6, 19, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
4286 /* 390 */ 3, 4, 5, 8, 9, 13, 19, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
4287 /* 411 */ 1, 2, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
4288 /* 432 */ 3, 13, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
4289 /* 453 */ 3, 8, 13, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
4290 /* 475 */ 3, 9, 13, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
4291};
4292
4293/// Get the dimensions of register pressure impacted by this register class.
4294/// Returns a -1 terminated array of pressure set IDs
4295const int *X86GenRegisterInfo::
4296getRegClassPressureSets(const TargetRegisterClass *RC) const {
4297 static const uint16_t RCSetStartTable[] = {
4298 301,1,300,295,312,333,1,18,97,101,4,4,4,4,4,4,4,4,4,4,0,295,1,15,14,4,4,4,4,4,4,18,18,18,15,18,18,97,10,14,97,97,101,101,4,177,2,4,295,157,433,433,433,108,222,294,433,185,237,26,1,1,330,433,432,197,155,250,267,197,81,2,18,15,18,18,17,12,14,97,97,172,45,20,37,129,129,120,59,101,4,6,214,120,177,51,145,4,145,136,283,239,68,295,157,433,433,120,26,433,108,222,294,185,237,433,145,81,330,433,432,197,155,250,267,1,2,1,15,14,15,14,15,14,8,};
4299 return &RCSetsTable[RCSetStartTable[RC->getID()]];
4300}
4301
4302/// Get the dimensions of register pressure impacted by this register unit.
4303/// Returns a -1 terminated array of pressure set IDs
4304const int *X86GenRegisterInfo::
4305getRegUnitPressureSets(MCRegUnit RegUnit) const {
4306 assert(static_cast<unsigned>(RegUnit) < 221 && "invalid register unit");
4307 static const uint16_t RUSetStartTable[] = {
4308 454,476,330,330,351,1,453,475,0,1,454,371,1,476,0,1,1,1,1,1,1,1,81,1,1,0,390,1,1,411,1,1,1,1,0,1,0,1,1,1,1,0,1,1,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,2,2,2,2,2,2,2,1,6,6,6,6,6,6,6,6,416,1,1,416,1,1,416,1,1,416,1,1,300,1,1,300,1,1,300,1,1,300,1,1,1,1,1,1,1,1,1,1,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,4,4,4,4,4,4,4,4,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,1,8,8,8,8,8,8,8,8,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,};
4309 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
4310}
4311
4312ArrayRef<MCPhysReg> X86GenRegisterInfo::getRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) const {
4313 switch (RC.getID()) {
4314 case X86::GR8RegClassID:
4315 return GR8GetRawAllocationOrder(RC, MF, Rev);
4316 case X86::GR8_NOREX2RegClassID:
4317 return GR8_NOREX2GetRawAllocationOrder(RC, MF, Rev);
4318 case X86::GR8_NOREXRegClassID:
4319 return GR8_NOREXGetRawAllocationOrder(RC, MF, Rev);
4320 case X86::FR32XRegClassID:
4321 return FR32XGetRawAllocationOrder(RC, MF, Rev);
4322 case X86::FR64XRegClassID:
4323 return FR64XGetRawAllocationOrder(RC, MF, Rev);
4324 case X86::VR128XRegClassID:
4325 return VR128XGetRawAllocationOrder(RC, MF, Rev);
4326 case X86::VR256XRegClassID:
4327 return VR256XGetRawAllocationOrder(RC, MF, Rev);
4328 }
4329 return RC.getRegisters();
4330}
4331
4332
4333// Register to minimal register class mapping
4334
4335const TargetRegisterClass *X86GenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
4336 static const uint16_t InvalidRegClassID = UINT16_MAX;
4337
4338 static const uint16_t Mapping[388] = {
4339 InvalidRegClassID, // NoRegister
4340 X86::GR8_ABCD_HRegClassID, // AH
4341 X86::GR8_ABCD_LRegClassID, // AL
4342 X86::GR16_ABCDRegClassID, // AX
4343 X86::GR8_ABCD_HRegClassID, // BH
4344 X86::GR8_ABCD_LRegClassID, // BL
4345 X86::GR16_NOREXRegClassID, // BP
4346 X86::GRH8RegClassID, // BPH
4347 X86::GR8_NOREX2RegClassID, // BPL
4348 X86::GR16_ABCDRegClassID, // BX
4349 X86::GR8_ABCD_HRegClassID, // CH
4350 X86::GR8_ABCD_LRegClassID, // CL
4351 X86::SEGMENT_REGRegClassID, // CS
4352 X86::GR16_ABCDRegClassID, // CX
4353 X86::DFCCRRegClassID, // DF
4354 X86::GR8_ABCD_HRegClassID, // DH
4355 X86::GR16_NOREXRegClassID, // DI
4356 X86::GRH8RegClassID, // DIH
4357 X86::GR8_NOREX2RegClassID, // DIL
4358 X86::GR8_ABCD_LRegClassID, // DL
4359 X86::SEGMENT_REGRegClassID, // DS
4360 X86::GR16_ABCDRegClassID, // DX
4361 X86::GR32_ADRegClassID, // EAX
4362 X86::GR32_BPSP_and_GR32_DIBPRegClassID, // EBP
4363 X86::GR32_ABCD_and_GR32_BSIRegClassID, // EBX
4364 X86::GR32_ArgRef_and_GR32_CBRegClassID, // ECX
4365 X86::GR32_DIBP_and_GR32_SIDIRegClassID, // EDI
4366 X86::GR32_AD_and_GR32_ArgRefRegClassID, // EDX
4367 X86::CCRRegClassID, // EFLAGS
4368 InvalidRegClassID, // EIP
4369 InvalidRegClassID, // EIZ
4370 X86::SEGMENT_REGRegClassID, // ES
4371 X86::GR32_BSI_and_GR32_SIDIRegClassID, // ESI
4372 X86::GR32_BPSP_and_GR32_TCRegClassID, // ESP
4373 InvalidRegClassID, // FPCW
4374 X86::FPCCRRegClassID, // FPSW
4375 X86::SEGMENT_REGRegClassID, // FS
4376 InvalidRegClassID, // FS_BASE
4377 X86::SEGMENT_REGRegClassID, // GS
4378 InvalidRegClassID, // GS_BASE
4379 X86::GRH16RegClassID, // HAX
4380 X86::GRH16RegClassID, // HBP
4381 X86::GRH16RegClassID, // HBX
4382 X86::GRH16RegClassID, // HCX
4383 X86::GRH16RegClassID, // HDI
4384 X86::GRH16RegClassID, // HDX
4385 X86::GRH16RegClassID, // HIP
4386 X86::GRH16RegClassID, // HSI
4387 X86::GRH16RegClassID, // HSP
4388 InvalidRegClassID, // IP
4389 InvalidRegClassID, // MXCSR
4390 X86::GR64_ARegClassID, // RAX
4391 X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID, // RBP
4392 X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID, // RBX
4393 X86::GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID, // RCX
4394 X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID, // RDI
4395 X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID, // RDX
4396 InvalidRegClassID, // RFLAGS
4397 X86::GR64_and_LOW32_ADDR_ACCESSRegClassID, // RIP
4398 InvalidRegClassID, // RIZ
4399 X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID, // RSI
4400 X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID, // RSP
4401 X86::GR16_NOREXRegClassID, // SI
4402 X86::GRH8RegClassID, // SIH
4403 X86::GR8_NOREX2RegClassID, // SIL
4404 X86::GR16_NOREXRegClassID, // SP
4405 X86::GRH8RegClassID, // SPH
4406 X86::GR8_NOREX2RegClassID, // SPL
4407 X86::SEGMENT_REGRegClassID, // SS
4408 InvalidRegClassID, // SSP
4409 InvalidRegClassID, // _EFLAGS
4410 X86::CONTROL_REGRegClassID, // CR0
4411 X86::CONTROL_REGRegClassID, // CR1
4412 X86::CONTROL_REGRegClassID, // CR2
4413 X86::CONTROL_REGRegClassID, // CR3
4414 X86::CONTROL_REGRegClassID, // CR4
4415 X86::CONTROL_REGRegClassID, // CR5
4416 X86::CONTROL_REGRegClassID, // CR6
4417 X86::CONTROL_REGRegClassID, // CR7
4418 X86::CONTROL_REGRegClassID, // CR8
4419 X86::CONTROL_REGRegClassID, // CR9
4420 X86::CONTROL_REGRegClassID, // CR10
4421 X86::CONTROL_REGRegClassID, // CR11
4422 X86::CONTROL_REGRegClassID, // CR12
4423 X86::CONTROL_REGRegClassID, // CR13
4424 X86::CONTROL_REGRegClassID, // CR14
4425 X86::CONTROL_REGRegClassID, // CR15
4426 X86::DEBUG_REGRegClassID, // DR0
4427 X86::DEBUG_REGRegClassID, // DR1
4428 X86::DEBUG_REGRegClassID, // DR2
4429 X86::DEBUG_REGRegClassID, // DR3
4430 X86::DEBUG_REGRegClassID, // DR4
4431 X86::DEBUG_REGRegClassID, // DR5
4432 X86::DEBUG_REGRegClassID, // DR6
4433 X86::DEBUG_REGRegClassID, // DR7
4434 X86::DEBUG_REGRegClassID, // DR8
4435 X86::DEBUG_REGRegClassID, // DR9
4436 X86::DEBUG_REGRegClassID, // DR10
4437 X86::DEBUG_REGRegClassID, // DR11
4438 X86::DEBUG_REGRegClassID, // DR12
4439 X86::DEBUG_REGRegClassID, // DR13
4440 X86::DEBUG_REGRegClassID, // DR14
4441 X86::DEBUG_REGRegClassID, // DR15
4442 X86::RFP80RegClassID, // FP0
4443 X86::RFP80RegClassID, // FP1
4444 X86::RFP80RegClassID, // FP2
4445 X86::RFP80RegClassID, // FP3
4446 X86::RFP80RegClassID, // FP4
4447 X86::RFP80RegClassID, // FP5
4448 X86::RFP80RegClassID, // FP6
4449 X86::RFP80_7RegClassID, // FP7
4450 X86::VR64RegClassID, // MM0
4451 X86::VR64RegClassID, // MM1
4452 X86::VR64RegClassID, // MM2
4453 X86::VR64RegClassID, // MM3
4454 X86::VR64RegClassID, // MM4
4455 X86::VR64RegClassID, // MM5
4456 X86::VR64RegClassID, // MM6
4457 X86::VR64RegClassID, // MM7
4458 X86::GR64PLTSafe_and_GR64_TCW64RegClassID, // R8
4459 X86::GR64PLTSafe_and_GR64_TCW64RegClassID, // R9
4460 X86::GR64_ArgRefRegClassID, // R10
4461 X86::GR64_ArgRef_and_GR64_TCRegClassID, // R11
4462 X86::GR64PLTSafeRegClassID, // R12
4463 X86::GR64PLTSafeRegClassID, // R13
4464 X86::GR64PLTSafeRegClassID, // R14
4465 X86::GR64PLTSafeRegClassID, // R15
4466 X86::RSTRegClassID, // ST0
4467 X86::RSTRegClassID, // ST1
4468 X86::RSTRegClassID, // ST2
4469 X86::RSTRegClassID, // ST3
4470 X86::RSTRegClassID, // ST4
4471 X86::RSTRegClassID, // ST5
4472 X86::RSTRegClassID, // ST6
4473 X86::RSTRegClassID, // ST7
4474 X86::VR128RegClassID, // XMM0
4475 X86::VR128RegClassID, // XMM1
4476 X86::VR128RegClassID, // XMM2
4477 X86::VR128RegClassID, // XMM3
4478 X86::VR128RegClassID, // XMM4
4479 X86::VR128RegClassID, // XMM5
4480 X86::VR128RegClassID, // XMM6
4481 X86::VR128RegClassID, // XMM7
4482 X86::VR128RegClassID, // XMM8
4483 X86::VR128RegClassID, // XMM9
4484 X86::VR128RegClassID, // XMM10
4485 X86::VR128RegClassID, // XMM11
4486 X86::VR128RegClassID, // XMM12
4487 X86::VR128RegClassID, // XMM13
4488 X86::VR128RegClassID, // XMM14
4489 X86::VR128RegClassID, // XMM15
4490 X86::GR8_NOREX2RegClassID, // R8B
4491 X86::GR8_NOREX2RegClassID, // R9B
4492 X86::GR8_NOREX2RegClassID, // R10B
4493 X86::GR8_NOREX2RegClassID, // R11B
4494 X86::GR8_NOREX2RegClassID, // R12B
4495 X86::GR8_NOREX2RegClassID, // R13B
4496 X86::GR8_NOREX2RegClassID, // R14B
4497 X86::GR8_NOREX2RegClassID, // R15B
4498 X86::GRH8RegClassID, // R8BH
4499 X86::GRH8RegClassID, // R9BH
4500 X86::GRH8RegClassID, // R10BH
4501 X86::GRH8RegClassID, // R11BH
4502 X86::GRH8RegClassID, // R12BH
4503 X86::GRH8RegClassID, // R13BH
4504 X86::GRH8RegClassID, // R14BH
4505 X86::GRH8RegClassID, // R15BH
4506 X86::GR32_NOREX2_NOSPRegClassID, // R8D
4507 X86::GR32_NOREX2_NOSPRegClassID, // R9D
4508 X86::GR32_NOREX2_NOSPRegClassID, // R10D
4509 X86::GR32_NOREX2_NOSPRegClassID, // R11D
4510 X86::GR32_NOREX2_NOSPRegClassID, // R12D
4511 X86::GR32_NOREX2_NOSPRegClassID, // R13D
4512 X86::GR32_NOREX2_NOSPRegClassID, // R14D
4513 X86::GR32_NOREX2_NOSPRegClassID, // R15D
4514 X86::GR16_NOREX2RegClassID, // R8W
4515 X86::GR16_NOREX2RegClassID, // R9W
4516 X86::GR16_NOREX2RegClassID, // R10W
4517 X86::GR16_NOREX2RegClassID, // R11W
4518 X86::GR16_NOREX2RegClassID, // R12W
4519 X86::GR16_NOREX2RegClassID, // R13W
4520 X86::GR16_NOREX2RegClassID, // R14W
4521 X86::GR16_NOREX2RegClassID, // R15W
4522 X86::GRH16RegClassID, // R8WH
4523 X86::GRH16RegClassID, // R9WH
4524 X86::GRH16RegClassID, // R10WH
4525 X86::GRH16RegClassID, // R11WH
4526 X86::GRH16RegClassID, // R12WH
4527 X86::GRH16RegClassID, // R13WH
4528 X86::GRH16RegClassID, // R14WH
4529 X86::GRH16RegClassID, // R15WH
4530 X86::VR256RegClassID, // YMM0
4531 X86::VR256RegClassID, // YMM1
4532 X86::VR256RegClassID, // YMM2
4533 X86::VR256RegClassID, // YMM3
4534 X86::VR256RegClassID, // YMM4
4535 X86::VR256RegClassID, // YMM5
4536 X86::VR256RegClassID, // YMM6
4537 X86::VR256RegClassID, // YMM7
4538 X86::VR256RegClassID, // YMM8
4539 X86::VR256RegClassID, // YMM9
4540 X86::VR256RegClassID, // YMM10
4541 X86::VR256RegClassID, // YMM11
4542 X86::VR256RegClassID, // YMM12
4543 X86::VR256RegClassID, // YMM13
4544 X86::VR256RegClassID, // YMM14
4545 X86::VR256RegClassID, // YMM15
4546 X86::VK64RegClassID, // K0
4547 X86::VK64WMRegClassID, // K1
4548 X86::VK64WMRegClassID, // K2
4549 X86::VK64WMRegClassID, // K3
4550 X86::VK64WMRegClassID, // K4
4551 X86::VK64WMRegClassID, // K5
4552 X86::VK64WMRegClassID, // K6
4553 X86::VK64WMRegClassID, // K7
4554 X86::VR128XRegClassID, // XMM16
4555 X86::VR128XRegClassID, // XMM17
4556 X86::VR128XRegClassID, // XMM18
4557 X86::VR128XRegClassID, // XMM19
4558 X86::VR128XRegClassID, // XMM20
4559 X86::VR128XRegClassID, // XMM21
4560 X86::VR128XRegClassID, // XMM22
4561 X86::VR128XRegClassID, // XMM23
4562 X86::VR128XRegClassID, // XMM24
4563 X86::VR128XRegClassID, // XMM25
4564 X86::VR128XRegClassID, // XMM26
4565 X86::VR128XRegClassID, // XMM27
4566 X86::VR128XRegClassID, // XMM28
4567 X86::VR128XRegClassID, // XMM29
4568 X86::VR128XRegClassID, // XMM30
4569 X86::VR128XRegClassID, // XMM31
4570 X86::VR256XRegClassID, // YMM16
4571 X86::VR256XRegClassID, // YMM17
4572 X86::VR256XRegClassID, // YMM18
4573 X86::VR256XRegClassID, // YMM19
4574 X86::VR256XRegClassID, // YMM20
4575 X86::VR256XRegClassID, // YMM21
4576 X86::VR256XRegClassID, // YMM22
4577 X86::VR256XRegClassID, // YMM23
4578 X86::VR256XRegClassID, // YMM24
4579 X86::VR256XRegClassID, // YMM25
4580 X86::VR256XRegClassID, // YMM26
4581 X86::VR256XRegClassID, // YMM27
4582 X86::VR256XRegClassID, // YMM28
4583 X86::VR256XRegClassID, // YMM29
4584 X86::VR256XRegClassID, // YMM30
4585 X86::VR256XRegClassID, // YMM31
4586 X86::VR512_0_15RegClassID, // ZMM0
4587 X86::VR512_0_15RegClassID, // ZMM1
4588 X86::VR512_0_15RegClassID, // ZMM2
4589 X86::VR512_0_15RegClassID, // ZMM3
4590 X86::VR512_0_15RegClassID, // ZMM4
4591 X86::VR512_0_15RegClassID, // ZMM5
4592 X86::VR512_0_15RegClassID, // ZMM6
4593 X86::VR512_0_15RegClassID, // ZMM7
4594 X86::VR512_0_15RegClassID, // ZMM8
4595 X86::VR512_0_15RegClassID, // ZMM9
4596 X86::VR512_0_15RegClassID, // ZMM10
4597 X86::VR512_0_15RegClassID, // ZMM11
4598 X86::VR512_0_15RegClassID, // ZMM12
4599 X86::VR512_0_15RegClassID, // ZMM13
4600 X86::VR512_0_15RegClassID, // ZMM14
4601 X86::VR512_0_15RegClassID, // ZMM15
4602 X86::VR512RegClassID, // ZMM16
4603 X86::VR512RegClassID, // ZMM17
4604 X86::VR512RegClassID, // ZMM18
4605 X86::VR512RegClassID, // ZMM19
4606 X86::VR512RegClassID, // ZMM20
4607 X86::VR512RegClassID, // ZMM21
4608 X86::VR512RegClassID, // ZMM22
4609 X86::VR512RegClassID, // ZMM23
4610 X86::VR512RegClassID, // ZMM24
4611 X86::VR512RegClassID, // ZMM25
4612 X86::VR512RegClassID, // ZMM26
4613 X86::VR512RegClassID, // ZMM27
4614 X86::VR512RegClassID, // ZMM28
4615 X86::VR512RegClassID, // ZMM29
4616 X86::VR512RegClassID, // ZMM30
4617 X86::VR512RegClassID, // ZMM31
4618 X86::VK8PAIRRegClassID, // K0_K1
4619 X86::VK1PAIR_with_sub_mask_0_in_VK1WMRegClassID, // K2_K3
4620 X86::VK1PAIR_with_sub_mask_0_in_VK1WMRegClassID, // K4_K5
4621 X86::VK1PAIR_with_sub_mask_0_in_VK1WMRegClassID, // K6_K7
4622 InvalidRegClassID, // TMMCFG
4623 X86::TILERegClassID, // TMM0
4624 X86::TILERegClassID, // TMM1
4625 X86::TILERegClassID, // TMM2
4626 X86::TILERegClassID, // TMM3
4627 X86::TILERegClassID, // TMM4
4628 X86::TILERegClassID, // TMM5
4629 X86::TILERegClassID, // TMM6
4630 X86::TILERegClassID, // TMM7
4631 X86::GR64_NOSPRegClassID, // R16
4632 X86::GR64_NOSPRegClassID, // R17
4633 X86::GR64_NOSPRegClassID, // R18
4634 X86::GR64_NOSPRegClassID, // R19
4635 X86::GR64_NOSPRegClassID, // R20
4636 X86::GR64_NOSPRegClassID, // R21
4637 X86::GR64_NOSPRegClassID, // R22
4638 X86::GR64_NOSPRegClassID, // R23
4639 X86::GR64_NOSPRegClassID, // R24
4640 X86::GR64_NOSPRegClassID, // R25
4641 X86::GR64_NOSPRegClassID, // R26
4642 X86::GR64_NOSPRegClassID, // R27
4643 X86::GR64_NOSPRegClassID, // R28
4644 X86::GR64_NOSPRegClassID, // R29
4645 X86::GR64_NOSPRegClassID, // R30
4646 X86::GR64_NOSPRegClassID, // R31
4647 X86::GR8RegClassID, // R16B
4648 X86::GR8RegClassID, // R17B
4649 X86::GR8RegClassID, // R18B
4650 X86::GR8RegClassID, // R19B
4651 X86::GR8RegClassID, // R20B
4652 X86::GR8RegClassID, // R21B
4653 X86::GR8RegClassID, // R22B
4654 X86::GR8RegClassID, // R23B
4655 X86::GR8RegClassID, // R24B
4656 X86::GR8RegClassID, // R25B
4657 X86::GR8RegClassID, // R26B
4658 X86::GR8RegClassID, // R27B
4659 X86::GR8RegClassID, // R28B
4660 X86::GR8RegClassID, // R29B
4661 X86::GR8RegClassID, // R30B
4662 X86::GR8RegClassID, // R31B
4663 X86::GRH8RegClassID, // R16BH
4664 X86::GRH8RegClassID, // R17BH
4665 X86::GRH8RegClassID, // R18BH
4666 X86::GRH8RegClassID, // R19BH
4667 X86::GRH8RegClassID, // R20BH
4668 X86::GRH8RegClassID, // R21BH
4669 X86::GRH8RegClassID, // R22BH
4670 X86::GRH8RegClassID, // R23BH
4671 X86::GRH8RegClassID, // R24BH
4672 X86::GRH8RegClassID, // R25BH
4673 X86::GRH8RegClassID, // R26BH
4674 X86::GRH8RegClassID, // R27BH
4675 X86::GRH8RegClassID, // R28BH
4676 X86::GRH8RegClassID, // R29BH
4677 X86::GRH8RegClassID, // R30BH
4678 X86::GRH8RegClassID, // R31BH
4679 X86::GR32_NOSPRegClassID, // R16D
4680 X86::GR32_NOSPRegClassID, // R17D
4681 X86::GR32_NOSPRegClassID, // R18D
4682 X86::GR32_NOSPRegClassID, // R19D
4683 X86::GR32_NOSPRegClassID, // R20D
4684 X86::GR32_NOSPRegClassID, // R21D
4685 X86::GR32_NOSPRegClassID, // R22D
4686 X86::GR32_NOSPRegClassID, // R23D
4687 X86::GR32_NOSPRegClassID, // R24D
4688 X86::GR32_NOSPRegClassID, // R25D
4689 X86::GR32_NOSPRegClassID, // R26D
4690 X86::GR32_NOSPRegClassID, // R27D
4691 X86::GR32_NOSPRegClassID, // R28D
4692 X86::GR32_NOSPRegClassID, // R29D
4693 X86::GR32_NOSPRegClassID, // R30D
4694 X86::GR32_NOSPRegClassID, // R31D
4695 X86::GR16RegClassID, // R16W
4696 X86::GR16RegClassID, // R17W
4697 X86::GR16RegClassID, // R18W
4698 X86::GR16RegClassID, // R19W
4699 X86::GR16RegClassID, // R20W
4700 X86::GR16RegClassID, // R21W
4701 X86::GR16RegClassID, // R22W
4702 X86::GR16RegClassID, // R23W
4703 X86::GR16RegClassID, // R24W
4704 X86::GR16RegClassID, // R25W
4705 X86::GR16RegClassID, // R26W
4706 X86::GR16RegClassID, // R27W
4707 X86::GR16RegClassID, // R28W
4708 X86::GR16RegClassID, // R29W
4709 X86::GR16RegClassID, // R30W
4710 X86::GR16RegClassID, // R31W
4711 X86::GRH16RegClassID, // R16WH
4712 X86::GRH16RegClassID, // R17WH
4713 X86::GRH16RegClassID, // R18WH
4714 X86::GRH16RegClassID, // R19WH
4715 X86::GRH16RegClassID, // R20WH
4716 X86::GRH16RegClassID, // R21WH
4717 X86::GRH16RegClassID, // R22WH
4718 X86::GRH16RegClassID, // R23WH
4719 X86::GRH16RegClassID, // R24WH
4720 X86::GRH16RegClassID, // R25WH
4721 X86::GRH16RegClassID, // R26WH
4722 X86::GRH16RegClassID, // R27WH
4723 X86::GRH16RegClassID, // R28WH
4724 X86::GRH16RegClassID, // R29WH
4725 X86::GRH16RegClassID, // R30WH
4726 X86::GRH16RegClassID, // R31WH
4727 };
4728
4729 assert(Reg < ArrayRef(Mapping).size());
4730 unsigned RCID = Mapping[Reg.id()];
4731 if (RCID == InvalidRegClassID)
4732 return nullptr;
4733 return &X86MCRegisterClassStorage.Classes[RCID];
4734}
4735extern const MCRegisterDesc X86RegDesc[];
4736extern const int16_t X86RegDiffLists[];
4737extern const LaneBitmask X86LaneMaskLists[];
4738extern const char X86RegStrings[];
4739extern const char X86RegClassStrings[];
4740extern const MCPhysReg X86RegUnitRoots[][2];
4741extern const uint16_t X86SubRegIdxLists[];
4742extern const uint16_t X86RegEncodingTable[];
4743// X86 Dwarf<->LLVM register mappings.
4744extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[];
4745extern const unsigned X86DwarfFlavour0Dwarf2LSize;
4746
4747extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[];
4748extern const unsigned X86DwarfFlavour1Dwarf2LSize;
4749
4750extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[];
4751extern const unsigned X86DwarfFlavour2Dwarf2LSize;
4752
4753extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[];
4754extern const unsigned X86EHFlavour0Dwarf2LSize;
4755
4756extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[];
4757extern const unsigned X86EHFlavour1Dwarf2LSize;
4758
4759extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[];
4760extern const unsigned X86EHFlavour2Dwarf2LSize;
4761
4762extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[];
4763extern const unsigned X86DwarfFlavour0L2DwarfSize;
4764
4765extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[];
4766extern const unsigned X86DwarfFlavour1L2DwarfSize;
4767
4768extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[];
4769extern const unsigned X86DwarfFlavour2L2DwarfSize;
4770
4771extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[];
4772extern const unsigned X86EHFlavour0L2DwarfSize;
4773
4774extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[];
4775extern const unsigned X86EHFlavour1L2DwarfSize;
4776
4777extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[];
4778extern const unsigned X86EHFlavour2L2DwarfSize;
4779
4780
4781X86GenRegisterInfo::
4782X86GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
4783 unsigned PC, unsigned HwMode)
4784 : TargetRegisterInfo(&X86RegInfoDesc,
4785 X86SubRegIndexStrings, X86SubRegIndexNameOffsets,
4786 X86SubRegIdxRangeTable, X86SubRegIndexLaneMaskTable,
4787
4788 LaneBitmask(0xFFFFFFFFFFFFFFB0), X86RegClassInfos, X86VTLists, HwMode) {
4789 InitMCRegisterInfo(D: X86RegDesc, NR: 388, RA, PC,
4790 C: &getX86MCRegisterClass(RC: 0), NC: 135, RURoots: X86RegUnitRoots, NRU: 221, DL: X86RegDiffLists,
4791 RUMS: X86LaneMaskLists, Strings: X86RegStrings, ClassStrings: X86RegClassStrings, SubIndices: X86SubRegIdxLists, NumIndices: 11,
4792 RET: X86RegEncodingTable, RUI: nullptr);
4793
4794 switch (DwarfFlavour) {
4795 default:
4796 llvm_unreachable("Unknown DWARF flavour");
4797 case 0:
4798 mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour0Dwarf2L, Size: X86DwarfFlavour0Dwarf2LSize, isEH: false);
4799 break;
4800 case 1:
4801 mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour1Dwarf2L, Size: X86DwarfFlavour1Dwarf2LSize, isEH: false);
4802 break;
4803 case 2:
4804 mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour2Dwarf2L, Size: X86DwarfFlavour2Dwarf2LSize, isEH: false);
4805 break;
4806 }
4807 switch (EHFlavour) {
4808 default:
4809 llvm_unreachable("Unknown DWARF flavour");
4810 case 0:
4811 mapDwarfRegsToLLVMRegs(Map: X86EHFlavour0Dwarf2L, Size: X86EHFlavour0Dwarf2LSize, isEH: true);
4812 break;
4813 case 1:
4814 mapDwarfRegsToLLVMRegs(Map: X86EHFlavour1Dwarf2L, Size: X86EHFlavour1Dwarf2LSize, isEH: true);
4815 break;
4816 case 2:
4817 mapDwarfRegsToLLVMRegs(Map: X86EHFlavour2Dwarf2L, Size: X86EHFlavour2Dwarf2LSize, isEH: true);
4818 break;
4819 }
4820 switch (DwarfFlavour) {
4821 default:
4822 llvm_unreachable("Unknown DWARF flavour");
4823 case 0:
4824 mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour0L2Dwarf, Size: X86DwarfFlavour0L2DwarfSize, isEH: false);
4825 break;
4826 case 1:
4827 mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour1L2Dwarf, Size: X86DwarfFlavour1L2DwarfSize, isEH: false);
4828 break;
4829 case 2:
4830 mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour2L2Dwarf, Size: X86DwarfFlavour2L2DwarfSize, isEH: false);
4831 break;
4832 }
4833 switch (EHFlavour) {
4834 default:
4835 llvm_unreachable("Unknown DWARF flavour");
4836 case 0:
4837 mapLLVMRegsToDwarfRegs(Map: X86EHFlavour0L2Dwarf, Size: X86EHFlavour0L2DwarfSize, isEH: true);
4838 break;
4839 case 1:
4840 mapLLVMRegsToDwarfRegs(Map: X86EHFlavour1L2Dwarf, Size: X86EHFlavour1L2DwarfSize, isEH: true);
4841 break;
4842 case 2:
4843 mapLLVMRegsToDwarfRegs(Map: X86EHFlavour2L2Dwarf, Size: X86EHFlavour2L2DwarfSize, isEH: true);
4844 break;
4845 }
4846}
4847
4848static const MCPhysReg CSR_32_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
4849static const uint32_t CSR_32_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4850static const MCPhysReg CSR_32EHRet_SaveList[] = { X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
4851static const uint32_t CSR_32EHRet_RegMask[] = { 0x0def83fe, 0xc000b701, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4852static const MCPhysReg CSR_32_AllRegs_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, 0 };
4853static const uint32_t CSR_32_AllRegs_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4854static const MCPhysReg CSR_32_AllRegs_AVX_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, 0 };
4855static const uint32_t CSR_32_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00007f80, 0x80000000, 0x0000007f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4856static const MCPhysReg CSR_32_AllRegs_AVX512_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
4857static const uint32_t CSR_32_AllRegs_AVX512_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00007f80, 0x80000000, 0x007f807f, 0x7f800000, 0x07800000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4858static const MCPhysReg CSR_32_AllRegs_SSE_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
4859static const uint32_t CSR_32_AllRegs_SSE_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00007f80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4860static const MCPhysReg CSR_32_RegCall_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
4861static const uint32_t CSR_32_RegCall_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00007800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4862static const MCPhysReg CSR_32_RegCall_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
4863static const uint32_t CSR_32_RegCall_NoSSE_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4864static const MCPhysReg CSR_64_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
4865static const uint32_t CSR_64_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4866static const MCPhysReg CSR_64EHRet_SaveList[] = { X86::RAX, X86::RDX, X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
4867static const uint32_t CSR_64EHRet_RegMask[] = { 0x09e883fe, 0x01382700, 0x00000000, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4868static const MCPhysReg CSR_64_AllRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::RAX, 0 };
4869static const uint32_t CSR_64_AllRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xffffff80, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4870static const MCPhysReg CSR_64_AllRegs_AVX_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
4871static const uint32_t CSR_64_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xffffff80, 0xffffffff, 0x00007fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4872static const MCPhysReg CSR_64_AllRegs_AVX512_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
4873static const uint32_t CSR_64_AllRegs_AVX512_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xffffff80, 0xffffffff, 0xffffffff, 0xffffffff, 0x07ffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4874static const MCPhysReg CSR_64_AllRegs_NoSSE_SaveList[] = { X86::RAX, X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
4875static const uint32_t CSR_64_AllRegs_NoSSE_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xff800000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4876static const MCPhysReg CSR_64_CXX_TLS_Darwin_PE_SaveList[] = { X86::RBP, 0 };
4877static const uint32_t CSR_64_CXX_TLS_Darwin_PE_RegMask[] = { 0x008001c0, 0x00100200, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4878static const MCPhysReg CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 };
4879static const uint32_t CSR_64_CXX_TLS_Darwin_ViaCopy_RegMask[] = { 0x0b28ae30, 0xd160ac01, 0x00000001, 0x7f800000, 0xff800000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4880static const MCPhysReg CSR_64_Intel_OCL_BI_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
4881static const uint32_t CSR_64_Intel_OCL_BI_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x787f8000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4882static const MCPhysReg CSR_64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
4883static const uint32_t CSR_64_Intel_OCL_BI_AVX_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x787f8000, 0x78787878, 0x00007f80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4884static const MCPhysReg CSR_64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RSI, X86::R14, X86::R15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
4885static const uint32_t CSR_64_Intel_OCL_BI_AVX512_RegMask[] = { 0x01000230, 0xd0208401, 0x00000001, 0x60000000, 0x60000000, 0x60606060, 0xfff80000, 0x007fffff, 0x067fff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4886static const MCPhysReg CSR_64_MostRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
4887static const uint32_t CSR_64_MostRegs_RegMask[] = { 0x0fafaff0, 0xd1f0be01, 0x00000001, 0x7f800000, 0xffffff80, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4888static const MCPhysReg CSR_64_NoneRegs_SaveList[] = { X86::RBP, 0 };
4889static const uint32_t CSR_64_NoneRegs_RegMask[] = { 0x008001c0, 0x00100200, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4890static const MCPhysReg CSR_64_RT_AllRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
4891static const uint32_t CSR_64_RT_AllRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffff80, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4892static const MCPhysReg CSR_64_RT_AllRegs_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
4893static const uint32_t CSR_64_RT_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffff80, 0xfbfbfbfb, 0x00007fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4894static const MCPhysReg CSR_64_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, 0 };
4895static const uint32_t CSR_64_RT_MostRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfb800000, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4896static const MCPhysReg CSR_64_SwiftError_SaveList[] = { X86::RBX, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
4897static const uint32_t CSR_64_SwiftError_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x70000000, 0x70000000, 0x70707070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4898static const MCPhysReg CSR_64_SwiftTail_SaveList[] = { X86::RBX, X86::R12, X86::R15, X86::RBP, 0 };
4899static const uint32_t CSR_64_SwiftTail_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x48000000, 0x48000000, 0x48484848, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4900static const MCPhysReg CSR_64_TLS_Darwin_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 };
4901static const uint32_t CSR_64_TLS_Darwin_RegMask[] = { 0x0ba8aff0, 0xd170ae01, 0x00000001, 0x7f800000, 0xff800000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4902static const MCPhysReg CSR_IPRA_32_SaveList[] = { X86::EBP, X86::ESI, 0 };
4903static const uint32_t CSR_IPRA_32_RegMask[] = { 0x008001c0, 0xc0008201, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4904static const MCPhysReg CSR_IPRA_64_SaveList[] = { X86::RBP, X86::RBX, 0 };
4905static const uint32_t CSR_IPRA_64_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4906static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
4907static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4908static const MCPhysReg CSR_SysV64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
4909static const uint32_t CSR_SysV64_RegCall_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x787f8000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4910static const MCPhysReg CSR_SysV64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
4911static const uint32_t CSR_SysV64_RegCall_NoSSE_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4912static const MCPhysReg CSR_Win32_CFGuard_Check_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::ECX, 0 };
4913static const uint32_t CSR_Win32_CFGuard_Check_RegMask[] = { 0x07872ff0, 0xc0009e01, 0x00000001, 0x00000000, 0x00007800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4914static const MCPhysReg CSR_Win32_CFGuard_Check_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ECX, 0 };
4915static const uint32_t CSR_Win32_CFGuard_Check_NoSSE_RegMask[] = { 0x07872ff0, 0xc0009e01, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4916static const MCPhysReg CSR_Win64_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
4917static const uint32_t CSR_Win64_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4918static const MCPhysReg CSR_Win64_APX_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::R30, X86::R31, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
4919static const uint32_t CSR_Win64_APX_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x000c0000, 0x000c000c, 0x000c000c, 0x0000000c, };
4920static const MCPhysReg CSR_Win64_APX_CFGuard_Check_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::R16, X86::R17, X86::R18, X86::R19, X86::R20, X86::R21, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::R28, X86::R29, X86::R30, X86::R31, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::RCX, 0 };
4921static const uint32_t CSR_Win64_APX_CFGuard_Check_RegMask[] = { 0x03802ff0, 0x00700e00, 0x00000000, 0x7e000000, 0x7e7f8000, 0x7e7e7e7e, 0x00000000, 0x00000000, 0x00000000, 0xfffffff0, 0xffffffff, 0xffffffff, 0x0000000f, };
4922static const MCPhysReg CSR_Win64_APX_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::R30, X86::R31, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
4923static const uint32_t CSR_Win64_APX_Intel_OCL_BI_AVX_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x00007fe0, 0x00000000, 0x00000000, 0x000c0000, 0x000c000c, 0x000c000c, 0x0000000c, };
4924static const MCPhysReg CSR_Win64_APX_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::R30, X86::R31, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
4925static const uint32_t CSR_Win64_APX_Intel_OCL_BI_AVX512_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x1ff87fe0, 0xe0001f80, 0x06001fff, 0x000c0000, 0x000c000c, 0x000c000c, 0x0000000c, };
4926static const MCPhysReg CSR_Win64_APX_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R30, X86::R31, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
4927static const uint32_t CSR_Win64_APX_RT_MostRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffe000, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x000c0000, 0x000c000c, 0x000c000c, 0x0000000c, };
4928static const MCPhysReg CSR_Win64_APX_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::R30, X86::R31, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
4929static const uint32_t CSR_Win64_APX_RegCall_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x7e000000, 0x7e7f8000, 0x7e7e7e7e, 0x00000000, 0x00000000, 0x00000000, 0x000c0000, 0x000c000c, 0x000c000c, 0x0000000c, };
4930static const MCPhysReg CSR_Win64_APX_SwiftError_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R13, X86::R14, X86::R15, X86::R30, X86::R31, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
4931static const uint32_t CSR_Win64_APX_SwiftError_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x70000000, 0x707fe000, 0x70707070, 0x00000000, 0x00000000, 0x00000000, 0x000c0000, 0x000c000c, 0x000c000c, 0x0000000c, };
4932static const MCPhysReg CSR_Win64_APX_SwiftTail_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R15, X86::R30, X86::R31, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
4933static const uint32_t CSR_Win64_APX_SwiftTail_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x48000000, 0x487fe000, 0x48484848, 0x00000000, 0x00000000, 0x00000000, 0x000c0000, 0x000c000c, 0x000c000c, 0x0000000c, };
4934static const MCPhysReg CSR_Win64_CFGuard_Check_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::RCX, 0 };
4935static const uint32_t CSR_Win64_CFGuard_Check_RegMask[] = { 0x03802ff0, 0x00700e00, 0x00000000, 0x7e000000, 0x7e7f8000, 0x7e7e7e7e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4936static const MCPhysReg CSR_Win64_CFGuard_Check_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RCX, 0 };
4937static const uint32_t CSR_Win64_CFGuard_Check_NoSSE_RegMask[] = { 0x03802ff0, 0x00700e00, 0x00000000, 0x7e000000, 0x7e000000, 0x7e7e7e7e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4938static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
4939static const uint32_t CSR_Win64_Intel_OCL_BI_AVX_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x00007fe0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4940static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
4941static const uint32_t CSR_Win64_Intel_OCL_BI_AVX512_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x1ff87fe0, 0xe0001f80, 0x06001fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4942static const MCPhysReg CSR_Win64_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
4943static const uint32_t CSR_Win64_NoSSE_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4944static const MCPhysReg CSR_Win64_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
4945static const uint32_t CSR_Win64_RT_MostRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffe000, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4946static const MCPhysReg CSR_Win64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
4947static const uint32_t CSR_Win64_RegCall_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x7e000000, 0x7e7f8000, 0x7e7e7e7e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4948static const MCPhysReg CSR_Win64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
4949static const uint32_t CSR_Win64_RegCall_NoSSE_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x7e000000, 0x7e000000, 0x7e7e7e7e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4950static const MCPhysReg CSR_Win64_SwiftError_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
4951static const uint32_t CSR_Win64_SwiftError_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x70000000, 0x707fe000, 0x70707070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4952static const MCPhysReg CSR_Win64_SwiftTail_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
4953static const uint32_t CSR_Win64_SwiftTail_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x48000000, 0x487fe000, 0x48484848, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
4954
4955
4956ArrayRef<const uint32_t *> X86GenRegisterInfo::getRegMasks() const {
4957 static const uint32_t *const Masks[] = {
4958 CSR_32_RegMask,
4959 CSR_32EHRet_RegMask,
4960 CSR_32_AllRegs_RegMask,
4961 CSR_32_AllRegs_AVX_RegMask,
4962 CSR_32_AllRegs_AVX512_RegMask,
4963 CSR_32_AllRegs_SSE_RegMask,
4964 CSR_32_RegCall_RegMask,
4965 CSR_32_RegCall_NoSSE_RegMask,
4966 CSR_64_RegMask,
4967 CSR_64EHRet_RegMask,
4968 CSR_64_AllRegs_RegMask,
4969 CSR_64_AllRegs_AVX_RegMask,
4970 CSR_64_AllRegs_AVX512_RegMask,
4971 CSR_64_AllRegs_NoSSE_RegMask,
4972 CSR_64_CXX_TLS_Darwin_PE_RegMask,
4973 CSR_64_CXX_TLS_Darwin_ViaCopy_RegMask,
4974 CSR_64_Intel_OCL_BI_RegMask,
4975 CSR_64_Intel_OCL_BI_AVX_RegMask,
4976 CSR_64_Intel_OCL_BI_AVX512_RegMask,
4977 CSR_64_MostRegs_RegMask,
4978 CSR_64_NoneRegs_RegMask,
4979 CSR_64_RT_AllRegs_RegMask,
4980 CSR_64_RT_AllRegs_AVX_RegMask,
4981 CSR_64_RT_MostRegs_RegMask,
4982 CSR_64_SwiftError_RegMask,
4983 CSR_64_SwiftTail_RegMask,
4984 CSR_64_TLS_Darwin_RegMask,
4985 CSR_IPRA_32_RegMask,
4986 CSR_IPRA_64_RegMask,
4987 CSR_NoRegs_RegMask,
4988 CSR_SysV64_RegCall_RegMask,
4989 CSR_SysV64_RegCall_NoSSE_RegMask,
4990 CSR_Win32_CFGuard_Check_RegMask,
4991 CSR_Win32_CFGuard_Check_NoSSE_RegMask,
4992 CSR_Win64_RegMask,
4993 CSR_Win64_APX_RegMask,
4994 CSR_Win64_APX_CFGuard_Check_RegMask,
4995 CSR_Win64_APX_Intel_OCL_BI_AVX_RegMask,
4996 CSR_Win64_APX_Intel_OCL_BI_AVX512_RegMask,
4997 CSR_Win64_APX_RT_MostRegs_RegMask,
4998 CSR_Win64_APX_RegCall_RegMask,
4999 CSR_Win64_APX_SwiftError_RegMask,
5000 CSR_Win64_APX_SwiftTail_RegMask,
5001 CSR_Win64_CFGuard_Check_RegMask,
5002 CSR_Win64_CFGuard_Check_NoSSE_RegMask,
5003 CSR_Win64_Intel_OCL_BI_AVX_RegMask,
5004 CSR_Win64_Intel_OCL_BI_AVX512_RegMask,
5005 CSR_Win64_NoSSE_RegMask,
5006 CSR_Win64_RT_MostRegs_RegMask,
5007 CSR_Win64_RegCall_RegMask,
5008 CSR_Win64_RegCall_NoSSE_RegMask,
5009 CSR_Win64_SwiftError_RegMask,
5010 CSR_Win64_SwiftTail_RegMask,
5011 };
5012 return ArrayRef(Masks);
5013}
5014
5015bool X86GenRegisterInfo::
5016isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
5017 return
5018 X86::GR64RegClass.contains(Reg: PhysReg) ||
5019 X86::GR32RegClass.contains(Reg: PhysReg) ||
5020 X86::GR16RegClass.contains(Reg: PhysReg) ||
5021 X86::GR8RegClass.contains(Reg: PhysReg) ||
5022 false;
5023}
5024
5025bool X86GenRegisterInfo::
5026isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
5027 return
5028 X86::GR64RegClass.hasSubClassEq(RC) ||
5029 X86::GR32RegClass.hasSubClassEq(RC) ||
5030 X86::GR16RegClass.hasSubClassEq(RC) ||
5031 X86::GR8RegClass.hasSubClassEq(RC) ||
5032 false;
5033}
5034
5035bool X86GenRegisterInfo::
5036isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
5037 return
5038 X86::DEBUG_REGRegClass.contains(Reg: PhysReg) ||
5039 X86::CONTROL_REGRegClass.contains(Reg: PhysReg) ||
5040 X86::CCRRegClass.contains(Reg: PhysReg) ||
5041 X86::FPCCRRegClass.contains(Reg: PhysReg) ||
5042 X86::DFCCRRegClass.contains(Reg: PhysReg) ||
5043 X86::TILERegClass.contains(Reg: PhysReg) ||
5044 X86::VK1PAIRRegClass.contains(Reg: PhysReg) ||
5045 X86::VK2PAIRRegClass.contains(Reg: PhysReg) ||
5046 X86::VK4PAIRRegClass.contains(Reg: PhysReg) ||
5047 X86::VK8PAIRRegClass.contains(Reg: PhysReg) ||
5048 X86::VK16PAIRRegClass.contains(Reg: PhysReg) ||
5049 false;
5050}
5051
5052bool X86GenRegisterInfo::
5053isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
5054 return
5055 false;
5056}
5057
5058bool X86GenRegisterInfo::
5059isConstantPhysReg(MCRegister PhysReg) const {
5060 return
5061 false;
5062}
5063
5064ArrayRef<const char *> X86GenRegisterInfo::getRegMaskNames() const {
5065 static const char *Names[] = {
5066 "CSR_32",
5067 "CSR_32EHRet",
5068 "CSR_32_AllRegs",
5069 "CSR_32_AllRegs_AVX",
5070 "CSR_32_AllRegs_AVX512",
5071 "CSR_32_AllRegs_SSE",
5072 "CSR_32_RegCall",
5073 "CSR_32_RegCall_NoSSE",
5074 "CSR_64",
5075 "CSR_64EHRet",
5076 "CSR_64_AllRegs",
5077 "CSR_64_AllRegs_AVX",
5078 "CSR_64_AllRegs_AVX512",
5079 "CSR_64_AllRegs_NoSSE",
5080 "CSR_64_CXX_TLS_Darwin_PE",
5081 "CSR_64_CXX_TLS_Darwin_ViaCopy",
5082 "CSR_64_Intel_OCL_BI",
5083 "CSR_64_Intel_OCL_BI_AVX",
5084 "CSR_64_Intel_OCL_BI_AVX512",
5085 "CSR_64_MostRegs",
5086 "CSR_64_NoneRegs",
5087 "CSR_64_RT_AllRegs",
5088 "CSR_64_RT_AllRegs_AVX",
5089 "CSR_64_RT_MostRegs",
5090 "CSR_64_SwiftError",
5091 "CSR_64_SwiftTail",
5092 "CSR_64_TLS_Darwin",
5093 "CSR_IPRA_32",
5094 "CSR_IPRA_64",
5095 "CSR_NoRegs",
5096 "CSR_SysV64_RegCall",
5097 "CSR_SysV64_RegCall_NoSSE",
5098 "CSR_Win32_CFGuard_Check",
5099 "CSR_Win32_CFGuard_Check_NoSSE",
5100 "CSR_Win64",
5101 "CSR_Win64_APX",
5102 "CSR_Win64_APX_CFGuard_Check",
5103 "CSR_Win64_APX_Intel_OCL_BI_AVX",
5104 "CSR_Win64_APX_Intel_OCL_BI_AVX512",
5105 "CSR_Win64_APX_RT_MostRegs",
5106 "CSR_Win64_APX_RegCall",
5107 "CSR_Win64_APX_SwiftError",
5108 "CSR_Win64_APX_SwiftTail",
5109 "CSR_Win64_CFGuard_Check",
5110 "CSR_Win64_CFGuard_Check_NoSSE",
5111 "CSR_Win64_Intel_OCL_BI_AVX",
5112 "CSR_Win64_Intel_OCL_BI_AVX512",
5113 "CSR_Win64_NoSSE",
5114 "CSR_Win64_RT_MostRegs",
5115 "CSR_Win64_RegCall",
5116 "CSR_Win64_RegCall_NoSSE",
5117 "CSR_Win64_SwiftError",
5118 "CSR_Win64_SwiftTail",
5119 };
5120 return ArrayRef(Names);
5121}
5122
5123const X86FrameLowering *
5124X86GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
5125 return static_cast<const X86FrameLowering *>(
5126 MF.getSubtarget().getFrameLowering());
5127}
5128
5129
5130} // namespace llvm
5131