1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass X86MCRegisterClasses[];
12
13static const MVT::SimpleValueType X86VTLists[] = {
14 /* 0 */ MVT::i8, MVT::Other,
15 /* 2 */ MVT::i16, MVT::Other,
16 /* 4 */ MVT::i32, MVT::Other,
17 /* 6 */ MVT::i64, MVT::Other,
18 /* 8 */ MVT::f16, MVT::Other,
19 /* 10 */ MVT::f80, MVT::f64, MVT::f32, MVT::Other,
20 /* 14 */ MVT::f64, MVT::Other,
21 /* 16 */ MVT::f80, MVT::Other,
22 /* 18 */ MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::v8bf16, MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::f128, MVT::Other,
23 /* 28 */ MVT::v1i1, MVT::Other,
24 /* 30 */ MVT::v2i1, MVT::Other,
25 /* 32 */ MVT::v4i1, MVT::Other,
26 /* 34 */ MVT::v8i1, MVT::Other,
27 /* 36 */ MVT::v16i1, MVT::Other,
28 /* 38 */ MVT::v32i1, MVT::Other,
29 /* 40 */ MVT::v64i1, MVT::Other,
30 /* 42 */ MVT::v8f32, MVT::v4f64, MVT::v16f16, MVT::v16bf16, MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::Other,
31 /* 51 */ MVT::v16f32, MVT::v8f64, MVT::v32f16, MVT::v32bf16, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
32 /* 60 */ MVT::v16f32, MVT::v8f64, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
33 /* 67 */ MVT::x86mmx, MVT::Other,
34 /* 69 */ MVT::Untyped, MVT::Other,
35 /* 71 */ MVT::x86amx, MVT::Other,
36};
37
38#ifdef __GNUC__
39#pragma GCC diagnostic push
40#pragma GCC diagnostic ignored "-Woverlength-strings"
41#endif
42static constexpr char X86SubRegIndexStrings[] = {
43 /* 0 */ "sub_mask_0\000"
44 /* 11 */ "sub_mask_1\000"
45 /* 22 */ "sub_16bit_hi\000"
46 /* 35 */ "sub_8bit_hi\000"
47 /* 47 */ "sub_xmm\000"
48 /* 55 */ "sub_ymm\000"
49 /* 63 */ "sub_32bit\000"
50 /* 73 */ "sub_16bit\000"
51 /* 83 */ "sub_8bit\000"
52 /* 92 */ "sub_8bit_hi_phony\000"
53};
54#ifdef __GNUC__
55#pragma GCC diagnostic pop
56#endif
57
58
59static constexpr uint32_t X86SubRegIndexNameOffsets[] = {
60 83,
61 35,
62 92,
63 73,
64 22,
65 63,
66 0,
67 11,
68 47,
69 55,
70};
71
72static const TargetRegisterInfo::SubRegCoveredBits X86SubRegIdxRangeTable[] = {
73 { .Offset: 4294967295, .Size: 4294967295 },
74 { .Offset: 0, .Size: 8 }, // sub_8bit
75 { .Offset: 8, .Size: 8 }, // sub_8bit_hi
76 { .Offset: 8, .Size: 8 }, // sub_8bit_hi_phony
77 { .Offset: 0, .Size: 16 }, // sub_16bit
78 { .Offset: 16, .Size: 16 }, // sub_16bit_hi
79 { .Offset: 0, .Size: 32 }, // sub_32bit
80 { .Offset: 0, .Size: 4294967295 }, // sub_mask_0
81 { .Offset: 4294967295, .Size: 4294967295 }, // sub_mask_1
82 { .Offset: 0, .Size: 128 }, // sub_xmm
83 { .Offset: 0, .Size: 256 }, // sub_ymm
84 { .Offset: 4294967295, .Size: 4294967295 },
85 { .Offset: 0, .Size: 8 }, // sub_8bit
86 { .Offset: 8, .Size: 8 }, // sub_8bit_hi
87 { .Offset: 8, .Size: 8 }, // sub_8bit_hi_phony
88 { .Offset: 0, .Size: 16 }, // sub_16bit
89 { .Offset: 16, .Size: 16 }, // sub_16bit_hi
90 { .Offset: 0, .Size: 32 }, // sub_32bit
91 { .Offset: 0, .Size: 4294967295 }, // sub_mask_0
92 { .Offset: 4294967295, .Size: 4294967295 }, // sub_mask_1
93 { .Offset: 0, .Size: 128 }, // sub_xmm
94 { .Offset: 0, .Size: 256 }, // sub_ymm
95 { .Offset: 4294967295, .Size: 4294967295 },
96 { .Offset: 0, .Size: 8 }, // sub_8bit
97 { .Offset: 8, .Size: 8 }, // sub_8bit_hi
98 { .Offset: 8, .Size: 8 }, // sub_8bit_hi_phony
99 { .Offset: 0, .Size: 16 }, // sub_16bit
100 { .Offset: 16, .Size: 16 }, // sub_16bit_hi
101 { .Offset: 0, .Size: 32 }, // sub_32bit
102 { .Offset: 0, .Size: 4294967295 }, // sub_mask_0
103 { .Offset: 4294967295, .Size: 4294967295 }, // sub_mask_1
104 { .Offset: 0, .Size: 128 }, // sub_xmm
105 { .Offset: 0, .Size: 256 }, // sub_ymm
106};
107
108
109static const LaneBitmask X86SubRegIndexLaneMaskTable[] = {
110 LaneBitmask::getAll(),
111 LaneBitmask(0x0000000000000001), // sub_8bit
112 LaneBitmask(0x0000000000000002), // sub_8bit_hi
113 LaneBitmask(0x0000000000000004), // sub_8bit_hi_phony
114 LaneBitmask(0x0000000000000007), // sub_16bit
115 LaneBitmask(0x0000000000000008), // sub_16bit_hi
116 LaneBitmask(0x000000000000000F), // sub_32bit
117 LaneBitmask(0x0000000000000010), // sub_mask_0
118 LaneBitmask(0x0000000000000020), // sub_mask_1
119 LaneBitmask(0x0000000000000040), // sub_xmm
120 LaneBitmask(0x0000000000000040), // sub_ymm
121 };
122
123
124
125static const TargetRegisterInfo::RegClassInfo X86RegClassInfos[] = {
126 // Mode = 0 (DefaultMode)
127 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8
128 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GRH8
129 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_NOREX2
130 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_NOREX
131 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_H
132 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_L
133 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GRH16
134 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16
135 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_NOREX2
136 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_NOREX
137 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 28 }, // VK1
138 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 36 }, // VK16
139 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 30 }, // VK2
140 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 32 }, // VK4
141 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 34 }, // VK8
142 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 36 }, // VK16WM
143 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 28 }, // VK1WM
144 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 30 }, // VK2WM
145 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 32 }, // VK4WM
146 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 34 }, // VK8WM
147 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // SEGMENT_REG
148 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_ABCD
149 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // FPCCR
150 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 8 }, // FR16X
151 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 8 }, // FR16
152 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK16PAIR
153 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK1PAIR
154 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK2PAIR
155 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK4PAIR
156 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK8PAIR
157 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK1PAIR_with_sub_mask_0_in_VK1WM
158 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP
159 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS
160 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
161 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // FR32X
162 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32
163 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOSP
164 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
165 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // DEBUG_REG
166 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // FR32
167 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2
168 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2_NOSP
169 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
170 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX
171 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 38 }, // VK32
172 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX_NOSP
173 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // RFP32
174 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 38 }, // VK32WM
175 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD
176 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_TC
177 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_TC
178 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_AD
179 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef
180 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP
181 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BSI
182 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_CB
183 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DC
184 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DIBP
185 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_SIDI
186 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
187 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // CCR
188 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // DFCCR
189 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_BSI
190 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_AD_and_GR32_ArgRef
191 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef_and_GR32_CB
192 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_DIBP
193 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_TC
194 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BSI_and_GR32_SIDI
195 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DIBP_and_GR32_SIDI
196 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
197 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_with_sub_32bit
198 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 14 }, // RFP64
199 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64
200 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 14 }, // FR64X
201 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_8bit
202 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOSP
203 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2
204 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // CONTROL_REG
205 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 14 }, // FR64
206 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX2
207 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP
208 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe
209 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC
210 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX
211 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64
212 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_with_sub_8bit
213 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TC
214 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_with_sub_8bit
215 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_TCW64
216 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX
217 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 40 }, // VK64
218 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 67 }, // VR64
219 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TC
220 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TCW64
221 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_NOSP
222 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TC
223 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_and_GR64_TC_with_sub_8bit
224 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 40 }, // VK64WM
225 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
226 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
227 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TCW64
228 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
229 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TCW64
230 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ABCD
231 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_TC
232 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
233 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_AD
234 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef
235 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS_RBP
236 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef
237 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP
238 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI
239 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_CB
240 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP
241 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_SIDI
242 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_A
243 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef_and_GR64_TC
244 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS
245 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
246 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
247 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
248 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
249 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
250 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
251 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
252 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 10 }, // RST
253 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 16 }, // RFP80
254 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 16 }, // RFP80_7
255 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*X86VTLists+*/.VTListOffset: 18 }, // VR128X
256 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*X86VTLists+*/.VTListOffset: 18 }, // VR128
257 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*X86VTLists+*/.VTListOffset: 42 }, // VR256X
258 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*X86VTLists+*/.VTListOffset: 42 }, // VR256
259 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*X86VTLists+*/.VTListOffset: 51 }, // VR512
260 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*X86VTLists+*/.VTListOffset: 60 }, // VR512_0_15
261 { .RegSize: 8192, .SpillSize: 8192, .SpillAlignment: 8192, /*X86VTLists+*/.VTListOffset: 71 }, // TILE
262 // Mode = 1 (X86_64)
263 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8
264 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GRH8
265 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_NOREX2
266 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_NOREX
267 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_H
268 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_L
269 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GRH16
270 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16
271 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_NOREX2
272 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_NOREX
273 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 28 }, // VK1
274 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 36 }, // VK16
275 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 30 }, // VK2
276 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 32 }, // VK4
277 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 34 }, // VK8
278 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 36 }, // VK16WM
279 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 28 }, // VK1WM
280 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 30 }, // VK2WM
281 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 32 }, // VK4WM
282 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 34 }, // VK8WM
283 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // SEGMENT_REG
284 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_ABCD
285 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // FPCCR
286 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 8 }, // FR16X
287 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 8 }, // FR16
288 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK16PAIR
289 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK1PAIR
290 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK2PAIR
291 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK4PAIR
292 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK8PAIR
293 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK1PAIR_with_sub_mask_0_in_VK1WM
294 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP
295 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS
296 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
297 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // FR32X
298 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32
299 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOSP
300 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
301 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // DEBUG_REG
302 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // FR32
303 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2
304 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2_NOSP
305 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
306 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX
307 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 38 }, // VK32
308 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX_NOSP
309 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // RFP32
310 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 38 }, // VK32WM
311 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD
312 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_TC
313 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_TC
314 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_AD
315 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef
316 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP
317 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BSI
318 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_CB
319 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DC
320 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DIBP
321 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_SIDI
322 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
323 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // CCR
324 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // DFCCR
325 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_BSI
326 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_AD_and_GR32_ArgRef
327 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef_and_GR32_CB
328 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_DIBP
329 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_TC
330 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BSI_and_GR32_SIDI
331 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DIBP_and_GR32_SIDI
332 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
333 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_with_sub_32bit
334 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 14 }, // RFP64
335 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64
336 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 14 }, // FR64X
337 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_8bit
338 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOSP
339 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2
340 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // CONTROL_REG
341 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 14 }, // FR64
342 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX2
343 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP
344 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe
345 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC
346 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX
347 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64
348 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_with_sub_8bit
349 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TC
350 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_with_sub_8bit
351 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_TCW64
352 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX
353 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 40 }, // VK64
354 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 67 }, // VR64
355 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TC
356 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TCW64
357 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_NOSP
358 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TC
359 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_and_GR64_TC_with_sub_8bit
360 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 40 }, // VK64WM
361 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
362 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
363 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TCW64
364 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
365 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TCW64
366 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ABCD
367 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_TC
368 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
369 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_AD
370 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef
371 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS_RBP
372 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef
373 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP
374 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI
375 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_CB
376 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP
377 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_SIDI
378 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_A
379 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef_and_GR64_TC
380 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS
381 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
382 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
383 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
384 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
385 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
386 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
387 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
388 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 10 }, // RST
389 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 16 }, // RFP80
390 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 16 }, // RFP80_7
391 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*X86VTLists+*/.VTListOffset: 18 }, // VR128X
392 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*X86VTLists+*/.VTListOffset: 18 }, // VR128
393 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*X86VTLists+*/.VTListOffset: 42 }, // VR256X
394 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*X86VTLists+*/.VTListOffset: 42 }, // VR256
395 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*X86VTLists+*/.VTListOffset: 51 }, // VR512
396 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*X86VTLists+*/.VTListOffset: 60 }, // VR512_0_15
397 { .RegSize: 8192, .SpillSize: 8192, .SpillAlignment: 8192, /*X86VTLists+*/.VTListOffset: 71 }, // TILE
398 // Mode = 2 (X86_64_X32)
399 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8
400 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GRH8
401 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_NOREX2
402 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_NOREX
403 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_H
404 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_L
405 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GRH16
406 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16
407 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_NOREX2
408 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_NOREX
409 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 28 }, // VK1
410 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 36 }, // VK16
411 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 30 }, // VK2
412 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 32 }, // VK4
413 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 34 }, // VK8
414 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 36 }, // VK16WM
415 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 28 }, // VK1WM
416 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 30 }, // VK2WM
417 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 32 }, // VK4WM
418 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 34 }, // VK8WM
419 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // SEGMENT_REG
420 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_ABCD
421 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // FPCCR
422 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 8 }, // FR16X
423 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 8 }, // FR16
424 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK16PAIR
425 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK1PAIR
426 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK2PAIR
427 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK4PAIR
428 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK8PAIR
429 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK1PAIR_with_sub_mask_0_in_VK1WM
430 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP
431 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS
432 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
433 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // FR32X
434 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32
435 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOSP
436 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
437 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // DEBUG_REG
438 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // FR32
439 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2
440 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2_NOSP
441 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
442 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX
443 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 38 }, // VK32
444 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX_NOSP
445 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // RFP32
446 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 38 }, // VK32WM
447 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD
448 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_TC
449 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_TC
450 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_AD
451 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef
452 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP
453 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BSI
454 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_CB
455 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DC
456 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DIBP
457 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_SIDI
458 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
459 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // CCR
460 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // DFCCR
461 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_BSI
462 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_AD_and_GR32_ArgRef
463 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef_and_GR32_CB
464 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_DIBP
465 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_TC
466 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BSI_and_GR32_SIDI
467 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DIBP_and_GR32_SIDI
468 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
469 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_with_sub_32bit
470 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 14 }, // RFP64
471 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64
472 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 14 }, // FR64X
473 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_8bit
474 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOSP
475 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2
476 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // CONTROL_REG
477 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 14 }, // FR64
478 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX2
479 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP
480 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe
481 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC
482 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX
483 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64
484 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_with_sub_8bit
485 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TC
486 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_with_sub_8bit
487 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_TCW64
488 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX
489 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 40 }, // VK64
490 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 67 }, // VR64
491 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TC
492 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TCW64
493 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_NOSP
494 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TC
495 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_and_GR64_TC_with_sub_8bit
496 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 40 }, // VK64WM
497 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
498 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
499 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TCW64
500 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
501 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TCW64
502 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ABCD
503 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_TC
504 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
505 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_AD
506 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef
507 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS_RBP
508 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef
509 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP
510 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI
511 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_CB
512 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP
513 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_SIDI
514 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_A
515 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef_and_GR64_TC
516 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS
517 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
518 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
519 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
520 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
521 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
522 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
523 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
524 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 10 }, // RST
525 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 16 }, // RFP80
526 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 16 }, // RFP80_7
527 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*X86VTLists+*/.VTListOffset: 18 }, // VR128X
528 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*X86VTLists+*/.VTListOffset: 18 }, // VR128
529 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*X86VTLists+*/.VTListOffset: 42 }, // VR256X
530 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*X86VTLists+*/.VTListOffset: 42 }, // VR256
531 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*X86VTLists+*/.VTListOffset: 51 }, // VR512
532 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*X86VTLists+*/.VTListOffset: 60 }, // VR512_0_15
533 { .RegSize: 8192, .SpillSize: 8192, .SpillAlignment: 8192, /*X86VTLists+*/.VTListOffset: 71 }, // TILE
534};
535static const uint32_t GR8SubClassMask[] = {
536 0x0000003d, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
537 0x00200380, 0xc7ff2f3a, 0x72e38c3f, 0x1fdfefbd, 0x00000000, // sub_8bit
538 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
539};
540
541static const uint32_t GRH8SubClassMask[] = {
542 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
543};
544
545static const uint32_t GR8_NOREX2SubClassMask[] = {
546 0x0000003c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
547 0x00200300, 0xc7ff2f20, 0x72e3803f, 0x1fdfefbd, 0x00000000, // sub_8bit
548 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
549};
550
551static const uint32_t GR8_NOREXSubClassMask[] = {
552 0x00000038, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
553 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit
554 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
555};
556
557static const uint32_t GR8_ABCD_HSubClassMask[] = {
558 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
559 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
560};
561
562static const uint32_t GR8_ABCD_LSubClassMask[] = {
563 0x00000020, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
564 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit
565};
566
567static const uint32_t GRH16SubClassMask[] = {
568 0x00000040, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
569};
570
571static const uint32_t GR16SubClassMask[] = {
572 0x00200380, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
573 0x00000000, 0xc7ff2f3a, 0x72e38c3f, 0x1fdfefbd, 0x00000000, // sub_16bit
574};
575
576static const uint32_t GR16_NOREX2SubClassMask[] = {
577 0x00200300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
578 0x00000000, 0xc7ff2f20, 0x72e3803f, 0x1fdfefbd, 0x00000000, // sub_16bit
579};
580
581static const uint32_t GR16_NOREXSubClassMask[] = {
582 0x00200200, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
583 0x00000000, 0xc7ff2c00, 0x4200003f, 0x1fcfe7a8, 0x00000000, // sub_16bit
584};
585
586static const uint32_t VK1SubClassMask[] = {
587 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
588 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
589 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
590};
591
592static const uint32_t VK16SubClassMask[] = {
593 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
594 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
595 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
596};
597
598static const uint32_t VK2SubClassMask[] = {
599 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
600 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
601 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
602};
603
604static const uint32_t VK4SubClassMask[] = {
605 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
606 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
607 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
608};
609
610static const uint32_t VK8SubClassMask[] = {
611 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
612 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
613 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
614};
615
616static const uint32_t VK16WMSubClassMask[] = {
617 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
618 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
619 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
620};
621
622static const uint32_t VK1WMSubClassMask[] = {
623 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
624 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
625 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
626};
627
628static const uint32_t VK2WMSubClassMask[] = {
629 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
630 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
631 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
632};
633
634static const uint32_t VK4WMSubClassMask[] = {
635 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
636 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
637 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
638};
639
640static const uint32_t VK8WMSubClassMask[] = {
641 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
642 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
643 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
644};
645
646static const uint32_t SEGMENT_REGSubClassMask[] = {
647 0x00100000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
648};
649
650static const uint32_t GR16_ABCDSubClassMask[] = {
651 0x00200000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
652 0x00000000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_16bit
653};
654
655static const uint32_t FPCCRSubClassMask[] = {
656 0x00400000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
657};
658
659static const uint32_t FR16XSubClassMask[] = {
660 0x01800000, 0x00000084, 0x00004200, 0x00000000, 0x00000003,
661 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
662};
663
664static const uint32_t FR16SubClassMask[] = {
665 0x01000000, 0x00000080, 0x00004000, 0x00000000, 0x00000002,
666 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
667};
668
669static const uint32_t VK16PAIRSubClassMask[] = {
670 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
671};
672
673static const uint32_t VK1PAIRSubClassMask[] = {
674 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
675};
676
677static const uint32_t VK2PAIRSubClassMask[] = {
678 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
679};
680
681static const uint32_t VK4PAIRSubClassMask[] = {
682 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
683};
684
685static const uint32_t VK8PAIRSubClassMask[] = {
686 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
687};
688
689static const uint32_t VK1PAIR_with_sub_mask_0_in_VK1WMSubClassMask[] = {
690 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
691};
692
693static const uint32_t LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
694 0x80000000, 0xcfff2f3b, 0x0000007f, 0x02201000, 0x00000000,
695 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
696};
697
698static const uint32_t LOW32_ADDR_ACCESSSubClassMask[] = {
699 0x00000000, 0xc7ff2b19, 0x0000005f, 0x00200000, 0x00000000,
700 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
701};
702
703static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask[] = {
704 0x00000000, 0xc7ff2f3a, 0x0000003f, 0x02000000, 0x00000000,
705 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
706};
707
708static const uint32_t FR32XSubClassMask[] = {
709 0x00000000, 0x00000084, 0x00004200, 0x00000000, 0x00000003,
710 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
711};
712
713static const uint32_t GR32SubClassMask[] = {
714 0x00000000, 0xc7ff2b18, 0x0000001f, 0x00000000, 0x00000000,
715 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
716};
717
718static const uint32_t GR32_NOSPSubClassMask[] = {
719 0x00000000, 0xc7dd2210, 0x0000001b, 0x00000000, 0x00000000,
720 0x00000000, 0x00000000, 0x70430820, 0x1bdfaeb4, 0x00000000, // sub_32bit
721};
722
723static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2SubClassMask[] = {
724 0x00000000, 0xc7ff2f20, 0x0000003f, 0x02000000, 0x00000000,
725 0x00000000, 0x00000000, 0x72e38020, 0x1fdfefbd, 0x00000000, // sub_32bit
726};
727
728static const uint32_t DEBUG_REGSubClassMask[] = {
729 0x00000000, 0x00000040, 0x00000000, 0x00000000, 0x00000000,
730};
731
732static const uint32_t FR32SubClassMask[] = {
733 0x00000000, 0x00000080, 0x00004000, 0x00000000, 0x00000002,
734 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
735};
736
737static const uint32_t GR32_NOREX2SubClassMask[] = {
738 0x00000000, 0xc7ff2b00, 0x0000001f, 0x00000000, 0x00000000,
739 0x00000000, 0x00000000, 0x72e38020, 0x1fdfefbd, 0x00000000, // sub_32bit
740};
741
742static const uint32_t GR32_NOREX2_NOSPSubClassMask[] = {
743 0x00000000, 0xc7dd2200, 0x0000001b, 0x00000000, 0x00000000,
744 0x00000000, 0x00000000, 0x70430020, 0x1bdfaeb4, 0x00000000, // sub_32bit
745};
746
747static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
748 0x00000000, 0xc7ff2c00, 0x0000003f, 0x02000000, 0x00000000,
749 0x00000000, 0x00000000, 0x42000020, 0x1fcfe7a8, 0x00000000, // sub_32bit
750};
751
752static const uint32_t GR32_NOREXSubClassMask[] = {
753 0x00000000, 0xc7ff2800, 0x0000001f, 0x00000000, 0x00000000,
754 0x00000000, 0x00000000, 0x42000020, 0x1fcfe7a8, 0x00000000, // sub_32bit
755};
756
757static const uint32_t VK32SubClassMask[] = {
758 0x00000000, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
759 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
760 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
761};
762
763static const uint32_t GR32_NOREX_NOSPSubClassMask[] = {
764 0x00000000, 0xc7dd2000, 0x0000001b, 0x00000000, 0x00000000,
765 0x00000000, 0x00000000, 0x40000020, 0x1bcfa6a0, 0x00000000, // sub_32bit
766};
767
768static const uint32_t RFP32SubClassMask[] = {
769 0x00000000, 0x00004000, 0x00000080, 0x40000000, 0x00000000,
770};
771
772static const uint32_t VK32WMSubClassMask[] = {
773 0x00000000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
774 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
775 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
776};
777
778static const uint32_t GR32_ABCDSubClassMask[] = {
779 0x00000000, 0xc19d0000, 0x00000001, 0x00000000, 0x00000000,
780 0x00000000, 0x00000000, 0x00000000, 0x01c92680, 0x00000000, // sub_32bit
781};
782
783static const uint32_t GR32_TCSubClassMask[] = {
784 0x00000000, 0x811e0000, 0x00000005, 0x00000000, 0x00000000,
785 0x00000000, 0x00000000, 0x00000000, 0x05882700, 0x00000000, // sub_32bit
786};
787
788static const uint32_t GR32_ABCD_and_GR32_TCSubClassMask[] = {
789 0x00000000, 0x811c0000, 0x00000001, 0x00000000, 0x00000000,
790 0x00000000, 0x00000000, 0x00000000, 0x01882600, 0x00000000, // sub_32bit
791};
792
793static const uint32_t GR32_ADSubClassMask[] = {
794 0x00000000, 0x80080000, 0x00000000, 0x00000000, 0x00000000,
795 0x00000000, 0x00000000, 0x00000000, 0x00880400, 0x00000000, // sub_32bit
796};
797
798static const uint32_t GR32_ArgRefSubClassMask[] = {
799 0x00000000, 0x81100000, 0x00000001, 0x00000000, 0x00000000,
800 0x00000000, 0x00000000, 0x00000000, 0x01802000, 0x00000000, // sub_32bit
801};
802
803static const uint32_t GR32_BPSPSubClassMask[] = {
804 0x00000000, 0x00200000, 0x00000006, 0x00000000, 0x00000000,
805 0x00000000, 0x00000000, 0x00000020, 0x06004000, 0x00000000, // sub_32bit
806};
807
808static const uint32_t GR32_BSISubClassMask[] = {
809 0x00000000, 0x40400000, 0x00000008, 0x00000000, 0x00000000,
810 0x00000000, 0x00000000, 0x00000000, 0x08408000, 0x00000000, // sub_32bit
811};
812
813static const uint32_t GR32_CBSubClassMask[] = {
814 0x00000000, 0x40800000, 0x00000001, 0x00000000, 0x00000000,
815 0x00000000, 0x00000000, 0x00000000, 0x01410000, 0x00000000, // sub_32bit
816};
817
818static const uint32_t GR32_DCSubClassMask[] = {
819 0x00000000, 0x81000000, 0x00000001, 0x00000000, 0x00000000,
820 0x00000000, 0x00000000, 0x00000000, 0x01802000, 0x00000000, // sub_32bit
821};
822
823static const uint32_t GR32_DIBPSubClassMask[] = {
824 0x00000000, 0x02000000, 0x00000012, 0x00000000, 0x00000000,
825 0x00000000, 0x00000000, 0x00000020, 0x12020000, 0x00000000, // sub_32bit
826};
827
828static const uint32_t GR32_SIDISubClassMask[] = {
829 0x00000000, 0x04000000, 0x00000018, 0x00000000, 0x00000000,
830 0x00000000, 0x00000000, 0x00000000, 0x18040000, 0x00000000, // sub_32bit
831};
832
833static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask[] = {
834 0x00000000, 0x08000000, 0x00000060, 0x02201000, 0x00000000,
835};
836
837static const uint32_t CCRSubClassMask[] = {
838 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000,
839};
840
841static const uint32_t DFCCRSubClassMask[] = {
842 0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00000000,
843};
844
845static const uint32_t GR32_ABCD_and_GR32_BSISubClassMask[] = {
846 0x00000000, 0x40000000, 0x00000000, 0x00000000, 0x00000000,
847 0x00000000, 0x00000000, 0x00000000, 0x00400000, 0x00000000, // sub_32bit
848};
849
850static const uint32_t GR32_AD_and_GR32_ArgRefSubClassMask[] = {
851 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000,
852 0x00000000, 0x00000000, 0x00000000, 0x00800000, 0x00000000, // sub_32bit
853};
854
855static const uint32_t GR32_ArgRef_and_GR32_CBSubClassMask[] = {
856 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000,
857 0x00000000, 0x00000000, 0x00000000, 0x01000000, 0x00000000, // sub_32bit
858};
859
860static const uint32_t GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
861 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000,
862 0x00000000, 0x00000000, 0x00000020, 0x02000000, 0x00000000, // sub_32bit
863};
864
865static const uint32_t GR32_BPSP_and_GR32_TCSubClassMask[] = {
866 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000,
867 0x00000000, 0x00000000, 0x00000000, 0x04000000, 0x00000000, // sub_32bit
868};
869
870static const uint32_t GR32_BSI_and_GR32_SIDISubClassMask[] = {
871 0x00000000, 0x00000000, 0x00000008, 0x00000000, 0x00000000,
872 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000000, // sub_32bit
873};
874
875static const uint32_t GR32_DIBP_and_GR32_SIDISubClassMask[] = {
876 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000,
877 0x00000000, 0x00000000, 0x00000000, 0x10000000, 0x00000000, // sub_32bit
878};
879
880static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask[] = {
881 0x00000000, 0x00000000, 0x00000020, 0x02000000, 0x00000000,
882};
883
884static const uint32_t LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask[] = {
885 0x00000000, 0x00000000, 0x00000040, 0x00200000, 0x00000000,
886};
887
888static const uint32_t RFP64SubClassMask[] = {
889 0x00000000, 0x00000000, 0x00000080, 0x40000000, 0x00000000,
890};
891
892static const uint32_t GR64SubClassMask[] = {
893 0x00000000, 0x00000000, 0xf3ff9d00, 0x1ffffffd, 0x00000000,
894};
895
896static const uint32_t FR64XSubClassMask[] = {
897 0x00000000, 0x00000000, 0x00004200, 0x00000000, 0x00000003,
898 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
899};
900
901static const uint32_t GR64_with_sub_8bitSubClassMask[] = {
902 0x00000000, 0x00000000, 0x72e38c00, 0x1fdfefbd, 0x00000000,
903};
904
905static const uint32_t GR64_NOSPSubClassMask[] = {
906 0x00000000, 0x00000000, 0x70430800, 0x1bdfaeb4, 0x00000000,
907};
908
909static const uint32_t GR64_NOREX2SubClassMask[] = {
910 0x00000000, 0x00000000, 0xf3ff9000, 0x1ffffffd, 0x00000000,
911};
912
913static const uint32_t CONTROL_REGSubClassMask[] = {
914 0x00000000, 0x00000000, 0x00002000, 0x00000000, 0x00000000,
915};
916
917static const uint32_t FR64SubClassMask[] = {
918 0x00000000, 0x00000000, 0x00004000, 0x00000000, 0x00000002,
919 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
920};
921
922static const uint32_t GR64_with_sub_16bit_in_GR16_NOREX2SubClassMask[] = {
923 0x00000000, 0x00000000, 0x72e38000, 0x1fdfefbd, 0x00000000,
924};
925
926static const uint32_t GR64_NOREX2_NOSPSubClassMask[] = {
927 0x00000000, 0x00000000, 0x70430000, 0x1bdfaeb4, 0x00000000,
928};
929
930static const uint32_t GR64PLTSafeSubClassMask[] = {
931 0x00000000, 0x00000000, 0x50020000, 0x1bcfa6b0, 0x00000000,
932};
933
934static const uint32_t GR64_TCSubClassMask[] = {
935 0x00000000, 0x00000000, 0x91640000, 0x1dbc277d, 0x00000000,
936};
937
938static const uint32_t GR64_NOREXSubClassMask[] = {
939 0x00000000, 0x00000000, 0xc2080000, 0x1feff7e8, 0x00000000,
940};
941
942static const uint32_t GR64_TCW64SubClassMask[] = {
943 0x00000000, 0x00000000, 0x21900000, 0x05b82f55, 0x00000000,
944};
945
946static const uint32_t GR64_TC_with_sub_8bitSubClassMask[] = {
947 0x00000000, 0x00000000, 0x10600000, 0x1d9c273d, 0x00000000,
948};
949
950static const uint32_t GR64_NOREX2_NOSP_and_GR64_TCSubClassMask[] = {
951 0x00000000, 0x00000000, 0x10400000, 0x199c2634, 0x00000000,
952};
953
954static const uint32_t GR64_TCW64_with_sub_8bitSubClassMask[] = {
955 0x00000000, 0x00000000, 0x20800000, 0x05982f15, 0x00000000,
956};
957
958static const uint32_t GR64_TC_and_GR64_TCW64SubClassMask[] = {
959 0x00000000, 0x00000000, 0x01000000, 0x05b82755, 0x00000000,
960};
961
962static const uint32_t GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
963 0x00000000, 0x00000000, 0x42000000, 0x1fcfe7a8, 0x00000000,
964};
965
966static const uint32_t VK64SubClassMask[] = {
967 0x00000000, 0x00000000, 0x04000000, 0x00000002, 0x00000000,
968 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
969 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
970};
971
972static const uint32_t VR64SubClassMask[] = {
973 0x00000000, 0x00000000, 0x08000000, 0x00000000, 0x00000000,
974};
975
976static const uint32_t GR64PLTSafe_and_GR64_TCSubClassMask[] = {
977 0x00000000, 0x00000000, 0x10000000, 0x198c2630, 0x00000000,
978};
979
980static const uint32_t GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask[] = {
981 0x00000000, 0x00000000, 0x20000000, 0x01982e14, 0x00000000,
982};
983
984static const uint32_t GR64_NOREX_NOSPSubClassMask[] = {
985 0x00000000, 0x00000000, 0x40000000, 0x1bcfa6a0, 0x00000000,
986};
987
988static const uint32_t GR64_NOREX_and_GR64_TCSubClassMask[] = {
989 0x00000000, 0x00000000, 0x80000000, 0x1dac2768, 0x00000000,
990};
991
992static const uint32_t GR64_TCW64_and_GR64_TC_with_sub_8bitSubClassMask[] = {
993 0x00000000, 0x00000000, 0x00000000, 0x05982715, 0x00000000,
994};
995
996static const uint32_t VK64WMSubClassMask[] = {
997 0x00000000, 0x00000000, 0x00000000, 0x00000002, 0x00000000,
998 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
999 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
1000};
1001
1002static const uint32_t GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask[] = {
1003 0x00000000, 0x00000000, 0x00000000, 0x01982614, 0x00000000,
1004};
1005
1006static const uint32_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
1007 0x00000000, 0x00000000, 0x00000000, 0x1d8c2728, 0x00000000,
1008};
1009
1010static const uint32_t GR64PLTSafe_and_GR64_TCW64SubClassMask[] = {
1011 0x00000000, 0x00000000, 0x00000000, 0x01882610, 0x00000000,
1012};
1013
1014static const uint32_t GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSubClassMask[] = {
1015 0x00000000, 0x00000000, 0x00000000, 0x198c2620, 0x00000000,
1016};
1017
1018static const uint32_t GR64_NOREX_and_GR64_TCW64SubClassMask[] = {
1019 0x00000000, 0x00000000, 0x00000000, 0x05a82740, 0x00000000,
1020};
1021
1022static const uint32_t GR64_ABCDSubClassMask[] = {
1023 0x00000000, 0x00000000, 0x00000000, 0x01c92680, 0x00000000,
1024};
1025
1026static const uint32_t GR64_with_sub_32bit_in_GR32_TCSubClassMask[] = {
1027 0x00000000, 0x00000000, 0x00000000, 0x05882700, 0x00000000,
1028};
1029
1030static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSubClassMask[] = {
1031 0x00000000, 0x00000000, 0x00000000, 0x01882600, 0x00000000,
1032};
1033
1034static const uint32_t GR64_ADSubClassMask[] = {
1035 0x00000000, 0x00000000, 0x00000000, 0x00880400, 0x00000000,
1036};
1037
1038static const uint32_t GR64_ArgRefSubClassMask[] = {
1039 0x00000000, 0x00000000, 0x00000000, 0x00100800, 0x00000000,
1040};
1041
1042static const uint32_t GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
1043 0x00000000, 0x00000000, 0x00000000, 0x02201000, 0x00000000,
1044};
1045
1046static const uint32_t GR64_with_sub_32bit_in_GR32_ArgRefSubClassMask[] = {
1047 0x00000000, 0x00000000, 0x00000000, 0x01802000, 0x00000000,
1048};
1049
1050static const uint32_t GR64_with_sub_32bit_in_GR32_BPSPSubClassMask[] = {
1051 0x00000000, 0x00000000, 0x00000000, 0x06004000, 0x00000000,
1052};
1053
1054static const uint32_t GR64_with_sub_32bit_in_GR32_BSISubClassMask[] = {
1055 0x00000000, 0x00000000, 0x00000000, 0x08408000, 0x00000000,
1056};
1057
1058static const uint32_t GR64_with_sub_32bit_in_GR32_CBSubClassMask[] = {
1059 0x00000000, 0x00000000, 0x00000000, 0x01410000, 0x00000000,
1060};
1061
1062static const uint32_t GR64_with_sub_32bit_in_GR32_DIBPSubClassMask[] = {
1063 0x00000000, 0x00000000, 0x00000000, 0x12020000, 0x00000000,
1064};
1065
1066static const uint32_t GR64_with_sub_32bit_in_GR32_SIDISubClassMask[] = {
1067 0x00000000, 0x00000000, 0x00000000, 0x18040000, 0x00000000,
1068};
1069
1070static const uint32_t GR64_ASubClassMask[] = {
1071 0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00000000,
1072};
1073
1074static const uint32_t GR64_ArgRef_and_GR64_TCSubClassMask[] = {
1075 0x00000000, 0x00000000, 0x00000000, 0x00100000, 0x00000000,
1076};
1077
1078static const uint32_t GR64_and_LOW32_ADDR_ACCESSSubClassMask[] = {
1079 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00000000,
1080};
1081
1082static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask[] = {
1083 0x00000000, 0x00000000, 0x00000000, 0x00400000, 0x00000000,
1084};
1085
1086static const uint32_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSubClassMask[] = {
1087 0x00000000, 0x00000000, 0x00000000, 0x00800000, 0x00000000,
1088};
1089
1090static const uint32_t GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSubClassMask[] = {
1091 0x00000000, 0x00000000, 0x00000000, 0x01000000, 0x00000000,
1092};
1093
1094static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
1095 0x00000000, 0x00000000, 0x00000000, 0x02000000, 0x00000000,
1096};
1097
1098static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSubClassMask[] = {
1099 0x00000000, 0x00000000, 0x00000000, 0x04000000, 0x00000000,
1100};
1101
1102static const uint32_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask[] = {
1103 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000000,
1104};
1105
1106static const uint32_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask[] = {
1107 0x00000000, 0x00000000, 0x00000000, 0x10000000, 0x00000000,
1108};
1109
1110static const uint32_t RSTSubClassMask[] = {
1111 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000,
1112};
1113
1114static const uint32_t RFP80SubClassMask[] = {
1115 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00000000,
1116};
1117
1118static const uint32_t RFP80_7SubClassMask[] = {
1119 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00000000,
1120};
1121
1122static const uint32_t VR128XSubClassMask[] = {
1123 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000003,
1124 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
1125};
1126
1127static const uint32_t VR128SubClassMask[] = {
1128 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000002,
1129 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
1130};
1131
1132static const uint32_t VR256XSubClassMask[] = {
1133 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000c,
1134 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000030, // sub_ymm
1135};
1136
1137static const uint32_t VR256SubClassMask[] = {
1138 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008,
1139 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000020, // sub_ymm
1140};
1141
1142static const uint32_t VR512SubClassMask[] = {
1143 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000030,
1144};
1145
1146static const uint32_t VR512_0_15SubClassMask[] = {
1147 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000020,
1148};
1149
1150static const uint32_t TILESubClassMask[] = {
1151 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000040,
1152};
1153
1154static const uint16_t SuperRegIdxSeqs[] = {
1155 /* 0 */ 1, 0,
1156 /* 2 */ 1, 2, 0,
1157 /* 5 */ 4, 0,
1158 /* 7 */ 6, 0,
1159 /* 9 */ 7, 8, 0,
1160 /* 12 */ 9, 0,
1161 /* 14 */ 10, 0,
1162};
1163
1164static unsigned const GR8_NOREX2Superclasses[] = {
1165 X86::GR8RegClassID,
1166};
1167
1168static unsigned const GR8_NOREXSuperclasses[] = {
1169 X86::GR8RegClassID,
1170 X86::GR8_NOREX2RegClassID,
1171};
1172
1173static unsigned const GR8_ABCD_HSuperclasses[] = {
1174 X86::GR8RegClassID,
1175 X86::GR8_NOREX2RegClassID,
1176 X86::GR8_NOREXRegClassID,
1177};
1178
1179static unsigned const GR8_ABCD_LSuperclasses[] = {
1180 X86::GR8RegClassID,
1181 X86::GR8_NOREX2RegClassID,
1182 X86::GR8_NOREXRegClassID,
1183};
1184
1185static unsigned const GR16_NOREX2Superclasses[] = {
1186 X86::GR16RegClassID,
1187};
1188
1189static unsigned const GR16_NOREXSuperclasses[] = {
1190 X86::GR16RegClassID,
1191 X86::GR16_NOREX2RegClassID,
1192};
1193
1194static unsigned const VK1Superclasses[] = {
1195 X86::VK16RegClassID,
1196 X86::VK2RegClassID,
1197 X86::VK4RegClassID,
1198 X86::VK8RegClassID,
1199};
1200
1201static unsigned const VK16Superclasses[] = {
1202 X86::VK1RegClassID,
1203 X86::VK2RegClassID,
1204 X86::VK4RegClassID,
1205 X86::VK8RegClassID,
1206};
1207
1208static unsigned const VK2Superclasses[] = {
1209 X86::VK1RegClassID,
1210 X86::VK16RegClassID,
1211 X86::VK4RegClassID,
1212 X86::VK8RegClassID,
1213};
1214
1215static unsigned const VK4Superclasses[] = {
1216 X86::VK1RegClassID,
1217 X86::VK16RegClassID,
1218 X86::VK2RegClassID,
1219 X86::VK8RegClassID,
1220};
1221
1222static unsigned const VK8Superclasses[] = {
1223 X86::VK1RegClassID,
1224 X86::VK16RegClassID,
1225 X86::VK2RegClassID,
1226 X86::VK4RegClassID,
1227};
1228
1229static unsigned const VK16WMSuperclasses[] = {
1230 X86::VK1RegClassID,
1231 X86::VK16RegClassID,
1232 X86::VK2RegClassID,
1233 X86::VK4RegClassID,
1234 X86::VK8RegClassID,
1235 X86::VK1WMRegClassID,
1236 X86::VK2WMRegClassID,
1237 X86::VK4WMRegClassID,
1238 X86::VK8WMRegClassID,
1239};
1240
1241static unsigned const VK1WMSuperclasses[] = {
1242 X86::VK1RegClassID,
1243 X86::VK16RegClassID,
1244 X86::VK2RegClassID,
1245 X86::VK4RegClassID,
1246 X86::VK8RegClassID,
1247 X86::VK16WMRegClassID,
1248 X86::VK2WMRegClassID,
1249 X86::VK4WMRegClassID,
1250 X86::VK8WMRegClassID,
1251};
1252
1253static unsigned const VK2WMSuperclasses[] = {
1254 X86::VK1RegClassID,
1255 X86::VK16RegClassID,
1256 X86::VK2RegClassID,
1257 X86::VK4RegClassID,
1258 X86::VK8RegClassID,
1259 X86::VK16WMRegClassID,
1260 X86::VK1WMRegClassID,
1261 X86::VK4WMRegClassID,
1262 X86::VK8WMRegClassID,
1263};
1264
1265static unsigned const VK4WMSuperclasses[] = {
1266 X86::VK1RegClassID,
1267 X86::VK16RegClassID,
1268 X86::VK2RegClassID,
1269 X86::VK4RegClassID,
1270 X86::VK8RegClassID,
1271 X86::VK16WMRegClassID,
1272 X86::VK1WMRegClassID,
1273 X86::VK2WMRegClassID,
1274 X86::VK8WMRegClassID,
1275};
1276
1277static unsigned const VK8WMSuperclasses[] = {
1278 X86::VK1RegClassID,
1279 X86::VK16RegClassID,
1280 X86::VK2RegClassID,
1281 X86::VK4RegClassID,
1282 X86::VK8RegClassID,
1283 X86::VK16WMRegClassID,
1284 X86::VK1WMRegClassID,
1285 X86::VK2WMRegClassID,
1286 X86::VK4WMRegClassID,
1287};
1288
1289static unsigned const GR16_ABCDSuperclasses[] = {
1290 X86::GR16RegClassID,
1291 X86::GR16_NOREX2RegClassID,
1292 X86::GR16_NOREXRegClassID,
1293};
1294
1295static unsigned const FR16Superclasses[] = {
1296 X86::FR16XRegClassID,
1297};
1298
1299static unsigned const VK16PAIRSuperclasses[] = {
1300 X86::VK1PAIRRegClassID,
1301 X86::VK2PAIRRegClassID,
1302 X86::VK4PAIRRegClassID,
1303 X86::VK8PAIRRegClassID,
1304};
1305
1306static unsigned const VK1PAIRSuperclasses[] = {
1307 X86::VK16PAIRRegClassID,
1308 X86::VK2PAIRRegClassID,
1309 X86::VK4PAIRRegClassID,
1310 X86::VK8PAIRRegClassID,
1311};
1312
1313static unsigned const VK2PAIRSuperclasses[] = {
1314 X86::VK16PAIRRegClassID,
1315 X86::VK1PAIRRegClassID,
1316 X86::VK4PAIRRegClassID,
1317 X86::VK8PAIRRegClassID,
1318};
1319
1320static unsigned const VK4PAIRSuperclasses[] = {
1321 X86::VK16PAIRRegClassID,
1322 X86::VK1PAIRRegClassID,
1323 X86::VK2PAIRRegClassID,
1324 X86::VK8PAIRRegClassID,
1325};
1326
1327static unsigned const VK8PAIRSuperclasses[] = {
1328 X86::VK16PAIRRegClassID,
1329 X86::VK1PAIRRegClassID,
1330 X86::VK2PAIRRegClassID,
1331 X86::VK4PAIRRegClassID,
1332};
1333
1334static unsigned const VK1PAIR_with_sub_mask_0_in_VK1WMSuperclasses[] = {
1335 X86::VK16PAIRRegClassID,
1336 X86::VK1PAIRRegClassID,
1337 X86::VK2PAIRRegClassID,
1338 X86::VK4PAIRRegClassID,
1339 X86::VK8PAIRRegClassID,
1340};
1341
1342static unsigned const LOW32_ADDR_ACCESSSuperclasses[] = {
1343 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1344};
1345
1346static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses[] = {
1347 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1348};
1349
1350static unsigned const FR32XSuperclasses[] = {
1351 X86::FR16XRegClassID,
1352};
1353
1354static unsigned const GR32Superclasses[] = {
1355 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1356 X86::LOW32_ADDR_ACCESSRegClassID,
1357 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1358};
1359
1360static unsigned const GR32_NOSPSuperclasses[] = {
1361 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1362 X86::LOW32_ADDR_ACCESSRegClassID,
1363 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1364 X86::GR32RegClassID,
1365};
1366
1367static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Superclasses[] = {
1368 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1369 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1370};
1371
1372static unsigned const FR32Superclasses[] = {
1373 X86::FR16XRegClassID,
1374 X86::FR16RegClassID,
1375 X86::FR32XRegClassID,
1376};
1377
1378static unsigned const GR32_NOREX2Superclasses[] = {
1379 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1380 X86::LOW32_ADDR_ACCESSRegClassID,
1381 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1382 X86::GR32RegClassID,
1383 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1384};
1385
1386static unsigned const GR32_NOREX2_NOSPSuperclasses[] = {
1387 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1388 X86::LOW32_ADDR_ACCESSRegClassID,
1389 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1390 X86::GR32RegClassID,
1391 X86::GR32_NOSPRegClassID,
1392 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1393 X86::GR32_NOREX2RegClassID,
1394};
1395
1396static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
1397 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1398 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1399 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1400};
1401
1402static unsigned const GR32_NOREXSuperclasses[] = {
1403 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1404 X86::LOW32_ADDR_ACCESSRegClassID,
1405 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1406 X86::GR32RegClassID,
1407 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1408 X86::GR32_NOREX2RegClassID,
1409 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1410};
1411
1412static unsigned const VK32Superclasses[] = {
1413 X86::VK1RegClassID,
1414 X86::VK16RegClassID,
1415 X86::VK2RegClassID,
1416 X86::VK4RegClassID,
1417 X86::VK8RegClassID,
1418};
1419
1420static unsigned const GR32_NOREX_NOSPSuperclasses[] = {
1421 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1422 X86::LOW32_ADDR_ACCESSRegClassID,
1423 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1424 X86::GR32RegClassID,
1425 X86::GR32_NOSPRegClassID,
1426 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1427 X86::GR32_NOREX2RegClassID,
1428 X86::GR32_NOREX2_NOSPRegClassID,
1429 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1430 X86::GR32_NOREXRegClassID,
1431};
1432
1433static unsigned const VK32WMSuperclasses[] = {
1434 X86::VK1RegClassID,
1435 X86::VK16RegClassID,
1436 X86::VK2RegClassID,
1437 X86::VK4RegClassID,
1438 X86::VK8RegClassID,
1439 X86::VK16WMRegClassID,
1440 X86::VK1WMRegClassID,
1441 X86::VK2WMRegClassID,
1442 X86::VK4WMRegClassID,
1443 X86::VK8WMRegClassID,
1444 X86::VK32RegClassID,
1445};
1446
1447static unsigned const GR32_ABCDSuperclasses[] = {
1448 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1449 X86::LOW32_ADDR_ACCESSRegClassID,
1450 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1451 X86::GR32RegClassID,
1452 X86::GR32_NOSPRegClassID,
1453 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1454 X86::GR32_NOREX2RegClassID,
1455 X86::GR32_NOREX2_NOSPRegClassID,
1456 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1457 X86::GR32_NOREXRegClassID,
1458 X86::GR32_NOREX_NOSPRegClassID,
1459};
1460
1461static unsigned const GR32_TCSuperclasses[] = {
1462 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1463 X86::LOW32_ADDR_ACCESSRegClassID,
1464 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1465 X86::GR32RegClassID,
1466 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1467 X86::GR32_NOREX2RegClassID,
1468 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1469 X86::GR32_NOREXRegClassID,
1470};
1471
1472static unsigned const GR32_ABCD_and_GR32_TCSuperclasses[] = {
1473 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1474 X86::LOW32_ADDR_ACCESSRegClassID,
1475 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1476 X86::GR32RegClassID,
1477 X86::GR32_NOSPRegClassID,
1478 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1479 X86::GR32_NOREX2RegClassID,
1480 X86::GR32_NOREX2_NOSPRegClassID,
1481 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1482 X86::GR32_NOREXRegClassID,
1483 X86::GR32_NOREX_NOSPRegClassID,
1484 X86::GR32_ABCDRegClassID,
1485 X86::GR32_TCRegClassID,
1486};
1487
1488static unsigned const GR32_ADSuperclasses[] = {
1489 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1490 X86::LOW32_ADDR_ACCESSRegClassID,
1491 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1492 X86::GR32RegClassID,
1493 X86::GR32_NOSPRegClassID,
1494 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1495 X86::GR32_NOREX2RegClassID,
1496 X86::GR32_NOREX2_NOSPRegClassID,
1497 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1498 X86::GR32_NOREXRegClassID,
1499 X86::GR32_NOREX_NOSPRegClassID,
1500 X86::GR32_ABCDRegClassID,
1501 X86::GR32_TCRegClassID,
1502 X86::GR32_ABCD_and_GR32_TCRegClassID,
1503};
1504
1505static unsigned const GR32_ArgRefSuperclasses[] = {
1506 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1507 X86::LOW32_ADDR_ACCESSRegClassID,
1508 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1509 X86::GR32RegClassID,
1510 X86::GR32_NOSPRegClassID,
1511 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1512 X86::GR32_NOREX2RegClassID,
1513 X86::GR32_NOREX2_NOSPRegClassID,
1514 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1515 X86::GR32_NOREXRegClassID,
1516 X86::GR32_NOREX_NOSPRegClassID,
1517 X86::GR32_ABCDRegClassID,
1518 X86::GR32_TCRegClassID,
1519 X86::GR32_ABCD_and_GR32_TCRegClassID,
1520};
1521
1522static unsigned const GR32_BPSPSuperclasses[] = {
1523 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1524 X86::LOW32_ADDR_ACCESSRegClassID,
1525 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1526 X86::GR32RegClassID,
1527 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1528 X86::GR32_NOREX2RegClassID,
1529 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1530 X86::GR32_NOREXRegClassID,
1531};
1532
1533static unsigned const GR32_BSISuperclasses[] = {
1534 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1535 X86::LOW32_ADDR_ACCESSRegClassID,
1536 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1537 X86::GR32RegClassID,
1538 X86::GR32_NOSPRegClassID,
1539 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1540 X86::GR32_NOREX2RegClassID,
1541 X86::GR32_NOREX2_NOSPRegClassID,
1542 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1543 X86::GR32_NOREXRegClassID,
1544 X86::GR32_NOREX_NOSPRegClassID,
1545};
1546
1547static unsigned const GR32_CBSuperclasses[] = {
1548 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1549 X86::LOW32_ADDR_ACCESSRegClassID,
1550 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1551 X86::GR32RegClassID,
1552 X86::GR32_NOSPRegClassID,
1553 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1554 X86::GR32_NOREX2RegClassID,
1555 X86::GR32_NOREX2_NOSPRegClassID,
1556 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1557 X86::GR32_NOREXRegClassID,
1558 X86::GR32_NOREX_NOSPRegClassID,
1559 X86::GR32_ABCDRegClassID,
1560};
1561
1562static unsigned const GR32_DCSuperclasses[] = {
1563 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1564 X86::LOW32_ADDR_ACCESSRegClassID,
1565 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1566 X86::GR32RegClassID,
1567 X86::GR32_NOSPRegClassID,
1568 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1569 X86::GR32_NOREX2RegClassID,
1570 X86::GR32_NOREX2_NOSPRegClassID,
1571 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1572 X86::GR32_NOREXRegClassID,
1573 X86::GR32_NOREX_NOSPRegClassID,
1574 X86::GR32_ABCDRegClassID,
1575 X86::GR32_TCRegClassID,
1576 X86::GR32_ABCD_and_GR32_TCRegClassID,
1577 X86::GR32_ArgRefRegClassID,
1578};
1579
1580static unsigned const GR32_DIBPSuperclasses[] = {
1581 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1582 X86::LOW32_ADDR_ACCESSRegClassID,
1583 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1584 X86::GR32RegClassID,
1585 X86::GR32_NOSPRegClassID,
1586 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1587 X86::GR32_NOREX2RegClassID,
1588 X86::GR32_NOREX2_NOSPRegClassID,
1589 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1590 X86::GR32_NOREXRegClassID,
1591 X86::GR32_NOREX_NOSPRegClassID,
1592};
1593
1594static unsigned const GR32_SIDISuperclasses[] = {
1595 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1596 X86::LOW32_ADDR_ACCESSRegClassID,
1597 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1598 X86::GR32RegClassID,
1599 X86::GR32_NOSPRegClassID,
1600 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1601 X86::GR32_NOREX2RegClassID,
1602 X86::GR32_NOREX2_NOSPRegClassID,
1603 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1604 X86::GR32_NOREXRegClassID,
1605 X86::GR32_NOREX_NOSPRegClassID,
1606};
1607
1608static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses[] = {
1609 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1610};
1611
1612static unsigned const GR32_ABCD_and_GR32_BSISuperclasses[] = {
1613 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1614 X86::LOW32_ADDR_ACCESSRegClassID,
1615 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1616 X86::GR32RegClassID,
1617 X86::GR32_NOSPRegClassID,
1618 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1619 X86::GR32_NOREX2RegClassID,
1620 X86::GR32_NOREX2_NOSPRegClassID,
1621 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1622 X86::GR32_NOREXRegClassID,
1623 X86::GR32_NOREX_NOSPRegClassID,
1624 X86::GR32_ABCDRegClassID,
1625 X86::GR32_BSIRegClassID,
1626 X86::GR32_CBRegClassID,
1627};
1628
1629static unsigned const GR32_AD_and_GR32_ArgRefSuperclasses[] = {
1630 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1631 X86::LOW32_ADDR_ACCESSRegClassID,
1632 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1633 X86::GR32RegClassID,
1634 X86::GR32_NOSPRegClassID,
1635 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1636 X86::GR32_NOREX2RegClassID,
1637 X86::GR32_NOREX2_NOSPRegClassID,
1638 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1639 X86::GR32_NOREXRegClassID,
1640 X86::GR32_NOREX_NOSPRegClassID,
1641 X86::GR32_ABCDRegClassID,
1642 X86::GR32_TCRegClassID,
1643 X86::GR32_ABCD_and_GR32_TCRegClassID,
1644 X86::GR32_ADRegClassID,
1645 X86::GR32_ArgRefRegClassID,
1646 X86::GR32_DCRegClassID,
1647};
1648
1649static unsigned const GR32_ArgRef_and_GR32_CBSuperclasses[] = {
1650 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1651 X86::LOW32_ADDR_ACCESSRegClassID,
1652 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1653 X86::GR32RegClassID,
1654 X86::GR32_NOSPRegClassID,
1655 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1656 X86::GR32_NOREX2RegClassID,
1657 X86::GR32_NOREX2_NOSPRegClassID,
1658 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1659 X86::GR32_NOREXRegClassID,
1660 X86::GR32_NOREX_NOSPRegClassID,
1661 X86::GR32_ABCDRegClassID,
1662 X86::GR32_TCRegClassID,
1663 X86::GR32_ABCD_and_GR32_TCRegClassID,
1664 X86::GR32_ArgRefRegClassID,
1665 X86::GR32_CBRegClassID,
1666 X86::GR32_DCRegClassID,
1667};
1668
1669static unsigned const GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
1670 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1671 X86::LOW32_ADDR_ACCESSRegClassID,
1672 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1673 X86::GR32RegClassID,
1674 X86::GR32_NOSPRegClassID,
1675 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1676 X86::GR32_NOREX2RegClassID,
1677 X86::GR32_NOREX2_NOSPRegClassID,
1678 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1679 X86::GR32_NOREXRegClassID,
1680 X86::GR32_NOREX_NOSPRegClassID,
1681 X86::GR32_BPSPRegClassID,
1682 X86::GR32_DIBPRegClassID,
1683};
1684
1685static unsigned const GR32_BPSP_and_GR32_TCSuperclasses[] = {
1686 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1687 X86::LOW32_ADDR_ACCESSRegClassID,
1688 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1689 X86::GR32RegClassID,
1690 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1691 X86::GR32_NOREX2RegClassID,
1692 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1693 X86::GR32_NOREXRegClassID,
1694 X86::GR32_TCRegClassID,
1695 X86::GR32_BPSPRegClassID,
1696};
1697
1698static unsigned const GR32_BSI_and_GR32_SIDISuperclasses[] = {
1699 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1700 X86::LOW32_ADDR_ACCESSRegClassID,
1701 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1702 X86::GR32RegClassID,
1703 X86::GR32_NOSPRegClassID,
1704 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1705 X86::GR32_NOREX2RegClassID,
1706 X86::GR32_NOREX2_NOSPRegClassID,
1707 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1708 X86::GR32_NOREXRegClassID,
1709 X86::GR32_NOREX_NOSPRegClassID,
1710 X86::GR32_BSIRegClassID,
1711 X86::GR32_SIDIRegClassID,
1712};
1713
1714static unsigned const GR32_DIBP_and_GR32_SIDISuperclasses[] = {
1715 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1716 X86::LOW32_ADDR_ACCESSRegClassID,
1717 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1718 X86::GR32RegClassID,
1719 X86::GR32_NOSPRegClassID,
1720 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1721 X86::GR32_NOREX2RegClassID,
1722 X86::GR32_NOREX2_NOSPRegClassID,
1723 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1724 X86::GR32_NOREXRegClassID,
1725 X86::GR32_NOREX_NOSPRegClassID,
1726 X86::GR32_DIBPRegClassID,
1727 X86::GR32_SIDIRegClassID,
1728};
1729
1730static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses[] = {
1731 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1732 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1733 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1734 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1735 X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
1736};
1737
1738static unsigned const LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses[] = {
1739 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1740 X86::LOW32_ADDR_ACCESSRegClassID,
1741 X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
1742};
1743
1744static unsigned const RFP64Superclasses[] = {
1745 X86::RFP32RegClassID,
1746};
1747
1748static unsigned const FR64XSuperclasses[] = {
1749 X86::FR16XRegClassID,
1750 X86::FR32XRegClassID,
1751};
1752
1753static unsigned const GR64_with_sub_8bitSuperclasses[] = {
1754 X86::GR64RegClassID,
1755};
1756
1757static unsigned const GR64_NOSPSuperclasses[] = {
1758 X86::GR64RegClassID,
1759 X86::GR64_with_sub_8bitRegClassID,
1760};
1761
1762static unsigned const GR64_NOREX2Superclasses[] = {
1763 X86::GR64RegClassID,
1764};
1765
1766static unsigned const FR64Superclasses[] = {
1767 X86::FR16XRegClassID,
1768 X86::FR16RegClassID,
1769 X86::FR32XRegClassID,
1770 X86::FR32RegClassID,
1771 X86::FR64XRegClassID,
1772};
1773
1774static unsigned const GR64_with_sub_16bit_in_GR16_NOREX2Superclasses[] = {
1775 X86::GR64RegClassID,
1776 X86::GR64_with_sub_8bitRegClassID,
1777 X86::GR64_NOREX2RegClassID,
1778};
1779
1780static unsigned const GR64_NOREX2_NOSPSuperclasses[] = {
1781 X86::GR64RegClassID,
1782 X86::GR64_with_sub_8bitRegClassID,
1783 X86::GR64_NOSPRegClassID,
1784 X86::GR64_NOREX2RegClassID,
1785 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1786};
1787
1788static unsigned const GR64PLTSafeSuperclasses[] = {
1789 X86::GR64RegClassID,
1790 X86::GR64_with_sub_8bitRegClassID,
1791 X86::GR64_NOSPRegClassID,
1792 X86::GR64_NOREX2RegClassID,
1793 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1794 X86::GR64_NOREX2_NOSPRegClassID,
1795};
1796
1797static unsigned const GR64_TCSuperclasses[] = {
1798 X86::GR64RegClassID,
1799 X86::GR64_NOREX2RegClassID,
1800};
1801
1802static unsigned const GR64_NOREXSuperclasses[] = {
1803 X86::GR64RegClassID,
1804 X86::GR64_NOREX2RegClassID,
1805};
1806
1807static unsigned const GR64_TCW64Superclasses[] = {
1808 X86::GR64RegClassID,
1809 X86::GR64_NOREX2RegClassID,
1810};
1811
1812static unsigned const GR64_TC_with_sub_8bitSuperclasses[] = {
1813 X86::GR64RegClassID,
1814 X86::GR64_with_sub_8bitRegClassID,
1815 X86::GR64_NOREX2RegClassID,
1816 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1817 X86::GR64_TCRegClassID,
1818};
1819
1820static unsigned const GR64_NOREX2_NOSP_and_GR64_TCSuperclasses[] = {
1821 X86::GR64RegClassID,
1822 X86::GR64_with_sub_8bitRegClassID,
1823 X86::GR64_NOSPRegClassID,
1824 X86::GR64_NOREX2RegClassID,
1825 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1826 X86::GR64_NOREX2_NOSPRegClassID,
1827 X86::GR64_TCRegClassID,
1828 X86::GR64_TC_with_sub_8bitRegClassID,
1829};
1830
1831static unsigned const GR64_TCW64_with_sub_8bitSuperclasses[] = {
1832 X86::GR64RegClassID,
1833 X86::GR64_with_sub_8bitRegClassID,
1834 X86::GR64_NOREX2RegClassID,
1835 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1836 X86::GR64_TCW64RegClassID,
1837};
1838
1839static unsigned const GR64_TC_and_GR64_TCW64Superclasses[] = {
1840 X86::GR64RegClassID,
1841 X86::GR64_NOREX2RegClassID,
1842 X86::GR64_TCRegClassID,
1843 X86::GR64_TCW64RegClassID,
1844};
1845
1846static unsigned const GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
1847 X86::GR64RegClassID,
1848 X86::GR64_with_sub_8bitRegClassID,
1849 X86::GR64_NOREX2RegClassID,
1850 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1851 X86::GR64_NOREXRegClassID,
1852};
1853
1854static unsigned const VK64Superclasses[] = {
1855 X86::VK1RegClassID,
1856 X86::VK16RegClassID,
1857 X86::VK2RegClassID,
1858 X86::VK4RegClassID,
1859 X86::VK8RegClassID,
1860 X86::VK32RegClassID,
1861};
1862
1863static unsigned const GR64PLTSafe_and_GR64_TCSuperclasses[] = {
1864 X86::GR64RegClassID,
1865 X86::GR64_with_sub_8bitRegClassID,
1866 X86::GR64_NOSPRegClassID,
1867 X86::GR64_NOREX2RegClassID,
1868 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1869 X86::GR64_NOREX2_NOSPRegClassID,
1870 X86::GR64PLTSafeRegClassID,
1871 X86::GR64_TCRegClassID,
1872 X86::GR64_TC_with_sub_8bitRegClassID,
1873 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
1874};
1875
1876static unsigned const GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses[] = {
1877 X86::GR64RegClassID,
1878 X86::GR64_with_sub_8bitRegClassID,
1879 X86::GR64_NOSPRegClassID,
1880 X86::GR64_NOREX2RegClassID,
1881 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1882 X86::GR64_NOREX2_NOSPRegClassID,
1883 X86::GR64_TCW64RegClassID,
1884 X86::GR64_TCW64_with_sub_8bitRegClassID,
1885};
1886
1887static unsigned const GR64_NOREX_NOSPSuperclasses[] = {
1888 X86::GR64RegClassID,
1889 X86::GR64_with_sub_8bitRegClassID,
1890 X86::GR64_NOSPRegClassID,
1891 X86::GR64_NOREX2RegClassID,
1892 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1893 X86::GR64_NOREX2_NOSPRegClassID,
1894 X86::GR64PLTSafeRegClassID,
1895 X86::GR64_NOREXRegClassID,
1896 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
1897};
1898
1899static unsigned const GR64_NOREX_and_GR64_TCSuperclasses[] = {
1900 X86::GR64RegClassID,
1901 X86::GR64_NOREX2RegClassID,
1902 X86::GR64_TCRegClassID,
1903 X86::GR64_NOREXRegClassID,
1904};
1905
1906static unsigned const GR64_TCW64_and_GR64_TC_with_sub_8bitSuperclasses[] = {
1907 X86::GR64RegClassID,
1908 X86::GR64_with_sub_8bitRegClassID,
1909 X86::GR64_NOREX2RegClassID,
1910 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1911 X86::GR64_TCRegClassID,
1912 X86::GR64_TCW64RegClassID,
1913 X86::GR64_TC_with_sub_8bitRegClassID,
1914 X86::GR64_TCW64_with_sub_8bitRegClassID,
1915 X86::GR64_TC_and_GR64_TCW64RegClassID,
1916};
1917
1918static unsigned const VK64WMSuperclasses[] = {
1919 X86::VK1RegClassID,
1920 X86::VK16RegClassID,
1921 X86::VK2RegClassID,
1922 X86::VK4RegClassID,
1923 X86::VK8RegClassID,
1924 X86::VK16WMRegClassID,
1925 X86::VK1WMRegClassID,
1926 X86::VK2WMRegClassID,
1927 X86::VK4WMRegClassID,
1928 X86::VK8WMRegClassID,
1929 X86::VK32RegClassID,
1930 X86::VK32WMRegClassID,
1931 X86::VK64RegClassID,
1932};
1933
1934static unsigned const GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses[] = {
1935 X86::GR64RegClassID,
1936 X86::GR64_with_sub_8bitRegClassID,
1937 X86::GR64_NOSPRegClassID,
1938 X86::GR64_NOREX2RegClassID,
1939 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1940 X86::GR64_NOREX2_NOSPRegClassID,
1941 X86::GR64_TCRegClassID,
1942 X86::GR64_TCW64RegClassID,
1943 X86::GR64_TC_with_sub_8bitRegClassID,
1944 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
1945 X86::GR64_TCW64_with_sub_8bitRegClassID,
1946 X86::GR64_TC_and_GR64_TCW64RegClassID,
1947 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
1948 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
1949};
1950
1951static unsigned const GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
1952 X86::GR64RegClassID,
1953 X86::GR64_with_sub_8bitRegClassID,
1954 X86::GR64_NOREX2RegClassID,
1955 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1956 X86::GR64_TCRegClassID,
1957 X86::GR64_NOREXRegClassID,
1958 X86::GR64_TC_with_sub_8bitRegClassID,
1959 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
1960 X86::GR64_NOREX_and_GR64_TCRegClassID,
1961};
1962
1963static unsigned const GR64PLTSafe_and_GR64_TCW64Superclasses[] = {
1964 X86::GR64RegClassID,
1965 X86::GR64_with_sub_8bitRegClassID,
1966 X86::GR64_NOSPRegClassID,
1967 X86::GR64_NOREX2RegClassID,
1968 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1969 X86::GR64_NOREX2_NOSPRegClassID,
1970 X86::GR64PLTSafeRegClassID,
1971 X86::GR64_TCRegClassID,
1972 X86::GR64_TCW64RegClassID,
1973 X86::GR64_TC_with_sub_8bitRegClassID,
1974 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
1975 X86::GR64_TCW64_with_sub_8bitRegClassID,
1976 X86::GR64_TC_and_GR64_TCW64RegClassID,
1977 X86::GR64PLTSafe_and_GR64_TCRegClassID,
1978 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
1979 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
1980 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
1981};
1982
1983static unsigned const GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSuperclasses[] = {
1984 X86::GR64RegClassID,
1985 X86::GR64_with_sub_8bitRegClassID,
1986 X86::GR64_NOSPRegClassID,
1987 X86::GR64_NOREX2RegClassID,
1988 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1989 X86::GR64_NOREX2_NOSPRegClassID,
1990 X86::GR64PLTSafeRegClassID,
1991 X86::GR64_TCRegClassID,
1992 X86::GR64_NOREXRegClassID,
1993 X86::GR64_TC_with_sub_8bitRegClassID,
1994 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
1995 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
1996 X86::GR64PLTSafe_and_GR64_TCRegClassID,
1997 X86::GR64_NOREX_NOSPRegClassID,
1998 X86::GR64_NOREX_and_GR64_TCRegClassID,
1999 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2000};
2001
2002static unsigned const GR64_NOREX_and_GR64_TCW64Superclasses[] = {
2003 X86::GR64RegClassID,
2004 X86::GR64_NOREX2RegClassID,
2005 X86::GR64_TCRegClassID,
2006 X86::GR64_NOREXRegClassID,
2007 X86::GR64_TCW64RegClassID,
2008 X86::GR64_TC_and_GR64_TCW64RegClassID,
2009 X86::GR64_NOREX_and_GR64_TCRegClassID,
2010};
2011
2012static unsigned const GR64_ABCDSuperclasses[] = {
2013 X86::GR64RegClassID,
2014 X86::GR64_with_sub_8bitRegClassID,
2015 X86::GR64_NOSPRegClassID,
2016 X86::GR64_NOREX2RegClassID,
2017 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2018 X86::GR64_NOREX2_NOSPRegClassID,
2019 X86::GR64PLTSafeRegClassID,
2020 X86::GR64_NOREXRegClassID,
2021 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2022 X86::GR64_NOREX_NOSPRegClassID,
2023};
2024
2025static unsigned const GR64_with_sub_32bit_in_GR32_TCSuperclasses[] = {
2026 X86::GR64RegClassID,
2027 X86::GR64_with_sub_8bitRegClassID,
2028 X86::GR64_NOREX2RegClassID,
2029 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2030 X86::GR64_TCRegClassID,
2031 X86::GR64_NOREXRegClassID,
2032 X86::GR64_TCW64RegClassID,
2033 X86::GR64_TC_with_sub_8bitRegClassID,
2034 X86::GR64_TCW64_with_sub_8bitRegClassID,
2035 X86::GR64_TC_and_GR64_TCW64RegClassID,
2036 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2037 X86::GR64_NOREX_and_GR64_TCRegClassID,
2038 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2039 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2040 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2041};
2042
2043static unsigned const GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSuperclasses[] = {
2044 X86::GR64RegClassID,
2045 X86::GR64_with_sub_8bitRegClassID,
2046 X86::GR64_NOSPRegClassID,
2047 X86::GR64_NOREX2RegClassID,
2048 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2049 X86::GR64_NOREX2_NOSPRegClassID,
2050 X86::GR64PLTSafeRegClassID,
2051 X86::GR64_TCRegClassID,
2052 X86::GR64_NOREXRegClassID,
2053 X86::GR64_TCW64RegClassID,
2054 X86::GR64_TC_with_sub_8bitRegClassID,
2055 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2056 X86::GR64_TCW64_with_sub_8bitRegClassID,
2057 X86::GR64_TC_and_GR64_TCW64RegClassID,
2058 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2059 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2060 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2061 X86::GR64_NOREX_NOSPRegClassID,
2062 X86::GR64_NOREX_and_GR64_TCRegClassID,
2063 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2064 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2065 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2066 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
2067 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2068 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2069 X86::GR64_ABCDRegClassID,
2070 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
2071};
2072
2073static unsigned const GR64_ADSuperclasses[] = {
2074 X86::GR64RegClassID,
2075 X86::GR64_with_sub_8bitRegClassID,
2076 X86::GR64_NOSPRegClassID,
2077 X86::GR64_NOREX2RegClassID,
2078 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2079 X86::GR64_NOREX2_NOSPRegClassID,
2080 X86::GR64PLTSafeRegClassID,
2081 X86::GR64_TCRegClassID,
2082 X86::GR64_NOREXRegClassID,
2083 X86::GR64_TCW64RegClassID,
2084 X86::GR64_TC_with_sub_8bitRegClassID,
2085 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2086 X86::GR64_TCW64_with_sub_8bitRegClassID,
2087 X86::GR64_TC_and_GR64_TCW64RegClassID,
2088 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2089 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2090 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2091 X86::GR64_NOREX_NOSPRegClassID,
2092 X86::GR64_NOREX_and_GR64_TCRegClassID,
2093 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2094 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2095 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2096 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
2097 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2098 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2099 X86::GR64_ABCDRegClassID,
2100 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
2101 X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
2102};
2103
2104static unsigned const GR64_ArgRefSuperclasses[] = {
2105 X86::GR64RegClassID,
2106 X86::GR64_with_sub_8bitRegClassID,
2107 X86::GR64_NOSPRegClassID,
2108 X86::GR64_NOREX2RegClassID,
2109 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2110 X86::GR64_NOREX2_NOSPRegClassID,
2111 X86::GR64_TCW64RegClassID,
2112 X86::GR64_TCW64_with_sub_8bitRegClassID,
2113 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2114};
2115
2116static unsigned const GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses[] = {
2117 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
2118 X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
2119 X86::GR64RegClassID,
2120 X86::GR64_NOREX2RegClassID,
2121 X86::GR64_NOREXRegClassID,
2122};
2123
2124static unsigned const GR64_with_sub_32bit_in_GR32_ArgRefSuperclasses[] = {
2125 X86::GR64RegClassID,
2126 X86::GR64_with_sub_8bitRegClassID,
2127 X86::GR64_NOSPRegClassID,
2128 X86::GR64_NOREX2RegClassID,
2129 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2130 X86::GR64_NOREX2_NOSPRegClassID,
2131 X86::GR64PLTSafeRegClassID,
2132 X86::GR64_TCRegClassID,
2133 X86::GR64_NOREXRegClassID,
2134 X86::GR64_TCW64RegClassID,
2135 X86::GR64_TC_with_sub_8bitRegClassID,
2136 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2137 X86::GR64_TCW64_with_sub_8bitRegClassID,
2138 X86::GR64_TC_and_GR64_TCW64RegClassID,
2139 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2140 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2141 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2142 X86::GR64_NOREX_NOSPRegClassID,
2143 X86::GR64_NOREX_and_GR64_TCRegClassID,
2144 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2145 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2146 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2147 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
2148 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2149 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2150 X86::GR64_ABCDRegClassID,
2151 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
2152 X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
2153};
2154
2155static unsigned const GR64_with_sub_32bit_in_GR32_BPSPSuperclasses[] = {
2156 X86::GR64RegClassID,
2157 X86::GR64_with_sub_8bitRegClassID,
2158 X86::GR64_NOREX2RegClassID,
2159 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2160 X86::GR64_NOREXRegClassID,
2161 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2162};
2163
2164static unsigned const GR64_with_sub_32bit_in_GR32_BSISuperclasses[] = {
2165 X86::GR64RegClassID,
2166 X86::GR64_with_sub_8bitRegClassID,
2167 X86::GR64_NOSPRegClassID,
2168 X86::GR64_NOREX2RegClassID,
2169 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2170 X86::GR64_NOREX2_NOSPRegClassID,
2171 X86::GR64PLTSafeRegClassID,
2172 X86::GR64_NOREXRegClassID,
2173 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2174 X86::GR64_NOREX_NOSPRegClassID,
2175};
2176
2177static unsigned const GR64_with_sub_32bit_in_GR32_CBSuperclasses[] = {
2178 X86::GR64RegClassID,
2179 X86::GR64_with_sub_8bitRegClassID,
2180 X86::GR64_NOSPRegClassID,
2181 X86::GR64_NOREX2RegClassID,
2182 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2183 X86::GR64_NOREX2_NOSPRegClassID,
2184 X86::GR64PLTSafeRegClassID,
2185 X86::GR64_NOREXRegClassID,
2186 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2187 X86::GR64_NOREX_NOSPRegClassID,
2188 X86::GR64_ABCDRegClassID,
2189};
2190
2191static unsigned const GR64_with_sub_32bit_in_GR32_DIBPSuperclasses[] = {
2192 X86::GR64RegClassID,
2193 X86::GR64_with_sub_8bitRegClassID,
2194 X86::GR64_NOSPRegClassID,
2195 X86::GR64_NOREX2RegClassID,
2196 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2197 X86::GR64_NOREX2_NOSPRegClassID,
2198 X86::GR64PLTSafeRegClassID,
2199 X86::GR64_NOREXRegClassID,
2200 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2201 X86::GR64_NOREX_NOSPRegClassID,
2202};
2203
2204static unsigned const GR64_with_sub_32bit_in_GR32_SIDISuperclasses[] = {
2205 X86::GR64RegClassID,
2206 X86::GR64_with_sub_8bitRegClassID,
2207 X86::GR64_NOSPRegClassID,
2208 X86::GR64_NOREX2RegClassID,
2209 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2210 X86::GR64_NOREX2_NOSPRegClassID,
2211 X86::GR64PLTSafeRegClassID,
2212 X86::GR64_TCRegClassID,
2213 X86::GR64_NOREXRegClassID,
2214 X86::GR64_TC_with_sub_8bitRegClassID,
2215 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2216 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2217 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2218 X86::GR64_NOREX_NOSPRegClassID,
2219 X86::GR64_NOREX_and_GR64_TCRegClassID,
2220 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2221 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2222};
2223
2224static unsigned const GR64_ASuperclasses[] = {
2225 X86::GR64RegClassID,
2226 X86::GR64_with_sub_8bitRegClassID,
2227 X86::GR64_NOSPRegClassID,
2228 X86::GR64_NOREX2RegClassID,
2229 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2230 X86::GR64_NOREX2_NOSPRegClassID,
2231 X86::GR64PLTSafeRegClassID,
2232 X86::GR64_TCRegClassID,
2233 X86::GR64_NOREXRegClassID,
2234 X86::GR64_TCW64RegClassID,
2235 X86::GR64_TC_with_sub_8bitRegClassID,
2236 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2237 X86::GR64_TCW64_with_sub_8bitRegClassID,
2238 X86::GR64_TC_and_GR64_TCW64RegClassID,
2239 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2240 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2241 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2242 X86::GR64_NOREX_NOSPRegClassID,
2243 X86::GR64_NOREX_and_GR64_TCRegClassID,
2244 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2245 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2246 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2247 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
2248 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2249 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2250 X86::GR64_ABCDRegClassID,
2251 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
2252 X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
2253 X86::GR64_ADRegClassID,
2254};
2255
2256static unsigned const GR64_ArgRef_and_GR64_TCSuperclasses[] = {
2257 X86::GR64RegClassID,
2258 X86::GR64_with_sub_8bitRegClassID,
2259 X86::GR64_NOSPRegClassID,
2260 X86::GR64_NOREX2RegClassID,
2261 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2262 X86::GR64_NOREX2_NOSPRegClassID,
2263 X86::GR64_TCRegClassID,
2264 X86::GR64_TCW64RegClassID,
2265 X86::GR64_TC_with_sub_8bitRegClassID,
2266 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2267 X86::GR64_TCW64_with_sub_8bitRegClassID,
2268 X86::GR64_TC_and_GR64_TCW64RegClassID,
2269 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2270 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2271 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2272 X86::GR64_ArgRefRegClassID,
2273};
2274
2275static unsigned const GR64_and_LOW32_ADDR_ACCESSSuperclasses[] = {
2276 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
2277 X86::LOW32_ADDR_ACCESSRegClassID,
2278 X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
2279 X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClassID,
2280 X86::GR64RegClassID,
2281 X86::GR64_NOREX2RegClassID,
2282 X86::GR64_TCRegClassID,
2283 X86::GR64_NOREXRegClassID,
2284 X86::GR64_TCW64RegClassID,
2285 X86::GR64_TC_and_GR64_TCW64RegClassID,
2286 X86::GR64_NOREX_and_GR64_TCRegClassID,
2287 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2288 X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID,
2289};
2290
2291static unsigned const GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISuperclasses[] = {
2292 X86::GR64RegClassID,
2293 X86::GR64_with_sub_8bitRegClassID,
2294 X86::GR64_NOSPRegClassID,
2295 X86::GR64_NOREX2RegClassID,
2296 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2297 X86::GR64_NOREX2_NOSPRegClassID,
2298 X86::GR64PLTSafeRegClassID,
2299 X86::GR64_NOREXRegClassID,
2300 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2301 X86::GR64_NOREX_NOSPRegClassID,
2302 X86::GR64_ABCDRegClassID,
2303 X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID,
2304 X86::GR64_with_sub_32bit_in_GR32_CBRegClassID,
2305};
2306
2307static unsigned const GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSuperclasses[] = {
2308 X86::GR64RegClassID,
2309 X86::GR64_with_sub_8bitRegClassID,
2310 X86::GR64_NOSPRegClassID,
2311 X86::GR64_NOREX2RegClassID,
2312 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2313 X86::GR64_NOREX2_NOSPRegClassID,
2314 X86::GR64PLTSafeRegClassID,
2315 X86::GR64_TCRegClassID,
2316 X86::GR64_NOREXRegClassID,
2317 X86::GR64_TCW64RegClassID,
2318 X86::GR64_TC_with_sub_8bitRegClassID,
2319 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2320 X86::GR64_TCW64_with_sub_8bitRegClassID,
2321 X86::GR64_TC_and_GR64_TCW64RegClassID,
2322 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2323 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2324 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2325 X86::GR64_NOREX_NOSPRegClassID,
2326 X86::GR64_NOREX_and_GR64_TCRegClassID,
2327 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2328 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2329 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2330 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
2331 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2332 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2333 X86::GR64_ABCDRegClassID,
2334 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
2335 X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
2336 X86::GR64_ADRegClassID,
2337 X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID,
2338};
2339
2340static unsigned const GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSuperclasses[] = {
2341 X86::GR64RegClassID,
2342 X86::GR64_with_sub_8bitRegClassID,
2343 X86::GR64_NOSPRegClassID,
2344 X86::GR64_NOREX2RegClassID,
2345 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2346 X86::GR64_NOREX2_NOSPRegClassID,
2347 X86::GR64PLTSafeRegClassID,
2348 X86::GR64_TCRegClassID,
2349 X86::GR64_NOREXRegClassID,
2350 X86::GR64_TCW64RegClassID,
2351 X86::GR64_TC_with_sub_8bitRegClassID,
2352 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2353 X86::GR64_TCW64_with_sub_8bitRegClassID,
2354 X86::GR64_TC_and_GR64_TCW64RegClassID,
2355 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2356 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2357 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2358 X86::GR64_NOREX_NOSPRegClassID,
2359 X86::GR64_NOREX_and_GR64_TCRegClassID,
2360 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2361 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2362 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2363 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
2364 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2365 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2366 X86::GR64_ABCDRegClassID,
2367 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
2368 X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
2369 X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID,
2370 X86::GR64_with_sub_32bit_in_GR32_CBRegClassID,
2371};
2372
2373static unsigned const GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
2374 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
2375 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
2376 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
2377 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
2378 X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
2379 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID,
2380 X86::GR64RegClassID,
2381 X86::GR64_with_sub_8bitRegClassID,
2382 X86::GR64_NOSPRegClassID,
2383 X86::GR64_NOREX2RegClassID,
2384 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2385 X86::GR64_NOREX2_NOSPRegClassID,
2386 X86::GR64PLTSafeRegClassID,
2387 X86::GR64_NOREXRegClassID,
2388 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2389 X86::GR64_NOREX_NOSPRegClassID,
2390 X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID,
2391 X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID,
2392 X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID,
2393};
2394
2395static unsigned const GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSuperclasses[] = {
2396 X86::GR64RegClassID,
2397 X86::GR64_with_sub_8bitRegClassID,
2398 X86::GR64_NOREX2RegClassID,
2399 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2400 X86::GR64_TCRegClassID,
2401 X86::GR64_NOREXRegClassID,
2402 X86::GR64_TCW64RegClassID,
2403 X86::GR64_TC_with_sub_8bitRegClassID,
2404 X86::GR64_TCW64_with_sub_8bitRegClassID,
2405 X86::GR64_TC_and_GR64_TCW64RegClassID,
2406 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2407 X86::GR64_NOREX_and_GR64_TCRegClassID,
2408 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2409 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2410 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2411 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
2412 X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID,
2413};
2414
2415static unsigned const GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISuperclasses[] = {
2416 X86::GR64RegClassID,
2417 X86::GR64_with_sub_8bitRegClassID,
2418 X86::GR64_NOSPRegClassID,
2419 X86::GR64_NOREX2RegClassID,
2420 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2421 X86::GR64_NOREX2_NOSPRegClassID,
2422 X86::GR64PLTSafeRegClassID,
2423 X86::GR64_TCRegClassID,
2424 X86::GR64_NOREXRegClassID,
2425 X86::GR64_TC_with_sub_8bitRegClassID,
2426 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2427 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2428 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2429 X86::GR64_NOREX_NOSPRegClassID,
2430 X86::GR64_NOREX_and_GR64_TCRegClassID,
2431 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2432 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2433 X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID,
2434 X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID,
2435};
2436
2437static unsigned const GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISuperclasses[] = {
2438 X86::GR64RegClassID,
2439 X86::GR64_with_sub_8bitRegClassID,
2440 X86::GR64_NOSPRegClassID,
2441 X86::GR64_NOREX2RegClassID,
2442 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2443 X86::GR64_NOREX2_NOSPRegClassID,
2444 X86::GR64PLTSafeRegClassID,
2445 X86::GR64_TCRegClassID,
2446 X86::GR64_NOREXRegClassID,
2447 X86::GR64_TC_with_sub_8bitRegClassID,
2448 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2449 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2450 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2451 X86::GR64_NOREX_NOSPRegClassID,
2452 X86::GR64_NOREX_and_GR64_TCRegClassID,
2453 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2454 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2455 X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID,
2456 X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID,
2457};
2458
2459static unsigned const RFP80Superclasses[] = {
2460 X86::RFP32RegClassID,
2461 X86::RFP64RegClassID,
2462};
2463
2464static unsigned const VR128XSuperclasses[] = {
2465 X86::FR16XRegClassID,
2466 X86::FR32XRegClassID,
2467 X86::FR64XRegClassID,
2468};
2469
2470static unsigned const VR128Superclasses[] = {
2471 X86::FR16XRegClassID,
2472 X86::FR16RegClassID,
2473 X86::FR32XRegClassID,
2474 X86::FR32RegClassID,
2475 X86::FR64XRegClassID,
2476 X86::FR64RegClassID,
2477 X86::VR128XRegClassID,
2478};
2479
2480static unsigned const VR256Superclasses[] = {
2481 X86::VR256XRegClassID,
2482};
2483
2484static unsigned const VR512_0_15Superclasses[] = {
2485 X86::VR512RegClassID,
2486};
2487
2488
2489static inline unsigned GR8AltOrderSelect(const MachineFunction &MF, bool Rev) {
2490 return MF.getSubtarget<X86Subtarget>().is64Bit();
2491 }
2492
2493static ArrayRef<MCPhysReg> GR8GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2494 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R16B, X86::R17B, X86::R18B, X86::R19B, X86::R22B, X86::R23B, X86::R24B, X86::R25B, X86::R26B, X86::R27B, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::R20B, X86::R21B, X86::R28B, X86::R29B, X86::R30B, X86::R31B };
2495 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8RegClassID];
2496 const ArrayRef<MCPhysReg> Order[] = {
2497 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2498 ArrayRef(AltOrder1)
2499 };
2500 const unsigned Select = GR8AltOrderSelect(MF, Rev);
2501 assert(Select < 2);
2502 return Order[Select];
2503}
2504
2505static inline unsigned GR8_NOREX2AltOrderSelect(const MachineFunction &MF, bool Rev) {
2506 return MF.getSubtarget<X86Subtarget>().is64Bit();
2507 }
2508
2509static ArrayRef<MCPhysReg> GR8_NOREX2GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2510 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B };
2511 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8_NOREX2RegClassID];
2512 const ArrayRef<MCPhysReg> Order[] = {
2513 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2514 ArrayRef(AltOrder1)
2515 };
2516 const unsigned Select = GR8_NOREX2AltOrderSelect(MF, Rev);
2517 assert(Select < 2);
2518 return Order[Select];
2519}
2520
2521static inline unsigned GR8_NOREXAltOrderSelect(const MachineFunction &MF, bool Rev) {
2522 return MF.getSubtarget<X86Subtarget>().is64Bit();
2523 }
2524
2525static ArrayRef<MCPhysReg> GR8_NOREXGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2526 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL };
2527 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8_NOREXRegClassID];
2528 const ArrayRef<MCPhysReg> Order[] = {
2529 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2530 ArrayRef(AltOrder1)
2531 };
2532 const unsigned Select = GR8_NOREXAltOrderSelect(MF, Rev);
2533 assert(Select < 2);
2534 return Order[Select];
2535}
2536
2537static inline unsigned FR32XAltOrderSelect(const MachineFunction &MF, bool Rev) {
2538 return Rev;
2539 }
2540
2541static ArrayRef<MCPhysReg> FR32XGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2542 static const MCPhysReg AltOrder1[] = { X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 };
2543 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::FR32XRegClassID];
2544 const ArrayRef<MCPhysReg> Order[] = {
2545 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2546 ArrayRef(AltOrder1)
2547 };
2548 const unsigned Select = FR32XAltOrderSelect(MF, Rev);
2549 assert(Select < 2);
2550 return Order[Select];
2551}
2552
2553static inline unsigned FR64XAltOrderSelect(const MachineFunction &MF, bool Rev) {
2554 return Rev;
2555 }
2556
2557static ArrayRef<MCPhysReg> FR64XGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2558 static const MCPhysReg AltOrder1[] = { X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 };
2559 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::FR64XRegClassID];
2560 const ArrayRef<MCPhysReg> Order[] = {
2561 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2562 ArrayRef(AltOrder1)
2563 };
2564 const unsigned Select = FR64XAltOrderSelect(MF, Rev);
2565 assert(Select < 2);
2566 return Order[Select];
2567}
2568
2569static inline unsigned VR128XAltOrderSelect(const MachineFunction &MF, bool Rev) {
2570 return Rev;
2571 }
2572
2573static ArrayRef<MCPhysReg> VR128XGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2574 static const MCPhysReg AltOrder1[] = { X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 };
2575 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::VR128XRegClassID];
2576 const ArrayRef<MCPhysReg> Order[] = {
2577 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2578 ArrayRef(AltOrder1)
2579 };
2580 const unsigned Select = VR128XAltOrderSelect(MF, Rev);
2581 assert(Select < 2);
2582 return Order[Select];
2583}
2584
2585static inline unsigned VR256XAltOrderSelect(const MachineFunction &MF, bool Rev) {
2586 return Rev;
2587 }
2588
2589static ArrayRef<MCPhysReg> VR256XGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2590 static const MCPhysReg AltOrder1[] = { X86::YMM16, X86::YMM17, X86::YMM18, X86::YMM19, X86::YMM20, X86::YMM21, X86::YMM22, X86::YMM23, X86::YMM24, X86::YMM25, X86::YMM26, X86::YMM27, X86::YMM28, X86::YMM29, X86::YMM30, X86::YMM31, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15 };
2591 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::VR256XRegClassID];
2592 const ArrayRef<MCPhysReg> Order[] = {
2593 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2594 ArrayRef(AltOrder1)
2595 };
2596 const unsigned Select = VR256XAltOrderSelect(MF, Rev);
2597 assert(Select < 2);
2598 return Order[Select];
2599}
2600namespace X86 {
2601
2602// Register class instances.
2603 extern const TargetRegisterClass GR8RegClass = {
2604 .MC: &X86MCRegisterClasses[GR8RegClassID],
2605 .SubClassMask: GR8SubClassMask,
2606 .SuperRegIndices: SuperRegIdxSeqs + 2,
2607 .LaneMask: LaneBitmask(0x0000000000000001),
2608 .AllocationPriority: 0,
2609 .GlobalPriority: false,
2610 .TSFlags: 0x00, /* TSFlags */
2611 .SpillStackID: 0, /* SpillStackID */
2612 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2613 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2614 .SuperClasses: nullptr, .SuperClassesSize: 0,
2615 .OrderFunc: GR8GetRawAllocationOrder
2616 };
2617
2618 extern const TargetRegisterClass GRH8RegClass = {
2619 .MC: &X86MCRegisterClasses[GRH8RegClassID],
2620 .SubClassMask: GRH8SubClassMask,
2621 .SuperRegIndices: SuperRegIdxSeqs + 1,
2622 .LaneMask: LaneBitmask(0x0000000000000001),
2623 .AllocationPriority: 0,
2624 .GlobalPriority: false,
2625 .TSFlags: 0x00, /* TSFlags */
2626 .SpillStackID: 0, /* SpillStackID */
2627 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2628 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2629 .SuperClasses: nullptr, .SuperClassesSize: 0,
2630 .OrderFunc: nullptr
2631 };
2632
2633 extern const TargetRegisterClass GR8_NOREX2RegClass = {
2634 .MC: &X86MCRegisterClasses[GR8_NOREX2RegClassID],
2635 .SubClassMask: GR8_NOREX2SubClassMask,
2636 .SuperRegIndices: SuperRegIdxSeqs + 2,
2637 .LaneMask: LaneBitmask(0x0000000000000001),
2638 .AllocationPriority: 0,
2639 .GlobalPriority: false,
2640 .TSFlags: 0x00, /* TSFlags */
2641 .SpillStackID: 0, /* SpillStackID */
2642 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2643 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2644 .SuperClasses: GR8_NOREX2Superclasses, .SuperClassesSize: 1,
2645 .OrderFunc: GR8_NOREX2GetRawAllocationOrder
2646 };
2647
2648 extern const TargetRegisterClass GR8_NOREXRegClass = {
2649 .MC: &X86MCRegisterClasses[GR8_NOREXRegClassID],
2650 .SubClassMask: GR8_NOREXSubClassMask,
2651 .SuperRegIndices: SuperRegIdxSeqs + 2,
2652 .LaneMask: LaneBitmask(0x0000000000000001),
2653 .AllocationPriority: 0,
2654 .GlobalPriority: false,
2655 .TSFlags: 0x00, /* TSFlags */
2656 .SpillStackID: 0, /* SpillStackID */
2657 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2658 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2659 .SuperClasses: GR8_NOREXSuperclasses, .SuperClassesSize: 2,
2660 .OrderFunc: GR8_NOREXGetRawAllocationOrder
2661 };
2662
2663 extern const TargetRegisterClass GR8_ABCD_HRegClass = {
2664 .MC: &X86MCRegisterClasses[GR8_ABCD_HRegClassID],
2665 .SubClassMask: GR8_ABCD_HSubClassMask,
2666 .SuperRegIndices: SuperRegIdxSeqs + 3,
2667 .LaneMask: LaneBitmask(0x0000000000000001),
2668 .AllocationPriority: 0,
2669 .GlobalPriority: false,
2670 .TSFlags: 0x00, /* TSFlags */
2671 .SpillStackID: 0, /* SpillStackID */
2672 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2673 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2674 .SuperClasses: GR8_ABCD_HSuperclasses, .SuperClassesSize: 3,
2675 .OrderFunc: nullptr
2676 };
2677
2678 extern const TargetRegisterClass GR8_ABCD_LRegClass = {
2679 .MC: &X86MCRegisterClasses[GR8_ABCD_LRegClassID],
2680 .SubClassMask: GR8_ABCD_LSubClassMask,
2681 .SuperRegIndices: SuperRegIdxSeqs + 0,
2682 .LaneMask: LaneBitmask(0x0000000000000001),
2683 .AllocationPriority: 0,
2684 .GlobalPriority: false,
2685 .TSFlags: 0x00, /* TSFlags */
2686 .SpillStackID: 0, /* SpillStackID */
2687 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2688 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2689 .SuperClasses: GR8_ABCD_LSuperclasses, .SuperClassesSize: 3,
2690 .OrderFunc: nullptr
2691 };
2692
2693 extern const TargetRegisterClass GRH16RegClass = {
2694 .MC: &X86MCRegisterClasses[GRH16RegClassID],
2695 .SubClassMask: GRH16SubClassMask,
2696 .SuperRegIndices: SuperRegIdxSeqs + 1,
2697 .LaneMask: LaneBitmask(0x0000000000000001),
2698 .AllocationPriority: 0,
2699 .GlobalPriority: false,
2700 .TSFlags: 0x00, /* TSFlags */
2701 .SpillStackID: 0, /* SpillStackID */
2702 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2703 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2704 .SuperClasses: nullptr, .SuperClassesSize: 0,
2705 .OrderFunc: nullptr
2706 };
2707
2708 extern const TargetRegisterClass GR16RegClass = {
2709 .MC: &X86MCRegisterClasses[GR16RegClassID],
2710 .SubClassMask: GR16SubClassMask,
2711 .SuperRegIndices: SuperRegIdxSeqs + 5,
2712 .LaneMask: LaneBitmask(0x0000000000000003),
2713 .AllocationPriority: 0,
2714 .GlobalPriority: false,
2715 .TSFlags: 0x00, /* TSFlags */
2716 .SpillStackID: 0, /* SpillStackID */
2717 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2718 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2719 .SuperClasses: nullptr, .SuperClassesSize: 0,
2720 .OrderFunc: nullptr
2721 };
2722
2723 extern const TargetRegisterClass GR16_NOREX2RegClass = {
2724 .MC: &X86MCRegisterClasses[GR16_NOREX2RegClassID],
2725 .SubClassMask: GR16_NOREX2SubClassMask,
2726 .SuperRegIndices: SuperRegIdxSeqs + 5,
2727 .LaneMask: LaneBitmask(0x0000000000000003),
2728 .AllocationPriority: 0,
2729 .GlobalPriority: false,
2730 .TSFlags: 0x00, /* TSFlags */
2731 .SpillStackID: 0, /* SpillStackID */
2732 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2733 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2734 .SuperClasses: GR16_NOREX2Superclasses, .SuperClassesSize: 1,
2735 .OrderFunc: nullptr
2736 };
2737
2738 extern const TargetRegisterClass GR16_NOREXRegClass = {
2739 .MC: &X86MCRegisterClasses[GR16_NOREXRegClassID],
2740 .SubClassMask: GR16_NOREXSubClassMask,
2741 .SuperRegIndices: SuperRegIdxSeqs + 5,
2742 .LaneMask: LaneBitmask(0x0000000000000003),
2743 .AllocationPriority: 0,
2744 .GlobalPriority: false,
2745 .TSFlags: 0x00, /* TSFlags */
2746 .SpillStackID: 0, /* SpillStackID */
2747 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2748 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2749 .SuperClasses: GR16_NOREXSuperclasses, .SuperClassesSize: 2,
2750 .OrderFunc: nullptr
2751 };
2752
2753 extern const TargetRegisterClass VK1RegClass = {
2754 .MC: &X86MCRegisterClasses[VK1RegClassID],
2755 .SubClassMask: VK1SubClassMask,
2756 .SuperRegIndices: SuperRegIdxSeqs + 9,
2757 .LaneMask: LaneBitmask(0x0000000000000001),
2758 .AllocationPriority: 0,
2759 .GlobalPriority: false,
2760 .TSFlags: 0x00, /* TSFlags */
2761 .SpillStackID: 0, /* SpillStackID */
2762 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2763 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2764 .SuperClasses: VK1Superclasses, .SuperClassesSize: 4,
2765 .OrderFunc: nullptr
2766 };
2767
2768 extern const TargetRegisterClass VK16RegClass = {
2769 .MC: &X86MCRegisterClasses[VK16RegClassID],
2770 .SubClassMask: VK16SubClassMask,
2771 .SuperRegIndices: SuperRegIdxSeqs + 9,
2772 .LaneMask: LaneBitmask(0x0000000000000001),
2773 .AllocationPriority: 0,
2774 .GlobalPriority: false,
2775 .TSFlags: 0x00, /* TSFlags */
2776 .SpillStackID: 0, /* SpillStackID */
2777 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2778 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2779 .SuperClasses: VK16Superclasses, .SuperClassesSize: 4,
2780 .OrderFunc: nullptr
2781 };
2782
2783 extern const TargetRegisterClass VK2RegClass = {
2784 .MC: &X86MCRegisterClasses[VK2RegClassID],
2785 .SubClassMask: VK2SubClassMask,
2786 .SuperRegIndices: SuperRegIdxSeqs + 9,
2787 .LaneMask: LaneBitmask(0x0000000000000001),
2788 .AllocationPriority: 0,
2789 .GlobalPriority: false,
2790 .TSFlags: 0x00, /* TSFlags */
2791 .SpillStackID: 0, /* SpillStackID */
2792 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2793 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2794 .SuperClasses: VK2Superclasses, .SuperClassesSize: 4,
2795 .OrderFunc: nullptr
2796 };
2797
2798 extern const TargetRegisterClass VK4RegClass = {
2799 .MC: &X86MCRegisterClasses[VK4RegClassID],
2800 .SubClassMask: VK4SubClassMask,
2801 .SuperRegIndices: SuperRegIdxSeqs + 9,
2802 .LaneMask: LaneBitmask(0x0000000000000001),
2803 .AllocationPriority: 0,
2804 .GlobalPriority: false,
2805 .TSFlags: 0x00, /* TSFlags */
2806 .SpillStackID: 0, /* SpillStackID */
2807 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2808 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2809 .SuperClasses: VK4Superclasses, .SuperClassesSize: 4,
2810 .OrderFunc: nullptr
2811 };
2812
2813 extern const TargetRegisterClass VK8RegClass = {
2814 .MC: &X86MCRegisterClasses[VK8RegClassID],
2815 .SubClassMask: VK8SubClassMask,
2816 .SuperRegIndices: SuperRegIdxSeqs + 9,
2817 .LaneMask: LaneBitmask(0x0000000000000001),
2818 .AllocationPriority: 0,
2819 .GlobalPriority: false,
2820 .TSFlags: 0x00, /* TSFlags */
2821 .SpillStackID: 0, /* SpillStackID */
2822 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2823 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2824 .SuperClasses: VK8Superclasses, .SuperClassesSize: 4,
2825 .OrderFunc: nullptr
2826 };
2827
2828 extern const TargetRegisterClass VK16WMRegClass = {
2829 .MC: &X86MCRegisterClasses[VK16WMRegClassID],
2830 .SubClassMask: VK16WMSubClassMask,
2831 .SuperRegIndices: SuperRegIdxSeqs + 9,
2832 .LaneMask: LaneBitmask(0x0000000000000001),
2833 .AllocationPriority: 0,
2834 .GlobalPriority: false,
2835 .TSFlags: 0x00, /* TSFlags */
2836 .SpillStackID: 0, /* SpillStackID */
2837 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2838 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2839 .SuperClasses: VK16WMSuperclasses, .SuperClassesSize: 9,
2840 .OrderFunc: nullptr
2841 };
2842
2843 extern const TargetRegisterClass VK1WMRegClass = {
2844 .MC: &X86MCRegisterClasses[VK1WMRegClassID],
2845 .SubClassMask: VK1WMSubClassMask,
2846 .SuperRegIndices: SuperRegIdxSeqs + 9,
2847 .LaneMask: LaneBitmask(0x0000000000000001),
2848 .AllocationPriority: 0,
2849 .GlobalPriority: false,
2850 .TSFlags: 0x00, /* TSFlags */
2851 .SpillStackID: 0, /* SpillStackID */
2852 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2853 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2854 .SuperClasses: VK1WMSuperclasses, .SuperClassesSize: 9,
2855 .OrderFunc: nullptr
2856 };
2857
2858 extern const TargetRegisterClass VK2WMRegClass = {
2859 .MC: &X86MCRegisterClasses[VK2WMRegClassID],
2860 .SubClassMask: VK2WMSubClassMask,
2861 .SuperRegIndices: SuperRegIdxSeqs + 9,
2862 .LaneMask: LaneBitmask(0x0000000000000001),
2863 .AllocationPriority: 0,
2864 .GlobalPriority: false,
2865 .TSFlags: 0x00, /* TSFlags */
2866 .SpillStackID: 0, /* SpillStackID */
2867 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2868 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2869 .SuperClasses: VK2WMSuperclasses, .SuperClassesSize: 9,
2870 .OrderFunc: nullptr
2871 };
2872
2873 extern const TargetRegisterClass VK4WMRegClass = {
2874 .MC: &X86MCRegisterClasses[VK4WMRegClassID],
2875 .SubClassMask: VK4WMSubClassMask,
2876 .SuperRegIndices: SuperRegIdxSeqs + 9,
2877 .LaneMask: LaneBitmask(0x0000000000000001),
2878 .AllocationPriority: 0,
2879 .GlobalPriority: false,
2880 .TSFlags: 0x00, /* TSFlags */
2881 .SpillStackID: 0, /* SpillStackID */
2882 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2883 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2884 .SuperClasses: VK4WMSuperclasses, .SuperClassesSize: 9,
2885 .OrderFunc: nullptr
2886 };
2887
2888 extern const TargetRegisterClass VK8WMRegClass = {
2889 .MC: &X86MCRegisterClasses[VK8WMRegClassID],
2890 .SubClassMask: VK8WMSubClassMask,
2891 .SuperRegIndices: SuperRegIdxSeqs + 9,
2892 .LaneMask: LaneBitmask(0x0000000000000001),
2893 .AllocationPriority: 0,
2894 .GlobalPriority: false,
2895 .TSFlags: 0x00, /* TSFlags */
2896 .SpillStackID: 0, /* SpillStackID */
2897 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2898 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2899 .SuperClasses: VK8WMSuperclasses, .SuperClassesSize: 9,
2900 .OrderFunc: nullptr
2901 };
2902
2903 extern const TargetRegisterClass SEGMENT_REGRegClass = {
2904 .MC: &X86MCRegisterClasses[SEGMENT_REGRegClassID],
2905 .SubClassMask: SEGMENT_REGSubClassMask,
2906 .SuperRegIndices: SuperRegIdxSeqs + 1,
2907 .LaneMask: LaneBitmask(0x0000000000000001),
2908 .AllocationPriority: 0,
2909 .GlobalPriority: false,
2910 .TSFlags: 0x00, /* TSFlags */
2911 .SpillStackID: 0, /* SpillStackID */
2912 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2913 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2914 .SuperClasses: nullptr, .SuperClassesSize: 0,
2915 .OrderFunc: nullptr
2916 };
2917
2918 extern const TargetRegisterClass GR16_ABCDRegClass = {
2919 .MC: &X86MCRegisterClasses[GR16_ABCDRegClassID],
2920 .SubClassMask: GR16_ABCDSubClassMask,
2921 .SuperRegIndices: SuperRegIdxSeqs + 5,
2922 .LaneMask: LaneBitmask(0x0000000000000003),
2923 .AllocationPriority: 0,
2924 .GlobalPriority: false,
2925 .TSFlags: 0x00, /* TSFlags */
2926 .SpillStackID: 0, /* SpillStackID */
2927 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2928 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2929 .SuperClasses: GR16_ABCDSuperclasses, .SuperClassesSize: 3,
2930 .OrderFunc: nullptr
2931 };
2932
2933 extern const TargetRegisterClass FPCCRRegClass = {
2934 .MC: &X86MCRegisterClasses[FPCCRRegClassID],
2935 .SubClassMask: FPCCRSubClassMask,
2936 .SuperRegIndices: SuperRegIdxSeqs + 1,
2937 .LaneMask: LaneBitmask(0x0000000000000001),
2938 .AllocationPriority: 0,
2939 .GlobalPriority: false,
2940 .TSFlags: 0x00, /* TSFlags */
2941 .SpillStackID: 0, /* SpillStackID */
2942 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2943 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2944 .SuperClasses: nullptr, .SuperClassesSize: 0,
2945 .OrderFunc: nullptr
2946 };
2947
2948 extern const TargetRegisterClass FR16XRegClass = {
2949 .MC: &X86MCRegisterClasses[FR16XRegClassID],
2950 .SubClassMask: FR16XSubClassMask,
2951 .SuperRegIndices: SuperRegIdxSeqs + 12,
2952 .LaneMask: LaneBitmask(0x0000000000000001),
2953 .AllocationPriority: 0,
2954 .GlobalPriority: false,
2955 .TSFlags: 0x00, /* TSFlags */
2956 .SpillStackID: 0, /* SpillStackID */
2957 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2958 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2959 .SuperClasses: nullptr, .SuperClassesSize: 0,
2960 .OrderFunc: nullptr
2961 };
2962
2963 extern const TargetRegisterClass FR16RegClass = {
2964 .MC: &X86MCRegisterClasses[FR16RegClassID],
2965 .SubClassMask: FR16SubClassMask,
2966 .SuperRegIndices: SuperRegIdxSeqs + 12,
2967 .LaneMask: LaneBitmask(0x0000000000000001),
2968 .AllocationPriority: 0,
2969 .GlobalPriority: false,
2970 .TSFlags: 0x00, /* TSFlags */
2971 .SpillStackID: 0, /* SpillStackID */
2972 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2973 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2974 .SuperClasses: FR16Superclasses, .SuperClassesSize: 1,
2975 .OrderFunc: nullptr
2976 };
2977
2978 extern const TargetRegisterClass VK16PAIRRegClass = {
2979 .MC: &X86MCRegisterClasses[VK16PAIRRegClassID],
2980 .SubClassMask: VK16PAIRSubClassMask,
2981 .SuperRegIndices: SuperRegIdxSeqs + 1,
2982 .LaneMask: LaneBitmask(0x0000000000000030),
2983 .AllocationPriority: 0,
2984 .GlobalPriority: false,
2985 .TSFlags: 0x00, /* TSFlags */
2986 .SpillStackID: 0, /* SpillStackID */
2987 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2988 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2989 .SuperClasses: VK16PAIRSuperclasses, .SuperClassesSize: 4,
2990 .OrderFunc: nullptr
2991 };
2992
2993 extern const TargetRegisterClass VK1PAIRRegClass = {
2994 .MC: &X86MCRegisterClasses[VK1PAIRRegClassID],
2995 .SubClassMask: VK1PAIRSubClassMask,
2996 .SuperRegIndices: SuperRegIdxSeqs + 1,
2997 .LaneMask: LaneBitmask(0x0000000000000030),
2998 .AllocationPriority: 0,
2999 .GlobalPriority: false,
3000 .TSFlags: 0x00, /* TSFlags */
3001 .SpillStackID: 0, /* SpillStackID */
3002 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3003 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3004 .SuperClasses: VK1PAIRSuperclasses, .SuperClassesSize: 4,
3005 .OrderFunc: nullptr
3006 };
3007
3008 extern const TargetRegisterClass VK2PAIRRegClass = {
3009 .MC: &X86MCRegisterClasses[VK2PAIRRegClassID],
3010 .SubClassMask: VK2PAIRSubClassMask,
3011 .SuperRegIndices: SuperRegIdxSeqs + 1,
3012 .LaneMask: LaneBitmask(0x0000000000000030),
3013 .AllocationPriority: 0,
3014 .GlobalPriority: false,
3015 .TSFlags: 0x00, /* TSFlags */
3016 .SpillStackID: 0, /* SpillStackID */
3017 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3018 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3019 .SuperClasses: VK2PAIRSuperclasses, .SuperClassesSize: 4,
3020 .OrderFunc: nullptr
3021 };
3022
3023 extern const TargetRegisterClass VK4PAIRRegClass = {
3024 .MC: &X86MCRegisterClasses[VK4PAIRRegClassID],
3025 .SubClassMask: VK4PAIRSubClassMask,
3026 .SuperRegIndices: SuperRegIdxSeqs + 1,
3027 .LaneMask: LaneBitmask(0x0000000000000030),
3028 .AllocationPriority: 0,
3029 .GlobalPriority: false,
3030 .TSFlags: 0x00, /* TSFlags */
3031 .SpillStackID: 0, /* SpillStackID */
3032 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3033 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3034 .SuperClasses: VK4PAIRSuperclasses, .SuperClassesSize: 4,
3035 .OrderFunc: nullptr
3036 };
3037
3038 extern const TargetRegisterClass VK8PAIRRegClass = {
3039 .MC: &X86MCRegisterClasses[VK8PAIRRegClassID],
3040 .SubClassMask: VK8PAIRSubClassMask,
3041 .SuperRegIndices: SuperRegIdxSeqs + 1,
3042 .LaneMask: LaneBitmask(0x0000000000000030),
3043 .AllocationPriority: 0,
3044 .GlobalPriority: false,
3045 .TSFlags: 0x00, /* TSFlags */
3046 .SpillStackID: 0, /* SpillStackID */
3047 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3048 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3049 .SuperClasses: VK8PAIRSuperclasses, .SuperClassesSize: 4,
3050 .OrderFunc: nullptr
3051 };
3052
3053 extern const TargetRegisterClass VK1PAIR_with_sub_mask_0_in_VK1WMRegClass = {
3054 .MC: &X86MCRegisterClasses[VK1PAIR_with_sub_mask_0_in_VK1WMRegClassID],
3055 .SubClassMask: VK1PAIR_with_sub_mask_0_in_VK1WMSubClassMask,
3056 .SuperRegIndices: SuperRegIdxSeqs + 1,
3057 .LaneMask: LaneBitmask(0x0000000000000030),
3058 .AllocationPriority: 0,
3059 .GlobalPriority: false,
3060 .TSFlags: 0x00, /* TSFlags */
3061 .SpillStackID: 0, /* SpillStackID */
3062 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3063 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3064 .SuperClasses: VK1PAIR_with_sub_mask_0_in_VK1WMSuperclasses, .SuperClassesSize: 5,
3065 .OrderFunc: nullptr
3066 };
3067
3068 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass = {
3069 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBPRegClassID],
3070 .SubClassMask: LOW32_ADDR_ACCESS_RBPSubClassMask,
3071 .SuperRegIndices: SuperRegIdxSeqs + 7,
3072 .LaneMask: LaneBitmask(0x000000000000000F),
3073 .AllocationPriority: 0,
3074 .GlobalPriority: false,
3075 .TSFlags: 0x00, /* TSFlags */
3076 .SpillStackID: 0, /* SpillStackID */
3077 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3078 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3079 .SuperClasses: nullptr, .SuperClassesSize: 0,
3080 .OrderFunc: nullptr
3081 };
3082
3083 extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass = {
3084 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESSRegClassID],
3085 .SubClassMask: LOW32_ADDR_ACCESSSubClassMask,
3086 .SuperRegIndices: SuperRegIdxSeqs + 7,
3087 .LaneMask: LaneBitmask(0x000000000000000F),
3088 .AllocationPriority: 0,
3089 .GlobalPriority: false,
3090 .TSFlags: 0x00, /* TSFlags */
3091 .SpillStackID: 0, /* SpillStackID */
3092 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3093 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3094 .SuperClasses: LOW32_ADDR_ACCESSSuperclasses, .SuperClassesSize: 1,
3095 .OrderFunc: nullptr
3096 };
3097
3098 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass = {
3099 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID],
3100 .SubClassMask: LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask,
3101 .SuperRegIndices: SuperRegIdxSeqs + 7,
3102 .LaneMask: LaneBitmask(0x000000000000000F),
3103 .AllocationPriority: 0,
3104 .GlobalPriority: false,
3105 .TSFlags: 0x00, /* TSFlags */
3106 .SpillStackID: 0, /* SpillStackID */
3107 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3108 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3109 .SuperClasses: LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses, .SuperClassesSize: 1,
3110 .OrderFunc: nullptr
3111 };
3112
3113 extern const TargetRegisterClass FR32XRegClass = {
3114 .MC: &X86MCRegisterClasses[FR32XRegClassID],
3115 .SubClassMask: FR32XSubClassMask,
3116 .SuperRegIndices: SuperRegIdxSeqs + 12,
3117 .LaneMask: LaneBitmask(0x0000000000000001),
3118 .AllocationPriority: 0,
3119 .GlobalPriority: false,
3120 .TSFlags: 0x00, /* TSFlags */
3121 .SpillStackID: 0, /* SpillStackID */
3122 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3123 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3124 .SuperClasses: FR32XSuperclasses, .SuperClassesSize: 1,
3125 .OrderFunc: FR32XGetRawAllocationOrder
3126 };
3127
3128 extern const TargetRegisterClass GR32RegClass = {
3129 .MC: &X86MCRegisterClasses[GR32RegClassID],
3130 .SubClassMask: GR32SubClassMask,
3131 .SuperRegIndices: SuperRegIdxSeqs + 7,
3132 .LaneMask: LaneBitmask(0x000000000000000F),
3133 .AllocationPriority: 0,
3134 .GlobalPriority: false,
3135 .TSFlags: 0x00, /* TSFlags */
3136 .SpillStackID: 0, /* SpillStackID */
3137 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3138 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3139 .SuperClasses: GR32Superclasses, .SuperClassesSize: 3,
3140 .OrderFunc: nullptr
3141 };
3142
3143 extern const TargetRegisterClass GR32_NOSPRegClass = {
3144 .MC: &X86MCRegisterClasses[GR32_NOSPRegClassID],
3145 .SubClassMask: GR32_NOSPSubClassMask,
3146 .SuperRegIndices: SuperRegIdxSeqs + 7,
3147 .LaneMask: LaneBitmask(0x000000000000000F),
3148 .AllocationPriority: 0,
3149 .GlobalPriority: false,
3150 .TSFlags: 0x00, /* TSFlags */
3151 .SpillStackID: 0, /* SpillStackID */
3152 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3153 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3154 .SuperClasses: GR32_NOSPSuperclasses, .SuperClassesSize: 4,
3155 .OrderFunc: nullptr
3156 };
3157
3158 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass = {
3159 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID],
3160 .SubClassMask: LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2SubClassMask,
3161 .SuperRegIndices: SuperRegIdxSeqs + 7,
3162 .LaneMask: LaneBitmask(0x000000000000000F),
3163 .AllocationPriority: 0,
3164 .GlobalPriority: false,
3165 .TSFlags: 0x00, /* TSFlags */
3166 .SpillStackID: 0, /* SpillStackID */
3167 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3168 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3169 .SuperClasses: LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Superclasses, .SuperClassesSize: 2,
3170 .OrderFunc: nullptr
3171 };
3172
3173 extern const TargetRegisterClass DEBUG_REGRegClass = {
3174 .MC: &X86MCRegisterClasses[DEBUG_REGRegClassID],
3175 .SubClassMask: DEBUG_REGSubClassMask,
3176 .SuperRegIndices: SuperRegIdxSeqs + 1,
3177 .LaneMask: LaneBitmask(0x0000000000000001),
3178 .AllocationPriority: 0,
3179 .GlobalPriority: false,
3180 .TSFlags: 0x00, /* TSFlags */
3181 .SpillStackID: 0, /* SpillStackID */
3182 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3183 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3184 .SuperClasses: nullptr, .SuperClassesSize: 0,
3185 .OrderFunc: nullptr
3186 };
3187
3188 extern const TargetRegisterClass FR32RegClass = {
3189 .MC: &X86MCRegisterClasses[FR32RegClassID],
3190 .SubClassMask: FR32SubClassMask,
3191 .SuperRegIndices: SuperRegIdxSeqs + 12,
3192 .LaneMask: LaneBitmask(0x0000000000000001),
3193 .AllocationPriority: 0,
3194 .GlobalPriority: false,
3195 .TSFlags: 0x00, /* TSFlags */
3196 .SpillStackID: 0, /* SpillStackID */
3197 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3198 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3199 .SuperClasses: FR32Superclasses, .SuperClassesSize: 3,
3200 .OrderFunc: nullptr
3201 };
3202
3203 extern const TargetRegisterClass GR32_NOREX2RegClass = {
3204 .MC: &X86MCRegisterClasses[GR32_NOREX2RegClassID],
3205 .SubClassMask: GR32_NOREX2SubClassMask,
3206 .SuperRegIndices: SuperRegIdxSeqs + 7,
3207 .LaneMask: LaneBitmask(0x000000000000000F),
3208 .AllocationPriority: 0,
3209 .GlobalPriority: false,
3210 .TSFlags: 0x00, /* TSFlags */
3211 .SpillStackID: 0, /* SpillStackID */
3212 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3213 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3214 .SuperClasses: GR32_NOREX2Superclasses, .SuperClassesSize: 5,
3215 .OrderFunc: nullptr
3216 };
3217
3218 extern const TargetRegisterClass GR32_NOREX2_NOSPRegClass = {
3219 .MC: &X86MCRegisterClasses[GR32_NOREX2_NOSPRegClassID],
3220 .SubClassMask: GR32_NOREX2_NOSPSubClassMask,
3221 .SuperRegIndices: SuperRegIdxSeqs + 7,
3222 .LaneMask: LaneBitmask(0x000000000000000F),
3223 .AllocationPriority: 0,
3224 .GlobalPriority: false,
3225 .TSFlags: 0x00, /* TSFlags */
3226 .SpillStackID: 0, /* SpillStackID */
3227 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3228 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3229 .SuperClasses: GR32_NOREX2_NOSPSuperclasses, .SuperClassesSize: 7,
3230 .OrderFunc: nullptr
3231 };
3232
3233 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass = {
3234 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID],
3235 .SubClassMask: LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask,
3236 .SuperRegIndices: SuperRegIdxSeqs + 7,
3237 .LaneMask: LaneBitmask(0x000000000000000F),
3238 .AllocationPriority: 0,
3239 .GlobalPriority: false,
3240 .TSFlags: 0x00, /* TSFlags */
3241 .SpillStackID: 0, /* SpillStackID */
3242 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3243 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3244 .SuperClasses: LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses, .SuperClassesSize: 3,
3245 .OrderFunc: nullptr
3246 };
3247
3248 extern const TargetRegisterClass GR32_NOREXRegClass = {
3249 .MC: &X86MCRegisterClasses[GR32_NOREXRegClassID],
3250 .SubClassMask: GR32_NOREXSubClassMask,
3251 .SuperRegIndices: SuperRegIdxSeqs + 7,
3252 .LaneMask: LaneBitmask(0x000000000000000F),
3253 .AllocationPriority: 0,
3254 .GlobalPriority: false,
3255 .TSFlags: 0x00, /* TSFlags */
3256 .SpillStackID: 0, /* SpillStackID */
3257 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3258 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3259 .SuperClasses: GR32_NOREXSuperclasses, .SuperClassesSize: 7,
3260 .OrderFunc: nullptr
3261 };
3262
3263 extern const TargetRegisterClass VK32RegClass = {
3264 .MC: &X86MCRegisterClasses[VK32RegClassID],
3265 .SubClassMask: VK32SubClassMask,
3266 .SuperRegIndices: SuperRegIdxSeqs + 9,
3267 .LaneMask: LaneBitmask(0x0000000000000001),
3268 .AllocationPriority: 0,
3269 .GlobalPriority: false,
3270 .TSFlags: 0x00, /* TSFlags */
3271 .SpillStackID: 0, /* SpillStackID */
3272 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3273 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3274 .SuperClasses: VK32Superclasses, .SuperClassesSize: 5,
3275 .OrderFunc: nullptr
3276 };
3277
3278 extern const TargetRegisterClass GR32_NOREX_NOSPRegClass = {
3279 .MC: &X86MCRegisterClasses[GR32_NOREX_NOSPRegClassID],
3280 .SubClassMask: GR32_NOREX_NOSPSubClassMask,
3281 .SuperRegIndices: SuperRegIdxSeqs + 7,
3282 .LaneMask: LaneBitmask(0x000000000000000F),
3283 .AllocationPriority: 0,
3284 .GlobalPriority: false,
3285 .TSFlags: 0x00, /* TSFlags */
3286 .SpillStackID: 0, /* SpillStackID */
3287 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3288 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3289 .SuperClasses: GR32_NOREX_NOSPSuperclasses, .SuperClassesSize: 10,
3290 .OrderFunc: nullptr
3291 };
3292
3293 extern const TargetRegisterClass RFP32RegClass = {
3294 .MC: &X86MCRegisterClasses[RFP32RegClassID],
3295 .SubClassMask: RFP32SubClassMask,
3296 .SuperRegIndices: SuperRegIdxSeqs + 1,
3297 .LaneMask: LaneBitmask(0x0000000000000001),
3298 .AllocationPriority: 0,
3299 .GlobalPriority: false,
3300 .TSFlags: 0x00, /* TSFlags */
3301 .SpillStackID: 0, /* SpillStackID */
3302 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3303 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3304 .SuperClasses: nullptr, .SuperClassesSize: 0,
3305 .OrderFunc: nullptr
3306 };
3307
3308 extern const TargetRegisterClass VK32WMRegClass = {
3309 .MC: &X86MCRegisterClasses[VK32WMRegClassID],
3310 .SubClassMask: VK32WMSubClassMask,
3311 .SuperRegIndices: SuperRegIdxSeqs + 9,
3312 .LaneMask: LaneBitmask(0x0000000000000001),
3313 .AllocationPriority: 0,
3314 .GlobalPriority: false,
3315 .TSFlags: 0x00, /* TSFlags */
3316 .SpillStackID: 0, /* SpillStackID */
3317 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3318 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3319 .SuperClasses: VK32WMSuperclasses, .SuperClassesSize: 11,
3320 .OrderFunc: nullptr
3321 };
3322
3323 extern const TargetRegisterClass GR32_ABCDRegClass = {
3324 .MC: &X86MCRegisterClasses[GR32_ABCDRegClassID],
3325 .SubClassMask: GR32_ABCDSubClassMask,
3326 .SuperRegIndices: SuperRegIdxSeqs + 7,
3327 .LaneMask: LaneBitmask(0x000000000000000F),
3328 .AllocationPriority: 0,
3329 .GlobalPriority: false,
3330 .TSFlags: 0x00, /* TSFlags */
3331 .SpillStackID: 0, /* SpillStackID */
3332 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3333 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3334 .SuperClasses: GR32_ABCDSuperclasses, .SuperClassesSize: 11,
3335 .OrderFunc: nullptr
3336 };
3337
3338 extern const TargetRegisterClass GR32_TCRegClass = {
3339 .MC: &X86MCRegisterClasses[GR32_TCRegClassID],
3340 .SubClassMask: GR32_TCSubClassMask,
3341 .SuperRegIndices: SuperRegIdxSeqs + 7,
3342 .LaneMask: LaneBitmask(0x000000000000000F),
3343 .AllocationPriority: 0,
3344 .GlobalPriority: false,
3345 .TSFlags: 0x00, /* TSFlags */
3346 .SpillStackID: 0, /* SpillStackID */
3347 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3348 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3349 .SuperClasses: GR32_TCSuperclasses, .SuperClassesSize: 8,
3350 .OrderFunc: nullptr
3351 };
3352
3353 extern const TargetRegisterClass GR32_ABCD_and_GR32_TCRegClass = {
3354 .MC: &X86MCRegisterClasses[GR32_ABCD_and_GR32_TCRegClassID],
3355 .SubClassMask: GR32_ABCD_and_GR32_TCSubClassMask,
3356 .SuperRegIndices: SuperRegIdxSeqs + 7,
3357 .LaneMask: LaneBitmask(0x000000000000000F),
3358 .AllocationPriority: 0,
3359 .GlobalPriority: false,
3360 .TSFlags: 0x00, /* TSFlags */
3361 .SpillStackID: 0, /* SpillStackID */
3362 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3363 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3364 .SuperClasses: GR32_ABCD_and_GR32_TCSuperclasses, .SuperClassesSize: 13,
3365 .OrderFunc: nullptr
3366 };
3367
3368 extern const TargetRegisterClass GR32_ADRegClass = {
3369 .MC: &X86MCRegisterClasses[GR32_ADRegClassID],
3370 .SubClassMask: GR32_ADSubClassMask,
3371 .SuperRegIndices: SuperRegIdxSeqs + 7,
3372 .LaneMask: LaneBitmask(0x000000000000000F),
3373 .AllocationPriority: 0,
3374 .GlobalPriority: false,
3375 .TSFlags: 0x00, /* TSFlags */
3376 .SpillStackID: 0, /* SpillStackID */
3377 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3378 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3379 .SuperClasses: GR32_ADSuperclasses, .SuperClassesSize: 14,
3380 .OrderFunc: nullptr
3381 };
3382
3383 extern const TargetRegisterClass GR32_ArgRefRegClass = {
3384 .MC: &X86MCRegisterClasses[GR32_ArgRefRegClassID],
3385 .SubClassMask: GR32_ArgRefSubClassMask,
3386 .SuperRegIndices: SuperRegIdxSeqs + 7,
3387 .LaneMask: LaneBitmask(0x000000000000000F),
3388 .AllocationPriority: 0,
3389 .GlobalPriority: false,
3390 .TSFlags: 0x00, /* TSFlags */
3391 .SpillStackID: 0, /* SpillStackID */
3392 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3393 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3394 .SuperClasses: GR32_ArgRefSuperclasses, .SuperClassesSize: 14,
3395 .OrderFunc: nullptr
3396 };
3397
3398 extern const TargetRegisterClass GR32_BPSPRegClass = {
3399 .MC: &X86MCRegisterClasses[GR32_BPSPRegClassID],
3400 .SubClassMask: GR32_BPSPSubClassMask,
3401 .SuperRegIndices: SuperRegIdxSeqs + 7,
3402 .LaneMask: LaneBitmask(0x000000000000000F),
3403 .AllocationPriority: 0,
3404 .GlobalPriority: false,
3405 .TSFlags: 0x00, /* TSFlags */
3406 .SpillStackID: 0, /* SpillStackID */
3407 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3408 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3409 .SuperClasses: GR32_BPSPSuperclasses, .SuperClassesSize: 8,
3410 .OrderFunc: nullptr
3411 };
3412
3413 extern const TargetRegisterClass GR32_BSIRegClass = {
3414 .MC: &X86MCRegisterClasses[GR32_BSIRegClassID],
3415 .SubClassMask: GR32_BSISubClassMask,
3416 .SuperRegIndices: SuperRegIdxSeqs + 7,
3417 .LaneMask: LaneBitmask(0x000000000000000F),
3418 .AllocationPriority: 0,
3419 .GlobalPriority: false,
3420 .TSFlags: 0x00, /* TSFlags */
3421 .SpillStackID: 0, /* SpillStackID */
3422 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3423 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3424 .SuperClasses: GR32_BSISuperclasses, .SuperClassesSize: 11,
3425 .OrderFunc: nullptr
3426 };
3427
3428 extern const TargetRegisterClass GR32_CBRegClass = {
3429 .MC: &X86MCRegisterClasses[GR32_CBRegClassID],
3430 .SubClassMask: GR32_CBSubClassMask,
3431 .SuperRegIndices: SuperRegIdxSeqs + 7,
3432 .LaneMask: LaneBitmask(0x000000000000000F),
3433 .AllocationPriority: 0,
3434 .GlobalPriority: false,
3435 .TSFlags: 0x00, /* TSFlags */
3436 .SpillStackID: 0, /* SpillStackID */
3437 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3438 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3439 .SuperClasses: GR32_CBSuperclasses, .SuperClassesSize: 12,
3440 .OrderFunc: nullptr
3441 };
3442
3443 extern const TargetRegisterClass GR32_DCRegClass = {
3444 .MC: &X86MCRegisterClasses[GR32_DCRegClassID],
3445 .SubClassMask: GR32_DCSubClassMask,
3446 .SuperRegIndices: SuperRegIdxSeqs + 7,
3447 .LaneMask: LaneBitmask(0x000000000000000F),
3448 .AllocationPriority: 0,
3449 .GlobalPriority: false,
3450 .TSFlags: 0x00, /* TSFlags */
3451 .SpillStackID: 0, /* SpillStackID */
3452 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3453 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3454 .SuperClasses: GR32_DCSuperclasses, .SuperClassesSize: 15,
3455 .OrderFunc: nullptr
3456 };
3457
3458 extern const TargetRegisterClass GR32_DIBPRegClass = {
3459 .MC: &X86MCRegisterClasses[GR32_DIBPRegClassID],
3460 .SubClassMask: GR32_DIBPSubClassMask,
3461 .SuperRegIndices: SuperRegIdxSeqs + 7,
3462 .LaneMask: LaneBitmask(0x000000000000000F),
3463 .AllocationPriority: 0,
3464 .GlobalPriority: false,
3465 .TSFlags: 0x00, /* TSFlags */
3466 .SpillStackID: 0, /* SpillStackID */
3467 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3468 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3469 .SuperClasses: GR32_DIBPSuperclasses, .SuperClassesSize: 11,
3470 .OrderFunc: nullptr
3471 };
3472
3473 extern const TargetRegisterClass GR32_SIDIRegClass = {
3474 .MC: &X86MCRegisterClasses[GR32_SIDIRegClassID],
3475 .SubClassMask: GR32_SIDISubClassMask,
3476 .SuperRegIndices: SuperRegIdxSeqs + 7,
3477 .LaneMask: LaneBitmask(0x000000000000000F),
3478 .AllocationPriority: 0,
3479 .GlobalPriority: false,
3480 .TSFlags: 0x00, /* TSFlags */
3481 .SpillStackID: 0, /* SpillStackID */
3482 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3483 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3484 .SuperClasses: GR32_SIDISuperclasses, .SuperClassesSize: 11,
3485 .OrderFunc: nullptr
3486 };
3487
3488 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass = {
3489 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID],
3490 .SubClassMask: LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask,
3491 .SuperRegIndices: SuperRegIdxSeqs + 1,
3492 .LaneMask: LaneBitmask(0x000000000000000F),
3493 .AllocationPriority: 0,
3494 .GlobalPriority: false,
3495 .TSFlags: 0x00, /* TSFlags */
3496 .SpillStackID: 0, /* SpillStackID */
3497 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3498 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3499 .SuperClasses: LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses, .SuperClassesSize: 1,
3500 .OrderFunc: nullptr
3501 };
3502
3503 extern const TargetRegisterClass CCRRegClass = {
3504 .MC: &X86MCRegisterClasses[CCRRegClassID],
3505 .SubClassMask: CCRSubClassMask,
3506 .SuperRegIndices: SuperRegIdxSeqs + 1,
3507 .LaneMask: LaneBitmask(0x0000000000000001),
3508 .AllocationPriority: 0,
3509 .GlobalPriority: false,
3510 .TSFlags: 0x00, /* TSFlags */
3511 .SpillStackID: 0, /* SpillStackID */
3512 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3513 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3514 .SuperClasses: nullptr, .SuperClassesSize: 0,
3515 .OrderFunc: nullptr
3516 };
3517
3518 extern const TargetRegisterClass DFCCRRegClass = {
3519 .MC: &X86MCRegisterClasses[DFCCRRegClassID],
3520 .SubClassMask: DFCCRSubClassMask,
3521 .SuperRegIndices: SuperRegIdxSeqs + 1,
3522 .LaneMask: LaneBitmask(0x0000000000000001),
3523 .AllocationPriority: 0,
3524 .GlobalPriority: false,
3525 .TSFlags: 0x00, /* TSFlags */
3526 .SpillStackID: 0, /* SpillStackID */
3527 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3528 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3529 .SuperClasses: nullptr, .SuperClassesSize: 0,
3530 .OrderFunc: nullptr
3531 };
3532
3533 extern const TargetRegisterClass GR32_ABCD_and_GR32_BSIRegClass = {
3534 .MC: &X86MCRegisterClasses[GR32_ABCD_and_GR32_BSIRegClassID],
3535 .SubClassMask: GR32_ABCD_and_GR32_BSISubClassMask,
3536 .SuperRegIndices: SuperRegIdxSeqs + 7,
3537 .LaneMask: LaneBitmask(0x000000000000000F),
3538 .AllocationPriority: 0,
3539 .GlobalPriority: false,
3540 .TSFlags: 0x00, /* TSFlags */
3541 .SpillStackID: 0, /* SpillStackID */
3542 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3543 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3544 .SuperClasses: GR32_ABCD_and_GR32_BSISuperclasses, .SuperClassesSize: 14,
3545 .OrderFunc: nullptr
3546 };
3547
3548 extern const TargetRegisterClass GR32_AD_and_GR32_ArgRefRegClass = {
3549 .MC: &X86MCRegisterClasses[GR32_AD_and_GR32_ArgRefRegClassID],
3550 .SubClassMask: GR32_AD_and_GR32_ArgRefSubClassMask,
3551 .SuperRegIndices: SuperRegIdxSeqs + 7,
3552 .LaneMask: LaneBitmask(0x000000000000000F),
3553 .AllocationPriority: 0,
3554 .GlobalPriority: false,
3555 .TSFlags: 0x00, /* TSFlags */
3556 .SpillStackID: 0, /* SpillStackID */
3557 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3558 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3559 .SuperClasses: GR32_AD_and_GR32_ArgRefSuperclasses, .SuperClassesSize: 17,
3560 .OrderFunc: nullptr
3561 };
3562
3563 extern const TargetRegisterClass GR32_ArgRef_and_GR32_CBRegClass = {
3564 .MC: &X86MCRegisterClasses[GR32_ArgRef_and_GR32_CBRegClassID],
3565 .SubClassMask: GR32_ArgRef_and_GR32_CBSubClassMask,
3566 .SuperRegIndices: SuperRegIdxSeqs + 7,
3567 .LaneMask: LaneBitmask(0x000000000000000F),
3568 .AllocationPriority: 0,
3569 .GlobalPriority: false,
3570 .TSFlags: 0x00, /* TSFlags */
3571 .SpillStackID: 0, /* SpillStackID */
3572 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3573 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3574 .SuperClasses: GR32_ArgRef_and_GR32_CBSuperclasses, .SuperClassesSize: 17,
3575 .OrderFunc: nullptr
3576 };
3577
3578 extern const TargetRegisterClass GR32_BPSP_and_GR32_DIBPRegClass = {
3579 .MC: &X86MCRegisterClasses[GR32_BPSP_and_GR32_DIBPRegClassID],
3580 .SubClassMask: GR32_BPSP_and_GR32_DIBPSubClassMask,
3581 .SuperRegIndices: SuperRegIdxSeqs + 7,
3582 .LaneMask: LaneBitmask(0x000000000000000F),
3583 .AllocationPriority: 0,
3584 .GlobalPriority: false,
3585 .TSFlags: 0x00, /* TSFlags */
3586 .SpillStackID: 0, /* SpillStackID */
3587 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3588 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3589 .SuperClasses: GR32_BPSP_and_GR32_DIBPSuperclasses, .SuperClassesSize: 13,
3590 .OrderFunc: nullptr
3591 };
3592
3593 extern const TargetRegisterClass GR32_BPSP_and_GR32_TCRegClass = {
3594 .MC: &X86MCRegisterClasses[GR32_BPSP_and_GR32_TCRegClassID],
3595 .SubClassMask: GR32_BPSP_and_GR32_TCSubClassMask,
3596 .SuperRegIndices: SuperRegIdxSeqs + 7,
3597 .LaneMask: LaneBitmask(0x000000000000000F),
3598 .AllocationPriority: 0,
3599 .GlobalPriority: false,
3600 .TSFlags: 0x00, /* TSFlags */
3601 .SpillStackID: 0, /* SpillStackID */
3602 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3603 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3604 .SuperClasses: GR32_BPSP_and_GR32_TCSuperclasses, .SuperClassesSize: 10,
3605 .OrderFunc: nullptr
3606 };
3607
3608 extern const TargetRegisterClass GR32_BSI_and_GR32_SIDIRegClass = {
3609 .MC: &X86MCRegisterClasses[GR32_BSI_and_GR32_SIDIRegClassID],
3610 .SubClassMask: GR32_BSI_and_GR32_SIDISubClassMask,
3611 .SuperRegIndices: SuperRegIdxSeqs + 7,
3612 .LaneMask: LaneBitmask(0x000000000000000F),
3613 .AllocationPriority: 0,
3614 .GlobalPriority: false,
3615 .TSFlags: 0x00, /* TSFlags */
3616 .SpillStackID: 0, /* SpillStackID */
3617 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3618 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3619 .SuperClasses: GR32_BSI_and_GR32_SIDISuperclasses, .SuperClassesSize: 13,
3620 .OrderFunc: nullptr
3621 };
3622
3623 extern const TargetRegisterClass GR32_DIBP_and_GR32_SIDIRegClass = {
3624 .MC: &X86MCRegisterClasses[GR32_DIBP_and_GR32_SIDIRegClassID],
3625 .SubClassMask: GR32_DIBP_and_GR32_SIDISubClassMask,
3626 .SuperRegIndices: SuperRegIdxSeqs + 7,
3627 .LaneMask: LaneBitmask(0x000000000000000F),
3628 .AllocationPriority: 0,
3629 .GlobalPriority: false,
3630 .TSFlags: 0x00, /* TSFlags */
3631 .SpillStackID: 0, /* SpillStackID */
3632 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3633 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3634 .SuperClasses: GR32_DIBP_and_GR32_SIDISuperclasses, .SuperClassesSize: 13,
3635 .OrderFunc: nullptr
3636 };
3637
3638 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass = {
3639 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID],
3640 .SubClassMask: LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask,
3641 .SuperRegIndices: SuperRegIdxSeqs + 1,
3642 .LaneMask: LaneBitmask(0x000000000000000F),
3643 .AllocationPriority: 0,
3644 .GlobalPriority: false,
3645 .TSFlags: 0x00, /* TSFlags */
3646 .SpillStackID: 0, /* SpillStackID */
3647 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3648 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3649 .SuperClasses: LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses, .SuperClassesSize: 5,
3650 .OrderFunc: nullptr
3651 };
3652
3653 extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass = {
3654 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESS_with_sub_32bitRegClassID],
3655 .SubClassMask: LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask,
3656 .SuperRegIndices: SuperRegIdxSeqs + 1,
3657 .LaneMask: LaneBitmask(0x000000000000000F),
3658 .AllocationPriority: 0,
3659 .GlobalPriority: false,
3660 .TSFlags: 0x00, /* TSFlags */
3661 .SpillStackID: 0, /* SpillStackID */
3662 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3663 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3664 .SuperClasses: LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses, .SuperClassesSize: 3,
3665 .OrderFunc: nullptr
3666 };
3667
3668 extern const TargetRegisterClass RFP64RegClass = {
3669 .MC: &X86MCRegisterClasses[RFP64RegClassID],
3670 .SubClassMask: RFP64SubClassMask,
3671 .SuperRegIndices: SuperRegIdxSeqs + 1,
3672 .LaneMask: LaneBitmask(0x0000000000000001),
3673 .AllocationPriority: 0,
3674 .GlobalPriority: false,
3675 .TSFlags: 0x00, /* TSFlags */
3676 .SpillStackID: 0, /* SpillStackID */
3677 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3678 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3679 .SuperClasses: RFP64Superclasses, .SuperClassesSize: 1,
3680 .OrderFunc: nullptr
3681 };
3682
3683 extern const TargetRegisterClass GR64RegClass = {
3684 .MC: &X86MCRegisterClasses[GR64RegClassID],
3685 .SubClassMask: GR64SubClassMask,
3686 .SuperRegIndices: SuperRegIdxSeqs + 1,
3687 .LaneMask: LaneBitmask(0x000000000000000F),
3688 .AllocationPriority: 0,
3689 .GlobalPriority: false,
3690 .TSFlags: 0x00, /* TSFlags */
3691 .SpillStackID: 0, /* SpillStackID */
3692 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3693 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3694 .SuperClasses: nullptr, .SuperClassesSize: 0,
3695 .OrderFunc: nullptr
3696 };
3697
3698 extern const TargetRegisterClass FR64XRegClass = {
3699 .MC: &X86MCRegisterClasses[FR64XRegClassID],
3700 .SubClassMask: FR64XSubClassMask,
3701 .SuperRegIndices: SuperRegIdxSeqs + 12,
3702 .LaneMask: LaneBitmask(0x0000000000000001),
3703 .AllocationPriority: 0,
3704 .GlobalPriority: false,
3705 .TSFlags: 0x00, /* TSFlags */
3706 .SpillStackID: 0, /* SpillStackID */
3707 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3708 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3709 .SuperClasses: FR64XSuperclasses, .SuperClassesSize: 2,
3710 .OrderFunc: FR64XGetRawAllocationOrder
3711 };
3712
3713 extern const TargetRegisterClass GR64_with_sub_8bitRegClass = {
3714 .MC: &X86MCRegisterClasses[GR64_with_sub_8bitRegClassID],
3715 .SubClassMask: GR64_with_sub_8bitSubClassMask,
3716 .SuperRegIndices: SuperRegIdxSeqs + 1,
3717 .LaneMask: LaneBitmask(0x000000000000000F),
3718 .AllocationPriority: 0,
3719 .GlobalPriority: false,
3720 .TSFlags: 0x00, /* TSFlags */
3721 .SpillStackID: 0, /* SpillStackID */
3722 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3723 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3724 .SuperClasses: GR64_with_sub_8bitSuperclasses, .SuperClassesSize: 1,
3725 .OrderFunc: nullptr
3726 };
3727
3728 extern const TargetRegisterClass GR64_NOSPRegClass = {
3729 .MC: &X86MCRegisterClasses[GR64_NOSPRegClassID],
3730 .SubClassMask: GR64_NOSPSubClassMask,
3731 .SuperRegIndices: SuperRegIdxSeqs + 1,
3732 .LaneMask: LaneBitmask(0x000000000000000F),
3733 .AllocationPriority: 0,
3734 .GlobalPriority: false,
3735 .TSFlags: 0x00, /* TSFlags */
3736 .SpillStackID: 0, /* SpillStackID */
3737 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3738 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3739 .SuperClasses: GR64_NOSPSuperclasses, .SuperClassesSize: 2,
3740 .OrderFunc: nullptr
3741 };
3742
3743 extern const TargetRegisterClass GR64_NOREX2RegClass = {
3744 .MC: &X86MCRegisterClasses[GR64_NOREX2RegClassID],
3745 .SubClassMask: GR64_NOREX2SubClassMask,
3746 .SuperRegIndices: SuperRegIdxSeqs + 1,
3747 .LaneMask: LaneBitmask(0x000000000000000F),
3748 .AllocationPriority: 0,
3749 .GlobalPriority: false,
3750 .TSFlags: 0x00, /* TSFlags */
3751 .SpillStackID: 0, /* SpillStackID */
3752 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3753 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3754 .SuperClasses: GR64_NOREX2Superclasses, .SuperClassesSize: 1,
3755 .OrderFunc: nullptr
3756 };
3757
3758 extern const TargetRegisterClass CONTROL_REGRegClass = {
3759 .MC: &X86MCRegisterClasses[CONTROL_REGRegClassID],
3760 .SubClassMask: CONTROL_REGSubClassMask,
3761 .SuperRegIndices: SuperRegIdxSeqs + 1,
3762 .LaneMask: LaneBitmask(0x0000000000000001),
3763 .AllocationPriority: 0,
3764 .GlobalPriority: false,
3765 .TSFlags: 0x00, /* TSFlags */
3766 .SpillStackID: 0, /* SpillStackID */
3767 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3768 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3769 .SuperClasses: nullptr, .SuperClassesSize: 0,
3770 .OrderFunc: nullptr
3771 };
3772
3773 extern const TargetRegisterClass FR64RegClass = {
3774 .MC: &X86MCRegisterClasses[FR64RegClassID],
3775 .SubClassMask: FR64SubClassMask,
3776 .SuperRegIndices: SuperRegIdxSeqs + 12,
3777 .LaneMask: LaneBitmask(0x0000000000000001),
3778 .AllocationPriority: 0,
3779 .GlobalPriority: false,
3780 .TSFlags: 0x00, /* TSFlags */
3781 .SpillStackID: 0, /* SpillStackID */
3782 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3783 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3784 .SuperClasses: FR64Superclasses, .SuperClassesSize: 5,
3785 .OrderFunc: nullptr
3786 };
3787
3788 extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREX2RegClass = {
3789 .MC: &X86MCRegisterClasses[GR64_with_sub_16bit_in_GR16_NOREX2RegClassID],
3790 .SubClassMask: GR64_with_sub_16bit_in_GR16_NOREX2SubClassMask,
3791 .SuperRegIndices: SuperRegIdxSeqs + 1,
3792 .LaneMask: LaneBitmask(0x000000000000000F),
3793 .AllocationPriority: 0,
3794 .GlobalPriority: false,
3795 .TSFlags: 0x00, /* TSFlags */
3796 .SpillStackID: 0, /* SpillStackID */
3797 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3798 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3799 .SuperClasses: GR64_with_sub_16bit_in_GR16_NOREX2Superclasses, .SuperClassesSize: 3,
3800 .OrderFunc: nullptr
3801 };
3802
3803 extern const TargetRegisterClass GR64_NOREX2_NOSPRegClass = {
3804 .MC: &X86MCRegisterClasses[GR64_NOREX2_NOSPRegClassID],
3805 .SubClassMask: GR64_NOREX2_NOSPSubClassMask,
3806 .SuperRegIndices: SuperRegIdxSeqs + 1,
3807 .LaneMask: LaneBitmask(0x000000000000000F),
3808 .AllocationPriority: 0,
3809 .GlobalPriority: false,
3810 .TSFlags: 0x00, /* TSFlags */
3811 .SpillStackID: 0, /* SpillStackID */
3812 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3813 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3814 .SuperClasses: GR64_NOREX2_NOSPSuperclasses, .SuperClassesSize: 5,
3815 .OrderFunc: nullptr
3816 };
3817
3818 extern const TargetRegisterClass GR64PLTSafeRegClass = {
3819 .MC: &X86MCRegisterClasses[GR64PLTSafeRegClassID],
3820 .SubClassMask: GR64PLTSafeSubClassMask,
3821 .SuperRegIndices: SuperRegIdxSeqs + 1,
3822 .LaneMask: LaneBitmask(0x000000000000000F),
3823 .AllocationPriority: 0,
3824 .GlobalPriority: false,
3825 .TSFlags: 0x00, /* TSFlags */
3826 .SpillStackID: 0, /* SpillStackID */
3827 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3828 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3829 .SuperClasses: GR64PLTSafeSuperclasses, .SuperClassesSize: 6,
3830 .OrderFunc: nullptr
3831 };
3832
3833 extern const TargetRegisterClass GR64_TCRegClass = {
3834 .MC: &X86MCRegisterClasses[GR64_TCRegClassID],
3835 .SubClassMask: GR64_TCSubClassMask,
3836 .SuperRegIndices: SuperRegIdxSeqs + 1,
3837 .LaneMask: LaneBitmask(0x000000000000000F),
3838 .AllocationPriority: 0,
3839 .GlobalPriority: false,
3840 .TSFlags: 0x00, /* TSFlags */
3841 .SpillStackID: 0, /* SpillStackID */
3842 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3843 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3844 .SuperClasses: GR64_TCSuperclasses, .SuperClassesSize: 2,
3845 .OrderFunc: nullptr
3846 };
3847
3848 extern const TargetRegisterClass GR64_NOREXRegClass = {
3849 .MC: &X86MCRegisterClasses[GR64_NOREXRegClassID],
3850 .SubClassMask: GR64_NOREXSubClassMask,
3851 .SuperRegIndices: SuperRegIdxSeqs + 1,
3852 .LaneMask: LaneBitmask(0x000000000000000F),
3853 .AllocationPriority: 0,
3854 .GlobalPriority: false,
3855 .TSFlags: 0x00, /* TSFlags */
3856 .SpillStackID: 0, /* SpillStackID */
3857 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3858 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3859 .SuperClasses: GR64_NOREXSuperclasses, .SuperClassesSize: 2,
3860 .OrderFunc: nullptr
3861 };
3862
3863 extern const TargetRegisterClass GR64_TCW64RegClass = {
3864 .MC: &X86MCRegisterClasses[GR64_TCW64RegClassID],
3865 .SubClassMask: GR64_TCW64SubClassMask,
3866 .SuperRegIndices: SuperRegIdxSeqs + 1,
3867 .LaneMask: LaneBitmask(0x000000000000000F),
3868 .AllocationPriority: 0,
3869 .GlobalPriority: false,
3870 .TSFlags: 0x00, /* TSFlags */
3871 .SpillStackID: 0, /* SpillStackID */
3872 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3873 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3874 .SuperClasses: GR64_TCW64Superclasses, .SuperClassesSize: 2,
3875 .OrderFunc: nullptr
3876 };
3877
3878 extern const TargetRegisterClass GR64_TC_with_sub_8bitRegClass = {
3879 .MC: &X86MCRegisterClasses[GR64_TC_with_sub_8bitRegClassID],
3880 .SubClassMask: GR64_TC_with_sub_8bitSubClassMask,
3881 .SuperRegIndices: SuperRegIdxSeqs + 1,
3882 .LaneMask: LaneBitmask(0x000000000000000F),
3883 .AllocationPriority: 0,
3884 .GlobalPriority: false,
3885 .TSFlags: 0x00, /* TSFlags */
3886 .SpillStackID: 0, /* SpillStackID */
3887 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3888 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3889 .SuperClasses: GR64_TC_with_sub_8bitSuperclasses, .SuperClassesSize: 5,
3890 .OrderFunc: nullptr
3891 };
3892
3893 extern const TargetRegisterClass GR64_NOREX2_NOSP_and_GR64_TCRegClass = {
3894 .MC: &X86MCRegisterClasses[GR64_NOREX2_NOSP_and_GR64_TCRegClassID],
3895 .SubClassMask: GR64_NOREX2_NOSP_and_GR64_TCSubClassMask,
3896 .SuperRegIndices: SuperRegIdxSeqs + 1,
3897 .LaneMask: LaneBitmask(0x000000000000000F),
3898 .AllocationPriority: 0,
3899 .GlobalPriority: false,
3900 .TSFlags: 0x00, /* TSFlags */
3901 .SpillStackID: 0, /* SpillStackID */
3902 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3903 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3904 .SuperClasses: GR64_NOREX2_NOSP_and_GR64_TCSuperclasses, .SuperClassesSize: 8,
3905 .OrderFunc: nullptr
3906 };
3907
3908 extern const TargetRegisterClass GR64_TCW64_with_sub_8bitRegClass = {
3909 .MC: &X86MCRegisterClasses[GR64_TCW64_with_sub_8bitRegClassID],
3910 .SubClassMask: GR64_TCW64_with_sub_8bitSubClassMask,
3911 .SuperRegIndices: SuperRegIdxSeqs + 1,
3912 .LaneMask: LaneBitmask(0x000000000000000F),
3913 .AllocationPriority: 0,
3914 .GlobalPriority: false,
3915 .TSFlags: 0x00, /* TSFlags */
3916 .SpillStackID: 0, /* SpillStackID */
3917 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3918 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3919 .SuperClasses: GR64_TCW64_with_sub_8bitSuperclasses, .SuperClassesSize: 5,
3920 .OrderFunc: nullptr
3921 };
3922
3923 extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass = {
3924 .MC: &X86MCRegisterClasses[GR64_TC_and_GR64_TCW64RegClassID],
3925 .SubClassMask: GR64_TC_and_GR64_TCW64SubClassMask,
3926 .SuperRegIndices: SuperRegIdxSeqs + 1,
3927 .LaneMask: LaneBitmask(0x000000000000000F),
3928 .AllocationPriority: 0,
3929 .GlobalPriority: false,
3930 .TSFlags: 0x00, /* TSFlags */
3931 .SpillStackID: 0, /* SpillStackID */
3932 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3933 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3934 .SuperClasses: GR64_TC_and_GR64_TCW64Superclasses, .SuperClassesSize: 4,
3935 .OrderFunc: nullptr
3936 };
3937
3938 extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass = {
3939 .MC: &X86MCRegisterClasses[GR64_with_sub_16bit_in_GR16_NOREXRegClassID],
3940 .SubClassMask: GR64_with_sub_16bit_in_GR16_NOREXSubClassMask,
3941 .SuperRegIndices: SuperRegIdxSeqs + 1,
3942 .LaneMask: LaneBitmask(0x000000000000000F),
3943 .AllocationPriority: 0,
3944 .GlobalPriority: false,
3945 .TSFlags: 0x00, /* TSFlags */
3946 .SpillStackID: 0, /* SpillStackID */
3947 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3948 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3949 .SuperClasses: GR64_with_sub_16bit_in_GR16_NOREXSuperclasses, .SuperClassesSize: 5,
3950 .OrderFunc: nullptr
3951 };
3952
3953 extern const TargetRegisterClass VK64RegClass = {
3954 .MC: &X86MCRegisterClasses[VK64RegClassID],
3955 .SubClassMask: VK64SubClassMask,
3956 .SuperRegIndices: SuperRegIdxSeqs + 9,
3957 .LaneMask: LaneBitmask(0x0000000000000001),
3958 .AllocationPriority: 0,
3959 .GlobalPriority: false,
3960 .TSFlags: 0x00, /* TSFlags */
3961 .SpillStackID: 0, /* SpillStackID */
3962 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3963 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3964 .SuperClasses: VK64Superclasses, .SuperClassesSize: 6,
3965 .OrderFunc: nullptr
3966 };
3967
3968 extern const TargetRegisterClass VR64RegClass = {
3969 .MC: &X86MCRegisterClasses[VR64RegClassID],
3970 .SubClassMask: VR64SubClassMask,
3971 .SuperRegIndices: SuperRegIdxSeqs + 1,
3972 .LaneMask: LaneBitmask(0x0000000000000001),
3973 .AllocationPriority: 0,
3974 .GlobalPriority: false,
3975 .TSFlags: 0x00, /* TSFlags */
3976 .SpillStackID: 0, /* SpillStackID */
3977 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3978 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3979 .SuperClasses: nullptr, .SuperClassesSize: 0,
3980 .OrderFunc: nullptr
3981 };
3982
3983 extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCRegClass = {
3984 .MC: &X86MCRegisterClasses[GR64PLTSafe_and_GR64_TCRegClassID],
3985 .SubClassMask: GR64PLTSafe_and_GR64_TCSubClassMask,
3986 .SuperRegIndices: SuperRegIdxSeqs + 1,
3987 .LaneMask: LaneBitmask(0x000000000000000F),
3988 .AllocationPriority: 0,
3989 .GlobalPriority: false,
3990 .TSFlags: 0x00, /* TSFlags */
3991 .SpillStackID: 0, /* SpillStackID */
3992 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3993 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3994 .SuperClasses: GR64PLTSafe_and_GR64_TCSuperclasses, .SuperClassesSize: 10,
3995 .OrderFunc: nullptr
3996 };
3997
3998 extern const TargetRegisterClass GR64_NOREX2_NOSP_and_GR64_TCW64RegClass = {
3999 .MC: &X86MCRegisterClasses[GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID],
4000 .SubClassMask: GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask,
4001 .SuperRegIndices: SuperRegIdxSeqs + 1,
4002 .LaneMask: LaneBitmask(0x000000000000000F),
4003 .AllocationPriority: 0,
4004 .GlobalPriority: false,
4005 .TSFlags: 0x00, /* TSFlags */
4006 .SpillStackID: 0, /* SpillStackID */
4007 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4008 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4009 .SuperClasses: GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses, .SuperClassesSize: 8,
4010 .OrderFunc: nullptr
4011 };
4012
4013 extern const TargetRegisterClass GR64_NOREX_NOSPRegClass = {
4014 .MC: &X86MCRegisterClasses[GR64_NOREX_NOSPRegClassID],
4015 .SubClassMask: GR64_NOREX_NOSPSubClassMask,
4016 .SuperRegIndices: SuperRegIdxSeqs + 1,
4017 .LaneMask: LaneBitmask(0x000000000000000F),
4018 .AllocationPriority: 0,
4019 .GlobalPriority: false,
4020 .TSFlags: 0x00, /* TSFlags */
4021 .SpillStackID: 0, /* SpillStackID */
4022 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4023 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4024 .SuperClasses: GR64_NOREX_NOSPSuperclasses, .SuperClassesSize: 9,
4025 .OrderFunc: nullptr
4026 };
4027
4028 extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass = {
4029 .MC: &X86MCRegisterClasses[GR64_NOREX_and_GR64_TCRegClassID],
4030 .SubClassMask: GR64_NOREX_and_GR64_TCSubClassMask,
4031 .SuperRegIndices: SuperRegIdxSeqs + 1,
4032 .LaneMask: LaneBitmask(0x000000000000000F),
4033 .AllocationPriority: 0,
4034 .GlobalPriority: false,
4035 .TSFlags: 0x00, /* TSFlags */
4036 .SpillStackID: 0, /* SpillStackID */
4037 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4038 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4039 .SuperClasses: GR64_NOREX_and_GR64_TCSuperclasses, .SuperClassesSize: 4,
4040 .OrderFunc: nullptr
4041 };
4042
4043 extern const TargetRegisterClass GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass = {
4044 .MC: &X86MCRegisterClasses[GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID],
4045 .SubClassMask: GR64_TCW64_and_GR64_TC_with_sub_8bitSubClassMask,
4046 .SuperRegIndices: SuperRegIdxSeqs + 1,
4047 .LaneMask: LaneBitmask(0x000000000000000F),
4048 .AllocationPriority: 0,
4049 .GlobalPriority: false,
4050 .TSFlags: 0x00, /* TSFlags */
4051 .SpillStackID: 0, /* SpillStackID */
4052 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4053 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4054 .SuperClasses: GR64_TCW64_and_GR64_TC_with_sub_8bitSuperclasses, .SuperClassesSize: 9,
4055 .OrderFunc: nullptr
4056 };
4057
4058 extern const TargetRegisterClass VK64WMRegClass = {
4059 .MC: &X86MCRegisterClasses[VK64WMRegClassID],
4060 .SubClassMask: VK64WMSubClassMask,
4061 .SuperRegIndices: SuperRegIdxSeqs + 9,
4062 .LaneMask: LaneBitmask(0x0000000000000001),
4063 .AllocationPriority: 0,
4064 .GlobalPriority: false,
4065 .TSFlags: 0x00, /* TSFlags */
4066 .SpillStackID: 0, /* SpillStackID */
4067 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4068 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4069 .SuperClasses: VK64WMSuperclasses, .SuperClassesSize: 13,
4070 .OrderFunc: nullptr
4071 };
4072
4073 extern const TargetRegisterClass GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClass = {
4074 .MC: &X86MCRegisterClasses[GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID],
4075 .SubClassMask: GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask,
4076 .SuperRegIndices: SuperRegIdxSeqs + 1,
4077 .LaneMask: LaneBitmask(0x000000000000000F),
4078 .AllocationPriority: 0,
4079 .GlobalPriority: false,
4080 .TSFlags: 0x00, /* TSFlags */
4081 .SpillStackID: 0, /* SpillStackID */
4082 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4083 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4084 .SuperClasses: GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses, .SuperClassesSize: 14,
4085 .OrderFunc: nullptr
4086 };
4087
4088 extern const TargetRegisterClass GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass = {
4089 .MC: &X86MCRegisterClasses[GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID],
4090 .SubClassMask: GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSubClassMask,
4091 .SuperRegIndices: SuperRegIdxSeqs + 1,
4092 .LaneMask: LaneBitmask(0x000000000000000F),
4093 .AllocationPriority: 0,
4094 .GlobalPriority: false,
4095 .TSFlags: 0x00, /* TSFlags */
4096 .SpillStackID: 0, /* SpillStackID */
4097 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4098 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4099 .SuperClasses: GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSuperclasses, .SuperClassesSize: 9,
4100 .OrderFunc: nullptr
4101 };
4102
4103 extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCW64RegClass = {
4104 .MC: &X86MCRegisterClasses[GR64PLTSafe_and_GR64_TCW64RegClassID],
4105 .SubClassMask: GR64PLTSafe_and_GR64_TCW64SubClassMask,
4106 .SuperRegIndices: SuperRegIdxSeqs + 1,
4107 .LaneMask: LaneBitmask(0x000000000000000F),
4108 .AllocationPriority: 0,
4109 .GlobalPriority: false,
4110 .TSFlags: 0x00, /* TSFlags */
4111 .SpillStackID: 0, /* SpillStackID */
4112 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4113 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4114 .SuperClasses: GR64PLTSafe_and_GR64_TCW64Superclasses, .SuperClassesSize: 17,
4115 .OrderFunc: nullptr
4116 };
4117
4118 extern const TargetRegisterClass GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass = {
4119 .MC: &X86MCRegisterClasses[GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID],
4120 .SubClassMask: GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSubClassMask,
4121 .SuperRegIndices: SuperRegIdxSeqs + 1,
4122 .LaneMask: LaneBitmask(0x000000000000000F),
4123 .AllocationPriority: 0,
4124 .GlobalPriority: false,
4125 .TSFlags: 0x00, /* TSFlags */
4126 .SpillStackID: 0, /* SpillStackID */
4127 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4128 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4129 .SuperClasses: GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSuperclasses, .SuperClassesSize: 16,
4130 .OrderFunc: nullptr
4131 };
4132
4133 extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass = {
4134 .MC: &X86MCRegisterClasses[GR64_NOREX_and_GR64_TCW64RegClassID],
4135 .SubClassMask: GR64_NOREX_and_GR64_TCW64SubClassMask,
4136 .SuperRegIndices: SuperRegIdxSeqs + 1,
4137 .LaneMask: LaneBitmask(0x000000000000000F),
4138 .AllocationPriority: 0,
4139 .GlobalPriority: false,
4140 .TSFlags: 0x00, /* TSFlags */
4141 .SpillStackID: 0, /* SpillStackID */
4142 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4143 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4144 .SuperClasses: GR64_NOREX_and_GR64_TCW64Superclasses, .SuperClassesSize: 7,
4145 .OrderFunc: nullptr
4146 };
4147
4148 extern const TargetRegisterClass GR64_ABCDRegClass = {
4149 .MC: &X86MCRegisterClasses[GR64_ABCDRegClassID],
4150 .SubClassMask: GR64_ABCDSubClassMask,
4151 .SuperRegIndices: SuperRegIdxSeqs + 1,
4152 .LaneMask: LaneBitmask(0x000000000000000F),
4153 .AllocationPriority: 0,
4154 .GlobalPriority: false,
4155 .TSFlags: 0x00, /* TSFlags */
4156 .SpillStackID: 0, /* SpillStackID */
4157 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4158 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4159 .SuperClasses: GR64_ABCDSuperclasses, .SuperClassesSize: 10,
4160 .OrderFunc: nullptr
4161 };
4162
4163 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass = {
4164 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_TCRegClassID],
4165 .SubClassMask: GR64_with_sub_32bit_in_GR32_TCSubClassMask,
4166 .SuperRegIndices: SuperRegIdxSeqs + 1,
4167 .LaneMask: LaneBitmask(0x000000000000000F),
4168 .AllocationPriority: 0,
4169 .GlobalPriority: false,
4170 .TSFlags: 0x00, /* TSFlags */
4171 .SpillStackID: 0, /* SpillStackID */
4172 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4173 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4174 .SuperClasses: GR64_with_sub_32bit_in_GR32_TCSuperclasses, .SuperClassesSize: 15,
4175 .OrderFunc: nullptr
4176 };
4177
4178 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass = {
4179 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID],
4180 .SubClassMask: GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSubClassMask,
4181 .SuperRegIndices: SuperRegIdxSeqs + 1,
4182 .LaneMask: LaneBitmask(0x000000000000000F),
4183 .AllocationPriority: 0,
4184 .GlobalPriority: false,
4185 .TSFlags: 0x00, /* TSFlags */
4186 .SpillStackID: 0, /* SpillStackID */
4187 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4188 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4189 .SuperClasses: GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSuperclasses, .SuperClassesSize: 27,
4190 .OrderFunc: nullptr
4191 };
4192
4193 extern const TargetRegisterClass GR64_ADRegClass = {
4194 .MC: &X86MCRegisterClasses[GR64_ADRegClassID],
4195 .SubClassMask: GR64_ADSubClassMask,
4196 .SuperRegIndices: SuperRegIdxSeqs + 1,
4197 .LaneMask: LaneBitmask(0x000000000000000F),
4198 .AllocationPriority: 0,
4199 .GlobalPriority: false,
4200 .TSFlags: 0x00, /* TSFlags */
4201 .SpillStackID: 0, /* SpillStackID */
4202 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4203 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4204 .SuperClasses: GR64_ADSuperclasses, .SuperClassesSize: 28,
4205 .OrderFunc: nullptr
4206 };
4207
4208 extern const TargetRegisterClass GR64_ArgRefRegClass = {
4209 .MC: &X86MCRegisterClasses[GR64_ArgRefRegClassID],
4210 .SubClassMask: GR64_ArgRefSubClassMask,
4211 .SuperRegIndices: SuperRegIdxSeqs + 1,
4212 .LaneMask: LaneBitmask(0x000000000000000F),
4213 .AllocationPriority: 0,
4214 .GlobalPriority: false,
4215 .TSFlags: 0x00, /* TSFlags */
4216 .SpillStackID: 0, /* SpillStackID */
4217 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4218 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4219 .SuperClasses: GR64_ArgRefSuperclasses, .SuperClassesSize: 9,
4220 .OrderFunc: nullptr
4221 };
4222
4223 extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass = {
4224 .MC: &X86MCRegisterClasses[GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID],
4225 .SubClassMask: GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask,
4226 .SuperRegIndices: SuperRegIdxSeqs + 1,
4227 .LaneMask: LaneBitmask(0x000000000000000F),
4228 .AllocationPriority: 0,
4229 .GlobalPriority: false,
4230 .TSFlags: 0x00, /* TSFlags */
4231 .SpillStackID: 0, /* SpillStackID */
4232 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4233 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4234 .SuperClasses: GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses, .SuperClassesSize: 5,
4235 .OrderFunc: nullptr
4236 };
4237
4238 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ArgRefRegClass = {
4239 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ArgRefRegClassID],
4240 .SubClassMask: GR64_with_sub_32bit_in_GR32_ArgRefSubClassMask,
4241 .SuperRegIndices: SuperRegIdxSeqs + 1,
4242 .LaneMask: LaneBitmask(0x000000000000000F),
4243 .AllocationPriority: 0,
4244 .GlobalPriority: false,
4245 .TSFlags: 0x00, /* TSFlags */
4246 .SpillStackID: 0, /* SpillStackID */
4247 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4248 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4249 .SuperClasses: GR64_with_sub_32bit_in_GR32_ArgRefSuperclasses, .SuperClassesSize: 28,
4250 .OrderFunc: nullptr
4251 };
4252
4253 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSPRegClass = {
4254 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSPRegClassID],
4255 .SubClassMask: GR64_with_sub_32bit_in_GR32_BPSPSubClassMask,
4256 .SuperRegIndices: SuperRegIdxSeqs + 1,
4257 .LaneMask: LaneBitmask(0x000000000000000F),
4258 .AllocationPriority: 0,
4259 .GlobalPriority: false,
4260 .TSFlags: 0x00, /* TSFlags */
4261 .SpillStackID: 0, /* SpillStackID */
4262 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4263 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4264 .SuperClasses: GR64_with_sub_32bit_in_GR32_BPSPSuperclasses, .SuperClassesSize: 6,
4265 .OrderFunc: nullptr
4266 };
4267
4268 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSIRegClass = {
4269 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BSIRegClassID],
4270 .SubClassMask: GR64_with_sub_32bit_in_GR32_BSISubClassMask,
4271 .SuperRegIndices: SuperRegIdxSeqs + 1,
4272 .LaneMask: LaneBitmask(0x000000000000000F),
4273 .AllocationPriority: 0,
4274 .GlobalPriority: false,
4275 .TSFlags: 0x00, /* TSFlags */
4276 .SpillStackID: 0, /* SpillStackID */
4277 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4278 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4279 .SuperClasses: GR64_with_sub_32bit_in_GR32_BSISuperclasses, .SuperClassesSize: 10,
4280 .OrderFunc: nullptr
4281 };
4282
4283 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CBRegClass = {
4284 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_CBRegClassID],
4285 .SubClassMask: GR64_with_sub_32bit_in_GR32_CBSubClassMask,
4286 .SuperRegIndices: SuperRegIdxSeqs + 1,
4287 .LaneMask: LaneBitmask(0x000000000000000F),
4288 .AllocationPriority: 0,
4289 .GlobalPriority: false,
4290 .TSFlags: 0x00, /* TSFlags */
4291 .SpillStackID: 0, /* SpillStackID */
4292 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4293 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4294 .SuperClasses: GR64_with_sub_32bit_in_GR32_CBSuperclasses, .SuperClassesSize: 11,
4295 .OrderFunc: nullptr
4296 };
4297
4298 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBPRegClass = {
4299 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DIBPRegClassID],
4300 .SubClassMask: GR64_with_sub_32bit_in_GR32_DIBPSubClassMask,
4301 .SuperRegIndices: SuperRegIdxSeqs + 1,
4302 .LaneMask: LaneBitmask(0x000000000000000F),
4303 .AllocationPriority: 0,
4304 .GlobalPriority: false,
4305 .TSFlags: 0x00, /* TSFlags */
4306 .SpillStackID: 0, /* SpillStackID */
4307 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4308 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4309 .SuperClasses: GR64_with_sub_32bit_in_GR32_DIBPSuperclasses, .SuperClassesSize: 10,
4310 .OrderFunc: nullptr
4311 };
4312
4313 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_SIDIRegClass = {
4314 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_SIDIRegClassID],
4315 .SubClassMask: GR64_with_sub_32bit_in_GR32_SIDISubClassMask,
4316 .SuperRegIndices: SuperRegIdxSeqs + 1,
4317 .LaneMask: LaneBitmask(0x000000000000000F),
4318 .AllocationPriority: 0,
4319 .GlobalPriority: false,
4320 .TSFlags: 0x00, /* TSFlags */
4321 .SpillStackID: 0, /* SpillStackID */
4322 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4323 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4324 .SuperClasses: GR64_with_sub_32bit_in_GR32_SIDISuperclasses, .SuperClassesSize: 17,
4325 .OrderFunc: nullptr
4326 };
4327
4328 extern const TargetRegisterClass GR64_ARegClass = {
4329 .MC: &X86MCRegisterClasses[GR64_ARegClassID],
4330 .SubClassMask: GR64_ASubClassMask,
4331 .SuperRegIndices: SuperRegIdxSeqs + 1,
4332 .LaneMask: LaneBitmask(0x000000000000000F),
4333 .AllocationPriority: 0,
4334 .GlobalPriority: false,
4335 .TSFlags: 0x00, /* TSFlags */
4336 .SpillStackID: 0, /* SpillStackID */
4337 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4338 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4339 .SuperClasses: GR64_ASuperclasses, .SuperClassesSize: 29,
4340 .OrderFunc: nullptr
4341 };
4342
4343 extern const TargetRegisterClass GR64_ArgRef_and_GR64_TCRegClass = {
4344 .MC: &X86MCRegisterClasses[GR64_ArgRef_and_GR64_TCRegClassID],
4345 .SubClassMask: GR64_ArgRef_and_GR64_TCSubClassMask,
4346 .SuperRegIndices: SuperRegIdxSeqs + 1,
4347 .LaneMask: LaneBitmask(0x000000000000000F),
4348 .AllocationPriority: 0,
4349 .GlobalPriority: false,
4350 .TSFlags: 0x00, /* TSFlags */
4351 .SpillStackID: 0, /* SpillStackID */
4352 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4353 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4354 .SuperClasses: GR64_ArgRef_and_GR64_TCSuperclasses, .SuperClassesSize: 16,
4355 .OrderFunc: nullptr
4356 };
4357
4358 extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass = {
4359 .MC: &X86MCRegisterClasses[GR64_and_LOW32_ADDR_ACCESSRegClassID],
4360 .SubClassMask: GR64_and_LOW32_ADDR_ACCESSSubClassMask,
4361 .SuperRegIndices: SuperRegIdxSeqs + 1,
4362 .LaneMask: LaneBitmask(0x000000000000000F),
4363 .AllocationPriority: 0,
4364 .GlobalPriority: false,
4365 .TSFlags: 0x00, /* TSFlags */
4366 .SpillStackID: 0, /* SpillStackID */
4367 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4368 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4369 .SuperClasses: GR64_and_LOW32_ADDR_ACCESSSuperclasses, .SuperClassesSize: 13,
4370 .OrderFunc: nullptr
4371 };
4372
4373 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass = {
4374 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID],
4375 .SubClassMask: GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask,
4376 .SuperRegIndices: SuperRegIdxSeqs + 1,
4377 .LaneMask: LaneBitmask(0x000000000000000F),
4378 .AllocationPriority: 0,
4379 .GlobalPriority: false,
4380 .TSFlags: 0x00, /* TSFlags */
4381 .SpillStackID: 0, /* SpillStackID */
4382 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4383 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4384 .SuperClasses: GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISuperclasses, .SuperClassesSize: 13,
4385 .OrderFunc: nullptr
4386 };
4387
4388 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClass = {
4389 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID],
4390 .SubClassMask: GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSubClassMask,
4391 .SuperRegIndices: SuperRegIdxSeqs + 1,
4392 .LaneMask: LaneBitmask(0x000000000000000F),
4393 .AllocationPriority: 0,
4394 .GlobalPriority: false,
4395 .TSFlags: 0x00, /* TSFlags */
4396 .SpillStackID: 0, /* SpillStackID */
4397 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4398 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4399 .SuperClasses: GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSuperclasses, .SuperClassesSize: 30,
4400 .OrderFunc: nullptr
4401 };
4402
4403 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClass = {
4404 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID],
4405 .SubClassMask: GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSubClassMask,
4406 .SuperRegIndices: SuperRegIdxSeqs + 1,
4407 .LaneMask: LaneBitmask(0x000000000000000F),
4408 .AllocationPriority: 0,
4409 .GlobalPriority: false,
4410 .TSFlags: 0x00, /* TSFlags */
4411 .SpillStackID: 0, /* SpillStackID */
4412 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4413 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4414 .SuperClasses: GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSuperclasses, .SuperClassesSize: 30,
4415 .OrderFunc: nullptr
4416 };
4417
4418 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass = {
4419 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID],
4420 .SubClassMask: GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask,
4421 .SuperRegIndices: SuperRegIdxSeqs + 1,
4422 .LaneMask: LaneBitmask(0x000000000000000F),
4423 .AllocationPriority: 0,
4424 .GlobalPriority: false,
4425 .TSFlags: 0x00, /* TSFlags */
4426 .SpillStackID: 0, /* SpillStackID */
4427 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4428 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4429 .SuperClasses: GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSuperclasses, .SuperClassesSize: 19,
4430 .OrderFunc: nullptr
4431 };
4432
4433 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass = {
4434 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID],
4435 .SubClassMask: GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSubClassMask,
4436 .SuperRegIndices: SuperRegIdxSeqs + 1,
4437 .LaneMask: LaneBitmask(0x000000000000000F),
4438 .AllocationPriority: 0,
4439 .GlobalPriority: false,
4440 .TSFlags: 0x00, /* TSFlags */
4441 .SpillStackID: 0, /* SpillStackID */
4442 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4443 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4444 .SuperClasses: GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSuperclasses, .SuperClassesSize: 17,
4445 .OrderFunc: nullptr
4446 };
4447
4448 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass = {
4449 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID],
4450 .SubClassMask: GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask,
4451 .SuperRegIndices: SuperRegIdxSeqs + 1,
4452 .LaneMask: LaneBitmask(0x000000000000000F),
4453 .AllocationPriority: 0,
4454 .GlobalPriority: false,
4455 .TSFlags: 0x00, /* TSFlags */
4456 .SpillStackID: 0, /* SpillStackID */
4457 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4458 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4459 .SuperClasses: GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISuperclasses, .SuperClassesSize: 19,
4460 .OrderFunc: nullptr
4461 };
4462
4463 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass = {
4464 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID],
4465 .SubClassMask: GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask,
4466 .SuperRegIndices: SuperRegIdxSeqs + 1,
4467 .LaneMask: LaneBitmask(0x000000000000000F),
4468 .AllocationPriority: 0,
4469 .GlobalPriority: false,
4470 .TSFlags: 0x00, /* TSFlags */
4471 .SpillStackID: 0, /* SpillStackID */
4472 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4473 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4474 .SuperClasses: GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISuperclasses, .SuperClassesSize: 19,
4475 .OrderFunc: nullptr
4476 };
4477
4478 extern const TargetRegisterClass RSTRegClass = {
4479 .MC: &X86MCRegisterClasses[RSTRegClassID],
4480 .SubClassMask: RSTSubClassMask,
4481 .SuperRegIndices: SuperRegIdxSeqs + 1,
4482 .LaneMask: LaneBitmask(0x0000000000000001),
4483 .AllocationPriority: 0,
4484 .GlobalPriority: false,
4485 .TSFlags: 0x00, /* TSFlags */
4486 .SpillStackID: 0, /* SpillStackID */
4487 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4488 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4489 .SuperClasses: nullptr, .SuperClassesSize: 0,
4490 .OrderFunc: nullptr
4491 };
4492
4493 extern const TargetRegisterClass RFP80RegClass = {
4494 .MC: &X86MCRegisterClasses[RFP80RegClassID],
4495 .SubClassMask: RFP80SubClassMask,
4496 .SuperRegIndices: SuperRegIdxSeqs + 1,
4497 .LaneMask: LaneBitmask(0x0000000000000001),
4498 .AllocationPriority: 0,
4499 .GlobalPriority: false,
4500 .TSFlags: 0x00, /* TSFlags */
4501 .SpillStackID: 0, /* SpillStackID */
4502 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4503 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4504 .SuperClasses: RFP80Superclasses, .SuperClassesSize: 2,
4505 .OrderFunc: nullptr
4506 };
4507
4508 extern const TargetRegisterClass RFP80_7RegClass = {
4509 .MC: &X86MCRegisterClasses[RFP80_7RegClassID],
4510 .SubClassMask: RFP80_7SubClassMask,
4511 .SuperRegIndices: SuperRegIdxSeqs + 1,
4512 .LaneMask: LaneBitmask(0x0000000000000001),
4513 .AllocationPriority: 0,
4514 .GlobalPriority: false,
4515 .TSFlags: 0x00, /* TSFlags */
4516 .SpillStackID: 0, /* SpillStackID */
4517 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4518 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4519 .SuperClasses: nullptr, .SuperClassesSize: 0,
4520 .OrderFunc: nullptr
4521 };
4522
4523 extern const TargetRegisterClass VR128XRegClass = {
4524 .MC: &X86MCRegisterClasses[VR128XRegClassID],
4525 .SubClassMask: VR128XSubClassMask,
4526 .SuperRegIndices: SuperRegIdxSeqs + 12,
4527 .LaneMask: LaneBitmask(0x0000000000000001),
4528 .AllocationPriority: 0,
4529 .GlobalPriority: false,
4530 .TSFlags: 0x00, /* TSFlags */
4531 .SpillStackID: 0, /* SpillStackID */
4532 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4533 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4534 .SuperClasses: VR128XSuperclasses, .SuperClassesSize: 3,
4535 .OrderFunc: VR128XGetRawAllocationOrder
4536 };
4537
4538 extern const TargetRegisterClass VR128RegClass = {
4539 .MC: &X86MCRegisterClasses[VR128RegClassID],
4540 .SubClassMask: VR128SubClassMask,
4541 .SuperRegIndices: SuperRegIdxSeqs + 12,
4542 .LaneMask: LaneBitmask(0x0000000000000001),
4543 .AllocationPriority: 0,
4544 .GlobalPriority: false,
4545 .TSFlags: 0x00, /* TSFlags */
4546 .SpillStackID: 0, /* SpillStackID */
4547 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4548 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4549 .SuperClasses: VR128Superclasses, .SuperClassesSize: 7,
4550 .OrderFunc: nullptr
4551 };
4552
4553 extern const TargetRegisterClass VR256XRegClass = {
4554 .MC: &X86MCRegisterClasses[VR256XRegClassID],
4555 .SubClassMask: VR256XSubClassMask,
4556 .SuperRegIndices: SuperRegIdxSeqs + 14,
4557 .LaneMask: LaneBitmask(0x0000000000000040),
4558 .AllocationPriority: 0,
4559 .GlobalPriority: false,
4560 .TSFlags: 0x00, /* TSFlags */
4561 .SpillStackID: 0, /* SpillStackID */
4562 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4563 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4564 .SuperClasses: nullptr, .SuperClassesSize: 0,
4565 .OrderFunc: VR256XGetRawAllocationOrder
4566 };
4567
4568 extern const TargetRegisterClass VR256RegClass = {
4569 .MC: &X86MCRegisterClasses[VR256RegClassID],
4570 .SubClassMask: VR256SubClassMask,
4571 .SuperRegIndices: SuperRegIdxSeqs + 14,
4572 .LaneMask: LaneBitmask(0x0000000000000040),
4573 .AllocationPriority: 0,
4574 .GlobalPriority: false,
4575 .TSFlags: 0x00, /* TSFlags */
4576 .SpillStackID: 0, /* SpillStackID */
4577 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4578 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4579 .SuperClasses: VR256Superclasses, .SuperClassesSize: 1,
4580 .OrderFunc: nullptr
4581 };
4582
4583 extern const TargetRegisterClass VR512RegClass = {
4584 .MC: &X86MCRegisterClasses[VR512RegClassID],
4585 .SubClassMask: VR512SubClassMask,
4586 .SuperRegIndices: SuperRegIdxSeqs + 1,
4587 .LaneMask: LaneBitmask(0x0000000000000040),
4588 .AllocationPriority: 0,
4589 .GlobalPriority: false,
4590 .TSFlags: 0x00, /* TSFlags */
4591 .SpillStackID: 0, /* SpillStackID */
4592 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4593 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4594 .SuperClasses: nullptr, .SuperClassesSize: 0,
4595 .OrderFunc: nullptr
4596 };
4597
4598 extern const TargetRegisterClass VR512_0_15RegClass = {
4599 .MC: &X86MCRegisterClasses[VR512_0_15RegClassID],
4600 .SubClassMask: VR512_0_15SubClassMask,
4601 .SuperRegIndices: SuperRegIdxSeqs + 1,
4602 .LaneMask: LaneBitmask(0x0000000000000040),
4603 .AllocationPriority: 0,
4604 .GlobalPriority: false,
4605 .TSFlags: 0x00, /* TSFlags */
4606 .SpillStackID: 0, /* SpillStackID */
4607 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4608 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4609 .SuperClasses: VR512_0_15Superclasses, .SuperClassesSize: 1,
4610 .OrderFunc: nullptr
4611 };
4612
4613 extern const TargetRegisterClass TILERegClass = {
4614 .MC: &X86MCRegisterClasses[TILERegClassID],
4615 .SubClassMask: TILESubClassMask,
4616 .SuperRegIndices: SuperRegIdxSeqs + 1,
4617 .LaneMask: LaneBitmask(0x0000000000000001),
4618 .AllocationPriority: 0,
4619 .GlobalPriority: false,
4620 .TSFlags: 0x00, /* TSFlags */
4621 .SpillStackID: 0, /* SpillStackID */
4622 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4623 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4624 .SuperClasses: nullptr, .SuperClassesSize: 0,
4625 .OrderFunc: nullptr
4626 };
4627
4628
4629} // namespace X86
4630static const TargetRegisterClass *const X86RegisterClasses[] = {
4631 &X86::GR8RegClass,
4632 &X86::GRH8RegClass,
4633 &X86::GR8_NOREX2RegClass,
4634 &X86::GR8_NOREXRegClass,
4635 &X86::GR8_ABCD_HRegClass,
4636 &X86::GR8_ABCD_LRegClass,
4637 &X86::GRH16RegClass,
4638 &X86::GR16RegClass,
4639 &X86::GR16_NOREX2RegClass,
4640 &X86::GR16_NOREXRegClass,
4641 &X86::VK1RegClass,
4642 &X86::VK16RegClass,
4643 &X86::VK2RegClass,
4644 &X86::VK4RegClass,
4645 &X86::VK8RegClass,
4646 &X86::VK16WMRegClass,
4647 &X86::VK1WMRegClass,
4648 &X86::VK2WMRegClass,
4649 &X86::VK4WMRegClass,
4650 &X86::VK8WMRegClass,
4651 &X86::SEGMENT_REGRegClass,
4652 &X86::GR16_ABCDRegClass,
4653 &X86::FPCCRRegClass,
4654 &X86::FR16XRegClass,
4655 &X86::FR16RegClass,
4656 &X86::VK16PAIRRegClass,
4657 &X86::VK1PAIRRegClass,
4658 &X86::VK2PAIRRegClass,
4659 &X86::VK4PAIRRegClass,
4660 &X86::VK8PAIRRegClass,
4661 &X86::VK1PAIR_with_sub_mask_0_in_VK1WMRegClass,
4662 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
4663 &X86::LOW32_ADDR_ACCESSRegClass,
4664 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
4665 &X86::FR32XRegClass,
4666 &X86::GR32RegClass,
4667 &X86::GR32_NOSPRegClass,
4668 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
4669 &X86::DEBUG_REGRegClass,
4670 &X86::FR32RegClass,
4671 &X86::GR32_NOREX2RegClass,
4672 &X86::GR32_NOREX2_NOSPRegClass,
4673 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
4674 &X86::GR32_NOREXRegClass,
4675 &X86::VK32RegClass,
4676 &X86::GR32_NOREX_NOSPRegClass,
4677 &X86::RFP32RegClass,
4678 &X86::VK32WMRegClass,
4679 &X86::GR32_ABCDRegClass,
4680 &X86::GR32_TCRegClass,
4681 &X86::GR32_ABCD_and_GR32_TCRegClass,
4682 &X86::GR32_ADRegClass,
4683 &X86::GR32_ArgRefRegClass,
4684 &X86::GR32_BPSPRegClass,
4685 &X86::GR32_BSIRegClass,
4686 &X86::GR32_CBRegClass,
4687 &X86::GR32_DCRegClass,
4688 &X86::GR32_DIBPRegClass,
4689 &X86::GR32_SIDIRegClass,
4690 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
4691 &X86::CCRRegClass,
4692 &X86::DFCCRRegClass,
4693 &X86::GR32_ABCD_and_GR32_BSIRegClass,
4694 &X86::GR32_AD_and_GR32_ArgRefRegClass,
4695 &X86::GR32_ArgRef_and_GR32_CBRegClass,
4696 &X86::GR32_BPSP_and_GR32_DIBPRegClass,
4697 &X86::GR32_BPSP_and_GR32_TCRegClass,
4698 &X86::GR32_BSI_and_GR32_SIDIRegClass,
4699 &X86::GR32_DIBP_and_GR32_SIDIRegClass,
4700 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass,
4701 &X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClass,
4702 &X86::RFP64RegClass,
4703 &X86::GR64RegClass,
4704 &X86::FR64XRegClass,
4705 &X86::GR64_with_sub_8bitRegClass,
4706 &X86::GR64_NOSPRegClass,
4707 &X86::GR64_NOREX2RegClass,
4708 &X86::CONTROL_REGRegClass,
4709 &X86::FR64RegClass,
4710 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
4711 &X86::GR64_NOREX2_NOSPRegClass,
4712 &X86::GR64PLTSafeRegClass,
4713 &X86::GR64_TCRegClass,
4714 &X86::GR64_NOREXRegClass,
4715 &X86::GR64_TCW64RegClass,
4716 &X86::GR64_TC_with_sub_8bitRegClass,
4717 &X86::GR64_NOREX2_NOSP_and_GR64_TCRegClass,
4718 &X86::GR64_TCW64_with_sub_8bitRegClass,
4719 &X86::GR64_TC_and_GR64_TCW64RegClass,
4720 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
4721 &X86::VK64RegClass,
4722 &X86::VR64RegClass,
4723 &X86::GR64PLTSafe_and_GR64_TCRegClass,
4724 &X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
4725 &X86::GR64_NOREX_NOSPRegClass,
4726 &X86::GR64_NOREX_and_GR64_TCRegClass,
4727 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
4728 &X86::VK64WMRegClass,
4729 &X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
4730 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
4731 &X86::GR64PLTSafe_and_GR64_TCW64RegClass,
4732 &X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
4733 &X86::GR64_NOREX_and_GR64_TCW64RegClass,
4734 &X86::GR64_ABCDRegClass,
4735 &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
4736 &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
4737 &X86::GR64_ADRegClass,
4738 &X86::GR64_ArgRefRegClass,
4739 &X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClass,
4740 &X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClass,
4741 &X86::GR64_with_sub_32bit_in_GR32_BPSPRegClass,
4742 &X86::GR64_with_sub_32bit_in_GR32_BSIRegClass,
4743 &X86::GR64_with_sub_32bit_in_GR32_CBRegClass,
4744 &X86::GR64_with_sub_32bit_in_GR32_DIBPRegClass,
4745 &X86::GR64_with_sub_32bit_in_GR32_SIDIRegClass,
4746 &X86::GR64_ARegClass,
4747 &X86::GR64_ArgRef_and_GR64_TCRegClass,
4748 &X86::GR64_and_LOW32_ADDR_ACCESSRegClass,
4749 &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass,
4750 &X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClass,
4751 &X86::GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClass,
4752 &X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass,
4753 &X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass,
4754 &X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass,
4755 &X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass,
4756 &X86::RSTRegClass,
4757 &X86::RFP80RegClass,
4758 &X86::RFP80_7RegClass,
4759 &X86::VR128XRegClass,
4760 &X86::VR128RegClass,
4761 &X86::VR256XRegClass,
4762 &X86::VR256RegClass,
4763 &X86::VR512RegClass,
4764 &X86::VR512_0_15RegClass,
4765 &X86::TILERegClass,
4766 };
4767
4768static const uint8_t X86CostPerUseTable[] = {
47690, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
4770
4771
4772static const bool X86InAllocatableClassTable[] = {
4773false, true, true, true, true, true, true, false, true, true, true, true, true, true, false, true, true, false, true, true, true, true, true, true, true, true, true, true, false, false, false, true, true, true, false, false, true, false, true, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, true, false, true, true, true, false, true, true, false, true, true, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, };
4774
4775
4776static const TargetRegisterInfoDesc X86RegInfoDesc = { // Extra Descriptors
4777.CostPerUse: X86CostPerUseTable, .NumCosts: 1, .InAllocatableClass: X86InAllocatableClassTable};
4778
4779unsigned X86GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
4780 static const uint8_t Rows[1][10] = {
4781 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4782 };
4783
4784 --IdxA; assert(IdxA < 10); (void) IdxA;
4785 --IdxB; assert(IdxB < 10);
4786 return Rows[0][IdxB];
4787}
4788
4789unsigned X86GenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
4790 static const uint8_t Table[10][10] = {
4791 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4792 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4793 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4794 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4795 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4796 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4797 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4798 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4799 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4800 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4801 };
4802
4803 --IdxA; assert(IdxA < 10);
4804 --IdxB; assert(IdxB < 10);
4805 return Table[IdxA][IdxB];
4806 }
4807
4808 struct MaskRolOp {
4809 LaneBitmask Mask;
4810 uint8_t RotateLeft;
4811 };
4812 static const MaskRolOp LaneMaskComposeSequences[] = {
4813 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
4814 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
4815 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
4816 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 6
4817 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 4 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 8
4818 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 5 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 10
4819 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 6 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 12
4820 };
4821 static const uint8_t CompositeSequences[] = {
4822 0, // to sub_8bit
4823 2, // to sub_8bit_hi
4824 4, // to sub_8bit_hi_phony
4825 0, // to sub_16bit
4826 6, // to sub_16bit_hi
4827 0, // to sub_32bit
4828 8, // to sub_mask_0
4829 10, // to sub_mask_1
4830 12, // to sub_xmm
4831 0 // to sub_ymm
4832 };
4833
4834LaneBitmask X86GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
4835 --IdxA; assert(IdxA < 10 && "Subregister index out of bounds");
4836 LaneBitmask Result;
4837 for (const MaskRolOp *Ops =
4838 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
4839 Ops->Mask.any(); ++Ops) {
4840 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
4841 if (unsigned S = Ops->RotateLeft)
4842 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
4843 else
4844 Result |= LaneBitmask(M);
4845 }
4846 return Result;
4847}
4848
4849LaneBitmask X86GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
4850 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
4851 --IdxA; assert(IdxA < 10 && "Subregister index out of bounds");
4852 LaneBitmask Result;
4853 for (const MaskRolOp *Ops =
4854 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
4855 Ops->Mask.any(); ++Ops) {
4856 LaneBitmask::Type M = LaneMask.getAsInteger();
4857 if (unsigned S = Ops->RotateLeft)
4858 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
4859 else
4860 Result |= LaneBitmask(M);
4861 }
4862 return Result;
4863}
4864
4865const TargetRegisterClass *X86GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
4866 static constexpr uint8_t Table[135][10] = {
4867 { // GR8
4868 0, // sub_8bit
4869 0, // sub_8bit_hi
4870 0, // sub_8bit_hi_phony
4871 0, // sub_16bit
4872 0, // sub_16bit_hi
4873 0, // sub_32bit
4874 0, // sub_mask_0
4875 0, // sub_mask_1
4876 0, // sub_xmm
4877 0, // sub_ymm
4878 },
4879 { // GRH8
4880 0, // sub_8bit
4881 0, // sub_8bit_hi
4882 0, // sub_8bit_hi_phony
4883 0, // sub_16bit
4884 0, // sub_16bit_hi
4885 0, // sub_32bit
4886 0, // sub_mask_0
4887 0, // sub_mask_1
4888 0, // sub_xmm
4889 0, // sub_ymm
4890 },
4891 { // GR8_NOREX2
4892 0, // sub_8bit
4893 0, // sub_8bit_hi
4894 0, // sub_8bit_hi_phony
4895 0, // sub_16bit
4896 0, // sub_16bit_hi
4897 0, // sub_32bit
4898 0, // sub_mask_0
4899 0, // sub_mask_1
4900 0, // sub_xmm
4901 0, // sub_ymm
4902 },
4903 { // GR8_NOREX
4904 0, // sub_8bit
4905 0, // sub_8bit_hi
4906 0, // sub_8bit_hi_phony
4907 0, // sub_16bit
4908 0, // sub_16bit_hi
4909 0, // sub_32bit
4910 0, // sub_mask_0
4911 0, // sub_mask_1
4912 0, // sub_xmm
4913 0, // sub_ymm
4914 },
4915 { // GR8_ABCD_H
4916 0, // sub_8bit
4917 0, // sub_8bit_hi
4918 0, // sub_8bit_hi_phony
4919 0, // sub_16bit
4920 0, // sub_16bit_hi
4921 0, // sub_32bit
4922 0, // sub_mask_0
4923 0, // sub_mask_1
4924 0, // sub_xmm
4925 0, // sub_ymm
4926 },
4927 { // GR8_ABCD_L
4928 0, // sub_8bit
4929 0, // sub_8bit_hi
4930 0, // sub_8bit_hi_phony
4931 0, // sub_16bit
4932 0, // sub_16bit_hi
4933 0, // sub_32bit
4934 0, // sub_mask_0
4935 0, // sub_mask_1
4936 0, // sub_xmm
4937 0, // sub_ymm
4938 },
4939 { // GRH16
4940 0, // sub_8bit
4941 0, // sub_8bit_hi
4942 0, // sub_8bit_hi_phony
4943 0, // sub_16bit
4944 0, // sub_16bit_hi
4945 0, // sub_32bit
4946 0, // sub_mask_0
4947 0, // sub_mask_1
4948 0, // sub_xmm
4949 0, // sub_ymm
4950 },
4951 { // GR16
4952 8, // sub_8bit -> GR16
4953 22, // sub_8bit_hi -> GR16_ABCD
4954 0, // sub_8bit_hi_phony
4955 0, // sub_16bit
4956 0, // sub_16bit_hi
4957 0, // sub_32bit
4958 0, // sub_mask_0
4959 0, // sub_mask_1
4960 0, // sub_xmm
4961 0, // sub_ymm
4962 },
4963 { // GR16_NOREX2
4964 9, // sub_8bit -> GR16_NOREX2
4965 22, // sub_8bit_hi -> GR16_ABCD
4966 0, // sub_8bit_hi_phony
4967 0, // sub_16bit
4968 0, // sub_16bit_hi
4969 0, // sub_32bit
4970 0, // sub_mask_0
4971 0, // sub_mask_1
4972 0, // sub_xmm
4973 0, // sub_ymm
4974 },
4975 { // GR16_NOREX
4976 10, // sub_8bit -> GR16_NOREX
4977 22, // sub_8bit_hi -> GR16_ABCD
4978 0, // sub_8bit_hi_phony
4979 0, // sub_16bit
4980 0, // sub_16bit_hi
4981 0, // sub_32bit
4982 0, // sub_mask_0
4983 0, // sub_mask_1
4984 0, // sub_xmm
4985 0, // sub_ymm
4986 },
4987 { // VK1
4988 0, // sub_8bit
4989 0, // sub_8bit_hi
4990 0, // sub_8bit_hi_phony
4991 0, // sub_16bit
4992 0, // sub_16bit_hi
4993 0, // sub_32bit
4994 0, // sub_mask_0
4995 0, // sub_mask_1
4996 0, // sub_xmm
4997 0, // sub_ymm
4998 },
4999 { // VK16
5000 0, // sub_8bit
5001 0, // sub_8bit_hi
5002 0, // sub_8bit_hi_phony
5003 0, // sub_16bit
5004 0, // sub_16bit_hi
5005 0, // sub_32bit
5006 0, // sub_mask_0
5007 0, // sub_mask_1
5008 0, // sub_xmm
5009 0, // sub_ymm
5010 },
5011 { // VK2
5012 0, // sub_8bit
5013 0, // sub_8bit_hi
5014 0, // sub_8bit_hi_phony
5015 0, // sub_16bit
5016 0, // sub_16bit_hi
5017 0, // sub_32bit
5018 0, // sub_mask_0
5019 0, // sub_mask_1
5020 0, // sub_xmm
5021 0, // sub_ymm
5022 },
5023 { // VK4
5024 0, // sub_8bit
5025 0, // sub_8bit_hi
5026 0, // sub_8bit_hi_phony
5027 0, // sub_16bit
5028 0, // sub_16bit_hi
5029 0, // sub_32bit
5030 0, // sub_mask_0
5031 0, // sub_mask_1
5032 0, // sub_xmm
5033 0, // sub_ymm
5034 },
5035 { // VK8
5036 0, // sub_8bit
5037 0, // sub_8bit_hi
5038 0, // sub_8bit_hi_phony
5039 0, // sub_16bit
5040 0, // sub_16bit_hi
5041 0, // sub_32bit
5042 0, // sub_mask_0
5043 0, // sub_mask_1
5044 0, // sub_xmm
5045 0, // sub_ymm
5046 },
5047 { // VK16WM
5048 0, // sub_8bit
5049 0, // sub_8bit_hi
5050 0, // sub_8bit_hi_phony
5051 0, // sub_16bit
5052 0, // sub_16bit_hi
5053 0, // sub_32bit
5054 0, // sub_mask_0
5055 0, // sub_mask_1
5056 0, // sub_xmm
5057 0, // sub_ymm
5058 },
5059 { // VK1WM
5060 0, // sub_8bit
5061 0, // sub_8bit_hi
5062 0, // sub_8bit_hi_phony
5063 0, // sub_16bit
5064 0, // sub_16bit_hi
5065 0, // sub_32bit
5066 0, // sub_mask_0
5067 0, // sub_mask_1
5068 0, // sub_xmm
5069 0, // sub_ymm
5070 },
5071 { // VK2WM
5072 0, // sub_8bit
5073 0, // sub_8bit_hi
5074 0, // sub_8bit_hi_phony
5075 0, // sub_16bit
5076 0, // sub_16bit_hi
5077 0, // sub_32bit
5078 0, // sub_mask_0
5079 0, // sub_mask_1
5080 0, // sub_xmm
5081 0, // sub_ymm
5082 },
5083 { // VK4WM
5084 0, // sub_8bit
5085 0, // sub_8bit_hi
5086 0, // sub_8bit_hi_phony
5087 0, // sub_16bit
5088 0, // sub_16bit_hi
5089 0, // sub_32bit
5090 0, // sub_mask_0
5091 0, // sub_mask_1
5092 0, // sub_xmm
5093 0, // sub_ymm
5094 },
5095 { // VK8WM
5096 0, // sub_8bit
5097 0, // sub_8bit_hi
5098 0, // sub_8bit_hi_phony
5099 0, // sub_16bit
5100 0, // sub_16bit_hi
5101 0, // sub_32bit
5102 0, // sub_mask_0
5103 0, // sub_mask_1
5104 0, // sub_xmm
5105 0, // sub_ymm
5106 },
5107 { // SEGMENT_REG
5108 0, // sub_8bit
5109 0, // sub_8bit_hi
5110 0, // sub_8bit_hi_phony
5111 0, // sub_16bit
5112 0, // sub_16bit_hi
5113 0, // sub_32bit
5114 0, // sub_mask_0
5115 0, // sub_mask_1
5116 0, // sub_xmm
5117 0, // sub_ymm
5118 },
5119 { // GR16_ABCD
5120 22, // sub_8bit -> GR16_ABCD
5121 22, // sub_8bit_hi -> GR16_ABCD
5122 0, // sub_8bit_hi_phony
5123 0, // sub_16bit
5124 0, // sub_16bit_hi
5125 0, // sub_32bit
5126 0, // sub_mask_0
5127 0, // sub_mask_1
5128 0, // sub_xmm
5129 0, // sub_ymm
5130 },
5131 { // FPCCR
5132 0, // sub_8bit
5133 0, // sub_8bit_hi
5134 0, // sub_8bit_hi_phony
5135 0, // sub_16bit
5136 0, // sub_16bit_hi
5137 0, // sub_32bit
5138 0, // sub_mask_0
5139 0, // sub_mask_1
5140 0, // sub_xmm
5141 0, // sub_ymm
5142 },
5143 { // FR16X
5144 0, // sub_8bit
5145 0, // sub_8bit_hi
5146 0, // sub_8bit_hi_phony
5147 0, // sub_16bit
5148 0, // sub_16bit_hi
5149 0, // sub_32bit
5150 0, // sub_mask_0
5151 0, // sub_mask_1
5152 0, // sub_xmm
5153 0, // sub_ymm
5154 },
5155 { // FR16
5156 0, // sub_8bit
5157 0, // sub_8bit_hi
5158 0, // sub_8bit_hi_phony
5159 0, // sub_16bit
5160 0, // sub_16bit_hi
5161 0, // sub_32bit
5162 0, // sub_mask_0
5163 0, // sub_mask_1
5164 0, // sub_xmm
5165 0, // sub_ymm
5166 },
5167 { // VK16PAIR
5168 0, // sub_8bit
5169 0, // sub_8bit_hi
5170 0, // sub_8bit_hi_phony
5171 0, // sub_16bit
5172 0, // sub_16bit_hi
5173 0, // sub_32bit
5174 26, // sub_mask_0 -> VK16PAIR
5175 26, // sub_mask_1 -> VK16PAIR
5176 0, // sub_xmm
5177 0, // sub_ymm
5178 },
5179 { // VK1PAIR
5180 0, // sub_8bit
5181 0, // sub_8bit_hi
5182 0, // sub_8bit_hi_phony
5183 0, // sub_16bit
5184 0, // sub_16bit_hi
5185 0, // sub_32bit
5186 27, // sub_mask_0 -> VK1PAIR
5187 27, // sub_mask_1 -> VK1PAIR
5188 0, // sub_xmm
5189 0, // sub_ymm
5190 },
5191 { // VK2PAIR
5192 0, // sub_8bit
5193 0, // sub_8bit_hi
5194 0, // sub_8bit_hi_phony
5195 0, // sub_16bit
5196 0, // sub_16bit_hi
5197 0, // sub_32bit
5198 28, // sub_mask_0 -> VK2PAIR
5199 28, // sub_mask_1 -> VK2PAIR
5200 0, // sub_xmm
5201 0, // sub_ymm
5202 },
5203 { // VK4PAIR
5204 0, // sub_8bit
5205 0, // sub_8bit_hi
5206 0, // sub_8bit_hi_phony
5207 0, // sub_16bit
5208 0, // sub_16bit_hi
5209 0, // sub_32bit
5210 29, // sub_mask_0 -> VK4PAIR
5211 29, // sub_mask_1 -> VK4PAIR
5212 0, // sub_xmm
5213 0, // sub_ymm
5214 },
5215 { // VK8PAIR
5216 0, // sub_8bit
5217 0, // sub_8bit_hi
5218 0, // sub_8bit_hi_phony
5219 0, // sub_16bit
5220 0, // sub_16bit_hi
5221 0, // sub_32bit
5222 30, // sub_mask_0 -> VK8PAIR
5223 30, // sub_mask_1 -> VK8PAIR
5224 0, // sub_xmm
5225 0, // sub_ymm
5226 },
5227 { // VK1PAIR_with_sub_mask_0_in_VK1WM
5228 0, // sub_8bit
5229 0, // sub_8bit_hi
5230 0, // sub_8bit_hi_phony
5231 0, // sub_16bit
5232 0, // sub_16bit_hi
5233 0, // sub_32bit
5234 31, // sub_mask_0 -> VK1PAIR_with_sub_mask_0_in_VK1WM
5235 31, // sub_mask_1 -> VK1PAIR_with_sub_mask_0_in_VK1WM
5236 0, // sub_xmm
5237 0, // sub_ymm
5238 },
5239 { // LOW32_ADDR_ACCESS_RBP
5240 34, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
5241 49, // sub_8bit_hi -> GR32_ABCD
5242 0, // sub_8bit_hi_phony
5243 32, // sub_16bit -> LOW32_ADDR_ACCESS_RBP
5244 32, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP
5245 60, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
5246 0, // sub_mask_0
5247 0, // sub_mask_1
5248 0, // sub_xmm
5249 0, // sub_ymm
5250 },
5251 { // LOW32_ADDR_ACCESS
5252 36, // sub_8bit -> GR32
5253 49, // sub_8bit_hi -> GR32_ABCD
5254 0, // sub_8bit_hi_phony
5255 33, // sub_16bit -> LOW32_ADDR_ACCESS
5256 33, // sub_16bit_hi -> LOW32_ADDR_ACCESS
5257 71, // sub_32bit -> LOW32_ADDR_ACCESS_with_sub_32bit
5258 0, // sub_mask_0
5259 0, // sub_mask_1
5260 0, // sub_xmm
5261 0, // sub_ymm
5262 },
5263 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
5264 34, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
5265 49, // sub_8bit_hi -> GR32_ABCD
5266 0, // sub_8bit_hi_phony
5267 34, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
5268 34, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
5269 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5270 0, // sub_mask_0
5271 0, // sub_mask_1
5272 0, // sub_xmm
5273 0, // sub_ymm
5274 },
5275 { // FR32X
5276 0, // sub_8bit
5277 0, // sub_8bit_hi
5278 0, // sub_8bit_hi_phony
5279 0, // sub_16bit
5280 0, // sub_16bit_hi
5281 0, // sub_32bit
5282 0, // sub_mask_0
5283 0, // sub_mask_1
5284 0, // sub_xmm
5285 0, // sub_ymm
5286 },
5287 { // GR32
5288 36, // sub_8bit -> GR32
5289 49, // sub_8bit_hi -> GR32_ABCD
5290 0, // sub_8bit_hi_phony
5291 36, // sub_16bit -> GR32
5292 36, // sub_16bit_hi -> GR32
5293 0, // sub_32bit
5294 0, // sub_mask_0
5295 0, // sub_mask_1
5296 0, // sub_xmm
5297 0, // sub_ymm
5298 },
5299 { // GR32_NOSP
5300 37, // sub_8bit -> GR32_NOSP
5301 49, // sub_8bit_hi -> GR32_ABCD
5302 0, // sub_8bit_hi_phony
5303 37, // sub_16bit -> GR32_NOSP
5304 37, // sub_16bit_hi -> GR32_NOSP
5305 0, // sub_32bit
5306 0, // sub_mask_0
5307 0, // sub_mask_1
5308 0, // sub_xmm
5309 0, // sub_ymm
5310 },
5311 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
5312 38, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
5313 49, // sub_8bit_hi -> GR32_ABCD
5314 0, // sub_8bit_hi_phony
5315 38, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
5316 38, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
5317 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5318 0, // sub_mask_0
5319 0, // sub_mask_1
5320 0, // sub_xmm
5321 0, // sub_ymm
5322 },
5323 { // DEBUG_REG
5324 0, // sub_8bit
5325 0, // sub_8bit_hi
5326 0, // sub_8bit_hi_phony
5327 0, // sub_16bit
5328 0, // sub_16bit_hi
5329 0, // sub_32bit
5330 0, // sub_mask_0
5331 0, // sub_mask_1
5332 0, // sub_xmm
5333 0, // sub_ymm
5334 },
5335 { // FR32
5336 0, // sub_8bit
5337 0, // sub_8bit_hi
5338 0, // sub_8bit_hi_phony
5339 0, // sub_16bit
5340 0, // sub_16bit_hi
5341 0, // sub_32bit
5342 0, // sub_mask_0
5343 0, // sub_mask_1
5344 0, // sub_xmm
5345 0, // sub_ymm
5346 },
5347 { // GR32_NOREX2
5348 41, // sub_8bit -> GR32_NOREX2
5349 49, // sub_8bit_hi -> GR32_ABCD
5350 0, // sub_8bit_hi_phony
5351 41, // sub_16bit -> GR32_NOREX2
5352 41, // sub_16bit_hi -> GR32_NOREX2
5353 0, // sub_32bit
5354 0, // sub_mask_0
5355 0, // sub_mask_1
5356 0, // sub_xmm
5357 0, // sub_ymm
5358 },
5359 { // GR32_NOREX2_NOSP
5360 42, // sub_8bit -> GR32_NOREX2_NOSP
5361 49, // sub_8bit_hi -> GR32_ABCD
5362 0, // sub_8bit_hi_phony
5363 42, // sub_16bit -> GR32_NOREX2_NOSP
5364 42, // sub_16bit_hi -> GR32_NOREX2_NOSP
5365 0, // sub_32bit
5366 0, // sub_mask_0
5367 0, // sub_mask_1
5368 0, // sub_xmm
5369 0, // sub_ymm
5370 },
5371 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
5372 43, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
5373 49, // sub_8bit_hi -> GR32_ABCD
5374 0, // sub_8bit_hi_phony
5375 43, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
5376 43, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
5377 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5378 0, // sub_mask_0
5379 0, // sub_mask_1
5380 0, // sub_xmm
5381 0, // sub_ymm
5382 },
5383 { // GR32_NOREX
5384 44, // sub_8bit -> GR32_NOREX
5385 49, // sub_8bit_hi -> GR32_ABCD
5386 0, // sub_8bit_hi_phony
5387 44, // sub_16bit -> GR32_NOREX
5388 44, // sub_16bit_hi -> GR32_NOREX
5389 0, // sub_32bit
5390 0, // sub_mask_0
5391 0, // sub_mask_1
5392 0, // sub_xmm
5393 0, // sub_ymm
5394 },
5395 { // VK32
5396 0, // sub_8bit
5397 0, // sub_8bit_hi
5398 0, // sub_8bit_hi_phony
5399 0, // sub_16bit
5400 0, // sub_16bit_hi
5401 0, // sub_32bit
5402 0, // sub_mask_0
5403 0, // sub_mask_1
5404 0, // sub_xmm
5405 0, // sub_ymm
5406 },
5407 { // GR32_NOREX_NOSP
5408 46, // sub_8bit -> GR32_NOREX_NOSP
5409 49, // sub_8bit_hi -> GR32_ABCD
5410 0, // sub_8bit_hi_phony
5411 46, // sub_16bit -> GR32_NOREX_NOSP
5412 46, // sub_16bit_hi -> GR32_NOREX_NOSP
5413 0, // sub_32bit
5414 0, // sub_mask_0
5415 0, // sub_mask_1
5416 0, // sub_xmm
5417 0, // sub_ymm
5418 },
5419 { // RFP32
5420 0, // sub_8bit
5421 0, // sub_8bit_hi
5422 0, // sub_8bit_hi_phony
5423 0, // sub_16bit
5424 0, // sub_16bit_hi
5425 0, // sub_32bit
5426 0, // sub_mask_0
5427 0, // sub_mask_1
5428 0, // sub_xmm
5429 0, // sub_ymm
5430 },
5431 { // VK32WM
5432 0, // sub_8bit
5433 0, // sub_8bit_hi
5434 0, // sub_8bit_hi_phony
5435 0, // sub_16bit
5436 0, // sub_16bit_hi
5437 0, // sub_32bit
5438 0, // sub_mask_0
5439 0, // sub_mask_1
5440 0, // sub_xmm
5441 0, // sub_ymm
5442 },
5443 { // GR32_ABCD
5444 49, // sub_8bit -> GR32_ABCD
5445 49, // sub_8bit_hi -> GR32_ABCD
5446 0, // sub_8bit_hi_phony
5447 49, // sub_16bit -> GR32_ABCD
5448 49, // sub_16bit_hi -> GR32_ABCD
5449 0, // sub_32bit
5450 0, // sub_mask_0
5451 0, // sub_mask_1
5452 0, // sub_xmm
5453 0, // sub_ymm
5454 },
5455 { // GR32_TC
5456 50, // sub_8bit -> GR32_TC
5457 51, // sub_8bit_hi -> GR32_ABCD_and_GR32_TC
5458 0, // sub_8bit_hi_phony
5459 50, // sub_16bit -> GR32_TC
5460 50, // sub_16bit_hi -> GR32_TC
5461 0, // sub_32bit
5462 0, // sub_mask_0
5463 0, // sub_mask_1
5464 0, // sub_xmm
5465 0, // sub_ymm
5466 },
5467 { // GR32_ABCD_and_GR32_TC
5468 51, // sub_8bit -> GR32_ABCD_and_GR32_TC
5469 51, // sub_8bit_hi -> GR32_ABCD_and_GR32_TC
5470 0, // sub_8bit_hi_phony
5471 51, // sub_16bit -> GR32_ABCD_and_GR32_TC
5472 51, // sub_16bit_hi -> GR32_ABCD_and_GR32_TC
5473 0, // sub_32bit
5474 0, // sub_mask_0
5475 0, // sub_mask_1
5476 0, // sub_xmm
5477 0, // sub_ymm
5478 },
5479 { // GR32_AD
5480 52, // sub_8bit -> GR32_AD
5481 52, // sub_8bit_hi -> GR32_AD
5482 0, // sub_8bit_hi_phony
5483 52, // sub_16bit -> GR32_AD
5484 52, // sub_16bit_hi -> GR32_AD
5485 0, // sub_32bit
5486 0, // sub_mask_0
5487 0, // sub_mask_1
5488 0, // sub_xmm
5489 0, // sub_ymm
5490 },
5491 { // GR32_ArgRef
5492 53, // sub_8bit -> GR32_ArgRef
5493 53, // sub_8bit_hi -> GR32_ArgRef
5494 0, // sub_8bit_hi_phony
5495 53, // sub_16bit -> GR32_ArgRef
5496 53, // sub_16bit_hi -> GR32_ArgRef
5497 0, // sub_32bit
5498 0, // sub_mask_0
5499 0, // sub_mask_1
5500 0, // sub_xmm
5501 0, // sub_ymm
5502 },
5503 { // GR32_BPSP
5504 54, // sub_8bit -> GR32_BPSP
5505 0, // sub_8bit_hi
5506 54, // sub_8bit_hi_phony -> GR32_BPSP
5507 54, // sub_16bit -> GR32_BPSP
5508 54, // sub_16bit_hi -> GR32_BPSP
5509 0, // sub_32bit
5510 0, // sub_mask_0
5511 0, // sub_mask_1
5512 0, // sub_xmm
5513 0, // sub_ymm
5514 },
5515 { // GR32_BSI
5516 55, // sub_8bit -> GR32_BSI
5517 63, // sub_8bit_hi -> GR32_ABCD_and_GR32_BSI
5518 0, // sub_8bit_hi_phony
5519 55, // sub_16bit -> GR32_BSI
5520 55, // sub_16bit_hi -> GR32_BSI
5521 0, // sub_32bit
5522 0, // sub_mask_0
5523 0, // sub_mask_1
5524 0, // sub_xmm
5525 0, // sub_ymm
5526 },
5527 { // GR32_CB
5528 56, // sub_8bit -> GR32_CB
5529 56, // sub_8bit_hi -> GR32_CB
5530 0, // sub_8bit_hi_phony
5531 56, // sub_16bit -> GR32_CB
5532 56, // sub_16bit_hi -> GR32_CB
5533 0, // sub_32bit
5534 0, // sub_mask_0
5535 0, // sub_mask_1
5536 0, // sub_xmm
5537 0, // sub_ymm
5538 },
5539 { // GR32_DC
5540 57, // sub_8bit -> GR32_DC
5541 57, // sub_8bit_hi -> GR32_DC
5542 0, // sub_8bit_hi_phony
5543 57, // sub_16bit -> GR32_DC
5544 57, // sub_16bit_hi -> GR32_DC
5545 0, // sub_32bit
5546 0, // sub_mask_0
5547 0, // sub_mask_1
5548 0, // sub_xmm
5549 0, // sub_ymm
5550 },
5551 { // GR32_DIBP
5552 58, // sub_8bit -> GR32_DIBP
5553 0, // sub_8bit_hi
5554 58, // sub_8bit_hi_phony -> GR32_DIBP
5555 58, // sub_16bit -> GR32_DIBP
5556 58, // sub_16bit_hi -> GR32_DIBP
5557 0, // sub_32bit
5558 0, // sub_mask_0
5559 0, // sub_mask_1
5560 0, // sub_xmm
5561 0, // sub_ymm
5562 },
5563 { // GR32_SIDI
5564 59, // sub_8bit -> GR32_SIDI
5565 0, // sub_8bit_hi
5566 59, // sub_8bit_hi_phony -> GR32_SIDI
5567 59, // sub_16bit -> GR32_SIDI
5568 59, // sub_16bit_hi -> GR32_SIDI
5569 0, // sub_32bit
5570 0, // sub_mask_0
5571 0, // sub_mask_1
5572 0, // sub_xmm
5573 0, // sub_ymm
5574 },
5575 { // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
5576 70, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5577 0, // sub_8bit_hi
5578 0, // sub_8bit_hi_phony
5579 60, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
5580 60, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
5581 60, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
5582 0, // sub_mask_0
5583 0, // sub_mask_1
5584 0, // sub_xmm
5585 0, // sub_ymm
5586 },
5587 { // CCR
5588 0, // sub_8bit
5589 0, // sub_8bit_hi
5590 0, // sub_8bit_hi_phony
5591 0, // sub_16bit
5592 0, // sub_16bit_hi
5593 0, // sub_32bit
5594 0, // sub_mask_0
5595 0, // sub_mask_1
5596 0, // sub_xmm
5597 0, // sub_ymm
5598 },
5599 { // DFCCR
5600 0, // sub_8bit
5601 0, // sub_8bit_hi
5602 0, // sub_8bit_hi_phony
5603 0, // sub_16bit
5604 0, // sub_16bit_hi
5605 0, // sub_32bit
5606 0, // sub_mask_0
5607 0, // sub_mask_1
5608 0, // sub_xmm
5609 0, // sub_ymm
5610 },
5611 { // GR32_ABCD_and_GR32_BSI
5612 63, // sub_8bit -> GR32_ABCD_and_GR32_BSI
5613 63, // sub_8bit_hi -> GR32_ABCD_and_GR32_BSI
5614 0, // sub_8bit_hi_phony
5615 63, // sub_16bit -> GR32_ABCD_and_GR32_BSI
5616 63, // sub_16bit_hi -> GR32_ABCD_and_GR32_BSI
5617 0, // sub_32bit
5618 0, // sub_mask_0
5619 0, // sub_mask_1
5620 0, // sub_xmm
5621 0, // sub_ymm
5622 },
5623 { // GR32_AD_and_GR32_ArgRef
5624 64, // sub_8bit -> GR32_AD_and_GR32_ArgRef
5625 64, // sub_8bit_hi -> GR32_AD_and_GR32_ArgRef
5626 0, // sub_8bit_hi_phony
5627 64, // sub_16bit -> GR32_AD_and_GR32_ArgRef
5628 64, // sub_16bit_hi -> GR32_AD_and_GR32_ArgRef
5629 0, // sub_32bit
5630 0, // sub_mask_0
5631 0, // sub_mask_1
5632 0, // sub_xmm
5633 0, // sub_ymm
5634 },
5635 { // GR32_ArgRef_and_GR32_CB
5636 65, // sub_8bit -> GR32_ArgRef_and_GR32_CB
5637 65, // sub_8bit_hi -> GR32_ArgRef_and_GR32_CB
5638 0, // sub_8bit_hi_phony
5639 65, // sub_16bit -> GR32_ArgRef_and_GR32_CB
5640 65, // sub_16bit_hi -> GR32_ArgRef_and_GR32_CB
5641 0, // sub_32bit
5642 0, // sub_mask_0
5643 0, // sub_mask_1
5644 0, // sub_xmm
5645 0, // sub_ymm
5646 },
5647 { // GR32_BPSP_and_GR32_DIBP
5648 66, // sub_8bit -> GR32_BPSP_and_GR32_DIBP
5649 0, // sub_8bit_hi
5650 66, // sub_8bit_hi_phony -> GR32_BPSP_and_GR32_DIBP
5651 66, // sub_16bit -> GR32_BPSP_and_GR32_DIBP
5652 66, // sub_16bit_hi -> GR32_BPSP_and_GR32_DIBP
5653 0, // sub_32bit
5654 0, // sub_mask_0
5655 0, // sub_mask_1
5656 0, // sub_xmm
5657 0, // sub_ymm
5658 },
5659 { // GR32_BPSP_and_GR32_TC
5660 67, // sub_8bit -> GR32_BPSP_and_GR32_TC
5661 0, // sub_8bit_hi
5662 67, // sub_8bit_hi_phony -> GR32_BPSP_and_GR32_TC
5663 67, // sub_16bit -> GR32_BPSP_and_GR32_TC
5664 67, // sub_16bit_hi -> GR32_BPSP_and_GR32_TC
5665 0, // sub_32bit
5666 0, // sub_mask_0
5667 0, // sub_mask_1
5668 0, // sub_xmm
5669 0, // sub_ymm
5670 },
5671 { // GR32_BSI_and_GR32_SIDI
5672 68, // sub_8bit -> GR32_BSI_and_GR32_SIDI
5673 0, // sub_8bit_hi
5674 68, // sub_8bit_hi_phony -> GR32_BSI_and_GR32_SIDI
5675 68, // sub_16bit -> GR32_BSI_and_GR32_SIDI
5676 68, // sub_16bit_hi -> GR32_BSI_and_GR32_SIDI
5677 0, // sub_32bit
5678 0, // sub_mask_0
5679 0, // sub_mask_1
5680 0, // sub_xmm
5681 0, // sub_ymm
5682 },
5683 { // GR32_DIBP_and_GR32_SIDI
5684 69, // sub_8bit -> GR32_DIBP_and_GR32_SIDI
5685 0, // sub_8bit_hi
5686 69, // sub_8bit_hi_phony -> GR32_DIBP_and_GR32_SIDI
5687 69, // sub_16bit -> GR32_DIBP_and_GR32_SIDI
5688 69, // sub_16bit_hi -> GR32_DIBP_and_GR32_SIDI
5689 0, // sub_32bit
5690 0, // sub_mask_0
5691 0, // sub_mask_1
5692 0, // sub_xmm
5693 0, // sub_ymm
5694 },
5695 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5696 70, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5697 0, // sub_8bit_hi
5698 70, // sub_8bit_hi_phony -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5699 70, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5700 70, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5701 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5702 0, // sub_mask_0
5703 0, // sub_mask_1
5704 0, // sub_xmm
5705 0, // sub_ymm
5706 },
5707 { // LOW32_ADDR_ACCESS_with_sub_32bit
5708 0, // sub_8bit
5709 0, // sub_8bit_hi
5710 0, // sub_8bit_hi_phony
5711 71, // sub_16bit -> LOW32_ADDR_ACCESS_with_sub_32bit
5712 71, // sub_16bit_hi -> LOW32_ADDR_ACCESS_with_sub_32bit
5713 71, // sub_32bit -> LOW32_ADDR_ACCESS_with_sub_32bit
5714 0, // sub_mask_0
5715 0, // sub_mask_1
5716 0, // sub_xmm
5717 0, // sub_ymm
5718 },
5719 { // RFP64
5720 0, // sub_8bit
5721 0, // sub_8bit_hi
5722 0, // sub_8bit_hi_phony
5723 0, // sub_16bit
5724 0, // sub_16bit_hi
5725 0, // sub_32bit
5726 0, // sub_mask_0
5727 0, // sub_mask_1
5728 0, // sub_xmm
5729 0, // sub_ymm
5730 },
5731 { // GR64
5732 75, // sub_8bit -> GR64_with_sub_8bit
5733 104, // sub_8bit_hi -> GR64_ABCD
5734 0, // sub_8bit_hi_phony
5735 73, // sub_16bit -> GR64
5736 73, // sub_16bit_hi -> GR64
5737 73, // sub_32bit -> GR64
5738 0, // sub_mask_0
5739 0, // sub_mask_1
5740 0, // sub_xmm
5741 0, // sub_ymm
5742 },
5743 { // FR64X
5744 0, // sub_8bit
5745 0, // sub_8bit_hi
5746 0, // sub_8bit_hi_phony
5747 0, // sub_16bit
5748 0, // sub_16bit_hi
5749 0, // sub_32bit
5750 0, // sub_mask_0
5751 0, // sub_mask_1
5752 0, // sub_xmm
5753 0, // sub_ymm
5754 },
5755 { // GR64_with_sub_8bit
5756 75, // sub_8bit -> GR64_with_sub_8bit
5757 104, // sub_8bit_hi -> GR64_ABCD
5758 0, // sub_8bit_hi_phony
5759 75, // sub_16bit -> GR64_with_sub_8bit
5760 75, // sub_16bit_hi -> GR64_with_sub_8bit
5761 75, // sub_32bit -> GR64_with_sub_8bit
5762 0, // sub_mask_0
5763 0, // sub_mask_1
5764 0, // sub_xmm
5765 0, // sub_ymm
5766 },
5767 { // GR64_NOSP
5768 76, // sub_8bit -> GR64_NOSP
5769 104, // sub_8bit_hi -> GR64_ABCD
5770 0, // sub_8bit_hi_phony
5771 76, // sub_16bit -> GR64_NOSP
5772 76, // sub_16bit_hi -> GR64_NOSP
5773 76, // sub_32bit -> GR64_NOSP
5774 0, // sub_mask_0
5775 0, // sub_mask_1
5776 0, // sub_xmm
5777 0, // sub_ymm
5778 },
5779 { // GR64_NOREX2
5780 80, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX2
5781 104, // sub_8bit_hi -> GR64_ABCD
5782 0, // sub_8bit_hi_phony
5783 77, // sub_16bit -> GR64_NOREX2
5784 77, // sub_16bit_hi -> GR64_NOREX2
5785 77, // sub_32bit -> GR64_NOREX2
5786 0, // sub_mask_0
5787 0, // sub_mask_1
5788 0, // sub_xmm
5789 0, // sub_ymm
5790 },
5791 { // CONTROL_REG
5792 0, // sub_8bit
5793 0, // sub_8bit_hi
5794 0, // sub_8bit_hi_phony
5795 0, // sub_16bit
5796 0, // sub_16bit_hi
5797 0, // sub_32bit
5798 0, // sub_mask_0
5799 0, // sub_mask_1
5800 0, // sub_xmm
5801 0, // sub_ymm
5802 },
5803 { // FR64
5804 0, // sub_8bit
5805 0, // sub_8bit_hi
5806 0, // sub_8bit_hi_phony
5807 0, // sub_16bit
5808 0, // sub_16bit_hi
5809 0, // sub_32bit
5810 0, // sub_mask_0
5811 0, // sub_mask_1
5812 0, // sub_xmm
5813 0, // sub_ymm
5814 },
5815 { // GR64_with_sub_16bit_in_GR16_NOREX2
5816 80, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX2
5817 104, // sub_8bit_hi -> GR64_ABCD
5818 0, // sub_8bit_hi_phony
5819 80, // sub_16bit -> GR64_with_sub_16bit_in_GR16_NOREX2
5820 80, // sub_16bit_hi -> GR64_with_sub_16bit_in_GR16_NOREX2
5821 80, // sub_32bit -> GR64_with_sub_16bit_in_GR16_NOREX2
5822 0, // sub_mask_0
5823 0, // sub_mask_1
5824 0, // sub_xmm
5825 0, // sub_ymm
5826 },
5827 { // GR64_NOREX2_NOSP
5828 81, // sub_8bit -> GR64_NOREX2_NOSP
5829 104, // sub_8bit_hi -> GR64_ABCD
5830 0, // sub_8bit_hi_phony
5831 81, // sub_16bit -> GR64_NOREX2_NOSP
5832 81, // sub_16bit_hi -> GR64_NOREX2_NOSP
5833 81, // sub_32bit -> GR64_NOREX2_NOSP
5834 0, // sub_mask_0
5835 0, // sub_mask_1
5836 0, // sub_xmm
5837 0, // sub_ymm
5838 },
5839 { // GR64PLTSafe
5840 82, // sub_8bit -> GR64PLTSafe
5841 104, // sub_8bit_hi -> GR64_ABCD
5842 0, // sub_8bit_hi_phony
5843 82, // sub_16bit -> GR64PLTSafe
5844 82, // sub_16bit_hi -> GR64PLTSafe
5845 82, // sub_32bit -> GR64PLTSafe
5846 0, // sub_mask_0
5847 0, // sub_mask_1
5848 0, // sub_xmm
5849 0, // sub_ymm
5850 },
5851 { // GR64_TC
5852 86, // sub_8bit -> GR64_TC_with_sub_8bit
5853 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5854 0, // sub_8bit_hi_phony
5855 83, // sub_16bit -> GR64_TC
5856 83, // sub_16bit_hi -> GR64_TC
5857 83, // sub_32bit -> GR64_TC
5858 0, // sub_mask_0
5859 0, // sub_mask_1
5860 0, // sub_xmm
5861 0, // sub_ymm
5862 },
5863 { // GR64_NOREX
5864 90, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX
5865 104, // sub_8bit_hi -> GR64_ABCD
5866 0, // sub_8bit_hi_phony
5867 84, // sub_16bit -> GR64_NOREX
5868 84, // sub_16bit_hi -> GR64_NOREX
5869 84, // sub_32bit -> GR64_NOREX
5870 0, // sub_mask_0
5871 0, // sub_mask_1
5872 0, // sub_xmm
5873 0, // sub_ymm
5874 },
5875 { // GR64_TCW64
5876 88, // sub_8bit -> GR64_TCW64_with_sub_8bit
5877 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5878 0, // sub_8bit_hi_phony
5879 85, // sub_16bit -> GR64_TCW64
5880 85, // sub_16bit_hi -> GR64_TCW64
5881 85, // sub_32bit -> GR64_TCW64
5882 0, // sub_mask_0
5883 0, // sub_mask_1
5884 0, // sub_xmm
5885 0, // sub_ymm
5886 },
5887 { // GR64_TC_with_sub_8bit
5888 86, // sub_8bit -> GR64_TC_with_sub_8bit
5889 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5890 0, // sub_8bit_hi_phony
5891 86, // sub_16bit -> GR64_TC_with_sub_8bit
5892 86, // sub_16bit_hi -> GR64_TC_with_sub_8bit
5893 86, // sub_32bit -> GR64_TC_with_sub_8bit
5894 0, // sub_mask_0
5895 0, // sub_mask_1
5896 0, // sub_xmm
5897 0, // sub_ymm
5898 },
5899 { // GR64_NOREX2_NOSP_and_GR64_TC
5900 87, // sub_8bit -> GR64_NOREX2_NOSP_and_GR64_TC
5901 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5902 0, // sub_8bit_hi_phony
5903 87, // sub_16bit -> GR64_NOREX2_NOSP_and_GR64_TC
5904 87, // sub_16bit_hi -> GR64_NOREX2_NOSP_and_GR64_TC
5905 87, // sub_32bit -> GR64_NOREX2_NOSP_and_GR64_TC
5906 0, // sub_mask_0
5907 0, // sub_mask_1
5908 0, // sub_xmm
5909 0, // sub_ymm
5910 },
5911 { // GR64_TCW64_with_sub_8bit
5912 88, // sub_8bit -> GR64_TCW64_with_sub_8bit
5913 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5914 0, // sub_8bit_hi_phony
5915 88, // sub_16bit -> GR64_TCW64_with_sub_8bit
5916 88, // sub_16bit_hi -> GR64_TCW64_with_sub_8bit
5917 88, // sub_32bit -> GR64_TCW64_with_sub_8bit
5918 0, // sub_mask_0
5919 0, // sub_mask_1
5920 0, // sub_xmm
5921 0, // sub_ymm
5922 },
5923 { // GR64_TC_and_GR64_TCW64
5924 97, // sub_8bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
5925 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5926 0, // sub_8bit_hi_phony
5927 89, // sub_16bit -> GR64_TC_and_GR64_TCW64
5928 89, // sub_16bit_hi -> GR64_TC_and_GR64_TCW64
5929 89, // sub_32bit -> GR64_TC_and_GR64_TCW64
5930 0, // sub_mask_0
5931 0, // sub_mask_1
5932 0, // sub_xmm
5933 0, // sub_ymm
5934 },
5935 { // GR64_with_sub_16bit_in_GR16_NOREX
5936 90, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX
5937 104, // sub_8bit_hi -> GR64_ABCD
5938 0, // sub_8bit_hi_phony
5939 90, // sub_16bit -> GR64_with_sub_16bit_in_GR16_NOREX
5940 90, // sub_16bit_hi -> GR64_with_sub_16bit_in_GR16_NOREX
5941 90, // sub_32bit -> GR64_with_sub_16bit_in_GR16_NOREX
5942 0, // sub_mask_0
5943 0, // sub_mask_1
5944 0, // sub_xmm
5945 0, // sub_ymm
5946 },
5947 { // VK64
5948 0, // sub_8bit
5949 0, // sub_8bit_hi
5950 0, // sub_8bit_hi_phony
5951 0, // sub_16bit
5952 0, // sub_16bit_hi
5953 0, // sub_32bit
5954 0, // sub_mask_0
5955 0, // sub_mask_1
5956 0, // sub_xmm
5957 0, // sub_ymm
5958 },
5959 { // VR64
5960 0, // sub_8bit
5961 0, // sub_8bit_hi
5962 0, // sub_8bit_hi_phony
5963 0, // sub_16bit
5964 0, // sub_16bit_hi
5965 0, // sub_32bit
5966 0, // sub_mask_0
5967 0, // sub_mask_1
5968 0, // sub_xmm
5969 0, // sub_ymm
5970 },
5971 { // GR64PLTSafe_and_GR64_TC
5972 93, // sub_8bit -> GR64PLTSafe_and_GR64_TC
5973 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5974 0, // sub_8bit_hi_phony
5975 93, // sub_16bit -> GR64PLTSafe_and_GR64_TC
5976 93, // sub_16bit_hi -> GR64PLTSafe_and_GR64_TC
5977 93, // sub_32bit -> GR64PLTSafe_and_GR64_TC
5978 0, // sub_mask_0
5979 0, // sub_mask_1
5980 0, // sub_xmm
5981 0, // sub_ymm
5982 },
5983 { // GR64_NOREX2_NOSP_and_GR64_TCW64
5984 94, // sub_8bit -> GR64_NOREX2_NOSP_and_GR64_TCW64
5985 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5986 0, // sub_8bit_hi_phony
5987 94, // sub_16bit -> GR64_NOREX2_NOSP_and_GR64_TCW64
5988 94, // sub_16bit_hi -> GR64_NOREX2_NOSP_and_GR64_TCW64
5989 94, // sub_32bit -> GR64_NOREX2_NOSP_and_GR64_TCW64
5990 0, // sub_mask_0
5991 0, // sub_mask_1
5992 0, // sub_xmm
5993 0, // sub_ymm
5994 },
5995 { // GR64_NOREX_NOSP
5996 95, // sub_8bit -> GR64_NOREX_NOSP
5997 104, // sub_8bit_hi -> GR64_ABCD
5998 0, // sub_8bit_hi_phony
5999 95, // sub_16bit -> GR64_NOREX_NOSP
6000 95, // sub_16bit_hi -> GR64_NOREX_NOSP
6001 95, // sub_32bit -> GR64_NOREX_NOSP
6002 0, // sub_mask_0
6003 0, // sub_mask_1
6004 0, // sub_xmm
6005 0, // sub_ymm
6006 },
6007 { // GR64_NOREX_and_GR64_TC
6008 100, // sub_8bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
6009 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
6010 0, // sub_8bit_hi_phony
6011 96, // sub_16bit -> GR64_NOREX_and_GR64_TC
6012 96, // sub_16bit_hi -> GR64_NOREX_and_GR64_TC
6013 96, // sub_32bit -> GR64_NOREX_and_GR64_TC
6014 0, // sub_mask_0
6015 0, // sub_mask_1
6016 0, // sub_xmm
6017 0, // sub_ymm
6018 },
6019 { // GR64_TCW64_and_GR64_TC_with_sub_8bit
6020 97, // sub_8bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
6021 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
6022 0, // sub_8bit_hi_phony
6023 97, // sub_16bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
6024 97, // sub_16bit_hi -> GR64_TCW64_and_GR64_TC_with_sub_8bit
6025 97, // sub_32bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
6026 0, // sub_mask_0
6027 0, // sub_mask_1
6028 0, // sub_xmm
6029 0, // sub_ymm
6030 },
6031 { // VK64WM
6032 0, // sub_8bit
6033 0, // sub_8bit_hi
6034 0, // sub_8bit_hi_phony
6035 0, // sub_16bit
6036 0, // sub_16bit_hi
6037 0, // sub_32bit
6038 0, // sub_mask_0
6039 0, // sub_mask_1
6040 0, // sub_xmm
6041 0, // sub_ymm
6042 },
6043 { // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
6044 99, // sub_8bit -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
6045 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
6046 0, // sub_8bit_hi_phony
6047 99, // sub_16bit -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
6048 99, // sub_16bit_hi -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
6049 99, // sub_32bit -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
6050 0, // sub_mask_0
6051 0, // sub_mask_1
6052 0, // sub_xmm
6053 0, // sub_ymm
6054 },
6055 { // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
6056 100, // sub_8bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
6057 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
6058 0, // sub_8bit_hi_phony
6059 100, // sub_16bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
6060 100, // sub_16bit_hi -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
6061 100, // sub_32bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
6062 0, // sub_mask_0
6063 0, // sub_mask_1
6064 0, // sub_xmm
6065 0, // sub_ymm
6066 },
6067 { // GR64PLTSafe_and_GR64_TCW64
6068 101, // sub_8bit -> GR64PLTSafe_and_GR64_TCW64
6069 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
6070 0, // sub_8bit_hi_phony
6071 101, // sub_16bit -> GR64PLTSafe_and_GR64_TCW64
6072 101, // sub_16bit_hi -> GR64PLTSafe_and_GR64_TCW64
6073 101, // sub_32bit -> GR64PLTSafe_and_GR64_TCW64
6074 0, // sub_mask_0
6075 0, // sub_mask_1
6076 0, // sub_xmm
6077 0, // sub_ymm
6078 },
6079 { // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
6080 102, // sub_8bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
6081 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
6082 0, // sub_8bit_hi_phony
6083 102, // sub_16bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
6084 102, // sub_16bit_hi -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
6085 102, // sub_32bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
6086 0, // sub_mask_0
6087 0, // sub_mask_1
6088 0, // sub_xmm
6089 0, // sub_ymm
6090 },
6091 { // GR64_NOREX_and_GR64_TCW64
6092 105, // sub_8bit -> GR64_with_sub_32bit_in_GR32_TC
6093 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
6094 0, // sub_8bit_hi_phony
6095 103, // sub_16bit -> GR64_NOREX_and_GR64_TCW64
6096 103, // sub_16bit_hi -> GR64_NOREX_and_GR64_TCW64
6097 103, // sub_32bit -> GR64_NOREX_and_GR64_TCW64
6098 0, // sub_mask_0
6099 0, // sub_mask_1
6100 0, // sub_xmm
6101 0, // sub_ymm
6102 },
6103 { // GR64_ABCD
6104 104, // sub_8bit -> GR64_ABCD
6105 104, // sub_8bit_hi -> GR64_ABCD
6106 0, // sub_8bit_hi_phony
6107 104, // sub_16bit -> GR64_ABCD
6108 104, // sub_16bit_hi -> GR64_ABCD
6109 104, // sub_32bit -> GR64_ABCD
6110 0, // sub_mask_0
6111 0, // sub_mask_1
6112 0, // sub_xmm
6113 0, // sub_ymm
6114 },
6115 { // GR64_with_sub_32bit_in_GR32_TC
6116 105, // sub_8bit -> GR64_with_sub_32bit_in_GR32_TC
6117 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
6118 0, // sub_8bit_hi_phony
6119 105, // sub_16bit -> GR64_with_sub_32bit_in_GR32_TC
6120 105, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_TC
6121 105, // sub_32bit -> GR64_with_sub_32bit_in_GR32_TC
6122 0, // sub_mask_0
6123 0, // sub_mask_1
6124 0, // sub_xmm
6125 0, // sub_ymm
6126 },
6127 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
6128 106, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
6129 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
6130 0, // sub_8bit_hi_phony
6131 106, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
6132 106, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
6133 106, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
6134 0, // sub_mask_0
6135 0, // sub_mask_1
6136 0, // sub_xmm
6137 0, // sub_ymm
6138 },
6139 { // GR64_AD
6140 107, // sub_8bit -> GR64_AD
6141 107, // sub_8bit_hi -> GR64_AD
6142 0, // sub_8bit_hi_phony
6143 107, // sub_16bit -> GR64_AD
6144 107, // sub_16bit_hi -> GR64_AD
6145 107, // sub_32bit -> GR64_AD
6146 0, // sub_mask_0
6147 0, // sub_mask_1
6148 0, // sub_xmm
6149 0, // sub_ymm
6150 },
6151 { // GR64_ArgRef
6152 108, // sub_8bit -> GR64_ArgRef
6153 0, // sub_8bit_hi
6154 108, // sub_8bit_hi_phony -> GR64_ArgRef
6155 108, // sub_16bit -> GR64_ArgRef
6156 108, // sub_16bit_hi -> GR64_ArgRef
6157 108, // sub_32bit -> GR64_ArgRef
6158 0, // sub_mask_0
6159 0, // sub_mask_1
6160 0, // sub_xmm
6161 0, // sub_ymm
6162 },
6163 { // GR64_and_LOW32_ADDR_ACCESS_RBP
6164 122, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
6165 0, // sub_8bit_hi
6166 0, // sub_8bit_hi_phony
6167 109, // sub_16bit -> GR64_and_LOW32_ADDR_ACCESS_RBP
6168 109, // sub_16bit_hi -> GR64_and_LOW32_ADDR_ACCESS_RBP
6169 109, // sub_32bit -> GR64_and_LOW32_ADDR_ACCESS_RBP
6170 0, // sub_mask_0
6171 0, // sub_mask_1
6172 0, // sub_xmm
6173 0, // sub_ymm
6174 },
6175 { // GR64_with_sub_32bit_in_GR32_ArgRef
6176 110, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ArgRef
6177 110, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef
6178 0, // sub_8bit_hi_phony
6179 110, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ArgRef
6180 110, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef
6181 110, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ArgRef
6182 0, // sub_mask_0
6183 0, // sub_mask_1
6184 0, // sub_xmm
6185 0, // sub_ymm
6186 },
6187 { // GR64_with_sub_32bit_in_GR32_BPSP
6188 111, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP
6189 0, // sub_8bit_hi
6190 111, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BPSP
6191 111, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP
6192 111, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BPSP
6193 111, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP
6194 0, // sub_mask_0
6195 0, // sub_mask_1
6196 0, // sub_xmm
6197 0, // sub_ymm
6198 },
6199 { // GR64_with_sub_32bit_in_GR32_BSI
6200 112, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BSI
6201 119, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
6202 0, // sub_8bit_hi_phony
6203 112, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BSI
6204 112, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BSI
6205 112, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BSI
6206 0, // sub_mask_0
6207 0, // sub_mask_1
6208 0, // sub_xmm
6209 0, // sub_ymm
6210 },
6211 { // GR64_with_sub_32bit_in_GR32_CB
6212 113, // sub_8bit -> GR64_with_sub_32bit_in_GR32_CB
6213 113, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_CB
6214 0, // sub_8bit_hi_phony
6215 113, // sub_16bit -> GR64_with_sub_32bit_in_GR32_CB
6216 113, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_CB
6217 113, // sub_32bit -> GR64_with_sub_32bit_in_GR32_CB
6218 0, // sub_mask_0
6219 0, // sub_mask_1
6220 0, // sub_xmm
6221 0, // sub_ymm
6222 },
6223 { // GR64_with_sub_32bit_in_GR32_DIBP
6224 114, // sub_8bit -> GR64_with_sub_32bit_in_GR32_DIBP
6225 0, // sub_8bit_hi
6226 114, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_DIBP
6227 114, // sub_16bit -> GR64_with_sub_32bit_in_GR32_DIBP
6228 114, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_DIBP
6229 114, // sub_32bit -> GR64_with_sub_32bit_in_GR32_DIBP
6230 0, // sub_mask_0
6231 0, // sub_mask_1
6232 0, // sub_xmm
6233 0, // sub_ymm
6234 },
6235 { // GR64_with_sub_32bit_in_GR32_SIDI
6236 115, // sub_8bit -> GR64_with_sub_32bit_in_GR32_SIDI
6237 0, // sub_8bit_hi
6238 115, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_SIDI
6239 115, // sub_16bit -> GR64_with_sub_32bit_in_GR32_SIDI
6240 115, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_SIDI
6241 115, // sub_32bit -> GR64_with_sub_32bit_in_GR32_SIDI
6242 0, // sub_mask_0
6243 0, // sub_mask_1
6244 0, // sub_xmm
6245 0, // sub_ymm
6246 },
6247 { // GR64_A
6248 116, // sub_8bit -> GR64_A
6249 116, // sub_8bit_hi -> GR64_A
6250 0, // sub_8bit_hi_phony
6251 116, // sub_16bit -> GR64_A
6252 116, // sub_16bit_hi -> GR64_A
6253 116, // sub_32bit -> GR64_A
6254 0, // sub_mask_0
6255 0, // sub_mask_1
6256 0, // sub_xmm
6257 0, // sub_ymm
6258 },
6259 { // GR64_ArgRef_and_GR64_TC
6260 117, // sub_8bit -> GR64_ArgRef_and_GR64_TC
6261 0, // sub_8bit_hi
6262 117, // sub_8bit_hi_phony -> GR64_ArgRef_and_GR64_TC
6263 117, // sub_16bit -> GR64_ArgRef_and_GR64_TC
6264 117, // sub_16bit_hi -> GR64_ArgRef_and_GR64_TC
6265 117, // sub_32bit -> GR64_ArgRef_and_GR64_TC
6266 0, // sub_mask_0
6267 0, // sub_mask_1
6268 0, // sub_xmm
6269 0, // sub_ymm
6270 },
6271 { // GR64_and_LOW32_ADDR_ACCESS
6272 0, // sub_8bit
6273 0, // sub_8bit_hi
6274 0, // sub_8bit_hi_phony
6275 118, // sub_16bit -> GR64_and_LOW32_ADDR_ACCESS
6276 118, // sub_16bit_hi -> GR64_and_LOW32_ADDR_ACCESS
6277 118, // sub_32bit -> GR64_and_LOW32_ADDR_ACCESS
6278 0, // sub_mask_0
6279 0, // sub_mask_1
6280 0, // sub_xmm
6281 0, // sub_ymm
6282 },
6283 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
6284 119, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
6285 119, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
6286 0, // sub_8bit_hi_phony
6287 119, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
6288 119, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
6289 119, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
6290 0, // sub_mask_0
6291 0, // sub_mask_1
6292 0, // sub_xmm
6293 0, // sub_ymm
6294 },
6295 { // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
6296 120, // sub_8bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
6297 120, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
6298 0, // sub_8bit_hi_phony
6299 120, // sub_16bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
6300 120, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
6301 120, // sub_32bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
6302 0, // sub_mask_0
6303 0, // sub_mask_1
6304 0, // sub_xmm
6305 0, // sub_ymm
6306 },
6307 { // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
6308 121, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
6309 121, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
6310 0, // sub_8bit_hi_phony
6311 121, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
6312 121, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
6313 121, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
6314 0, // sub_mask_0
6315 0, // sub_mask_1
6316 0, // sub_xmm
6317 0, // sub_ymm
6318 },
6319 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
6320 122, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
6321 0, // sub_8bit_hi
6322 122, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
6323 122, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
6324 122, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
6325 122, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
6326 0, // sub_mask_0
6327 0, // sub_mask_1
6328 0, // sub_xmm
6329 0, // sub_ymm
6330 },
6331 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
6332 123, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
6333 0, // sub_8bit_hi
6334 123, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
6335 123, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
6336 123, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
6337 123, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
6338 0, // sub_mask_0
6339 0, // sub_mask_1
6340 0, // sub_xmm
6341 0, // sub_ymm
6342 },
6343 { // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
6344 124, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
6345 0, // sub_8bit_hi
6346 124, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
6347 124, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
6348 124, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
6349 124, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
6350 0, // sub_mask_0
6351 0, // sub_mask_1
6352 0, // sub_xmm
6353 0, // sub_ymm
6354 },
6355 { // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
6356 125, // sub_8bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
6357 0, // sub_8bit_hi
6358 125, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
6359 125, // sub_16bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
6360 125, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
6361 125, // sub_32bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
6362 0, // sub_mask_0
6363 0, // sub_mask_1
6364 0, // sub_xmm
6365 0, // sub_ymm
6366 },
6367 { // RST
6368 0, // sub_8bit
6369 0, // sub_8bit_hi
6370 0, // sub_8bit_hi_phony
6371 0, // sub_16bit
6372 0, // sub_16bit_hi
6373 0, // sub_32bit
6374 0, // sub_mask_0
6375 0, // sub_mask_1
6376 0, // sub_xmm
6377 0, // sub_ymm
6378 },
6379 { // RFP80
6380 0, // sub_8bit
6381 0, // sub_8bit_hi
6382 0, // sub_8bit_hi_phony
6383 0, // sub_16bit
6384 0, // sub_16bit_hi
6385 0, // sub_32bit
6386 0, // sub_mask_0
6387 0, // sub_mask_1
6388 0, // sub_xmm
6389 0, // sub_ymm
6390 },
6391 { // RFP80_7
6392 0, // sub_8bit
6393 0, // sub_8bit_hi
6394 0, // sub_8bit_hi_phony
6395 0, // sub_16bit
6396 0, // sub_16bit_hi
6397 0, // sub_32bit
6398 0, // sub_mask_0
6399 0, // sub_mask_1
6400 0, // sub_xmm
6401 0, // sub_ymm
6402 },
6403 { // VR128X
6404 0, // sub_8bit
6405 0, // sub_8bit_hi
6406 0, // sub_8bit_hi_phony
6407 0, // sub_16bit
6408 0, // sub_16bit_hi
6409 0, // sub_32bit
6410 0, // sub_mask_0
6411 0, // sub_mask_1
6412 0, // sub_xmm
6413 0, // sub_ymm
6414 },
6415 { // VR128
6416 0, // sub_8bit
6417 0, // sub_8bit_hi
6418 0, // sub_8bit_hi_phony
6419 0, // sub_16bit
6420 0, // sub_16bit_hi
6421 0, // sub_32bit
6422 0, // sub_mask_0
6423 0, // sub_mask_1
6424 0, // sub_xmm
6425 0, // sub_ymm
6426 },
6427 { // VR256X
6428 0, // sub_8bit
6429 0, // sub_8bit_hi
6430 0, // sub_8bit_hi_phony
6431 0, // sub_16bit
6432 0, // sub_16bit_hi
6433 0, // sub_32bit
6434 0, // sub_mask_0
6435 0, // sub_mask_1
6436 131, // sub_xmm -> VR256X
6437 0, // sub_ymm
6438 },
6439 { // VR256
6440 0, // sub_8bit
6441 0, // sub_8bit_hi
6442 0, // sub_8bit_hi_phony
6443 0, // sub_16bit
6444 0, // sub_16bit_hi
6445 0, // sub_32bit
6446 0, // sub_mask_0
6447 0, // sub_mask_1
6448 132, // sub_xmm -> VR256
6449 0, // sub_ymm
6450 },
6451 { // VR512
6452 0, // sub_8bit
6453 0, // sub_8bit_hi
6454 0, // sub_8bit_hi_phony
6455 0, // sub_16bit
6456 0, // sub_16bit_hi
6457 0, // sub_32bit
6458 0, // sub_mask_0
6459 0, // sub_mask_1
6460 133, // sub_xmm -> VR512
6461 133, // sub_ymm -> VR512
6462 },
6463 { // VR512_0_15
6464 0, // sub_8bit
6465 0, // sub_8bit_hi
6466 0, // sub_8bit_hi_phony
6467 0, // sub_16bit
6468 0, // sub_16bit_hi
6469 0, // sub_32bit
6470 0, // sub_mask_0
6471 0, // sub_mask_1
6472 134, // sub_xmm -> VR512_0_15
6473 134, // sub_ymm -> VR512_0_15
6474 },
6475 { // TILE
6476 0, // sub_8bit
6477 0, // sub_8bit_hi
6478 0, // sub_8bit_hi_phony
6479 0, // sub_16bit
6480 0, // sub_16bit_hi
6481 0, // sub_32bit
6482 0, // sub_mask_0
6483 0, // sub_mask_1
6484 0, // sub_xmm
6485 0, // sub_ymm
6486 },
6487
6488 };
6489 assert(RC && "Missing regclass");
6490 if (!Idx) return RC;
6491 --Idx;
6492 assert(Idx < 10 && "Bad subreg");
6493 unsigned TV = Table[RC->getID()][Idx];
6494 return TV ? getRegClass(i: TV - 1) : nullptr;
6495}const TargetRegisterClass *X86GenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
6496 static constexpr uint8_t Table[135][10] = {
6497 { // GR8
6498 0, // GR8:sub_8bit
6499 0, // GR8:sub_8bit_hi
6500 0, // GR8:sub_8bit_hi_phony
6501 0, // GR8:sub_16bit
6502 0, // GR8:sub_16bit_hi
6503 0, // GR8:sub_32bit
6504 0, // GR8:sub_mask_0
6505 0, // GR8:sub_mask_1
6506 0, // GR8:sub_xmm
6507 0, // GR8:sub_ymm
6508 },
6509 { // GRH8
6510 0, // GRH8:sub_8bit
6511 0, // GRH8:sub_8bit_hi
6512 0, // GRH8:sub_8bit_hi_phony
6513 0, // GRH8:sub_16bit
6514 0, // GRH8:sub_16bit_hi
6515 0, // GRH8:sub_32bit
6516 0, // GRH8:sub_mask_0
6517 0, // GRH8:sub_mask_1
6518 0, // GRH8:sub_xmm
6519 0, // GRH8:sub_ymm
6520 },
6521 { // GR8_NOREX2
6522 0, // GR8_NOREX2:sub_8bit
6523 0, // GR8_NOREX2:sub_8bit_hi
6524 0, // GR8_NOREX2:sub_8bit_hi_phony
6525 0, // GR8_NOREX2:sub_16bit
6526 0, // GR8_NOREX2:sub_16bit_hi
6527 0, // GR8_NOREX2:sub_32bit
6528 0, // GR8_NOREX2:sub_mask_0
6529 0, // GR8_NOREX2:sub_mask_1
6530 0, // GR8_NOREX2:sub_xmm
6531 0, // GR8_NOREX2:sub_ymm
6532 },
6533 { // GR8_NOREX
6534 0, // GR8_NOREX:sub_8bit
6535 0, // GR8_NOREX:sub_8bit_hi
6536 0, // GR8_NOREX:sub_8bit_hi_phony
6537 0, // GR8_NOREX:sub_16bit
6538 0, // GR8_NOREX:sub_16bit_hi
6539 0, // GR8_NOREX:sub_32bit
6540 0, // GR8_NOREX:sub_mask_0
6541 0, // GR8_NOREX:sub_mask_1
6542 0, // GR8_NOREX:sub_xmm
6543 0, // GR8_NOREX:sub_ymm
6544 },
6545 { // GR8_ABCD_H
6546 0, // GR8_ABCD_H:sub_8bit
6547 0, // GR8_ABCD_H:sub_8bit_hi
6548 0, // GR8_ABCD_H:sub_8bit_hi_phony
6549 0, // GR8_ABCD_H:sub_16bit
6550 0, // GR8_ABCD_H:sub_16bit_hi
6551 0, // GR8_ABCD_H:sub_32bit
6552 0, // GR8_ABCD_H:sub_mask_0
6553 0, // GR8_ABCD_H:sub_mask_1
6554 0, // GR8_ABCD_H:sub_xmm
6555 0, // GR8_ABCD_H:sub_ymm
6556 },
6557 { // GR8_ABCD_L
6558 0, // GR8_ABCD_L:sub_8bit
6559 0, // GR8_ABCD_L:sub_8bit_hi
6560 0, // GR8_ABCD_L:sub_8bit_hi_phony
6561 0, // GR8_ABCD_L:sub_16bit
6562 0, // GR8_ABCD_L:sub_16bit_hi
6563 0, // GR8_ABCD_L:sub_32bit
6564 0, // GR8_ABCD_L:sub_mask_0
6565 0, // GR8_ABCD_L:sub_mask_1
6566 0, // GR8_ABCD_L:sub_xmm
6567 0, // GR8_ABCD_L:sub_ymm
6568 },
6569 { // GRH16
6570 0, // GRH16:sub_8bit
6571 0, // GRH16:sub_8bit_hi
6572 0, // GRH16:sub_8bit_hi_phony
6573 0, // GRH16:sub_16bit
6574 0, // GRH16:sub_16bit_hi
6575 0, // GRH16:sub_32bit
6576 0, // GRH16:sub_mask_0
6577 0, // GRH16:sub_mask_1
6578 0, // GRH16:sub_xmm
6579 0, // GRH16:sub_ymm
6580 },
6581 { // GR16
6582 1, // GR16:sub_8bit -> GR8
6583 5, // GR16:sub_8bit_hi -> GR8_ABCD_H
6584 0, // GR16:sub_8bit_hi_phony
6585 0, // GR16:sub_16bit
6586 0, // GR16:sub_16bit_hi
6587 0, // GR16:sub_32bit
6588 0, // GR16:sub_mask_0
6589 0, // GR16:sub_mask_1
6590 0, // GR16:sub_xmm
6591 0, // GR16:sub_ymm
6592 },
6593 { // GR16_NOREX2
6594 3, // GR16_NOREX2:sub_8bit -> GR8_NOREX2
6595 5, // GR16_NOREX2:sub_8bit_hi -> GR8_ABCD_H
6596 0, // GR16_NOREX2:sub_8bit_hi_phony
6597 0, // GR16_NOREX2:sub_16bit
6598 0, // GR16_NOREX2:sub_16bit_hi
6599 0, // GR16_NOREX2:sub_32bit
6600 0, // GR16_NOREX2:sub_mask_0
6601 0, // GR16_NOREX2:sub_mask_1
6602 0, // GR16_NOREX2:sub_xmm
6603 0, // GR16_NOREX2:sub_ymm
6604 },
6605 { // GR16_NOREX
6606 3, // GR16_NOREX:sub_8bit -> GR8_NOREX2
6607 5, // GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
6608 0, // GR16_NOREX:sub_8bit_hi_phony
6609 0, // GR16_NOREX:sub_16bit
6610 0, // GR16_NOREX:sub_16bit_hi
6611 0, // GR16_NOREX:sub_32bit
6612 0, // GR16_NOREX:sub_mask_0
6613 0, // GR16_NOREX:sub_mask_1
6614 0, // GR16_NOREX:sub_xmm
6615 0, // GR16_NOREX:sub_ymm
6616 },
6617 { // VK1
6618 0, // VK1:sub_8bit
6619 0, // VK1:sub_8bit_hi
6620 0, // VK1:sub_8bit_hi_phony
6621 0, // VK1:sub_16bit
6622 0, // VK1:sub_16bit_hi
6623 0, // VK1:sub_32bit
6624 0, // VK1:sub_mask_0
6625 0, // VK1:sub_mask_1
6626 0, // VK1:sub_xmm
6627 0, // VK1:sub_ymm
6628 },
6629 { // VK16
6630 0, // VK16:sub_8bit
6631 0, // VK16:sub_8bit_hi
6632 0, // VK16:sub_8bit_hi_phony
6633 0, // VK16:sub_16bit
6634 0, // VK16:sub_16bit_hi
6635 0, // VK16:sub_32bit
6636 0, // VK16:sub_mask_0
6637 0, // VK16:sub_mask_1
6638 0, // VK16:sub_xmm
6639 0, // VK16:sub_ymm
6640 },
6641 { // VK2
6642 0, // VK2:sub_8bit
6643 0, // VK2:sub_8bit_hi
6644 0, // VK2:sub_8bit_hi_phony
6645 0, // VK2:sub_16bit
6646 0, // VK2:sub_16bit_hi
6647 0, // VK2:sub_32bit
6648 0, // VK2:sub_mask_0
6649 0, // VK2:sub_mask_1
6650 0, // VK2:sub_xmm
6651 0, // VK2:sub_ymm
6652 },
6653 { // VK4
6654 0, // VK4:sub_8bit
6655 0, // VK4:sub_8bit_hi
6656 0, // VK4:sub_8bit_hi_phony
6657 0, // VK4:sub_16bit
6658 0, // VK4:sub_16bit_hi
6659 0, // VK4:sub_32bit
6660 0, // VK4:sub_mask_0
6661 0, // VK4:sub_mask_1
6662 0, // VK4:sub_xmm
6663 0, // VK4:sub_ymm
6664 },
6665 { // VK8
6666 0, // VK8:sub_8bit
6667 0, // VK8:sub_8bit_hi
6668 0, // VK8:sub_8bit_hi_phony
6669 0, // VK8:sub_16bit
6670 0, // VK8:sub_16bit_hi
6671 0, // VK8:sub_32bit
6672 0, // VK8:sub_mask_0
6673 0, // VK8:sub_mask_1
6674 0, // VK8:sub_xmm
6675 0, // VK8:sub_ymm
6676 },
6677 { // VK16WM
6678 0, // VK16WM:sub_8bit
6679 0, // VK16WM:sub_8bit_hi
6680 0, // VK16WM:sub_8bit_hi_phony
6681 0, // VK16WM:sub_16bit
6682 0, // VK16WM:sub_16bit_hi
6683 0, // VK16WM:sub_32bit
6684 0, // VK16WM:sub_mask_0
6685 0, // VK16WM:sub_mask_1
6686 0, // VK16WM:sub_xmm
6687 0, // VK16WM:sub_ymm
6688 },
6689 { // VK1WM
6690 0, // VK1WM:sub_8bit
6691 0, // VK1WM:sub_8bit_hi
6692 0, // VK1WM:sub_8bit_hi_phony
6693 0, // VK1WM:sub_16bit
6694 0, // VK1WM:sub_16bit_hi
6695 0, // VK1WM:sub_32bit
6696 0, // VK1WM:sub_mask_0
6697 0, // VK1WM:sub_mask_1
6698 0, // VK1WM:sub_xmm
6699 0, // VK1WM:sub_ymm
6700 },
6701 { // VK2WM
6702 0, // VK2WM:sub_8bit
6703 0, // VK2WM:sub_8bit_hi
6704 0, // VK2WM:sub_8bit_hi_phony
6705 0, // VK2WM:sub_16bit
6706 0, // VK2WM:sub_16bit_hi
6707 0, // VK2WM:sub_32bit
6708 0, // VK2WM:sub_mask_0
6709 0, // VK2WM:sub_mask_1
6710 0, // VK2WM:sub_xmm
6711 0, // VK2WM:sub_ymm
6712 },
6713 { // VK4WM
6714 0, // VK4WM:sub_8bit
6715 0, // VK4WM:sub_8bit_hi
6716 0, // VK4WM:sub_8bit_hi_phony
6717 0, // VK4WM:sub_16bit
6718 0, // VK4WM:sub_16bit_hi
6719 0, // VK4WM:sub_32bit
6720 0, // VK4WM:sub_mask_0
6721 0, // VK4WM:sub_mask_1
6722 0, // VK4WM:sub_xmm
6723 0, // VK4WM:sub_ymm
6724 },
6725 { // VK8WM
6726 0, // VK8WM:sub_8bit
6727 0, // VK8WM:sub_8bit_hi
6728 0, // VK8WM:sub_8bit_hi_phony
6729 0, // VK8WM:sub_16bit
6730 0, // VK8WM:sub_16bit_hi
6731 0, // VK8WM:sub_32bit
6732 0, // VK8WM:sub_mask_0
6733 0, // VK8WM:sub_mask_1
6734 0, // VK8WM:sub_xmm
6735 0, // VK8WM:sub_ymm
6736 },
6737 { // SEGMENT_REG
6738 0, // SEGMENT_REG:sub_8bit
6739 0, // SEGMENT_REG:sub_8bit_hi
6740 0, // SEGMENT_REG:sub_8bit_hi_phony
6741 0, // SEGMENT_REG:sub_16bit
6742 0, // SEGMENT_REG:sub_16bit_hi
6743 0, // SEGMENT_REG:sub_32bit
6744 0, // SEGMENT_REG:sub_mask_0
6745 0, // SEGMENT_REG:sub_mask_1
6746 0, // SEGMENT_REG:sub_xmm
6747 0, // SEGMENT_REG:sub_ymm
6748 },
6749 { // GR16_ABCD
6750 6, // GR16_ABCD:sub_8bit -> GR8_ABCD_L
6751 5, // GR16_ABCD:sub_8bit_hi -> GR8_ABCD_H
6752 0, // GR16_ABCD:sub_8bit_hi_phony
6753 0, // GR16_ABCD:sub_16bit
6754 0, // GR16_ABCD:sub_16bit_hi
6755 0, // GR16_ABCD:sub_32bit
6756 0, // GR16_ABCD:sub_mask_0
6757 0, // GR16_ABCD:sub_mask_1
6758 0, // GR16_ABCD:sub_xmm
6759 0, // GR16_ABCD:sub_ymm
6760 },
6761 { // FPCCR
6762 0, // FPCCR:sub_8bit
6763 0, // FPCCR:sub_8bit_hi
6764 0, // FPCCR:sub_8bit_hi_phony
6765 0, // FPCCR:sub_16bit
6766 0, // FPCCR:sub_16bit_hi
6767 0, // FPCCR:sub_32bit
6768 0, // FPCCR:sub_mask_0
6769 0, // FPCCR:sub_mask_1
6770 0, // FPCCR:sub_xmm
6771 0, // FPCCR:sub_ymm
6772 },
6773 { // FR16X
6774 0, // FR16X:sub_8bit
6775 0, // FR16X:sub_8bit_hi
6776 0, // FR16X:sub_8bit_hi_phony
6777 0, // FR16X:sub_16bit
6778 0, // FR16X:sub_16bit_hi
6779 0, // FR16X:sub_32bit
6780 0, // FR16X:sub_mask_0
6781 0, // FR16X:sub_mask_1
6782 0, // FR16X:sub_xmm
6783 0, // FR16X:sub_ymm
6784 },
6785 { // FR16
6786 0, // FR16:sub_8bit
6787 0, // FR16:sub_8bit_hi
6788 0, // FR16:sub_8bit_hi_phony
6789 0, // FR16:sub_16bit
6790 0, // FR16:sub_16bit_hi
6791 0, // FR16:sub_32bit
6792 0, // FR16:sub_mask_0
6793 0, // FR16:sub_mask_1
6794 0, // FR16:sub_xmm
6795 0, // FR16:sub_ymm
6796 },
6797 { // VK16PAIR
6798 0, // VK16PAIR:sub_8bit
6799 0, // VK16PAIR:sub_8bit_hi
6800 0, // VK16PAIR:sub_8bit_hi_phony
6801 0, // VK16PAIR:sub_16bit
6802 0, // VK16PAIR:sub_16bit_hi
6803 0, // VK16PAIR:sub_32bit
6804 91, // VK16PAIR:sub_mask_0 -> VK64
6805 98, // VK16PAIR:sub_mask_1 -> VK64WM
6806 0, // VK16PAIR:sub_xmm
6807 0, // VK16PAIR:sub_ymm
6808 },
6809 { // VK1PAIR
6810 0, // VK1PAIR:sub_8bit
6811 0, // VK1PAIR:sub_8bit_hi
6812 0, // VK1PAIR:sub_8bit_hi_phony
6813 0, // VK1PAIR:sub_16bit
6814 0, // VK1PAIR:sub_16bit_hi
6815 0, // VK1PAIR:sub_32bit
6816 91, // VK1PAIR:sub_mask_0 -> VK64
6817 98, // VK1PAIR:sub_mask_1 -> VK64WM
6818 0, // VK1PAIR:sub_xmm
6819 0, // VK1PAIR:sub_ymm
6820 },
6821 { // VK2PAIR
6822 0, // VK2PAIR:sub_8bit
6823 0, // VK2PAIR:sub_8bit_hi
6824 0, // VK2PAIR:sub_8bit_hi_phony
6825 0, // VK2PAIR:sub_16bit
6826 0, // VK2PAIR:sub_16bit_hi
6827 0, // VK2PAIR:sub_32bit
6828 91, // VK2PAIR:sub_mask_0 -> VK64
6829 98, // VK2PAIR:sub_mask_1 -> VK64WM
6830 0, // VK2PAIR:sub_xmm
6831 0, // VK2PAIR:sub_ymm
6832 },
6833 { // VK4PAIR
6834 0, // VK4PAIR:sub_8bit
6835 0, // VK4PAIR:sub_8bit_hi
6836 0, // VK4PAIR:sub_8bit_hi_phony
6837 0, // VK4PAIR:sub_16bit
6838 0, // VK4PAIR:sub_16bit_hi
6839 0, // VK4PAIR:sub_32bit
6840 91, // VK4PAIR:sub_mask_0 -> VK64
6841 98, // VK4PAIR:sub_mask_1 -> VK64WM
6842 0, // VK4PAIR:sub_xmm
6843 0, // VK4PAIR:sub_ymm
6844 },
6845 { // VK8PAIR
6846 0, // VK8PAIR:sub_8bit
6847 0, // VK8PAIR:sub_8bit_hi
6848 0, // VK8PAIR:sub_8bit_hi_phony
6849 0, // VK8PAIR:sub_16bit
6850 0, // VK8PAIR:sub_16bit_hi
6851 0, // VK8PAIR:sub_32bit
6852 91, // VK8PAIR:sub_mask_0 -> VK64
6853 98, // VK8PAIR:sub_mask_1 -> VK64WM
6854 0, // VK8PAIR:sub_xmm
6855 0, // VK8PAIR:sub_ymm
6856 },
6857 { // VK1PAIR_with_sub_mask_0_in_VK1WM
6858 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_8bit
6859 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_8bit_hi
6860 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_8bit_hi_phony
6861 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_16bit
6862 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_16bit_hi
6863 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_32bit
6864 98, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_mask_0 -> VK64WM
6865 98, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_mask_1 -> VK64WM
6866 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_xmm
6867 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_ymm
6868 },
6869 { // LOW32_ADDR_ACCESS_RBP
6870 1, // LOW32_ADDR_ACCESS_RBP:sub_8bit -> GR8
6871 5, // LOW32_ADDR_ACCESS_RBP:sub_8bit_hi -> GR8_ABCD_H
6872 0, // LOW32_ADDR_ACCESS_RBP:sub_8bit_hi_phony
6873 8, // LOW32_ADDR_ACCESS_RBP:sub_16bit -> GR16
6874 0, // LOW32_ADDR_ACCESS_RBP:sub_16bit_hi
6875 66, // LOW32_ADDR_ACCESS_RBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
6876 0, // LOW32_ADDR_ACCESS_RBP:sub_mask_0
6877 0, // LOW32_ADDR_ACCESS_RBP:sub_mask_1
6878 0, // LOW32_ADDR_ACCESS_RBP:sub_xmm
6879 0, // LOW32_ADDR_ACCESS_RBP:sub_ymm
6880 },
6881 { // LOW32_ADDR_ACCESS
6882 1, // LOW32_ADDR_ACCESS:sub_8bit -> GR8
6883 5, // LOW32_ADDR_ACCESS:sub_8bit_hi -> GR8_ABCD_H
6884 0, // LOW32_ADDR_ACCESS:sub_8bit_hi_phony
6885 8, // LOW32_ADDR_ACCESS:sub_16bit -> GR16
6886 0, // LOW32_ADDR_ACCESS:sub_16bit_hi
6887 0, // LOW32_ADDR_ACCESS:sub_32bit
6888 0, // LOW32_ADDR_ACCESS:sub_mask_0
6889 0, // LOW32_ADDR_ACCESS:sub_mask_1
6890 0, // LOW32_ADDR_ACCESS:sub_xmm
6891 0, // LOW32_ADDR_ACCESS:sub_ymm
6892 },
6893 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
6894 1, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit -> GR8
6895 5, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
6896 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit_hi_phony
6897 8, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_16bit -> GR16
6898 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_16bit_hi
6899 66, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
6900 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_mask_0
6901 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_mask_1
6902 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_xmm
6903 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_ymm
6904 },
6905 { // FR32X
6906 0, // FR32X:sub_8bit
6907 0, // FR32X:sub_8bit_hi
6908 0, // FR32X:sub_8bit_hi_phony
6909 0, // FR32X:sub_16bit
6910 0, // FR32X:sub_16bit_hi
6911 0, // FR32X:sub_32bit
6912 0, // FR32X:sub_mask_0
6913 0, // FR32X:sub_mask_1
6914 0, // FR32X:sub_xmm
6915 0, // FR32X:sub_ymm
6916 },
6917 { // GR32
6918 1, // GR32:sub_8bit -> GR8
6919 5, // GR32:sub_8bit_hi -> GR8_ABCD_H
6920 0, // GR32:sub_8bit_hi_phony
6921 8, // GR32:sub_16bit -> GR16
6922 0, // GR32:sub_16bit_hi
6923 0, // GR32:sub_32bit
6924 0, // GR32:sub_mask_0
6925 0, // GR32:sub_mask_1
6926 0, // GR32:sub_xmm
6927 0, // GR32:sub_ymm
6928 },
6929 { // GR32_NOSP
6930 1, // GR32_NOSP:sub_8bit -> GR8
6931 5, // GR32_NOSP:sub_8bit_hi -> GR8_ABCD_H
6932 0, // GR32_NOSP:sub_8bit_hi_phony
6933 8, // GR32_NOSP:sub_16bit -> GR16
6934 0, // GR32_NOSP:sub_16bit_hi
6935 0, // GR32_NOSP:sub_32bit
6936 0, // GR32_NOSP:sub_mask_0
6937 0, // GR32_NOSP:sub_mask_1
6938 0, // GR32_NOSP:sub_xmm
6939 0, // GR32_NOSP:sub_ymm
6940 },
6941 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
6942 3, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_8bit -> GR8_NOREX2
6943 5, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi -> GR8_ABCD_H
6944 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi_phony
6945 9, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_16bit -> GR16_NOREX2
6946 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_16bit_hi
6947 66, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_32bit -> GR32_BPSP_and_GR32_DIBP
6948 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_mask_0
6949 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_mask_1
6950 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_xmm
6951 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_ymm
6952 },
6953 { // DEBUG_REG
6954 0, // DEBUG_REG:sub_8bit
6955 0, // DEBUG_REG:sub_8bit_hi
6956 0, // DEBUG_REG:sub_8bit_hi_phony
6957 0, // DEBUG_REG:sub_16bit
6958 0, // DEBUG_REG:sub_16bit_hi
6959 0, // DEBUG_REG:sub_32bit
6960 0, // DEBUG_REG:sub_mask_0
6961 0, // DEBUG_REG:sub_mask_1
6962 0, // DEBUG_REG:sub_xmm
6963 0, // DEBUG_REG:sub_ymm
6964 },
6965 { // FR32
6966 0, // FR32:sub_8bit
6967 0, // FR32:sub_8bit_hi
6968 0, // FR32:sub_8bit_hi_phony
6969 0, // FR32:sub_16bit
6970 0, // FR32:sub_16bit_hi
6971 0, // FR32:sub_32bit
6972 0, // FR32:sub_mask_0
6973 0, // FR32:sub_mask_1
6974 0, // FR32:sub_xmm
6975 0, // FR32:sub_ymm
6976 },
6977 { // GR32_NOREX2
6978 3, // GR32_NOREX2:sub_8bit -> GR8_NOREX2
6979 5, // GR32_NOREX2:sub_8bit_hi -> GR8_ABCD_H
6980 0, // GR32_NOREX2:sub_8bit_hi_phony
6981 9, // GR32_NOREX2:sub_16bit -> GR16_NOREX2
6982 0, // GR32_NOREX2:sub_16bit_hi
6983 0, // GR32_NOREX2:sub_32bit
6984 0, // GR32_NOREX2:sub_mask_0
6985 0, // GR32_NOREX2:sub_mask_1
6986 0, // GR32_NOREX2:sub_xmm
6987 0, // GR32_NOREX2:sub_ymm
6988 },
6989 { // GR32_NOREX2_NOSP
6990 3, // GR32_NOREX2_NOSP:sub_8bit -> GR8_NOREX2
6991 5, // GR32_NOREX2_NOSP:sub_8bit_hi -> GR8_ABCD_H
6992 0, // GR32_NOREX2_NOSP:sub_8bit_hi_phony
6993 9, // GR32_NOREX2_NOSP:sub_16bit -> GR16_NOREX2
6994 0, // GR32_NOREX2_NOSP:sub_16bit_hi
6995 0, // GR32_NOREX2_NOSP:sub_32bit
6996 0, // GR32_NOREX2_NOSP:sub_mask_0
6997 0, // GR32_NOREX2_NOSP:sub_mask_1
6998 0, // GR32_NOREX2_NOSP:sub_xmm
6999 0, // GR32_NOREX2_NOSP:sub_ymm
7000 },
7001 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
7002 3, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8_NOREX2
7003 5, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
7004 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
7005 10, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
7006 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
7007 66, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_BPSP_and_GR32_DIBP
7008 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_mask_0
7009 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_mask_1
7010 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_xmm
7011 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_ymm
7012 },
7013 { // GR32_NOREX
7014 3, // GR32_NOREX:sub_8bit -> GR8_NOREX2
7015 5, // GR32_NOREX:sub_8bit_hi -> GR8_ABCD_H
7016 0, // GR32_NOREX:sub_8bit_hi_phony
7017 10, // GR32_NOREX:sub_16bit -> GR16_NOREX
7018 0, // GR32_NOREX:sub_16bit_hi
7019 0, // GR32_NOREX:sub_32bit
7020 0, // GR32_NOREX:sub_mask_0
7021 0, // GR32_NOREX:sub_mask_1
7022 0, // GR32_NOREX:sub_xmm
7023 0, // GR32_NOREX:sub_ymm
7024 },
7025 { // VK32
7026 0, // VK32:sub_8bit
7027 0, // VK32:sub_8bit_hi
7028 0, // VK32:sub_8bit_hi_phony
7029 0, // VK32:sub_16bit
7030 0, // VK32:sub_16bit_hi
7031 0, // VK32:sub_32bit
7032 0, // VK32:sub_mask_0
7033 0, // VK32:sub_mask_1
7034 0, // VK32:sub_xmm
7035 0, // VK32:sub_ymm
7036 },
7037 { // GR32_NOREX_NOSP
7038 3, // GR32_NOREX_NOSP:sub_8bit -> GR8_NOREX2
7039 5, // GR32_NOREX_NOSP:sub_8bit_hi -> GR8_ABCD_H
7040 0, // GR32_NOREX_NOSP:sub_8bit_hi_phony
7041 10, // GR32_NOREX_NOSP:sub_16bit -> GR16_NOREX
7042 0, // GR32_NOREX_NOSP:sub_16bit_hi
7043 0, // GR32_NOREX_NOSP:sub_32bit
7044 0, // GR32_NOREX_NOSP:sub_mask_0
7045 0, // GR32_NOREX_NOSP:sub_mask_1
7046 0, // GR32_NOREX_NOSP:sub_xmm
7047 0, // GR32_NOREX_NOSP:sub_ymm
7048 },
7049 { // RFP32
7050 0, // RFP32:sub_8bit
7051 0, // RFP32:sub_8bit_hi
7052 0, // RFP32:sub_8bit_hi_phony
7053 0, // RFP32:sub_16bit
7054 0, // RFP32:sub_16bit_hi
7055 0, // RFP32:sub_32bit
7056 0, // RFP32:sub_mask_0
7057 0, // RFP32:sub_mask_1
7058 0, // RFP32:sub_xmm
7059 0, // RFP32:sub_ymm
7060 },
7061 { // VK32WM
7062 0, // VK32WM:sub_8bit
7063 0, // VK32WM:sub_8bit_hi
7064 0, // VK32WM:sub_8bit_hi_phony
7065 0, // VK32WM:sub_16bit
7066 0, // VK32WM:sub_16bit_hi
7067 0, // VK32WM:sub_32bit
7068 0, // VK32WM:sub_mask_0
7069 0, // VK32WM:sub_mask_1
7070 0, // VK32WM:sub_xmm
7071 0, // VK32WM:sub_ymm
7072 },
7073 { // GR32_ABCD
7074 6, // GR32_ABCD:sub_8bit -> GR8_ABCD_L
7075 5, // GR32_ABCD:sub_8bit_hi -> GR8_ABCD_H
7076 0, // GR32_ABCD:sub_8bit_hi_phony
7077 22, // GR32_ABCD:sub_16bit -> GR16_ABCD
7078 0, // GR32_ABCD:sub_16bit_hi
7079 0, // GR32_ABCD:sub_32bit
7080 0, // GR32_ABCD:sub_mask_0
7081 0, // GR32_ABCD:sub_mask_1
7082 0, // GR32_ABCD:sub_xmm
7083 0, // GR32_ABCD:sub_ymm
7084 },
7085 { // GR32_TC
7086 3, // GR32_TC:sub_8bit -> GR8_NOREX2
7087 5, // GR32_TC:sub_8bit_hi -> GR8_ABCD_H
7088 0, // GR32_TC:sub_8bit_hi_phony
7089 10, // GR32_TC:sub_16bit -> GR16_NOREX
7090 0, // GR32_TC:sub_16bit_hi
7091 0, // GR32_TC:sub_32bit
7092 0, // GR32_TC:sub_mask_0
7093 0, // GR32_TC:sub_mask_1
7094 0, // GR32_TC:sub_xmm
7095 0, // GR32_TC:sub_ymm
7096 },
7097 { // GR32_ABCD_and_GR32_TC
7098 6, // GR32_ABCD_and_GR32_TC:sub_8bit -> GR8_ABCD_L
7099 5, // GR32_ABCD_and_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
7100 0, // GR32_ABCD_and_GR32_TC:sub_8bit_hi_phony
7101 22, // GR32_ABCD_and_GR32_TC:sub_16bit -> GR16_ABCD
7102 0, // GR32_ABCD_and_GR32_TC:sub_16bit_hi
7103 0, // GR32_ABCD_and_GR32_TC:sub_32bit
7104 0, // GR32_ABCD_and_GR32_TC:sub_mask_0
7105 0, // GR32_ABCD_and_GR32_TC:sub_mask_1
7106 0, // GR32_ABCD_and_GR32_TC:sub_xmm
7107 0, // GR32_ABCD_and_GR32_TC:sub_ymm
7108 },
7109 { // GR32_AD
7110 6, // GR32_AD:sub_8bit -> GR8_ABCD_L
7111 5, // GR32_AD:sub_8bit_hi -> GR8_ABCD_H
7112 0, // GR32_AD:sub_8bit_hi_phony
7113 22, // GR32_AD:sub_16bit -> GR16_ABCD
7114 0, // GR32_AD:sub_16bit_hi
7115 0, // GR32_AD:sub_32bit
7116 0, // GR32_AD:sub_mask_0
7117 0, // GR32_AD:sub_mask_1
7118 0, // GR32_AD:sub_xmm
7119 0, // GR32_AD:sub_ymm
7120 },
7121 { // GR32_ArgRef
7122 6, // GR32_ArgRef:sub_8bit -> GR8_ABCD_L
7123 5, // GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
7124 0, // GR32_ArgRef:sub_8bit_hi_phony
7125 22, // GR32_ArgRef:sub_16bit -> GR16_ABCD
7126 0, // GR32_ArgRef:sub_16bit_hi
7127 0, // GR32_ArgRef:sub_32bit
7128 0, // GR32_ArgRef:sub_mask_0
7129 0, // GR32_ArgRef:sub_mask_1
7130 0, // GR32_ArgRef:sub_xmm
7131 0, // GR32_ArgRef:sub_ymm
7132 },
7133 { // GR32_BPSP
7134 3, // GR32_BPSP:sub_8bit -> GR8_NOREX2
7135 0, // GR32_BPSP:sub_8bit_hi
7136 0, // GR32_BPSP:sub_8bit_hi_phony
7137 10, // GR32_BPSP:sub_16bit -> GR16_NOREX
7138 0, // GR32_BPSP:sub_16bit_hi
7139 0, // GR32_BPSP:sub_32bit
7140 0, // GR32_BPSP:sub_mask_0
7141 0, // GR32_BPSP:sub_mask_1
7142 0, // GR32_BPSP:sub_xmm
7143 0, // GR32_BPSP:sub_ymm
7144 },
7145 { // GR32_BSI
7146 3, // GR32_BSI:sub_8bit -> GR8_NOREX2
7147 5, // GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
7148 0, // GR32_BSI:sub_8bit_hi_phony
7149 10, // GR32_BSI:sub_16bit -> GR16_NOREX
7150 0, // GR32_BSI:sub_16bit_hi
7151 0, // GR32_BSI:sub_32bit
7152 0, // GR32_BSI:sub_mask_0
7153 0, // GR32_BSI:sub_mask_1
7154 0, // GR32_BSI:sub_xmm
7155 0, // GR32_BSI:sub_ymm
7156 },
7157 { // GR32_CB
7158 6, // GR32_CB:sub_8bit -> GR8_ABCD_L
7159 5, // GR32_CB:sub_8bit_hi -> GR8_ABCD_H
7160 0, // GR32_CB:sub_8bit_hi_phony
7161 22, // GR32_CB:sub_16bit -> GR16_ABCD
7162 0, // GR32_CB:sub_16bit_hi
7163 0, // GR32_CB:sub_32bit
7164 0, // GR32_CB:sub_mask_0
7165 0, // GR32_CB:sub_mask_1
7166 0, // GR32_CB:sub_xmm
7167 0, // GR32_CB:sub_ymm
7168 },
7169 { // GR32_DC
7170 6, // GR32_DC:sub_8bit -> GR8_ABCD_L
7171 5, // GR32_DC:sub_8bit_hi -> GR8_ABCD_H
7172 0, // GR32_DC:sub_8bit_hi_phony
7173 22, // GR32_DC:sub_16bit -> GR16_ABCD
7174 0, // GR32_DC:sub_16bit_hi
7175 0, // GR32_DC:sub_32bit
7176 0, // GR32_DC:sub_mask_0
7177 0, // GR32_DC:sub_mask_1
7178 0, // GR32_DC:sub_xmm
7179 0, // GR32_DC:sub_ymm
7180 },
7181 { // GR32_DIBP
7182 3, // GR32_DIBP:sub_8bit -> GR8_NOREX2
7183 0, // GR32_DIBP:sub_8bit_hi
7184 0, // GR32_DIBP:sub_8bit_hi_phony
7185 10, // GR32_DIBP:sub_16bit -> GR16_NOREX
7186 0, // GR32_DIBP:sub_16bit_hi
7187 0, // GR32_DIBP:sub_32bit
7188 0, // GR32_DIBP:sub_mask_0
7189 0, // GR32_DIBP:sub_mask_1
7190 0, // GR32_DIBP:sub_xmm
7191 0, // GR32_DIBP:sub_ymm
7192 },
7193 { // GR32_SIDI
7194 3, // GR32_SIDI:sub_8bit -> GR8_NOREX2
7195 0, // GR32_SIDI:sub_8bit_hi
7196 0, // GR32_SIDI:sub_8bit_hi_phony
7197 10, // GR32_SIDI:sub_16bit -> GR16_NOREX
7198 0, // GR32_SIDI:sub_16bit_hi
7199 0, // GR32_SIDI:sub_32bit
7200 0, // GR32_SIDI:sub_mask_0
7201 0, // GR32_SIDI:sub_mask_1
7202 0, // GR32_SIDI:sub_xmm
7203 0, // GR32_SIDI:sub_ymm
7204 },
7205 { // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
7206 3, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit -> GR8_NOREX2
7207 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit_hi
7208 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit_hi_phony
7209 10, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_16bit -> GR16_NOREX
7210 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_16bit_hi
7211 66, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
7212 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_mask_0
7213 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_mask_1
7214 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_xmm
7215 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_ymm
7216 },
7217 { // CCR
7218 0, // CCR:sub_8bit
7219 0, // CCR:sub_8bit_hi
7220 0, // CCR:sub_8bit_hi_phony
7221 0, // CCR:sub_16bit
7222 0, // CCR:sub_16bit_hi
7223 0, // CCR:sub_32bit
7224 0, // CCR:sub_mask_0
7225 0, // CCR:sub_mask_1
7226 0, // CCR:sub_xmm
7227 0, // CCR:sub_ymm
7228 },
7229 { // DFCCR
7230 0, // DFCCR:sub_8bit
7231 0, // DFCCR:sub_8bit_hi
7232 0, // DFCCR:sub_8bit_hi_phony
7233 0, // DFCCR:sub_16bit
7234 0, // DFCCR:sub_16bit_hi
7235 0, // DFCCR:sub_32bit
7236 0, // DFCCR:sub_mask_0
7237 0, // DFCCR:sub_mask_1
7238 0, // DFCCR:sub_xmm
7239 0, // DFCCR:sub_ymm
7240 },
7241 { // GR32_ABCD_and_GR32_BSI
7242 6, // GR32_ABCD_and_GR32_BSI:sub_8bit -> GR8_ABCD_L
7243 5, // GR32_ABCD_and_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
7244 0, // GR32_ABCD_and_GR32_BSI:sub_8bit_hi_phony
7245 22, // GR32_ABCD_and_GR32_BSI:sub_16bit -> GR16_ABCD
7246 0, // GR32_ABCD_and_GR32_BSI:sub_16bit_hi
7247 0, // GR32_ABCD_and_GR32_BSI:sub_32bit
7248 0, // GR32_ABCD_and_GR32_BSI:sub_mask_0
7249 0, // GR32_ABCD_and_GR32_BSI:sub_mask_1
7250 0, // GR32_ABCD_and_GR32_BSI:sub_xmm
7251 0, // GR32_ABCD_and_GR32_BSI:sub_ymm
7252 },
7253 { // GR32_AD_and_GR32_ArgRef
7254 6, // GR32_AD_and_GR32_ArgRef:sub_8bit -> GR8_ABCD_L
7255 5, // GR32_AD_and_GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
7256 0, // GR32_AD_and_GR32_ArgRef:sub_8bit_hi_phony
7257 22, // GR32_AD_and_GR32_ArgRef:sub_16bit -> GR16_ABCD
7258 0, // GR32_AD_and_GR32_ArgRef:sub_16bit_hi
7259 0, // GR32_AD_and_GR32_ArgRef:sub_32bit
7260 0, // GR32_AD_and_GR32_ArgRef:sub_mask_0
7261 0, // GR32_AD_and_GR32_ArgRef:sub_mask_1
7262 0, // GR32_AD_and_GR32_ArgRef:sub_xmm
7263 0, // GR32_AD_and_GR32_ArgRef:sub_ymm
7264 },
7265 { // GR32_ArgRef_and_GR32_CB
7266 6, // GR32_ArgRef_and_GR32_CB:sub_8bit -> GR8_ABCD_L
7267 5, // GR32_ArgRef_and_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
7268 0, // GR32_ArgRef_and_GR32_CB:sub_8bit_hi_phony
7269 22, // GR32_ArgRef_and_GR32_CB:sub_16bit -> GR16_ABCD
7270 0, // GR32_ArgRef_and_GR32_CB:sub_16bit_hi
7271 0, // GR32_ArgRef_and_GR32_CB:sub_32bit
7272 0, // GR32_ArgRef_and_GR32_CB:sub_mask_0
7273 0, // GR32_ArgRef_and_GR32_CB:sub_mask_1
7274 0, // GR32_ArgRef_and_GR32_CB:sub_xmm
7275 0, // GR32_ArgRef_and_GR32_CB:sub_ymm
7276 },
7277 { // GR32_BPSP_and_GR32_DIBP
7278 3, // GR32_BPSP_and_GR32_DIBP:sub_8bit -> GR8_NOREX2
7279 0, // GR32_BPSP_and_GR32_DIBP:sub_8bit_hi
7280 0, // GR32_BPSP_and_GR32_DIBP:sub_8bit_hi_phony
7281 10, // GR32_BPSP_and_GR32_DIBP:sub_16bit -> GR16_NOREX
7282 0, // GR32_BPSP_and_GR32_DIBP:sub_16bit_hi
7283 0, // GR32_BPSP_and_GR32_DIBP:sub_32bit
7284 0, // GR32_BPSP_and_GR32_DIBP:sub_mask_0
7285 0, // GR32_BPSP_and_GR32_DIBP:sub_mask_1
7286 0, // GR32_BPSP_and_GR32_DIBP:sub_xmm
7287 0, // GR32_BPSP_and_GR32_DIBP:sub_ymm
7288 },
7289 { // GR32_BPSP_and_GR32_TC
7290 3, // GR32_BPSP_and_GR32_TC:sub_8bit -> GR8_NOREX2
7291 0, // GR32_BPSP_and_GR32_TC:sub_8bit_hi
7292 0, // GR32_BPSP_and_GR32_TC:sub_8bit_hi_phony
7293 10, // GR32_BPSP_and_GR32_TC:sub_16bit -> GR16_NOREX
7294 0, // GR32_BPSP_and_GR32_TC:sub_16bit_hi
7295 0, // GR32_BPSP_and_GR32_TC:sub_32bit
7296 0, // GR32_BPSP_and_GR32_TC:sub_mask_0
7297 0, // GR32_BPSP_and_GR32_TC:sub_mask_1
7298 0, // GR32_BPSP_and_GR32_TC:sub_xmm
7299 0, // GR32_BPSP_and_GR32_TC:sub_ymm
7300 },
7301 { // GR32_BSI_and_GR32_SIDI
7302 3, // GR32_BSI_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
7303 0, // GR32_BSI_and_GR32_SIDI:sub_8bit_hi
7304 0, // GR32_BSI_and_GR32_SIDI:sub_8bit_hi_phony
7305 10, // GR32_BSI_and_GR32_SIDI:sub_16bit -> GR16_NOREX
7306 0, // GR32_BSI_and_GR32_SIDI:sub_16bit_hi
7307 0, // GR32_BSI_and_GR32_SIDI:sub_32bit
7308 0, // GR32_BSI_and_GR32_SIDI:sub_mask_0
7309 0, // GR32_BSI_and_GR32_SIDI:sub_mask_1
7310 0, // GR32_BSI_and_GR32_SIDI:sub_xmm
7311 0, // GR32_BSI_and_GR32_SIDI:sub_ymm
7312 },
7313 { // GR32_DIBP_and_GR32_SIDI
7314 3, // GR32_DIBP_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
7315 0, // GR32_DIBP_and_GR32_SIDI:sub_8bit_hi
7316 0, // GR32_DIBP_and_GR32_SIDI:sub_8bit_hi_phony
7317 10, // GR32_DIBP_and_GR32_SIDI:sub_16bit -> GR16_NOREX
7318 0, // GR32_DIBP_and_GR32_SIDI:sub_16bit_hi
7319 0, // GR32_DIBP_and_GR32_SIDI:sub_32bit
7320 0, // GR32_DIBP_and_GR32_SIDI:sub_mask_0
7321 0, // GR32_DIBP_and_GR32_SIDI:sub_mask_1
7322 0, // GR32_DIBP_and_GR32_SIDI:sub_xmm
7323 0, // GR32_DIBP_and_GR32_SIDI:sub_ymm
7324 },
7325 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
7326 3, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit -> GR8_NOREX2
7327 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit_hi
7328 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit_hi_phony
7329 10, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_16bit -> GR16_NOREX
7330 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_16bit_hi
7331 66, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
7332 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_mask_0
7333 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_mask_1
7334 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_xmm
7335 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_ymm
7336 },
7337 { // LOW32_ADDR_ACCESS_with_sub_32bit
7338 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit
7339 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit_hi
7340 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit_hi_phony
7341 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_16bit
7342 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_16bit_hi
7343 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_32bit
7344 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_mask_0
7345 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_mask_1
7346 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_xmm
7347 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_ymm
7348 },
7349 { // RFP64
7350 0, // RFP64:sub_8bit
7351 0, // RFP64:sub_8bit_hi
7352 0, // RFP64:sub_8bit_hi_phony
7353 0, // RFP64:sub_16bit
7354 0, // RFP64:sub_16bit_hi
7355 0, // RFP64:sub_32bit
7356 0, // RFP64:sub_mask_0
7357 0, // RFP64:sub_mask_1
7358 0, // RFP64:sub_xmm
7359 0, // RFP64:sub_ymm
7360 },
7361 { // GR64
7362 1, // GR64:sub_8bit -> GR8
7363 5, // GR64:sub_8bit_hi -> GR8_ABCD_H
7364 0, // GR64:sub_8bit_hi_phony
7365 8, // GR64:sub_16bit -> GR16
7366 0, // GR64:sub_16bit_hi
7367 36, // GR64:sub_32bit -> GR32
7368 0, // GR64:sub_mask_0
7369 0, // GR64:sub_mask_1
7370 0, // GR64:sub_xmm
7371 0, // GR64:sub_ymm
7372 },
7373 { // FR64X
7374 0, // FR64X:sub_8bit
7375 0, // FR64X:sub_8bit_hi
7376 0, // FR64X:sub_8bit_hi_phony
7377 0, // FR64X:sub_16bit
7378 0, // FR64X:sub_16bit_hi
7379 0, // FR64X:sub_32bit
7380 0, // FR64X:sub_mask_0
7381 0, // FR64X:sub_mask_1
7382 0, // FR64X:sub_xmm
7383 0, // FR64X:sub_ymm
7384 },
7385 { // GR64_with_sub_8bit
7386 1, // GR64_with_sub_8bit:sub_8bit -> GR8
7387 5, // GR64_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
7388 0, // GR64_with_sub_8bit:sub_8bit_hi_phony
7389 8, // GR64_with_sub_8bit:sub_16bit -> GR16
7390 0, // GR64_with_sub_8bit:sub_16bit_hi
7391 36, // GR64_with_sub_8bit:sub_32bit -> GR32
7392 0, // GR64_with_sub_8bit:sub_mask_0
7393 0, // GR64_with_sub_8bit:sub_mask_1
7394 0, // GR64_with_sub_8bit:sub_xmm
7395 0, // GR64_with_sub_8bit:sub_ymm
7396 },
7397 { // GR64_NOSP
7398 1, // GR64_NOSP:sub_8bit -> GR8
7399 5, // GR64_NOSP:sub_8bit_hi -> GR8_ABCD_H
7400 0, // GR64_NOSP:sub_8bit_hi_phony
7401 8, // GR64_NOSP:sub_16bit -> GR16
7402 0, // GR64_NOSP:sub_16bit_hi
7403 37, // GR64_NOSP:sub_32bit -> GR32_NOSP
7404 0, // GR64_NOSP:sub_mask_0
7405 0, // GR64_NOSP:sub_mask_1
7406 0, // GR64_NOSP:sub_xmm
7407 0, // GR64_NOSP:sub_ymm
7408 },
7409 { // GR64_NOREX2
7410 3, // GR64_NOREX2:sub_8bit -> GR8_NOREX2
7411 5, // GR64_NOREX2:sub_8bit_hi -> GR8_ABCD_H
7412 0, // GR64_NOREX2:sub_8bit_hi_phony
7413 9, // GR64_NOREX2:sub_16bit -> GR16_NOREX2
7414 0, // GR64_NOREX2:sub_16bit_hi
7415 41, // GR64_NOREX2:sub_32bit -> GR32_NOREX2
7416 0, // GR64_NOREX2:sub_mask_0
7417 0, // GR64_NOREX2:sub_mask_1
7418 0, // GR64_NOREX2:sub_xmm
7419 0, // GR64_NOREX2:sub_ymm
7420 },
7421 { // CONTROL_REG
7422 0, // CONTROL_REG:sub_8bit
7423 0, // CONTROL_REG:sub_8bit_hi
7424 0, // CONTROL_REG:sub_8bit_hi_phony
7425 0, // CONTROL_REG:sub_16bit
7426 0, // CONTROL_REG:sub_16bit_hi
7427 0, // CONTROL_REG:sub_32bit
7428 0, // CONTROL_REG:sub_mask_0
7429 0, // CONTROL_REG:sub_mask_1
7430 0, // CONTROL_REG:sub_xmm
7431 0, // CONTROL_REG:sub_ymm
7432 },
7433 { // FR64
7434 0, // FR64:sub_8bit
7435 0, // FR64:sub_8bit_hi
7436 0, // FR64:sub_8bit_hi_phony
7437 0, // FR64:sub_16bit
7438 0, // FR64:sub_16bit_hi
7439 0, // FR64:sub_32bit
7440 0, // FR64:sub_mask_0
7441 0, // FR64:sub_mask_1
7442 0, // FR64:sub_xmm
7443 0, // FR64:sub_ymm
7444 },
7445 { // GR64_with_sub_16bit_in_GR16_NOREX2
7446 3, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_8bit -> GR8_NOREX2
7447 5, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi -> GR8_ABCD_H
7448 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi_phony
7449 9, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_16bit -> GR16_NOREX2
7450 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_16bit_hi
7451 41, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_32bit -> GR32_NOREX2
7452 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_mask_0
7453 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_mask_1
7454 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_xmm
7455 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_ymm
7456 },
7457 { // GR64_NOREX2_NOSP
7458 3, // GR64_NOREX2_NOSP:sub_8bit -> GR8_NOREX2
7459 5, // GR64_NOREX2_NOSP:sub_8bit_hi -> GR8_ABCD_H
7460 0, // GR64_NOREX2_NOSP:sub_8bit_hi_phony
7461 9, // GR64_NOREX2_NOSP:sub_16bit -> GR16_NOREX2
7462 0, // GR64_NOREX2_NOSP:sub_16bit_hi
7463 42, // GR64_NOREX2_NOSP:sub_32bit -> GR32_NOREX2_NOSP
7464 0, // GR64_NOREX2_NOSP:sub_mask_0
7465 0, // GR64_NOREX2_NOSP:sub_mask_1
7466 0, // GR64_NOREX2_NOSP:sub_xmm
7467 0, // GR64_NOREX2_NOSP:sub_ymm
7468 },
7469 { // GR64PLTSafe
7470 3, // GR64PLTSafe:sub_8bit -> GR8_NOREX2
7471 5, // GR64PLTSafe:sub_8bit_hi -> GR8_ABCD_H
7472 0, // GR64PLTSafe:sub_8bit_hi_phony
7473 9, // GR64PLTSafe:sub_16bit -> GR16_NOREX2
7474 0, // GR64PLTSafe:sub_16bit_hi
7475 42, // GR64PLTSafe:sub_32bit -> GR32_NOREX2_NOSP
7476 0, // GR64PLTSafe:sub_mask_0
7477 0, // GR64PLTSafe:sub_mask_1
7478 0, // GR64PLTSafe:sub_xmm
7479 0, // GR64PLTSafe:sub_ymm
7480 },
7481 { // GR64_TC
7482 3, // GR64_TC:sub_8bit -> GR8_NOREX2
7483 5, // GR64_TC:sub_8bit_hi -> GR8_ABCD_H
7484 0, // GR64_TC:sub_8bit_hi_phony
7485 9, // GR64_TC:sub_16bit -> GR16_NOREX2
7486 0, // GR64_TC:sub_16bit_hi
7487 41, // GR64_TC:sub_32bit -> GR32_NOREX2
7488 0, // GR64_TC:sub_mask_0
7489 0, // GR64_TC:sub_mask_1
7490 0, // GR64_TC:sub_xmm
7491 0, // GR64_TC:sub_ymm
7492 },
7493 { // GR64_NOREX
7494 3, // GR64_NOREX:sub_8bit -> GR8_NOREX2
7495 5, // GR64_NOREX:sub_8bit_hi -> GR8_ABCD_H
7496 0, // GR64_NOREX:sub_8bit_hi_phony
7497 10, // GR64_NOREX:sub_16bit -> GR16_NOREX
7498 0, // GR64_NOREX:sub_16bit_hi
7499 44, // GR64_NOREX:sub_32bit -> GR32_NOREX
7500 0, // GR64_NOREX:sub_mask_0
7501 0, // GR64_NOREX:sub_mask_1
7502 0, // GR64_NOREX:sub_xmm
7503 0, // GR64_NOREX:sub_ymm
7504 },
7505 { // GR64_TCW64
7506 3, // GR64_TCW64:sub_8bit -> GR8_NOREX2
7507 5, // GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
7508 0, // GR64_TCW64:sub_8bit_hi_phony
7509 9, // GR64_TCW64:sub_16bit -> GR16_NOREX2
7510 0, // GR64_TCW64:sub_16bit_hi
7511 41, // GR64_TCW64:sub_32bit -> GR32_NOREX2
7512 0, // GR64_TCW64:sub_mask_0
7513 0, // GR64_TCW64:sub_mask_1
7514 0, // GR64_TCW64:sub_xmm
7515 0, // GR64_TCW64:sub_ymm
7516 },
7517 { // GR64_TC_with_sub_8bit
7518 3, // GR64_TC_with_sub_8bit:sub_8bit -> GR8_NOREX2
7519 5, // GR64_TC_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
7520 0, // GR64_TC_with_sub_8bit:sub_8bit_hi_phony
7521 9, // GR64_TC_with_sub_8bit:sub_16bit -> GR16_NOREX2
7522 0, // GR64_TC_with_sub_8bit:sub_16bit_hi
7523 41, // GR64_TC_with_sub_8bit:sub_32bit -> GR32_NOREX2
7524 0, // GR64_TC_with_sub_8bit:sub_mask_0
7525 0, // GR64_TC_with_sub_8bit:sub_mask_1
7526 0, // GR64_TC_with_sub_8bit:sub_xmm
7527 0, // GR64_TC_with_sub_8bit:sub_ymm
7528 },
7529 { // GR64_NOREX2_NOSP_and_GR64_TC
7530 3, // GR64_NOREX2_NOSP_and_GR64_TC:sub_8bit -> GR8_NOREX2
7531 5, // GR64_NOREX2_NOSP_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
7532 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_8bit_hi_phony
7533 9, // GR64_NOREX2_NOSP_and_GR64_TC:sub_16bit -> GR16_NOREX2
7534 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_16bit_hi
7535 42, // GR64_NOREX2_NOSP_and_GR64_TC:sub_32bit -> GR32_NOREX2_NOSP
7536 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_mask_0
7537 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_mask_1
7538 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_xmm
7539 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_ymm
7540 },
7541 { // GR64_TCW64_with_sub_8bit
7542 3, // GR64_TCW64_with_sub_8bit:sub_8bit -> GR8_NOREX2
7543 5, // GR64_TCW64_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
7544 0, // GR64_TCW64_with_sub_8bit:sub_8bit_hi_phony
7545 9, // GR64_TCW64_with_sub_8bit:sub_16bit -> GR16_NOREX2
7546 0, // GR64_TCW64_with_sub_8bit:sub_16bit_hi
7547 41, // GR64_TCW64_with_sub_8bit:sub_32bit -> GR32_NOREX2
7548 0, // GR64_TCW64_with_sub_8bit:sub_mask_0
7549 0, // GR64_TCW64_with_sub_8bit:sub_mask_1
7550 0, // GR64_TCW64_with_sub_8bit:sub_xmm
7551 0, // GR64_TCW64_with_sub_8bit:sub_ymm
7552 },
7553 { // GR64_TC_and_GR64_TCW64
7554 3, // GR64_TC_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
7555 5, // GR64_TC_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
7556 0, // GR64_TC_and_GR64_TCW64:sub_8bit_hi_phony
7557 9, // GR64_TC_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
7558 0, // GR64_TC_and_GR64_TCW64:sub_16bit_hi
7559 41, // GR64_TC_and_GR64_TCW64:sub_32bit -> GR32_NOREX2
7560 0, // GR64_TC_and_GR64_TCW64:sub_mask_0
7561 0, // GR64_TC_and_GR64_TCW64:sub_mask_1
7562 0, // GR64_TC_and_GR64_TCW64:sub_xmm
7563 0, // GR64_TC_and_GR64_TCW64:sub_ymm
7564 },
7565 { // GR64_with_sub_16bit_in_GR16_NOREX
7566 3, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8_NOREX2
7567 5, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
7568 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
7569 10, // GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
7570 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
7571 44, // GR64_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_NOREX
7572 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_0
7573 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_1
7574 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_xmm
7575 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_ymm
7576 },
7577 { // VK64
7578 0, // VK64:sub_8bit
7579 0, // VK64:sub_8bit_hi
7580 0, // VK64:sub_8bit_hi_phony
7581 0, // VK64:sub_16bit
7582 0, // VK64:sub_16bit_hi
7583 0, // VK64:sub_32bit
7584 0, // VK64:sub_mask_0
7585 0, // VK64:sub_mask_1
7586 0, // VK64:sub_xmm
7587 0, // VK64:sub_ymm
7588 },
7589 { // VR64
7590 0, // VR64:sub_8bit
7591 0, // VR64:sub_8bit_hi
7592 0, // VR64:sub_8bit_hi_phony
7593 0, // VR64:sub_16bit
7594 0, // VR64:sub_16bit_hi
7595 0, // VR64:sub_32bit
7596 0, // VR64:sub_mask_0
7597 0, // VR64:sub_mask_1
7598 0, // VR64:sub_xmm
7599 0, // VR64:sub_ymm
7600 },
7601 { // GR64PLTSafe_and_GR64_TC
7602 3, // GR64PLTSafe_and_GR64_TC:sub_8bit -> GR8_NOREX2
7603 5, // GR64PLTSafe_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
7604 0, // GR64PLTSafe_and_GR64_TC:sub_8bit_hi_phony
7605 9, // GR64PLTSafe_and_GR64_TC:sub_16bit -> GR16_NOREX2
7606 0, // GR64PLTSafe_and_GR64_TC:sub_16bit_hi
7607 42, // GR64PLTSafe_and_GR64_TC:sub_32bit -> GR32_NOREX2_NOSP
7608 0, // GR64PLTSafe_and_GR64_TC:sub_mask_0
7609 0, // GR64PLTSafe_and_GR64_TC:sub_mask_1
7610 0, // GR64PLTSafe_and_GR64_TC:sub_xmm
7611 0, // GR64PLTSafe_and_GR64_TC:sub_ymm
7612 },
7613 { // GR64_NOREX2_NOSP_and_GR64_TCW64
7614 3, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
7615 5, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
7616 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi_phony
7617 9, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
7618 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit_hi
7619 42, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_32bit -> GR32_NOREX2_NOSP
7620 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_0
7621 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_1
7622 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_xmm
7623 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_ymm
7624 },
7625 { // GR64_NOREX_NOSP
7626 3, // GR64_NOREX_NOSP:sub_8bit -> GR8_NOREX2
7627 5, // GR64_NOREX_NOSP:sub_8bit_hi -> GR8_ABCD_H
7628 0, // GR64_NOREX_NOSP:sub_8bit_hi_phony
7629 10, // GR64_NOREX_NOSP:sub_16bit -> GR16_NOREX
7630 0, // GR64_NOREX_NOSP:sub_16bit_hi
7631 46, // GR64_NOREX_NOSP:sub_32bit -> GR32_NOREX_NOSP
7632 0, // GR64_NOREX_NOSP:sub_mask_0
7633 0, // GR64_NOREX_NOSP:sub_mask_1
7634 0, // GR64_NOREX_NOSP:sub_xmm
7635 0, // GR64_NOREX_NOSP:sub_ymm
7636 },
7637 { // GR64_NOREX_and_GR64_TC
7638 3, // GR64_NOREX_and_GR64_TC:sub_8bit -> GR8_NOREX2
7639 5, // GR64_NOREX_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
7640 0, // GR64_NOREX_and_GR64_TC:sub_8bit_hi_phony
7641 10, // GR64_NOREX_and_GR64_TC:sub_16bit -> GR16_NOREX
7642 0, // GR64_NOREX_and_GR64_TC:sub_16bit_hi
7643 44, // GR64_NOREX_and_GR64_TC:sub_32bit -> GR32_NOREX
7644 0, // GR64_NOREX_and_GR64_TC:sub_mask_0
7645 0, // GR64_NOREX_and_GR64_TC:sub_mask_1
7646 0, // GR64_NOREX_and_GR64_TC:sub_xmm
7647 0, // GR64_NOREX_and_GR64_TC:sub_ymm
7648 },
7649 { // GR64_TCW64_and_GR64_TC_with_sub_8bit
7650 3, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit -> GR8_NOREX2
7651 5, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
7652 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit_hi_phony
7653 9, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_16bit -> GR16_NOREX2
7654 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_16bit_hi
7655 41, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_32bit -> GR32_NOREX2
7656 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_mask_0
7657 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_mask_1
7658 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_xmm
7659 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_ymm
7660 },
7661 { // VK64WM
7662 0, // VK64WM:sub_8bit
7663 0, // VK64WM:sub_8bit_hi
7664 0, // VK64WM:sub_8bit_hi_phony
7665 0, // VK64WM:sub_16bit
7666 0, // VK64WM:sub_16bit_hi
7667 0, // VK64WM:sub_32bit
7668 0, // VK64WM:sub_mask_0
7669 0, // VK64WM:sub_mask_1
7670 0, // VK64WM:sub_xmm
7671 0, // VK64WM:sub_ymm
7672 },
7673 { // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
7674 3, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
7675 5, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
7676 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi_phony
7677 9, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
7678 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit_hi
7679 42, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_32bit -> GR32_NOREX2_NOSP
7680 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_0
7681 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_1
7682 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_xmm
7683 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_ymm
7684 },
7685 { // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
7686 3, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8_NOREX2
7687 5, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
7688 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
7689 10, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
7690 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
7691 44, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_NOREX
7692 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_0
7693 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_1
7694 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_xmm
7695 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_ymm
7696 },
7697 { // GR64PLTSafe_and_GR64_TCW64
7698 3, // GR64PLTSafe_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
7699 5, // GR64PLTSafe_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
7700 0, // GR64PLTSafe_and_GR64_TCW64:sub_8bit_hi_phony
7701 9, // GR64PLTSafe_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
7702 0, // GR64PLTSafe_and_GR64_TCW64:sub_16bit_hi
7703 42, // GR64PLTSafe_and_GR64_TCW64:sub_32bit -> GR32_NOREX2_NOSP
7704 0, // GR64PLTSafe_and_GR64_TCW64:sub_mask_0
7705 0, // GR64PLTSafe_and_GR64_TCW64:sub_mask_1
7706 0, // GR64PLTSafe_and_GR64_TCW64:sub_xmm
7707 0, // GR64PLTSafe_and_GR64_TCW64:sub_ymm
7708 },
7709 { // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
7710 3, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit -> GR8_NOREX2
7711 5, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
7712 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit_hi_phony
7713 10, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_16bit -> GR16_NOREX
7714 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_16bit_hi
7715 46, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_32bit -> GR32_NOREX_NOSP
7716 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_mask_0
7717 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_mask_1
7718 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_xmm
7719 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_ymm
7720 },
7721 { // GR64_NOREX_and_GR64_TCW64
7722 3, // GR64_NOREX_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
7723 5, // GR64_NOREX_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
7724 0, // GR64_NOREX_and_GR64_TCW64:sub_8bit_hi_phony
7725 10, // GR64_NOREX_and_GR64_TCW64:sub_16bit -> GR16_NOREX
7726 0, // GR64_NOREX_and_GR64_TCW64:sub_16bit_hi
7727 50, // GR64_NOREX_and_GR64_TCW64:sub_32bit -> GR32_TC
7728 0, // GR64_NOREX_and_GR64_TCW64:sub_mask_0
7729 0, // GR64_NOREX_and_GR64_TCW64:sub_mask_1
7730 0, // GR64_NOREX_and_GR64_TCW64:sub_xmm
7731 0, // GR64_NOREX_and_GR64_TCW64:sub_ymm
7732 },
7733 { // GR64_ABCD
7734 6, // GR64_ABCD:sub_8bit -> GR8_ABCD_L
7735 5, // GR64_ABCD:sub_8bit_hi -> GR8_ABCD_H
7736 0, // GR64_ABCD:sub_8bit_hi_phony
7737 22, // GR64_ABCD:sub_16bit -> GR16_ABCD
7738 0, // GR64_ABCD:sub_16bit_hi
7739 49, // GR64_ABCD:sub_32bit -> GR32_ABCD
7740 0, // GR64_ABCD:sub_mask_0
7741 0, // GR64_ABCD:sub_mask_1
7742 0, // GR64_ABCD:sub_xmm
7743 0, // GR64_ABCD:sub_ymm
7744 },
7745 { // GR64_with_sub_32bit_in_GR32_TC
7746 3, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit -> GR8_NOREX2
7747 5, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
7748 0, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit_hi_phony
7749 10, // GR64_with_sub_32bit_in_GR32_TC:sub_16bit -> GR16_NOREX
7750 0, // GR64_with_sub_32bit_in_GR32_TC:sub_16bit_hi
7751 50, // GR64_with_sub_32bit_in_GR32_TC:sub_32bit -> GR32_TC
7752 0, // GR64_with_sub_32bit_in_GR32_TC:sub_mask_0
7753 0, // GR64_with_sub_32bit_in_GR32_TC:sub_mask_1
7754 0, // GR64_with_sub_32bit_in_GR32_TC:sub_xmm
7755 0, // GR64_with_sub_32bit_in_GR32_TC:sub_ymm
7756 },
7757 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
7758 6, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit -> GR8_ABCD_L
7759 5, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
7760 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit_hi_phony
7761 22, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_16bit -> GR16_ABCD
7762 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_16bit_hi
7763 51, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_32bit -> GR32_ABCD_and_GR32_TC
7764 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_mask_0
7765 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_mask_1
7766 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_xmm
7767 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_ymm
7768 },
7769 { // GR64_AD
7770 6, // GR64_AD:sub_8bit -> GR8_ABCD_L
7771 5, // GR64_AD:sub_8bit_hi -> GR8_ABCD_H
7772 0, // GR64_AD:sub_8bit_hi_phony
7773 22, // GR64_AD:sub_16bit -> GR16_ABCD
7774 0, // GR64_AD:sub_16bit_hi
7775 52, // GR64_AD:sub_32bit -> GR32_AD
7776 0, // GR64_AD:sub_mask_0
7777 0, // GR64_AD:sub_mask_1
7778 0, // GR64_AD:sub_xmm
7779 0, // GR64_AD:sub_ymm
7780 },
7781 { // GR64_ArgRef
7782 3, // GR64_ArgRef:sub_8bit -> GR8_NOREX2
7783 0, // GR64_ArgRef:sub_8bit_hi
7784 0, // GR64_ArgRef:sub_8bit_hi_phony
7785 9, // GR64_ArgRef:sub_16bit -> GR16_NOREX2
7786 0, // GR64_ArgRef:sub_16bit_hi
7787 42, // GR64_ArgRef:sub_32bit -> GR32_NOREX2_NOSP
7788 0, // GR64_ArgRef:sub_mask_0
7789 0, // GR64_ArgRef:sub_mask_1
7790 0, // GR64_ArgRef:sub_xmm
7791 0, // GR64_ArgRef:sub_ymm
7792 },
7793 { // GR64_and_LOW32_ADDR_ACCESS_RBP
7794 3, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit -> GR8_NOREX2
7795 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit_hi
7796 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit_hi_phony
7797 10, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_16bit -> GR16_NOREX
7798 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_16bit_hi
7799 66, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
7800 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_mask_0
7801 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_mask_1
7802 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_xmm
7803 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_ymm
7804 },
7805 { // GR64_with_sub_32bit_in_GR32_ArgRef
7806 6, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_8bit -> GR8_ABCD_L
7807 5, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
7808 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_8bit_hi_phony
7809 22, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_16bit -> GR16_ABCD
7810 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_16bit_hi
7811 53, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_32bit -> GR32_ArgRef
7812 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_mask_0
7813 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_mask_1
7814 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_xmm
7815 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_ymm
7816 },
7817 { // GR64_with_sub_32bit_in_GR32_BPSP
7818 3, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit -> GR8_NOREX2
7819 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit_hi
7820 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit_hi_phony
7821 10, // GR64_with_sub_32bit_in_GR32_BPSP:sub_16bit -> GR16_NOREX
7822 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_16bit_hi
7823 54, // GR64_with_sub_32bit_in_GR32_BPSP:sub_32bit -> GR32_BPSP
7824 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_mask_0
7825 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_mask_1
7826 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_xmm
7827 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_ymm
7828 },
7829 { // GR64_with_sub_32bit_in_GR32_BSI
7830 3, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit -> GR8_NOREX2
7831 5, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
7832 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit_hi_phony
7833 10, // GR64_with_sub_32bit_in_GR32_BSI:sub_16bit -> GR16_NOREX
7834 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_16bit_hi
7835 55, // GR64_with_sub_32bit_in_GR32_BSI:sub_32bit -> GR32_BSI
7836 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_mask_0
7837 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_mask_1
7838 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_xmm
7839 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_ymm
7840 },
7841 { // GR64_with_sub_32bit_in_GR32_CB
7842 6, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit -> GR8_ABCD_L
7843 5, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
7844 0, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit_hi_phony
7845 22, // GR64_with_sub_32bit_in_GR32_CB:sub_16bit -> GR16_ABCD
7846 0, // GR64_with_sub_32bit_in_GR32_CB:sub_16bit_hi
7847 56, // GR64_with_sub_32bit_in_GR32_CB:sub_32bit -> GR32_CB
7848 0, // GR64_with_sub_32bit_in_GR32_CB:sub_mask_0
7849 0, // GR64_with_sub_32bit_in_GR32_CB:sub_mask_1
7850 0, // GR64_with_sub_32bit_in_GR32_CB:sub_xmm
7851 0, // GR64_with_sub_32bit_in_GR32_CB:sub_ymm
7852 },
7853 { // GR64_with_sub_32bit_in_GR32_DIBP
7854 3, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit -> GR8_NOREX2
7855 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit_hi
7856 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit_hi_phony
7857 10, // GR64_with_sub_32bit_in_GR32_DIBP:sub_16bit -> GR16_NOREX
7858 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_16bit_hi
7859 58, // GR64_with_sub_32bit_in_GR32_DIBP:sub_32bit -> GR32_DIBP
7860 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_mask_0
7861 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_mask_1
7862 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_xmm
7863 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_ymm
7864 },
7865 { // GR64_with_sub_32bit_in_GR32_SIDI
7866 3, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit -> GR8_NOREX2
7867 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit_hi
7868 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit_hi_phony
7869 10, // GR64_with_sub_32bit_in_GR32_SIDI:sub_16bit -> GR16_NOREX
7870 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_16bit_hi
7871 59, // GR64_with_sub_32bit_in_GR32_SIDI:sub_32bit -> GR32_SIDI
7872 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_mask_0
7873 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_mask_1
7874 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_xmm
7875 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_ymm
7876 },
7877 { // GR64_A
7878 6, // GR64_A:sub_8bit -> GR8_ABCD_L
7879 5, // GR64_A:sub_8bit_hi -> GR8_ABCD_H
7880 0, // GR64_A:sub_8bit_hi_phony
7881 22, // GR64_A:sub_16bit -> GR16_ABCD
7882 0, // GR64_A:sub_16bit_hi
7883 52, // GR64_A:sub_32bit -> GR32_AD
7884 0, // GR64_A:sub_mask_0
7885 0, // GR64_A:sub_mask_1
7886 0, // GR64_A:sub_xmm
7887 0, // GR64_A:sub_ymm
7888 },
7889 { // GR64_ArgRef_and_GR64_TC
7890 3, // GR64_ArgRef_and_GR64_TC:sub_8bit -> GR8_NOREX2
7891 0, // GR64_ArgRef_and_GR64_TC:sub_8bit_hi
7892 0, // GR64_ArgRef_and_GR64_TC:sub_8bit_hi_phony
7893 9, // GR64_ArgRef_and_GR64_TC:sub_16bit -> GR16_NOREX2
7894 0, // GR64_ArgRef_and_GR64_TC:sub_16bit_hi
7895 42, // GR64_ArgRef_and_GR64_TC:sub_32bit -> GR32_NOREX2_NOSP
7896 0, // GR64_ArgRef_and_GR64_TC:sub_mask_0
7897 0, // GR64_ArgRef_and_GR64_TC:sub_mask_1
7898 0, // GR64_ArgRef_and_GR64_TC:sub_xmm
7899 0, // GR64_ArgRef_and_GR64_TC:sub_ymm
7900 },
7901 { // GR64_and_LOW32_ADDR_ACCESS
7902 0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit
7903 0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit_hi
7904 0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit_hi_phony
7905 0, // GR64_and_LOW32_ADDR_ACCESS:sub_16bit
7906 0, // GR64_and_LOW32_ADDR_ACCESS:sub_16bit_hi
7907 0, // GR64_and_LOW32_ADDR_ACCESS:sub_32bit
7908 0, // GR64_and_LOW32_ADDR_ACCESS:sub_mask_0
7909 0, // GR64_and_LOW32_ADDR_ACCESS:sub_mask_1
7910 0, // GR64_and_LOW32_ADDR_ACCESS:sub_xmm
7911 0, // GR64_and_LOW32_ADDR_ACCESS:sub_ymm
7912 },
7913 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
7914 6, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit -> GR8_ABCD_L
7915 5, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
7916 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit_hi_phony
7917 22, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_16bit -> GR16_ABCD
7918 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_16bit_hi
7919 63, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_32bit -> GR32_ABCD_and_GR32_BSI
7920 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_mask_0
7921 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_mask_1
7922 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_xmm
7923 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_ymm
7924 },
7925 { // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
7926 6, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_8bit -> GR8_ABCD_L
7927 5, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
7928 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_8bit_hi_phony
7929 22, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_16bit -> GR16_ABCD
7930 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_16bit_hi
7931 64, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_32bit -> GR32_AD_and_GR32_ArgRef
7932 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_mask_0
7933 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_mask_1
7934 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_xmm
7935 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_ymm
7936 },
7937 { // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
7938 6, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_8bit -> GR8_ABCD_L
7939 5, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
7940 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_8bit_hi_phony
7941 22, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_16bit -> GR16_ABCD
7942 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_16bit_hi
7943 65, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_32bit -> GR32_ArgRef_and_GR32_CB
7944 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_mask_0
7945 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_mask_1
7946 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_xmm
7947 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_ymm
7948 },
7949 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
7950 3, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit -> GR8_NOREX2
7951 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit_hi
7952 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit_hi_phony
7953 10, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_16bit -> GR16_NOREX
7954 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_16bit_hi
7955 66, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
7956 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_mask_0
7957 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_mask_1
7958 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_xmm
7959 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_ymm
7960 },
7961 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
7962 3, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit -> GR8_NOREX2
7963 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit_hi
7964 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit_hi_phony
7965 10, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_16bit -> GR16_NOREX
7966 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_16bit_hi
7967 67, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_32bit -> GR32_BPSP_and_GR32_TC
7968 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_mask_0
7969 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_mask_1
7970 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_xmm
7971 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_ymm
7972 },
7973 { // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
7974 3, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
7975 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit_hi
7976 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit_hi_phony
7977 10, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_16bit -> GR16_NOREX
7978 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_16bit_hi
7979 68, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_32bit -> GR32_BSI_and_GR32_SIDI
7980 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_mask_0
7981 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_mask_1
7982 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_xmm
7983 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_ymm
7984 },
7985 { // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
7986 3, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
7987 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit_hi
7988 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit_hi_phony
7989 10, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_16bit -> GR16_NOREX
7990 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_16bit_hi
7991 69, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_32bit -> GR32_DIBP_and_GR32_SIDI
7992 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_mask_0
7993 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_mask_1
7994 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_xmm
7995 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_ymm
7996 },
7997 { // RST
7998 0, // RST:sub_8bit
7999 0, // RST:sub_8bit_hi
8000 0, // RST:sub_8bit_hi_phony
8001 0, // RST:sub_16bit
8002 0, // RST:sub_16bit_hi
8003 0, // RST:sub_32bit
8004 0, // RST:sub_mask_0
8005 0, // RST:sub_mask_1
8006 0, // RST:sub_xmm
8007 0, // RST:sub_ymm
8008 },
8009 { // RFP80
8010 0, // RFP80:sub_8bit
8011 0, // RFP80:sub_8bit_hi
8012 0, // RFP80:sub_8bit_hi_phony
8013 0, // RFP80:sub_16bit
8014 0, // RFP80:sub_16bit_hi
8015 0, // RFP80:sub_32bit
8016 0, // RFP80:sub_mask_0
8017 0, // RFP80:sub_mask_1
8018 0, // RFP80:sub_xmm
8019 0, // RFP80:sub_ymm
8020 },
8021 { // RFP80_7
8022 0, // RFP80_7:sub_8bit
8023 0, // RFP80_7:sub_8bit_hi
8024 0, // RFP80_7:sub_8bit_hi_phony
8025 0, // RFP80_7:sub_16bit
8026 0, // RFP80_7:sub_16bit_hi
8027 0, // RFP80_7:sub_32bit
8028 0, // RFP80_7:sub_mask_0
8029 0, // RFP80_7:sub_mask_1
8030 0, // RFP80_7:sub_xmm
8031 0, // RFP80_7:sub_ymm
8032 },
8033 { // VR128X
8034 0, // VR128X:sub_8bit
8035 0, // VR128X:sub_8bit_hi
8036 0, // VR128X:sub_8bit_hi_phony
8037 0, // VR128X:sub_16bit
8038 0, // VR128X:sub_16bit_hi
8039 0, // VR128X:sub_32bit
8040 0, // VR128X:sub_mask_0
8041 0, // VR128X:sub_mask_1
8042 0, // VR128X:sub_xmm
8043 0, // VR128X:sub_ymm
8044 },
8045 { // VR128
8046 0, // VR128:sub_8bit
8047 0, // VR128:sub_8bit_hi
8048 0, // VR128:sub_8bit_hi_phony
8049 0, // VR128:sub_16bit
8050 0, // VR128:sub_16bit_hi
8051 0, // VR128:sub_32bit
8052 0, // VR128:sub_mask_0
8053 0, // VR128:sub_mask_1
8054 0, // VR128:sub_xmm
8055 0, // VR128:sub_ymm
8056 },
8057 { // VR256X
8058 0, // VR256X:sub_8bit
8059 0, // VR256X:sub_8bit_hi
8060 0, // VR256X:sub_8bit_hi_phony
8061 0, // VR256X:sub_16bit
8062 0, // VR256X:sub_16bit_hi
8063 0, // VR256X:sub_32bit
8064 0, // VR256X:sub_mask_0
8065 0, // VR256X:sub_mask_1
8066 24, // VR256X:sub_xmm -> FR16X
8067 0, // VR256X:sub_ymm
8068 },
8069 { // VR256
8070 0, // VR256:sub_8bit
8071 0, // VR256:sub_8bit_hi
8072 0, // VR256:sub_8bit_hi_phony
8073 0, // VR256:sub_16bit
8074 0, // VR256:sub_16bit_hi
8075 0, // VR256:sub_32bit
8076 0, // VR256:sub_mask_0
8077 0, // VR256:sub_mask_1
8078 25, // VR256:sub_xmm -> FR16
8079 0, // VR256:sub_ymm
8080 },
8081 { // VR512
8082 0, // VR512:sub_8bit
8083 0, // VR512:sub_8bit_hi
8084 0, // VR512:sub_8bit_hi_phony
8085 0, // VR512:sub_16bit
8086 0, // VR512:sub_16bit_hi
8087 0, // VR512:sub_32bit
8088 0, // VR512:sub_mask_0
8089 0, // VR512:sub_mask_1
8090 24, // VR512:sub_xmm -> FR16X
8091 131, // VR512:sub_ymm -> VR256X
8092 },
8093 { // VR512_0_15
8094 0, // VR512_0_15:sub_8bit
8095 0, // VR512_0_15:sub_8bit_hi
8096 0, // VR512_0_15:sub_8bit_hi_phony
8097 0, // VR512_0_15:sub_16bit
8098 0, // VR512_0_15:sub_16bit_hi
8099 0, // VR512_0_15:sub_32bit
8100 0, // VR512_0_15:sub_mask_0
8101 0, // VR512_0_15:sub_mask_1
8102 25, // VR512_0_15:sub_xmm -> FR16
8103 132, // VR512_0_15:sub_ymm -> VR256
8104 },
8105 { // TILE
8106 0, // TILE:sub_8bit
8107 0, // TILE:sub_8bit_hi
8108 0, // TILE:sub_8bit_hi_phony
8109 0, // TILE:sub_16bit
8110 0, // TILE:sub_16bit_hi
8111 0, // TILE:sub_32bit
8112 0, // TILE:sub_mask_0
8113 0, // TILE:sub_mask_1
8114 0, // TILE:sub_xmm
8115 0, // TILE:sub_ymm
8116 },
8117
8118 };
8119 assert(RC && "Missing regclass");
8120 if (!Idx) return RC;
8121 --Idx;
8122 assert(Idx < 10 && "Bad subreg");
8123 unsigned TV = Table[RC->getID()][Idx];
8124 return TV ? getRegClass(i: TV - 1) : nullptr;
8125}/// Get the weight in units of pressure for this register class.
8126const RegClassWeight &X86GenRegisterInfo::
8127getRegClassWeight(const TargetRegisterClass *RC) const {
8128 static const RegClassWeight RCWeightTable[] = {
8129 {.RegWeight: 1, .WeightLimit: 36}, // GR8
8130 {.RegWeight: 0, .WeightLimit: 0}, // GRH8
8131 {.RegWeight: 1, .WeightLimit: 20}, // GR8_NOREX2
8132 {.RegWeight: 1, .WeightLimit: 8}, // GR8_NOREX
8133 {.RegWeight: 1, .WeightLimit: 4}, // GR8_ABCD_H
8134 {.RegWeight: 1, .WeightLimit: 4}, // GR8_ABCD_L
8135 {.RegWeight: 0, .WeightLimit: 0}, // GRH16
8136 {.RegWeight: 2, .WeightLimit: 64}, // GR16
8137 {.RegWeight: 2, .WeightLimit: 32}, // GR16_NOREX2
8138 {.RegWeight: 2, .WeightLimit: 16}, // GR16_NOREX
8139 {.RegWeight: 1, .WeightLimit: 8}, // VK1
8140 {.RegWeight: 1, .WeightLimit: 8}, // VK16
8141 {.RegWeight: 1, .WeightLimit: 8}, // VK2
8142 {.RegWeight: 1, .WeightLimit: 8}, // VK4
8143 {.RegWeight: 1, .WeightLimit: 8}, // VK8
8144 {.RegWeight: 1, .WeightLimit: 7}, // VK16WM
8145 {.RegWeight: 1, .WeightLimit: 7}, // VK1WM
8146 {.RegWeight: 1, .WeightLimit: 7}, // VK2WM
8147 {.RegWeight: 1, .WeightLimit: 7}, // VK4WM
8148 {.RegWeight: 1, .WeightLimit: 7}, // VK8WM
8149 {.RegWeight: 1, .WeightLimit: 6}, // SEGMENT_REG
8150 {.RegWeight: 2, .WeightLimit: 8}, // GR16_ABCD
8151 {.RegWeight: 0, .WeightLimit: 0}, // FPCCR
8152 {.RegWeight: 1, .WeightLimit: 32}, // FR16X
8153 {.RegWeight: 1, .WeightLimit: 16}, // FR16
8154 {.RegWeight: 2, .WeightLimit: 8}, // VK16PAIR
8155 {.RegWeight: 2, .WeightLimit: 8}, // VK1PAIR
8156 {.RegWeight: 2, .WeightLimit: 8}, // VK2PAIR
8157 {.RegWeight: 2, .WeightLimit: 8}, // VK4PAIR
8158 {.RegWeight: 2, .WeightLimit: 8}, // VK8PAIR
8159 {.RegWeight: 2, .WeightLimit: 6}, // VK1PAIR_with_sub_mask_0_in_VK1WM
8160 {.RegWeight: 2, .WeightLimit: 66}, // LOW32_ADDR_ACCESS_RBP
8161 {.RegWeight: 2, .WeightLimit: 66}, // LOW32_ADDR_ACCESS
8162 {.RegWeight: 2, .WeightLimit: 64}, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
8163 {.RegWeight: 1, .WeightLimit: 32}, // FR32X
8164 {.RegWeight: 2, .WeightLimit: 64}, // GR32
8165 {.RegWeight: 2, .WeightLimit: 62}, // GR32_NOSP
8166 {.RegWeight: 2, .WeightLimit: 32}, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
8167 {.RegWeight: 1, .WeightLimit: 16}, // DEBUG_REG
8168 {.RegWeight: 1, .WeightLimit: 16}, // FR32
8169 {.RegWeight: 2, .WeightLimit: 32}, // GR32_NOREX2
8170 {.RegWeight: 2, .WeightLimit: 30}, // GR32_NOREX2_NOSP
8171 {.RegWeight: 2, .WeightLimit: 16}, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
8172 {.RegWeight: 2, .WeightLimit: 16}, // GR32_NOREX
8173 {.RegWeight: 1, .WeightLimit: 8}, // VK32
8174 {.RegWeight: 2, .WeightLimit: 14}, // GR32_NOREX_NOSP
8175 {.RegWeight: 1, .WeightLimit: 7}, // RFP32
8176 {.RegWeight: 1, .WeightLimit: 7}, // VK32WM
8177 {.RegWeight: 2, .WeightLimit: 8}, // GR32_ABCD
8178 {.RegWeight: 2, .WeightLimit: 8}, // GR32_TC
8179 {.RegWeight: 2, .WeightLimit: 6}, // GR32_ABCD_and_GR32_TC
8180 {.RegWeight: 2, .WeightLimit: 4}, // GR32_AD
8181 {.RegWeight: 2, .WeightLimit: 4}, // GR32_ArgRef
8182 {.RegWeight: 2, .WeightLimit: 4}, // GR32_BPSP
8183 {.RegWeight: 2, .WeightLimit: 4}, // GR32_BSI
8184 {.RegWeight: 2, .WeightLimit: 4}, // GR32_CB
8185 {.RegWeight: 2, .WeightLimit: 4}, // GR32_DC
8186 {.RegWeight: 2, .WeightLimit: 4}, // GR32_DIBP
8187 {.RegWeight: 2, .WeightLimit: 4}, // GR32_SIDI
8188 {.RegWeight: 2, .WeightLimit: 4}, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
8189 {.RegWeight: 0, .WeightLimit: 0}, // CCR
8190 {.RegWeight: 0, .WeightLimit: 0}, // DFCCR
8191 {.RegWeight: 2, .WeightLimit: 2}, // GR32_ABCD_and_GR32_BSI
8192 {.RegWeight: 2, .WeightLimit: 2}, // GR32_AD_and_GR32_ArgRef
8193 {.RegWeight: 2, .WeightLimit: 2}, // GR32_ArgRef_and_GR32_CB
8194 {.RegWeight: 2, .WeightLimit: 2}, // GR32_BPSP_and_GR32_DIBP
8195 {.RegWeight: 2, .WeightLimit: 2}, // GR32_BPSP_and_GR32_TC
8196 {.RegWeight: 2, .WeightLimit: 2}, // GR32_BSI_and_GR32_SIDI
8197 {.RegWeight: 2, .WeightLimit: 2}, // GR32_DIBP_and_GR32_SIDI
8198 {.RegWeight: 2, .WeightLimit: 2}, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
8199 {.RegWeight: 2, .WeightLimit: 2}, // LOW32_ADDR_ACCESS_with_sub_32bit
8200 {.RegWeight: 1, .WeightLimit: 7}, // RFP64
8201 {.RegWeight: 2, .WeightLimit: 66}, // GR64
8202 {.RegWeight: 1, .WeightLimit: 32}, // FR64X
8203 {.RegWeight: 2, .WeightLimit: 64}, // GR64_with_sub_8bit
8204 {.RegWeight: 2, .WeightLimit: 62}, // GR64_NOSP
8205 {.RegWeight: 2, .WeightLimit: 34}, // GR64_NOREX2
8206 {.RegWeight: 1, .WeightLimit: 16}, // CONTROL_REG
8207 {.RegWeight: 1, .WeightLimit: 16}, // FR64
8208 {.RegWeight: 2, .WeightLimit: 32}, // GR64_with_sub_16bit_in_GR16_NOREX2
8209 {.RegWeight: 2, .WeightLimit: 30}, // GR64_NOREX2_NOSP
8210 {.RegWeight: 2, .WeightLimit: 26}, // GR64PLTSafe
8211 {.RegWeight: 2, .WeightLimit: 20}, // GR64_TC
8212 {.RegWeight: 2, .WeightLimit: 18}, // GR64_NOREX
8213 {.RegWeight: 2, .WeightLimit: 18}, // GR64_TCW64
8214 {.RegWeight: 2, .WeightLimit: 18}, // GR64_TC_with_sub_8bit
8215 {.RegWeight: 2, .WeightLimit: 16}, // GR64_NOREX2_NOSP_and_GR64_TC
8216 {.RegWeight: 2, .WeightLimit: 16}, // GR64_TCW64_with_sub_8bit
8217 {.RegWeight: 2, .WeightLimit: 16}, // GR64_TC_and_GR64_TCW64
8218 {.RegWeight: 2, .WeightLimit: 16}, // GR64_with_sub_16bit_in_GR16_NOREX
8219 {.RegWeight: 1, .WeightLimit: 8}, // VK64
8220 {.RegWeight: 1, .WeightLimit: 8}, // VR64
8221 {.RegWeight: 2, .WeightLimit: 14}, // GR64PLTSafe_and_GR64_TC
8222 {.RegWeight: 2, .WeightLimit: 14}, // GR64_NOREX2_NOSP_and_GR64_TCW64
8223 {.RegWeight: 2, .WeightLimit: 14}, // GR64_NOREX_NOSP
8224 {.RegWeight: 2, .WeightLimit: 14}, // GR64_NOREX_and_GR64_TC
8225 {.RegWeight: 2, .WeightLimit: 14}, // GR64_TCW64_and_GR64_TC_with_sub_8bit
8226 {.RegWeight: 1, .WeightLimit: 7}, // VK64WM
8227 {.RegWeight: 2, .WeightLimit: 12}, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
8228 {.RegWeight: 2, .WeightLimit: 12}, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
8229 {.RegWeight: 2, .WeightLimit: 10}, // GR64PLTSafe_and_GR64_TCW64
8230 {.RegWeight: 2, .WeightLimit: 10}, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
8231 {.RegWeight: 2, .WeightLimit: 10}, // GR64_NOREX_and_GR64_TCW64
8232 {.RegWeight: 2, .WeightLimit: 8}, // GR64_ABCD
8233 {.RegWeight: 2, .WeightLimit: 8}, // GR64_with_sub_32bit_in_GR32_TC
8234 {.RegWeight: 2, .WeightLimit: 6}, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
8235 {.RegWeight: 2, .WeightLimit: 4}, // GR64_AD
8236 {.RegWeight: 2, .WeightLimit: 4}, // GR64_ArgRef
8237 {.RegWeight: 2, .WeightLimit: 4}, // GR64_and_LOW32_ADDR_ACCESS_RBP
8238 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_ArgRef
8239 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_BPSP
8240 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_BSI
8241 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_CB
8242 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_DIBP
8243 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_SIDI
8244 {.RegWeight: 2, .WeightLimit: 2}, // GR64_A
8245 {.RegWeight: 2, .WeightLimit: 2}, // GR64_ArgRef_and_GR64_TC
8246 {.RegWeight: 2, .WeightLimit: 2}, // GR64_and_LOW32_ADDR_ACCESS
8247 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
8248 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
8249 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
8250 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
8251 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
8252 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
8253 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
8254 {.RegWeight: 0, .WeightLimit: 0}, // RST
8255 {.RegWeight: 1, .WeightLimit: 7}, // RFP80
8256 {.RegWeight: 0, .WeightLimit: 0}, // RFP80_7
8257 {.RegWeight: 1, .WeightLimit: 32}, // VR128X
8258 {.RegWeight: 1, .WeightLimit: 16}, // VR128
8259 {.RegWeight: 1, .WeightLimit: 32}, // VR256X
8260 {.RegWeight: 1, .WeightLimit: 16}, // VR256
8261 {.RegWeight: 1, .WeightLimit: 32}, // VR512
8262 {.RegWeight: 1, .WeightLimit: 16}, // VR512_0_15
8263 {.RegWeight: 1, .WeightLimit: 8}, // TILE
8264 };
8265 return RCWeightTable[RC->getID()];
8266}
8267
8268/// Get the weight in units of pressure for this register unit.
8269unsigned X86GenRegisterInfo::
8270getRegUnitWeight(MCRegUnit RegUnit) const {
8271 assert(static_cast<unsigned>(RegUnit) < 221 && "invalid register unit");
8272 // All register units have unit weight.
8273 return 1;
8274}
8275
8276
8277// Get the number of dimensions of register pressure.
8278unsigned X86GenRegisterInfo::getNumRegPressureSets() const {
8279 return 36;
8280}
8281
8282// Get the name of this register unit pressure set.
8283const char *X86GenRegisterInfo::
8284getRegPressureSetName(unsigned Idx) const {
8285 static const char *PressureNameTable[] = {
8286 "SEGMENT_REG",
8287 "GR32_BPSP",
8288 "LOW32_ADDR_ACCESS_with_sub_32bit",
8289 "GR32_BSI",
8290 "GR32_SIDI",
8291 "GR32_DIBP_with_GR32_SIDI",
8292 "GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit",
8293 "RFP32",
8294 "GR8_ABCD_H_with_GR32_BSI",
8295 "GR8_ABCD_L_with_GR32_BSI",
8296 "VK1",
8297 "VR64",
8298 "TILE",
8299 "GR8_NOREX",
8300 "GR32_TC",
8301 "GR32_BPSP_with_GR32_TC",
8302 "FR16",
8303 "DEBUG_REG",
8304 "CONTROL_REG",
8305 "GR64_NOREX",
8306 "GR64_TCW64",
8307 "GR32_BPSP_with_GR64_TCW64",
8308 "GR64_TC_with_GR64_TCW64",
8309 "GR64_TC",
8310 "FR16X",
8311 "GR64PLTSafe_with_GR64_TC",
8312 "GR8",
8313 "GR8_with_GR32_DIBP",
8314 "GR8_with_GR32_BSI",
8315 "GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit",
8316 "GR8_with_GR64_NOREX",
8317 "GR8_with_GR64_TCW64",
8318 "GR8_with_GR64_TC",
8319 "GR8_with_GR64PLTSafe",
8320 "GR8_with_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2",
8321 "GR16",
8322 };
8323 return PressureNameTable[Idx];
8324}
8325
8326// Get the register unit pressure limit for this dimension.
8327// This limit must be adjusted dynamically for reserved registers.
8328unsigned X86GenRegisterInfo::
8329getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
8330 static const uint8_t PressureLimitTable[] = {
8331 6, // 0: SEGMENT_REG
8332 6, // 1: GR32_BPSP
8333 6, // 2: LOW32_ADDR_ACCESS_with_sub_32bit
8334 6, // 3: GR32_BSI
8335 6, // 4: GR32_SIDI
8336 6, // 5: GR32_DIBP_with_GR32_SIDI
8337 6, // 6: GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit
8338 7, // 7: RFP32
8339 7, // 8: GR8_ABCD_H_with_GR32_BSI
8340 7, // 9: GR8_ABCD_L_with_GR32_BSI
8341 8, // 10: VK1
8342 8, // 11: VR64
8343 8, // 12: TILE
8344 10, // 13: GR8_NOREX
8345 12, // 14: GR32_TC
8346 12, // 15: GR32_BPSP_with_GR32_TC
8347 16, // 16: FR16
8348 16, // 17: DEBUG_REG
8349 16, // 18: CONTROL_REG
8350 18, // 19: GR64_NOREX
8351 20, // 20: GR64_TCW64
8352 20, // 21: GR32_BPSP_with_GR64_TCW64
8353 22, // 22: GR64_TC_with_GR64_TCW64
8354 26, // 23: GR64_TC
8355 32, // 24: FR16X
8356 34, // 25: GR64PLTSafe_with_GR64_TC
8357 38, // 26: GR8
8358 38, // 27: GR8_with_GR32_DIBP
8359 38, // 28: GR8_with_GR32_BSI
8360 39, // 29: GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit
8361 42, // 30: GR8_with_GR64_NOREX
8362 43, // 31: GR8_with_GR64_TCW64
8363 44, // 32: GR8_with_GR64_TC
8364 45, // 33: GR8_with_GR64PLTSafe
8365 48, // 34: GR8_with_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
8366 66, // 35: GR16
8367 };
8368 return PressureLimitTable[Idx];
8369}
8370
8371/// Table of pressure sets per register class or unit.
8372static const int RCSetsTable[] = {
8373 /* 0 */ 0, -1,
8374 /* 2 */ 7, -1,
8375 /* 4 */ 10, -1,
8376 /* 6 */ 11, -1,
8377 /* 8 */ 12, -1,
8378 /* 10 */ 17, -1,
8379 /* 12 */ 18, -1,
8380 /* 14 */ 16, 24, -1,
8381 /* 17 */ 25, 35, -1,
8382 /* 20 */ 19, 23, 25, 30, 35, -1,
8383 /* 26 */ 2, 6, 15, 19, 21, 23, 25, 29, 30, 35, -1,
8384 /* 37 */ 20, 21, 22, 23, 25, 31, 35, -1,
8385 /* 45 */ 22, 23, 25, 32, 35, -1,
8386 /* 51 */ 19, 22, 23, 25, 30, 32, 35, -1,
8387 /* 59 */ 20, 21, 22, 23, 25, 31, 32, 35, -1,
8388 /* 68 */ 14, 15, 19, 20, 21, 22, 23, 25, 30, 31, 32, 35, -1,
8389 /* 81 */ 2, 6, 14, 15, 19, 20, 21, 22, 23, 25, 29, 30, 31, 32, 35, -1,
8390 /* 97 */ 25, 34, 35, -1,
8391 /* 101 */ 19, 23, 25, 30, 34, 35, -1,
8392 /* 108 */ 1, 2, 15, 19, 21, 23, 25, 26, 30, 34, 35, -1,
8393 /* 120 */ 20, 21, 22, 23, 25, 31, 34, 35, -1,
8394 /* 129 */ 22, 23, 25, 32, 34, 35, -1,
8395 /* 136 */ 19, 22, 23, 25, 30, 32, 34, 35, -1,
8396 /* 145 */ 20, 21, 22, 23, 25, 31, 32, 34, 35, -1,
8397 /* 155 */ 1, 2, 14, 15, 19, 20, 21, 22, 23, 25, 26, 30, 31, 32, 34, 35, -1,
8398 /* 172 */ 25, 33, 34, 35, -1,
8399 /* 177 */ 19, 23, 25, 30, 33, 34, 35, -1,
8400 /* 185 */ 1, 5, 6, 19, 23, 25, 27, 30, 33, 34, 35, -1,
8401 /* 197 */ 1, 2, 5, 6, 15, 19, 21, 23, 25, 26, 27, 29, 30, 33, 34, 35, -1,
8402 /* 214 */ 22, 23, 25, 32, 33, 34, 35, -1,
8403 /* 222 */ 3, 4, 8, 9, 13, 19, 23, 25, 28, 30, 32, 33, 34, 35, -1,
8404 /* 237 */ 4, 5, 19, 22, 23, 25, 28, 30, 32, 33, 34, 35, -1,
8405 /* 250 */ 3, 4, 5, 8, 9, 13, 19, 22, 23, 25, 28, 30, 32, 33, 34, 35, -1,
8406 /* 267 */ 1, 4, 5, 6, 19, 22, 23, 25, 27, 28, 30, 32, 33, 34, 35, -1,
8407 /* 283 */ 20, 21, 22, 23, 25, 31, 32, 33, 34, 35, -1,
8408 /* 294 */ 3, 13, 14, 19, 20, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8409 /* 312 */ 8, 13, 14, 19, 20, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8410 /* 330 */ 3, 4, 8, 9, 13, 14, 19, 20, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8411 /* 351 */ 1, 2, 5, 6, 15, 19, 21, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8412 /* 371 */ 1, 4, 5, 6, 19, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8413 /* 390 */ 3, 4, 5, 8, 9, 13, 19, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8414 /* 411 */ 1, 2, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8415 /* 432 */ 3, 13, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8416 /* 453 */ 3, 8, 13, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8417 /* 475 */ 3, 9, 13, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8418};
8419
8420/// Get the dimensions of register pressure impacted by this register class.
8421/// Returns a -1 terminated array of pressure set IDs
8422const int *X86GenRegisterInfo::
8423getRegClassPressureSets(const TargetRegisterClass *RC) const {
8424 static const uint16_t RCSetStartTable[] = {
8425 301,1,300,295,312,333,1,18,97,101,4,4,4,4,4,4,4,4,4,4,0,295,1,15,14,4,4,4,4,4,4,18,18,18,15,18,18,97,10,14,97,97,101,101,4,177,2,4,295,157,433,433,433,108,222,294,433,185,237,26,1,1,330,433,432,197,155,250,267,197,81,2,18,15,18,18,17,12,14,97,97,172,45,20,37,129,129,120,59,101,4,6,214,120,177,51,145,4,145,136,283,239,68,295,157,433,433,120,26,433,108,222,294,185,237,433,145,81,330,433,432,197,155,250,267,1,2,1,15,14,15,14,15,14,8,};
8426 return &RCSetsTable[RCSetStartTable[RC->getID()]];
8427}
8428
8429/// Get the dimensions of register pressure impacted by this register unit.
8430/// Returns a -1 terminated array of pressure set IDs
8431const int *X86GenRegisterInfo::
8432getRegUnitPressureSets(MCRegUnit RegUnit) const {
8433 assert(static_cast<unsigned>(RegUnit) < 221 && "invalid register unit");
8434 static const uint16_t RUSetStartTable[] = {
8435 454,476,330,330,351,1,453,475,0,1,454,371,1,476,0,1,1,1,1,1,1,1,81,1,1,0,390,1,1,411,1,1,1,1,0,1,0,1,1,1,1,0,1,1,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,2,2,2,2,2,2,2,1,6,6,6,6,6,6,6,6,416,1,1,416,1,1,416,1,1,416,1,1,300,1,1,300,1,1,300,1,1,300,1,1,1,1,1,1,1,1,1,1,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,4,4,4,4,4,4,4,4,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,1,8,8,8,8,8,8,8,8,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,};
8436 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
8437}
8438
8439
8440// Register to minimal register class mapping
8441
8442const TargetRegisterClass *X86GenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
8443 static const uint16_t InvalidRegClassID = UINT16_MAX;
8444
8445 static const uint16_t Mapping[388] = {
8446 InvalidRegClassID, // NoRegister
8447 X86::GR8_ABCD_HRegClassID, // AH
8448 X86::GR8_ABCD_LRegClassID, // AL
8449 X86::GR16_ABCDRegClassID, // AX
8450 X86::GR8_ABCD_HRegClassID, // BH
8451 X86::GR8_ABCD_LRegClassID, // BL
8452 X86::GR16_NOREXRegClassID, // BP
8453 X86::GRH8RegClassID, // BPH
8454 X86::GR8_NOREX2RegClassID, // BPL
8455 X86::GR16_ABCDRegClassID, // BX
8456 X86::GR8_ABCD_HRegClassID, // CH
8457 X86::GR8_ABCD_LRegClassID, // CL
8458 X86::SEGMENT_REGRegClassID, // CS
8459 X86::GR16_ABCDRegClassID, // CX
8460 X86::DFCCRRegClassID, // DF
8461 X86::GR8_ABCD_HRegClassID, // DH
8462 X86::GR16_NOREXRegClassID, // DI
8463 X86::GRH8RegClassID, // DIH
8464 X86::GR8_NOREX2RegClassID, // DIL
8465 X86::GR8_ABCD_LRegClassID, // DL
8466 X86::SEGMENT_REGRegClassID, // DS
8467 X86::GR16_ABCDRegClassID, // DX
8468 X86::GR32_ADRegClassID, // EAX
8469 X86::GR32_BPSP_and_GR32_DIBPRegClassID, // EBP
8470 X86::GR32_ABCD_and_GR32_BSIRegClassID, // EBX
8471 X86::GR32_ArgRef_and_GR32_CBRegClassID, // ECX
8472 X86::GR32_DIBP_and_GR32_SIDIRegClassID, // EDI
8473 X86::GR32_AD_and_GR32_ArgRefRegClassID, // EDX
8474 X86::CCRRegClassID, // EFLAGS
8475 InvalidRegClassID, // EIP
8476 InvalidRegClassID, // EIZ
8477 X86::SEGMENT_REGRegClassID, // ES
8478 X86::GR32_BSI_and_GR32_SIDIRegClassID, // ESI
8479 X86::GR32_BPSP_and_GR32_TCRegClassID, // ESP
8480 InvalidRegClassID, // FPCW
8481 X86::FPCCRRegClassID, // FPSW
8482 X86::SEGMENT_REGRegClassID, // FS
8483 InvalidRegClassID, // FS_BASE
8484 X86::SEGMENT_REGRegClassID, // GS
8485 InvalidRegClassID, // GS_BASE
8486 X86::GRH16RegClassID, // HAX
8487 X86::GRH16RegClassID, // HBP
8488 X86::GRH16RegClassID, // HBX
8489 X86::GRH16RegClassID, // HCX
8490 X86::GRH16RegClassID, // HDI
8491 X86::GRH16RegClassID, // HDX
8492 X86::GRH16RegClassID, // HIP
8493 X86::GRH16RegClassID, // HSI
8494 X86::GRH16RegClassID, // HSP
8495 InvalidRegClassID, // IP
8496 InvalidRegClassID, // MXCSR
8497 X86::GR64_ARegClassID, // RAX
8498 X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID, // RBP
8499 X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID, // RBX
8500 X86::GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID, // RCX
8501 X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID, // RDI
8502 X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID, // RDX
8503 InvalidRegClassID, // RFLAGS
8504 X86::GR64_and_LOW32_ADDR_ACCESSRegClassID, // RIP
8505 InvalidRegClassID, // RIZ
8506 X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID, // RSI
8507 X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID, // RSP
8508 X86::GR16_NOREXRegClassID, // SI
8509 X86::GRH8RegClassID, // SIH
8510 X86::GR8_NOREX2RegClassID, // SIL
8511 X86::GR16_NOREXRegClassID, // SP
8512 X86::GRH8RegClassID, // SPH
8513 X86::GR8_NOREX2RegClassID, // SPL
8514 X86::SEGMENT_REGRegClassID, // SS
8515 InvalidRegClassID, // SSP
8516 InvalidRegClassID, // _EFLAGS
8517 X86::CONTROL_REGRegClassID, // CR0
8518 X86::CONTROL_REGRegClassID, // CR1
8519 X86::CONTROL_REGRegClassID, // CR2
8520 X86::CONTROL_REGRegClassID, // CR3
8521 X86::CONTROL_REGRegClassID, // CR4
8522 X86::CONTROL_REGRegClassID, // CR5
8523 X86::CONTROL_REGRegClassID, // CR6
8524 X86::CONTROL_REGRegClassID, // CR7
8525 X86::CONTROL_REGRegClassID, // CR8
8526 X86::CONTROL_REGRegClassID, // CR9
8527 X86::CONTROL_REGRegClassID, // CR10
8528 X86::CONTROL_REGRegClassID, // CR11
8529 X86::CONTROL_REGRegClassID, // CR12
8530 X86::CONTROL_REGRegClassID, // CR13
8531 X86::CONTROL_REGRegClassID, // CR14
8532 X86::CONTROL_REGRegClassID, // CR15
8533 X86::DEBUG_REGRegClassID, // DR0
8534 X86::DEBUG_REGRegClassID, // DR1
8535 X86::DEBUG_REGRegClassID, // DR2
8536 X86::DEBUG_REGRegClassID, // DR3
8537 X86::DEBUG_REGRegClassID, // DR4
8538 X86::DEBUG_REGRegClassID, // DR5
8539 X86::DEBUG_REGRegClassID, // DR6
8540 X86::DEBUG_REGRegClassID, // DR7
8541 X86::DEBUG_REGRegClassID, // DR8
8542 X86::DEBUG_REGRegClassID, // DR9
8543 X86::DEBUG_REGRegClassID, // DR10
8544 X86::DEBUG_REGRegClassID, // DR11
8545 X86::DEBUG_REGRegClassID, // DR12
8546 X86::DEBUG_REGRegClassID, // DR13
8547 X86::DEBUG_REGRegClassID, // DR14
8548 X86::DEBUG_REGRegClassID, // DR15
8549 X86::RFP80RegClassID, // FP0
8550 X86::RFP80RegClassID, // FP1
8551 X86::RFP80RegClassID, // FP2
8552 X86::RFP80RegClassID, // FP3
8553 X86::RFP80RegClassID, // FP4
8554 X86::RFP80RegClassID, // FP5
8555 X86::RFP80RegClassID, // FP6
8556 X86::RFP80_7RegClassID, // FP7
8557 X86::VR64RegClassID, // MM0
8558 X86::VR64RegClassID, // MM1
8559 X86::VR64RegClassID, // MM2
8560 X86::VR64RegClassID, // MM3
8561 X86::VR64RegClassID, // MM4
8562 X86::VR64RegClassID, // MM5
8563 X86::VR64RegClassID, // MM6
8564 X86::VR64RegClassID, // MM7
8565 X86::GR64PLTSafe_and_GR64_TCW64RegClassID, // R8
8566 X86::GR64PLTSafe_and_GR64_TCW64RegClassID, // R9
8567 X86::GR64_ArgRefRegClassID, // R10
8568 X86::GR64_ArgRef_and_GR64_TCRegClassID, // R11
8569 X86::GR64PLTSafeRegClassID, // R12
8570 X86::GR64PLTSafeRegClassID, // R13
8571 X86::GR64PLTSafeRegClassID, // R14
8572 X86::GR64PLTSafeRegClassID, // R15
8573 X86::RSTRegClassID, // ST0
8574 X86::RSTRegClassID, // ST1
8575 X86::RSTRegClassID, // ST2
8576 X86::RSTRegClassID, // ST3
8577 X86::RSTRegClassID, // ST4
8578 X86::RSTRegClassID, // ST5
8579 X86::RSTRegClassID, // ST6
8580 X86::RSTRegClassID, // ST7
8581 X86::VR128RegClassID, // XMM0
8582 X86::VR128RegClassID, // XMM1
8583 X86::VR128RegClassID, // XMM2
8584 X86::VR128RegClassID, // XMM3
8585 X86::VR128RegClassID, // XMM4
8586 X86::VR128RegClassID, // XMM5
8587 X86::VR128RegClassID, // XMM6
8588 X86::VR128RegClassID, // XMM7
8589 X86::VR128RegClassID, // XMM8
8590 X86::VR128RegClassID, // XMM9
8591 X86::VR128RegClassID, // XMM10
8592 X86::VR128RegClassID, // XMM11
8593 X86::VR128RegClassID, // XMM12
8594 X86::VR128RegClassID, // XMM13
8595 X86::VR128RegClassID, // XMM14
8596 X86::VR128RegClassID, // XMM15
8597 X86::GR8_NOREX2RegClassID, // R8B
8598 X86::GR8_NOREX2RegClassID, // R9B
8599 X86::GR8_NOREX2RegClassID, // R10B
8600 X86::GR8_NOREX2RegClassID, // R11B
8601 X86::GR8_NOREX2RegClassID, // R12B
8602 X86::GR8_NOREX2RegClassID, // R13B
8603 X86::GR8_NOREX2RegClassID, // R14B
8604 X86::GR8_NOREX2RegClassID, // R15B
8605 X86::GRH8RegClassID, // R8BH
8606 X86::GRH8RegClassID, // R9BH
8607 X86::GRH8RegClassID, // R10BH
8608 X86::GRH8RegClassID, // R11BH
8609 X86::GRH8RegClassID, // R12BH
8610 X86::GRH8RegClassID, // R13BH
8611 X86::GRH8RegClassID, // R14BH
8612 X86::GRH8RegClassID, // R15BH
8613 X86::GR32_NOREX2_NOSPRegClassID, // R8D
8614 X86::GR32_NOREX2_NOSPRegClassID, // R9D
8615 X86::GR32_NOREX2_NOSPRegClassID, // R10D
8616 X86::GR32_NOREX2_NOSPRegClassID, // R11D
8617 X86::GR32_NOREX2_NOSPRegClassID, // R12D
8618 X86::GR32_NOREX2_NOSPRegClassID, // R13D
8619 X86::GR32_NOREX2_NOSPRegClassID, // R14D
8620 X86::GR32_NOREX2_NOSPRegClassID, // R15D
8621 X86::GR16_NOREX2RegClassID, // R8W
8622 X86::GR16_NOREX2RegClassID, // R9W
8623 X86::GR16_NOREX2RegClassID, // R10W
8624 X86::GR16_NOREX2RegClassID, // R11W
8625 X86::GR16_NOREX2RegClassID, // R12W
8626 X86::GR16_NOREX2RegClassID, // R13W
8627 X86::GR16_NOREX2RegClassID, // R14W
8628 X86::GR16_NOREX2RegClassID, // R15W
8629 X86::GRH16RegClassID, // R8WH
8630 X86::GRH16RegClassID, // R9WH
8631 X86::GRH16RegClassID, // R10WH
8632 X86::GRH16RegClassID, // R11WH
8633 X86::GRH16RegClassID, // R12WH
8634 X86::GRH16RegClassID, // R13WH
8635 X86::GRH16RegClassID, // R14WH
8636 X86::GRH16RegClassID, // R15WH
8637 X86::VR256RegClassID, // YMM0
8638 X86::VR256RegClassID, // YMM1
8639 X86::VR256RegClassID, // YMM2
8640 X86::VR256RegClassID, // YMM3
8641 X86::VR256RegClassID, // YMM4
8642 X86::VR256RegClassID, // YMM5
8643 X86::VR256RegClassID, // YMM6
8644 X86::VR256RegClassID, // YMM7
8645 X86::VR256RegClassID, // YMM8
8646 X86::VR256RegClassID, // YMM9
8647 X86::VR256RegClassID, // YMM10
8648 X86::VR256RegClassID, // YMM11
8649 X86::VR256RegClassID, // YMM12
8650 X86::VR256RegClassID, // YMM13
8651 X86::VR256RegClassID, // YMM14
8652 X86::VR256RegClassID, // YMM15
8653 X86::VK64RegClassID, // K0
8654 X86::VK64WMRegClassID, // K1
8655 X86::VK64WMRegClassID, // K2
8656 X86::VK64WMRegClassID, // K3
8657 X86::VK64WMRegClassID, // K4
8658 X86::VK64WMRegClassID, // K5
8659 X86::VK64WMRegClassID, // K6
8660 X86::VK64WMRegClassID, // K7
8661 X86::VR128XRegClassID, // XMM16
8662 X86::VR128XRegClassID, // XMM17
8663 X86::VR128XRegClassID, // XMM18
8664 X86::VR128XRegClassID, // XMM19
8665 X86::VR128XRegClassID, // XMM20
8666 X86::VR128XRegClassID, // XMM21
8667 X86::VR128XRegClassID, // XMM22
8668 X86::VR128XRegClassID, // XMM23
8669 X86::VR128XRegClassID, // XMM24
8670 X86::VR128XRegClassID, // XMM25
8671 X86::VR128XRegClassID, // XMM26
8672 X86::VR128XRegClassID, // XMM27
8673 X86::VR128XRegClassID, // XMM28
8674 X86::VR128XRegClassID, // XMM29
8675 X86::VR128XRegClassID, // XMM30
8676 X86::VR128XRegClassID, // XMM31
8677 X86::VR256XRegClassID, // YMM16
8678 X86::VR256XRegClassID, // YMM17
8679 X86::VR256XRegClassID, // YMM18
8680 X86::VR256XRegClassID, // YMM19
8681 X86::VR256XRegClassID, // YMM20
8682 X86::VR256XRegClassID, // YMM21
8683 X86::VR256XRegClassID, // YMM22
8684 X86::VR256XRegClassID, // YMM23
8685 X86::VR256XRegClassID, // YMM24
8686 X86::VR256XRegClassID, // YMM25
8687 X86::VR256XRegClassID, // YMM26
8688 X86::VR256XRegClassID, // YMM27
8689 X86::VR256XRegClassID, // YMM28
8690 X86::VR256XRegClassID, // YMM29
8691 X86::VR256XRegClassID, // YMM30
8692 X86::VR256XRegClassID, // YMM31
8693 X86::VR512_0_15RegClassID, // ZMM0
8694 X86::VR512_0_15RegClassID, // ZMM1
8695 X86::VR512_0_15RegClassID, // ZMM2
8696 X86::VR512_0_15RegClassID, // ZMM3
8697 X86::VR512_0_15RegClassID, // ZMM4
8698 X86::VR512_0_15RegClassID, // ZMM5
8699 X86::VR512_0_15RegClassID, // ZMM6
8700 X86::VR512_0_15RegClassID, // ZMM7
8701 X86::VR512_0_15RegClassID, // ZMM8
8702 X86::VR512_0_15RegClassID, // ZMM9
8703 X86::VR512_0_15RegClassID, // ZMM10
8704 X86::VR512_0_15RegClassID, // ZMM11
8705 X86::VR512_0_15RegClassID, // ZMM12
8706 X86::VR512_0_15RegClassID, // ZMM13
8707 X86::VR512_0_15RegClassID, // ZMM14
8708 X86::VR512_0_15RegClassID, // ZMM15
8709 X86::VR512RegClassID, // ZMM16
8710 X86::VR512RegClassID, // ZMM17
8711 X86::VR512RegClassID, // ZMM18
8712 X86::VR512RegClassID, // ZMM19
8713 X86::VR512RegClassID, // ZMM20
8714 X86::VR512RegClassID, // ZMM21
8715 X86::VR512RegClassID, // ZMM22
8716 X86::VR512RegClassID, // ZMM23
8717 X86::VR512RegClassID, // ZMM24
8718 X86::VR512RegClassID, // ZMM25
8719 X86::VR512RegClassID, // ZMM26
8720 X86::VR512RegClassID, // ZMM27
8721 X86::VR512RegClassID, // ZMM28
8722 X86::VR512RegClassID, // ZMM29
8723 X86::VR512RegClassID, // ZMM30
8724 X86::VR512RegClassID, // ZMM31
8725 X86::VK8PAIRRegClassID, // K0_K1
8726 X86::VK1PAIR_with_sub_mask_0_in_VK1WMRegClassID, // K2_K3
8727 X86::VK1PAIR_with_sub_mask_0_in_VK1WMRegClassID, // K4_K5
8728 X86::VK1PAIR_with_sub_mask_0_in_VK1WMRegClassID, // K6_K7
8729 InvalidRegClassID, // TMMCFG
8730 X86::TILERegClassID, // TMM0
8731 X86::TILERegClassID, // TMM1
8732 X86::TILERegClassID, // TMM2
8733 X86::TILERegClassID, // TMM3
8734 X86::TILERegClassID, // TMM4
8735 X86::TILERegClassID, // TMM5
8736 X86::TILERegClassID, // TMM6
8737 X86::TILERegClassID, // TMM7
8738 X86::GR64_NOSPRegClassID, // R16
8739 X86::GR64_NOSPRegClassID, // R17
8740 X86::GR64_NOSPRegClassID, // R18
8741 X86::GR64_NOSPRegClassID, // R19
8742 X86::GR64_NOSPRegClassID, // R20
8743 X86::GR64_NOSPRegClassID, // R21
8744 X86::GR64_NOSPRegClassID, // R22
8745 X86::GR64_NOSPRegClassID, // R23
8746 X86::GR64_NOSPRegClassID, // R24
8747 X86::GR64_NOSPRegClassID, // R25
8748 X86::GR64_NOSPRegClassID, // R26
8749 X86::GR64_NOSPRegClassID, // R27
8750 X86::GR64_NOSPRegClassID, // R28
8751 X86::GR64_NOSPRegClassID, // R29
8752 X86::GR64_NOSPRegClassID, // R30
8753 X86::GR64_NOSPRegClassID, // R31
8754 X86::GR8RegClassID, // R16B
8755 X86::GR8RegClassID, // R17B
8756 X86::GR8RegClassID, // R18B
8757 X86::GR8RegClassID, // R19B
8758 X86::GR8RegClassID, // R20B
8759 X86::GR8RegClassID, // R21B
8760 X86::GR8RegClassID, // R22B
8761 X86::GR8RegClassID, // R23B
8762 X86::GR8RegClassID, // R24B
8763 X86::GR8RegClassID, // R25B
8764 X86::GR8RegClassID, // R26B
8765 X86::GR8RegClassID, // R27B
8766 X86::GR8RegClassID, // R28B
8767 X86::GR8RegClassID, // R29B
8768 X86::GR8RegClassID, // R30B
8769 X86::GR8RegClassID, // R31B
8770 X86::GRH8RegClassID, // R16BH
8771 X86::GRH8RegClassID, // R17BH
8772 X86::GRH8RegClassID, // R18BH
8773 X86::GRH8RegClassID, // R19BH
8774 X86::GRH8RegClassID, // R20BH
8775 X86::GRH8RegClassID, // R21BH
8776 X86::GRH8RegClassID, // R22BH
8777 X86::GRH8RegClassID, // R23BH
8778 X86::GRH8RegClassID, // R24BH
8779 X86::GRH8RegClassID, // R25BH
8780 X86::GRH8RegClassID, // R26BH
8781 X86::GRH8RegClassID, // R27BH
8782 X86::GRH8RegClassID, // R28BH
8783 X86::GRH8RegClassID, // R29BH
8784 X86::GRH8RegClassID, // R30BH
8785 X86::GRH8RegClassID, // R31BH
8786 X86::GR32_NOSPRegClassID, // R16D
8787 X86::GR32_NOSPRegClassID, // R17D
8788 X86::GR32_NOSPRegClassID, // R18D
8789 X86::GR32_NOSPRegClassID, // R19D
8790 X86::GR32_NOSPRegClassID, // R20D
8791 X86::GR32_NOSPRegClassID, // R21D
8792 X86::GR32_NOSPRegClassID, // R22D
8793 X86::GR32_NOSPRegClassID, // R23D
8794 X86::GR32_NOSPRegClassID, // R24D
8795 X86::GR32_NOSPRegClassID, // R25D
8796 X86::GR32_NOSPRegClassID, // R26D
8797 X86::GR32_NOSPRegClassID, // R27D
8798 X86::GR32_NOSPRegClassID, // R28D
8799 X86::GR32_NOSPRegClassID, // R29D
8800 X86::GR32_NOSPRegClassID, // R30D
8801 X86::GR32_NOSPRegClassID, // R31D
8802 X86::GR16RegClassID, // R16W
8803 X86::GR16RegClassID, // R17W
8804 X86::GR16RegClassID, // R18W
8805 X86::GR16RegClassID, // R19W
8806 X86::GR16RegClassID, // R20W
8807 X86::GR16RegClassID, // R21W
8808 X86::GR16RegClassID, // R22W
8809 X86::GR16RegClassID, // R23W
8810 X86::GR16RegClassID, // R24W
8811 X86::GR16RegClassID, // R25W
8812 X86::GR16RegClassID, // R26W
8813 X86::GR16RegClassID, // R27W
8814 X86::GR16RegClassID, // R28W
8815 X86::GR16RegClassID, // R29W
8816 X86::GR16RegClassID, // R30W
8817 X86::GR16RegClassID, // R31W
8818 X86::GRH16RegClassID, // R16WH
8819 X86::GRH16RegClassID, // R17WH
8820 X86::GRH16RegClassID, // R18WH
8821 X86::GRH16RegClassID, // R19WH
8822 X86::GRH16RegClassID, // R20WH
8823 X86::GRH16RegClassID, // R21WH
8824 X86::GRH16RegClassID, // R22WH
8825 X86::GRH16RegClassID, // R23WH
8826 X86::GRH16RegClassID, // R24WH
8827 X86::GRH16RegClassID, // R25WH
8828 X86::GRH16RegClassID, // R26WH
8829 X86::GRH16RegClassID, // R27WH
8830 X86::GRH16RegClassID, // R28WH
8831 X86::GRH16RegClassID, // R29WH
8832 X86::GRH16RegClassID, // R30WH
8833 X86::GRH16RegClassID, // R31WH
8834 };
8835
8836 assert(Reg < ArrayRef(Mapping).size());
8837 unsigned RCID = Mapping[Reg.id()];
8838 if (RCID == InvalidRegClassID)
8839 return nullptr;
8840 return X86RegisterClasses[RCID];
8841}
8842extern const MCRegisterDesc X86RegDesc[];
8843extern const int16_t X86RegDiffLists[];
8844extern const LaneBitmask X86LaneMaskLists[];
8845extern const char X86RegStrings[];
8846extern const char X86RegClassStrings[];
8847extern const MCPhysReg X86RegUnitRoots[][2];
8848extern const uint16_t X86SubRegIdxLists[];
8849extern const uint16_t X86RegEncodingTable[];
8850// X86 Dwarf<->LLVM register mappings.
8851extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[];
8852extern const unsigned X86DwarfFlavour0Dwarf2LSize;
8853
8854extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[];
8855extern const unsigned X86DwarfFlavour1Dwarf2LSize;
8856
8857extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[];
8858extern const unsigned X86DwarfFlavour2Dwarf2LSize;
8859
8860extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[];
8861extern const unsigned X86EHFlavour0Dwarf2LSize;
8862
8863extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[];
8864extern const unsigned X86EHFlavour1Dwarf2LSize;
8865
8866extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[];
8867extern const unsigned X86EHFlavour2Dwarf2LSize;
8868
8869extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[];
8870extern const unsigned X86DwarfFlavour0L2DwarfSize;
8871
8872extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[];
8873extern const unsigned X86DwarfFlavour1L2DwarfSize;
8874
8875extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[];
8876extern const unsigned X86DwarfFlavour2L2DwarfSize;
8877
8878extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[];
8879extern const unsigned X86EHFlavour0L2DwarfSize;
8880
8881extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[];
8882extern const unsigned X86EHFlavour1L2DwarfSize;
8883
8884extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[];
8885extern const unsigned X86EHFlavour2L2DwarfSize;
8886
8887
8888X86GenRegisterInfo::
8889X86GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
8890 unsigned PC, unsigned HwMode)
8891 : TargetRegisterInfo(&X86RegInfoDesc, X86RegisterClasses,
8892 X86SubRegIndexStrings, X86SubRegIndexNameOffsets,
8893 X86SubRegIdxRangeTable, X86SubRegIndexLaneMaskTable,
8894
8895 LaneBitmask(0xFFFFFFFFFFFFFFB0), X86RegClassInfos, X86VTLists, HwMode) {
8896 InitMCRegisterInfo(D: X86RegDesc, NR: 388, RA, PC,
8897 C: X86MCRegisterClasses, NC: 135, RURoots: X86RegUnitRoots, NRU: 221, DL: X86RegDiffLists,
8898 RUMS: X86LaneMaskLists, Strings: X86RegStrings, ClassStrings: X86RegClassStrings, SubIndices: X86SubRegIdxLists, NumIndices: 11,
8899 RET: X86RegEncodingTable, RUI: nullptr);
8900
8901 switch (DwarfFlavour) {
8902 default:
8903 llvm_unreachable("Unknown DWARF flavour");
8904 case 0:
8905 mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour0Dwarf2L, Size: X86DwarfFlavour0Dwarf2LSize, isEH: false);
8906 break;
8907 case 1:
8908 mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour1Dwarf2L, Size: X86DwarfFlavour1Dwarf2LSize, isEH: false);
8909 break;
8910 case 2:
8911 mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour2Dwarf2L, Size: X86DwarfFlavour2Dwarf2LSize, isEH: false);
8912 break;
8913 }
8914 switch (EHFlavour) {
8915 default:
8916 llvm_unreachable("Unknown DWARF flavour");
8917 case 0:
8918 mapDwarfRegsToLLVMRegs(Map: X86EHFlavour0Dwarf2L, Size: X86EHFlavour0Dwarf2LSize, isEH: true);
8919 break;
8920 case 1:
8921 mapDwarfRegsToLLVMRegs(Map: X86EHFlavour1Dwarf2L, Size: X86EHFlavour1Dwarf2LSize, isEH: true);
8922 break;
8923 case 2:
8924 mapDwarfRegsToLLVMRegs(Map: X86EHFlavour2Dwarf2L, Size: X86EHFlavour2Dwarf2LSize, isEH: true);
8925 break;
8926 }
8927 switch (DwarfFlavour) {
8928 default:
8929 llvm_unreachable("Unknown DWARF flavour");
8930 case 0:
8931 mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour0L2Dwarf, Size: X86DwarfFlavour0L2DwarfSize, isEH: false);
8932 break;
8933 case 1:
8934 mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour1L2Dwarf, Size: X86DwarfFlavour1L2DwarfSize, isEH: false);
8935 break;
8936 case 2:
8937 mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour2L2Dwarf, Size: X86DwarfFlavour2L2DwarfSize, isEH: false);
8938 break;
8939 }
8940 switch (EHFlavour) {
8941 default:
8942 llvm_unreachable("Unknown DWARF flavour");
8943 case 0:
8944 mapLLVMRegsToDwarfRegs(Map: X86EHFlavour0L2Dwarf, Size: X86EHFlavour0L2DwarfSize, isEH: true);
8945 break;
8946 case 1:
8947 mapLLVMRegsToDwarfRegs(Map: X86EHFlavour1L2Dwarf, Size: X86EHFlavour1L2DwarfSize, isEH: true);
8948 break;
8949 case 2:
8950 mapLLVMRegsToDwarfRegs(Map: X86EHFlavour2L2Dwarf, Size: X86EHFlavour2L2DwarfSize, isEH: true);
8951 break;
8952 }
8953}
8954
8955static const MCPhysReg CSR_32_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
8956static const uint32_t CSR_32_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8957static const MCPhysReg CSR_32EHRet_SaveList[] = { X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
8958static const uint32_t CSR_32EHRet_RegMask[] = { 0x0def83fe, 0xc000b701, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8959static const MCPhysReg CSR_32_AllRegs_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, 0 };
8960static const uint32_t CSR_32_AllRegs_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8961static const MCPhysReg CSR_32_AllRegs_AVX_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, 0 };
8962static const uint32_t CSR_32_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00007f80, 0x80000000, 0x0000007f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8963static const MCPhysReg CSR_32_AllRegs_AVX512_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
8964static const uint32_t CSR_32_AllRegs_AVX512_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00007f80, 0x80000000, 0x007f807f, 0x7f800000, 0x07800000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8965static const MCPhysReg CSR_32_AllRegs_SSE_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
8966static const uint32_t CSR_32_AllRegs_SSE_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00007f80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8967static const MCPhysReg CSR_32_RegCall_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
8968static const uint32_t CSR_32_RegCall_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00007800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8969static const MCPhysReg CSR_32_RegCall_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
8970static const uint32_t CSR_32_RegCall_NoSSE_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8971static const MCPhysReg CSR_64_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
8972static const uint32_t CSR_64_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8973static const MCPhysReg CSR_64EHRet_SaveList[] = { X86::RAX, X86::RDX, X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
8974static const uint32_t CSR_64EHRet_RegMask[] = { 0x09e883fe, 0x01382700, 0x00000000, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8975static const MCPhysReg CSR_64_AllRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::RAX, 0 };
8976static const uint32_t CSR_64_AllRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xffffff80, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8977static const MCPhysReg CSR_64_AllRegs_AVX_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
8978static const uint32_t CSR_64_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xffffff80, 0xffffffff, 0x00007fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8979static const MCPhysReg CSR_64_AllRegs_AVX512_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
8980static const uint32_t CSR_64_AllRegs_AVX512_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xffffff80, 0xffffffff, 0xffffffff, 0xffffffff, 0x07ffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8981static const MCPhysReg CSR_64_AllRegs_NoSSE_SaveList[] = { X86::RAX, X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
8982static const uint32_t CSR_64_AllRegs_NoSSE_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xff800000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8983static const MCPhysReg CSR_64_CXX_TLS_Darwin_PE_SaveList[] = { X86::RBP, 0 };
8984static const uint32_t CSR_64_CXX_TLS_Darwin_PE_RegMask[] = { 0x008001c0, 0x00100200, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8985static const MCPhysReg CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 };
8986static const uint32_t CSR_64_CXX_TLS_Darwin_ViaCopy_RegMask[] = { 0x0b28ae30, 0xd160ac01, 0x00000001, 0x7f800000, 0xff800000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8987static const MCPhysReg CSR_64_Intel_OCL_BI_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
8988static const uint32_t CSR_64_Intel_OCL_BI_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x787f8000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8989static const MCPhysReg CSR_64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
8990static const uint32_t CSR_64_Intel_OCL_BI_AVX_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x787f8000, 0x78787878, 0x00007f80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8991static const MCPhysReg CSR_64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RSI, X86::R14, X86::R15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
8992static const uint32_t CSR_64_Intel_OCL_BI_AVX512_RegMask[] = { 0x01000230, 0xd0208401, 0x00000001, 0x60000000, 0x60000000, 0x60606060, 0xfff80000, 0x007fffff, 0x067fff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8993static const MCPhysReg CSR_64_MostRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
8994static const uint32_t CSR_64_MostRegs_RegMask[] = { 0x0fafaff0, 0xd1f0be01, 0x00000001, 0x7f800000, 0xffffff80, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8995static const MCPhysReg CSR_64_NoneRegs_SaveList[] = { X86::RBP, 0 };
8996static const uint32_t CSR_64_NoneRegs_RegMask[] = { 0x008001c0, 0x00100200, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8997static const MCPhysReg CSR_64_RT_AllRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
8998static const uint32_t CSR_64_RT_AllRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffff80, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8999static const MCPhysReg CSR_64_RT_AllRegs_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
9000static const uint32_t CSR_64_RT_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffff80, 0xfbfbfbfb, 0x00007fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9001static const MCPhysReg CSR_64_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, 0 };
9002static const uint32_t CSR_64_RT_MostRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfb800000, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9003static const MCPhysReg CSR_64_SwiftError_SaveList[] = { X86::RBX, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
9004static const uint32_t CSR_64_SwiftError_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x70000000, 0x70000000, 0x70707070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9005static const MCPhysReg CSR_64_SwiftTail_SaveList[] = { X86::RBX, X86::R12, X86::R15, X86::RBP, 0 };
9006static const uint32_t CSR_64_SwiftTail_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x48000000, 0x48000000, 0x48484848, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9007static const MCPhysReg CSR_64_TLS_Darwin_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 };
9008static const uint32_t CSR_64_TLS_Darwin_RegMask[] = { 0x0ba8aff0, 0xd170ae01, 0x00000001, 0x7f800000, 0xff800000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9009static const MCPhysReg CSR_IPRA_32_SaveList[] = { X86::EBP, X86::ESI, 0 };
9010static const uint32_t CSR_IPRA_32_RegMask[] = { 0x008001c0, 0xc0008201, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9011static const MCPhysReg CSR_IPRA_64_SaveList[] = { X86::RBP, X86::RBX, 0 };
9012static const uint32_t CSR_IPRA_64_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9013static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
9014static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9015static const MCPhysReg CSR_SysV64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
9016static const uint32_t CSR_SysV64_RegCall_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x787f8000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9017static const MCPhysReg CSR_SysV64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
9018static const uint32_t CSR_SysV64_RegCall_NoSSE_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9019static const MCPhysReg CSR_Win32_CFGuard_Check_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::ECX, 0 };
9020static const uint32_t CSR_Win32_CFGuard_Check_RegMask[] = { 0x07872ff0, 0xc0009e01, 0x00000001, 0x00000000, 0x00007800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9021static const MCPhysReg CSR_Win32_CFGuard_Check_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ECX, 0 };
9022static const uint32_t CSR_Win32_CFGuard_Check_NoSSE_RegMask[] = { 0x07872ff0, 0xc0009e01, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9023static const MCPhysReg CSR_Win64_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
9024static const uint32_t CSR_Win64_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9025static const MCPhysReg CSR_Win64_APX_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::R30, X86::R31, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
9026static const uint32_t CSR_Win64_APX_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x000c0000, 0x000c000c, 0x000c000c, 0x0000000c, };
9027static const MCPhysReg CSR_Win64_APX_CFGuard_Check_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::R16, X86::R17, X86::R18, X86::R19, X86::R20, X86::R21, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::R28, X86::R29, X86::R30, X86::R31, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::RCX, 0 };
9028static const uint32_t CSR_Win64_APX_CFGuard_Check_RegMask[] = { 0x03802ff0, 0x00700e00, 0x00000000, 0x7e000000, 0x7e7f8000, 0x7e7e7e7e, 0x00000000, 0x00000000, 0x00000000, 0xfffffff0, 0xffffffff, 0xffffffff, 0x0000000f, };
9029static const MCPhysReg CSR_Win64_APX_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::R30, X86::R31, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
9030static const uint32_t CSR_Win64_APX_Intel_OCL_BI_AVX_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x00007fe0, 0x00000000, 0x00000000, 0x000c0000, 0x000c000c, 0x000c000c, 0x0000000c, };
9031static const MCPhysReg CSR_Win64_APX_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::R30, X86::R31, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
9032static const uint32_t CSR_Win64_APX_Intel_OCL_BI_AVX512_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x1ff87fe0, 0xe0001f80, 0x06001fff, 0x000c0000, 0x000c000c, 0x000c000c, 0x0000000c, };
9033static const MCPhysReg CSR_Win64_APX_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R30, X86::R31, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
9034static const uint32_t CSR_Win64_APX_RT_MostRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffe000, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x000c0000, 0x000c000c, 0x000c000c, 0x0000000c, };
9035static const MCPhysReg CSR_Win64_APX_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::R30, X86::R31, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
9036static const uint32_t CSR_Win64_APX_RegCall_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x7e000000, 0x7e7f8000, 0x7e7e7e7e, 0x00000000, 0x00000000, 0x00000000, 0x000c0000, 0x000c000c, 0x000c000c, 0x0000000c, };
9037static const MCPhysReg CSR_Win64_APX_SwiftError_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R13, X86::R14, X86::R15, X86::R30, X86::R31, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
9038static const uint32_t CSR_Win64_APX_SwiftError_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x70000000, 0x707fe000, 0x70707070, 0x00000000, 0x00000000, 0x00000000, 0x000c0000, 0x000c000c, 0x000c000c, 0x0000000c, };
9039static const MCPhysReg CSR_Win64_APX_SwiftTail_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R15, X86::R30, X86::R31, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
9040static const uint32_t CSR_Win64_APX_SwiftTail_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x48000000, 0x487fe000, 0x48484848, 0x00000000, 0x00000000, 0x00000000, 0x000c0000, 0x000c000c, 0x000c000c, 0x0000000c, };
9041static const MCPhysReg CSR_Win64_CFGuard_Check_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::RCX, 0 };
9042static const uint32_t CSR_Win64_CFGuard_Check_RegMask[] = { 0x03802ff0, 0x00700e00, 0x00000000, 0x7e000000, 0x7e7f8000, 0x7e7e7e7e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9043static const MCPhysReg CSR_Win64_CFGuard_Check_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RCX, 0 };
9044static const uint32_t CSR_Win64_CFGuard_Check_NoSSE_RegMask[] = { 0x03802ff0, 0x00700e00, 0x00000000, 0x7e000000, 0x7e000000, 0x7e7e7e7e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9045static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
9046static const uint32_t CSR_Win64_Intel_OCL_BI_AVX_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x00007fe0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9047static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
9048static const uint32_t CSR_Win64_Intel_OCL_BI_AVX512_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x1ff87fe0, 0xe0001f80, 0x06001fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9049static const MCPhysReg CSR_Win64_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
9050static const uint32_t CSR_Win64_NoSSE_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9051static const MCPhysReg CSR_Win64_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
9052static const uint32_t CSR_Win64_RT_MostRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffe000, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9053static const MCPhysReg CSR_Win64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
9054static const uint32_t CSR_Win64_RegCall_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x7e000000, 0x7e7f8000, 0x7e7e7e7e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9055static const MCPhysReg CSR_Win64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
9056static const uint32_t CSR_Win64_RegCall_NoSSE_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x7e000000, 0x7e000000, 0x7e7e7e7e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9057static const MCPhysReg CSR_Win64_SwiftError_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
9058static const uint32_t CSR_Win64_SwiftError_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x70000000, 0x707fe000, 0x70707070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9059static const MCPhysReg CSR_Win64_SwiftTail_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
9060static const uint32_t CSR_Win64_SwiftTail_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x48000000, 0x487fe000, 0x48484848, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
9061
9062
9063ArrayRef<const uint32_t *> X86GenRegisterInfo::getRegMasks() const {
9064 static const uint32_t *const Masks[] = {
9065 CSR_32_RegMask,
9066 CSR_32EHRet_RegMask,
9067 CSR_32_AllRegs_RegMask,
9068 CSR_32_AllRegs_AVX_RegMask,
9069 CSR_32_AllRegs_AVX512_RegMask,
9070 CSR_32_AllRegs_SSE_RegMask,
9071 CSR_32_RegCall_RegMask,
9072 CSR_32_RegCall_NoSSE_RegMask,
9073 CSR_64_RegMask,
9074 CSR_64EHRet_RegMask,
9075 CSR_64_AllRegs_RegMask,
9076 CSR_64_AllRegs_AVX_RegMask,
9077 CSR_64_AllRegs_AVX512_RegMask,
9078 CSR_64_AllRegs_NoSSE_RegMask,
9079 CSR_64_CXX_TLS_Darwin_PE_RegMask,
9080 CSR_64_CXX_TLS_Darwin_ViaCopy_RegMask,
9081 CSR_64_Intel_OCL_BI_RegMask,
9082 CSR_64_Intel_OCL_BI_AVX_RegMask,
9083 CSR_64_Intel_OCL_BI_AVX512_RegMask,
9084 CSR_64_MostRegs_RegMask,
9085 CSR_64_NoneRegs_RegMask,
9086 CSR_64_RT_AllRegs_RegMask,
9087 CSR_64_RT_AllRegs_AVX_RegMask,
9088 CSR_64_RT_MostRegs_RegMask,
9089 CSR_64_SwiftError_RegMask,
9090 CSR_64_SwiftTail_RegMask,
9091 CSR_64_TLS_Darwin_RegMask,
9092 CSR_IPRA_32_RegMask,
9093 CSR_IPRA_64_RegMask,
9094 CSR_NoRegs_RegMask,
9095 CSR_SysV64_RegCall_RegMask,
9096 CSR_SysV64_RegCall_NoSSE_RegMask,
9097 CSR_Win32_CFGuard_Check_RegMask,
9098 CSR_Win32_CFGuard_Check_NoSSE_RegMask,
9099 CSR_Win64_RegMask,
9100 CSR_Win64_APX_RegMask,
9101 CSR_Win64_APX_CFGuard_Check_RegMask,
9102 CSR_Win64_APX_Intel_OCL_BI_AVX_RegMask,
9103 CSR_Win64_APX_Intel_OCL_BI_AVX512_RegMask,
9104 CSR_Win64_APX_RT_MostRegs_RegMask,
9105 CSR_Win64_APX_RegCall_RegMask,
9106 CSR_Win64_APX_SwiftError_RegMask,
9107 CSR_Win64_APX_SwiftTail_RegMask,
9108 CSR_Win64_CFGuard_Check_RegMask,
9109 CSR_Win64_CFGuard_Check_NoSSE_RegMask,
9110 CSR_Win64_Intel_OCL_BI_AVX_RegMask,
9111 CSR_Win64_Intel_OCL_BI_AVX512_RegMask,
9112 CSR_Win64_NoSSE_RegMask,
9113 CSR_Win64_RT_MostRegs_RegMask,
9114 CSR_Win64_RegCall_RegMask,
9115 CSR_Win64_RegCall_NoSSE_RegMask,
9116 CSR_Win64_SwiftError_RegMask,
9117 CSR_Win64_SwiftTail_RegMask,
9118 };
9119 return ArrayRef(Masks);
9120}
9121
9122bool X86GenRegisterInfo::
9123isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
9124 return
9125 X86::GR64RegClass.contains(Reg: PhysReg) ||
9126 X86::GR32RegClass.contains(Reg: PhysReg) ||
9127 X86::GR16RegClass.contains(Reg: PhysReg) ||
9128 X86::GR8RegClass.contains(Reg: PhysReg) ||
9129 false;
9130}
9131
9132bool X86GenRegisterInfo::
9133isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
9134 return
9135 X86::GR64RegClass.hasSubClassEq(RC) ||
9136 X86::GR32RegClass.hasSubClassEq(RC) ||
9137 X86::GR16RegClass.hasSubClassEq(RC) ||
9138 X86::GR8RegClass.hasSubClassEq(RC) ||
9139 false;
9140}
9141
9142bool X86GenRegisterInfo::
9143isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
9144 return
9145 X86::DEBUG_REGRegClass.contains(Reg: PhysReg) ||
9146 X86::CONTROL_REGRegClass.contains(Reg: PhysReg) ||
9147 X86::CCRRegClass.contains(Reg: PhysReg) ||
9148 X86::FPCCRRegClass.contains(Reg: PhysReg) ||
9149 X86::DFCCRRegClass.contains(Reg: PhysReg) ||
9150 X86::TILERegClass.contains(Reg: PhysReg) ||
9151 X86::VK1PAIRRegClass.contains(Reg: PhysReg) ||
9152 X86::VK2PAIRRegClass.contains(Reg: PhysReg) ||
9153 X86::VK4PAIRRegClass.contains(Reg: PhysReg) ||
9154 X86::VK8PAIRRegClass.contains(Reg: PhysReg) ||
9155 X86::VK16PAIRRegClass.contains(Reg: PhysReg) ||
9156 false;
9157}
9158
9159bool X86GenRegisterInfo::
9160isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
9161 return
9162 false;
9163}
9164
9165bool X86GenRegisterInfo::
9166isConstantPhysReg(MCRegister PhysReg) const {
9167 return
9168 false;
9169}
9170
9171ArrayRef<const char *> X86GenRegisterInfo::getRegMaskNames() const {
9172 static const char *Names[] = {
9173 "CSR_32",
9174 "CSR_32EHRet",
9175 "CSR_32_AllRegs",
9176 "CSR_32_AllRegs_AVX",
9177 "CSR_32_AllRegs_AVX512",
9178 "CSR_32_AllRegs_SSE",
9179 "CSR_32_RegCall",
9180 "CSR_32_RegCall_NoSSE",
9181 "CSR_64",
9182 "CSR_64EHRet",
9183 "CSR_64_AllRegs",
9184 "CSR_64_AllRegs_AVX",
9185 "CSR_64_AllRegs_AVX512",
9186 "CSR_64_AllRegs_NoSSE",
9187 "CSR_64_CXX_TLS_Darwin_PE",
9188 "CSR_64_CXX_TLS_Darwin_ViaCopy",
9189 "CSR_64_Intel_OCL_BI",
9190 "CSR_64_Intel_OCL_BI_AVX",
9191 "CSR_64_Intel_OCL_BI_AVX512",
9192 "CSR_64_MostRegs",
9193 "CSR_64_NoneRegs",
9194 "CSR_64_RT_AllRegs",
9195 "CSR_64_RT_AllRegs_AVX",
9196 "CSR_64_RT_MostRegs",
9197 "CSR_64_SwiftError",
9198 "CSR_64_SwiftTail",
9199 "CSR_64_TLS_Darwin",
9200 "CSR_IPRA_32",
9201 "CSR_IPRA_64",
9202 "CSR_NoRegs",
9203 "CSR_SysV64_RegCall",
9204 "CSR_SysV64_RegCall_NoSSE",
9205 "CSR_Win32_CFGuard_Check",
9206 "CSR_Win32_CFGuard_Check_NoSSE",
9207 "CSR_Win64",
9208 "CSR_Win64_APX",
9209 "CSR_Win64_APX_CFGuard_Check",
9210 "CSR_Win64_APX_Intel_OCL_BI_AVX",
9211 "CSR_Win64_APX_Intel_OCL_BI_AVX512",
9212 "CSR_Win64_APX_RT_MostRegs",
9213 "CSR_Win64_APX_RegCall",
9214 "CSR_Win64_APX_SwiftError",
9215 "CSR_Win64_APX_SwiftTail",
9216 "CSR_Win64_CFGuard_Check",
9217 "CSR_Win64_CFGuard_Check_NoSSE",
9218 "CSR_Win64_Intel_OCL_BI_AVX",
9219 "CSR_Win64_Intel_OCL_BI_AVX512",
9220 "CSR_Win64_NoSSE",
9221 "CSR_Win64_RT_MostRegs",
9222 "CSR_Win64_RegCall",
9223 "CSR_Win64_RegCall_NoSSE",
9224 "CSR_Win64_SwiftError",
9225 "CSR_Win64_SwiftTail",
9226 };
9227 return ArrayRef(Names);
9228}
9229
9230const X86FrameLowering *
9231X86GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
9232 return static_cast<const X86FrameLowering *>(
9233 MF.getSubtarget().getFrameLowering());
9234}
9235
9236
9237} // namespace llvm
9238