1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass X86MCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::i8, MVT::Other,
15 /* 2 */ MVT::i16, MVT::Other,
16 /* 4 */ MVT::i32, MVT::Other,
17 /* 6 */ MVT::i64, MVT::Other,
18 /* 8 */ MVT::f16, MVT::Other,
19 /* 10 */ MVT::f80, MVT::f64, MVT::f32, MVT::Other,
20 /* 14 */ MVT::f64, MVT::Other,
21 /* 16 */ MVT::f80, MVT::Other,
22 /* 18 */ MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::v8bf16, MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::f128, MVT::Other,
23 /* 28 */ MVT::v1i1, MVT::Other,
24 /* 30 */ MVT::v2i1, MVT::Other,
25 /* 32 */ MVT::v4i1, MVT::Other,
26 /* 34 */ MVT::v8i1, MVT::Other,
27 /* 36 */ MVT::v16i1, MVT::Other,
28 /* 38 */ MVT::v32i1, MVT::Other,
29 /* 40 */ MVT::v64i1, MVT::Other,
30 /* 42 */ MVT::v8f32, MVT::v4f64, MVT::v16f16, MVT::v16bf16, MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::Other,
31 /* 51 */ MVT::v16f32, MVT::v8f64, MVT::v32f16, MVT::v32bf16, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
32 /* 60 */ MVT::v16f32, MVT::v8f64, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
33 /* 67 */ MVT::x86mmx, MVT::Other,
34 /* 69 */ MVT::Untyped, MVT::Other,
35 /* 71 */ MVT::x86amx, MVT::Other,
36};
37
38static const char *SubRegIndexNameTable[] = { "sub_8bit", "sub_8bit_hi", "sub_8bit_hi_phony", "sub_16bit", "sub_16bit_hi", "sub_32bit", "sub_mask_0", "sub_mask_1", "sub_xmm", "sub_ymm", "" };
39
40static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
41 { .Offset: 65535, .Size: 65535 },
42 { .Offset: 0, .Size: 8 }, // sub_8bit
43 { .Offset: 8, .Size: 8 }, // sub_8bit_hi
44 { .Offset: 8, .Size: 8 }, // sub_8bit_hi_phony
45 { .Offset: 0, .Size: 16 }, // sub_16bit
46 { .Offset: 16, .Size: 16 }, // sub_16bit_hi
47 { .Offset: 0, .Size: 32 }, // sub_32bit
48 { .Offset: 0, .Size: 65535 }, // sub_mask_0
49 { .Offset: 65535, .Size: 65535 }, // sub_mask_1
50 { .Offset: 0, .Size: 128 }, // sub_xmm
51 { .Offset: 0, .Size: 256 }, // sub_ymm
52 { .Offset: 65535, .Size: 65535 },
53 { .Offset: 0, .Size: 8 }, // sub_8bit
54 { .Offset: 8, .Size: 8 }, // sub_8bit_hi
55 { .Offset: 8, .Size: 8 }, // sub_8bit_hi_phony
56 { .Offset: 0, .Size: 16 }, // sub_16bit
57 { .Offset: 16, .Size: 16 }, // sub_16bit_hi
58 { .Offset: 0, .Size: 32 }, // sub_32bit
59 { .Offset: 0, .Size: 65535 }, // sub_mask_0
60 { .Offset: 65535, .Size: 65535 }, // sub_mask_1
61 { .Offset: 0, .Size: 128 }, // sub_xmm
62 { .Offset: 0, .Size: 256 }, // sub_ymm
63 { .Offset: 65535, .Size: 65535 },
64 { .Offset: 0, .Size: 8 }, // sub_8bit
65 { .Offset: 8, .Size: 8 }, // sub_8bit_hi
66 { .Offset: 8, .Size: 8 }, // sub_8bit_hi_phony
67 { .Offset: 0, .Size: 16 }, // sub_16bit
68 { .Offset: 16, .Size: 16 }, // sub_16bit_hi
69 { .Offset: 0, .Size: 32 }, // sub_32bit
70 { .Offset: 0, .Size: 65535 }, // sub_mask_0
71 { .Offset: 65535, .Size: 65535 }, // sub_mask_1
72 { .Offset: 0, .Size: 128 }, // sub_xmm
73 { .Offset: 0, .Size: 256 }, // sub_ymm
74};
75
76
77static const LaneBitmask SubRegIndexLaneMaskTable[] = {
78 LaneBitmask::getAll(),
79 LaneBitmask(0x0000000000000001), // sub_8bit
80 LaneBitmask(0x0000000000000002), // sub_8bit_hi
81 LaneBitmask(0x0000000000000004), // sub_8bit_hi_phony
82 LaneBitmask(0x0000000000000007), // sub_16bit
83 LaneBitmask(0x0000000000000008), // sub_16bit_hi
84 LaneBitmask(0x000000000000000F), // sub_32bit
85 LaneBitmask(0x0000000000000010), // sub_mask_0
86 LaneBitmask(0x0000000000000020), // sub_mask_1
87 LaneBitmask(0x0000000000000040), // sub_xmm
88 LaneBitmask(0x0000000000000040), // sub_ymm
89 };
90
91
92
93static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
94 // Mode = 0 (Default)
95 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GR8
96 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GRH8
97 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GR8_NOREX2
98 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GR8_NOREX
99 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_H
100 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_L
101 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 2 }, // GRH16
102 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 2 }, // GR16
103 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 2 }, // GR16_NOREX2
104 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 2 }, // GR16_NOREX
105 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 28 }, // VK1
106 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 36 }, // VK16
107 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 30 }, // VK2
108 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 32 }, // VK4
109 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 34 }, // VK8
110 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 36 }, // VK16WM
111 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 28 }, // VK1WM
112 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 30 }, // VK2WM
113 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 32 }, // VK4WM
114 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 34 }, // VK8WM
115 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 2 }, // SEGMENT_REG
116 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 2 }, // GR16_ABCD
117 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 2 }, // FPCCR
118 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 8 }, // FR16X
119 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 8 }, // FR16
120 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 69 }, // VK16PAIR
121 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 69 }, // VK1PAIR
122 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 69 }, // VK2PAIR
123 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 69 }, // VK4PAIR
124 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 69 }, // VK8PAIR
125 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 69 }, // VK1PAIR_with_sub_mask_0_in_VK1WM
126 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP
127 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS
128 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
129 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 12 }, // FR32X
130 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32
131 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_NOSP
132 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
133 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // DEBUG_REG
134 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 12 }, // FR32
135 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2
136 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2_NOSP
137 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
138 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_NOREX
139 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 38 }, // VK32
140 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_NOREX_NOSP
141 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 12 }, // RFP32
142 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 38 }, // VK32WM
143 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_ABCD
144 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_TC
145 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_TC
146 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_AD
147 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef
148 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_BPSP
149 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_BSI
150 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_CB
151 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_DC
152 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_DIBP
153 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_SIDI
154 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
155 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // CCR
156 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // DFCCR
157 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_BSI
158 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_AD_and_GR32_ArgRef
159 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef_and_GR32_CB
160 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_DIBP
161 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_TC
162 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_BSI_and_GR32_SIDI
163 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_DIBP_and_GR32_SIDI
164 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
165 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_with_sub_32bit
166 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 14 }, // RFP64
167 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64
168 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 14 }, // FR64X
169 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_8bit
170 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOSP
171 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2
172 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // CONTROL_REG
173 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 14 }, // FR64
174 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX2
175 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP
176 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe
177 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TC
178 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX
179 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TCW64
180 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TC_with_sub_8bit
181 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TC
182 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_with_sub_8bit
183 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_TCW64
184 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX
185 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 40 }, // VK64
186 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 67 }, // VR64
187 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TC
188 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TCW64
189 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_NOSP
190 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TC
191 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_and_GR64_TC_with_sub_8bit
192 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 40 }, // VK64WM
193 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
194 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
195 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TCW64
196 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
197 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TCW64
198 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_ABCD
199 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_TC
200 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
201 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_AD
202 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef
203 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS_RBP
204 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef
205 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP
206 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI
207 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_CB
208 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP
209 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_SIDI
210 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_A
211 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef_and_GR64_TC
212 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS
213 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
214 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
215 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
216 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
217 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
218 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
219 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
220 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 10 }, // RST
221 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 16 }, // RFP80
222 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 16 }, // RFP80_7
223 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 18 }, // VR128X
224 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 18 }, // VR128
225 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*VTLists+*/.VTListOffset: 42 }, // VR256X
226 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*VTLists+*/.VTListOffset: 42 }, // VR256
227 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*VTLists+*/.VTListOffset: 51 }, // VR512
228 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*VTLists+*/.VTListOffset: 60 }, // VR512_0_15
229 { .RegSize: 8192, .SpillSize: 8192, .SpillAlignment: 8192, /*VTLists+*/.VTListOffset: 71 }, // TILE
230 // Mode = 1 (X86_64)
231 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GR8
232 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GRH8
233 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GR8_NOREX2
234 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GR8_NOREX
235 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_H
236 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_L
237 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 2 }, // GRH16
238 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 2 }, // GR16
239 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 2 }, // GR16_NOREX2
240 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 2 }, // GR16_NOREX
241 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 28 }, // VK1
242 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 36 }, // VK16
243 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 30 }, // VK2
244 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 32 }, // VK4
245 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 34 }, // VK8
246 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 36 }, // VK16WM
247 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 28 }, // VK1WM
248 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 30 }, // VK2WM
249 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 32 }, // VK4WM
250 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 34 }, // VK8WM
251 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 2 }, // SEGMENT_REG
252 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 2 }, // GR16_ABCD
253 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 2 }, // FPCCR
254 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 8 }, // FR16X
255 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 8 }, // FR16
256 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 69 }, // VK16PAIR
257 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 69 }, // VK1PAIR
258 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 69 }, // VK2PAIR
259 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 69 }, // VK4PAIR
260 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 69 }, // VK8PAIR
261 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 69 }, // VK1PAIR_with_sub_mask_0_in_VK1WM
262 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP
263 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS
264 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
265 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 12 }, // FR32X
266 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32
267 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_NOSP
268 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
269 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // DEBUG_REG
270 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 12 }, // FR32
271 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2
272 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2_NOSP
273 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
274 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_NOREX
275 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 38 }, // VK32
276 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_NOREX_NOSP
277 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 12 }, // RFP32
278 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 38 }, // VK32WM
279 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_ABCD
280 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_TC
281 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_TC
282 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_AD
283 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef
284 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_BPSP
285 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_BSI
286 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_CB
287 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_DC
288 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_DIBP
289 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_SIDI
290 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
291 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // CCR
292 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // DFCCR
293 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_BSI
294 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_AD_and_GR32_ArgRef
295 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef_and_GR32_CB
296 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_DIBP
297 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_TC
298 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_BSI_and_GR32_SIDI
299 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_DIBP_and_GR32_SIDI
300 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
301 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_with_sub_32bit
302 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 14 }, // RFP64
303 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64
304 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 14 }, // FR64X
305 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_8bit
306 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOSP
307 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2
308 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // CONTROL_REG
309 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 14 }, // FR64
310 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX2
311 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP
312 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe
313 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TC
314 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX
315 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TCW64
316 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TC_with_sub_8bit
317 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TC
318 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_with_sub_8bit
319 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_TCW64
320 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX
321 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 40 }, // VK64
322 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 67 }, // VR64
323 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TC
324 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TCW64
325 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_NOSP
326 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TC
327 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_and_GR64_TC_with_sub_8bit
328 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 40 }, // VK64WM
329 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
330 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
331 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TCW64
332 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
333 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TCW64
334 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_ABCD
335 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_TC
336 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
337 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_AD
338 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef
339 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS_RBP
340 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef
341 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP
342 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI
343 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_CB
344 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP
345 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_SIDI
346 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_A
347 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef_and_GR64_TC
348 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS
349 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
350 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
351 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
352 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
353 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
354 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
355 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
356 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 10 }, // RST
357 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 16 }, // RFP80
358 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 16 }, // RFP80_7
359 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 18 }, // VR128X
360 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 18 }, // VR128
361 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*VTLists+*/.VTListOffset: 42 }, // VR256X
362 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*VTLists+*/.VTListOffset: 42 }, // VR256
363 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*VTLists+*/.VTListOffset: 51 }, // VR512
364 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*VTLists+*/.VTListOffset: 60 }, // VR512_0_15
365 { .RegSize: 8192, .SpillSize: 8192, .SpillAlignment: 8192, /*VTLists+*/.VTListOffset: 71 }, // TILE
366 // Mode = 2 (X86_64_X32)
367 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GR8
368 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GRH8
369 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GR8_NOREX2
370 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GR8_NOREX
371 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_H
372 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_L
373 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 2 }, // GRH16
374 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 2 }, // GR16
375 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 2 }, // GR16_NOREX2
376 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 2 }, // GR16_NOREX
377 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 28 }, // VK1
378 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 36 }, // VK16
379 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 30 }, // VK2
380 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 32 }, // VK4
381 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 34 }, // VK8
382 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 36 }, // VK16WM
383 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 28 }, // VK1WM
384 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 30 }, // VK2WM
385 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 32 }, // VK4WM
386 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 34 }, // VK8WM
387 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 2 }, // SEGMENT_REG
388 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 2 }, // GR16_ABCD
389 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 2 }, // FPCCR
390 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 8 }, // FR16X
391 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 8 }, // FR16
392 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 69 }, // VK16PAIR
393 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 69 }, // VK1PAIR
394 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 69 }, // VK2PAIR
395 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 69 }, // VK4PAIR
396 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 69 }, // VK8PAIR
397 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*VTLists+*/.VTListOffset: 69 }, // VK1PAIR_with_sub_mask_0_in_VK1WM
398 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP
399 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS
400 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
401 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 12 }, // FR32X
402 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32
403 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_NOSP
404 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
405 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // DEBUG_REG
406 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 12 }, // FR32
407 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2
408 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2_NOSP
409 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
410 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_NOREX
411 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 38 }, // VK32
412 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_NOREX_NOSP
413 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 12 }, // RFP32
414 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 38 }, // VK32WM
415 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_ABCD
416 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_TC
417 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_TC
418 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_AD
419 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef
420 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_BPSP
421 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_BSI
422 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_CB
423 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_DC
424 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_DIBP
425 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_SIDI
426 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
427 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // CCR
428 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // DFCCR
429 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_BSI
430 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_AD_and_GR32_ArgRef
431 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef_and_GR32_CB
432 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_DIBP
433 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_TC
434 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_BSI_and_GR32_SIDI
435 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GR32_DIBP_and_GR32_SIDI
436 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
437 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_with_sub_32bit
438 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 14 }, // RFP64
439 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64
440 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 14 }, // FR64X
441 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_8bit
442 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOSP
443 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2
444 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // CONTROL_REG
445 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 14 }, // FR64
446 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX2
447 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP
448 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe
449 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TC
450 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX
451 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TCW64
452 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TC_with_sub_8bit
453 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TC
454 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_with_sub_8bit
455 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_TCW64
456 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX
457 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 40 }, // VK64
458 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 67 }, // VR64
459 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TC
460 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TCW64
461 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_NOSP
462 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TC
463 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_and_GR64_TC_with_sub_8bit
464 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 40 }, // VK64WM
465 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
466 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
467 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TCW64
468 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
469 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TCW64
470 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_ABCD
471 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_TC
472 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
473 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_AD
474 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef
475 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS_RBP
476 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef
477 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP
478 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI
479 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_CB
480 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP
481 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_SIDI
482 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_A
483 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef_and_GR64_TC
484 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS
485 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
486 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
487 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
488 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
489 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
490 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
491 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
492 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 10 }, // RST
493 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 16 }, // RFP80
494 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 16 }, // RFP80_7
495 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 18 }, // VR128X
496 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 18 }, // VR128
497 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*VTLists+*/.VTListOffset: 42 }, // VR256X
498 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*VTLists+*/.VTListOffset: 42 }, // VR256
499 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*VTLists+*/.VTListOffset: 51 }, // VR512
500 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*VTLists+*/.VTListOffset: 60 }, // VR512_0_15
501 { .RegSize: 8192, .SpillSize: 8192, .SpillAlignment: 8192, /*VTLists+*/.VTListOffset: 71 }, // TILE
502};
503static const uint32_t GR8SubClassMask[] = {
504 0x0000003d, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
505 0x00200380, 0xc7ff2f3a, 0x72e38c3f, 0x1fdfefbd, 0x00000000, // sub_8bit
506 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
507};
508
509static const uint32_t GRH8SubClassMask[] = {
510 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
511};
512
513static const uint32_t GR8_NOREX2SubClassMask[] = {
514 0x0000003c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
515 0x00200300, 0xc7ff2f20, 0x72e3803f, 0x1fdfefbd, 0x00000000, // sub_8bit
516 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
517};
518
519static const uint32_t GR8_NOREXSubClassMask[] = {
520 0x00000038, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
521 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit
522 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
523};
524
525static const uint32_t GR8_ABCD_HSubClassMask[] = {
526 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
527 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
528};
529
530static const uint32_t GR8_ABCD_LSubClassMask[] = {
531 0x00000020, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
532 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit
533};
534
535static const uint32_t GRH16SubClassMask[] = {
536 0x00000040, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
537};
538
539static const uint32_t GR16SubClassMask[] = {
540 0x00200380, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
541 0x00000000, 0xc7ff2f3a, 0x72e38c3f, 0x1fdfefbd, 0x00000000, // sub_16bit
542};
543
544static const uint32_t GR16_NOREX2SubClassMask[] = {
545 0x00200300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
546 0x00000000, 0xc7ff2f20, 0x72e3803f, 0x1fdfefbd, 0x00000000, // sub_16bit
547};
548
549static const uint32_t GR16_NOREXSubClassMask[] = {
550 0x00200200, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
551 0x00000000, 0xc7ff2c00, 0x4200003f, 0x1fcfe7a8, 0x00000000, // sub_16bit
552};
553
554static const uint32_t VK1SubClassMask[] = {
555 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
556 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
557 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
558};
559
560static const uint32_t VK16SubClassMask[] = {
561 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
562 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
563 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
564};
565
566static const uint32_t VK2SubClassMask[] = {
567 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
568 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
569 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
570};
571
572static const uint32_t VK4SubClassMask[] = {
573 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
574 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
575 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
576};
577
578static const uint32_t VK8SubClassMask[] = {
579 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
580 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
581 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
582};
583
584static const uint32_t VK16WMSubClassMask[] = {
585 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
586 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
587 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
588};
589
590static const uint32_t VK1WMSubClassMask[] = {
591 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
592 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
593 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
594};
595
596static const uint32_t VK2WMSubClassMask[] = {
597 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
598 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
599 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
600};
601
602static const uint32_t VK4WMSubClassMask[] = {
603 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
604 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
605 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
606};
607
608static const uint32_t VK8WMSubClassMask[] = {
609 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
610 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
611 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
612};
613
614static const uint32_t SEGMENT_REGSubClassMask[] = {
615 0x00100000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
616};
617
618static const uint32_t GR16_ABCDSubClassMask[] = {
619 0x00200000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
620 0x00000000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_16bit
621};
622
623static const uint32_t FPCCRSubClassMask[] = {
624 0x00400000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
625};
626
627static const uint32_t FR16XSubClassMask[] = {
628 0x01800000, 0x00000084, 0x00004200, 0x00000000, 0x00000003,
629 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
630};
631
632static const uint32_t FR16SubClassMask[] = {
633 0x01000000, 0x00000080, 0x00004000, 0x00000000, 0x00000002,
634 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
635};
636
637static const uint32_t VK16PAIRSubClassMask[] = {
638 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
639};
640
641static const uint32_t VK1PAIRSubClassMask[] = {
642 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
643};
644
645static const uint32_t VK2PAIRSubClassMask[] = {
646 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
647};
648
649static const uint32_t VK4PAIRSubClassMask[] = {
650 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
651};
652
653static const uint32_t VK8PAIRSubClassMask[] = {
654 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
655};
656
657static const uint32_t VK1PAIR_with_sub_mask_0_in_VK1WMSubClassMask[] = {
658 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
659};
660
661static const uint32_t LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
662 0x80000000, 0xcfff2f3b, 0x0000007f, 0x02201000, 0x00000000,
663 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
664};
665
666static const uint32_t LOW32_ADDR_ACCESSSubClassMask[] = {
667 0x00000000, 0xc7ff2b19, 0x0000005f, 0x00200000, 0x00000000,
668 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
669};
670
671static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask[] = {
672 0x00000000, 0xc7ff2f3a, 0x0000003f, 0x02000000, 0x00000000,
673 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
674};
675
676static const uint32_t FR32XSubClassMask[] = {
677 0x00000000, 0x00000084, 0x00004200, 0x00000000, 0x00000003,
678 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
679};
680
681static const uint32_t GR32SubClassMask[] = {
682 0x00000000, 0xc7ff2b18, 0x0000001f, 0x00000000, 0x00000000,
683 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
684};
685
686static const uint32_t GR32_NOSPSubClassMask[] = {
687 0x00000000, 0xc7dd2210, 0x0000001b, 0x00000000, 0x00000000,
688 0x00000000, 0x00000000, 0x70430820, 0x1bdfaeb4, 0x00000000, // sub_32bit
689};
690
691static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2SubClassMask[] = {
692 0x00000000, 0xc7ff2f20, 0x0000003f, 0x02000000, 0x00000000,
693 0x00000000, 0x00000000, 0x72e38020, 0x1fdfefbd, 0x00000000, // sub_32bit
694};
695
696static const uint32_t DEBUG_REGSubClassMask[] = {
697 0x00000000, 0x00000040, 0x00000000, 0x00000000, 0x00000000,
698};
699
700static const uint32_t FR32SubClassMask[] = {
701 0x00000000, 0x00000080, 0x00004000, 0x00000000, 0x00000002,
702 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
703};
704
705static const uint32_t GR32_NOREX2SubClassMask[] = {
706 0x00000000, 0xc7ff2b00, 0x0000001f, 0x00000000, 0x00000000,
707 0x00000000, 0x00000000, 0x72e38020, 0x1fdfefbd, 0x00000000, // sub_32bit
708};
709
710static const uint32_t GR32_NOREX2_NOSPSubClassMask[] = {
711 0x00000000, 0xc7dd2200, 0x0000001b, 0x00000000, 0x00000000,
712 0x00000000, 0x00000000, 0x70430020, 0x1bdfaeb4, 0x00000000, // sub_32bit
713};
714
715static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
716 0x00000000, 0xc7ff2c00, 0x0000003f, 0x02000000, 0x00000000,
717 0x00000000, 0x00000000, 0x42000020, 0x1fcfe7a8, 0x00000000, // sub_32bit
718};
719
720static const uint32_t GR32_NOREXSubClassMask[] = {
721 0x00000000, 0xc7ff2800, 0x0000001f, 0x00000000, 0x00000000,
722 0x00000000, 0x00000000, 0x42000020, 0x1fcfe7a8, 0x00000000, // sub_32bit
723};
724
725static const uint32_t VK32SubClassMask[] = {
726 0x00000000, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
727 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
728 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
729};
730
731static const uint32_t GR32_NOREX_NOSPSubClassMask[] = {
732 0x00000000, 0xc7dd2000, 0x0000001b, 0x00000000, 0x00000000,
733 0x00000000, 0x00000000, 0x40000020, 0x1bcfa6a0, 0x00000000, // sub_32bit
734};
735
736static const uint32_t RFP32SubClassMask[] = {
737 0x00000000, 0x00004000, 0x00000080, 0x40000000, 0x00000000,
738};
739
740static const uint32_t VK32WMSubClassMask[] = {
741 0x00000000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
742 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
743 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
744};
745
746static const uint32_t GR32_ABCDSubClassMask[] = {
747 0x00000000, 0xc19d0000, 0x00000001, 0x00000000, 0x00000000,
748 0x00000000, 0x00000000, 0x00000000, 0x01c92680, 0x00000000, // sub_32bit
749};
750
751static const uint32_t GR32_TCSubClassMask[] = {
752 0x00000000, 0x811e0000, 0x00000005, 0x00000000, 0x00000000,
753 0x00000000, 0x00000000, 0x00000000, 0x05882700, 0x00000000, // sub_32bit
754};
755
756static const uint32_t GR32_ABCD_and_GR32_TCSubClassMask[] = {
757 0x00000000, 0x811c0000, 0x00000001, 0x00000000, 0x00000000,
758 0x00000000, 0x00000000, 0x00000000, 0x01882600, 0x00000000, // sub_32bit
759};
760
761static const uint32_t GR32_ADSubClassMask[] = {
762 0x00000000, 0x80080000, 0x00000000, 0x00000000, 0x00000000,
763 0x00000000, 0x00000000, 0x00000000, 0x00880400, 0x00000000, // sub_32bit
764};
765
766static const uint32_t GR32_ArgRefSubClassMask[] = {
767 0x00000000, 0x81100000, 0x00000001, 0x00000000, 0x00000000,
768 0x00000000, 0x00000000, 0x00000000, 0x01802000, 0x00000000, // sub_32bit
769};
770
771static const uint32_t GR32_BPSPSubClassMask[] = {
772 0x00000000, 0x00200000, 0x00000006, 0x00000000, 0x00000000,
773 0x00000000, 0x00000000, 0x00000020, 0x06004000, 0x00000000, // sub_32bit
774};
775
776static const uint32_t GR32_BSISubClassMask[] = {
777 0x00000000, 0x40400000, 0x00000008, 0x00000000, 0x00000000,
778 0x00000000, 0x00000000, 0x00000000, 0x08408000, 0x00000000, // sub_32bit
779};
780
781static const uint32_t GR32_CBSubClassMask[] = {
782 0x00000000, 0x40800000, 0x00000001, 0x00000000, 0x00000000,
783 0x00000000, 0x00000000, 0x00000000, 0x01410000, 0x00000000, // sub_32bit
784};
785
786static const uint32_t GR32_DCSubClassMask[] = {
787 0x00000000, 0x81000000, 0x00000001, 0x00000000, 0x00000000,
788 0x00000000, 0x00000000, 0x00000000, 0x01802000, 0x00000000, // sub_32bit
789};
790
791static const uint32_t GR32_DIBPSubClassMask[] = {
792 0x00000000, 0x02000000, 0x00000012, 0x00000000, 0x00000000,
793 0x00000000, 0x00000000, 0x00000020, 0x12020000, 0x00000000, // sub_32bit
794};
795
796static const uint32_t GR32_SIDISubClassMask[] = {
797 0x00000000, 0x04000000, 0x00000018, 0x00000000, 0x00000000,
798 0x00000000, 0x00000000, 0x00000000, 0x18040000, 0x00000000, // sub_32bit
799};
800
801static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask[] = {
802 0x00000000, 0x08000000, 0x00000060, 0x02201000, 0x00000000,
803};
804
805static const uint32_t CCRSubClassMask[] = {
806 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000,
807};
808
809static const uint32_t DFCCRSubClassMask[] = {
810 0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00000000,
811};
812
813static const uint32_t GR32_ABCD_and_GR32_BSISubClassMask[] = {
814 0x00000000, 0x40000000, 0x00000000, 0x00000000, 0x00000000,
815 0x00000000, 0x00000000, 0x00000000, 0x00400000, 0x00000000, // sub_32bit
816};
817
818static const uint32_t GR32_AD_and_GR32_ArgRefSubClassMask[] = {
819 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000,
820 0x00000000, 0x00000000, 0x00000000, 0x00800000, 0x00000000, // sub_32bit
821};
822
823static const uint32_t GR32_ArgRef_and_GR32_CBSubClassMask[] = {
824 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000,
825 0x00000000, 0x00000000, 0x00000000, 0x01000000, 0x00000000, // sub_32bit
826};
827
828static const uint32_t GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
829 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000,
830 0x00000000, 0x00000000, 0x00000020, 0x02000000, 0x00000000, // sub_32bit
831};
832
833static const uint32_t GR32_BPSP_and_GR32_TCSubClassMask[] = {
834 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000,
835 0x00000000, 0x00000000, 0x00000000, 0x04000000, 0x00000000, // sub_32bit
836};
837
838static const uint32_t GR32_BSI_and_GR32_SIDISubClassMask[] = {
839 0x00000000, 0x00000000, 0x00000008, 0x00000000, 0x00000000,
840 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000000, // sub_32bit
841};
842
843static const uint32_t GR32_DIBP_and_GR32_SIDISubClassMask[] = {
844 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000,
845 0x00000000, 0x00000000, 0x00000000, 0x10000000, 0x00000000, // sub_32bit
846};
847
848static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask[] = {
849 0x00000000, 0x00000000, 0x00000020, 0x02000000, 0x00000000,
850};
851
852static const uint32_t LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask[] = {
853 0x00000000, 0x00000000, 0x00000040, 0x00200000, 0x00000000,
854};
855
856static const uint32_t RFP64SubClassMask[] = {
857 0x00000000, 0x00000000, 0x00000080, 0x40000000, 0x00000000,
858};
859
860static const uint32_t GR64SubClassMask[] = {
861 0x00000000, 0x00000000, 0xf3ff9d00, 0x1ffffffd, 0x00000000,
862};
863
864static const uint32_t FR64XSubClassMask[] = {
865 0x00000000, 0x00000000, 0x00004200, 0x00000000, 0x00000003,
866 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
867};
868
869static const uint32_t GR64_with_sub_8bitSubClassMask[] = {
870 0x00000000, 0x00000000, 0x72e38c00, 0x1fdfefbd, 0x00000000,
871};
872
873static const uint32_t GR64_NOSPSubClassMask[] = {
874 0x00000000, 0x00000000, 0x70430800, 0x1bdfaeb4, 0x00000000,
875};
876
877static const uint32_t GR64_NOREX2SubClassMask[] = {
878 0x00000000, 0x00000000, 0xf3ff9000, 0x1ffffffd, 0x00000000,
879};
880
881static const uint32_t CONTROL_REGSubClassMask[] = {
882 0x00000000, 0x00000000, 0x00002000, 0x00000000, 0x00000000,
883};
884
885static const uint32_t FR64SubClassMask[] = {
886 0x00000000, 0x00000000, 0x00004000, 0x00000000, 0x00000002,
887 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
888};
889
890static const uint32_t GR64_with_sub_16bit_in_GR16_NOREX2SubClassMask[] = {
891 0x00000000, 0x00000000, 0x72e38000, 0x1fdfefbd, 0x00000000,
892};
893
894static const uint32_t GR64_NOREX2_NOSPSubClassMask[] = {
895 0x00000000, 0x00000000, 0x70430000, 0x1bdfaeb4, 0x00000000,
896};
897
898static const uint32_t GR64PLTSafeSubClassMask[] = {
899 0x00000000, 0x00000000, 0x50020000, 0x1bcfa6b0, 0x00000000,
900};
901
902static const uint32_t GR64_TCSubClassMask[] = {
903 0x00000000, 0x00000000, 0x91640000, 0x1dbc277d, 0x00000000,
904};
905
906static const uint32_t GR64_NOREXSubClassMask[] = {
907 0x00000000, 0x00000000, 0xc2080000, 0x1feff7e8, 0x00000000,
908};
909
910static const uint32_t GR64_TCW64SubClassMask[] = {
911 0x00000000, 0x00000000, 0x21900000, 0x05b82f55, 0x00000000,
912};
913
914static const uint32_t GR64_TC_with_sub_8bitSubClassMask[] = {
915 0x00000000, 0x00000000, 0x10600000, 0x1d9c273d, 0x00000000,
916};
917
918static const uint32_t GR64_NOREX2_NOSP_and_GR64_TCSubClassMask[] = {
919 0x00000000, 0x00000000, 0x10400000, 0x199c2634, 0x00000000,
920};
921
922static const uint32_t GR64_TCW64_with_sub_8bitSubClassMask[] = {
923 0x00000000, 0x00000000, 0x20800000, 0x05982f15, 0x00000000,
924};
925
926static const uint32_t GR64_TC_and_GR64_TCW64SubClassMask[] = {
927 0x00000000, 0x00000000, 0x01000000, 0x05b82755, 0x00000000,
928};
929
930static const uint32_t GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
931 0x00000000, 0x00000000, 0x42000000, 0x1fcfe7a8, 0x00000000,
932};
933
934static const uint32_t VK64SubClassMask[] = {
935 0x00000000, 0x00000000, 0x04000000, 0x00000002, 0x00000000,
936 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
937 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
938};
939
940static const uint32_t VR64SubClassMask[] = {
941 0x00000000, 0x00000000, 0x08000000, 0x00000000, 0x00000000,
942};
943
944static const uint32_t GR64PLTSafe_and_GR64_TCSubClassMask[] = {
945 0x00000000, 0x00000000, 0x10000000, 0x198c2630, 0x00000000,
946};
947
948static const uint32_t GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask[] = {
949 0x00000000, 0x00000000, 0x20000000, 0x01982e14, 0x00000000,
950};
951
952static const uint32_t GR64_NOREX_NOSPSubClassMask[] = {
953 0x00000000, 0x00000000, 0x40000000, 0x1bcfa6a0, 0x00000000,
954};
955
956static const uint32_t GR64_NOREX_and_GR64_TCSubClassMask[] = {
957 0x00000000, 0x00000000, 0x80000000, 0x1dac2768, 0x00000000,
958};
959
960static const uint32_t GR64_TCW64_and_GR64_TC_with_sub_8bitSubClassMask[] = {
961 0x00000000, 0x00000000, 0x00000000, 0x05982715, 0x00000000,
962};
963
964static const uint32_t VK64WMSubClassMask[] = {
965 0x00000000, 0x00000000, 0x00000000, 0x00000002, 0x00000000,
966 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
967 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
968};
969
970static const uint32_t GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask[] = {
971 0x00000000, 0x00000000, 0x00000000, 0x01982614, 0x00000000,
972};
973
974static const uint32_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
975 0x00000000, 0x00000000, 0x00000000, 0x1d8c2728, 0x00000000,
976};
977
978static const uint32_t GR64PLTSafe_and_GR64_TCW64SubClassMask[] = {
979 0x00000000, 0x00000000, 0x00000000, 0x01882610, 0x00000000,
980};
981
982static const uint32_t GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSubClassMask[] = {
983 0x00000000, 0x00000000, 0x00000000, 0x198c2620, 0x00000000,
984};
985
986static const uint32_t GR64_NOREX_and_GR64_TCW64SubClassMask[] = {
987 0x00000000, 0x00000000, 0x00000000, 0x05a82740, 0x00000000,
988};
989
990static const uint32_t GR64_ABCDSubClassMask[] = {
991 0x00000000, 0x00000000, 0x00000000, 0x01c92680, 0x00000000,
992};
993
994static const uint32_t GR64_with_sub_32bit_in_GR32_TCSubClassMask[] = {
995 0x00000000, 0x00000000, 0x00000000, 0x05882700, 0x00000000,
996};
997
998static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSubClassMask[] = {
999 0x00000000, 0x00000000, 0x00000000, 0x01882600, 0x00000000,
1000};
1001
1002static const uint32_t GR64_ADSubClassMask[] = {
1003 0x00000000, 0x00000000, 0x00000000, 0x00880400, 0x00000000,
1004};
1005
1006static const uint32_t GR64_ArgRefSubClassMask[] = {
1007 0x00000000, 0x00000000, 0x00000000, 0x00100800, 0x00000000,
1008};
1009
1010static const uint32_t GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
1011 0x00000000, 0x00000000, 0x00000000, 0x02201000, 0x00000000,
1012};
1013
1014static const uint32_t GR64_with_sub_32bit_in_GR32_ArgRefSubClassMask[] = {
1015 0x00000000, 0x00000000, 0x00000000, 0x01802000, 0x00000000,
1016};
1017
1018static const uint32_t GR64_with_sub_32bit_in_GR32_BPSPSubClassMask[] = {
1019 0x00000000, 0x00000000, 0x00000000, 0x06004000, 0x00000000,
1020};
1021
1022static const uint32_t GR64_with_sub_32bit_in_GR32_BSISubClassMask[] = {
1023 0x00000000, 0x00000000, 0x00000000, 0x08408000, 0x00000000,
1024};
1025
1026static const uint32_t GR64_with_sub_32bit_in_GR32_CBSubClassMask[] = {
1027 0x00000000, 0x00000000, 0x00000000, 0x01410000, 0x00000000,
1028};
1029
1030static const uint32_t GR64_with_sub_32bit_in_GR32_DIBPSubClassMask[] = {
1031 0x00000000, 0x00000000, 0x00000000, 0x12020000, 0x00000000,
1032};
1033
1034static const uint32_t GR64_with_sub_32bit_in_GR32_SIDISubClassMask[] = {
1035 0x00000000, 0x00000000, 0x00000000, 0x18040000, 0x00000000,
1036};
1037
1038static const uint32_t GR64_ASubClassMask[] = {
1039 0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00000000,
1040};
1041
1042static const uint32_t GR64_ArgRef_and_GR64_TCSubClassMask[] = {
1043 0x00000000, 0x00000000, 0x00000000, 0x00100000, 0x00000000,
1044};
1045
1046static const uint32_t GR64_and_LOW32_ADDR_ACCESSSubClassMask[] = {
1047 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00000000,
1048};
1049
1050static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask[] = {
1051 0x00000000, 0x00000000, 0x00000000, 0x00400000, 0x00000000,
1052};
1053
1054static const uint32_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSubClassMask[] = {
1055 0x00000000, 0x00000000, 0x00000000, 0x00800000, 0x00000000,
1056};
1057
1058static const uint32_t GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSubClassMask[] = {
1059 0x00000000, 0x00000000, 0x00000000, 0x01000000, 0x00000000,
1060};
1061
1062static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
1063 0x00000000, 0x00000000, 0x00000000, 0x02000000, 0x00000000,
1064};
1065
1066static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSubClassMask[] = {
1067 0x00000000, 0x00000000, 0x00000000, 0x04000000, 0x00000000,
1068};
1069
1070static const uint32_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask[] = {
1071 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000000,
1072};
1073
1074static const uint32_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask[] = {
1075 0x00000000, 0x00000000, 0x00000000, 0x10000000, 0x00000000,
1076};
1077
1078static const uint32_t RSTSubClassMask[] = {
1079 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000,
1080};
1081
1082static const uint32_t RFP80SubClassMask[] = {
1083 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00000000,
1084};
1085
1086static const uint32_t RFP80_7SubClassMask[] = {
1087 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00000000,
1088};
1089
1090static const uint32_t VR128XSubClassMask[] = {
1091 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000003,
1092 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
1093};
1094
1095static const uint32_t VR128SubClassMask[] = {
1096 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000002,
1097 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
1098};
1099
1100static const uint32_t VR256XSubClassMask[] = {
1101 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000c,
1102 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000030, // sub_ymm
1103};
1104
1105static const uint32_t VR256SubClassMask[] = {
1106 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008,
1107 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000020, // sub_ymm
1108};
1109
1110static const uint32_t VR512SubClassMask[] = {
1111 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000030,
1112};
1113
1114static const uint32_t VR512_0_15SubClassMask[] = {
1115 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000020,
1116};
1117
1118static const uint32_t TILESubClassMask[] = {
1119 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000040,
1120};
1121
1122static const uint16_t SuperRegIdxSeqs[] = {
1123 /* 0 */ 1, 0,
1124 /* 2 */ 1, 2, 0,
1125 /* 5 */ 4, 0,
1126 /* 7 */ 6, 0,
1127 /* 9 */ 7, 8, 0,
1128 /* 12 */ 9, 0,
1129 /* 14 */ 10, 0,
1130};
1131
1132static unsigned const GR8_NOREX2Superclasses[] = {
1133 X86::GR8RegClassID,
1134};
1135
1136static unsigned const GR8_NOREXSuperclasses[] = {
1137 X86::GR8RegClassID,
1138 X86::GR8_NOREX2RegClassID,
1139};
1140
1141static unsigned const GR8_ABCD_HSuperclasses[] = {
1142 X86::GR8RegClassID,
1143 X86::GR8_NOREX2RegClassID,
1144 X86::GR8_NOREXRegClassID,
1145};
1146
1147static unsigned const GR8_ABCD_LSuperclasses[] = {
1148 X86::GR8RegClassID,
1149 X86::GR8_NOREX2RegClassID,
1150 X86::GR8_NOREXRegClassID,
1151};
1152
1153static unsigned const GR16_NOREX2Superclasses[] = {
1154 X86::GR16RegClassID,
1155};
1156
1157static unsigned const GR16_NOREXSuperclasses[] = {
1158 X86::GR16RegClassID,
1159 X86::GR16_NOREX2RegClassID,
1160};
1161
1162static unsigned const VK1Superclasses[] = {
1163 X86::VK16RegClassID,
1164 X86::VK2RegClassID,
1165 X86::VK4RegClassID,
1166 X86::VK8RegClassID,
1167};
1168
1169static unsigned const VK16Superclasses[] = {
1170 X86::VK1RegClassID,
1171 X86::VK2RegClassID,
1172 X86::VK4RegClassID,
1173 X86::VK8RegClassID,
1174};
1175
1176static unsigned const VK2Superclasses[] = {
1177 X86::VK1RegClassID,
1178 X86::VK16RegClassID,
1179 X86::VK4RegClassID,
1180 X86::VK8RegClassID,
1181};
1182
1183static unsigned const VK4Superclasses[] = {
1184 X86::VK1RegClassID,
1185 X86::VK16RegClassID,
1186 X86::VK2RegClassID,
1187 X86::VK8RegClassID,
1188};
1189
1190static unsigned const VK8Superclasses[] = {
1191 X86::VK1RegClassID,
1192 X86::VK16RegClassID,
1193 X86::VK2RegClassID,
1194 X86::VK4RegClassID,
1195};
1196
1197static unsigned const VK16WMSuperclasses[] = {
1198 X86::VK1RegClassID,
1199 X86::VK16RegClassID,
1200 X86::VK2RegClassID,
1201 X86::VK4RegClassID,
1202 X86::VK8RegClassID,
1203 X86::VK1WMRegClassID,
1204 X86::VK2WMRegClassID,
1205 X86::VK4WMRegClassID,
1206 X86::VK8WMRegClassID,
1207};
1208
1209static unsigned const VK1WMSuperclasses[] = {
1210 X86::VK1RegClassID,
1211 X86::VK16RegClassID,
1212 X86::VK2RegClassID,
1213 X86::VK4RegClassID,
1214 X86::VK8RegClassID,
1215 X86::VK16WMRegClassID,
1216 X86::VK2WMRegClassID,
1217 X86::VK4WMRegClassID,
1218 X86::VK8WMRegClassID,
1219};
1220
1221static unsigned const VK2WMSuperclasses[] = {
1222 X86::VK1RegClassID,
1223 X86::VK16RegClassID,
1224 X86::VK2RegClassID,
1225 X86::VK4RegClassID,
1226 X86::VK8RegClassID,
1227 X86::VK16WMRegClassID,
1228 X86::VK1WMRegClassID,
1229 X86::VK4WMRegClassID,
1230 X86::VK8WMRegClassID,
1231};
1232
1233static unsigned const VK4WMSuperclasses[] = {
1234 X86::VK1RegClassID,
1235 X86::VK16RegClassID,
1236 X86::VK2RegClassID,
1237 X86::VK4RegClassID,
1238 X86::VK8RegClassID,
1239 X86::VK16WMRegClassID,
1240 X86::VK1WMRegClassID,
1241 X86::VK2WMRegClassID,
1242 X86::VK8WMRegClassID,
1243};
1244
1245static unsigned const VK8WMSuperclasses[] = {
1246 X86::VK1RegClassID,
1247 X86::VK16RegClassID,
1248 X86::VK2RegClassID,
1249 X86::VK4RegClassID,
1250 X86::VK8RegClassID,
1251 X86::VK16WMRegClassID,
1252 X86::VK1WMRegClassID,
1253 X86::VK2WMRegClassID,
1254 X86::VK4WMRegClassID,
1255};
1256
1257static unsigned const GR16_ABCDSuperclasses[] = {
1258 X86::GR16RegClassID,
1259 X86::GR16_NOREX2RegClassID,
1260 X86::GR16_NOREXRegClassID,
1261};
1262
1263static unsigned const FR16Superclasses[] = {
1264 X86::FR16XRegClassID,
1265};
1266
1267static unsigned const VK16PAIRSuperclasses[] = {
1268 X86::VK1PAIRRegClassID,
1269 X86::VK2PAIRRegClassID,
1270 X86::VK4PAIRRegClassID,
1271 X86::VK8PAIRRegClassID,
1272};
1273
1274static unsigned const VK1PAIRSuperclasses[] = {
1275 X86::VK16PAIRRegClassID,
1276 X86::VK2PAIRRegClassID,
1277 X86::VK4PAIRRegClassID,
1278 X86::VK8PAIRRegClassID,
1279};
1280
1281static unsigned const VK2PAIRSuperclasses[] = {
1282 X86::VK16PAIRRegClassID,
1283 X86::VK1PAIRRegClassID,
1284 X86::VK4PAIRRegClassID,
1285 X86::VK8PAIRRegClassID,
1286};
1287
1288static unsigned const VK4PAIRSuperclasses[] = {
1289 X86::VK16PAIRRegClassID,
1290 X86::VK1PAIRRegClassID,
1291 X86::VK2PAIRRegClassID,
1292 X86::VK8PAIRRegClassID,
1293};
1294
1295static unsigned const VK8PAIRSuperclasses[] = {
1296 X86::VK16PAIRRegClassID,
1297 X86::VK1PAIRRegClassID,
1298 X86::VK2PAIRRegClassID,
1299 X86::VK4PAIRRegClassID,
1300};
1301
1302static unsigned const VK1PAIR_with_sub_mask_0_in_VK1WMSuperclasses[] = {
1303 X86::VK16PAIRRegClassID,
1304 X86::VK1PAIRRegClassID,
1305 X86::VK2PAIRRegClassID,
1306 X86::VK4PAIRRegClassID,
1307 X86::VK8PAIRRegClassID,
1308};
1309
1310static unsigned const LOW32_ADDR_ACCESSSuperclasses[] = {
1311 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1312};
1313
1314static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses[] = {
1315 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1316};
1317
1318static unsigned const FR32XSuperclasses[] = {
1319 X86::FR16XRegClassID,
1320};
1321
1322static unsigned const GR32Superclasses[] = {
1323 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1324 X86::LOW32_ADDR_ACCESSRegClassID,
1325 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1326};
1327
1328static unsigned const GR32_NOSPSuperclasses[] = {
1329 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1330 X86::LOW32_ADDR_ACCESSRegClassID,
1331 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1332 X86::GR32RegClassID,
1333};
1334
1335static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Superclasses[] = {
1336 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1337 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1338};
1339
1340static unsigned const FR32Superclasses[] = {
1341 X86::FR16XRegClassID,
1342 X86::FR16RegClassID,
1343 X86::FR32XRegClassID,
1344};
1345
1346static unsigned const GR32_NOREX2Superclasses[] = {
1347 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1348 X86::LOW32_ADDR_ACCESSRegClassID,
1349 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1350 X86::GR32RegClassID,
1351 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1352};
1353
1354static unsigned const GR32_NOREX2_NOSPSuperclasses[] = {
1355 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1356 X86::LOW32_ADDR_ACCESSRegClassID,
1357 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1358 X86::GR32RegClassID,
1359 X86::GR32_NOSPRegClassID,
1360 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1361 X86::GR32_NOREX2RegClassID,
1362};
1363
1364static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
1365 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1366 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1367 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1368};
1369
1370static unsigned const GR32_NOREXSuperclasses[] = {
1371 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1372 X86::LOW32_ADDR_ACCESSRegClassID,
1373 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1374 X86::GR32RegClassID,
1375 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1376 X86::GR32_NOREX2RegClassID,
1377 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1378};
1379
1380static unsigned const VK32Superclasses[] = {
1381 X86::VK1RegClassID,
1382 X86::VK16RegClassID,
1383 X86::VK2RegClassID,
1384 X86::VK4RegClassID,
1385 X86::VK8RegClassID,
1386};
1387
1388static unsigned const GR32_NOREX_NOSPSuperclasses[] = {
1389 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1390 X86::LOW32_ADDR_ACCESSRegClassID,
1391 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1392 X86::GR32RegClassID,
1393 X86::GR32_NOSPRegClassID,
1394 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1395 X86::GR32_NOREX2RegClassID,
1396 X86::GR32_NOREX2_NOSPRegClassID,
1397 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1398 X86::GR32_NOREXRegClassID,
1399};
1400
1401static unsigned const VK32WMSuperclasses[] = {
1402 X86::VK1RegClassID,
1403 X86::VK16RegClassID,
1404 X86::VK2RegClassID,
1405 X86::VK4RegClassID,
1406 X86::VK8RegClassID,
1407 X86::VK16WMRegClassID,
1408 X86::VK1WMRegClassID,
1409 X86::VK2WMRegClassID,
1410 X86::VK4WMRegClassID,
1411 X86::VK8WMRegClassID,
1412 X86::VK32RegClassID,
1413};
1414
1415static unsigned const GR32_ABCDSuperclasses[] = {
1416 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1417 X86::LOW32_ADDR_ACCESSRegClassID,
1418 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1419 X86::GR32RegClassID,
1420 X86::GR32_NOSPRegClassID,
1421 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1422 X86::GR32_NOREX2RegClassID,
1423 X86::GR32_NOREX2_NOSPRegClassID,
1424 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1425 X86::GR32_NOREXRegClassID,
1426 X86::GR32_NOREX_NOSPRegClassID,
1427};
1428
1429static unsigned const GR32_TCSuperclasses[] = {
1430 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1431 X86::LOW32_ADDR_ACCESSRegClassID,
1432 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1433 X86::GR32RegClassID,
1434 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1435 X86::GR32_NOREX2RegClassID,
1436 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1437 X86::GR32_NOREXRegClassID,
1438};
1439
1440static unsigned const GR32_ABCD_and_GR32_TCSuperclasses[] = {
1441 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1442 X86::LOW32_ADDR_ACCESSRegClassID,
1443 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1444 X86::GR32RegClassID,
1445 X86::GR32_NOSPRegClassID,
1446 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1447 X86::GR32_NOREX2RegClassID,
1448 X86::GR32_NOREX2_NOSPRegClassID,
1449 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1450 X86::GR32_NOREXRegClassID,
1451 X86::GR32_NOREX_NOSPRegClassID,
1452 X86::GR32_ABCDRegClassID,
1453 X86::GR32_TCRegClassID,
1454};
1455
1456static unsigned const GR32_ADSuperclasses[] = {
1457 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1458 X86::LOW32_ADDR_ACCESSRegClassID,
1459 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1460 X86::GR32RegClassID,
1461 X86::GR32_NOSPRegClassID,
1462 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1463 X86::GR32_NOREX2RegClassID,
1464 X86::GR32_NOREX2_NOSPRegClassID,
1465 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1466 X86::GR32_NOREXRegClassID,
1467 X86::GR32_NOREX_NOSPRegClassID,
1468 X86::GR32_ABCDRegClassID,
1469 X86::GR32_TCRegClassID,
1470 X86::GR32_ABCD_and_GR32_TCRegClassID,
1471};
1472
1473static unsigned const GR32_ArgRefSuperclasses[] = {
1474 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1475 X86::LOW32_ADDR_ACCESSRegClassID,
1476 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1477 X86::GR32RegClassID,
1478 X86::GR32_NOSPRegClassID,
1479 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1480 X86::GR32_NOREX2RegClassID,
1481 X86::GR32_NOREX2_NOSPRegClassID,
1482 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1483 X86::GR32_NOREXRegClassID,
1484 X86::GR32_NOREX_NOSPRegClassID,
1485 X86::GR32_ABCDRegClassID,
1486 X86::GR32_TCRegClassID,
1487 X86::GR32_ABCD_and_GR32_TCRegClassID,
1488};
1489
1490static unsigned const GR32_BPSPSuperclasses[] = {
1491 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1492 X86::LOW32_ADDR_ACCESSRegClassID,
1493 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1494 X86::GR32RegClassID,
1495 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1496 X86::GR32_NOREX2RegClassID,
1497 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1498 X86::GR32_NOREXRegClassID,
1499};
1500
1501static unsigned const GR32_BSISuperclasses[] = {
1502 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1503 X86::LOW32_ADDR_ACCESSRegClassID,
1504 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1505 X86::GR32RegClassID,
1506 X86::GR32_NOSPRegClassID,
1507 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1508 X86::GR32_NOREX2RegClassID,
1509 X86::GR32_NOREX2_NOSPRegClassID,
1510 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1511 X86::GR32_NOREXRegClassID,
1512 X86::GR32_NOREX_NOSPRegClassID,
1513};
1514
1515static unsigned const GR32_CBSuperclasses[] = {
1516 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1517 X86::LOW32_ADDR_ACCESSRegClassID,
1518 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1519 X86::GR32RegClassID,
1520 X86::GR32_NOSPRegClassID,
1521 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1522 X86::GR32_NOREX2RegClassID,
1523 X86::GR32_NOREX2_NOSPRegClassID,
1524 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1525 X86::GR32_NOREXRegClassID,
1526 X86::GR32_NOREX_NOSPRegClassID,
1527 X86::GR32_ABCDRegClassID,
1528};
1529
1530static unsigned const GR32_DCSuperclasses[] = {
1531 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1532 X86::LOW32_ADDR_ACCESSRegClassID,
1533 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1534 X86::GR32RegClassID,
1535 X86::GR32_NOSPRegClassID,
1536 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1537 X86::GR32_NOREX2RegClassID,
1538 X86::GR32_NOREX2_NOSPRegClassID,
1539 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1540 X86::GR32_NOREXRegClassID,
1541 X86::GR32_NOREX_NOSPRegClassID,
1542 X86::GR32_ABCDRegClassID,
1543 X86::GR32_TCRegClassID,
1544 X86::GR32_ABCD_and_GR32_TCRegClassID,
1545 X86::GR32_ArgRefRegClassID,
1546};
1547
1548static unsigned const GR32_DIBPSuperclasses[] = {
1549 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1550 X86::LOW32_ADDR_ACCESSRegClassID,
1551 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1552 X86::GR32RegClassID,
1553 X86::GR32_NOSPRegClassID,
1554 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1555 X86::GR32_NOREX2RegClassID,
1556 X86::GR32_NOREX2_NOSPRegClassID,
1557 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1558 X86::GR32_NOREXRegClassID,
1559 X86::GR32_NOREX_NOSPRegClassID,
1560};
1561
1562static unsigned const GR32_SIDISuperclasses[] = {
1563 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1564 X86::LOW32_ADDR_ACCESSRegClassID,
1565 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1566 X86::GR32RegClassID,
1567 X86::GR32_NOSPRegClassID,
1568 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1569 X86::GR32_NOREX2RegClassID,
1570 X86::GR32_NOREX2_NOSPRegClassID,
1571 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1572 X86::GR32_NOREXRegClassID,
1573 X86::GR32_NOREX_NOSPRegClassID,
1574};
1575
1576static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses[] = {
1577 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1578};
1579
1580static unsigned const GR32_ABCD_and_GR32_BSISuperclasses[] = {
1581 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1582 X86::LOW32_ADDR_ACCESSRegClassID,
1583 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1584 X86::GR32RegClassID,
1585 X86::GR32_NOSPRegClassID,
1586 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1587 X86::GR32_NOREX2RegClassID,
1588 X86::GR32_NOREX2_NOSPRegClassID,
1589 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1590 X86::GR32_NOREXRegClassID,
1591 X86::GR32_NOREX_NOSPRegClassID,
1592 X86::GR32_ABCDRegClassID,
1593 X86::GR32_BSIRegClassID,
1594 X86::GR32_CBRegClassID,
1595};
1596
1597static unsigned const GR32_AD_and_GR32_ArgRefSuperclasses[] = {
1598 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1599 X86::LOW32_ADDR_ACCESSRegClassID,
1600 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1601 X86::GR32RegClassID,
1602 X86::GR32_NOSPRegClassID,
1603 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1604 X86::GR32_NOREX2RegClassID,
1605 X86::GR32_NOREX2_NOSPRegClassID,
1606 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1607 X86::GR32_NOREXRegClassID,
1608 X86::GR32_NOREX_NOSPRegClassID,
1609 X86::GR32_ABCDRegClassID,
1610 X86::GR32_TCRegClassID,
1611 X86::GR32_ABCD_and_GR32_TCRegClassID,
1612 X86::GR32_ADRegClassID,
1613 X86::GR32_ArgRefRegClassID,
1614 X86::GR32_DCRegClassID,
1615};
1616
1617static unsigned const GR32_ArgRef_and_GR32_CBSuperclasses[] = {
1618 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1619 X86::LOW32_ADDR_ACCESSRegClassID,
1620 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1621 X86::GR32RegClassID,
1622 X86::GR32_NOSPRegClassID,
1623 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1624 X86::GR32_NOREX2RegClassID,
1625 X86::GR32_NOREX2_NOSPRegClassID,
1626 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1627 X86::GR32_NOREXRegClassID,
1628 X86::GR32_NOREX_NOSPRegClassID,
1629 X86::GR32_ABCDRegClassID,
1630 X86::GR32_TCRegClassID,
1631 X86::GR32_ABCD_and_GR32_TCRegClassID,
1632 X86::GR32_ArgRefRegClassID,
1633 X86::GR32_CBRegClassID,
1634 X86::GR32_DCRegClassID,
1635};
1636
1637static unsigned const GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
1638 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1639 X86::LOW32_ADDR_ACCESSRegClassID,
1640 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1641 X86::GR32RegClassID,
1642 X86::GR32_NOSPRegClassID,
1643 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1644 X86::GR32_NOREX2RegClassID,
1645 X86::GR32_NOREX2_NOSPRegClassID,
1646 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1647 X86::GR32_NOREXRegClassID,
1648 X86::GR32_NOREX_NOSPRegClassID,
1649 X86::GR32_BPSPRegClassID,
1650 X86::GR32_DIBPRegClassID,
1651};
1652
1653static unsigned const GR32_BPSP_and_GR32_TCSuperclasses[] = {
1654 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1655 X86::LOW32_ADDR_ACCESSRegClassID,
1656 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1657 X86::GR32RegClassID,
1658 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1659 X86::GR32_NOREX2RegClassID,
1660 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1661 X86::GR32_NOREXRegClassID,
1662 X86::GR32_TCRegClassID,
1663 X86::GR32_BPSPRegClassID,
1664};
1665
1666static unsigned const GR32_BSI_and_GR32_SIDISuperclasses[] = {
1667 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1668 X86::LOW32_ADDR_ACCESSRegClassID,
1669 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1670 X86::GR32RegClassID,
1671 X86::GR32_NOSPRegClassID,
1672 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1673 X86::GR32_NOREX2RegClassID,
1674 X86::GR32_NOREX2_NOSPRegClassID,
1675 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1676 X86::GR32_NOREXRegClassID,
1677 X86::GR32_NOREX_NOSPRegClassID,
1678 X86::GR32_BSIRegClassID,
1679 X86::GR32_SIDIRegClassID,
1680};
1681
1682static unsigned const GR32_DIBP_and_GR32_SIDISuperclasses[] = {
1683 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1684 X86::LOW32_ADDR_ACCESSRegClassID,
1685 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1686 X86::GR32RegClassID,
1687 X86::GR32_NOSPRegClassID,
1688 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1689 X86::GR32_NOREX2RegClassID,
1690 X86::GR32_NOREX2_NOSPRegClassID,
1691 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1692 X86::GR32_NOREXRegClassID,
1693 X86::GR32_NOREX_NOSPRegClassID,
1694 X86::GR32_DIBPRegClassID,
1695 X86::GR32_SIDIRegClassID,
1696};
1697
1698static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses[] = {
1699 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1700 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1701 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1702 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1703 X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
1704};
1705
1706static unsigned const LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses[] = {
1707 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1708 X86::LOW32_ADDR_ACCESSRegClassID,
1709 X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
1710};
1711
1712static unsigned const RFP64Superclasses[] = {
1713 X86::RFP32RegClassID,
1714};
1715
1716static unsigned const FR64XSuperclasses[] = {
1717 X86::FR16XRegClassID,
1718 X86::FR32XRegClassID,
1719};
1720
1721static unsigned const GR64_with_sub_8bitSuperclasses[] = {
1722 X86::GR64RegClassID,
1723};
1724
1725static unsigned const GR64_NOSPSuperclasses[] = {
1726 X86::GR64RegClassID,
1727 X86::GR64_with_sub_8bitRegClassID,
1728};
1729
1730static unsigned const GR64_NOREX2Superclasses[] = {
1731 X86::GR64RegClassID,
1732};
1733
1734static unsigned const FR64Superclasses[] = {
1735 X86::FR16XRegClassID,
1736 X86::FR16RegClassID,
1737 X86::FR32XRegClassID,
1738 X86::FR32RegClassID,
1739 X86::FR64XRegClassID,
1740};
1741
1742static unsigned const GR64_with_sub_16bit_in_GR16_NOREX2Superclasses[] = {
1743 X86::GR64RegClassID,
1744 X86::GR64_with_sub_8bitRegClassID,
1745 X86::GR64_NOREX2RegClassID,
1746};
1747
1748static unsigned const GR64_NOREX2_NOSPSuperclasses[] = {
1749 X86::GR64RegClassID,
1750 X86::GR64_with_sub_8bitRegClassID,
1751 X86::GR64_NOSPRegClassID,
1752 X86::GR64_NOREX2RegClassID,
1753 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1754};
1755
1756static unsigned const GR64PLTSafeSuperclasses[] = {
1757 X86::GR64RegClassID,
1758 X86::GR64_with_sub_8bitRegClassID,
1759 X86::GR64_NOSPRegClassID,
1760 X86::GR64_NOREX2RegClassID,
1761 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1762 X86::GR64_NOREX2_NOSPRegClassID,
1763};
1764
1765static unsigned const GR64_TCSuperclasses[] = {
1766 X86::GR64RegClassID,
1767 X86::GR64_NOREX2RegClassID,
1768};
1769
1770static unsigned const GR64_NOREXSuperclasses[] = {
1771 X86::GR64RegClassID,
1772 X86::GR64_NOREX2RegClassID,
1773};
1774
1775static unsigned const GR64_TCW64Superclasses[] = {
1776 X86::GR64RegClassID,
1777 X86::GR64_NOREX2RegClassID,
1778};
1779
1780static unsigned const GR64_TC_with_sub_8bitSuperclasses[] = {
1781 X86::GR64RegClassID,
1782 X86::GR64_with_sub_8bitRegClassID,
1783 X86::GR64_NOREX2RegClassID,
1784 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1785 X86::GR64_TCRegClassID,
1786};
1787
1788static unsigned const GR64_NOREX2_NOSP_and_GR64_TCSuperclasses[] = {
1789 X86::GR64RegClassID,
1790 X86::GR64_with_sub_8bitRegClassID,
1791 X86::GR64_NOSPRegClassID,
1792 X86::GR64_NOREX2RegClassID,
1793 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1794 X86::GR64_NOREX2_NOSPRegClassID,
1795 X86::GR64_TCRegClassID,
1796 X86::GR64_TC_with_sub_8bitRegClassID,
1797};
1798
1799static unsigned const GR64_TCW64_with_sub_8bitSuperclasses[] = {
1800 X86::GR64RegClassID,
1801 X86::GR64_with_sub_8bitRegClassID,
1802 X86::GR64_NOREX2RegClassID,
1803 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1804 X86::GR64_TCW64RegClassID,
1805};
1806
1807static unsigned const GR64_TC_and_GR64_TCW64Superclasses[] = {
1808 X86::GR64RegClassID,
1809 X86::GR64_NOREX2RegClassID,
1810 X86::GR64_TCRegClassID,
1811 X86::GR64_TCW64RegClassID,
1812};
1813
1814static unsigned const GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
1815 X86::GR64RegClassID,
1816 X86::GR64_with_sub_8bitRegClassID,
1817 X86::GR64_NOREX2RegClassID,
1818 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1819 X86::GR64_NOREXRegClassID,
1820};
1821
1822static unsigned const VK64Superclasses[] = {
1823 X86::VK1RegClassID,
1824 X86::VK16RegClassID,
1825 X86::VK2RegClassID,
1826 X86::VK4RegClassID,
1827 X86::VK8RegClassID,
1828 X86::VK32RegClassID,
1829};
1830
1831static unsigned const GR64PLTSafe_and_GR64_TCSuperclasses[] = {
1832 X86::GR64RegClassID,
1833 X86::GR64_with_sub_8bitRegClassID,
1834 X86::GR64_NOSPRegClassID,
1835 X86::GR64_NOREX2RegClassID,
1836 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1837 X86::GR64_NOREX2_NOSPRegClassID,
1838 X86::GR64PLTSafeRegClassID,
1839 X86::GR64_TCRegClassID,
1840 X86::GR64_TC_with_sub_8bitRegClassID,
1841 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
1842};
1843
1844static unsigned const GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses[] = {
1845 X86::GR64RegClassID,
1846 X86::GR64_with_sub_8bitRegClassID,
1847 X86::GR64_NOSPRegClassID,
1848 X86::GR64_NOREX2RegClassID,
1849 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1850 X86::GR64_NOREX2_NOSPRegClassID,
1851 X86::GR64_TCW64RegClassID,
1852 X86::GR64_TCW64_with_sub_8bitRegClassID,
1853};
1854
1855static unsigned const GR64_NOREX_NOSPSuperclasses[] = {
1856 X86::GR64RegClassID,
1857 X86::GR64_with_sub_8bitRegClassID,
1858 X86::GR64_NOSPRegClassID,
1859 X86::GR64_NOREX2RegClassID,
1860 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1861 X86::GR64_NOREX2_NOSPRegClassID,
1862 X86::GR64PLTSafeRegClassID,
1863 X86::GR64_NOREXRegClassID,
1864 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
1865};
1866
1867static unsigned const GR64_NOREX_and_GR64_TCSuperclasses[] = {
1868 X86::GR64RegClassID,
1869 X86::GR64_NOREX2RegClassID,
1870 X86::GR64_TCRegClassID,
1871 X86::GR64_NOREXRegClassID,
1872};
1873
1874static unsigned const GR64_TCW64_and_GR64_TC_with_sub_8bitSuperclasses[] = {
1875 X86::GR64RegClassID,
1876 X86::GR64_with_sub_8bitRegClassID,
1877 X86::GR64_NOREX2RegClassID,
1878 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1879 X86::GR64_TCRegClassID,
1880 X86::GR64_TCW64RegClassID,
1881 X86::GR64_TC_with_sub_8bitRegClassID,
1882 X86::GR64_TCW64_with_sub_8bitRegClassID,
1883 X86::GR64_TC_and_GR64_TCW64RegClassID,
1884};
1885
1886static unsigned const VK64WMSuperclasses[] = {
1887 X86::VK1RegClassID,
1888 X86::VK16RegClassID,
1889 X86::VK2RegClassID,
1890 X86::VK4RegClassID,
1891 X86::VK8RegClassID,
1892 X86::VK16WMRegClassID,
1893 X86::VK1WMRegClassID,
1894 X86::VK2WMRegClassID,
1895 X86::VK4WMRegClassID,
1896 X86::VK8WMRegClassID,
1897 X86::VK32RegClassID,
1898 X86::VK32WMRegClassID,
1899 X86::VK64RegClassID,
1900};
1901
1902static unsigned const GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses[] = {
1903 X86::GR64RegClassID,
1904 X86::GR64_with_sub_8bitRegClassID,
1905 X86::GR64_NOSPRegClassID,
1906 X86::GR64_NOREX2RegClassID,
1907 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1908 X86::GR64_NOREX2_NOSPRegClassID,
1909 X86::GR64_TCRegClassID,
1910 X86::GR64_TCW64RegClassID,
1911 X86::GR64_TC_with_sub_8bitRegClassID,
1912 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
1913 X86::GR64_TCW64_with_sub_8bitRegClassID,
1914 X86::GR64_TC_and_GR64_TCW64RegClassID,
1915 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
1916 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
1917};
1918
1919static unsigned const GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
1920 X86::GR64RegClassID,
1921 X86::GR64_with_sub_8bitRegClassID,
1922 X86::GR64_NOREX2RegClassID,
1923 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1924 X86::GR64_TCRegClassID,
1925 X86::GR64_NOREXRegClassID,
1926 X86::GR64_TC_with_sub_8bitRegClassID,
1927 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
1928 X86::GR64_NOREX_and_GR64_TCRegClassID,
1929};
1930
1931static unsigned const GR64PLTSafe_and_GR64_TCW64Superclasses[] = {
1932 X86::GR64RegClassID,
1933 X86::GR64_with_sub_8bitRegClassID,
1934 X86::GR64_NOSPRegClassID,
1935 X86::GR64_NOREX2RegClassID,
1936 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1937 X86::GR64_NOREX2_NOSPRegClassID,
1938 X86::GR64PLTSafeRegClassID,
1939 X86::GR64_TCRegClassID,
1940 X86::GR64_TCW64RegClassID,
1941 X86::GR64_TC_with_sub_8bitRegClassID,
1942 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
1943 X86::GR64_TCW64_with_sub_8bitRegClassID,
1944 X86::GR64_TC_and_GR64_TCW64RegClassID,
1945 X86::GR64PLTSafe_and_GR64_TCRegClassID,
1946 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
1947 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
1948 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
1949};
1950
1951static unsigned const GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSuperclasses[] = {
1952 X86::GR64RegClassID,
1953 X86::GR64_with_sub_8bitRegClassID,
1954 X86::GR64_NOSPRegClassID,
1955 X86::GR64_NOREX2RegClassID,
1956 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1957 X86::GR64_NOREX2_NOSPRegClassID,
1958 X86::GR64PLTSafeRegClassID,
1959 X86::GR64_TCRegClassID,
1960 X86::GR64_NOREXRegClassID,
1961 X86::GR64_TC_with_sub_8bitRegClassID,
1962 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
1963 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
1964 X86::GR64PLTSafe_and_GR64_TCRegClassID,
1965 X86::GR64_NOREX_NOSPRegClassID,
1966 X86::GR64_NOREX_and_GR64_TCRegClassID,
1967 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
1968};
1969
1970static unsigned const GR64_NOREX_and_GR64_TCW64Superclasses[] = {
1971 X86::GR64RegClassID,
1972 X86::GR64_NOREX2RegClassID,
1973 X86::GR64_TCRegClassID,
1974 X86::GR64_NOREXRegClassID,
1975 X86::GR64_TCW64RegClassID,
1976 X86::GR64_TC_and_GR64_TCW64RegClassID,
1977 X86::GR64_NOREX_and_GR64_TCRegClassID,
1978};
1979
1980static unsigned const GR64_ABCDSuperclasses[] = {
1981 X86::GR64RegClassID,
1982 X86::GR64_with_sub_8bitRegClassID,
1983 X86::GR64_NOSPRegClassID,
1984 X86::GR64_NOREX2RegClassID,
1985 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1986 X86::GR64_NOREX2_NOSPRegClassID,
1987 X86::GR64PLTSafeRegClassID,
1988 X86::GR64_NOREXRegClassID,
1989 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
1990 X86::GR64_NOREX_NOSPRegClassID,
1991};
1992
1993static unsigned const GR64_with_sub_32bit_in_GR32_TCSuperclasses[] = {
1994 X86::GR64RegClassID,
1995 X86::GR64_with_sub_8bitRegClassID,
1996 X86::GR64_NOREX2RegClassID,
1997 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1998 X86::GR64_TCRegClassID,
1999 X86::GR64_NOREXRegClassID,
2000 X86::GR64_TCW64RegClassID,
2001 X86::GR64_TC_with_sub_8bitRegClassID,
2002 X86::GR64_TCW64_with_sub_8bitRegClassID,
2003 X86::GR64_TC_and_GR64_TCW64RegClassID,
2004 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2005 X86::GR64_NOREX_and_GR64_TCRegClassID,
2006 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2007 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2008 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2009};
2010
2011static unsigned const GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSuperclasses[] = {
2012 X86::GR64RegClassID,
2013 X86::GR64_with_sub_8bitRegClassID,
2014 X86::GR64_NOSPRegClassID,
2015 X86::GR64_NOREX2RegClassID,
2016 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2017 X86::GR64_NOREX2_NOSPRegClassID,
2018 X86::GR64PLTSafeRegClassID,
2019 X86::GR64_TCRegClassID,
2020 X86::GR64_NOREXRegClassID,
2021 X86::GR64_TCW64RegClassID,
2022 X86::GR64_TC_with_sub_8bitRegClassID,
2023 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2024 X86::GR64_TCW64_with_sub_8bitRegClassID,
2025 X86::GR64_TC_and_GR64_TCW64RegClassID,
2026 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2027 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2028 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2029 X86::GR64_NOREX_NOSPRegClassID,
2030 X86::GR64_NOREX_and_GR64_TCRegClassID,
2031 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2032 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2033 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2034 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
2035 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2036 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2037 X86::GR64_ABCDRegClassID,
2038 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
2039};
2040
2041static unsigned const GR64_ADSuperclasses[] = {
2042 X86::GR64RegClassID,
2043 X86::GR64_with_sub_8bitRegClassID,
2044 X86::GR64_NOSPRegClassID,
2045 X86::GR64_NOREX2RegClassID,
2046 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2047 X86::GR64_NOREX2_NOSPRegClassID,
2048 X86::GR64PLTSafeRegClassID,
2049 X86::GR64_TCRegClassID,
2050 X86::GR64_NOREXRegClassID,
2051 X86::GR64_TCW64RegClassID,
2052 X86::GR64_TC_with_sub_8bitRegClassID,
2053 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2054 X86::GR64_TCW64_with_sub_8bitRegClassID,
2055 X86::GR64_TC_and_GR64_TCW64RegClassID,
2056 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2057 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2058 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2059 X86::GR64_NOREX_NOSPRegClassID,
2060 X86::GR64_NOREX_and_GR64_TCRegClassID,
2061 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2062 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2063 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2064 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
2065 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2066 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2067 X86::GR64_ABCDRegClassID,
2068 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
2069 X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
2070};
2071
2072static unsigned const GR64_ArgRefSuperclasses[] = {
2073 X86::GR64RegClassID,
2074 X86::GR64_with_sub_8bitRegClassID,
2075 X86::GR64_NOSPRegClassID,
2076 X86::GR64_NOREX2RegClassID,
2077 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2078 X86::GR64_NOREX2_NOSPRegClassID,
2079 X86::GR64_TCW64RegClassID,
2080 X86::GR64_TCW64_with_sub_8bitRegClassID,
2081 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2082};
2083
2084static unsigned const GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses[] = {
2085 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
2086 X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
2087 X86::GR64RegClassID,
2088 X86::GR64_NOREX2RegClassID,
2089 X86::GR64_NOREXRegClassID,
2090};
2091
2092static unsigned const GR64_with_sub_32bit_in_GR32_ArgRefSuperclasses[] = {
2093 X86::GR64RegClassID,
2094 X86::GR64_with_sub_8bitRegClassID,
2095 X86::GR64_NOSPRegClassID,
2096 X86::GR64_NOREX2RegClassID,
2097 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2098 X86::GR64_NOREX2_NOSPRegClassID,
2099 X86::GR64PLTSafeRegClassID,
2100 X86::GR64_TCRegClassID,
2101 X86::GR64_NOREXRegClassID,
2102 X86::GR64_TCW64RegClassID,
2103 X86::GR64_TC_with_sub_8bitRegClassID,
2104 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2105 X86::GR64_TCW64_with_sub_8bitRegClassID,
2106 X86::GR64_TC_and_GR64_TCW64RegClassID,
2107 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2108 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2109 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2110 X86::GR64_NOREX_NOSPRegClassID,
2111 X86::GR64_NOREX_and_GR64_TCRegClassID,
2112 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2113 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2114 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2115 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
2116 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2117 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2118 X86::GR64_ABCDRegClassID,
2119 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
2120 X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
2121};
2122
2123static unsigned const GR64_with_sub_32bit_in_GR32_BPSPSuperclasses[] = {
2124 X86::GR64RegClassID,
2125 X86::GR64_with_sub_8bitRegClassID,
2126 X86::GR64_NOREX2RegClassID,
2127 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2128 X86::GR64_NOREXRegClassID,
2129 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2130};
2131
2132static unsigned const GR64_with_sub_32bit_in_GR32_BSISuperclasses[] = {
2133 X86::GR64RegClassID,
2134 X86::GR64_with_sub_8bitRegClassID,
2135 X86::GR64_NOSPRegClassID,
2136 X86::GR64_NOREX2RegClassID,
2137 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2138 X86::GR64_NOREX2_NOSPRegClassID,
2139 X86::GR64PLTSafeRegClassID,
2140 X86::GR64_NOREXRegClassID,
2141 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2142 X86::GR64_NOREX_NOSPRegClassID,
2143};
2144
2145static unsigned const GR64_with_sub_32bit_in_GR32_CBSuperclasses[] = {
2146 X86::GR64RegClassID,
2147 X86::GR64_with_sub_8bitRegClassID,
2148 X86::GR64_NOSPRegClassID,
2149 X86::GR64_NOREX2RegClassID,
2150 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2151 X86::GR64_NOREX2_NOSPRegClassID,
2152 X86::GR64PLTSafeRegClassID,
2153 X86::GR64_NOREXRegClassID,
2154 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2155 X86::GR64_NOREX_NOSPRegClassID,
2156 X86::GR64_ABCDRegClassID,
2157};
2158
2159static unsigned const GR64_with_sub_32bit_in_GR32_DIBPSuperclasses[] = {
2160 X86::GR64RegClassID,
2161 X86::GR64_with_sub_8bitRegClassID,
2162 X86::GR64_NOSPRegClassID,
2163 X86::GR64_NOREX2RegClassID,
2164 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2165 X86::GR64_NOREX2_NOSPRegClassID,
2166 X86::GR64PLTSafeRegClassID,
2167 X86::GR64_NOREXRegClassID,
2168 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2169 X86::GR64_NOREX_NOSPRegClassID,
2170};
2171
2172static unsigned const GR64_with_sub_32bit_in_GR32_SIDISuperclasses[] = {
2173 X86::GR64RegClassID,
2174 X86::GR64_with_sub_8bitRegClassID,
2175 X86::GR64_NOSPRegClassID,
2176 X86::GR64_NOREX2RegClassID,
2177 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2178 X86::GR64_NOREX2_NOSPRegClassID,
2179 X86::GR64PLTSafeRegClassID,
2180 X86::GR64_TCRegClassID,
2181 X86::GR64_NOREXRegClassID,
2182 X86::GR64_TC_with_sub_8bitRegClassID,
2183 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2184 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2185 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2186 X86::GR64_NOREX_NOSPRegClassID,
2187 X86::GR64_NOREX_and_GR64_TCRegClassID,
2188 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2189 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2190};
2191
2192static unsigned const GR64_ASuperclasses[] = {
2193 X86::GR64RegClassID,
2194 X86::GR64_with_sub_8bitRegClassID,
2195 X86::GR64_NOSPRegClassID,
2196 X86::GR64_NOREX2RegClassID,
2197 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2198 X86::GR64_NOREX2_NOSPRegClassID,
2199 X86::GR64PLTSafeRegClassID,
2200 X86::GR64_TCRegClassID,
2201 X86::GR64_NOREXRegClassID,
2202 X86::GR64_TCW64RegClassID,
2203 X86::GR64_TC_with_sub_8bitRegClassID,
2204 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2205 X86::GR64_TCW64_with_sub_8bitRegClassID,
2206 X86::GR64_TC_and_GR64_TCW64RegClassID,
2207 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2208 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2209 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2210 X86::GR64_NOREX_NOSPRegClassID,
2211 X86::GR64_NOREX_and_GR64_TCRegClassID,
2212 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2213 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2214 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2215 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
2216 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2217 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2218 X86::GR64_ABCDRegClassID,
2219 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
2220 X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
2221 X86::GR64_ADRegClassID,
2222};
2223
2224static unsigned const GR64_ArgRef_and_GR64_TCSuperclasses[] = {
2225 X86::GR64RegClassID,
2226 X86::GR64_with_sub_8bitRegClassID,
2227 X86::GR64_NOSPRegClassID,
2228 X86::GR64_NOREX2RegClassID,
2229 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2230 X86::GR64_NOREX2_NOSPRegClassID,
2231 X86::GR64_TCRegClassID,
2232 X86::GR64_TCW64RegClassID,
2233 X86::GR64_TC_with_sub_8bitRegClassID,
2234 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2235 X86::GR64_TCW64_with_sub_8bitRegClassID,
2236 X86::GR64_TC_and_GR64_TCW64RegClassID,
2237 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2238 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2239 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2240 X86::GR64_ArgRefRegClassID,
2241};
2242
2243static unsigned const GR64_and_LOW32_ADDR_ACCESSSuperclasses[] = {
2244 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
2245 X86::LOW32_ADDR_ACCESSRegClassID,
2246 X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
2247 X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClassID,
2248 X86::GR64RegClassID,
2249 X86::GR64_NOREX2RegClassID,
2250 X86::GR64_TCRegClassID,
2251 X86::GR64_NOREXRegClassID,
2252 X86::GR64_TCW64RegClassID,
2253 X86::GR64_TC_and_GR64_TCW64RegClassID,
2254 X86::GR64_NOREX_and_GR64_TCRegClassID,
2255 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2256 X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID,
2257};
2258
2259static unsigned const GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISuperclasses[] = {
2260 X86::GR64RegClassID,
2261 X86::GR64_with_sub_8bitRegClassID,
2262 X86::GR64_NOSPRegClassID,
2263 X86::GR64_NOREX2RegClassID,
2264 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2265 X86::GR64_NOREX2_NOSPRegClassID,
2266 X86::GR64PLTSafeRegClassID,
2267 X86::GR64_NOREXRegClassID,
2268 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2269 X86::GR64_NOREX_NOSPRegClassID,
2270 X86::GR64_ABCDRegClassID,
2271 X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID,
2272 X86::GR64_with_sub_32bit_in_GR32_CBRegClassID,
2273};
2274
2275static unsigned const GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSuperclasses[] = {
2276 X86::GR64RegClassID,
2277 X86::GR64_with_sub_8bitRegClassID,
2278 X86::GR64_NOSPRegClassID,
2279 X86::GR64_NOREX2RegClassID,
2280 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2281 X86::GR64_NOREX2_NOSPRegClassID,
2282 X86::GR64PLTSafeRegClassID,
2283 X86::GR64_TCRegClassID,
2284 X86::GR64_NOREXRegClassID,
2285 X86::GR64_TCW64RegClassID,
2286 X86::GR64_TC_with_sub_8bitRegClassID,
2287 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2288 X86::GR64_TCW64_with_sub_8bitRegClassID,
2289 X86::GR64_TC_and_GR64_TCW64RegClassID,
2290 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2291 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2292 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2293 X86::GR64_NOREX_NOSPRegClassID,
2294 X86::GR64_NOREX_and_GR64_TCRegClassID,
2295 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2296 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2297 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2298 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
2299 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2300 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2301 X86::GR64_ABCDRegClassID,
2302 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
2303 X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
2304 X86::GR64_ADRegClassID,
2305 X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID,
2306};
2307
2308static unsigned const GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSuperclasses[] = {
2309 X86::GR64RegClassID,
2310 X86::GR64_with_sub_8bitRegClassID,
2311 X86::GR64_NOSPRegClassID,
2312 X86::GR64_NOREX2RegClassID,
2313 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2314 X86::GR64_NOREX2_NOSPRegClassID,
2315 X86::GR64PLTSafeRegClassID,
2316 X86::GR64_TCRegClassID,
2317 X86::GR64_NOREXRegClassID,
2318 X86::GR64_TCW64RegClassID,
2319 X86::GR64_TC_with_sub_8bitRegClassID,
2320 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2321 X86::GR64_TCW64_with_sub_8bitRegClassID,
2322 X86::GR64_TC_and_GR64_TCW64RegClassID,
2323 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2324 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2325 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2326 X86::GR64_NOREX_NOSPRegClassID,
2327 X86::GR64_NOREX_and_GR64_TCRegClassID,
2328 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2329 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2330 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2331 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
2332 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2333 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2334 X86::GR64_ABCDRegClassID,
2335 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
2336 X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
2337 X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID,
2338 X86::GR64_with_sub_32bit_in_GR32_CBRegClassID,
2339};
2340
2341static unsigned const GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
2342 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
2343 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
2344 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
2345 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
2346 X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
2347 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID,
2348 X86::GR64RegClassID,
2349 X86::GR64_with_sub_8bitRegClassID,
2350 X86::GR64_NOSPRegClassID,
2351 X86::GR64_NOREX2RegClassID,
2352 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2353 X86::GR64_NOREX2_NOSPRegClassID,
2354 X86::GR64PLTSafeRegClassID,
2355 X86::GR64_NOREXRegClassID,
2356 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2357 X86::GR64_NOREX_NOSPRegClassID,
2358 X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID,
2359 X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID,
2360 X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID,
2361};
2362
2363static unsigned const GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSuperclasses[] = {
2364 X86::GR64RegClassID,
2365 X86::GR64_with_sub_8bitRegClassID,
2366 X86::GR64_NOREX2RegClassID,
2367 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2368 X86::GR64_TCRegClassID,
2369 X86::GR64_NOREXRegClassID,
2370 X86::GR64_TCW64RegClassID,
2371 X86::GR64_TC_with_sub_8bitRegClassID,
2372 X86::GR64_TCW64_with_sub_8bitRegClassID,
2373 X86::GR64_TC_and_GR64_TCW64RegClassID,
2374 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2375 X86::GR64_NOREX_and_GR64_TCRegClassID,
2376 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2377 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2378 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2379 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
2380 X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID,
2381};
2382
2383static unsigned const GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISuperclasses[] = {
2384 X86::GR64RegClassID,
2385 X86::GR64_with_sub_8bitRegClassID,
2386 X86::GR64_NOSPRegClassID,
2387 X86::GR64_NOREX2RegClassID,
2388 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2389 X86::GR64_NOREX2_NOSPRegClassID,
2390 X86::GR64PLTSafeRegClassID,
2391 X86::GR64_TCRegClassID,
2392 X86::GR64_NOREXRegClassID,
2393 X86::GR64_TC_with_sub_8bitRegClassID,
2394 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2395 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2396 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2397 X86::GR64_NOREX_NOSPRegClassID,
2398 X86::GR64_NOREX_and_GR64_TCRegClassID,
2399 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2400 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2401 X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID,
2402 X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID,
2403};
2404
2405static unsigned const GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISuperclasses[] = {
2406 X86::GR64RegClassID,
2407 X86::GR64_with_sub_8bitRegClassID,
2408 X86::GR64_NOSPRegClassID,
2409 X86::GR64_NOREX2RegClassID,
2410 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2411 X86::GR64_NOREX2_NOSPRegClassID,
2412 X86::GR64PLTSafeRegClassID,
2413 X86::GR64_TCRegClassID,
2414 X86::GR64_NOREXRegClassID,
2415 X86::GR64_TC_with_sub_8bitRegClassID,
2416 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2417 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2418 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2419 X86::GR64_NOREX_NOSPRegClassID,
2420 X86::GR64_NOREX_and_GR64_TCRegClassID,
2421 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2422 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2423 X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID,
2424 X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID,
2425};
2426
2427static unsigned const RFP80Superclasses[] = {
2428 X86::RFP32RegClassID,
2429 X86::RFP64RegClassID,
2430};
2431
2432static unsigned const VR128XSuperclasses[] = {
2433 X86::FR16XRegClassID,
2434 X86::FR32XRegClassID,
2435 X86::FR64XRegClassID,
2436};
2437
2438static unsigned const VR128Superclasses[] = {
2439 X86::FR16XRegClassID,
2440 X86::FR16RegClassID,
2441 X86::FR32XRegClassID,
2442 X86::FR32RegClassID,
2443 X86::FR64XRegClassID,
2444 X86::FR64RegClassID,
2445 X86::VR128XRegClassID,
2446};
2447
2448static unsigned const VR256Superclasses[] = {
2449 X86::VR256XRegClassID,
2450};
2451
2452static unsigned const VR512_0_15Superclasses[] = {
2453 X86::VR512RegClassID,
2454};
2455
2456
2457static inline unsigned GR8AltOrderSelect(const MachineFunction &MF, bool Rev) {
2458 return MF.getSubtarget<X86Subtarget>().is64Bit();
2459 }
2460
2461static ArrayRef<MCPhysReg> GR8GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2462 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R16B, X86::R17B, X86::R18B, X86::R19B, X86::R22B, X86::R23B, X86::R24B, X86::R25B, X86::R26B, X86::R27B, X86::R30B, X86::R31B, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::R20B, X86::R21B, X86::R28B, X86::R29B };
2463 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8RegClassID];
2464 const ArrayRef<MCPhysReg> Order[] = {
2465 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2466 ArrayRef(AltOrder1)
2467 };
2468 const unsigned Select = GR8AltOrderSelect(MF, Rev);
2469 assert(Select < 2);
2470 return Order[Select];
2471}
2472
2473static inline unsigned GR8_NOREX2AltOrderSelect(const MachineFunction &MF, bool Rev) {
2474 return MF.getSubtarget<X86Subtarget>().is64Bit();
2475 }
2476
2477static ArrayRef<MCPhysReg> GR8_NOREX2GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2478 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B };
2479 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8_NOREX2RegClassID];
2480 const ArrayRef<MCPhysReg> Order[] = {
2481 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2482 ArrayRef(AltOrder1)
2483 };
2484 const unsigned Select = GR8_NOREX2AltOrderSelect(MF, Rev);
2485 assert(Select < 2);
2486 return Order[Select];
2487}
2488
2489static inline unsigned GR8_NOREXAltOrderSelect(const MachineFunction &MF, bool Rev) {
2490 return MF.getSubtarget<X86Subtarget>().is64Bit();
2491 }
2492
2493static ArrayRef<MCPhysReg> GR8_NOREXGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2494 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL };
2495 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8_NOREXRegClassID];
2496 const ArrayRef<MCPhysReg> Order[] = {
2497 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2498 ArrayRef(AltOrder1)
2499 };
2500 const unsigned Select = GR8_NOREXAltOrderSelect(MF, Rev);
2501 assert(Select < 2);
2502 return Order[Select];
2503}
2504
2505static inline unsigned FR32XAltOrderSelect(const MachineFunction &MF, bool Rev) {
2506 return Rev;
2507 }
2508
2509static ArrayRef<MCPhysReg> FR32XGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2510 static const MCPhysReg AltOrder1[] = { X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 };
2511 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::FR32XRegClassID];
2512 const ArrayRef<MCPhysReg> Order[] = {
2513 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2514 ArrayRef(AltOrder1)
2515 };
2516 const unsigned Select = FR32XAltOrderSelect(MF, Rev);
2517 assert(Select < 2);
2518 return Order[Select];
2519}
2520
2521static inline unsigned FR64XAltOrderSelect(const MachineFunction &MF, bool Rev) {
2522 return Rev;
2523 }
2524
2525static ArrayRef<MCPhysReg> FR64XGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2526 static const MCPhysReg AltOrder1[] = { X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 };
2527 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::FR64XRegClassID];
2528 const ArrayRef<MCPhysReg> Order[] = {
2529 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2530 ArrayRef(AltOrder1)
2531 };
2532 const unsigned Select = FR64XAltOrderSelect(MF, Rev);
2533 assert(Select < 2);
2534 return Order[Select];
2535}
2536
2537static inline unsigned VR128XAltOrderSelect(const MachineFunction &MF, bool Rev) {
2538 return Rev;
2539 }
2540
2541static ArrayRef<MCPhysReg> VR128XGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2542 static const MCPhysReg AltOrder1[] = { X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 };
2543 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::VR128XRegClassID];
2544 const ArrayRef<MCPhysReg> Order[] = {
2545 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2546 ArrayRef(AltOrder1)
2547 };
2548 const unsigned Select = VR128XAltOrderSelect(MF, Rev);
2549 assert(Select < 2);
2550 return Order[Select];
2551}
2552
2553static inline unsigned VR256XAltOrderSelect(const MachineFunction &MF, bool Rev) {
2554 return Rev;
2555 }
2556
2557static ArrayRef<MCPhysReg> VR256XGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2558 static const MCPhysReg AltOrder1[] = { X86::YMM16, X86::YMM17, X86::YMM18, X86::YMM19, X86::YMM20, X86::YMM21, X86::YMM22, X86::YMM23, X86::YMM24, X86::YMM25, X86::YMM26, X86::YMM27, X86::YMM28, X86::YMM29, X86::YMM30, X86::YMM31, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15 };
2559 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::VR256XRegClassID];
2560 const ArrayRef<MCPhysReg> Order[] = {
2561 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2562 ArrayRef(AltOrder1)
2563 };
2564 const unsigned Select = VR256XAltOrderSelect(MF, Rev);
2565 assert(Select < 2);
2566 return Order[Select];
2567}
2568
2569namespace X86 { // Register class instances
2570 extern const TargetRegisterClass GR8RegClass = {
2571 .MC: &X86MCRegisterClasses[GR8RegClassID],
2572 .SubClassMask: GR8SubClassMask,
2573 .SuperRegIndices: SuperRegIdxSeqs + 2,
2574 .LaneMask: LaneBitmask(0x0000000000000001),
2575 .AllocationPriority: 0,
2576 .GlobalPriority: false,
2577 .TSFlags: 0x00, /* TSFlags */
2578 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2579 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2580 .SuperClasses: nullptr, .SuperClassesSize: 0,
2581 .OrderFunc: GR8GetRawAllocationOrder
2582 };
2583
2584 extern const TargetRegisterClass GRH8RegClass = {
2585 .MC: &X86MCRegisterClasses[GRH8RegClassID],
2586 .SubClassMask: GRH8SubClassMask,
2587 .SuperRegIndices: SuperRegIdxSeqs + 1,
2588 .LaneMask: LaneBitmask(0x0000000000000001),
2589 .AllocationPriority: 0,
2590 .GlobalPriority: false,
2591 .TSFlags: 0x00, /* TSFlags */
2592 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2593 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2594 .SuperClasses: nullptr, .SuperClassesSize: 0,
2595 .OrderFunc: nullptr
2596 };
2597
2598 extern const TargetRegisterClass GR8_NOREX2RegClass = {
2599 .MC: &X86MCRegisterClasses[GR8_NOREX2RegClassID],
2600 .SubClassMask: GR8_NOREX2SubClassMask,
2601 .SuperRegIndices: SuperRegIdxSeqs + 2,
2602 .LaneMask: LaneBitmask(0x0000000000000001),
2603 .AllocationPriority: 0,
2604 .GlobalPriority: false,
2605 .TSFlags: 0x00, /* TSFlags */
2606 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2607 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2608 .SuperClasses: GR8_NOREX2Superclasses, .SuperClassesSize: 1,
2609 .OrderFunc: GR8_NOREX2GetRawAllocationOrder
2610 };
2611
2612 extern const TargetRegisterClass GR8_NOREXRegClass = {
2613 .MC: &X86MCRegisterClasses[GR8_NOREXRegClassID],
2614 .SubClassMask: GR8_NOREXSubClassMask,
2615 .SuperRegIndices: SuperRegIdxSeqs + 2,
2616 .LaneMask: LaneBitmask(0x0000000000000001),
2617 .AllocationPriority: 0,
2618 .GlobalPriority: false,
2619 .TSFlags: 0x00, /* TSFlags */
2620 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2621 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2622 .SuperClasses: GR8_NOREXSuperclasses, .SuperClassesSize: 2,
2623 .OrderFunc: GR8_NOREXGetRawAllocationOrder
2624 };
2625
2626 extern const TargetRegisterClass GR8_ABCD_HRegClass = {
2627 .MC: &X86MCRegisterClasses[GR8_ABCD_HRegClassID],
2628 .SubClassMask: GR8_ABCD_HSubClassMask,
2629 .SuperRegIndices: SuperRegIdxSeqs + 3,
2630 .LaneMask: LaneBitmask(0x0000000000000001),
2631 .AllocationPriority: 0,
2632 .GlobalPriority: false,
2633 .TSFlags: 0x00, /* TSFlags */
2634 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2635 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2636 .SuperClasses: GR8_ABCD_HSuperclasses, .SuperClassesSize: 3,
2637 .OrderFunc: nullptr
2638 };
2639
2640 extern const TargetRegisterClass GR8_ABCD_LRegClass = {
2641 .MC: &X86MCRegisterClasses[GR8_ABCD_LRegClassID],
2642 .SubClassMask: GR8_ABCD_LSubClassMask,
2643 .SuperRegIndices: SuperRegIdxSeqs + 0,
2644 .LaneMask: LaneBitmask(0x0000000000000001),
2645 .AllocationPriority: 0,
2646 .GlobalPriority: false,
2647 .TSFlags: 0x00, /* TSFlags */
2648 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2649 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2650 .SuperClasses: GR8_ABCD_LSuperclasses, .SuperClassesSize: 3,
2651 .OrderFunc: nullptr
2652 };
2653
2654 extern const TargetRegisterClass GRH16RegClass = {
2655 .MC: &X86MCRegisterClasses[GRH16RegClassID],
2656 .SubClassMask: GRH16SubClassMask,
2657 .SuperRegIndices: SuperRegIdxSeqs + 1,
2658 .LaneMask: LaneBitmask(0x0000000000000001),
2659 .AllocationPriority: 0,
2660 .GlobalPriority: false,
2661 .TSFlags: 0x00, /* TSFlags */
2662 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2663 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2664 .SuperClasses: nullptr, .SuperClassesSize: 0,
2665 .OrderFunc: nullptr
2666 };
2667
2668 extern const TargetRegisterClass GR16RegClass = {
2669 .MC: &X86MCRegisterClasses[GR16RegClassID],
2670 .SubClassMask: GR16SubClassMask,
2671 .SuperRegIndices: SuperRegIdxSeqs + 5,
2672 .LaneMask: LaneBitmask(0x0000000000000003),
2673 .AllocationPriority: 0,
2674 .GlobalPriority: false,
2675 .TSFlags: 0x00, /* TSFlags */
2676 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2677 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2678 .SuperClasses: nullptr, .SuperClassesSize: 0,
2679 .OrderFunc: nullptr
2680 };
2681
2682 extern const TargetRegisterClass GR16_NOREX2RegClass = {
2683 .MC: &X86MCRegisterClasses[GR16_NOREX2RegClassID],
2684 .SubClassMask: GR16_NOREX2SubClassMask,
2685 .SuperRegIndices: SuperRegIdxSeqs + 5,
2686 .LaneMask: LaneBitmask(0x0000000000000003),
2687 .AllocationPriority: 0,
2688 .GlobalPriority: false,
2689 .TSFlags: 0x00, /* TSFlags */
2690 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2691 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2692 .SuperClasses: GR16_NOREX2Superclasses, .SuperClassesSize: 1,
2693 .OrderFunc: nullptr
2694 };
2695
2696 extern const TargetRegisterClass GR16_NOREXRegClass = {
2697 .MC: &X86MCRegisterClasses[GR16_NOREXRegClassID],
2698 .SubClassMask: GR16_NOREXSubClassMask,
2699 .SuperRegIndices: SuperRegIdxSeqs + 5,
2700 .LaneMask: LaneBitmask(0x0000000000000003),
2701 .AllocationPriority: 0,
2702 .GlobalPriority: false,
2703 .TSFlags: 0x00, /* TSFlags */
2704 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2705 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2706 .SuperClasses: GR16_NOREXSuperclasses, .SuperClassesSize: 2,
2707 .OrderFunc: nullptr
2708 };
2709
2710 extern const TargetRegisterClass VK1RegClass = {
2711 .MC: &X86MCRegisterClasses[VK1RegClassID],
2712 .SubClassMask: VK1SubClassMask,
2713 .SuperRegIndices: SuperRegIdxSeqs + 9,
2714 .LaneMask: LaneBitmask(0x0000000000000001),
2715 .AllocationPriority: 0,
2716 .GlobalPriority: false,
2717 .TSFlags: 0x00, /* TSFlags */
2718 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2719 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2720 .SuperClasses: VK1Superclasses, .SuperClassesSize: 4,
2721 .OrderFunc: nullptr
2722 };
2723
2724 extern const TargetRegisterClass VK16RegClass = {
2725 .MC: &X86MCRegisterClasses[VK16RegClassID],
2726 .SubClassMask: VK16SubClassMask,
2727 .SuperRegIndices: SuperRegIdxSeqs + 9,
2728 .LaneMask: LaneBitmask(0x0000000000000001),
2729 .AllocationPriority: 0,
2730 .GlobalPriority: false,
2731 .TSFlags: 0x00, /* TSFlags */
2732 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2733 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2734 .SuperClasses: VK16Superclasses, .SuperClassesSize: 4,
2735 .OrderFunc: nullptr
2736 };
2737
2738 extern const TargetRegisterClass VK2RegClass = {
2739 .MC: &X86MCRegisterClasses[VK2RegClassID],
2740 .SubClassMask: VK2SubClassMask,
2741 .SuperRegIndices: SuperRegIdxSeqs + 9,
2742 .LaneMask: LaneBitmask(0x0000000000000001),
2743 .AllocationPriority: 0,
2744 .GlobalPriority: false,
2745 .TSFlags: 0x00, /* TSFlags */
2746 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2747 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2748 .SuperClasses: VK2Superclasses, .SuperClassesSize: 4,
2749 .OrderFunc: nullptr
2750 };
2751
2752 extern const TargetRegisterClass VK4RegClass = {
2753 .MC: &X86MCRegisterClasses[VK4RegClassID],
2754 .SubClassMask: VK4SubClassMask,
2755 .SuperRegIndices: SuperRegIdxSeqs + 9,
2756 .LaneMask: LaneBitmask(0x0000000000000001),
2757 .AllocationPriority: 0,
2758 .GlobalPriority: false,
2759 .TSFlags: 0x00, /* TSFlags */
2760 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2761 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2762 .SuperClasses: VK4Superclasses, .SuperClassesSize: 4,
2763 .OrderFunc: nullptr
2764 };
2765
2766 extern const TargetRegisterClass VK8RegClass = {
2767 .MC: &X86MCRegisterClasses[VK8RegClassID],
2768 .SubClassMask: VK8SubClassMask,
2769 .SuperRegIndices: SuperRegIdxSeqs + 9,
2770 .LaneMask: LaneBitmask(0x0000000000000001),
2771 .AllocationPriority: 0,
2772 .GlobalPriority: false,
2773 .TSFlags: 0x00, /* TSFlags */
2774 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2775 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2776 .SuperClasses: VK8Superclasses, .SuperClassesSize: 4,
2777 .OrderFunc: nullptr
2778 };
2779
2780 extern const TargetRegisterClass VK16WMRegClass = {
2781 .MC: &X86MCRegisterClasses[VK16WMRegClassID],
2782 .SubClassMask: VK16WMSubClassMask,
2783 .SuperRegIndices: SuperRegIdxSeqs + 9,
2784 .LaneMask: LaneBitmask(0x0000000000000001),
2785 .AllocationPriority: 0,
2786 .GlobalPriority: false,
2787 .TSFlags: 0x00, /* TSFlags */
2788 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2789 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2790 .SuperClasses: VK16WMSuperclasses, .SuperClassesSize: 9,
2791 .OrderFunc: nullptr
2792 };
2793
2794 extern const TargetRegisterClass VK1WMRegClass = {
2795 .MC: &X86MCRegisterClasses[VK1WMRegClassID],
2796 .SubClassMask: VK1WMSubClassMask,
2797 .SuperRegIndices: SuperRegIdxSeqs + 9,
2798 .LaneMask: LaneBitmask(0x0000000000000001),
2799 .AllocationPriority: 0,
2800 .GlobalPriority: false,
2801 .TSFlags: 0x00, /* TSFlags */
2802 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2803 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2804 .SuperClasses: VK1WMSuperclasses, .SuperClassesSize: 9,
2805 .OrderFunc: nullptr
2806 };
2807
2808 extern const TargetRegisterClass VK2WMRegClass = {
2809 .MC: &X86MCRegisterClasses[VK2WMRegClassID],
2810 .SubClassMask: VK2WMSubClassMask,
2811 .SuperRegIndices: SuperRegIdxSeqs + 9,
2812 .LaneMask: LaneBitmask(0x0000000000000001),
2813 .AllocationPriority: 0,
2814 .GlobalPriority: false,
2815 .TSFlags: 0x00, /* TSFlags */
2816 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2817 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2818 .SuperClasses: VK2WMSuperclasses, .SuperClassesSize: 9,
2819 .OrderFunc: nullptr
2820 };
2821
2822 extern const TargetRegisterClass VK4WMRegClass = {
2823 .MC: &X86MCRegisterClasses[VK4WMRegClassID],
2824 .SubClassMask: VK4WMSubClassMask,
2825 .SuperRegIndices: SuperRegIdxSeqs + 9,
2826 .LaneMask: LaneBitmask(0x0000000000000001),
2827 .AllocationPriority: 0,
2828 .GlobalPriority: false,
2829 .TSFlags: 0x00, /* TSFlags */
2830 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2831 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2832 .SuperClasses: VK4WMSuperclasses, .SuperClassesSize: 9,
2833 .OrderFunc: nullptr
2834 };
2835
2836 extern const TargetRegisterClass VK8WMRegClass = {
2837 .MC: &X86MCRegisterClasses[VK8WMRegClassID],
2838 .SubClassMask: VK8WMSubClassMask,
2839 .SuperRegIndices: SuperRegIdxSeqs + 9,
2840 .LaneMask: LaneBitmask(0x0000000000000001),
2841 .AllocationPriority: 0,
2842 .GlobalPriority: false,
2843 .TSFlags: 0x00, /* TSFlags */
2844 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2845 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2846 .SuperClasses: VK8WMSuperclasses, .SuperClassesSize: 9,
2847 .OrderFunc: nullptr
2848 };
2849
2850 extern const TargetRegisterClass SEGMENT_REGRegClass = {
2851 .MC: &X86MCRegisterClasses[SEGMENT_REGRegClassID],
2852 .SubClassMask: SEGMENT_REGSubClassMask,
2853 .SuperRegIndices: SuperRegIdxSeqs + 1,
2854 .LaneMask: LaneBitmask(0x0000000000000001),
2855 .AllocationPriority: 0,
2856 .GlobalPriority: false,
2857 .TSFlags: 0x00, /* TSFlags */
2858 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2859 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2860 .SuperClasses: nullptr, .SuperClassesSize: 0,
2861 .OrderFunc: nullptr
2862 };
2863
2864 extern const TargetRegisterClass GR16_ABCDRegClass = {
2865 .MC: &X86MCRegisterClasses[GR16_ABCDRegClassID],
2866 .SubClassMask: GR16_ABCDSubClassMask,
2867 .SuperRegIndices: SuperRegIdxSeqs + 5,
2868 .LaneMask: LaneBitmask(0x0000000000000003),
2869 .AllocationPriority: 0,
2870 .GlobalPriority: false,
2871 .TSFlags: 0x00, /* TSFlags */
2872 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2873 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2874 .SuperClasses: GR16_ABCDSuperclasses, .SuperClassesSize: 3,
2875 .OrderFunc: nullptr
2876 };
2877
2878 extern const TargetRegisterClass FPCCRRegClass = {
2879 .MC: &X86MCRegisterClasses[FPCCRRegClassID],
2880 .SubClassMask: FPCCRSubClassMask,
2881 .SuperRegIndices: SuperRegIdxSeqs + 1,
2882 .LaneMask: LaneBitmask(0x0000000000000001),
2883 .AllocationPriority: 0,
2884 .GlobalPriority: false,
2885 .TSFlags: 0x00, /* TSFlags */
2886 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2887 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2888 .SuperClasses: nullptr, .SuperClassesSize: 0,
2889 .OrderFunc: nullptr
2890 };
2891
2892 extern const TargetRegisterClass FR16XRegClass = {
2893 .MC: &X86MCRegisterClasses[FR16XRegClassID],
2894 .SubClassMask: FR16XSubClassMask,
2895 .SuperRegIndices: SuperRegIdxSeqs + 12,
2896 .LaneMask: LaneBitmask(0x0000000000000001),
2897 .AllocationPriority: 0,
2898 .GlobalPriority: false,
2899 .TSFlags: 0x00, /* TSFlags */
2900 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2901 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2902 .SuperClasses: nullptr, .SuperClassesSize: 0,
2903 .OrderFunc: nullptr
2904 };
2905
2906 extern const TargetRegisterClass FR16RegClass = {
2907 .MC: &X86MCRegisterClasses[FR16RegClassID],
2908 .SubClassMask: FR16SubClassMask,
2909 .SuperRegIndices: SuperRegIdxSeqs + 12,
2910 .LaneMask: LaneBitmask(0x0000000000000001),
2911 .AllocationPriority: 0,
2912 .GlobalPriority: false,
2913 .TSFlags: 0x00, /* TSFlags */
2914 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2915 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2916 .SuperClasses: FR16Superclasses, .SuperClassesSize: 1,
2917 .OrderFunc: nullptr
2918 };
2919
2920 extern const TargetRegisterClass VK16PAIRRegClass = {
2921 .MC: &X86MCRegisterClasses[VK16PAIRRegClassID],
2922 .SubClassMask: VK16PAIRSubClassMask,
2923 .SuperRegIndices: SuperRegIdxSeqs + 1,
2924 .LaneMask: LaneBitmask(0x0000000000000030),
2925 .AllocationPriority: 0,
2926 .GlobalPriority: false,
2927 .TSFlags: 0x00, /* TSFlags */
2928 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2929 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2930 .SuperClasses: VK16PAIRSuperclasses, .SuperClassesSize: 4,
2931 .OrderFunc: nullptr
2932 };
2933
2934 extern const TargetRegisterClass VK1PAIRRegClass = {
2935 .MC: &X86MCRegisterClasses[VK1PAIRRegClassID],
2936 .SubClassMask: VK1PAIRSubClassMask,
2937 .SuperRegIndices: SuperRegIdxSeqs + 1,
2938 .LaneMask: LaneBitmask(0x0000000000000030),
2939 .AllocationPriority: 0,
2940 .GlobalPriority: false,
2941 .TSFlags: 0x00, /* TSFlags */
2942 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2943 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2944 .SuperClasses: VK1PAIRSuperclasses, .SuperClassesSize: 4,
2945 .OrderFunc: nullptr
2946 };
2947
2948 extern const TargetRegisterClass VK2PAIRRegClass = {
2949 .MC: &X86MCRegisterClasses[VK2PAIRRegClassID],
2950 .SubClassMask: VK2PAIRSubClassMask,
2951 .SuperRegIndices: SuperRegIdxSeqs + 1,
2952 .LaneMask: LaneBitmask(0x0000000000000030),
2953 .AllocationPriority: 0,
2954 .GlobalPriority: false,
2955 .TSFlags: 0x00, /* TSFlags */
2956 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2957 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2958 .SuperClasses: VK2PAIRSuperclasses, .SuperClassesSize: 4,
2959 .OrderFunc: nullptr
2960 };
2961
2962 extern const TargetRegisterClass VK4PAIRRegClass = {
2963 .MC: &X86MCRegisterClasses[VK4PAIRRegClassID],
2964 .SubClassMask: VK4PAIRSubClassMask,
2965 .SuperRegIndices: SuperRegIdxSeqs + 1,
2966 .LaneMask: LaneBitmask(0x0000000000000030),
2967 .AllocationPriority: 0,
2968 .GlobalPriority: false,
2969 .TSFlags: 0x00, /* TSFlags */
2970 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2971 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2972 .SuperClasses: VK4PAIRSuperclasses, .SuperClassesSize: 4,
2973 .OrderFunc: nullptr
2974 };
2975
2976 extern const TargetRegisterClass VK8PAIRRegClass = {
2977 .MC: &X86MCRegisterClasses[VK8PAIRRegClassID],
2978 .SubClassMask: VK8PAIRSubClassMask,
2979 .SuperRegIndices: SuperRegIdxSeqs + 1,
2980 .LaneMask: LaneBitmask(0x0000000000000030),
2981 .AllocationPriority: 0,
2982 .GlobalPriority: false,
2983 .TSFlags: 0x00, /* TSFlags */
2984 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2985 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2986 .SuperClasses: VK8PAIRSuperclasses, .SuperClassesSize: 4,
2987 .OrderFunc: nullptr
2988 };
2989
2990 extern const TargetRegisterClass VK1PAIR_with_sub_mask_0_in_VK1WMRegClass = {
2991 .MC: &X86MCRegisterClasses[VK1PAIR_with_sub_mask_0_in_VK1WMRegClassID],
2992 .SubClassMask: VK1PAIR_with_sub_mask_0_in_VK1WMSubClassMask,
2993 .SuperRegIndices: SuperRegIdxSeqs + 1,
2994 .LaneMask: LaneBitmask(0x0000000000000030),
2995 .AllocationPriority: 0,
2996 .GlobalPriority: false,
2997 .TSFlags: 0x00, /* TSFlags */
2998 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2999 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3000 .SuperClasses: VK1PAIR_with_sub_mask_0_in_VK1WMSuperclasses, .SuperClassesSize: 5,
3001 .OrderFunc: nullptr
3002 };
3003
3004 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass = {
3005 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBPRegClassID],
3006 .SubClassMask: LOW32_ADDR_ACCESS_RBPSubClassMask,
3007 .SuperRegIndices: SuperRegIdxSeqs + 7,
3008 .LaneMask: LaneBitmask(0x000000000000000F),
3009 .AllocationPriority: 0,
3010 .GlobalPriority: false,
3011 .TSFlags: 0x00, /* TSFlags */
3012 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3013 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3014 .SuperClasses: nullptr, .SuperClassesSize: 0,
3015 .OrderFunc: nullptr
3016 };
3017
3018 extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass = {
3019 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESSRegClassID],
3020 .SubClassMask: LOW32_ADDR_ACCESSSubClassMask,
3021 .SuperRegIndices: SuperRegIdxSeqs + 7,
3022 .LaneMask: LaneBitmask(0x000000000000000F),
3023 .AllocationPriority: 0,
3024 .GlobalPriority: false,
3025 .TSFlags: 0x00, /* TSFlags */
3026 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3027 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3028 .SuperClasses: LOW32_ADDR_ACCESSSuperclasses, .SuperClassesSize: 1,
3029 .OrderFunc: nullptr
3030 };
3031
3032 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass = {
3033 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID],
3034 .SubClassMask: LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask,
3035 .SuperRegIndices: SuperRegIdxSeqs + 7,
3036 .LaneMask: LaneBitmask(0x000000000000000F),
3037 .AllocationPriority: 0,
3038 .GlobalPriority: false,
3039 .TSFlags: 0x00, /* TSFlags */
3040 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3041 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3042 .SuperClasses: LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses, .SuperClassesSize: 1,
3043 .OrderFunc: nullptr
3044 };
3045
3046 extern const TargetRegisterClass FR32XRegClass = {
3047 .MC: &X86MCRegisterClasses[FR32XRegClassID],
3048 .SubClassMask: FR32XSubClassMask,
3049 .SuperRegIndices: SuperRegIdxSeqs + 12,
3050 .LaneMask: LaneBitmask(0x0000000000000001),
3051 .AllocationPriority: 0,
3052 .GlobalPriority: false,
3053 .TSFlags: 0x00, /* TSFlags */
3054 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3055 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3056 .SuperClasses: FR32XSuperclasses, .SuperClassesSize: 1,
3057 .OrderFunc: FR32XGetRawAllocationOrder
3058 };
3059
3060 extern const TargetRegisterClass GR32RegClass = {
3061 .MC: &X86MCRegisterClasses[GR32RegClassID],
3062 .SubClassMask: GR32SubClassMask,
3063 .SuperRegIndices: SuperRegIdxSeqs + 7,
3064 .LaneMask: LaneBitmask(0x000000000000000F),
3065 .AllocationPriority: 0,
3066 .GlobalPriority: false,
3067 .TSFlags: 0x00, /* TSFlags */
3068 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3069 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3070 .SuperClasses: GR32Superclasses, .SuperClassesSize: 3,
3071 .OrderFunc: nullptr
3072 };
3073
3074 extern const TargetRegisterClass GR32_NOSPRegClass = {
3075 .MC: &X86MCRegisterClasses[GR32_NOSPRegClassID],
3076 .SubClassMask: GR32_NOSPSubClassMask,
3077 .SuperRegIndices: SuperRegIdxSeqs + 7,
3078 .LaneMask: LaneBitmask(0x000000000000000F),
3079 .AllocationPriority: 0,
3080 .GlobalPriority: false,
3081 .TSFlags: 0x00, /* TSFlags */
3082 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3083 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3084 .SuperClasses: GR32_NOSPSuperclasses, .SuperClassesSize: 4,
3085 .OrderFunc: nullptr
3086 };
3087
3088 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass = {
3089 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID],
3090 .SubClassMask: LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2SubClassMask,
3091 .SuperRegIndices: SuperRegIdxSeqs + 7,
3092 .LaneMask: LaneBitmask(0x000000000000000F),
3093 .AllocationPriority: 0,
3094 .GlobalPriority: false,
3095 .TSFlags: 0x00, /* TSFlags */
3096 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3097 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3098 .SuperClasses: LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Superclasses, .SuperClassesSize: 2,
3099 .OrderFunc: nullptr
3100 };
3101
3102 extern const TargetRegisterClass DEBUG_REGRegClass = {
3103 .MC: &X86MCRegisterClasses[DEBUG_REGRegClassID],
3104 .SubClassMask: DEBUG_REGSubClassMask,
3105 .SuperRegIndices: SuperRegIdxSeqs + 1,
3106 .LaneMask: LaneBitmask(0x0000000000000001),
3107 .AllocationPriority: 0,
3108 .GlobalPriority: false,
3109 .TSFlags: 0x00, /* TSFlags */
3110 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3111 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3112 .SuperClasses: nullptr, .SuperClassesSize: 0,
3113 .OrderFunc: nullptr
3114 };
3115
3116 extern const TargetRegisterClass FR32RegClass = {
3117 .MC: &X86MCRegisterClasses[FR32RegClassID],
3118 .SubClassMask: FR32SubClassMask,
3119 .SuperRegIndices: SuperRegIdxSeqs + 12,
3120 .LaneMask: LaneBitmask(0x0000000000000001),
3121 .AllocationPriority: 0,
3122 .GlobalPriority: false,
3123 .TSFlags: 0x00, /* TSFlags */
3124 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3125 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3126 .SuperClasses: FR32Superclasses, .SuperClassesSize: 3,
3127 .OrderFunc: nullptr
3128 };
3129
3130 extern const TargetRegisterClass GR32_NOREX2RegClass = {
3131 .MC: &X86MCRegisterClasses[GR32_NOREX2RegClassID],
3132 .SubClassMask: GR32_NOREX2SubClassMask,
3133 .SuperRegIndices: SuperRegIdxSeqs + 7,
3134 .LaneMask: LaneBitmask(0x000000000000000F),
3135 .AllocationPriority: 0,
3136 .GlobalPriority: false,
3137 .TSFlags: 0x00, /* TSFlags */
3138 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3139 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3140 .SuperClasses: GR32_NOREX2Superclasses, .SuperClassesSize: 5,
3141 .OrderFunc: nullptr
3142 };
3143
3144 extern const TargetRegisterClass GR32_NOREX2_NOSPRegClass = {
3145 .MC: &X86MCRegisterClasses[GR32_NOREX2_NOSPRegClassID],
3146 .SubClassMask: GR32_NOREX2_NOSPSubClassMask,
3147 .SuperRegIndices: SuperRegIdxSeqs + 7,
3148 .LaneMask: LaneBitmask(0x000000000000000F),
3149 .AllocationPriority: 0,
3150 .GlobalPriority: false,
3151 .TSFlags: 0x00, /* TSFlags */
3152 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3153 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3154 .SuperClasses: GR32_NOREX2_NOSPSuperclasses, .SuperClassesSize: 7,
3155 .OrderFunc: nullptr
3156 };
3157
3158 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass = {
3159 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID],
3160 .SubClassMask: LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask,
3161 .SuperRegIndices: SuperRegIdxSeqs + 7,
3162 .LaneMask: LaneBitmask(0x000000000000000F),
3163 .AllocationPriority: 0,
3164 .GlobalPriority: false,
3165 .TSFlags: 0x00, /* TSFlags */
3166 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3167 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3168 .SuperClasses: LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses, .SuperClassesSize: 3,
3169 .OrderFunc: nullptr
3170 };
3171
3172 extern const TargetRegisterClass GR32_NOREXRegClass = {
3173 .MC: &X86MCRegisterClasses[GR32_NOREXRegClassID],
3174 .SubClassMask: GR32_NOREXSubClassMask,
3175 .SuperRegIndices: SuperRegIdxSeqs + 7,
3176 .LaneMask: LaneBitmask(0x000000000000000F),
3177 .AllocationPriority: 0,
3178 .GlobalPriority: false,
3179 .TSFlags: 0x00, /* TSFlags */
3180 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3181 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3182 .SuperClasses: GR32_NOREXSuperclasses, .SuperClassesSize: 7,
3183 .OrderFunc: nullptr
3184 };
3185
3186 extern const TargetRegisterClass VK32RegClass = {
3187 .MC: &X86MCRegisterClasses[VK32RegClassID],
3188 .SubClassMask: VK32SubClassMask,
3189 .SuperRegIndices: SuperRegIdxSeqs + 9,
3190 .LaneMask: LaneBitmask(0x0000000000000001),
3191 .AllocationPriority: 0,
3192 .GlobalPriority: false,
3193 .TSFlags: 0x00, /* TSFlags */
3194 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3195 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3196 .SuperClasses: VK32Superclasses, .SuperClassesSize: 5,
3197 .OrderFunc: nullptr
3198 };
3199
3200 extern const TargetRegisterClass GR32_NOREX_NOSPRegClass = {
3201 .MC: &X86MCRegisterClasses[GR32_NOREX_NOSPRegClassID],
3202 .SubClassMask: GR32_NOREX_NOSPSubClassMask,
3203 .SuperRegIndices: SuperRegIdxSeqs + 7,
3204 .LaneMask: LaneBitmask(0x000000000000000F),
3205 .AllocationPriority: 0,
3206 .GlobalPriority: false,
3207 .TSFlags: 0x00, /* TSFlags */
3208 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3209 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3210 .SuperClasses: GR32_NOREX_NOSPSuperclasses, .SuperClassesSize: 10,
3211 .OrderFunc: nullptr
3212 };
3213
3214 extern const TargetRegisterClass RFP32RegClass = {
3215 .MC: &X86MCRegisterClasses[RFP32RegClassID],
3216 .SubClassMask: RFP32SubClassMask,
3217 .SuperRegIndices: SuperRegIdxSeqs + 1,
3218 .LaneMask: LaneBitmask(0x0000000000000001),
3219 .AllocationPriority: 0,
3220 .GlobalPriority: false,
3221 .TSFlags: 0x00, /* TSFlags */
3222 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3223 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3224 .SuperClasses: nullptr, .SuperClassesSize: 0,
3225 .OrderFunc: nullptr
3226 };
3227
3228 extern const TargetRegisterClass VK32WMRegClass = {
3229 .MC: &X86MCRegisterClasses[VK32WMRegClassID],
3230 .SubClassMask: VK32WMSubClassMask,
3231 .SuperRegIndices: SuperRegIdxSeqs + 9,
3232 .LaneMask: LaneBitmask(0x0000000000000001),
3233 .AllocationPriority: 0,
3234 .GlobalPriority: false,
3235 .TSFlags: 0x00, /* TSFlags */
3236 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3237 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3238 .SuperClasses: VK32WMSuperclasses, .SuperClassesSize: 11,
3239 .OrderFunc: nullptr
3240 };
3241
3242 extern const TargetRegisterClass GR32_ABCDRegClass = {
3243 .MC: &X86MCRegisterClasses[GR32_ABCDRegClassID],
3244 .SubClassMask: GR32_ABCDSubClassMask,
3245 .SuperRegIndices: SuperRegIdxSeqs + 7,
3246 .LaneMask: LaneBitmask(0x000000000000000F),
3247 .AllocationPriority: 0,
3248 .GlobalPriority: false,
3249 .TSFlags: 0x00, /* TSFlags */
3250 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3251 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3252 .SuperClasses: GR32_ABCDSuperclasses, .SuperClassesSize: 11,
3253 .OrderFunc: nullptr
3254 };
3255
3256 extern const TargetRegisterClass GR32_TCRegClass = {
3257 .MC: &X86MCRegisterClasses[GR32_TCRegClassID],
3258 .SubClassMask: GR32_TCSubClassMask,
3259 .SuperRegIndices: SuperRegIdxSeqs + 7,
3260 .LaneMask: LaneBitmask(0x000000000000000F),
3261 .AllocationPriority: 0,
3262 .GlobalPriority: false,
3263 .TSFlags: 0x00, /* TSFlags */
3264 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3265 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3266 .SuperClasses: GR32_TCSuperclasses, .SuperClassesSize: 8,
3267 .OrderFunc: nullptr
3268 };
3269
3270 extern const TargetRegisterClass GR32_ABCD_and_GR32_TCRegClass = {
3271 .MC: &X86MCRegisterClasses[GR32_ABCD_and_GR32_TCRegClassID],
3272 .SubClassMask: GR32_ABCD_and_GR32_TCSubClassMask,
3273 .SuperRegIndices: SuperRegIdxSeqs + 7,
3274 .LaneMask: LaneBitmask(0x000000000000000F),
3275 .AllocationPriority: 0,
3276 .GlobalPriority: false,
3277 .TSFlags: 0x00, /* TSFlags */
3278 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3279 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3280 .SuperClasses: GR32_ABCD_and_GR32_TCSuperclasses, .SuperClassesSize: 13,
3281 .OrderFunc: nullptr
3282 };
3283
3284 extern const TargetRegisterClass GR32_ADRegClass = {
3285 .MC: &X86MCRegisterClasses[GR32_ADRegClassID],
3286 .SubClassMask: GR32_ADSubClassMask,
3287 .SuperRegIndices: SuperRegIdxSeqs + 7,
3288 .LaneMask: LaneBitmask(0x000000000000000F),
3289 .AllocationPriority: 0,
3290 .GlobalPriority: false,
3291 .TSFlags: 0x00, /* TSFlags */
3292 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3293 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3294 .SuperClasses: GR32_ADSuperclasses, .SuperClassesSize: 14,
3295 .OrderFunc: nullptr
3296 };
3297
3298 extern const TargetRegisterClass GR32_ArgRefRegClass = {
3299 .MC: &X86MCRegisterClasses[GR32_ArgRefRegClassID],
3300 .SubClassMask: GR32_ArgRefSubClassMask,
3301 .SuperRegIndices: SuperRegIdxSeqs + 7,
3302 .LaneMask: LaneBitmask(0x000000000000000F),
3303 .AllocationPriority: 0,
3304 .GlobalPriority: false,
3305 .TSFlags: 0x00, /* TSFlags */
3306 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3307 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3308 .SuperClasses: GR32_ArgRefSuperclasses, .SuperClassesSize: 14,
3309 .OrderFunc: nullptr
3310 };
3311
3312 extern const TargetRegisterClass GR32_BPSPRegClass = {
3313 .MC: &X86MCRegisterClasses[GR32_BPSPRegClassID],
3314 .SubClassMask: GR32_BPSPSubClassMask,
3315 .SuperRegIndices: SuperRegIdxSeqs + 7,
3316 .LaneMask: LaneBitmask(0x000000000000000F),
3317 .AllocationPriority: 0,
3318 .GlobalPriority: false,
3319 .TSFlags: 0x00, /* TSFlags */
3320 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3321 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3322 .SuperClasses: GR32_BPSPSuperclasses, .SuperClassesSize: 8,
3323 .OrderFunc: nullptr
3324 };
3325
3326 extern const TargetRegisterClass GR32_BSIRegClass = {
3327 .MC: &X86MCRegisterClasses[GR32_BSIRegClassID],
3328 .SubClassMask: GR32_BSISubClassMask,
3329 .SuperRegIndices: SuperRegIdxSeqs + 7,
3330 .LaneMask: LaneBitmask(0x000000000000000F),
3331 .AllocationPriority: 0,
3332 .GlobalPriority: false,
3333 .TSFlags: 0x00, /* TSFlags */
3334 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3335 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3336 .SuperClasses: GR32_BSISuperclasses, .SuperClassesSize: 11,
3337 .OrderFunc: nullptr
3338 };
3339
3340 extern const TargetRegisterClass GR32_CBRegClass = {
3341 .MC: &X86MCRegisterClasses[GR32_CBRegClassID],
3342 .SubClassMask: GR32_CBSubClassMask,
3343 .SuperRegIndices: SuperRegIdxSeqs + 7,
3344 .LaneMask: LaneBitmask(0x000000000000000F),
3345 .AllocationPriority: 0,
3346 .GlobalPriority: false,
3347 .TSFlags: 0x00, /* TSFlags */
3348 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3349 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3350 .SuperClasses: GR32_CBSuperclasses, .SuperClassesSize: 12,
3351 .OrderFunc: nullptr
3352 };
3353
3354 extern const TargetRegisterClass GR32_DCRegClass = {
3355 .MC: &X86MCRegisterClasses[GR32_DCRegClassID],
3356 .SubClassMask: GR32_DCSubClassMask,
3357 .SuperRegIndices: SuperRegIdxSeqs + 7,
3358 .LaneMask: LaneBitmask(0x000000000000000F),
3359 .AllocationPriority: 0,
3360 .GlobalPriority: false,
3361 .TSFlags: 0x00, /* TSFlags */
3362 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3363 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3364 .SuperClasses: GR32_DCSuperclasses, .SuperClassesSize: 15,
3365 .OrderFunc: nullptr
3366 };
3367
3368 extern const TargetRegisterClass GR32_DIBPRegClass = {
3369 .MC: &X86MCRegisterClasses[GR32_DIBPRegClassID],
3370 .SubClassMask: GR32_DIBPSubClassMask,
3371 .SuperRegIndices: SuperRegIdxSeqs + 7,
3372 .LaneMask: LaneBitmask(0x000000000000000F),
3373 .AllocationPriority: 0,
3374 .GlobalPriority: false,
3375 .TSFlags: 0x00, /* TSFlags */
3376 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3377 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3378 .SuperClasses: GR32_DIBPSuperclasses, .SuperClassesSize: 11,
3379 .OrderFunc: nullptr
3380 };
3381
3382 extern const TargetRegisterClass GR32_SIDIRegClass = {
3383 .MC: &X86MCRegisterClasses[GR32_SIDIRegClassID],
3384 .SubClassMask: GR32_SIDISubClassMask,
3385 .SuperRegIndices: SuperRegIdxSeqs + 7,
3386 .LaneMask: LaneBitmask(0x000000000000000F),
3387 .AllocationPriority: 0,
3388 .GlobalPriority: false,
3389 .TSFlags: 0x00, /* TSFlags */
3390 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3391 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3392 .SuperClasses: GR32_SIDISuperclasses, .SuperClassesSize: 11,
3393 .OrderFunc: nullptr
3394 };
3395
3396 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass = {
3397 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID],
3398 .SubClassMask: LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask,
3399 .SuperRegIndices: SuperRegIdxSeqs + 1,
3400 .LaneMask: LaneBitmask(0x000000000000000F),
3401 .AllocationPriority: 0,
3402 .GlobalPriority: false,
3403 .TSFlags: 0x00, /* TSFlags */
3404 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3405 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3406 .SuperClasses: LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses, .SuperClassesSize: 1,
3407 .OrderFunc: nullptr
3408 };
3409
3410 extern const TargetRegisterClass CCRRegClass = {
3411 .MC: &X86MCRegisterClasses[CCRRegClassID],
3412 .SubClassMask: CCRSubClassMask,
3413 .SuperRegIndices: SuperRegIdxSeqs + 1,
3414 .LaneMask: LaneBitmask(0x0000000000000001),
3415 .AllocationPriority: 0,
3416 .GlobalPriority: false,
3417 .TSFlags: 0x00, /* TSFlags */
3418 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3419 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3420 .SuperClasses: nullptr, .SuperClassesSize: 0,
3421 .OrderFunc: nullptr
3422 };
3423
3424 extern const TargetRegisterClass DFCCRRegClass = {
3425 .MC: &X86MCRegisterClasses[DFCCRRegClassID],
3426 .SubClassMask: DFCCRSubClassMask,
3427 .SuperRegIndices: SuperRegIdxSeqs + 1,
3428 .LaneMask: LaneBitmask(0x0000000000000001),
3429 .AllocationPriority: 0,
3430 .GlobalPriority: false,
3431 .TSFlags: 0x00, /* TSFlags */
3432 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3433 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3434 .SuperClasses: nullptr, .SuperClassesSize: 0,
3435 .OrderFunc: nullptr
3436 };
3437
3438 extern const TargetRegisterClass GR32_ABCD_and_GR32_BSIRegClass = {
3439 .MC: &X86MCRegisterClasses[GR32_ABCD_and_GR32_BSIRegClassID],
3440 .SubClassMask: GR32_ABCD_and_GR32_BSISubClassMask,
3441 .SuperRegIndices: SuperRegIdxSeqs + 7,
3442 .LaneMask: LaneBitmask(0x000000000000000F),
3443 .AllocationPriority: 0,
3444 .GlobalPriority: false,
3445 .TSFlags: 0x00, /* TSFlags */
3446 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3447 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3448 .SuperClasses: GR32_ABCD_and_GR32_BSISuperclasses, .SuperClassesSize: 14,
3449 .OrderFunc: nullptr
3450 };
3451
3452 extern const TargetRegisterClass GR32_AD_and_GR32_ArgRefRegClass = {
3453 .MC: &X86MCRegisterClasses[GR32_AD_and_GR32_ArgRefRegClassID],
3454 .SubClassMask: GR32_AD_and_GR32_ArgRefSubClassMask,
3455 .SuperRegIndices: SuperRegIdxSeqs + 7,
3456 .LaneMask: LaneBitmask(0x000000000000000F),
3457 .AllocationPriority: 0,
3458 .GlobalPriority: false,
3459 .TSFlags: 0x00, /* TSFlags */
3460 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3461 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3462 .SuperClasses: GR32_AD_and_GR32_ArgRefSuperclasses, .SuperClassesSize: 17,
3463 .OrderFunc: nullptr
3464 };
3465
3466 extern const TargetRegisterClass GR32_ArgRef_and_GR32_CBRegClass = {
3467 .MC: &X86MCRegisterClasses[GR32_ArgRef_and_GR32_CBRegClassID],
3468 .SubClassMask: GR32_ArgRef_and_GR32_CBSubClassMask,
3469 .SuperRegIndices: SuperRegIdxSeqs + 7,
3470 .LaneMask: LaneBitmask(0x000000000000000F),
3471 .AllocationPriority: 0,
3472 .GlobalPriority: false,
3473 .TSFlags: 0x00, /* TSFlags */
3474 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3475 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3476 .SuperClasses: GR32_ArgRef_and_GR32_CBSuperclasses, .SuperClassesSize: 17,
3477 .OrderFunc: nullptr
3478 };
3479
3480 extern const TargetRegisterClass GR32_BPSP_and_GR32_DIBPRegClass = {
3481 .MC: &X86MCRegisterClasses[GR32_BPSP_and_GR32_DIBPRegClassID],
3482 .SubClassMask: GR32_BPSP_and_GR32_DIBPSubClassMask,
3483 .SuperRegIndices: SuperRegIdxSeqs + 7,
3484 .LaneMask: LaneBitmask(0x000000000000000F),
3485 .AllocationPriority: 0,
3486 .GlobalPriority: false,
3487 .TSFlags: 0x00, /* TSFlags */
3488 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3489 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3490 .SuperClasses: GR32_BPSP_and_GR32_DIBPSuperclasses, .SuperClassesSize: 13,
3491 .OrderFunc: nullptr
3492 };
3493
3494 extern const TargetRegisterClass GR32_BPSP_and_GR32_TCRegClass = {
3495 .MC: &X86MCRegisterClasses[GR32_BPSP_and_GR32_TCRegClassID],
3496 .SubClassMask: GR32_BPSP_and_GR32_TCSubClassMask,
3497 .SuperRegIndices: SuperRegIdxSeqs + 7,
3498 .LaneMask: LaneBitmask(0x000000000000000F),
3499 .AllocationPriority: 0,
3500 .GlobalPriority: false,
3501 .TSFlags: 0x00, /* TSFlags */
3502 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3503 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3504 .SuperClasses: GR32_BPSP_and_GR32_TCSuperclasses, .SuperClassesSize: 10,
3505 .OrderFunc: nullptr
3506 };
3507
3508 extern const TargetRegisterClass GR32_BSI_and_GR32_SIDIRegClass = {
3509 .MC: &X86MCRegisterClasses[GR32_BSI_and_GR32_SIDIRegClassID],
3510 .SubClassMask: GR32_BSI_and_GR32_SIDISubClassMask,
3511 .SuperRegIndices: SuperRegIdxSeqs + 7,
3512 .LaneMask: LaneBitmask(0x000000000000000F),
3513 .AllocationPriority: 0,
3514 .GlobalPriority: false,
3515 .TSFlags: 0x00, /* TSFlags */
3516 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3517 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3518 .SuperClasses: GR32_BSI_and_GR32_SIDISuperclasses, .SuperClassesSize: 13,
3519 .OrderFunc: nullptr
3520 };
3521
3522 extern const TargetRegisterClass GR32_DIBP_and_GR32_SIDIRegClass = {
3523 .MC: &X86MCRegisterClasses[GR32_DIBP_and_GR32_SIDIRegClassID],
3524 .SubClassMask: GR32_DIBP_and_GR32_SIDISubClassMask,
3525 .SuperRegIndices: SuperRegIdxSeqs + 7,
3526 .LaneMask: LaneBitmask(0x000000000000000F),
3527 .AllocationPriority: 0,
3528 .GlobalPriority: false,
3529 .TSFlags: 0x00, /* TSFlags */
3530 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3531 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3532 .SuperClasses: GR32_DIBP_and_GR32_SIDISuperclasses, .SuperClassesSize: 13,
3533 .OrderFunc: nullptr
3534 };
3535
3536 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass = {
3537 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID],
3538 .SubClassMask: LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask,
3539 .SuperRegIndices: SuperRegIdxSeqs + 1,
3540 .LaneMask: LaneBitmask(0x000000000000000F),
3541 .AllocationPriority: 0,
3542 .GlobalPriority: false,
3543 .TSFlags: 0x00, /* TSFlags */
3544 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3545 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3546 .SuperClasses: LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses, .SuperClassesSize: 5,
3547 .OrderFunc: nullptr
3548 };
3549
3550 extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass = {
3551 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESS_with_sub_32bitRegClassID],
3552 .SubClassMask: LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask,
3553 .SuperRegIndices: SuperRegIdxSeqs + 1,
3554 .LaneMask: LaneBitmask(0x000000000000000F),
3555 .AllocationPriority: 0,
3556 .GlobalPriority: false,
3557 .TSFlags: 0x00, /* TSFlags */
3558 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3559 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3560 .SuperClasses: LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses, .SuperClassesSize: 3,
3561 .OrderFunc: nullptr
3562 };
3563
3564 extern const TargetRegisterClass RFP64RegClass = {
3565 .MC: &X86MCRegisterClasses[RFP64RegClassID],
3566 .SubClassMask: RFP64SubClassMask,
3567 .SuperRegIndices: SuperRegIdxSeqs + 1,
3568 .LaneMask: LaneBitmask(0x0000000000000001),
3569 .AllocationPriority: 0,
3570 .GlobalPriority: false,
3571 .TSFlags: 0x00, /* TSFlags */
3572 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3573 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3574 .SuperClasses: RFP64Superclasses, .SuperClassesSize: 1,
3575 .OrderFunc: nullptr
3576 };
3577
3578 extern const TargetRegisterClass GR64RegClass = {
3579 .MC: &X86MCRegisterClasses[GR64RegClassID],
3580 .SubClassMask: GR64SubClassMask,
3581 .SuperRegIndices: SuperRegIdxSeqs + 1,
3582 .LaneMask: LaneBitmask(0x000000000000000F),
3583 .AllocationPriority: 0,
3584 .GlobalPriority: false,
3585 .TSFlags: 0x00, /* TSFlags */
3586 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3587 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3588 .SuperClasses: nullptr, .SuperClassesSize: 0,
3589 .OrderFunc: nullptr
3590 };
3591
3592 extern const TargetRegisterClass FR64XRegClass = {
3593 .MC: &X86MCRegisterClasses[FR64XRegClassID],
3594 .SubClassMask: FR64XSubClassMask,
3595 .SuperRegIndices: SuperRegIdxSeqs + 12,
3596 .LaneMask: LaneBitmask(0x0000000000000001),
3597 .AllocationPriority: 0,
3598 .GlobalPriority: false,
3599 .TSFlags: 0x00, /* TSFlags */
3600 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3601 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3602 .SuperClasses: FR64XSuperclasses, .SuperClassesSize: 2,
3603 .OrderFunc: FR64XGetRawAllocationOrder
3604 };
3605
3606 extern const TargetRegisterClass GR64_with_sub_8bitRegClass = {
3607 .MC: &X86MCRegisterClasses[GR64_with_sub_8bitRegClassID],
3608 .SubClassMask: GR64_with_sub_8bitSubClassMask,
3609 .SuperRegIndices: SuperRegIdxSeqs + 1,
3610 .LaneMask: LaneBitmask(0x000000000000000F),
3611 .AllocationPriority: 0,
3612 .GlobalPriority: false,
3613 .TSFlags: 0x00, /* TSFlags */
3614 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3615 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3616 .SuperClasses: GR64_with_sub_8bitSuperclasses, .SuperClassesSize: 1,
3617 .OrderFunc: nullptr
3618 };
3619
3620 extern const TargetRegisterClass GR64_NOSPRegClass = {
3621 .MC: &X86MCRegisterClasses[GR64_NOSPRegClassID],
3622 .SubClassMask: GR64_NOSPSubClassMask,
3623 .SuperRegIndices: SuperRegIdxSeqs + 1,
3624 .LaneMask: LaneBitmask(0x000000000000000F),
3625 .AllocationPriority: 0,
3626 .GlobalPriority: false,
3627 .TSFlags: 0x00, /* TSFlags */
3628 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3629 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3630 .SuperClasses: GR64_NOSPSuperclasses, .SuperClassesSize: 2,
3631 .OrderFunc: nullptr
3632 };
3633
3634 extern const TargetRegisterClass GR64_NOREX2RegClass = {
3635 .MC: &X86MCRegisterClasses[GR64_NOREX2RegClassID],
3636 .SubClassMask: GR64_NOREX2SubClassMask,
3637 .SuperRegIndices: SuperRegIdxSeqs + 1,
3638 .LaneMask: LaneBitmask(0x000000000000000F),
3639 .AllocationPriority: 0,
3640 .GlobalPriority: false,
3641 .TSFlags: 0x00, /* TSFlags */
3642 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3643 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3644 .SuperClasses: GR64_NOREX2Superclasses, .SuperClassesSize: 1,
3645 .OrderFunc: nullptr
3646 };
3647
3648 extern const TargetRegisterClass CONTROL_REGRegClass = {
3649 .MC: &X86MCRegisterClasses[CONTROL_REGRegClassID],
3650 .SubClassMask: CONTROL_REGSubClassMask,
3651 .SuperRegIndices: SuperRegIdxSeqs + 1,
3652 .LaneMask: LaneBitmask(0x0000000000000001),
3653 .AllocationPriority: 0,
3654 .GlobalPriority: false,
3655 .TSFlags: 0x00, /* TSFlags */
3656 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3657 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3658 .SuperClasses: nullptr, .SuperClassesSize: 0,
3659 .OrderFunc: nullptr
3660 };
3661
3662 extern const TargetRegisterClass FR64RegClass = {
3663 .MC: &X86MCRegisterClasses[FR64RegClassID],
3664 .SubClassMask: FR64SubClassMask,
3665 .SuperRegIndices: SuperRegIdxSeqs + 12,
3666 .LaneMask: LaneBitmask(0x0000000000000001),
3667 .AllocationPriority: 0,
3668 .GlobalPriority: false,
3669 .TSFlags: 0x00, /* TSFlags */
3670 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3671 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3672 .SuperClasses: FR64Superclasses, .SuperClassesSize: 5,
3673 .OrderFunc: nullptr
3674 };
3675
3676 extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREX2RegClass = {
3677 .MC: &X86MCRegisterClasses[GR64_with_sub_16bit_in_GR16_NOREX2RegClassID],
3678 .SubClassMask: GR64_with_sub_16bit_in_GR16_NOREX2SubClassMask,
3679 .SuperRegIndices: SuperRegIdxSeqs + 1,
3680 .LaneMask: LaneBitmask(0x000000000000000F),
3681 .AllocationPriority: 0,
3682 .GlobalPriority: false,
3683 .TSFlags: 0x00, /* TSFlags */
3684 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3685 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3686 .SuperClasses: GR64_with_sub_16bit_in_GR16_NOREX2Superclasses, .SuperClassesSize: 3,
3687 .OrderFunc: nullptr
3688 };
3689
3690 extern const TargetRegisterClass GR64_NOREX2_NOSPRegClass = {
3691 .MC: &X86MCRegisterClasses[GR64_NOREX2_NOSPRegClassID],
3692 .SubClassMask: GR64_NOREX2_NOSPSubClassMask,
3693 .SuperRegIndices: SuperRegIdxSeqs + 1,
3694 .LaneMask: LaneBitmask(0x000000000000000F),
3695 .AllocationPriority: 0,
3696 .GlobalPriority: false,
3697 .TSFlags: 0x00, /* TSFlags */
3698 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3699 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3700 .SuperClasses: GR64_NOREX2_NOSPSuperclasses, .SuperClassesSize: 5,
3701 .OrderFunc: nullptr
3702 };
3703
3704 extern const TargetRegisterClass GR64PLTSafeRegClass = {
3705 .MC: &X86MCRegisterClasses[GR64PLTSafeRegClassID],
3706 .SubClassMask: GR64PLTSafeSubClassMask,
3707 .SuperRegIndices: SuperRegIdxSeqs + 1,
3708 .LaneMask: LaneBitmask(0x000000000000000F),
3709 .AllocationPriority: 0,
3710 .GlobalPriority: false,
3711 .TSFlags: 0x00, /* TSFlags */
3712 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3713 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3714 .SuperClasses: GR64PLTSafeSuperclasses, .SuperClassesSize: 6,
3715 .OrderFunc: nullptr
3716 };
3717
3718 extern const TargetRegisterClass GR64_TCRegClass = {
3719 .MC: &X86MCRegisterClasses[GR64_TCRegClassID],
3720 .SubClassMask: GR64_TCSubClassMask,
3721 .SuperRegIndices: SuperRegIdxSeqs + 1,
3722 .LaneMask: LaneBitmask(0x000000000000000F),
3723 .AllocationPriority: 0,
3724 .GlobalPriority: false,
3725 .TSFlags: 0x00, /* TSFlags */
3726 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3727 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3728 .SuperClasses: GR64_TCSuperclasses, .SuperClassesSize: 2,
3729 .OrderFunc: nullptr
3730 };
3731
3732 extern const TargetRegisterClass GR64_NOREXRegClass = {
3733 .MC: &X86MCRegisterClasses[GR64_NOREXRegClassID],
3734 .SubClassMask: GR64_NOREXSubClassMask,
3735 .SuperRegIndices: SuperRegIdxSeqs + 1,
3736 .LaneMask: LaneBitmask(0x000000000000000F),
3737 .AllocationPriority: 0,
3738 .GlobalPriority: false,
3739 .TSFlags: 0x00, /* TSFlags */
3740 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3741 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3742 .SuperClasses: GR64_NOREXSuperclasses, .SuperClassesSize: 2,
3743 .OrderFunc: nullptr
3744 };
3745
3746 extern const TargetRegisterClass GR64_TCW64RegClass = {
3747 .MC: &X86MCRegisterClasses[GR64_TCW64RegClassID],
3748 .SubClassMask: GR64_TCW64SubClassMask,
3749 .SuperRegIndices: SuperRegIdxSeqs + 1,
3750 .LaneMask: LaneBitmask(0x000000000000000F),
3751 .AllocationPriority: 0,
3752 .GlobalPriority: false,
3753 .TSFlags: 0x00, /* TSFlags */
3754 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3755 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3756 .SuperClasses: GR64_TCW64Superclasses, .SuperClassesSize: 2,
3757 .OrderFunc: nullptr
3758 };
3759
3760 extern const TargetRegisterClass GR64_TC_with_sub_8bitRegClass = {
3761 .MC: &X86MCRegisterClasses[GR64_TC_with_sub_8bitRegClassID],
3762 .SubClassMask: GR64_TC_with_sub_8bitSubClassMask,
3763 .SuperRegIndices: SuperRegIdxSeqs + 1,
3764 .LaneMask: LaneBitmask(0x000000000000000F),
3765 .AllocationPriority: 0,
3766 .GlobalPriority: false,
3767 .TSFlags: 0x00, /* TSFlags */
3768 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3769 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3770 .SuperClasses: GR64_TC_with_sub_8bitSuperclasses, .SuperClassesSize: 5,
3771 .OrderFunc: nullptr
3772 };
3773
3774 extern const TargetRegisterClass GR64_NOREX2_NOSP_and_GR64_TCRegClass = {
3775 .MC: &X86MCRegisterClasses[GR64_NOREX2_NOSP_and_GR64_TCRegClassID],
3776 .SubClassMask: GR64_NOREX2_NOSP_and_GR64_TCSubClassMask,
3777 .SuperRegIndices: SuperRegIdxSeqs + 1,
3778 .LaneMask: LaneBitmask(0x000000000000000F),
3779 .AllocationPriority: 0,
3780 .GlobalPriority: false,
3781 .TSFlags: 0x00, /* TSFlags */
3782 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3783 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3784 .SuperClasses: GR64_NOREX2_NOSP_and_GR64_TCSuperclasses, .SuperClassesSize: 8,
3785 .OrderFunc: nullptr
3786 };
3787
3788 extern const TargetRegisterClass GR64_TCW64_with_sub_8bitRegClass = {
3789 .MC: &X86MCRegisterClasses[GR64_TCW64_with_sub_8bitRegClassID],
3790 .SubClassMask: GR64_TCW64_with_sub_8bitSubClassMask,
3791 .SuperRegIndices: SuperRegIdxSeqs + 1,
3792 .LaneMask: LaneBitmask(0x000000000000000F),
3793 .AllocationPriority: 0,
3794 .GlobalPriority: false,
3795 .TSFlags: 0x00, /* TSFlags */
3796 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3797 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3798 .SuperClasses: GR64_TCW64_with_sub_8bitSuperclasses, .SuperClassesSize: 5,
3799 .OrderFunc: nullptr
3800 };
3801
3802 extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass = {
3803 .MC: &X86MCRegisterClasses[GR64_TC_and_GR64_TCW64RegClassID],
3804 .SubClassMask: GR64_TC_and_GR64_TCW64SubClassMask,
3805 .SuperRegIndices: SuperRegIdxSeqs + 1,
3806 .LaneMask: LaneBitmask(0x000000000000000F),
3807 .AllocationPriority: 0,
3808 .GlobalPriority: false,
3809 .TSFlags: 0x00, /* TSFlags */
3810 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3811 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3812 .SuperClasses: GR64_TC_and_GR64_TCW64Superclasses, .SuperClassesSize: 4,
3813 .OrderFunc: nullptr
3814 };
3815
3816 extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass = {
3817 .MC: &X86MCRegisterClasses[GR64_with_sub_16bit_in_GR16_NOREXRegClassID],
3818 .SubClassMask: GR64_with_sub_16bit_in_GR16_NOREXSubClassMask,
3819 .SuperRegIndices: SuperRegIdxSeqs + 1,
3820 .LaneMask: LaneBitmask(0x000000000000000F),
3821 .AllocationPriority: 0,
3822 .GlobalPriority: false,
3823 .TSFlags: 0x00, /* TSFlags */
3824 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3825 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3826 .SuperClasses: GR64_with_sub_16bit_in_GR16_NOREXSuperclasses, .SuperClassesSize: 5,
3827 .OrderFunc: nullptr
3828 };
3829
3830 extern const TargetRegisterClass VK64RegClass = {
3831 .MC: &X86MCRegisterClasses[VK64RegClassID],
3832 .SubClassMask: VK64SubClassMask,
3833 .SuperRegIndices: SuperRegIdxSeqs + 9,
3834 .LaneMask: LaneBitmask(0x0000000000000001),
3835 .AllocationPriority: 0,
3836 .GlobalPriority: false,
3837 .TSFlags: 0x00, /* TSFlags */
3838 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3839 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3840 .SuperClasses: VK64Superclasses, .SuperClassesSize: 6,
3841 .OrderFunc: nullptr
3842 };
3843
3844 extern const TargetRegisterClass VR64RegClass = {
3845 .MC: &X86MCRegisterClasses[VR64RegClassID],
3846 .SubClassMask: VR64SubClassMask,
3847 .SuperRegIndices: SuperRegIdxSeqs + 1,
3848 .LaneMask: LaneBitmask(0x0000000000000001),
3849 .AllocationPriority: 0,
3850 .GlobalPriority: false,
3851 .TSFlags: 0x00, /* TSFlags */
3852 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3853 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3854 .SuperClasses: nullptr, .SuperClassesSize: 0,
3855 .OrderFunc: nullptr
3856 };
3857
3858 extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCRegClass = {
3859 .MC: &X86MCRegisterClasses[GR64PLTSafe_and_GR64_TCRegClassID],
3860 .SubClassMask: GR64PLTSafe_and_GR64_TCSubClassMask,
3861 .SuperRegIndices: SuperRegIdxSeqs + 1,
3862 .LaneMask: LaneBitmask(0x000000000000000F),
3863 .AllocationPriority: 0,
3864 .GlobalPriority: false,
3865 .TSFlags: 0x00, /* TSFlags */
3866 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3867 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3868 .SuperClasses: GR64PLTSafe_and_GR64_TCSuperclasses, .SuperClassesSize: 10,
3869 .OrderFunc: nullptr
3870 };
3871
3872 extern const TargetRegisterClass GR64_NOREX2_NOSP_and_GR64_TCW64RegClass = {
3873 .MC: &X86MCRegisterClasses[GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID],
3874 .SubClassMask: GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask,
3875 .SuperRegIndices: SuperRegIdxSeqs + 1,
3876 .LaneMask: LaneBitmask(0x000000000000000F),
3877 .AllocationPriority: 0,
3878 .GlobalPriority: false,
3879 .TSFlags: 0x00, /* TSFlags */
3880 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3881 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3882 .SuperClasses: GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses, .SuperClassesSize: 8,
3883 .OrderFunc: nullptr
3884 };
3885
3886 extern const TargetRegisterClass GR64_NOREX_NOSPRegClass = {
3887 .MC: &X86MCRegisterClasses[GR64_NOREX_NOSPRegClassID],
3888 .SubClassMask: GR64_NOREX_NOSPSubClassMask,
3889 .SuperRegIndices: SuperRegIdxSeqs + 1,
3890 .LaneMask: LaneBitmask(0x000000000000000F),
3891 .AllocationPriority: 0,
3892 .GlobalPriority: false,
3893 .TSFlags: 0x00, /* TSFlags */
3894 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3895 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3896 .SuperClasses: GR64_NOREX_NOSPSuperclasses, .SuperClassesSize: 9,
3897 .OrderFunc: nullptr
3898 };
3899
3900 extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass = {
3901 .MC: &X86MCRegisterClasses[GR64_NOREX_and_GR64_TCRegClassID],
3902 .SubClassMask: GR64_NOREX_and_GR64_TCSubClassMask,
3903 .SuperRegIndices: SuperRegIdxSeqs + 1,
3904 .LaneMask: LaneBitmask(0x000000000000000F),
3905 .AllocationPriority: 0,
3906 .GlobalPriority: false,
3907 .TSFlags: 0x00, /* TSFlags */
3908 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3909 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3910 .SuperClasses: GR64_NOREX_and_GR64_TCSuperclasses, .SuperClassesSize: 4,
3911 .OrderFunc: nullptr
3912 };
3913
3914 extern const TargetRegisterClass GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass = {
3915 .MC: &X86MCRegisterClasses[GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID],
3916 .SubClassMask: GR64_TCW64_and_GR64_TC_with_sub_8bitSubClassMask,
3917 .SuperRegIndices: SuperRegIdxSeqs + 1,
3918 .LaneMask: LaneBitmask(0x000000000000000F),
3919 .AllocationPriority: 0,
3920 .GlobalPriority: false,
3921 .TSFlags: 0x00, /* TSFlags */
3922 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3923 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3924 .SuperClasses: GR64_TCW64_and_GR64_TC_with_sub_8bitSuperclasses, .SuperClassesSize: 9,
3925 .OrderFunc: nullptr
3926 };
3927
3928 extern const TargetRegisterClass VK64WMRegClass = {
3929 .MC: &X86MCRegisterClasses[VK64WMRegClassID],
3930 .SubClassMask: VK64WMSubClassMask,
3931 .SuperRegIndices: SuperRegIdxSeqs + 9,
3932 .LaneMask: LaneBitmask(0x0000000000000001),
3933 .AllocationPriority: 0,
3934 .GlobalPriority: false,
3935 .TSFlags: 0x00, /* TSFlags */
3936 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3937 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3938 .SuperClasses: VK64WMSuperclasses, .SuperClassesSize: 13,
3939 .OrderFunc: nullptr
3940 };
3941
3942 extern const TargetRegisterClass GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClass = {
3943 .MC: &X86MCRegisterClasses[GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID],
3944 .SubClassMask: GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask,
3945 .SuperRegIndices: SuperRegIdxSeqs + 1,
3946 .LaneMask: LaneBitmask(0x000000000000000F),
3947 .AllocationPriority: 0,
3948 .GlobalPriority: false,
3949 .TSFlags: 0x00, /* TSFlags */
3950 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3951 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3952 .SuperClasses: GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses, .SuperClassesSize: 14,
3953 .OrderFunc: nullptr
3954 };
3955
3956 extern const TargetRegisterClass GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass = {
3957 .MC: &X86MCRegisterClasses[GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID],
3958 .SubClassMask: GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSubClassMask,
3959 .SuperRegIndices: SuperRegIdxSeqs + 1,
3960 .LaneMask: LaneBitmask(0x000000000000000F),
3961 .AllocationPriority: 0,
3962 .GlobalPriority: false,
3963 .TSFlags: 0x00, /* TSFlags */
3964 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3965 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3966 .SuperClasses: GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSuperclasses, .SuperClassesSize: 9,
3967 .OrderFunc: nullptr
3968 };
3969
3970 extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCW64RegClass = {
3971 .MC: &X86MCRegisterClasses[GR64PLTSafe_and_GR64_TCW64RegClassID],
3972 .SubClassMask: GR64PLTSafe_and_GR64_TCW64SubClassMask,
3973 .SuperRegIndices: SuperRegIdxSeqs + 1,
3974 .LaneMask: LaneBitmask(0x000000000000000F),
3975 .AllocationPriority: 0,
3976 .GlobalPriority: false,
3977 .TSFlags: 0x00, /* TSFlags */
3978 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3979 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3980 .SuperClasses: GR64PLTSafe_and_GR64_TCW64Superclasses, .SuperClassesSize: 17,
3981 .OrderFunc: nullptr
3982 };
3983
3984 extern const TargetRegisterClass GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass = {
3985 .MC: &X86MCRegisterClasses[GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID],
3986 .SubClassMask: GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSubClassMask,
3987 .SuperRegIndices: SuperRegIdxSeqs + 1,
3988 .LaneMask: LaneBitmask(0x000000000000000F),
3989 .AllocationPriority: 0,
3990 .GlobalPriority: false,
3991 .TSFlags: 0x00, /* TSFlags */
3992 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3993 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3994 .SuperClasses: GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSuperclasses, .SuperClassesSize: 16,
3995 .OrderFunc: nullptr
3996 };
3997
3998 extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass = {
3999 .MC: &X86MCRegisterClasses[GR64_NOREX_and_GR64_TCW64RegClassID],
4000 .SubClassMask: GR64_NOREX_and_GR64_TCW64SubClassMask,
4001 .SuperRegIndices: SuperRegIdxSeqs + 1,
4002 .LaneMask: LaneBitmask(0x000000000000000F),
4003 .AllocationPriority: 0,
4004 .GlobalPriority: false,
4005 .TSFlags: 0x00, /* TSFlags */
4006 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4007 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4008 .SuperClasses: GR64_NOREX_and_GR64_TCW64Superclasses, .SuperClassesSize: 7,
4009 .OrderFunc: nullptr
4010 };
4011
4012 extern const TargetRegisterClass GR64_ABCDRegClass = {
4013 .MC: &X86MCRegisterClasses[GR64_ABCDRegClassID],
4014 .SubClassMask: GR64_ABCDSubClassMask,
4015 .SuperRegIndices: SuperRegIdxSeqs + 1,
4016 .LaneMask: LaneBitmask(0x000000000000000F),
4017 .AllocationPriority: 0,
4018 .GlobalPriority: false,
4019 .TSFlags: 0x00, /* TSFlags */
4020 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4021 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4022 .SuperClasses: GR64_ABCDSuperclasses, .SuperClassesSize: 10,
4023 .OrderFunc: nullptr
4024 };
4025
4026 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass = {
4027 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_TCRegClassID],
4028 .SubClassMask: GR64_with_sub_32bit_in_GR32_TCSubClassMask,
4029 .SuperRegIndices: SuperRegIdxSeqs + 1,
4030 .LaneMask: LaneBitmask(0x000000000000000F),
4031 .AllocationPriority: 0,
4032 .GlobalPriority: false,
4033 .TSFlags: 0x00, /* TSFlags */
4034 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4035 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4036 .SuperClasses: GR64_with_sub_32bit_in_GR32_TCSuperclasses, .SuperClassesSize: 15,
4037 .OrderFunc: nullptr
4038 };
4039
4040 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass = {
4041 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID],
4042 .SubClassMask: GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSubClassMask,
4043 .SuperRegIndices: SuperRegIdxSeqs + 1,
4044 .LaneMask: LaneBitmask(0x000000000000000F),
4045 .AllocationPriority: 0,
4046 .GlobalPriority: false,
4047 .TSFlags: 0x00, /* TSFlags */
4048 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4049 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4050 .SuperClasses: GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSuperclasses, .SuperClassesSize: 27,
4051 .OrderFunc: nullptr
4052 };
4053
4054 extern const TargetRegisterClass GR64_ADRegClass = {
4055 .MC: &X86MCRegisterClasses[GR64_ADRegClassID],
4056 .SubClassMask: GR64_ADSubClassMask,
4057 .SuperRegIndices: SuperRegIdxSeqs + 1,
4058 .LaneMask: LaneBitmask(0x000000000000000F),
4059 .AllocationPriority: 0,
4060 .GlobalPriority: false,
4061 .TSFlags: 0x00, /* TSFlags */
4062 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4063 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4064 .SuperClasses: GR64_ADSuperclasses, .SuperClassesSize: 28,
4065 .OrderFunc: nullptr
4066 };
4067
4068 extern const TargetRegisterClass GR64_ArgRefRegClass = {
4069 .MC: &X86MCRegisterClasses[GR64_ArgRefRegClassID],
4070 .SubClassMask: GR64_ArgRefSubClassMask,
4071 .SuperRegIndices: SuperRegIdxSeqs + 1,
4072 .LaneMask: LaneBitmask(0x000000000000000F),
4073 .AllocationPriority: 0,
4074 .GlobalPriority: false,
4075 .TSFlags: 0x00, /* TSFlags */
4076 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4077 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4078 .SuperClasses: GR64_ArgRefSuperclasses, .SuperClassesSize: 9,
4079 .OrderFunc: nullptr
4080 };
4081
4082 extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass = {
4083 .MC: &X86MCRegisterClasses[GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID],
4084 .SubClassMask: GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask,
4085 .SuperRegIndices: SuperRegIdxSeqs + 1,
4086 .LaneMask: LaneBitmask(0x000000000000000F),
4087 .AllocationPriority: 0,
4088 .GlobalPriority: false,
4089 .TSFlags: 0x00, /* TSFlags */
4090 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4091 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4092 .SuperClasses: GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses, .SuperClassesSize: 5,
4093 .OrderFunc: nullptr
4094 };
4095
4096 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ArgRefRegClass = {
4097 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ArgRefRegClassID],
4098 .SubClassMask: GR64_with_sub_32bit_in_GR32_ArgRefSubClassMask,
4099 .SuperRegIndices: SuperRegIdxSeqs + 1,
4100 .LaneMask: LaneBitmask(0x000000000000000F),
4101 .AllocationPriority: 0,
4102 .GlobalPriority: false,
4103 .TSFlags: 0x00, /* TSFlags */
4104 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4105 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4106 .SuperClasses: GR64_with_sub_32bit_in_GR32_ArgRefSuperclasses, .SuperClassesSize: 28,
4107 .OrderFunc: nullptr
4108 };
4109
4110 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSPRegClass = {
4111 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSPRegClassID],
4112 .SubClassMask: GR64_with_sub_32bit_in_GR32_BPSPSubClassMask,
4113 .SuperRegIndices: SuperRegIdxSeqs + 1,
4114 .LaneMask: LaneBitmask(0x000000000000000F),
4115 .AllocationPriority: 0,
4116 .GlobalPriority: false,
4117 .TSFlags: 0x00, /* TSFlags */
4118 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4119 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4120 .SuperClasses: GR64_with_sub_32bit_in_GR32_BPSPSuperclasses, .SuperClassesSize: 6,
4121 .OrderFunc: nullptr
4122 };
4123
4124 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSIRegClass = {
4125 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BSIRegClassID],
4126 .SubClassMask: GR64_with_sub_32bit_in_GR32_BSISubClassMask,
4127 .SuperRegIndices: SuperRegIdxSeqs + 1,
4128 .LaneMask: LaneBitmask(0x000000000000000F),
4129 .AllocationPriority: 0,
4130 .GlobalPriority: false,
4131 .TSFlags: 0x00, /* TSFlags */
4132 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4133 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4134 .SuperClasses: GR64_with_sub_32bit_in_GR32_BSISuperclasses, .SuperClassesSize: 10,
4135 .OrderFunc: nullptr
4136 };
4137
4138 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CBRegClass = {
4139 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_CBRegClassID],
4140 .SubClassMask: GR64_with_sub_32bit_in_GR32_CBSubClassMask,
4141 .SuperRegIndices: SuperRegIdxSeqs + 1,
4142 .LaneMask: LaneBitmask(0x000000000000000F),
4143 .AllocationPriority: 0,
4144 .GlobalPriority: false,
4145 .TSFlags: 0x00, /* TSFlags */
4146 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4147 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4148 .SuperClasses: GR64_with_sub_32bit_in_GR32_CBSuperclasses, .SuperClassesSize: 11,
4149 .OrderFunc: nullptr
4150 };
4151
4152 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBPRegClass = {
4153 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DIBPRegClassID],
4154 .SubClassMask: GR64_with_sub_32bit_in_GR32_DIBPSubClassMask,
4155 .SuperRegIndices: SuperRegIdxSeqs + 1,
4156 .LaneMask: LaneBitmask(0x000000000000000F),
4157 .AllocationPriority: 0,
4158 .GlobalPriority: false,
4159 .TSFlags: 0x00, /* TSFlags */
4160 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4161 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4162 .SuperClasses: GR64_with_sub_32bit_in_GR32_DIBPSuperclasses, .SuperClassesSize: 10,
4163 .OrderFunc: nullptr
4164 };
4165
4166 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_SIDIRegClass = {
4167 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_SIDIRegClassID],
4168 .SubClassMask: GR64_with_sub_32bit_in_GR32_SIDISubClassMask,
4169 .SuperRegIndices: SuperRegIdxSeqs + 1,
4170 .LaneMask: LaneBitmask(0x000000000000000F),
4171 .AllocationPriority: 0,
4172 .GlobalPriority: false,
4173 .TSFlags: 0x00, /* TSFlags */
4174 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4175 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4176 .SuperClasses: GR64_with_sub_32bit_in_GR32_SIDISuperclasses, .SuperClassesSize: 17,
4177 .OrderFunc: nullptr
4178 };
4179
4180 extern const TargetRegisterClass GR64_ARegClass = {
4181 .MC: &X86MCRegisterClasses[GR64_ARegClassID],
4182 .SubClassMask: GR64_ASubClassMask,
4183 .SuperRegIndices: SuperRegIdxSeqs + 1,
4184 .LaneMask: LaneBitmask(0x000000000000000F),
4185 .AllocationPriority: 0,
4186 .GlobalPriority: false,
4187 .TSFlags: 0x00, /* TSFlags */
4188 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4189 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4190 .SuperClasses: GR64_ASuperclasses, .SuperClassesSize: 29,
4191 .OrderFunc: nullptr
4192 };
4193
4194 extern const TargetRegisterClass GR64_ArgRef_and_GR64_TCRegClass = {
4195 .MC: &X86MCRegisterClasses[GR64_ArgRef_and_GR64_TCRegClassID],
4196 .SubClassMask: GR64_ArgRef_and_GR64_TCSubClassMask,
4197 .SuperRegIndices: SuperRegIdxSeqs + 1,
4198 .LaneMask: LaneBitmask(0x000000000000000F),
4199 .AllocationPriority: 0,
4200 .GlobalPriority: false,
4201 .TSFlags: 0x00, /* TSFlags */
4202 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4203 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4204 .SuperClasses: GR64_ArgRef_and_GR64_TCSuperclasses, .SuperClassesSize: 16,
4205 .OrderFunc: nullptr
4206 };
4207
4208 extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass = {
4209 .MC: &X86MCRegisterClasses[GR64_and_LOW32_ADDR_ACCESSRegClassID],
4210 .SubClassMask: GR64_and_LOW32_ADDR_ACCESSSubClassMask,
4211 .SuperRegIndices: SuperRegIdxSeqs + 1,
4212 .LaneMask: LaneBitmask(0x000000000000000F),
4213 .AllocationPriority: 0,
4214 .GlobalPriority: false,
4215 .TSFlags: 0x00, /* TSFlags */
4216 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4217 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4218 .SuperClasses: GR64_and_LOW32_ADDR_ACCESSSuperclasses, .SuperClassesSize: 13,
4219 .OrderFunc: nullptr
4220 };
4221
4222 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass = {
4223 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID],
4224 .SubClassMask: GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask,
4225 .SuperRegIndices: SuperRegIdxSeqs + 1,
4226 .LaneMask: LaneBitmask(0x000000000000000F),
4227 .AllocationPriority: 0,
4228 .GlobalPriority: false,
4229 .TSFlags: 0x00, /* TSFlags */
4230 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4231 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4232 .SuperClasses: GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISuperclasses, .SuperClassesSize: 13,
4233 .OrderFunc: nullptr
4234 };
4235
4236 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClass = {
4237 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID],
4238 .SubClassMask: GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSubClassMask,
4239 .SuperRegIndices: SuperRegIdxSeqs + 1,
4240 .LaneMask: LaneBitmask(0x000000000000000F),
4241 .AllocationPriority: 0,
4242 .GlobalPriority: false,
4243 .TSFlags: 0x00, /* TSFlags */
4244 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4245 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4246 .SuperClasses: GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSuperclasses, .SuperClassesSize: 30,
4247 .OrderFunc: nullptr
4248 };
4249
4250 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClass = {
4251 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID],
4252 .SubClassMask: GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSubClassMask,
4253 .SuperRegIndices: SuperRegIdxSeqs + 1,
4254 .LaneMask: LaneBitmask(0x000000000000000F),
4255 .AllocationPriority: 0,
4256 .GlobalPriority: false,
4257 .TSFlags: 0x00, /* TSFlags */
4258 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4259 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4260 .SuperClasses: GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSuperclasses, .SuperClassesSize: 30,
4261 .OrderFunc: nullptr
4262 };
4263
4264 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass = {
4265 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID],
4266 .SubClassMask: GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask,
4267 .SuperRegIndices: SuperRegIdxSeqs + 1,
4268 .LaneMask: LaneBitmask(0x000000000000000F),
4269 .AllocationPriority: 0,
4270 .GlobalPriority: false,
4271 .TSFlags: 0x00, /* TSFlags */
4272 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4273 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4274 .SuperClasses: GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSuperclasses, .SuperClassesSize: 19,
4275 .OrderFunc: nullptr
4276 };
4277
4278 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass = {
4279 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID],
4280 .SubClassMask: GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSubClassMask,
4281 .SuperRegIndices: SuperRegIdxSeqs + 1,
4282 .LaneMask: LaneBitmask(0x000000000000000F),
4283 .AllocationPriority: 0,
4284 .GlobalPriority: false,
4285 .TSFlags: 0x00, /* TSFlags */
4286 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4287 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4288 .SuperClasses: GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSuperclasses, .SuperClassesSize: 17,
4289 .OrderFunc: nullptr
4290 };
4291
4292 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass = {
4293 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID],
4294 .SubClassMask: GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask,
4295 .SuperRegIndices: SuperRegIdxSeqs + 1,
4296 .LaneMask: LaneBitmask(0x000000000000000F),
4297 .AllocationPriority: 0,
4298 .GlobalPriority: false,
4299 .TSFlags: 0x00, /* TSFlags */
4300 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4301 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4302 .SuperClasses: GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISuperclasses, .SuperClassesSize: 19,
4303 .OrderFunc: nullptr
4304 };
4305
4306 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass = {
4307 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID],
4308 .SubClassMask: GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask,
4309 .SuperRegIndices: SuperRegIdxSeqs + 1,
4310 .LaneMask: LaneBitmask(0x000000000000000F),
4311 .AllocationPriority: 0,
4312 .GlobalPriority: false,
4313 .TSFlags: 0x00, /* TSFlags */
4314 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4315 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4316 .SuperClasses: GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISuperclasses, .SuperClassesSize: 19,
4317 .OrderFunc: nullptr
4318 };
4319
4320 extern const TargetRegisterClass RSTRegClass = {
4321 .MC: &X86MCRegisterClasses[RSTRegClassID],
4322 .SubClassMask: RSTSubClassMask,
4323 .SuperRegIndices: SuperRegIdxSeqs + 1,
4324 .LaneMask: LaneBitmask(0x0000000000000001),
4325 .AllocationPriority: 0,
4326 .GlobalPriority: false,
4327 .TSFlags: 0x00, /* TSFlags */
4328 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4329 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4330 .SuperClasses: nullptr, .SuperClassesSize: 0,
4331 .OrderFunc: nullptr
4332 };
4333
4334 extern const TargetRegisterClass RFP80RegClass = {
4335 .MC: &X86MCRegisterClasses[RFP80RegClassID],
4336 .SubClassMask: RFP80SubClassMask,
4337 .SuperRegIndices: SuperRegIdxSeqs + 1,
4338 .LaneMask: LaneBitmask(0x0000000000000001),
4339 .AllocationPriority: 0,
4340 .GlobalPriority: false,
4341 .TSFlags: 0x00, /* TSFlags */
4342 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4343 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4344 .SuperClasses: RFP80Superclasses, .SuperClassesSize: 2,
4345 .OrderFunc: nullptr
4346 };
4347
4348 extern const TargetRegisterClass RFP80_7RegClass = {
4349 .MC: &X86MCRegisterClasses[RFP80_7RegClassID],
4350 .SubClassMask: RFP80_7SubClassMask,
4351 .SuperRegIndices: SuperRegIdxSeqs + 1,
4352 .LaneMask: LaneBitmask(0x0000000000000001),
4353 .AllocationPriority: 0,
4354 .GlobalPriority: false,
4355 .TSFlags: 0x00, /* TSFlags */
4356 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4357 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4358 .SuperClasses: nullptr, .SuperClassesSize: 0,
4359 .OrderFunc: nullptr
4360 };
4361
4362 extern const TargetRegisterClass VR128XRegClass = {
4363 .MC: &X86MCRegisterClasses[VR128XRegClassID],
4364 .SubClassMask: VR128XSubClassMask,
4365 .SuperRegIndices: SuperRegIdxSeqs + 12,
4366 .LaneMask: LaneBitmask(0x0000000000000001),
4367 .AllocationPriority: 0,
4368 .GlobalPriority: false,
4369 .TSFlags: 0x00, /* TSFlags */
4370 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4371 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4372 .SuperClasses: VR128XSuperclasses, .SuperClassesSize: 3,
4373 .OrderFunc: VR128XGetRawAllocationOrder
4374 };
4375
4376 extern const TargetRegisterClass VR128RegClass = {
4377 .MC: &X86MCRegisterClasses[VR128RegClassID],
4378 .SubClassMask: VR128SubClassMask,
4379 .SuperRegIndices: SuperRegIdxSeqs + 12,
4380 .LaneMask: LaneBitmask(0x0000000000000001),
4381 .AllocationPriority: 0,
4382 .GlobalPriority: false,
4383 .TSFlags: 0x00, /* TSFlags */
4384 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4385 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4386 .SuperClasses: VR128Superclasses, .SuperClassesSize: 7,
4387 .OrderFunc: nullptr
4388 };
4389
4390 extern const TargetRegisterClass VR256XRegClass = {
4391 .MC: &X86MCRegisterClasses[VR256XRegClassID],
4392 .SubClassMask: VR256XSubClassMask,
4393 .SuperRegIndices: SuperRegIdxSeqs + 14,
4394 .LaneMask: LaneBitmask(0x0000000000000040),
4395 .AllocationPriority: 0,
4396 .GlobalPriority: false,
4397 .TSFlags: 0x00, /* TSFlags */
4398 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4399 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4400 .SuperClasses: nullptr, .SuperClassesSize: 0,
4401 .OrderFunc: VR256XGetRawAllocationOrder
4402 };
4403
4404 extern const TargetRegisterClass VR256RegClass = {
4405 .MC: &X86MCRegisterClasses[VR256RegClassID],
4406 .SubClassMask: VR256SubClassMask,
4407 .SuperRegIndices: SuperRegIdxSeqs + 14,
4408 .LaneMask: LaneBitmask(0x0000000000000040),
4409 .AllocationPriority: 0,
4410 .GlobalPriority: false,
4411 .TSFlags: 0x00, /* TSFlags */
4412 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4413 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4414 .SuperClasses: VR256Superclasses, .SuperClassesSize: 1,
4415 .OrderFunc: nullptr
4416 };
4417
4418 extern const TargetRegisterClass VR512RegClass = {
4419 .MC: &X86MCRegisterClasses[VR512RegClassID],
4420 .SubClassMask: VR512SubClassMask,
4421 .SuperRegIndices: SuperRegIdxSeqs + 1,
4422 .LaneMask: LaneBitmask(0x0000000000000040),
4423 .AllocationPriority: 0,
4424 .GlobalPriority: false,
4425 .TSFlags: 0x00, /* TSFlags */
4426 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4427 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4428 .SuperClasses: nullptr, .SuperClassesSize: 0,
4429 .OrderFunc: nullptr
4430 };
4431
4432 extern const TargetRegisterClass VR512_0_15RegClass = {
4433 .MC: &X86MCRegisterClasses[VR512_0_15RegClassID],
4434 .SubClassMask: VR512_0_15SubClassMask,
4435 .SuperRegIndices: SuperRegIdxSeqs + 1,
4436 .LaneMask: LaneBitmask(0x0000000000000040),
4437 .AllocationPriority: 0,
4438 .GlobalPriority: false,
4439 .TSFlags: 0x00, /* TSFlags */
4440 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4441 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4442 .SuperClasses: VR512_0_15Superclasses, .SuperClassesSize: 1,
4443 .OrderFunc: nullptr
4444 };
4445
4446 extern const TargetRegisterClass TILERegClass = {
4447 .MC: &X86MCRegisterClasses[TILERegClassID],
4448 .SubClassMask: TILESubClassMask,
4449 .SuperRegIndices: SuperRegIdxSeqs + 1,
4450 .LaneMask: LaneBitmask(0x0000000000000001),
4451 .AllocationPriority: 0,
4452 .GlobalPriority: false,
4453 .TSFlags: 0x00, /* TSFlags */
4454 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4455 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4456 .SuperClasses: nullptr, .SuperClassesSize: 0,
4457 .OrderFunc: nullptr
4458 };
4459
4460} // end namespace X86
4461
4462namespace {
4463 const TargetRegisterClass *const RegisterClasses[] = {
4464 &X86::GR8RegClass,
4465 &X86::GRH8RegClass,
4466 &X86::GR8_NOREX2RegClass,
4467 &X86::GR8_NOREXRegClass,
4468 &X86::GR8_ABCD_HRegClass,
4469 &X86::GR8_ABCD_LRegClass,
4470 &X86::GRH16RegClass,
4471 &X86::GR16RegClass,
4472 &X86::GR16_NOREX2RegClass,
4473 &X86::GR16_NOREXRegClass,
4474 &X86::VK1RegClass,
4475 &X86::VK16RegClass,
4476 &X86::VK2RegClass,
4477 &X86::VK4RegClass,
4478 &X86::VK8RegClass,
4479 &X86::VK16WMRegClass,
4480 &X86::VK1WMRegClass,
4481 &X86::VK2WMRegClass,
4482 &X86::VK4WMRegClass,
4483 &X86::VK8WMRegClass,
4484 &X86::SEGMENT_REGRegClass,
4485 &X86::GR16_ABCDRegClass,
4486 &X86::FPCCRRegClass,
4487 &X86::FR16XRegClass,
4488 &X86::FR16RegClass,
4489 &X86::VK16PAIRRegClass,
4490 &X86::VK1PAIRRegClass,
4491 &X86::VK2PAIRRegClass,
4492 &X86::VK4PAIRRegClass,
4493 &X86::VK8PAIRRegClass,
4494 &X86::VK1PAIR_with_sub_mask_0_in_VK1WMRegClass,
4495 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
4496 &X86::LOW32_ADDR_ACCESSRegClass,
4497 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
4498 &X86::FR32XRegClass,
4499 &X86::GR32RegClass,
4500 &X86::GR32_NOSPRegClass,
4501 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
4502 &X86::DEBUG_REGRegClass,
4503 &X86::FR32RegClass,
4504 &X86::GR32_NOREX2RegClass,
4505 &X86::GR32_NOREX2_NOSPRegClass,
4506 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
4507 &X86::GR32_NOREXRegClass,
4508 &X86::VK32RegClass,
4509 &X86::GR32_NOREX_NOSPRegClass,
4510 &X86::RFP32RegClass,
4511 &X86::VK32WMRegClass,
4512 &X86::GR32_ABCDRegClass,
4513 &X86::GR32_TCRegClass,
4514 &X86::GR32_ABCD_and_GR32_TCRegClass,
4515 &X86::GR32_ADRegClass,
4516 &X86::GR32_ArgRefRegClass,
4517 &X86::GR32_BPSPRegClass,
4518 &X86::GR32_BSIRegClass,
4519 &X86::GR32_CBRegClass,
4520 &X86::GR32_DCRegClass,
4521 &X86::GR32_DIBPRegClass,
4522 &X86::GR32_SIDIRegClass,
4523 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
4524 &X86::CCRRegClass,
4525 &X86::DFCCRRegClass,
4526 &X86::GR32_ABCD_and_GR32_BSIRegClass,
4527 &X86::GR32_AD_and_GR32_ArgRefRegClass,
4528 &X86::GR32_ArgRef_and_GR32_CBRegClass,
4529 &X86::GR32_BPSP_and_GR32_DIBPRegClass,
4530 &X86::GR32_BPSP_and_GR32_TCRegClass,
4531 &X86::GR32_BSI_and_GR32_SIDIRegClass,
4532 &X86::GR32_DIBP_and_GR32_SIDIRegClass,
4533 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass,
4534 &X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClass,
4535 &X86::RFP64RegClass,
4536 &X86::GR64RegClass,
4537 &X86::FR64XRegClass,
4538 &X86::GR64_with_sub_8bitRegClass,
4539 &X86::GR64_NOSPRegClass,
4540 &X86::GR64_NOREX2RegClass,
4541 &X86::CONTROL_REGRegClass,
4542 &X86::FR64RegClass,
4543 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
4544 &X86::GR64_NOREX2_NOSPRegClass,
4545 &X86::GR64PLTSafeRegClass,
4546 &X86::GR64_TCRegClass,
4547 &X86::GR64_NOREXRegClass,
4548 &X86::GR64_TCW64RegClass,
4549 &X86::GR64_TC_with_sub_8bitRegClass,
4550 &X86::GR64_NOREX2_NOSP_and_GR64_TCRegClass,
4551 &X86::GR64_TCW64_with_sub_8bitRegClass,
4552 &X86::GR64_TC_and_GR64_TCW64RegClass,
4553 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
4554 &X86::VK64RegClass,
4555 &X86::VR64RegClass,
4556 &X86::GR64PLTSafe_and_GR64_TCRegClass,
4557 &X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
4558 &X86::GR64_NOREX_NOSPRegClass,
4559 &X86::GR64_NOREX_and_GR64_TCRegClass,
4560 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
4561 &X86::VK64WMRegClass,
4562 &X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
4563 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
4564 &X86::GR64PLTSafe_and_GR64_TCW64RegClass,
4565 &X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
4566 &X86::GR64_NOREX_and_GR64_TCW64RegClass,
4567 &X86::GR64_ABCDRegClass,
4568 &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
4569 &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
4570 &X86::GR64_ADRegClass,
4571 &X86::GR64_ArgRefRegClass,
4572 &X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClass,
4573 &X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClass,
4574 &X86::GR64_with_sub_32bit_in_GR32_BPSPRegClass,
4575 &X86::GR64_with_sub_32bit_in_GR32_BSIRegClass,
4576 &X86::GR64_with_sub_32bit_in_GR32_CBRegClass,
4577 &X86::GR64_with_sub_32bit_in_GR32_DIBPRegClass,
4578 &X86::GR64_with_sub_32bit_in_GR32_SIDIRegClass,
4579 &X86::GR64_ARegClass,
4580 &X86::GR64_ArgRef_and_GR64_TCRegClass,
4581 &X86::GR64_and_LOW32_ADDR_ACCESSRegClass,
4582 &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass,
4583 &X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClass,
4584 &X86::GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClass,
4585 &X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass,
4586 &X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass,
4587 &X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass,
4588 &X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass,
4589 &X86::RSTRegClass,
4590 &X86::RFP80RegClass,
4591 &X86::RFP80_7RegClass,
4592 &X86::VR128XRegClass,
4593 &X86::VR128RegClass,
4594 &X86::VR256XRegClass,
4595 &X86::VR256RegClass,
4596 &X86::VR512RegClass,
4597 &X86::VR512_0_15RegClass,
4598 &X86::TILERegClass,
4599 };
4600} // end anonymous namespace
4601
4602static const uint8_t CostPerUseTable[] = {
46030, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
4604
4605
4606static const bool InAllocatableClassTable[] = {
4607false, true, true, true, true, true, true, false, true, true, true, true, true, true, false, true, true, false, true, true, true, true, true, true, true, true, true, true, false, false, false, true, true, true, false, false, true, false, true, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, true, false, true, true, true, false, true, true, false, true, true, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, };
4608
4609
4610static const TargetRegisterInfoDesc X86RegInfoDesc = { // Extra Descriptors
4611.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
4612
4613unsigned X86GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
4614 static const uint8_t Rows[1][10] = {
4615 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4616 };
4617
4618 --IdxA; assert(IdxA < 10); (void) IdxA;
4619 --IdxB; assert(IdxB < 10);
4620 return Rows[0][IdxB];
4621}
4622
4623unsigned X86GenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
4624 static const uint8_t Table[10][10] = {
4625 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4626 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4627 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4628 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4629 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4630 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4631 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4632 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4633 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4634 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4635 };
4636
4637 --IdxA; assert(IdxA < 10);
4638 --IdxB; assert(IdxB < 10);
4639 return Table[IdxA][IdxB];
4640 }
4641
4642 struct MaskRolOp {
4643 LaneBitmask Mask;
4644 uint8_t RotateLeft;
4645 };
4646 static const MaskRolOp LaneMaskComposeSequences[] = {
4647 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
4648 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
4649 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
4650 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 6
4651 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 4 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 8
4652 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 5 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 10
4653 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 6 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 12
4654 };
4655 static const uint8_t CompositeSequences[] = {
4656 0, // to sub_8bit
4657 2, // to sub_8bit_hi
4658 4, // to sub_8bit_hi_phony
4659 0, // to sub_16bit
4660 6, // to sub_16bit_hi
4661 0, // to sub_32bit
4662 8, // to sub_mask_0
4663 10, // to sub_mask_1
4664 12, // to sub_xmm
4665 0 // to sub_ymm
4666 };
4667
4668LaneBitmask X86GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
4669 --IdxA; assert(IdxA < 10 && "Subregister index out of bounds");
4670 LaneBitmask Result;
4671 for (const MaskRolOp *Ops =
4672 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
4673 Ops->Mask.any(); ++Ops) {
4674 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
4675 if (unsigned S = Ops->RotateLeft)
4676 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
4677 else
4678 Result |= LaneBitmask(M);
4679 }
4680 return Result;
4681}
4682
4683LaneBitmask X86GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
4684 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
4685 --IdxA; assert(IdxA < 10 && "Subregister index out of bounds");
4686 LaneBitmask Result;
4687 for (const MaskRolOp *Ops =
4688 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
4689 Ops->Mask.any(); ++Ops) {
4690 LaneBitmask::Type M = LaneMask.getAsInteger();
4691 if (unsigned S = Ops->RotateLeft)
4692 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
4693 else
4694 Result |= LaneBitmask(M);
4695 }
4696 return Result;
4697}
4698
4699const TargetRegisterClass *X86GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
4700 static const uint8_t Table[135][10] = {
4701 { // GR8
4702 0, // sub_8bit
4703 0, // sub_8bit_hi
4704 0, // sub_8bit_hi_phony
4705 0, // sub_16bit
4706 0, // sub_16bit_hi
4707 0, // sub_32bit
4708 0, // sub_mask_0
4709 0, // sub_mask_1
4710 0, // sub_xmm
4711 0, // sub_ymm
4712 },
4713 { // GRH8
4714 0, // sub_8bit
4715 0, // sub_8bit_hi
4716 0, // sub_8bit_hi_phony
4717 0, // sub_16bit
4718 0, // sub_16bit_hi
4719 0, // sub_32bit
4720 0, // sub_mask_0
4721 0, // sub_mask_1
4722 0, // sub_xmm
4723 0, // sub_ymm
4724 },
4725 { // GR8_NOREX2
4726 0, // sub_8bit
4727 0, // sub_8bit_hi
4728 0, // sub_8bit_hi_phony
4729 0, // sub_16bit
4730 0, // sub_16bit_hi
4731 0, // sub_32bit
4732 0, // sub_mask_0
4733 0, // sub_mask_1
4734 0, // sub_xmm
4735 0, // sub_ymm
4736 },
4737 { // GR8_NOREX
4738 0, // sub_8bit
4739 0, // sub_8bit_hi
4740 0, // sub_8bit_hi_phony
4741 0, // sub_16bit
4742 0, // sub_16bit_hi
4743 0, // sub_32bit
4744 0, // sub_mask_0
4745 0, // sub_mask_1
4746 0, // sub_xmm
4747 0, // sub_ymm
4748 },
4749 { // GR8_ABCD_H
4750 0, // sub_8bit
4751 0, // sub_8bit_hi
4752 0, // sub_8bit_hi_phony
4753 0, // sub_16bit
4754 0, // sub_16bit_hi
4755 0, // sub_32bit
4756 0, // sub_mask_0
4757 0, // sub_mask_1
4758 0, // sub_xmm
4759 0, // sub_ymm
4760 },
4761 { // GR8_ABCD_L
4762 0, // sub_8bit
4763 0, // sub_8bit_hi
4764 0, // sub_8bit_hi_phony
4765 0, // sub_16bit
4766 0, // sub_16bit_hi
4767 0, // sub_32bit
4768 0, // sub_mask_0
4769 0, // sub_mask_1
4770 0, // sub_xmm
4771 0, // sub_ymm
4772 },
4773 { // GRH16
4774 0, // sub_8bit
4775 0, // sub_8bit_hi
4776 0, // sub_8bit_hi_phony
4777 0, // sub_16bit
4778 0, // sub_16bit_hi
4779 0, // sub_32bit
4780 0, // sub_mask_0
4781 0, // sub_mask_1
4782 0, // sub_xmm
4783 0, // sub_ymm
4784 },
4785 { // GR16
4786 8, // sub_8bit -> GR16
4787 22, // sub_8bit_hi -> GR16_ABCD
4788 0, // sub_8bit_hi_phony
4789 0, // sub_16bit
4790 0, // sub_16bit_hi
4791 0, // sub_32bit
4792 0, // sub_mask_0
4793 0, // sub_mask_1
4794 0, // sub_xmm
4795 0, // sub_ymm
4796 },
4797 { // GR16_NOREX2
4798 9, // sub_8bit -> GR16_NOREX2
4799 22, // sub_8bit_hi -> GR16_ABCD
4800 0, // sub_8bit_hi_phony
4801 0, // sub_16bit
4802 0, // sub_16bit_hi
4803 0, // sub_32bit
4804 0, // sub_mask_0
4805 0, // sub_mask_1
4806 0, // sub_xmm
4807 0, // sub_ymm
4808 },
4809 { // GR16_NOREX
4810 10, // sub_8bit -> GR16_NOREX
4811 22, // sub_8bit_hi -> GR16_ABCD
4812 0, // sub_8bit_hi_phony
4813 0, // sub_16bit
4814 0, // sub_16bit_hi
4815 0, // sub_32bit
4816 0, // sub_mask_0
4817 0, // sub_mask_1
4818 0, // sub_xmm
4819 0, // sub_ymm
4820 },
4821 { // VK1
4822 0, // sub_8bit
4823 0, // sub_8bit_hi
4824 0, // sub_8bit_hi_phony
4825 0, // sub_16bit
4826 0, // sub_16bit_hi
4827 0, // sub_32bit
4828 0, // sub_mask_0
4829 0, // sub_mask_1
4830 0, // sub_xmm
4831 0, // sub_ymm
4832 },
4833 { // VK16
4834 0, // sub_8bit
4835 0, // sub_8bit_hi
4836 0, // sub_8bit_hi_phony
4837 0, // sub_16bit
4838 0, // sub_16bit_hi
4839 0, // sub_32bit
4840 0, // sub_mask_0
4841 0, // sub_mask_1
4842 0, // sub_xmm
4843 0, // sub_ymm
4844 },
4845 { // VK2
4846 0, // sub_8bit
4847 0, // sub_8bit_hi
4848 0, // sub_8bit_hi_phony
4849 0, // sub_16bit
4850 0, // sub_16bit_hi
4851 0, // sub_32bit
4852 0, // sub_mask_0
4853 0, // sub_mask_1
4854 0, // sub_xmm
4855 0, // sub_ymm
4856 },
4857 { // VK4
4858 0, // sub_8bit
4859 0, // sub_8bit_hi
4860 0, // sub_8bit_hi_phony
4861 0, // sub_16bit
4862 0, // sub_16bit_hi
4863 0, // sub_32bit
4864 0, // sub_mask_0
4865 0, // sub_mask_1
4866 0, // sub_xmm
4867 0, // sub_ymm
4868 },
4869 { // VK8
4870 0, // sub_8bit
4871 0, // sub_8bit_hi
4872 0, // sub_8bit_hi_phony
4873 0, // sub_16bit
4874 0, // sub_16bit_hi
4875 0, // sub_32bit
4876 0, // sub_mask_0
4877 0, // sub_mask_1
4878 0, // sub_xmm
4879 0, // sub_ymm
4880 },
4881 { // VK16WM
4882 0, // sub_8bit
4883 0, // sub_8bit_hi
4884 0, // sub_8bit_hi_phony
4885 0, // sub_16bit
4886 0, // sub_16bit_hi
4887 0, // sub_32bit
4888 0, // sub_mask_0
4889 0, // sub_mask_1
4890 0, // sub_xmm
4891 0, // sub_ymm
4892 },
4893 { // VK1WM
4894 0, // sub_8bit
4895 0, // sub_8bit_hi
4896 0, // sub_8bit_hi_phony
4897 0, // sub_16bit
4898 0, // sub_16bit_hi
4899 0, // sub_32bit
4900 0, // sub_mask_0
4901 0, // sub_mask_1
4902 0, // sub_xmm
4903 0, // sub_ymm
4904 },
4905 { // VK2WM
4906 0, // sub_8bit
4907 0, // sub_8bit_hi
4908 0, // sub_8bit_hi_phony
4909 0, // sub_16bit
4910 0, // sub_16bit_hi
4911 0, // sub_32bit
4912 0, // sub_mask_0
4913 0, // sub_mask_1
4914 0, // sub_xmm
4915 0, // sub_ymm
4916 },
4917 { // VK4WM
4918 0, // sub_8bit
4919 0, // sub_8bit_hi
4920 0, // sub_8bit_hi_phony
4921 0, // sub_16bit
4922 0, // sub_16bit_hi
4923 0, // sub_32bit
4924 0, // sub_mask_0
4925 0, // sub_mask_1
4926 0, // sub_xmm
4927 0, // sub_ymm
4928 },
4929 { // VK8WM
4930 0, // sub_8bit
4931 0, // sub_8bit_hi
4932 0, // sub_8bit_hi_phony
4933 0, // sub_16bit
4934 0, // sub_16bit_hi
4935 0, // sub_32bit
4936 0, // sub_mask_0
4937 0, // sub_mask_1
4938 0, // sub_xmm
4939 0, // sub_ymm
4940 },
4941 { // SEGMENT_REG
4942 0, // sub_8bit
4943 0, // sub_8bit_hi
4944 0, // sub_8bit_hi_phony
4945 0, // sub_16bit
4946 0, // sub_16bit_hi
4947 0, // sub_32bit
4948 0, // sub_mask_0
4949 0, // sub_mask_1
4950 0, // sub_xmm
4951 0, // sub_ymm
4952 },
4953 { // GR16_ABCD
4954 22, // sub_8bit -> GR16_ABCD
4955 22, // sub_8bit_hi -> GR16_ABCD
4956 0, // sub_8bit_hi_phony
4957 0, // sub_16bit
4958 0, // sub_16bit_hi
4959 0, // sub_32bit
4960 0, // sub_mask_0
4961 0, // sub_mask_1
4962 0, // sub_xmm
4963 0, // sub_ymm
4964 },
4965 { // FPCCR
4966 0, // sub_8bit
4967 0, // sub_8bit_hi
4968 0, // sub_8bit_hi_phony
4969 0, // sub_16bit
4970 0, // sub_16bit_hi
4971 0, // sub_32bit
4972 0, // sub_mask_0
4973 0, // sub_mask_1
4974 0, // sub_xmm
4975 0, // sub_ymm
4976 },
4977 { // FR16X
4978 0, // sub_8bit
4979 0, // sub_8bit_hi
4980 0, // sub_8bit_hi_phony
4981 0, // sub_16bit
4982 0, // sub_16bit_hi
4983 0, // sub_32bit
4984 0, // sub_mask_0
4985 0, // sub_mask_1
4986 0, // sub_xmm
4987 0, // sub_ymm
4988 },
4989 { // FR16
4990 0, // sub_8bit
4991 0, // sub_8bit_hi
4992 0, // sub_8bit_hi_phony
4993 0, // sub_16bit
4994 0, // sub_16bit_hi
4995 0, // sub_32bit
4996 0, // sub_mask_0
4997 0, // sub_mask_1
4998 0, // sub_xmm
4999 0, // sub_ymm
5000 },
5001 { // VK16PAIR
5002 0, // sub_8bit
5003 0, // sub_8bit_hi
5004 0, // sub_8bit_hi_phony
5005 0, // sub_16bit
5006 0, // sub_16bit_hi
5007 0, // sub_32bit
5008 26, // sub_mask_0 -> VK16PAIR
5009 26, // sub_mask_1 -> VK16PAIR
5010 0, // sub_xmm
5011 0, // sub_ymm
5012 },
5013 { // VK1PAIR
5014 0, // sub_8bit
5015 0, // sub_8bit_hi
5016 0, // sub_8bit_hi_phony
5017 0, // sub_16bit
5018 0, // sub_16bit_hi
5019 0, // sub_32bit
5020 27, // sub_mask_0 -> VK1PAIR
5021 27, // sub_mask_1 -> VK1PAIR
5022 0, // sub_xmm
5023 0, // sub_ymm
5024 },
5025 { // VK2PAIR
5026 0, // sub_8bit
5027 0, // sub_8bit_hi
5028 0, // sub_8bit_hi_phony
5029 0, // sub_16bit
5030 0, // sub_16bit_hi
5031 0, // sub_32bit
5032 28, // sub_mask_0 -> VK2PAIR
5033 28, // sub_mask_1 -> VK2PAIR
5034 0, // sub_xmm
5035 0, // sub_ymm
5036 },
5037 { // VK4PAIR
5038 0, // sub_8bit
5039 0, // sub_8bit_hi
5040 0, // sub_8bit_hi_phony
5041 0, // sub_16bit
5042 0, // sub_16bit_hi
5043 0, // sub_32bit
5044 29, // sub_mask_0 -> VK4PAIR
5045 29, // sub_mask_1 -> VK4PAIR
5046 0, // sub_xmm
5047 0, // sub_ymm
5048 },
5049 { // VK8PAIR
5050 0, // sub_8bit
5051 0, // sub_8bit_hi
5052 0, // sub_8bit_hi_phony
5053 0, // sub_16bit
5054 0, // sub_16bit_hi
5055 0, // sub_32bit
5056 30, // sub_mask_0 -> VK8PAIR
5057 30, // sub_mask_1 -> VK8PAIR
5058 0, // sub_xmm
5059 0, // sub_ymm
5060 },
5061 { // VK1PAIR_with_sub_mask_0_in_VK1WM
5062 0, // sub_8bit
5063 0, // sub_8bit_hi
5064 0, // sub_8bit_hi_phony
5065 0, // sub_16bit
5066 0, // sub_16bit_hi
5067 0, // sub_32bit
5068 31, // sub_mask_0 -> VK1PAIR_with_sub_mask_0_in_VK1WM
5069 31, // sub_mask_1 -> VK1PAIR_with_sub_mask_0_in_VK1WM
5070 0, // sub_xmm
5071 0, // sub_ymm
5072 },
5073 { // LOW32_ADDR_ACCESS_RBP
5074 34, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
5075 49, // sub_8bit_hi -> GR32_ABCD
5076 0, // sub_8bit_hi_phony
5077 32, // sub_16bit -> LOW32_ADDR_ACCESS_RBP
5078 32, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP
5079 60, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
5080 0, // sub_mask_0
5081 0, // sub_mask_1
5082 0, // sub_xmm
5083 0, // sub_ymm
5084 },
5085 { // LOW32_ADDR_ACCESS
5086 36, // sub_8bit -> GR32
5087 49, // sub_8bit_hi -> GR32_ABCD
5088 0, // sub_8bit_hi_phony
5089 33, // sub_16bit -> LOW32_ADDR_ACCESS
5090 33, // sub_16bit_hi -> LOW32_ADDR_ACCESS
5091 71, // sub_32bit -> LOW32_ADDR_ACCESS_with_sub_32bit
5092 0, // sub_mask_0
5093 0, // sub_mask_1
5094 0, // sub_xmm
5095 0, // sub_ymm
5096 },
5097 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
5098 34, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
5099 49, // sub_8bit_hi -> GR32_ABCD
5100 0, // sub_8bit_hi_phony
5101 34, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
5102 34, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
5103 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5104 0, // sub_mask_0
5105 0, // sub_mask_1
5106 0, // sub_xmm
5107 0, // sub_ymm
5108 },
5109 { // FR32X
5110 0, // sub_8bit
5111 0, // sub_8bit_hi
5112 0, // sub_8bit_hi_phony
5113 0, // sub_16bit
5114 0, // sub_16bit_hi
5115 0, // sub_32bit
5116 0, // sub_mask_0
5117 0, // sub_mask_1
5118 0, // sub_xmm
5119 0, // sub_ymm
5120 },
5121 { // GR32
5122 36, // sub_8bit -> GR32
5123 49, // sub_8bit_hi -> GR32_ABCD
5124 0, // sub_8bit_hi_phony
5125 36, // sub_16bit -> GR32
5126 36, // sub_16bit_hi -> GR32
5127 0, // sub_32bit
5128 0, // sub_mask_0
5129 0, // sub_mask_1
5130 0, // sub_xmm
5131 0, // sub_ymm
5132 },
5133 { // GR32_NOSP
5134 37, // sub_8bit -> GR32_NOSP
5135 49, // sub_8bit_hi -> GR32_ABCD
5136 0, // sub_8bit_hi_phony
5137 37, // sub_16bit -> GR32_NOSP
5138 37, // sub_16bit_hi -> GR32_NOSP
5139 0, // sub_32bit
5140 0, // sub_mask_0
5141 0, // sub_mask_1
5142 0, // sub_xmm
5143 0, // sub_ymm
5144 },
5145 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
5146 38, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
5147 49, // sub_8bit_hi -> GR32_ABCD
5148 0, // sub_8bit_hi_phony
5149 38, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
5150 38, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
5151 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5152 0, // sub_mask_0
5153 0, // sub_mask_1
5154 0, // sub_xmm
5155 0, // sub_ymm
5156 },
5157 { // DEBUG_REG
5158 0, // sub_8bit
5159 0, // sub_8bit_hi
5160 0, // sub_8bit_hi_phony
5161 0, // sub_16bit
5162 0, // sub_16bit_hi
5163 0, // sub_32bit
5164 0, // sub_mask_0
5165 0, // sub_mask_1
5166 0, // sub_xmm
5167 0, // sub_ymm
5168 },
5169 { // FR32
5170 0, // sub_8bit
5171 0, // sub_8bit_hi
5172 0, // sub_8bit_hi_phony
5173 0, // sub_16bit
5174 0, // sub_16bit_hi
5175 0, // sub_32bit
5176 0, // sub_mask_0
5177 0, // sub_mask_1
5178 0, // sub_xmm
5179 0, // sub_ymm
5180 },
5181 { // GR32_NOREX2
5182 41, // sub_8bit -> GR32_NOREX2
5183 49, // sub_8bit_hi -> GR32_ABCD
5184 0, // sub_8bit_hi_phony
5185 41, // sub_16bit -> GR32_NOREX2
5186 41, // sub_16bit_hi -> GR32_NOREX2
5187 0, // sub_32bit
5188 0, // sub_mask_0
5189 0, // sub_mask_1
5190 0, // sub_xmm
5191 0, // sub_ymm
5192 },
5193 { // GR32_NOREX2_NOSP
5194 42, // sub_8bit -> GR32_NOREX2_NOSP
5195 49, // sub_8bit_hi -> GR32_ABCD
5196 0, // sub_8bit_hi_phony
5197 42, // sub_16bit -> GR32_NOREX2_NOSP
5198 42, // sub_16bit_hi -> GR32_NOREX2_NOSP
5199 0, // sub_32bit
5200 0, // sub_mask_0
5201 0, // sub_mask_1
5202 0, // sub_xmm
5203 0, // sub_ymm
5204 },
5205 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
5206 43, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
5207 49, // sub_8bit_hi -> GR32_ABCD
5208 0, // sub_8bit_hi_phony
5209 43, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
5210 43, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
5211 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5212 0, // sub_mask_0
5213 0, // sub_mask_1
5214 0, // sub_xmm
5215 0, // sub_ymm
5216 },
5217 { // GR32_NOREX
5218 44, // sub_8bit -> GR32_NOREX
5219 49, // sub_8bit_hi -> GR32_ABCD
5220 0, // sub_8bit_hi_phony
5221 44, // sub_16bit -> GR32_NOREX
5222 44, // sub_16bit_hi -> GR32_NOREX
5223 0, // sub_32bit
5224 0, // sub_mask_0
5225 0, // sub_mask_1
5226 0, // sub_xmm
5227 0, // sub_ymm
5228 },
5229 { // VK32
5230 0, // sub_8bit
5231 0, // sub_8bit_hi
5232 0, // sub_8bit_hi_phony
5233 0, // sub_16bit
5234 0, // sub_16bit_hi
5235 0, // sub_32bit
5236 0, // sub_mask_0
5237 0, // sub_mask_1
5238 0, // sub_xmm
5239 0, // sub_ymm
5240 },
5241 { // GR32_NOREX_NOSP
5242 46, // sub_8bit -> GR32_NOREX_NOSP
5243 49, // sub_8bit_hi -> GR32_ABCD
5244 0, // sub_8bit_hi_phony
5245 46, // sub_16bit -> GR32_NOREX_NOSP
5246 46, // sub_16bit_hi -> GR32_NOREX_NOSP
5247 0, // sub_32bit
5248 0, // sub_mask_0
5249 0, // sub_mask_1
5250 0, // sub_xmm
5251 0, // sub_ymm
5252 },
5253 { // RFP32
5254 0, // sub_8bit
5255 0, // sub_8bit_hi
5256 0, // sub_8bit_hi_phony
5257 0, // sub_16bit
5258 0, // sub_16bit_hi
5259 0, // sub_32bit
5260 0, // sub_mask_0
5261 0, // sub_mask_1
5262 0, // sub_xmm
5263 0, // sub_ymm
5264 },
5265 { // VK32WM
5266 0, // sub_8bit
5267 0, // sub_8bit_hi
5268 0, // sub_8bit_hi_phony
5269 0, // sub_16bit
5270 0, // sub_16bit_hi
5271 0, // sub_32bit
5272 0, // sub_mask_0
5273 0, // sub_mask_1
5274 0, // sub_xmm
5275 0, // sub_ymm
5276 },
5277 { // GR32_ABCD
5278 49, // sub_8bit -> GR32_ABCD
5279 49, // sub_8bit_hi -> GR32_ABCD
5280 0, // sub_8bit_hi_phony
5281 49, // sub_16bit -> GR32_ABCD
5282 49, // sub_16bit_hi -> GR32_ABCD
5283 0, // sub_32bit
5284 0, // sub_mask_0
5285 0, // sub_mask_1
5286 0, // sub_xmm
5287 0, // sub_ymm
5288 },
5289 { // GR32_TC
5290 50, // sub_8bit -> GR32_TC
5291 51, // sub_8bit_hi -> GR32_ABCD_and_GR32_TC
5292 0, // sub_8bit_hi_phony
5293 50, // sub_16bit -> GR32_TC
5294 50, // sub_16bit_hi -> GR32_TC
5295 0, // sub_32bit
5296 0, // sub_mask_0
5297 0, // sub_mask_1
5298 0, // sub_xmm
5299 0, // sub_ymm
5300 },
5301 { // GR32_ABCD_and_GR32_TC
5302 51, // sub_8bit -> GR32_ABCD_and_GR32_TC
5303 51, // sub_8bit_hi -> GR32_ABCD_and_GR32_TC
5304 0, // sub_8bit_hi_phony
5305 51, // sub_16bit -> GR32_ABCD_and_GR32_TC
5306 51, // sub_16bit_hi -> GR32_ABCD_and_GR32_TC
5307 0, // sub_32bit
5308 0, // sub_mask_0
5309 0, // sub_mask_1
5310 0, // sub_xmm
5311 0, // sub_ymm
5312 },
5313 { // GR32_AD
5314 52, // sub_8bit -> GR32_AD
5315 52, // sub_8bit_hi -> GR32_AD
5316 0, // sub_8bit_hi_phony
5317 52, // sub_16bit -> GR32_AD
5318 52, // sub_16bit_hi -> GR32_AD
5319 0, // sub_32bit
5320 0, // sub_mask_0
5321 0, // sub_mask_1
5322 0, // sub_xmm
5323 0, // sub_ymm
5324 },
5325 { // GR32_ArgRef
5326 53, // sub_8bit -> GR32_ArgRef
5327 53, // sub_8bit_hi -> GR32_ArgRef
5328 0, // sub_8bit_hi_phony
5329 53, // sub_16bit -> GR32_ArgRef
5330 53, // sub_16bit_hi -> GR32_ArgRef
5331 0, // sub_32bit
5332 0, // sub_mask_0
5333 0, // sub_mask_1
5334 0, // sub_xmm
5335 0, // sub_ymm
5336 },
5337 { // GR32_BPSP
5338 54, // sub_8bit -> GR32_BPSP
5339 0, // sub_8bit_hi
5340 54, // sub_8bit_hi_phony -> GR32_BPSP
5341 54, // sub_16bit -> GR32_BPSP
5342 54, // sub_16bit_hi -> GR32_BPSP
5343 0, // sub_32bit
5344 0, // sub_mask_0
5345 0, // sub_mask_1
5346 0, // sub_xmm
5347 0, // sub_ymm
5348 },
5349 { // GR32_BSI
5350 55, // sub_8bit -> GR32_BSI
5351 63, // sub_8bit_hi -> GR32_ABCD_and_GR32_BSI
5352 0, // sub_8bit_hi_phony
5353 55, // sub_16bit -> GR32_BSI
5354 55, // sub_16bit_hi -> GR32_BSI
5355 0, // sub_32bit
5356 0, // sub_mask_0
5357 0, // sub_mask_1
5358 0, // sub_xmm
5359 0, // sub_ymm
5360 },
5361 { // GR32_CB
5362 56, // sub_8bit -> GR32_CB
5363 56, // sub_8bit_hi -> GR32_CB
5364 0, // sub_8bit_hi_phony
5365 56, // sub_16bit -> GR32_CB
5366 56, // sub_16bit_hi -> GR32_CB
5367 0, // sub_32bit
5368 0, // sub_mask_0
5369 0, // sub_mask_1
5370 0, // sub_xmm
5371 0, // sub_ymm
5372 },
5373 { // GR32_DC
5374 57, // sub_8bit -> GR32_DC
5375 57, // sub_8bit_hi -> GR32_DC
5376 0, // sub_8bit_hi_phony
5377 57, // sub_16bit -> GR32_DC
5378 57, // sub_16bit_hi -> GR32_DC
5379 0, // sub_32bit
5380 0, // sub_mask_0
5381 0, // sub_mask_1
5382 0, // sub_xmm
5383 0, // sub_ymm
5384 },
5385 { // GR32_DIBP
5386 58, // sub_8bit -> GR32_DIBP
5387 0, // sub_8bit_hi
5388 58, // sub_8bit_hi_phony -> GR32_DIBP
5389 58, // sub_16bit -> GR32_DIBP
5390 58, // sub_16bit_hi -> GR32_DIBP
5391 0, // sub_32bit
5392 0, // sub_mask_0
5393 0, // sub_mask_1
5394 0, // sub_xmm
5395 0, // sub_ymm
5396 },
5397 { // GR32_SIDI
5398 59, // sub_8bit -> GR32_SIDI
5399 0, // sub_8bit_hi
5400 59, // sub_8bit_hi_phony -> GR32_SIDI
5401 59, // sub_16bit -> GR32_SIDI
5402 59, // sub_16bit_hi -> GR32_SIDI
5403 0, // sub_32bit
5404 0, // sub_mask_0
5405 0, // sub_mask_1
5406 0, // sub_xmm
5407 0, // sub_ymm
5408 },
5409 { // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
5410 70, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5411 0, // sub_8bit_hi
5412 0, // sub_8bit_hi_phony
5413 60, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
5414 60, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
5415 60, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
5416 0, // sub_mask_0
5417 0, // sub_mask_1
5418 0, // sub_xmm
5419 0, // sub_ymm
5420 },
5421 { // CCR
5422 0, // sub_8bit
5423 0, // sub_8bit_hi
5424 0, // sub_8bit_hi_phony
5425 0, // sub_16bit
5426 0, // sub_16bit_hi
5427 0, // sub_32bit
5428 0, // sub_mask_0
5429 0, // sub_mask_1
5430 0, // sub_xmm
5431 0, // sub_ymm
5432 },
5433 { // DFCCR
5434 0, // sub_8bit
5435 0, // sub_8bit_hi
5436 0, // sub_8bit_hi_phony
5437 0, // sub_16bit
5438 0, // sub_16bit_hi
5439 0, // sub_32bit
5440 0, // sub_mask_0
5441 0, // sub_mask_1
5442 0, // sub_xmm
5443 0, // sub_ymm
5444 },
5445 { // GR32_ABCD_and_GR32_BSI
5446 63, // sub_8bit -> GR32_ABCD_and_GR32_BSI
5447 63, // sub_8bit_hi -> GR32_ABCD_and_GR32_BSI
5448 0, // sub_8bit_hi_phony
5449 63, // sub_16bit -> GR32_ABCD_and_GR32_BSI
5450 63, // sub_16bit_hi -> GR32_ABCD_and_GR32_BSI
5451 0, // sub_32bit
5452 0, // sub_mask_0
5453 0, // sub_mask_1
5454 0, // sub_xmm
5455 0, // sub_ymm
5456 },
5457 { // GR32_AD_and_GR32_ArgRef
5458 64, // sub_8bit -> GR32_AD_and_GR32_ArgRef
5459 64, // sub_8bit_hi -> GR32_AD_and_GR32_ArgRef
5460 0, // sub_8bit_hi_phony
5461 64, // sub_16bit -> GR32_AD_and_GR32_ArgRef
5462 64, // sub_16bit_hi -> GR32_AD_and_GR32_ArgRef
5463 0, // sub_32bit
5464 0, // sub_mask_0
5465 0, // sub_mask_1
5466 0, // sub_xmm
5467 0, // sub_ymm
5468 },
5469 { // GR32_ArgRef_and_GR32_CB
5470 65, // sub_8bit -> GR32_ArgRef_and_GR32_CB
5471 65, // sub_8bit_hi -> GR32_ArgRef_and_GR32_CB
5472 0, // sub_8bit_hi_phony
5473 65, // sub_16bit -> GR32_ArgRef_and_GR32_CB
5474 65, // sub_16bit_hi -> GR32_ArgRef_and_GR32_CB
5475 0, // sub_32bit
5476 0, // sub_mask_0
5477 0, // sub_mask_1
5478 0, // sub_xmm
5479 0, // sub_ymm
5480 },
5481 { // GR32_BPSP_and_GR32_DIBP
5482 66, // sub_8bit -> GR32_BPSP_and_GR32_DIBP
5483 0, // sub_8bit_hi
5484 66, // sub_8bit_hi_phony -> GR32_BPSP_and_GR32_DIBP
5485 66, // sub_16bit -> GR32_BPSP_and_GR32_DIBP
5486 66, // sub_16bit_hi -> GR32_BPSP_and_GR32_DIBP
5487 0, // sub_32bit
5488 0, // sub_mask_0
5489 0, // sub_mask_1
5490 0, // sub_xmm
5491 0, // sub_ymm
5492 },
5493 { // GR32_BPSP_and_GR32_TC
5494 67, // sub_8bit -> GR32_BPSP_and_GR32_TC
5495 0, // sub_8bit_hi
5496 67, // sub_8bit_hi_phony -> GR32_BPSP_and_GR32_TC
5497 67, // sub_16bit -> GR32_BPSP_and_GR32_TC
5498 67, // sub_16bit_hi -> GR32_BPSP_and_GR32_TC
5499 0, // sub_32bit
5500 0, // sub_mask_0
5501 0, // sub_mask_1
5502 0, // sub_xmm
5503 0, // sub_ymm
5504 },
5505 { // GR32_BSI_and_GR32_SIDI
5506 68, // sub_8bit -> GR32_BSI_and_GR32_SIDI
5507 0, // sub_8bit_hi
5508 68, // sub_8bit_hi_phony -> GR32_BSI_and_GR32_SIDI
5509 68, // sub_16bit -> GR32_BSI_and_GR32_SIDI
5510 68, // sub_16bit_hi -> GR32_BSI_and_GR32_SIDI
5511 0, // sub_32bit
5512 0, // sub_mask_0
5513 0, // sub_mask_1
5514 0, // sub_xmm
5515 0, // sub_ymm
5516 },
5517 { // GR32_DIBP_and_GR32_SIDI
5518 69, // sub_8bit -> GR32_DIBP_and_GR32_SIDI
5519 0, // sub_8bit_hi
5520 69, // sub_8bit_hi_phony -> GR32_DIBP_and_GR32_SIDI
5521 69, // sub_16bit -> GR32_DIBP_and_GR32_SIDI
5522 69, // sub_16bit_hi -> GR32_DIBP_and_GR32_SIDI
5523 0, // sub_32bit
5524 0, // sub_mask_0
5525 0, // sub_mask_1
5526 0, // sub_xmm
5527 0, // sub_ymm
5528 },
5529 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5530 70, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5531 0, // sub_8bit_hi
5532 70, // sub_8bit_hi_phony -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5533 70, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5534 70, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5535 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5536 0, // sub_mask_0
5537 0, // sub_mask_1
5538 0, // sub_xmm
5539 0, // sub_ymm
5540 },
5541 { // LOW32_ADDR_ACCESS_with_sub_32bit
5542 0, // sub_8bit
5543 0, // sub_8bit_hi
5544 0, // sub_8bit_hi_phony
5545 71, // sub_16bit -> LOW32_ADDR_ACCESS_with_sub_32bit
5546 71, // sub_16bit_hi -> LOW32_ADDR_ACCESS_with_sub_32bit
5547 71, // sub_32bit -> LOW32_ADDR_ACCESS_with_sub_32bit
5548 0, // sub_mask_0
5549 0, // sub_mask_1
5550 0, // sub_xmm
5551 0, // sub_ymm
5552 },
5553 { // RFP64
5554 0, // sub_8bit
5555 0, // sub_8bit_hi
5556 0, // sub_8bit_hi_phony
5557 0, // sub_16bit
5558 0, // sub_16bit_hi
5559 0, // sub_32bit
5560 0, // sub_mask_0
5561 0, // sub_mask_1
5562 0, // sub_xmm
5563 0, // sub_ymm
5564 },
5565 { // GR64
5566 75, // sub_8bit -> GR64_with_sub_8bit
5567 104, // sub_8bit_hi -> GR64_ABCD
5568 0, // sub_8bit_hi_phony
5569 73, // sub_16bit -> GR64
5570 73, // sub_16bit_hi -> GR64
5571 73, // sub_32bit -> GR64
5572 0, // sub_mask_0
5573 0, // sub_mask_1
5574 0, // sub_xmm
5575 0, // sub_ymm
5576 },
5577 { // FR64X
5578 0, // sub_8bit
5579 0, // sub_8bit_hi
5580 0, // sub_8bit_hi_phony
5581 0, // sub_16bit
5582 0, // sub_16bit_hi
5583 0, // sub_32bit
5584 0, // sub_mask_0
5585 0, // sub_mask_1
5586 0, // sub_xmm
5587 0, // sub_ymm
5588 },
5589 { // GR64_with_sub_8bit
5590 75, // sub_8bit -> GR64_with_sub_8bit
5591 104, // sub_8bit_hi -> GR64_ABCD
5592 0, // sub_8bit_hi_phony
5593 75, // sub_16bit -> GR64_with_sub_8bit
5594 75, // sub_16bit_hi -> GR64_with_sub_8bit
5595 75, // sub_32bit -> GR64_with_sub_8bit
5596 0, // sub_mask_0
5597 0, // sub_mask_1
5598 0, // sub_xmm
5599 0, // sub_ymm
5600 },
5601 { // GR64_NOSP
5602 76, // sub_8bit -> GR64_NOSP
5603 104, // sub_8bit_hi -> GR64_ABCD
5604 0, // sub_8bit_hi_phony
5605 76, // sub_16bit -> GR64_NOSP
5606 76, // sub_16bit_hi -> GR64_NOSP
5607 76, // sub_32bit -> GR64_NOSP
5608 0, // sub_mask_0
5609 0, // sub_mask_1
5610 0, // sub_xmm
5611 0, // sub_ymm
5612 },
5613 { // GR64_NOREX2
5614 80, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX2
5615 104, // sub_8bit_hi -> GR64_ABCD
5616 0, // sub_8bit_hi_phony
5617 77, // sub_16bit -> GR64_NOREX2
5618 77, // sub_16bit_hi -> GR64_NOREX2
5619 77, // sub_32bit -> GR64_NOREX2
5620 0, // sub_mask_0
5621 0, // sub_mask_1
5622 0, // sub_xmm
5623 0, // sub_ymm
5624 },
5625 { // CONTROL_REG
5626 0, // sub_8bit
5627 0, // sub_8bit_hi
5628 0, // sub_8bit_hi_phony
5629 0, // sub_16bit
5630 0, // sub_16bit_hi
5631 0, // sub_32bit
5632 0, // sub_mask_0
5633 0, // sub_mask_1
5634 0, // sub_xmm
5635 0, // sub_ymm
5636 },
5637 { // FR64
5638 0, // sub_8bit
5639 0, // sub_8bit_hi
5640 0, // sub_8bit_hi_phony
5641 0, // sub_16bit
5642 0, // sub_16bit_hi
5643 0, // sub_32bit
5644 0, // sub_mask_0
5645 0, // sub_mask_1
5646 0, // sub_xmm
5647 0, // sub_ymm
5648 },
5649 { // GR64_with_sub_16bit_in_GR16_NOREX2
5650 80, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX2
5651 104, // sub_8bit_hi -> GR64_ABCD
5652 0, // sub_8bit_hi_phony
5653 80, // sub_16bit -> GR64_with_sub_16bit_in_GR16_NOREX2
5654 80, // sub_16bit_hi -> GR64_with_sub_16bit_in_GR16_NOREX2
5655 80, // sub_32bit -> GR64_with_sub_16bit_in_GR16_NOREX2
5656 0, // sub_mask_0
5657 0, // sub_mask_1
5658 0, // sub_xmm
5659 0, // sub_ymm
5660 },
5661 { // GR64_NOREX2_NOSP
5662 81, // sub_8bit -> GR64_NOREX2_NOSP
5663 104, // sub_8bit_hi -> GR64_ABCD
5664 0, // sub_8bit_hi_phony
5665 81, // sub_16bit -> GR64_NOREX2_NOSP
5666 81, // sub_16bit_hi -> GR64_NOREX2_NOSP
5667 81, // sub_32bit -> GR64_NOREX2_NOSP
5668 0, // sub_mask_0
5669 0, // sub_mask_1
5670 0, // sub_xmm
5671 0, // sub_ymm
5672 },
5673 { // GR64PLTSafe
5674 82, // sub_8bit -> GR64PLTSafe
5675 104, // sub_8bit_hi -> GR64_ABCD
5676 0, // sub_8bit_hi_phony
5677 82, // sub_16bit -> GR64PLTSafe
5678 82, // sub_16bit_hi -> GR64PLTSafe
5679 82, // sub_32bit -> GR64PLTSafe
5680 0, // sub_mask_0
5681 0, // sub_mask_1
5682 0, // sub_xmm
5683 0, // sub_ymm
5684 },
5685 { // GR64_TC
5686 86, // sub_8bit -> GR64_TC_with_sub_8bit
5687 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5688 0, // sub_8bit_hi_phony
5689 83, // sub_16bit -> GR64_TC
5690 83, // sub_16bit_hi -> GR64_TC
5691 83, // sub_32bit -> GR64_TC
5692 0, // sub_mask_0
5693 0, // sub_mask_1
5694 0, // sub_xmm
5695 0, // sub_ymm
5696 },
5697 { // GR64_NOREX
5698 90, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX
5699 104, // sub_8bit_hi -> GR64_ABCD
5700 0, // sub_8bit_hi_phony
5701 84, // sub_16bit -> GR64_NOREX
5702 84, // sub_16bit_hi -> GR64_NOREX
5703 84, // sub_32bit -> GR64_NOREX
5704 0, // sub_mask_0
5705 0, // sub_mask_1
5706 0, // sub_xmm
5707 0, // sub_ymm
5708 },
5709 { // GR64_TCW64
5710 88, // sub_8bit -> GR64_TCW64_with_sub_8bit
5711 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5712 0, // sub_8bit_hi_phony
5713 85, // sub_16bit -> GR64_TCW64
5714 85, // sub_16bit_hi -> GR64_TCW64
5715 85, // sub_32bit -> GR64_TCW64
5716 0, // sub_mask_0
5717 0, // sub_mask_1
5718 0, // sub_xmm
5719 0, // sub_ymm
5720 },
5721 { // GR64_TC_with_sub_8bit
5722 86, // sub_8bit -> GR64_TC_with_sub_8bit
5723 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5724 0, // sub_8bit_hi_phony
5725 86, // sub_16bit -> GR64_TC_with_sub_8bit
5726 86, // sub_16bit_hi -> GR64_TC_with_sub_8bit
5727 86, // sub_32bit -> GR64_TC_with_sub_8bit
5728 0, // sub_mask_0
5729 0, // sub_mask_1
5730 0, // sub_xmm
5731 0, // sub_ymm
5732 },
5733 { // GR64_NOREX2_NOSP_and_GR64_TC
5734 87, // sub_8bit -> GR64_NOREX2_NOSP_and_GR64_TC
5735 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5736 0, // sub_8bit_hi_phony
5737 87, // sub_16bit -> GR64_NOREX2_NOSP_and_GR64_TC
5738 87, // sub_16bit_hi -> GR64_NOREX2_NOSP_and_GR64_TC
5739 87, // sub_32bit -> GR64_NOREX2_NOSP_and_GR64_TC
5740 0, // sub_mask_0
5741 0, // sub_mask_1
5742 0, // sub_xmm
5743 0, // sub_ymm
5744 },
5745 { // GR64_TCW64_with_sub_8bit
5746 88, // sub_8bit -> GR64_TCW64_with_sub_8bit
5747 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5748 0, // sub_8bit_hi_phony
5749 88, // sub_16bit -> GR64_TCW64_with_sub_8bit
5750 88, // sub_16bit_hi -> GR64_TCW64_with_sub_8bit
5751 88, // sub_32bit -> GR64_TCW64_with_sub_8bit
5752 0, // sub_mask_0
5753 0, // sub_mask_1
5754 0, // sub_xmm
5755 0, // sub_ymm
5756 },
5757 { // GR64_TC_and_GR64_TCW64
5758 97, // sub_8bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
5759 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5760 0, // sub_8bit_hi_phony
5761 89, // sub_16bit -> GR64_TC_and_GR64_TCW64
5762 89, // sub_16bit_hi -> GR64_TC_and_GR64_TCW64
5763 89, // sub_32bit -> GR64_TC_and_GR64_TCW64
5764 0, // sub_mask_0
5765 0, // sub_mask_1
5766 0, // sub_xmm
5767 0, // sub_ymm
5768 },
5769 { // GR64_with_sub_16bit_in_GR16_NOREX
5770 90, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX
5771 104, // sub_8bit_hi -> GR64_ABCD
5772 0, // sub_8bit_hi_phony
5773 90, // sub_16bit -> GR64_with_sub_16bit_in_GR16_NOREX
5774 90, // sub_16bit_hi -> GR64_with_sub_16bit_in_GR16_NOREX
5775 90, // sub_32bit -> GR64_with_sub_16bit_in_GR16_NOREX
5776 0, // sub_mask_0
5777 0, // sub_mask_1
5778 0, // sub_xmm
5779 0, // sub_ymm
5780 },
5781 { // VK64
5782 0, // sub_8bit
5783 0, // sub_8bit_hi
5784 0, // sub_8bit_hi_phony
5785 0, // sub_16bit
5786 0, // sub_16bit_hi
5787 0, // sub_32bit
5788 0, // sub_mask_0
5789 0, // sub_mask_1
5790 0, // sub_xmm
5791 0, // sub_ymm
5792 },
5793 { // VR64
5794 0, // sub_8bit
5795 0, // sub_8bit_hi
5796 0, // sub_8bit_hi_phony
5797 0, // sub_16bit
5798 0, // sub_16bit_hi
5799 0, // sub_32bit
5800 0, // sub_mask_0
5801 0, // sub_mask_1
5802 0, // sub_xmm
5803 0, // sub_ymm
5804 },
5805 { // GR64PLTSafe_and_GR64_TC
5806 93, // sub_8bit -> GR64PLTSafe_and_GR64_TC
5807 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5808 0, // sub_8bit_hi_phony
5809 93, // sub_16bit -> GR64PLTSafe_and_GR64_TC
5810 93, // sub_16bit_hi -> GR64PLTSafe_and_GR64_TC
5811 93, // sub_32bit -> GR64PLTSafe_and_GR64_TC
5812 0, // sub_mask_0
5813 0, // sub_mask_1
5814 0, // sub_xmm
5815 0, // sub_ymm
5816 },
5817 { // GR64_NOREX2_NOSP_and_GR64_TCW64
5818 94, // sub_8bit -> GR64_NOREX2_NOSP_and_GR64_TCW64
5819 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5820 0, // sub_8bit_hi_phony
5821 94, // sub_16bit -> GR64_NOREX2_NOSP_and_GR64_TCW64
5822 94, // sub_16bit_hi -> GR64_NOREX2_NOSP_and_GR64_TCW64
5823 94, // sub_32bit -> GR64_NOREX2_NOSP_and_GR64_TCW64
5824 0, // sub_mask_0
5825 0, // sub_mask_1
5826 0, // sub_xmm
5827 0, // sub_ymm
5828 },
5829 { // GR64_NOREX_NOSP
5830 95, // sub_8bit -> GR64_NOREX_NOSP
5831 104, // sub_8bit_hi -> GR64_ABCD
5832 0, // sub_8bit_hi_phony
5833 95, // sub_16bit -> GR64_NOREX_NOSP
5834 95, // sub_16bit_hi -> GR64_NOREX_NOSP
5835 95, // sub_32bit -> GR64_NOREX_NOSP
5836 0, // sub_mask_0
5837 0, // sub_mask_1
5838 0, // sub_xmm
5839 0, // sub_ymm
5840 },
5841 { // GR64_NOREX_and_GR64_TC
5842 100, // sub_8bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
5843 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5844 0, // sub_8bit_hi_phony
5845 96, // sub_16bit -> GR64_NOREX_and_GR64_TC
5846 96, // sub_16bit_hi -> GR64_NOREX_and_GR64_TC
5847 96, // sub_32bit -> GR64_NOREX_and_GR64_TC
5848 0, // sub_mask_0
5849 0, // sub_mask_1
5850 0, // sub_xmm
5851 0, // sub_ymm
5852 },
5853 { // GR64_TCW64_and_GR64_TC_with_sub_8bit
5854 97, // sub_8bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
5855 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5856 0, // sub_8bit_hi_phony
5857 97, // sub_16bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
5858 97, // sub_16bit_hi -> GR64_TCW64_and_GR64_TC_with_sub_8bit
5859 97, // sub_32bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
5860 0, // sub_mask_0
5861 0, // sub_mask_1
5862 0, // sub_xmm
5863 0, // sub_ymm
5864 },
5865 { // VK64WM
5866 0, // sub_8bit
5867 0, // sub_8bit_hi
5868 0, // sub_8bit_hi_phony
5869 0, // sub_16bit
5870 0, // sub_16bit_hi
5871 0, // sub_32bit
5872 0, // sub_mask_0
5873 0, // sub_mask_1
5874 0, // sub_xmm
5875 0, // sub_ymm
5876 },
5877 { // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
5878 99, // sub_8bit -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
5879 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5880 0, // sub_8bit_hi_phony
5881 99, // sub_16bit -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
5882 99, // sub_16bit_hi -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
5883 99, // sub_32bit -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
5884 0, // sub_mask_0
5885 0, // sub_mask_1
5886 0, // sub_xmm
5887 0, // sub_ymm
5888 },
5889 { // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
5890 100, // sub_8bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
5891 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5892 0, // sub_8bit_hi_phony
5893 100, // sub_16bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
5894 100, // sub_16bit_hi -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
5895 100, // sub_32bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
5896 0, // sub_mask_0
5897 0, // sub_mask_1
5898 0, // sub_xmm
5899 0, // sub_ymm
5900 },
5901 { // GR64PLTSafe_and_GR64_TCW64
5902 101, // sub_8bit -> GR64PLTSafe_and_GR64_TCW64
5903 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5904 0, // sub_8bit_hi_phony
5905 101, // sub_16bit -> GR64PLTSafe_and_GR64_TCW64
5906 101, // sub_16bit_hi -> GR64PLTSafe_and_GR64_TCW64
5907 101, // sub_32bit -> GR64PLTSafe_and_GR64_TCW64
5908 0, // sub_mask_0
5909 0, // sub_mask_1
5910 0, // sub_xmm
5911 0, // sub_ymm
5912 },
5913 { // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
5914 102, // sub_8bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
5915 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5916 0, // sub_8bit_hi_phony
5917 102, // sub_16bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
5918 102, // sub_16bit_hi -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
5919 102, // sub_32bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
5920 0, // sub_mask_0
5921 0, // sub_mask_1
5922 0, // sub_xmm
5923 0, // sub_ymm
5924 },
5925 { // GR64_NOREX_and_GR64_TCW64
5926 105, // sub_8bit -> GR64_with_sub_32bit_in_GR32_TC
5927 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5928 0, // sub_8bit_hi_phony
5929 103, // sub_16bit -> GR64_NOREX_and_GR64_TCW64
5930 103, // sub_16bit_hi -> GR64_NOREX_and_GR64_TCW64
5931 103, // sub_32bit -> GR64_NOREX_and_GR64_TCW64
5932 0, // sub_mask_0
5933 0, // sub_mask_1
5934 0, // sub_xmm
5935 0, // sub_ymm
5936 },
5937 { // GR64_ABCD
5938 104, // sub_8bit -> GR64_ABCD
5939 104, // sub_8bit_hi -> GR64_ABCD
5940 0, // sub_8bit_hi_phony
5941 104, // sub_16bit -> GR64_ABCD
5942 104, // sub_16bit_hi -> GR64_ABCD
5943 104, // sub_32bit -> GR64_ABCD
5944 0, // sub_mask_0
5945 0, // sub_mask_1
5946 0, // sub_xmm
5947 0, // sub_ymm
5948 },
5949 { // GR64_with_sub_32bit_in_GR32_TC
5950 105, // sub_8bit -> GR64_with_sub_32bit_in_GR32_TC
5951 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5952 0, // sub_8bit_hi_phony
5953 105, // sub_16bit -> GR64_with_sub_32bit_in_GR32_TC
5954 105, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_TC
5955 105, // sub_32bit -> GR64_with_sub_32bit_in_GR32_TC
5956 0, // sub_mask_0
5957 0, // sub_mask_1
5958 0, // sub_xmm
5959 0, // sub_ymm
5960 },
5961 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5962 106, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5963 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5964 0, // sub_8bit_hi_phony
5965 106, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5966 106, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5967 106, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5968 0, // sub_mask_0
5969 0, // sub_mask_1
5970 0, // sub_xmm
5971 0, // sub_ymm
5972 },
5973 { // GR64_AD
5974 107, // sub_8bit -> GR64_AD
5975 107, // sub_8bit_hi -> GR64_AD
5976 0, // sub_8bit_hi_phony
5977 107, // sub_16bit -> GR64_AD
5978 107, // sub_16bit_hi -> GR64_AD
5979 107, // sub_32bit -> GR64_AD
5980 0, // sub_mask_0
5981 0, // sub_mask_1
5982 0, // sub_xmm
5983 0, // sub_ymm
5984 },
5985 { // GR64_ArgRef
5986 108, // sub_8bit -> GR64_ArgRef
5987 0, // sub_8bit_hi
5988 108, // sub_8bit_hi_phony -> GR64_ArgRef
5989 108, // sub_16bit -> GR64_ArgRef
5990 108, // sub_16bit_hi -> GR64_ArgRef
5991 108, // sub_32bit -> GR64_ArgRef
5992 0, // sub_mask_0
5993 0, // sub_mask_1
5994 0, // sub_xmm
5995 0, // sub_ymm
5996 },
5997 { // GR64_and_LOW32_ADDR_ACCESS_RBP
5998 122, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
5999 0, // sub_8bit_hi
6000 0, // sub_8bit_hi_phony
6001 109, // sub_16bit -> GR64_and_LOW32_ADDR_ACCESS_RBP
6002 109, // sub_16bit_hi -> GR64_and_LOW32_ADDR_ACCESS_RBP
6003 109, // sub_32bit -> GR64_and_LOW32_ADDR_ACCESS_RBP
6004 0, // sub_mask_0
6005 0, // sub_mask_1
6006 0, // sub_xmm
6007 0, // sub_ymm
6008 },
6009 { // GR64_with_sub_32bit_in_GR32_ArgRef
6010 110, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ArgRef
6011 110, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef
6012 0, // sub_8bit_hi_phony
6013 110, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ArgRef
6014 110, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef
6015 110, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ArgRef
6016 0, // sub_mask_0
6017 0, // sub_mask_1
6018 0, // sub_xmm
6019 0, // sub_ymm
6020 },
6021 { // GR64_with_sub_32bit_in_GR32_BPSP
6022 111, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP
6023 0, // sub_8bit_hi
6024 111, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BPSP
6025 111, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP
6026 111, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BPSP
6027 111, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP
6028 0, // sub_mask_0
6029 0, // sub_mask_1
6030 0, // sub_xmm
6031 0, // sub_ymm
6032 },
6033 { // GR64_with_sub_32bit_in_GR32_BSI
6034 112, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BSI
6035 119, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
6036 0, // sub_8bit_hi_phony
6037 112, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BSI
6038 112, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BSI
6039 112, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BSI
6040 0, // sub_mask_0
6041 0, // sub_mask_1
6042 0, // sub_xmm
6043 0, // sub_ymm
6044 },
6045 { // GR64_with_sub_32bit_in_GR32_CB
6046 113, // sub_8bit -> GR64_with_sub_32bit_in_GR32_CB
6047 113, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_CB
6048 0, // sub_8bit_hi_phony
6049 113, // sub_16bit -> GR64_with_sub_32bit_in_GR32_CB
6050 113, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_CB
6051 113, // sub_32bit -> GR64_with_sub_32bit_in_GR32_CB
6052 0, // sub_mask_0
6053 0, // sub_mask_1
6054 0, // sub_xmm
6055 0, // sub_ymm
6056 },
6057 { // GR64_with_sub_32bit_in_GR32_DIBP
6058 114, // sub_8bit -> GR64_with_sub_32bit_in_GR32_DIBP
6059 0, // sub_8bit_hi
6060 114, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_DIBP
6061 114, // sub_16bit -> GR64_with_sub_32bit_in_GR32_DIBP
6062 114, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_DIBP
6063 114, // sub_32bit -> GR64_with_sub_32bit_in_GR32_DIBP
6064 0, // sub_mask_0
6065 0, // sub_mask_1
6066 0, // sub_xmm
6067 0, // sub_ymm
6068 },
6069 { // GR64_with_sub_32bit_in_GR32_SIDI
6070 115, // sub_8bit -> GR64_with_sub_32bit_in_GR32_SIDI
6071 0, // sub_8bit_hi
6072 115, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_SIDI
6073 115, // sub_16bit -> GR64_with_sub_32bit_in_GR32_SIDI
6074 115, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_SIDI
6075 115, // sub_32bit -> GR64_with_sub_32bit_in_GR32_SIDI
6076 0, // sub_mask_0
6077 0, // sub_mask_1
6078 0, // sub_xmm
6079 0, // sub_ymm
6080 },
6081 { // GR64_A
6082 116, // sub_8bit -> GR64_A
6083 116, // sub_8bit_hi -> GR64_A
6084 0, // sub_8bit_hi_phony
6085 116, // sub_16bit -> GR64_A
6086 116, // sub_16bit_hi -> GR64_A
6087 116, // sub_32bit -> GR64_A
6088 0, // sub_mask_0
6089 0, // sub_mask_1
6090 0, // sub_xmm
6091 0, // sub_ymm
6092 },
6093 { // GR64_ArgRef_and_GR64_TC
6094 117, // sub_8bit -> GR64_ArgRef_and_GR64_TC
6095 0, // sub_8bit_hi
6096 117, // sub_8bit_hi_phony -> GR64_ArgRef_and_GR64_TC
6097 117, // sub_16bit -> GR64_ArgRef_and_GR64_TC
6098 117, // sub_16bit_hi -> GR64_ArgRef_and_GR64_TC
6099 117, // sub_32bit -> GR64_ArgRef_and_GR64_TC
6100 0, // sub_mask_0
6101 0, // sub_mask_1
6102 0, // sub_xmm
6103 0, // sub_ymm
6104 },
6105 { // GR64_and_LOW32_ADDR_ACCESS
6106 0, // sub_8bit
6107 0, // sub_8bit_hi
6108 0, // sub_8bit_hi_phony
6109 118, // sub_16bit -> GR64_and_LOW32_ADDR_ACCESS
6110 118, // sub_16bit_hi -> GR64_and_LOW32_ADDR_ACCESS
6111 118, // sub_32bit -> GR64_and_LOW32_ADDR_ACCESS
6112 0, // sub_mask_0
6113 0, // sub_mask_1
6114 0, // sub_xmm
6115 0, // sub_ymm
6116 },
6117 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
6118 119, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
6119 119, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
6120 0, // sub_8bit_hi_phony
6121 119, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
6122 119, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
6123 119, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
6124 0, // sub_mask_0
6125 0, // sub_mask_1
6126 0, // sub_xmm
6127 0, // sub_ymm
6128 },
6129 { // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
6130 120, // sub_8bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
6131 120, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
6132 0, // sub_8bit_hi_phony
6133 120, // sub_16bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
6134 120, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
6135 120, // sub_32bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
6136 0, // sub_mask_0
6137 0, // sub_mask_1
6138 0, // sub_xmm
6139 0, // sub_ymm
6140 },
6141 { // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
6142 121, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
6143 121, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
6144 0, // sub_8bit_hi_phony
6145 121, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
6146 121, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
6147 121, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
6148 0, // sub_mask_0
6149 0, // sub_mask_1
6150 0, // sub_xmm
6151 0, // sub_ymm
6152 },
6153 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
6154 122, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
6155 0, // sub_8bit_hi
6156 122, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
6157 122, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
6158 122, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
6159 122, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
6160 0, // sub_mask_0
6161 0, // sub_mask_1
6162 0, // sub_xmm
6163 0, // sub_ymm
6164 },
6165 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
6166 123, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
6167 0, // sub_8bit_hi
6168 123, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
6169 123, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
6170 123, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
6171 123, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
6172 0, // sub_mask_0
6173 0, // sub_mask_1
6174 0, // sub_xmm
6175 0, // sub_ymm
6176 },
6177 { // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
6178 124, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
6179 0, // sub_8bit_hi
6180 124, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
6181 124, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
6182 124, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
6183 124, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
6184 0, // sub_mask_0
6185 0, // sub_mask_1
6186 0, // sub_xmm
6187 0, // sub_ymm
6188 },
6189 { // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
6190 125, // sub_8bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
6191 0, // sub_8bit_hi
6192 125, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
6193 125, // sub_16bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
6194 125, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
6195 125, // sub_32bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
6196 0, // sub_mask_0
6197 0, // sub_mask_1
6198 0, // sub_xmm
6199 0, // sub_ymm
6200 },
6201 { // RST
6202 0, // sub_8bit
6203 0, // sub_8bit_hi
6204 0, // sub_8bit_hi_phony
6205 0, // sub_16bit
6206 0, // sub_16bit_hi
6207 0, // sub_32bit
6208 0, // sub_mask_0
6209 0, // sub_mask_1
6210 0, // sub_xmm
6211 0, // sub_ymm
6212 },
6213 { // RFP80
6214 0, // sub_8bit
6215 0, // sub_8bit_hi
6216 0, // sub_8bit_hi_phony
6217 0, // sub_16bit
6218 0, // sub_16bit_hi
6219 0, // sub_32bit
6220 0, // sub_mask_0
6221 0, // sub_mask_1
6222 0, // sub_xmm
6223 0, // sub_ymm
6224 },
6225 { // RFP80_7
6226 0, // sub_8bit
6227 0, // sub_8bit_hi
6228 0, // sub_8bit_hi_phony
6229 0, // sub_16bit
6230 0, // sub_16bit_hi
6231 0, // sub_32bit
6232 0, // sub_mask_0
6233 0, // sub_mask_1
6234 0, // sub_xmm
6235 0, // sub_ymm
6236 },
6237 { // VR128X
6238 0, // sub_8bit
6239 0, // sub_8bit_hi
6240 0, // sub_8bit_hi_phony
6241 0, // sub_16bit
6242 0, // sub_16bit_hi
6243 0, // sub_32bit
6244 0, // sub_mask_0
6245 0, // sub_mask_1
6246 0, // sub_xmm
6247 0, // sub_ymm
6248 },
6249 { // VR128
6250 0, // sub_8bit
6251 0, // sub_8bit_hi
6252 0, // sub_8bit_hi_phony
6253 0, // sub_16bit
6254 0, // sub_16bit_hi
6255 0, // sub_32bit
6256 0, // sub_mask_0
6257 0, // sub_mask_1
6258 0, // sub_xmm
6259 0, // sub_ymm
6260 },
6261 { // VR256X
6262 0, // sub_8bit
6263 0, // sub_8bit_hi
6264 0, // sub_8bit_hi_phony
6265 0, // sub_16bit
6266 0, // sub_16bit_hi
6267 0, // sub_32bit
6268 0, // sub_mask_0
6269 0, // sub_mask_1
6270 131, // sub_xmm -> VR256X
6271 0, // sub_ymm
6272 },
6273 { // VR256
6274 0, // sub_8bit
6275 0, // sub_8bit_hi
6276 0, // sub_8bit_hi_phony
6277 0, // sub_16bit
6278 0, // sub_16bit_hi
6279 0, // sub_32bit
6280 0, // sub_mask_0
6281 0, // sub_mask_1
6282 132, // sub_xmm -> VR256
6283 0, // sub_ymm
6284 },
6285 { // VR512
6286 0, // sub_8bit
6287 0, // sub_8bit_hi
6288 0, // sub_8bit_hi_phony
6289 0, // sub_16bit
6290 0, // sub_16bit_hi
6291 0, // sub_32bit
6292 0, // sub_mask_0
6293 0, // sub_mask_1
6294 133, // sub_xmm -> VR512
6295 133, // sub_ymm -> VR512
6296 },
6297 { // VR512_0_15
6298 0, // sub_8bit
6299 0, // sub_8bit_hi
6300 0, // sub_8bit_hi_phony
6301 0, // sub_16bit
6302 0, // sub_16bit_hi
6303 0, // sub_32bit
6304 0, // sub_mask_0
6305 0, // sub_mask_1
6306 134, // sub_xmm -> VR512_0_15
6307 134, // sub_ymm -> VR512_0_15
6308 },
6309 { // TILE
6310 0, // sub_8bit
6311 0, // sub_8bit_hi
6312 0, // sub_8bit_hi_phony
6313 0, // sub_16bit
6314 0, // sub_16bit_hi
6315 0, // sub_32bit
6316 0, // sub_mask_0
6317 0, // sub_mask_1
6318 0, // sub_xmm
6319 0, // sub_ymm
6320 },
6321 };
6322 assert(RC && "Missing regclass");
6323 if (!Idx) return RC;
6324 --Idx;
6325 assert(Idx < 10 && "Bad subreg");
6326 unsigned TV = Table[RC->getID()][Idx];
6327 return TV ? getRegClass(i: TV - 1) : nullptr;
6328}
6329
6330const TargetRegisterClass *X86GenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
6331 static const uint8_t Table[135][10] = {
6332 { // GR8
6333 0, // GR8:sub_8bit
6334 0, // GR8:sub_8bit_hi
6335 0, // GR8:sub_8bit_hi_phony
6336 0, // GR8:sub_16bit
6337 0, // GR8:sub_16bit_hi
6338 0, // GR8:sub_32bit
6339 0, // GR8:sub_mask_0
6340 0, // GR8:sub_mask_1
6341 0, // GR8:sub_xmm
6342 0, // GR8:sub_ymm
6343 },
6344 { // GRH8
6345 0, // GRH8:sub_8bit
6346 0, // GRH8:sub_8bit_hi
6347 0, // GRH8:sub_8bit_hi_phony
6348 0, // GRH8:sub_16bit
6349 0, // GRH8:sub_16bit_hi
6350 0, // GRH8:sub_32bit
6351 0, // GRH8:sub_mask_0
6352 0, // GRH8:sub_mask_1
6353 0, // GRH8:sub_xmm
6354 0, // GRH8:sub_ymm
6355 },
6356 { // GR8_NOREX2
6357 0, // GR8_NOREX2:sub_8bit
6358 0, // GR8_NOREX2:sub_8bit_hi
6359 0, // GR8_NOREX2:sub_8bit_hi_phony
6360 0, // GR8_NOREX2:sub_16bit
6361 0, // GR8_NOREX2:sub_16bit_hi
6362 0, // GR8_NOREX2:sub_32bit
6363 0, // GR8_NOREX2:sub_mask_0
6364 0, // GR8_NOREX2:sub_mask_1
6365 0, // GR8_NOREX2:sub_xmm
6366 0, // GR8_NOREX2:sub_ymm
6367 },
6368 { // GR8_NOREX
6369 0, // GR8_NOREX:sub_8bit
6370 0, // GR8_NOREX:sub_8bit_hi
6371 0, // GR8_NOREX:sub_8bit_hi_phony
6372 0, // GR8_NOREX:sub_16bit
6373 0, // GR8_NOREX:sub_16bit_hi
6374 0, // GR8_NOREX:sub_32bit
6375 0, // GR8_NOREX:sub_mask_0
6376 0, // GR8_NOREX:sub_mask_1
6377 0, // GR8_NOREX:sub_xmm
6378 0, // GR8_NOREX:sub_ymm
6379 },
6380 { // GR8_ABCD_H
6381 0, // GR8_ABCD_H:sub_8bit
6382 0, // GR8_ABCD_H:sub_8bit_hi
6383 0, // GR8_ABCD_H:sub_8bit_hi_phony
6384 0, // GR8_ABCD_H:sub_16bit
6385 0, // GR8_ABCD_H:sub_16bit_hi
6386 0, // GR8_ABCD_H:sub_32bit
6387 0, // GR8_ABCD_H:sub_mask_0
6388 0, // GR8_ABCD_H:sub_mask_1
6389 0, // GR8_ABCD_H:sub_xmm
6390 0, // GR8_ABCD_H:sub_ymm
6391 },
6392 { // GR8_ABCD_L
6393 0, // GR8_ABCD_L:sub_8bit
6394 0, // GR8_ABCD_L:sub_8bit_hi
6395 0, // GR8_ABCD_L:sub_8bit_hi_phony
6396 0, // GR8_ABCD_L:sub_16bit
6397 0, // GR8_ABCD_L:sub_16bit_hi
6398 0, // GR8_ABCD_L:sub_32bit
6399 0, // GR8_ABCD_L:sub_mask_0
6400 0, // GR8_ABCD_L:sub_mask_1
6401 0, // GR8_ABCD_L:sub_xmm
6402 0, // GR8_ABCD_L:sub_ymm
6403 },
6404 { // GRH16
6405 0, // GRH16:sub_8bit
6406 0, // GRH16:sub_8bit_hi
6407 0, // GRH16:sub_8bit_hi_phony
6408 0, // GRH16:sub_16bit
6409 0, // GRH16:sub_16bit_hi
6410 0, // GRH16:sub_32bit
6411 0, // GRH16:sub_mask_0
6412 0, // GRH16:sub_mask_1
6413 0, // GRH16:sub_xmm
6414 0, // GRH16:sub_ymm
6415 },
6416 { // GR16
6417 1, // GR16:sub_8bit -> GR8
6418 5, // GR16:sub_8bit_hi -> GR8_ABCD_H
6419 0, // GR16:sub_8bit_hi_phony
6420 0, // GR16:sub_16bit
6421 0, // GR16:sub_16bit_hi
6422 0, // GR16:sub_32bit
6423 0, // GR16:sub_mask_0
6424 0, // GR16:sub_mask_1
6425 0, // GR16:sub_xmm
6426 0, // GR16:sub_ymm
6427 },
6428 { // GR16_NOREX2
6429 3, // GR16_NOREX2:sub_8bit -> GR8_NOREX2
6430 5, // GR16_NOREX2:sub_8bit_hi -> GR8_ABCD_H
6431 0, // GR16_NOREX2:sub_8bit_hi_phony
6432 0, // GR16_NOREX2:sub_16bit
6433 0, // GR16_NOREX2:sub_16bit_hi
6434 0, // GR16_NOREX2:sub_32bit
6435 0, // GR16_NOREX2:sub_mask_0
6436 0, // GR16_NOREX2:sub_mask_1
6437 0, // GR16_NOREX2:sub_xmm
6438 0, // GR16_NOREX2:sub_ymm
6439 },
6440 { // GR16_NOREX
6441 3, // GR16_NOREX:sub_8bit -> GR8_NOREX2
6442 5, // GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
6443 0, // GR16_NOREX:sub_8bit_hi_phony
6444 0, // GR16_NOREX:sub_16bit
6445 0, // GR16_NOREX:sub_16bit_hi
6446 0, // GR16_NOREX:sub_32bit
6447 0, // GR16_NOREX:sub_mask_0
6448 0, // GR16_NOREX:sub_mask_1
6449 0, // GR16_NOREX:sub_xmm
6450 0, // GR16_NOREX:sub_ymm
6451 },
6452 { // VK1
6453 0, // VK1:sub_8bit
6454 0, // VK1:sub_8bit_hi
6455 0, // VK1:sub_8bit_hi_phony
6456 0, // VK1:sub_16bit
6457 0, // VK1:sub_16bit_hi
6458 0, // VK1:sub_32bit
6459 0, // VK1:sub_mask_0
6460 0, // VK1:sub_mask_1
6461 0, // VK1:sub_xmm
6462 0, // VK1:sub_ymm
6463 },
6464 { // VK16
6465 0, // VK16:sub_8bit
6466 0, // VK16:sub_8bit_hi
6467 0, // VK16:sub_8bit_hi_phony
6468 0, // VK16:sub_16bit
6469 0, // VK16:sub_16bit_hi
6470 0, // VK16:sub_32bit
6471 0, // VK16:sub_mask_0
6472 0, // VK16:sub_mask_1
6473 0, // VK16:sub_xmm
6474 0, // VK16:sub_ymm
6475 },
6476 { // VK2
6477 0, // VK2:sub_8bit
6478 0, // VK2:sub_8bit_hi
6479 0, // VK2:sub_8bit_hi_phony
6480 0, // VK2:sub_16bit
6481 0, // VK2:sub_16bit_hi
6482 0, // VK2:sub_32bit
6483 0, // VK2:sub_mask_0
6484 0, // VK2:sub_mask_1
6485 0, // VK2:sub_xmm
6486 0, // VK2:sub_ymm
6487 },
6488 { // VK4
6489 0, // VK4:sub_8bit
6490 0, // VK4:sub_8bit_hi
6491 0, // VK4:sub_8bit_hi_phony
6492 0, // VK4:sub_16bit
6493 0, // VK4:sub_16bit_hi
6494 0, // VK4:sub_32bit
6495 0, // VK4:sub_mask_0
6496 0, // VK4:sub_mask_1
6497 0, // VK4:sub_xmm
6498 0, // VK4:sub_ymm
6499 },
6500 { // VK8
6501 0, // VK8:sub_8bit
6502 0, // VK8:sub_8bit_hi
6503 0, // VK8:sub_8bit_hi_phony
6504 0, // VK8:sub_16bit
6505 0, // VK8:sub_16bit_hi
6506 0, // VK8:sub_32bit
6507 0, // VK8:sub_mask_0
6508 0, // VK8:sub_mask_1
6509 0, // VK8:sub_xmm
6510 0, // VK8:sub_ymm
6511 },
6512 { // VK16WM
6513 0, // VK16WM:sub_8bit
6514 0, // VK16WM:sub_8bit_hi
6515 0, // VK16WM:sub_8bit_hi_phony
6516 0, // VK16WM:sub_16bit
6517 0, // VK16WM:sub_16bit_hi
6518 0, // VK16WM:sub_32bit
6519 0, // VK16WM:sub_mask_0
6520 0, // VK16WM:sub_mask_1
6521 0, // VK16WM:sub_xmm
6522 0, // VK16WM:sub_ymm
6523 },
6524 { // VK1WM
6525 0, // VK1WM:sub_8bit
6526 0, // VK1WM:sub_8bit_hi
6527 0, // VK1WM:sub_8bit_hi_phony
6528 0, // VK1WM:sub_16bit
6529 0, // VK1WM:sub_16bit_hi
6530 0, // VK1WM:sub_32bit
6531 0, // VK1WM:sub_mask_0
6532 0, // VK1WM:sub_mask_1
6533 0, // VK1WM:sub_xmm
6534 0, // VK1WM:sub_ymm
6535 },
6536 { // VK2WM
6537 0, // VK2WM:sub_8bit
6538 0, // VK2WM:sub_8bit_hi
6539 0, // VK2WM:sub_8bit_hi_phony
6540 0, // VK2WM:sub_16bit
6541 0, // VK2WM:sub_16bit_hi
6542 0, // VK2WM:sub_32bit
6543 0, // VK2WM:sub_mask_0
6544 0, // VK2WM:sub_mask_1
6545 0, // VK2WM:sub_xmm
6546 0, // VK2WM:sub_ymm
6547 },
6548 { // VK4WM
6549 0, // VK4WM:sub_8bit
6550 0, // VK4WM:sub_8bit_hi
6551 0, // VK4WM:sub_8bit_hi_phony
6552 0, // VK4WM:sub_16bit
6553 0, // VK4WM:sub_16bit_hi
6554 0, // VK4WM:sub_32bit
6555 0, // VK4WM:sub_mask_0
6556 0, // VK4WM:sub_mask_1
6557 0, // VK4WM:sub_xmm
6558 0, // VK4WM:sub_ymm
6559 },
6560 { // VK8WM
6561 0, // VK8WM:sub_8bit
6562 0, // VK8WM:sub_8bit_hi
6563 0, // VK8WM:sub_8bit_hi_phony
6564 0, // VK8WM:sub_16bit
6565 0, // VK8WM:sub_16bit_hi
6566 0, // VK8WM:sub_32bit
6567 0, // VK8WM:sub_mask_0
6568 0, // VK8WM:sub_mask_1
6569 0, // VK8WM:sub_xmm
6570 0, // VK8WM:sub_ymm
6571 },
6572 { // SEGMENT_REG
6573 0, // SEGMENT_REG:sub_8bit
6574 0, // SEGMENT_REG:sub_8bit_hi
6575 0, // SEGMENT_REG:sub_8bit_hi_phony
6576 0, // SEGMENT_REG:sub_16bit
6577 0, // SEGMENT_REG:sub_16bit_hi
6578 0, // SEGMENT_REG:sub_32bit
6579 0, // SEGMENT_REG:sub_mask_0
6580 0, // SEGMENT_REG:sub_mask_1
6581 0, // SEGMENT_REG:sub_xmm
6582 0, // SEGMENT_REG:sub_ymm
6583 },
6584 { // GR16_ABCD
6585 6, // GR16_ABCD:sub_8bit -> GR8_ABCD_L
6586 5, // GR16_ABCD:sub_8bit_hi -> GR8_ABCD_H
6587 0, // GR16_ABCD:sub_8bit_hi_phony
6588 0, // GR16_ABCD:sub_16bit
6589 0, // GR16_ABCD:sub_16bit_hi
6590 0, // GR16_ABCD:sub_32bit
6591 0, // GR16_ABCD:sub_mask_0
6592 0, // GR16_ABCD:sub_mask_1
6593 0, // GR16_ABCD:sub_xmm
6594 0, // GR16_ABCD:sub_ymm
6595 },
6596 { // FPCCR
6597 0, // FPCCR:sub_8bit
6598 0, // FPCCR:sub_8bit_hi
6599 0, // FPCCR:sub_8bit_hi_phony
6600 0, // FPCCR:sub_16bit
6601 0, // FPCCR:sub_16bit_hi
6602 0, // FPCCR:sub_32bit
6603 0, // FPCCR:sub_mask_0
6604 0, // FPCCR:sub_mask_1
6605 0, // FPCCR:sub_xmm
6606 0, // FPCCR:sub_ymm
6607 },
6608 { // FR16X
6609 0, // FR16X:sub_8bit
6610 0, // FR16X:sub_8bit_hi
6611 0, // FR16X:sub_8bit_hi_phony
6612 0, // FR16X:sub_16bit
6613 0, // FR16X:sub_16bit_hi
6614 0, // FR16X:sub_32bit
6615 0, // FR16X:sub_mask_0
6616 0, // FR16X:sub_mask_1
6617 0, // FR16X:sub_xmm
6618 0, // FR16X:sub_ymm
6619 },
6620 { // FR16
6621 0, // FR16:sub_8bit
6622 0, // FR16:sub_8bit_hi
6623 0, // FR16:sub_8bit_hi_phony
6624 0, // FR16:sub_16bit
6625 0, // FR16:sub_16bit_hi
6626 0, // FR16:sub_32bit
6627 0, // FR16:sub_mask_0
6628 0, // FR16:sub_mask_1
6629 0, // FR16:sub_xmm
6630 0, // FR16:sub_ymm
6631 },
6632 { // VK16PAIR
6633 0, // VK16PAIR:sub_8bit
6634 0, // VK16PAIR:sub_8bit_hi
6635 0, // VK16PAIR:sub_8bit_hi_phony
6636 0, // VK16PAIR:sub_16bit
6637 0, // VK16PAIR:sub_16bit_hi
6638 0, // VK16PAIR:sub_32bit
6639 91, // VK16PAIR:sub_mask_0 -> VK64
6640 98, // VK16PAIR:sub_mask_1 -> VK64WM
6641 0, // VK16PAIR:sub_xmm
6642 0, // VK16PAIR:sub_ymm
6643 },
6644 { // VK1PAIR
6645 0, // VK1PAIR:sub_8bit
6646 0, // VK1PAIR:sub_8bit_hi
6647 0, // VK1PAIR:sub_8bit_hi_phony
6648 0, // VK1PAIR:sub_16bit
6649 0, // VK1PAIR:sub_16bit_hi
6650 0, // VK1PAIR:sub_32bit
6651 91, // VK1PAIR:sub_mask_0 -> VK64
6652 98, // VK1PAIR:sub_mask_1 -> VK64WM
6653 0, // VK1PAIR:sub_xmm
6654 0, // VK1PAIR:sub_ymm
6655 },
6656 { // VK2PAIR
6657 0, // VK2PAIR:sub_8bit
6658 0, // VK2PAIR:sub_8bit_hi
6659 0, // VK2PAIR:sub_8bit_hi_phony
6660 0, // VK2PAIR:sub_16bit
6661 0, // VK2PAIR:sub_16bit_hi
6662 0, // VK2PAIR:sub_32bit
6663 91, // VK2PAIR:sub_mask_0 -> VK64
6664 98, // VK2PAIR:sub_mask_1 -> VK64WM
6665 0, // VK2PAIR:sub_xmm
6666 0, // VK2PAIR:sub_ymm
6667 },
6668 { // VK4PAIR
6669 0, // VK4PAIR:sub_8bit
6670 0, // VK4PAIR:sub_8bit_hi
6671 0, // VK4PAIR:sub_8bit_hi_phony
6672 0, // VK4PAIR:sub_16bit
6673 0, // VK4PAIR:sub_16bit_hi
6674 0, // VK4PAIR:sub_32bit
6675 91, // VK4PAIR:sub_mask_0 -> VK64
6676 98, // VK4PAIR:sub_mask_1 -> VK64WM
6677 0, // VK4PAIR:sub_xmm
6678 0, // VK4PAIR:sub_ymm
6679 },
6680 { // VK8PAIR
6681 0, // VK8PAIR:sub_8bit
6682 0, // VK8PAIR:sub_8bit_hi
6683 0, // VK8PAIR:sub_8bit_hi_phony
6684 0, // VK8PAIR:sub_16bit
6685 0, // VK8PAIR:sub_16bit_hi
6686 0, // VK8PAIR:sub_32bit
6687 91, // VK8PAIR:sub_mask_0 -> VK64
6688 98, // VK8PAIR:sub_mask_1 -> VK64WM
6689 0, // VK8PAIR:sub_xmm
6690 0, // VK8PAIR:sub_ymm
6691 },
6692 { // VK1PAIR_with_sub_mask_0_in_VK1WM
6693 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_8bit
6694 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_8bit_hi
6695 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_8bit_hi_phony
6696 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_16bit
6697 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_16bit_hi
6698 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_32bit
6699 98, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_mask_0 -> VK64WM
6700 98, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_mask_1 -> VK64WM
6701 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_xmm
6702 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_ymm
6703 },
6704 { // LOW32_ADDR_ACCESS_RBP
6705 1, // LOW32_ADDR_ACCESS_RBP:sub_8bit -> GR8
6706 5, // LOW32_ADDR_ACCESS_RBP:sub_8bit_hi -> GR8_ABCD_H
6707 0, // LOW32_ADDR_ACCESS_RBP:sub_8bit_hi_phony
6708 8, // LOW32_ADDR_ACCESS_RBP:sub_16bit -> GR16
6709 0, // LOW32_ADDR_ACCESS_RBP:sub_16bit_hi
6710 66, // LOW32_ADDR_ACCESS_RBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
6711 0, // LOW32_ADDR_ACCESS_RBP:sub_mask_0
6712 0, // LOW32_ADDR_ACCESS_RBP:sub_mask_1
6713 0, // LOW32_ADDR_ACCESS_RBP:sub_xmm
6714 0, // LOW32_ADDR_ACCESS_RBP:sub_ymm
6715 },
6716 { // LOW32_ADDR_ACCESS
6717 1, // LOW32_ADDR_ACCESS:sub_8bit -> GR8
6718 5, // LOW32_ADDR_ACCESS:sub_8bit_hi -> GR8_ABCD_H
6719 0, // LOW32_ADDR_ACCESS:sub_8bit_hi_phony
6720 8, // LOW32_ADDR_ACCESS:sub_16bit -> GR16
6721 0, // LOW32_ADDR_ACCESS:sub_16bit_hi
6722 0, // LOW32_ADDR_ACCESS:sub_32bit
6723 0, // LOW32_ADDR_ACCESS:sub_mask_0
6724 0, // LOW32_ADDR_ACCESS:sub_mask_1
6725 0, // LOW32_ADDR_ACCESS:sub_xmm
6726 0, // LOW32_ADDR_ACCESS:sub_ymm
6727 },
6728 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
6729 1, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit -> GR8
6730 5, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
6731 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit_hi_phony
6732 8, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_16bit -> GR16
6733 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_16bit_hi
6734 66, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
6735 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_mask_0
6736 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_mask_1
6737 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_xmm
6738 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_ymm
6739 },
6740 { // FR32X
6741 0, // FR32X:sub_8bit
6742 0, // FR32X:sub_8bit_hi
6743 0, // FR32X:sub_8bit_hi_phony
6744 0, // FR32X:sub_16bit
6745 0, // FR32X:sub_16bit_hi
6746 0, // FR32X:sub_32bit
6747 0, // FR32X:sub_mask_0
6748 0, // FR32X:sub_mask_1
6749 0, // FR32X:sub_xmm
6750 0, // FR32X:sub_ymm
6751 },
6752 { // GR32
6753 1, // GR32:sub_8bit -> GR8
6754 5, // GR32:sub_8bit_hi -> GR8_ABCD_H
6755 0, // GR32:sub_8bit_hi_phony
6756 8, // GR32:sub_16bit -> GR16
6757 0, // GR32:sub_16bit_hi
6758 0, // GR32:sub_32bit
6759 0, // GR32:sub_mask_0
6760 0, // GR32:sub_mask_1
6761 0, // GR32:sub_xmm
6762 0, // GR32:sub_ymm
6763 },
6764 { // GR32_NOSP
6765 1, // GR32_NOSP:sub_8bit -> GR8
6766 5, // GR32_NOSP:sub_8bit_hi -> GR8_ABCD_H
6767 0, // GR32_NOSP:sub_8bit_hi_phony
6768 8, // GR32_NOSP:sub_16bit -> GR16
6769 0, // GR32_NOSP:sub_16bit_hi
6770 0, // GR32_NOSP:sub_32bit
6771 0, // GR32_NOSP:sub_mask_0
6772 0, // GR32_NOSP:sub_mask_1
6773 0, // GR32_NOSP:sub_xmm
6774 0, // GR32_NOSP:sub_ymm
6775 },
6776 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
6777 3, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_8bit -> GR8_NOREX2
6778 5, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi -> GR8_ABCD_H
6779 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi_phony
6780 9, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_16bit -> GR16_NOREX2
6781 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_16bit_hi
6782 66, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_32bit -> GR32_BPSP_and_GR32_DIBP
6783 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_mask_0
6784 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_mask_1
6785 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_xmm
6786 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_ymm
6787 },
6788 { // DEBUG_REG
6789 0, // DEBUG_REG:sub_8bit
6790 0, // DEBUG_REG:sub_8bit_hi
6791 0, // DEBUG_REG:sub_8bit_hi_phony
6792 0, // DEBUG_REG:sub_16bit
6793 0, // DEBUG_REG:sub_16bit_hi
6794 0, // DEBUG_REG:sub_32bit
6795 0, // DEBUG_REG:sub_mask_0
6796 0, // DEBUG_REG:sub_mask_1
6797 0, // DEBUG_REG:sub_xmm
6798 0, // DEBUG_REG:sub_ymm
6799 },
6800 { // FR32
6801 0, // FR32:sub_8bit
6802 0, // FR32:sub_8bit_hi
6803 0, // FR32:sub_8bit_hi_phony
6804 0, // FR32:sub_16bit
6805 0, // FR32:sub_16bit_hi
6806 0, // FR32:sub_32bit
6807 0, // FR32:sub_mask_0
6808 0, // FR32:sub_mask_1
6809 0, // FR32:sub_xmm
6810 0, // FR32:sub_ymm
6811 },
6812 { // GR32_NOREX2
6813 3, // GR32_NOREX2:sub_8bit -> GR8_NOREX2
6814 5, // GR32_NOREX2:sub_8bit_hi -> GR8_ABCD_H
6815 0, // GR32_NOREX2:sub_8bit_hi_phony
6816 9, // GR32_NOREX2:sub_16bit -> GR16_NOREX2
6817 0, // GR32_NOREX2:sub_16bit_hi
6818 0, // GR32_NOREX2:sub_32bit
6819 0, // GR32_NOREX2:sub_mask_0
6820 0, // GR32_NOREX2:sub_mask_1
6821 0, // GR32_NOREX2:sub_xmm
6822 0, // GR32_NOREX2:sub_ymm
6823 },
6824 { // GR32_NOREX2_NOSP
6825 3, // GR32_NOREX2_NOSP:sub_8bit -> GR8_NOREX2
6826 5, // GR32_NOREX2_NOSP:sub_8bit_hi -> GR8_ABCD_H
6827 0, // GR32_NOREX2_NOSP:sub_8bit_hi_phony
6828 9, // GR32_NOREX2_NOSP:sub_16bit -> GR16_NOREX2
6829 0, // GR32_NOREX2_NOSP:sub_16bit_hi
6830 0, // GR32_NOREX2_NOSP:sub_32bit
6831 0, // GR32_NOREX2_NOSP:sub_mask_0
6832 0, // GR32_NOREX2_NOSP:sub_mask_1
6833 0, // GR32_NOREX2_NOSP:sub_xmm
6834 0, // GR32_NOREX2_NOSP:sub_ymm
6835 },
6836 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
6837 3, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8_NOREX2
6838 5, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
6839 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
6840 10, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
6841 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
6842 66, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_BPSP_and_GR32_DIBP
6843 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_mask_0
6844 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_mask_1
6845 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_xmm
6846 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_ymm
6847 },
6848 { // GR32_NOREX
6849 3, // GR32_NOREX:sub_8bit -> GR8_NOREX2
6850 5, // GR32_NOREX:sub_8bit_hi -> GR8_ABCD_H
6851 0, // GR32_NOREX:sub_8bit_hi_phony
6852 10, // GR32_NOREX:sub_16bit -> GR16_NOREX
6853 0, // GR32_NOREX:sub_16bit_hi
6854 0, // GR32_NOREX:sub_32bit
6855 0, // GR32_NOREX:sub_mask_0
6856 0, // GR32_NOREX:sub_mask_1
6857 0, // GR32_NOREX:sub_xmm
6858 0, // GR32_NOREX:sub_ymm
6859 },
6860 { // VK32
6861 0, // VK32:sub_8bit
6862 0, // VK32:sub_8bit_hi
6863 0, // VK32:sub_8bit_hi_phony
6864 0, // VK32:sub_16bit
6865 0, // VK32:sub_16bit_hi
6866 0, // VK32:sub_32bit
6867 0, // VK32:sub_mask_0
6868 0, // VK32:sub_mask_1
6869 0, // VK32:sub_xmm
6870 0, // VK32:sub_ymm
6871 },
6872 { // GR32_NOREX_NOSP
6873 3, // GR32_NOREX_NOSP:sub_8bit -> GR8_NOREX2
6874 5, // GR32_NOREX_NOSP:sub_8bit_hi -> GR8_ABCD_H
6875 0, // GR32_NOREX_NOSP:sub_8bit_hi_phony
6876 10, // GR32_NOREX_NOSP:sub_16bit -> GR16_NOREX
6877 0, // GR32_NOREX_NOSP:sub_16bit_hi
6878 0, // GR32_NOREX_NOSP:sub_32bit
6879 0, // GR32_NOREX_NOSP:sub_mask_0
6880 0, // GR32_NOREX_NOSP:sub_mask_1
6881 0, // GR32_NOREX_NOSP:sub_xmm
6882 0, // GR32_NOREX_NOSP:sub_ymm
6883 },
6884 { // RFP32
6885 0, // RFP32:sub_8bit
6886 0, // RFP32:sub_8bit_hi
6887 0, // RFP32:sub_8bit_hi_phony
6888 0, // RFP32:sub_16bit
6889 0, // RFP32:sub_16bit_hi
6890 0, // RFP32:sub_32bit
6891 0, // RFP32:sub_mask_0
6892 0, // RFP32:sub_mask_1
6893 0, // RFP32:sub_xmm
6894 0, // RFP32:sub_ymm
6895 },
6896 { // VK32WM
6897 0, // VK32WM:sub_8bit
6898 0, // VK32WM:sub_8bit_hi
6899 0, // VK32WM:sub_8bit_hi_phony
6900 0, // VK32WM:sub_16bit
6901 0, // VK32WM:sub_16bit_hi
6902 0, // VK32WM:sub_32bit
6903 0, // VK32WM:sub_mask_0
6904 0, // VK32WM:sub_mask_1
6905 0, // VK32WM:sub_xmm
6906 0, // VK32WM:sub_ymm
6907 },
6908 { // GR32_ABCD
6909 6, // GR32_ABCD:sub_8bit -> GR8_ABCD_L
6910 5, // GR32_ABCD:sub_8bit_hi -> GR8_ABCD_H
6911 0, // GR32_ABCD:sub_8bit_hi_phony
6912 22, // GR32_ABCD:sub_16bit -> GR16_ABCD
6913 0, // GR32_ABCD:sub_16bit_hi
6914 0, // GR32_ABCD:sub_32bit
6915 0, // GR32_ABCD:sub_mask_0
6916 0, // GR32_ABCD:sub_mask_1
6917 0, // GR32_ABCD:sub_xmm
6918 0, // GR32_ABCD:sub_ymm
6919 },
6920 { // GR32_TC
6921 3, // GR32_TC:sub_8bit -> GR8_NOREX2
6922 5, // GR32_TC:sub_8bit_hi -> GR8_ABCD_H
6923 0, // GR32_TC:sub_8bit_hi_phony
6924 10, // GR32_TC:sub_16bit -> GR16_NOREX
6925 0, // GR32_TC:sub_16bit_hi
6926 0, // GR32_TC:sub_32bit
6927 0, // GR32_TC:sub_mask_0
6928 0, // GR32_TC:sub_mask_1
6929 0, // GR32_TC:sub_xmm
6930 0, // GR32_TC:sub_ymm
6931 },
6932 { // GR32_ABCD_and_GR32_TC
6933 6, // GR32_ABCD_and_GR32_TC:sub_8bit -> GR8_ABCD_L
6934 5, // GR32_ABCD_and_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
6935 0, // GR32_ABCD_and_GR32_TC:sub_8bit_hi_phony
6936 22, // GR32_ABCD_and_GR32_TC:sub_16bit -> GR16_ABCD
6937 0, // GR32_ABCD_and_GR32_TC:sub_16bit_hi
6938 0, // GR32_ABCD_and_GR32_TC:sub_32bit
6939 0, // GR32_ABCD_and_GR32_TC:sub_mask_0
6940 0, // GR32_ABCD_and_GR32_TC:sub_mask_1
6941 0, // GR32_ABCD_and_GR32_TC:sub_xmm
6942 0, // GR32_ABCD_and_GR32_TC:sub_ymm
6943 },
6944 { // GR32_AD
6945 6, // GR32_AD:sub_8bit -> GR8_ABCD_L
6946 5, // GR32_AD:sub_8bit_hi -> GR8_ABCD_H
6947 0, // GR32_AD:sub_8bit_hi_phony
6948 22, // GR32_AD:sub_16bit -> GR16_ABCD
6949 0, // GR32_AD:sub_16bit_hi
6950 0, // GR32_AD:sub_32bit
6951 0, // GR32_AD:sub_mask_0
6952 0, // GR32_AD:sub_mask_1
6953 0, // GR32_AD:sub_xmm
6954 0, // GR32_AD:sub_ymm
6955 },
6956 { // GR32_ArgRef
6957 6, // GR32_ArgRef:sub_8bit -> GR8_ABCD_L
6958 5, // GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
6959 0, // GR32_ArgRef:sub_8bit_hi_phony
6960 22, // GR32_ArgRef:sub_16bit -> GR16_ABCD
6961 0, // GR32_ArgRef:sub_16bit_hi
6962 0, // GR32_ArgRef:sub_32bit
6963 0, // GR32_ArgRef:sub_mask_0
6964 0, // GR32_ArgRef:sub_mask_1
6965 0, // GR32_ArgRef:sub_xmm
6966 0, // GR32_ArgRef:sub_ymm
6967 },
6968 { // GR32_BPSP
6969 3, // GR32_BPSP:sub_8bit -> GR8_NOREX2
6970 0, // GR32_BPSP:sub_8bit_hi
6971 0, // GR32_BPSP:sub_8bit_hi_phony
6972 10, // GR32_BPSP:sub_16bit -> GR16_NOREX
6973 0, // GR32_BPSP:sub_16bit_hi
6974 0, // GR32_BPSP:sub_32bit
6975 0, // GR32_BPSP:sub_mask_0
6976 0, // GR32_BPSP:sub_mask_1
6977 0, // GR32_BPSP:sub_xmm
6978 0, // GR32_BPSP:sub_ymm
6979 },
6980 { // GR32_BSI
6981 3, // GR32_BSI:sub_8bit -> GR8_NOREX2
6982 5, // GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
6983 0, // GR32_BSI:sub_8bit_hi_phony
6984 10, // GR32_BSI:sub_16bit -> GR16_NOREX
6985 0, // GR32_BSI:sub_16bit_hi
6986 0, // GR32_BSI:sub_32bit
6987 0, // GR32_BSI:sub_mask_0
6988 0, // GR32_BSI:sub_mask_1
6989 0, // GR32_BSI:sub_xmm
6990 0, // GR32_BSI:sub_ymm
6991 },
6992 { // GR32_CB
6993 6, // GR32_CB:sub_8bit -> GR8_ABCD_L
6994 5, // GR32_CB:sub_8bit_hi -> GR8_ABCD_H
6995 0, // GR32_CB:sub_8bit_hi_phony
6996 22, // GR32_CB:sub_16bit -> GR16_ABCD
6997 0, // GR32_CB:sub_16bit_hi
6998 0, // GR32_CB:sub_32bit
6999 0, // GR32_CB:sub_mask_0
7000 0, // GR32_CB:sub_mask_1
7001 0, // GR32_CB:sub_xmm
7002 0, // GR32_CB:sub_ymm
7003 },
7004 { // GR32_DC
7005 6, // GR32_DC:sub_8bit -> GR8_ABCD_L
7006 5, // GR32_DC:sub_8bit_hi -> GR8_ABCD_H
7007 0, // GR32_DC:sub_8bit_hi_phony
7008 22, // GR32_DC:sub_16bit -> GR16_ABCD
7009 0, // GR32_DC:sub_16bit_hi
7010 0, // GR32_DC:sub_32bit
7011 0, // GR32_DC:sub_mask_0
7012 0, // GR32_DC:sub_mask_1
7013 0, // GR32_DC:sub_xmm
7014 0, // GR32_DC:sub_ymm
7015 },
7016 { // GR32_DIBP
7017 3, // GR32_DIBP:sub_8bit -> GR8_NOREX2
7018 0, // GR32_DIBP:sub_8bit_hi
7019 0, // GR32_DIBP:sub_8bit_hi_phony
7020 10, // GR32_DIBP:sub_16bit -> GR16_NOREX
7021 0, // GR32_DIBP:sub_16bit_hi
7022 0, // GR32_DIBP:sub_32bit
7023 0, // GR32_DIBP:sub_mask_0
7024 0, // GR32_DIBP:sub_mask_1
7025 0, // GR32_DIBP:sub_xmm
7026 0, // GR32_DIBP:sub_ymm
7027 },
7028 { // GR32_SIDI
7029 3, // GR32_SIDI:sub_8bit -> GR8_NOREX2
7030 0, // GR32_SIDI:sub_8bit_hi
7031 0, // GR32_SIDI:sub_8bit_hi_phony
7032 10, // GR32_SIDI:sub_16bit -> GR16_NOREX
7033 0, // GR32_SIDI:sub_16bit_hi
7034 0, // GR32_SIDI:sub_32bit
7035 0, // GR32_SIDI:sub_mask_0
7036 0, // GR32_SIDI:sub_mask_1
7037 0, // GR32_SIDI:sub_xmm
7038 0, // GR32_SIDI:sub_ymm
7039 },
7040 { // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
7041 3, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit -> GR8_NOREX2
7042 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit_hi
7043 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit_hi_phony
7044 10, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_16bit -> GR16_NOREX
7045 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_16bit_hi
7046 66, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
7047 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_mask_0
7048 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_mask_1
7049 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_xmm
7050 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_ymm
7051 },
7052 { // CCR
7053 0, // CCR:sub_8bit
7054 0, // CCR:sub_8bit_hi
7055 0, // CCR:sub_8bit_hi_phony
7056 0, // CCR:sub_16bit
7057 0, // CCR:sub_16bit_hi
7058 0, // CCR:sub_32bit
7059 0, // CCR:sub_mask_0
7060 0, // CCR:sub_mask_1
7061 0, // CCR:sub_xmm
7062 0, // CCR:sub_ymm
7063 },
7064 { // DFCCR
7065 0, // DFCCR:sub_8bit
7066 0, // DFCCR:sub_8bit_hi
7067 0, // DFCCR:sub_8bit_hi_phony
7068 0, // DFCCR:sub_16bit
7069 0, // DFCCR:sub_16bit_hi
7070 0, // DFCCR:sub_32bit
7071 0, // DFCCR:sub_mask_0
7072 0, // DFCCR:sub_mask_1
7073 0, // DFCCR:sub_xmm
7074 0, // DFCCR:sub_ymm
7075 },
7076 { // GR32_ABCD_and_GR32_BSI
7077 6, // GR32_ABCD_and_GR32_BSI:sub_8bit -> GR8_ABCD_L
7078 5, // GR32_ABCD_and_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
7079 0, // GR32_ABCD_and_GR32_BSI:sub_8bit_hi_phony
7080 22, // GR32_ABCD_and_GR32_BSI:sub_16bit -> GR16_ABCD
7081 0, // GR32_ABCD_and_GR32_BSI:sub_16bit_hi
7082 0, // GR32_ABCD_and_GR32_BSI:sub_32bit
7083 0, // GR32_ABCD_and_GR32_BSI:sub_mask_0
7084 0, // GR32_ABCD_and_GR32_BSI:sub_mask_1
7085 0, // GR32_ABCD_and_GR32_BSI:sub_xmm
7086 0, // GR32_ABCD_and_GR32_BSI:sub_ymm
7087 },
7088 { // GR32_AD_and_GR32_ArgRef
7089 6, // GR32_AD_and_GR32_ArgRef:sub_8bit -> GR8_ABCD_L
7090 5, // GR32_AD_and_GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
7091 0, // GR32_AD_and_GR32_ArgRef:sub_8bit_hi_phony
7092 22, // GR32_AD_and_GR32_ArgRef:sub_16bit -> GR16_ABCD
7093 0, // GR32_AD_and_GR32_ArgRef:sub_16bit_hi
7094 0, // GR32_AD_and_GR32_ArgRef:sub_32bit
7095 0, // GR32_AD_and_GR32_ArgRef:sub_mask_0
7096 0, // GR32_AD_and_GR32_ArgRef:sub_mask_1
7097 0, // GR32_AD_and_GR32_ArgRef:sub_xmm
7098 0, // GR32_AD_and_GR32_ArgRef:sub_ymm
7099 },
7100 { // GR32_ArgRef_and_GR32_CB
7101 6, // GR32_ArgRef_and_GR32_CB:sub_8bit -> GR8_ABCD_L
7102 5, // GR32_ArgRef_and_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
7103 0, // GR32_ArgRef_and_GR32_CB:sub_8bit_hi_phony
7104 22, // GR32_ArgRef_and_GR32_CB:sub_16bit -> GR16_ABCD
7105 0, // GR32_ArgRef_and_GR32_CB:sub_16bit_hi
7106 0, // GR32_ArgRef_and_GR32_CB:sub_32bit
7107 0, // GR32_ArgRef_and_GR32_CB:sub_mask_0
7108 0, // GR32_ArgRef_and_GR32_CB:sub_mask_1
7109 0, // GR32_ArgRef_and_GR32_CB:sub_xmm
7110 0, // GR32_ArgRef_and_GR32_CB:sub_ymm
7111 },
7112 { // GR32_BPSP_and_GR32_DIBP
7113 3, // GR32_BPSP_and_GR32_DIBP:sub_8bit -> GR8_NOREX2
7114 0, // GR32_BPSP_and_GR32_DIBP:sub_8bit_hi
7115 0, // GR32_BPSP_and_GR32_DIBP:sub_8bit_hi_phony
7116 10, // GR32_BPSP_and_GR32_DIBP:sub_16bit -> GR16_NOREX
7117 0, // GR32_BPSP_and_GR32_DIBP:sub_16bit_hi
7118 0, // GR32_BPSP_and_GR32_DIBP:sub_32bit
7119 0, // GR32_BPSP_and_GR32_DIBP:sub_mask_0
7120 0, // GR32_BPSP_and_GR32_DIBP:sub_mask_1
7121 0, // GR32_BPSP_and_GR32_DIBP:sub_xmm
7122 0, // GR32_BPSP_and_GR32_DIBP:sub_ymm
7123 },
7124 { // GR32_BPSP_and_GR32_TC
7125 3, // GR32_BPSP_and_GR32_TC:sub_8bit -> GR8_NOREX2
7126 0, // GR32_BPSP_and_GR32_TC:sub_8bit_hi
7127 0, // GR32_BPSP_and_GR32_TC:sub_8bit_hi_phony
7128 10, // GR32_BPSP_and_GR32_TC:sub_16bit -> GR16_NOREX
7129 0, // GR32_BPSP_and_GR32_TC:sub_16bit_hi
7130 0, // GR32_BPSP_and_GR32_TC:sub_32bit
7131 0, // GR32_BPSP_and_GR32_TC:sub_mask_0
7132 0, // GR32_BPSP_and_GR32_TC:sub_mask_1
7133 0, // GR32_BPSP_and_GR32_TC:sub_xmm
7134 0, // GR32_BPSP_and_GR32_TC:sub_ymm
7135 },
7136 { // GR32_BSI_and_GR32_SIDI
7137 3, // GR32_BSI_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
7138 0, // GR32_BSI_and_GR32_SIDI:sub_8bit_hi
7139 0, // GR32_BSI_and_GR32_SIDI:sub_8bit_hi_phony
7140 10, // GR32_BSI_and_GR32_SIDI:sub_16bit -> GR16_NOREX
7141 0, // GR32_BSI_and_GR32_SIDI:sub_16bit_hi
7142 0, // GR32_BSI_and_GR32_SIDI:sub_32bit
7143 0, // GR32_BSI_and_GR32_SIDI:sub_mask_0
7144 0, // GR32_BSI_and_GR32_SIDI:sub_mask_1
7145 0, // GR32_BSI_and_GR32_SIDI:sub_xmm
7146 0, // GR32_BSI_and_GR32_SIDI:sub_ymm
7147 },
7148 { // GR32_DIBP_and_GR32_SIDI
7149 3, // GR32_DIBP_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
7150 0, // GR32_DIBP_and_GR32_SIDI:sub_8bit_hi
7151 0, // GR32_DIBP_and_GR32_SIDI:sub_8bit_hi_phony
7152 10, // GR32_DIBP_and_GR32_SIDI:sub_16bit -> GR16_NOREX
7153 0, // GR32_DIBP_and_GR32_SIDI:sub_16bit_hi
7154 0, // GR32_DIBP_and_GR32_SIDI:sub_32bit
7155 0, // GR32_DIBP_and_GR32_SIDI:sub_mask_0
7156 0, // GR32_DIBP_and_GR32_SIDI:sub_mask_1
7157 0, // GR32_DIBP_and_GR32_SIDI:sub_xmm
7158 0, // GR32_DIBP_and_GR32_SIDI:sub_ymm
7159 },
7160 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
7161 3, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit -> GR8_NOREX2
7162 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit_hi
7163 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit_hi_phony
7164 10, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_16bit -> GR16_NOREX
7165 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_16bit_hi
7166 66, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
7167 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_mask_0
7168 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_mask_1
7169 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_xmm
7170 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_ymm
7171 },
7172 { // LOW32_ADDR_ACCESS_with_sub_32bit
7173 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit
7174 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit_hi
7175 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit_hi_phony
7176 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_16bit
7177 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_16bit_hi
7178 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_32bit
7179 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_mask_0
7180 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_mask_1
7181 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_xmm
7182 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_ymm
7183 },
7184 { // RFP64
7185 0, // RFP64:sub_8bit
7186 0, // RFP64:sub_8bit_hi
7187 0, // RFP64:sub_8bit_hi_phony
7188 0, // RFP64:sub_16bit
7189 0, // RFP64:sub_16bit_hi
7190 0, // RFP64:sub_32bit
7191 0, // RFP64:sub_mask_0
7192 0, // RFP64:sub_mask_1
7193 0, // RFP64:sub_xmm
7194 0, // RFP64:sub_ymm
7195 },
7196 { // GR64
7197 1, // GR64:sub_8bit -> GR8
7198 5, // GR64:sub_8bit_hi -> GR8_ABCD_H
7199 0, // GR64:sub_8bit_hi_phony
7200 8, // GR64:sub_16bit -> GR16
7201 0, // GR64:sub_16bit_hi
7202 36, // GR64:sub_32bit -> GR32
7203 0, // GR64:sub_mask_0
7204 0, // GR64:sub_mask_1
7205 0, // GR64:sub_xmm
7206 0, // GR64:sub_ymm
7207 },
7208 { // FR64X
7209 0, // FR64X:sub_8bit
7210 0, // FR64X:sub_8bit_hi
7211 0, // FR64X:sub_8bit_hi_phony
7212 0, // FR64X:sub_16bit
7213 0, // FR64X:sub_16bit_hi
7214 0, // FR64X:sub_32bit
7215 0, // FR64X:sub_mask_0
7216 0, // FR64X:sub_mask_1
7217 0, // FR64X:sub_xmm
7218 0, // FR64X:sub_ymm
7219 },
7220 { // GR64_with_sub_8bit
7221 1, // GR64_with_sub_8bit:sub_8bit -> GR8
7222 5, // GR64_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
7223 0, // GR64_with_sub_8bit:sub_8bit_hi_phony
7224 8, // GR64_with_sub_8bit:sub_16bit -> GR16
7225 0, // GR64_with_sub_8bit:sub_16bit_hi
7226 36, // GR64_with_sub_8bit:sub_32bit -> GR32
7227 0, // GR64_with_sub_8bit:sub_mask_0
7228 0, // GR64_with_sub_8bit:sub_mask_1
7229 0, // GR64_with_sub_8bit:sub_xmm
7230 0, // GR64_with_sub_8bit:sub_ymm
7231 },
7232 { // GR64_NOSP
7233 1, // GR64_NOSP:sub_8bit -> GR8
7234 5, // GR64_NOSP:sub_8bit_hi -> GR8_ABCD_H
7235 0, // GR64_NOSP:sub_8bit_hi_phony
7236 8, // GR64_NOSP:sub_16bit -> GR16
7237 0, // GR64_NOSP:sub_16bit_hi
7238 37, // GR64_NOSP:sub_32bit -> GR32_NOSP
7239 0, // GR64_NOSP:sub_mask_0
7240 0, // GR64_NOSP:sub_mask_1
7241 0, // GR64_NOSP:sub_xmm
7242 0, // GR64_NOSP:sub_ymm
7243 },
7244 { // GR64_NOREX2
7245 3, // GR64_NOREX2:sub_8bit -> GR8_NOREX2
7246 5, // GR64_NOREX2:sub_8bit_hi -> GR8_ABCD_H
7247 0, // GR64_NOREX2:sub_8bit_hi_phony
7248 9, // GR64_NOREX2:sub_16bit -> GR16_NOREX2
7249 0, // GR64_NOREX2:sub_16bit_hi
7250 41, // GR64_NOREX2:sub_32bit -> GR32_NOREX2
7251 0, // GR64_NOREX2:sub_mask_0
7252 0, // GR64_NOREX2:sub_mask_1
7253 0, // GR64_NOREX2:sub_xmm
7254 0, // GR64_NOREX2:sub_ymm
7255 },
7256 { // CONTROL_REG
7257 0, // CONTROL_REG:sub_8bit
7258 0, // CONTROL_REG:sub_8bit_hi
7259 0, // CONTROL_REG:sub_8bit_hi_phony
7260 0, // CONTROL_REG:sub_16bit
7261 0, // CONTROL_REG:sub_16bit_hi
7262 0, // CONTROL_REG:sub_32bit
7263 0, // CONTROL_REG:sub_mask_0
7264 0, // CONTROL_REG:sub_mask_1
7265 0, // CONTROL_REG:sub_xmm
7266 0, // CONTROL_REG:sub_ymm
7267 },
7268 { // FR64
7269 0, // FR64:sub_8bit
7270 0, // FR64:sub_8bit_hi
7271 0, // FR64:sub_8bit_hi_phony
7272 0, // FR64:sub_16bit
7273 0, // FR64:sub_16bit_hi
7274 0, // FR64:sub_32bit
7275 0, // FR64:sub_mask_0
7276 0, // FR64:sub_mask_1
7277 0, // FR64:sub_xmm
7278 0, // FR64:sub_ymm
7279 },
7280 { // GR64_with_sub_16bit_in_GR16_NOREX2
7281 3, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_8bit -> GR8_NOREX2
7282 5, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi -> GR8_ABCD_H
7283 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi_phony
7284 9, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_16bit -> GR16_NOREX2
7285 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_16bit_hi
7286 41, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_32bit -> GR32_NOREX2
7287 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_mask_0
7288 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_mask_1
7289 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_xmm
7290 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_ymm
7291 },
7292 { // GR64_NOREX2_NOSP
7293 3, // GR64_NOREX2_NOSP:sub_8bit -> GR8_NOREX2
7294 5, // GR64_NOREX2_NOSP:sub_8bit_hi -> GR8_ABCD_H
7295 0, // GR64_NOREX2_NOSP:sub_8bit_hi_phony
7296 9, // GR64_NOREX2_NOSP:sub_16bit -> GR16_NOREX2
7297 0, // GR64_NOREX2_NOSP:sub_16bit_hi
7298 42, // GR64_NOREX2_NOSP:sub_32bit -> GR32_NOREX2_NOSP
7299 0, // GR64_NOREX2_NOSP:sub_mask_0
7300 0, // GR64_NOREX2_NOSP:sub_mask_1
7301 0, // GR64_NOREX2_NOSP:sub_xmm
7302 0, // GR64_NOREX2_NOSP:sub_ymm
7303 },
7304 { // GR64PLTSafe
7305 3, // GR64PLTSafe:sub_8bit -> GR8_NOREX2
7306 5, // GR64PLTSafe:sub_8bit_hi -> GR8_ABCD_H
7307 0, // GR64PLTSafe:sub_8bit_hi_phony
7308 9, // GR64PLTSafe:sub_16bit -> GR16_NOREX2
7309 0, // GR64PLTSafe:sub_16bit_hi
7310 42, // GR64PLTSafe:sub_32bit -> GR32_NOREX2_NOSP
7311 0, // GR64PLTSafe:sub_mask_0
7312 0, // GR64PLTSafe:sub_mask_1
7313 0, // GR64PLTSafe:sub_xmm
7314 0, // GR64PLTSafe:sub_ymm
7315 },
7316 { // GR64_TC
7317 3, // GR64_TC:sub_8bit -> GR8_NOREX2
7318 5, // GR64_TC:sub_8bit_hi -> GR8_ABCD_H
7319 0, // GR64_TC:sub_8bit_hi_phony
7320 9, // GR64_TC:sub_16bit -> GR16_NOREX2
7321 0, // GR64_TC:sub_16bit_hi
7322 41, // GR64_TC:sub_32bit -> GR32_NOREX2
7323 0, // GR64_TC:sub_mask_0
7324 0, // GR64_TC:sub_mask_1
7325 0, // GR64_TC:sub_xmm
7326 0, // GR64_TC:sub_ymm
7327 },
7328 { // GR64_NOREX
7329 3, // GR64_NOREX:sub_8bit -> GR8_NOREX2
7330 5, // GR64_NOREX:sub_8bit_hi -> GR8_ABCD_H
7331 0, // GR64_NOREX:sub_8bit_hi_phony
7332 10, // GR64_NOREX:sub_16bit -> GR16_NOREX
7333 0, // GR64_NOREX:sub_16bit_hi
7334 44, // GR64_NOREX:sub_32bit -> GR32_NOREX
7335 0, // GR64_NOREX:sub_mask_0
7336 0, // GR64_NOREX:sub_mask_1
7337 0, // GR64_NOREX:sub_xmm
7338 0, // GR64_NOREX:sub_ymm
7339 },
7340 { // GR64_TCW64
7341 3, // GR64_TCW64:sub_8bit -> GR8_NOREX2
7342 5, // GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
7343 0, // GR64_TCW64:sub_8bit_hi_phony
7344 9, // GR64_TCW64:sub_16bit -> GR16_NOREX2
7345 0, // GR64_TCW64:sub_16bit_hi
7346 41, // GR64_TCW64:sub_32bit -> GR32_NOREX2
7347 0, // GR64_TCW64:sub_mask_0
7348 0, // GR64_TCW64:sub_mask_1
7349 0, // GR64_TCW64:sub_xmm
7350 0, // GR64_TCW64:sub_ymm
7351 },
7352 { // GR64_TC_with_sub_8bit
7353 3, // GR64_TC_with_sub_8bit:sub_8bit -> GR8_NOREX2
7354 5, // GR64_TC_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
7355 0, // GR64_TC_with_sub_8bit:sub_8bit_hi_phony
7356 9, // GR64_TC_with_sub_8bit:sub_16bit -> GR16_NOREX2
7357 0, // GR64_TC_with_sub_8bit:sub_16bit_hi
7358 41, // GR64_TC_with_sub_8bit:sub_32bit -> GR32_NOREX2
7359 0, // GR64_TC_with_sub_8bit:sub_mask_0
7360 0, // GR64_TC_with_sub_8bit:sub_mask_1
7361 0, // GR64_TC_with_sub_8bit:sub_xmm
7362 0, // GR64_TC_with_sub_8bit:sub_ymm
7363 },
7364 { // GR64_NOREX2_NOSP_and_GR64_TC
7365 3, // GR64_NOREX2_NOSP_and_GR64_TC:sub_8bit -> GR8_NOREX2
7366 5, // GR64_NOREX2_NOSP_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
7367 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_8bit_hi_phony
7368 9, // GR64_NOREX2_NOSP_and_GR64_TC:sub_16bit -> GR16_NOREX2
7369 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_16bit_hi
7370 42, // GR64_NOREX2_NOSP_and_GR64_TC:sub_32bit -> GR32_NOREX2_NOSP
7371 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_mask_0
7372 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_mask_1
7373 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_xmm
7374 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_ymm
7375 },
7376 { // GR64_TCW64_with_sub_8bit
7377 3, // GR64_TCW64_with_sub_8bit:sub_8bit -> GR8_NOREX2
7378 5, // GR64_TCW64_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
7379 0, // GR64_TCW64_with_sub_8bit:sub_8bit_hi_phony
7380 9, // GR64_TCW64_with_sub_8bit:sub_16bit -> GR16_NOREX2
7381 0, // GR64_TCW64_with_sub_8bit:sub_16bit_hi
7382 41, // GR64_TCW64_with_sub_8bit:sub_32bit -> GR32_NOREX2
7383 0, // GR64_TCW64_with_sub_8bit:sub_mask_0
7384 0, // GR64_TCW64_with_sub_8bit:sub_mask_1
7385 0, // GR64_TCW64_with_sub_8bit:sub_xmm
7386 0, // GR64_TCW64_with_sub_8bit:sub_ymm
7387 },
7388 { // GR64_TC_and_GR64_TCW64
7389 3, // GR64_TC_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
7390 5, // GR64_TC_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
7391 0, // GR64_TC_and_GR64_TCW64:sub_8bit_hi_phony
7392 9, // GR64_TC_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
7393 0, // GR64_TC_and_GR64_TCW64:sub_16bit_hi
7394 41, // GR64_TC_and_GR64_TCW64:sub_32bit -> GR32_NOREX2
7395 0, // GR64_TC_and_GR64_TCW64:sub_mask_0
7396 0, // GR64_TC_and_GR64_TCW64:sub_mask_1
7397 0, // GR64_TC_and_GR64_TCW64:sub_xmm
7398 0, // GR64_TC_and_GR64_TCW64:sub_ymm
7399 },
7400 { // GR64_with_sub_16bit_in_GR16_NOREX
7401 3, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8_NOREX2
7402 5, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
7403 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
7404 10, // GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
7405 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
7406 44, // GR64_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_NOREX
7407 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_0
7408 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_1
7409 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_xmm
7410 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_ymm
7411 },
7412 { // VK64
7413 0, // VK64:sub_8bit
7414 0, // VK64:sub_8bit_hi
7415 0, // VK64:sub_8bit_hi_phony
7416 0, // VK64:sub_16bit
7417 0, // VK64:sub_16bit_hi
7418 0, // VK64:sub_32bit
7419 0, // VK64:sub_mask_0
7420 0, // VK64:sub_mask_1
7421 0, // VK64:sub_xmm
7422 0, // VK64:sub_ymm
7423 },
7424 { // VR64
7425 0, // VR64:sub_8bit
7426 0, // VR64:sub_8bit_hi
7427 0, // VR64:sub_8bit_hi_phony
7428 0, // VR64:sub_16bit
7429 0, // VR64:sub_16bit_hi
7430 0, // VR64:sub_32bit
7431 0, // VR64:sub_mask_0
7432 0, // VR64:sub_mask_1
7433 0, // VR64:sub_xmm
7434 0, // VR64:sub_ymm
7435 },
7436 { // GR64PLTSafe_and_GR64_TC
7437 3, // GR64PLTSafe_and_GR64_TC:sub_8bit -> GR8_NOREX2
7438 5, // GR64PLTSafe_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
7439 0, // GR64PLTSafe_and_GR64_TC:sub_8bit_hi_phony
7440 9, // GR64PLTSafe_and_GR64_TC:sub_16bit -> GR16_NOREX2
7441 0, // GR64PLTSafe_and_GR64_TC:sub_16bit_hi
7442 42, // GR64PLTSafe_and_GR64_TC:sub_32bit -> GR32_NOREX2_NOSP
7443 0, // GR64PLTSafe_and_GR64_TC:sub_mask_0
7444 0, // GR64PLTSafe_and_GR64_TC:sub_mask_1
7445 0, // GR64PLTSafe_and_GR64_TC:sub_xmm
7446 0, // GR64PLTSafe_and_GR64_TC:sub_ymm
7447 },
7448 { // GR64_NOREX2_NOSP_and_GR64_TCW64
7449 3, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
7450 5, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
7451 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi_phony
7452 9, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
7453 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit_hi
7454 42, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_32bit -> GR32_NOREX2_NOSP
7455 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_0
7456 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_1
7457 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_xmm
7458 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_ymm
7459 },
7460 { // GR64_NOREX_NOSP
7461 3, // GR64_NOREX_NOSP:sub_8bit -> GR8_NOREX2
7462 5, // GR64_NOREX_NOSP:sub_8bit_hi -> GR8_ABCD_H
7463 0, // GR64_NOREX_NOSP:sub_8bit_hi_phony
7464 10, // GR64_NOREX_NOSP:sub_16bit -> GR16_NOREX
7465 0, // GR64_NOREX_NOSP:sub_16bit_hi
7466 46, // GR64_NOREX_NOSP:sub_32bit -> GR32_NOREX_NOSP
7467 0, // GR64_NOREX_NOSP:sub_mask_0
7468 0, // GR64_NOREX_NOSP:sub_mask_1
7469 0, // GR64_NOREX_NOSP:sub_xmm
7470 0, // GR64_NOREX_NOSP:sub_ymm
7471 },
7472 { // GR64_NOREX_and_GR64_TC
7473 3, // GR64_NOREX_and_GR64_TC:sub_8bit -> GR8_NOREX2
7474 5, // GR64_NOREX_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
7475 0, // GR64_NOREX_and_GR64_TC:sub_8bit_hi_phony
7476 10, // GR64_NOREX_and_GR64_TC:sub_16bit -> GR16_NOREX
7477 0, // GR64_NOREX_and_GR64_TC:sub_16bit_hi
7478 44, // GR64_NOREX_and_GR64_TC:sub_32bit -> GR32_NOREX
7479 0, // GR64_NOREX_and_GR64_TC:sub_mask_0
7480 0, // GR64_NOREX_and_GR64_TC:sub_mask_1
7481 0, // GR64_NOREX_and_GR64_TC:sub_xmm
7482 0, // GR64_NOREX_and_GR64_TC:sub_ymm
7483 },
7484 { // GR64_TCW64_and_GR64_TC_with_sub_8bit
7485 3, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit -> GR8_NOREX2
7486 5, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
7487 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit_hi_phony
7488 9, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_16bit -> GR16_NOREX2
7489 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_16bit_hi
7490 41, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_32bit -> GR32_NOREX2
7491 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_mask_0
7492 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_mask_1
7493 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_xmm
7494 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_ymm
7495 },
7496 { // VK64WM
7497 0, // VK64WM:sub_8bit
7498 0, // VK64WM:sub_8bit_hi
7499 0, // VK64WM:sub_8bit_hi_phony
7500 0, // VK64WM:sub_16bit
7501 0, // VK64WM:sub_16bit_hi
7502 0, // VK64WM:sub_32bit
7503 0, // VK64WM:sub_mask_0
7504 0, // VK64WM:sub_mask_1
7505 0, // VK64WM:sub_xmm
7506 0, // VK64WM:sub_ymm
7507 },
7508 { // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
7509 3, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
7510 5, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
7511 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi_phony
7512 9, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
7513 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit_hi
7514 42, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_32bit -> GR32_NOREX2_NOSP
7515 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_0
7516 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_1
7517 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_xmm
7518 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_ymm
7519 },
7520 { // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
7521 3, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8_NOREX2
7522 5, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
7523 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
7524 10, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
7525 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
7526 44, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_NOREX
7527 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_0
7528 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_1
7529 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_xmm
7530 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_ymm
7531 },
7532 { // GR64PLTSafe_and_GR64_TCW64
7533 3, // GR64PLTSafe_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
7534 5, // GR64PLTSafe_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
7535 0, // GR64PLTSafe_and_GR64_TCW64:sub_8bit_hi_phony
7536 9, // GR64PLTSafe_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
7537 0, // GR64PLTSafe_and_GR64_TCW64:sub_16bit_hi
7538 42, // GR64PLTSafe_and_GR64_TCW64:sub_32bit -> GR32_NOREX2_NOSP
7539 0, // GR64PLTSafe_and_GR64_TCW64:sub_mask_0
7540 0, // GR64PLTSafe_and_GR64_TCW64:sub_mask_1
7541 0, // GR64PLTSafe_and_GR64_TCW64:sub_xmm
7542 0, // GR64PLTSafe_and_GR64_TCW64:sub_ymm
7543 },
7544 { // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
7545 3, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit -> GR8_NOREX2
7546 5, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
7547 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit_hi_phony
7548 10, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_16bit -> GR16_NOREX
7549 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_16bit_hi
7550 46, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_32bit -> GR32_NOREX_NOSP
7551 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_mask_0
7552 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_mask_1
7553 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_xmm
7554 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_ymm
7555 },
7556 { // GR64_NOREX_and_GR64_TCW64
7557 3, // GR64_NOREX_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
7558 5, // GR64_NOREX_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
7559 0, // GR64_NOREX_and_GR64_TCW64:sub_8bit_hi_phony
7560 10, // GR64_NOREX_and_GR64_TCW64:sub_16bit -> GR16_NOREX
7561 0, // GR64_NOREX_and_GR64_TCW64:sub_16bit_hi
7562 50, // GR64_NOREX_and_GR64_TCW64:sub_32bit -> GR32_TC
7563 0, // GR64_NOREX_and_GR64_TCW64:sub_mask_0
7564 0, // GR64_NOREX_and_GR64_TCW64:sub_mask_1
7565 0, // GR64_NOREX_and_GR64_TCW64:sub_xmm
7566 0, // GR64_NOREX_and_GR64_TCW64:sub_ymm
7567 },
7568 { // GR64_ABCD
7569 6, // GR64_ABCD:sub_8bit -> GR8_ABCD_L
7570 5, // GR64_ABCD:sub_8bit_hi -> GR8_ABCD_H
7571 0, // GR64_ABCD:sub_8bit_hi_phony
7572 22, // GR64_ABCD:sub_16bit -> GR16_ABCD
7573 0, // GR64_ABCD:sub_16bit_hi
7574 49, // GR64_ABCD:sub_32bit -> GR32_ABCD
7575 0, // GR64_ABCD:sub_mask_0
7576 0, // GR64_ABCD:sub_mask_1
7577 0, // GR64_ABCD:sub_xmm
7578 0, // GR64_ABCD:sub_ymm
7579 },
7580 { // GR64_with_sub_32bit_in_GR32_TC
7581 3, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit -> GR8_NOREX2
7582 5, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
7583 0, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit_hi_phony
7584 10, // GR64_with_sub_32bit_in_GR32_TC:sub_16bit -> GR16_NOREX
7585 0, // GR64_with_sub_32bit_in_GR32_TC:sub_16bit_hi
7586 50, // GR64_with_sub_32bit_in_GR32_TC:sub_32bit -> GR32_TC
7587 0, // GR64_with_sub_32bit_in_GR32_TC:sub_mask_0
7588 0, // GR64_with_sub_32bit_in_GR32_TC:sub_mask_1
7589 0, // GR64_with_sub_32bit_in_GR32_TC:sub_xmm
7590 0, // GR64_with_sub_32bit_in_GR32_TC:sub_ymm
7591 },
7592 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
7593 6, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit -> GR8_ABCD_L
7594 5, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
7595 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit_hi_phony
7596 22, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_16bit -> GR16_ABCD
7597 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_16bit_hi
7598 51, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_32bit -> GR32_ABCD_and_GR32_TC
7599 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_mask_0
7600 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_mask_1
7601 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_xmm
7602 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_ymm
7603 },
7604 { // GR64_AD
7605 6, // GR64_AD:sub_8bit -> GR8_ABCD_L
7606 5, // GR64_AD:sub_8bit_hi -> GR8_ABCD_H
7607 0, // GR64_AD:sub_8bit_hi_phony
7608 22, // GR64_AD:sub_16bit -> GR16_ABCD
7609 0, // GR64_AD:sub_16bit_hi
7610 52, // GR64_AD:sub_32bit -> GR32_AD
7611 0, // GR64_AD:sub_mask_0
7612 0, // GR64_AD:sub_mask_1
7613 0, // GR64_AD:sub_xmm
7614 0, // GR64_AD:sub_ymm
7615 },
7616 { // GR64_ArgRef
7617 3, // GR64_ArgRef:sub_8bit -> GR8_NOREX2
7618 0, // GR64_ArgRef:sub_8bit_hi
7619 0, // GR64_ArgRef:sub_8bit_hi_phony
7620 9, // GR64_ArgRef:sub_16bit -> GR16_NOREX2
7621 0, // GR64_ArgRef:sub_16bit_hi
7622 42, // GR64_ArgRef:sub_32bit -> GR32_NOREX2_NOSP
7623 0, // GR64_ArgRef:sub_mask_0
7624 0, // GR64_ArgRef:sub_mask_1
7625 0, // GR64_ArgRef:sub_xmm
7626 0, // GR64_ArgRef:sub_ymm
7627 },
7628 { // GR64_and_LOW32_ADDR_ACCESS_RBP
7629 3, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit -> GR8_NOREX2
7630 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit_hi
7631 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit_hi_phony
7632 10, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_16bit -> GR16_NOREX
7633 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_16bit_hi
7634 66, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
7635 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_mask_0
7636 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_mask_1
7637 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_xmm
7638 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_ymm
7639 },
7640 { // GR64_with_sub_32bit_in_GR32_ArgRef
7641 6, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_8bit -> GR8_ABCD_L
7642 5, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
7643 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_8bit_hi_phony
7644 22, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_16bit -> GR16_ABCD
7645 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_16bit_hi
7646 53, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_32bit -> GR32_ArgRef
7647 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_mask_0
7648 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_mask_1
7649 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_xmm
7650 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_ymm
7651 },
7652 { // GR64_with_sub_32bit_in_GR32_BPSP
7653 3, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit -> GR8_NOREX2
7654 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit_hi
7655 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit_hi_phony
7656 10, // GR64_with_sub_32bit_in_GR32_BPSP:sub_16bit -> GR16_NOREX
7657 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_16bit_hi
7658 54, // GR64_with_sub_32bit_in_GR32_BPSP:sub_32bit -> GR32_BPSP
7659 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_mask_0
7660 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_mask_1
7661 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_xmm
7662 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_ymm
7663 },
7664 { // GR64_with_sub_32bit_in_GR32_BSI
7665 3, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit -> GR8_NOREX2
7666 5, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
7667 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit_hi_phony
7668 10, // GR64_with_sub_32bit_in_GR32_BSI:sub_16bit -> GR16_NOREX
7669 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_16bit_hi
7670 55, // GR64_with_sub_32bit_in_GR32_BSI:sub_32bit -> GR32_BSI
7671 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_mask_0
7672 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_mask_1
7673 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_xmm
7674 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_ymm
7675 },
7676 { // GR64_with_sub_32bit_in_GR32_CB
7677 6, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit -> GR8_ABCD_L
7678 5, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
7679 0, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit_hi_phony
7680 22, // GR64_with_sub_32bit_in_GR32_CB:sub_16bit -> GR16_ABCD
7681 0, // GR64_with_sub_32bit_in_GR32_CB:sub_16bit_hi
7682 56, // GR64_with_sub_32bit_in_GR32_CB:sub_32bit -> GR32_CB
7683 0, // GR64_with_sub_32bit_in_GR32_CB:sub_mask_0
7684 0, // GR64_with_sub_32bit_in_GR32_CB:sub_mask_1
7685 0, // GR64_with_sub_32bit_in_GR32_CB:sub_xmm
7686 0, // GR64_with_sub_32bit_in_GR32_CB:sub_ymm
7687 },
7688 { // GR64_with_sub_32bit_in_GR32_DIBP
7689 3, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit -> GR8_NOREX2
7690 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit_hi
7691 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit_hi_phony
7692 10, // GR64_with_sub_32bit_in_GR32_DIBP:sub_16bit -> GR16_NOREX
7693 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_16bit_hi
7694 58, // GR64_with_sub_32bit_in_GR32_DIBP:sub_32bit -> GR32_DIBP
7695 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_mask_0
7696 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_mask_1
7697 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_xmm
7698 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_ymm
7699 },
7700 { // GR64_with_sub_32bit_in_GR32_SIDI
7701 3, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit -> GR8_NOREX2
7702 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit_hi
7703 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit_hi_phony
7704 10, // GR64_with_sub_32bit_in_GR32_SIDI:sub_16bit -> GR16_NOREX
7705 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_16bit_hi
7706 59, // GR64_with_sub_32bit_in_GR32_SIDI:sub_32bit -> GR32_SIDI
7707 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_mask_0
7708 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_mask_1
7709 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_xmm
7710 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_ymm
7711 },
7712 { // GR64_A
7713 6, // GR64_A:sub_8bit -> GR8_ABCD_L
7714 5, // GR64_A:sub_8bit_hi -> GR8_ABCD_H
7715 0, // GR64_A:sub_8bit_hi_phony
7716 22, // GR64_A:sub_16bit -> GR16_ABCD
7717 0, // GR64_A:sub_16bit_hi
7718 52, // GR64_A:sub_32bit -> GR32_AD
7719 0, // GR64_A:sub_mask_0
7720 0, // GR64_A:sub_mask_1
7721 0, // GR64_A:sub_xmm
7722 0, // GR64_A:sub_ymm
7723 },
7724 { // GR64_ArgRef_and_GR64_TC
7725 3, // GR64_ArgRef_and_GR64_TC:sub_8bit -> GR8_NOREX2
7726 0, // GR64_ArgRef_and_GR64_TC:sub_8bit_hi
7727 0, // GR64_ArgRef_and_GR64_TC:sub_8bit_hi_phony
7728 9, // GR64_ArgRef_and_GR64_TC:sub_16bit -> GR16_NOREX2
7729 0, // GR64_ArgRef_and_GR64_TC:sub_16bit_hi
7730 42, // GR64_ArgRef_and_GR64_TC:sub_32bit -> GR32_NOREX2_NOSP
7731 0, // GR64_ArgRef_and_GR64_TC:sub_mask_0
7732 0, // GR64_ArgRef_and_GR64_TC:sub_mask_1
7733 0, // GR64_ArgRef_and_GR64_TC:sub_xmm
7734 0, // GR64_ArgRef_and_GR64_TC:sub_ymm
7735 },
7736 { // GR64_and_LOW32_ADDR_ACCESS
7737 0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit
7738 0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit_hi
7739 0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit_hi_phony
7740 0, // GR64_and_LOW32_ADDR_ACCESS:sub_16bit
7741 0, // GR64_and_LOW32_ADDR_ACCESS:sub_16bit_hi
7742 0, // GR64_and_LOW32_ADDR_ACCESS:sub_32bit
7743 0, // GR64_and_LOW32_ADDR_ACCESS:sub_mask_0
7744 0, // GR64_and_LOW32_ADDR_ACCESS:sub_mask_1
7745 0, // GR64_and_LOW32_ADDR_ACCESS:sub_xmm
7746 0, // GR64_and_LOW32_ADDR_ACCESS:sub_ymm
7747 },
7748 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
7749 6, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit -> GR8_ABCD_L
7750 5, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
7751 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit_hi_phony
7752 22, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_16bit -> GR16_ABCD
7753 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_16bit_hi
7754 63, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_32bit -> GR32_ABCD_and_GR32_BSI
7755 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_mask_0
7756 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_mask_1
7757 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_xmm
7758 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_ymm
7759 },
7760 { // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
7761 6, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_8bit -> GR8_ABCD_L
7762 5, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
7763 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_8bit_hi_phony
7764 22, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_16bit -> GR16_ABCD
7765 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_16bit_hi
7766 64, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_32bit -> GR32_AD_and_GR32_ArgRef
7767 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_mask_0
7768 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_mask_1
7769 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_xmm
7770 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_ymm
7771 },
7772 { // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
7773 6, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_8bit -> GR8_ABCD_L
7774 5, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
7775 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_8bit_hi_phony
7776 22, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_16bit -> GR16_ABCD
7777 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_16bit_hi
7778 65, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_32bit -> GR32_ArgRef_and_GR32_CB
7779 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_mask_0
7780 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_mask_1
7781 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_xmm
7782 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_ymm
7783 },
7784 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
7785 3, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit -> GR8_NOREX2
7786 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit_hi
7787 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit_hi_phony
7788 10, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_16bit -> GR16_NOREX
7789 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_16bit_hi
7790 66, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
7791 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_mask_0
7792 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_mask_1
7793 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_xmm
7794 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_ymm
7795 },
7796 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
7797 3, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit -> GR8_NOREX2
7798 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit_hi
7799 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit_hi_phony
7800 10, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_16bit -> GR16_NOREX
7801 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_16bit_hi
7802 67, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_32bit -> GR32_BPSP_and_GR32_TC
7803 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_mask_0
7804 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_mask_1
7805 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_xmm
7806 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_ymm
7807 },
7808 { // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
7809 3, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
7810 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit_hi
7811 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit_hi_phony
7812 10, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_16bit -> GR16_NOREX
7813 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_16bit_hi
7814 68, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_32bit -> GR32_BSI_and_GR32_SIDI
7815 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_mask_0
7816 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_mask_1
7817 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_xmm
7818 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_ymm
7819 },
7820 { // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
7821 3, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
7822 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit_hi
7823 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit_hi_phony
7824 10, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_16bit -> GR16_NOREX
7825 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_16bit_hi
7826 69, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_32bit -> GR32_DIBP_and_GR32_SIDI
7827 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_mask_0
7828 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_mask_1
7829 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_xmm
7830 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_ymm
7831 },
7832 { // RST
7833 0, // RST:sub_8bit
7834 0, // RST:sub_8bit_hi
7835 0, // RST:sub_8bit_hi_phony
7836 0, // RST:sub_16bit
7837 0, // RST:sub_16bit_hi
7838 0, // RST:sub_32bit
7839 0, // RST:sub_mask_0
7840 0, // RST:sub_mask_1
7841 0, // RST:sub_xmm
7842 0, // RST:sub_ymm
7843 },
7844 { // RFP80
7845 0, // RFP80:sub_8bit
7846 0, // RFP80:sub_8bit_hi
7847 0, // RFP80:sub_8bit_hi_phony
7848 0, // RFP80:sub_16bit
7849 0, // RFP80:sub_16bit_hi
7850 0, // RFP80:sub_32bit
7851 0, // RFP80:sub_mask_0
7852 0, // RFP80:sub_mask_1
7853 0, // RFP80:sub_xmm
7854 0, // RFP80:sub_ymm
7855 },
7856 { // RFP80_7
7857 0, // RFP80_7:sub_8bit
7858 0, // RFP80_7:sub_8bit_hi
7859 0, // RFP80_7:sub_8bit_hi_phony
7860 0, // RFP80_7:sub_16bit
7861 0, // RFP80_7:sub_16bit_hi
7862 0, // RFP80_7:sub_32bit
7863 0, // RFP80_7:sub_mask_0
7864 0, // RFP80_7:sub_mask_1
7865 0, // RFP80_7:sub_xmm
7866 0, // RFP80_7:sub_ymm
7867 },
7868 { // VR128X
7869 0, // VR128X:sub_8bit
7870 0, // VR128X:sub_8bit_hi
7871 0, // VR128X:sub_8bit_hi_phony
7872 0, // VR128X:sub_16bit
7873 0, // VR128X:sub_16bit_hi
7874 0, // VR128X:sub_32bit
7875 0, // VR128X:sub_mask_0
7876 0, // VR128X:sub_mask_1
7877 0, // VR128X:sub_xmm
7878 0, // VR128X:sub_ymm
7879 },
7880 { // VR128
7881 0, // VR128:sub_8bit
7882 0, // VR128:sub_8bit_hi
7883 0, // VR128:sub_8bit_hi_phony
7884 0, // VR128:sub_16bit
7885 0, // VR128:sub_16bit_hi
7886 0, // VR128:sub_32bit
7887 0, // VR128:sub_mask_0
7888 0, // VR128:sub_mask_1
7889 0, // VR128:sub_xmm
7890 0, // VR128:sub_ymm
7891 },
7892 { // VR256X
7893 0, // VR256X:sub_8bit
7894 0, // VR256X:sub_8bit_hi
7895 0, // VR256X:sub_8bit_hi_phony
7896 0, // VR256X:sub_16bit
7897 0, // VR256X:sub_16bit_hi
7898 0, // VR256X:sub_32bit
7899 0, // VR256X:sub_mask_0
7900 0, // VR256X:sub_mask_1
7901 24, // VR256X:sub_xmm -> FR16X
7902 0, // VR256X:sub_ymm
7903 },
7904 { // VR256
7905 0, // VR256:sub_8bit
7906 0, // VR256:sub_8bit_hi
7907 0, // VR256:sub_8bit_hi_phony
7908 0, // VR256:sub_16bit
7909 0, // VR256:sub_16bit_hi
7910 0, // VR256:sub_32bit
7911 0, // VR256:sub_mask_0
7912 0, // VR256:sub_mask_1
7913 25, // VR256:sub_xmm -> FR16
7914 0, // VR256:sub_ymm
7915 },
7916 { // VR512
7917 0, // VR512:sub_8bit
7918 0, // VR512:sub_8bit_hi
7919 0, // VR512:sub_8bit_hi_phony
7920 0, // VR512:sub_16bit
7921 0, // VR512:sub_16bit_hi
7922 0, // VR512:sub_32bit
7923 0, // VR512:sub_mask_0
7924 0, // VR512:sub_mask_1
7925 24, // VR512:sub_xmm -> FR16X
7926 131, // VR512:sub_ymm -> VR256X
7927 },
7928 { // VR512_0_15
7929 0, // VR512_0_15:sub_8bit
7930 0, // VR512_0_15:sub_8bit_hi
7931 0, // VR512_0_15:sub_8bit_hi_phony
7932 0, // VR512_0_15:sub_16bit
7933 0, // VR512_0_15:sub_16bit_hi
7934 0, // VR512_0_15:sub_32bit
7935 0, // VR512_0_15:sub_mask_0
7936 0, // VR512_0_15:sub_mask_1
7937 25, // VR512_0_15:sub_xmm -> FR16
7938 132, // VR512_0_15:sub_ymm -> VR256
7939 },
7940 { // TILE
7941 0, // TILE:sub_8bit
7942 0, // TILE:sub_8bit_hi
7943 0, // TILE:sub_8bit_hi_phony
7944 0, // TILE:sub_16bit
7945 0, // TILE:sub_16bit_hi
7946 0, // TILE:sub_32bit
7947 0, // TILE:sub_mask_0
7948 0, // TILE:sub_mask_1
7949 0, // TILE:sub_xmm
7950 0, // TILE:sub_ymm
7951 },
7952 };
7953 assert(RC && "Missing regclass");
7954 if (!Idx) return RC;
7955 --Idx;
7956 assert(Idx < 10 && "Bad subreg");
7957 unsigned TV = Table[RC->getID()][Idx];
7958 return TV ? getRegClass(i: TV - 1) : nullptr;
7959}
7960
7961/// Get the weight in units of pressure for this register class.
7962const RegClassWeight &X86GenRegisterInfo::
7963getRegClassWeight(const TargetRegisterClass *RC) const {
7964 static const RegClassWeight RCWeightTable[] = {
7965 {.RegWeight: 1, .WeightLimit: 36}, // GR8
7966 {.RegWeight: 0, .WeightLimit: 0}, // GRH8
7967 {.RegWeight: 1, .WeightLimit: 20}, // GR8_NOREX2
7968 {.RegWeight: 1, .WeightLimit: 8}, // GR8_NOREX
7969 {.RegWeight: 1, .WeightLimit: 4}, // GR8_ABCD_H
7970 {.RegWeight: 1, .WeightLimit: 4}, // GR8_ABCD_L
7971 {.RegWeight: 0, .WeightLimit: 0}, // GRH16
7972 {.RegWeight: 2, .WeightLimit: 64}, // GR16
7973 {.RegWeight: 2, .WeightLimit: 32}, // GR16_NOREX2
7974 {.RegWeight: 2, .WeightLimit: 16}, // GR16_NOREX
7975 {.RegWeight: 1, .WeightLimit: 8}, // VK1
7976 {.RegWeight: 1, .WeightLimit: 8}, // VK16
7977 {.RegWeight: 1, .WeightLimit: 8}, // VK2
7978 {.RegWeight: 1, .WeightLimit: 8}, // VK4
7979 {.RegWeight: 1, .WeightLimit: 8}, // VK8
7980 {.RegWeight: 1, .WeightLimit: 7}, // VK16WM
7981 {.RegWeight: 1, .WeightLimit: 7}, // VK1WM
7982 {.RegWeight: 1, .WeightLimit: 7}, // VK2WM
7983 {.RegWeight: 1, .WeightLimit: 7}, // VK4WM
7984 {.RegWeight: 1, .WeightLimit: 7}, // VK8WM
7985 {.RegWeight: 1, .WeightLimit: 6}, // SEGMENT_REG
7986 {.RegWeight: 2, .WeightLimit: 8}, // GR16_ABCD
7987 {.RegWeight: 0, .WeightLimit: 0}, // FPCCR
7988 {.RegWeight: 1, .WeightLimit: 32}, // FR16X
7989 {.RegWeight: 1, .WeightLimit: 16}, // FR16
7990 {.RegWeight: 2, .WeightLimit: 8}, // VK16PAIR
7991 {.RegWeight: 2, .WeightLimit: 8}, // VK1PAIR
7992 {.RegWeight: 2, .WeightLimit: 8}, // VK2PAIR
7993 {.RegWeight: 2, .WeightLimit: 8}, // VK4PAIR
7994 {.RegWeight: 2, .WeightLimit: 8}, // VK8PAIR
7995 {.RegWeight: 2, .WeightLimit: 6}, // VK1PAIR_with_sub_mask_0_in_VK1WM
7996 {.RegWeight: 2, .WeightLimit: 66}, // LOW32_ADDR_ACCESS_RBP
7997 {.RegWeight: 2, .WeightLimit: 66}, // LOW32_ADDR_ACCESS
7998 {.RegWeight: 2, .WeightLimit: 64}, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
7999 {.RegWeight: 1, .WeightLimit: 32}, // FR32X
8000 {.RegWeight: 2, .WeightLimit: 64}, // GR32
8001 {.RegWeight: 2, .WeightLimit: 62}, // GR32_NOSP
8002 {.RegWeight: 2, .WeightLimit: 32}, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
8003 {.RegWeight: 1, .WeightLimit: 16}, // DEBUG_REG
8004 {.RegWeight: 1, .WeightLimit: 16}, // FR32
8005 {.RegWeight: 2, .WeightLimit: 32}, // GR32_NOREX2
8006 {.RegWeight: 2, .WeightLimit: 30}, // GR32_NOREX2_NOSP
8007 {.RegWeight: 2, .WeightLimit: 16}, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
8008 {.RegWeight: 2, .WeightLimit: 16}, // GR32_NOREX
8009 {.RegWeight: 1, .WeightLimit: 8}, // VK32
8010 {.RegWeight: 2, .WeightLimit: 14}, // GR32_NOREX_NOSP
8011 {.RegWeight: 1, .WeightLimit: 7}, // RFP32
8012 {.RegWeight: 1, .WeightLimit: 7}, // VK32WM
8013 {.RegWeight: 2, .WeightLimit: 8}, // GR32_ABCD
8014 {.RegWeight: 2, .WeightLimit: 8}, // GR32_TC
8015 {.RegWeight: 2, .WeightLimit: 6}, // GR32_ABCD_and_GR32_TC
8016 {.RegWeight: 2, .WeightLimit: 4}, // GR32_AD
8017 {.RegWeight: 2, .WeightLimit: 4}, // GR32_ArgRef
8018 {.RegWeight: 2, .WeightLimit: 4}, // GR32_BPSP
8019 {.RegWeight: 2, .WeightLimit: 4}, // GR32_BSI
8020 {.RegWeight: 2, .WeightLimit: 4}, // GR32_CB
8021 {.RegWeight: 2, .WeightLimit: 4}, // GR32_DC
8022 {.RegWeight: 2, .WeightLimit: 4}, // GR32_DIBP
8023 {.RegWeight: 2, .WeightLimit: 4}, // GR32_SIDI
8024 {.RegWeight: 2, .WeightLimit: 4}, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
8025 {.RegWeight: 0, .WeightLimit: 0}, // CCR
8026 {.RegWeight: 0, .WeightLimit: 0}, // DFCCR
8027 {.RegWeight: 2, .WeightLimit: 2}, // GR32_ABCD_and_GR32_BSI
8028 {.RegWeight: 2, .WeightLimit: 2}, // GR32_AD_and_GR32_ArgRef
8029 {.RegWeight: 2, .WeightLimit: 2}, // GR32_ArgRef_and_GR32_CB
8030 {.RegWeight: 2, .WeightLimit: 2}, // GR32_BPSP_and_GR32_DIBP
8031 {.RegWeight: 2, .WeightLimit: 2}, // GR32_BPSP_and_GR32_TC
8032 {.RegWeight: 2, .WeightLimit: 2}, // GR32_BSI_and_GR32_SIDI
8033 {.RegWeight: 2, .WeightLimit: 2}, // GR32_DIBP_and_GR32_SIDI
8034 {.RegWeight: 2, .WeightLimit: 2}, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
8035 {.RegWeight: 2, .WeightLimit: 2}, // LOW32_ADDR_ACCESS_with_sub_32bit
8036 {.RegWeight: 1, .WeightLimit: 7}, // RFP64
8037 {.RegWeight: 2, .WeightLimit: 66}, // GR64
8038 {.RegWeight: 1, .WeightLimit: 32}, // FR64X
8039 {.RegWeight: 2, .WeightLimit: 64}, // GR64_with_sub_8bit
8040 {.RegWeight: 2, .WeightLimit: 62}, // GR64_NOSP
8041 {.RegWeight: 2, .WeightLimit: 34}, // GR64_NOREX2
8042 {.RegWeight: 1, .WeightLimit: 16}, // CONTROL_REG
8043 {.RegWeight: 1, .WeightLimit: 16}, // FR64
8044 {.RegWeight: 2, .WeightLimit: 32}, // GR64_with_sub_16bit_in_GR16_NOREX2
8045 {.RegWeight: 2, .WeightLimit: 30}, // GR64_NOREX2_NOSP
8046 {.RegWeight: 2, .WeightLimit: 26}, // GR64PLTSafe
8047 {.RegWeight: 2, .WeightLimit: 20}, // GR64_TC
8048 {.RegWeight: 2, .WeightLimit: 18}, // GR64_NOREX
8049 {.RegWeight: 2, .WeightLimit: 18}, // GR64_TCW64
8050 {.RegWeight: 2, .WeightLimit: 18}, // GR64_TC_with_sub_8bit
8051 {.RegWeight: 2, .WeightLimit: 16}, // GR64_NOREX2_NOSP_and_GR64_TC
8052 {.RegWeight: 2, .WeightLimit: 16}, // GR64_TCW64_with_sub_8bit
8053 {.RegWeight: 2, .WeightLimit: 16}, // GR64_TC_and_GR64_TCW64
8054 {.RegWeight: 2, .WeightLimit: 16}, // GR64_with_sub_16bit_in_GR16_NOREX
8055 {.RegWeight: 1, .WeightLimit: 8}, // VK64
8056 {.RegWeight: 1, .WeightLimit: 8}, // VR64
8057 {.RegWeight: 2, .WeightLimit: 14}, // GR64PLTSafe_and_GR64_TC
8058 {.RegWeight: 2, .WeightLimit: 14}, // GR64_NOREX2_NOSP_and_GR64_TCW64
8059 {.RegWeight: 2, .WeightLimit: 14}, // GR64_NOREX_NOSP
8060 {.RegWeight: 2, .WeightLimit: 14}, // GR64_NOREX_and_GR64_TC
8061 {.RegWeight: 2, .WeightLimit: 14}, // GR64_TCW64_and_GR64_TC_with_sub_8bit
8062 {.RegWeight: 1, .WeightLimit: 7}, // VK64WM
8063 {.RegWeight: 2, .WeightLimit: 12}, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
8064 {.RegWeight: 2, .WeightLimit: 12}, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
8065 {.RegWeight: 2, .WeightLimit: 10}, // GR64PLTSafe_and_GR64_TCW64
8066 {.RegWeight: 2, .WeightLimit: 10}, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
8067 {.RegWeight: 2, .WeightLimit: 10}, // GR64_NOREX_and_GR64_TCW64
8068 {.RegWeight: 2, .WeightLimit: 8}, // GR64_ABCD
8069 {.RegWeight: 2, .WeightLimit: 8}, // GR64_with_sub_32bit_in_GR32_TC
8070 {.RegWeight: 2, .WeightLimit: 6}, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
8071 {.RegWeight: 2, .WeightLimit: 4}, // GR64_AD
8072 {.RegWeight: 2, .WeightLimit: 4}, // GR64_ArgRef
8073 {.RegWeight: 2, .WeightLimit: 4}, // GR64_and_LOW32_ADDR_ACCESS_RBP
8074 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_ArgRef
8075 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_BPSP
8076 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_BSI
8077 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_CB
8078 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_DIBP
8079 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_SIDI
8080 {.RegWeight: 2, .WeightLimit: 2}, // GR64_A
8081 {.RegWeight: 2, .WeightLimit: 2}, // GR64_ArgRef_and_GR64_TC
8082 {.RegWeight: 2, .WeightLimit: 2}, // GR64_and_LOW32_ADDR_ACCESS
8083 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
8084 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
8085 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
8086 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
8087 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
8088 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
8089 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
8090 {.RegWeight: 0, .WeightLimit: 0}, // RST
8091 {.RegWeight: 1, .WeightLimit: 7}, // RFP80
8092 {.RegWeight: 0, .WeightLimit: 0}, // RFP80_7
8093 {.RegWeight: 1, .WeightLimit: 32}, // VR128X
8094 {.RegWeight: 1, .WeightLimit: 16}, // VR128
8095 {.RegWeight: 1, .WeightLimit: 32}, // VR256X
8096 {.RegWeight: 1, .WeightLimit: 16}, // VR256
8097 {.RegWeight: 1, .WeightLimit: 32}, // VR512
8098 {.RegWeight: 1, .WeightLimit: 16}, // VR512_0_15
8099 {.RegWeight: 1, .WeightLimit: 8}, // TILE
8100 };
8101 return RCWeightTable[RC->getID()];
8102}
8103
8104/// Get the weight in units of pressure for this register unit.
8105unsigned X86GenRegisterInfo::
8106getRegUnitWeight(MCRegUnit RegUnit) const {
8107 assert(static_cast<unsigned>(RegUnit) < 221 && "invalid register unit");
8108 // All register units have unit weight.
8109 return 1;
8110}
8111
8112
8113// Get the number of dimensions of register pressure.
8114unsigned X86GenRegisterInfo::getNumRegPressureSets() const {
8115 return 36;
8116}
8117
8118// Get the name of this register unit pressure set.
8119const char *X86GenRegisterInfo::
8120getRegPressureSetName(unsigned Idx) const {
8121 static const char *PressureNameTable[] = {
8122 "SEGMENT_REG",
8123 "GR32_BPSP",
8124 "LOW32_ADDR_ACCESS_with_sub_32bit",
8125 "GR32_BSI",
8126 "GR32_SIDI",
8127 "GR32_DIBP_with_GR32_SIDI",
8128 "GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit",
8129 "RFP32",
8130 "GR8_ABCD_H_with_GR32_BSI",
8131 "GR8_ABCD_L_with_GR32_BSI",
8132 "VK1",
8133 "VR64",
8134 "TILE",
8135 "GR8_NOREX",
8136 "GR32_TC",
8137 "GR32_BPSP_with_GR32_TC",
8138 "FR16",
8139 "DEBUG_REG",
8140 "CONTROL_REG",
8141 "GR64_NOREX",
8142 "GR64_TCW64",
8143 "GR32_BPSP_with_GR64_TCW64",
8144 "GR64_TC_with_GR64_TCW64",
8145 "GR64_TC",
8146 "FR16X",
8147 "GR64PLTSafe_with_GR64_TC",
8148 "GR8",
8149 "GR8_with_GR32_DIBP",
8150 "GR8_with_GR32_BSI",
8151 "GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit",
8152 "GR8_with_GR64_NOREX",
8153 "GR8_with_GR64_TCW64",
8154 "GR8_with_GR64_TC",
8155 "GR8_with_GR64PLTSafe",
8156 "GR8_with_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2",
8157 "GR16",
8158 };
8159 return PressureNameTable[Idx];
8160}
8161
8162// Get the register unit pressure limit for this dimension.
8163// This limit must be adjusted dynamically for reserved registers.
8164unsigned X86GenRegisterInfo::
8165getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
8166 static const uint8_t PressureLimitTable[] = {
8167 6, // 0: SEGMENT_REG
8168 6, // 1: GR32_BPSP
8169 6, // 2: LOW32_ADDR_ACCESS_with_sub_32bit
8170 6, // 3: GR32_BSI
8171 6, // 4: GR32_SIDI
8172 6, // 5: GR32_DIBP_with_GR32_SIDI
8173 6, // 6: GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit
8174 7, // 7: RFP32
8175 7, // 8: GR8_ABCD_H_with_GR32_BSI
8176 7, // 9: GR8_ABCD_L_with_GR32_BSI
8177 8, // 10: VK1
8178 8, // 11: VR64
8179 8, // 12: TILE
8180 10, // 13: GR8_NOREX
8181 12, // 14: GR32_TC
8182 12, // 15: GR32_BPSP_with_GR32_TC
8183 16, // 16: FR16
8184 16, // 17: DEBUG_REG
8185 16, // 18: CONTROL_REG
8186 18, // 19: GR64_NOREX
8187 20, // 20: GR64_TCW64
8188 20, // 21: GR32_BPSP_with_GR64_TCW64
8189 22, // 22: GR64_TC_with_GR64_TCW64
8190 26, // 23: GR64_TC
8191 32, // 24: FR16X
8192 34, // 25: GR64PLTSafe_with_GR64_TC
8193 38, // 26: GR8
8194 38, // 27: GR8_with_GR32_DIBP
8195 38, // 28: GR8_with_GR32_BSI
8196 39, // 29: GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit
8197 42, // 30: GR8_with_GR64_NOREX
8198 43, // 31: GR8_with_GR64_TCW64
8199 44, // 32: GR8_with_GR64_TC
8200 45, // 33: GR8_with_GR64PLTSafe
8201 48, // 34: GR8_with_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
8202 66, // 35: GR16
8203 };
8204 return PressureLimitTable[Idx];
8205}
8206
8207/// Table of pressure sets per register class or unit.
8208static const int RCSetsTable[] = {
8209 /* 0 */ 0, -1,
8210 /* 2 */ 7, -1,
8211 /* 4 */ 10, -1,
8212 /* 6 */ 11, -1,
8213 /* 8 */ 12, -1,
8214 /* 10 */ 17, -1,
8215 /* 12 */ 18, -1,
8216 /* 14 */ 16, 24, -1,
8217 /* 17 */ 25, 35, -1,
8218 /* 20 */ 19, 23, 25, 30, 35, -1,
8219 /* 26 */ 2, 6, 15, 19, 21, 23, 25, 29, 30, 35, -1,
8220 /* 37 */ 20, 21, 22, 23, 25, 31, 35, -1,
8221 /* 45 */ 22, 23, 25, 32, 35, -1,
8222 /* 51 */ 19, 22, 23, 25, 30, 32, 35, -1,
8223 /* 59 */ 20, 21, 22, 23, 25, 31, 32, 35, -1,
8224 /* 68 */ 14, 15, 19, 20, 21, 22, 23, 25, 30, 31, 32, 35, -1,
8225 /* 81 */ 2, 6, 14, 15, 19, 20, 21, 22, 23, 25, 29, 30, 31, 32, 35, -1,
8226 /* 97 */ 25, 34, 35, -1,
8227 /* 101 */ 19, 23, 25, 30, 34, 35, -1,
8228 /* 108 */ 1, 2, 15, 19, 21, 23, 25, 26, 30, 34, 35, -1,
8229 /* 120 */ 20, 21, 22, 23, 25, 31, 34, 35, -1,
8230 /* 129 */ 22, 23, 25, 32, 34, 35, -1,
8231 /* 136 */ 19, 22, 23, 25, 30, 32, 34, 35, -1,
8232 /* 145 */ 20, 21, 22, 23, 25, 31, 32, 34, 35, -1,
8233 /* 155 */ 1, 2, 14, 15, 19, 20, 21, 22, 23, 25, 26, 30, 31, 32, 34, 35, -1,
8234 /* 172 */ 25, 33, 34, 35, -1,
8235 /* 177 */ 19, 23, 25, 30, 33, 34, 35, -1,
8236 /* 185 */ 1, 5, 6, 19, 23, 25, 27, 30, 33, 34, 35, -1,
8237 /* 197 */ 1, 2, 5, 6, 15, 19, 21, 23, 25, 26, 27, 29, 30, 33, 34, 35, -1,
8238 /* 214 */ 22, 23, 25, 32, 33, 34, 35, -1,
8239 /* 222 */ 3, 4, 8, 9, 13, 19, 23, 25, 28, 30, 32, 33, 34, 35, -1,
8240 /* 237 */ 4, 5, 19, 22, 23, 25, 28, 30, 32, 33, 34, 35, -1,
8241 /* 250 */ 3, 4, 5, 8, 9, 13, 19, 22, 23, 25, 28, 30, 32, 33, 34, 35, -1,
8242 /* 267 */ 1, 4, 5, 6, 19, 22, 23, 25, 27, 28, 30, 32, 33, 34, 35, -1,
8243 /* 283 */ 20, 21, 22, 23, 25, 31, 32, 33, 34, 35, -1,
8244 /* 294 */ 3, 13, 14, 19, 20, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8245 /* 312 */ 8, 13, 14, 19, 20, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8246 /* 330 */ 3, 4, 8, 9, 13, 14, 19, 20, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8247 /* 351 */ 1, 2, 5, 6, 15, 19, 21, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8248 /* 371 */ 1, 4, 5, 6, 19, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8249 /* 390 */ 3, 4, 5, 8, 9, 13, 19, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8250 /* 411 */ 1, 2, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8251 /* 432 */ 3, 13, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8252 /* 453 */ 3, 8, 13, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8253 /* 475 */ 3, 9, 13, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8254};
8255
8256/// Get the dimensions of register pressure impacted by this register class.
8257/// Returns a -1 terminated array of pressure set IDs
8258const int *X86GenRegisterInfo::
8259getRegClassPressureSets(const TargetRegisterClass *RC) const {
8260 static const uint16_t RCSetStartTable[] = {
8261 301,1,300,295,312,333,1,18,97,101,4,4,4,4,4,4,4,4,4,4,0,295,1,15,14,4,4,4,4,4,4,18,18,18,15,18,18,97,10,14,97,97,101,101,4,177,2,4,295,157,433,433,433,108,222,294,433,185,237,26,1,1,330,433,432,197,155,250,267,197,81,2,18,15,18,18,17,12,14,97,97,172,45,20,37,129,129,120,59,101,4,6,214,120,177,51,145,4,145,136,283,239,68,295,157,433,433,120,26,433,108,222,294,185,237,433,145,81,330,433,432,197,155,250,267,1,2,1,15,14,15,14,15,14,8,};
8262 return &RCSetsTable[RCSetStartTable[RC->getID()]];
8263}
8264
8265/// Get the dimensions of register pressure impacted by this register unit.
8266/// Returns a -1 terminated array of pressure set IDs
8267const int *X86GenRegisterInfo::
8268getRegUnitPressureSets(MCRegUnit RegUnit) const {
8269 assert(static_cast<unsigned>(RegUnit) < 221 && "invalid register unit");
8270 static const uint16_t RUSetStartTable[] = {
8271 454,476,330,330,351,1,453,475,0,1,454,371,1,476,0,1,1,1,1,1,1,1,81,1,1,0,390,1,1,411,1,1,1,1,0,1,0,1,1,1,1,0,1,1,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,2,2,2,2,2,2,2,1,6,6,6,6,6,6,6,6,416,1,1,416,1,1,416,1,1,416,1,1,300,1,1,300,1,1,300,1,1,300,1,1,1,1,1,1,1,1,1,1,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,4,4,4,4,4,4,4,4,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,1,8,8,8,8,8,8,8,8,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,};
8272 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
8273}
8274
8275extern const MCRegisterDesc X86RegDesc[];
8276extern const int16_t X86RegDiffLists[];
8277extern const LaneBitmask X86LaneMaskLists[];
8278extern const char X86RegStrings[];
8279extern const char X86RegClassStrings[];
8280extern const MCPhysReg X86RegUnitRoots[][2];
8281extern const uint16_t X86SubRegIdxLists[];
8282extern const uint16_t X86RegEncodingTable[];
8283// X86 Dwarf<->LLVM register mappings.
8284extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[];
8285extern const unsigned X86DwarfFlavour0Dwarf2LSize;
8286
8287extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[];
8288extern const unsigned X86DwarfFlavour1Dwarf2LSize;
8289
8290extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[];
8291extern const unsigned X86DwarfFlavour2Dwarf2LSize;
8292
8293extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[];
8294extern const unsigned X86EHFlavour0Dwarf2LSize;
8295
8296extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[];
8297extern const unsigned X86EHFlavour1Dwarf2LSize;
8298
8299extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[];
8300extern const unsigned X86EHFlavour2Dwarf2LSize;
8301
8302extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[];
8303extern const unsigned X86DwarfFlavour0L2DwarfSize;
8304
8305extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[];
8306extern const unsigned X86DwarfFlavour1L2DwarfSize;
8307
8308extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[];
8309extern const unsigned X86DwarfFlavour2L2DwarfSize;
8310
8311extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[];
8312extern const unsigned X86EHFlavour0L2DwarfSize;
8313
8314extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[];
8315extern const unsigned X86EHFlavour1L2DwarfSize;
8316
8317extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[];
8318extern const unsigned X86EHFlavour2L2DwarfSize;
8319
8320X86GenRegisterInfo::
8321X86GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
8322 unsigned PC, unsigned HwMode)
8323 : TargetRegisterInfo(&X86RegInfoDesc, RegisterClasses, RegisterClasses+135,
8324 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
8325 LaneBitmask(0xFFFFFFFFFFFFFFB0), RegClassInfos, VTLists, HwMode) {
8326 InitMCRegisterInfo(D: X86RegDesc, NR: 388, RA, PC,
8327 C: X86MCRegisterClasses, NC: 135,
8328 RURoots: X86RegUnitRoots,
8329 NRU: 221,
8330 DL: X86RegDiffLists,
8331 RUMS: X86LaneMaskLists,
8332 Strings: X86RegStrings,
8333 ClassStrings: X86RegClassStrings,
8334 SubIndices: X86SubRegIdxLists,
8335 NumIndices: 11,
8336 RET: X86RegEncodingTable);
8337
8338 switch (DwarfFlavour) {
8339 default:
8340 llvm_unreachable("Unknown DWARF flavour");
8341 case 0:
8342 mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour0Dwarf2L, Size: X86DwarfFlavour0Dwarf2LSize, isEH: false);
8343 break;
8344 case 1:
8345 mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour1Dwarf2L, Size: X86DwarfFlavour1Dwarf2LSize, isEH: false);
8346 break;
8347 case 2:
8348 mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour2Dwarf2L, Size: X86DwarfFlavour2Dwarf2LSize, isEH: false);
8349 break;
8350 }
8351 switch (EHFlavour) {
8352 default:
8353 llvm_unreachable("Unknown DWARF flavour");
8354 case 0:
8355 mapDwarfRegsToLLVMRegs(Map: X86EHFlavour0Dwarf2L, Size: X86EHFlavour0Dwarf2LSize, isEH: true);
8356 break;
8357 case 1:
8358 mapDwarfRegsToLLVMRegs(Map: X86EHFlavour1Dwarf2L, Size: X86EHFlavour1Dwarf2LSize, isEH: true);
8359 break;
8360 case 2:
8361 mapDwarfRegsToLLVMRegs(Map: X86EHFlavour2Dwarf2L, Size: X86EHFlavour2Dwarf2LSize, isEH: true);
8362 break;
8363 }
8364 switch (DwarfFlavour) {
8365 default:
8366 llvm_unreachable("Unknown DWARF flavour");
8367 case 0:
8368 mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour0L2Dwarf, Size: X86DwarfFlavour0L2DwarfSize, isEH: false);
8369 break;
8370 case 1:
8371 mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour1L2Dwarf, Size: X86DwarfFlavour1L2DwarfSize, isEH: false);
8372 break;
8373 case 2:
8374 mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour2L2Dwarf, Size: X86DwarfFlavour2L2DwarfSize, isEH: false);
8375 break;
8376 }
8377 switch (EHFlavour) {
8378 default:
8379 llvm_unreachable("Unknown DWARF flavour");
8380 case 0:
8381 mapLLVMRegsToDwarfRegs(Map: X86EHFlavour0L2Dwarf, Size: X86EHFlavour0L2DwarfSize, isEH: true);
8382 break;
8383 case 1:
8384 mapLLVMRegsToDwarfRegs(Map: X86EHFlavour1L2Dwarf, Size: X86EHFlavour1L2DwarfSize, isEH: true);
8385 break;
8386 case 2:
8387 mapLLVMRegsToDwarfRegs(Map: X86EHFlavour2L2Dwarf, Size: X86EHFlavour2L2DwarfSize, isEH: true);
8388 break;
8389 }
8390}
8391
8392static const MCPhysReg CSR_32_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
8393static const uint32_t CSR_32_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8394static const MCPhysReg CSR_32EHRet_SaveList[] = { X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
8395static const uint32_t CSR_32EHRet_RegMask[] = { 0x0def83fe, 0xc000b701, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8396static const MCPhysReg CSR_32_AllRegs_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, 0 };
8397static const uint32_t CSR_32_AllRegs_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8398static const MCPhysReg CSR_32_AllRegs_AVX_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, 0 };
8399static const uint32_t CSR_32_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00007f80, 0x80000000, 0x0000007f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8400static const MCPhysReg CSR_32_AllRegs_AVX512_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
8401static const uint32_t CSR_32_AllRegs_AVX512_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00007f80, 0x80000000, 0x007f807f, 0x7f800000, 0x07800000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8402static const MCPhysReg CSR_32_AllRegs_SSE_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
8403static const uint32_t CSR_32_AllRegs_SSE_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00007f80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8404static const MCPhysReg CSR_32_RegCall_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
8405static const uint32_t CSR_32_RegCall_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00007800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8406static const MCPhysReg CSR_32_RegCall_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
8407static const uint32_t CSR_32_RegCall_NoSSE_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8408static const MCPhysReg CSR_64_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
8409static const uint32_t CSR_64_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8410static const MCPhysReg CSR_64EHRet_SaveList[] = { X86::RAX, X86::RDX, X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
8411static const uint32_t CSR_64EHRet_RegMask[] = { 0x09e883fe, 0x01382700, 0x00000000, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8412static const MCPhysReg CSR_64_AllRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::RAX, 0 };
8413static const uint32_t CSR_64_AllRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xffffff80, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8414static const MCPhysReg CSR_64_AllRegs_AVX_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
8415static const uint32_t CSR_64_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xffffff80, 0xffffffff, 0x00007fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8416static const MCPhysReg CSR_64_AllRegs_AVX512_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
8417static const uint32_t CSR_64_AllRegs_AVX512_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xffffff80, 0xffffffff, 0xffffffff, 0xffffffff, 0x07ffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8418static const MCPhysReg CSR_64_AllRegs_NoSSE_SaveList[] = { X86::RAX, X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
8419static const uint32_t CSR_64_AllRegs_NoSSE_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xff800000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8420static const MCPhysReg CSR_64_CXX_TLS_Darwin_PE_SaveList[] = { X86::RBP, 0 };
8421static const uint32_t CSR_64_CXX_TLS_Darwin_PE_RegMask[] = { 0x008001c0, 0x00100200, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8422static const MCPhysReg CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 };
8423static const uint32_t CSR_64_CXX_TLS_Darwin_ViaCopy_RegMask[] = { 0x0b28ae30, 0xd160ac01, 0x00000001, 0x7f800000, 0xff800000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8424static const MCPhysReg CSR_64_Intel_OCL_BI_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
8425static const uint32_t CSR_64_Intel_OCL_BI_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x787f8000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8426static const MCPhysReg CSR_64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
8427static const uint32_t CSR_64_Intel_OCL_BI_AVX_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x787f8000, 0x78787878, 0x00007f80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8428static const MCPhysReg CSR_64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RSI, X86::R14, X86::R15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
8429static const uint32_t CSR_64_Intel_OCL_BI_AVX512_RegMask[] = { 0x01000230, 0xd0208401, 0x00000001, 0x60000000, 0x60000000, 0x60606060, 0xfff80000, 0x007fffff, 0x067fff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8430static const MCPhysReg CSR_64_MostRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
8431static const uint32_t CSR_64_MostRegs_RegMask[] = { 0x0fafaff0, 0xd1f0be01, 0x00000001, 0x7f800000, 0xffffff80, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8432static const MCPhysReg CSR_64_NoneRegs_SaveList[] = { X86::RBP, 0 };
8433static const uint32_t CSR_64_NoneRegs_RegMask[] = { 0x008001c0, 0x00100200, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8434static const MCPhysReg CSR_64_RT_AllRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
8435static const uint32_t CSR_64_RT_AllRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffff80, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8436static const MCPhysReg CSR_64_RT_AllRegs_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
8437static const uint32_t CSR_64_RT_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffff80, 0xfbfbfbfb, 0x00007fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8438static const MCPhysReg CSR_64_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, 0 };
8439static const uint32_t CSR_64_RT_MostRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfb800000, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8440static const MCPhysReg CSR_64_SwiftError_SaveList[] = { X86::RBX, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
8441static const uint32_t CSR_64_SwiftError_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x70000000, 0x70000000, 0x70707070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8442static const MCPhysReg CSR_64_SwiftTail_SaveList[] = { X86::RBX, X86::R12, X86::R15, X86::RBP, 0 };
8443static const uint32_t CSR_64_SwiftTail_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x48000000, 0x48000000, 0x48484848, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8444static const MCPhysReg CSR_64_TLS_Darwin_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 };
8445static const uint32_t CSR_64_TLS_Darwin_RegMask[] = { 0x0ba8aff0, 0xd170ae01, 0x00000001, 0x7f800000, 0xff800000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8446static const MCPhysReg CSR_IPRA_32_SaveList[] = { X86::EBP, X86::ESI, 0 };
8447static const uint32_t CSR_IPRA_32_RegMask[] = { 0x008001c0, 0xc0008201, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8448static const MCPhysReg CSR_IPRA_64_SaveList[] = { X86::RBP, X86::RBX, 0 };
8449static const uint32_t CSR_IPRA_64_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8450static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
8451static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8452static const MCPhysReg CSR_SysV64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
8453static const uint32_t CSR_SysV64_RegCall_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x787f8000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8454static const MCPhysReg CSR_SysV64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
8455static const uint32_t CSR_SysV64_RegCall_NoSSE_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8456static const MCPhysReg CSR_Win32_CFGuard_Check_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::ECX, 0 };
8457static const uint32_t CSR_Win32_CFGuard_Check_RegMask[] = { 0x07872ff0, 0xc0009e01, 0x00000001, 0x00000000, 0x00007800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8458static const MCPhysReg CSR_Win32_CFGuard_Check_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ECX, 0 };
8459static const uint32_t CSR_Win32_CFGuard_Check_NoSSE_RegMask[] = { 0x07872ff0, 0xc0009e01, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8460static const MCPhysReg CSR_Win64_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
8461static const uint32_t CSR_Win64_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8462static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
8463static const uint32_t CSR_Win64_Intel_OCL_BI_AVX_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x00007fe0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8464static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
8465static const uint32_t CSR_Win64_Intel_OCL_BI_AVX512_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x1ff87fe0, 0xe0001f80, 0x06001fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8466static const MCPhysReg CSR_Win64_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
8467static const uint32_t CSR_Win64_NoSSE_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8468static const MCPhysReg CSR_Win64_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
8469static const uint32_t CSR_Win64_RT_MostRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffe000, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8470static const MCPhysReg CSR_Win64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
8471static const uint32_t CSR_Win64_RegCall_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x7e000000, 0x7e7f8000, 0x7e7e7e7e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8472static const MCPhysReg CSR_Win64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
8473static const uint32_t CSR_Win64_RegCall_NoSSE_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x7e000000, 0x7e000000, 0x7e7e7e7e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8474static const MCPhysReg CSR_Win64_SwiftError_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
8475static const uint32_t CSR_Win64_SwiftError_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x70000000, 0x707fe000, 0x70707070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8476static const MCPhysReg CSR_Win64_SwiftTail_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
8477static const uint32_t CSR_Win64_SwiftTail_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x48000000, 0x487fe000, 0x48484848, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8478
8479
8480ArrayRef<const uint32_t *> X86GenRegisterInfo::getRegMasks() const {
8481 static const uint32_t *const Masks[] = {
8482 CSR_32_RegMask,
8483 CSR_32EHRet_RegMask,
8484 CSR_32_AllRegs_RegMask,
8485 CSR_32_AllRegs_AVX_RegMask,
8486 CSR_32_AllRegs_AVX512_RegMask,
8487 CSR_32_AllRegs_SSE_RegMask,
8488 CSR_32_RegCall_RegMask,
8489 CSR_32_RegCall_NoSSE_RegMask,
8490 CSR_64_RegMask,
8491 CSR_64EHRet_RegMask,
8492 CSR_64_AllRegs_RegMask,
8493 CSR_64_AllRegs_AVX_RegMask,
8494 CSR_64_AllRegs_AVX512_RegMask,
8495 CSR_64_AllRegs_NoSSE_RegMask,
8496 CSR_64_CXX_TLS_Darwin_PE_RegMask,
8497 CSR_64_CXX_TLS_Darwin_ViaCopy_RegMask,
8498 CSR_64_Intel_OCL_BI_RegMask,
8499 CSR_64_Intel_OCL_BI_AVX_RegMask,
8500 CSR_64_Intel_OCL_BI_AVX512_RegMask,
8501 CSR_64_MostRegs_RegMask,
8502 CSR_64_NoneRegs_RegMask,
8503 CSR_64_RT_AllRegs_RegMask,
8504 CSR_64_RT_AllRegs_AVX_RegMask,
8505 CSR_64_RT_MostRegs_RegMask,
8506 CSR_64_SwiftError_RegMask,
8507 CSR_64_SwiftTail_RegMask,
8508 CSR_64_TLS_Darwin_RegMask,
8509 CSR_IPRA_32_RegMask,
8510 CSR_IPRA_64_RegMask,
8511 CSR_NoRegs_RegMask,
8512 CSR_SysV64_RegCall_RegMask,
8513 CSR_SysV64_RegCall_NoSSE_RegMask,
8514 CSR_Win32_CFGuard_Check_RegMask,
8515 CSR_Win32_CFGuard_Check_NoSSE_RegMask,
8516 CSR_Win64_RegMask,
8517 CSR_Win64_Intel_OCL_BI_AVX_RegMask,
8518 CSR_Win64_Intel_OCL_BI_AVX512_RegMask,
8519 CSR_Win64_NoSSE_RegMask,
8520 CSR_Win64_RT_MostRegs_RegMask,
8521 CSR_Win64_RegCall_RegMask,
8522 CSR_Win64_RegCall_NoSSE_RegMask,
8523 CSR_Win64_SwiftError_RegMask,
8524 CSR_Win64_SwiftTail_RegMask,
8525 };
8526 return ArrayRef(Masks);
8527}
8528
8529bool X86GenRegisterInfo::
8530isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
8531 return
8532 X86::GR64RegClass.contains(Reg: PhysReg) ||
8533 X86::GR32RegClass.contains(Reg: PhysReg) ||
8534 X86::GR16RegClass.contains(Reg: PhysReg) ||
8535 X86::GR8RegClass.contains(Reg: PhysReg) ||
8536 false;
8537}
8538
8539bool X86GenRegisterInfo::
8540isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
8541 return
8542 X86::GR64RegClass.hasSubClassEq(RC) ||
8543 X86::GR32RegClass.hasSubClassEq(RC) ||
8544 X86::GR16RegClass.hasSubClassEq(RC) ||
8545 X86::GR8RegClass.hasSubClassEq(RC) ||
8546 false;
8547}
8548
8549bool X86GenRegisterInfo::
8550isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
8551 return
8552 X86::DEBUG_REGRegClass.contains(Reg: PhysReg) ||
8553 X86::CONTROL_REGRegClass.contains(Reg: PhysReg) ||
8554 X86::CCRRegClass.contains(Reg: PhysReg) ||
8555 X86::FPCCRRegClass.contains(Reg: PhysReg) ||
8556 X86::DFCCRRegClass.contains(Reg: PhysReg) ||
8557 X86::TILERegClass.contains(Reg: PhysReg) ||
8558 X86::VK1PAIRRegClass.contains(Reg: PhysReg) ||
8559 X86::VK2PAIRRegClass.contains(Reg: PhysReg) ||
8560 X86::VK4PAIRRegClass.contains(Reg: PhysReg) ||
8561 X86::VK8PAIRRegClass.contains(Reg: PhysReg) ||
8562 X86::VK16PAIRRegClass.contains(Reg: PhysReg) ||
8563 false;
8564}
8565
8566bool X86GenRegisterInfo::
8567isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
8568 return
8569 false;
8570}
8571
8572bool X86GenRegisterInfo::
8573isConstantPhysReg(MCRegister PhysReg) const {
8574 return
8575 false;
8576}
8577
8578ArrayRef<const char *> X86GenRegisterInfo::getRegMaskNames() const {
8579 static const char *Names[] = {
8580 "CSR_32",
8581 "CSR_32EHRet",
8582 "CSR_32_AllRegs",
8583 "CSR_32_AllRegs_AVX",
8584 "CSR_32_AllRegs_AVX512",
8585 "CSR_32_AllRegs_SSE",
8586 "CSR_32_RegCall",
8587 "CSR_32_RegCall_NoSSE",
8588 "CSR_64",
8589 "CSR_64EHRet",
8590 "CSR_64_AllRegs",
8591 "CSR_64_AllRegs_AVX",
8592 "CSR_64_AllRegs_AVX512",
8593 "CSR_64_AllRegs_NoSSE",
8594 "CSR_64_CXX_TLS_Darwin_PE",
8595 "CSR_64_CXX_TLS_Darwin_ViaCopy",
8596 "CSR_64_Intel_OCL_BI",
8597 "CSR_64_Intel_OCL_BI_AVX",
8598 "CSR_64_Intel_OCL_BI_AVX512",
8599 "CSR_64_MostRegs",
8600 "CSR_64_NoneRegs",
8601 "CSR_64_RT_AllRegs",
8602 "CSR_64_RT_AllRegs_AVX",
8603 "CSR_64_RT_MostRegs",
8604 "CSR_64_SwiftError",
8605 "CSR_64_SwiftTail",
8606 "CSR_64_TLS_Darwin",
8607 "CSR_IPRA_32",
8608 "CSR_IPRA_64",
8609 "CSR_NoRegs",
8610 "CSR_SysV64_RegCall",
8611 "CSR_SysV64_RegCall_NoSSE",
8612 "CSR_Win32_CFGuard_Check",
8613 "CSR_Win32_CFGuard_Check_NoSSE",
8614 "CSR_Win64",
8615 "CSR_Win64_Intel_OCL_BI_AVX",
8616 "CSR_Win64_Intel_OCL_BI_AVX512",
8617 "CSR_Win64_NoSSE",
8618 "CSR_Win64_RT_MostRegs",
8619 "CSR_Win64_RegCall",
8620 "CSR_Win64_RegCall_NoSSE",
8621 "CSR_Win64_SwiftError",
8622 "CSR_Win64_SwiftTail",
8623 };
8624 return ArrayRef(Names);
8625}
8626
8627const X86FrameLowering *
8628X86GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
8629 return static_cast<const X86FrameLowering *>(
8630 MF.getSubtarget().getFrameLowering());
8631}
8632
8633} // end namespace llvm
8634
8635