1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass X86MCRegisterClasses[];
12
13static const MVT::SimpleValueType X86VTLists[] = {
14 /* 0 */ MVT::i8, MVT::Other,
15 /* 2 */ MVT::i16, MVT::Other,
16 /* 4 */ MVT::i32, MVT::Other,
17 /* 6 */ MVT::i64, MVT::Other,
18 /* 8 */ MVT::f16, MVT::Other,
19 /* 10 */ MVT::f80, MVT::f64, MVT::f32, MVT::Other,
20 /* 14 */ MVT::f64, MVT::Other,
21 /* 16 */ MVT::f80, MVT::Other,
22 /* 18 */ MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::v8bf16, MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::f128, MVT::Other,
23 /* 28 */ MVT::v1i1, MVT::Other,
24 /* 30 */ MVT::v2i1, MVT::Other,
25 /* 32 */ MVT::v4i1, MVT::Other,
26 /* 34 */ MVT::v8i1, MVT::Other,
27 /* 36 */ MVT::v16i1, MVT::Other,
28 /* 38 */ MVT::v32i1, MVT::Other,
29 /* 40 */ MVT::v64i1, MVT::Other,
30 /* 42 */ MVT::v8f32, MVT::v4f64, MVT::v16f16, MVT::v16bf16, MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::Other,
31 /* 51 */ MVT::v16f32, MVT::v8f64, MVT::v32f16, MVT::v32bf16, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
32 /* 60 */ MVT::v16f32, MVT::v8f64, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
33 /* 67 */ MVT::x86mmx, MVT::Other,
34 /* 69 */ MVT::Untyped, MVT::Other,
35 /* 71 */ MVT::x86amx, MVT::Other,
36};
37
38#ifdef __GNUC__
39#pragma GCC diagnostic push
40#pragma GCC diagnostic ignored "-Woverlength-strings"
41#endif
42static constexpr char X86SubRegIndexStrings[] = {
43 /* 0 */ "sub_mask_0\000"
44 /* 11 */ "sub_mask_1\000"
45 /* 22 */ "sub_16bit_hi\000"
46 /* 35 */ "sub_8bit_hi\000"
47 /* 47 */ "sub_xmm\000"
48 /* 55 */ "sub_ymm\000"
49 /* 63 */ "sub_32bit\000"
50 /* 73 */ "sub_16bit\000"
51 /* 83 */ "sub_8bit\000"
52 /* 92 */ "sub_8bit_hi_phony\000"
53};
54#ifdef __GNUC__
55#pragma GCC diagnostic pop
56#endif
57
58
59static constexpr uint32_t X86SubRegIndexNameOffsets[] = {
60 83,
61 35,
62 92,
63 73,
64 22,
65 63,
66 0,
67 11,
68 47,
69 55,
70};
71
72static const TargetRegisterInfo::SubRegCoveredBits X86SubRegIdxRangeTable[] = {
73 { .Offset: 65535, .Size: 65535 },
74 { .Offset: 0, .Size: 8 }, // sub_8bit
75 { .Offset: 8, .Size: 8 }, // sub_8bit_hi
76 { .Offset: 8, .Size: 8 }, // sub_8bit_hi_phony
77 { .Offset: 0, .Size: 16 }, // sub_16bit
78 { .Offset: 16, .Size: 16 }, // sub_16bit_hi
79 { .Offset: 0, .Size: 32 }, // sub_32bit
80 { .Offset: 0, .Size: 65535 }, // sub_mask_0
81 { .Offset: 65535, .Size: 65535 }, // sub_mask_1
82 { .Offset: 0, .Size: 128 }, // sub_xmm
83 { .Offset: 0, .Size: 256 }, // sub_ymm
84 { .Offset: 65535, .Size: 65535 },
85 { .Offset: 0, .Size: 8 }, // sub_8bit
86 { .Offset: 8, .Size: 8 }, // sub_8bit_hi
87 { .Offset: 8, .Size: 8 }, // sub_8bit_hi_phony
88 { .Offset: 0, .Size: 16 }, // sub_16bit
89 { .Offset: 16, .Size: 16 }, // sub_16bit_hi
90 { .Offset: 0, .Size: 32 }, // sub_32bit
91 { .Offset: 0, .Size: 65535 }, // sub_mask_0
92 { .Offset: 65535, .Size: 65535 }, // sub_mask_1
93 { .Offset: 0, .Size: 128 }, // sub_xmm
94 { .Offset: 0, .Size: 256 }, // sub_ymm
95 { .Offset: 65535, .Size: 65535 },
96 { .Offset: 0, .Size: 8 }, // sub_8bit
97 { .Offset: 8, .Size: 8 }, // sub_8bit_hi
98 { .Offset: 8, .Size: 8 }, // sub_8bit_hi_phony
99 { .Offset: 0, .Size: 16 }, // sub_16bit
100 { .Offset: 16, .Size: 16 }, // sub_16bit_hi
101 { .Offset: 0, .Size: 32 }, // sub_32bit
102 { .Offset: 0, .Size: 65535 }, // sub_mask_0
103 { .Offset: 65535, .Size: 65535 }, // sub_mask_1
104 { .Offset: 0, .Size: 128 }, // sub_xmm
105 { .Offset: 0, .Size: 256 }, // sub_ymm
106};
107
108
109static const LaneBitmask X86SubRegIndexLaneMaskTable[] = {
110 LaneBitmask::getAll(),
111 LaneBitmask(0x0000000000000001), // sub_8bit
112 LaneBitmask(0x0000000000000002), // sub_8bit_hi
113 LaneBitmask(0x0000000000000004), // sub_8bit_hi_phony
114 LaneBitmask(0x0000000000000007), // sub_16bit
115 LaneBitmask(0x0000000000000008), // sub_16bit_hi
116 LaneBitmask(0x000000000000000F), // sub_32bit
117 LaneBitmask(0x0000000000000010), // sub_mask_0
118 LaneBitmask(0x0000000000000020), // sub_mask_1
119 LaneBitmask(0x0000000000000040), // sub_xmm
120 LaneBitmask(0x0000000000000040), // sub_ymm
121 };
122
123
124
125static const TargetRegisterInfo::RegClassInfo X86RegClassInfos[] = {
126 // Mode = 0 (DefaultMode)
127 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8
128 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GRH8
129 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_NOREX2
130 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_NOREX
131 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_H
132 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_L
133 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GRH16
134 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16
135 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_NOREX2
136 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_NOREX
137 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 28 }, // VK1
138 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 36 }, // VK16
139 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 30 }, // VK2
140 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 32 }, // VK4
141 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 34 }, // VK8
142 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 36 }, // VK16WM
143 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 28 }, // VK1WM
144 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 30 }, // VK2WM
145 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 32 }, // VK4WM
146 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 34 }, // VK8WM
147 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // SEGMENT_REG
148 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_ABCD
149 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // FPCCR
150 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 8 }, // FR16X
151 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 8 }, // FR16
152 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK16PAIR
153 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK1PAIR
154 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK2PAIR
155 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK4PAIR
156 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK8PAIR
157 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK1PAIR_with_sub_mask_0_in_VK1WM
158 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP
159 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS
160 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
161 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // FR32X
162 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32
163 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOSP
164 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
165 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // DEBUG_REG
166 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // FR32
167 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2
168 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2_NOSP
169 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
170 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX
171 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 38 }, // VK32
172 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX_NOSP
173 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // RFP32
174 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 38 }, // VK32WM
175 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD
176 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_TC
177 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_TC
178 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_AD
179 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef
180 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP
181 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BSI
182 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_CB
183 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DC
184 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DIBP
185 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_SIDI
186 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
187 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // CCR
188 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // DFCCR
189 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_BSI
190 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_AD_and_GR32_ArgRef
191 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef_and_GR32_CB
192 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_DIBP
193 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_TC
194 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BSI_and_GR32_SIDI
195 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DIBP_and_GR32_SIDI
196 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
197 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_with_sub_32bit
198 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 14 }, // RFP64
199 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64
200 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 14 }, // FR64X
201 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_8bit
202 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOSP
203 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2
204 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // CONTROL_REG
205 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 14 }, // FR64
206 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX2
207 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP
208 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe
209 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC
210 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX
211 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64
212 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_with_sub_8bit
213 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TC
214 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_with_sub_8bit
215 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_TCW64
216 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX
217 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 40 }, // VK64
218 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 67 }, // VR64
219 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TC
220 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TCW64
221 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_NOSP
222 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TC
223 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_and_GR64_TC_with_sub_8bit
224 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 40 }, // VK64WM
225 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
226 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
227 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TCW64
228 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
229 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TCW64
230 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ABCD
231 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_TC
232 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
233 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_AD
234 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef
235 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS_RBP
236 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef
237 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP
238 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI
239 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_CB
240 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP
241 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_SIDI
242 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_A
243 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef_and_GR64_TC
244 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS
245 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
246 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
247 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
248 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
249 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
250 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
251 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
252 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 10 }, // RST
253 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 16 }, // RFP80
254 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 16 }, // RFP80_7
255 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*X86VTLists+*/.VTListOffset: 18 }, // VR128X
256 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*X86VTLists+*/.VTListOffset: 18 }, // VR128
257 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*X86VTLists+*/.VTListOffset: 42 }, // VR256X
258 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*X86VTLists+*/.VTListOffset: 42 }, // VR256
259 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*X86VTLists+*/.VTListOffset: 51 }, // VR512
260 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*X86VTLists+*/.VTListOffset: 60 }, // VR512_0_15
261 { .RegSize: 8192, .SpillSize: 8192, .SpillAlignment: 8192, /*X86VTLists+*/.VTListOffset: 71 }, // TILE
262 // Mode = 1 (X86_64)
263 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8
264 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GRH8
265 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_NOREX2
266 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_NOREX
267 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_H
268 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_L
269 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GRH16
270 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16
271 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_NOREX2
272 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_NOREX
273 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 28 }, // VK1
274 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 36 }, // VK16
275 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 30 }, // VK2
276 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 32 }, // VK4
277 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 34 }, // VK8
278 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 36 }, // VK16WM
279 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 28 }, // VK1WM
280 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 30 }, // VK2WM
281 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 32 }, // VK4WM
282 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 34 }, // VK8WM
283 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // SEGMENT_REG
284 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_ABCD
285 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // FPCCR
286 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 8 }, // FR16X
287 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 8 }, // FR16
288 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK16PAIR
289 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK1PAIR
290 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK2PAIR
291 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK4PAIR
292 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK8PAIR
293 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK1PAIR_with_sub_mask_0_in_VK1WM
294 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP
295 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS
296 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
297 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // FR32X
298 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32
299 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOSP
300 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
301 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // DEBUG_REG
302 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // FR32
303 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2
304 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2_NOSP
305 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
306 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX
307 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 38 }, // VK32
308 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX_NOSP
309 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // RFP32
310 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 38 }, // VK32WM
311 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD
312 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_TC
313 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_TC
314 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_AD
315 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef
316 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP
317 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BSI
318 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_CB
319 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DC
320 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DIBP
321 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_SIDI
322 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
323 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // CCR
324 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // DFCCR
325 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_BSI
326 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_AD_and_GR32_ArgRef
327 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef_and_GR32_CB
328 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_DIBP
329 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_TC
330 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BSI_and_GR32_SIDI
331 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DIBP_and_GR32_SIDI
332 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
333 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_with_sub_32bit
334 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 14 }, // RFP64
335 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64
336 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 14 }, // FR64X
337 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_8bit
338 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOSP
339 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2
340 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // CONTROL_REG
341 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 14 }, // FR64
342 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX2
343 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP
344 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe
345 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC
346 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX
347 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64
348 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_with_sub_8bit
349 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TC
350 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_with_sub_8bit
351 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_TCW64
352 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX
353 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 40 }, // VK64
354 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 67 }, // VR64
355 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TC
356 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TCW64
357 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_NOSP
358 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TC
359 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_and_GR64_TC_with_sub_8bit
360 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 40 }, // VK64WM
361 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
362 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
363 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TCW64
364 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
365 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TCW64
366 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ABCD
367 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_TC
368 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
369 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_AD
370 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef
371 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS_RBP
372 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef
373 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP
374 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI
375 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_CB
376 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP
377 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_SIDI
378 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_A
379 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef_and_GR64_TC
380 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS
381 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
382 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
383 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
384 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
385 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
386 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
387 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
388 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 10 }, // RST
389 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 16 }, // RFP80
390 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 16 }, // RFP80_7
391 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*X86VTLists+*/.VTListOffset: 18 }, // VR128X
392 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*X86VTLists+*/.VTListOffset: 18 }, // VR128
393 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*X86VTLists+*/.VTListOffset: 42 }, // VR256X
394 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*X86VTLists+*/.VTListOffset: 42 }, // VR256
395 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*X86VTLists+*/.VTListOffset: 51 }, // VR512
396 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*X86VTLists+*/.VTListOffset: 60 }, // VR512_0_15
397 { .RegSize: 8192, .SpillSize: 8192, .SpillAlignment: 8192, /*X86VTLists+*/.VTListOffset: 71 }, // TILE
398 // Mode = 2 (X86_64_X32)
399 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8
400 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GRH8
401 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_NOREX2
402 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_NOREX
403 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_H
404 { .RegSize: 8, .SpillSize: 8, .SpillAlignment: 8, /*X86VTLists+*/.VTListOffset: 0 }, // GR8_ABCD_L
405 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GRH16
406 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16
407 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_NOREX2
408 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_NOREX
409 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 28 }, // VK1
410 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 36 }, // VK16
411 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 30 }, // VK2
412 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 32 }, // VK4
413 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 34 }, // VK8
414 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 36 }, // VK16WM
415 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 28 }, // VK1WM
416 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 30 }, // VK2WM
417 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 32 }, // VK4WM
418 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 34 }, // VK8WM
419 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // SEGMENT_REG
420 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // GR16_ABCD
421 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 2 }, // FPCCR
422 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 8 }, // FR16X
423 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 8 }, // FR16
424 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK16PAIR
425 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK1PAIR
426 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK2PAIR
427 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK4PAIR
428 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK8PAIR
429 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 16, /*X86VTLists+*/.VTListOffset: 69 }, // VK1PAIR_with_sub_mask_0_in_VK1WM
430 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP
431 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS
432 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
433 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // FR32X
434 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32
435 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOSP
436 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
437 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // DEBUG_REG
438 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // FR32
439 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2
440 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX2_NOSP
441 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
442 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX
443 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 38 }, // VK32
444 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_NOREX_NOSP
445 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 12 }, // RFP32
446 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 38 }, // VK32WM
447 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD
448 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_TC
449 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_TC
450 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_AD
451 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef
452 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP
453 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BSI
454 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_CB
455 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DC
456 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DIBP
457 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_SIDI
458 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
459 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // CCR
460 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // DFCCR
461 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ABCD_and_GR32_BSI
462 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_AD_and_GR32_ArgRef
463 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_ArgRef_and_GR32_CB
464 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_DIBP
465 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BPSP_and_GR32_TC
466 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_BSI_and_GR32_SIDI
467 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // GR32_DIBP_and_GR32_SIDI
468 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
469 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 4 }, // LOW32_ADDR_ACCESS_with_sub_32bit
470 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 14 }, // RFP64
471 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64
472 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 14 }, // FR64X
473 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_8bit
474 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOSP
475 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2
476 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // CONTROL_REG
477 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 14 }, // FR64
478 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX2
479 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP
480 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe
481 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC
482 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX
483 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64
484 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_with_sub_8bit
485 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TC
486 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_with_sub_8bit
487 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_TCW64
488 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_16bit_in_GR16_NOREX
489 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 40 }, // VK64
490 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 67 }, // VR64
491 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TC
492 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX2_NOSP_and_GR64_TCW64
493 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_NOSP
494 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TC
495 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TCW64_and_GR64_TC_with_sub_8bit
496 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 40 }, // VK64WM
497 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
498 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
499 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64PLTSafe_and_GR64_TCW64
500 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
501 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_NOREX_and_GR64_TCW64
502 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ABCD
503 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_TC
504 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
505 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_AD
506 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef
507 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS_RBP
508 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef
509 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP
510 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI
511 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_CB
512 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP
513 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_SIDI
514 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_A
515 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_ArgRef_and_GR64_TC
516 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_and_LOW32_ADDR_ACCESS
517 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
518 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
519 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
520 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
521 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
522 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
523 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*X86VTLists+*/.VTListOffset: 6 }, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
524 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 10 }, // RST
525 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 16 }, // RFP80
526 { .RegSize: 80, .SpillSize: 80, .SpillAlignment: 32, /*X86VTLists+*/.VTListOffset: 16 }, // RFP80_7
527 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*X86VTLists+*/.VTListOffset: 18 }, // VR128X
528 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*X86VTLists+*/.VTListOffset: 18 }, // VR128
529 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*X86VTLists+*/.VTListOffset: 42 }, // VR256X
530 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*X86VTLists+*/.VTListOffset: 42 }, // VR256
531 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*X86VTLists+*/.VTListOffset: 51 }, // VR512
532 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*X86VTLists+*/.VTListOffset: 60 }, // VR512_0_15
533 { .RegSize: 8192, .SpillSize: 8192, .SpillAlignment: 8192, /*X86VTLists+*/.VTListOffset: 71 }, // TILE
534};
535static const uint32_t GR8SubClassMask[] = {
536 0x0000003d, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
537 0x00200380, 0xc7ff2f3a, 0x72e38c3f, 0x1fdfefbd, 0x00000000, // sub_8bit
538 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
539};
540
541static const uint32_t GRH8SubClassMask[] = {
542 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
543};
544
545static const uint32_t GR8_NOREX2SubClassMask[] = {
546 0x0000003c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
547 0x00200300, 0xc7ff2f20, 0x72e3803f, 0x1fdfefbd, 0x00000000, // sub_8bit
548 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
549};
550
551static const uint32_t GR8_NOREXSubClassMask[] = {
552 0x00000038, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
553 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit
554 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
555};
556
557static const uint32_t GR8_ABCD_HSubClassMask[] = {
558 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
559 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit_hi
560};
561
562static const uint32_t GR8_ABCD_LSubClassMask[] = {
563 0x00000020, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
564 0x00200000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_8bit
565};
566
567static const uint32_t GRH16SubClassMask[] = {
568 0x00000040, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
569};
570
571static const uint32_t GR16SubClassMask[] = {
572 0x00200380, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
573 0x00000000, 0xc7ff2f3a, 0x72e38c3f, 0x1fdfefbd, 0x00000000, // sub_16bit
574};
575
576static const uint32_t GR16_NOREX2SubClassMask[] = {
577 0x00200300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
578 0x00000000, 0xc7ff2f20, 0x72e3803f, 0x1fdfefbd, 0x00000000, // sub_16bit
579};
580
581static const uint32_t GR16_NOREXSubClassMask[] = {
582 0x00200200, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
583 0x00000000, 0xc7ff2c00, 0x4200003f, 0x1fcfe7a8, 0x00000000, // sub_16bit
584};
585
586static const uint32_t VK1SubClassMask[] = {
587 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
588 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
589 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
590};
591
592static const uint32_t VK16SubClassMask[] = {
593 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
594 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
595 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
596};
597
598static const uint32_t VK2SubClassMask[] = {
599 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
600 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
601 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
602};
603
604static const uint32_t VK4SubClassMask[] = {
605 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
606 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
607 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
608};
609
610static const uint32_t VK8SubClassMask[] = {
611 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
612 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
613 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
614};
615
616static const uint32_t VK16WMSubClassMask[] = {
617 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
618 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
619 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
620};
621
622static const uint32_t VK1WMSubClassMask[] = {
623 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
624 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
625 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
626};
627
628static const uint32_t VK2WMSubClassMask[] = {
629 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
630 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
631 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
632};
633
634static const uint32_t VK4WMSubClassMask[] = {
635 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
636 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
637 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
638};
639
640static const uint32_t VK8WMSubClassMask[] = {
641 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
642 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
643 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
644};
645
646static const uint32_t SEGMENT_REGSubClassMask[] = {
647 0x00100000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
648};
649
650static const uint32_t GR16_ABCDSubClassMask[] = {
651 0x00200000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
652 0x00000000, 0xc19d0000, 0x00000001, 0x01c92680, 0x00000000, // sub_16bit
653};
654
655static const uint32_t FPCCRSubClassMask[] = {
656 0x00400000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
657};
658
659static const uint32_t FR16XSubClassMask[] = {
660 0x01800000, 0x00000084, 0x00004200, 0x00000000, 0x00000003,
661 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
662};
663
664static const uint32_t FR16SubClassMask[] = {
665 0x01000000, 0x00000080, 0x00004000, 0x00000000, 0x00000002,
666 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
667};
668
669static const uint32_t VK16PAIRSubClassMask[] = {
670 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
671};
672
673static const uint32_t VK1PAIRSubClassMask[] = {
674 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
675};
676
677static const uint32_t VK2PAIRSubClassMask[] = {
678 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
679};
680
681static const uint32_t VK4PAIRSubClassMask[] = {
682 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
683};
684
685static const uint32_t VK8PAIRSubClassMask[] = {
686 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
687};
688
689static const uint32_t VK1PAIR_with_sub_mask_0_in_VK1WMSubClassMask[] = {
690 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
691};
692
693static const uint32_t LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
694 0x80000000, 0xcfff2f3b, 0x0000007f, 0x02201000, 0x00000000,
695 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
696};
697
698static const uint32_t LOW32_ADDR_ACCESSSubClassMask[] = {
699 0x00000000, 0xc7ff2b19, 0x0000005f, 0x00200000, 0x00000000,
700 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
701};
702
703static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask[] = {
704 0x00000000, 0xc7ff2f3a, 0x0000003f, 0x02000000, 0x00000000,
705 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
706};
707
708static const uint32_t FR32XSubClassMask[] = {
709 0x00000000, 0x00000084, 0x00004200, 0x00000000, 0x00000003,
710 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
711};
712
713static const uint32_t GR32SubClassMask[] = {
714 0x00000000, 0xc7ff2b18, 0x0000001f, 0x00000000, 0x00000000,
715 0x00000000, 0x00000000, 0x72e38c20, 0x1fdfefbd, 0x00000000, // sub_32bit
716};
717
718static const uint32_t GR32_NOSPSubClassMask[] = {
719 0x00000000, 0xc7dd2210, 0x0000001b, 0x00000000, 0x00000000,
720 0x00000000, 0x00000000, 0x70430820, 0x1bdfaeb4, 0x00000000, // sub_32bit
721};
722
723static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2SubClassMask[] = {
724 0x00000000, 0xc7ff2f20, 0x0000003f, 0x02000000, 0x00000000,
725 0x00000000, 0x00000000, 0x72e38020, 0x1fdfefbd, 0x00000000, // sub_32bit
726};
727
728static const uint32_t DEBUG_REGSubClassMask[] = {
729 0x00000000, 0x00000040, 0x00000000, 0x00000000, 0x00000000,
730};
731
732static const uint32_t FR32SubClassMask[] = {
733 0x00000000, 0x00000080, 0x00004000, 0x00000000, 0x00000002,
734 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
735};
736
737static const uint32_t GR32_NOREX2SubClassMask[] = {
738 0x00000000, 0xc7ff2b00, 0x0000001f, 0x00000000, 0x00000000,
739 0x00000000, 0x00000000, 0x72e38020, 0x1fdfefbd, 0x00000000, // sub_32bit
740};
741
742static const uint32_t GR32_NOREX2_NOSPSubClassMask[] = {
743 0x00000000, 0xc7dd2200, 0x0000001b, 0x00000000, 0x00000000,
744 0x00000000, 0x00000000, 0x70430020, 0x1bdfaeb4, 0x00000000, // sub_32bit
745};
746
747static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
748 0x00000000, 0xc7ff2c00, 0x0000003f, 0x02000000, 0x00000000,
749 0x00000000, 0x00000000, 0x42000020, 0x1fcfe7a8, 0x00000000, // sub_32bit
750};
751
752static const uint32_t GR32_NOREXSubClassMask[] = {
753 0x00000000, 0xc7ff2800, 0x0000001f, 0x00000000, 0x00000000,
754 0x00000000, 0x00000000, 0x42000020, 0x1fcfe7a8, 0x00000000, // sub_32bit
755};
756
757static const uint32_t VK32SubClassMask[] = {
758 0x00000000, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
759 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
760 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
761};
762
763static const uint32_t GR32_NOREX_NOSPSubClassMask[] = {
764 0x00000000, 0xc7dd2000, 0x0000001b, 0x00000000, 0x00000000,
765 0x00000000, 0x00000000, 0x40000020, 0x1bcfa6a0, 0x00000000, // sub_32bit
766};
767
768static const uint32_t RFP32SubClassMask[] = {
769 0x00000000, 0x00004000, 0x00000080, 0x40000000, 0x00000000,
770};
771
772static const uint32_t VK32WMSubClassMask[] = {
773 0x00000000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
774 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
775 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
776};
777
778static const uint32_t GR32_ABCDSubClassMask[] = {
779 0x00000000, 0xc19d0000, 0x00000001, 0x00000000, 0x00000000,
780 0x00000000, 0x00000000, 0x00000000, 0x01c92680, 0x00000000, // sub_32bit
781};
782
783static const uint32_t GR32_TCSubClassMask[] = {
784 0x00000000, 0x811e0000, 0x00000005, 0x00000000, 0x00000000,
785 0x00000000, 0x00000000, 0x00000000, 0x05882700, 0x00000000, // sub_32bit
786};
787
788static const uint32_t GR32_ABCD_and_GR32_TCSubClassMask[] = {
789 0x00000000, 0x811c0000, 0x00000001, 0x00000000, 0x00000000,
790 0x00000000, 0x00000000, 0x00000000, 0x01882600, 0x00000000, // sub_32bit
791};
792
793static const uint32_t GR32_ADSubClassMask[] = {
794 0x00000000, 0x80080000, 0x00000000, 0x00000000, 0x00000000,
795 0x00000000, 0x00000000, 0x00000000, 0x00880400, 0x00000000, // sub_32bit
796};
797
798static const uint32_t GR32_ArgRefSubClassMask[] = {
799 0x00000000, 0x81100000, 0x00000001, 0x00000000, 0x00000000,
800 0x00000000, 0x00000000, 0x00000000, 0x01802000, 0x00000000, // sub_32bit
801};
802
803static const uint32_t GR32_BPSPSubClassMask[] = {
804 0x00000000, 0x00200000, 0x00000006, 0x00000000, 0x00000000,
805 0x00000000, 0x00000000, 0x00000020, 0x06004000, 0x00000000, // sub_32bit
806};
807
808static const uint32_t GR32_BSISubClassMask[] = {
809 0x00000000, 0x40400000, 0x00000008, 0x00000000, 0x00000000,
810 0x00000000, 0x00000000, 0x00000000, 0x08408000, 0x00000000, // sub_32bit
811};
812
813static const uint32_t GR32_CBSubClassMask[] = {
814 0x00000000, 0x40800000, 0x00000001, 0x00000000, 0x00000000,
815 0x00000000, 0x00000000, 0x00000000, 0x01410000, 0x00000000, // sub_32bit
816};
817
818static const uint32_t GR32_DCSubClassMask[] = {
819 0x00000000, 0x81000000, 0x00000001, 0x00000000, 0x00000000,
820 0x00000000, 0x00000000, 0x00000000, 0x01802000, 0x00000000, // sub_32bit
821};
822
823static const uint32_t GR32_DIBPSubClassMask[] = {
824 0x00000000, 0x02000000, 0x00000012, 0x00000000, 0x00000000,
825 0x00000000, 0x00000000, 0x00000020, 0x12020000, 0x00000000, // sub_32bit
826};
827
828static const uint32_t GR32_SIDISubClassMask[] = {
829 0x00000000, 0x04000000, 0x00000018, 0x00000000, 0x00000000,
830 0x00000000, 0x00000000, 0x00000000, 0x18040000, 0x00000000, // sub_32bit
831};
832
833static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask[] = {
834 0x00000000, 0x08000000, 0x00000060, 0x02201000, 0x00000000,
835};
836
837static const uint32_t CCRSubClassMask[] = {
838 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000,
839};
840
841static const uint32_t DFCCRSubClassMask[] = {
842 0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00000000,
843};
844
845static const uint32_t GR32_ABCD_and_GR32_BSISubClassMask[] = {
846 0x00000000, 0x40000000, 0x00000000, 0x00000000, 0x00000000,
847 0x00000000, 0x00000000, 0x00000000, 0x00400000, 0x00000000, // sub_32bit
848};
849
850static const uint32_t GR32_AD_and_GR32_ArgRefSubClassMask[] = {
851 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000,
852 0x00000000, 0x00000000, 0x00000000, 0x00800000, 0x00000000, // sub_32bit
853};
854
855static const uint32_t GR32_ArgRef_and_GR32_CBSubClassMask[] = {
856 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000,
857 0x00000000, 0x00000000, 0x00000000, 0x01000000, 0x00000000, // sub_32bit
858};
859
860static const uint32_t GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
861 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000,
862 0x00000000, 0x00000000, 0x00000020, 0x02000000, 0x00000000, // sub_32bit
863};
864
865static const uint32_t GR32_BPSP_and_GR32_TCSubClassMask[] = {
866 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000,
867 0x00000000, 0x00000000, 0x00000000, 0x04000000, 0x00000000, // sub_32bit
868};
869
870static const uint32_t GR32_BSI_and_GR32_SIDISubClassMask[] = {
871 0x00000000, 0x00000000, 0x00000008, 0x00000000, 0x00000000,
872 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000000, // sub_32bit
873};
874
875static const uint32_t GR32_DIBP_and_GR32_SIDISubClassMask[] = {
876 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000,
877 0x00000000, 0x00000000, 0x00000000, 0x10000000, 0x00000000, // sub_32bit
878};
879
880static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask[] = {
881 0x00000000, 0x00000000, 0x00000020, 0x02000000, 0x00000000,
882};
883
884static const uint32_t LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask[] = {
885 0x00000000, 0x00000000, 0x00000040, 0x00200000, 0x00000000,
886};
887
888static const uint32_t RFP64SubClassMask[] = {
889 0x00000000, 0x00000000, 0x00000080, 0x40000000, 0x00000000,
890};
891
892static const uint32_t GR64SubClassMask[] = {
893 0x00000000, 0x00000000, 0xf3ff9d00, 0x1ffffffd, 0x00000000,
894};
895
896static const uint32_t FR64XSubClassMask[] = {
897 0x00000000, 0x00000000, 0x00004200, 0x00000000, 0x00000003,
898 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
899};
900
901static const uint32_t GR64_with_sub_8bitSubClassMask[] = {
902 0x00000000, 0x00000000, 0x72e38c00, 0x1fdfefbd, 0x00000000,
903};
904
905static const uint32_t GR64_NOSPSubClassMask[] = {
906 0x00000000, 0x00000000, 0x70430800, 0x1bdfaeb4, 0x00000000,
907};
908
909static const uint32_t GR64_NOREX2SubClassMask[] = {
910 0x00000000, 0x00000000, 0xf3ff9000, 0x1ffffffd, 0x00000000,
911};
912
913static const uint32_t CONTROL_REGSubClassMask[] = {
914 0x00000000, 0x00000000, 0x00002000, 0x00000000, 0x00000000,
915};
916
917static const uint32_t FR64SubClassMask[] = {
918 0x00000000, 0x00000000, 0x00004000, 0x00000000, 0x00000002,
919 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
920};
921
922static const uint32_t GR64_with_sub_16bit_in_GR16_NOREX2SubClassMask[] = {
923 0x00000000, 0x00000000, 0x72e38000, 0x1fdfefbd, 0x00000000,
924};
925
926static const uint32_t GR64_NOREX2_NOSPSubClassMask[] = {
927 0x00000000, 0x00000000, 0x70430000, 0x1bdfaeb4, 0x00000000,
928};
929
930static const uint32_t GR64PLTSafeSubClassMask[] = {
931 0x00000000, 0x00000000, 0x50020000, 0x1bcfa6b0, 0x00000000,
932};
933
934static const uint32_t GR64_TCSubClassMask[] = {
935 0x00000000, 0x00000000, 0x91640000, 0x1dbc277d, 0x00000000,
936};
937
938static const uint32_t GR64_NOREXSubClassMask[] = {
939 0x00000000, 0x00000000, 0xc2080000, 0x1feff7e8, 0x00000000,
940};
941
942static const uint32_t GR64_TCW64SubClassMask[] = {
943 0x00000000, 0x00000000, 0x21900000, 0x05b82f55, 0x00000000,
944};
945
946static const uint32_t GR64_TC_with_sub_8bitSubClassMask[] = {
947 0x00000000, 0x00000000, 0x10600000, 0x1d9c273d, 0x00000000,
948};
949
950static const uint32_t GR64_NOREX2_NOSP_and_GR64_TCSubClassMask[] = {
951 0x00000000, 0x00000000, 0x10400000, 0x199c2634, 0x00000000,
952};
953
954static const uint32_t GR64_TCW64_with_sub_8bitSubClassMask[] = {
955 0x00000000, 0x00000000, 0x20800000, 0x05982f15, 0x00000000,
956};
957
958static const uint32_t GR64_TC_and_GR64_TCW64SubClassMask[] = {
959 0x00000000, 0x00000000, 0x01000000, 0x05b82755, 0x00000000,
960};
961
962static const uint32_t GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
963 0x00000000, 0x00000000, 0x42000000, 0x1fcfe7a8, 0x00000000,
964};
965
966static const uint32_t VK64SubClassMask[] = {
967 0x00000000, 0x00000000, 0x04000000, 0x00000002, 0x00000000,
968 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
969 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
970};
971
972static const uint32_t VR64SubClassMask[] = {
973 0x00000000, 0x00000000, 0x08000000, 0x00000000, 0x00000000,
974};
975
976static const uint32_t GR64PLTSafe_and_GR64_TCSubClassMask[] = {
977 0x00000000, 0x00000000, 0x10000000, 0x198c2630, 0x00000000,
978};
979
980static const uint32_t GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask[] = {
981 0x00000000, 0x00000000, 0x20000000, 0x01982e14, 0x00000000,
982};
983
984static const uint32_t GR64_NOREX_NOSPSubClassMask[] = {
985 0x00000000, 0x00000000, 0x40000000, 0x1bcfa6a0, 0x00000000,
986};
987
988static const uint32_t GR64_NOREX_and_GR64_TCSubClassMask[] = {
989 0x00000000, 0x00000000, 0x80000000, 0x1dac2768, 0x00000000,
990};
991
992static const uint32_t GR64_TCW64_and_GR64_TC_with_sub_8bitSubClassMask[] = {
993 0x00000000, 0x00000000, 0x00000000, 0x05982715, 0x00000000,
994};
995
996static const uint32_t VK64WMSubClassMask[] = {
997 0x00000000, 0x00000000, 0x00000000, 0x00000002, 0x00000000,
998 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
999 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
1000};
1001
1002static const uint32_t GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask[] = {
1003 0x00000000, 0x00000000, 0x00000000, 0x01982614, 0x00000000,
1004};
1005
1006static const uint32_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
1007 0x00000000, 0x00000000, 0x00000000, 0x1d8c2728, 0x00000000,
1008};
1009
1010static const uint32_t GR64PLTSafe_and_GR64_TCW64SubClassMask[] = {
1011 0x00000000, 0x00000000, 0x00000000, 0x01882610, 0x00000000,
1012};
1013
1014static const uint32_t GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSubClassMask[] = {
1015 0x00000000, 0x00000000, 0x00000000, 0x198c2620, 0x00000000,
1016};
1017
1018static const uint32_t GR64_NOREX_and_GR64_TCW64SubClassMask[] = {
1019 0x00000000, 0x00000000, 0x00000000, 0x05a82740, 0x00000000,
1020};
1021
1022static const uint32_t GR64_ABCDSubClassMask[] = {
1023 0x00000000, 0x00000000, 0x00000000, 0x01c92680, 0x00000000,
1024};
1025
1026static const uint32_t GR64_with_sub_32bit_in_GR32_TCSubClassMask[] = {
1027 0x00000000, 0x00000000, 0x00000000, 0x05882700, 0x00000000,
1028};
1029
1030static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSubClassMask[] = {
1031 0x00000000, 0x00000000, 0x00000000, 0x01882600, 0x00000000,
1032};
1033
1034static const uint32_t GR64_ADSubClassMask[] = {
1035 0x00000000, 0x00000000, 0x00000000, 0x00880400, 0x00000000,
1036};
1037
1038static const uint32_t GR64_ArgRefSubClassMask[] = {
1039 0x00000000, 0x00000000, 0x00000000, 0x00100800, 0x00000000,
1040};
1041
1042static const uint32_t GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
1043 0x00000000, 0x00000000, 0x00000000, 0x02201000, 0x00000000,
1044};
1045
1046static const uint32_t GR64_with_sub_32bit_in_GR32_ArgRefSubClassMask[] = {
1047 0x00000000, 0x00000000, 0x00000000, 0x01802000, 0x00000000,
1048};
1049
1050static const uint32_t GR64_with_sub_32bit_in_GR32_BPSPSubClassMask[] = {
1051 0x00000000, 0x00000000, 0x00000000, 0x06004000, 0x00000000,
1052};
1053
1054static const uint32_t GR64_with_sub_32bit_in_GR32_BSISubClassMask[] = {
1055 0x00000000, 0x00000000, 0x00000000, 0x08408000, 0x00000000,
1056};
1057
1058static const uint32_t GR64_with_sub_32bit_in_GR32_CBSubClassMask[] = {
1059 0x00000000, 0x00000000, 0x00000000, 0x01410000, 0x00000000,
1060};
1061
1062static const uint32_t GR64_with_sub_32bit_in_GR32_DIBPSubClassMask[] = {
1063 0x00000000, 0x00000000, 0x00000000, 0x12020000, 0x00000000,
1064};
1065
1066static const uint32_t GR64_with_sub_32bit_in_GR32_SIDISubClassMask[] = {
1067 0x00000000, 0x00000000, 0x00000000, 0x18040000, 0x00000000,
1068};
1069
1070static const uint32_t GR64_ASubClassMask[] = {
1071 0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00000000,
1072};
1073
1074static const uint32_t GR64_ArgRef_and_GR64_TCSubClassMask[] = {
1075 0x00000000, 0x00000000, 0x00000000, 0x00100000, 0x00000000,
1076};
1077
1078static const uint32_t GR64_and_LOW32_ADDR_ACCESSSubClassMask[] = {
1079 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00000000,
1080};
1081
1082static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask[] = {
1083 0x00000000, 0x00000000, 0x00000000, 0x00400000, 0x00000000,
1084};
1085
1086static const uint32_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSubClassMask[] = {
1087 0x00000000, 0x00000000, 0x00000000, 0x00800000, 0x00000000,
1088};
1089
1090static const uint32_t GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSubClassMask[] = {
1091 0x00000000, 0x00000000, 0x00000000, 0x01000000, 0x00000000,
1092};
1093
1094static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
1095 0x00000000, 0x00000000, 0x00000000, 0x02000000, 0x00000000,
1096};
1097
1098static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSubClassMask[] = {
1099 0x00000000, 0x00000000, 0x00000000, 0x04000000, 0x00000000,
1100};
1101
1102static const uint32_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask[] = {
1103 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000000,
1104};
1105
1106static const uint32_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask[] = {
1107 0x00000000, 0x00000000, 0x00000000, 0x10000000, 0x00000000,
1108};
1109
1110static const uint32_t RSTSubClassMask[] = {
1111 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000,
1112};
1113
1114static const uint32_t RFP80SubClassMask[] = {
1115 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00000000,
1116};
1117
1118static const uint32_t RFP80_7SubClassMask[] = {
1119 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00000000,
1120};
1121
1122static const uint32_t VR128XSubClassMask[] = {
1123 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000003,
1124 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003c, // sub_xmm
1125};
1126
1127static const uint32_t VR128SubClassMask[] = {
1128 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000002,
1129 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, // sub_xmm
1130};
1131
1132static const uint32_t VR256XSubClassMask[] = {
1133 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000c,
1134 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000030, // sub_ymm
1135};
1136
1137static const uint32_t VR256SubClassMask[] = {
1138 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008,
1139 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000020, // sub_ymm
1140};
1141
1142static const uint32_t VR512SubClassMask[] = {
1143 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000030,
1144};
1145
1146static const uint32_t VR512_0_15SubClassMask[] = {
1147 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000020,
1148};
1149
1150static const uint32_t TILESubClassMask[] = {
1151 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000040,
1152};
1153
1154static const uint16_t SuperRegIdxSeqs[] = {
1155 /* 0 */ 1, 0,
1156 /* 2 */ 1, 2, 0,
1157 /* 5 */ 4, 0,
1158 /* 7 */ 6, 0,
1159 /* 9 */ 7, 8, 0,
1160 /* 12 */ 9, 0,
1161 /* 14 */ 10, 0,
1162};
1163
1164static unsigned const GR8_NOREX2Superclasses[] = {
1165 X86::GR8RegClassID,
1166};
1167
1168static unsigned const GR8_NOREXSuperclasses[] = {
1169 X86::GR8RegClassID,
1170 X86::GR8_NOREX2RegClassID,
1171};
1172
1173static unsigned const GR8_ABCD_HSuperclasses[] = {
1174 X86::GR8RegClassID,
1175 X86::GR8_NOREX2RegClassID,
1176 X86::GR8_NOREXRegClassID,
1177};
1178
1179static unsigned const GR8_ABCD_LSuperclasses[] = {
1180 X86::GR8RegClassID,
1181 X86::GR8_NOREX2RegClassID,
1182 X86::GR8_NOREXRegClassID,
1183};
1184
1185static unsigned const GR16_NOREX2Superclasses[] = {
1186 X86::GR16RegClassID,
1187};
1188
1189static unsigned const GR16_NOREXSuperclasses[] = {
1190 X86::GR16RegClassID,
1191 X86::GR16_NOREX2RegClassID,
1192};
1193
1194static unsigned const VK1Superclasses[] = {
1195 X86::VK16RegClassID,
1196 X86::VK2RegClassID,
1197 X86::VK4RegClassID,
1198 X86::VK8RegClassID,
1199};
1200
1201static unsigned const VK16Superclasses[] = {
1202 X86::VK1RegClassID,
1203 X86::VK2RegClassID,
1204 X86::VK4RegClassID,
1205 X86::VK8RegClassID,
1206};
1207
1208static unsigned const VK2Superclasses[] = {
1209 X86::VK1RegClassID,
1210 X86::VK16RegClassID,
1211 X86::VK4RegClassID,
1212 X86::VK8RegClassID,
1213};
1214
1215static unsigned const VK4Superclasses[] = {
1216 X86::VK1RegClassID,
1217 X86::VK16RegClassID,
1218 X86::VK2RegClassID,
1219 X86::VK8RegClassID,
1220};
1221
1222static unsigned const VK8Superclasses[] = {
1223 X86::VK1RegClassID,
1224 X86::VK16RegClassID,
1225 X86::VK2RegClassID,
1226 X86::VK4RegClassID,
1227};
1228
1229static unsigned const VK16WMSuperclasses[] = {
1230 X86::VK1RegClassID,
1231 X86::VK16RegClassID,
1232 X86::VK2RegClassID,
1233 X86::VK4RegClassID,
1234 X86::VK8RegClassID,
1235 X86::VK1WMRegClassID,
1236 X86::VK2WMRegClassID,
1237 X86::VK4WMRegClassID,
1238 X86::VK8WMRegClassID,
1239};
1240
1241static unsigned const VK1WMSuperclasses[] = {
1242 X86::VK1RegClassID,
1243 X86::VK16RegClassID,
1244 X86::VK2RegClassID,
1245 X86::VK4RegClassID,
1246 X86::VK8RegClassID,
1247 X86::VK16WMRegClassID,
1248 X86::VK2WMRegClassID,
1249 X86::VK4WMRegClassID,
1250 X86::VK8WMRegClassID,
1251};
1252
1253static unsigned const VK2WMSuperclasses[] = {
1254 X86::VK1RegClassID,
1255 X86::VK16RegClassID,
1256 X86::VK2RegClassID,
1257 X86::VK4RegClassID,
1258 X86::VK8RegClassID,
1259 X86::VK16WMRegClassID,
1260 X86::VK1WMRegClassID,
1261 X86::VK4WMRegClassID,
1262 X86::VK8WMRegClassID,
1263};
1264
1265static unsigned const VK4WMSuperclasses[] = {
1266 X86::VK1RegClassID,
1267 X86::VK16RegClassID,
1268 X86::VK2RegClassID,
1269 X86::VK4RegClassID,
1270 X86::VK8RegClassID,
1271 X86::VK16WMRegClassID,
1272 X86::VK1WMRegClassID,
1273 X86::VK2WMRegClassID,
1274 X86::VK8WMRegClassID,
1275};
1276
1277static unsigned const VK8WMSuperclasses[] = {
1278 X86::VK1RegClassID,
1279 X86::VK16RegClassID,
1280 X86::VK2RegClassID,
1281 X86::VK4RegClassID,
1282 X86::VK8RegClassID,
1283 X86::VK16WMRegClassID,
1284 X86::VK1WMRegClassID,
1285 X86::VK2WMRegClassID,
1286 X86::VK4WMRegClassID,
1287};
1288
1289static unsigned const GR16_ABCDSuperclasses[] = {
1290 X86::GR16RegClassID,
1291 X86::GR16_NOREX2RegClassID,
1292 X86::GR16_NOREXRegClassID,
1293};
1294
1295static unsigned const FR16Superclasses[] = {
1296 X86::FR16XRegClassID,
1297};
1298
1299static unsigned const VK16PAIRSuperclasses[] = {
1300 X86::VK1PAIRRegClassID,
1301 X86::VK2PAIRRegClassID,
1302 X86::VK4PAIRRegClassID,
1303 X86::VK8PAIRRegClassID,
1304};
1305
1306static unsigned const VK1PAIRSuperclasses[] = {
1307 X86::VK16PAIRRegClassID,
1308 X86::VK2PAIRRegClassID,
1309 X86::VK4PAIRRegClassID,
1310 X86::VK8PAIRRegClassID,
1311};
1312
1313static unsigned const VK2PAIRSuperclasses[] = {
1314 X86::VK16PAIRRegClassID,
1315 X86::VK1PAIRRegClassID,
1316 X86::VK4PAIRRegClassID,
1317 X86::VK8PAIRRegClassID,
1318};
1319
1320static unsigned const VK4PAIRSuperclasses[] = {
1321 X86::VK16PAIRRegClassID,
1322 X86::VK1PAIRRegClassID,
1323 X86::VK2PAIRRegClassID,
1324 X86::VK8PAIRRegClassID,
1325};
1326
1327static unsigned const VK8PAIRSuperclasses[] = {
1328 X86::VK16PAIRRegClassID,
1329 X86::VK1PAIRRegClassID,
1330 X86::VK2PAIRRegClassID,
1331 X86::VK4PAIRRegClassID,
1332};
1333
1334static unsigned const VK1PAIR_with_sub_mask_0_in_VK1WMSuperclasses[] = {
1335 X86::VK16PAIRRegClassID,
1336 X86::VK1PAIRRegClassID,
1337 X86::VK2PAIRRegClassID,
1338 X86::VK4PAIRRegClassID,
1339 X86::VK8PAIRRegClassID,
1340};
1341
1342static unsigned const LOW32_ADDR_ACCESSSuperclasses[] = {
1343 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1344};
1345
1346static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses[] = {
1347 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1348};
1349
1350static unsigned const FR32XSuperclasses[] = {
1351 X86::FR16XRegClassID,
1352};
1353
1354static unsigned const GR32Superclasses[] = {
1355 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1356 X86::LOW32_ADDR_ACCESSRegClassID,
1357 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1358};
1359
1360static unsigned const GR32_NOSPSuperclasses[] = {
1361 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1362 X86::LOW32_ADDR_ACCESSRegClassID,
1363 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1364 X86::GR32RegClassID,
1365};
1366
1367static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Superclasses[] = {
1368 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1369 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1370};
1371
1372static unsigned const FR32Superclasses[] = {
1373 X86::FR16XRegClassID,
1374 X86::FR16RegClassID,
1375 X86::FR32XRegClassID,
1376};
1377
1378static unsigned const GR32_NOREX2Superclasses[] = {
1379 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1380 X86::LOW32_ADDR_ACCESSRegClassID,
1381 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1382 X86::GR32RegClassID,
1383 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1384};
1385
1386static unsigned const GR32_NOREX2_NOSPSuperclasses[] = {
1387 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1388 X86::LOW32_ADDR_ACCESSRegClassID,
1389 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1390 X86::GR32RegClassID,
1391 X86::GR32_NOSPRegClassID,
1392 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1393 X86::GR32_NOREX2RegClassID,
1394};
1395
1396static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
1397 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1398 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1399 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1400};
1401
1402static unsigned const GR32_NOREXSuperclasses[] = {
1403 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1404 X86::LOW32_ADDR_ACCESSRegClassID,
1405 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1406 X86::GR32RegClassID,
1407 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1408 X86::GR32_NOREX2RegClassID,
1409 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1410};
1411
1412static unsigned const VK32Superclasses[] = {
1413 X86::VK1RegClassID,
1414 X86::VK16RegClassID,
1415 X86::VK2RegClassID,
1416 X86::VK4RegClassID,
1417 X86::VK8RegClassID,
1418};
1419
1420static unsigned const GR32_NOREX_NOSPSuperclasses[] = {
1421 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1422 X86::LOW32_ADDR_ACCESSRegClassID,
1423 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1424 X86::GR32RegClassID,
1425 X86::GR32_NOSPRegClassID,
1426 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1427 X86::GR32_NOREX2RegClassID,
1428 X86::GR32_NOREX2_NOSPRegClassID,
1429 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1430 X86::GR32_NOREXRegClassID,
1431};
1432
1433static unsigned const VK32WMSuperclasses[] = {
1434 X86::VK1RegClassID,
1435 X86::VK16RegClassID,
1436 X86::VK2RegClassID,
1437 X86::VK4RegClassID,
1438 X86::VK8RegClassID,
1439 X86::VK16WMRegClassID,
1440 X86::VK1WMRegClassID,
1441 X86::VK2WMRegClassID,
1442 X86::VK4WMRegClassID,
1443 X86::VK8WMRegClassID,
1444 X86::VK32RegClassID,
1445};
1446
1447static unsigned const GR32_ABCDSuperclasses[] = {
1448 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1449 X86::LOW32_ADDR_ACCESSRegClassID,
1450 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1451 X86::GR32RegClassID,
1452 X86::GR32_NOSPRegClassID,
1453 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1454 X86::GR32_NOREX2RegClassID,
1455 X86::GR32_NOREX2_NOSPRegClassID,
1456 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1457 X86::GR32_NOREXRegClassID,
1458 X86::GR32_NOREX_NOSPRegClassID,
1459};
1460
1461static unsigned const GR32_TCSuperclasses[] = {
1462 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1463 X86::LOW32_ADDR_ACCESSRegClassID,
1464 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1465 X86::GR32RegClassID,
1466 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1467 X86::GR32_NOREX2RegClassID,
1468 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1469 X86::GR32_NOREXRegClassID,
1470};
1471
1472static unsigned const GR32_ABCD_and_GR32_TCSuperclasses[] = {
1473 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1474 X86::LOW32_ADDR_ACCESSRegClassID,
1475 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1476 X86::GR32RegClassID,
1477 X86::GR32_NOSPRegClassID,
1478 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1479 X86::GR32_NOREX2RegClassID,
1480 X86::GR32_NOREX2_NOSPRegClassID,
1481 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1482 X86::GR32_NOREXRegClassID,
1483 X86::GR32_NOREX_NOSPRegClassID,
1484 X86::GR32_ABCDRegClassID,
1485 X86::GR32_TCRegClassID,
1486};
1487
1488static unsigned const GR32_ADSuperclasses[] = {
1489 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1490 X86::LOW32_ADDR_ACCESSRegClassID,
1491 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1492 X86::GR32RegClassID,
1493 X86::GR32_NOSPRegClassID,
1494 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1495 X86::GR32_NOREX2RegClassID,
1496 X86::GR32_NOREX2_NOSPRegClassID,
1497 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1498 X86::GR32_NOREXRegClassID,
1499 X86::GR32_NOREX_NOSPRegClassID,
1500 X86::GR32_ABCDRegClassID,
1501 X86::GR32_TCRegClassID,
1502 X86::GR32_ABCD_and_GR32_TCRegClassID,
1503};
1504
1505static unsigned const GR32_ArgRefSuperclasses[] = {
1506 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1507 X86::LOW32_ADDR_ACCESSRegClassID,
1508 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1509 X86::GR32RegClassID,
1510 X86::GR32_NOSPRegClassID,
1511 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1512 X86::GR32_NOREX2RegClassID,
1513 X86::GR32_NOREX2_NOSPRegClassID,
1514 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1515 X86::GR32_NOREXRegClassID,
1516 X86::GR32_NOREX_NOSPRegClassID,
1517 X86::GR32_ABCDRegClassID,
1518 X86::GR32_TCRegClassID,
1519 X86::GR32_ABCD_and_GR32_TCRegClassID,
1520};
1521
1522static unsigned const GR32_BPSPSuperclasses[] = {
1523 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1524 X86::LOW32_ADDR_ACCESSRegClassID,
1525 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1526 X86::GR32RegClassID,
1527 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1528 X86::GR32_NOREX2RegClassID,
1529 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1530 X86::GR32_NOREXRegClassID,
1531};
1532
1533static unsigned const GR32_BSISuperclasses[] = {
1534 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1535 X86::LOW32_ADDR_ACCESSRegClassID,
1536 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1537 X86::GR32RegClassID,
1538 X86::GR32_NOSPRegClassID,
1539 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1540 X86::GR32_NOREX2RegClassID,
1541 X86::GR32_NOREX2_NOSPRegClassID,
1542 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1543 X86::GR32_NOREXRegClassID,
1544 X86::GR32_NOREX_NOSPRegClassID,
1545};
1546
1547static unsigned const GR32_CBSuperclasses[] = {
1548 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1549 X86::LOW32_ADDR_ACCESSRegClassID,
1550 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1551 X86::GR32RegClassID,
1552 X86::GR32_NOSPRegClassID,
1553 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1554 X86::GR32_NOREX2RegClassID,
1555 X86::GR32_NOREX2_NOSPRegClassID,
1556 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1557 X86::GR32_NOREXRegClassID,
1558 X86::GR32_NOREX_NOSPRegClassID,
1559 X86::GR32_ABCDRegClassID,
1560};
1561
1562static unsigned const GR32_DCSuperclasses[] = {
1563 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1564 X86::LOW32_ADDR_ACCESSRegClassID,
1565 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1566 X86::GR32RegClassID,
1567 X86::GR32_NOSPRegClassID,
1568 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1569 X86::GR32_NOREX2RegClassID,
1570 X86::GR32_NOREX2_NOSPRegClassID,
1571 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1572 X86::GR32_NOREXRegClassID,
1573 X86::GR32_NOREX_NOSPRegClassID,
1574 X86::GR32_ABCDRegClassID,
1575 X86::GR32_TCRegClassID,
1576 X86::GR32_ABCD_and_GR32_TCRegClassID,
1577 X86::GR32_ArgRefRegClassID,
1578};
1579
1580static unsigned const GR32_DIBPSuperclasses[] = {
1581 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1582 X86::LOW32_ADDR_ACCESSRegClassID,
1583 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1584 X86::GR32RegClassID,
1585 X86::GR32_NOSPRegClassID,
1586 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1587 X86::GR32_NOREX2RegClassID,
1588 X86::GR32_NOREX2_NOSPRegClassID,
1589 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1590 X86::GR32_NOREXRegClassID,
1591 X86::GR32_NOREX_NOSPRegClassID,
1592};
1593
1594static unsigned const GR32_SIDISuperclasses[] = {
1595 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1596 X86::LOW32_ADDR_ACCESSRegClassID,
1597 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1598 X86::GR32RegClassID,
1599 X86::GR32_NOSPRegClassID,
1600 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1601 X86::GR32_NOREX2RegClassID,
1602 X86::GR32_NOREX2_NOSPRegClassID,
1603 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1604 X86::GR32_NOREXRegClassID,
1605 X86::GR32_NOREX_NOSPRegClassID,
1606};
1607
1608static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses[] = {
1609 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1610};
1611
1612static unsigned const GR32_ABCD_and_GR32_BSISuperclasses[] = {
1613 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1614 X86::LOW32_ADDR_ACCESSRegClassID,
1615 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1616 X86::GR32RegClassID,
1617 X86::GR32_NOSPRegClassID,
1618 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1619 X86::GR32_NOREX2RegClassID,
1620 X86::GR32_NOREX2_NOSPRegClassID,
1621 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1622 X86::GR32_NOREXRegClassID,
1623 X86::GR32_NOREX_NOSPRegClassID,
1624 X86::GR32_ABCDRegClassID,
1625 X86::GR32_BSIRegClassID,
1626 X86::GR32_CBRegClassID,
1627};
1628
1629static unsigned const GR32_AD_and_GR32_ArgRefSuperclasses[] = {
1630 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1631 X86::LOW32_ADDR_ACCESSRegClassID,
1632 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1633 X86::GR32RegClassID,
1634 X86::GR32_NOSPRegClassID,
1635 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1636 X86::GR32_NOREX2RegClassID,
1637 X86::GR32_NOREX2_NOSPRegClassID,
1638 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1639 X86::GR32_NOREXRegClassID,
1640 X86::GR32_NOREX_NOSPRegClassID,
1641 X86::GR32_ABCDRegClassID,
1642 X86::GR32_TCRegClassID,
1643 X86::GR32_ABCD_and_GR32_TCRegClassID,
1644 X86::GR32_ADRegClassID,
1645 X86::GR32_ArgRefRegClassID,
1646 X86::GR32_DCRegClassID,
1647};
1648
1649static unsigned const GR32_ArgRef_and_GR32_CBSuperclasses[] = {
1650 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1651 X86::LOW32_ADDR_ACCESSRegClassID,
1652 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1653 X86::GR32RegClassID,
1654 X86::GR32_NOSPRegClassID,
1655 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1656 X86::GR32_NOREX2RegClassID,
1657 X86::GR32_NOREX2_NOSPRegClassID,
1658 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1659 X86::GR32_NOREXRegClassID,
1660 X86::GR32_NOREX_NOSPRegClassID,
1661 X86::GR32_ABCDRegClassID,
1662 X86::GR32_TCRegClassID,
1663 X86::GR32_ABCD_and_GR32_TCRegClassID,
1664 X86::GR32_ArgRefRegClassID,
1665 X86::GR32_CBRegClassID,
1666 X86::GR32_DCRegClassID,
1667};
1668
1669static unsigned const GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
1670 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1671 X86::LOW32_ADDR_ACCESSRegClassID,
1672 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1673 X86::GR32RegClassID,
1674 X86::GR32_NOSPRegClassID,
1675 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1676 X86::GR32_NOREX2RegClassID,
1677 X86::GR32_NOREX2_NOSPRegClassID,
1678 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1679 X86::GR32_NOREXRegClassID,
1680 X86::GR32_NOREX_NOSPRegClassID,
1681 X86::GR32_BPSPRegClassID,
1682 X86::GR32_DIBPRegClassID,
1683};
1684
1685static unsigned const GR32_BPSP_and_GR32_TCSuperclasses[] = {
1686 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1687 X86::LOW32_ADDR_ACCESSRegClassID,
1688 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1689 X86::GR32RegClassID,
1690 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1691 X86::GR32_NOREX2RegClassID,
1692 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1693 X86::GR32_NOREXRegClassID,
1694 X86::GR32_TCRegClassID,
1695 X86::GR32_BPSPRegClassID,
1696};
1697
1698static unsigned const GR32_BSI_and_GR32_SIDISuperclasses[] = {
1699 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1700 X86::LOW32_ADDR_ACCESSRegClassID,
1701 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1702 X86::GR32RegClassID,
1703 X86::GR32_NOSPRegClassID,
1704 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1705 X86::GR32_NOREX2RegClassID,
1706 X86::GR32_NOREX2_NOSPRegClassID,
1707 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1708 X86::GR32_NOREXRegClassID,
1709 X86::GR32_NOREX_NOSPRegClassID,
1710 X86::GR32_BSIRegClassID,
1711 X86::GR32_SIDIRegClassID,
1712};
1713
1714static unsigned const GR32_DIBP_and_GR32_SIDISuperclasses[] = {
1715 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1716 X86::LOW32_ADDR_ACCESSRegClassID,
1717 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1718 X86::GR32RegClassID,
1719 X86::GR32_NOSPRegClassID,
1720 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1721 X86::GR32_NOREX2RegClassID,
1722 X86::GR32_NOREX2_NOSPRegClassID,
1723 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1724 X86::GR32_NOREXRegClassID,
1725 X86::GR32_NOREX_NOSPRegClassID,
1726 X86::GR32_DIBPRegClassID,
1727 X86::GR32_SIDIRegClassID,
1728};
1729
1730static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses[] = {
1731 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1732 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
1733 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
1734 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
1735 X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
1736};
1737
1738static unsigned const LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses[] = {
1739 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
1740 X86::LOW32_ADDR_ACCESSRegClassID,
1741 X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
1742};
1743
1744static unsigned const RFP64Superclasses[] = {
1745 X86::RFP32RegClassID,
1746};
1747
1748static unsigned const FR64XSuperclasses[] = {
1749 X86::FR16XRegClassID,
1750 X86::FR32XRegClassID,
1751};
1752
1753static unsigned const GR64_with_sub_8bitSuperclasses[] = {
1754 X86::GR64RegClassID,
1755};
1756
1757static unsigned const GR64_NOSPSuperclasses[] = {
1758 X86::GR64RegClassID,
1759 X86::GR64_with_sub_8bitRegClassID,
1760};
1761
1762static unsigned const GR64_NOREX2Superclasses[] = {
1763 X86::GR64RegClassID,
1764};
1765
1766static unsigned const FR64Superclasses[] = {
1767 X86::FR16XRegClassID,
1768 X86::FR16RegClassID,
1769 X86::FR32XRegClassID,
1770 X86::FR32RegClassID,
1771 X86::FR64XRegClassID,
1772};
1773
1774static unsigned const GR64_with_sub_16bit_in_GR16_NOREX2Superclasses[] = {
1775 X86::GR64RegClassID,
1776 X86::GR64_with_sub_8bitRegClassID,
1777 X86::GR64_NOREX2RegClassID,
1778};
1779
1780static unsigned const GR64_NOREX2_NOSPSuperclasses[] = {
1781 X86::GR64RegClassID,
1782 X86::GR64_with_sub_8bitRegClassID,
1783 X86::GR64_NOSPRegClassID,
1784 X86::GR64_NOREX2RegClassID,
1785 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1786};
1787
1788static unsigned const GR64PLTSafeSuperclasses[] = {
1789 X86::GR64RegClassID,
1790 X86::GR64_with_sub_8bitRegClassID,
1791 X86::GR64_NOSPRegClassID,
1792 X86::GR64_NOREX2RegClassID,
1793 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1794 X86::GR64_NOREX2_NOSPRegClassID,
1795};
1796
1797static unsigned const GR64_TCSuperclasses[] = {
1798 X86::GR64RegClassID,
1799 X86::GR64_NOREX2RegClassID,
1800};
1801
1802static unsigned const GR64_NOREXSuperclasses[] = {
1803 X86::GR64RegClassID,
1804 X86::GR64_NOREX2RegClassID,
1805};
1806
1807static unsigned const GR64_TCW64Superclasses[] = {
1808 X86::GR64RegClassID,
1809 X86::GR64_NOREX2RegClassID,
1810};
1811
1812static unsigned const GR64_TC_with_sub_8bitSuperclasses[] = {
1813 X86::GR64RegClassID,
1814 X86::GR64_with_sub_8bitRegClassID,
1815 X86::GR64_NOREX2RegClassID,
1816 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1817 X86::GR64_TCRegClassID,
1818};
1819
1820static unsigned const GR64_NOREX2_NOSP_and_GR64_TCSuperclasses[] = {
1821 X86::GR64RegClassID,
1822 X86::GR64_with_sub_8bitRegClassID,
1823 X86::GR64_NOSPRegClassID,
1824 X86::GR64_NOREX2RegClassID,
1825 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1826 X86::GR64_NOREX2_NOSPRegClassID,
1827 X86::GR64_TCRegClassID,
1828 X86::GR64_TC_with_sub_8bitRegClassID,
1829};
1830
1831static unsigned const GR64_TCW64_with_sub_8bitSuperclasses[] = {
1832 X86::GR64RegClassID,
1833 X86::GR64_with_sub_8bitRegClassID,
1834 X86::GR64_NOREX2RegClassID,
1835 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1836 X86::GR64_TCW64RegClassID,
1837};
1838
1839static unsigned const GR64_TC_and_GR64_TCW64Superclasses[] = {
1840 X86::GR64RegClassID,
1841 X86::GR64_NOREX2RegClassID,
1842 X86::GR64_TCRegClassID,
1843 X86::GR64_TCW64RegClassID,
1844};
1845
1846static unsigned const GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
1847 X86::GR64RegClassID,
1848 X86::GR64_with_sub_8bitRegClassID,
1849 X86::GR64_NOREX2RegClassID,
1850 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1851 X86::GR64_NOREXRegClassID,
1852};
1853
1854static unsigned const VK64Superclasses[] = {
1855 X86::VK1RegClassID,
1856 X86::VK16RegClassID,
1857 X86::VK2RegClassID,
1858 X86::VK4RegClassID,
1859 X86::VK8RegClassID,
1860 X86::VK32RegClassID,
1861};
1862
1863static unsigned const GR64PLTSafe_and_GR64_TCSuperclasses[] = {
1864 X86::GR64RegClassID,
1865 X86::GR64_with_sub_8bitRegClassID,
1866 X86::GR64_NOSPRegClassID,
1867 X86::GR64_NOREX2RegClassID,
1868 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1869 X86::GR64_NOREX2_NOSPRegClassID,
1870 X86::GR64PLTSafeRegClassID,
1871 X86::GR64_TCRegClassID,
1872 X86::GR64_TC_with_sub_8bitRegClassID,
1873 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
1874};
1875
1876static unsigned const GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses[] = {
1877 X86::GR64RegClassID,
1878 X86::GR64_with_sub_8bitRegClassID,
1879 X86::GR64_NOSPRegClassID,
1880 X86::GR64_NOREX2RegClassID,
1881 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1882 X86::GR64_NOREX2_NOSPRegClassID,
1883 X86::GR64_TCW64RegClassID,
1884 X86::GR64_TCW64_with_sub_8bitRegClassID,
1885};
1886
1887static unsigned const GR64_NOREX_NOSPSuperclasses[] = {
1888 X86::GR64RegClassID,
1889 X86::GR64_with_sub_8bitRegClassID,
1890 X86::GR64_NOSPRegClassID,
1891 X86::GR64_NOREX2RegClassID,
1892 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1893 X86::GR64_NOREX2_NOSPRegClassID,
1894 X86::GR64PLTSafeRegClassID,
1895 X86::GR64_NOREXRegClassID,
1896 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
1897};
1898
1899static unsigned const GR64_NOREX_and_GR64_TCSuperclasses[] = {
1900 X86::GR64RegClassID,
1901 X86::GR64_NOREX2RegClassID,
1902 X86::GR64_TCRegClassID,
1903 X86::GR64_NOREXRegClassID,
1904};
1905
1906static unsigned const GR64_TCW64_and_GR64_TC_with_sub_8bitSuperclasses[] = {
1907 X86::GR64RegClassID,
1908 X86::GR64_with_sub_8bitRegClassID,
1909 X86::GR64_NOREX2RegClassID,
1910 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1911 X86::GR64_TCRegClassID,
1912 X86::GR64_TCW64RegClassID,
1913 X86::GR64_TC_with_sub_8bitRegClassID,
1914 X86::GR64_TCW64_with_sub_8bitRegClassID,
1915 X86::GR64_TC_and_GR64_TCW64RegClassID,
1916};
1917
1918static unsigned const VK64WMSuperclasses[] = {
1919 X86::VK1RegClassID,
1920 X86::VK16RegClassID,
1921 X86::VK2RegClassID,
1922 X86::VK4RegClassID,
1923 X86::VK8RegClassID,
1924 X86::VK16WMRegClassID,
1925 X86::VK1WMRegClassID,
1926 X86::VK2WMRegClassID,
1927 X86::VK4WMRegClassID,
1928 X86::VK8WMRegClassID,
1929 X86::VK32RegClassID,
1930 X86::VK32WMRegClassID,
1931 X86::VK64RegClassID,
1932};
1933
1934static unsigned const GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses[] = {
1935 X86::GR64RegClassID,
1936 X86::GR64_with_sub_8bitRegClassID,
1937 X86::GR64_NOSPRegClassID,
1938 X86::GR64_NOREX2RegClassID,
1939 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1940 X86::GR64_NOREX2_NOSPRegClassID,
1941 X86::GR64_TCRegClassID,
1942 X86::GR64_TCW64RegClassID,
1943 X86::GR64_TC_with_sub_8bitRegClassID,
1944 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
1945 X86::GR64_TCW64_with_sub_8bitRegClassID,
1946 X86::GR64_TC_and_GR64_TCW64RegClassID,
1947 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
1948 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
1949};
1950
1951static unsigned const GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
1952 X86::GR64RegClassID,
1953 X86::GR64_with_sub_8bitRegClassID,
1954 X86::GR64_NOREX2RegClassID,
1955 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1956 X86::GR64_TCRegClassID,
1957 X86::GR64_NOREXRegClassID,
1958 X86::GR64_TC_with_sub_8bitRegClassID,
1959 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
1960 X86::GR64_NOREX_and_GR64_TCRegClassID,
1961};
1962
1963static unsigned const GR64PLTSafe_and_GR64_TCW64Superclasses[] = {
1964 X86::GR64RegClassID,
1965 X86::GR64_with_sub_8bitRegClassID,
1966 X86::GR64_NOSPRegClassID,
1967 X86::GR64_NOREX2RegClassID,
1968 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1969 X86::GR64_NOREX2_NOSPRegClassID,
1970 X86::GR64PLTSafeRegClassID,
1971 X86::GR64_TCRegClassID,
1972 X86::GR64_TCW64RegClassID,
1973 X86::GR64_TC_with_sub_8bitRegClassID,
1974 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
1975 X86::GR64_TCW64_with_sub_8bitRegClassID,
1976 X86::GR64_TC_and_GR64_TCW64RegClassID,
1977 X86::GR64PLTSafe_and_GR64_TCRegClassID,
1978 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
1979 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
1980 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
1981};
1982
1983static unsigned const GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSuperclasses[] = {
1984 X86::GR64RegClassID,
1985 X86::GR64_with_sub_8bitRegClassID,
1986 X86::GR64_NOSPRegClassID,
1987 X86::GR64_NOREX2RegClassID,
1988 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
1989 X86::GR64_NOREX2_NOSPRegClassID,
1990 X86::GR64PLTSafeRegClassID,
1991 X86::GR64_TCRegClassID,
1992 X86::GR64_NOREXRegClassID,
1993 X86::GR64_TC_with_sub_8bitRegClassID,
1994 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
1995 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
1996 X86::GR64PLTSafe_and_GR64_TCRegClassID,
1997 X86::GR64_NOREX_NOSPRegClassID,
1998 X86::GR64_NOREX_and_GR64_TCRegClassID,
1999 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2000};
2001
2002static unsigned const GR64_NOREX_and_GR64_TCW64Superclasses[] = {
2003 X86::GR64RegClassID,
2004 X86::GR64_NOREX2RegClassID,
2005 X86::GR64_TCRegClassID,
2006 X86::GR64_NOREXRegClassID,
2007 X86::GR64_TCW64RegClassID,
2008 X86::GR64_TC_and_GR64_TCW64RegClassID,
2009 X86::GR64_NOREX_and_GR64_TCRegClassID,
2010};
2011
2012static unsigned const GR64_ABCDSuperclasses[] = {
2013 X86::GR64RegClassID,
2014 X86::GR64_with_sub_8bitRegClassID,
2015 X86::GR64_NOSPRegClassID,
2016 X86::GR64_NOREX2RegClassID,
2017 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2018 X86::GR64_NOREX2_NOSPRegClassID,
2019 X86::GR64PLTSafeRegClassID,
2020 X86::GR64_NOREXRegClassID,
2021 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2022 X86::GR64_NOREX_NOSPRegClassID,
2023};
2024
2025static unsigned const GR64_with_sub_32bit_in_GR32_TCSuperclasses[] = {
2026 X86::GR64RegClassID,
2027 X86::GR64_with_sub_8bitRegClassID,
2028 X86::GR64_NOREX2RegClassID,
2029 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2030 X86::GR64_TCRegClassID,
2031 X86::GR64_NOREXRegClassID,
2032 X86::GR64_TCW64RegClassID,
2033 X86::GR64_TC_with_sub_8bitRegClassID,
2034 X86::GR64_TCW64_with_sub_8bitRegClassID,
2035 X86::GR64_TC_and_GR64_TCW64RegClassID,
2036 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2037 X86::GR64_NOREX_and_GR64_TCRegClassID,
2038 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2039 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2040 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2041};
2042
2043static unsigned const GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSuperclasses[] = {
2044 X86::GR64RegClassID,
2045 X86::GR64_with_sub_8bitRegClassID,
2046 X86::GR64_NOSPRegClassID,
2047 X86::GR64_NOREX2RegClassID,
2048 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2049 X86::GR64_NOREX2_NOSPRegClassID,
2050 X86::GR64PLTSafeRegClassID,
2051 X86::GR64_TCRegClassID,
2052 X86::GR64_NOREXRegClassID,
2053 X86::GR64_TCW64RegClassID,
2054 X86::GR64_TC_with_sub_8bitRegClassID,
2055 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2056 X86::GR64_TCW64_with_sub_8bitRegClassID,
2057 X86::GR64_TC_and_GR64_TCW64RegClassID,
2058 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2059 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2060 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2061 X86::GR64_NOREX_NOSPRegClassID,
2062 X86::GR64_NOREX_and_GR64_TCRegClassID,
2063 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2064 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2065 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2066 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
2067 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2068 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2069 X86::GR64_ABCDRegClassID,
2070 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
2071};
2072
2073static unsigned const GR64_ADSuperclasses[] = {
2074 X86::GR64RegClassID,
2075 X86::GR64_with_sub_8bitRegClassID,
2076 X86::GR64_NOSPRegClassID,
2077 X86::GR64_NOREX2RegClassID,
2078 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2079 X86::GR64_NOREX2_NOSPRegClassID,
2080 X86::GR64PLTSafeRegClassID,
2081 X86::GR64_TCRegClassID,
2082 X86::GR64_NOREXRegClassID,
2083 X86::GR64_TCW64RegClassID,
2084 X86::GR64_TC_with_sub_8bitRegClassID,
2085 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2086 X86::GR64_TCW64_with_sub_8bitRegClassID,
2087 X86::GR64_TC_and_GR64_TCW64RegClassID,
2088 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2089 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2090 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2091 X86::GR64_NOREX_NOSPRegClassID,
2092 X86::GR64_NOREX_and_GR64_TCRegClassID,
2093 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2094 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2095 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2096 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
2097 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2098 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2099 X86::GR64_ABCDRegClassID,
2100 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
2101 X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
2102};
2103
2104static unsigned const GR64_ArgRefSuperclasses[] = {
2105 X86::GR64RegClassID,
2106 X86::GR64_with_sub_8bitRegClassID,
2107 X86::GR64_NOSPRegClassID,
2108 X86::GR64_NOREX2RegClassID,
2109 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2110 X86::GR64_NOREX2_NOSPRegClassID,
2111 X86::GR64_TCW64RegClassID,
2112 X86::GR64_TCW64_with_sub_8bitRegClassID,
2113 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2114};
2115
2116static unsigned const GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses[] = {
2117 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
2118 X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
2119 X86::GR64RegClassID,
2120 X86::GR64_NOREX2RegClassID,
2121 X86::GR64_NOREXRegClassID,
2122};
2123
2124static unsigned const GR64_with_sub_32bit_in_GR32_ArgRefSuperclasses[] = {
2125 X86::GR64RegClassID,
2126 X86::GR64_with_sub_8bitRegClassID,
2127 X86::GR64_NOSPRegClassID,
2128 X86::GR64_NOREX2RegClassID,
2129 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2130 X86::GR64_NOREX2_NOSPRegClassID,
2131 X86::GR64PLTSafeRegClassID,
2132 X86::GR64_TCRegClassID,
2133 X86::GR64_NOREXRegClassID,
2134 X86::GR64_TCW64RegClassID,
2135 X86::GR64_TC_with_sub_8bitRegClassID,
2136 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2137 X86::GR64_TCW64_with_sub_8bitRegClassID,
2138 X86::GR64_TC_and_GR64_TCW64RegClassID,
2139 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2140 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2141 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2142 X86::GR64_NOREX_NOSPRegClassID,
2143 X86::GR64_NOREX_and_GR64_TCRegClassID,
2144 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2145 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2146 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2147 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
2148 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2149 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2150 X86::GR64_ABCDRegClassID,
2151 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
2152 X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
2153};
2154
2155static unsigned const GR64_with_sub_32bit_in_GR32_BPSPSuperclasses[] = {
2156 X86::GR64RegClassID,
2157 X86::GR64_with_sub_8bitRegClassID,
2158 X86::GR64_NOREX2RegClassID,
2159 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2160 X86::GR64_NOREXRegClassID,
2161 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2162};
2163
2164static unsigned const GR64_with_sub_32bit_in_GR32_BSISuperclasses[] = {
2165 X86::GR64RegClassID,
2166 X86::GR64_with_sub_8bitRegClassID,
2167 X86::GR64_NOSPRegClassID,
2168 X86::GR64_NOREX2RegClassID,
2169 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2170 X86::GR64_NOREX2_NOSPRegClassID,
2171 X86::GR64PLTSafeRegClassID,
2172 X86::GR64_NOREXRegClassID,
2173 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2174 X86::GR64_NOREX_NOSPRegClassID,
2175};
2176
2177static unsigned const GR64_with_sub_32bit_in_GR32_CBSuperclasses[] = {
2178 X86::GR64RegClassID,
2179 X86::GR64_with_sub_8bitRegClassID,
2180 X86::GR64_NOSPRegClassID,
2181 X86::GR64_NOREX2RegClassID,
2182 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2183 X86::GR64_NOREX2_NOSPRegClassID,
2184 X86::GR64PLTSafeRegClassID,
2185 X86::GR64_NOREXRegClassID,
2186 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2187 X86::GR64_NOREX_NOSPRegClassID,
2188 X86::GR64_ABCDRegClassID,
2189};
2190
2191static unsigned const GR64_with_sub_32bit_in_GR32_DIBPSuperclasses[] = {
2192 X86::GR64RegClassID,
2193 X86::GR64_with_sub_8bitRegClassID,
2194 X86::GR64_NOSPRegClassID,
2195 X86::GR64_NOREX2RegClassID,
2196 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2197 X86::GR64_NOREX2_NOSPRegClassID,
2198 X86::GR64PLTSafeRegClassID,
2199 X86::GR64_NOREXRegClassID,
2200 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2201 X86::GR64_NOREX_NOSPRegClassID,
2202};
2203
2204static unsigned const GR64_with_sub_32bit_in_GR32_SIDISuperclasses[] = {
2205 X86::GR64RegClassID,
2206 X86::GR64_with_sub_8bitRegClassID,
2207 X86::GR64_NOSPRegClassID,
2208 X86::GR64_NOREX2RegClassID,
2209 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2210 X86::GR64_NOREX2_NOSPRegClassID,
2211 X86::GR64PLTSafeRegClassID,
2212 X86::GR64_TCRegClassID,
2213 X86::GR64_NOREXRegClassID,
2214 X86::GR64_TC_with_sub_8bitRegClassID,
2215 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2216 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2217 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2218 X86::GR64_NOREX_NOSPRegClassID,
2219 X86::GR64_NOREX_and_GR64_TCRegClassID,
2220 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2221 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2222};
2223
2224static unsigned const GR64_ASuperclasses[] = {
2225 X86::GR64RegClassID,
2226 X86::GR64_with_sub_8bitRegClassID,
2227 X86::GR64_NOSPRegClassID,
2228 X86::GR64_NOREX2RegClassID,
2229 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2230 X86::GR64_NOREX2_NOSPRegClassID,
2231 X86::GR64PLTSafeRegClassID,
2232 X86::GR64_TCRegClassID,
2233 X86::GR64_NOREXRegClassID,
2234 X86::GR64_TCW64RegClassID,
2235 X86::GR64_TC_with_sub_8bitRegClassID,
2236 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2237 X86::GR64_TCW64_with_sub_8bitRegClassID,
2238 X86::GR64_TC_and_GR64_TCW64RegClassID,
2239 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2240 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2241 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2242 X86::GR64_NOREX_NOSPRegClassID,
2243 X86::GR64_NOREX_and_GR64_TCRegClassID,
2244 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2245 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2246 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2247 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
2248 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2249 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2250 X86::GR64_ABCDRegClassID,
2251 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
2252 X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
2253 X86::GR64_ADRegClassID,
2254};
2255
2256static unsigned const GR64_ArgRef_and_GR64_TCSuperclasses[] = {
2257 X86::GR64RegClassID,
2258 X86::GR64_with_sub_8bitRegClassID,
2259 X86::GR64_NOSPRegClassID,
2260 X86::GR64_NOREX2RegClassID,
2261 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2262 X86::GR64_NOREX2_NOSPRegClassID,
2263 X86::GR64_TCRegClassID,
2264 X86::GR64_TCW64RegClassID,
2265 X86::GR64_TC_with_sub_8bitRegClassID,
2266 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2267 X86::GR64_TCW64_with_sub_8bitRegClassID,
2268 X86::GR64_TC_and_GR64_TCW64RegClassID,
2269 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2270 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2271 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2272 X86::GR64_ArgRefRegClassID,
2273};
2274
2275static unsigned const GR64_and_LOW32_ADDR_ACCESSSuperclasses[] = {
2276 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
2277 X86::LOW32_ADDR_ACCESSRegClassID,
2278 X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
2279 X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClassID,
2280 X86::GR64RegClassID,
2281 X86::GR64_NOREX2RegClassID,
2282 X86::GR64_TCRegClassID,
2283 X86::GR64_NOREXRegClassID,
2284 X86::GR64_TCW64RegClassID,
2285 X86::GR64_TC_and_GR64_TCW64RegClassID,
2286 X86::GR64_NOREX_and_GR64_TCRegClassID,
2287 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2288 X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID,
2289};
2290
2291static unsigned const GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISuperclasses[] = {
2292 X86::GR64RegClassID,
2293 X86::GR64_with_sub_8bitRegClassID,
2294 X86::GR64_NOSPRegClassID,
2295 X86::GR64_NOREX2RegClassID,
2296 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2297 X86::GR64_NOREX2_NOSPRegClassID,
2298 X86::GR64PLTSafeRegClassID,
2299 X86::GR64_NOREXRegClassID,
2300 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2301 X86::GR64_NOREX_NOSPRegClassID,
2302 X86::GR64_ABCDRegClassID,
2303 X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID,
2304 X86::GR64_with_sub_32bit_in_GR32_CBRegClassID,
2305};
2306
2307static unsigned const GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSuperclasses[] = {
2308 X86::GR64RegClassID,
2309 X86::GR64_with_sub_8bitRegClassID,
2310 X86::GR64_NOSPRegClassID,
2311 X86::GR64_NOREX2RegClassID,
2312 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2313 X86::GR64_NOREX2_NOSPRegClassID,
2314 X86::GR64PLTSafeRegClassID,
2315 X86::GR64_TCRegClassID,
2316 X86::GR64_NOREXRegClassID,
2317 X86::GR64_TCW64RegClassID,
2318 X86::GR64_TC_with_sub_8bitRegClassID,
2319 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2320 X86::GR64_TCW64_with_sub_8bitRegClassID,
2321 X86::GR64_TC_and_GR64_TCW64RegClassID,
2322 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2323 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2324 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2325 X86::GR64_NOREX_NOSPRegClassID,
2326 X86::GR64_NOREX_and_GR64_TCRegClassID,
2327 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2328 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2329 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2330 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
2331 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2332 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2333 X86::GR64_ABCDRegClassID,
2334 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
2335 X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
2336 X86::GR64_ADRegClassID,
2337 X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID,
2338};
2339
2340static unsigned const GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSuperclasses[] = {
2341 X86::GR64RegClassID,
2342 X86::GR64_with_sub_8bitRegClassID,
2343 X86::GR64_NOSPRegClassID,
2344 X86::GR64_NOREX2RegClassID,
2345 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2346 X86::GR64_NOREX2_NOSPRegClassID,
2347 X86::GR64PLTSafeRegClassID,
2348 X86::GR64_TCRegClassID,
2349 X86::GR64_NOREXRegClassID,
2350 X86::GR64_TCW64RegClassID,
2351 X86::GR64_TC_with_sub_8bitRegClassID,
2352 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2353 X86::GR64_TCW64_with_sub_8bitRegClassID,
2354 X86::GR64_TC_and_GR64_TCW64RegClassID,
2355 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2356 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2357 X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2358 X86::GR64_NOREX_NOSPRegClassID,
2359 X86::GR64_NOREX_and_GR64_TCRegClassID,
2360 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2361 X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
2362 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2363 X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
2364 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2365 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2366 X86::GR64_ABCDRegClassID,
2367 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
2368 X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
2369 X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID,
2370 X86::GR64_with_sub_32bit_in_GR32_CBRegClassID,
2371};
2372
2373static unsigned const GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
2374 X86::LOW32_ADDR_ACCESS_RBPRegClassID,
2375 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
2376 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
2377 X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
2378 X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
2379 X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID,
2380 X86::GR64RegClassID,
2381 X86::GR64_with_sub_8bitRegClassID,
2382 X86::GR64_NOSPRegClassID,
2383 X86::GR64_NOREX2RegClassID,
2384 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2385 X86::GR64_NOREX2_NOSPRegClassID,
2386 X86::GR64PLTSafeRegClassID,
2387 X86::GR64_NOREXRegClassID,
2388 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2389 X86::GR64_NOREX_NOSPRegClassID,
2390 X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID,
2391 X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID,
2392 X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID,
2393};
2394
2395static unsigned const GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSuperclasses[] = {
2396 X86::GR64RegClassID,
2397 X86::GR64_with_sub_8bitRegClassID,
2398 X86::GR64_NOREX2RegClassID,
2399 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2400 X86::GR64_TCRegClassID,
2401 X86::GR64_NOREXRegClassID,
2402 X86::GR64_TCW64RegClassID,
2403 X86::GR64_TC_with_sub_8bitRegClassID,
2404 X86::GR64_TCW64_with_sub_8bitRegClassID,
2405 X86::GR64_TC_and_GR64_TCW64RegClassID,
2406 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2407 X86::GR64_NOREX_and_GR64_TCRegClassID,
2408 X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
2409 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2410 X86::GR64_NOREX_and_GR64_TCW64RegClassID,
2411 X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
2412 X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID,
2413};
2414
2415static unsigned const GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISuperclasses[] = {
2416 X86::GR64RegClassID,
2417 X86::GR64_with_sub_8bitRegClassID,
2418 X86::GR64_NOSPRegClassID,
2419 X86::GR64_NOREX2RegClassID,
2420 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2421 X86::GR64_NOREX2_NOSPRegClassID,
2422 X86::GR64PLTSafeRegClassID,
2423 X86::GR64_TCRegClassID,
2424 X86::GR64_NOREXRegClassID,
2425 X86::GR64_TC_with_sub_8bitRegClassID,
2426 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2427 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2428 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2429 X86::GR64_NOREX_NOSPRegClassID,
2430 X86::GR64_NOREX_and_GR64_TCRegClassID,
2431 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2432 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2433 X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID,
2434 X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID,
2435};
2436
2437static unsigned const GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISuperclasses[] = {
2438 X86::GR64RegClassID,
2439 X86::GR64_with_sub_8bitRegClassID,
2440 X86::GR64_NOSPRegClassID,
2441 X86::GR64_NOREX2RegClassID,
2442 X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
2443 X86::GR64_NOREX2_NOSPRegClassID,
2444 X86::GR64PLTSafeRegClassID,
2445 X86::GR64_TCRegClassID,
2446 X86::GR64_NOREXRegClassID,
2447 X86::GR64_TC_with_sub_8bitRegClassID,
2448 X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
2449 X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2450 X86::GR64PLTSafe_and_GR64_TCRegClassID,
2451 X86::GR64_NOREX_NOSPRegClassID,
2452 X86::GR64_NOREX_and_GR64_TCRegClassID,
2453 X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
2454 X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
2455 X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID,
2456 X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID,
2457};
2458
2459static unsigned const RFP80Superclasses[] = {
2460 X86::RFP32RegClassID,
2461 X86::RFP64RegClassID,
2462};
2463
2464static unsigned const VR128XSuperclasses[] = {
2465 X86::FR16XRegClassID,
2466 X86::FR32XRegClassID,
2467 X86::FR64XRegClassID,
2468};
2469
2470static unsigned const VR128Superclasses[] = {
2471 X86::FR16XRegClassID,
2472 X86::FR16RegClassID,
2473 X86::FR32XRegClassID,
2474 X86::FR32RegClassID,
2475 X86::FR64XRegClassID,
2476 X86::FR64RegClassID,
2477 X86::VR128XRegClassID,
2478};
2479
2480static unsigned const VR256Superclasses[] = {
2481 X86::VR256XRegClassID,
2482};
2483
2484static unsigned const VR512_0_15Superclasses[] = {
2485 X86::VR512RegClassID,
2486};
2487
2488
2489static inline unsigned GR8AltOrderSelect(const MachineFunction &MF, bool Rev) {
2490 return MF.getSubtarget<X86Subtarget>().is64Bit();
2491 }
2492
2493static ArrayRef<MCPhysReg> GR8GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2494 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R16B, X86::R17B, X86::R18B, X86::R19B, X86::R22B, X86::R23B, X86::R24B, X86::R25B, X86::R26B, X86::R27B, X86::R30B, X86::R31B, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::R20B, X86::R21B, X86::R28B, X86::R29B };
2495 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8RegClassID];
2496 const ArrayRef<MCPhysReg> Order[] = {
2497 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2498 ArrayRef(AltOrder1)
2499 };
2500 const unsigned Select = GR8AltOrderSelect(MF, Rev);
2501 assert(Select < 2);
2502 return Order[Select];
2503}
2504
2505static inline unsigned GR8_NOREX2AltOrderSelect(const MachineFunction &MF, bool Rev) {
2506 return MF.getSubtarget<X86Subtarget>().is64Bit();
2507 }
2508
2509static ArrayRef<MCPhysReg> GR8_NOREX2GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2510 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B };
2511 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8_NOREX2RegClassID];
2512 const ArrayRef<MCPhysReg> Order[] = {
2513 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2514 ArrayRef(AltOrder1)
2515 };
2516 const unsigned Select = GR8_NOREX2AltOrderSelect(MF, Rev);
2517 assert(Select < 2);
2518 return Order[Select];
2519}
2520
2521static inline unsigned GR8_NOREXAltOrderSelect(const MachineFunction &MF, bool Rev) {
2522 return MF.getSubtarget<X86Subtarget>().is64Bit();
2523 }
2524
2525static ArrayRef<MCPhysReg> GR8_NOREXGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2526 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL };
2527 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8_NOREXRegClassID];
2528 const ArrayRef<MCPhysReg> Order[] = {
2529 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2530 ArrayRef(AltOrder1)
2531 };
2532 const unsigned Select = GR8_NOREXAltOrderSelect(MF, Rev);
2533 assert(Select < 2);
2534 return Order[Select];
2535}
2536
2537static inline unsigned FR32XAltOrderSelect(const MachineFunction &MF, bool Rev) {
2538 return Rev;
2539 }
2540
2541static ArrayRef<MCPhysReg> FR32XGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2542 static const MCPhysReg AltOrder1[] = { X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 };
2543 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::FR32XRegClassID];
2544 const ArrayRef<MCPhysReg> Order[] = {
2545 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2546 ArrayRef(AltOrder1)
2547 };
2548 const unsigned Select = FR32XAltOrderSelect(MF, Rev);
2549 assert(Select < 2);
2550 return Order[Select];
2551}
2552
2553static inline unsigned FR64XAltOrderSelect(const MachineFunction &MF, bool Rev) {
2554 return Rev;
2555 }
2556
2557static ArrayRef<MCPhysReg> FR64XGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2558 static const MCPhysReg AltOrder1[] = { X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 };
2559 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::FR64XRegClassID];
2560 const ArrayRef<MCPhysReg> Order[] = {
2561 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2562 ArrayRef(AltOrder1)
2563 };
2564 const unsigned Select = FR64XAltOrderSelect(MF, Rev);
2565 assert(Select < 2);
2566 return Order[Select];
2567}
2568
2569static inline unsigned VR128XAltOrderSelect(const MachineFunction &MF, bool Rev) {
2570 return Rev;
2571 }
2572
2573static ArrayRef<MCPhysReg> VR128XGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2574 static const MCPhysReg AltOrder1[] = { X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 };
2575 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::VR128XRegClassID];
2576 const ArrayRef<MCPhysReg> Order[] = {
2577 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2578 ArrayRef(AltOrder1)
2579 };
2580 const unsigned Select = VR128XAltOrderSelect(MF, Rev);
2581 assert(Select < 2);
2582 return Order[Select];
2583}
2584
2585static inline unsigned VR256XAltOrderSelect(const MachineFunction &MF, bool Rev) {
2586 return Rev;
2587 }
2588
2589static ArrayRef<MCPhysReg> VR256XGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
2590 static const MCPhysReg AltOrder1[] = { X86::YMM16, X86::YMM17, X86::YMM18, X86::YMM19, X86::YMM20, X86::YMM21, X86::YMM22, X86::YMM23, X86::YMM24, X86::YMM25, X86::YMM26, X86::YMM27, X86::YMM28, X86::YMM29, X86::YMM30, X86::YMM31, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15 };
2591 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::VR256XRegClassID];
2592 const ArrayRef<MCPhysReg> Order[] = {
2593 ArrayRef(MCR.begin(), MCR.getNumRegs()),
2594 ArrayRef(AltOrder1)
2595 };
2596 const unsigned Select = VR256XAltOrderSelect(MF, Rev);
2597 assert(Select < 2);
2598 return Order[Select];
2599}
2600namespace X86 {
2601
2602// Register class instances.
2603 extern const TargetRegisterClass GR8RegClass = {
2604 .MC: &X86MCRegisterClasses[GR8RegClassID],
2605 .SubClassMask: GR8SubClassMask,
2606 .SuperRegIndices: SuperRegIdxSeqs + 2,
2607 .LaneMask: LaneBitmask(0x0000000000000001),
2608 .AllocationPriority: 0,
2609 .GlobalPriority: false,
2610 .TSFlags: 0x00, /* TSFlags */
2611 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2612 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2613 .SuperClasses: nullptr, .SuperClassesSize: 0,
2614 .OrderFunc: GR8GetRawAllocationOrder
2615 };
2616
2617 extern const TargetRegisterClass GRH8RegClass = {
2618 .MC: &X86MCRegisterClasses[GRH8RegClassID],
2619 .SubClassMask: GRH8SubClassMask,
2620 .SuperRegIndices: SuperRegIdxSeqs + 1,
2621 .LaneMask: LaneBitmask(0x0000000000000001),
2622 .AllocationPriority: 0,
2623 .GlobalPriority: false,
2624 .TSFlags: 0x00, /* TSFlags */
2625 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2626 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2627 .SuperClasses: nullptr, .SuperClassesSize: 0,
2628 .OrderFunc: nullptr
2629 };
2630
2631 extern const TargetRegisterClass GR8_NOREX2RegClass = {
2632 .MC: &X86MCRegisterClasses[GR8_NOREX2RegClassID],
2633 .SubClassMask: GR8_NOREX2SubClassMask,
2634 .SuperRegIndices: SuperRegIdxSeqs + 2,
2635 .LaneMask: LaneBitmask(0x0000000000000001),
2636 .AllocationPriority: 0,
2637 .GlobalPriority: false,
2638 .TSFlags: 0x00, /* TSFlags */
2639 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2640 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2641 .SuperClasses: GR8_NOREX2Superclasses, .SuperClassesSize: 1,
2642 .OrderFunc: GR8_NOREX2GetRawAllocationOrder
2643 };
2644
2645 extern const TargetRegisterClass GR8_NOREXRegClass = {
2646 .MC: &X86MCRegisterClasses[GR8_NOREXRegClassID],
2647 .SubClassMask: GR8_NOREXSubClassMask,
2648 .SuperRegIndices: SuperRegIdxSeqs + 2,
2649 .LaneMask: LaneBitmask(0x0000000000000001),
2650 .AllocationPriority: 0,
2651 .GlobalPriority: false,
2652 .TSFlags: 0x00, /* TSFlags */
2653 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2654 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2655 .SuperClasses: GR8_NOREXSuperclasses, .SuperClassesSize: 2,
2656 .OrderFunc: GR8_NOREXGetRawAllocationOrder
2657 };
2658
2659 extern const TargetRegisterClass GR8_ABCD_HRegClass = {
2660 .MC: &X86MCRegisterClasses[GR8_ABCD_HRegClassID],
2661 .SubClassMask: GR8_ABCD_HSubClassMask,
2662 .SuperRegIndices: SuperRegIdxSeqs + 3,
2663 .LaneMask: LaneBitmask(0x0000000000000001),
2664 .AllocationPriority: 0,
2665 .GlobalPriority: false,
2666 .TSFlags: 0x00, /* TSFlags */
2667 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2668 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2669 .SuperClasses: GR8_ABCD_HSuperclasses, .SuperClassesSize: 3,
2670 .OrderFunc: nullptr
2671 };
2672
2673 extern const TargetRegisterClass GR8_ABCD_LRegClass = {
2674 .MC: &X86MCRegisterClasses[GR8_ABCD_LRegClassID],
2675 .SubClassMask: GR8_ABCD_LSubClassMask,
2676 .SuperRegIndices: SuperRegIdxSeqs + 0,
2677 .LaneMask: LaneBitmask(0x0000000000000001),
2678 .AllocationPriority: 0,
2679 .GlobalPriority: false,
2680 .TSFlags: 0x00, /* TSFlags */
2681 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2682 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2683 .SuperClasses: GR8_ABCD_LSuperclasses, .SuperClassesSize: 3,
2684 .OrderFunc: nullptr
2685 };
2686
2687 extern const TargetRegisterClass GRH16RegClass = {
2688 .MC: &X86MCRegisterClasses[GRH16RegClassID],
2689 .SubClassMask: GRH16SubClassMask,
2690 .SuperRegIndices: SuperRegIdxSeqs + 1,
2691 .LaneMask: LaneBitmask(0x0000000000000001),
2692 .AllocationPriority: 0,
2693 .GlobalPriority: false,
2694 .TSFlags: 0x00, /* TSFlags */
2695 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2696 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2697 .SuperClasses: nullptr, .SuperClassesSize: 0,
2698 .OrderFunc: nullptr
2699 };
2700
2701 extern const TargetRegisterClass GR16RegClass = {
2702 .MC: &X86MCRegisterClasses[GR16RegClassID],
2703 .SubClassMask: GR16SubClassMask,
2704 .SuperRegIndices: SuperRegIdxSeqs + 5,
2705 .LaneMask: LaneBitmask(0x0000000000000003),
2706 .AllocationPriority: 0,
2707 .GlobalPriority: false,
2708 .TSFlags: 0x00, /* TSFlags */
2709 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2710 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2711 .SuperClasses: nullptr, .SuperClassesSize: 0,
2712 .OrderFunc: nullptr
2713 };
2714
2715 extern const TargetRegisterClass GR16_NOREX2RegClass = {
2716 .MC: &X86MCRegisterClasses[GR16_NOREX2RegClassID],
2717 .SubClassMask: GR16_NOREX2SubClassMask,
2718 .SuperRegIndices: SuperRegIdxSeqs + 5,
2719 .LaneMask: LaneBitmask(0x0000000000000003),
2720 .AllocationPriority: 0,
2721 .GlobalPriority: false,
2722 .TSFlags: 0x00, /* TSFlags */
2723 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2724 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2725 .SuperClasses: GR16_NOREX2Superclasses, .SuperClassesSize: 1,
2726 .OrderFunc: nullptr
2727 };
2728
2729 extern const TargetRegisterClass GR16_NOREXRegClass = {
2730 .MC: &X86MCRegisterClasses[GR16_NOREXRegClassID],
2731 .SubClassMask: GR16_NOREXSubClassMask,
2732 .SuperRegIndices: SuperRegIdxSeqs + 5,
2733 .LaneMask: LaneBitmask(0x0000000000000003),
2734 .AllocationPriority: 0,
2735 .GlobalPriority: false,
2736 .TSFlags: 0x00, /* TSFlags */
2737 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2738 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2739 .SuperClasses: GR16_NOREXSuperclasses, .SuperClassesSize: 2,
2740 .OrderFunc: nullptr
2741 };
2742
2743 extern const TargetRegisterClass VK1RegClass = {
2744 .MC: &X86MCRegisterClasses[VK1RegClassID],
2745 .SubClassMask: VK1SubClassMask,
2746 .SuperRegIndices: SuperRegIdxSeqs + 9,
2747 .LaneMask: LaneBitmask(0x0000000000000001),
2748 .AllocationPriority: 0,
2749 .GlobalPriority: false,
2750 .TSFlags: 0x00, /* TSFlags */
2751 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2752 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2753 .SuperClasses: VK1Superclasses, .SuperClassesSize: 4,
2754 .OrderFunc: nullptr
2755 };
2756
2757 extern const TargetRegisterClass VK16RegClass = {
2758 .MC: &X86MCRegisterClasses[VK16RegClassID],
2759 .SubClassMask: VK16SubClassMask,
2760 .SuperRegIndices: SuperRegIdxSeqs + 9,
2761 .LaneMask: LaneBitmask(0x0000000000000001),
2762 .AllocationPriority: 0,
2763 .GlobalPriority: false,
2764 .TSFlags: 0x00, /* TSFlags */
2765 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2766 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2767 .SuperClasses: VK16Superclasses, .SuperClassesSize: 4,
2768 .OrderFunc: nullptr
2769 };
2770
2771 extern const TargetRegisterClass VK2RegClass = {
2772 .MC: &X86MCRegisterClasses[VK2RegClassID],
2773 .SubClassMask: VK2SubClassMask,
2774 .SuperRegIndices: SuperRegIdxSeqs + 9,
2775 .LaneMask: LaneBitmask(0x0000000000000001),
2776 .AllocationPriority: 0,
2777 .GlobalPriority: false,
2778 .TSFlags: 0x00, /* TSFlags */
2779 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2780 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2781 .SuperClasses: VK2Superclasses, .SuperClassesSize: 4,
2782 .OrderFunc: nullptr
2783 };
2784
2785 extern const TargetRegisterClass VK4RegClass = {
2786 .MC: &X86MCRegisterClasses[VK4RegClassID],
2787 .SubClassMask: VK4SubClassMask,
2788 .SuperRegIndices: SuperRegIdxSeqs + 9,
2789 .LaneMask: LaneBitmask(0x0000000000000001),
2790 .AllocationPriority: 0,
2791 .GlobalPriority: false,
2792 .TSFlags: 0x00, /* TSFlags */
2793 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2794 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2795 .SuperClasses: VK4Superclasses, .SuperClassesSize: 4,
2796 .OrderFunc: nullptr
2797 };
2798
2799 extern const TargetRegisterClass VK8RegClass = {
2800 .MC: &X86MCRegisterClasses[VK8RegClassID],
2801 .SubClassMask: VK8SubClassMask,
2802 .SuperRegIndices: SuperRegIdxSeqs + 9,
2803 .LaneMask: LaneBitmask(0x0000000000000001),
2804 .AllocationPriority: 0,
2805 .GlobalPriority: false,
2806 .TSFlags: 0x00, /* TSFlags */
2807 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2808 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2809 .SuperClasses: VK8Superclasses, .SuperClassesSize: 4,
2810 .OrderFunc: nullptr
2811 };
2812
2813 extern const TargetRegisterClass VK16WMRegClass = {
2814 .MC: &X86MCRegisterClasses[VK16WMRegClassID],
2815 .SubClassMask: VK16WMSubClassMask,
2816 .SuperRegIndices: SuperRegIdxSeqs + 9,
2817 .LaneMask: LaneBitmask(0x0000000000000001),
2818 .AllocationPriority: 0,
2819 .GlobalPriority: false,
2820 .TSFlags: 0x00, /* TSFlags */
2821 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2822 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2823 .SuperClasses: VK16WMSuperclasses, .SuperClassesSize: 9,
2824 .OrderFunc: nullptr
2825 };
2826
2827 extern const TargetRegisterClass VK1WMRegClass = {
2828 .MC: &X86MCRegisterClasses[VK1WMRegClassID],
2829 .SubClassMask: VK1WMSubClassMask,
2830 .SuperRegIndices: SuperRegIdxSeqs + 9,
2831 .LaneMask: LaneBitmask(0x0000000000000001),
2832 .AllocationPriority: 0,
2833 .GlobalPriority: false,
2834 .TSFlags: 0x00, /* TSFlags */
2835 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2836 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2837 .SuperClasses: VK1WMSuperclasses, .SuperClassesSize: 9,
2838 .OrderFunc: nullptr
2839 };
2840
2841 extern const TargetRegisterClass VK2WMRegClass = {
2842 .MC: &X86MCRegisterClasses[VK2WMRegClassID],
2843 .SubClassMask: VK2WMSubClassMask,
2844 .SuperRegIndices: SuperRegIdxSeqs + 9,
2845 .LaneMask: LaneBitmask(0x0000000000000001),
2846 .AllocationPriority: 0,
2847 .GlobalPriority: false,
2848 .TSFlags: 0x00, /* TSFlags */
2849 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2850 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2851 .SuperClasses: VK2WMSuperclasses, .SuperClassesSize: 9,
2852 .OrderFunc: nullptr
2853 };
2854
2855 extern const TargetRegisterClass VK4WMRegClass = {
2856 .MC: &X86MCRegisterClasses[VK4WMRegClassID],
2857 .SubClassMask: VK4WMSubClassMask,
2858 .SuperRegIndices: SuperRegIdxSeqs + 9,
2859 .LaneMask: LaneBitmask(0x0000000000000001),
2860 .AllocationPriority: 0,
2861 .GlobalPriority: false,
2862 .TSFlags: 0x00, /* TSFlags */
2863 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2864 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2865 .SuperClasses: VK4WMSuperclasses, .SuperClassesSize: 9,
2866 .OrderFunc: nullptr
2867 };
2868
2869 extern const TargetRegisterClass VK8WMRegClass = {
2870 .MC: &X86MCRegisterClasses[VK8WMRegClassID],
2871 .SubClassMask: VK8WMSubClassMask,
2872 .SuperRegIndices: SuperRegIdxSeqs + 9,
2873 .LaneMask: LaneBitmask(0x0000000000000001),
2874 .AllocationPriority: 0,
2875 .GlobalPriority: false,
2876 .TSFlags: 0x00, /* TSFlags */
2877 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2878 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2879 .SuperClasses: VK8WMSuperclasses, .SuperClassesSize: 9,
2880 .OrderFunc: nullptr
2881 };
2882
2883 extern const TargetRegisterClass SEGMENT_REGRegClass = {
2884 .MC: &X86MCRegisterClasses[SEGMENT_REGRegClassID],
2885 .SubClassMask: SEGMENT_REGSubClassMask,
2886 .SuperRegIndices: SuperRegIdxSeqs + 1,
2887 .LaneMask: LaneBitmask(0x0000000000000001),
2888 .AllocationPriority: 0,
2889 .GlobalPriority: false,
2890 .TSFlags: 0x00, /* TSFlags */
2891 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2892 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2893 .SuperClasses: nullptr, .SuperClassesSize: 0,
2894 .OrderFunc: nullptr
2895 };
2896
2897 extern const TargetRegisterClass GR16_ABCDRegClass = {
2898 .MC: &X86MCRegisterClasses[GR16_ABCDRegClassID],
2899 .SubClassMask: GR16_ABCDSubClassMask,
2900 .SuperRegIndices: SuperRegIdxSeqs + 5,
2901 .LaneMask: LaneBitmask(0x0000000000000003),
2902 .AllocationPriority: 0,
2903 .GlobalPriority: false,
2904 .TSFlags: 0x00, /* TSFlags */
2905 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2906 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2907 .SuperClasses: GR16_ABCDSuperclasses, .SuperClassesSize: 3,
2908 .OrderFunc: nullptr
2909 };
2910
2911 extern const TargetRegisterClass FPCCRRegClass = {
2912 .MC: &X86MCRegisterClasses[FPCCRRegClassID],
2913 .SubClassMask: FPCCRSubClassMask,
2914 .SuperRegIndices: SuperRegIdxSeqs + 1,
2915 .LaneMask: LaneBitmask(0x0000000000000001),
2916 .AllocationPriority: 0,
2917 .GlobalPriority: false,
2918 .TSFlags: 0x00, /* TSFlags */
2919 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2920 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2921 .SuperClasses: nullptr, .SuperClassesSize: 0,
2922 .OrderFunc: nullptr
2923 };
2924
2925 extern const TargetRegisterClass FR16XRegClass = {
2926 .MC: &X86MCRegisterClasses[FR16XRegClassID],
2927 .SubClassMask: FR16XSubClassMask,
2928 .SuperRegIndices: SuperRegIdxSeqs + 12,
2929 .LaneMask: LaneBitmask(0x0000000000000001),
2930 .AllocationPriority: 0,
2931 .GlobalPriority: false,
2932 .TSFlags: 0x00, /* TSFlags */
2933 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2934 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2935 .SuperClasses: nullptr, .SuperClassesSize: 0,
2936 .OrderFunc: nullptr
2937 };
2938
2939 extern const TargetRegisterClass FR16RegClass = {
2940 .MC: &X86MCRegisterClasses[FR16RegClassID],
2941 .SubClassMask: FR16SubClassMask,
2942 .SuperRegIndices: SuperRegIdxSeqs + 12,
2943 .LaneMask: LaneBitmask(0x0000000000000001),
2944 .AllocationPriority: 0,
2945 .GlobalPriority: false,
2946 .TSFlags: 0x00, /* TSFlags */
2947 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
2948 .CoveredBySubRegs: false, /* CoveredBySubRegs */
2949 .SuperClasses: FR16Superclasses, .SuperClassesSize: 1,
2950 .OrderFunc: nullptr
2951 };
2952
2953 extern const TargetRegisterClass VK16PAIRRegClass = {
2954 .MC: &X86MCRegisterClasses[VK16PAIRRegClassID],
2955 .SubClassMask: VK16PAIRSubClassMask,
2956 .SuperRegIndices: SuperRegIdxSeqs + 1,
2957 .LaneMask: LaneBitmask(0x0000000000000030),
2958 .AllocationPriority: 0,
2959 .GlobalPriority: false,
2960 .TSFlags: 0x00, /* TSFlags */
2961 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2962 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2963 .SuperClasses: VK16PAIRSuperclasses, .SuperClassesSize: 4,
2964 .OrderFunc: nullptr
2965 };
2966
2967 extern const TargetRegisterClass VK1PAIRRegClass = {
2968 .MC: &X86MCRegisterClasses[VK1PAIRRegClassID],
2969 .SubClassMask: VK1PAIRSubClassMask,
2970 .SuperRegIndices: SuperRegIdxSeqs + 1,
2971 .LaneMask: LaneBitmask(0x0000000000000030),
2972 .AllocationPriority: 0,
2973 .GlobalPriority: false,
2974 .TSFlags: 0x00, /* TSFlags */
2975 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2976 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2977 .SuperClasses: VK1PAIRSuperclasses, .SuperClassesSize: 4,
2978 .OrderFunc: nullptr
2979 };
2980
2981 extern const TargetRegisterClass VK2PAIRRegClass = {
2982 .MC: &X86MCRegisterClasses[VK2PAIRRegClassID],
2983 .SubClassMask: VK2PAIRSubClassMask,
2984 .SuperRegIndices: SuperRegIdxSeqs + 1,
2985 .LaneMask: LaneBitmask(0x0000000000000030),
2986 .AllocationPriority: 0,
2987 .GlobalPriority: false,
2988 .TSFlags: 0x00, /* TSFlags */
2989 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2990 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2991 .SuperClasses: VK2PAIRSuperclasses, .SuperClassesSize: 4,
2992 .OrderFunc: nullptr
2993 };
2994
2995 extern const TargetRegisterClass VK4PAIRRegClass = {
2996 .MC: &X86MCRegisterClasses[VK4PAIRRegClassID],
2997 .SubClassMask: VK4PAIRSubClassMask,
2998 .SuperRegIndices: SuperRegIdxSeqs + 1,
2999 .LaneMask: LaneBitmask(0x0000000000000030),
3000 .AllocationPriority: 0,
3001 .GlobalPriority: false,
3002 .TSFlags: 0x00, /* TSFlags */
3003 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3004 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3005 .SuperClasses: VK4PAIRSuperclasses, .SuperClassesSize: 4,
3006 .OrderFunc: nullptr
3007 };
3008
3009 extern const TargetRegisterClass VK8PAIRRegClass = {
3010 .MC: &X86MCRegisterClasses[VK8PAIRRegClassID],
3011 .SubClassMask: VK8PAIRSubClassMask,
3012 .SuperRegIndices: SuperRegIdxSeqs + 1,
3013 .LaneMask: LaneBitmask(0x0000000000000030),
3014 .AllocationPriority: 0,
3015 .GlobalPriority: false,
3016 .TSFlags: 0x00, /* TSFlags */
3017 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3018 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3019 .SuperClasses: VK8PAIRSuperclasses, .SuperClassesSize: 4,
3020 .OrderFunc: nullptr
3021 };
3022
3023 extern const TargetRegisterClass VK1PAIR_with_sub_mask_0_in_VK1WMRegClass = {
3024 .MC: &X86MCRegisterClasses[VK1PAIR_with_sub_mask_0_in_VK1WMRegClassID],
3025 .SubClassMask: VK1PAIR_with_sub_mask_0_in_VK1WMSubClassMask,
3026 .SuperRegIndices: SuperRegIdxSeqs + 1,
3027 .LaneMask: LaneBitmask(0x0000000000000030),
3028 .AllocationPriority: 0,
3029 .GlobalPriority: false,
3030 .TSFlags: 0x00, /* TSFlags */
3031 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3032 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3033 .SuperClasses: VK1PAIR_with_sub_mask_0_in_VK1WMSuperclasses, .SuperClassesSize: 5,
3034 .OrderFunc: nullptr
3035 };
3036
3037 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass = {
3038 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBPRegClassID],
3039 .SubClassMask: LOW32_ADDR_ACCESS_RBPSubClassMask,
3040 .SuperRegIndices: SuperRegIdxSeqs + 7,
3041 .LaneMask: LaneBitmask(0x000000000000000F),
3042 .AllocationPriority: 0,
3043 .GlobalPriority: false,
3044 .TSFlags: 0x00, /* TSFlags */
3045 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3046 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3047 .SuperClasses: nullptr, .SuperClassesSize: 0,
3048 .OrderFunc: nullptr
3049 };
3050
3051 extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass = {
3052 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESSRegClassID],
3053 .SubClassMask: LOW32_ADDR_ACCESSSubClassMask,
3054 .SuperRegIndices: SuperRegIdxSeqs + 7,
3055 .LaneMask: LaneBitmask(0x000000000000000F),
3056 .AllocationPriority: 0,
3057 .GlobalPriority: false,
3058 .TSFlags: 0x00, /* TSFlags */
3059 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3060 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3061 .SuperClasses: LOW32_ADDR_ACCESSSuperclasses, .SuperClassesSize: 1,
3062 .OrderFunc: nullptr
3063 };
3064
3065 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass = {
3066 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID],
3067 .SubClassMask: LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask,
3068 .SuperRegIndices: SuperRegIdxSeqs + 7,
3069 .LaneMask: LaneBitmask(0x000000000000000F),
3070 .AllocationPriority: 0,
3071 .GlobalPriority: false,
3072 .TSFlags: 0x00, /* TSFlags */
3073 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3074 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3075 .SuperClasses: LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses, .SuperClassesSize: 1,
3076 .OrderFunc: nullptr
3077 };
3078
3079 extern const TargetRegisterClass FR32XRegClass = {
3080 .MC: &X86MCRegisterClasses[FR32XRegClassID],
3081 .SubClassMask: FR32XSubClassMask,
3082 .SuperRegIndices: SuperRegIdxSeqs + 12,
3083 .LaneMask: LaneBitmask(0x0000000000000001),
3084 .AllocationPriority: 0,
3085 .GlobalPriority: false,
3086 .TSFlags: 0x00, /* TSFlags */
3087 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3088 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3089 .SuperClasses: FR32XSuperclasses, .SuperClassesSize: 1,
3090 .OrderFunc: FR32XGetRawAllocationOrder
3091 };
3092
3093 extern const TargetRegisterClass GR32RegClass = {
3094 .MC: &X86MCRegisterClasses[GR32RegClassID],
3095 .SubClassMask: GR32SubClassMask,
3096 .SuperRegIndices: SuperRegIdxSeqs + 7,
3097 .LaneMask: LaneBitmask(0x000000000000000F),
3098 .AllocationPriority: 0,
3099 .GlobalPriority: false,
3100 .TSFlags: 0x00, /* TSFlags */
3101 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3102 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3103 .SuperClasses: GR32Superclasses, .SuperClassesSize: 3,
3104 .OrderFunc: nullptr
3105 };
3106
3107 extern const TargetRegisterClass GR32_NOSPRegClass = {
3108 .MC: &X86MCRegisterClasses[GR32_NOSPRegClassID],
3109 .SubClassMask: GR32_NOSPSubClassMask,
3110 .SuperRegIndices: SuperRegIdxSeqs + 7,
3111 .LaneMask: LaneBitmask(0x000000000000000F),
3112 .AllocationPriority: 0,
3113 .GlobalPriority: false,
3114 .TSFlags: 0x00, /* TSFlags */
3115 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3116 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3117 .SuperClasses: GR32_NOSPSuperclasses, .SuperClassesSize: 4,
3118 .OrderFunc: nullptr
3119 };
3120
3121 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass = {
3122 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID],
3123 .SubClassMask: LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2SubClassMask,
3124 .SuperRegIndices: SuperRegIdxSeqs + 7,
3125 .LaneMask: LaneBitmask(0x000000000000000F),
3126 .AllocationPriority: 0,
3127 .GlobalPriority: false,
3128 .TSFlags: 0x00, /* TSFlags */
3129 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3130 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3131 .SuperClasses: LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Superclasses, .SuperClassesSize: 2,
3132 .OrderFunc: nullptr
3133 };
3134
3135 extern const TargetRegisterClass DEBUG_REGRegClass = {
3136 .MC: &X86MCRegisterClasses[DEBUG_REGRegClassID],
3137 .SubClassMask: DEBUG_REGSubClassMask,
3138 .SuperRegIndices: SuperRegIdxSeqs + 1,
3139 .LaneMask: LaneBitmask(0x0000000000000001),
3140 .AllocationPriority: 0,
3141 .GlobalPriority: false,
3142 .TSFlags: 0x00, /* TSFlags */
3143 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3144 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3145 .SuperClasses: nullptr, .SuperClassesSize: 0,
3146 .OrderFunc: nullptr
3147 };
3148
3149 extern const TargetRegisterClass FR32RegClass = {
3150 .MC: &X86MCRegisterClasses[FR32RegClassID],
3151 .SubClassMask: FR32SubClassMask,
3152 .SuperRegIndices: SuperRegIdxSeqs + 12,
3153 .LaneMask: LaneBitmask(0x0000000000000001),
3154 .AllocationPriority: 0,
3155 .GlobalPriority: false,
3156 .TSFlags: 0x00, /* TSFlags */
3157 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3158 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3159 .SuperClasses: FR32Superclasses, .SuperClassesSize: 3,
3160 .OrderFunc: nullptr
3161 };
3162
3163 extern const TargetRegisterClass GR32_NOREX2RegClass = {
3164 .MC: &X86MCRegisterClasses[GR32_NOREX2RegClassID],
3165 .SubClassMask: GR32_NOREX2SubClassMask,
3166 .SuperRegIndices: SuperRegIdxSeqs + 7,
3167 .LaneMask: LaneBitmask(0x000000000000000F),
3168 .AllocationPriority: 0,
3169 .GlobalPriority: false,
3170 .TSFlags: 0x00, /* TSFlags */
3171 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3172 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3173 .SuperClasses: GR32_NOREX2Superclasses, .SuperClassesSize: 5,
3174 .OrderFunc: nullptr
3175 };
3176
3177 extern const TargetRegisterClass GR32_NOREX2_NOSPRegClass = {
3178 .MC: &X86MCRegisterClasses[GR32_NOREX2_NOSPRegClassID],
3179 .SubClassMask: GR32_NOREX2_NOSPSubClassMask,
3180 .SuperRegIndices: SuperRegIdxSeqs + 7,
3181 .LaneMask: LaneBitmask(0x000000000000000F),
3182 .AllocationPriority: 0,
3183 .GlobalPriority: false,
3184 .TSFlags: 0x00, /* TSFlags */
3185 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3186 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3187 .SuperClasses: GR32_NOREX2_NOSPSuperclasses, .SuperClassesSize: 7,
3188 .OrderFunc: nullptr
3189 };
3190
3191 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass = {
3192 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID],
3193 .SubClassMask: LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask,
3194 .SuperRegIndices: SuperRegIdxSeqs + 7,
3195 .LaneMask: LaneBitmask(0x000000000000000F),
3196 .AllocationPriority: 0,
3197 .GlobalPriority: false,
3198 .TSFlags: 0x00, /* TSFlags */
3199 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3200 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3201 .SuperClasses: LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses, .SuperClassesSize: 3,
3202 .OrderFunc: nullptr
3203 };
3204
3205 extern const TargetRegisterClass GR32_NOREXRegClass = {
3206 .MC: &X86MCRegisterClasses[GR32_NOREXRegClassID],
3207 .SubClassMask: GR32_NOREXSubClassMask,
3208 .SuperRegIndices: SuperRegIdxSeqs + 7,
3209 .LaneMask: LaneBitmask(0x000000000000000F),
3210 .AllocationPriority: 0,
3211 .GlobalPriority: false,
3212 .TSFlags: 0x00, /* TSFlags */
3213 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3214 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3215 .SuperClasses: GR32_NOREXSuperclasses, .SuperClassesSize: 7,
3216 .OrderFunc: nullptr
3217 };
3218
3219 extern const TargetRegisterClass VK32RegClass = {
3220 .MC: &X86MCRegisterClasses[VK32RegClassID],
3221 .SubClassMask: VK32SubClassMask,
3222 .SuperRegIndices: SuperRegIdxSeqs + 9,
3223 .LaneMask: LaneBitmask(0x0000000000000001),
3224 .AllocationPriority: 0,
3225 .GlobalPriority: false,
3226 .TSFlags: 0x00, /* TSFlags */
3227 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3228 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3229 .SuperClasses: VK32Superclasses, .SuperClassesSize: 5,
3230 .OrderFunc: nullptr
3231 };
3232
3233 extern const TargetRegisterClass GR32_NOREX_NOSPRegClass = {
3234 .MC: &X86MCRegisterClasses[GR32_NOREX_NOSPRegClassID],
3235 .SubClassMask: GR32_NOREX_NOSPSubClassMask,
3236 .SuperRegIndices: SuperRegIdxSeqs + 7,
3237 .LaneMask: LaneBitmask(0x000000000000000F),
3238 .AllocationPriority: 0,
3239 .GlobalPriority: false,
3240 .TSFlags: 0x00, /* TSFlags */
3241 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3242 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3243 .SuperClasses: GR32_NOREX_NOSPSuperclasses, .SuperClassesSize: 10,
3244 .OrderFunc: nullptr
3245 };
3246
3247 extern const TargetRegisterClass RFP32RegClass = {
3248 .MC: &X86MCRegisterClasses[RFP32RegClassID],
3249 .SubClassMask: RFP32SubClassMask,
3250 .SuperRegIndices: SuperRegIdxSeqs + 1,
3251 .LaneMask: LaneBitmask(0x0000000000000001),
3252 .AllocationPriority: 0,
3253 .GlobalPriority: false,
3254 .TSFlags: 0x00, /* TSFlags */
3255 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3256 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3257 .SuperClasses: nullptr, .SuperClassesSize: 0,
3258 .OrderFunc: nullptr
3259 };
3260
3261 extern const TargetRegisterClass VK32WMRegClass = {
3262 .MC: &X86MCRegisterClasses[VK32WMRegClassID],
3263 .SubClassMask: VK32WMSubClassMask,
3264 .SuperRegIndices: SuperRegIdxSeqs + 9,
3265 .LaneMask: LaneBitmask(0x0000000000000001),
3266 .AllocationPriority: 0,
3267 .GlobalPriority: false,
3268 .TSFlags: 0x00, /* TSFlags */
3269 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3270 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3271 .SuperClasses: VK32WMSuperclasses, .SuperClassesSize: 11,
3272 .OrderFunc: nullptr
3273 };
3274
3275 extern const TargetRegisterClass GR32_ABCDRegClass = {
3276 .MC: &X86MCRegisterClasses[GR32_ABCDRegClassID],
3277 .SubClassMask: GR32_ABCDSubClassMask,
3278 .SuperRegIndices: SuperRegIdxSeqs + 7,
3279 .LaneMask: LaneBitmask(0x000000000000000F),
3280 .AllocationPriority: 0,
3281 .GlobalPriority: false,
3282 .TSFlags: 0x00, /* TSFlags */
3283 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3284 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3285 .SuperClasses: GR32_ABCDSuperclasses, .SuperClassesSize: 11,
3286 .OrderFunc: nullptr
3287 };
3288
3289 extern const TargetRegisterClass GR32_TCRegClass = {
3290 .MC: &X86MCRegisterClasses[GR32_TCRegClassID],
3291 .SubClassMask: GR32_TCSubClassMask,
3292 .SuperRegIndices: SuperRegIdxSeqs + 7,
3293 .LaneMask: LaneBitmask(0x000000000000000F),
3294 .AllocationPriority: 0,
3295 .GlobalPriority: false,
3296 .TSFlags: 0x00, /* TSFlags */
3297 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3298 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3299 .SuperClasses: GR32_TCSuperclasses, .SuperClassesSize: 8,
3300 .OrderFunc: nullptr
3301 };
3302
3303 extern const TargetRegisterClass GR32_ABCD_and_GR32_TCRegClass = {
3304 .MC: &X86MCRegisterClasses[GR32_ABCD_and_GR32_TCRegClassID],
3305 .SubClassMask: GR32_ABCD_and_GR32_TCSubClassMask,
3306 .SuperRegIndices: SuperRegIdxSeqs + 7,
3307 .LaneMask: LaneBitmask(0x000000000000000F),
3308 .AllocationPriority: 0,
3309 .GlobalPriority: false,
3310 .TSFlags: 0x00, /* TSFlags */
3311 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3312 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3313 .SuperClasses: GR32_ABCD_and_GR32_TCSuperclasses, .SuperClassesSize: 13,
3314 .OrderFunc: nullptr
3315 };
3316
3317 extern const TargetRegisterClass GR32_ADRegClass = {
3318 .MC: &X86MCRegisterClasses[GR32_ADRegClassID],
3319 .SubClassMask: GR32_ADSubClassMask,
3320 .SuperRegIndices: SuperRegIdxSeqs + 7,
3321 .LaneMask: LaneBitmask(0x000000000000000F),
3322 .AllocationPriority: 0,
3323 .GlobalPriority: false,
3324 .TSFlags: 0x00, /* TSFlags */
3325 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3326 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3327 .SuperClasses: GR32_ADSuperclasses, .SuperClassesSize: 14,
3328 .OrderFunc: nullptr
3329 };
3330
3331 extern const TargetRegisterClass GR32_ArgRefRegClass = {
3332 .MC: &X86MCRegisterClasses[GR32_ArgRefRegClassID],
3333 .SubClassMask: GR32_ArgRefSubClassMask,
3334 .SuperRegIndices: SuperRegIdxSeqs + 7,
3335 .LaneMask: LaneBitmask(0x000000000000000F),
3336 .AllocationPriority: 0,
3337 .GlobalPriority: false,
3338 .TSFlags: 0x00, /* TSFlags */
3339 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3340 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3341 .SuperClasses: GR32_ArgRefSuperclasses, .SuperClassesSize: 14,
3342 .OrderFunc: nullptr
3343 };
3344
3345 extern const TargetRegisterClass GR32_BPSPRegClass = {
3346 .MC: &X86MCRegisterClasses[GR32_BPSPRegClassID],
3347 .SubClassMask: GR32_BPSPSubClassMask,
3348 .SuperRegIndices: SuperRegIdxSeqs + 7,
3349 .LaneMask: LaneBitmask(0x000000000000000F),
3350 .AllocationPriority: 0,
3351 .GlobalPriority: false,
3352 .TSFlags: 0x00, /* TSFlags */
3353 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3354 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3355 .SuperClasses: GR32_BPSPSuperclasses, .SuperClassesSize: 8,
3356 .OrderFunc: nullptr
3357 };
3358
3359 extern const TargetRegisterClass GR32_BSIRegClass = {
3360 .MC: &X86MCRegisterClasses[GR32_BSIRegClassID],
3361 .SubClassMask: GR32_BSISubClassMask,
3362 .SuperRegIndices: SuperRegIdxSeqs + 7,
3363 .LaneMask: LaneBitmask(0x000000000000000F),
3364 .AllocationPriority: 0,
3365 .GlobalPriority: false,
3366 .TSFlags: 0x00, /* TSFlags */
3367 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3368 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3369 .SuperClasses: GR32_BSISuperclasses, .SuperClassesSize: 11,
3370 .OrderFunc: nullptr
3371 };
3372
3373 extern const TargetRegisterClass GR32_CBRegClass = {
3374 .MC: &X86MCRegisterClasses[GR32_CBRegClassID],
3375 .SubClassMask: GR32_CBSubClassMask,
3376 .SuperRegIndices: SuperRegIdxSeqs + 7,
3377 .LaneMask: LaneBitmask(0x000000000000000F),
3378 .AllocationPriority: 0,
3379 .GlobalPriority: false,
3380 .TSFlags: 0x00, /* TSFlags */
3381 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3382 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3383 .SuperClasses: GR32_CBSuperclasses, .SuperClassesSize: 12,
3384 .OrderFunc: nullptr
3385 };
3386
3387 extern const TargetRegisterClass GR32_DCRegClass = {
3388 .MC: &X86MCRegisterClasses[GR32_DCRegClassID],
3389 .SubClassMask: GR32_DCSubClassMask,
3390 .SuperRegIndices: SuperRegIdxSeqs + 7,
3391 .LaneMask: LaneBitmask(0x000000000000000F),
3392 .AllocationPriority: 0,
3393 .GlobalPriority: false,
3394 .TSFlags: 0x00, /* TSFlags */
3395 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3396 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3397 .SuperClasses: GR32_DCSuperclasses, .SuperClassesSize: 15,
3398 .OrderFunc: nullptr
3399 };
3400
3401 extern const TargetRegisterClass GR32_DIBPRegClass = {
3402 .MC: &X86MCRegisterClasses[GR32_DIBPRegClassID],
3403 .SubClassMask: GR32_DIBPSubClassMask,
3404 .SuperRegIndices: SuperRegIdxSeqs + 7,
3405 .LaneMask: LaneBitmask(0x000000000000000F),
3406 .AllocationPriority: 0,
3407 .GlobalPriority: false,
3408 .TSFlags: 0x00, /* TSFlags */
3409 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3410 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3411 .SuperClasses: GR32_DIBPSuperclasses, .SuperClassesSize: 11,
3412 .OrderFunc: nullptr
3413 };
3414
3415 extern const TargetRegisterClass GR32_SIDIRegClass = {
3416 .MC: &X86MCRegisterClasses[GR32_SIDIRegClassID],
3417 .SubClassMask: GR32_SIDISubClassMask,
3418 .SuperRegIndices: SuperRegIdxSeqs + 7,
3419 .LaneMask: LaneBitmask(0x000000000000000F),
3420 .AllocationPriority: 0,
3421 .GlobalPriority: false,
3422 .TSFlags: 0x00, /* TSFlags */
3423 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3424 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3425 .SuperClasses: GR32_SIDISuperclasses, .SuperClassesSize: 11,
3426 .OrderFunc: nullptr
3427 };
3428
3429 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass = {
3430 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID],
3431 .SubClassMask: LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask,
3432 .SuperRegIndices: SuperRegIdxSeqs + 1,
3433 .LaneMask: LaneBitmask(0x000000000000000F),
3434 .AllocationPriority: 0,
3435 .GlobalPriority: false,
3436 .TSFlags: 0x00, /* TSFlags */
3437 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3438 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3439 .SuperClasses: LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses, .SuperClassesSize: 1,
3440 .OrderFunc: nullptr
3441 };
3442
3443 extern const TargetRegisterClass CCRRegClass = {
3444 .MC: &X86MCRegisterClasses[CCRRegClassID],
3445 .SubClassMask: CCRSubClassMask,
3446 .SuperRegIndices: SuperRegIdxSeqs + 1,
3447 .LaneMask: LaneBitmask(0x0000000000000001),
3448 .AllocationPriority: 0,
3449 .GlobalPriority: false,
3450 .TSFlags: 0x00, /* TSFlags */
3451 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3452 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3453 .SuperClasses: nullptr, .SuperClassesSize: 0,
3454 .OrderFunc: nullptr
3455 };
3456
3457 extern const TargetRegisterClass DFCCRRegClass = {
3458 .MC: &X86MCRegisterClasses[DFCCRRegClassID],
3459 .SubClassMask: DFCCRSubClassMask,
3460 .SuperRegIndices: SuperRegIdxSeqs + 1,
3461 .LaneMask: LaneBitmask(0x0000000000000001),
3462 .AllocationPriority: 0,
3463 .GlobalPriority: false,
3464 .TSFlags: 0x00, /* TSFlags */
3465 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3466 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3467 .SuperClasses: nullptr, .SuperClassesSize: 0,
3468 .OrderFunc: nullptr
3469 };
3470
3471 extern const TargetRegisterClass GR32_ABCD_and_GR32_BSIRegClass = {
3472 .MC: &X86MCRegisterClasses[GR32_ABCD_and_GR32_BSIRegClassID],
3473 .SubClassMask: GR32_ABCD_and_GR32_BSISubClassMask,
3474 .SuperRegIndices: SuperRegIdxSeqs + 7,
3475 .LaneMask: LaneBitmask(0x000000000000000F),
3476 .AllocationPriority: 0,
3477 .GlobalPriority: false,
3478 .TSFlags: 0x00, /* TSFlags */
3479 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3480 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3481 .SuperClasses: GR32_ABCD_and_GR32_BSISuperclasses, .SuperClassesSize: 14,
3482 .OrderFunc: nullptr
3483 };
3484
3485 extern const TargetRegisterClass GR32_AD_and_GR32_ArgRefRegClass = {
3486 .MC: &X86MCRegisterClasses[GR32_AD_and_GR32_ArgRefRegClassID],
3487 .SubClassMask: GR32_AD_and_GR32_ArgRefSubClassMask,
3488 .SuperRegIndices: SuperRegIdxSeqs + 7,
3489 .LaneMask: LaneBitmask(0x000000000000000F),
3490 .AllocationPriority: 0,
3491 .GlobalPriority: false,
3492 .TSFlags: 0x00, /* TSFlags */
3493 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3494 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3495 .SuperClasses: GR32_AD_and_GR32_ArgRefSuperclasses, .SuperClassesSize: 17,
3496 .OrderFunc: nullptr
3497 };
3498
3499 extern const TargetRegisterClass GR32_ArgRef_and_GR32_CBRegClass = {
3500 .MC: &X86MCRegisterClasses[GR32_ArgRef_and_GR32_CBRegClassID],
3501 .SubClassMask: GR32_ArgRef_and_GR32_CBSubClassMask,
3502 .SuperRegIndices: SuperRegIdxSeqs + 7,
3503 .LaneMask: LaneBitmask(0x000000000000000F),
3504 .AllocationPriority: 0,
3505 .GlobalPriority: false,
3506 .TSFlags: 0x00, /* TSFlags */
3507 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3508 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3509 .SuperClasses: GR32_ArgRef_and_GR32_CBSuperclasses, .SuperClassesSize: 17,
3510 .OrderFunc: nullptr
3511 };
3512
3513 extern const TargetRegisterClass GR32_BPSP_and_GR32_DIBPRegClass = {
3514 .MC: &X86MCRegisterClasses[GR32_BPSP_and_GR32_DIBPRegClassID],
3515 .SubClassMask: GR32_BPSP_and_GR32_DIBPSubClassMask,
3516 .SuperRegIndices: SuperRegIdxSeqs + 7,
3517 .LaneMask: LaneBitmask(0x000000000000000F),
3518 .AllocationPriority: 0,
3519 .GlobalPriority: false,
3520 .TSFlags: 0x00, /* TSFlags */
3521 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3522 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3523 .SuperClasses: GR32_BPSP_and_GR32_DIBPSuperclasses, .SuperClassesSize: 13,
3524 .OrderFunc: nullptr
3525 };
3526
3527 extern const TargetRegisterClass GR32_BPSP_and_GR32_TCRegClass = {
3528 .MC: &X86MCRegisterClasses[GR32_BPSP_and_GR32_TCRegClassID],
3529 .SubClassMask: GR32_BPSP_and_GR32_TCSubClassMask,
3530 .SuperRegIndices: SuperRegIdxSeqs + 7,
3531 .LaneMask: LaneBitmask(0x000000000000000F),
3532 .AllocationPriority: 0,
3533 .GlobalPriority: false,
3534 .TSFlags: 0x00, /* TSFlags */
3535 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3536 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3537 .SuperClasses: GR32_BPSP_and_GR32_TCSuperclasses, .SuperClassesSize: 10,
3538 .OrderFunc: nullptr
3539 };
3540
3541 extern const TargetRegisterClass GR32_BSI_and_GR32_SIDIRegClass = {
3542 .MC: &X86MCRegisterClasses[GR32_BSI_and_GR32_SIDIRegClassID],
3543 .SubClassMask: GR32_BSI_and_GR32_SIDISubClassMask,
3544 .SuperRegIndices: SuperRegIdxSeqs + 7,
3545 .LaneMask: LaneBitmask(0x000000000000000F),
3546 .AllocationPriority: 0,
3547 .GlobalPriority: false,
3548 .TSFlags: 0x00, /* TSFlags */
3549 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3550 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3551 .SuperClasses: GR32_BSI_and_GR32_SIDISuperclasses, .SuperClassesSize: 13,
3552 .OrderFunc: nullptr
3553 };
3554
3555 extern const TargetRegisterClass GR32_DIBP_and_GR32_SIDIRegClass = {
3556 .MC: &X86MCRegisterClasses[GR32_DIBP_and_GR32_SIDIRegClassID],
3557 .SubClassMask: GR32_DIBP_and_GR32_SIDISubClassMask,
3558 .SuperRegIndices: SuperRegIdxSeqs + 7,
3559 .LaneMask: LaneBitmask(0x000000000000000F),
3560 .AllocationPriority: 0,
3561 .GlobalPriority: false,
3562 .TSFlags: 0x00, /* TSFlags */
3563 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3564 .CoveredBySubRegs: true, /* CoveredBySubRegs */
3565 .SuperClasses: GR32_DIBP_and_GR32_SIDISuperclasses, .SuperClassesSize: 13,
3566 .OrderFunc: nullptr
3567 };
3568
3569 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass = {
3570 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID],
3571 .SubClassMask: LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask,
3572 .SuperRegIndices: SuperRegIdxSeqs + 1,
3573 .LaneMask: LaneBitmask(0x000000000000000F),
3574 .AllocationPriority: 0,
3575 .GlobalPriority: false,
3576 .TSFlags: 0x00, /* TSFlags */
3577 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3578 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3579 .SuperClasses: LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses, .SuperClassesSize: 5,
3580 .OrderFunc: nullptr
3581 };
3582
3583 extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass = {
3584 .MC: &X86MCRegisterClasses[LOW32_ADDR_ACCESS_with_sub_32bitRegClassID],
3585 .SubClassMask: LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask,
3586 .SuperRegIndices: SuperRegIdxSeqs + 1,
3587 .LaneMask: LaneBitmask(0x000000000000000F),
3588 .AllocationPriority: 0,
3589 .GlobalPriority: false,
3590 .TSFlags: 0x00, /* TSFlags */
3591 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3592 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3593 .SuperClasses: LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses, .SuperClassesSize: 3,
3594 .OrderFunc: nullptr
3595 };
3596
3597 extern const TargetRegisterClass RFP64RegClass = {
3598 .MC: &X86MCRegisterClasses[RFP64RegClassID],
3599 .SubClassMask: RFP64SubClassMask,
3600 .SuperRegIndices: SuperRegIdxSeqs + 1,
3601 .LaneMask: LaneBitmask(0x0000000000000001),
3602 .AllocationPriority: 0,
3603 .GlobalPriority: false,
3604 .TSFlags: 0x00, /* TSFlags */
3605 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3606 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3607 .SuperClasses: RFP64Superclasses, .SuperClassesSize: 1,
3608 .OrderFunc: nullptr
3609 };
3610
3611 extern const TargetRegisterClass GR64RegClass = {
3612 .MC: &X86MCRegisterClasses[GR64RegClassID],
3613 .SubClassMask: GR64SubClassMask,
3614 .SuperRegIndices: SuperRegIdxSeqs + 1,
3615 .LaneMask: LaneBitmask(0x000000000000000F),
3616 .AllocationPriority: 0,
3617 .GlobalPriority: false,
3618 .TSFlags: 0x00, /* TSFlags */
3619 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3620 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3621 .SuperClasses: nullptr, .SuperClassesSize: 0,
3622 .OrderFunc: nullptr
3623 };
3624
3625 extern const TargetRegisterClass FR64XRegClass = {
3626 .MC: &X86MCRegisterClasses[FR64XRegClassID],
3627 .SubClassMask: FR64XSubClassMask,
3628 .SuperRegIndices: SuperRegIdxSeqs + 12,
3629 .LaneMask: LaneBitmask(0x0000000000000001),
3630 .AllocationPriority: 0,
3631 .GlobalPriority: false,
3632 .TSFlags: 0x00, /* TSFlags */
3633 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3634 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3635 .SuperClasses: FR64XSuperclasses, .SuperClassesSize: 2,
3636 .OrderFunc: FR64XGetRawAllocationOrder
3637 };
3638
3639 extern const TargetRegisterClass GR64_with_sub_8bitRegClass = {
3640 .MC: &X86MCRegisterClasses[GR64_with_sub_8bitRegClassID],
3641 .SubClassMask: GR64_with_sub_8bitSubClassMask,
3642 .SuperRegIndices: SuperRegIdxSeqs + 1,
3643 .LaneMask: LaneBitmask(0x000000000000000F),
3644 .AllocationPriority: 0,
3645 .GlobalPriority: false,
3646 .TSFlags: 0x00, /* TSFlags */
3647 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3648 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3649 .SuperClasses: GR64_with_sub_8bitSuperclasses, .SuperClassesSize: 1,
3650 .OrderFunc: nullptr
3651 };
3652
3653 extern const TargetRegisterClass GR64_NOSPRegClass = {
3654 .MC: &X86MCRegisterClasses[GR64_NOSPRegClassID],
3655 .SubClassMask: GR64_NOSPSubClassMask,
3656 .SuperRegIndices: SuperRegIdxSeqs + 1,
3657 .LaneMask: LaneBitmask(0x000000000000000F),
3658 .AllocationPriority: 0,
3659 .GlobalPriority: false,
3660 .TSFlags: 0x00, /* TSFlags */
3661 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3662 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3663 .SuperClasses: GR64_NOSPSuperclasses, .SuperClassesSize: 2,
3664 .OrderFunc: nullptr
3665 };
3666
3667 extern const TargetRegisterClass GR64_NOREX2RegClass = {
3668 .MC: &X86MCRegisterClasses[GR64_NOREX2RegClassID],
3669 .SubClassMask: GR64_NOREX2SubClassMask,
3670 .SuperRegIndices: SuperRegIdxSeqs + 1,
3671 .LaneMask: LaneBitmask(0x000000000000000F),
3672 .AllocationPriority: 0,
3673 .GlobalPriority: false,
3674 .TSFlags: 0x00, /* TSFlags */
3675 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3676 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3677 .SuperClasses: GR64_NOREX2Superclasses, .SuperClassesSize: 1,
3678 .OrderFunc: nullptr
3679 };
3680
3681 extern const TargetRegisterClass CONTROL_REGRegClass = {
3682 .MC: &X86MCRegisterClasses[CONTROL_REGRegClassID],
3683 .SubClassMask: CONTROL_REGSubClassMask,
3684 .SuperRegIndices: SuperRegIdxSeqs + 1,
3685 .LaneMask: LaneBitmask(0x0000000000000001),
3686 .AllocationPriority: 0,
3687 .GlobalPriority: false,
3688 .TSFlags: 0x00, /* TSFlags */
3689 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3690 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3691 .SuperClasses: nullptr, .SuperClassesSize: 0,
3692 .OrderFunc: nullptr
3693 };
3694
3695 extern const TargetRegisterClass FR64RegClass = {
3696 .MC: &X86MCRegisterClasses[FR64RegClassID],
3697 .SubClassMask: FR64SubClassMask,
3698 .SuperRegIndices: SuperRegIdxSeqs + 12,
3699 .LaneMask: LaneBitmask(0x0000000000000001),
3700 .AllocationPriority: 0,
3701 .GlobalPriority: false,
3702 .TSFlags: 0x00, /* TSFlags */
3703 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3704 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3705 .SuperClasses: FR64Superclasses, .SuperClassesSize: 5,
3706 .OrderFunc: nullptr
3707 };
3708
3709 extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREX2RegClass = {
3710 .MC: &X86MCRegisterClasses[GR64_with_sub_16bit_in_GR16_NOREX2RegClassID],
3711 .SubClassMask: GR64_with_sub_16bit_in_GR16_NOREX2SubClassMask,
3712 .SuperRegIndices: SuperRegIdxSeqs + 1,
3713 .LaneMask: LaneBitmask(0x000000000000000F),
3714 .AllocationPriority: 0,
3715 .GlobalPriority: false,
3716 .TSFlags: 0x00, /* TSFlags */
3717 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3718 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3719 .SuperClasses: GR64_with_sub_16bit_in_GR16_NOREX2Superclasses, .SuperClassesSize: 3,
3720 .OrderFunc: nullptr
3721 };
3722
3723 extern const TargetRegisterClass GR64_NOREX2_NOSPRegClass = {
3724 .MC: &X86MCRegisterClasses[GR64_NOREX2_NOSPRegClassID],
3725 .SubClassMask: GR64_NOREX2_NOSPSubClassMask,
3726 .SuperRegIndices: SuperRegIdxSeqs + 1,
3727 .LaneMask: LaneBitmask(0x000000000000000F),
3728 .AllocationPriority: 0,
3729 .GlobalPriority: false,
3730 .TSFlags: 0x00, /* TSFlags */
3731 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3732 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3733 .SuperClasses: GR64_NOREX2_NOSPSuperclasses, .SuperClassesSize: 5,
3734 .OrderFunc: nullptr
3735 };
3736
3737 extern const TargetRegisterClass GR64PLTSafeRegClass = {
3738 .MC: &X86MCRegisterClasses[GR64PLTSafeRegClassID],
3739 .SubClassMask: GR64PLTSafeSubClassMask,
3740 .SuperRegIndices: SuperRegIdxSeqs + 1,
3741 .LaneMask: LaneBitmask(0x000000000000000F),
3742 .AllocationPriority: 0,
3743 .GlobalPriority: false,
3744 .TSFlags: 0x00, /* TSFlags */
3745 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3746 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3747 .SuperClasses: GR64PLTSafeSuperclasses, .SuperClassesSize: 6,
3748 .OrderFunc: nullptr
3749 };
3750
3751 extern const TargetRegisterClass GR64_TCRegClass = {
3752 .MC: &X86MCRegisterClasses[GR64_TCRegClassID],
3753 .SubClassMask: GR64_TCSubClassMask,
3754 .SuperRegIndices: SuperRegIdxSeqs + 1,
3755 .LaneMask: LaneBitmask(0x000000000000000F),
3756 .AllocationPriority: 0,
3757 .GlobalPriority: false,
3758 .TSFlags: 0x00, /* TSFlags */
3759 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3760 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3761 .SuperClasses: GR64_TCSuperclasses, .SuperClassesSize: 2,
3762 .OrderFunc: nullptr
3763 };
3764
3765 extern const TargetRegisterClass GR64_NOREXRegClass = {
3766 .MC: &X86MCRegisterClasses[GR64_NOREXRegClassID],
3767 .SubClassMask: GR64_NOREXSubClassMask,
3768 .SuperRegIndices: SuperRegIdxSeqs + 1,
3769 .LaneMask: LaneBitmask(0x000000000000000F),
3770 .AllocationPriority: 0,
3771 .GlobalPriority: false,
3772 .TSFlags: 0x00, /* TSFlags */
3773 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3774 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3775 .SuperClasses: GR64_NOREXSuperclasses, .SuperClassesSize: 2,
3776 .OrderFunc: nullptr
3777 };
3778
3779 extern const TargetRegisterClass GR64_TCW64RegClass = {
3780 .MC: &X86MCRegisterClasses[GR64_TCW64RegClassID],
3781 .SubClassMask: GR64_TCW64SubClassMask,
3782 .SuperRegIndices: SuperRegIdxSeqs + 1,
3783 .LaneMask: LaneBitmask(0x000000000000000F),
3784 .AllocationPriority: 0,
3785 .GlobalPriority: false,
3786 .TSFlags: 0x00, /* TSFlags */
3787 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3788 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3789 .SuperClasses: GR64_TCW64Superclasses, .SuperClassesSize: 2,
3790 .OrderFunc: nullptr
3791 };
3792
3793 extern const TargetRegisterClass GR64_TC_with_sub_8bitRegClass = {
3794 .MC: &X86MCRegisterClasses[GR64_TC_with_sub_8bitRegClassID],
3795 .SubClassMask: GR64_TC_with_sub_8bitSubClassMask,
3796 .SuperRegIndices: SuperRegIdxSeqs + 1,
3797 .LaneMask: LaneBitmask(0x000000000000000F),
3798 .AllocationPriority: 0,
3799 .GlobalPriority: false,
3800 .TSFlags: 0x00, /* TSFlags */
3801 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3802 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3803 .SuperClasses: GR64_TC_with_sub_8bitSuperclasses, .SuperClassesSize: 5,
3804 .OrderFunc: nullptr
3805 };
3806
3807 extern const TargetRegisterClass GR64_NOREX2_NOSP_and_GR64_TCRegClass = {
3808 .MC: &X86MCRegisterClasses[GR64_NOREX2_NOSP_and_GR64_TCRegClassID],
3809 .SubClassMask: GR64_NOREX2_NOSP_and_GR64_TCSubClassMask,
3810 .SuperRegIndices: SuperRegIdxSeqs + 1,
3811 .LaneMask: LaneBitmask(0x000000000000000F),
3812 .AllocationPriority: 0,
3813 .GlobalPriority: false,
3814 .TSFlags: 0x00, /* TSFlags */
3815 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3816 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3817 .SuperClasses: GR64_NOREX2_NOSP_and_GR64_TCSuperclasses, .SuperClassesSize: 8,
3818 .OrderFunc: nullptr
3819 };
3820
3821 extern const TargetRegisterClass GR64_TCW64_with_sub_8bitRegClass = {
3822 .MC: &X86MCRegisterClasses[GR64_TCW64_with_sub_8bitRegClassID],
3823 .SubClassMask: GR64_TCW64_with_sub_8bitSubClassMask,
3824 .SuperRegIndices: SuperRegIdxSeqs + 1,
3825 .LaneMask: LaneBitmask(0x000000000000000F),
3826 .AllocationPriority: 0,
3827 .GlobalPriority: false,
3828 .TSFlags: 0x00, /* TSFlags */
3829 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3830 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3831 .SuperClasses: GR64_TCW64_with_sub_8bitSuperclasses, .SuperClassesSize: 5,
3832 .OrderFunc: nullptr
3833 };
3834
3835 extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass = {
3836 .MC: &X86MCRegisterClasses[GR64_TC_and_GR64_TCW64RegClassID],
3837 .SubClassMask: GR64_TC_and_GR64_TCW64SubClassMask,
3838 .SuperRegIndices: SuperRegIdxSeqs + 1,
3839 .LaneMask: LaneBitmask(0x000000000000000F),
3840 .AllocationPriority: 0,
3841 .GlobalPriority: false,
3842 .TSFlags: 0x00, /* TSFlags */
3843 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3844 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3845 .SuperClasses: GR64_TC_and_GR64_TCW64Superclasses, .SuperClassesSize: 4,
3846 .OrderFunc: nullptr
3847 };
3848
3849 extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass = {
3850 .MC: &X86MCRegisterClasses[GR64_with_sub_16bit_in_GR16_NOREXRegClassID],
3851 .SubClassMask: GR64_with_sub_16bit_in_GR16_NOREXSubClassMask,
3852 .SuperRegIndices: SuperRegIdxSeqs + 1,
3853 .LaneMask: LaneBitmask(0x000000000000000F),
3854 .AllocationPriority: 0,
3855 .GlobalPriority: false,
3856 .TSFlags: 0x00, /* TSFlags */
3857 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3858 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3859 .SuperClasses: GR64_with_sub_16bit_in_GR16_NOREXSuperclasses, .SuperClassesSize: 5,
3860 .OrderFunc: nullptr
3861 };
3862
3863 extern const TargetRegisterClass VK64RegClass = {
3864 .MC: &X86MCRegisterClasses[VK64RegClassID],
3865 .SubClassMask: VK64SubClassMask,
3866 .SuperRegIndices: SuperRegIdxSeqs + 9,
3867 .LaneMask: LaneBitmask(0x0000000000000001),
3868 .AllocationPriority: 0,
3869 .GlobalPriority: false,
3870 .TSFlags: 0x00, /* TSFlags */
3871 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3872 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3873 .SuperClasses: VK64Superclasses, .SuperClassesSize: 6,
3874 .OrderFunc: nullptr
3875 };
3876
3877 extern const TargetRegisterClass VR64RegClass = {
3878 .MC: &X86MCRegisterClasses[VR64RegClassID],
3879 .SubClassMask: VR64SubClassMask,
3880 .SuperRegIndices: SuperRegIdxSeqs + 1,
3881 .LaneMask: LaneBitmask(0x0000000000000001),
3882 .AllocationPriority: 0,
3883 .GlobalPriority: false,
3884 .TSFlags: 0x00, /* TSFlags */
3885 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3886 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3887 .SuperClasses: nullptr, .SuperClassesSize: 0,
3888 .OrderFunc: nullptr
3889 };
3890
3891 extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCRegClass = {
3892 .MC: &X86MCRegisterClasses[GR64PLTSafe_and_GR64_TCRegClassID],
3893 .SubClassMask: GR64PLTSafe_and_GR64_TCSubClassMask,
3894 .SuperRegIndices: SuperRegIdxSeqs + 1,
3895 .LaneMask: LaneBitmask(0x000000000000000F),
3896 .AllocationPriority: 0,
3897 .GlobalPriority: false,
3898 .TSFlags: 0x00, /* TSFlags */
3899 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3900 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3901 .SuperClasses: GR64PLTSafe_and_GR64_TCSuperclasses, .SuperClassesSize: 10,
3902 .OrderFunc: nullptr
3903 };
3904
3905 extern const TargetRegisterClass GR64_NOREX2_NOSP_and_GR64_TCW64RegClass = {
3906 .MC: &X86MCRegisterClasses[GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID],
3907 .SubClassMask: GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask,
3908 .SuperRegIndices: SuperRegIdxSeqs + 1,
3909 .LaneMask: LaneBitmask(0x000000000000000F),
3910 .AllocationPriority: 0,
3911 .GlobalPriority: false,
3912 .TSFlags: 0x00, /* TSFlags */
3913 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3914 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3915 .SuperClasses: GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses, .SuperClassesSize: 8,
3916 .OrderFunc: nullptr
3917 };
3918
3919 extern const TargetRegisterClass GR64_NOREX_NOSPRegClass = {
3920 .MC: &X86MCRegisterClasses[GR64_NOREX_NOSPRegClassID],
3921 .SubClassMask: GR64_NOREX_NOSPSubClassMask,
3922 .SuperRegIndices: SuperRegIdxSeqs + 1,
3923 .LaneMask: LaneBitmask(0x000000000000000F),
3924 .AllocationPriority: 0,
3925 .GlobalPriority: false,
3926 .TSFlags: 0x00, /* TSFlags */
3927 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3928 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3929 .SuperClasses: GR64_NOREX_NOSPSuperclasses, .SuperClassesSize: 9,
3930 .OrderFunc: nullptr
3931 };
3932
3933 extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass = {
3934 .MC: &X86MCRegisterClasses[GR64_NOREX_and_GR64_TCRegClassID],
3935 .SubClassMask: GR64_NOREX_and_GR64_TCSubClassMask,
3936 .SuperRegIndices: SuperRegIdxSeqs + 1,
3937 .LaneMask: LaneBitmask(0x000000000000000F),
3938 .AllocationPriority: 0,
3939 .GlobalPriority: false,
3940 .TSFlags: 0x00, /* TSFlags */
3941 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3942 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3943 .SuperClasses: GR64_NOREX_and_GR64_TCSuperclasses, .SuperClassesSize: 4,
3944 .OrderFunc: nullptr
3945 };
3946
3947 extern const TargetRegisterClass GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass = {
3948 .MC: &X86MCRegisterClasses[GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID],
3949 .SubClassMask: GR64_TCW64_and_GR64_TC_with_sub_8bitSubClassMask,
3950 .SuperRegIndices: SuperRegIdxSeqs + 1,
3951 .LaneMask: LaneBitmask(0x000000000000000F),
3952 .AllocationPriority: 0,
3953 .GlobalPriority: false,
3954 .TSFlags: 0x00, /* TSFlags */
3955 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3956 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3957 .SuperClasses: GR64_TCW64_and_GR64_TC_with_sub_8bitSuperclasses, .SuperClassesSize: 9,
3958 .OrderFunc: nullptr
3959 };
3960
3961 extern const TargetRegisterClass VK64WMRegClass = {
3962 .MC: &X86MCRegisterClasses[VK64WMRegClassID],
3963 .SubClassMask: VK64WMSubClassMask,
3964 .SuperRegIndices: SuperRegIdxSeqs + 9,
3965 .LaneMask: LaneBitmask(0x0000000000000001),
3966 .AllocationPriority: 0,
3967 .GlobalPriority: false,
3968 .TSFlags: 0x00, /* TSFlags */
3969 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
3970 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3971 .SuperClasses: VK64WMSuperclasses, .SuperClassesSize: 13,
3972 .OrderFunc: nullptr
3973 };
3974
3975 extern const TargetRegisterClass GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClass = {
3976 .MC: &X86MCRegisterClasses[GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID],
3977 .SubClassMask: GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask,
3978 .SuperRegIndices: SuperRegIdxSeqs + 1,
3979 .LaneMask: LaneBitmask(0x000000000000000F),
3980 .AllocationPriority: 0,
3981 .GlobalPriority: false,
3982 .TSFlags: 0x00, /* TSFlags */
3983 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3984 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3985 .SuperClasses: GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses, .SuperClassesSize: 14,
3986 .OrderFunc: nullptr
3987 };
3988
3989 extern const TargetRegisterClass GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass = {
3990 .MC: &X86MCRegisterClasses[GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID],
3991 .SubClassMask: GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSubClassMask,
3992 .SuperRegIndices: SuperRegIdxSeqs + 1,
3993 .LaneMask: LaneBitmask(0x000000000000000F),
3994 .AllocationPriority: 0,
3995 .GlobalPriority: false,
3996 .TSFlags: 0x00, /* TSFlags */
3997 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
3998 .CoveredBySubRegs: false, /* CoveredBySubRegs */
3999 .SuperClasses: GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSuperclasses, .SuperClassesSize: 9,
4000 .OrderFunc: nullptr
4001 };
4002
4003 extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCW64RegClass = {
4004 .MC: &X86MCRegisterClasses[GR64PLTSafe_and_GR64_TCW64RegClassID],
4005 .SubClassMask: GR64PLTSafe_and_GR64_TCW64SubClassMask,
4006 .SuperRegIndices: SuperRegIdxSeqs + 1,
4007 .LaneMask: LaneBitmask(0x000000000000000F),
4008 .AllocationPriority: 0,
4009 .GlobalPriority: false,
4010 .TSFlags: 0x00, /* TSFlags */
4011 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4012 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4013 .SuperClasses: GR64PLTSafe_and_GR64_TCW64Superclasses, .SuperClassesSize: 17,
4014 .OrderFunc: nullptr
4015 };
4016
4017 extern const TargetRegisterClass GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass = {
4018 .MC: &X86MCRegisterClasses[GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID],
4019 .SubClassMask: GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSubClassMask,
4020 .SuperRegIndices: SuperRegIdxSeqs + 1,
4021 .LaneMask: LaneBitmask(0x000000000000000F),
4022 .AllocationPriority: 0,
4023 .GlobalPriority: false,
4024 .TSFlags: 0x00, /* TSFlags */
4025 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4026 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4027 .SuperClasses: GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSuperclasses, .SuperClassesSize: 16,
4028 .OrderFunc: nullptr
4029 };
4030
4031 extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass = {
4032 .MC: &X86MCRegisterClasses[GR64_NOREX_and_GR64_TCW64RegClassID],
4033 .SubClassMask: GR64_NOREX_and_GR64_TCW64SubClassMask,
4034 .SuperRegIndices: SuperRegIdxSeqs + 1,
4035 .LaneMask: LaneBitmask(0x000000000000000F),
4036 .AllocationPriority: 0,
4037 .GlobalPriority: false,
4038 .TSFlags: 0x00, /* TSFlags */
4039 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4040 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4041 .SuperClasses: GR64_NOREX_and_GR64_TCW64Superclasses, .SuperClassesSize: 7,
4042 .OrderFunc: nullptr
4043 };
4044
4045 extern const TargetRegisterClass GR64_ABCDRegClass = {
4046 .MC: &X86MCRegisterClasses[GR64_ABCDRegClassID],
4047 .SubClassMask: GR64_ABCDSubClassMask,
4048 .SuperRegIndices: SuperRegIdxSeqs + 1,
4049 .LaneMask: LaneBitmask(0x000000000000000F),
4050 .AllocationPriority: 0,
4051 .GlobalPriority: false,
4052 .TSFlags: 0x00, /* TSFlags */
4053 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4054 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4055 .SuperClasses: GR64_ABCDSuperclasses, .SuperClassesSize: 10,
4056 .OrderFunc: nullptr
4057 };
4058
4059 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass = {
4060 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_TCRegClassID],
4061 .SubClassMask: GR64_with_sub_32bit_in_GR32_TCSubClassMask,
4062 .SuperRegIndices: SuperRegIdxSeqs + 1,
4063 .LaneMask: LaneBitmask(0x000000000000000F),
4064 .AllocationPriority: 0,
4065 .GlobalPriority: false,
4066 .TSFlags: 0x00, /* TSFlags */
4067 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4068 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4069 .SuperClasses: GR64_with_sub_32bit_in_GR32_TCSuperclasses, .SuperClassesSize: 15,
4070 .OrderFunc: nullptr
4071 };
4072
4073 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass = {
4074 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID],
4075 .SubClassMask: GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSubClassMask,
4076 .SuperRegIndices: SuperRegIdxSeqs + 1,
4077 .LaneMask: LaneBitmask(0x000000000000000F),
4078 .AllocationPriority: 0,
4079 .GlobalPriority: false,
4080 .TSFlags: 0x00, /* TSFlags */
4081 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4082 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4083 .SuperClasses: GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSuperclasses, .SuperClassesSize: 27,
4084 .OrderFunc: nullptr
4085 };
4086
4087 extern const TargetRegisterClass GR64_ADRegClass = {
4088 .MC: &X86MCRegisterClasses[GR64_ADRegClassID],
4089 .SubClassMask: GR64_ADSubClassMask,
4090 .SuperRegIndices: SuperRegIdxSeqs + 1,
4091 .LaneMask: LaneBitmask(0x000000000000000F),
4092 .AllocationPriority: 0,
4093 .GlobalPriority: false,
4094 .TSFlags: 0x00, /* TSFlags */
4095 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4096 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4097 .SuperClasses: GR64_ADSuperclasses, .SuperClassesSize: 28,
4098 .OrderFunc: nullptr
4099 };
4100
4101 extern const TargetRegisterClass GR64_ArgRefRegClass = {
4102 .MC: &X86MCRegisterClasses[GR64_ArgRefRegClassID],
4103 .SubClassMask: GR64_ArgRefSubClassMask,
4104 .SuperRegIndices: SuperRegIdxSeqs + 1,
4105 .LaneMask: LaneBitmask(0x000000000000000F),
4106 .AllocationPriority: 0,
4107 .GlobalPriority: false,
4108 .TSFlags: 0x00, /* TSFlags */
4109 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4110 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4111 .SuperClasses: GR64_ArgRefSuperclasses, .SuperClassesSize: 9,
4112 .OrderFunc: nullptr
4113 };
4114
4115 extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass = {
4116 .MC: &X86MCRegisterClasses[GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID],
4117 .SubClassMask: GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask,
4118 .SuperRegIndices: SuperRegIdxSeqs + 1,
4119 .LaneMask: LaneBitmask(0x000000000000000F),
4120 .AllocationPriority: 0,
4121 .GlobalPriority: false,
4122 .TSFlags: 0x00, /* TSFlags */
4123 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4124 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4125 .SuperClasses: GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses, .SuperClassesSize: 5,
4126 .OrderFunc: nullptr
4127 };
4128
4129 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ArgRefRegClass = {
4130 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ArgRefRegClassID],
4131 .SubClassMask: GR64_with_sub_32bit_in_GR32_ArgRefSubClassMask,
4132 .SuperRegIndices: SuperRegIdxSeqs + 1,
4133 .LaneMask: LaneBitmask(0x000000000000000F),
4134 .AllocationPriority: 0,
4135 .GlobalPriority: false,
4136 .TSFlags: 0x00, /* TSFlags */
4137 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4138 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4139 .SuperClasses: GR64_with_sub_32bit_in_GR32_ArgRefSuperclasses, .SuperClassesSize: 28,
4140 .OrderFunc: nullptr
4141 };
4142
4143 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSPRegClass = {
4144 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSPRegClassID],
4145 .SubClassMask: GR64_with_sub_32bit_in_GR32_BPSPSubClassMask,
4146 .SuperRegIndices: SuperRegIdxSeqs + 1,
4147 .LaneMask: LaneBitmask(0x000000000000000F),
4148 .AllocationPriority: 0,
4149 .GlobalPriority: false,
4150 .TSFlags: 0x00, /* TSFlags */
4151 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4152 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4153 .SuperClasses: GR64_with_sub_32bit_in_GR32_BPSPSuperclasses, .SuperClassesSize: 6,
4154 .OrderFunc: nullptr
4155 };
4156
4157 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSIRegClass = {
4158 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BSIRegClassID],
4159 .SubClassMask: GR64_with_sub_32bit_in_GR32_BSISubClassMask,
4160 .SuperRegIndices: SuperRegIdxSeqs + 1,
4161 .LaneMask: LaneBitmask(0x000000000000000F),
4162 .AllocationPriority: 0,
4163 .GlobalPriority: false,
4164 .TSFlags: 0x00, /* TSFlags */
4165 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4166 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4167 .SuperClasses: GR64_with_sub_32bit_in_GR32_BSISuperclasses, .SuperClassesSize: 10,
4168 .OrderFunc: nullptr
4169 };
4170
4171 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CBRegClass = {
4172 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_CBRegClassID],
4173 .SubClassMask: GR64_with_sub_32bit_in_GR32_CBSubClassMask,
4174 .SuperRegIndices: SuperRegIdxSeqs + 1,
4175 .LaneMask: LaneBitmask(0x000000000000000F),
4176 .AllocationPriority: 0,
4177 .GlobalPriority: false,
4178 .TSFlags: 0x00, /* TSFlags */
4179 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4180 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4181 .SuperClasses: GR64_with_sub_32bit_in_GR32_CBSuperclasses, .SuperClassesSize: 11,
4182 .OrderFunc: nullptr
4183 };
4184
4185 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBPRegClass = {
4186 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DIBPRegClassID],
4187 .SubClassMask: GR64_with_sub_32bit_in_GR32_DIBPSubClassMask,
4188 .SuperRegIndices: SuperRegIdxSeqs + 1,
4189 .LaneMask: LaneBitmask(0x000000000000000F),
4190 .AllocationPriority: 0,
4191 .GlobalPriority: false,
4192 .TSFlags: 0x00, /* TSFlags */
4193 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4194 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4195 .SuperClasses: GR64_with_sub_32bit_in_GR32_DIBPSuperclasses, .SuperClassesSize: 10,
4196 .OrderFunc: nullptr
4197 };
4198
4199 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_SIDIRegClass = {
4200 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_SIDIRegClassID],
4201 .SubClassMask: GR64_with_sub_32bit_in_GR32_SIDISubClassMask,
4202 .SuperRegIndices: SuperRegIdxSeqs + 1,
4203 .LaneMask: LaneBitmask(0x000000000000000F),
4204 .AllocationPriority: 0,
4205 .GlobalPriority: false,
4206 .TSFlags: 0x00, /* TSFlags */
4207 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4208 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4209 .SuperClasses: GR64_with_sub_32bit_in_GR32_SIDISuperclasses, .SuperClassesSize: 17,
4210 .OrderFunc: nullptr
4211 };
4212
4213 extern const TargetRegisterClass GR64_ARegClass = {
4214 .MC: &X86MCRegisterClasses[GR64_ARegClassID],
4215 .SubClassMask: GR64_ASubClassMask,
4216 .SuperRegIndices: SuperRegIdxSeqs + 1,
4217 .LaneMask: LaneBitmask(0x000000000000000F),
4218 .AllocationPriority: 0,
4219 .GlobalPriority: false,
4220 .TSFlags: 0x00, /* TSFlags */
4221 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4222 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4223 .SuperClasses: GR64_ASuperclasses, .SuperClassesSize: 29,
4224 .OrderFunc: nullptr
4225 };
4226
4227 extern const TargetRegisterClass GR64_ArgRef_and_GR64_TCRegClass = {
4228 .MC: &X86MCRegisterClasses[GR64_ArgRef_and_GR64_TCRegClassID],
4229 .SubClassMask: GR64_ArgRef_and_GR64_TCSubClassMask,
4230 .SuperRegIndices: SuperRegIdxSeqs + 1,
4231 .LaneMask: LaneBitmask(0x000000000000000F),
4232 .AllocationPriority: 0,
4233 .GlobalPriority: false,
4234 .TSFlags: 0x00, /* TSFlags */
4235 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4236 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4237 .SuperClasses: GR64_ArgRef_and_GR64_TCSuperclasses, .SuperClassesSize: 16,
4238 .OrderFunc: nullptr
4239 };
4240
4241 extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass = {
4242 .MC: &X86MCRegisterClasses[GR64_and_LOW32_ADDR_ACCESSRegClassID],
4243 .SubClassMask: GR64_and_LOW32_ADDR_ACCESSSubClassMask,
4244 .SuperRegIndices: SuperRegIdxSeqs + 1,
4245 .LaneMask: LaneBitmask(0x000000000000000F),
4246 .AllocationPriority: 0,
4247 .GlobalPriority: false,
4248 .TSFlags: 0x00, /* TSFlags */
4249 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4250 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4251 .SuperClasses: GR64_and_LOW32_ADDR_ACCESSSuperclasses, .SuperClassesSize: 13,
4252 .OrderFunc: nullptr
4253 };
4254
4255 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass = {
4256 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID],
4257 .SubClassMask: GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask,
4258 .SuperRegIndices: SuperRegIdxSeqs + 1,
4259 .LaneMask: LaneBitmask(0x000000000000000F),
4260 .AllocationPriority: 0,
4261 .GlobalPriority: false,
4262 .TSFlags: 0x00, /* TSFlags */
4263 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4264 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4265 .SuperClasses: GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISuperclasses, .SuperClassesSize: 13,
4266 .OrderFunc: nullptr
4267 };
4268
4269 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClass = {
4270 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID],
4271 .SubClassMask: GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSubClassMask,
4272 .SuperRegIndices: SuperRegIdxSeqs + 1,
4273 .LaneMask: LaneBitmask(0x000000000000000F),
4274 .AllocationPriority: 0,
4275 .GlobalPriority: false,
4276 .TSFlags: 0x00, /* TSFlags */
4277 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4278 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4279 .SuperClasses: GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSuperclasses, .SuperClassesSize: 30,
4280 .OrderFunc: nullptr
4281 };
4282
4283 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClass = {
4284 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID],
4285 .SubClassMask: GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSubClassMask,
4286 .SuperRegIndices: SuperRegIdxSeqs + 1,
4287 .LaneMask: LaneBitmask(0x000000000000000F),
4288 .AllocationPriority: 0,
4289 .GlobalPriority: false,
4290 .TSFlags: 0x00, /* TSFlags */
4291 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4292 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4293 .SuperClasses: GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSuperclasses, .SuperClassesSize: 30,
4294 .OrderFunc: nullptr
4295 };
4296
4297 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass = {
4298 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID],
4299 .SubClassMask: GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask,
4300 .SuperRegIndices: SuperRegIdxSeqs + 1,
4301 .LaneMask: LaneBitmask(0x000000000000000F),
4302 .AllocationPriority: 0,
4303 .GlobalPriority: false,
4304 .TSFlags: 0x00, /* TSFlags */
4305 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4306 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4307 .SuperClasses: GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSuperclasses, .SuperClassesSize: 19,
4308 .OrderFunc: nullptr
4309 };
4310
4311 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass = {
4312 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID],
4313 .SubClassMask: GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSubClassMask,
4314 .SuperRegIndices: SuperRegIdxSeqs + 1,
4315 .LaneMask: LaneBitmask(0x000000000000000F),
4316 .AllocationPriority: 0,
4317 .GlobalPriority: false,
4318 .TSFlags: 0x00, /* TSFlags */
4319 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4320 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4321 .SuperClasses: GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSuperclasses, .SuperClassesSize: 17,
4322 .OrderFunc: nullptr
4323 };
4324
4325 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass = {
4326 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID],
4327 .SubClassMask: GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask,
4328 .SuperRegIndices: SuperRegIdxSeqs + 1,
4329 .LaneMask: LaneBitmask(0x000000000000000F),
4330 .AllocationPriority: 0,
4331 .GlobalPriority: false,
4332 .TSFlags: 0x00, /* TSFlags */
4333 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4334 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4335 .SuperClasses: GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISuperclasses, .SuperClassesSize: 19,
4336 .OrderFunc: nullptr
4337 };
4338
4339 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass = {
4340 .MC: &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID],
4341 .SubClassMask: GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask,
4342 .SuperRegIndices: SuperRegIdxSeqs + 1,
4343 .LaneMask: LaneBitmask(0x000000000000000F),
4344 .AllocationPriority: 0,
4345 .GlobalPriority: false,
4346 .TSFlags: 0x00, /* TSFlags */
4347 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
4348 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4349 .SuperClasses: GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISuperclasses, .SuperClassesSize: 19,
4350 .OrderFunc: nullptr
4351 };
4352
4353 extern const TargetRegisterClass RSTRegClass = {
4354 .MC: &X86MCRegisterClasses[RSTRegClassID],
4355 .SubClassMask: RSTSubClassMask,
4356 .SuperRegIndices: SuperRegIdxSeqs + 1,
4357 .LaneMask: LaneBitmask(0x0000000000000001),
4358 .AllocationPriority: 0,
4359 .GlobalPriority: false,
4360 .TSFlags: 0x00, /* TSFlags */
4361 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4362 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4363 .SuperClasses: nullptr, .SuperClassesSize: 0,
4364 .OrderFunc: nullptr
4365 };
4366
4367 extern const TargetRegisterClass RFP80RegClass = {
4368 .MC: &X86MCRegisterClasses[RFP80RegClassID],
4369 .SubClassMask: RFP80SubClassMask,
4370 .SuperRegIndices: SuperRegIdxSeqs + 1,
4371 .LaneMask: LaneBitmask(0x0000000000000001),
4372 .AllocationPriority: 0,
4373 .GlobalPriority: false,
4374 .TSFlags: 0x00, /* TSFlags */
4375 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4376 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4377 .SuperClasses: RFP80Superclasses, .SuperClassesSize: 2,
4378 .OrderFunc: nullptr
4379 };
4380
4381 extern const TargetRegisterClass RFP80_7RegClass = {
4382 .MC: &X86MCRegisterClasses[RFP80_7RegClassID],
4383 .SubClassMask: RFP80_7SubClassMask,
4384 .SuperRegIndices: SuperRegIdxSeqs + 1,
4385 .LaneMask: LaneBitmask(0x0000000000000001),
4386 .AllocationPriority: 0,
4387 .GlobalPriority: false,
4388 .TSFlags: 0x00, /* TSFlags */
4389 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4390 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4391 .SuperClasses: nullptr, .SuperClassesSize: 0,
4392 .OrderFunc: nullptr
4393 };
4394
4395 extern const TargetRegisterClass VR128XRegClass = {
4396 .MC: &X86MCRegisterClasses[VR128XRegClassID],
4397 .SubClassMask: VR128XSubClassMask,
4398 .SuperRegIndices: SuperRegIdxSeqs + 12,
4399 .LaneMask: LaneBitmask(0x0000000000000001),
4400 .AllocationPriority: 0,
4401 .GlobalPriority: false,
4402 .TSFlags: 0x00, /* TSFlags */
4403 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4404 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4405 .SuperClasses: VR128XSuperclasses, .SuperClassesSize: 3,
4406 .OrderFunc: VR128XGetRawAllocationOrder
4407 };
4408
4409 extern const TargetRegisterClass VR128RegClass = {
4410 .MC: &X86MCRegisterClasses[VR128RegClassID],
4411 .SubClassMask: VR128SubClassMask,
4412 .SuperRegIndices: SuperRegIdxSeqs + 12,
4413 .LaneMask: LaneBitmask(0x0000000000000001),
4414 .AllocationPriority: 0,
4415 .GlobalPriority: false,
4416 .TSFlags: 0x00, /* TSFlags */
4417 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4418 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4419 .SuperClasses: VR128Superclasses, .SuperClassesSize: 7,
4420 .OrderFunc: nullptr
4421 };
4422
4423 extern const TargetRegisterClass VR256XRegClass = {
4424 .MC: &X86MCRegisterClasses[VR256XRegClassID],
4425 .SubClassMask: VR256XSubClassMask,
4426 .SuperRegIndices: SuperRegIdxSeqs + 14,
4427 .LaneMask: LaneBitmask(0x0000000000000040),
4428 .AllocationPriority: 0,
4429 .GlobalPriority: false,
4430 .TSFlags: 0x00, /* TSFlags */
4431 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4432 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4433 .SuperClasses: nullptr, .SuperClassesSize: 0,
4434 .OrderFunc: VR256XGetRawAllocationOrder
4435 };
4436
4437 extern const TargetRegisterClass VR256RegClass = {
4438 .MC: &X86MCRegisterClasses[VR256RegClassID],
4439 .SubClassMask: VR256SubClassMask,
4440 .SuperRegIndices: SuperRegIdxSeqs + 14,
4441 .LaneMask: LaneBitmask(0x0000000000000040),
4442 .AllocationPriority: 0,
4443 .GlobalPriority: false,
4444 .TSFlags: 0x00, /* TSFlags */
4445 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4446 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4447 .SuperClasses: VR256Superclasses, .SuperClassesSize: 1,
4448 .OrderFunc: nullptr
4449 };
4450
4451 extern const TargetRegisterClass VR512RegClass = {
4452 .MC: &X86MCRegisterClasses[VR512RegClassID],
4453 .SubClassMask: VR512SubClassMask,
4454 .SuperRegIndices: SuperRegIdxSeqs + 1,
4455 .LaneMask: LaneBitmask(0x0000000000000040),
4456 .AllocationPriority: 0,
4457 .GlobalPriority: false,
4458 .TSFlags: 0x00, /* TSFlags */
4459 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4460 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4461 .SuperClasses: nullptr, .SuperClassesSize: 0,
4462 .OrderFunc: nullptr
4463 };
4464
4465 extern const TargetRegisterClass VR512_0_15RegClass = {
4466 .MC: &X86MCRegisterClasses[VR512_0_15RegClassID],
4467 .SubClassMask: VR512_0_15SubClassMask,
4468 .SuperRegIndices: SuperRegIdxSeqs + 1,
4469 .LaneMask: LaneBitmask(0x0000000000000040),
4470 .AllocationPriority: 0,
4471 .GlobalPriority: false,
4472 .TSFlags: 0x00, /* TSFlags */
4473 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4474 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4475 .SuperClasses: VR512_0_15Superclasses, .SuperClassesSize: 1,
4476 .OrderFunc: nullptr
4477 };
4478
4479 extern const TargetRegisterClass TILERegClass = {
4480 .MC: &X86MCRegisterClasses[TILERegClassID],
4481 .SubClassMask: TILESubClassMask,
4482 .SuperRegIndices: SuperRegIdxSeqs + 1,
4483 .LaneMask: LaneBitmask(0x0000000000000001),
4484 .AllocationPriority: 0,
4485 .GlobalPriority: false,
4486 .TSFlags: 0x00, /* TSFlags */
4487 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
4488 .CoveredBySubRegs: false, /* CoveredBySubRegs */
4489 .SuperClasses: nullptr, .SuperClassesSize: 0,
4490 .OrderFunc: nullptr
4491 };
4492
4493
4494} // namespace X86
4495static const TargetRegisterClass *const X86RegisterClasses[] = {
4496 &X86::GR8RegClass,
4497 &X86::GRH8RegClass,
4498 &X86::GR8_NOREX2RegClass,
4499 &X86::GR8_NOREXRegClass,
4500 &X86::GR8_ABCD_HRegClass,
4501 &X86::GR8_ABCD_LRegClass,
4502 &X86::GRH16RegClass,
4503 &X86::GR16RegClass,
4504 &X86::GR16_NOREX2RegClass,
4505 &X86::GR16_NOREXRegClass,
4506 &X86::VK1RegClass,
4507 &X86::VK16RegClass,
4508 &X86::VK2RegClass,
4509 &X86::VK4RegClass,
4510 &X86::VK8RegClass,
4511 &X86::VK16WMRegClass,
4512 &X86::VK1WMRegClass,
4513 &X86::VK2WMRegClass,
4514 &X86::VK4WMRegClass,
4515 &X86::VK8WMRegClass,
4516 &X86::SEGMENT_REGRegClass,
4517 &X86::GR16_ABCDRegClass,
4518 &X86::FPCCRRegClass,
4519 &X86::FR16XRegClass,
4520 &X86::FR16RegClass,
4521 &X86::VK16PAIRRegClass,
4522 &X86::VK1PAIRRegClass,
4523 &X86::VK2PAIRRegClass,
4524 &X86::VK4PAIRRegClass,
4525 &X86::VK8PAIRRegClass,
4526 &X86::VK1PAIR_with_sub_mask_0_in_VK1WMRegClass,
4527 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
4528 &X86::LOW32_ADDR_ACCESSRegClass,
4529 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
4530 &X86::FR32XRegClass,
4531 &X86::GR32RegClass,
4532 &X86::GR32_NOSPRegClass,
4533 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
4534 &X86::DEBUG_REGRegClass,
4535 &X86::FR32RegClass,
4536 &X86::GR32_NOREX2RegClass,
4537 &X86::GR32_NOREX2_NOSPRegClass,
4538 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
4539 &X86::GR32_NOREXRegClass,
4540 &X86::VK32RegClass,
4541 &X86::GR32_NOREX_NOSPRegClass,
4542 &X86::RFP32RegClass,
4543 &X86::VK32WMRegClass,
4544 &X86::GR32_ABCDRegClass,
4545 &X86::GR32_TCRegClass,
4546 &X86::GR32_ABCD_and_GR32_TCRegClass,
4547 &X86::GR32_ADRegClass,
4548 &X86::GR32_ArgRefRegClass,
4549 &X86::GR32_BPSPRegClass,
4550 &X86::GR32_BSIRegClass,
4551 &X86::GR32_CBRegClass,
4552 &X86::GR32_DCRegClass,
4553 &X86::GR32_DIBPRegClass,
4554 &X86::GR32_SIDIRegClass,
4555 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
4556 &X86::CCRRegClass,
4557 &X86::DFCCRRegClass,
4558 &X86::GR32_ABCD_and_GR32_BSIRegClass,
4559 &X86::GR32_AD_and_GR32_ArgRefRegClass,
4560 &X86::GR32_ArgRef_and_GR32_CBRegClass,
4561 &X86::GR32_BPSP_and_GR32_DIBPRegClass,
4562 &X86::GR32_BPSP_and_GR32_TCRegClass,
4563 &X86::GR32_BSI_and_GR32_SIDIRegClass,
4564 &X86::GR32_DIBP_and_GR32_SIDIRegClass,
4565 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass,
4566 &X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClass,
4567 &X86::RFP64RegClass,
4568 &X86::GR64RegClass,
4569 &X86::FR64XRegClass,
4570 &X86::GR64_with_sub_8bitRegClass,
4571 &X86::GR64_NOSPRegClass,
4572 &X86::GR64_NOREX2RegClass,
4573 &X86::CONTROL_REGRegClass,
4574 &X86::FR64RegClass,
4575 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
4576 &X86::GR64_NOREX2_NOSPRegClass,
4577 &X86::GR64PLTSafeRegClass,
4578 &X86::GR64_TCRegClass,
4579 &X86::GR64_NOREXRegClass,
4580 &X86::GR64_TCW64RegClass,
4581 &X86::GR64_TC_with_sub_8bitRegClass,
4582 &X86::GR64_NOREX2_NOSP_and_GR64_TCRegClass,
4583 &X86::GR64_TCW64_with_sub_8bitRegClass,
4584 &X86::GR64_TC_and_GR64_TCW64RegClass,
4585 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
4586 &X86::VK64RegClass,
4587 &X86::VR64RegClass,
4588 &X86::GR64PLTSafe_and_GR64_TCRegClass,
4589 &X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
4590 &X86::GR64_NOREX_NOSPRegClass,
4591 &X86::GR64_NOREX_and_GR64_TCRegClass,
4592 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
4593 &X86::VK64WMRegClass,
4594 &X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
4595 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
4596 &X86::GR64PLTSafe_and_GR64_TCW64RegClass,
4597 &X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
4598 &X86::GR64_NOREX_and_GR64_TCW64RegClass,
4599 &X86::GR64_ABCDRegClass,
4600 &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
4601 &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
4602 &X86::GR64_ADRegClass,
4603 &X86::GR64_ArgRefRegClass,
4604 &X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClass,
4605 &X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClass,
4606 &X86::GR64_with_sub_32bit_in_GR32_BPSPRegClass,
4607 &X86::GR64_with_sub_32bit_in_GR32_BSIRegClass,
4608 &X86::GR64_with_sub_32bit_in_GR32_CBRegClass,
4609 &X86::GR64_with_sub_32bit_in_GR32_DIBPRegClass,
4610 &X86::GR64_with_sub_32bit_in_GR32_SIDIRegClass,
4611 &X86::GR64_ARegClass,
4612 &X86::GR64_ArgRef_and_GR64_TCRegClass,
4613 &X86::GR64_and_LOW32_ADDR_ACCESSRegClass,
4614 &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass,
4615 &X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClass,
4616 &X86::GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClass,
4617 &X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass,
4618 &X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass,
4619 &X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass,
4620 &X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass,
4621 &X86::RSTRegClass,
4622 &X86::RFP80RegClass,
4623 &X86::RFP80_7RegClass,
4624 &X86::VR128XRegClass,
4625 &X86::VR128RegClass,
4626 &X86::VR256XRegClass,
4627 &X86::VR256RegClass,
4628 &X86::VR512RegClass,
4629 &X86::VR512_0_15RegClass,
4630 &X86::TILERegClass,
4631 };
4632
4633static const uint8_t X86CostPerUseTable[] = {
46340, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
4635
4636
4637static const bool X86InAllocatableClassTable[] = {
4638false, true, true, true, true, true, true, false, true, true, true, true, true, true, false, true, true, false, true, true, true, true, true, true, true, true, true, true, false, false, false, true, true, true, false, false, true, false, true, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, true, false, true, true, true, false, true, true, false, true, true, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, };
4639
4640
4641static const TargetRegisterInfoDesc X86RegInfoDesc = { // Extra Descriptors
4642.CostPerUse: X86CostPerUseTable, .NumCosts: 1, .InAllocatableClass: X86InAllocatableClassTable};
4643
4644unsigned X86GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
4645 static const uint8_t Rows[1][10] = {
4646 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4647 };
4648
4649 --IdxA; assert(IdxA < 10); (void) IdxA;
4650 --IdxB; assert(IdxB < 10);
4651 return Rows[0][IdxB];
4652}
4653
4654unsigned X86GenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
4655 static const uint8_t Table[10][10] = {
4656 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4657 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4658 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4659 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4660 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4661 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4662 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4663 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4664 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4665 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
4666 };
4667
4668 --IdxA; assert(IdxA < 10);
4669 --IdxB; assert(IdxB < 10);
4670 return Table[IdxA][IdxB];
4671 }
4672
4673 struct MaskRolOp {
4674 LaneBitmask Mask;
4675 uint8_t RotateLeft;
4676 };
4677 static const MaskRolOp LaneMaskComposeSequences[] = {
4678 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
4679 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
4680 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
4681 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 6
4682 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 4 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 8
4683 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 5 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 10
4684 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 6 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 12
4685 };
4686 static const uint8_t CompositeSequences[] = {
4687 0, // to sub_8bit
4688 2, // to sub_8bit_hi
4689 4, // to sub_8bit_hi_phony
4690 0, // to sub_16bit
4691 6, // to sub_16bit_hi
4692 0, // to sub_32bit
4693 8, // to sub_mask_0
4694 10, // to sub_mask_1
4695 12, // to sub_xmm
4696 0 // to sub_ymm
4697 };
4698
4699LaneBitmask X86GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
4700 --IdxA; assert(IdxA < 10 && "Subregister index out of bounds");
4701 LaneBitmask Result;
4702 for (const MaskRolOp *Ops =
4703 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
4704 Ops->Mask.any(); ++Ops) {
4705 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
4706 if (unsigned S = Ops->RotateLeft)
4707 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
4708 else
4709 Result |= LaneBitmask(M);
4710 }
4711 return Result;
4712}
4713
4714LaneBitmask X86GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
4715 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
4716 --IdxA; assert(IdxA < 10 && "Subregister index out of bounds");
4717 LaneBitmask Result;
4718 for (const MaskRolOp *Ops =
4719 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
4720 Ops->Mask.any(); ++Ops) {
4721 LaneBitmask::Type M = LaneMask.getAsInteger();
4722 if (unsigned S = Ops->RotateLeft)
4723 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
4724 else
4725 Result |= LaneBitmask(M);
4726 }
4727 return Result;
4728}
4729
4730const TargetRegisterClass *X86GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
4731 static constexpr uint8_t Table[135][10] = {
4732 { // GR8
4733 0, // sub_8bit
4734 0, // sub_8bit_hi
4735 0, // sub_8bit_hi_phony
4736 0, // sub_16bit
4737 0, // sub_16bit_hi
4738 0, // sub_32bit
4739 0, // sub_mask_0
4740 0, // sub_mask_1
4741 0, // sub_xmm
4742 0, // sub_ymm
4743 },
4744 { // GRH8
4745 0, // sub_8bit
4746 0, // sub_8bit_hi
4747 0, // sub_8bit_hi_phony
4748 0, // sub_16bit
4749 0, // sub_16bit_hi
4750 0, // sub_32bit
4751 0, // sub_mask_0
4752 0, // sub_mask_1
4753 0, // sub_xmm
4754 0, // sub_ymm
4755 },
4756 { // GR8_NOREX2
4757 0, // sub_8bit
4758 0, // sub_8bit_hi
4759 0, // sub_8bit_hi_phony
4760 0, // sub_16bit
4761 0, // sub_16bit_hi
4762 0, // sub_32bit
4763 0, // sub_mask_0
4764 0, // sub_mask_1
4765 0, // sub_xmm
4766 0, // sub_ymm
4767 },
4768 { // GR8_NOREX
4769 0, // sub_8bit
4770 0, // sub_8bit_hi
4771 0, // sub_8bit_hi_phony
4772 0, // sub_16bit
4773 0, // sub_16bit_hi
4774 0, // sub_32bit
4775 0, // sub_mask_0
4776 0, // sub_mask_1
4777 0, // sub_xmm
4778 0, // sub_ymm
4779 },
4780 { // GR8_ABCD_H
4781 0, // sub_8bit
4782 0, // sub_8bit_hi
4783 0, // sub_8bit_hi_phony
4784 0, // sub_16bit
4785 0, // sub_16bit_hi
4786 0, // sub_32bit
4787 0, // sub_mask_0
4788 0, // sub_mask_1
4789 0, // sub_xmm
4790 0, // sub_ymm
4791 },
4792 { // GR8_ABCD_L
4793 0, // sub_8bit
4794 0, // sub_8bit_hi
4795 0, // sub_8bit_hi_phony
4796 0, // sub_16bit
4797 0, // sub_16bit_hi
4798 0, // sub_32bit
4799 0, // sub_mask_0
4800 0, // sub_mask_1
4801 0, // sub_xmm
4802 0, // sub_ymm
4803 },
4804 { // GRH16
4805 0, // sub_8bit
4806 0, // sub_8bit_hi
4807 0, // sub_8bit_hi_phony
4808 0, // sub_16bit
4809 0, // sub_16bit_hi
4810 0, // sub_32bit
4811 0, // sub_mask_0
4812 0, // sub_mask_1
4813 0, // sub_xmm
4814 0, // sub_ymm
4815 },
4816 { // GR16
4817 8, // sub_8bit -> GR16
4818 22, // sub_8bit_hi -> GR16_ABCD
4819 0, // sub_8bit_hi_phony
4820 0, // sub_16bit
4821 0, // sub_16bit_hi
4822 0, // sub_32bit
4823 0, // sub_mask_0
4824 0, // sub_mask_1
4825 0, // sub_xmm
4826 0, // sub_ymm
4827 },
4828 { // GR16_NOREX2
4829 9, // sub_8bit -> GR16_NOREX2
4830 22, // sub_8bit_hi -> GR16_ABCD
4831 0, // sub_8bit_hi_phony
4832 0, // sub_16bit
4833 0, // sub_16bit_hi
4834 0, // sub_32bit
4835 0, // sub_mask_0
4836 0, // sub_mask_1
4837 0, // sub_xmm
4838 0, // sub_ymm
4839 },
4840 { // GR16_NOREX
4841 10, // sub_8bit -> GR16_NOREX
4842 22, // sub_8bit_hi -> GR16_ABCD
4843 0, // sub_8bit_hi_phony
4844 0, // sub_16bit
4845 0, // sub_16bit_hi
4846 0, // sub_32bit
4847 0, // sub_mask_0
4848 0, // sub_mask_1
4849 0, // sub_xmm
4850 0, // sub_ymm
4851 },
4852 { // VK1
4853 0, // sub_8bit
4854 0, // sub_8bit_hi
4855 0, // sub_8bit_hi_phony
4856 0, // sub_16bit
4857 0, // sub_16bit_hi
4858 0, // sub_32bit
4859 0, // sub_mask_0
4860 0, // sub_mask_1
4861 0, // sub_xmm
4862 0, // sub_ymm
4863 },
4864 { // VK16
4865 0, // sub_8bit
4866 0, // sub_8bit_hi
4867 0, // sub_8bit_hi_phony
4868 0, // sub_16bit
4869 0, // sub_16bit_hi
4870 0, // sub_32bit
4871 0, // sub_mask_0
4872 0, // sub_mask_1
4873 0, // sub_xmm
4874 0, // sub_ymm
4875 },
4876 { // VK2
4877 0, // sub_8bit
4878 0, // sub_8bit_hi
4879 0, // sub_8bit_hi_phony
4880 0, // sub_16bit
4881 0, // sub_16bit_hi
4882 0, // sub_32bit
4883 0, // sub_mask_0
4884 0, // sub_mask_1
4885 0, // sub_xmm
4886 0, // sub_ymm
4887 },
4888 { // VK4
4889 0, // sub_8bit
4890 0, // sub_8bit_hi
4891 0, // sub_8bit_hi_phony
4892 0, // sub_16bit
4893 0, // sub_16bit_hi
4894 0, // sub_32bit
4895 0, // sub_mask_0
4896 0, // sub_mask_1
4897 0, // sub_xmm
4898 0, // sub_ymm
4899 },
4900 { // VK8
4901 0, // sub_8bit
4902 0, // sub_8bit_hi
4903 0, // sub_8bit_hi_phony
4904 0, // sub_16bit
4905 0, // sub_16bit_hi
4906 0, // sub_32bit
4907 0, // sub_mask_0
4908 0, // sub_mask_1
4909 0, // sub_xmm
4910 0, // sub_ymm
4911 },
4912 { // VK16WM
4913 0, // sub_8bit
4914 0, // sub_8bit_hi
4915 0, // sub_8bit_hi_phony
4916 0, // sub_16bit
4917 0, // sub_16bit_hi
4918 0, // sub_32bit
4919 0, // sub_mask_0
4920 0, // sub_mask_1
4921 0, // sub_xmm
4922 0, // sub_ymm
4923 },
4924 { // VK1WM
4925 0, // sub_8bit
4926 0, // sub_8bit_hi
4927 0, // sub_8bit_hi_phony
4928 0, // sub_16bit
4929 0, // sub_16bit_hi
4930 0, // sub_32bit
4931 0, // sub_mask_0
4932 0, // sub_mask_1
4933 0, // sub_xmm
4934 0, // sub_ymm
4935 },
4936 { // VK2WM
4937 0, // sub_8bit
4938 0, // sub_8bit_hi
4939 0, // sub_8bit_hi_phony
4940 0, // sub_16bit
4941 0, // sub_16bit_hi
4942 0, // sub_32bit
4943 0, // sub_mask_0
4944 0, // sub_mask_1
4945 0, // sub_xmm
4946 0, // sub_ymm
4947 },
4948 { // VK4WM
4949 0, // sub_8bit
4950 0, // sub_8bit_hi
4951 0, // sub_8bit_hi_phony
4952 0, // sub_16bit
4953 0, // sub_16bit_hi
4954 0, // sub_32bit
4955 0, // sub_mask_0
4956 0, // sub_mask_1
4957 0, // sub_xmm
4958 0, // sub_ymm
4959 },
4960 { // VK8WM
4961 0, // sub_8bit
4962 0, // sub_8bit_hi
4963 0, // sub_8bit_hi_phony
4964 0, // sub_16bit
4965 0, // sub_16bit_hi
4966 0, // sub_32bit
4967 0, // sub_mask_0
4968 0, // sub_mask_1
4969 0, // sub_xmm
4970 0, // sub_ymm
4971 },
4972 { // SEGMENT_REG
4973 0, // sub_8bit
4974 0, // sub_8bit_hi
4975 0, // sub_8bit_hi_phony
4976 0, // sub_16bit
4977 0, // sub_16bit_hi
4978 0, // sub_32bit
4979 0, // sub_mask_0
4980 0, // sub_mask_1
4981 0, // sub_xmm
4982 0, // sub_ymm
4983 },
4984 { // GR16_ABCD
4985 22, // sub_8bit -> GR16_ABCD
4986 22, // sub_8bit_hi -> GR16_ABCD
4987 0, // sub_8bit_hi_phony
4988 0, // sub_16bit
4989 0, // sub_16bit_hi
4990 0, // sub_32bit
4991 0, // sub_mask_0
4992 0, // sub_mask_1
4993 0, // sub_xmm
4994 0, // sub_ymm
4995 },
4996 { // FPCCR
4997 0, // sub_8bit
4998 0, // sub_8bit_hi
4999 0, // sub_8bit_hi_phony
5000 0, // sub_16bit
5001 0, // sub_16bit_hi
5002 0, // sub_32bit
5003 0, // sub_mask_0
5004 0, // sub_mask_1
5005 0, // sub_xmm
5006 0, // sub_ymm
5007 },
5008 { // FR16X
5009 0, // sub_8bit
5010 0, // sub_8bit_hi
5011 0, // sub_8bit_hi_phony
5012 0, // sub_16bit
5013 0, // sub_16bit_hi
5014 0, // sub_32bit
5015 0, // sub_mask_0
5016 0, // sub_mask_1
5017 0, // sub_xmm
5018 0, // sub_ymm
5019 },
5020 { // FR16
5021 0, // sub_8bit
5022 0, // sub_8bit_hi
5023 0, // sub_8bit_hi_phony
5024 0, // sub_16bit
5025 0, // sub_16bit_hi
5026 0, // sub_32bit
5027 0, // sub_mask_0
5028 0, // sub_mask_1
5029 0, // sub_xmm
5030 0, // sub_ymm
5031 },
5032 { // VK16PAIR
5033 0, // sub_8bit
5034 0, // sub_8bit_hi
5035 0, // sub_8bit_hi_phony
5036 0, // sub_16bit
5037 0, // sub_16bit_hi
5038 0, // sub_32bit
5039 26, // sub_mask_0 -> VK16PAIR
5040 26, // sub_mask_1 -> VK16PAIR
5041 0, // sub_xmm
5042 0, // sub_ymm
5043 },
5044 { // VK1PAIR
5045 0, // sub_8bit
5046 0, // sub_8bit_hi
5047 0, // sub_8bit_hi_phony
5048 0, // sub_16bit
5049 0, // sub_16bit_hi
5050 0, // sub_32bit
5051 27, // sub_mask_0 -> VK1PAIR
5052 27, // sub_mask_1 -> VK1PAIR
5053 0, // sub_xmm
5054 0, // sub_ymm
5055 },
5056 { // VK2PAIR
5057 0, // sub_8bit
5058 0, // sub_8bit_hi
5059 0, // sub_8bit_hi_phony
5060 0, // sub_16bit
5061 0, // sub_16bit_hi
5062 0, // sub_32bit
5063 28, // sub_mask_0 -> VK2PAIR
5064 28, // sub_mask_1 -> VK2PAIR
5065 0, // sub_xmm
5066 0, // sub_ymm
5067 },
5068 { // VK4PAIR
5069 0, // sub_8bit
5070 0, // sub_8bit_hi
5071 0, // sub_8bit_hi_phony
5072 0, // sub_16bit
5073 0, // sub_16bit_hi
5074 0, // sub_32bit
5075 29, // sub_mask_0 -> VK4PAIR
5076 29, // sub_mask_1 -> VK4PAIR
5077 0, // sub_xmm
5078 0, // sub_ymm
5079 },
5080 { // VK8PAIR
5081 0, // sub_8bit
5082 0, // sub_8bit_hi
5083 0, // sub_8bit_hi_phony
5084 0, // sub_16bit
5085 0, // sub_16bit_hi
5086 0, // sub_32bit
5087 30, // sub_mask_0 -> VK8PAIR
5088 30, // sub_mask_1 -> VK8PAIR
5089 0, // sub_xmm
5090 0, // sub_ymm
5091 },
5092 { // VK1PAIR_with_sub_mask_0_in_VK1WM
5093 0, // sub_8bit
5094 0, // sub_8bit_hi
5095 0, // sub_8bit_hi_phony
5096 0, // sub_16bit
5097 0, // sub_16bit_hi
5098 0, // sub_32bit
5099 31, // sub_mask_0 -> VK1PAIR_with_sub_mask_0_in_VK1WM
5100 31, // sub_mask_1 -> VK1PAIR_with_sub_mask_0_in_VK1WM
5101 0, // sub_xmm
5102 0, // sub_ymm
5103 },
5104 { // LOW32_ADDR_ACCESS_RBP
5105 34, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
5106 49, // sub_8bit_hi -> GR32_ABCD
5107 0, // sub_8bit_hi_phony
5108 32, // sub_16bit -> LOW32_ADDR_ACCESS_RBP
5109 32, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP
5110 60, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
5111 0, // sub_mask_0
5112 0, // sub_mask_1
5113 0, // sub_xmm
5114 0, // sub_ymm
5115 },
5116 { // LOW32_ADDR_ACCESS
5117 36, // sub_8bit -> GR32
5118 49, // sub_8bit_hi -> GR32_ABCD
5119 0, // sub_8bit_hi_phony
5120 33, // sub_16bit -> LOW32_ADDR_ACCESS
5121 33, // sub_16bit_hi -> LOW32_ADDR_ACCESS
5122 71, // sub_32bit -> LOW32_ADDR_ACCESS_with_sub_32bit
5123 0, // sub_mask_0
5124 0, // sub_mask_1
5125 0, // sub_xmm
5126 0, // sub_ymm
5127 },
5128 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
5129 34, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
5130 49, // sub_8bit_hi -> GR32_ABCD
5131 0, // sub_8bit_hi_phony
5132 34, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
5133 34, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
5134 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5135 0, // sub_mask_0
5136 0, // sub_mask_1
5137 0, // sub_xmm
5138 0, // sub_ymm
5139 },
5140 { // FR32X
5141 0, // sub_8bit
5142 0, // sub_8bit_hi
5143 0, // sub_8bit_hi_phony
5144 0, // sub_16bit
5145 0, // sub_16bit_hi
5146 0, // sub_32bit
5147 0, // sub_mask_0
5148 0, // sub_mask_1
5149 0, // sub_xmm
5150 0, // sub_ymm
5151 },
5152 { // GR32
5153 36, // sub_8bit -> GR32
5154 49, // sub_8bit_hi -> GR32_ABCD
5155 0, // sub_8bit_hi_phony
5156 36, // sub_16bit -> GR32
5157 36, // sub_16bit_hi -> GR32
5158 0, // sub_32bit
5159 0, // sub_mask_0
5160 0, // sub_mask_1
5161 0, // sub_xmm
5162 0, // sub_ymm
5163 },
5164 { // GR32_NOSP
5165 37, // sub_8bit -> GR32_NOSP
5166 49, // sub_8bit_hi -> GR32_ABCD
5167 0, // sub_8bit_hi_phony
5168 37, // sub_16bit -> GR32_NOSP
5169 37, // sub_16bit_hi -> GR32_NOSP
5170 0, // sub_32bit
5171 0, // sub_mask_0
5172 0, // sub_mask_1
5173 0, // sub_xmm
5174 0, // sub_ymm
5175 },
5176 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
5177 38, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
5178 49, // sub_8bit_hi -> GR32_ABCD
5179 0, // sub_8bit_hi_phony
5180 38, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
5181 38, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
5182 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5183 0, // sub_mask_0
5184 0, // sub_mask_1
5185 0, // sub_xmm
5186 0, // sub_ymm
5187 },
5188 { // DEBUG_REG
5189 0, // sub_8bit
5190 0, // sub_8bit_hi
5191 0, // sub_8bit_hi_phony
5192 0, // sub_16bit
5193 0, // sub_16bit_hi
5194 0, // sub_32bit
5195 0, // sub_mask_0
5196 0, // sub_mask_1
5197 0, // sub_xmm
5198 0, // sub_ymm
5199 },
5200 { // FR32
5201 0, // sub_8bit
5202 0, // sub_8bit_hi
5203 0, // sub_8bit_hi_phony
5204 0, // sub_16bit
5205 0, // sub_16bit_hi
5206 0, // sub_32bit
5207 0, // sub_mask_0
5208 0, // sub_mask_1
5209 0, // sub_xmm
5210 0, // sub_ymm
5211 },
5212 { // GR32_NOREX2
5213 41, // sub_8bit -> GR32_NOREX2
5214 49, // sub_8bit_hi -> GR32_ABCD
5215 0, // sub_8bit_hi_phony
5216 41, // sub_16bit -> GR32_NOREX2
5217 41, // sub_16bit_hi -> GR32_NOREX2
5218 0, // sub_32bit
5219 0, // sub_mask_0
5220 0, // sub_mask_1
5221 0, // sub_xmm
5222 0, // sub_ymm
5223 },
5224 { // GR32_NOREX2_NOSP
5225 42, // sub_8bit -> GR32_NOREX2_NOSP
5226 49, // sub_8bit_hi -> GR32_ABCD
5227 0, // sub_8bit_hi_phony
5228 42, // sub_16bit -> GR32_NOREX2_NOSP
5229 42, // sub_16bit_hi -> GR32_NOREX2_NOSP
5230 0, // sub_32bit
5231 0, // sub_mask_0
5232 0, // sub_mask_1
5233 0, // sub_xmm
5234 0, // sub_ymm
5235 },
5236 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
5237 43, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
5238 49, // sub_8bit_hi -> GR32_ABCD
5239 0, // sub_8bit_hi_phony
5240 43, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
5241 43, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
5242 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5243 0, // sub_mask_0
5244 0, // sub_mask_1
5245 0, // sub_xmm
5246 0, // sub_ymm
5247 },
5248 { // GR32_NOREX
5249 44, // sub_8bit -> GR32_NOREX
5250 49, // sub_8bit_hi -> GR32_ABCD
5251 0, // sub_8bit_hi_phony
5252 44, // sub_16bit -> GR32_NOREX
5253 44, // sub_16bit_hi -> GR32_NOREX
5254 0, // sub_32bit
5255 0, // sub_mask_0
5256 0, // sub_mask_1
5257 0, // sub_xmm
5258 0, // sub_ymm
5259 },
5260 { // VK32
5261 0, // sub_8bit
5262 0, // sub_8bit_hi
5263 0, // sub_8bit_hi_phony
5264 0, // sub_16bit
5265 0, // sub_16bit_hi
5266 0, // sub_32bit
5267 0, // sub_mask_0
5268 0, // sub_mask_1
5269 0, // sub_xmm
5270 0, // sub_ymm
5271 },
5272 { // GR32_NOREX_NOSP
5273 46, // sub_8bit -> GR32_NOREX_NOSP
5274 49, // sub_8bit_hi -> GR32_ABCD
5275 0, // sub_8bit_hi_phony
5276 46, // sub_16bit -> GR32_NOREX_NOSP
5277 46, // sub_16bit_hi -> GR32_NOREX_NOSP
5278 0, // sub_32bit
5279 0, // sub_mask_0
5280 0, // sub_mask_1
5281 0, // sub_xmm
5282 0, // sub_ymm
5283 },
5284 { // RFP32
5285 0, // sub_8bit
5286 0, // sub_8bit_hi
5287 0, // sub_8bit_hi_phony
5288 0, // sub_16bit
5289 0, // sub_16bit_hi
5290 0, // sub_32bit
5291 0, // sub_mask_0
5292 0, // sub_mask_1
5293 0, // sub_xmm
5294 0, // sub_ymm
5295 },
5296 { // VK32WM
5297 0, // sub_8bit
5298 0, // sub_8bit_hi
5299 0, // sub_8bit_hi_phony
5300 0, // sub_16bit
5301 0, // sub_16bit_hi
5302 0, // sub_32bit
5303 0, // sub_mask_0
5304 0, // sub_mask_1
5305 0, // sub_xmm
5306 0, // sub_ymm
5307 },
5308 { // GR32_ABCD
5309 49, // sub_8bit -> GR32_ABCD
5310 49, // sub_8bit_hi -> GR32_ABCD
5311 0, // sub_8bit_hi_phony
5312 49, // sub_16bit -> GR32_ABCD
5313 49, // sub_16bit_hi -> GR32_ABCD
5314 0, // sub_32bit
5315 0, // sub_mask_0
5316 0, // sub_mask_1
5317 0, // sub_xmm
5318 0, // sub_ymm
5319 },
5320 { // GR32_TC
5321 50, // sub_8bit -> GR32_TC
5322 51, // sub_8bit_hi -> GR32_ABCD_and_GR32_TC
5323 0, // sub_8bit_hi_phony
5324 50, // sub_16bit -> GR32_TC
5325 50, // sub_16bit_hi -> GR32_TC
5326 0, // sub_32bit
5327 0, // sub_mask_0
5328 0, // sub_mask_1
5329 0, // sub_xmm
5330 0, // sub_ymm
5331 },
5332 { // GR32_ABCD_and_GR32_TC
5333 51, // sub_8bit -> GR32_ABCD_and_GR32_TC
5334 51, // sub_8bit_hi -> GR32_ABCD_and_GR32_TC
5335 0, // sub_8bit_hi_phony
5336 51, // sub_16bit -> GR32_ABCD_and_GR32_TC
5337 51, // sub_16bit_hi -> GR32_ABCD_and_GR32_TC
5338 0, // sub_32bit
5339 0, // sub_mask_0
5340 0, // sub_mask_1
5341 0, // sub_xmm
5342 0, // sub_ymm
5343 },
5344 { // GR32_AD
5345 52, // sub_8bit -> GR32_AD
5346 52, // sub_8bit_hi -> GR32_AD
5347 0, // sub_8bit_hi_phony
5348 52, // sub_16bit -> GR32_AD
5349 52, // sub_16bit_hi -> GR32_AD
5350 0, // sub_32bit
5351 0, // sub_mask_0
5352 0, // sub_mask_1
5353 0, // sub_xmm
5354 0, // sub_ymm
5355 },
5356 { // GR32_ArgRef
5357 53, // sub_8bit -> GR32_ArgRef
5358 53, // sub_8bit_hi -> GR32_ArgRef
5359 0, // sub_8bit_hi_phony
5360 53, // sub_16bit -> GR32_ArgRef
5361 53, // sub_16bit_hi -> GR32_ArgRef
5362 0, // sub_32bit
5363 0, // sub_mask_0
5364 0, // sub_mask_1
5365 0, // sub_xmm
5366 0, // sub_ymm
5367 },
5368 { // GR32_BPSP
5369 54, // sub_8bit -> GR32_BPSP
5370 0, // sub_8bit_hi
5371 54, // sub_8bit_hi_phony -> GR32_BPSP
5372 54, // sub_16bit -> GR32_BPSP
5373 54, // sub_16bit_hi -> GR32_BPSP
5374 0, // sub_32bit
5375 0, // sub_mask_0
5376 0, // sub_mask_1
5377 0, // sub_xmm
5378 0, // sub_ymm
5379 },
5380 { // GR32_BSI
5381 55, // sub_8bit -> GR32_BSI
5382 63, // sub_8bit_hi -> GR32_ABCD_and_GR32_BSI
5383 0, // sub_8bit_hi_phony
5384 55, // sub_16bit -> GR32_BSI
5385 55, // sub_16bit_hi -> GR32_BSI
5386 0, // sub_32bit
5387 0, // sub_mask_0
5388 0, // sub_mask_1
5389 0, // sub_xmm
5390 0, // sub_ymm
5391 },
5392 { // GR32_CB
5393 56, // sub_8bit -> GR32_CB
5394 56, // sub_8bit_hi -> GR32_CB
5395 0, // sub_8bit_hi_phony
5396 56, // sub_16bit -> GR32_CB
5397 56, // sub_16bit_hi -> GR32_CB
5398 0, // sub_32bit
5399 0, // sub_mask_0
5400 0, // sub_mask_1
5401 0, // sub_xmm
5402 0, // sub_ymm
5403 },
5404 { // GR32_DC
5405 57, // sub_8bit -> GR32_DC
5406 57, // sub_8bit_hi -> GR32_DC
5407 0, // sub_8bit_hi_phony
5408 57, // sub_16bit -> GR32_DC
5409 57, // sub_16bit_hi -> GR32_DC
5410 0, // sub_32bit
5411 0, // sub_mask_0
5412 0, // sub_mask_1
5413 0, // sub_xmm
5414 0, // sub_ymm
5415 },
5416 { // GR32_DIBP
5417 58, // sub_8bit -> GR32_DIBP
5418 0, // sub_8bit_hi
5419 58, // sub_8bit_hi_phony -> GR32_DIBP
5420 58, // sub_16bit -> GR32_DIBP
5421 58, // sub_16bit_hi -> GR32_DIBP
5422 0, // sub_32bit
5423 0, // sub_mask_0
5424 0, // sub_mask_1
5425 0, // sub_xmm
5426 0, // sub_ymm
5427 },
5428 { // GR32_SIDI
5429 59, // sub_8bit -> GR32_SIDI
5430 0, // sub_8bit_hi
5431 59, // sub_8bit_hi_phony -> GR32_SIDI
5432 59, // sub_16bit -> GR32_SIDI
5433 59, // sub_16bit_hi -> GR32_SIDI
5434 0, // sub_32bit
5435 0, // sub_mask_0
5436 0, // sub_mask_1
5437 0, // sub_xmm
5438 0, // sub_ymm
5439 },
5440 { // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
5441 70, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5442 0, // sub_8bit_hi
5443 0, // sub_8bit_hi_phony
5444 60, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
5445 60, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
5446 60, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
5447 0, // sub_mask_0
5448 0, // sub_mask_1
5449 0, // sub_xmm
5450 0, // sub_ymm
5451 },
5452 { // CCR
5453 0, // sub_8bit
5454 0, // sub_8bit_hi
5455 0, // sub_8bit_hi_phony
5456 0, // sub_16bit
5457 0, // sub_16bit_hi
5458 0, // sub_32bit
5459 0, // sub_mask_0
5460 0, // sub_mask_1
5461 0, // sub_xmm
5462 0, // sub_ymm
5463 },
5464 { // DFCCR
5465 0, // sub_8bit
5466 0, // sub_8bit_hi
5467 0, // sub_8bit_hi_phony
5468 0, // sub_16bit
5469 0, // sub_16bit_hi
5470 0, // sub_32bit
5471 0, // sub_mask_0
5472 0, // sub_mask_1
5473 0, // sub_xmm
5474 0, // sub_ymm
5475 },
5476 { // GR32_ABCD_and_GR32_BSI
5477 63, // sub_8bit -> GR32_ABCD_and_GR32_BSI
5478 63, // sub_8bit_hi -> GR32_ABCD_and_GR32_BSI
5479 0, // sub_8bit_hi_phony
5480 63, // sub_16bit -> GR32_ABCD_and_GR32_BSI
5481 63, // sub_16bit_hi -> GR32_ABCD_and_GR32_BSI
5482 0, // sub_32bit
5483 0, // sub_mask_0
5484 0, // sub_mask_1
5485 0, // sub_xmm
5486 0, // sub_ymm
5487 },
5488 { // GR32_AD_and_GR32_ArgRef
5489 64, // sub_8bit -> GR32_AD_and_GR32_ArgRef
5490 64, // sub_8bit_hi -> GR32_AD_and_GR32_ArgRef
5491 0, // sub_8bit_hi_phony
5492 64, // sub_16bit -> GR32_AD_and_GR32_ArgRef
5493 64, // sub_16bit_hi -> GR32_AD_and_GR32_ArgRef
5494 0, // sub_32bit
5495 0, // sub_mask_0
5496 0, // sub_mask_1
5497 0, // sub_xmm
5498 0, // sub_ymm
5499 },
5500 { // GR32_ArgRef_and_GR32_CB
5501 65, // sub_8bit -> GR32_ArgRef_and_GR32_CB
5502 65, // sub_8bit_hi -> GR32_ArgRef_and_GR32_CB
5503 0, // sub_8bit_hi_phony
5504 65, // sub_16bit -> GR32_ArgRef_and_GR32_CB
5505 65, // sub_16bit_hi -> GR32_ArgRef_and_GR32_CB
5506 0, // sub_32bit
5507 0, // sub_mask_0
5508 0, // sub_mask_1
5509 0, // sub_xmm
5510 0, // sub_ymm
5511 },
5512 { // GR32_BPSP_and_GR32_DIBP
5513 66, // sub_8bit -> GR32_BPSP_and_GR32_DIBP
5514 0, // sub_8bit_hi
5515 66, // sub_8bit_hi_phony -> GR32_BPSP_and_GR32_DIBP
5516 66, // sub_16bit -> GR32_BPSP_and_GR32_DIBP
5517 66, // sub_16bit_hi -> GR32_BPSP_and_GR32_DIBP
5518 0, // sub_32bit
5519 0, // sub_mask_0
5520 0, // sub_mask_1
5521 0, // sub_xmm
5522 0, // sub_ymm
5523 },
5524 { // GR32_BPSP_and_GR32_TC
5525 67, // sub_8bit -> GR32_BPSP_and_GR32_TC
5526 0, // sub_8bit_hi
5527 67, // sub_8bit_hi_phony -> GR32_BPSP_and_GR32_TC
5528 67, // sub_16bit -> GR32_BPSP_and_GR32_TC
5529 67, // sub_16bit_hi -> GR32_BPSP_and_GR32_TC
5530 0, // sub_32bit
5531 0, // sub_mask_0
5532 0, // sub_mask_1
5533 0, // sub_xmm
5534 0, // sub_ymm
5535 },
5536 { // GR32_BSI_and_GR32_SIDI
5537 68, // sub_8bit -> GR32_BSI_and_GR32_SIDI
5538 0, // sub_8bit_hi
5539 68, // sub_8bit_hi_phony -> GR32_BSI_and_GR32_SIDI
5540 68, // sub_16bit -> GR32_BSI_and_GR32_SIDI
5541 68, // sub_16bit_hi -> GR32_BSI_and_GR32_SIDI
5542 0, // sub_32bit
5543 0, // sub_mask_0
5544 0, // sub_mask_1
5545 0, // sub_xmm
5546 0, // sub_ymm
5547 },
5548 { // GR32_DIBP_and_GR32_SIDI
5549 69, // sub_8bit -> GR32_DIBP_and_GR32_SIDI
5550 0, // sub_8bit_hi
5551 69, // sub_8bit_hi_phony -> GR32_DIBP_and_GR32_SIDI
5552 69, // sub_16bit -> GR32_DIBP_and_GR32_SIDI
5553 69, // sub_16bit_hi -> GR32_DIBP_and_GR32_SIDI
5554 0, // sub_32bit
5555 0, // sub_mask_0
5556 0, // sub_mask_1
5557 0, // sub_xmm
5558 0, // sub_ymm
5559 },
5560 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5561 70, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5562 0, // sub_8bit_hi
5563 70, // sub_8bit_hi_phony -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5564 70, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5565 70, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5566 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5567 0, // sub_mask_0
5568 0, // sub_mask_1
5569 0, // sub_xmm
5570 0, // sub_ymm
5571 },
5572 { // LOW32_ADDR_ACCESS_with_sub_32bit
5573 0, // sub_8bit
5574 0, // sub_8bit_hi
5575 0, // sub_8bit_hi_phony
5576 71, // sub_16bit -> LOW32_ADDR_ACCESS_with_sub_32bit
5577 71, // sub_16bit_hi -> LOW32_ADDR_ACCESS_with_sub_32bit
5578 71, // sub_32bit -> LOW32_ADDR_ACCESS_with_sub_32bit
5579 0, // sub_mask_0
5580 0, // sub_mask_1
5581 0, // sub_xmm
5582 0, // sub_ymm
5583 },
5584 { // RFP64
5585 0, // sub_8bit
5586 0, // sub_8bit_hi
5587 0, // sub_8bit_hi_phony
5588 0, // sub_16bit
5589 0, // sub_16bit_hi
5590 0, // sub_32bit
5591 0, // sub_mask_0
5592 0, // sub_mask_1
5593 0, // sub_xmm
5594 0, // sub_ymm
5595 },
5596 { // GR64
5597 75, // sub_8bit -> GR64_with_sub_8bit
5598 104, // sub_8bit_hi -> GR64_ABCD
5599 0, // sub_8bit_hi_phony
5600 73, // sub_16bit -> GR64
5601 73, // sub_16bit_hi -> GR64
5602 73, // sub_32bit -> GR64
5603 0, // sub_mask_0
5604 0, // sub_mask_1
5605 0, // sub_xmm
5606 0, // sub_ymm
5607 },
5608 { // FR64X
5609 0, // sub_8bit
5610 0, // sub_8bit_hi
5611 0, // sub_8bit_hi_phony
5612 0, // sub_16bit
5613 0, // sub_16bit_hi
5614 0, // sub_32bit
5615 0, // sub_mask_0
5616 0, // sub_mask_1
5617 0, // sub_xmm
5618 0, // sub_ymm
5619 },
5620 { // GR64_with_sub_8bit
5621 75, // sub_8bit -> GR64_with_sub_8bit
5622 104, // sub_8bit_hi -> GR64_ABCD
5623 0, // sub_8bit_hi_phony
5624 75, // sub_16bit -> GR64_with_sub_8bit
5625 75, // sub_16bit_hi -> GR64_with_sub_8bit
5626 75, // sub_32bit -> GR64_with_sub_8bit
5627 0, // sub_mask_0
5628 0, // sub_mask_1
5629 0, // sub_xmm
5630 0, // sub_ymm
5631 },
5632 { // GR64_NOSP
5633 76, // sub_8bit -> GR64_NOSP
5634 104, // sub_8bit_hi -> GR64_ABCD
5635 0, // sub_8bit_hi_phony
5636 76, // sub_16bit -> GR64_NOSP
5637 76, // sub_16bit_hi -> GR64_NOSP
5638 76, // sub_32bit -> GR64_NOSP
5639 0, // sub_mask_0
5640 0, // sub_mask_1
5641 0, // sub_xmm
5642 0, // sub_ymm
5643 },
5644 { // GR64_NOREX2
5645 80, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX2
5646 104, // sub_8bit_hi -> GR64_ABCD
5647 0, // sub_8bit_hi_phony
5648 77, // sub_16bit -> GR64_NOREX2
5649 77, // sub_16bit_hi -> GR64_NOREX2
5650 77, // sub_32bit -> GR64_NOREX2
5651 0, // sub_mask_0
5652 0, // sub_mask_1
5653 0, // sub_xmm
5654 0, // sub_ymm
5655 },
5656 { // CONTROL_REG
5657 0, // sub_8bit
5658 0, // sub_8bit_hi
5659 0, // sub_8bit_hi_phony
5660 0, // sub_16bit
5661 0, // sub_16bit_hi
5662 0, // sub_32bit
5663 0, // sub_mask_0
5664 0, // sub_mask_1
5665 0, // sub_xmm
5666 0, // sub_ymm
5667 },
5668 { // FR64
5669 0, // sub_8bit
5670 0, // sub_8bit_hi
5671 0, // sub_8bit_hi_phony
5672 0, // sub_16bit
5673 0, // sub_16bit_hi
5674 0, // sub_32bit
5675 0, // sub_mask_0
5676 0, // sub_mask_1
5677 0, // sub_xmm
5678 0, // sub_ymm
5679 },
5680 { // GR64_with_sub_16bit_in_GR16_NOREX2
5681 80, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX2
5682 104, // sub_8bit_hi -> GR64_ABCD
5683 0, // sub_8bit_hi_phony
5684 80, // sub_16bit -> GR64_with_sub_16bit_in_GR16_NOREX2
5685 80, // sub_16bit_hi -> GR64_with_sub_16bit_in_GR16_NOREX2
5686 80, // sub_32bit -> GR64_with_sub_16bit_in_GR16_NOREX2
5687 0, // sub_mask_0
5688 0, // sub_mask_1
5689 0, // sub_xmm
5690 0, // sub_ymm
5691 },
5692 { // GR64_NOREX2_NOSP
5693 81, // sub_8bit -> GR64_NOREX2_NOSP
5694 104, // sub_8bit_hi -> GR64_ABCD
5695 0, // sub_8bit_hi_phony
5696 81, // sub_16bit -> GR64_NOREX2_NOSP
5697 81, // sub_16bit_hi -> GR64_NOREX2_NOSP
5698 81, // sub_32bit -> GR64_NOREX2_NOSP
5699 0, // sub_mask_0
5700 0, // sub_mask_1
5701 0, // sub_xmm
5702 0, // sub_ymm
5703 },
5704 { // GR64PLTSafe
5705 82, // sub_8bit -> GR64PLTSafe
5706 104, // sub_8bit_hi -> GR64_ABCD
5707 0, // sub_8bit_hi_phony
5708 82, // sub_16bit -> GR64PLTSafe
5709 82, // sub_16bit_hi -> GR64PLTSafe
5710 82, // sub_32bit -> GR64PLTSafe
5711 0, // sub_mask_0
5712 0, // sub_mask_1
5713 0, // sub_xmm
5714 0, // sub_ymm
5715 },
5716 { // GR64_TC
5717 86, // sub_8bit -> GR64_TC_with_sub_8bit
5718 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5719 0, // sub_8bit_hi_phony
5720 83, // sub_16bit -> GR64_TC
5721 83, // sub_16bit_hi -> GR64_TC
5722 83, // sub_32bit -> GR64_TC
5723 0, // sub_mask_0
5724 0, // sub_mask_1
5725 0, // sub_xmm
5726 0, // sub_ymm
5727 },
5728 { // GR64_NOREX
5729 90, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX
5730 104, // sub_8bit_hi -> GR64_ABCD
5731 0, // sub_8bit_hi_phony
5732 84, // sub_16bit -> GR64_NOREX
5733 84, // sub_16bit_hi -> GR64_NOREX
5734 84, // sub_32bit -> GR64_NOREX
5735 0, // sub_mask_0
5736 0, // sub_mask_1
5737 0, // sub_xmm
5738 0, // sub_ymm
5739 },
5740 { // GR64_TCW64
5741 88, // sub_8bit -> GR64_TCW64_with_sub_8bit
5742 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5743 0, // sub_8bit_hi_phony
5744 85, // sub_16bit -> GR64_TCW64
5745 85, // sub_16bit_hi -> GR64_TCW64
5746 85, // sub_32bit -> GR64_TCW64
5747 0, // sub_mask_0
5748 0, // sub_mask_1
5749 0, // sub_xmm
5750 0, // sub_ymm
5751 },
5752 { // GR64_TC_with_sub_8bit
5753 86, // sub_8bit -> GR64_TC_with_sub_8bit
5754 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5755 0, // sub_8bit_hi_phony
5756 86, // sub_16bit -> GR64_TC_with_sub_8bit
5757 86, // sub_16bit_hi -> GR64_TC_with_sub_8bit
5758 86, // sub_32bit -> GR64_TC_with_sub_8bit
5759 0, // sub_mask_0
5760 0, // sub_mask_1
5761 0, // sub_xmm
5762 0, // sub_ymm
5763 },
5764 { // GR64_NOREX2_NOSP_and_GR64_TC
5765 87, // sub_8bit -> GR64_NOREX2_NOSP_and_GR64_TC
5766 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5767 0, // sub_8bit_hi_phony
5768 87, // sub_16bit -> GR64_NOREX2_NOSP_and_GR64_TC
5769 87, // sub_16bit_hi -> GR64_NOREX2_NOSP_and_GR64_TC
5770 87, // sub_32bit -> GR64_NOREX2_NOSP_and_GR64_TC
5771 0, // sub_mask_0
5772 0, // sub_mask_1
5773 0, // sub_xmm
5774 0, // sub_ymm
5775 },
5776 { // GR64_TCW64_with_sub_8bit
5777 88, // sub_8bit -> GR64_TCW64_with_sub_8bit
5778 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5779 0, // sub_8bit_hi_phony
5780 88, // sub_16bit -> GR64_TCW64_with_sub_8bit
5781 88, // sub_16bit_hi -> GR64_TCW64_with_sub_8bit
5782 88, // sub_32bit -> GR64_TCW64_with_sub_8bit
5783 0, // sub_mask_0
5784 0, // sub_mask_1
5785 0, // sub_xmm
5786 0, // sub_ymm
5787 },
5788 { // GR64_TC_and_GR64_TCW64
5789 97, // sub_8bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
5790 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5791 0, // sub_8bit_hi_phony
5792 89, // sub_16bit -> GR64_TC_and_GR64_TCW64
5793 89, // sub_16bit_hi -> GR64_TC_and_GR64_TCW64
5794 89, // sub_32bit -> GR64_TC_and_GR64_TCW64
5795 0, // sub_mask_0
5796 0, // sub_mask_1
5797 0, // sub_xmm
5798 0, // sub_ymm
5799 },
5800 { // GR64_with_sub_16bit_in_GR16_NOREX
5801 90, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX
5802 104, // sub_8bit_hi -> GR64_ABCD
5803 0, // sub_8bit_hi_phony
5804 90, // sub_16bit -> GR64_with_sub_16bit_in_GR16_NOREX
5805 90, // sub_16bit_hi -> GR64_with_sub_16bit_in_GR16_NOREX
5806 90, // sub_32bit -> GR64_with_sub_16bit_in_GR16_NOREX
5807 0, // sub_mask_0
5808 0, // sub_mask_1
5809 0, // sub_xmm
5810 0, // sub_ymm
5811 },
5812 { // VK64
5813 0, // sub_8bit
5814 0, // sub_8bit_hi
5815 0, // sub_8bit_hi_phony
5816 0, // sub_16bit
5817 0, // sub_16bit_hi
5818 0, // sub_32bit
5819 0, // sub_mask_0
5820 0, // sub_mask_1
5821 0, // sub_xmm
5822 0, // sub_ymm
5823 },
5824 { // VR64
5825 0, // sub_8bit
5826 0, // sub_8bit_hi
5827 0, // sub_8bit_hi_phony
5828 0, // sub_16bit
5829 0, // sub_16bit_hi
5830 0, // sub_32bit
5831 0, // sub_mask_0
5832 0, // sub_mask_1
5833 0, // sub_xmm
5834 0, // sub_ymm
5835 },
5836 { // GR64PLTSafe_and_GR64_TC
5837 93, // sub_8bit -> GR64PLTSafe_and_GR64_TC
5838 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5839 0, // sub_8bit_hi_phony
5840 93, // sub_16bit -> GR64PLTSafe_and_GR64_TC
5841 93, // sub_16bit_hi -> GR64PLTSafe_and_GR64_TC
5842 93, // sub_32bit -> GR64PLTSafe_and_GR64_TC
5843 0, // sub_mask_0
5844 0, // sub_mask_1
5845 0, // sub_xmm
5846 0, // sub_ymm
5847 },
5848 { // GR64_NOREX2_NOSP_and_GR64_TCW64
5849 94, // sub_8bit -> GR64_NOREX2_NOSP_and_GR64_TCW64
5850 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5851 0, // sub_8bit_hi_phony
5852 94, // sub_16bit -> GR64_NOREX2_NOSP_and_GR64_TCW64
5853 94, // sub_16bit_hi -> GR64_NOREX2_NOSP_and_GR64_TCW64
5854 94, // sub_32bit -> GR64_NOREX2_NOSP_and_GR64_TCW64
5855 0, // sub_mask_0
5856 0, // sub_mask_1
5857 0, // sub_xmm
5858 0, // sub_ymm
5859 },
5860 { // GR64_NOREX_NOSP
5861 95, // sub_8bit -> GR64_NOREX_NOSP
5862 104, // sub_8bit_hi -> GR64_ABCD
5863 0, // sub_8bit_hi_phony
5864 95, // sub_16bit -> GR64_NOREX_NOSP
5865 95, // sub_16bit_hi -> GR64_NOREX_NOSP
5866 95, // sub_32bit -> GR64_NOREX_NOSP
5867 0, // sub_mask_0
5868 0, // sub_mask_1
5869 0, // sub_xmm
5870 0, // sub_ymm
5871 },
5872 { // GR64_NOREX_and_GR64_TC
5873 100, // sub_8bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
5874 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5875 0, // sub_8bit_hi_phony
5876 96, // sub_16bit -> GR64_NOREX_and_GR64_TC
5877 96, // sub_16bit_hi -> GR64_NOREX_and_GR64_TC
5878 96, // sub_32bit -> GR64_NOREX_and_GR64_TC
5879 0, // sub_mask_0
5880 0, // sub_mask_1
5881 0, // sub_xmm
5882 0, // sub_ymm
5883 },
5884 { // GR64_TCW64_and_GR64_TC_with_sub_8bit
5885 97, // sub_8bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
5886 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5887 0, // sub_8bit_hi_phony
5888 97, // sub_16bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
5889 97, // sub_16bit_hi -> GR64_TCW64_and_GR64_TC_with_sub_8bit
5890 97, // sub_32bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
5891 0, // sub_mask_0
5892 0, // sub_mask_1
5893 0, // sub_xmm
5894 0, // sub_ymm
5895 },
5896 { // VK64WM
5897 0, // sub_8bit
5898 0, // sub_8bit_hi
5899 0, // sub_8bit_hi_phony
5900 0, // sub_16bit
5901 0, // sub_16bit_hi
5902 0, // sub_32bit
5903 0, // sub_mask_0
5904 0, // sub_mask_1
5905 0, // sub_xmm
5906 0, // sub_ymm
5907 },
5908 { // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
5909 99, // sub_8bit -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
5910 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5911 0, // sub_8bit_hi_phony
5912 99, // sub_16bit -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
5913 99, // sub_16bit_hi -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
5914 99, // sub_32bit -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
5915 0, // sub_mask_0
5916 0, // sub_mask_1
5917 0, // sub_xmm
5918 0, // sub_ymm
5919 },
5920 { // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
5921 100, // sub_8bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
5922 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5923 0, // sub_8bit_hi_phony
5924 100, // sub_16bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
5925 100, // sub_16bit_hi -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
5926 100, // sub_32bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
5927 0, // sub_mask_0
5928 0, // sub_mask_1
5929 0, // sub_xmm
5930 0, // sub_ymm
5931 },
5932 { // GR64PLTSafe_and_GR64_TCW64
5933 101, // sub_8bit -> GR64PLTSafe_and_GR64_TCW64
5934 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5935 0, // sub_8bit_hi_phony
5936 101, // sub_16bit -> GR64PLTSafe_and_GR64_TCW64
5937 101, // sub_16bit_hi -> GR64PLTSafe_and_GR64_TCW64
5938 101, // sub_32bit -> GR64PLTSafe_and_GR64_TCW64
5939 0, // sub_mask_0
5940 0, // sub_mask_1
5941 0, // sub_xmm
5942 0, // sub_ymm
5943 },
5944 { // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
5945 102, // sub_8bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
5946 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5947 0, // sub_8bit_hi_phony
5948 102, // sub_16bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
5949 102, // sub_16bit_hi -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
5950 102, // sub_32bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
5951 0, // sub_mask_0
5952 0, // sub_mask_1
5953 0, // sub_xmm
5954 0, // sub_ymm
5955 },
5956 { // GR64_NOREX_and_GR64_TCW64
5957 105, // sub_8bit -> GR64_with_sub_32bit_in_GR32_TC
5958 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5959 0, // sub_8bit_hi_phony
5960 103, // sub_16bit -> GR64_NOREX_and_GR64_TCW64
5961 103, // sub_16bit_hi -> GR64_NOREX_and_GR64_TCW64
5962 103, // sub_32bit -> GR64_NOREX_and_GR64_TCW64
5963 0, // sub_mask_0
5964 0, // sub_mask_1
5965 0, // sub_xmm
5966 0, // sub_ymm
5967 },
5968 { // GR64_ABCD
5969 104, // sub_8bit -> GR64_ABCD
5970 104, // sub_8bit_hi -> GR64_ABCD
5971 0, // sub_8bit_hi_phony
5972 104, // sub_16bit -> GR64_ABCD
5973 104, // sub_16bit_hi -> GR64_ABCD
5974 104, // sub_32bit -> GR64_ABCD
5975 0, // sub_mask_0
5976 0, // sub_mask_1
5977 0, // sub_xmm
5978 0, // sub_ymm
5979 },
5980 { // GR64_with_sub_32bit_in_GR32_TC
5981 105, // sub_8bit -> GR64_with_sub_32bit_in_GR32_TC
5982 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5983 0, // sub_8bit_hi_phony
5984 105, // sub_16bit -> GR64_with_sub_32bit_in_GR32_TC
5985 105, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_TC
5986 105, // sub_32bit -> GR64_with_sub_32bit_in_GR32_TC
5987 0, // sub_mask_0
5988 0, // sub_mask_1
5989 0, // sub_xmm
5990 0, // sub_ymm
5991 },
5992 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5993 106, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5994 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5995 0, // sub_8bit_hi_phony
5996 106, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5997 106, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5998 106, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5999 0, // sub_mask_0
6000 0, // sub_mask_1
6001 0, // sub_xmm
6002 0, // sub_ymm
6003 },
6004 { // GR64_AD
6005 107, // sub_8bit -> GR64_AD
6006 107, // sub_8bit_hi -> GR64_AD
6007 0, // sub_8bit_hi_phony
6008 107, // sub_16bit -> GR64_AD
6009 107, // sub_16bit_hi -> GR64_AD
6010 107, // sub_32bit -> GR64_AD
6011 0, // sub_mask_0
6012 0, // sub_mask_1
6013 0, // sub_xmm
6014 0, // sub_ymm
6015 },
6016 { // GR64_ArgRef
6017 108, // sub_8bit -> GR64_ArgRef
6018 0, // sub_8bit_hi
6019 108, // sub_8bit_hi_phony -> GR64_ArgRef
6020 108, // sub_16bit -> GR64_ArgRef
6021 108, // sub_16bit_hi -> GR64_ArgRef
6022 108, // sub_32bit -> GR64_ArgRef
6023 0, // sub_mask_0
6024 0, // sub_mask_1
6025 0, // sub_xmm
6026 0, // sub_ymm
6027 },
6028 { // GR64_and_LOW32_ADDR_ACCESS_RBP
6029 122, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
6030 0, // sub_8bit_hi
6031 0, // sub_8bit_hi_phony
6032 109, // sub_16bit -> GR64_and_LOW32_ADDR_ACCESS_RBP
6033 109, // sub_16bit_hi -> GR64_and_LOW32_ADDR_ACCESS_RBP
6034 109, // sub_32bit -> GR64_and_LOW32_ADDR_ACCESS_RBP
6035 0, // sub_mask_0
6036 0, // sub_mask_1
6037 0, // sub_xmm
6038 0, // sub_ymm
6039 },
6040 { // GR64_with_sub_32bit_in_GR32_ArgRef
6041 110, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ArgRef
6042 110, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef
6043 0, // sub_8bit_hi_phony
6044 110, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ArgRef
6045 110, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef
6046 110, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ArgRef
6047 0, // sub_mask_0
6048 0, // sub_mask_1
6049 0, // sub_xmm
6050 0, // sub_ymm
6051 },
6052 { // GR64_with_sub_32bit_in_GR32_BPSP
6053 111, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP
6054 0, // sub_8bit_hi
6055 111, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BPSP
6056 111, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP
6057 111, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BPSP
6058 111, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP
6059 0, // sub_mask_0
6060 0, // sub_mask_1
6061 0, // sub_xmm
6062 0, // sub_ymm
6063 },
6064 { // GR64_with_sub_32bit_in_GR32_BSI
6065 112, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BSI
6066 119, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
6067 0, // sub_8bit_hi_phony
6068 112, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BSI
6069 112, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BSI
6070 112, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BSI
6071 0, // sub_mask_0
6072 0, // sub_mask_1
6073 0, // sub_xmm
6074 0, // sub_ymm
6075 },
6076 { // GR64_with_sub_32bit_in_GR32_CB
6077 113, // sub_8bit -> GR64_with_sub_32bit_in_GR32_CB
6078 113, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_CB
6079 0, // sub_8bit_hi_phony
6080 113, // sub_16bit -> GR64_with_sub_32bit_in_GR32_CB
6081 113, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_CB
6082 113, // sub_32bit -> GR64_with_sub_32bit_in_GR32_CB
6083 0, // sub_mask_0
6084 0, // sub_mask_1
6085 0, // sub_xmm
6086 0, // sub_ymm
6087 },
6088 { // GR64_with_sub_32bit_in_GR32_DIBP
6089 114, // sub_8bit -> GR64_with_sub_32bit_in_GR32_DIBP
6090 0, // sub_8bit_hi
6091 114, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_DIBP
6092 114, // sub_16bit -> GR64_with_sub_32bit_in_GR32_DIBP
6093 114, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_DIBP
6094 114, // sub_32bit -> GR64_with_sub_32bit_in_GR32_DIBP
6095 0, // sub_mask_0
6096 0, // sub_mask_1
6097 0, // sub_xmm
6098 0, // sub_ymm
6099 },
6100 { // GR64_with_sub_32bit_in_GR32_SIDI
6101 115, // sub_8bit -> GR64_with_sub_32bit_in_GR32_SIDI
6102 0, // sub_8bit_hi
6103 115, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_SIDI
6104 115, // sub_16bit -> GR64_with_sub_32bit_in_GR32_SIDI
6105 115, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_SIDI
6106 115, // sub_32bit -> GR64_with_sub_32bit_in_GR32_SIDI
6107 0, // sub_mask_0
6108 0, // sub_mask_1
6109 0, // sub_xmm
6110 0, // sub_ymm
6111 },
6112 { // GR64_A
6113 116, // sub_8bit -> GR64_A
6114 116, // sub_8bit_hi -> GR64_A
6115 0, // sub_8bit_hi_phony
6116 116, // sub_16bit -> GR64_A
6117 116, // sub_16bit_hi -> GR64_A
6118 116, // sub_32bit -> GR64_A
6119 0, // sub_mask_0
6120 0, // sub_mask_1
6121 0, // sub_xmm
6122 0, // sub_ymm
6123 },
6124 { // GR64_ArgRef_and_GR64_TC
6125 117, // sub_8bit -> GR64_ArgRef_and_GR64_TC
6126 0, // sub_8bit_hi
6127 117, // sub_8bit_hi_phony -> GR64_ArgRef_and_GR64_TC
6128 117, // sub_16bit -> GR64_ArgRef_and_GR64_TC
6129 117, // sub_16bit_hi -> GR64_ArgRef_and_GR64_TC
6130 117, // sub_32bit -> GR64_ArgRef_and_GR64_TC
6131 0, // sub_mask_0
6132 0, // sub_mask_1
6133 0, // sub_xmm
6134 0, // sub_ymm
6135 },
6136 { // GR64_and_LOW32_ADDR_ACCESS
6137 0, // sub_8bit
6138 0, // sub_8bit_hi
6139 0, // sub_8bit_hi_phony
6140 118, // sub_16bit -> GR64_and_LOW32_ADDR_ACCESS
6141 118, // sub_16bit_hi -> GR64_and_LOW32_ADDR_ACCESS
6142 118, // sub_32bit -> GR64_and_LOW32_ADDR_ACCESS
6143 0, // sub_mask_0
6144 0, // sub_mask_1
6145 0, // sub_xmm
6146 0, // sub_ymm
6147 },
6148 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
6149 119, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
6150 119, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
6151 0, // sub_8bit_hi_phony
6152 119, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
6153 119, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
6154 119, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
6155 0, // sub_mask_0
6156 0, // sub_mask_1
6157 0, // sub_xmm
6158 0, // sub_ymm
6159 },
6160 { // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
6161 120, // sub_8bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
6162 120, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
6163 0, // sub_8bit_hi_phony
6164 120, // sub_16bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
6165 120, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
6166 120, // sub_32bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
6167 0, // sub_mask_0
6168 0, // sub_mask_1
6169 0, // sub_xmm
6170 0, // sub_ymm
6171 },
6172 { // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
6173 121, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
6174 121, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
6175 0, // sub_8bit_hi_phony
6176 121, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
6177 121, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
6178 121, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
6179 0, // sub_mask_0
6180 0, // sub_mask_1
6181 0, // sub_xmm
6182 0, // sub_ymm
6183 },
6184 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
6185 122, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
6186 0, // sub_8bit_hi
6187 122, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
6188 122, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
6189 122, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
6190 122, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
6191 0, // sub_mask_0
6192 0, // sub_mask_1
6193 0, // sub_xmm
6194 0, // sub_ymm
6195 },
6196 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
6197 123, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
6198 0, // sub_8bit_hi
6199 123, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
6200 123, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
6201 123, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
6202 123, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
6203 0, // sub_mask_0
6204 0, // sub_mask_1
6205 0, // sub_xmm
6206 0, // sub_ymm
6207 },
6208 { // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
6209 124, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
6210 0, // sub_8bit_hi
6211 124, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
6212 124, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
6213 124, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
6214 124, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
6215 0, // sub_mask_0
6216 0, // sub_mask_1
6217 0, // sub_xmm
6218 0, // sub_ymm
6219 },
6220 { // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
6221 125, // sub_8bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
6222 0, // sub_8bit_hi
6223 125, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
6224 125, // sub_16bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
6225 125, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
6226 125, // sub_32bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
6227 0, // sub_mask_0
6228 0, // sub_mask_1
6229 0, // sub_xmm
6230 0, // sub_ymm
6231 },
6232 { // RST
6233 0, // sub_8bit
6234 0, // sub_8bit_hi
6235 0, // sub_8bit_hi_phony
6236 0, // sub_16bit
6237 0, // sub_16bit_hi
6238 0, // sub_32bit
6239 0, // sub_mask_0
6240 0, // sub_mask_1
6241 0, // sub_xmm
6242 0, // sub_ymm
6243 },
6244 { // RFP80
6245 0, // sub_8bit
6246 0, // sub_8bit_hi
6247 0, // sub_8bit_hi_phony
6248 0, // sub_16bit
6249 0, // sub_16bit_hi
6250 0, // sub_32bit
6251 0, // sub_mask_0
6252 0, // sub_mask_1
6253 0, // sub_xmm
6254 0, // sub_ymm
6255 },
6256 { // RFP80_7
6257 0, // sub_8bit
6258 0, // sub_8bit_hi
6259 0, // sub_8bit_hi_phony
6260 0, // sub_16bit
6261 0, // sub_16bit_hi
6262 0, // sub_32bit
6263 0, // sub_mask_0
6264 0, // sub_mask_1
6265 0, // sub_xmm
6266 0, // sub_ymm
6267 },
6268 { // VR128X
6269 0, // sub_8bit
6270 0, // sub_8bit_hi
6271 0, // sub_8bit_hi_phony
6272 0, // sub_16bit
6273 0, // sub_16bit_hi
6274 0, // sub_32bit
6275 0, // sub_mask_0
6276 0, // sub_mask_1
6277 0, // sub_xmm
6278 0, // sub_ymm
6279 },
6280 { // VR128
6281 0, // sub_8bit
6282 0, // sub_8bit_hi
6283 0, // sub_8bit_hi_phony
6284 0, // sub_16bit
6285 0, // sub_16bit_hi
6286 0, // sub_32bit
6287 0, // sub_mask_0
6288 0, // sub_mask_1
6289 0, // sub_xmm
6290 0, // sub_ymm
6291 },
6292 { // VR256X
6293 0, // sub_8bit
6294 0, // sub_8bit_hi
6295 0, // sub_8bit_hi_phony
6296 0, // sub_16bit
6297 0, // sub_16bit_hi
6298 0, // sub_32bit
6299 0, // sub_mask_0
6300 0, // sub_mask_1
6301 131, // sub_xmm -> VR256X
6302 0, // sub_ymm
6303 },
6304 { // VR256
6305 0, // sub_8bit
6306 0, // sub_8bit_hi
6307 0, // sub_8bit_hi_phony
6308 0, // sub_16bit
6309 0, // sub_16bit_hi
6310 0, // sub_32bit
6311 0, // sub_mask_0
6312 0, // sub_mask_1
6313 132, // sub_xmm -> VR256
6314 0, // sub_ymm
6315 },
6316 { // VR512
6317 0, // sub_8bit
6318 0, // sub_8bit_hi
6319 0, // sub_8bit_hi_phony
6320 0, // sub_16bit
6321 0, // sub_16bit_hi
6322 0, // sub_32bit
6323 0, // sub_mask_0
6324 0, // sub_mask_1
6325 133, // sub_xmm -> VR512
6326 133, // sub_ymm -> VR512
6327 },
6328 { // VR512_0_15
6329 0, // sub_8bit
6330 0, // sub_8bit_hi
6331 0, // sub_8bit_hi_phony
6332 0, // sub_16bit
6333 0, // sub_16bit_hi
6334 0, // sub_32bit
6335 0, // sub_mask_0
6336 0, // sub_mask_1
6337 134, // sub_xmm -> VR512_0_15
6338 134, // sub_ymm -> VR512_0_15
6339 },
6340 { // TILE
6341 0, // sub_8bit
6342 0, // sub_8bit_hi
6343 0, // sub_8bit_hi_phony
6344 0, // sub_16bit
6345 0, // sub_16bit_hi
6346 0, // sub_32bit
6347 0, // sub_mask_0
6348 0, // sub_mask_1
6349 0, // sub_xmm
6350 0, // sub_ymm
6351 },
6352
6353 };
6354 assert(RC && "Missing regclass");
6355 if (!Idx) return RC;
6356 --Idx;
6357 assert(Idx < 10 && "Bad subreg");
6358 unsigned TV = Table[RC->getID()][Idx];
6359 return TV ? getRegClass(i: TV - 1) : nullptr;
6360}const TargetRegisterClass *X86GenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
6361 static constexpr uint8_t Table[135][10] = {
6362 { // GR8
6363 0, // GR8:sub_8bit
6364 0, // GR8:sub_8bit_hi
6365 0, // GR8:sub_8bit_hi_phony
6366 0, // GR8:sub_16bit
6367 0, // GR8:sub_16bit_hi
6368 0, // GR8:sub_32bit
6369 0, // GR8:sub_mask_0
6370 0, // GR8:sub_mask_1
6371 0, // GR8:sub_xmm
6372 0, // GR8:sub_ymm
6373 },
6374 { // GRH8
6375 0, // GRH8:sub_8bit
6376 0, // GRH8:sub_8bit_hi
6377 0, // GRH8:sub_8bit_hi_phony
6378 0, // GRH8:sub_16bit
6379 0, // GRH8:sub_16bit_hi
6380 0, // GRH8:sub_32bit
6381 0, // GRH8:sub_mask_0
6382 0, // GRH8:sub_mask_1
6383 0, // GRH8:sub_xmm
6384 0, // GRH8:sub_ymm
6385 },
6386 { // GR8_NOREX2
6387 0, // GR8_NOREX2:sub_8bit
6388 0, // GR8_NOREX2:sub_8bit_hi
6389 0, // GR8_NOREX2:sub_8bit_hi_phony
6390 0, // GR8_NOREX2:sub_16bit
6391 0, // GR8_NOREX2:sub_16bit_hi
6392 0, // GR8_NOREX2:sub_32bit
6393 0, // GR8_NOREX2:sub_mask_0
6394 0, // GR8_NOREX2:sub_mask_1
6395 0, // GR8_NOREX2:sub_xmm
6396 0, // GR8_NOREX2:sub_ymm
6397 },
6398 { // GR8_NOREX
6399 0, // GR8_NOREX:sub_8bit
6400 0, // GR8_NOREX:sub_8bit_hi
6401 0, // GR8_NOREX:sub_8bit_hi_phony
6402 0, // GR8_NOREX:sub_16bit
6403 0, // GR8_NOREX:sub_16bit_hi
6404 0, // GR8_NOREX:sub_32bit
6405 0, // GR8_NOREX:sub_mask_0
6406 0, // GR8_NOREX:sub_mask_1
6407 0, // GR8_NOREX:sub_xmm
6408 0, // GR8_NOREX:sub_ymm
6409 },
6410 { // GR8_ABCD_H
6411 0, // GR8_ABCD_H:sub_8bit
6412 0, // GR8_ABCD_H:sub_8bit_hi
6413 0, // GR8_ABCD_H:sub_8bit_hi_phony
6414 0, // GR8_ABCD_H:sub_16bit
6415 0, // GR8_ABCD_H:sub_16bit_hi
6416 0, // GR8_ABCD_H:sub_32bit
6417 0, // GR8_ABCD_H:sub_mask_0
6418 0, // GR8_ABCD_H:sub_mask_1
6419 0, // GR8_ABCD_H:sub_xmm
6420 0, // GR8_ABCD_H:sub_ymm
6421 },
6422 { // GR8_ABCD_L
6423 0, // GR8_ABCD_L:sub_8bit
6424 0, // GR8_ABCD_L:sub_8bit_hi
6425 0, // GR8_ABCD_L:sub_8bit_hi_phony
6426 0, // GR8_ABCD_L:sub_16bit
6427 0, // GR8_ABCD_L:sub_16bit_hi
6428 0, // GR8_ABCD_L:sub_32bit
6429 0, // GR8_ABCD_L:sub_mask_0
6430 0, // GR8_ABCD_L:sub_mask_1
6431 0, // GR8_ABCD_L:sub_xmm
6432 0, // GR8_ABCD_L:sub_ymm
6433 },
6434 { // GRH16
6435 0, // GRH16:sub_8bit
6436 0, // GRH16:sub_8bit_hi
6437 0, // GRH16:sub_8bit_hi_phony
6438 0, // GRH16:sub_16bit
6439 0, // GRH16:sub_16bit_hi
6440 0, // GRH16:sub_32bit
6441 0, // GRH16:sub_mask_0
6442 0, // GRH16:sub_mask_1
6443 0, // GRH16:sub_xmm
6444 0, // GRH16:sub_ymm
6445 },
6446 { // GR16
6447 1, // GR16:sub_8bit -> GR8
6448 5, // GR16:sub_8bit_hi -> GR8_ABCD_H
6449 0, // GR16:sub_8bit_hi_phony
6450 0, // GR16:sub_16bit
6451 0, // GR16:sub_16bit_hi
6452 0, // GR16:sub_32bit
6453 0, // GR16:sub_mask_0
6454 0, // GR16:sub_mask_1
6455 0, // GR16:sub_xmm
6456 0, // GR16:sub_ymm
6457 },
6458 { // GR16_NOREX2
6459 3, // GR16_NOREX2:sub_8bit -> GR8_NOREX2
6460 5, // GR16_NOREX2:sub_8bit_hi -> GR8_ABCD_H
6461 0, // GR16_NOREX2:sub_8bit_hi_phony
6462 0, // GR16_NOREX2:sub_16bit
6463 0, // GR16_NOREX2:sub_16bit_hi
6464 0, // GR16_NOREX2:sub_32bit
6465 0, // GR16_NOREX2:sub_mask_0
6466 0, // GR16_NOREX2:sub_mask_1
6467 0, // GR16_NOREX2:sub_xmm
6468 0, // GR16_NOREX2:sub_ymm
6469 },
6470 { // GR16_NOREX
6471 3, // GR16_NOREX:sub_8bit -> GR8_NOREX2
6472 5, // GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
6473 0, // GR16_NOREX:sub_8bit_hi_phony
6474 0, // GR16_NOREX:sub_16bit
6475 0, // GR16_NOREX:sub_16bit_hi
6476 0, // GR16_NOREX:sub_32bit
6477 0, // GR16_NOREX:sub_mask_0
6478 0, // GR16_NOREX:sub_mask_1
6479 0, // GR16_NOREX:sub_xmm
6480 0, // GR16_NOREX:sub_ymm
6481 },
6482 { // VK1
6483 0, // VK1:sub_8bit
6484 0, // VK1:sub_8bit_hi
6485 0, // VK1:sub_8bit_hi_phony
6486 0, // VK1:sub_16bit
6487 0, // VK1:sub_16bit_hi
6488 0, // VK1:sub_32bit
6489 0, // VK1:sub_mask_0
6490 0, // VK1:sub_mask_1
6491 0, // VK1:sub_xmm
6492 0, // VK1:sub_ymm
6493 },
6494 { // VK16
6495 0, // VK16:sub_8bit
6496 0, // VK16:sub_8bit_hi
6497 0, // VK16:sub_8bit_hi_phony
6498 0, // VK16:sub_16bit
6499 0, // VK16:sub_16bit_hi
6500 0, // VK16:sub_32bit
6501 0, // VK16:sub_mask_0
6502 0, // VK16:sub_mask_1
6503 0, // VK16:sub_xmm
6504 0, // VK16:sub_ymm
6505 },
6506 { // VK2
6507 0, // VK2:sub_8bit
6508 0, // VK2:sub_8bit_hi
6509 0, // VK2:sub_8bit_hi_phony
6510 0, // VK2:sub_16bit
6511 0, // VK2:sub_16bit_hi
6512 0, // VK2:sub_32bit
6513 0, // VK2:sub_mask_0
6514 0, // VK2:sub_mask_1
6515 0, // VK2:sub_xmm
6516 0, // VK2:sub_ymm
6517 },
6518 { // VK4
6519 0, // VK4:sub_8bit
6520 0, // VK4:sub_8bit_hi
6521 0, // VK4:sub_8bit_hi_phony
6522 0, // VK4:sub_16bit
6523 0, // VK4:sub_16bit_hi
6524 0, // VK4:sub_32bit
6525 0, // VK4:sub_mask_0
6526 0, // VK4:sub_mask_1
6527 0, // VK4:sub_xmm
6528 0, // VK4:sub_ymm
6529 },
6530 { // VK8
6531 0, // VK8:sub_8bit
6532 0, // VK8:sub_8bit_hi
6533 0, // VK8:sub_8bit_hi_phony
6534 0, // VK8:sub_16bit
6535 0, // VK8:sub_16bit_hi
6536 0, // VK8:sub_32bit
6537 0, // VK8:sub_mask_0
6538 0, // VK8:sub_mask_1
6539 0, // VK8:sub_xmm
6540 0, // VK8:sub_ymm
6541 },
6542 { // VK16WM
6543 0, // VK16WM:sub_8bit
6544 0, // VK16WM:sub_8bit_hi
6545 0, // VK16WM:sub_8bit_hi_phony
6546 0, // VK16WM:sub_16bit
6547 0, // VK16WM:sub_16bit_hi
6548 0, // VK16WM:sub_32bit
6549 0, // VK16WM:sub_mask_0
6550 0, // VK16WM:sub_mask_1
6551 0, // VK16WM:sub_xmm
6552 0, // VK16WM:sub_ymm
6553 },
6554 { // VK1WM
6555 0, // VK1WM:sub_8bit
6556 0, // VK1WM:sub_8bit_hi
6557 0, // VK1WM:sub_8bit_hi_phony
6558 0, // VK1WM:sub_16bit
6559 0, // VK1WM:sub_16bit_hi
6560 0, // VK1WM:sub_32bit
6561 0, // VK1WM:sub_mask_0
6562 0, // VK1WM:sub_mask_1
6563 0, // VK1WM:sub_xmm
6564 0, // VK1WM:sub_ymm
6565 },
6566 { // VK2WM
6567 0, // VK2WM:sub_8bit
6568 0, // VK2WM:sub_8bit_hi
6569 0, // VK2WM:sub_8bit_hi_phony
6570 0, // VK2WM:sub_16bit
6571 0, // VK2WM:sub_16bit_hi
6572 0, // VK2WM:sub_32bit
6573 0, // VK2WM:sub_mask_0
6574 0, // VK2WM:sub_mask_1
6575 0, // VK2WM:sub_xmm
6576 0, // VK2WM:sub_ymm
6577 },
6578 { // VK4WM
6579 0, // VK4WM:sub_8bit
6580 0, // VK4WM:sub_8bit_hi
6581 0, // VK4WM:sub_8bit_hi_phony
6582 0, // VK4WM:sub_16bit
6583 0, // VK4WM:sub_16bit_hi
6584 0, // VK4WM:sub_32bit
6585 0, // VK4WM:sub_mask_0
6586 0, // VK4WM:sub_mask_1
6587 0, // VK4WM:sub_xmm
6588 0, // VK4WM:sub_ymm
6589 },
6590 { // VK8WM
6591 0, // VK8WM:sub_8bit
6592 0, // VK8WM:sub_8bit_hi
6593 0, // VK8WM:sub_8bit_hi_phony
6594 0, // VK8WM:sub_16bit
6595 0, // VK8WM:sub_16bit_hi
6596 0, // VK8WM:sub_32bit
6597 0, // VK8WM:sub_mask_0
6598 0, // VK8WM:sub_mask_1
6599 0, // VK8WM:sub_xmm
6600 0, // VK8WM:sub_ymm
6601 },
6602 { // SEGMENT_REG
6603 0, // SEGMENT_REG:sub_8bit
6604 0, // SEGMENT_REG:sub_8bit_hi
6605 0, // SEGMENT_REG:sub_8bit_hi_phony
6606 0, // SEGMENT_REG:sub_16bit
6607 0, // SEGMENT_REG:sub_16bit_hi
6608 0, // SEGMENT_REG:sub_32bit
6609 0, // SEGMENT_REG:sub_mask_0
6610 0, // SEGMENT_REG:sub_mask_1
6611 0, // SEGMENT_REG:sub_xmm
6612 0, // SEGMENT_REG:sub_ymm
6613 },
6614 { // GR16_ABCD
6615 6, // GR16_ABCD:sub_8bit -> GR8_ABCD_L
6616 5, // GR16_ABCD:sub_8bit_hi -> GR8_ABCD_H
6617 0, // GR16_ABCD:sub_8bit_hi_phony
6618 0, // GR16_ABCD:sub_16bit
6619 0, // GR16_ABCD:sub_16bit_hi
6620 0, // GR16_ABCD:sub_32bit
6621 0, // GR16_ABCD:sub_mask_0
6622 0, // GR16_ABCD:sub_mask_1
6623 0, // GR16_ABCD:sub_xmm
6624 0, // GR16_ABCD:sub_ymm
6625 },
6626 { // FPCCR
6627 0, // FPCCR:sub_8bit
6628 0, // FPCCR:sub_8bit_hi
6629 0, // FPCCR:sub_8bit_hi_phony
6630 0, // FPCCR:sub_16bit
6631 0, // FPCCR:sub_16bit_hi
6632 0, // FPCCR:sub_32bit
6633 0, // FPCCR:sub_mask_0
6634 0, // FPCCR:sub_mask_1
6635 0, // FPCCR:sub_xmm
6636 0, // FPCCR:sub_ymm
6637 },
6638 { // FR16X
6639 0, // FR16X:sub_8bit
6640 0, // FR16X:sub_8bit_hi
6641 0, // FR16X:sub_8bit_hi_phony
6642 0, // FR16X:sub_16bit
6643 0, // FR16X:sub_16bit_hi
6644 0, // FR16X:sub_32bit
6645 0, // FR16X:sub_mask_0
6646 0, // FR16X:sub_mask_1
6647 0, // FR16X:sub_xmm
6648 0, // FR16X:sub_ymm
6649 },
6650 { // FR16
6651 0, // FR16:sub_8bit
6652 0, // FR16:sub_8bit_hi
6653 0, // FR16:sub_8bit_hi_phony
6654 0, // FR16:sub_16bit
6655 0, // FR16:sub_16bit_hi
6656 0, // FR16:sub_32bit
6657 0, // FR16:sub_mask_0
6658 0, // FR16:sub_mask_1
6659 0, // FR16:sub_xmm
6660 0, // FR16:sub_ymm
6661 },
6662 { // VK16PAIR
6663 0, // VK16PAIR:sub_8bit
6664 0, // VK16PAIR:sub_8bit_hi
6665 0, // VK16PAIR:sub_8bit_hi_phony
6666 0, // VK16PAIR:sub_16bit
6667 0, // VK16PAIR:sub_16bit_hi
6668 0, // VK16PAIR:sub_32bit
6669 91, // VK16PAIR:sub_mask_0 -> VK64
6670 98, // VK16PAIR:sub_mask_1 -> VK64WM
6671 0, // VK16PAIR:sub_xmm
6672 0, // VK16PAIR:sub_ymm
6673 },
6674 { // VK1PAIR
6675 0, // VK1PAIR:sub_8bit
6676 0, // VK1PAIR:sub_8bit_hi
6677 0, // VK1PAIR:sub_8bit_hi_phony
6678 0, // VK1PAIR:sub_16bit
6679 0, // VK1PAIR:sub_16bit_hi
6680 0, // VK1PAIR:sub_32bit
6681 91, // VK1PAIR:sub_mask_0 -> VK64
6682 98, // VK1PAIR:sub_mask_1 -> VK64WM
6683 0, // VK1PAIR:sub_xmm
6684 0, // VK1PAIR:sub_ymm
6685 },
6686 { // VK2PAIR
6687 0, // VK2PAIR:sub_8bit
6688 0, // VK2PAIR:sub_8bit_hi
6689 0, // VK2PAIR:sub_8bit_hi_phony
6690 0, // VK2PAIR:sub_16bit
6691 0, // VK2PAIR:sub_16bit_hi
6692 0, // VK2PAIR:sub_32bit
6693 91, // VK2PAIR:sub_mask_0 -> VK64
6694 98, // VK2PAIR:sub_mask_1 -> VK64WM
6695 0, // VK2PAIR:sub_xmm
6696 0, // VK2PAIR:sub_ymm
6697 },
6698 { // VK4PAIR
6699 0, // VK4PAIR:sub_8bit
6700 0, // VK4PAIR:sub_8bit_hi
6701 0, // VK4PAIR:sub_8bit_hi_phony
6702 0, // VK4PAIR:sub_16bit
6703 0, // VK4PAIR:sub_16bit_hi
6704 0, // VK4PAIR:sub_32bit
6705 91, // VK4PAIR:sub_mask_0 -> VK64
6706 98, // VK4PAIR:sub_mask_1 -> VK64WM
6707 0, // VK4PAIR:sub_xmm
6708 0, // VK4PAIR:sub_ymm
6709 },
6710 { // VK8PAIR
6711 0, // VK8PAIR:sub_8bit
6712 0, // VK8PAIR:sub_8bit_hi
6713 0, // VK8PAIR:sub_8bit_hi_phony
6714 0, // VK8PAIR:sub_16bit
6715 0, // VK8PAIR:sub_16bit_hi
6716 0, // VK8PAIR:sub_32bit
6717 91, // VK8PAIR:sub_mask_0 -> VK64
6718 98, // VK8PAIR:sub_mask_1 -> VK64WM
6719 0, // VK8PAIR:sub_xmm
6720 0, // VK8PAIR:sub_ymm
6721 },
6722 { // VK1PAIR_with_sub_mask_0_in_VK1WM
6723 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_8bit
6724 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_8bit_hi
6725 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_8bit_hi_phony
6726 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_16bit
6727 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_16bit_hi
6728 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_32bit
6729 98, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_mask_0 -> VK64WM
6730 98, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_mask_1 -> VK64WM
6731 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_xmm
6732 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_ymm
6733 },
6734 { // LOW32_ADDR_ACCESS_RBP
6735 1, // LOW32_ADDR_ACCESS_RBP:sub_8bit -> GR8
6736 5, // LOW32_ADDR_ACCESS_RBP:sub_8bit_hi -> GR8_ABCD_H
6737 0, // LOW32_ADDR_ACCESS_RBP:sub_8bit_hi_phony
6738 8, // LOW32_ADDR_ACCESS_RBP:sub_16bit -> GR16
6739 0, // LOW32_ADDR_ACCESS_RBP:sub_16bit_hi
6740 66, // LOW32_ADDR_ACCESS_RBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
6741 0, // LOW32_ADDR_ACCESS_RBP:sub_mask_0
6742 0, // LOW32_ADDR_ACCESS_RBP:sub_mask_1
6743 0, // LOW32_ADDR_ACCESS_RBP:sub_xmm
6744 0, // LOW32_ADDR_ACCESS_RBP:sub_ymm
6745 },
6746 { // LOW32_ADDR_ACCESS
6747 1, // LOW32_ADDR_ACCESS:sub_8bit -> GR8
6748 5, // LOW32_ADDR_ACCESS:sub_8bit_hi -> GR8_ABCD_H
6749 0, // LOW32_ADDR_ACCESS:sub_8bit_hi_phony
6750 8, // LOW32_ADDR_ACCESS:sub_16bit -> GR16
6751 0, // LOW32_ADDR_ACCESS:sub_16bit_hi
6752 0, // LOW32_ADDR_ACCESS:sub_32bit
6753 0, // LOW32_ADDR_ACCESS:sub_mask_0
6754 0, // LOW32_ADDR_ACCESS:sub_mask_1
6755 0, // LOW32_ADDR_ACCESS:sub_xmm
6756 0, // LOW32_ADDR_ACCESS:sub_ymm
6757 },
6758 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
6759 1, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit -> GR8
6760 5, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
6761 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit_hi_phony
6762 8, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_16bit -> GR16
6763 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_16bit_hi
6764 66, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
6765 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_mask_0
6766 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_mask_1
6767 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_xmm
6768 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_ymm
6769 },
6770 { // FR32X
6771 0, // FR32X:sub_8bit
6772 0, // FR32X:sub_8bit_hi
6773 0, // FR32X:sub_8bit_hi_phony
6774 0, // FR32X:sub_16bit
6775 0, // FR32X:sub_16bit_hi
6776 0, // FR32X:sub_32bit
6777 0, // FR32X:sub_mask_0
6778 0, // FR32X:sub_mask_1
6779 0, // FR32X:sub_xmm
6780 0, // FR32X:sub_ymm
6781 },
6782 { // GR32
6783 1, // GR32:sub_8bit -> GR8
6784 5, // GR32:sub_8bit_hi -> GR8_ABCD_H
6785 0, // GR32:sub_8bit_hi_phony
6786 8, // GR32:sub_16bit -> GR16
6787 0, // GR32:sub_16bit_hi
6788 0, // GR32:sub_32bit
6789 0, // GR32:sub_mask_0
6790 0, // GR32:sub_mask_1
6791 0, // GR32:sub_xmm
6792 0, // GR32:sub_ymm
6793 },
6794 { // GR32_NOSP
6795 1, // GR32_NOSP:sub_8bit -> GR8
6796 5, // GR32_NOSP:sub_8bit_hi -> GR8_ABCD_H
6797 0, // GR32_NOSP:sub_8bit_hi_phony
6798 8, // GR32_NOSP:sub_16bit -> GR16
6799 0, // GR32_NOSP:sub_16bit_hi
6800 0, // GR32_NOSP:sub_32bit
6801 0, // GR32_NOSP:sub_mask_0
6802 0, // GR32_NOSP:sub_mask_1
6803 0, // GR32_NOSP:sub_xmm
6804 0, // GR32_NOSP:sub_ymm
6805 },
6806 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
6807 3, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_8bit -> GR8_NOREX2
6808 5, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi -> GR8_ABCD_H
6809 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi_phony
6810 9, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_16bit -> GR16_NOREX2
6811 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_16bit_hi
6812 66, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_32bit -> GR32_BPSP_and_GR32_DIBP
6813 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_mask_0
6814 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_mask_1
6815 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_xmm
6816 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_ymm
6817 },
6818 { // DEBUG_REG
6819 0, // DEBUG_REG:sub_8bit
6820 0, // DEBUG_REG:sub_8bit_hi
6821 0, // DEBUG_REG:sub_8bit_hi_phony
6822 0, // DEBUG_REG:sub_16bit
6823 0, // DEBUG_REG:sub_16bit_hi
6824 0, // DEBUG_REG:sub_32bit
6825 0, // DEBUG_REG:sub_mask_0
6826 0, // DEBUG_REG:sub_mask_1
6827 0, // DEBUG_REG:sub_xmm
6828 0, // DEBUG_REG:sub_ymm
6829 },
6830 { // FR32
6831 0, // FR32:sub_8bit
6832 0, // FR32:sub_8bit_hi
6833 0, // FR32:sub_8bit_hi_phony
6834 0, // FR32:sub_16bit
6835 0, // FR32:sub_16bit_hi
6836 0, // FR32:sub_32bit
6837 0, // FR32:sub_mask_0
6838 0, // FR32:sub_mask_1
6839 0, // FR32:sub_xmm
6840 0, // FR32:sub_ymm
6841 },
6842 { // GR32_NOREX2
6843 3, // GR32_NOREX2:sub_8bit -> GR8_NOREX2
6844 5, // GR32_NOREX2:sub_8bit_hi -> GR8_ABCD_H
6845 0, // GR32_NOREX2:sub_8bit_hi_phony
6846 9, // GR32_NOREX2:sub_16bit -> GR16_NOREX2
6847 0, // GR32_NOREX2:sub_16bit_hi
6848 0, // GR32_NOREX2:sub_32bit
6849 0, // GR32_NOREX2:sub_mask_0
6850 0, // GR32_NOREX2:sub_mask_1
6851 0, // GR32_NOREX2:sub_xmm
6852 0, // GR32_NOREX2:sub_ymm
6853 },
6854 { // GR32_NOREX2_NOSP
6855 3, // GR32_NOREX2_NOSP:sub_8bit -> GR8_NOREX2
6856 5, // GR32_NOREX2_NOSP:sub_8bit_hi -> GR8_ABCD_H
6857 0, // GR32_NOREX2_NOSP:sub_8bit_hi_phony
6858 9, // GR32_NOREX2_NOSP:sub_16bit -> GR16_NOREX2
6859 0, // GR32_NOREX2_NOSP:sub_16bit_hi
6860 0, // GR32_NOREX2_NOSP:sub_32bit
6861 0, // GR32_NOREX2_NOSP:sub_mask_0
6862 0, // GR32_NOREX2_NOSP:sub_mask_1
6863 0, // GR32_NOREX2_NOSP:sub_xmm
6864 0, // GR32_NOREX2_NOSP:sub_ymm
6865 },
6866 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
6867 3, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8_NOREX2
6868 5, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
6869 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
6870 10, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
6871 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
6872 66, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_BPSP_and_GR32_DIBP
6873 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_mask_0
6874 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_mask_1
6875 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_xmm
6876 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_ymm
6877 },
6878 { // GR32_NOREX
6879 3, // GR32_NOREX:sub_8bit -> GR8_NOREX2
6880 5, // GR32_NOREX:sub_8bit_hi -> GR8_ABCD_H
6881 0, // GR32_NOREX:sub_8bit_hi_phony
6882 10, // GR32_NOREX:sub_16bit -> GR16_NOREX
6883 0, // GR32_NOREX:sub_16bit_hi
6884 0, // GR32_NOREX:sub_32bit
6885 0, // GR32_NOREX:sub_mask_0
6886 0, // GR32_NOREX:sub_mask_1
6887 0, // GR32_NOREX:sub_xmm
6888 0, // GR32_NOREX:sub_ymm
6889 },
6890 { // VK32
6891 0, // VK32:sub_8bit
6892 0, // VK32:sub_8bit_hi
6893 0, // VK32:sub_8bit_hi_phony
6894 0, // VK32:sub_16bit
6895 0, // VK32:sub_16bit_hi
6896 0, // VK32:sub_32bit
6897 0, // VK32:sub_mask_0
6898 0, // VK32:sub_mask_1
6899 0, // VK32:sub_xmm
6900 0, // VK32:sub_ymm
6901 },
6902 { // GR32_NOREX_NOSP
6903 3, // GR32_NOREX_NOSP:sub_8bit -> GR8_NOREX2
6904 5, // GR32_NOREX_NOSP:sub_8bit_hi -> GR8_ABCD_H
6905 0, // GR32_NOREX_NOSP:sub_8bit_hi_phony
6906 10, // GR32_NOREX_NOSP:sub_16bit -> GR16_NOREX
6907 0, // GR32_NOREX_NOSP:sub_16bit_hi
6908 0, // GR32_NOREX_NOSP:sub_32bit
6909 0, // GR32_NOREX_NOSP:sub_mask_0
6910 0, // GR32_NOREX_NOSP:sub_mask_1
6911 0, // GR32_NOREX_NOSP:sub_xmm
6912 0, // GR32_NOREX_NOSP:sub_ymm
6913 },
6914 { // RFP32
6915 0, // RFP32:sub_8bit
6916 0, // RFP32:sub_8bit_hi
6917 0, // RFP32:sub_8bit_hi_phony
6918 0, // RFP32:sub_16bit
6919 0, // RFP32:sub_16bit_hi
6920 0, // RFP32:sub_32bit
6921 0, // RFP32:sub_mask_0
6922 0, // RFP32:sub_mask_1
6923 0, // RFP32:sub_xmm
6924 0, // RFP32:sub_ymm
6925 },
6926 { // VK32WM
6927 0, // VK32WM:sub_8bit
6928 0, // VK32WM:sub_8bit_hi
6929 0, // VK32WM:sub_8bit_hi_phony
6930 0, // VK32WM:sub_16bit
6931 0, // VK32WM:sub_16bit_hi
6932 0, // VK32WM:sub_32bit
6933 0, // VK32WM:sub_mask_0
6934 0, // VK32WM:sub_mask_1
6935 0, // VK32WM:sub_xmm
6936 0, // VK32WM:sub_ymm
6937 },
6938 { // GR32_ABCD
6939 6, // GR32_ABCD:sub_8bit -> GR8_ABCD_L
6940 5, // GR32_ABCD:sub_8bit_hi -> GR8_ABCD_H
6941 0, // GR32_ABCD:sub_8bit_hi_phony
6942 22, // GR32_ABCD:sub_16bit -> GR16_ABCD
6943 0, // GR32_ABCD:sub_16bit_hi
6944 0, // GR32_ABCD:sub_32bit
6945 0, // GR32_ABCD:sub_mask_0
6946 0, // GR32_ABCD:sub_mask_1
6947 0, // GR32_ABCD:sub_xmm
6948 0, // GR32_ABCD:sub_ymm
6949 },
6950 { // GR32_TC
6951 3, // GR32_TC:sub_8bit -> GR8_NOREX2
6952 5, // GR32_TC:sub_8bit_hi -> GR8_ABCD_H
6953 0, // GR32_TC:sub_8bit_hi_phony
6954 10, // GR32_TC:sub_16bit -> GR16_NOREX
6955 0, // GR32_TC:sub_16bit_hi
6956 0, // GR32_TC:sub_32bit
6957 0, // GR32_TC:sub_mask_0
6958 0, // GR32_TC:sub_mask_1
6959 0, // GR32_TC:sub_xmm
6960 0, // GR32_TC:sub_ymm
6961 },
6962 { // GR32_ABCD_and_GR32_TC
6963 6, // GR32_ABCD_and_GR32_TC:sub_8bit -> GR8_ABCD_L
6964 5, // GR32_ABCD_and_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
6965 0, // GR32_ABCD_and_GR32_TC:sub_8bit_hi_phony
6966 22, // GR32_ABCD_and_GR32_TC:sub_16bit -> GR16_ABCD
6967 0, // GR32_ABCD_and_GR32_TC:sub_16bit_hi
6968 0, // GR32_ABCD_and_GR32_TC:sub_32bit
6969 0, // GR32_ABCD_and_GR32_TC:sub_mask_0
6970 0, // GR32_ABCD_and_GR32_TC:sub_mask_1
6971 0, // GR32_ABCD_and_GR32_TC:sub_xmm
6972 0, // GR32_ABCD_and_GR32_TC:sub_ymm
6973 },
6974 { // GR32_AD
6975 6, // GR32_AD:sub_8bit -> GR8_ABCD_L
6976 5, // GR32_AD:sub_8bit_hi -> GR8_ABCD_H
6977 0, // GR32_AD:sub_8bit_hi_phony
6978 22, // GR32_AD:sub_16bit -> GR16_ABCD
6979 0, // GR32_AD:sub_16bit_hi
6980 0, // GR32_AD:sub_32bit
6981 0, // GR32_AD:sub_mask_0
6982 0, // GR32_AD:sub_mask_1
6983 0, // GR32_AD:sub_xmm
6984 0, // GR32_AD:sub_ymm
6985 },
6986 { // GR32_ArgRef
6987 6, // GR32_ArgRef:sub_8bit -> GR8_ABCD_L
6988 5, // GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
6989 0, // GR32_ArgRef:sub_8bit_hi_phony
6990 22, // GR32_ArgRef:sub_16bit -> GR16_ABCD
6991 0, // GR32_ArgRef:sub_16bit_hi
6992 0, // GR32_ArgRef:sub_32bit
6993 0, // GR32_ArgRef:sub_mask_0
6994 0, // GR32_ArgRef:sub_mask_1
6995 0, // GR32_ArgRef:sub_xmm
6996 0, // GR32_ArgRef:sub_ymm
6997 },
6998 { // GR32_BPSP
6999 3, // GR32_BPSP:sub_8bit -> GR8_NOREX2
7000 0, // GR32_BPSP:sub_8bit_hi
7001 0, // GR32_BPSP:sub_8bit_hi_phony
7002 10, // GR32_BPSP:sub_16bit -> GR16_NOREX
7003 0, // GR32_BPSP:sub_16bit_hi
7004 0, // GR32_BPSP:sub_32bit
7005 0, // GR32_BPSP:sub_mask_0
7006 0, // GR32_BPSP:sub_mask_1
7007 0, // GR32_BPSP:sub_xmm
7008 0, // GR32_BPSP:sub_ymm
7009 },
7010 { // GR32_BSI
7011 3, // GR32_BSI:sub_8bit -> GR8_NOREX2
7012 5, // GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
7013 0, // GR32_BSI:sub_8bit_hi_phony
7014 10, // GR32_BSI:sub_16bit -> GR16_NOREX
7015 0, // GR32_BSI:sub_16bit_hi
7016 0, // GR32_BSI:sub_32bit
7017 0, // GR32_BSI:sub_mask_0
7018 0, // GR32_BSI:sub_mask_1
7019 0, // GR32_BSI:sub_xmm
7020 0, // GR32_BSI:sub_ymm
7021 },
7022 { // GR32_CB
7023 6, // GR32_CB:sub_8bit -> GR8_ABCD_L
7024 5, // GR32_CB:sub_8bit_hi -> GR8_ABCD_H
7025 0, // GR32_CB:sub_8bit_hi_phony
7026 22, // GR32_CB:sub_16bit -> GR16_ABCD
7027 0, // GR32_CB:sub_16bit_hi
7028 0, // GR32_CB:sub_32bit
7029 0, // GR32_CB:sub_mask_0
7030 0, // GR32_CB:sub_mask_1
7031 0, // GR32_CB:sub_xmm
7032 0, // GR32_CB:sub_ymm
7033 },
7034 { // GR32_DC
7035 6, // GR32_DC:sub_8bit -> GR8_ABCD_L
7036 5, // GR32_DC:sub_8bit_hi -> GR8_ABCD_H
7037 0, // GR32_DC:sub_8bit_hi_phony
7038 22, // GR32_DC:sub_16bit -> GR16_ABCD
7039 0, // GR32_DC:sub_16bit_hi
7040 0, // GR32_DC:sub_32bit
7041 0, // GR32_DC:sub_mask_0
7042 0, // GR32_DC:sub_mask_1
7043 0, // GR32_DC:sub_xmm
7044 0, // GR32_DC:sub_ymm
7045 },
7046 { // GR32_DIBP
7047 3, // GR32_DIBP:sub_8bit -> GR8_NOREX2
7048 0, // GR32_DIBP:sub_8bit_hi
7049 0, // GR32_DIBP:sub_8bit_hi_phony
7050 10, // GR32_DIBP:sub_16bit -> GR16_NOREX
7051 0, // GR32_DIBP:sub_16bit_hi
7052 0, // GR32_DIBP:sub_32bit
7053 0, // GR32_DIBP:sub_mask_0
7054 0, // GR32_DIBP:sub_mask_1
7055 0, // GR32_DIBP:sub_xmm
7056 0, // GR32_DIBP:sub_ymm
7057 },
7058 { // GR32_SIDI
7059 3, // GR32_SIDI:sub_8bit -> GR8_NOREX2
7060 0, // GR32_SIDI:sub_8bit_hi
7061 0, // GR32_SIDI:sub_8bit_hi_phony
7062 10, // GR32_SIDI:sub_16bit -> GR16_NOREX
7063 0, // GR32_SIDI:sub_16bit_hi
7064 0, // GR32_SIDI:sub_32bit
7065 0, // GR32_SIDI:sub_mask_0
7066 0, // GR32_SIDI:sub_mask_1
7067 0, // GR32_SIDI:sub_xmm
7068 0, // GR32_SIDI:sub_ymm
7069 },
7070 { // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
7071 3, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit -> GR8_NOREX2
7072 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit_hi
7073 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit_hi_phony
7074 10, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_16bit -> GR16_NOREX
7075 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_16bit_hi
7076 66, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
7077 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_mask_0
7078 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_mask_1
7079 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_xmm
7080 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_ymm
7081 },
7082 { // CCR
7083 0, // CCR:sub_8bit
7084 0, // CCR:sub_8bit_hi
7085 0, // CCR:sub_8bit_hi_phony
7086 0, // CCR:sub_16bit
7087 0, // CCR:sub_16bit_hi
7088 0, // CCR:sub_32bit
7089 0, // CCR:sub_mask_0
7090 0, // CCR:sub_mask_1
7091 0, // CCR:sub_xmm
7092 0, // CCR:sub_ymm
7093 },
7094 { // DFCCR
7095 0, // DFCCR:sub_8bit
7096 0, // DFCCR:sub_8bit_hi
7097 0, // DFCCR:sub_8bit_hi_phony
7098 0, // DFCCR:sub_16bit
7099 0, // DFCCR:sub_16bit_hi
7100 0, // DFCCR:sub_32bit
7101 0, // DFCCR:sub_mask_0
7102 0, // DFCCR:sub_mask_1
7103 0, // DFCCR:sub_xmm
7104 0, // DFCCR:sub_ymm
7105 },
7106 { // GR32_ABCD_and_GR32_BSI
7107 6, // GR32_ABCD_and_GR32_BSI:sub_8bit -> GR8_ABCD_L
7108 5, // GR32_ABCD_and_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
7109 0, // GR32_ABCD_and_GR32_BSI:sub_8bit_hi_phony
7110 22, // GR32_ABCD_and_GR32_BSI:sub_16bit -> GR16_ABCD
7111 0, // GR32_ABCD_and_GR32_BSI:sub_16bit_hi
7112 0, // GR32_ABCD_and_GR32_BSI:sub_32bit
7113 0, // GR32_ABCD_and_GR32_BSI:sub_mask_0
7114 0, // GR32_ABCD_and_GR32_BSI:sub_mask_1
7115 0, // GR32_ABCD_and_GR32_BSI:sub_xmm
7116 0, // GR32_ABCD_and_GR32_BSI:sub_ymm
7117 },
7118 { // GR32_AD_and_GR32_ArgRef
7119 6, // GR32_AD_and_GR32_ArgRef:sub_8bit -> GR8_ABCD_L
7120 5, // GR32_AD_and_GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
7121 0, // GR32_AD_and_GR32_ArgRef:sub_8bit_hi_phony
7122 22, // GR32_AD_and_GR32_ArgRef:sub_16bit -> GR16_ABCD
7123 0, // GR32_AD_and_GR32_ArgRef:sub_16bit_hi
7124 0, // GR32_AD_and_GR32_ArgRef:sub_32bit
7125 0, // GR32_AD_and_GR32_ArgRef:sub_mask_0
7126 0, // GR32_AD_and_GR32_ArgRef:sub_mask_1
7127 0, // GR32_AD_and_GR32_ArgRef:sub_xmm
7128 0, // GR32_AD_and_GR32_ArgRef:sub_ymm
7129 },
7130 { // GR32_ArgRef_and_GR32_CB
7131 6, // GR32_ArgRef_and_GR32_CB:sub_8bit -> GR8_ABCD_L
7132 5, // GR32_ArgRef_and_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
7133 0, // GR32_ArgRef_and_GR32_CB:sub_8bit_hi_phony
7134 22, // GR32_ArgRef_and_GR32_CB:sub_16bit -> GR16_ABCD
7135 0, // GR32_ArgRef_and_GR32_CB:sub_16bit_hi
7136 0, // GR32_ArgRef_and_GR32_CB:sub_32bit
7137 0, // GR32_ArgRef_and_GR32_CB:sub_mask_0
7138 0, // GR32_ArgRef_and_GR32_CB:sub_mask_1
7139 0, // GR32_ArgRef_and_GR32_CB:sub_xmm
7140 0, // GR32_ArgRef_and_GR32_CB:sub_ymm
7141 },
7142 { // GR32_BPSP_and_GR32_DIBP
7143 3, // GR32_BPSP_and_GR32_DIBP:sub_8bit -> GR8_NOREX2
7144 0, // GR32_BPSP_and_GR32_DIBP:sub_8bit_hi
7145 0, // GR32_BPSP_and_GR32_DIBP:sub_8bit_hi_phony
7146 10, // GR32_BPSP_and_GR32_DIBP:sub_16bit -> GR16_NOREX
7147 0, // GR32_BPSP_and_GR32_DIBP:sub_16bit_hi
7148 0, // GR32_BPSP_and_GR32_DIBP:sub_32bit
7149 0, // GR32_BPSP_and_GR32_DIBP:sub_mask_0
7150 0, // GR32_BPSP_and_GR32_DIBP:sub_mask_1
7151 0, // GR32_BPSP_and_GR32_DIBP:sub_xmm
7152 0, // GR32_BPSP_and_GR32_DIBP:sub_ymm
7153 },
7154 { // GR32_BPSP_and_GR32_TC
7155 3, // GR32_BPSP_and_GR32_TC:sub_8bit -> GR8_NOREX2
7156 0, // GR32_BPSP_and_GR32_TC:sub_8bit_hi
7157 0, // GR32_BPSP_and_GR32_TC:sub_8bit_hi_phony
7158 10, // GR32_BPSP_and_GR32_TC:sub_16bit -> GR16_NOREX
7159 0, // GR32_BPSP_and_GR32_TC:sub_16bit_hi
7160 0, // GR32_BPSP_and_GR32_TC:sub_32bit
7161 0, // GR32_BPSP_and_GR32_TC:sub_mask_0
7162 0, // GR32_BPSP_and_GR32_TC:sub_mask_1
7163 0, // GR32_BPSP_and_GR32_TC:sub_xmm
7164 0, // GR32_BPSP_and_GR32_TC:sub_ymm
7165 },
7166 { // GR32_BSI_and_GR32_SIDI
7167 3, // GR32_BSI_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
7168 0, // GR32_BSI_and_GR32_SIDI:sub_8bit_hi
7169 0, // GR32_BSI_and_GR32_SIDI:sub_8bit_hi_phony
7170 10, // GR32_BSI_and_GR32_SIDI:sub_16bit -> GR16_NOREX
7171 0, // GR32_BSI_and_GR32_SIDI:sub_16bit_hi
7172 0, // GR32_BSI_and_GR32_SIDI:sub_32bit
7173 0, // GR32_BSI_and_GR32_SIDI:sub_mask_0
7174 0, // GR32_BSI_and_GR32_SIDI:sub_mask_1
7175 0, // GR32_BSI_and_GR32_SIDI:sub_xmm
7176 0, // GR32_BSI_and_GR32_SIDI:sub_ymm
7177 },
7178 { // GR32_DIBP_and_GR32_SIDI
7179 3, // GR32_DIBP_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
7180 0, // GR32_DIBP_and_GR32_SIDI:sub_8bit_hi
7181 0, // GR32_DIBP_and_GR32_SIDI:sub_8bit_hi_phony
7182 10, // GR32_DIBP_and_GR32_SIDI:sub_16bit -> GR16_NOREX
7183 0, // GR32_DIBP_and_GR32_SIDI:sub_16bit_hi
7184 0, // GR32_DIBP_and_GR32_SIDI:sub_32bit
7185 0, // GR32_DIBP_and_GR32_SIDI:sub_mask_0
7186 0, // GR32_DIBP_and_GR32_SIDI:sub_mask_1
7187 0, // GR32_DIBP_and_GR32_SIDI:sub_xmm
7188 0, // GR32_DIBP_and_GR32_SIDI:sub_ymm
7189 },
7190 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
7191 3, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit -> GR8_NOREX2
7192 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit_hi
7193 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit_hi_phony
7194 10, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_16bit -> GR16_NOREX
7195 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_16bit_hi
7196 66, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
7197 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_mask_0
7198 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_mask_1
7199 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_xmm
7200 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_ymm
7201 },
7202 { // LOW32_ADDR_ACCESS_with_sub_32bit
7203 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit
7204 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit_hi
7205 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit_hi_phony
7206 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_16bit
7207 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_16bit_hi
7208 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_32bit
7209 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_mask_0
7210 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_mask_1
7211 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_xmm
7212 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_ymm
7213 },
7214 { // RFP64
7215 0, // RFP64:sub_8bit
7216 0, // RFP64:sub_8bit_hi
7217 0, // RFP64:sub_8bit_hi_phony
7218 0, // RFP64:sub_16bit
7219 0, // RFP64:sub_16bit_hi
7220 0, // RFP64:sub_32bit
7221 0, // RFP64:sub_mask_0
7222 0, // RFP64:sub_mask_1
7223 0, // RFP64:sub_xmm
7224 0, // RFP64:sub_ymm
7225 },
7226 { // GR64
7227 1, // GR64:sub_8bit -> GR8
7228 5, // GR64:sub_8bit_hi -> GR8_ABCD_H
7229 0, // GR64:sub_8bit_hi_phony
7230 8, // GR64:sub_16bit -> GR16
7231 0, // GR64:sub_16bit_hi
7232 36, // GR64:sub_32bit -> GR32
7233 0, // GR64:sub_mask_0
7234 0, // GR64:sub_mask_1
7235 0, // GR64:sub_xmm
7236 0, // GR64:sub_ymm
7237 },
7238 { // FR64X
7239 0, // FR64X:sub_8bit
7240 0, // FR64X:sub_8bit_hi
7241 0, // FR64X:sub_8bit_hi_phony
7242 0, // FR64X:sub_16bit
7243 0, // FR64X:sub_16bit_hi
7244 0, // FR64X:sub_32bit
7245 0, // FR64X:sub_mask_0
7246 0, // FR64X:sub_mask_1
7247 0, // FR64X:sub_xmm
7248 0, // FR64X:sub_ymm
7249 },
7250 { // GR64_with_sub_8bit
7251 1, // GR64_with_sub_8bit:sub_8bit -> GR8
7252 5, // GR64_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
7253 0, // GR64_with_sub_8bit:sub_8bit_hi_phony
7254 8, // GR64_with_sub_8bit:sub_16bit -> GR16
7255 0, // GR64_with_sub_8bit:sub_16bit_hi
7256 36, // GR64_with_sub_8bit:sub_32bit -> GR32
7257 0, // GR64_with_sub_8bit:sub_mask_0
7258 0, // GR64_with_sub_8bit:sub_mask_1
7259 0, // GR64_with_sub_8bit:sub_xmm
7260 0, // GR64_with_sub_8bit:sub_ymm
7261 },
7262 { // GR64_NOSP
7263 1, // GR64_NOSP:sub_8bit -> GR8
7264 5, // GR64_NOSP:sub_8bit_hi -> GR8_ABCD_H
7265 0, // GR64_NOSP:sub_8bit_hi_phony
7266 8, // GR64_NOSP:sub_16bit -> GR16
7267 0, // GR64_NOSP:sub_16bit_hi
7268 37, // GR64_NOSP:sub_32bit -> GR32_NOSP
7269 0, // GR64_NOSP:sub_mask_0
7270 0, // GR64_NOSP:sub_mask_1
7271 0, // GR64_NOSP:sub_xmm
7272 0, // GR64_NOSP:sub_ymm
7273 },
7274 { // GR64_NOREX2
7275 3, // GR64_NOREX2:sub_8bit -> GR8_NOREX2
7276 5, // GR64_NOREX2:sub_8bit_hi -> GR8_ABCD_H
7277 0, // GR64_NOREX2:sub_8bit_hi_phony
7278 9, // GR64_NOREX2:sub_16bit -> GR16_NOREX2
7279 0, // GR64_NOREX2:sub_16bit_hi
7280 41, // GR64_NOREX2:sub_32bit -> GR32_NOREX2
7281 0, // GR64_NOREX2:sub_mask_0
7282 0, // GR64_NOREX2:sub_mask_1
7283 0, // GR64_NOREX2:sub_xmm
7284 0, // GR64_NOREX2:sub_ymm
7285 },
7286 { // CONTROL_REG
7287 0, // CONTROL_REG:sub_8bit
7288 0, // CONTROL_REG:sub_8bit_hi
7289 0, // CONTROL_REG:sub_8bit_hi_phony
7290 0, // CONTROL_REG:sub_16bit
7291 0, // CONTROL_REG:sub_16bit_hi
7292 0, // CONTROL_REG:sub_32bit
7293 0, // CONTROL_REG:sub_mask_0
7294 0, // CONTROL_REG:sub_mask_1
7295 0, // CONTROL_REG:sub_xmm
7296 0, // CONTROL_REG:sub_ymm
7297 },
7298 { // FR64
7299 0, // FR64:sub_8bit
7300 0, // FR64:sub_8bit_hi
7301 0, // FR64:sub_8bit_hi_phony
7302 0, // FR64:sub_16bit
7303 0, // FR64:sub_16bit_hi
7304 0, // FR64:sub_32bit
7305 0, // FR64:sub_mask_0
7306 0, // FR64:sub_mask_1
7307 0, // FR64:sub_xmm
7308 0, // FR64:sub_ymm
7309 },
7310 { // GR64_with_sub_16bit_in_GR16_NOREX2
7311 3, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_8bit -> GR8_NOREX2
7312 5, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi -> GR8_ABCD_H
7313 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi_phony
7314 9, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_16bit -> GR16_NOREX2
7315 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_16bit_hi
7316 41, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_32bit -> GR32_NOREX2
7317 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_mask_0
7318 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_mask_1
7319 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_xmm
7320 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_ymm
7321 },
7322 { // GR64_NOREX2_NOSP
7323 3, // GR64_NOREX2_NOSP:sub_8bit -> GR8_NOREX2
7324 5, // GR64_NOREX2_NOSP:sub_8bit_hi -> GR8_ABCD_H
7325 0, // GR64_NOREX2_NOSP:sub_8bit_hi_phony
7326 9, // GR64_NOREX2_NOSP:sub_16bit -> GR16_NOREX2
7327 0, // GR64_NOREX2_NOSP:sub_16bit_hi
7328 42, // GR64_NOREX2_NOSP:sub_32bit -> GR32_NOREX2_NOSP
7329 0, // GR64_NOREX2_NOSP:sub_mask_0
7330 0, // GR64_NOREX2_NOSP:sub_mask_1
7331 0, // GR64_NOREX2_NOSP:sub_xmm
7332 0, // GR64_NOREX2_NOSP:sub_ymm
7333 },
7334 { // GR64PLTSafe
7335 3, // GR64PLTSafe:sub_8bit -> GR8_NOREX2
7336 5, // GR64PLTSafe:sub_8bit_hi -> GR8_ABCD_H
7337 0, // GR64PLTSafe:sub_8bit_hi_phony
7338 9, // GR64PLTSafe:sub_16bit -> GR16_NOREX2
7339 0, // GR64PLTSafe:sub_16bit_hi
7340 42, // GR64PLTSafe:sub_32bit -> GR32_NOREX2_NOSP
7341 0, // GR64PLTSafe:sub_mask_0
7342 0, // GR64PLTSafe:sub_mask_1
7343 0, // GR64PLTSafe:sub_xmm
7344 0, // GR64PLTSafe:sub_ymm
7345 },
7346 { // GR64_TC
7347 3, // GR64_TC:sub_8bit -> GR8_NOREX2
7348 5, // GR64_TC:sub_8bit_hi -> GR8_ABCD_H
7349 0, // GR64_TC:sub_8bit_hi_phony
7350 9, // GR64_TC:sub_16bit -> GR16_NOREX2
7351 0, // GR64_TC:sub_16bit_hi
7352 41, // GR64_TC:sub_32bit -> GR32_NOREX2
7353 0, // GR64_TC:sub_mask_0
7354 0, // GR64_TC:sub_mask_1
7355 0, // GR64_TC:sub_xmm
7356 0, // GR64_TC:sub_ymm
7357 },
7358 { // GR64_NOREX
7359 3, // GR64_NOREX:sub_8bit -> GR8_NOREX2
7360 5, // GR64_NOREX:sub_8bit_hi -> GR8_ABCD_H
7361 0, // GR64_NOREX:sub_8bit_hi_phony
7362 10, // GR64_NOREX:sub_16bit -> GR16_NOREX
7363 0, // GR64_NOREX:sub_16bit_hi
7364 44, // GR64_NOREX:sub_32bit -> GR32_NOREX
7365 0, // GR64_NOREX:sub_mask_0
7366 0, // GR64_NOREX:sub_mask_1
7367 0, // GR64_NOREX:sub_xmm
7368 0, // GR64_NOREX:sub_ymm
7369 },
7370 { // GR64_TCW64
7371 3, // GR64_TCW64:sub_8bit -> GR8_NOREX2
7372 5, // GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
7373 0, // GR64_TCW64:sub_8bit_hi_phony
7374 9, // GR64_TCW64:sub_16bit -> GR16_NOREX2
7375 0, // GR64_TCW64:sub_16bit_hi
7376 41, // GR64_TCW64:sub_32bit -> GR32_NOREX2
7377 0, // GR64_TCW64:sub_mask_0
7378 0, // GR64_TCW64:sub_mask_1
7379 0, // GR64_TCW64:sub_xmm
7380 0, // GR64_TCW64:sub_ymm
7381 },
7382 { // GR64_TC_with_sub_8bit
7383 3, // GR64_TC_with_sub_8bit:sub_8bit -> GR8_NOREX2
7384 5, // GR64_TC_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
7385 0, // GR64_TC_with_sub_8bit:sub_8bit_hi_phony
7386 9, // GR64_TC_with_sub_8bit:sub_16bit -> GR16_NOREX2
7387 0, // GR64_TC_with_sub_8bit:sub_16bit_hi
7388 41, // GR64_TC_with_sub_8bit:sub_32bit -> GR32_NOREX2
7389 0, // GR64_TC_with_sub_8bit:sub_mask_0
7390 0, // GR64_TC_with_sub_8bit:sub_mask_1
7391 0, // GR64_TC_with_sub_8bit:sub_xmm
7392 0, // GR64_TC_with_sub_8bit:sub_ymm
7393 },
7394 { // GR64_NOREX2_NOSP_and_GR64_TC
7395 3, // GR64_NOREX2_NOSP_and_GR64_TC:sub_8bit -> GR8_NOREX2
7396 5, // GR64_NOREX2_NOSP_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
7397 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_8bit_hi_phony
7398 9, // GR64_NOREX2_NOSP_and_GR64_TC:sub_16bit -> GR16_NOREX2
7399 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_16bit_hi
7400 42, // GR64_NOREX2_NOSP_and_GR64_TC:sub_32bit -> GR32_NOREX2_NOSP
7401 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_mask_0
7402 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_mask_1
7403 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_xmm
7404 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_ymm
7405 },
7406 { // GR64_TCW64_with_sub_8bit
7407 3, // GR64_TCW64_with_sub_8bit:sub_8bit -> GR8_NOREX2
7408 5, // GR64_TCW64_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
7409 0, // GR64_TCW64_with_sub_8bit:sub_8bit_hi_phony
7410 9, // GR64_TCW64_with_sub_8bit:sub_16bit -> GR16_NOREX2
7411 0, // GR64_TCW64_with_sub_8bit:sub_16bit_hi
7412 41, // GR64_TCW64_with_sub_8bit:sub_32bit -> GR32_NOREX2
7413 0, // GR64_TCW64_with_sub_8bit:sub_mask_0
7414 0, // GR64_TCW64_with_sub_8bit:sub_mask_1
7415 0, // GR64_TCW64_with_sub_8bit:sub_xmm
7416 0, // GR64_TCW64_with_sub_8bit:sub_ymm
7417 },
7418 { // GR64_TC_and_GR64_TCW64
7419 3, // GR64_TC_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
7420 5, // GR64_TC_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
7421 0, // GR64_TC_and_GR64_TCW64:sub_8bit_hi_phony
7422 9, // GR64_TC_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
7423 0, // GR64_TC_and_GR64_TCW64:sub_16bit_hi
7424 41, // GR64_TC_and_GR64_TCW64:sub_32bit -> GR32_NOREX2
7425 0, // GR64_TC_and_GR64_TCW64:sub_mask_0
7426 0, // GR64_TC_and_GR64_TCW64:sub_mask_1
7427 0, // GR64_TC_and_GR64_TCW64:sub_xmm
7428 0, // GR64_TC_and_GR64_TCW64:sub_ymm
7429 },
7430 { // GR64_with_sub_16bit_in_GR16_NOREX
7431 3, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8_NOREX2
7432 5, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
7433 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
7434 10, // GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
7435 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
7436 44, // GR64_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_NOREX
7437 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_0
7438 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_1
7439 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_xmm
7440 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_ymm
7441 },
7442 { // VK64
7443 0, // VK64:sub_8bit
7444 0, // VK64:sub_8bit_hi
7445 0, // VK64:sub_8bit_hi_phony
7446 0, // VK64:sub_16bit
7447 0, // VK64:sub_16bit_hi
7448 0, // VK64:sub_32bit
7449 0, // VK64:sub_mask_0
7450 0, // VK64:sub_mask_1
7451 0, // VK64:sub_xmm
7452 0, // VK64:sub_ymm
7453 },
7454 { // VR64
7455 0, // VR64:sub_8bit
7456 0, // VR64:sub_8bit_hi
7457 0, // VR64:sub_8bit_hi_phony
7458 0, // VR64:sub_16bit
7459 0, // VR64:sub_16bit_hi
7460 0, // VR64:sub_32bit
7461 0, // VR64:sub_mask_0
7462 0, // VR64:sub_mask_1
7463 0, // VR64:sub_xmm
7464 0, // VR64:sub_ymm
7465 },
7466 { // GR64PLTSafe_and_GR64_TC
7467 3, // GR64PLTSafe_and_GR64_TC:sub_8bit -> GR8_NOREX2
7468 5, // GR64PLTSafe_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
7469 0, // GR64PLTSafe_and_GR64_TC:sub_8bit_hi_phony
7470 9, // GR64PLTSafe_and_GR64_TC:sub_16bit -> GR16_NOREX2
7471 0, // GR64PLTSafe_and_GR64_TC:sub_16bit_hi
7472 42, // GR64PLTSafe_and_GR64_TC:sub_32bit -> GR32_NOREX2_NOSP
7473 0, // GR64PLTSafe_and_GR64_TC:sub_mask_0
7474 0, // GR64PLTSafe_and_GR64_TC:sub_mask_1
7475 0, // GR64PLTSafe_and_GR64_TC:sub_xmm
7476 0, // GR64PLTSafe_and_GR64_TC:sub_ymm
7477 },
7478 { // GR64_NOREX2_NOSP_and_GR64_TCW64
7479 3, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
7480 5, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
7481 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi_phony
7482 9, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
7483 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit_hi
7484 42, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_32bit -> GR32_NOREX2_NOSP
7485 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_0
7486 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_1
7487 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_xmm
7488 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_ymm
7489 },
7490 { // GR64_NOREX_NOSP
7491 3, // GR64_NOREX_NOSP:sub_8bit -> GR8_NOREX2
7492 5, // GR64_NOREX_NOSP:sub_8bit_hi -> GR8_ABCD_H
7493 0, // GR64_NOREX_NOSP:sub_8bit_hi_phony
7494 10, // GR64_NOREX_NOSP:sub_16bit -> GR16_NOREX
7495 0, // GR64_NOREX_NOSP:sub_16bit_hi
7496 46, // GR64_NOREX_NOSP:sub_32bit -> GR32_NOREX_NOSP
7497 0, // GR64_NOREX_NOSP:sub_mask_0
7498 0, // GR64_NOREX_NOSP:sub_mask_1
7499 0, // GR64_NOREX_NOSP:sub_xmm
7500 0, // GR64_NOREX_NOSP:sub_ymm
7501 },
7502 { // GR64_NOREX_and_GR64_TC
7503 3, // GR64_NOREX_and_GR64_TC:sub_8bit -> GR8_NOREX2
7504 5, // GR64_NOREX_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
7505 0, // GR64_NOREX_and_GR64_TC:sub_8bit_hi_phony
7506 10, // GR64_NOREX_and_GR64_TC:sub_16bit -> GR16_NOREX
7507 0, // GR64_NOREX_and_GR64_TC:sub_16bit_hi
7508 44, // GR64_NOREX_and_GR64_TC:sub_32bit -> GR32_NOREX
7509 0, // GR64_NOREX_and_GR64_TC:sub_mask_0
7510 0, // GR64_NOREX_and_GR64_TC:sub_mask_1
7511 0, // GR64_NOREX_and_GR64_TC:sub_xmm
7512 0, // GR64_NOREX_and_GR64_TC:sub_ymm
7513 },
7514 { // GR64_TCW64_and_GR64_TC_with_sub_8bit
7515 3, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit -> GR8_NOREX2
7516 5, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
7517 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit_hi_phony
7518 9, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_16bit -> GR16_NOREX2
7519 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_16bit_hi
7520 41, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_32bit -> GR32_NOREX2
7521 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_mask_0
7522 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_mask_1
7523 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_xmm
7524 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_ymm
7525 },
7526 { // VK64WM
7527 0, // VK64WM:sub_8bit
7528 0, // VK64WM:sub_8bit_hi
7529 0, // VK64WM:sub_8bit_hi_phony
7530 0, // VK64WM:sub_16bit
7531 0, // VK64WM:sub_16bit_hi
7532 0, // VK64WM:sub_32bit
7533 0, // VK64WM:sub_mask_0
7534 0, // VK64WM:sub_mask_1
7535 0, // VK64WM:sub_xmm
7536 0, // VK64WM:sub_ymm
7537 },
7538 { // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
7539 3, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
7540 5, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
7541 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi_phony
7542 9, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
7543 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit_hi
7544 42, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_32bit -> GR32_NOREX2_NOSP
7545 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_0
7546 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_1
7547 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_xmm
7548 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_ymm
7549 },
7550 { // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
7551 3, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8_NOREX2
7552 5, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
7553 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
7554 10, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
7555 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
7556 44, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_NOREX
7557 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_0
7558 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_1
7559 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_xmm
7560 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_ymm
7561 },
7562 { // GR64PLTSafe_and_GR64_TCW64
7563 3, // GR64PLTSafe_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
7564 5, // GR64PLTSafe_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
7565 0, // GR64PLTSafe_and_GR64_TCW64:sub_8bit_hi_phony
7566 9, // GR64PLTSafe_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
7567 0, // GR64PLTSafe_and_GR64_TCW64:sub_16bit_hi
7568 42, // GR64PLTSafe_and_GR64_TCW64:sub_32bit -> GR32_NOREX2_NOSP
7569 0, // GR64PLTSafe_and_GR64_TCW64:sub_mask_0
7570 0, // GR64PLTSafe_and_GR64_TCW64:sub_mask_1
7571 0, // GR64PLTSafe_and_GR64_TCW64:sub_xmm
7572 0, // GR64PLTSafe_and_GR64_TCW64:sub_ymm
7573 },
7574 { // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
7575 3, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit -> GR8_NOREX2
7576 5, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
7577 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit_hi_phony
7578 10, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_16bit -> GR16_NOREX
7579 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_16bit_hi
7580 46, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_32bit -> GR32_NOREX_NOSP
7581 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_mask_0
7582 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_mask_1
7583 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_xmm
7584 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_ymm
7585 },
7586 { // GR64_NOREX_and_GR64_TCW64
7587 3, // GR64_NOREX_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
7588 5, // GR64_NOREX_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
7589 0, // GR64_NOREX_and_GR64_TCW64:sub_8bit_hi_phony
7590 10, // GR64_NOREX_and_GR64_TCW64:sub_16bit -> GR16_NOREX
7591 0, // GR64_NOREX_and_GR64_TCW64:sub_16bit_hi
7592 50, // GR64_NOREX_and_GR64_TCW64:sub_32bit -> GR32_TC
7593 0, // GR64_NOREX_and_GR64_TCW64:sub_mask_0
7594 0, // GR64_NOREX_and_GR64_TCW64:sub_mask_1
7595 0, // GR64_NOREX_and_GR64_TCW64:sub_xmm
7596 0, // GR64_NOREX_and_GR64_TCW64:sub_ymm
7597 },
7598 { // GR64_ABCD
7599 6, // GR64_ABCD:sub_8bit -> GR8_ABCD_L
7600 5, // GR64_ABCD:sub_8bit_hi -> GR8_ABCD_H
7601 0, // GR64_ABCD:sub_8bit_hi_phony
7602 22, // GR64_ABCD:sub_16bit -> GR16_ABCD
7603 0, // GR64_ABCD:sub_16bit_hi
7604 49, // GR64_ABCD:sub_32bit -> GR32_ABCD
7605 0, // GR64_ABCD:sub_mask_0
7606 0, // GR64_ABCD:sub_mask_1
7607 0, // GR64_ABCD:sub_xmm
7608 0, // GR64_ABCD:sub_ymm
7609 },
7610 { // GR64_with_sub_32bit_in_GR32_TC
7611 3, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit -> GR8_NOREX2
7612 5, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
7613 0, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit_hi_phony
7614 10, // GR64_with_sub_32bit_in_GR32_TC:sub_16bit -> GR16_NOREX
7615 0, // GR64_with_sub_32bit_in_GR32_TC:sub_16bit_hi
7616 50, // GR64_with_sub_32bit_in_GR32_TC:sub_32bit -> GR32_TC
7617 0, // GR64_with_sub_32bit_in_GR32_TC:sub_mask_0
7618 0, // GR64_with_sub_32bit_in_GR32_TC:sub_mask_1
7619 0, // GR64_with_sub_32bit_in_GR32_TC:sub_xmm
7620 0, // GR64_with_sub_32bit_in_GR32_TC:sub_ymm
7621 },
7622 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
7623 6, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit -> GR8_ABCD_L
7624 5, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
7625 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit_hi_phony
7626 22, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_16bit -> GR16_ABCD
7627 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_16bit_hi
7628 51, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_32bit -> GR32_ABCD_and_GR32_TC
7629 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_mask_0
7630 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_mask_1
7631 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_xmm
7632 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_ymm
7633 },
7634 { // GR64_AD
7635 6, // GR64_AD:sub_8bit -> GR8_ABCD_L
7636 5, // GR64_AD:sub_8bit_hi -> GR8_ABCD_H
7637 0, // GR64_AD:sub_8bit_hi_phony
7638 22, // GR64_AD:sub_16bit -> GR16_ABCD
7639 0, // GR64_AD:sub_16bit_hi
7640 52, // GR64_AD:sub_32bit -> GR32_AD
7641 0, // GR64_AD:sub_mask_0
7642 0, // GR64_AD:sub_mask_1
7643 0, // GR64_AD:sub_xmm
7644 0, // GR64_AD:sub_ymm
7645 },
7646 { // GR64_ArgRef
7647 3, // GR64_ArgRef:sub_8bit -> GR8_NOREX2
7648 0, // GR64_ArgRef:sub_8bit_hi
7649 0, // GR64_ArgRef:sub_8bit_hi_phony
7650 9, // GR64_ArgRef:sub_16bit -> GR16_NOREX2
7651 0, // GR64_ArgRef:sub_16bit_hi
7652 42, // GR64_ArgRef:sub_32bit -> GR32_NOREX2_NOSP
7653 0, // GR64_ArgRef:sub_mask_0
7654 0, // GR64_ArgRef:sub_mask_1
7655 0, // GR64_ArgRef:sub_xmm
7656 0, // GR64_ArgRef:sub_ymm
7657 },
7658 { // GR64_and_LOW32_ADDR_ACCESS_RBP
7659 3, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit -> GR8_NOREX2
7660 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit_hi
7661 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit_hi_phony
7662 10, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_16bit -> GR16_NOREX
7663 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_16bit_hi
7664 66, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
7665 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_mask_0
7666 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_mask_1
7667 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_xmm
7668 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_ymm
7669 },
7670 { // GR64_with_sub_32bit_in_GR32_ArgRef
7671 6, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_8bit -> GR8_ABCD_L
7672 5, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
7673 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_8bit_hi_phony
7674 22, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_16bit -> GR16_ABCD
7675 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_16bit_hi
7676 53, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_32bit -> GR32_ArgRef
7677 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_mask_0
7678 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_mask_1
7679 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_xmm
7680 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_ymm
7681 },
7682 { // GR64_with_sub_32bit_in_GR32_BPSP
7683 3, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit -> GR8_NOREX2
7684 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit_hi
7685 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit_hi_phony
7686 10, // GR64_with_sub_32bit_in_GR32_BPSP:sub_16bit -> GR16_NOREX
7687 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_16bit_hi
7688 54, // GR64_with_sub_32bit_in_GR32_BPSP:sub_32bit -> GR32_BPSP
7689 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_mask_0
7690 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_mask_1
7691 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_xmm
7692 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_ymm
7693 },
7694 { // GR64_with_sub_32bit_in_GR32_BSI
7695 3, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit -> GR8_NOREX2
7696 5, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
7697 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit_hi_phony
7698 10, // GR64_with_sub_32bit_in_GR32_BSI:sub_16bit -> GR16_NOREX
7699 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_16bit_hi
7700 55, // GR64_with_sub_32bit_in_GR32_BSI:sub_32bit -> GR32_BSI
7701 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_mask_0
7702 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_mask_1
7703 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_xmm
7704 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_ymm
7705 },
7706 { // GR64_with_sub_32bit_in_GR32_CB
7707 6, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit -> GR8_ABCD_L
7708 5, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
7709 0, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit_hi_phony
7710 22, // GR64_with_sub_32bit_in_GR32_CB:sub_16bit -> GR16_ABCD
7711 0, // GR64_with_sub_32bit_in_GR32_CB:sub_16bit_hi
7712 56, // GR64_with_sub_32bit_in_GR32_CB:sub_32bit -> GR32_CB
7713 0, // GR64_with_sub_32bit_in_GR32_CB:sub_mask_0
7714 0, // GR64_with_sub_32bit_in_GR32_CB:sub_mask_1
7715 0, // GR64_with_sub_32bit_in_GR32_CB:sub_xmm
7716 0, // GR64_with_sub_32bit_in_GR32_CB:sub_ymm
7717 },
7718 { // GR64_with_sub_32bit_in_GR32_DIBP
7719 3, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit -> GR8_NOREX2
7720 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit_hi
7721 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit_hi_phony
7722 10, // GR64_with_sub_32bit_in_GR32_DIBP:sub_16bit -> GR16_NOREX
7723 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_16bit_hi
7724 58, // GR64_with_sub_32bit_in_GR32_DIBP:sub_32bit -> GR32_DIBP
7725 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_mask_0
7726 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_mask_1
7727 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_xmm
7728 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_ymm
7729 },
7730 { // GR64_with_sub_32bit_in_GR32_SIDI
7731 3, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit -> GR8_NOREX2
7732 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit_hi
7733 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit_hi_phony
7734 10, // GR64_with_sub_32bit_in_GR32_SIDI:sub_16bit -> GR16_NOREX
7735 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_16bit_hi
7736 59, // GR64_with_sub_32bit_in_GR32_SIDI:sub_32bit -> GR32_SIDI
7737 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_mask_0
7738 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_mask_1
7739 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_xmm
7740 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_ymm
7741 },
7742 { // GR64_A
7743 6, // GR64_A:sub_8bit -> GR8_ABCD_L
7744 5, // GR64_A:sub_8bit_hi -> GR8_ABCD_H
7745 0, // GR64_A:sub_8bit_hi_phony
7746 22, // GR64_A:sub_16bit -> GR16_ABCD
7747 0, // GR64_A:sub_16bit_hi
7748 52, // GR64_A:sub_32bit -> GR32_AD
7749 0, // GR64_A:sub_mask_0
7750 0, // GR64_A:sub_mask_1
7751 0, // GR64_A:sub_xmm
7752 0, // GR64_A:sub_ymm
7753 },
7754 { // GR64_ArgRef_and_GR64_TC
7755 3, // GR64_ArgRef_and_GR64_TC:sub_8bit -> GR8_NOREX2
7756 0, // GR64_ArgRef_and_GR64_TC:sub_8bit_hi
7757 0, // GR64_ArgRef_and_GR64_TC:sub_8bit_hi_phony
7758 9, // GR64_ArgRef_and_GR64_TC:sub_16bit -> GR16_NOREX2
7759 0, // GR64_ArgRef_and_GR64_TC:sub_16bit_hi
7760 42, // GR64_ArgRef_and_GR64_TC:sub_32bit -> GR32_NOREX2_NOSP
7761 0, // GR64_ArgRef_and_GR64_TC:sub_mask_0
7762 0, // GR64_ArgRef_and_GR64_TC:sub_mask_1
7763 0, // GR64_ArgRef_and_GR64_TC:sub_xmm
7764 0, // GR64_ArgRef_and_GR64_TC:sub_ymm
7765 },
7766 { // GR64_and_LOW32_ADDR_ACCESS
7767 0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit
7768 0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit_hi
7769 0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit_hi_phony
7770 0, // GR64_and_LOW32_ADDR_ACCESS:sub_16bit
7771 0, // GR64_and_LOW32_ADDR_ACCESS:sub_16bit_hi
7772 0, // GR64_and_LOW32_ADDR_ACCESS:sub_32bit
7773 0, // GR64_and_LOW32_ADDR_ACCESS:sub_mask_0
7774 0, // GR64_and_LOW32_ADDR_ACCESS:sub_mask_1
7775 0, // GR64_and_LOW32_ADDR_ACCESS:sub_xmm
7776 0, // GR64_and_LOW32_ADDR_ACCESS:sub_ymm
7777 },
7778 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
7779 6, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit -> GR8_ABCD_L
7780 5, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
7781 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit_hi_phony
7782 22, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_16bit -> GR16_ABCD
7783 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_16bit_hi
7784 63, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_32bit -> GR32_ABCD_and_GR32_BSI
7785 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_mask_0
7786 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_mask_1
7787 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_xmm
7788 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_ymm
7789 },
7790 { // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
7791 6, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_8bit -> GR8_ABCD_L
7792 5, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
7793 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_8bit_hi_phony
7794 22, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_16bit -> GR16_ABCD
7795 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_16bit_hi
7796 64, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_32bit -> GR32_AD_and_GR32_ArgRef
7797 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_mask_0
7798 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_mask_1
7799 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_xmm
7800 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_ymm
7801 },
7802 { // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
7803 6, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_8bit -> GR8_ABCD_L
7804 5, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
7805 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_8bit_hi_phony
7806 22, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_16bit -> GR16_ABCD
7807 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_16bit_hi
7808 65, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_32bit -> GR32_ArgRef_and_GR32_CB
7809 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_mask_0
7810 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_mask_1
7811 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_xmm
7812 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_ymm
7813 },
7814 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
7815 3, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit -> GR8_NOREX2
7816 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit_hi
7817 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit_hi_phony
7818 10, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_16bit -> GR16_NOREX
7819 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_16bit_hi
7820 66, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
7821 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_mask_0
7822 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_mask_1
7823 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_xmm
7824 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_ymm
7825 },
7826 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
7827 3, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit -> GR8_NOREX2
7828 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit_hi
7829 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit_hi_phony
7830 10, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_16bit -> GR16_NOREX
7831 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_16bit_hi
7832 67, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_32bit -> GR32_BPSP_and_GR32_TC
7833 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_mask_0
7834 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_mask_1
7835 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_xmm
7836 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_ymm
7837 },
7838 { // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
7839 3, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
7840 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit_hi
7841 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit_hi_phony
7842 10, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_16bit -> GR16_NOREX
7843 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_16bit_hi
7844 68, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_32bit -> GR32_BSI_and_GR32_SIDI
7845 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_mask_0
7846 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_mask_1
7847 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_xmm
7848 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_ymm
7849 },
7850 { // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
7851 3, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
7852 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit_hi
7853 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit_hi_phony
7854 10, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_16bit -> GR16_NOREX
7855 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_16bit_hi
7856 69, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_32bit -> GR32_DIBP_and_GR32_SIDI
7857 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_mask_0
7858 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_mask_1
7859 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_xmm
7860 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_ymm
7861 },
7862 { // RST
7863 0, // RST:sub_8bit
7864 0, // RST:sub_8bit_hi
7865 0, // RST:sub_8bit_hi_phony
7866 0, // RST:sub_16bit
7867 0, // RST:sub_16bit_hi
7868 0, // RST:sub_32bit
7869 0, // RST:sub_mask_0
7870 0, // RST:sub_mask_1
7871 0, // RST:sub_xmm
7872 0, // RST:sub_ymm
7873 },
7874 { // RFP80
7875 0, // RFP80:sub_8bit
7876 0, // RFP80:sub_8bit_hi
7877 0, // RFP80:sub_8bit_hi_phony
7878 0, // RFP80:sub_16bit
7879 0, // RFP80:sub_16bit_hi
7880 0, // RFP80:sub_32bit
7881 0, // RFP80:sub_mask_0
7882 0, // RFP80:sub_mask_1
7883 0, // RFP80:sub_xmm
7884 0, // RFP80:sub_ymm
7885 },
7886 { // RFP80_7
7887 0, // RFP80_7:sub_8bit
7888 0, // RFP80_7:sub_8bit_hi
7889 0, // RFP80_7:sub_8bit_hi_phony
7890 0, // RFP80_7:sub_16bit
7891 0, // RFP80_7:sub_16bit_hi
7892 0, // RFP80_7:sub_32bit
7893 0, // RFP80_7:sub_mask_0
7894 0, // RFP80_7:sub_mask_1
7895 0, // RFP80_7:sub_xmm
7896 0, // RFP80_7:sub_ymm
7897 },
7898 { // VR128X
7899 0, // VR128X:sub_8bit
7900 0, // VR128X:sub_8bit_hi
7901 0, // VR128X:sub_8bit_hi_phony
7902 0, // VR128X:sub_16bit
7903 0, // VR128X:sub_16bit_hi
7904 0, // VR128X:sub_32bit
7905 0, // VR128X:sub_mask_0
7906 0, // VR128X:sub_mask_1
7907 0, // VR128X:sub_xmm
7908 0, // VR128X:sub_ymm
7909 },
7910 { // VR128
7911 0, // VR128:sub_8bit
7912 0, // VR128:sub_8bit_hi
7913 0, // VR128:sub_8bit_hi_phony
7914 0, // VR128:sub_16bit
7915 0, // VR128:sub_16bit_hi
7916 0, // VR128:sub_32bit
7917 0, // VR128:sub_mask_0
7918 0, // VR128:sub_mask_1
7919 0, // VR128:sub_xmm
7920 0, // VR128:sub_ymm
7921 },
7922 { // VR256X
7923 0, // VR256X:sub_8bit
7924 0, // VR256X:sub_8bit_hi
7925 0, // VR256X:sub_8bit_hi_phony
7926 0, // VR256X:sub_16bit
7927 0, // VR256X:sub_16bit_hi
7928 0, // VR256X:sub_32bit
7929 0, // VR256X:sub_mask_0
7930 0, // VR256X:sub_mask_1
7931 24, // VR256X:sub_xmm -> FR16X
7932 0, // VR256X:sub_ymm
7933 },
7934 { // VR256
7935 0, // VR256:sub_8bit
7936 0, // VR256:sub_8bit_hi
7937 0, // VR256:sub_8bit_hi_phony
7938 0, // VR256:sub_16bit
7939 0, // VR256:sub_16bit_hi
7940 0, // VR256:sub_32bit
7941 0, // VR256:sub_mask_0
7942 0, // VR256:sub_mask_1
7943 25, // VR256:sub_xmm -> FR16
7944 0, // VR256:sub_ymm
7945 },
7946 { // VR512
7947 0, // VR512:sub_8bit
7948 0, // VR512:sub_8bit_hi
7949 0, // VR512:sub_8bit_hi_phony
7950 0, // VR512:sub_16bit
7951 0, // VR512:sub_16bit_hi
7952 0, // VR512:sub_32bit
7953 0, // VR512:sub_mask_0
7954 0, // VR512:sub_mask_1
7955 24, // VR512:sub_xmm -> FR16X
7956 131, // VR512:sub_ymm -> VR256X
7957 },
7958 { // VR512_0_15
7959 0, // VR512_0_15:sub_8bit
7960 0, // VR512_0_15:sub_8bit_hi
7961 0, // VR512_0_15:sub_8bit_hi_phony
7962 0, // VR512_0_15:sub_16bit
7963 0, // VR512_0_15:sub_16bit_hi
7964 0, // VR512_0_15:sub_32bit
7965 0, // VR512_0_15:sub_mask_0
7966 0, // VR512_0_15:sub_mask_1
7967 25, // VR512_0_15:sub_xmm -> FR16
7968 132, // VR512_0_15:sub_ymm -> VR256
7969 },
7970 { // TILE
7971 0, // TILE:sub_8bit
7972 0, // TILE:sub_8bit_hi
7973 0, // TILE:sub_8bit_hi_phony
7974 0, // TILE:sub_16bit
7975 0, // TILE:sub_16bit_hi
7976 0, // TILE:sub_32bit
7977 0, // TILE:sub_mask_0
7978 0, // TILE:sub_mask_1
7979 0, // TILE:sub_xmm
7980 0, // TILE:sub_ymm
7981 },
7982
7983 };
7984 assert(RC && "Missing regclass");
7985 if (!Idx) return RC;
7986 --Idx;
7987 assert(Idx < 10 && "Bad subreg");
7988 unsigned TV = Table[RC->getID()][Idx];
7989 return TV ? getRegClass(i: TV - 1) : nullptr;
7990}/// Get the weight in units of pressure for this register class.
7991const RegClassWeight &X86GenRegisterInfo::
7992getRegClassWeight(const TargetRegisterClass *RC) const {
7993 static const RegClassWeight RCWeightTable[] = {
7994 {.RegWeight: 1, .WeightLimit: 36}, // GR8
7995 {.RegWeight: 0, .WeightLimit: 0}, // GRH8
7996 {.RegWeight: 1, .WeightLimit: 20}, // GR8_NOREX2
7997 {.RegWeight: 1, .WeightLimit: 8}, // GR8_NOREX
7998 {.RegWeight: 1, .WeightLimit: 4}, // GR8_ABCD_H
7999 {.RegWeight: 1, .WeightLimit: 4}, // GR8_ABCD_L
8000 {.RegWeight: 0, .WeightLimit: 0}, // GRH16
8001 {.RegWeight: 2, .WeightLimit: 64}, // GR16
8002 {.RegWeight: 2, .WeightLimit: 32}, // GR16_NOREX2
8003 {.RegWeight: 2, .WeightLimit: 16}, // GR16_NOREX
8004 {.RegWeight: 1, .WeightLimit: 8}, // VK1
8005 {.RegWeight: 1, .WeightLimit: 8}, // VK16
8006 {.RegWeight: 1, .WeightLimit: 8}, // VK2
8007 {.RegWeight: 1, .WeightLimit: 8}, // VK4
8008 {.RegWeight: 1, .WeightLimit: 8}, // VK8
8009 {.RegWeight: 1, .WeightLimit: 7}, // VK16WM
8010 {.RegWeight: 1, .WeightLimit: 7}, // VK1WM
8011 {.RegWeight: 1, .WeightLimit: 7}, // VK2WM
8012 {.RegWeight: 1, .WeightLimit: 7}, // VK4WM
8013 {.RegWeight: 1, .WeightLimit: 7}, // VK8WM
8014 {.RegWeight: 1, .WeightLimit: 6}, // SEGMENT_REG
8015 {.RegWeight: 2, .WeightLimit: 8}, // GR16_ABCD
8016 {.RegWeight: 0, .WeightLimit: 0}, // FPCCR
8017 {.RegWeight: 1, .WeightLimit: 32}, // FR16X
8018 {.RegWeight: 1, .WeightLimit: 16}, // FR16
8019 {.RegWeight: 2, .WeightLimit: 8}, // VK16PAIR
8020 {.RegWeight: 2, .WeightLimit: 8}, // VK1PAIR
8021 {.RegWeight: 2, .WeightLimit: 8}, // VK2PAIR
8022 {.RegWeight: 2, .WeightLimit: 8}, // VK4PAIR
8023 {.RegWeight: 2, .WeightLimit: 8}, // VK8PAIR
8024 {.RegWeight: 2, .WeightLimit: 6}, // VK1PAIR_with_sub_mask_0_in_VK1WM
8025 {.RegWeight: 2, .WeightLimit: 66}, // LOW32_ADDR_ACCESS_RBP
8026 {.RegWeight: 2, .WeightLimit: 66}, // LOW32_ADDR_ACCESS
8027 {.RegWeight: 2, .WeightLimit: 64}, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
8028 {.RegWeight: 1, .WeightLimit: 32}, // FR32X
8029 {.RegWeight: 2, .WeightLimit: 64}, // GR32
8030 {.RegWeight: 2, .WeightLimit: 62}, // GR32_NOSP
8031 {.RegWeight: 2, .WeightLimit: 32}, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
8032 {.RegWeight: 1, .WeightLimit: 16}, // DEBUG_REG
8033 {.RegWeight: 1, .WeightLimit: 16}, // FR32
8034 {.RegWeight: 2, .WeightLimit: 32}, // GR32_NOREX2
8035 {.RegWeight: 2, .WeightLimit: 30}, // GR32_NOREX2_NOSP
8036 {.RegWeight: 2, .WeightLimit: 16}, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
8037 {.RegWeight: 2, .WeightLimit: 16}, // GR32_NOREX
8038 {.RegWeight: 1, .WeightLimit: 8}, // VK32
8039 {.RegWeight: 2, .WeightLimit: 14}, // GR32_NOREX_NOSP
8040 {.RegWeight: 1, .WeightLimit: 7}, // RFP32
8041 {.RegWeight: 1, .WeightLimit: 7}, // VK32WM
8042 {.RegWeight: 2, .WeightLimit: 8}, // GR32_ABCD
8043 {.RegWeight: 2, .WeightLimit: 8}, // GR32_TC
8044 {.RegWeight: 2, .WeightLimit: 6}, // GR32_ABCD_and_GR32_TC
8045 {.RegWeight: 2, .WeightLimit: 4}, // GR32_AD
8046 {.RegWeight: 2, .WeightLimit: 4}, // GR32_ArgRef
8047 {.RegWeight: 2, .WeightLimit: 4}, // GR32_BPSP
8048 {.RegWeight: 2, .WeightLimit: 4}, // GR32_BSI
8049 {.RegWeight: 2, .WeightLimit: 4}, // GR32_CB
8050 {.RegWeight: 2, .WeightLimit: 4}, // GR32_DC
8051 {.RegWeight: 2, .WeightLimit: 4}, // GR32_DIBP
8052 {.RegWeight: 2, .WeightLimit: 4}, // GR32_SIDI
8053 {.RegWeight: 2, .WeightLimit: 4}, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
8054 {.RegWeight: 0, .WeightLimit: 0}, // CCR
8055 {.RegWeight: 0, .WeightLimit: 0}, // DFCCR
8056 {.RegWeight: 2, .WeightLimit: 2}, // GR32_ABCD_and_GR32_BSI
8057 {.RegWeight: 2, .WeightLimit: 2}, // GR32_AD_and_GR32_ArgRef
8058 {.RegWeight: 2, .WeightLimit: 2}, // GR32_ArgRef_and_GR32_CB
8059 {.RegWeight: 2, .WeightLimit: 2}, // GR32_BPSP_and_GR32_DIBP
8060 {.RegWeight: 2, .WeightLimit: 2}, // GR32_BPSP_and_GR32_TC
8061 {.RegWeight: 2, .WeightLimit: 2}, // GR32_BSI_and_GR32_SIDI
8062 {.RegWeight: 2, .WeightLimit: 2}, // GR32_DIBP_and_GR32_SIDI
8063 {.RegWeight: 2, .WeightLimit: 2}, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
8064 {.RegWeight: 2, .WeightLimit: 2}, // LOW32_ADDR_ACCESS_with_sub_32bit
8065 {.RegWeight: 1, .WeightLimit: 7}, // RFP64
8066 {.RegWeight: 2, .WeightLimit: 66}, // GR64
8067 {.RegWeight: 1, .WeightLimit: 32}, // FR64X
8068 {.RegWeight: 2, .WeightLimit: 64}, // GR64_with_sub_8bit
8069 {.RegWeight: 2, .WeightLimit: 62}, // GR64_NOSP
8070 {.RegWeight: 2, .WeightLimit: 34}, // GR64_NOREX2
8071 {.RegWeight: 1, .WeightLimit: 16}, // CONTROL_REG
8072 {.RegWeight: 1, .WeightLimit: 16}, // FR64
8073 {.RegWeight: 2, .WeightLimit: 32}, // GR64_with_sub_16bit_in_GR16_NOREX2
8074 {.RegWeight: 2, .WeightLimit: 30}, // GR64_NOREX2_NOSP
8075 {.RegWeight: 2, .WeightLimit: 26}, // GR64PLTSafe
8076 {.RegWeight: 2, .WeightLimit: 20}, // GR64_TC
8077 {.RegWeight: 2, .WeightLimit: 18}, // GR64_NOREX
8078 {.RegWeight: 2, .WeightLimit: 18}, // GR64_TCW64
8079 {.RegWeight: 2, .WeightLimit: 18}, // GR64_TC_with_sub_8bit
8080 {.RegWeight: 2, .WeightLimit: 16}, // GR64_NOREX2_NOSP_and_GR64_TC
8081 {.RegWeight: 2, .WeightLimit: 16}, // GR64_TCW64_with_sub_8bit
8082 {.RegWeight: 2, .WeightLimit: 16}, // GR64_TC_and_GR64_TCW64
8083 {.RegWeight: 2, .WeightLimit: 16}, // GR64_with_sub_16bit_in_GR16_NOREX
8084 {.RegWeight: 1, .WeightLimit: 8}, // VK64
8085 {.RegWeight: 1, .WeightLimit: 8}, // VR64
8086 {.RegWeight: 2, .WeightLimit: 14}, // GR64PLTSafe_and_GR64_TC
8087 {.RegWeight: 2, .WeightLimit: 14}, // GR64_NOREX2_NOSP_and_GR64_TCW64
8088 {.RegWeight: 2, .WeightLimit: 14}, // GR64_NOREX_NOSP
8089 {.RegWeight: 2, .WeightLimit: 14}, // GR64_NOREX_and_GR64_TC
8090 {.RegWeight: 2, .WeightLimit: 14}, // GR64_TCW64_and_GR64_TC_with_sub_8bit
8091 {.RegWeight: 1, .WeightLimit: 7}, // VK64WM
8092 {.RegWeight: 2, .WeightLimit: 12}, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
8093 {.RegWeight: 2, .WeightLimit: 12}, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
8094 {.RegWeight: 2, .WeightLimit: 10}, // GR64PLTSafe_and_GR64_TCW64
8095 {.RegWeight: 2, .WeightLimit: 10}, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
8096 {.RegWeight: 2, .WeightLimit: 10}, // GR64_NOREX_and_GR64_TCW64
8097 {.RegWeight: 2, .WeightLimit: 8}, // GR64_ABCD
8098 {.RegWeight: 2, .WeightLimit: 8}, // GR64_with_sub_32bit_in_GR32_TC
8099 {.RegWeight: 2, .WeightLimit: 6}, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
8100 {.RegWeight: 2, .WeightLimit: 4}, // GR64_AD
8101 {.RegWeight: 2, .WeightLimit: 4}, // GR64_ArgRef
8102 {.RegWeight: 2, .WeightLimit: 4}, // GR64_and_LOW32_ADDR_ACCESS_RBP
8103 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_ArgRef
8104 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_BPSP
8105 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_BSI
8106 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_CB
8107 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_DIBP
8108 {.RegWeight: 2, .WeightLimit: 4}, // GR64_with_sub_32bit_in_GR32_SIDI
8109 {.RegWeight: 2, .WeightLimit: 2}, // GR64_A
8110 {.RegWeight: 2, .WeightLimit: 2}, // GR64_ArgRef_and_GR64_TC
8111 {.RegWeight: 2, .WeightLimit: 2}, // GR64_and_LOW32_ADDR_ACCESS
8112 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
8113 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
8114 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
8115 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
8116 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
8117 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
8118 {.RegWeight: 2, .WeightLimit: 2}, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
8119 {.RegWeight: 0, .WeightLimit: 0}, // RST
8120 {.RegWeight: 1, .WeightLimit: 7}, // RFP80
8121 {.RegWeight: 0, .WeightLimit: 0}, // RFP80_7
8122 {.RegWeight: 1, .WeightLimit: 32}, // VR128X
8123 {.RegWeight: 1, .WeightLimit: 16}, // VR128
8124 {.RegWeight: 1, .WeightLimit: 32}, // VR256X
8125 {.RegWeight: 1, .WeightLimit: 16}, // VR256
8126 {.RegWeight: 1, .WeightLimit: 32}, // VR512
8127 {.RegWeight: 1, .WeightLimit: 16}, // VR512_0_15
8128 {.RegWeight: 1, .WeightLimit: 8}, // TILE
8129 };
8130 return RCWeightTable[RC->getID()];
8131}
8132
8133/// Get the weight in units of pressure for this register unit.
8134unsigned X86GenRegisterInfo::
8135getRegUnitWeight(MCRegUnit RegUnit) const {
8136 assert(static_cast<unsigned>(RegUnit) < 221 && "invalid register unit");
8137 // All register units have unit weight.
8138 return 1;
8139}
8140
8141
8142// Get the number of dimensions of register pressure.
8143unsigned X86GenRegisterInfo::getNumRegPressureSets() const {
8144 return 36;
8145}
8146
8147// Get the name of this register unit pressure set.
8148const char *X86GenRegisterInfo::
8149getRegPressureSetName(unsigned Idx) const {
8150 static const char *PressureNameTable[] = {
8151 "SEGMENT_REG",
8152 "GR32_BPSP",
8153 "LOW32_ADDR_ACCESS_with_sub_32bit",
8154 "GR32_BSI",
8155 "GR32_SIDI",
8156 "GR32_DIBP_with_GR32_SIDI",
8157 "GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit",
8158 "RFP32",
8159 "GR8_ABCD_H_with_GR32_BSI",
8160 "GR8_ABCD_L_with_GR32_BSI",
8161 "VK1",
8162 "VR64",
8163 "TILE",
8164 "GR8_NOREX",
8165 "GR32_TC",
8166 "GR32_BPSP_with_GR32_TC",
8167 "FR16",
8168 "DEBUG_REG",
8169 "CONTROL_REG",
8170 "GR64_NOREX",
8171 "GR64_TCW64",
8172 "GR32_BPSP_with_GR64_TCW64",
8173 "GR64_TC_with_GR64_TCW64",
8174 "GR64_TC",
8175 "FR16X",
8176 "GR64PLTSafe_with_GR64_TC",
8177 "GR8",
8178 "GR8_with_GR32_DIBP",
8179 "GR8_with_GR32_BSI",
8180 "GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit",
8181 "GR8_with_GR64_NOREX",
8182 "GR8_with_GR64_TCW64",
8183 "GR8_with_GR64_TC",
8184 "GR8_with_GR64PLTSafe",
8185 "GR8_with_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2",
8186 "GR16",
8187 };
8188 return PressureNameTable[Idx];
8189}
8190
8191// Get the register unit pressure limit for this dimension.
8192// This limit must be adjusted dynamically for reserved registers.
8193unsigned X86GenRegisterInfo::
8194getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
8195 static const uint8_t PressureLimitTable[] = {
8196 6, // 0: SEGMENT_REG
8197 6, // 1: GR32_BPSP
8198 6, // 2: LOW32_ADDR_ACCESS_with_sub_32bit
8199 6, // 3: GR32_BSI
8200 6, // 4: GR32_SIDI
8201 6, // 5: GR32_DIBP_with_GR32_SIDI
8202 6, // 6: GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit
8203 7, // 7: RFP32
8204 7, // 8: GR8_ABCD_H_with_GR32_BSI
8205 7, // 9: GR8_ABCD_L_with_GR32_BSI
8206 8, // 10: VK1
8207 8, // 11: VR64
8208 8, // 12: TILE
8209 10, // 13: GR8_NOREX
8210 12, // 14: GR32_TC
8211 12, // 15: GR32_BPSP_with_GR32_TC
8212 16, // 16: FR16
8213 16, // 17: DEBUG_REG
8214 16, // 18: CONTROL_REG
8215 18, // 19: GR64_NOREX
8216 20, // 20: GR64_TCW64
8217 20, // 21: GR32_BPSP_with_GR64_TCW64
8218 22, // 22: GR64_TC_with_GR64_TCW64
8219 26, // 23: GR64_TC
8220 32, // 24: FR16X
8221 34, // 25: GR64PLTSafe_with_GR64_TC
8222 38, // 26: GR8
8223 38, // 27: GR8_with_GR32_DIBP
8224 38, // 28: GR8_with_GR32_BSI
8225 39, // 29: GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit
8226 42, // 30: GR8_with_GR64_NOREX
8227 43, // 31: GR8_with_GR64_TCW64
8228 44, // 32: GR8_with_GR64_TC
8229 45, // 33: GR8_with_GR64PLTSafe
8230 48, // 34: GR8_with_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
8231 66, // 35: GR16
8232 };
8233 return PressureLimitTable[Idx];
8234}
8235
8236/// Table of pressure sets per register class or unit.
8237static const int RCSetsTable[] = {
8238 /* 0 */ 0, -1,
8239 /* 2 */ 7, -1,
8240 /* 4 */ 10, -1,
8241 /* 6 */ 11, -1,
8242 /* 8 */ 12, -1,
8243 /* 10 */ 17, -1,
8244 /* 12 */ 18, -1,
8245 /* 14 */ 16, 24, -1,
8246 /* 17 */ 25, 35, -1,
8247 /* 20 */ 19, 23, 25, 30, 35, -1,
8248 /* 26 */ 2, 6, 15, 19, 21, 23, 25, 29, 30, 35, -1,
8249 /* 37 */ 20, 21, 22, 23, 25, 31, 35, -1,
8250 /* 45 */ 22, 23, 25, 32, 35, -1,
8251 /* 51 */ 19, 22, 23, 25, 30, 32, 35, -1,
8252 /* 59 */ 20, 21, 22, 23, 25, 31, 32, 35, -1,
8253 /* 68 */ 14, 15, 19, 20, 21, 22, 23, 25, 30, 31, 32, 35, -1,
8254 /* 81 */ 2, 6, 14, 15, 19, 20, 21, 22, 23, 25, 29, 30, 31, 32, 35, -1,
8255 /* 97 */ 25, 34, 35, -1,
8256 /* 101 */ 19, 23, 25, 30, 34, 35, -1,
8257 /* 108 */ 1, 2, 15, 19, 21, 23, 25, 26, 30, 34, 35, -1,
8258 /* 120 */ 20, 21, 22, 23, 25, 31, 34, 35, -1,
8259 /* 129 */ 22, 23, 25, 32, 34, 35, -1,
8260 /* 136 */ 19, 22, 23, 25, 30, 32, 34, 35, -1,
8261 /* 145 */ 20, 21, 22, 23, 25, 31, 32, 34, 35, -1,
8262 /* 155 */ 1, 2, 14, 15, 19, 20, 21, 22, 23, 25, 26, 30, 31, 32, 34, 35, -1,
8263 /* 172 */ 25, 33, 34, 35, -1,
8264 /* 177 */ 19, 23, 25, 30, 33, 34, 35, -1,
8265 /* 185 */ 1, 5, 6, 19, 23, 25, 27, 30, 33, 34, 35, -1,
8266 /* 197 */ 1, 2, 5, 6, 15, 19, 21, 23, 25, 26, 27, 29, 30, 33, 34, 35, -1,
8267 /* 214 */ 22, 23, 25, 32, 33, 34, 35, -1,
8268 /* 222 */ 3, 4, 8, 9, 13, 19, 23, 25, 28, 30, 32, 33, 34, 35, -1,
8269 /* 237 */ 4, 5, 19, 22, 23, 25, 28, 30, 32, 33, 34, 35, -1,
8270 /* 250 */ 3, 4, 5, 8, 9, 13, 19, 22, 23, 25, 28, 30, 32, 33, 34, 35, -1,
8271 /* 267 */ 1, 4, 5, 6, 19, 22, 23, 25, 27, 28, 30, 32, 33, 34, 35, -1,
8272 /* 283 */ 20, 21, 22, 23, 25, 31, 32, 33, 34, 35, -1,
8273 /* 294 */ 3, 13, 14, 19, 20, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8274 /* 312 */ 8, 13, 14, 19, 20, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8275 /* 330 */ 3, 4, 8, 9, 13, 14, 19, 20, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8276 /* 351 */ 1, 2, 5, 6, 15, 19, 21, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8277 /* 371 */ 1, 4, 5, 6, 19, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8278 /* 390 */ 3, 4, 5, 8, 9, 13, 19, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8279 /* 411 */ 1, 2, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8280 /* 432 */ 3, 13, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8281 /* 453 */ 3, 8, 13, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8282 /* 475 */ 3, 9, 13, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
8283};
8284
8285/// Get the dimensions of register pressure impacted by this register class.
8286/// Returns a -1 terminated array of pressure set IDs
8287const int *X86GenRegisterInfo::
8288getRegClassPressureSets(const TargetRegisterClass *RC) const {
8289 static const uint16_t RCSetStartTable[] = {
8290 301,1,300,295,312,333,1,18,97,101,4,4,4,4,4,4,4,4,4,4,0,295,1,15,14,4,4,4,4,4,4,18,18,18,15,18,18,97,10,14,97,97,101,101,4,177,2,4,295,157,433,433,433,108,222,294,433,185,237,26,1,1,330,433,432,197,155,250,267,197,81,2,18,15,18,18,17,12,14,97,97,172,45,20,37,129,129,120,59,101,4,6,214,120,177,51,145,4,145,136,283,239,68,295,157,433,433,120,26,433,108,222,294,185,237,433,145,81,330,433,432,197,155,250,267,1,2,1,15,14,15,14,15,14,8,};
8291 return &RCSetsTable[RCSetStartTable[RC->getID()]];
8292}
8293
8294/// Get the dimensions of register pressure impacted by this register unit.
8295/// Returns a -1 terminated array of pressure set IDs
8296const int *X86GenRegisterInfo::
8297getRegUnitPressureSets(MCRegUnit RegUnit) const {
8298 assert(static_cast<unsigned>(RegUnit) < 221 && "invalid register unit");
8299 static const uint16_t RUSetStartTable[] = {
8300 454,476,330,330,351,1,453,475,0,1,454,371,1,476,0,1,1,1,1,1,1,1,81,1,1,0,390,1,1,411,1,1,1,1,0,1,0,1,1,1,1,0,1,1,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,2,2,2,2,2,2,2,1,6,6,6,6,6,6,6,6,416,1,1,416,1,1,416,1,1,416,1,1,300,1,1,300,1,1,300,1,1,300,1,1,1,1,1,1,1,1,1,1,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,4,4,4,4,4,4,4,4,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,1,8,8,8,8,8,8,8,8,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,};
8301 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
8302}
8303
8304extern const MCRegisterDesc X86RegDesc[];
8305extern const int16_t X86RegDiffLists[];
8306extern const LaneBitmask X86LaneMaskLists[];
8307extern const char X86RegStrings[];
8308extern const char X86RegClassStrings[];
8309extern const MCPhysReg X86RegUnitRoots[][2];
8310extern const uint16_t X86SubRegIdxLists[];
8311extern const uint16_t X86RegEncodingTable[];
8312// X86 Dwarf<->LLVM register mappings.
8313extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[];
8314extern const unsigned X86DwarfFlavour0Dwarf2LSize;
8315
8316extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[];
8317extern const unsigned X86DwarfFlavour1Dwarf2LSize;
8318
8319extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[];
8320extern const unsigned X86DwarfFlavour2Dwarf2LSize;
8321
8322extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[];
8323extern const unsigned X86EHFlavour0Dwarf2LSize;
8324
8325extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[];
8326extern const unsigned X86EHFlavour1Dwarf2LSize;
8327
8328extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[];
8329extern const unsigned X86EHFlavour2Dwarf2LSize;
8330
8331extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[];
8332extern const unsigned X86DwarfFlavour0L2DwarfSize;
8333
8334extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[];
8335extern const unsigned X86DwarfFlavour1L2DwarfSize;
8336
8337extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[];
8338extern const unsigned X86DwarfFlavour2L2DwarfSize;
8339
8340extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[];
8341extern const unsigned X86EHFlavour0L2DwarfSize;
8342
8343extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[];
8344extern const unsigned X86EHFlavour1L2DwarfSize;
8345
8346extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[];
8347extern const unsigned X86EHFlavour2L2DwarfSize;
8348
8349
8350X86GenRegisterInfo::
8351X86GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
8352 unsigned PC, unsigned HwMode)
8353 : TargetRegisterInfo(&X86RegInfoDesc, X86RegisterClasses,
8354 X86SubRegIndexStrings, X86SubRegIndexNameOffsets,
8355 X86SubRegIdxRangeTable, X86SubRegIndexLaneMaskTable,
8356
8357 LaneBitmask(0xFFFFFFFFFFFFFFB0), X86RegClassInfos, X86VTLists, HwMode) {
8358 InitMCRegisterInfo(D: X86RegDesc, NR: 388, RA, PC,
8359 C: X86MCRegisterClasses, NC: 135, RURoots: X86RegUnitRoots, NRU: 221, DL: X86RegDiffLists,
8360 RUMS: X86LaneMaskLists, Strings: X86RegStrings, ClassStrings: X86RegClassStrings, SubIndices: X86SubRegIdxLists, NumIndices: 11,
8361 RET: X86RegEncodingTable, RUI: nullptr);
8362
8363 switch (DwarfFlavour) {
8364 default:
8365 llvm_unreachable("Unknown DWARF flavour");
8366 case 0:
8367 mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour0Dwarf2L, Size: X86DwarfFlavour0Dwarf2LSize, isEH: false);
8368 break;
8369 case 1:
8370 mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour1Dwarf2L, Size: X86DwarfFlavour1Dwarf2LSize, isEH: false);
8371 break;
8372 case 2:
8373 mapDwarfRegsToLLVMRegs(Map: X86DwarfFlavour2Dwarf2L, Size: X86DwarfFlavour2Dwarf2LSize, isEH: false);
8374 break;
8375 }
8376 switch (EHFlavour) {
8377 default:
8378 llvm_unreachable("Unknown DWARF flavour");
8379 case 0:
8380 mapDwarfRegsToLLVMRegs(Map: X86EHFlavour0Dwarf2L, Size: X86EHFlavour0Dwarf2LSize, isEH: true);
8381 break;
8382 case 1:
8383 mapDwarfRegsToLLVMRegs(Map: X86EHFlavour1Dwarf2L, Size: X86EHFlavour1Dwarf2LSize, isEH: true);
8384 break;
8385 case 2:
8386 mapDwarfRegsToLLVMRegs(Map: X86EHFlavour2Dwarf2L, Size: X86EHFlavour2Dwarf2LSize, isEH: true);
8387 break;
8388 }
8389 switch (DwarfFlavour) {
8390 default:
8391 llvm_unreachable("Unknown DWARF flavour");
8392 case 0:
8393 mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour0L2Dwarf, Size: X86DwarfFlavour0L2DwarfSize, isEH: false);
8394 break;
8395 case 1:
8396 mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour1L2Dwarf, Size: X86DwarfFlavour1L2DwarfSize, isEH: false);
8397 break;
8398 case 2:
8399 mapLLVMRegsToDwarfRegs(Map: X86DwarfFlavour2L2Dwarf, Size: X86DwarfFlavour2L2DwarfSize, isEH: false);
8400 break;
8401 }
8402 switch (EHFlavour) {
8403 default:
8404 llvm_unreachable("Unknown DWARF flavour");
8405 case 0:
8406 mapLLVMRegsToDwarfRegs(Map: X86EHFlavour0L2Dwarf, Size: X86EHFlavour0L2DwarfSize, isEH: true);
8407 break;
8408 case 1:
8409 mapLLVMRegsToDwarfRegs(Map: X86EHFlavour1L2Dwarf, Size: X86EHFlavour1L2DwarfSize, isEH: true);
8410 break;
8411 case 2:
8412 mapLLVMRegsToDwarfRegs(Map: X86EHFlavour2L2Dwarf, Size: X86EHFlavour2L2DwarfSize, isEH: true);
8413 break;
8414 }
8415}
8416
8417static const MCPhysReg CSR_32_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
8418static const uint32_t CSR_32_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8419static const MCPhysReg CSR_32EHRet_SaveList[] = { X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
8420static const uint32_t CSR_32EHRet_RegMask[] = { 0x0def83fe, 0xc000b701, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8421static const MCPhysReg CSR_32_AllRegs_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, 0 };
8422static const uint32_t CSR_32_AllRegs_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8423static const MCPhysReg CSR_32_AllRegs_AVX_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, 0 };
8424static const uint32_t CSR_32_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00007f80, 0x80000000, 0x0000007f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8425static const MCPhysReg CSR_32_AllRegs_AVX512_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
8426static const uint32_t CSR_32_AllRegs_AVX512_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00007f80, 0x80000000, 0x007f807f, 0x7f800000, 0x07800000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8427static const MCPhysReg CSR_32_AllRegs_SSE_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
8428static const uint32_t CSR_32_AllRegs_SSE_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00007f80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8429static const MCPhysReg CSR_32_RegCall_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
8430static const uint32_t CSR_32_RegCall_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00007800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8431static const MCPhysReg CSR_32_RegCall_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
8432static const uint32_t CSR_32_RegCall_NoSSE_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8433static const MCPhysReg CSR_64_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
8434static const uint32_t CSR_64_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8435static const MCPhysReg CSR_64EHRet_SaveList[] = { X86::RAX, X86::RDX, X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
8436static const uint32_t CSR_64EHRet_RegMask[] = { 0x09e883fe, 0x01382700, 0x00000000, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8437static const MCPhysReg CSR_64_AllRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::RAX, 0 };
8438static const uint32_t CSR_64_AllRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xffffff80, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8439static const MCPhysReg CSR_64_AllRegs_AVX_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
8440static const uint32_t CSR_64_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xffffff80, 0xffffffff, 0x00007fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8441static const MCPhysReg CSR_64_AllRegs_AVX512_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
8442static const uint32_t CSR_64_AllRegs_AVX512_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xffffff80, 0xffffffff, 0xffffffff, 0xffffffff, 0x07ffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8443static const MCPhysReg CSR_64_AllRegs_NoSSE_SaveList[] = { X86::RAX, X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
8444static const uint32_t CSR_64_AllRegs_NoSSE_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xff800000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8445static const MCPhysReg CSR_64_CXX_TLS_Darwin_PE_SaveList[] = { X86::RBP, 0 };
8446static const uint32_t CSR_64_CXX_TLS_Darwin_PE_RegMask[] = { 0x008001c0, 0x00100200, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8447static const MCPhysReg CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 };
8448static const uint32_t CSR_64_CXX_TLS_Darwin_ViaCopy_RegMask[] = { 0x0b28ae30, 0xd160ac01, 0x00000001, 0x7f800000, 0xff800000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8449static const MCPhysReg CSR_64_Intel_OCL_BI_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
8450static const uint32_t CSR_64_Intel_OCL_BI_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x787f8000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8451static const MCPhysReg CSR_64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
8452static const uint32_t CSR_64_Intel_OCL_BI_AVX_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x787f8000, 0x78787878, 0x00007f80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8453static const MCPhysReg CSR_64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RSI, X86::R14, X86::R15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
8454static const uint32_t CSR_64_Intel_OCL_BI_AVX512_RegMask[] = { 0x01000230, 0xd0208401, 0x00000001, 0x60000000, 0x60000000, 0x60606060, 0xfff80000, 0x007fffff, 0x067fff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8455static const MCPhysReg CSR_64_MostRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
8456static const uint32_t CSR_64_MostRegs_RegMask[] = { 0x0fafaff0, 0xd1f0be01, 0x00000001, 0x7f800000, 0xffffff80, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8457static const MCPhysReg CSR_64_NoneRegs_SaveList[] = { X86::RBP, 0 };
8458static const uint32_t CSR_64_NoneRegs_RegMask[] = { 0x008001c0, 0x00100200, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8459static const MCPhysReg CSR_64_RT_AllRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
8460static const uint32_t CSR_64_RT_AllRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffff80, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8461static const MCPhysReg CSR_64_RT_AllRegs_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
8462static const uint32_t CSR_64_RT_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffff80, 0xfbfbfbfb, 0x00007fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8463static const MCPhysReg CSR_64_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, 0 };
8464static const uint32_t CSR_64_RT_MostRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfb800000, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8465static const MCPhysReg CSR_64_SwiftError_SaveList[] = { X86::RBX, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
8466static const uint32_t CSR_64_SwiftError_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x70000000, 0x70000000, 0x70707070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8467static const MCPhysReg CSR_64_SwiftTail_SaveList[] = { X86::RBX, X86::R12, X86::R15, X86::RBP, 0 };
8468static const uint32_t CSR_64_SwiftTail_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x48000000, 0x48000000, 0x48484848, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8469static const MCPhysReg CSR_64_TLS_Darwin_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 };
8470static const uint32_t CSR_64_TLS_Darwin_RegMask[] = { 0x0ba8aff0, 0xd170ae01, 0x00000001, 0x7f800000, 0xff800000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8471static const MCPhysReg CSR_IPRA_32_SaveList[] = { X86::EBP, X86::ESI, 0 };
8472static const uint32_t CSR_IPRA_32_RegMask[] = { 0x008001c0, 0xc0008201, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8473static const MCPhysReg CSR_IPRA_64_SaveList[] = { X86::RBP, X86::RBX, 0 };
8474static const uint32_t CSR_IPRA_64_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8475static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
8476static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8477static const MCPhysReg CSR_SysV64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
8478static const uint32_t CSR_SysV64_RegCall_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x787f8000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8479static const MCPhysReg CSR_SysV64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
8480static const uint32_t CSR_SysV64_RegCall_NoSSE_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8481static const MCPhysReg CSR_Win32_CFGuard_Check_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::ECX, 0 };
8482static const uint32_t CSR_Win32_CFGuard_Check_RegMask[] = { 0x07872ff0, 0xc0009e01, 0x00000001, 0x00000000, 0x00007800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8483static const MCPhysReg CSR_Win32_CFGuard_Check_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ECX, 0 };
8484static const uint32_t CSR_Win32_CFGuard_Check_NoSSE_RegMask[] = { 0x07872ff0, 0xc0009e01, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8485static const MCPhysReg CSR_Win64_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
8486static const uint32_t CSR_Win64_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8487static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
8488static const uint32_t CSR_Win64_Intel_OCL_BI_AVX_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x00007fe0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8489static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
8490static const uint32_t CSR_Win64_Intel_OCL_BI_AVX512_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x1ff87fe0, 0xe0001f80, 0x06001fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8491static const MCPhysReg CSR_Win64_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
8492static const uint32_t CSR_Win64_NoSSE_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8493static const MCPhysReg CSR_Win64_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
8494static const uint32_t CSR_Win64_RT_MostRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffe000, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8495static const MCPhysReg CSR_Win64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
8496static const uint32_t CSR_Win64_RegCall_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x7e000000, 0x7e7f8000, 0x7e7e7e7e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8497static const MCPhysReg CSR_Win64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
8498static const uint32_t CSR_Win64_RegCall_NoSSE_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x7e000000, 0x7e000000, 0x7e7e7e7e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8499static const MCPhysReg CSR_Win64_SwiftError_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
8500static const uint32_t CSR_Win64_SwiftError_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x70000000, 0x707fe000, 0x70707070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8501static const MCPhysReg CSR_Win64_SwiftTail_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
8502static const uint32_t CSR_Win64_SwiftTail_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x48000000, 0x487fe000, 0x48484848, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
8503
8504
8505ArrayRef<const uint32_t *> X86GenRegisterInfo::getRegMasks() const {
8506 static const uint32_t *const Masks[] = {
8507 CSR_32_RegMask,
8508 CSR_32EHRet_RegMask,
8509 CSR_32_AllRegs_RegMask,
8510 CSR_32_AllRegs_AVX_RegMask,
8511 CSR_32_AllRegs_AVX512_RegMask,
8512 CSR_32_AllRegs_SSE_RegMask,
8513 CSR_32_RegCall_RegMask,
8514 CSR_32_RegCall_NoSSE_RegMask,
8515 CSR_64_RegMask,
8516 CSR_64EHRet_RegMask,
8517 CSR_64_AllRegs_RegMask,
8518 CSR_64_AllRegs_AVX_RegMask,
8519 CSR_64_AllRegs_AVX512_RegMask,
8520 CSR_64_AllRegs_NoSSE_RegMask,
8521 CSR_64_CXX_TLS_Darwin_PE_RegMask,
8522 CSR_64_CXX_TLS_Darwin_ViaCopy_RegMask,
8523 CSR_64_Intel_OCL_BI_RegMask,
8524 CSR_64_Intel_OCL_BI_AVX_RegMask,
8525 CSR_64_Intel_OCL_BI_AVX512_RegMask,
8526 CSR_64_MostRegs_RegMask,
8527 CSR_64_NoneRegs_RegMask,
8528 CSR_64_RT_AllRegs_RegMask,
8529 CSR_64_RT_AllRegs_AVX_RegMask,
8530 CSR_64_RT_MostRegs_RegMask,
8531 CSR_64_SwiftError_RegMask,
8532 CSR_64_SwiftTail_RegMask,
8533 CSR_64_TLS_Darwin_RegMask,
8534 CSR_IPRA_32_RegMask,
8535 CSR_IPRA_64_RegMask,
8536 CSR_NoRegs_RegMask,
8537 CSR_SysV64_RegCall_RegMask,
8538 CSR_SysV64_RegCall_NoSSE_RegMask,
8539 CSR_Win32_CFGuard_Check_RegMask,
8540 CSR_Win32_CFGuard_Check_NoSSE_RegMask,
8541 CSR_Win64_RegMask,
8542 CSR_Win64_Intel_OCL_BI_AVX_RegMask,
8543 CSR_Win64_Intel_OCL_BI_AVX512_RegMask,
8544 CSR_Win64_NoSSE_RegMask,
8545 CSR_Win64_RT_MostRegs_RegMask,
8546 CSR_Win64_RegCall_RegMask,
8547 CSR_Win64_RegCall_NoSSE_RegMask,
8548 CSR_Win64_SwiftError_RegMask,
8549 CSR_Win64_SwiftTail_RegMask,
8550 };
8551 return ArrayRef(Masks);
8552}
8553
8554bool X86GenRegisterInfo::
8555isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
8556 return
8557 X86::GR64RegClass.contains(Reg: PhysReg) ||
8558 X86::GR32RegClass.contains(Reg: PhysReg) ||
8559 X86::GR16RegClass.contains(Reg: PhysReg) ||
8560 X86::GR8RegClass.contains(Reg: PhysReg) ||
8561 false;
8562}
8563
8564bool X86GenRegisterInfo::
8565isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
8566 return
8567 X86::GR64RegClass.hasSubClassEq(RC) ||
8568 X86::GR32RegClass.hasSubClassEq(RC) ||
8569 X86::GR16RegClass.hasSubClassEq(RC) ||
8570 X86::GR8RegClass.hasSubClassEq(RC) ||
8571 false;
8572}
8573
8574bool X86GenRegisterInfo::
8575isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
8576 return
8577 X86::DEBUG_REGRegClass.contains(Reg: PhysReg) ||
8578 X86::CONTROL_REGRegClass.contains(Reg: PhysReg) ||
8579 X86::CCRRegClass.contains(Reg: PhysReg) ||
8580 X86::FPCCRRegClass.contains(Reg: PhysReg) ||
8581 X86::DFCCRRegClass.contains(Reg: PhysReg) ||
8582 X86::TILERegClass.contains(Reg: PhysReg) ||
8583 X86::VK1PAIRRegClass.contains(Reg: PhysReg) ||
8584 X86::VK2PAIRRegClass.contains(Reg: PhysReg) ||
8585 X86::VK4PAIRRegClass.contains(Reg: PhysReg) ||
8586 X86::VK8PAIRRegClass.contains(Reg: PhysReg) ||
8587 X86::VK16PAIRRegClass.contains(Reg: PhysReg) ||
8588 false;
8589}
8590
8591bool X86GenRegisterInfo::
8592isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
8593 return
8594 false;
8595}
8596
8597bool X86GenRegisterInfo::
8598isConstantPhysReg(MCRegister PhysReg) const {
8599 return
8600 false;
8601}
8602
8603ArrayRef<const char *> X86GenRegisterInfo::getRegMaskNames() const {
8604 static const char *Names[] = {
8605 "CSR_32",
8606 "CSR_32EHRet",
8607 "CSR_32_AllRegs",
8608 "CSR_32_AllRegs_AVX",
8609 "CSR_32_AllRegs_AVX512",
8610 "CSR_32_AllRegs_SSE",
8611 "CSR_32_RegCall",
8612 "CSR_32_RegCall_NoSSE",
8613 "CSR_64",
8614 "CSR_64EHRet",
8615 "CSR_64_AllRegs",
8616 "CSR_64_AllRegs_AVX",
8617 "CSR_64_AllRegs_AVX512",
8618 "CSR_64_AllRegs_NoSSE",
8619 "CSR_64_CXX_TLS_Darwin_PE",
8620 "CSR_64_CXX_TLS_Darwin_ViaCopy",
8621 "CSR_64_Intel_OCL_BI",
8622 "CSR_64_Intel_OCL_BI_AVX",
8623 "CSR_64_Intel_OCL_BI_AVX512",
8624 "CSR_64_MostRegs",
8625 "CSR_64_NoneRegs",
8626 "CSR_64_RT_AllRegs",
8627 "CSR_64_RT_AllRegs_AVX",
8628 "CSR_64_RT_MostRegs",
8629 "CSR_64_SwiftError",
8630 "CSR_64_SwiftTail",
8631 "CSR_64_TLS_Darwin",
8632 "CSR_IPRA_32",
8633 "CSR_IPRA_64",
8634 "CSR_NoRegs",
8635 "CSR_SysV64_RegCall",
8636 "CSR_SysV64_RegCall_NoSSE",
8637 "CSR_Win32_CFGuard_Check",
8638 "CSR_Win32_CFGuard_Check_NoSSE",
8639 "CSR_Win64",
8640 "CSR_Win64_Intel_OCL_BI_AVX",
8641 "CSR_Win64_Intel_OCL_BI_AVX512",
8642 "CSR_Win64_NoSSE",
8643 "CSR_Win64_RT_MostRegs",
8644 "CSR_Win64_RegCall",
8645 "CSR_Win64_RegCall_NoSSE",
8646 "CSR_Win64_SwiftError",
8647 "CSR_Win64_SwiftTail",
8648 };
8649 return ArrayRef(Names);
8650}
8651
8652const X86FrameLowering *
8653X86GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
8654 return static_cast<const X86FrameLowering *>(
8655 MF.getSubtarget().getFrameLowering());
8656}
8657
8658
8659} // namespace llvm
8660