1//===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the X86 implementation of the TargetRegisterInfo class.
10// This file is responsible for the frame pointer elimination optimization
11// on X86.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86RegisterInfo.h"
16#include "X86FrameLowering.h"
17#include "X86MachineFunctionInfo.h"
18#include "X86Subtarget.h"
19#include "llvm/ADT/BitVector.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/ADT/SmallSet.h"
22#include "llvm/CodeGen/LiveRegMatrix.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/RegisterScavenging.h"
26#include "llvm/CodeGen/TargetFrameLowering.h"
27#include "llvm/CodeGen/TargetInstrInfo.h"
28#include "llvm/CodeGen/TileShapeInfo.h"
29#include "llvm/CodeGen/VirtRegMap.h"
30#include "llvm/IR/Function.h"
31#include "llvm/IR/Type.h"
32#include "llvm/MC/MCContext.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Target/TargetMachine.h"
35
36using namespace llvm;
37
38#define GET_REGINFO_TARGET_DESC
39#include "X86GenRegisterInfo.inc"
40
41X86RegisterInfo::X86RegisterInfo(const Triple &TT)
42 : X86GenRegisterInfo((TT.isX86_64() ? X86::RIP : X86::EIP),
43 X86_MC::getDwarfRegFlavour(TT, isEH: false),
44 X86_MC::getDwarfRegFlavour(TT, isEH: true),
45 (TT.isX86_64() ? X86::RIP : X86::EIP)) {
46 X86_MC::initLLVMToSEHAndCVRegMapping(MRI: this);
47
48 // Cache some information.
49 Is64Bit = TT.isX86_64();
50 IsTarget64BitLP64 = Is64Bit && !TT.isX32();
51 IsWin64 = Is64Bit && TT.isOSWindows();
52 IsUEFI64 = Is64Bit && TT.isUEFI();
53
54 // Use a callee-saved register as the base pointer. These registers must
55 // not conflict with any ABI requirements. For example, in 32-bit mode PIC
56 // requires GOT in the EBX register before function calls via PLT GOT pointer.
57 if (Is64Bit) {
58 SlotSize = 8;
59 // This matches the simplified 32-bit pointer code in the data layout
60 // computation.
61 // FIXME: Should use the data layout?
62 bool Use64BitReg = !TT.isX32();
63 StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
64 FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
65 BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
66 } else {
67 SlotSize = 4;
68 StackPtr = X86::ESP;
69 FramePtr = X86::EBP;
70 BasePtr = X86::ESI;
71 }
72}
73
74const TargetRegisterClass *
75X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
76 unsigned Idx) const {
77 // The sub_8bit sub-register index is more constrained in 32-bit mode.
78 // It behaves just like the sub_8bit_hi index.
79 if (!Is64Bit && Idx == X86::sub_8bit)
80 Idx = X86::sub_8bit_hi;
81
82 // Forward to TableGen's default version.
83 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
84}
85
86const TargetRegisterClass *
87X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
88 const TargetRegisterClass *B,
89 unsigned SubIdx) const {
90 // The sub_8bit sub-register index is more constrained in 32-bit mode.
91 if (!Is64Bit && SubIdx == X86::sub_8bit) {
92 A = X86GenRegisterInfo::getSubClassWithSubReg(RC: A, Idx: X86::sub_8bit_hi);
93 if (!A)
94 return nullptr;
95 }
96 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, Idx: SubIdx);
97}
98
99const TargetRegisterClass *
100X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
101 const MachineFunction &MF) const {
102 // Don't allow super-classes of GR8_NOREX. This class is only used after
103 // extracting sub_8bit_hi sub-registers. The H sub-registers cannot be copied
104 // to the full GR8 register class in 64-bit mode, so we cannot allow the
105 // reigster class inflation.
106 //
107 // The GR8_NOREX class is always used in a way that won't be constrained to a
108 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
109 // full GR8 class.
110 if (RC == &X86::GR8_NOREXRegClass)
111 return RC;
112
113 // Keep using non-rex2 register class when APX feature (EGPR/NDD/NF) is not
114 // enabled for relocation.
115 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
116 if (!Subtarget.getCLOpts().enable_apx_for_relocation && isNonRex2RegClass(RC))
117 return RC;
118
119 const TargetRegisterClass *Super = RC;
120 auto I = RC->superclasses().begin();
121 auto E = RC->superclasses().end();
122 do {
123 switch (Super->getID()) {
124 case X86::FR32RegClassID:
125 case X86::FR64RegClassID:
126 // If AVX-512 isn't supported we should only inflate to these classes.
127 if (!Subtarget.hasAVX512() &&
128 getRegSizeInBits(RC: *Super) == getRegSizeInBits(RC: *RC))
129 return Super;
130 break;
131 case X86::VR128RegClassID:
132 case X86::VR256RegClassID:
133 // If VLX isn't supported we should only inflate to these classes.
134 if (!Subtarget.hasVLX() &&
135 getRegSizeInBits(RC: *Super) == getRegSizeInBits(RC: *RC))
136 return Super;
137 break;
138 case X86::VR128XRegClassID:
139 case X86::VR256XRegClassID:
140 // If VLX isn't support we shouldn't inflate to these classes.
141 if (Subtarget.hasVLX() &&
142 getRegSizeInBits(RC: *Super) == getRegSizeInBits(RC: *RC))
143 return Super;
144 break;
145 case X86::FR32XRegClassID:
146 case X86::FR64XRegClassID:
147 // If AVX-512 isn't support we shouldn't inflate to these classes.
148 if (Subtarget.hasAVX512() &&
149 getRegSizeInBits(RC: *Super) == getRegSizeInBits(RC: *RC))
150 return Super;
151 break;
152 case X86::GR8RegClassID:
153 case X86::GR16RegClassID:
154 case X86::GR32RegClassID:
155 case X86::GR64RegClassID:
156 case X86::GR8_NOREX2RegClassID:
157 case X86::GR16_NOREX2RegClassID:
158 case X86::GR32_NOREX2RegClassID:
159 case X86::GR64_NOREX2RegClassID:
160 case X86::RFP32RegClassID:
161 case X86::RFP64RegClassID:
162 case X86::RFP80RegClassID:
163 case X86::VR512_0_15RegClassID:
164 case X86::VR512RegClassID:
165 // Don't return a super-class that would shrink the spill size.
166 // That can happen with the vector and float classes.
167 if (getRegSizeInBits(RC: *Super) == getRegSizeInBits(RC: *RC))
168 return Super;
169 }
170 if (I != E) {
171 Super = getRegClass(i: *I);
172 ++I;
173 } else {
174 Super = nullptr;
175 }
176 } while (Super);
177 return RC;
178}
179
180const TargetRegisterClass *
181X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
182 if (RC == &X86::CCRRegClass) {
183 if (Is64Bit)
184 return &X86::GR64RegClass;
185 else
186 return &X86::GR32RegClass;
187 }
188 return RC;
189}
190
191unsigned
192X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
193 MachineFunction &MF) const {
194 const X86FrameLowering *TFI = getFrameLowering(MF);
195
196 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
197 switch (RC->getID()) {
198 default:
199 return 0;
200 case X86::GR32RegClassID:
201 return 4 - FPDiff;
202 case X86::GR64RegClassID:
203 return 12 - FPDiff;
204 case X86::VR128RegClassID:
205 return Is64Bit ? 10 : 4;
206 case X86::VR64RegClassID:
207 return 4;
208 }
209}
210
211const MCPhysReg *
212X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
213 assert(MF && "MachineFunction required");
214
215 const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
216 const Function &F = MF->getFunction();
217 bool HasSSE = Subtarget.hasSSE1();
218 bool HasAVX = Subtarget.hasAVX();
219 bool HasAVX512 = Subtarget.hasAVX512();
220 bool HasEGPR = Subtarget.hasEGPR();
221 bool CallsEHReturn = MF->callsEHReturn();
222
223 CallingConv::ID CC = F.getCallingConv();
224
225 // If attribute NoCallerSavedRegisters exists then we set X86_INTR calling
226 // convention because it has the CSR list.
227 if (MF->getFunction().hasFnAttribute(Kind: "no_caller_saved_registers"))
228 CC = CallingConv::X86_INTR;
229
230 // If atribute specified, override the CSRs normally specified by the
231 // calling convention and use the empty set instead.
232 if (MF->getFunction().hasFnAttribute(Kind: "no_callee_saved_registers"))
233 return CSR_NoRegs_SaveList;
234
235 switch (CC) {
236 case CallingConv::GHC:
237 case CallingConv::HiPE:
238 return CSR_NoRegs_SaveList;
239 case CallingConv::AnyReg:
240 if (HasAVX)
241 return CSR_64_AllRegs_AVX_SaveList;
242 return CSR_64_AllRegs_SaveList;
243 case CallingConv::PreserveMost:
244 if (IsWin64)
245 return HasEGPR ? CSR_Win64_APX_RT_MostRegs_SaveList
246 : CSR_Win64_RT_MostRegs_SaveList;
247 return CSR_64_RT_MostRegs_SaveList;
248 case CallingConv::PreserveAll:
249 if (HasAVX)
250 return CSR_64_RT_AllRegs_AVX_SaveList;
251 return CSR_64_RT_AllRegs_SaveList;
252 case CallingConv::PreserveNone:
253 return CSR_64_NoneRegs_SaveList;
254 case CallingConv::CXX_FAST_TLS:
255 if (Is64Bit)
256 return MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR() ?
257 CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList;
258 break;
259 case CallingConv::Intel_OCL_BI: {
260 if (HasAVX512 && IsWin64)
261 return HasEGPR ? CSR_Win64_APX_Intel_OCL_BI_AVX512_SaveList
262 : CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
263 if (HasAVX512 && Is64Bit)
264 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
265 if (HasAVX && IsWin64)
266 return HasEGPR ? CSR_Win64_APX_Intel_OCL_BI_AVX_SaveList
267 : CSR_Win64_Intel_OCL_BI_AVX_SaveList;
268 if (HasAVX && Is64Bit)
269 return CSR_64_Intel_OCL_BI_AVX_SaveList;
270 if (!HasAVX && !IsWin64 && Is64Bit)
271 return CSR_64_Intel_OCL_BI_SaveList;
272 break;
273 }
274 case CallingConv::X86_RegCall:
275 if (Is64Bit) {
276 if (IsWin64) {
277 if (HasSSE)
278 return HasEGPR ? CSR_Win64_APX_RegCall_SaveList
279 : CSR_Win64_RegCall_SaveList;
280 return CSR_Win64_RegCall_NoSSE_SaveList;
281 }
282 return HasSSE ? CSR_SysV64_RegCall_SaveList
283 : CSR_SysV64_RegCall_NoSSE_SaveList;
284 }
285 return HasSSE ? CSR_32_RegCall_SaveList : CSR_32_RegCall_NoSSE_SaveList;
286 case CallingConv::CFGuard_Check:
287 assert(!Is64Bit && "CFGuard check mechanism only used on 32-bit X86");
288 return HasSSE ? CSR_Win32_CFGuard_Check_SaveList
289 : CSR_Win32_CFGuard_Check_NoSSE_SaveList;
290 case CallingConv::Cold:
291 if (Is64Bit)
292 return CSR_64_MostRegs_SaveList;
293 break;
294 case CallingConv::Win64:
295 if (HasSSE)
296 return HasEGPR ? CSR_Win64_APX_SaveList : CSR_Win64_SaveList;
297 return CSR_Win64_NoSSE_SaveList;
298 case CallingConv::SwiftTail:
299 if (!Is64Bit)
300 return CSR_32_SaveList;
301 if (IsWin64)
302 return HasEGPR ? CSR_Win64_APX_SwiftTail_SaveList
303 : CSR_Win64_SwiftTail_SaveList;
304 return CSR_64_SwiftTail_SaveList;
305 case CallingConv::X86_64_SysV:
306 if (CallsEHReturn)
307 return CSR_64EHRet_SaveList;
308 return CSR_64_SaveList;
309 case CallingConv::X86_INTR:
310 if (Is64Bit) {
311 if (HasAVX512)
312 return CSR_64_AllRegs_AVX512_SaveList;
313 if (HasAVX)
314 return CSR_64_AllRegs_AVX_SaveList;
315 if (HasSSE)
316 return CSR_64_AllRegs_SaveList;
317 return CSR_64_AllRegs_NoSSE_SaveList;
318 }
319 if (HasAVX512)
320 return CSR_32_AllRegs_AVX512_SaveList;
321 if (HasAVX)
322 return CSR_32_AllRegs_AVX_SaveList;
323 if (HasSSE)
324 return CSR_32_AllRegs_SSE_SaveList;
325 return CSR_32_AllRegs_SaveList;
326 default:
327 break;
328 }
329
330 if (Is64Bit) {
331 bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
332 F.getAttributes().hasAttrSomewhere(Kind: Attribute::SwiftError);
333 if (IsSwiftCC) {
334 if (IsWin64)
335 return HasEGPR ? CSR_Win64_APX_SwiftError_SaveList
336 : CSR_Win64_SwiftError_SaveList;
337 return CSR_64_SwiftError_SaveList;
338 }
339
340 if (IsWin64 || IsUEFI64) {
341 if (HasSSE)
342 return HasEGPR ? CSR_Win64_APX_SaveList : CSR_Win64_SaveList;
343 return CSR_Win64_NoSSE_SaveList;
344 }
345 if (CallsEHReturn)
346 return CSR_64EHRet_SaveList;
347 return CSR_64_SaveList;
348 }
349
350 return CallsEHReturn ? CSR_32EHRet_SaveList : CSR_32_SaveList;
351}
352
353const MCPhysReg *
354X86RegisterInfo::getIPRACSRegs(const MachineFunction *MF) const {
355 return Is64Bit ? CSR_IPRA_64_SaveList : CSR_IPRA_32_SaveList;
356}
357
358const MCPhysReg *X86RegisterInfo::getCalleeSavedRegsViaCopy(
359 const MachineFunction *MF) const {
360 assert(MF && "Invalid MachineFunction pointer.");
361 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
362 MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR())
363 return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
364 return nullptr;
365}
366
367const uint32_t *
368X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
369 CallingConv::ID CC) const {
370 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
371 bool HasSSE = Subtarget.hasSSE1();
372 bool HasAVX = Subtarget.hasAVX();
373 bool HasAVX512 = Subtarget.hasAVX512();
374 bool HasEGPR = Subtarget.hasEGPR();
375
376 switch (CC) {
377 case CallingConv::GHC:
378 case CallingConv::HiPE:
379 return CSR_NoRegs_RegMask;
380 case CallingConv::AnyReg:
381 if (HasAVX)
382 return CSR_64_AllRegs_AVX_RegMask;
383 return CSR_64_AllRegs_RegMask;
384 case CallingConv::PreserveMost:
385 if (IsWin64)
386 return HasEGPR ? CSR_Win64_APX_RT_MostRegs_RegMask
387 : CSR_Win64_RT_MostRegs_RegMask;
388 return CSR_64_RT_MostRegs_RegMask;
389 case CallingConv::PreserveAll:
390 if (HasAVX)
391 return CSR_64_RT_AllRegs_AVX_RegMask;
392 return CSR_64_RT_AllRegs_RegMask;
393 case CallingConv::PreserveNone:
394 return CSR_64_NoneRegs_RegMask;
395 case CallingConv::CXX_FAST_TLS:
396 if (Is64Bit)
397 return CSR_64_TLS_Darwin_RegMask;
398 break;
399 case CallingConv::Intel_OCL_BI: {
400 if (HasAVX512 && IsWin64)
401 return HasEGPR ? CSR_Win64_APX_Intel_OCL_BI_AVX512_RegMask
402 : CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
403 if (HasAVX512 && Is64Bit)
404 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
405 if (HasAVX && IsWin64)
406 return HasEGPR ? CSR_Win64_APX_Intel_OCL_BI_AVX_RegMask
407 : CSR_Win64_Intel_OCL_BI_AVX_RegMask;
408 if (HasAVX && Is64Bit)
409 return CSR_64_Intel_OCL_BI_AVX_RegMask;
410 if (!HasAVX && !IsWin64 && Is64Bit)
411 return CSR_64_Intel_OCL_BI_RegMask;
412 break;
413 }
414 case CallingConv::X86_RegCall:
415 if (Is64Bit) {
416 if (IsWin64) {
417 if (HasSSE)
418 return HasEGPR ? CSR_Win64_APX_RegCall_RegMask
419 : CSR_Win64_RegCall_RegMask;
420 return CSR_Win64_RegCall_NoSSE_RegMask;
421 }
422 return HasSSE ? CSR_SysV64_RegCall_RegMask
423 : CSR_SysV64_RegCall_NoSSE_RegMask;
424 }
425 return HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask;
426 case CallingConv::CFGuard_Check:
427 if (Is64Bit) {
428 if (HasSSE)
429 return HasEGPR ? CSR_Win64_APX_CFGuard_Check_RegMask
430 : CSR_Win64_CFGuard_Check_RegMask;
431 return CSR_Win64_CFGuard_Check_NoSSE_RegMask;
432 }
433 return HasSSE ? CSR_Win32_CFGuard_Check_RegMask
434 : CSR_Win32_CFGuard_Check_NoSSE_RegMask;
435 case CallingConv::Cold:
436 if (Is64Bit)
437 return CSR_64_MostRegs_RegMask;
438 break;
439 case CallingConv::Win64:
440 return HasEGPR ? CSR_Win64_APX_RegMask : CSR_Win64_RegMask;
441 case CallingConv::SwiftTail:
442 if (!Is64Bit)
443 return CSR_32_RegMask;
444 if (IsWin64)
445 return HasEGPR ? CSR_Win64_APX_SwiftTail_RegMask
446 : CSR_Win64_SwiftTail_RegMask;
447 return CSR_64_SwiftTail_RegMask;
448 case CallingConv::X86_64_SysV:
449 return CSR_64_RegMask;
450 case CallingConv::X86_INTR:
451 if (Is64Bit) {
452 if (HasAVX512)
453 return CSR_64_AllRegs_AVX512_RegMask;
454 if (HasAVX)
455 return CSR_64_AllRegs_AVX_RegMask;
456 if (HasSSE)
457 return CSR_64_AllRegs_RegMask;
458 return CSR_64_AllRegs_NoSSE_RegMask;
459 }
460 if (HasAVX512)
461 return CSR_32_AllRegs_AVX512_RegMask;
462 if (HasAVX)
463 return CSR_32_AllRegs_AVX_RegMask;
464 if (HasSSE)
465 return CSR_32_AllRegs_SSE_RegMask;
466 return CSR_32_AllRegs_RegMask;
467 default:
468 break;
469 }
470
471 // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
472 // callsEHReturn().
473 if (Is64Bit) {
474 const Function &F = MF.getFunction();
475 bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
476 F.getAttributes().hasAttrSomewhere(Kind: Attribute::SwiftError);
477 if (IsSwiftCC) {
478 if (IsWin64)
479 return HasEGPR ? CSR_Win64_APX_SwiftError_RegMask
480 : CSR_Win64_SwiftError_RegMask;
481 return CSR_64_SwiftError_RegMask;
482 }
483
484 if (IsWin64 || IsUEFI64)
485 return HasEGPR ? CSR_Win64_APX_RegMask : CSR_Win64_RegMask;
486 return CSR_64_RegMask;
487 }
488
489 return CSR_32_RegMask;
490}
491
492const uint32_t*
493X86RegisterInfo::getNoPreservedMask() const {
494 return CSR_NoRegs_RegMask;
495}
496
497const uint32_t *X86RegisterInfo::getDarwinTLSCallPreservedMask() const {
498 return CSR_64_TLS_Darwin_RegMask;
499}
500
501BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
502 BitVector Reserved(getNumRegs());
503 const X86FrameLowering *TFI = getFrameLowering(MF);
504
505 // Set the floating point control register as reserved.
506 Reserved.set(X86::FPCW);
507
508 // Set the floating point status register as reserved.
509 Reserved.set(X86::FPSW);
510
511 // Set the SIMD floating point control register as reserved.
512 Reserved.set(X86::MXCSR);
513
514 // Set the stack-pointer register and its aliases as reserved.
515 for (const MCPhysReg &SubReg : subregs_inclusive(Reg: X86::RSP))
516 Reserved.set(SubReg);
517
518 // Set the Shadow Stack Pointer as reserved.
519 Reserved.set(X86::SSP);
520
521 auto &ST = MF.getSubtarget<X86Subtarget>();
522 if (ST.hasUserReservedRegisters()) {
523 if (ST.is64Bit()) {
524 // Set r# as reserved register if user required.
525 for (unsigned Reg = X86::R8; Reg <= X86::R15; ++Reg)
526 if (ST.isRegisterReservedByUser(i: Reg))
527 for (const MCPhysReg &SubReg : subregs_inclusive(Reg))
528 Reserved.set(SubReg);
529 if (ST.hasEGPR())
530 for (unsigned Reg = X86::R16; Reg <= X86::R31; ++Reg)
531 if (ST.isRegisterReservedByUser(i: Reg))
532 for (const MCPhysReg &SubReg : subregs_inclusive(Reg))
533 Reserved.set(SubReg);
534 } else {
535 if (ST.isRegisterReservedByUser(i: X86::EDI))
536 for (const MCPhysReg &SubReg : sub_and_superregs_inclusive(Reg: X86::EDI))
537 Reserved.set(SubReg);
538 }
539 }
540
541 // Set the instruction pointer register and its aliases as reserved.
542 for (const MCPhysReg &SubReg : subregs_inclusive(Reg: X86::RIP))
543 Reserved.set(SubReg);
544
545 // Set the frame-pointer register and its aliases as reserved if needed.
546 if (TFI->hasFP(MF) || MF.framePointerIsReserved()) {
547 if (MF.getInfo<X86MachineFunctionInfo>()->getFPClobberedByInvoke())
548 MF.getContext().reportError(
549 L: SMLoc(),
550 Msg: "Frame pointer clobbered by function invoke is not supported.");
551
552 for (const MCPhysReg &SubReg : subregs_inclusive(Reg: X86::RBP))
553 Reserved.set(SubReg);
554 }
555
556 // Set the base-pointer register and its aliases as reserved if needed.
557 if (hasBasePointer(MF)) {
558 if (MF.getInfo<X86MachineFunctionInfo>()->getBPClobberedByInvoke())
559 MF.getContext().reportError(L: SMLoc(),
560 Msg: "Stack realignment in presence of dynamic "
561 "allocas is not supported with "
562 "this calling convention.");
563
564 Register BasePtr = getX86SubSuperRegister(Reg: getBaseRegister(), Size: 64);
565 for (const MCPhysReg &SubReg : subregs_inclusive(Reg: BasePtr))
566 Reserved.set(SubReg);
567 }
568
569 // Mark the segment registers as reserved.
570 Reserved.set(X86::CS);
571 Reserved.set(X86::SS);
572 Reserved.set(X86::DS);
573 Reserved.set(X86::ES);
574 Reserved.set(X86::FS);
575 Reserved.set(X86::GS);
576
577 // Mark the floating point stack registers as reserved.
578 for (unsigned n = 0; n != 8; ++n)
579 Reserved.set(X86::ST0 + n);
580
581 // Without usable x87 (soft float or -mno-x87), reserve the allocatable FPn
582 // pseudos (FP0-FP6; FP7 is already non-allocatable) so they aren't scrubbed.
583 if (ST.useSoftFloat() || !ST.hasX87())
584 for (unsigned n = 0; n != 7; ++n)
585 Reserved.set(X86::FP0 + n);
586
587 // Reserve the registers that only exist in 64-bit mode.
588 if (!Is64Bit) {
589 // These 8-bit registers are part of the x86-64 extension even though their
590 // super-registers are old 32-bits.
591 Reserved.set(X86::SIL);
592 Reserved.set(X86::DIL);
593 Reserved.set(X86::BPL);
594 Reserved.set(X86::SPL);
595 Reserved.set(X86::SIH);
596 Reserved.set(X86::DIH);
597 Reserved.set(X86::BPH);
598 Reserved.set(X86::SPH);
599
600 for (unsigned n = 0; n != 8; ++n) {
601 // R8, R9, ...
602 for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
603 Reserved.set(*AI);
604
605 // XMM8, XMM9, ...
606 for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
607 Reserved.set(*AI);
608 }
609 }
610 if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
611 for (unsigned n = 0; n != 16; ++n) {
612 for (MCRegAliasIterator AI(X86::XMM16 + n, this, true); AI.isValid();
613 ++AI)
614 Reserved.set(*AI);
615 }
616 }
617
618 // Reserve the extended general purpose registers.
619 if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasEGPR())
620 Reserved.set(I: X86::R16, E: X86::R31WH + 1);
621
622 // Due to specifics of setjmp unwinding in Win64 APX ABI, the unwinder
623 // cannot restore R30/R31. Reserve them to prevent register allocation.
624 // https://learn.microsoft.com/en-us/cpp/build/x64-calling-convention#setjmplongjmp
625 if (MF.exposesReturnsTwice() && ST.isTargetWin64()) {
626 unsigned NumReservedCSRs = 0;
627 for (unsigned Reg = X86::R16; Reg <= X86::R31; ++Reg)
628 if (isCalleeSavedPhysReg(PhysReg: Reg, MF)) {
629 ++NumReservedCSRs;
630 for (const MCPhysReg &SubReg : subregs_inclusive(Reg))
631 Reserved.set(SubReg);
632 }
633 if (NumReservedCSRs &&
634 MF.size() > ST.getCLOpts().setjmp_csr_warning_threshold &&
635 !MF.getRegInfo().reservedRegsFrozen()) {
636 MF.getContext().reportWarning(
637 L: SMLoc(), Msg: Twine(NumReservedCSRs) +
638 " callee-saved register(s) reserved due to setjmp in '" +
639 MF.getName() +
640 "'; this may impact performance in large functions");
641 }
642 }
643
644 if (MF.getFunction().getCallingConv() == CallingConv::GRAAL) {
645 for (MCRegAliasIterator AI(X86::R14, this, true); AI.isValid(); ++AI)
646 Reserved.set(*AI);
647 for (MCRegAliasIterator AI(X86::R15, this, true); AI.isValid(); ++AI)
648 Reserved.set(*AI);
649 }
650
651 // Reserve registers for LFI sandboxing.
652 if (MF.getSubtarget<X86Subtarget>().isLFI()) {
653 for (MCRegAliasIterator AI(X86::R11, this, true); AI.isValid(); ++AI)
654 Reserved.set(*AI);
655 for (MCRegAliasIterator AI(X86::R14, this, true); AI.isValid(); ++AI)
656 Reserved.set(*AI);
657 for (MCRegAliasIterator AI(X86::R15, this, true); AI.isValid(); ++AI)
658 Reserved.set(*AI);
659 }
660
661 assert(checkAllSuperRegsMarked(Reserved,
662 {X86::SIL, X86::DIL, X86::BPL, X86::SPL,
663 X86::SIH, X86::DIH, X86::BPH, X86::SPH}));
664 return Reserved;
665}
666
667unsigned X86RegisterInfo::getNumSupportedRegs(const MachineFunction &MF) const {
668 // All existing Intel CPUs that support AMX support AVX512 and all existing
669 // Intel CPUs that support APX support AMX. AVX512 implies AVX.
670 //
671 // We enumerate the registers in X86GenRegisterInfo.inc in this order:
672 //
673 // Registers before AVX512,
674 // AVX512 registers (X/YMM16-31, ZMM0-31, K registers)
675 // AMX registers (TMM)
676 // APX registers (R16-R31)
677 //
678 // and try to return the minimum number of registers supported by the target.
679 static_assert((X86::R15WH + 1 == X86::YMM0) && (X86::YMM15 + 1 == X86::K0) &&
680 (X86::K6_K7 + 1 == X86::TMMCFG) &&
681 (X86::TMM7 + 1 == X86::R16) &&
682 (X86::R31WH + 1 == X86::NUM_TARGET_REGS),
683 "Register number may be incorrect");
684
685 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
686 if (ST.hasEGPR())
687 return X86::NUM_TARGET_REGS;
688 if (ST.hasAMXTILE())
689 return X86::TMM7 + 1;
690 if (ST.hasAVX512())
691 return X86::K6_K7 + 1;
692 if (ST.hasAVX())
693 return X86::YMM15 + 1;
694 return X86::R15WH + 1;
695}
696
697bool X86RegisterInfo::isArgumentRegister(const MachineFunction &MF,
698 MCRegister Reg) const {
699 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
700 const TargetRegisterInfo &TRI = *ST.getRegisterInfo();
701 auto IsSubReg = [&](MCRegister RegA, MCRegister RegB) {
702 return TRI.isSuperOrSubRegisterEq(RegA, RegB);
703 };
704
705 if (!ST.is64Bit())
706 return llvm::any_of(
707 Range: SmallVector<MCRegister>{X86::EAX, X86::ECX, X86::EDX},
708 P: [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); }) ||
709 (ST.hasMMX() && X86::VR64RegClass.contains(Reg));
710
711 CallingConv::ID CC = MF.getFunction().getCallingConv();
712
713 if (CC == CallingConv::X86_64_SysV && IsSubReg(X86::RAX, Reg))
714 return true;
715
716 if (llvm::any_of(
717 Range: SmallVector<MCRegister>{X86::RDX, X86::RCX, X86::R8, X86::R9},
718 P: [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); }))
719 return true;
720
721 if (CC != CallingConv::Win64 &&
722 llvm::any_of(Range: SmallVector<MCRegister>{X86::RDI, X86::RSI},
723 P: [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); }))
724 return true;
725
726 if (ST.hasSSE1() &&
727 llvm::any_of(Range: SmallVector<MCRegister>{X86::XMM0, X86::XMM1, X86::XMM2,
728 X86::XMM3, X86::XMM4, X86::XMM5,
729 X86::XMM6, X86::XMM7},
730 P: [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); }))
731 return true;
732
733 return X86GenRegisterInfo::isArgumentRegister(MF, PhysReg: Reg);
734}
735
736bool X86RegisterInfo::isFixedRegister(const MachineFunction &MF,
737 MCRegister PhysReg) const {
738 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
739 const TargetRegisterInfo &TRI = *ST.getRegisterInfo();
740
741 // Stack pointer.
742 if (TRI.isSuperOrSubRegisterEq(RegA: X86::RSP, RegB: PhysReg))
743 return true;
744
745 // Don't use the frame pointer if it's being used.
746 const X86FrameLowering &TFI = *getFrameLowering(MF);
747 if (TFI.hasFP(MF) && TRI.isSuperOrSubRegisterEq(RegA: X86::RBP, RegB: PhysReg))
748 return true;
749
750 return X86GenRegisterInfo::isFixedRegister(MF, PhysReg);
751}
752
753bool X86RegisterInfo::isTileRegisterClass(const TargetRegisterClass *RC) const {
754 return RC->getID() == X86::TILERegClassID;
755}
756
757void X86RegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
758 // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
759 // because the calling convention defines the EFLAGS register as NOT
760 // preserved.
761 //
762 // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
763 // an assert to track this and clear the register afterwards to avoid
764 // unnecessary crashes during release builds.
765 assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
766 "EFLAGS are not live-out from a patchpoint.");
767
768 // Also clean other registers that don't need preserving (IP).
769 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
770 Mask[Reg / 32] &= ~(1U << (Reg % 32));
771}
772
773//===----------------------------------------------------------------------===//
774// Stack Frame Processing methods
775//===----------------------------------------------------------------------===//
776
777static bool CantUseSP(const MachineFrameInfo &MFI) {
778 return MFI.hasVarSizedObjects() || MFI.hasOpaqueSPAdjustment();
779}
780
781bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
782 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
783 // We have a virtual register to reference argument, and don't need base
784 // pointer.
785 if (X86FI->getStackPtrSaveMI() != nullptr)
786 return false;
787
788 if (X86FI->hasPreallocatedCall())
789 return true;
790
791 const MachineFrameInfo &MFI = MF.getFrameInfo();
792
793 if (!MF.getSubtarget<X86Subtarget>().getCLOpts().use_base_pointer)
794 return false;
795
796 // When we need stack realignment, we can't address the stack from the frame
797 // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
798 // can't address variables from the stack pointer. MS inline asm can
799 // reference locals while also adjusting the stack pointer. When we can't
800 // use both the SP and the FP, we need a separate base pointer register.
801 bool CantUseFP = hasStackRealignment(MF);
802 return CantUseFP && CantUseSP(MFI);
803}
804
805bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
806 if (!TargetRegisterInfo::canRealignStack(MF))
807 return false;
808
809 const MachineFrameInfo &MFI = MF.getFrameInfo();
810 const MachineRegisterInfo *MRI = &MF.getRegInfo();
811
812 // Stack realignment requires a frame pointer. If we already started
813 // register allocation with frame pointer elimination, it is too late now.
814 if (!MRI->canReserveReg(PhysReg: FramePtr))
815 return false;
816
817 // If a base pointer is necessary. Check that it isn't too late to reserve
818 // it.
819 if (CantUseSP(MFI))
820 return MRI->canReserveReg(PhysReg: BasePtr);
821 return true;
822}
823
824bool X86RegisterInfo::shouldRealignStack(const MachineFunction &MF) const {
825 if (TargetRegisterInfo::shouldRealignStack(MF))
826 return true;
827
828 return !Is64Bit && MF.getFunction().getCallingConv() == CallingConv::X86_INTR;
829}
830
831// tryOptimizeLEAtoMOV - helper function that tries to replace a LEA instruction
832// of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx'.
833// TODO: In this case we should be really trying first to entirely eliminate
834// this instruction which is a plain copy.
835static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II) {
836 MachineInstr &MI = *II;
837 unsigned Opc = II->getOpcode();
838 // Check if this is a LEA of the form 'lea (%esp), %ebx'
839 if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
840 MI.getOperand(i: 2).getImm() != 1 ||
841 MI.getOperand(i: 3).getReg() != X86::NoRegister ||
842 MI.getOperand(i: 4).getImm() != 0 ||
843 MI.getOperand(i: 5).getReg() != X86::NoRegister)
844 return false;
845 Register BasePtr = MI.getOperand(i: 1).getReg();
846 // In X32 mode, ensure the base-pointer is a 32-bit operand, so the LEA will
847 // be replaced with a 32-bit operand MOV which will zero extend the upper
848 // 32-bits of the super register.
849 if (Opc == X86::LEA64_32r)
850 BasePtr = getX86SubSuperRegister(Reg: BasePtr, Size: 32);
851 Register NewDestReg = MI.getOperand(i: 0).getReg();
852 const X86InstrInfo *TII =
853 MI.getParent()->getParent()->getSubtarget<X86Subtarget>().getInstrInfo();
854 TII->copyPhysReg(MBB&: *MI.getParent(), MI: II, DL: MI.getDebugLoc(), DestReg: NewDestReg, SrcReg: BasePtr,
855 KillSrc: MI.getOperand(i: 1).isKill());
856 MI.eraseFromParent();
857 return true;
858}
859
860static bool isFuncletReturnInstr(MachineInstr &MI) {
861 switch (MI.getOpcode()) {
862 case X86::CATCHRET:
863 case X86::CLEANUPRET:
864 return true;
865 default:
866 return false;
867 }
868 llvm_unreachable("impossible");
869}
870
871void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
872 unsigned FIOperandNum,
873 Register BaseReg,
874 int FIOffset) const {
875 MachineInstr &MI = *II;
876 unsigned Opc = MI.getOpcode();
877 if (Opc == TargetOpcode::LOCAL_ESCAPE) {
878 MachineOperand &FI = MI.getOperand(i: FIOperandNum);
879 FI.ChangeToImmediate(ImmVal: FIOffset);
880 return;
881 }
882
883 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: BaseReg, isDef: false);
884
885 // The frame index format for stackmaps and patchpoints is different from the
886 // X86 format. It only has a FI and an offset.
887 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
888 assert(BasePtr == FramePtr && "Expected the FP as base register");
889 int64_t Offset = MI.getOperand(i: FIOperandNum + 1).getImm() + FIOffset;
890 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Offset);
891 return;
892 }
893
894 if (MI.getOperand(i: FIOperandNum + 3).isImm()) {
895 // Offset is a 32-bit integer.
896 int Imm = (int)(MI.getOperand(i: FIOperandNum + 3).getImm());
897 int Offset = FIOffset + Imm;
898 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
899 "Requesting 64-bit offset in 32-bit immediate!");
900 if (Offset != 0)
901 MI.getOperand(i: FIOperandNum + 3).ChangeToImmediate(ImmVal: Offset);
902 } else {
903 // Offset is symbolic. This is extremely rare.
904 uint64_t Offset =
905 FIOffset + (uint64_t)MI.getOperand(i: FIOperandNum + 3).getOffset();
906 MI.getOperand(i: FIOperandNum + 3).setOffset(Offset);
907 }
908}
909
910bool
911X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
912 int SPAdj, unsigned FIOperandNum,
913 RegScavenger *RS) const {
914 MachineInstr &MI = *II;
915 MachineBasicBlock &MBB = *MI.getParent();
916 MachineFunction &MF = *MBB.getParent();
917 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
918 bool IsEHFuncletEpilogue = MBBI == MBB.end() ? false
919 : isFuncletReturnInstr(MI&: *MBBI);
920 const X86FrameLowering *TFI = getFrameLowering(MF);
921 int FrameIndex = MI.getOperand(i: FIOperandNum).getIndex();
922
923 // Determine base register and offset.
924 int64_t FIOffset;
925 Register BasePtr;
926 if (MI.isReturn()) {
927 assert((!hasStackRealignment(MF) ||
928 MF.getFrameInfo().isFixedObjectIndex(FrameIndex)) &&
929 "Return instruction can only reference SP relative frame objects");
930 FIOffset =
931 TFI->getFrameIndexReferenceSP(MF, FI: FrameIndex, SPReg&: BasePtr, Adjustment: 0).getFixed();
932 } else if (TFI->Is64Bit && (MBB.isEHFuncletEntry() || IsEHFuncletEpilogue)) {
933 FIOffset = TFI->getWin64EHFrameIndexRef(MF, FI: FrameIndex, SPReg&: BasePtr);
934 } else {
935 FIOffset = TFI->getFrameIndexReference(MF, FI: FrameIndex, FrameReg&: BasePtr).getFixed();
936 }
937
938 // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
939 // simple FP case, and doesn't work with stack realignment. On 32-bit, the
940 // offset is from the traditional base pointer location. On 64-bit, the
941 // offset is from the SP at the end of the prologue, not the FP location. This
942 // matches the behavior of llvm.frameaddress.
943 unsigned Opc = MI.getOpcode();
944 if (Opc == TargetOpcode::LOCAL_ESCAPE) {
945 MachineOperand &FI = MI.getOperand(i: FIOperandNum);
946 FI.ChangeToImmediate(ImmVal: FIOffset);
947 return false;
948 }
949
950 // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
951 // register as source operand, semantic is the same and destination is
952 // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
953 // Don't change BasePtr since it is used later for stack adjustment.
954 Register MachineBasePtr = BasePtr;
955 if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(Reg: BasePtr))
956 MachineBasePtr = getX86SubSuperRegister(Reg: BasePtr, Size: 64);
957
958 // This must be part of a four operand memory reference. Replace the
959 // FrameIndex with base register. Add an offset to the offset.
960 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: MachineBasePtr, isDef: false);
961
962 if (BasePtr == StackPtr)
963 FIOffset += SPAdj;
964
965 // The frame index format for stackmaps and patchpoints is different from the
966 // X86 format. It only has a FI and an offset.
967 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
968 assert(BasePtr == FramePtr && "Expected the FP as base register");
969 int64_t Offset = MI.getOperand(i: FIOperandNum + 1).getImm() + FIOffset;
970 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Offset);
971 return false;
972 }
973
974 if (MI.getOperand(i: FIOperandNum+3).isImm()) {
975 const X86InstrInfo *TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
976 const DebugLoc &DL = MI.getDebugLoc();
977 int64_t Imm = MI.getOperand(i: FIOperandNum + 3).getImm();
978 int64_t Offset = FIOffset + Imm;
979 bool FitsIn32Bits = isInt<32>(x: Offset);
980 // If the offset will not fit in a 32-bit displacement, then for 64-bit
981 // targets, scavenge a register to hold it. Otherwise...
982 if (Is64Bit && !FitsIn32Bits) {
983 assert(RS && "RegisterScavenger was NULL");
984
985 RS->enterBasicBlockEnd(MBB);
986 RS->backward(I: std::next(x: II));
987
988 Register ScratchReg = RS->scavengeRegisterBackwards(
989 RC: X86::GR64RegClass, To: II, /*RestoreAfter=*/false, /*SPAdj=*/0,
990 /*AllowSpill=*/true);
991 assert(ScratchReg != 0 && "scratch reg was 0");
992 RS->setRegUsed(Reg: ScratchReg);
993
994 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: X86::MOV64ri), DestReg: ScratchReg).addImm(Val: Offset);
995
996 MI.getOperand(i: FIOperandNum + 3).setImm(0);
997 if (MI.getOperand(i: FIOperandNum + 2).getReg() == X86::NoRegister) {
998 MI.getOperand(i: FIOperandNum + 2).setReg(ScratchReg);
999 } else {
1000 // The index register slot is already in use, fold the offset into
1001 // the base register instead. LEA does not clobber EFLAGS.
1002 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: X86::LEA64r), DestReg: ScratchReg)
1003 .addReg(RegNo: MachineBasePtr)
1004 .addImm(Val: 1)
1005 .addReg(RegNo: ScratchReg)
1006 .addImm(Val: 0)
1007 .addReg(RegNo: X86::NoRegister);
1008 MI.getOperand(i: FIOperandNum).setReg(ScratchReg);
1009 }
1010
1011 return false;
1012 }
1013
1014 // ... for 32-bit targets, this is a bug!
1015 if (!Is64Bit && !FitsIn32Bits) {
1016 MI.emitGenericError(ErrMsg: "64-bit offset calculated but target is 32-bit");
1017 // Trap so that the instruction verification pass does not fail if run.
1018 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: X86::TRAP));
1019 return false;
1020 }
1021
1022 if (Offset != 0 || !tryOptimizeLEAtoMOV(II))
1023 MI.getOperand(i: FIOperandNum + 3).ChangeToImmediate(ImmVal: Offset);
1024 } else {
1025 // Offset is symbolic. This is extremely rare.
1026 uint64_t Offset = FIOffset +
1027 (uint64_t)MI.getOperand(i: FIOperandNum+3).getOffset();
1028 MI.getOperand(i: FIOperandNum + 3).setOffset(Offset);
1029 }
1030 return false;
1031}
1032
1033unsigned X86RegisterInfo::findDeadCallerSavedReg(
1034 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI) const {
1035 const MachineFunction *MF = MBB.getParent();
1036 const MachineRegisterInfo &MRI = MF->getRegInfo();
1037 if (MF->callsEHReturn())
1038 return 0;
1039
1040 if (MBBI == MBB.end())
1041 return 0;
1042
1043 switch (MBBI->getOpcode()) {
1044 default:
1045 return 0;
1046 case TargetOpcode::PATCHABLE_RET:
1047 case X86::RET:
1048 case X86::RET32:
1049 case X86::RET64:
1050 case X86::RETI32:
1051 case X86::RETI64:
1052 case X86::TCRETURNdi:
1053 case X86::TCRETURNri:
1054 case X86::TCRETURN_WIN64ri:
1055 case X86::TCRETURN_HIPE32ri:
1056 case X86::TCRETURNmi:
1057 case X86::TCRETURNdi64:
1058 case X86::TCRETURNri64:
1059 case X86::TCRETURNri64_ImpCall:
1060 case X86::TCRETURNmi64:
1061 case X86::TCRETURN_WINmi64:
1062 case X86::EH_RETURN:
1063 case X86::EH_RETURN64: {
1064 LiveRegUnits LRU(*this);
1065 LRU.addLiveOuts(MBB);
1066 LRU.stepBackward(MI: *MBBI);
1067
1068 const TargetRegisterClass &RC =
1069 Is64Bit ? X86::GR64_NOSPRegClass : X86::GR32_NOSPRegClass;
1070 for (MCRegister Reg : RC) {
1071 if (LRU.available(Reg) && !MRI.isReserved(PhysReg: Reg))
1072 return Reg;
1073 }
1074 }
1075 }
1076
1077 return 0;
1078}
1079
1080Register X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1081 const X86FrameLowering *TFI = getFrameLowering(MF);
1082 return TFI->hasFP(MF) ? FramePtr : StackPtr;
1083}
1084
1085Register
1086X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const {
1087 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
1088 Register FrameReg = getFrameRegister(MF);
1089 if (Subtarget.isTarget64BitILP32())
1090 FrameReg = getX86SubSuperRegister(Reg: FrameReg, Size: 32);
1091 return FrameReg;
1092}
1093
1094Register
1095X86RegisterInfo::getPtrSizedStackRegister(const MachineFunction &MF) const {
1096 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
1097 Register StackReg = getStackRegister();
1098 if (Subtarget.isTarget64BitILP32())
1099 StackReg = getX86SubSuperRegister(Reg: StackReg, Size: 32);
1100 return StackReg;
1101}
1102
1103static ShapeT getTileShape(Register VirtReg, VirtRegMap *VRM,
1104 const MachineRegisterInfo *MRI) {
1105 if (VRM->hasShape(virtReg: VirtReg))
1106 return VRM->getShape(virtReg: VirtReg);
1107
1108 const MachineOperand &Def = *MRI->def_begin(RegNo: VirtReg);
1109 MachineInstr *MI = const_cast<MachineInstr *>(Def.getParent());
1110 unsigned OpCode = MI->getOpcode();
1111 switch (OpCode) {
1112 default:
1113 llvm_unreachable("Unexpected machine instruction on tile register!");
1114 break;
1115 case X86::COPY: {
1116 Register SrcReg = MI->getOperand(i: 1).getReg();
1117 ShapeT Shape = getTileShape(VirtReg: SrcReg, VRM, MRI);
1118 VRM->assignVirt2Shape(virtReg: VirtReg, shape: Shape);
1119 return Shape;
1120 }
1121 // We only collect the tile shape that is defined.
1122 case X86::PTILELOADDV:
1123 case X86::PTILELOADDT1V:
1124 case X86::PTDPBSSDV:
1125 case X86::PTDPBSUDV:
1126 case X86::PTDPBUSDV:
1127 case X86::PTDPBUUDV:
1128 case X86::PTILEZEROV:
1129 case X86::PTDPBF16PSV:
1130 case X86::PTDPFP16PSV:
1131 case X86::PTCMMIMFP16PSV:
1132 case X86::PTCMMRLFP16PSV:
1133 case X86::PTILELOADDRSV:
1134 case X86::PTILELOADDRST1V:
1135 case X86::PTDPBF8PSV:
1136 case X86::PTDPBHF8PSV:
1137 case X86::PTDPHBF8PSV:
1138 case X86::PTDPHF8PSV: {
1139 MachineOperand &MO1 = MI->getOperand(i: 1);
1140 MachineOperand &MO2 = MI->getOperand(i: 2);
1141 ShapeT Shape(&MO1, &MO2, MRI);
1142 VRM->assignVirt2Shape(virtReg: VirtReg, shape: Shape);
1143 return Shape;
1144 }
1145 }
1146}
1147
1148bool X86RegisterInfo::getRegAllocationHints(
1149 Register VirtReg, ArrayRef<MCPhysReg> Order,
1150 SmallSetVector<MCPhysReg, 16> &Hints, const MachineFunction &MF,
1151 const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
1152 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1153 const TargetRegisterClass &RC = *MRI->getRegClass(Reg: VirtReg);
1154 bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
1155 VirtReg, Order, Hints, MF, VRM, Matrix);
1156 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
1157 const TargetRegisterInfo &TRI = *ST.getRegisterInfo();
1158
1159 unsigned ID = RC.getID();
1160
1161 if (!VRM)
1162 return BaseImplRetVal;
1163
1164 if (ID != X86::TILERegClassID) {
1165 if (ST.getCLOpts().disable_regalloc_hints_for_ndd || !ST.hasNDD() ||
1166 !TRI.isGeneralPurposeRegisterClass(RC: &RC))
1167 return BaseImplRetVal;
1168
1169 // Add any two address hints after any copy hints.
1170 SmallSet<unsigned, 4> TwoAddrHints;
1171
1172 auto TryAddNDDHint = [&](const MachineOperand &MO) {
1173 Register Reg = MO.getReg();
1174 Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(virtReg: Reg));
1175 if (PhysReg && !MRI->isReserved(PhysReg) && !Hints.contains(key: PhysReg))
1176 TwoAddrHints.insert(V: PhysReg);
1177 };
1178
1179 // NDD instructions is compressible when Op0 is allocated to the same
1180 // physic register as Op1 (or Op2 if it's commutable).
1181 for (auto &MO : MRI->reg_nodbg_operands(Reg: VirtReg)) {
1182 const MachineInstr &MI = *MO.getParent();
1183 if (!X86::getNonNDVariant(Opc: MI.getOpcode()))
1184 continue;
1185 unsigned OpIdx = MI.getOperandNo(I: &MO);
1186 if (OpIdx == 0) {
1187 assert(MI.getOperand(1).isReg());
1188 TryAddNDDHint(MI.getOperand(i: 1));
1189 if (MI.isCommutable()) {
1190 assert(MI.getOperand(2).isReg());
1191 TryAddNDDHint(MI.getOperand(i: 2));
1192 }
1193 } else if (OpIdx == 1) {
1194 TryAddNDDHint(MI.getOperand(i: 0));
1195 } else if (MI.isCommutable() && OpIdx == 2) {
1196 TryAddNDDHint(MI.getOperand(i: 0));
1197 }
1198 }
1199
1200 for (MCPhysReg OrderReg : Order)
1201 if (TwoAddrHints.count(V: OrderReg))
1202 Hints.insert(X: OrderReg);
1203
1204 return BaseImplRetVal;
1205 }
1206
1207 ShapeT VirtShape = getTileShape(VirtReg, VRM: const_cast<VirtRegMap *>(VRM), MRI);
1208 auto AddHint = [&](MCPhysReg PhysReg) {
1209 Register VReg = Matrix->getOneVReg(PhysReg);
1210 if (VReg == MCRegister::NoRegister) { // Not allocated yet
1211 Hints.insert(X: PhysReg);
1212 return;
1213 }
1214 ShapeT PhysShape = getTileShape(VirtReg: VReg, VRM: const_cast<VirtRegMap *>(VRM), MRI);
1215 if (PhysShape == VirtShape)
1216 Hints.insert(X: PhysReg);
1217 };
1218
1219 SmallSetVector<MCPhysReg, 16> CopyHints(Hints);
1220 Hints.clear();
1221 for (auto Hint : CopyHints) {
1222 if (RC.contains(Reg: Hint) && !MRI->isReserved(PhysReg: Hint))
1223 AddHint(Hint);
1224 }
1225 for (MCPhysReg PhysReg : Order) {
1226 if (!CopyHints.contains(key: PhysReg) && RC.contains(Reg: PhysReg) &&
1227 !MRI->isReserved(PhysReg))
1228 AddHint(PhysReg);
1229 }
1230
1231#define DEBUG_TYPE "tile-hint"
1232 LLVM_DEBUG({
1233 dbgs() << "Hints for virtual register " << format_hex(VirtReg, 8) << "\n";
1234 for (auto Hint : Hints) {
1235 dbgs() << "tmm" << Hint << ",";
1236 }
1237 dbgs() << "\n";
1238 });
1239#undef DEBUG_TYPE
1240
1241 return true;
1242}
1243
1244const TargetRegisterClass *X86RegisterInfo::constrainRegClassToNonRex2(
1245 const TargetRegisterClass *RC) const {
1246 switch (RC->getID()) {
1247 default:
1248 return RC;
1249 case X86::GR8RegClassID:
1250 return &X86::GR8_NOREX2RegClass;
1251 case X86::GR16RegClassID:
1252 return &X86::GR16_NOREX2RegClass;
1253 case X86::GR32RegClassID:
1254 return &X86::GR32_NOREX2RegClass;
1255 case X86::GR64RegClassID:
1256 return &X86::GR64_NOREX2RegClass;
1257 case X86::GR32_NOSPRegClassID:
1258 return &X86::GR32_NOREX2_NOSPRegClass;
1259 case X86::GR64_NOSPRegClassID:
1260 return &X86::GR64_NOREX2_NOSPRegClass;
1261 }
1262}
1263
1264bool X86RegisterInfo::isNonRex2RegClass(const TargetRegisterClass *RC) const {
1265 switch (RC->getID()) {
1266 default:
1267 return false;
1268 case X86::GR8_NOREX2RegClassID:
1269 case X86::GR16_NOREX2RegClassID:
1270 case X86::GR32_NOREX2RegClassID:
1271 case X86::GR64_NOREX2RegClassID:
1272 case X86::GR32_NOREX2_NOSPRegClassID:
1273 case X86::GR64_NOREX2_NOSPRegClassID:
1274 case X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID:
1275 return true;
1276 }
1277}
1278
1279unsigned X86RegisterInfo::getCSRFirstUseCost(const MachineFunction &MF) const {
1280 // If PPX is implemented, push/pop pairs don't access memory.
1281 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
1282 if (ST.is64Bit() && ST.hasPPX())
1283 return 0;
1284
1285 // push + pop.
1286 return 2;
1287}
1288