1//===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the X86 implementation of the TargetRegisterInfo class.
10// This file is responsible for the frame pointer elimination optimization
11// on X86.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86RegisterInfo.h"
16#include "X86FrameLowering.h"
17#include "X86MachineFunctionInfo.h"
18#include "X86Subtarget.h"
19#include "llvm/ADT/BitVector.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/ADT/SmallSet.h"
22#include "llvm/CodeGen/LiveRegMatrix.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/RegisterScavenging.h"
26#include "llvm/CodeGen/TargetFrameLowering.h"
27#include "llvm/CodeGen/TargetInstrInfo.h"
28#include "llvm/CodeGen/TileShapeInfo.h"
29#include "llvm/CodeGen/VirtRegMap.h"
30#include "llvm/IR/Function.h"
31#include "llvm/IR/Type.h"
32#include "llvm/MC/MCContext.h"
33#include "llvm/Support/CommandLine.h"
34#include "llvm/Support/ErrorHandling.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetOptions.h"
37
38using namespace llvm;
39
40#define GET_REGINFO_TARGET_DESC
41#include "X86GenRegisterInfo.inc"
42
43static cl::opt<bool>
44EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(Val: true),
45 cl::desc("Enable use of a base pointer for complex stack frames"));
46
47static cl::opt<bool>
48 DisableRegAllocNDDHints("x86-disable-regalloc-hints-for-ndd", cl::Hidden,
49 cl::init(Val: false),
50 cl::desc("Disable two address hints for register "
51 "allocation"));
52
53static cl::opt<unsigned> SetjmpCSRWarningThreshold(
54 "x86-setjmp-csr-warning-threshold", cl::Hidden, cl::init(Val: 50),
55 cl::desc("Basic block count threshold for emitting a warning about "
56 "callee-saved registers reserved due to setjmp"));
57
58extern cl::opt<bool> X86EnableAPXForRelocation;
59
60X86RegisterInfo::X86RegisterInfo(const Triple &TT)
61 : X86GenRegisterInfo((TT.isX86_64() ? X86::RIP : X86::EIP),
62 X86_MC::getDwarfRegFlavour(TT, isEH: false),
63 X86_MC::getDwarfRegFlavour(TT, isEH: true),
64 (TT.isX86_64() ? X86::RIP : X86::EIP)) {
65 X86_MC::initLLVMToSEHAndCVRegMapping(MRI: this);
66
67 // Cache some information.
68 Is64Bit = TT.isX86_64();
69 IsTarget64BitLP64 = Is64Bit && !TT.isX32();
70 IsWin64 = Is64Bit && TT.isOSWindows();
71 IsUEFI64 = Is64Bit && TT.isUEFI();
72
73 // Use a callee-saved register as the base pointer. These registers must
74 // not conflict with any ABI requirements. For example, in 32-bit mode PIC
75 // requires GOT in the EBX register before function calls via PLT GOT pointer.
76 if (Is64Bit) {
77 SlotSize = 8;
78 // This matches the simplified 32-bit pointer code in the data layout
79 // computation.
80 // FIXME: Should use the data layout?
81 bool Use64BitReg = !TT.isX32();
82 StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
83 FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
84 BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
85 } else {
86 SlotSize = 4;
87 StackPtr = X86::ESP;
88 FramePtr = X86::EBP;
89 BasePtr = X86::ESI;
90 }
91}
92
93const TargetRegisterClass *
94X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
95 unsigned Idx) const {
96 // The sub_8bit sub-register index is more constrained in 32-bit mode.
97 // It behaves just like the sub_8bit_hi index.
98 if (!Is64Bit && Idx == X86::sub_8bit)
99 Idx = X86::sub_8bit_hi;
100
101 // Forward to TableGen's default version.
102 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
103}
104
105const TargetRegisterClass *
106X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
107 const TargetRegisterClass *B,
108 unsigned SubIdx) const {
109 // The sub_8bit sub-register index is more constrained in 32-bit mode.
110 if (!Is64Bit && SubIdx == X86::sub_8bit) {
111 A = X86GenRegisterInfo::getSubClassWithSubReg(RC: A, Idx: X86::sub_8bit_hi);
112 if (!A)
113 return nullptr;
114 }
115 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, Idx: SubIdx);
116}
117
118const TargetRegisterClass *
119X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
120 const MachineFunction &MF) const {
121 // Don't allow super-classes of GR8_NOREX. This class is only used after
122 // extracting sub_8bit_hi sub-registers. The H sub-registers cannot be copied
123 // to the full GR8 register class in 64-bit mode, so we cannot allow the
124 // reigster class inflation.
125 //
126 // The GR8_NOREX class is always used in a way that won't be constrained to a
127 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
128 // full GR8 class.
129 if (RC == &X86::GR8_NOREXRegClass)
130 return RC;
131
132 // Keep using non-rex2 register class when APX feature (EGPR/NDD/NF) is not
133 // enabled for relocation.
134 if (!X86EnableAPXForRelocation && isNonRex2RegClass(RC))
135 return RC;
136
137 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
138
139 const TargetRegisterClass *Super = RC;
140 auto I = RC->superclasses().begin();
141 auto E = RC->superclasses().end();
142 do {
143 switch (Super->getID()) {
144 case X86::FR32RegClassID:
145 case X86::FR64RegClassID:
146 // If AVX-512 isn't supported we should only inflate to these classes.
147 if (!Subtarget.hasAVX512() &&
148 getRegSizeInBits(RC: *Super) == getRegSizeInBits(RC: *RC))
149 return Super;
150 break;
151 case X86::VR128RegClassID:
152 case X86::VR256RegClassID:
153 // If VLX isn't supported we should only inflate to these classes.
154 if (!Subtarget.hasVLX() &&
155 getRegSizeInBits(RC: *Super) == getRegSizeInBits(RC: *RC))
156 return Super;
157 break;
158 case X86::VR128XRegClassID:
159 case X86::VR256XRegClassID:
160 // If VLX isn't support we shouldn't inflate to these classes.
161 if (Subtarget.hasVLX() &&
162 getRegSizeInBits(RC: *Super) == getRegSizeInBits(RC: *RC))
163 return Super;
164 break;
165 case X86::FR32XRegClassID:
166 case X86::FR64XRegClassID:
167 // If AVX-512 isn't support we shouldn't inflate to these classes.
168 if (Subtarget.hasAVX512() &&
169 getRegSizeInBits(RC: *Super) == getRegSizeInBits(RC: *RC))
170 return Super;
171 break;
172 case X86::GR8RegClassID:
173 case X86::GR16RegClassID:
174 case X86::GR32RegClassID:
175 case X86::GR64RegClassID:
176 case X86::GR8_NOREX2RegClassID:
177 case X86::GR16_NOREX2RegClassID:
178 case X86::GR32_NOREX2RegClassID:
179 case X86::GR64_NOREX2RegClassID:
180 case X86::RFP32RegClassID:
181 case X86::RFP64RegClassID:
182 case X86::RFP80RegClassID:
183 case X86::VR512_0_15RegClassID:
184 case X86::VR512RegClassID:
185 // Don't return a super-class that would shrink the spill size.
186 // That can happen with the vector and float classes.
187 if (getRegSizeInBits(RC: *Super) == getRegSizeInBits(RC: *RC))
188 return Super;
189 }
190 if (I != E) {
191 Super = getRegClass(i: *I);
192 ++I;
193 } else {
194 Super = nullptr;
195 }
196 } while (Super);
197 return RC;
198}
199
200const TargetRegisterClass *
201X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
202 assert(Kind == 0 && "this should only be used for default cases");
203 if (IsTarget64BitLP64)
204 return &X86::GR64RegClass;
205 // If the target is 64bit but we have been told to use 32bit addresses,
206 // we can still use 64-bit register as long as we know the high bits
207 // are zeros.
208 // Reflect that in the returned register class.
209 return Is64Bit ? &X86::LOW32_ADDR_ACCESSRegClass : &X86::GR32RegClass;
210}
211
212const TargetRegisterClass *
213X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
214 if (RC == &X86::CCRRegClass) {
215 if (Is64Bit)
216 return &X86::GR64RegClass;
217 else
218 return &X86::GR32RegClass;
219 }
220 return RC;
221}
222
223unsigned
224X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
225 MachineFunction &MF) const {
226 const X86FrameLowering *TFI = getFrameLowering(MF);
227
228 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
229 switch (RC->getID()) {
230 default:
231 return 0;
232 case X86::GR32RegClassID:
233 return 4 - FPDiff;
234 case X86::GR64RegClassID:
235 return 12 - FPDiff;
236 case X86::VR128RegClassID:
237 return Is64Bit ? 10 : 4;
238 case X86::VR64RegClassID:
239 return 4;
240 }
241}
242
243const MCPhysReg *
244X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
245 assert(MF && "MachineFunction required");
246
247 const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
248 const Function &F = MF->getFunction();
249 bool HasSSE = Subtarget.hasSSE1();
250 bool HasAVX = Subtarget.hasAVX();
251 bool HasAVX512 = Subtarget.hasAVX512();
252 bool HasEGPR = Subtarget.hasEGPR();
253 bool CallsEHReturn = MF->callsEHReturn();
254
255 CallingConv::ID CC = F.getCallingConv();
256
257 // If attribute NoCallerSavedRegisters exists then we set X86_INTR calling
258 // convention because it has the CSR list.
259 if (MF->getFunction().hasFnAttribute(Kind: "no_caller_saved_registers"))
260 CC = CallingConv::X86_INTR;
261
262 // If atribute specified, override the CSRs normally specified by the
263 // calling convention and use the empty set instead.
264 if (MF->getFunction().hasFnAttribute(Kind: "no_callee_saved_registers"))
265 return CSR_NoRegs_SaveList;
266
267 switch (CC) {
268 case CallingConv::GHC:
269 case CallingConv::HiPE:
270 return CSR_NoRegs_SaveList;
271 case CallingConv::AnyReg:
272 if (HasAVX)
273 return CSR_64_AllRegs_AVX_SaveList;
274 return CSR_64_AllRegs_SaveList;
275 case CallingConv::PreserveMost:
276 if (IsWin64)
277 return HasEGPR ? CSR_Win64_APX_RT_MostRegs_SaveList
278 : CSR_Win64_RT_MostRegs_SaveList;
279 return CSR_64_RT_MostRegs_SaveList;
280 case CallingConv::PreserveAll:
281 if (HasAVX)
282 return CSR_64_RT_AllRegs_AVX_SaveList;
283 return CSR_64_RT_AllRegs_SaveList;
284 case CallingConv::PreserveNone:
285 return CSR_64_NoneRegs_SaveList;
286 case CallingConv::CXX_FAST_TLS:
287 if (Is64Bit)
288 return MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR() ?
289 CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList;
290 break;
291 case CallingConv::Intel_OCL_BI: {
292 if (HasAVX512 && IsWin64)
293 return HasEGPR ? CSR_Win64_APX_Intel_OCL_BI_AVX512_SaveList
294 : CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
295 if (HasAVX512 && Is64Bit)
296 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
297 if (HasAVX && IsWin64)
298 return HasEGPR ? CSR_Win64_APX_Intel_OCL_BI_AVX_SaveList
299 : CSR_Win64_Intel_OCL_BI_AVX_SaveList;
300 if (HasAVX && Is64Bit)
301 return CSR_64_Intel_OCL_BI_AVX_SaveList;
302 if (!HasAVX && !IsWin64 && Is64Bit)
303 return CSR_64_Intel_OCL_BI_SaveList;
304 break;
305 }
306 case CallingConv::X86_RegCall:
307 if (Is64Bit) {
308 if (IsWin64) {
309 if (HasSSE)
310 return HasEGPR ? CSR_Win64_APX_RegCall_SaveList
311 : CSR_Win64_RegCall_SaveList;
312 return CSR_Win64_RegCall_NoSSE_SaveList;
313 }
314 return HasSSE ? CSR_SysV64_RegCall_SaveList
315 : CSR_SysV64_RegCall_NoSSE_SaveList;
316 }
317 return HasSSE ? CSR_32_RegCall_SaveList : CSR_32_RegCall_NoSSE_SaveList;
318 case CallingConv::CFGuard_Check:
319 assert(!Is64Bit && "CFGuard check mechanism only used on 32-bit X86");
320 return HasSSE ? CSR_Win32_CFGuard_Check_SaveList
321 : CSR_Win32_CFGuard_Check_NoSSE_SaveList;
322 case CallingConv::Cold:
323 if (Is64Bit)
324 return CSR_64_MostRegs_SaveList;
325 break;
326 case CallingConv::Win64:
327 if (HasSSE)
328 return HasEGPR ? CSR_Win64_APX_SaveList : CSR_Win64_SaveList;
329 return CSR_Win64_NoSSE_SaveList;
330 case CallingConv::SwiftTail:
331 if (!Is64Bit)
332 return CSR_32_SaveList;
333 if (IsWin64)
334 return HasEGPR ? CSR_Win64_APX_SwiftTail_SaveList
335 : CSR_Win64_SwiftTail_SaveList;
336 return CSR_64_SwiftTail_SaveList;
337 case CallingConv::X86_64_SysV:
338 if (CallsEHReturn)
339 return CSR_64EHRet_SaveList;
340 return CSR_64_SaveList;
341 case CallingConv::X86_INTR:
342 if (Is64Bit) {
343 if (HasAVX512)
344 return CSR_64_AllRegs_AVX512_SaveList;
345 if (HasAVX)
346 return CSR_64_AllRegs_AVX_SaveList;
347 if (HasSSE)
348 return CSR_64_AllRegs_SaveList;
349 return CSR_64_AllRegs_NoSSE_SaveList;
350 }
351 if (HasAVX512)
352 return CSR_32_AllRegs_AVX512_SaveList;
353 if (HasAVX)
354 return CSR_32_AllRegs_AVX_SaveList;
355 if (HasSSE)
356 return CSR_32_AllRegs_SSE_SaveList;
357 return CSR_32_AllRegs_SaveList;
358 default:
359 break;
360 }
361
362 if (Is64Bit) {
363 bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
364 F.getAttributes().hasAttrSomewhere(Kind: Attribute::SwiftError);
365 if (IsSwiftCC) {
366 if (IsWin64)
367 return HasEGPR ? CSR_Win64_APX_SwiftError_SaveList
368 : CSR_Win64_SwiftError_SaveList;
369 return CSR_64_SwiftError_SaveList;
370 }
371
372 if (IsWin64 || IsUEFI64) {
373 if (HasSSE)
374 return HasEGPR ? CSR_Win64_APX_SaveList : CSR_Win64_SaveList;
375 return CSR_Win64_NoSSE_SaveList;
376 }
377 if (CallsEHReturn)
378 return CSR_64EHRet_SaveList;
379 return CSR_64_SaveList;
380 }
381
382 return CallsEHReturn ? CSR_32EHRet_SaveList : CSR_32_SaveList;
383}
384
385const MCPhysReg *
386X86RegisterInfo::getIPRACSRegs(const MachineFunction *MF) const {
387 return Is64Bit ? CSR_IPRA_64_SaveList : CSR_IPRA_32_SaveList;
388}
389
390const MCPhysReg *X86RegisterInfo::getCalleeSavedRegsViaCopy(
391 const MachineFunction *MF) const {
392 assert(MF && "Invalid MachineFunction pointer.");
393 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
394 MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR())
395 return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
396 return nullptr;
397}
398
399const uint32_t *
400X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
401 CallingConv::ID CC) const {
402 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
403 bool HasSSE = Subtarget.hasSSE1();
404 bool HasAVX = Subtarget.hasAVX();
405 bool HasAVX512 = Subtarget.hasAVX512();
406 bool HasEGPR = Subtarget.hasEGPR();
407
408 switch (CC) {
409 case CallingConv::GHC:
410 case CallingConv::HiPE:
411 return CSR_NoRegs_RegMask;
412 case CallingConv::AnyReg:
413 if (HasAVX)
414 return CSR_64_AllRegs_AVX_RegMask;
415 return CSR_64_AllRegs_RegMask;
416 case CallingConv::PreserveMost:
417 if (IsWin64)
418 return HasEGPR ? CSR_Win64_APX_RT_MostRegs_RegMask
419 : CSR_Win64_RT_MostRegs_RegMask;
420 return CSR_64_RT_MostRegs_RegMask;
421 case CallingConv::PreserveAll:
422 if (HasAVX)
423 return CSR_64_RT_AllRegs_AVX_RegMask;
424 return CSR_64_RT_AllRegs_RegMask;
425 case CallingConv::PreserveNone:
426 return CSR_64_NoneRegs_RegMask;
427 case CallingConv::CXX_FAST_TLS:
428 if (Is64Bit)
429 return CSR_64_TLS_Darwin_RegMask;
430 break;
431 case CallingConv::Intel_OCL_BI: {
432 if (HasAVX512 && IsWin64)
433 return HasEGPR ? CSR_Win64_APX_Intel_OCL_BI_AVX512_RegMask
434 : CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
435 if (HasAVX512 && Is64Bit)
436 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
437 if (HasAVX && IsWin64)
438 return HasEGPR ? CSR_Win64_APX_Intel_OCL_BI_AVX_RegMask
439 : CSR_Win64_Intel_OCL_BI_AVX_RegMask;
440 if (HasAVX && Is64Bit)
441 return CSR_64_Intel_OCL_BI_AVX_RegMask;
442 if (!HasAVX && !IsWin64 && Is64Bit)
443 return CSR_64_Intel_OCL_BI_RegMask;
444 break;
445 }
446 case CallingConv::X86_RegCall:
447 if (Is64Bit) {
448 if (IsWin64) {
449 if (HasSSE)
450 return HasEGPR ? CSR_Win64_APX_RegCall_RegMask
451 : CSR_Win64_RegCall_RegMask;
452 return CSR_Win64_RegCall_NoSSE_RegMask;
453 }
454 return HasSSE ? CSR_SysV64_RegCall_RegMask
455 : CSR_SysV64_RegCall_NoSSE_RegMask;
456 }
457 return HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask;
458 case CallingConv::CFGuard_Check:
459 if (Is64Bit) {
460 if (HasSSE)
461 return HasEGPR ? CSR_Win64_APX_CFGuard_Check_RegMask
462 : CSR_Win64_CFGuard_Check_RegMask;
463 return CSR_Win64_CFGuard_Check_NoSSE_RegMask;
464 }
465 return HasSSE ? CSR_Win32_CFGuard_Check_RegMask
466 : CSR_Win32_CFGuard_Check_NoSSE_RegMask;
467 case CallingConv::Cold:
468 if (Is64Bit)
469 return CSR_64_MostRegs_RegMask;
470 break;
471 case CallingConv::Win64:
472 return HasEGPR ? CSR_Win64_APX_RegMask : CSR_Win64_RegMask;
473 case CallingConv::SwiftTail:
474 if (!Is64Bit)
475 return CSR_32_RegMask;
476 if (IsWin64)
477 return HasEGPR ? CSR_Win64_APX_SwiftTail_RegMask
478 : CSR_Win64_SwiftTail_RegMask;
479 return CSR_64_SwiftTail_RegMask;
480 case CallingConv::X86_64_SysV:
481 return CSR_64_RegMask;
482 case CallingConv::X86_INTR:
483 if (Is64Bit) {
484 if (HasAVX512)
485 return CSR_64_AllRegs_AVX512_RegMask;
486 if (HasAVX)
487 return CSR_64_AllRegs_AVX_RegMask;
488 if (HasSSE)
489 return CSR_64_AllRegs_RegMask;
490 return CSR_64_AllRegs_NoSSE_RegMask;
491 }
492 if (HasAVX512)
493 return CSR_32_AllRegs_AVX512_RegMask;
494 if (HasAVX)
495 return CSR_32_AllRegs_AVX_RegMask;
496 if (HasSSE)
497 return CSR_32_AllRegs_SSE_RegMask;
498 return CSR_32_AllRegs_RegMask;
499 default:
500 break;
501 }
502
503 // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
504 // callsEHReturn().
505 if (Is64Bit) {
506 const Function &F = MF.getFunction();
507 bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
508 F.getAttributes().hasAttrSomewhere(Kind: Attribute::SwiftError);
509 if (IsSwiftCC) {
510 if (IsWin64)
511 return HasEGPR ? CSR_Win64_APX_SwiftError_RegMask
512 : CSR_Win64_SwiftError_RegMask;
513 return CSR_64_SwiftError_RegMask;
514 }
515
516 if (IsWin64 || IsUEFI64)
517 return HasEGPR ? CSR_Win64_APX_RegMask : CSR_Win64_RegMask;
518 return CSR_64_RegMask;
519 }
520
521 return CSR_32_RegMask;
522}
523
524const uint32_t*
525X86RegisterInfo::getNoPreservedMask() const {
526 return CSR_NoRegs_RegMask;
527}
528
529const uint32_t *X86RegisterInfo::getDarwinTLSCallPreservedMask() const {
530 return CSR_64_TLS_Darwin_RegMask;
531}
532
533BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
534 BitVector Reserved(getNumRegs());
535 const X86FrameLowering *TFI = getFrameLowering(MF);
536
537 // Set the floating point control register as reserved.
538 Reserved.set(X86::FPCW);
539
540 // Set the floating point status register as reserved.
541 Reserved.set(X86::FPSW);
542
543 // Set the SIMD floating point control register as reserved.
544 Reserved.set(X86::MXCSR);
545
546 // Set the stack-pointer register and its aliases as reserved.
547 for (const MCPhysReg &SubReg : subregs_inclusive(Reg: X86::RSP))
548 Reserved.set(SubReg);
549
550 // Set the Shadow Stack Pointer as reserved.
551 Reserved.set(X86::SSP);
552
553 auto &ST = MF.getSubtarget<X86Subtarget>();
554 if (ST.hasUserReservedRegisters()) {
555 if (ST.is64Bit()) {
556 // Set r# as reserved register if user required.
557 for (unsigned Reg = X86::R8; Reg <= X86::R15; ++Reg)
558 if (ST.isRegisterReservedByUser(i: Reg))
559 for (const MCPhysReg &SubReg : subregs_inclusive(Reg))
560 Reserved.set(SubReg);
561 if (ST.hasEGPR())
562 for (unsigned Reg = X86::R16; Reg <= X86::R31; ++Reg)
563 if (ST.isRegisterReservedByUser(i: Reg))
564 for (const MCPhysReg &SubReg : subregs_inclusive(Reg))
565 Reserved.set(SubReg);
566 } else {
567 if (ST.isRegisterReservedByUser(i: X86::EDI))
568 for (const MCPhysReg &SubReg : sub_and_superregs_inclusive(Reg: X86::EDI))
569 Reserved.set(SubReg);
570 }
571 }
572
573 // Set the instruction pointer register and its aliases as reserved.
574 for (const MCPhysReg &SubReg : subregs_inclusive(Reg: X86::RIP))
575 Reserved.set(SubReg);
576
577 // Set the frame-pointer register and its aliases as reserved if needed.
578 if (TFI->hasFP(MF) || MF.getTarget().Options.FramePointerIsReserved(MF)) {
579 if (MF.getInfo<X86MachineFunctionInfo>()->getFPClobberedByInvoke())
580 MF.getContext().reportError(
581 L: SMLoc(),
582 Msg: "Frame pointer clobbered by function invoke is not supported.");
583
584 for (const MCPhysReg &SubReg : subregs_inclusive(Reg: X86::RBP))
585 Reserved.set(SubReg);
586 }
587
588 // Set the base-pointer register and its aliases as reserved if needed.
589 if (hasBasePointer(MF)) {
590 if (MF.getInfo<X86MachineFunctionInfo>()->getBPClobberedByInvoke())
591 MF.getContext().reportError(L: SMLoc(),
592 Msg: "Stack realignment in presence of dynamic "
593 "allocas is not supported with "
594 "this calling convention.");
595
596 Register BasePtr = getX86SubSuperRegister(Reg: getBaseRegister(), Size: 64);
597 for (const MCPhysReg &SubReg : subregs_inclusive(Reg: BasePtr))
598 Reserved.set(SubReg);
599 }
600
601 // Mark the segment registers as reserved.
602 Reserved.set(X86::CS);
603 Reserved.set(X86::SS);
604 Reserved.set(X86::DS);
605 Reserved.set(X86::ES);
606 Reserved.set(X86::FS);
607 Reserved.set(X86::GS);
608
609 // Mark the floating point stack registers as reserved.
610 for (unsigned n = 0; n != 8; ++n)
611 Reserved.set(X86::ST0 + n);
612
613 // Without usable x87 (soft float or -mno-x87), reserve the allocatable FPn
614 // pseudos (FP0-FP6; FP7 is already non-allocatable) so they aren't scrubbed.
615 if (ST.useSoftFloat() || !ST.hasX87())
616 for (unsigned n = 0; n != 7; ++n)
617 Reserved.set(X86::FP0 + n);
618
619 // Reserve the registers that only exist in 64-bit mode.
620 if (!Is64Bit) {
621 // These 8-bit registers are part of the x86-64 extension even though their
622 // super-registers are old 32-bits.
623 Reserved.set(X86::SIL);
624 Reserved.set(X86::DIL);
625 Reserved.set(X86::BPL);
626 Reserved.set(X86::SPL);
627 Reserved.set(X86::SIH);
628 Reserved.set(X86::DIH);
629 Reserved.set(X86::BPH);
630 Reserved.set(X86::SPH);
631
632 for (unsigned n = 0; n != 8; ++n) {
633 // R8, R9, ...
634 for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
635 Reserved.set(*AI);
636
637 // XMM8, XMM9, ...
638 for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
639 Reserved.set(*AI);
640 }
641 }
642 if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
643 for (unsigned n = 0; n != 16; ++n) {
644 for (MCRegAliasIterator AI(X86::XMM16 + n, this, true); AI.isValid();
645 ++AI)
646 Reserved.set(*AI);
647 }
648 }
649
650 // Reserve the extended general purpose registers.
651 if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasEGPR())
652 Reserved.set(I: X86::R16, E: X86::R31WH + 1);
653
654 // Due to specifics of setjmp unwinding in Win64 APX ABI, the unwinder
655 // cannot restore R30/R31. Reserve them to prevent register allocation.
656 // https://learn.microsoft.com/en-us/cpp/build/x64-calling-convention#setjmplongjmp
657 if (MF.exposesReturnsTwice() && ST.isTargetWin64()) {
658 unsigned NumReservedCSRs = 0;
659 for (unsigned Reg = X86::R16; Reg <= X86::R31; ++Reg)
660 if (isCalleeSavedPhysReg(PhysReg: Reg, MF)) {
661 ++NumReservedCSRs;
662 for (const MCPhysReg &SubReg : subregs_inclusive(Reg))
663 Reserved.set(SubReg);
664 }
665 if (NumReservedCSRs && MF.size() > SetjmpCSRWarningThreshold &&
666 !MF.getRegInfo().reservedRegsFrozen()) {
667 MF.getContext().reportWarning(
668 L: SMLoc(), Msg: Twine(NumReservedCSRs) +
669 " callee-saved register(s) reserved due to setjmp in '" +
670 MF.getName() +
671 "'; this may impact performance in large functions");
672 }
673 }
674
675 if (MF.getFunction().getCallingConv() == CallingConv::GRAAL) {
676 for (MCRegAliasIterator AI(X86::R14, this, true); AI.isValid(); ++AI)
677 Reserved.set(*AI);
678 for (MCRegAliasIterator AI(X86::R15, this, true); AI.isValid(); ++AI)
679 Reserved.set(*AI);
680 }
681
682 // Reserve registers for LFI sandboxing.
683 if (MF.getSubtarget<X86Subtarget>().isLFI()) {
684 for (MCRegAliasIterator AI(X86::R11, this, true); AI.isValid(); ++AI)
685 Reserved.set(*AI);
686 for (MCRegAliasIterator AI(X86::R14, this, true); AI.isValid(); ++AI)
687 Reserved.set(*AI);
688 for (MCRegAliasIterator AI(X86::R15, this, true); AI.isValid(); ++AI)
689 Reserved.set(*AI);
690 }
691
692 assert(checkAllSuperRegsMarked(Reserved,
693 {X86::SIL, X86::DIL, X86::BPL, X86::SPL,
694 X86::SIH, X86::DIH, X86::BPH, X86::SPH}));
695 return Reserved;
696}
697
698unsigned X86RegisterInfo::getNumSupportedRegs(const MachineFunction &MF) const {
699 // All existing Intel CPUs that support AMX support AVX512 and all existing
700 // Intel CPUs that support APX support AMX. AVX512 implies AVX.
701 //
702 // We enumerate the registers in X86GenRegisterInfo.inc in this order:
703 //
704 // Registers before AVX512,
705 // AVX512 registers (X/YMM16-31, ZMM0-31, K registers)
706 // AMX registers (TMM)
707 // APX registers (R16-R31)
708 //
709 // and try to return the minimum number of registers supported by the target.
710 static_assert((X86::R15WH + 1 == X86::YMM0) && (X86::YMM15 + 1 == X86::K0) &&
711 (X86::K6_K7 + 1 == X86::TMMCFG) &&
712 (X86::TMM7 + 1 == X86::R16) &&
713 (X86::R31WH + 1 == X86::NUM_TARGET_REGS),
714 "Register number may be incorrect");
715
716 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
717 if (ST.hasEGPR())
718 return X86::NUM_TARGET_REGS;
719 if (ST.hasAMXTILE())
720 return X86::TMM7 + 1;
721 if (ST.hasAVX512())
722 return X86::K6_K7 + 1;
723 if (ST.hasAVX())
724 return X86::YMM15 + 1;
725 return X86::R15WH + 1;
726}
727
728bool X86RegisterInfo::isArgumentRegister(const MachineFunction &MF,
729 MCRegister Reg) const {
730 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
731 const TargetRegisterInfo &TRI = *ST.getRegisterInfo();
732 auto IsSubReg = [&](MCRegister RegA, MCRegister RegB) {
733 return TRI.isSuperOrSubRegisterEq(RegA, RegB);
734 };
735
736 if (!ST.is64Bit())
737 return llvm::any_of(
738 Range: SmallVector<MCRegister>{X86::EAX, X86::ECX, X86::EDX},
739 P: [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); }) ||
740 (ST.hasMMX() && X86::VR64RegClass.contains(Reg));
741
742 CallingConv::ID CC = MF.getFunction().getCallingConv();
743
744 if (CC == CallingConv::X86_64_SysV && IsSubReg(X86::RAX, Reg))
745 return true;
746
747 if (llvm::any_of(
748 Range: SmallVector<MCRegister>{X86::RDX, X86::RCX, X86::R8, X86::R9},
749 P: [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); }))
750 return true;
751
752 if (CC != CallingConv::Win64 &&
753 llvm::any_of(Range: SmallVector<MCRegister>{X86::RDI, X86::RSI},
754 P: [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); }))
755 return true;
756
757 if (ST.hasSSE1() &&
758 llvm::any_of(Range: SmallVector<MCRegister>{X86::XMM0, X86::XMM1, X86::XMM2,
759 X86::XMM3, X86::XMM4, X86::XMM5,
760 X86::XMM6, X86::XMM7},
761 P: [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); }))
762 return true;
763
764 return X86GenRegisterInfo::isArgumentRegister(MF, PhysReg: Reg);
765}
766
767bool X86RegisterInfo::isFixedRegister(const MachineFunction &MF,
768 MCRegister PhysReg) const {
769 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
770 const TargetRegisterInfo &TRI = *ST.getRegisterInfo();
771
772 // Stack pointer.
773 if (TRI.isSuperOrSubRegisterEq(RegA: X86::RSP, RegB: PhysReg))
774 return true;
775
776 // Don't use the frame pointer if it's being used.
777 const X86FrameLowering &TFI = *getFrameLowering(MF);
778 if (TFI.hasFP(MF) && TRI.isSuperOrSubRegisterEq(RegA: X86::RBP, RegB: PhysReg))
779 return true;
780
781 return X86GenRegisterInfo::isFixedRegister(MF, PhysReg);
782}
783
784bool X86RegisterInfo::isTileRegisterClass(const TargetRegisterClass *RC) const {
785 return RC->getID() == X86::TILERegClassID;
786}
787
788void X86RegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
789 // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
790 // because the calling convention defines the EFLAGS register as NOT
791 // preserved.
792 //
793 // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
794 // an assert to track this and clear the register afterwards to avoid
795 // unnecessary crashes during release builds.
796 assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
797 "EFLAGS are not live-out from a patchpoint.");
798
799 // Also clean other registers that don't need preserving (IP).
800 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
801 Mask[Reg / 32] &= ~(1U << (Reg % 32));
802}
803
804//===----------------------------------------------------------------------===//
805// Stack Frame Processing methods
806//===----------------------------------------------------------------------===//
807
808static bool CantUseSP(const MachineFrameInfo &MFI) {
809 return MFI.hasVarSizedObjects() || MFI.hasOpaqueSPAdjustment();
810}
811
812bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
813 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
814 // We have a virtual register to reference argument, and don't need base
815 // pointer.
816 if (X86FI->getStackPtrSaveMI() != nullptr)
817 return false;
818
819 if (X86FI->hasPreallocatedCall())
820 return true;
821
822 const MachineFrameInfo &MFI = MF.getFrameInfo();
823
824 if (!EnableBasePointer)
825 return false;
826
827 // When we need stack realignment, we can't address the stack from the frame
828 // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
829 // can't address variables from the stack pointer. MS inline asm can
830 // reference locals while also adjusting the stack pointer. When we can't
831 // use both the SP and the FP, we need a separate base pointer register.
832 bool CantUseFP = hasStackRealignment(MF);
833 return CantUseFP && CantUseSP(MFI);
834}
835
836bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
837 if (!TargetRegisterInfo::canRealignStack(MF))
838 return false;
839
840 const MachineFrameInfo &MFI = MF.getFrameInfo();
841 const MachineRegisterInfo *MRI = &MF.getRegInfo();
842
843 // Stack realignment requires a frame pointer. If we already started
844 // register allocation with frame pointer elimination, it is too late now.
845 if (!MRI->canReserveReg(PhysReg: FramePtr))
846 return false;
847
848 // If a base pointer is necessary. Check that it isn't too late to reserve
849 // it.
850 if (CantUseSP(MFI))
851 return MRI->canReserveReg(PhysReg: BasePtr);
852 return true;
853}
854
855bool X86RegisterInfo::shouldRealignStack(const MachineFunction &MF) const {
856 if (TargetRegisterInfo::shouldRealignStack(MF))
857 return true;
858
859 return !Is64Bit && MF.getFunction().getCallingConv() == CallingConv::X86_INTR;
860}
861
862// tryOptimizeLEAtoMOV - helper function that tries to replace a LEA instruction
863// of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx'.
864// TODO: In this case we should be really trying first to entirely eliminate
865// this instruction which is a plain copy.
866static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II) {
867 MachineInstr &MI = *II;
868 unsigned Opc = II->getOpcode();
869 // Check if this is a LEA of the form 'lea (%esp), %ebx'
870 if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
871 MI.getOperand(i: 2).getImm() != 1 ||
872 MI.getOperand(i: 3).getReg() != X86::NoRegister ||
873 MI.getOperand(i: 4).getImm() != 0 ||
874 MI.getOperand(i: 5).getReg() != X86::NoRegister)
875 return false;
876 Register BasePtr = MI.getOperand(i: 1).getReg();
877 // In X32 mode, ensure the base-pointer is a 32-bit operand, so the LEA will
878 // be replaced with a 32-bit operand MOV which will zero extend the upper
879 // 32-bits of the super register.
880 if (Opc == X86::LEA64_32r)
881 BasePtr = getX86SubSuperRegister(Reg: BasePtr, Size: 32);
882 Register NewDestReg = MI.getOperand(i: 0).getReg();
883 const X86InstrInfo *TII =
884 MI.getParent()->getParent()->getSubtarget<X86Subtarget>().getInstrInfo();
885 TII->copyPhysReg(MBB&: *MI.getParent(), MI: II, DL: MI.getDebugLoc(), DestReg: NewDestReg, SrcReg: BasePtr,
886 KillSrc: MI.getOperand(i: 1).isKill());
887 MI.eraseFromParent();
888 return true;
889}
890
891static bool isFuncletReturnInstr(MachineInstr &MI) {
892 switch (MI.getOpcode()) {
893 case X86::CATCHRET:
894 case X86::CLEANUPRET:
895 return true;
896 default:
897 return false;
898 }
899 llvm_unreachable("impossible");
900}
901
902void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
903 unsigned FIOperandNum,
904 Register BaseReg,
905 int FIOffset) const {
906 MachineInstr &MI = *II;
907 unsigned Opc = MI.getOpcode();
908 if (Opc == TargetOpcode::LOCAL_ESCAPE) {
909 MachineOperand &FI = MI.getOperand(i: FIOperandNum);
910 FI.ChangeToImmediate(ImmVal: FIOffset);
911 return;
912 }
913
914 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: BaseReg, isDef: false);
915
916 // The frame index format for stackmaps and patchpoints is different from the
917 // X86 format. It only has a FI and an offset.
918 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
919 assert(BasePtr == FramePtr && "Expected the FP as base register");
920 int64_t Offset = MI.getOperand(i: FIOperandNum + 1).getImm() + FIOffset;
921 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Offset);
922 return;
923 }
924
925 if (MI.getOperand(i: FIOperandNum + 3).isImm()) {
926 // Offset is a 32-bit integer.
927 int Imm = (int)(MI.getOperand(i: FIOperandNum + 3).getImm());
928 int Offset = FIOffset + Imm;
929 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
930 "Requesting 64-bit offset in 32-bit immediate!");
931 if (Offset != 0)
932 MI.getOperand(i: FIOperandNum + 3).ChangeToImmediate(ImmVal: Offset);
933 } else {
934 // Offset is symbolic. This is extremely rare.
935 uint64_t Offset =
936 FIOffset + (uint64_t)MI.getOperand(i: FIOperandNum + 3).getOffset();
937 MI.getOperand(i: FIOperandNum + 3).setOffset(Offset);
938 }
939}
940
941bool
942X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
943 int SPAdj, unsigned FIOperandNum,
944 RegScavenger *RS) const {
945 MachineInstr &MI = *II;
946 MachineBasicBlock &MBB = *MI.getParent();
947 MachineFunction &MF = *MBB.getParent();
948 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
949 bool IsEHFuncletEpilogue = MBBI == MBB.end() ? false
950 : isFuncletReturnInstr(MI&: *MBBI);
951 const X86FrameLowering *TFI = getFrameLowering(MF);
952 int FrameIndex = MI.getOperand(i: FIOperandNum).getIndex();
953
954 // Determine base register and offset.
955 int64_t FIOffset;
956 Register BasePtr;
957 if (MI.isReturn()) {
958 assert((!hasStackRealignment(MF) ||
959 MF.getFrameInfo().isFixedObjectIndex(FrameIndex)) &&
960 "Return instruction can only reference SP relative frame objects");
961 FIOffset =
962 TFI->getFrameIndexReferenceSP(MF, FI: FrameIndex, SPReg&: BasePtr, Adjustment: 0).getFixed();
963 } else if (TFI->Is64Bit && (MBB.isEHFuncletEntry() || IsEHFuncletEpilogue)) {
964 FIOffset = TFI->getWin64EHFrameIndexRef(MF, FI: FrameIndex, SPReg&: BasePtr);
965 } else {
966 FIOffset = TFI->getFrameIndexReference(MF, FI: FrameIndex, FrameReg&: BasePtr).getFixed();
967 }
968
969 // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
970 // simple FP case, and doesn't work with stack realignment. On 32-bit, the
971 // offset is from the traditional base pointer location. On 64-bit, the
972 // offset is from the SP at the end of the prologue, not the FP location. This
973 // matches the behavior of llvm.frameaddress.
974 unsigned Opc = MI.getOpcode();
975 if (Opc == TargetOpcode::LOCAL_ESCAPE) {
976 MachineOperand &FI = MI.getOperand(i: FIOperandNum);
977 FI.ChangeToImmediate(ImmVal: FIOffset);
978 return false;
979 }
980
981 // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
982 // register as source operand, semantic is the same and destination is
983 // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
984 // Don't change BasePtr since it is used later for stack adjustment.
985 Register MachineBasePtr = BasePtr;
986 if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(Reg: BasePtr))
987 MachineBasePtr = getX86SubSuperRegister(Reg: BasePtr, Size: 64);
988
989 // This must be part of a four operand memory reference. Replace the
990 // FrameIndex with base register. Add an offset to the offset.
991 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: MachineBasePtr, isDef: false);
992
993 if (BasePtr == StackPtr)
994 FIOffset += SPAdj;
995
996 // The frame index format for stackmaps and patchpoints is different from the
997 // X86 format. It only has a FI and an offset.
998 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
999 assert(BasePtr == FramePtr && "Expected the FP as base register");
1000 int64_t Offset = MI.getOperand(i: FIOperandNum + 1).getImm() + FIOffset;
1001 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Offset);
1002 return false;
1003 }
1004
1005 if (MI.getOperand(i: FIOperandNum+3).isImm()) {
1006 const X86InstrInfo *TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
1007 const DebugLoc &DL = MI.getDebugLoc();
1008 int64_t Imm = MI.getOperand(i: FIOperandNum + 3).getImm();
1009 int64_t Offset = FIOffset + Imm;
1010 bool FitsIn32Bits = isInt<32>(x: Offset);
1011 // If the offset will not fit in a 32-bit displacement, then for 64-bit
1012 // targets, scavenge a register to hold it. Otherwise...
1013 if (Is64Bit && !FitsIn32Bits) {
1014 assert(RS && "RegisterScavenger was NULL");
1015
1016 RS->enterBasicBlockEnd(MBB);
1017 RS->backward(I: std::next(x: II));
1018
1019 Register ScratchReg = RS->scavengeRegisterBackwards(
1020 RC: X86::GR64RegClass, To: II, /*RestoreAfter=*/false, /*SPAdj=*/0,
1021 /*AllowSpill=*/true);
1022 assert(ScratchReg != 0 && "scratch reg was 0");
1023 RS->setRegUsed(Reg: ScratchReg);
1024
1025 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: X86::MOV64ri), DestReg: ScratchReg).addImm(Val: Offset);
1026
1027 MI.getOperand(i: FIOperandNum + 3).setImm(0);
1028 MI.getOperand(i: FIOperandNum + 2).setReg(ScratchReg);
1029
1030 return false;
1031 }
1032
1033 // ... for 32-bit targets, this is a bug!
1034 if (!Is64Bit && !FitsIn32Bits) {
1035 MI.emitGenericError(ErrMsg: "64-bit offset calculated but target is 32-bit");
1036 // Trap so that the instruction verification pass does not fail if run.
1037 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: X86::TRAP));
1038 return false;
1039 }
1040
1041 if (Offset != 0 || !tryOptimizeLEAtoMOV(II))
1042 MI.getOperand(i: FIOperandNum + 3).ChangeToImmediate(ImmVal: Offset);
1043 } else {
1044 // Offset is symbolic. This is extremely rare.
1045 uint64_t Offset = FIOffset +
1046 (uint64_t)MI.getOperand(i: FIOperandNum+3).getOffset();
1047 MI.getOperand(i: FIOperandNum + 3).setOffset(Offset);
1048 }
1049 return false;
1050}
1051
1052unsigned X86RegisterInfo::findDeadCallerSavedReg(
1053 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI) const {
1054 const MachineFunction *MF = MBB.getParent();
1055 const MachineRegisterInfo &MRI = MF->getRegInfo();
1056 if (MF->callsEHReturn())
1057 return 0;
1058
1059 if (MBBI == MBB.end())
1060 return 0;
1061
1062 switch (MBBI->getOpcode()) {
1063 default:
1064 return 0;
1065 case TargetOpcode::PATCHABLE_RET:
1066 case X86::RET:
1067 case X86::RET32:
1068 case X86::RET64:
1069 case X86::RETI32:
1070 case X86::RETI64:
1071 case X86::TCRETURNdi:
1072 case X86::TCRETURNri:
1073 case X86::TCRETURN_WIN64ri:
1074 case X86::TCRETURN_HIPE32ri:
1075 case X86::TCRETURNmi:
1076 case X86::TCRETURNdi64:
1077 case X86::TCRETURNri64:
1078 case X86::TCRETURNri64_ImpCall:
1079 case X86::TCRETURNmi64:
1080 case X86::TCRETURN_WINmi64:
1081 case X86::EH_RETURN:
1082 case X86::EH_RETURN64: {
1083 LiveRegUnits LRU(*this);
1084 LRU.addLiveOuts(MBB);
1085 LRU.stepBackward(MI: *MBBI);
1086
1087 const TargetRegisterClass &RC =
1088 Is64Bit ? X86::GR64_NOSPRegClass : X86::GR32_NOSPRegClass;
1089 for (MCRegister Reg : RC) {
1090 if (LRU.available(Reg) && !MRI.isReserved(PhysReg: Reg))
1091 return Reg;
1092 }
1093 }
1094 }
1095
1096 return 0;
1097}
1098
1099Register X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1100 const X86FrameLowering *TFI = getFrameLowering(MF);
1101 return TFI->hasFP(MF) ? FramePtr : StackPtr;
1102}
1103
1104Register
1105X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const {
1106 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
1107 Register FrameReg = getFrameRegister(MF);
1108 if (Subtarget.isTarget64BitILP32())
1109 FrameReg = getX86SubSuperRegister(Reg: FrameReg, Size: 32);
1110 return FrameReg;
1111}
1112
1113Register
1114X86RegisterInfo::getPtrSizedStackRegister(const MachineFunction &MF) const {
1115 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
1116 Register StackReg = getStackRegister();
1117 if (Subtarget.isTarget64BitILP32())
1118 StackReg = getX86SubSuperRegister(Reg: StackReg, Size: 32);
1119 return StackReg;
1120}
1121
1122static ShapeT getTileShape(Register VirtReg, VirtRegMap *VRM,
1123 const MachineRegisterInfo *MRI) {
1124 if (VRM->hasShape(virtReg: VirtReg))
1125 return VRM->getShape(virtReg: VirtReg);
1126
1127 const MachineOperand &Def = *MRI->def_begin(RegNo: VirtReg);
1128 MachineInstr *MI = const_cast<MachineInstr *>(Def.getParent());
1129 unsigned OpCode = MI->getOpcode();
1130 switch (OpCode) {
1131 default:
1132 llvm_unreachable("Unexpected machine instruction on tile register!");
1133 break;
1134 case X86::COPY: {
1135 Register SrcReg = MI->getOperand(i: 1).getReg();
1136 ShapeT Shape = getTileShape(VirtReg: SrcReg, VRM, MRI);
1137 VRM->assignVirt2Shape(virtReg: VirtReg, shape: Shape);
1138 return Shape;
1139 }
1140 // We only collect the tile shape that is defined.
1141 case X86::PTILELOADDV:
1142 case X86::PTILELOADDT1V:
1143 case X86::PTDPBSSDV:
1144 case X86::PTDPBSUDV:
1145 case X86::PTDPBUSDV:
1146 case X86::PTDPBUUDV:
1147 case X86::PTILEZEROV:
1148 case X86::PTDPBF16PSV:
1149 case X86::PTDPFP16PSV:
1150 case X86::PTCMMIMFP16PSV:
1151 case X86::PTCMMRLFP16PSV:
1152 case X86::PTILELOADDRSV:
1153 case X86::PTILELOADDRST1V:
1154 case X86::PTDPBF8PSV:
1155 case X86::PTDPBHF8PSV:
1156 case X86::PTDPHBF8PSV:
1157 case X86::PTDPHF8PSV: {
1158 MachineOperand &MO1 = MI->getOperand(i: 1);
1159 MachineOperand &MO2 = MI->getOperand(i: 2);
1160 ShapeT Shape(&MO1, &MO2, MRI);
1161 VRM->assignVirt2Shape(virtReg: VirtReg, shape: Shape);
1162 return Shape;
1163 }
1164 }
1165}
1166
1167bool X86RegisterInfo::getRegAllocationHints(Register VirtReg,
1168 ArrayRef<MCPhysReg> Order,
1169 SmallVectorImpl<MCPhysReg> &Hints,
1170 const MachineFunction &MF,
1171 const VirtRegMap *VRM,
1172 const LiveRegMatrix *Matrix) const {
1173 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1174 const TargetRegisterClass &RC = *MRI->getRegClass(Reg: VirtReg);
1175 bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
1176 VirtReg, Order, Hints, MF, VRM, Matrix);
1177 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
1178 const TargetRegisterInfo &TRI = *ST.getRegisterInfo();
1179
1180 unsigned ID = RC.getID();
1181
1182 if (!VRM)
1183 return BaseImplRetVal;
1184
1185 if (ID != X86::TILERegClassID) {
1186 if (DisableRegAllocNDDHints || !ST.hasNDD() ||
1187 !TRI.isGeneralPurposeRegisterClass(RC: &RC))
1188 return BaseImplRetVal;
1189
1190 // Add any two address hints after any copy hints.
1191 SmallSet<unsigned, 4> TwoAddrHints;
1192
1193 auto TryAddNDDHint = [&](const MachineOperand &MO) {
1194 Register Reg = MO.getReg();
1195 Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(virtReg: Reg));
1196 if (PhysReg && !MRI->isReserved(PhysReg) && !is_contained(Range&: Hints, Element: PhysReg))
1197 TwoAddrHints.insert(V: PhysReg);
1198 };
1199
1200 // NDD instructions is compressible when Op0 is allocated to the same
1201 // physic register as Op1 (or Op2 if it's commutable).
1202 for (auto &MO : MRI->reg_nodbg_operands(Reg: VirtReg)) {
1203 const MachineInstr &MI = *MO.getParent();
1204 if (!X86::getNonNDVariant(Opc: MI.getOpcode()))
1205 continue;
1206 unsigned OpIdx = MI.getOperandNo(I: &MO);
1207 if (OpIdx == 0) {
1208 assert(MI.getOperand(1).isReg());
1209 TryAddNDDHint(MI.getOperand(i: 1));
1210 if (MI.isCommutable()) {
1211 assert(MI.getOperand(2).isReg());
1212 TryAddNDDHint(MI.getOperand(i: 2));
1213 }
1214 } else if (OpIdx == 1) {
1215 TryAddNDDHint(MI.getOperand(i: 0));
1216 } else if (MI.isCommutable() && OpIdx == 2) {
1217 TryAddNDDHint(MI.getOperand(i: 0));
1218 }
1219 }
1220
1221 for (MCPhysReg OrderReg : Order)
1222 if (TwoAddrHints.count(V: OrderReg))
1223 Hints.push_back(Elt: OrderReg);
1224
1225 return BaseImplRetVal;
1226 }
1227
1228 ShapeT VirtShape = getTileShape(VirtReg, VRM: const_cast<VirtRegMap *>(VRM), MRI);
1229 auto AddHint = [&](MCPhysReg PhysReg) {
1230 Register VReg = Matrix->getOneVReg(PhysReg);
1231 if (VReg == MCRegister::NoRegister) { // Not allocated yet
1232 Hints.push_back(Elt: PhysReg);
1233 return;
1234 }
1235 ShapeT PhysShape = getTileShape(VirtReg: VReg, VRM: const_cast<VirtRegMap *>(VRM), MRI);
1236 if (PhysShape == VirtShape)
1237 Hints.push_back(Elt: PhysReg);
1238 };
1239
1240 SmallSet<MCPhysReg, 4> CopyHints(llvm::from_range, Hints);
1241 Hints.clear();
1242 for (auto Hint : CopyHints) {
1243 if (RC.contains(Reg: Hint) && !MRI->isReserved(PhysReg: Hint))
1244 AddHint(Hint);
1245 }
1246 for (MCPhysReg PhysReg : Order) {
1247 if (!CopyHints.count(V: PhysReg) && RC.contains(Reg: PhysReg) &&
1248 !MRI->isReserved(PhysReg))
1249 AddHint(PhysReg);
1250 }
1251
1252#define DEBUG_TYPE "tile-hint"
1253 LLVM_DEBUG({
1254 dbgs() << "Hints for virtual register " << format_hex(VirtReg, 8) << "\n";
1255 for (auto Hint : Hints) {
1256 dbgs() << "tmm" << Hint << ",";
1257 }
1258 dbgs() << "\n";
1259 });
1260#undef DEBUG_TYPE
1261
1262 return true;
1263}
1264
1265const TargetRegisterClass *X86RegisterInfo::constrainRegClassToNonRex2(
1266 const TargetRegisterClass *RC) const {
1267 switch (RC->getID()) {
1268 default:
1269 return RC;
1270 case X86::GR8RegClassID:
1271 return &X86::GR8_NOREX2RegClass;
1272 case X86::GR16RegClassID:
1273 return &X86::GR16_NOREX2RegClass;
1274 case X86::GR32RegClassID:
1275 return &X86::GR32_NOREX2RegClass;
1276 case X86::GR64RegClassID:
1277 return &X86::GR64_NOREX2RegClass;
1278 case X86::GR32_NOSPRegClassID:
1279 return &X86::GR32_NOREX2_NOSPRegClass;
1280 case X86::GR64_NOSPRegClassID:
1281 return &X86::GR64_NOREX2_NOSPRegClass;
1282 }
1283}
1284
1285bool X86RegisterInfo::isNonRex2RegClass(const TargetRegisterClass *RC) const {
1286 switch (RC->getID()) {
1287 default:
1288 return false;
1289 case X86::GR8_NOREX2RegClassID:
1290 case X86::GR16_NOREX2RegClassID:
1291 case X86::GR32_NOREX2RegClassID:
1292 case X86::GR64_NOREX2RegClassID:
1293 case X86::GR32_NOREX2_NOSPRegClassID:
1294 case X86::GR64_NOREX2_NOSPRegClassID:
1295 case X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID:
1296 return true;
1297 }
1298}
1299