1//===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the X86 implementation of the TargetRegisterInfo class.
10// This file is responsible for the frame pointer elimination optimization
11// on X86.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86RegisterInfo.h"
16#include "X86FrameLowering.h"
17#include "X86MachineFunctionInfo.h"
18#include "X86Subtarget.h"
19#include "llvm/ADT/BitVector.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/ADT/SmallSet.h"
22#include "llvm/CodeGen/LiveRegMatrix.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/RegisterScavenging.h"
26#include "llvm/CodeGen/TargetFrameLowering.h"
27#include "llvm/CodeGen/TargetInstrInfo.h"
28#include "llvm/CodeGen/TileShapeInfo.h"
29#include "llvm/CodeGen/VirtRegMap.h"
30#include "llvm/IR/Function.h"
31#include "llvm/IR/Type.h"
32#include "llvm/MC/MCContext.h"
33#include "llvm/Support/CommandLine.h"
34#include "llvm/Support/ErrorHandling.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetOptions.h"
37
38using namespace llvm;
39
40#define GET_REGINFO_TARGET_DESC
41#include "X86GenRegisterInfo.inc"
42
43static cl::opt<bool>
44EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(Val: true),
45 cl::desc("Enable use of a base pointer for complex stack frames"));
46
47static cl::opt<bool>
48 DisableRegAllocNDDHints("x86-disable-regalloc-hints-for-ndd", cl::Hidden,
49 cl::init(Val: false),
50 cl::desc("Disable two address hints for register "
51 "allocation"));
52
53static cl::opt<unsigned> SetjmpCSRWarningThreshold(
54 "x86-setjmp-csr-warning-threshold", cl::Hidden, cl::init(Val: 50),
55 cl::desc("Basic block count threshold for emitting a warning about "
56 "callee-saved registers reserved due to setjmp"));
57
58extern cl::opt<bool> X86EnableAPXForRelocation;
59
60X86RegisterInfo::X86RegisterInfo(const Triple &TT)
61 : X86GenRegisterInfo((TT.isX86_64() ? X86::RIP : X86::EIP),
62 X86_MC::getDwarfRegFlavour(TT, isEH: false),
63 X86_MC::getDwarfRegFlavour(TT, isEH: true),
64 (TT.isX86_64() ? X86::RIP : X86::EIP)) {
65 X86_MC::initLLVMToSEHAndCVRegMapping(MRI: this);
66
67 // Cache some information.
68 Is64Bit = TT.isX86_64();
69 IsTarget64BitLP64 = Is64Bit && !TT.isX32();
70 IsWin64 = Is64Bit && TT.isOSWindows();
71 IsUEFI64 = Is64Bit && TT.isUEFI();
72
73 // Use a callee-saved register as the base pointer. These registers must
74 // not conflict with any ABI requirements. For example, in 32-bit mode PIC
75 // requires GOT in the EBX register before function calls via PLT GOT pointer.
76 if (Is64Bit) {
77 SlotSize = 8;
78 // This matches the simplified 32-bit pointer code in the data layout
79 // computation.
80 // FIXME: Should use the data layout?
81 bool Use64BitReg = !TT.isX32();
82 StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
83 FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
84 BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
85 } else {
86 SlotSize = 4;
87 StackPtr = X86::ESP;
88 FramePtr = X86::EBP;
89 BasePtr = X86::ESI;
90 }
91}
92
93const TargetRegisterClass *
94X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
95 unsigned Idx) const {
96 // The sub_8bit sub-register index is more constrained in 32-bit mode.
97 // It behaves just like the sub_8bit_hi index.
98 if (!Is64Bit && Idx == X86::sub_8bit)
99 Idx = X86::sub_8bit_hi;
100
101 // Forward to TableGen's default version.
102 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
103}
104
105const TargetRegisterClass *
106X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
107 const TargetRegisterClass *B,
108 unsigned SubIdx) const {
109 // The sub_8bit sub-register index is more constrained in 32-bit mode.
110 if (!Is64Bit && SubIdx == X86::sub_8bit) {
111 A = X86GenRegisterInfo::getSubClassWithSubReg(RC: A, Idx: X86::sub_8bit_hi);
112 if (!A)
113 return nullptr;
114 }
115 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, Idx: SubIdx);
116}
117
118const TargetRegisterClass *
119X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
120 const MachineFunction &MF) const {
121 // Don't allow super-classes of GR8_NOREX. This class is only used after
122 // extracting sub_8bit_hi sub-registers. The H sub-registers cannot be copied
123 // to the full GR8 register class in 64-bit mode, so we cannot allow the
124 // reigster class inflation.
125 //
126 // The GR8_NOREX class is always used in a way that won't be constrained to a
127 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
128 // full GR8 class.
129 if (RC == &X86::GR8_NOREXRegClass)
130 return RC;
131
132 // Keep using non-rex2 register class when APX feature (EGPR/NDD/NF) is not
133 // enabled for relocation.
134 if (!X86EnableAPXForRelocation && isNonRex2RegClass(RC))
135 return RC;
136
137 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
138
139 const TargetRegisterClass *Super = RC;
140 auto I = RC->superclasses().begin();
141 auto E = RC->superclasses().end();
142 do {
143 switch (Super->getID()) {
144 case X86::FR32RegClassID:
145 case X86::FR64RegClassID:
146 // If AVX-512 isn't supported we should only inflate to these classes.
147 if (!Subtarget.hasAVX512() &&
148 getRegSizeInBits(RC: *Super) == getRegSizeInBits(RC: *RC))
149 return Super;
150 break;
151 case X86::VR128RegClassID:
152 case X86::VR256RegClassID:
153 // If VLX isn't supported we should only inflate to these classes.
154 if (!Subtarget.hasVLX() &&
155 getRegSizeInBits(RC: *Super) == getRegSizeInBits(RC: *RC))
156 return Super;
157 break;
158 case X86::VR128XRegClassID:
159 case X86::VR256XRegClassID:
160 // If VLX isn't support we shouldn't inflate to these classes.
161 if (Subtarget.hasVLX() &&
162 getRegSizeInBits(RC: *Super) == getRegSizeInBits(RC: *RC))
163 return Super;
164 break;
165 case X86::FR32XRegClassID:
166 case X86::FR64XRegClassID:
167 // If AVX-512 isn't support we shouldn't inflate to these classes.
168 if (Subtarget.hasAVX512() &&
169 getRegSizeInBits(RC: *Super) == getRegSizeInBits(RC: *RC))
170 return Super;
171 break;
172 case X86::GR8RegClassID:
173 case X86::GR16RegClassID:
174 case X86::GR32RegClassID:
175 case X86::GR64RegClassID:
176 case X86::GR8_NOREX2RegClassID:
177 case X86::GR16_NOREX2RegClassID:
178 case X86::GR32_NOREX2RegClassID:
179 case X86::GR64_NOREX2RegClassID:
180 case X86::RFP32RegClassID:
181 case X86::RFP64RegClassID:
182 case X86::RFP80RegClassID:
183 case X86::VR512_0_15RegClassID:
184 case X86::VR512RegClassID:
185 // Don't return a super-class that would shrink the spill size.
186 // That can happen with the vector and float classes.
187 if (getRegSizeInBits(RC: *Super) == getRegSizeInBits(RC: *RC))
188 return Super;
189 }
190 if (I != E) {
191 Super = getRegClass(i: *I);
192 ++I;
193 } else {
194 Super = nullptr;
195 }
196 } while (Super);
197 return RC;
198}
199
200const TargetRegisterClass *
201X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
202 assert(Kind == 0 && "this should only be used for default cases");
203 if (IsTarget64BitLP64)
204 return &X86::GR64RegClass;
205 // If the target is 64bit but we have been told to use 32bit addresses,
206 // we can still use 64-bit register as long as we know the high bits
207 // are zeros.
208 // Reflect that in the returned register class.
209 return Is64Bit ? &X86::LOW32_ADDR_ACCESSRegClass : &X86::GR32RegClass;
210}
211
212const TargetRegisterClass *
213X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
214 if (RC == &X86::CCRRegClass) {
215 if (Is64Bit)
216 return &X86::GR64RegClass;
217 else
218 return &X86::GR32RegClass;
219 }
220 return RC;
221}
222
223unsigned
224X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
225 MachineFunction &MF) const {
226 const X86FrameLowering *TFI = getFrameLowering(MF);
227
228 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
229 switch (RC->getID()) {
230 default:
231 return 0;
232 case X86::GR32RegClassID:
233 return 4 - FPDiff;
234 case X86::GR64RegClassID:
235 return 12 - FPDiff;
236 case X86::VR128RegClassID:
237 return Is64Bit ? 10 : 4;
238 case X86::VR64RegClassID:
239 return 4;
240 }
241}
242
243const MCPhysReg *
244X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
245 assert(MF && "MachineFunction required");
246
247 const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
248 const Function &F = MF->getFunction();
249 bool HasSSE = Subtarget.hasSSE1();
250 bool HasAVX = Subtarget.hasAVX();
251 bool HasAVX512 = Subtarget.hasAVX512();
252 bool HasEGPR = Subtarget.hasEGPR();
253 bool CallsEHReturn = MF->callsEHReturn();
254
255 CallingConv::ID CC = F.getCallingConv();
256
257 // If attribute NoCallerSavedRegisters exists then we set X86_INTR calling
258 // convention because it has the CSR list.
259 if (MF->getFunction().hasFnAttribute(Kind: "no_caller_saved_registers"))
260 CC = CallingConv::X86_INTR;
261
262 // If atribute specified, override the CSRs normally specified by the
263 // calling convention and use the empty set instead.
264 if (MF->getFunction().hasFnAttribute(Kind: "no_callee_saved_registers"))
265 return CSR_NoRegs_SaveList;
266
267 switch (CC) {
268 case CallingConv::GHC:
269 case CallingConv::HiPE:
270 return CSR_NoRegs_SaveList;
271 case CallingConv::AnyReg:
272 if (HasAVX)
273 return CSR_64_AllRegs_AVX_SaveList;
274 return CSR_64_AllRegs_SaveList;
275 case CallingConv::PreserveMost:
276 if (IsWin64)
277 return HasEGPR ? CSR_Win64_APX_RT_MostRegs_SaveList
278 : CSR_Win64_RT_MostRegs_SaveList;
279 return CSR_64_RT_MostRegs_SaveList;
280 case CallingConv::PreserveAll:
281 if (HasAVX)
282 return CSR_64_RT_AllRegs_AVX_SaveList;
283 return CSR_64_RT_AllRegs_SaveList;
284 case CallingConv::PreserveNone:
285 return CSR_64_NoneRegs_SaveList;
286 case CallingConv::CXX_FAST_TLS:
287 if (Is64Bit)
288 return MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR() ?
289 CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList;
290 break;
291 case CallingConv::Intel_OCL_BI: {
292 if (HasAVX512 && IsWin64)
293 return HasEGPR ? CSR_Win64_APX_Intel_OCL_BI_AVX512_SaveList
294 : CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
295 if (HasAVX512 && Is64Bit)
296 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
297 if (HasAVX && IsWin64)
298 return HasEGPR ? CSR_Win64_APX_Intel_OCL_BI_AVX_SaveList
299 : CSR_Win64_Intel_OCL_BI_AVX_SaveList;
300 if (HasAVX && Is64Bit)
301 return CSR_64_Intel_OCL_BI_AVX_SaveList;
302 if (!HasAVX && !IsWin64 && Is64Bit)
303 return CSR_64_Intel_OCL_BI_SaveList;
304 break;
305 }
306 case CallingConv::X86_RegCall:
307 if (Is64Bit) {
308 if (IsWin64) {
309 if (HasSSE)
310 return HasEGPR ? CSR_Win64_APX_RegCall_SaveList
311 : CSR_Win64_RegCall_SaveList;
312 return CSR_Win64_RegCall_NoSSE_SaveList;
313 }
314 return HasSSE ? CSR_SysV64_RegCall_SaveList
315 : CSR_SysV64_RegCall_NoSSE_SaveList;
316 }
317 return HasSSE ? CSR_32_RegCall_SaveList : CSR_32_RegCall_NoSSE_SaveList;
318 case CallingConv::CFGuard_Check:
319 assert(!Is64Bit && "CFGuard check mechanism only used on 32-bit X86");
320 return HasSSE ? CSR_Win32_CFGuard_Check_SaveList
321 : CSR_Win32_CFGuard_Check_NoSSE_SaveList;
322 case CallingConv::Cold:
323 if (Is64Bit)
324 return CSR_64_MostRegs_SaveList;
325 break;
326 case CallingConv::Win64:
327 if (HasSSE)
328 return HasEGPR ? CSR_Win64_APX_SaveList : CSR_Win64_SaveList;
329 return CSR_Win64_NoSSE_SaveList;
330 case CallingConv::SwiftTail:
331 if (!Is64Bit)
332 return CSR_32_SaveList;
333 if (IsWin64)
334 return HasEGPR ? CSR_Win64_APX_SwiftTail_SaveList
335 : CSR_Win64_SwiftTail_SaveList;
336 return CSR_64_SwiftTail_SaveList;
337 case CallingConv::X86_64_SysV:
338 if (CallsEHReturn)
339 return CSR_64EHRet_SaveList;
340 return CSR_64_SaveList;
341 case CallingConv::X86_INTR:
342 if (Is64Bit) {
343 if (HasAVX512)
344 return CSR_64_AllRegs_AVX512_SaveList;
345 if (HasAVX)
346 return CSR_64_AllRegs_AVX_SaveList;
347 if (HasSSE)
348 return CSR_64_AllRegs_SaveList;
349 return CSR_64_AllRegs_NoSSE_SaveList;
350 }
351 if (HasAVX512)
352 return CSR_32_AllRegs_AVX512_SaveList;
353 if (HasAVX)
354 return CSR_32_AllRegs_AVX_SaveList;
355 if (HasSSE)
356 return CSR_32_AllRegs_SSE_SaveList;
357 return CSR_32_AllRegs_SaveList;
358 default:
359 break;
360 }
361
362 if (Is64Bit) {
363 bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
364 F.getAttributes().hasAttrSomewhere(Kind: Attribute::SwiftError);
365 if (IsSwiftCC) {
366 if (IsWin64)
367 return HasEGPR ? CSR_Win64_APX_SwiftError_SaveList
368 : CSR_Win64_SwiftError_SaveList;
369 return CSR_64_SwiftError_SaveList;
370 }
371
372 if (IsWin64 || IsUEFI64) {
373 if (HasSSE)
374 return HasEGPR ? CSR_Win64_APX_SaveList : CSR_Win64_SaveList;
375 return CSR_Win64_NoSSE_SaveList;
376 }
377 if (CallsEHReturn)
378 return CSR_64EHRet_SaveList;
379 return CSR_64_SaveList;
380 }
381
382 return CallsEHReturn ? CSR_32EHRet_SaveList : CSR_32_SaveList;
383}
384
385const MCPhysReg *
386X86RegisterInfo::getIPRACSRegs(const MachineFunction *MF) const {
387 return Is64Bit ? CSR_IPRA_64_SaveList : CSR_IPRA_32_SaveList;
388}
389
390const MCPhysReg *X86RegisterInfo::getCalleeSavedRegsViaCopy(
391 const MachineFunction *MF) const {
392 assert(MF && "Invalid MachineFunction pointer.");
393 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
394 MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR())
395 return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
396 return nullptr;
397}
398
399const uint32_t *
400X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
401 CallingConv::ID CC) const {
402 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
403 bool HasSSE = Subtarget.hasSSE1();
404 bool HasAVX = Subtarget.hasAVX();
405 bool HasAVX512 = Subtarget.hasAVX512();
406 bool HasEGPR = Subtarget.hasEGPR();
407
408 switch (CC) {
409 case CallingConv::GHC:
410 case CallingConv::HiPE:
411 return CSR_NoRegs_RegMask;
412 case CallingConv::AnyReg:
413 if (HasAVX)
414 return CSR_64_AllRegs_AVX_RegMask;
415 return CSR_64_AllRegs_RegMask;
416 case CallingConv::PreserveMost:
417 if (IsWin64)
418 return HasEGPR ? CSR_Win64_APX_RT_MostRegs_RegMask
419 : CSR_Win64_RT_MostRegs_RegMask;
420 return CSR_64_RT_MostRegs_RegMask;
421 case CallingConv::PreserveAll:
422 if (HasAVX)
423 return CSR_64_RT_AllRegs_AVX_RegMask;
424 return CSR_64_RT_AllRegs_RegMask;
425 case CallingConv::PreserveNone:
426 return CSR_64_NoneRegs_RegMask;
427 case CallingConv::CXX_FAST_TLS:
428 if (Is64Bit)
429 return CSR_64_TLS_Darwin_RegMask;
430 break;
431 case CallingConv::Intel_OCL_BI: {
432 if (HasAVX512 && IsWin64)
433 return HasEGPR ? CSR_Win64_APX_Intel_OCL_BI_AVX512_RegMask
434 : CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
435 if (HasAVX512 && Is64Bit)
436 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
437 if (HasAVX && IsWin64)
438 return HasEGPR ? CSR_Win64_APX_Intel_OCL_BI_AVX_RegMask
439 : CSR_Win64_Intel_OCL_BI_AVX_RegMask;
440 if (HasAVX && Is64Bit)
441 return CSR_64_Intel_OCL_BI_AVX_RegMask;
442 if (!HasAVX && !IsWin64 && Is64Bit)
443 return CSR_64_Intel_OCL_BI_RegMask;
444 break;
445 }
446 case CallingConv::X86_RegCall:
447 if (Is64Bit) {
448 if (IsWin64) {
449 if (HasSSE)
450 return HasEGPR ? CSR_Win64_APX_RegCall_RegMask
451 : CSR_Win64_RegCall_RegMask;
452 return CSR_Win64_RegCall_NoSSE_RegMask;
453 }
454 return HasSSE ? CSR_SysV64_RegCall_RegMask
455 : CSR_SysV64_RegCall_NoSSE_RegMask;
456 }
457 return HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask;
458 case CallingConv::CFGuard_Check:
459 if (Is64Bit) {
460 if (HasSSE)
461 return HasEGPR ? CSR_Win64_APX_CFGuard_Check_RegMask
462 : CSR_Win64_CFGuard_Check_RegMask;
463 return CSR_Win64_CFGuard_Check_NoSSE_RegMask;
464 }
465 return HasSSE ? CSR_Win32_CFGuard_Check_RegMask
466 : CSR_Win32_CFGuard_Check_NoSSE_RegMask;
467 case CallingConv::Cold:
468 if (Is64Bit)
469 return CSR_64_MostRegs_RegMask;
470 break;
471 case CallingConv::Win64:
472 return HasEGPR ? CSR_Win64_APX_RegMask : CSR_Win64_RegMask;
473 case CallingConv::SwiftTail:
474 if (!Is64Bit)
475 return CSR_32_RegMask;
476 if (IsWin64)
477 return HasEGPR ? CSR_Win64_APX_SwiftTail_RegMask
478 : CSR_Win64_SwiftTail_RegMask;
479 return CSR_64_SwiftTail_RegMask;
480 case CallingConv::X86_64_SysV:
481 return CSR_64_RegMask;
482 case CallingConv::X86_INTR:
483 if (Is64Bit) {
484 if (HasAVX512)
485 return CSR_64_AllRegs_AVX512_RegMask;
486 if (HasAVX)
487 return CSR_64_AllRegs_AVX_RegMask;
488 if (HasSSE)
489 return CSR_64_AllRegs_RegMask;
490 return CSR_64_AllRegs_NoSSE_RegMask;
491 }
492 if (HasAVX512)
493 return CSR_32_AllRegs_AVX512_RegMask;
494 if (HasAVX)
495 return CSR_32_AllRegs_AVX_RegMask;
496 if (HasSSE)
497 return CSR_32_AllRegs_SSE_RegMask;
498 return CSR_32_AllRegs_RegMask;
499 default:
500 break;
501 }
502
503 // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
504 // callsEHReturn().
505 if (Is64Bit) {
506 const Function &F = MF.getFunction();
507 bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
508 F.getAttributes().hasAttrSomewhere(Kind: Attribute::SwiftError);
509 if (IsSwiftCC) {
510 if (IsWin64)
511 return HasEGPR ? CSR_Win64_APX_SwiftError_RegMask
512 : CSR_Win64_SwiftError_RegMask;
513 return CSR_64_SwiftError_RegMask;
514 }
515
516 if (IsWin64 || IsUEFI64)
517 return HasEGPR ? CSR_Win64_APX_RegMask : CSR_Win64_RegMask;
518 return CSR_64_RegMask;
519 }
520
521 return CSR_32_RegMask;
522}
523
524const uint32_t*
525X86RegisterInfo::getNoPreservedMask() const {
526 return CSR_NoRegs_RegMask;
527}
528
529const uint32_t *X86RegisterInfo::getDarwinTLSCallPreservedMask() const {
530 return CSR_64_TLS_Darwin_RegMask;
531}
532
533BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
534 BitVector Reserved(getNumRegs());
535 const X86FrameLowering *TFI = getFrameLowering(MF);
536
537 // Set the floating point control register as reserved.
538 Reserved.set(X86::FPCW);
539
540 // Set the floating point status register as reserved.
541 Reserved.set(X86::FPSW);
542
543 // Set the SIMD floating point control register as reserved.
544 Reserved.set(X86::MXCSR);
545
546 // Set the stack-pointer register and its aliases as reserved.
547 for (const MCPhysReg &SubReg : subregs_inclusive(Reg: X86::RSP))
548 Reserved.set(SubReg);
549
550 // Set the Shadow Stack Pointer as reserved.
551 Reserved.set(X86::SSP);
552
553 auto &ST = MF.getSubtarget<X86Subtarget>();
554 if (ST.hasUserReservedRegisters()) {
555 if (ST.is64Bit()) {
556 // Set r# as reserved register if user required.
557 for (unsigned Reg = X86::R8; Reg <= X86::R15; ++Reg)
558 if (ST.isRegisterReservedByUser(i: Reg))
559 for (const MCPhysReg &SubReg : subregs_inclusive(Reg))
560 Reserved.set(SubReg);
561 if (ST.hasEGPR())
562 for (unsigned Reg = X86::R16; Reg <= X86::R31; ++Reg)
563 if (ST.isRegisterReservedByUser(i: Reg))
564 for (const MCPhysReg &SubReg : subregs_inclusive(Reg))
565 Reserved.set(SubReg);
566 } else {
567 if (ST.isRegisterReservedByUser(i: X86::EDI))
568 for (const MCPhysReg &SubReg : sub_and_superregs_inclusive(Reg: X86::EDI))
569 Reserved.set(SubReg);
570 }
571 }
572
573 // Set the instruction pointer register and its aliases as reserved.
574 for (const MCPhysReg &SubReg : subregs_inclusive(Reg: X86::RIP))
575 Reserved.set(SubReg);
576
577 // Set the frame-pointer register and its aliases as reserved if needed.
578 if (TFI->hasFP(MF) || MF.getTarget().Options.FramePointerIsReserved(MF)) {
579 if (MF.getInfo<X86MachineFunctionInfo>()->getFPClobberedByInvoke())
580 MF.getContext().reportError(
581 L: SMLoc(),
582 Msg: "Frame pointer clobbered by function invoke is not supported.");
583
584 for (const MCPhysReg &SubReg : subregs_inclusive(Reg: X86::RBP))
585 Reserved.set(SubReg);
586 }
587
588 // Set the base-pointer register and its aliases as reserved if needed.
589 if (hasBasePointer(MF)) {
590 if (MF.getInfo<X86MachineFunctionInfo>()->getBPClobberedByInvoke())
591 MF.getContext().reportError(L: SMLoc(),
592 Msg: "Stack realignment in presence of dynamic "
593 "allocas is not supported with "
594 "this calling convention.");
595
596 Register BasePtr = getX86SubSuperRegister(Reg: getBaseRegister(), Size: 64);
597 for (const MCPhysReg &SubReg : subregs_inclusive(Reg: BasePtr))
598 Reserved.set(SubReg);
599 }
600
601 // Mark the segment registers as reserved.
602 Reserved.set(X86::CS);
603 Reserved.set(X86::SS);
604 Reserved.set(X86::DS);
605 Reserved.set(X86::ES);
606 Reserved.set(X86::FS);
607 Reserved.set(X86::GS);
608
609 // Mark the floating point stack registers as reserved.
610 for (unsigned n = 0; n != 8; ++n)
611 Reserved.set(X86::ST0 + n);
612
613 // Reserve the registers that only exist in 64-bit mode.
614 if (!Is64Bit) {
615 // These 8-bit registers are part of the x86-64 extension even though their
616 // super-registers are old 32-bits.
617 Reserved.set(X86::SIL);
618 Reserved.set(X86::DIL);
619 Reserved.set(X86::BPL);
620 Reserved.set(X86::SPL);
621 Reserved.set(X86::SIH);
622 Reserved.set(X86::DIH);
623 Reserved.set(X86::BPH);
624 Reserved.set(X86::SPH);
625
626 for (unsigned n = 0; n != 8; ++n) {
627 // R8, R9, ...
628 for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
629 Reserved.set(*AI);
630
631 // XMM8, XMM9, ...
632 for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
633 Reserved.set(*AI);
634 }
635 }
636 if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
637 for (unsigned n = 0; n != 16; ++n) {
638 for (MCRegAliasIterator AI(X86::XMM16 + n, this, true); AI.isValid();
639 ++AI)
640 Reserved.set(*AI);
641 }
642 }
643
644 // Reserve the extended general purpose registers.
645 if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasEGPR())
646 Reserved.set(I: X86::R16, E: X86::R31WH + 1);
647
648 // Due to specifics of setjmp unwinding in Win64 APX ABI, the unwinder
649 // cannot restore R30/R31. Reserve them to prevent register allocation.
650 // https://learn.microsoft.com/en-us/cpp/build/x64-calling-convention#setjmplongjmp
651 if (MF.exposesReturnsTwice() && ST.isTargetWin64()) {
652 unsigned NumReservedCSRs = 0;
653 for (unsigned Reg = X86::R16; Reg <= X86::R31; ++Reg)
654 if (isCalleeSavedPhysReg(PhysReg: Reg, MF)) {
655 ++NumReservedCSRs;
656 for (const MCPhysReg &SubReg : subregs_inclusive(Reg))
657 Reserved.set(SubReg);
658 }
659 if (NumReservedCSRs && MF.size() > SetjmpCSRWarningThreshold &&
660 !MF.getRegInfo().reservedRegsFrozen()) {
661 MF.getContext().reportWarning(
662 L: SMLoc(), Msg: Twine(NumReservedCSRs) +
663 " callee-saved register(s) reserved due to setjmp in '" +
664 MF.getName() +
665 "'; this may impact performance in large functions");
666 }
667 }
668
669 if (MF.getFunction().getCallingConv() == CallingConv::GRAAL) {
670 for (MCRegAliasIterator AI(X86::R14, this, true); AI.isValid(); ++AI)
671 Reserved.set(*AI);
672 for (MCRegAliasIterator AI(X86::R15, this, true); AI.isValid(); ++AI)
673 Reserved.set(*AI);
674 }
675
676 assert(checkAllSuperRegsMarked(Reserved,
677 {X86::SIL, X86::DIL, X86::BPL, X86::SPL,
678 X86::SIH, X86::DIH, X86::BPH, X86::SPH}));
679 return Reserved;
680}
681
682unsigned X86RegisterInfo::getNumSupportedRegs(const MachineFunction &MF) const {
683 // All existing Intel CPUs that support AMX support AVX512 and all existing
684 // Intel CPUs that support APX support AMX. AVX512 implies AVX.
685 //
686 // We enumerate the registers in X86GenRegisterInfo.inc in this order:
687 //
688 // Registers before AVX512,
689 // AVX512 registers (X/YMM16-31, ZMM0-31, K registers)
690 // AMX registers (TMM)
691 // APX registers (R16-R31)
692 //
693 // and try to return the minimum number of registers supported by the target.
694 static_assert((X86::R15WH + 1 == X86::YMM0) && (X86::YMM15 + 1 == X86::K0) &&
695 (X86::K6_K7 + 1 == X86::TMMCFG) &&
696 (X86::TMM7 + 1 == X86::R16) &&
697 (X86::R31WH + 1 == X86::NUM_TARGET_REGS),
698 "Register number may be incorrect");
699
700 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
701 if (ST.hasEGPR())
702 return X86::NUM_TARGET_REGS;
703 if (ST.hasAMXTILE())
704 return X86::TMM7 + 1;
705 if (ST.hasAVX512())
706 return X86::K6_K7 + 1;
707 if (ST.hasAVX())
708 return X86::YMM15 + 1;
709 return X86::R15WH + 1;
710}
711
712bool X86RegisterInfo::isArgumentRegister(const MachineFunction &MF,
713 MCRegister Reg) const {
714 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
715 const TargetRegisterInfo &TRI = *ST.getRegisterInfo();
716 auto IsSubReg = [&](MCRegister RegA, MCRegister RegB) {
717 return TRI.isSuperOrSubRegisterEq(RegA, RegB);
718 };
719
720 if (!ST.is64Bit())
721 return llvm::any_of(
722 Range: SmallVector<MCRegister>{X86::EAX, X86::ECX, X86::EDX},
723 P: [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); }) ||
724 (ST.hasMMX() && X86::VR64RegClass.contains(Reg));
725
726 CallingConv::ID CC = MF.getFunction().getCallingConv();
727
728 if (CC == CallingConv::X86_64_SysV && IsSubReg(X86::RAX, Reg))
729 return true;
730
731 if (llvm::any_of(
732 Range: SmallVector<MCRegister>{X86::RDX, X86::RCX, X86::R8, X86::R9},
733 P: [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); }))
734 return true;
735
736 if (CC != CallingConv::Win64 &&
737 llvm::any_of(Range: SmallVector<MCRegister>{X86::RDI, X86::RSI},
738 P: [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); }))
739 return true;
740
741 if (ST.hasSSE1() &&
742 llvm::any_of(Range: SmallVector<MCRegister>{X86::XMM0, X86::XMM1, X86::XMM2,
743 X86::XMM3, X86::XMM4, X86::XMM5,
744 X86::XMM6, X86::XMM7},
745 P: [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); }))
746 return true;
747
748 return X86GenRegisterInfo::isArgumentRegister(MF, PhysReg: Reg);
749}
750
751bool X86RegisterInfo::isFixedRegister(const MachineFunction &MF,
752 MCRegister PhysReg) const {
753 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
754 const TargetRegisterInfo &TRI = *ST.getRegisterInfo();
755
756 // Stack pointer.
757 if (TRI.isSuperOrSubRegisterEq(RegA: X86::RSP, RegB: PhysReg))
758 return true;
759
760 // Don't use the frame pointer if it's being used.
761 const X86FrameLowering &TFI = *getFrameLowering(MF);
762 if (TFI.hasFP(MF) && TRI.isSuperOrSubRegisterEq(RegA: X86::RBP, RegB: PhysReg))
763 return true;
764
765 return X86GenRegisterInfo::isFixedRegister(MF, PhysReg);
766}
767
768bool X86RegisterInfo::isTileRegisterClass(const TargetRegisterClass *RC) const {
769 return RC->getID() == X86::TILERegClassID;
770}
771
772void X86RegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
773 // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
774 // because the calling convention defines the EFLAGS register as NOT
775 // preserved.
776 //
777 // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
778 // an assert to track this and clear the register afterwards to avoid
779 // unnecessary crashes during release builds.
780 assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
781 "EFLAGS are not live-out from a patchpoint.");
782
783 // Also clean other registers that don't need preserving (IP).
784 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
785 Mask[Reg / 32] &= ~(1U << (Reg % 32));
786}
787
788//===----------------------------------------------------------------------===//
789// Stack Frame Processing methods
790//===----------------------------------------------------------------------===//
791
792static bool CantUseSP(const MachineFrameInfo &MFI) {
793 return MFI.hasVarSizedObjects() || MFI.hasOpaqueSPAdjustment();
794}
795
796bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
797 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
798 // We have a virtual register to reference argument, and don't need base
799 // pointer.
800 if (X86FI->getStackPtrSaveMI() != nullptr)
801 return false;
802
803 if (X86FI->hasPreallocatedCall())
804 return true;
805
806 const MachineFrameInfo &MFI = MF.getFrameInfo();
807
808 if (!EnableBasePointer)
809 return false;
810
811 // When we need stack realignment, we can't address the stack from the frame
812 // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
813 // can't address variables from the stack pointer. MS inline asm can
814 // reference locals while also adjusting the stack pointer. When we can't
815 // use both the SP and the FP, we need a separate base pointer register.
816 bool CantUseFP = hasStackRealignment(MF);
817 return CantUseFP && CantUseSP(MFI);
818}
819
820bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
821 if (!TargetRegisterInfo::canRealignStack(MF))
822 return false;
823
824 const MachineFrameInfo &MFI = MF.getFrameInfo();
825 const MachineRegisterInfo *MRI = &MF.getRegInfo();
826
827 // Stack realignment requires a frame pointer. If we already started
828 // register allocation with frame pointer elimination, it is too late now.
829 if (!MRI->canReserveReg(PhysReg: FramePtr))
830 return false;
831
832 // If a base pointer is necessary. Check that it isn't too late to reserve
833 // it.
834 if (CantUseSP(MFI))
835 return MRI->canReserveReg(PhysReg: BasePtr);
836 return true;
837}
838
839bool X86RegisterInfo::shouldRealignStack(const MachineFunction &MF) const {
840 if (TargetRegisterInfo::shouldRealignStack(MF))
841 return true;
842
843 return !Is64Bit && MF.getFunction().getCallingConv() == CallingConv::X86_INTR;
844}
845
846// tryOptimizeLEAtoMOV - helper function that tries to replace a LEA instruction
847// of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx'.
848// TODO: In this case we should be really trying first to entirely eliminate
849// this instruction which is a plain copy.
850static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II) {
851 MachineInstr &MI = *II;
852 unsigned Opc = II->getOpcode();
853 // Check if this is a LEA of the form 'lea (%esp), %ebx'
854 if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
855 MI.getOperand(i: 2).getImm() != 1 ||
856 MI.getOperand(i: 3).getReg() != X86::NoRegister ||
857 MI.getOperand(i: 4).getImm() != 0 ||
858 MI.getOperand(i: 5).getReg() != X86::NoRegister)
859 return false;
860 Register BasePtr = MI.getOperand(i: 1).getReg();
861 // In X32 mode, ensure the base-pointer is a 32-bit operand, so the LEA will
862 // be replaced with a 32-bit operand MOV which will zero extend the upper
863 // 32-bits of the super register.
864 if (Opc == X86::LEA64_32r)
865 BasePtr = getX86SubSuperRegister(Reg: BasePtr, Size: 32);
866 Register NewDestReg = MI.getOperand(i: 0).getReg();
867 const X86InstrInfo *TII =
868 MI.getParent()->getParent()->getSubtarget<X86Subtarget>().getInstrInfo();
869 TII->copyPhysReg(MBB&: *MI.getParent(), MI: II, DL: MI.getDebugLoc(), DestReg: NewDestReg, SrcReg: BasePtr,
870 KillSrc: MI.getOperand(i: 1).isKill());
871 MI.eraseFromParent();
872 return true;
873}
874
875static bool isFuncletReturnInstr(MachineInstr &MI) {
876 switch (MI.getOpcode()) {
877 case X86::CATCHRET:
878 case X86::CLEANUPRET:
879 return true;
880 default:
881 return false;
882 }
883 llvm_unreachable("impossible");
884}
885
886void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
887 unsigned FIOperandNum,
888 Register BaseReg,
889 int FIOffset) const {
890 MachineInstr &MI = *II;
891 unsigned Opc = MI.getOpcode();
892 if (Opc == TargetOpcode::LOCAL_ESCAPE) {
893 MachineOperand &FI = MI.getOperand(i: FIOperandNum);
894 FI.ChangeToImmediate(ImmVal: FIOffset);
895 return;
896 }
897
898 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: BaseReg, isDef: false);
899
900 // The frame index format for stackmaps and patchpoints is different from the
901 // X86 format. It only has a FI and an offset.
902 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
903 assert(BasePtr == FramePtr && "Expected the FP as base register");
904 int64_t Offset = MI.getOperand(i: FIOperandNum + 1).getImm() + FIOffset;
905 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Offset);
906 return;
907 }
908
909 if (MI.getOperand(i: FIOperandNum + 3).isImm()) {
910 // Offset is a 32-bit integer.
911 int Imm = (int)(MI.getOperand(i: FIOperandNum + 3).getImm());
912 int Offset = FIOffset + Imm;
913 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
914 "Requesting 64-bit offset in 32-bit immediate!");
915 if (Offset != 0)
916 MI.getOperand(i: FIOperandNum + 3).ChangeToImmediate(ImmVal: Offset);
917 } else {
918 // Offset is symbolic. This is extremely rare.
919 uint64_t Offset =
920 FIOffset + (uint64_t)MI.getOperand(i: FIOperandNum + 3).getOffset();
921 MI.getOperand(i: FIOperandNum + 3).setOffset(Offset);
922 }
923}
924
925bool
926X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
927 int SPAdj, unsigned FIOperandNum,
928 RegScavenger *RS) const {
929 MachineInstr &MI = *II;
930 MachineBasicBlock &MBB = *MI.getParent();
931 MachineFunction &MF = *MBB.getParent();
932 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
933 bool IsEHFuncletEpilogue = MBBI == MBB.end() ? false
934 : isFuncletReturnInstr(MI&: *MBBI);
935 const X86FrameLowering *TFI = getFrameLowering(MF);
936 int FrameIndex = MI.getOperand(i: FIOperandNum).getIndex();
937
938 // Determine base register and offset.
939 int64_t FIOffset;
940 Register BasePtr;
941 if (MI.isReturn()) {
942 assert((!hasStackRealignment(MF) ||
943 MF.getFrameInfo().isFixedObjectIndex(FrameIndex)) &&
944 "Return instruction can only reference SP relative frame objects");
945 FIOffset =
946 TFI->getFrameIndexReferenceSP(MF, FI: FrameIndex, SPReg&: BasePtr, Adjustment: 0).getFixed();
947 } else if (TFI->Is64Bit && (MBB.isEHFuncletEntry() || IsEHFuncletEpilogue)) {
948 FIOffset = TFI->getWin64EHFrameIndexRef(MF, FI: FrameIndex, SPReg&: BasePtr);
949 } else {
950 FIOffset = TFI->getFrameIndexReference(MF, FI: FrameIndex, FrameReg&: BasePtr).getFixed();
951 }
952
953 // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
954 // simple FP case, and doesn't work with stack realignment. On 32-bit, the
955 // offset is from the traditional base pointer location. On 64-bit, the
956 // offset is from the SP at the end of the prologue, not the FP location. This
957 // matches the behavior of llvm.frameaddress.
958 unsigned Opc = MI.getOpcode();
959 if (Opc == TargetOpcode::LOCAL_ESCAPE) {
960 MachineOperand &FI = MI.getOperand(i: FIOperandNum);
961 FI.ChangeToImmediate(ImmVal: FIOffset);
962 return false;
963 }
964
965 // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
966 // register as source operand, semantic is the same and destination is
967 // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
968 // Don't change BasePtr since it is used later for stack adjustment.
969 Register MachineBasePtr = BasePtr;
970 if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(Reg: BasePtr))
971 MachineBasePtr = getX86SubSuperRegister(Reg: BasePtr, Size: 64);
972
973 // This must be part of a four operand memory reference. Replace the
974 // FrameIndex with base register. Add an offset to the offset.
975 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: MachineBasePtr, isDef: false);
976
977 if (BasePtr == StackPtr)
978 FIOffset += SPAdj;
979
980 // The frame index format for stackmaps and patchpoints is different from the
981 // X86 format. It only has a FI and an offset.
982 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
983 assert(BasePtr == FramePtr && "Expected the FP as base register");
984 int64_t Offset = MI.getOperand(i: FIOperandNum + 1).getImm() + FIOffset;
985 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Offset);
986 return false;
987 }
988
989 if (MI.getOperand(i: FIOperandNum+3).isImm()) {
990 const X86InstrInfo *TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
991 const DebugLoc &DL = MI.getDebugLoc();
992 int64_t Imm = MI.getOperand(i: FIOperandNum + 3).getImm();
993 int64_t Offset = FIOffset + Imm;
994 bool FitsIn32Bits = isInt<32>(x: Offset);
995 // If the offset will not fit in a 32-bit displacement, then for 64-bit
996 // targets, scavenge a register to hold it. Otherwise...
997 if (Is64Bit && !FitsIn32Bits) {
998 assert(RS && "RegisterScavenger was NULL");
999
1000 RS->enterBasicBlockEnd(MBB);
1001 RS->backward(I: std::next(x: II));
1002
1003 Register ScratchReg = RS->scavengeRegisterBackwards(
1004 RC: X86::GR64RegClass, To: II, /*RestoreAfter=*/false, /*SPAdj=*/0,
1005 /*AllowSpill=*/true);
1006 assert(ScratchReg != 0 && "scratch reg was 0");
1007 RS->setRegUsed(Reg: ScratchReg);
1008
1009 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: X86::MOV64ri), DestReg: ScratchReg).addImm(Val: Offset);
1010
1011 MI.getOperand(i: FIOperandNum + 3).setImm(0);
1012 MI.getOperand(i: FIOperandNum + 2).setReg(ScratchReg);
1013
1014 return false;
1015 }
1016
1017 // ... for 32-bit targets, this is a bug!
1018 if (!Is64Bit && !FitsIn32Bits) {
1019 MI.emitGenericError(ErrMsg: "64-bit offset calculated but target is 32-bit");
1020 // Trap so that the instruction verification pass does not fail if run.
1021 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: X86::TRAP));
1022 return false;
1023 }
1024
1025 if (Offset != 0 || !tryOptimizeLEAtoMOV(II))
1026 MI.getOperand(i: FIOperandNum + 3).ChangeToImmediate(ImmVal: Offset);
1027 } else {
1028 // Offset is symbolic. This is extremely rare.
1029 uint64_t Offset = FIOffset +
1030 (uint64_t)MI.getOperand(i: FIOperandNum+3).getOffset();
1031 MI.getOperand(i: FIOperandNum + 3).setOffset(Offset);
1032 }
1033 return false;
1034}
1035
1036unsigned X86RegisterInfo::findDeadCallerSavedReg(
1037 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI) const {
1038 const MachineFunction *MF = MBB.getParent();
1039 const MachineRegisterInfo &MRI = MF->getRegInfo();
1040 if (MF->callsEHReturn())
1041 return 0;
1042
1043 if (MBBI == MBB.end())
1044 return 0;
1045
1046 switch (MBBI->getOpcode()) {
1047 default:
1048 return 0;
1049 case TargetOpcode::PATCHABLE_RET:
1050 case X86::RET:
1051 case X86::RET32:
1052 case X86::RET64:
1053 case X86::RETI32:
1054 case X86::RETI64:
1055 case X86::TCRETURNdi:
1056 case X86::TCRETURNri:
1057 case X86::TCRETURN_WIN64ri:
1058 case X86::TCRETURN_HIPE32ri:
1059 case X86::TCRETURNmi:
1060 case X86::TCRETURNdi64:
1061 case X86::TCRETURNri64:
1062 case X86::TCRETURNri64_ImpCall:
1063 case X86::TCRETURNmi64:
1064 case X86::TCRETURN_WINmi64:
1065 case X86::EH_RETURN:
1066 case X86::EH_RETURN64: {
1067 LiveRegUnits LRU(*this);
1068 LRU.addLiveOuts(MBB);
1069 LRU.stepBackward(MI: *MBBI);
1070
1071 const TargetRegisterClass &RC =
1072 Is64Bit ? X86::GR64_NOSPRegClass : X86::GR32_NOSPRegClass;
1073 for (MCRegister Reg : RC) {
1074 if (LRU.available(Reg) && !MRI.isReserved(PhysReg: Reg))
1075 return Reg;
1076 }
1077 }
1078 }
1079
1080 return 0;
1081}
1082
1083Register X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1084 const X86FrameLowering *TFI = getFrameLowering(MF);
1085 return TFI->hasFP(MF) ? FramePtr : StackPtr;
1086}
1087
1088Register
1089X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const {
1090 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
1091 Register FrameReg = getFrameRegister(MF);
1092 if (Subtarget.isTarget64BitILP32())
1093 FrameReg = getX86SubSuperRegister(Reg: FrameReg, Size: 32);
1094 return FrameReg;
1095}
1096
1097Register
1098X86RegisterInfo::getPtrSizedStackRegister(const MachineFunction &MF) const {
1099 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
1100 Register StackReg = getStackRegister();
1101 if (Subtarget.isTarget64BitILP32())
1102 StackReg = getX86SubSuperRegister(Reg: StackReg, Size: 32);
1103 return StackReg;
1104}
1105
1106static ShapeT getTileShape(Register VirtReg, VirtRegMap *VRM,
1107 const MachineRegisterInfo *MRI) {
1108 if (VRM->hasShape(virtReg: VirtReg))
1109 return VRM->getShape(virtReg: VirtReg);
1110
1111 const MachineOperand &Def = *MRI->def_begin(RegNo: VirtReg);
1112 MachineInstr *MI = const_cast<MachineInstr *>(Def.getParent());
1113 unsigned OpCode = MI->getOpcode();
1114 switch (OpCode) {
1115 default:
1116 llvm_unreachable("Unexpected machine instruction on tile register!");
1117 break;
1118 case X86::COPY: {
1119 Register SrcReg = MI->getOperand(i: 1).getReg();
1120 ShapeT Shape = getTileShape(VirtReg: SrcReg, VRM, MRI);
1121 VRM->assignVirt2Shape(virtReg: VirtReg, shape: Shape);
1122 return Shape;
1123 }
1124 // We only collect the tile shape that is defined.
1125 case X86::PTILELOADDV:
1126 case X86::PTILELOADDT1V:
1127 case X86::PTDPBSSDV:
1128 case X86::PTDPBSUDV:
1129 case X86::PTDPBUSDV:
1130 case X86::PTDPBUUDV:
1131 case X86::PTILEZEROV:
1132 case X86::PTDPBF16PSV:
1133 case X86::PTDPFP16PSV:
1134 case X86::PTCMMIMFP16PSV:
1135 case X86::PTCMMRLFP16PSV:
1136 case X86::PTILELOADDRSV:
1137 case X86::PTILELOADDRST1V:
1138 case X86::PTMMULTF32PSV:
1139 case X86::PTDPBF8PSV:
1140 case X86::PTDPBHF8PSV:
1141 case X86::PTDPHBF8PSV:
1142 case X86::PTDPHF8PSV: {
1143 MachineOperand &MO1 = MI->getOperand(i: 1);
1144 MachineOperand &MO2 = MI->getOperand(i: 2);
1145 ShapeT Shape(&MO1, &MO2, MRI);
1146 VRM->assignVirt2Shape(virtReg: VirtReg, shape: Shape);
1147 return Shape;
1148 }
1149 }
1150}
1151
1152bool X86RegisterInfo::getRegAllocationHints(Register VirtReg,
1153 ArrayRef<MCPhysReg> Order,
1154 SmallVectorImpl<MCPhysReg> &Hints,
1155 const MachineFunction &MF,
1156 const VirtRegMap *VRM,
1157 const LiveRegMatrix *Matrix) const {
1158 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1159 const TargetRegisterClass &RC = *MRI->getRegClass(Reg: VirtReg);
1160 bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
1161 VirtReg, Order, Hints, MF, VRM, Matrix);
1162 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
1163 const TargetRegisterInfo &TRI = *ST.getRegisterInfo();
1164
1165 unsigned ID = RC.getID();
1166
1167 if (!VRM)
1168 return BaseImplRetVal;
1169
1170 if (ID != X86::TILERegClassID) {
1171 if (DisableRegAllocNDDHints || !ST.hasNDD() ||
1172 !TRI.isGeneralPurposeRegisterClass(RC: &RC))
1173 return BaseImplRetVal;
1174
1175 // Add any two address hints after any copy hints.
1176 SmallSet<unsigned, 4> TwoAddrHints;
1177
1178 auto TryAddNDDHint = [&](const MachineOperand &MO) {
1179 Register Reg = MO.getReg();
1180 Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(virtReg: Reg));
1181 if (PhysReg && !MRI->isReserved(PhysReg) && !is_contained(Range&: Hints, Element: PhysReg))
1182 TwoAddrHints.insert(V: PhysReg);
1183 };
1184
1185 // NDD instructions is compressible when Op0 is allocated to the same
1186 // physic register as Op1 (or Op2 if it's commutable).
1187 for (auto &MO : MRI->reg_nodbg_operands(Reg: VirtReg)) {
1188 const MachineInstr &MI = *MO.getParent();
1189 if (!X86::getNonNDVariant(Opc: MI.getOpcode()))
1190 continue;
1191 unsigned OpIdx = MI.getOperandNo(I: &MO);
1192 if (OpIdx == 0) {
1193 assert(MI.getOperand(1).isReg());
1194 TryAddNDDHint(MI.getOperand(i: 1));
1195 if (MI.isCommutable()) {
1196 assert(MI.getOperand(2).isReg());
1197 TryAddNDDHint(MI.getOperand(i: 2));
1198 }
1199 } else if (OpIdx == 1) {
1200 TryAddNDDHint(MI.getOperand(i: 0));
1201 } else if (MI.isCommutable() && OpIdx == 2) {
1202 TryAddNDDHint(MI.getOperand(i: 0));
1203 }
1204 }
1205
1206 for (MCPhysReg OrderReg : Order)
1207 if (TwoAddrHints.count(V: OrderReg))
1208 Hints.push_back(Elt: OrderReg);
1209
1210 return BaseImplRetVal;
1211 }
1212
1213 ShapeT VirtShape = getTileShape(VirtReg, VRM: const_cast<VirtRegMap *>(VRM), MRI);
1214 auto AddHint = [&](MCPhysReg PhysReg) {
1215 Register VReg = Matrix->getOneVReg(PhysReg);
1216 if (VReg == MCRegister::NoRegister) { // Not allocated yet
1217 Hints.push_back(Elt: PhysReg);
1218 return;
1219 }
1220 ShapeT PhysShape = getTileShape(VirtReg: VReg, VRM: const_cast<VirtRegMap *>(VRM), MRI);
1221 if (PhysShape == VirtShape)
1222 Hints.push_back(Elt: PhysReg);
1223 };
1224
1225 SmallSet<MCPhysReg, 4> CopyHints(llvm::from_range, Hints);
1226 Hints.clear();
1227 for (auto Hint : CopyHints) {
1228 if (RC.contains(Reg: Hint) && !MRI->isReserved(PhysReg: Hint))
1229 AddHint(Hint);
1230 }
1231 for (MCPhysReg PhysReg : Order) {
1232 if (!CopyHints.count(V: PhysReg) && RC.contains(Reg: PhysReg) &&
1233 !MRI->isReserved(PhysReg))
1234 AddHint(PhysReg);
1235 }
1236
1237#define DEBUG_TYPE "tile-hint"
1238 LLVM_DEBUG({
1239 dbgs() << "Hints for virtual register " << format_hex(VirtReg, 8) << "\n";
1240 for (auto Hint : Hints) {
1241 dbgs() << "tmm" << Hint << ",";
1242 }
1243 dbgs() << "\n";
1244 });
1245#undef DEBUG_TYPE
1246
1247 return true;
1248}
1249
1250const TargetRegisterClass *X86RegisterInfo::constrainRegClassToNonRex2(
1251 const TargetRegisterClass *RC) const {
1252 switch (RC->getID()) {
1253 default:
1254 return RC;
1255 case X86::GR8RegClassID:
1256 return &X86::GR8_NOREX2RegClass;
1257 case X86::GR16RegClassID:
1258 return &X86::GR16_NOREX2RegClass;
1259 case X86::GR32RegClassID:
1260 return &X86::GR32_NOREX2RegClass;
1261 case X86::GR64RegClassID:
1262 return &X86::GR64_NOREX2RegClass;
1263 case X86::GR32_NOSPRegClassID:
1264 return &X86::GR32_NOREX2_NOSPRegClass;
1265 case X86::GR64_NOSPRegClassID:
1266 return &X86::GR64_NOREX2_NOSPRegClass;
1267 }
1268}
1269
1270bool X86RegisterInfo::isNonRex2RegClass(const TargetRegisterClass *RC) const {
1271 switch (RC->getID()) {
1272 default:
1273 return false;
1274 case X86::GR8_NOREX2RegClassID:
1275 case X86::GR16_NOREX2RegClassID:
1276 case X86::GR32_NOREX2RegClassID:
1277 case X86::GR64_NOREX2RegClassID:
1278 case X86::GR32_NOREX2_NOSPRegClassID:
1279 case X86::GR64_NOREX2_NOSPRegClassID:
1280 case X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID:
1281 return true;
1282 }
1283}
1284