1//===- AArch64SLSHardening.cpp - Harden Straight Line Missspeculation -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass to insert code to mitigate against side channel
10// vulnerabilities that may happen under straight line miss-speculation.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AArch64InstrInfo.h"
15#include "AArch64Subtarget.h"
16#include "llvm/ADT/StringSwitch.h"
17#include "llvm/CodeGen/IndirectThunks.h"
18#include "llvm/CodeGen/MachineBasicBlock.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
21#include "llvm/CodeGen/MachineInstr.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineOperand.h"
24#include "llvm/CodeGen/RegisterScavenging.h"
25#include "llvm/IR/DebugLoc.h"
26#include "llvm/Pass.h"
27#include "llvm/Support/ErrorHandling.h"
28#include "llvm/Support/FormatVariadic.h"
29#include "llvm/Target/TargetMachine.h"
30#include <cassert>
31#include <climits>
32#include <tuple>
33
34using namespace llvm;
35
36#define DEBUG_TYPE "aarch64-sls-hardening"
37
38#define AARCH64_SLS_HARDENING_NAME "AArch64 sls hardening pass"
39
40// Common name prefix of all thunks generated by this pass.
41//
42// The generic form is
43// __llvm_slsblr_thunk_xN for BLR thunks
44// __llvm_slsblr_thunk_(aaz|abz)_xN for BLRAAZ and BLRABZ thunks
45// __llvm_slsblr_thunk_(aa|ab)_xN_xM for BLRAA and BLRAB thunks
46static constexpr StringRef CommonNamePrefix = "__llvm_slsblr_thunk_";
47
48namespace {
49
50struct ThunkKind {
51 enum ThunkKindId {
52 ThunkBR,
53 ThunkBRAA,
54 ThunkBRAB,
55 ThunkBRAAZ,
56 ThunkBRABZ,
57 };
58
59 ThunkKindId Id;
60 StringRef NameInfix;
61 bool HasXmOperand;
62 bool NeedsPAuth;
63
64 // Opcode to perform indirect jump from inside the thunk.
65 unsigned BROpcode;
66
67 static const ThunkKind BR;
68 static const ThunkKind BRAA;
69 static const ThunkKind BRAB;
70 static const ThunkKind BRAAZ;
71 static const ThunkKind BRABZ;
72};
73
74// Set of inserted thunks.
75class ThunksSet {
76public:
77 static constexpr unsigned NumXRegisters = 32;
78
79 // Given Xn register, returns n.
80 static unsigned indexOfXReg(Register Xn);
81 // Given n, returns Xn register.
82 static Register xRegByIndex(unsigned N);
83
84 ThunksSet &operator|=(const ThunksSet &Other) {
85 BLRThunks |= Other.BLRThunks;
86 BLRAAZThunks |= Other.BLRAAZThunks;
87 BLRABZThunks |= Other.BLRABZThunks;
88 for (unsigned I = 0; I < NumXRegisters; ++I)
89 BLRAAThunks[I] |= Other.BLRAAThunks[I];
90 for (unsigned I = 0; I < NumXRegisters; ++I)
91 BLRABThunks[I] |= Other.BLRABThunks[I];
92
93 return *this;
94 }
95
96 bool get(ThunkKind::ThunkKindId Kind, Register Xn, Register Xm) {
97 reg_bitmask_t XnBit = reg_bitmask_t(1) << indexOfXReg(Xn);
98 return getBitmask(Kind, Xm) & XnBit;
99 }
100
101 void set(ThunkKind::ThunkKindId Kind, Register Xn, Register Xm) {
102 reg_bitmask_t XnBit = reg_bitmask_t(1) << indexOfXReg(Xn);
103 getBitmask(Kind, Xm) |= XnBit;
104 }
105
106private:
107 typedef uint32_t reg_bitmask_t;
108 static_assert(NumXRegisters <= sizeof(reg_bitmask_t) * CHAR_BIT,
109 "Bitmask is not wide enough to hold all Xn registers");
110
111 // Bitmasks representing operands used, with n-th bit corresponding to Xn
112 // register operand. If the instruction has a second operand (Xm), an array
113 // of bitmasks is used, indexed by m.
114 // Indexes corresponding to the forbidden x16, x17 and x30 registers are
115 // always unset, for simplicity there are no holes.
116 reg_bitmask_t BLRThunks = 0;
117 reg_bitmask_t BLRAAZThunks = 0;
118 reg_bitmask_t BLRABZThunks = 0;
119 reg_bitmask_t BLRAAThunks[NumXRegisters] = {};
120 reg_bitmask_t BLRABThunks[NumXRegisters] = {};
121
122 reg_bitmask_t &getBitmask(ThunkKind::ThunkKindId Kind, Register Xm) {
123 switch (Kind) {
124 case ThunkKind::ThunkBR:
125 return BLRThunks;
126 case ThunkKind::ThunkBRAAZ:
127 return BLRAAZThunks;
128 case ThunkKind::ThunkBRABZ:
129 return BLRABZThunks;
130 case ThunkKind::ThunkBRAA:
131 return BLRAAThunks[indexOfXReg(Xn: Xm)];
132 case ThunkKind::ThunkBRAB:
133 return BLRABThunks[indexOfXReg(Xn: Xm)];
134 }
135 llvm_unreachable("Unknown ThunkKindId enum");
136 }
137};
138
139struct SLSHardeningInserter : ThunkInserter<SLSHardeningInserter, ThunksSet> {
140public:
141 const char *getThunkPrefix() { return CommonNamePrefix.data(); }
142 bool mayUseThunk(const MachineFunction &MF) {
143 ComdatThunks &= !MF.getSubtarget<AArch64Subtarget>().hardenSlsNoComdat();
144 // We are inserting barriers aside from thunk calls, so
145 // check hardenSlsRetBr() as well.
146 return MF.getSubtarget<AArch64Subtarget>().hardenSlsBlr() ||
147 MF.getSubtarget<AArch64Subtarget>().hardenSlsRetBr();
148 }
149 ThunksSet insertThunks(MachineModuleInfo &MMI, MachineFunction &MF,
150 ThunksSet ExistingThunks);
151 void populateThunk(MachineFunction &MF);
152
153private:
154 bool ComdatThunks = true;
155
156 bool hardenReturnsAndBRs(MachineModuleInfo &MMI, MachineBasicBlock &MBB);
157 bool hardenBLRs(MachineModuleInfo &MMI, MachineBasicBlock &MBB,
158 ThunksSet &Thunks);
159
160 void convertBLRToBL(MachineModuleInfo &MMI, MachineBasicBlock &MBB,
161 MachineBasicBlock::instr_iterator MBBI,
162 ThunksSet &Thunks);
163};
164
165} // end anonymous namespace
166
167const ThunkKind ThunkKind::BR = {.Id: ThunkBR, .NameInfix: "", /*HasXmOperand=*/false,
168 /*NeedsPAuth=*/false, .BROpcode: AArch64::BR};
169const ThunkKind ThunkKind::BRAA = {.Id: ThunkBRAA, .NameInfix: "aa_", /*HasXmOperand=*/true,
170 /*NeedsPAuth=*/true, .BROpcode: AArch64::BRAA};
171const ThunkKind ThunkKind::BRAB = {.Id: ThunkBRAB, .NameInfix: "ab_", /*HasXmOperand=*/true,
172 /*NeedsPAuth=*/true, .BROpcode: AArch64::BRAB};
173const ThunkKind ThunkKind::BRAAZ = {.Id: ThunkBRAAZ, .NameInfix: "aaz_", /*HasXmOperand=*/false,
174 /*NeedsPAuth=*/true, .BROpcode: AArch64::BRAAZ};
175const ThunkKind ThunkKind::BRABZ = {.Id: ThunkBRABZ, .NameInfix: "abz_", /*HasXmOperand=*/false,
176 /*NeedsPAuth=*/true, .BROpcode: AArch64::BRABZ};
177
178// Returns thunk kind to emit, or nullptr if not a BLR* instruction.
179static const ThunkKind *getThunkKind(unsigned OriginalOpcode) {
180 switch (OriginalOpcode) {
181 case AArch64::BLR:
182 case AArch64::BLRNoIP:
183 return &ThunkKind::BR;
184 case AArch64::BLRAA:
185 return &ThunkKind::BRAA;
186 case AArch64::BLRAB:
187 return &ThunkKind::BRAB;
188 case AArch64::BLRAAZ:
189 return &ThunkKind::BRAAZ;
190 case AArch64::BLRABZ:
191 return &ThunkKind::BRABZ;
192 }
193 return nullptr;
194}
195
196static bool isBLR(const MachineInstr &MI) {
197 return getThunkKind(OriginalOpcode: MI.getOpcode()) != nullptr;
198}
199
200unsigned ThunksSet::indexOfXReg(Register Reg) {
201 assert(AArch64::GPR64RegClass.contains(Reg));
202 assert(Reg != AArch64::X16 && Reg != AArch64::X17 && Reg != AArch64::LR);
203
204 // Most Xn registers have consecutive ids, except for FP and XZR.
205 unsigned Result = (unsigned)Reg - (unsigned)AArch64::X0;
206 if (Reg == AArch64::FP)
207 Result = 29;
208 else if (Reg == AArch64::XZR)
209 Result = 31;
210
211 assert(Result < NumXRegisters && "Internal register numbering changed");
212 assert(AArch64::GPR64RegClass.getRegister(Result).id() == Reg &&
213 "Internal register numbering changed");
214
215 return Result;
216}
217
218Register ThunksSet::xRegByIndex(unsigned N) {
219 return AArch64::GPR64RegClass.getRegister(i: N);
220}
221
222static void insertSpeculationBarrier(const AArch64Subtarget *ST,
223 MachineBasicBlock &MBB,
224 MachineBasicBlock::iterator MBBI,
225 DebugLoc DL,
226 bool AlwaysUseISBDSB = false) {
227 assert(MBBI != MBB.begin() &&
228 "Must not insert SpeculationBarrierEndBB as only instruction in MBB.");
229 assert(std::prev(MBBI)->isBarrier() &&
230 "SpeculationBarrierEndBB must only follow unconditional control flow "
231 "instructions.");
232 assert(std::prev(MBBI)->isTerminator() &&
233 "SpeculationBarrierEndBB must only follow terminators.");
234 const TargetInstrInfo *TII = ST->getInstrInfo();
235 unsigned BarrierOpc = ST->hasSB() && !AlwaysUseISBDSB
236 ? AArch64::SpeculationBarrierSBEndBB
237 : AArch64::SpeculationBarrierISBDSBEndBB;
238 if (MBBI == MBB.end() ||
239 (MBBI->getOpcode() != AArch64::SpeculationBarrierSBEndBB &&
240 MBBI->getOpcode() != AArch64::SpeculationBarrierISBDSBEndBB))
241 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: BarrierOpc));
242}
243
244ThunksSet SLSHardeningInserter::insertThunks(MachineModuleInfo &MMI,
245 MachineFunction &MF,
246 ThunksSet ExistingThunks) {
247 const AArch64Subtarget *ST = &MF.getSubtarget<AArch64Subtarget>();
248
249 for (auto &MBB : MF) {
250 if (ST->hardenSlsRetBr())
251 hardenReturnsAndBRs(MMI, MBB);
252 if (ST->hardenSlsBlr())
253 hardenBLRs(MMI, MBB, Thunks&: ExistingThunks);
254 }
255 return ExistingThunks;
256}
257
258bool SLSHardeningInserter::hardenReturnsAndBRs(MachineModuleInfo &MMI,
259 MachineBasicBlock &MBB) {
260 const AArch64Subtarget *ST =
261 &MBB.getParent()->getSubtarget<AArch64Subtarget>();
262 bool Modified = false;
263 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator(), E = MBB.end();
264 MachineBasicBlock::iterator NextMBBI;
265 for (; MBBI != E; MBBI = NextMBBI) {
266 MachineInstr &MI = *MBBI;
267 NextMBBI = std::next(x: MBBI);
268 if (MI.isReturn() || isIndirectBranchOpcode(Opc: MI.getOpcode())) {
269 assert(MI.isTerminator());
270 insertSpeculationBarrier(ST, MBB, MBBI: std::next(x: MBBI), DL: MI.getDebugLoc());
271 Modified = true;
272 }
273 }
274 return Modified;
275}
276
277// Currently, the longest possible thunk name is
278// __llvm_slsblr_thunk_aa_xNN_xMM
279// which is 31 characters (without the '\0' character).
280static SmallString<32> createThunkName(const ThunkKind &Kind, Register Xn,
281 Register Xm) {
282 unsigned N = ThunksSet::indexOfXReg(Reg: Xn);
283 if (!Kind.HasXmOperand)
284 return formatv(Fmt: "{0}{1}x{2}", Vals: CommonNamePrefix, Vals: Kind.NameInfix, Vals&: N);
285
286 unsigned M = ThunksSet::indexOfXReg(Reg: Xm);
287 return formatv(Fmt: "{0}{1}x{2}_x{3}", Vals: CommonNamePrefix, Vals: Kind.NameInfix, Vals&: N, Vals&: M);
288}
289
290static std::tuple<const ThunkKind &, Register, Register>
291parseThunkName(StringRef ThunkName) {
292 assert(ThunkName.starts_with(CommonNamePrefix) &&
293 "Should be filtered out by ThunkInserter");
294 // Thunk name suffix, such as "x1" or "aa_x2_x3".
295 StringRef NameSuffix = ThunkName.drop_front(N: CommonNamePrefix.size());
296
297 // Parse thunk kind based on thunk name infix.
298 const ThunkKind &Kind = *StringSwitch<const ThunkKind *>(NameSuffix)
299 .StartsWith(S: "aa_", Value: &ThunkKind::BRAA)
300 .StartsWith(S: "ab_", Value: &ThunkKind::BRAB)
301 .StartsWith(S: "aaz_", Value: &ThunkKind::BRAAZ)
302 .StartsWith(S: "abz_", Value: &ThunkKind::BRABZ)
303 .Default(Value: &ThunkKind::BR);
304
305 auto ParseRegName = [](StringRef Name) {
306 unsigned N;
307
308 assert(Name.starts_with("x") && "xN register name expected");
309 bool Fail = Name.drop_front(N: 1).getAsInteger(/*Radix=*/10, Result&: N);
310 assert(!Fail && N < ThunksSet::NumXRegisters && "Unexpected register");
311 (void)Fail;
312
313 return ThunksSet::xRegByIndex(N);
314 };
315
316 // For example, "x1" or "x2_x3".
317 StringRef RegsStr = NameSuffix.drop_front(N: Kind.NameInfix.size());
318 StringRef XnStr, XmStr;
319 std::tie(args&: XnStr, args&: XmStr) = RegsStr.split(Separator: '_');
320
321 // Parse register operands.
322 Register Xn = ParseRegName(XnStr);
323 Register Xm = Kind.HasXmOperand ? ParseRegName(XmStr) : AArch64::NoRegister;
324
325 return std::make_tuple(args: std::ref(t: Kind), args&: Xn, args&: Xm);
326}
327
328void SLSHardeningInserter::populateThunk(MachineFunction &MF) {
329 assert(MF.getFunction().hasComdat() == ComdatThunks &&
330 "ComdatThunks value changed since MF creation");
331 Register Xn, Xm;
332 auto KindAndRegs = parseThunkName(ThunkName: MF.getName());
333 const ThunkKind &Kind = std::get<0>(t&: KindAndRegs);
334 std::tie(args: std::ignore, args&: Xn, args&: Xm) = KindAndRegs;
335
336 const TargetInstrInfo *TII =
337 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
338
339 // Depending on whether this pass is in the same FunctionPassManager as the
340 // IR->MIR conversion, the thunk may be completely empty, or contain a single
341 // basic block with a single return instruction. Normalise it to contain a
342 // single empty basic block.
343 if (MF.size() == 1) {
344 assert(MF.front().size() == 1);
345 assert(MF.front().front().getOpcode() == AArch64::RET);
346 MF.front().erase(I: MF.front().begin());
347 } else {
348 assert(MF.size() == 0);
349 MF.push_back(MBB: MF.CreateMachineBasicBlock());
350 }
351
352 MachineBasicBlock *Entry = &MF.front();
353 Entry->clear();
354
355 // These thunks need to consist of the following instructions:
356 // __llvm_slsblr_thunk_...:
357 // MOV x16, xN ; BR* instructions are not compatible with "BTI c"
358 // ; branch target unless xN is x16 or x17.
359 // BR* ... ; One of: BR x16
360 // ; BRA(A|B) x16, xM
361 // ; BRA(A|B)Z x16
362 // barrierInsts
363 Entry->addLiveIn(PhysReg: Xn);
364 // MOV X16, Reg == ORR X16, XZR, Reg, LSL #0
365 BuildMI(BB: Entry, MIMD: DebugLoc(), MCID: TII->get(Opcode: AArch64::ORRXrs), DestReg: AArch64::X16)
366 .addReg(RegNo: AArch64::XZR)
367 .addReg(RegNo: Xn)
368 .addImm(Val: 0);
369 MachineInstrBuilder Builder =
370 BuildMI(BB: Entry, MIMD: DebugLoc(), MCID: TII->get(Opcode: Kind.BROpcode)).addReg(RegNo: AArch64::X16);
371 if (Xm != AArch64::NoRegister) {
372 Entry->addLiveIn(PhysReg: Xm);
373 Builder.addReg(RegNo: Xm);
374 }
375
376 // Make sure the thunks do not make use of the SB extension in case there is
377 // a function somewhere that will call to it that for some reason disabled
378 // the SB extension locally on that function, even though it's enabled for
379 // the module otherwise. Therefore set AlwaysUseISBSDB to true.
380 insertSpeculationBarrier(ST: &MF.getSubtarget<AArch64Subtarget>(), MBB&: *Entry,
381 MBBI: Entry->end(), DL: DebugLoc(), AlwaysUseISBDSB: true /*AlwaysUseISBDSB*/);
382}
383
384void SLSHardeningInserter::convertBLRToBL(
385 MachineModuleInfo &MMI, MachineBasicBlock &MBB,
386 MachineBasicBlock::instr_iterator MBBI, ThunksSet &Thunks) {
387 // Transform a BLR* instruction (one of BLR, BLRAA/BLRAB or BLRAAZ/BLRABZ) to
388 // a BL to the thunk containing BR, BRAA/BRAB or BRAAZ/BRABZ, respectively.
389 //
390 // Before:
391 // |-----------------------------|
392 // | ... |
393 // | instI |
394 // | BLR* xN or BLR* xN, xM |
395 // | instJ |
396 // | ... |
397 // |-----------------------------|
398 //
399 // After:
400 // |-----------------------------|
401 // | ... |
402 // | instI |
403 // | BL __llvm_slsblr_thunk_... |
404 // | instJ |
405 // | ... |
406 // |-----------------------------|
407 //
408 // __llvm_slsblr_thunk_...:
409 // |-----------------------------|
410 // | MOV x16, xN |
411 // | BR* x16 or BR* x16, xM |
412 // | barrierInsts |
413 // |-----------------------------|
414 //
415 // This function needs to transform BLR* instruction into BL with the correct
416 // thunk name and lazily create the thunk if it does not exist yet.
417 //
418 // Since linkers are allowed to clobber X16 and X17 on function calls, the
419 // above mitigation only works if the original BLR* instruction had neither
420 // X16 nor X17 as one of its operands. Code generation before must make sure
421 // that no such BLR* instruction was produced if the mitigation is enabled.
422
423 MachineInstr &BLR = *MBBI;
424 assert(isBLR(BLR));
425 const ThunkKind &Kind = *getThunkKind(OriginalOpcode: BLR.getOpcode());
426
427 unsigned NumRegOperands = Kind.HasXmOperand ? 2 : 1;
428 assert(BLR.getNumExplicitOperands() == NumRegOperands &&
429 "Expected one or two register inputs");
430 Register Xn = BLR.getOperand(i: 0).getReg();
431 Register Xm =
432 Kind.HasXmOperand ? BLR.getOperand(i: 1).getReg() : AArch64::NoRegister;
433
434 DebugLoc DL = BLR.getDebugLoc();
435
436 MachineFunction &MF = *MBBI->getMF();
437 MCContext &Context = MBB.getParent()->getContext();
438 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
439
440 auto ThunkName = createThunkName(Kind, Xn, Xm);
441 MCSymbol *Sym = Context.getOrCreateSymbol(Name: ThunkName);
442
443 if (!Thunks.get(Kind: Kind.Id, Xn, Xm)) {
444 StringRef TargetAttrs = Kind.NeedsPAuth ? "+pauth" : "";
445 Thunks.set(Kind: Kind.Id, Xn, Xm);
446 createThunkFunction(MMI, Name: ThunkName, Comdat: ComdatThunks, TargetAttrs);
447 }
448
449 MachineInstr *BL = BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: AArch64::BL)).addSym(Sym);
450
451 // Now copy the implicit operands from BLR to BL and copy other necessary
452 // info.
453 // However, both BLR and BL instructions implicitly use SP and implicitly
454 // define LR. Blindly copying implicit operands would result in SP and LR
455 // operands to be present multiple times. While this may not be too much of
456 // an issue, let's avoid that for cleanliness, by removing those implicit
457 // operands from the BL created above before we copy over all implicit
458 // operands from the BLR.
459 int ImpLROpIdx = -1;
460 int ImpSPOpIdx = -1;
461 for (unsigned OpIdx = BL->getNumExplicitOperands();
462 OpIdx < BL->getNumOperands(); OpIdx++) {
463 MachineOperand Op = BL->getOperand(i: OpIdx);
464 if (!Op.isReg())
465 continue;
466 if (Op.getReg() == AArch64::LR && Op.isDef())
467 ImpLROpIdx = OpIdx;
468 if (Op.getReg() == AArch64::SP && !Op.isDef())
469 ImpSPOpIdx = OpIdx;
470 }
471 assert(ImpLROpIdx != -1);
472 assert(ImpSPOpIdx != -1);
473 int FirstOpIdxToRemove = std::max(a: ImpLROpIdx, b: ImpSPOpIdx);
474 int SecondOpIdxToRemove = std::min(a: ImpLROpIdx, b: ImpSPOpIdx);
475 BL->removeOperand(OpNo: FirstOpIdxToRemove);
476 BL->removeOperand(OpNo: SecondOpIdxToRemove);
477 // Now copy over the implicit operands from the original BLR
478 BL->copyImplicitOps(MF, MI: BLR);
479 MF.moveAdditionalCallInfo(Old: &BLR, New: BL);
480 // Also add the register operands of the original BLR* instruction
481 // as being used in the called thunk.
482 for (unsigned OpIdx = 0; OpIdx < NumRegOperands; ++OpIdx) {
483 MachineOperand &Op = BLR.getOperand(i: OpIdx);
484 BL->addOperand(Op: MachineOperand::CreateReg(Reg: Op.getReg(), /*isDef=*/false,
485 /*isImp=*/true, isKill: Op.isKill()));
486 }
487 // Remove BLR instruction
488 MBB.erase(I: MBBI);
489}
490
491bool SLSHardeningInserter::hardenBLRs(MachineModuleInfo &MMI,
492 MachineBasicBlock &MBB,
493 ThunksSet &Thunks) {
494 bool Modified = false;
495 MachineBasicBlock::instr_iterator MBBI = MBB.instr_begin(),
496 E = MBB.instr_end();
497 MachineBasicBlock::instr_iterator NextMBBI;
498 for (; MBBI != E; MBBI = NextMBBI) {
499 MachineInstr &MI = *MBBI;
500 NextMBBI = std::next(x: MBBI);
501 if (isBLR(MI)) {
502 convertBLRToBL(MMI, MBB, MBBI, Thunks);
503 Modified = true;
504 }
505 }
506 return Modified;
507}
508
509namespace {
510class AArch64SLSHardeningLegacy
511 : public ThunkInserterPass<SLSHardeningInserter> {
512public:
513 static char ID;
514
515 AArch64SLSHardeningLegacy() : ThunkInserterPass(ID) {}
516
517 StringRef getPassName() const override { return AARCH64_SLS_HARDENING_NAME; }
518};
519
520} // end anonymous namespace
521
522char AArch64SLSHardeningLegacy::ID = 0;
523
524INITIALIZE_PASS(AArch64SLSHardeningLegacy, "aarch64-sls-hardening",
525 AARCH64_SLS_HARDENING_NAME, false, false)
526
527FunctionPass *llvm::createAArch64SLSHardeningLegacyPass() {
528 return new AArch64SLSHardeningLegacy();
529}
530
531PreservedAnalyses
532AArch64SLSHardeningPass::run(MachineFunction &MF,
533 MachineFunctionAnalysisManager &MFAM) {
534 MachineModuleAnalysis::Result *MMI =
535 MFAM.getResult<ModuleAnalysisManagerMachineFunctionProxy>(IR&: MF)
536 .getCachedResult<MachineModuleAnalysis>(
537 IR&: *MF.getFunction().getParent());
538 assert(MMI && "MachineModuleAnalysis must be available");
539
540 SLSHardeningInserter Inserter;
541 Inserter.init(M&: *MF.getFunction().getParent());
542
543 if (Inserter.run(MMI&: MMI->getMMI(), MF)) {
544 PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
545 PA.preserveSet<CFGAnalyses>();
546 return PA;
547 }
548 return PreservedAnalyses::all();
549}
550