1//=== AArch64PostLegalizerCombiner.cpp --------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// Post-legalization combines on generic MachineInstrs.
11///
12/// The combines here must preserve instruction legality.
13///
14/// Lowering combines (e.g. pseudo matching) should be handled by
15/// AArch64PostLegalizerLowering.
16///
17/// Combines which don't rely on instruction legality should go in the
18/// AArch64PreLegalizerCombiner.
19///
20//===----------------------------------------------------------------------===//
21
22#include "AArch64.h"
23#include "AArch64TargetMachine.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
26#include "llvm/CodeGen/GlobalISel/CSEMIRBuilder.h"
27#include "llvm/CodeGen/GlobalISel/Combiner.h"
28#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
29#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
30#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
31#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
32#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h"
33#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
34#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
35#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
36#include "llvm/CodeGen/GlobalISel/Utils.h"
37#include "llvm/CodeGen/MachineDominators.h"
38#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
39#include "llvm/CodeGen/MachineFunctionPass.h"
40#include "llvm/CodeGen/MachinePassManager.h"
41#include "llvm/CodeGen/MachineRegisterInfo.h"
42#include "llvm/CodeGen/TargetOpcodes.h"
43#include "llvm/Support/Debug.h"
44
45#define GET_GICOMBINER_DEPS
46#include "AArch64GenPostLegalizeGICombiner.inc"
47#undef GET_GICOMBINER_DEPS
48
49#define DEBUG_TYPE "aarch64-postlegalizer-combiner"
50
51using namespace llvm;
52using namespace MIPatternMatch;
53
54#define GET_GICOMBINER_TYPES
55#include "AArch64GenPostLegalizeGICombiner.inc"
56#undef GET_GICOMBINER_TYPES
57
58namespace {
59
60/// This combine tries do what performExtractVectorEltCombine does in SDAG.
61/// Rewrite for pairwise fadd pattern
62/// (s32 (g_extract_vector_elt
63/// (g_fadd (vXs32 Other)
64/// (g_vector_shuffle (vXs32 Other) undef <1,X,...> )) 0))
65/// ->
66/// (s32 (g_fadd (g_extract_vector_elt (vXs32 Other) 0)
67/// (g_extract_vector_elt (vXs32 Other) 1))
68bool matchExtractVecEltPairwiseAdd(
69 MachineInstr &MI, MachineRegisterInfo &MRI,
70 std::tuple<unsigned, LLT, Register> &MatchInfo) {
71 Register Src1 = MI.getOperand(i: 1).getReg();
72 Register Src2 = MI.getOperand(i: 2).getReg();
73 LLT DstTy = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
74
75 auto Cst = getIConstantVRegValWithLookThrough(VReg: Src2, MRI);
76 if (!Cst || Cst->Value != 0)
77 return false;
78 // SDAG also checks for FullFP16, but this looks to be beneficial anyway.
79
80 // Now check for an fadd operation. TODO: expand this for integer add?
81 auto *FAddMI = getOpcodeDef(Opcode: TargetOpcode::G_FADD, Reg: Src1, MRI);
82 if (!FAddMI)
83 return false;
84
85 // If we add support for integer add, must restrict these types to just s64.
86 unsigned DstSize = DstTy.getSizeInBits();
87 if (DstSize != 16 && DstSize != 32 && DstSize != 64)
88 return false;
89
90 Register Src1Op1 = FAddMI->getOperand(i: 1).getReg();
91 Register Src1Op2 = FAddMI->getOperand(i: 2).getReg();
92 MachineInstr *Shuffle =
93 getOpcodeDef(Opcode: TargetOpcode::G_SHUFFLE_VECTOR, Reg: Src1Op2, MRI);
94 MachineInstr *Other = MRI.getVRegDef(Reg: Src1Op1);
95 if (!Shuffle) {
96 Shuffle = getOpcodeDef(Opcode: TargetOpcode::G_SHUFFLE_VECTOR, Reg: Src1Op1, MRI);
97 Other = MRI.getVRegDef(Reg: Src1Op2);
98 }
99
100 // We're looking for a shuffle that moves the second element to index 0.
101 if (Shuffle && Shuffle->getOperand(i: 3).getShuffleMask()[0] == 1 &&
102 Other == MRI.getVRegDef(Reg: Shuffle->getOperand(i: 1).getReg())) {
103 std::get<0>(t&: MatchInfo) = TargetOpcode::G_FADD;
104 std::get<1>(t&: MatchInfo) = DstTy;
105 std::get<2>(t&: MatchInfo) = Other->getOperand(i: 0).getReg();
106 return true;
107 }
108 return false;
109}
110
111void applyExtractVecEltPairwiseAdd(
112 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
113 std::tuple<unsigned, LLT, Register> &MatchInfo) {
114 unsigned Opc = std::get<0>(t&: MatchInfo);
115 assert(Opc == TargetOpcode::G_FADD && "Unexpected opcode!");
116 // We want to generate two extracts of elements 0 and 1, and add them.
117 LLT Ty = std::get<1>(t&: MatchInfo);
118 Register Src = std::get<2>(t&: MatchInfo);
119 LLT s64 = LLT::integer(SizeInBits: 64);
120 B.setInstrAndDebugLoc(MI);
121 auto Elt0 = B.buildExtractVectorElement(Res: Ty, Val: Src, Idx: B.buildConstant(Res: s64, Val: 0));
122 auto Elt1 = B.buildExtractVectorElement(Res: Ty, Val: Src, Idx: B.buildConstant(Res: s64, Val: 1));
123 B.buildInstr(Opc, DstOps: {MI.getOperand(i: 0).getReg()}, SrcOps: {Elt0, Elt1});
124 MI.eraseFromParent();
125}
126
127bool isSignExtended(Register R, MachineRegisterInfo &MRI) {
128 // TODO: check if extended build vector as well.
129 return mi_match(R, MRI, P: m_GSExt(Src: m_Reg())) ||
130 mi_match(R, MRI, P: m_GSExtInReg(Src: m_Reg()));
131}
132
133bool isZeroExtended(Register R, MachineRegisterInfo &MRI) {
134 // TODO: check if extended build vector as well.
135 return mi_match(R, MRI, P: m_GZExt(Src: m_Reg()));
136}
137
138bool matchAArch64MulConstCombine(
139 MachineInstr &MI, MachineRegisterInfo &MRI,
140 std::function<void(MachineIRBuilder &B, Register DstReg)> &ApplyFn) {
141 assert(MI.getOpcode() == TargetOpcode::G_MUL);
142 Register LHS = MI.getOperand(i: 1).getReg();
143 Register RHS = MI.getOperand(i: 2).getReg();
144 Register Dst = MI.getOperand(i: 0).getReg();
145 const LLT Ty = MRI.getType(Reg: LHS);
146
147 // The below optimizations require a constant RHS.
148 auto Const = getIConstantVRegValWithLookThrough(VReg: RHS, MRI);
149 if (!Const)
150 return false;
151
152 APInt ConstValue = Const->Value.sext(width: Ty.getSizeInBits());
153 // The following code is ported from AArch64ISelLowering.
154 // Multiplication of a power of two plus/minus one can be done more
155 // cheaply as shift+add/sub. For now, this is true unilaterally. If
156 // future CPUs have a cheaper MADD instruction, this may need to be
157 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
158 // 64-bit is 5 cycles, so this is always a win.
159 // More aggressively, some multiplications N0 * C can be lowered to
160 // shift+add+shift if the constant C = A * B where A = 2^N + 1 and B = 2^M,
161 // e.g. 6=3*2=(2+1)*2.
162 // TODO: consider lowering more cases, e.g. C = 14, -6, -14 or even 45
163 // which equals to (1+2)*16-(1+2).
164 // TrailingZeroes is used to test if the mul can be lowered to
165 // shift+add+shift.
166 unsigned TrailingZeroes = ConstValue.countr_zero();
167 if (TrailingZeroes) {
168 // Conservatively do not lower to shift+add+shift if the mul might be
169 // folded into smul or umul.
170 if (MRI.hasOneNonDBGUse(RegNo: LHS) &&
171 (isSignExtended(R: LHS, MRI) || isZeroExtended(R: LHS, MRI)))
172 return false;
173 // Conservatively do not lower to shift+add+shift if the mul might be
174 // folded into madd or msub.
175 if (MRI.hasOneNonDBGUse(RegNo: Dst)) {
176 MachineInstr &UseMI = *MRI.use_instr_begin(RegNo: Dst);
177 unsigned UseOpc = UseMI.getOpcode();
178 if (UseOpc == TargetOpcode::G_ADD || UseOpc == TargetOpcode::G_PTR_ADD ||
179 UseOpc == TargetOpcode::G_SUB)
180 return false;
181 }
182 }
183 // Use ShiftedConstValue instead of ConstValue to support both shift+add/sub
184 // and shift+add+shift.
185 APInt ShiftedConstValue = ConstValue.ashr(ShiftAmt: TrailingZeroes);
186
187 unsigned ShiftAmt, AddSubOpc;
188 // Is the shifted value the LHS operand of the add/sub?
189 bool ShiftValUseIsLHS = true;
190 // Do we need to negate the result?
191 bool NegateResult = false;
192
193 if (ConstValue.isNonNegative()) {
194 // (mul x, 2^N + 1) => (add (shl x, N), x)
195 // (mul x, 2^N - 1) => (sub (shl x, N), x)
196 // (mul x, (2^N + 1) * 2^M) => (shl (add (shl x, N), x), M)
197 APInt SCVMinus1 = ShiftedConstValue - 1;
198 APInt CVPlus1 = ConstValue + 1;
199 if (SCVMinus1.isPowerOf2()) {
200 ShiftAmt = SCVMinus1.logBase2();
201 AddSubOpc = TargetOpcode::G_ADD;
202 } else if (CVPlus1.isPowerOf2()) {
203 ShiftAmt = CVPlus1.logBase2();
204 AddSubOpc = TargetOpcode::G_SUB;
205 } else
206 return false;
207 } else {
208 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
209 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
210 APInt CVNegPlus1 = -ConstValue + 1;
211 APInt CVNegMinus1 = -ConstValue - 1;
212 if (CVNegPlus1.isPowerOf2()) {
213 ShiftAmt = CVNegPlus1.logBase2();
214 AddSubOpc = TargetOpcode::G_SUB;
215 ShiftValUseIsLHS = false;
216 } else if (CVNegMinus1.isPowerOf2()) {
217 ShiftAmt = CVNegMinus1.logBase2();
218 AddSubOpc = TargetOpcode::G_ADD;
219 NegateResult = true;
220 } else
221 return false;
222 }
223
224 if (NegateResult && TrailingZeroes)
225 return false;
226
227 ApplyFn = [=](MachineIRBuilder &B, Register DstReg) {
228 auto Shift = B.buildConstant(Res: LLT::integer(SizeInBits: 64), Val: ShiftAmt);
229 auto ShiftedVal = B.buildShl(Dst: Ty, Src0: LHS, Src1: Shift);
230
231 Register AddSubLHS = ShiftValUseIsLHS ? ShiftedVal.getReg(Idx: 0) : LHS;
232 Register AddSubRHS = ShiftValUseIsLHS ? LHS : ShiftedVal.getReg(Idx: 0);
233 auto Res = B.buildInstr(Opc: AddSubOpc, DstOps: {Ty}, SrcOps: {AddSubLHS, AddSubRHS});
234 assert(!(NegateResult && TrailingZeroes) &&
235 "NegateResult and TrailingZeroes cannot both be true for now.");
236 // Negate the result.
237 if (NegateResult) {
238 B.buildSub(Dst: DstReg, Src0: B.buildConstant(Res: Ty, Val: 0), Src1: Res);
239 return;
240 }
241 // Shift the result.
242 if (TrailingZeroes) {
243 B.buildShl(Dst: DstReg, Src0: Res,
244 Src1: B.buildConstant(Res: LLT::integer(SizeInBits: 64), Val: TrailingZeroes));
245 return;
246 }
247 B.buildCopy(Res: DstReg, Op: Res.getReg(Idx: 0));
248 };
249 return true;
250}
251
252void applyAArch64MulConstCombine(
253 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
254 std::function<void(MachineIRBuilder &B, Register DstReg)> &ApplyFn) {
255 B.setInstrAndDebugLoc(MI);
256 ApplyFn(B, MI.getOperand(i: 0).getReg());
257 MI.eraseFromParent();
258}
259
260/// Try to fold a G_MERGE_VALUES of 2 s32 sources, where the second source
261/// is a zero, into a G_ZEXT of the first.
262bool matchFoldMergeToZext(MachineInstr &MI, MachineRegisterInfo &MRI) {
263 auto &Merge = cast<GMerge>(Val&: MI);
264 LLT SrcTy = MRI.getType(Reg: Merge.getSourceReg(I: 0));
265 if (SrcTy != LLT::scalar(SizeInBits: 32) || Merge.getNumSources() != 2)
266 return false;
267 return mi_match(R: Merge.getSourceReg(I: 1), MRI, P: m_SpecificICst(RequestedValue: 0));
268}
269
270void applyFoldMergeToZext(MachineInstr &MI, MachineRegisterInfo &MRI,
271 MachineIRBuilder &B, GISelChangeObserver &Observer) {
272 // Mutate %d(s64) = G_MERGE_VALUES %a(s32), 0(s32)
273 // ->
274 // %d(s64) = G_ZEXT %a(s32)
275 Observer.changingInstr(MI);
276 MI.setDesc(B.getTII().get(Opcode: TargetOpcode::G_ZEXT));
277 MI.removeOperand(OpNo: 2);
278 Observer.changedInstr(MI);
279}
280
281/// \returns True if a G_ANYEXT instruction \p MI should be mutated to a G_ZEXT
282/// instruction.
283bool matchMutateAnyExtToZExt(MachineInstr &MI, MachineRegisterInfo &MRI) {
284 // If this is coming from a scalar compare then we can use a G_ZEXT instead of
285 // a G_ANYEXT:
286 //
287 // %cmp:_(s32) = G_[I|F]CMP ... <-- produces 0/1.
288 // %ext:_(s64) = G_ANYEXT %cmp(s32)
289 //
290 // By doing this, we can leverage more KnownBits combines.
291 assert(MI.getOpcode() == TargetOpcode::G_ANYEXT);
292 Register Dst = MI.getOperand(i: 0).getReg();
293 Register Src = MI.getOperand(i: 1).getReg();
294 return MRI.getType(Reg: Dst).isScalar() &&
295 mi_match(R: Src, MRI,
296 P: m_any_of(preds: m_GICmp(P: m_Pred(), L: m_Reg(), R: m_Reg()),
297 preds: m_GFCmp(P: m_Pred(), L: m_Reg(), R: m_Reg())));
298}
299
300void applyMutateAnyExtToZExt(MachineInstr &MI, MachineRegisterInfo &MRI,
301 MachineIRBuilder &B,
302 GISelChangeObserver &Observer) {
303 Observer.changingInstr(MI);
304 MI.setDesc(B.getTII().get(Opcode: TargetOpcode::G_ZEXT));
305 Observer.changedInstr(MI);
306}
307
308/// Match a 128b store of zero and split it into two 64 bit stores, for
309/// size/performance reasons.
310bool matchSplitStoreZero128(MachineInstr &MI, MachineRegisterInfo &MRI) {
311 GStore &Store = cast<GStore>(Val&: MI);
312 if (!Store.isSimple())
313 return false;
314 LLT ValTy = MRI.getType(Reg: Store.getValueReg());
315 if (ValTy.isScalableVector())
316 return false;
317 if (!ValTy.isVector() || ValTy.getSizeInBits() != 128)
318 return false;
319 if (Store.getMemSizeInBits() != ValTy.getSizeInBits())
320 return false; // Don't split truncating stores.
321 if (!MRI.hasOneNonDBGUse(RegNo: Store.getValueReg()))
322 return false;
323 auto MaybeCst = isConstantOrConstantSplatVector(Def: Store.getValueReg(), MRI);
324 return MaybeCst && MaybeCst->isZero();
325}
326
327void applySplitStoreZero128(MachineInstr &MI, MachineRegisterInfo &MRI,
328 MachineIRBuilder &B,
329 GISelChangeObserver &Observer) {
330 B.setInstrAndDebugLoc(MI);
331 GStore &Store = cast<GStore>(Val&: MI);
332 assert(MRI.getType(Store.getValueReg()).isVector() &&
333 "Expected a vector store value");
334 LLT NewTy = LLT::integer(SizeInBits: 64);
335 Register PtrReg = Store.getPointerReg();
336 auto Zero = B.buildConstant(Res: NewTy, Val: 0);
337 auto HighPtr =
338 B.buildPtrAdd(Res: MRI.getType(Reg: PtrReg), Op0: PtrReg, Op1: B.buildConstant(Res: NewTy, Val: 8));
339 auto &MF = *MI.getMF();
340 auto *LowMMO = MF.getMachineMemOperand(MMO: &Store.getMMO(), Offset: 0, Ty: NewTy);
341 auto *HighMMO = MF.getMachineMemOperand(MMO: &Store.getMMO(), Offset: 8, Ty: NewTy);
342 B.buildStore(Val: Zero, Addr: PtrReg, MMO&: *LowMMO);
343 B.buildStore(Val: Zero, Addr: HighPtr, MMO&: *HighMMO);
344 Store.eraseFromParent();
345}
346
347bool matchOrToBSP(MachineInstr &MI, MachineRegisterInfo &MRI,
348 std::tuple<Register, Register, Register> &MatchInfo) {
349 const LLT DstTy = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
350 if (!DstTy.isVector())
351 return false;
352
353 Register AO1, AO2, BVO1, BVO2;
354 if (!mi_match(MI, MRI,
355 P: m_GOr(L: m_GAnd(L: m_Reg(R&: AO1), R: m_Reg(R&: BVO1)),
356 R: m_GAnd(L: m_Reg(R&: AO2), R: m_Reg(R&: BVO2)))))
357 return false;
358
359 auto *BV1 = getOpcodeDef<GBuildVector>(Reg: BVO1, MRI);
360 auto *BV2 = getOpcodeDef<GBuildVector>(Reg: BVO2, MRI);
361 if (!BV1 || !BV2)
362 return false;
363
364 for (int I = 0, E = DstTy.getNumElements(); I < E; I++) {
365 auto ValAndVReg1 =
366 getIConstantVRegValWithLookThrough(VReg: BV1->getSourceReg(I), MRI);
367 auto ValAndVReg2 =
368 getIConstantVRegValWithLookThrough(VReg: BV2->getSourceReg(I), MRI);
369 if (!ValAndVReg1 || !ValAndVReg2 ||
370 ValAndVReg1->Value != ~ValAndVReg2->Value)
371 return false;
372 }
373
374 MatchInfo = {AO1, AO2, BVO1};
375 return true;
376}
377
378void applyOrToBSP(MachineInstr &MI, MachineRegisterInfo &MRI,
379 MachineIRBuilder &B,
380 std::tuple<Register, Register, Register> &MatchInfo) {
381 B.setInstrAndDebugLoc(MI);
382 B.buildInstr(
383 Opc: AArch64::G_BSP, DstOps: {MI.getOperand(i: 0).getReg()},
384 SrcOps: {std::get<2>(t&: MatchInfo), std::get<0>(t&: MatchInfo), std::get<1>(t&: MatchInfo)});
385 MI.eraseFromParent();
386}
387
388/// Match G_TRUNC (G_OR X, Y) => G_ADDHN X, Y when both inputs are sign
389/// extended from the result element type. The high half of the addition then
390/// equals the truncation of the OR.
391bool matchTruncOrToADDHN(MachineInstr &MI, MachineRegisterInfo &MRI,
392 GISelValueTracking *VT, Register Dst, Register Or,
393 Register Src0, Register Src1) {
394 if (!MRI.hasOneUse(RegNo: Or))
395 return false;
396
397 LLT DstTy = MRI.getType(Reg: Dst);
398 LLT SrcTy = MRI.getType(Reg: Or);
399 if (!((DstTy == LLT::fixed_vector(NumElements: 8, ScalarSizeInBits: 8) &&
400 SrcTy == LLT::fixed_vector(NumElements: 8, ScalarSizeInBits: 16)) ||
401 (DstTy == LLT::fixed_vector(NumElements: 4, ScalarSizeInBits: 16) &&
402 SrcTy == LLT::fixed_vector(NumElements: 4, ScalarSizeInBits: 32)) ||
403 (DstTy == LLT::fixed_vector(NumElements: 2, ScalarSizeInBits: 32) &&
404 SrcTy == LLT::fixed_vector(NumElements: 2, ScalarSizeInBits: 64))))
405 return false;
406
407 // If the narrow result is immediately any-extended back to the original type,
408 // the G_OR is cheaper than G_ADDHN followed by a vector widen.
409 if (MRI.hasOneNonDBGUse(RegNo: Dst)) {
410 MachineInstr &UseMI = *MRI.use_nodbg_instructions(Reg: Dst).begin();
411 if (UseMI.getOpcode() == TargetOpcode::G_ANYEXT &&
412 MRI.getType(Reg: UseMI.getOperand(i: 0).getReg()) == SrcTy)
413 return false;
414 }
415
416 unsigned EltSize = SrcTy.getScalarSizeInBits();
417 if (VT->computeNumSignBits(R: Src0) != EltSize ||
418 VT->computeNumSignBits(R: Src1) != EltSize)
419 return false;
420
421 return true;
422}
423
424// Combines Mul(And(Srl(X, 15), 0x10001), 0xffff) into CMLTz
425bool matchCombineMulCMLT(MachineInstr &MI, MachineRegisterInfo &MRI,
426 Register &SrcReg) {
427 LLT DstTy = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
428
429 if (DstTy != LLT::fixed_vector(NumElements: 2, ScalarSizeInBits: 64) && DstTy != LLT::fixed_vector(NumElements: 2, ScalarSizeInBits: 32) &&
430 DstTy != LLT::fixed_vector(NumElements: 4, ScalarSizeInBits: 32) && DstTy != LLT::fixed_vector(NumElements: 4, ScalarSizeInBits: 16) &&
431 DstTy != LLT::fixed_vector(NumElements: 8, ScalarSizeInBits: 16))
432 return false;
433
434 auto AndMI = getDefIgnoringCopies(Reg: MI.getOperand(i: 1).getReg(), MRI);
435 if (AndMI->getOpcode() != TargetOpcode::G_AND)
436 return false;
437 auto LShrMI = getDefIgnoringCopies(Reg: AndMI->getOperand(i: 1).getReg(), MRI);
438 if (LShrMI->getOpcode() != TargetOpcode::G_LSHR)
439 return false;
440
441 // Check the constant splat values
442 auto V1 = isConstantOrConstantSplatVector(Def: MI.getOperand(i: 2).getReg(), MRI);
443 auto V2 = isConstantOrConstantSplatVector(Def: AndMI->getOperand(i: 2).getReg(), MRI);
444 auto V3 =
445 isConstantOrConstantSplatVector(Def: LShrMI->getOperand(i: 2).getReg(), MRI);
446 if (!V1.has_value() || !V2.has_value() || !V3.has_value())
447 return false;
448 unsigned HalfSize = DstTy.getScalarSizeInBits() / 2;
449 if (!V1.value().isMask(numBits: HalfSize) || V2.value() != (1ULL | 1ULL << HalfSize) ||
450 V3 != (HalfSize - 1))
451 return false;
452
453 SrcReg = LShrMI->getOperand(i: 1).getReg();
454
455 return true;
456}
457
458void applyCombineMulCMLT(MachineInstr &MI, MachineRegisterInfo &MRI,
459 MachineIRBuilder &B, Register &SrcReg) {
460 Register DstReg = MI.getOperand(i: 0).getReg();
461 LLT DstTy = MRI.getType(Reg: DstReg);
462 LLT HalfTy = DstTy.changeElementCount(EC: DstTy.getElementCount() * 2)
463 .changeElementSize(NewEltSize: DstTy.getScalarSizeInBits() / 2);
464
465 Register ZeroVec = B.buildConstant(Res: HalfTy, Val: 0).getReg(Idx: 0);
466 Register CastReg =
467 B.buildInstr(Opc: TargetOpcode::G_BITCAST, DstOps: {HalfTy}, SrcOps: {SrcReg}).getReg(Idx: 0);
468 Register CMLTReg =
469 B.buildICmp(Pred: CmpInst::Predicate::ICMP_SLT, Res: HalfTy, Op0: CastReg, Op1: ZeroVec)
470 .getReg(Idx: 0);
471
472 B.buildInstr(Opc: TargetOpcode::G_BITCAST, DstOps: {DstReg}, SrcOps: {CMLTReg}).getReg(Idx: 0);
473 MI.eraseFromParent();
474}
475
476// Match mul({z/s}ext , {z/s}ext) => {u/s}mull
477bool matchExtMulToMULL(MachineInstr &MI, MachineRegisterInfo &MRI,
478 GISelValueTracking *KB,
479 std::tuple<bool, Register, Register> &MatchInfo) {
480 // Get the instructions that defined the source operand
481 LLT DstTy = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
482 MachineInstr *I1 = getDefIgnoringCopies(Reg: MI.getOperand(i: 1).getReg(), MRI);
483 MachineInstr *I2 = getDefIgnoringCopies(Reg: MI.getOperand(i: 2).getReg(), MRI);
484 unsigned I1Opc = I1->getOpcode();
485 unsigned I2Opc = I2->getOpcode();
486 unsigned EltSize = DstTy.getScalarSizeInBits();
487
488 if (!DstTy.isVector() || I1->getNumOperands() < 2 || I2->getNumOperands() < 2)
489 return false;
490
491 auto IsAtLeastDoubleExtend = [&](Register R) {
492 LLT Ty = MRI.getType(Reg: R);
493 return EltSize >= Ty.getScalarSizeInBits() * 2;
494 };
495
496 // If the source operands were EXTENDED before, then {U/S}MULL can be used
497 bool IsZExt1 =
498 I1Opc == TargetOpcode::G_ZEXT || I1Opc == TargetOpcode::G_ANYEXT;
499 bool IsZExt2 =
500 I2Opc == TargetOpcode::G_ZEXT || I2Opc == TargetOpcode::G_ANYEXT;
501 if (IsZExt1 && IsZExt2 && IsAtLeastDoubleExtend(I1->getOperand(i: 1).getReg()) &&
502 IsAtLeastDoubleExtend(I2->getOperand(i: 1).getReg())) {
503 get<0>(t&: MatchInfo) = true;
504 get<1>(t&: MatchInfo) = I1->getOperand(i: 1).getReg();
505 get<2>(t&: MatchInfo) = I2->getOperand(i: 1).getReg();
506 return true;
507 }
508
509 bool IsSExt1 =
510 I1Opc == TargetOpcode::G_SEXT || I1Opc == TargetOpcode::G_ANYEXT;
511 bool IsSExt2 =
512 I2Opc == TargetOpcode::G_SEXT || I2Opc == TargetOpcode::G_ANYEXT;
513 if (IsSExt1 && IsSExt2 && IsAtLeastDoubleExtend(I1->getOperand(i: 1).getReg()) &&
514 IsAtLeastDoubleExtend(I2->getOperand(i: 1).getReg())) {
515 get<0>(t&: MatchInfo) = false;
516 get<1>(t&: MatchInfo) = I1->getOperand(i: 1).getReg();
517 get<2>(t&: MatchInfo) = I2->getOperand(i: 1).getReg();
518 return true;
519 }
520
521 // Select UMULL if we can replace the other operand with an extend.
522 APInt Mask = APInt::getHighBitsSet(numBits: EltSize, hiBitsSet: EltSize / 2);
523 if (KB && (IsZExt1 || IsZExt2) &&
524 IsAtLeastDoubleExtend(IsZExt1 ? I1->getOperand(i: 1).getReg()
525 : I2->getOperand(i: 1).getReg())) {
526 Register ZExtOp =
527 IsZExt1 ? MI.getOperand(i: 2).getReg() : MI.getOperand(i: 1).getReg();
528 if (KB->maskedValueIsZero(Val: ZExtOp, Mask)) {
529 get<0>(t&: MatchInfo) = true;
530 get<1>(t&: MatchInfo) = IsZExt1 ? I1->getOperand(i: 1).getReg() : ZExtOp;
531 get<2>(t&: MatchInfo) = IsZExt1 ? ZExtOp : I2->getOperand(i: 1).getReg();
532 return true;
533 }
534 } else if (KB && DstTy == LLT::fixed_vector(NumElements: 2, ScalarSizeInBits: 64) &&
535 KB->maskedValueIsZero(Val: MI.getOperand(i: 1).getReg(), Mask) &&
536 KB->maskedValueIsZero(Val: MI.getOperand(i: 2).getReg(), Mask)) {
537 get<0>(t&: MatchInfo) = true;
538 get<1>(t&: MatchInfo) = MI.getOperand(i: 1).getReg();
539 get<2>(t&: MatchInfo) = MI.getOperand(i: 2).getReg();
540 return true;
541 }
542
543 if (KB && (IsSExt1 || IsSExt2) &&
544 IsAtLeastDoubleExtend(IsSExt1 ? I1->getOperand(i: 1).getReg()
545 : I2->getOperand(i: 1).getReg())) {
546 Register SExtOp =
547 IsSExt1 ? MI.getOperand(i: 2).getReg() : MI.getOperand(i: 1).getReg();
548 if (KB->computeNumSignBits(R: SExtOp) > EltSize / 2) {
549 get<0>(t&: MatchInfo) = false;
550 get<1>(t&: MatchInfo) = IsSExt1 ? I1->getOperand(i: 1).getReg() : SExtOp;
551 get<2>(t&: MatchInfo) = IsSExt1 ? SExtOp : I2->getOperand(i: 1).getReg();
552 return true;
553 }
554 } else if (KB && DstTy == LLT::fixed_vector(NumElements: 2, ScalarSizeInBits: 64) &&
555 KB->computeNumSignBits(R: MI.getOperand(i: 1).getReg()) > EltSize / 2 &&
556 KB->computeNumSignBits(R: MI.getOperand(i: 2).getReg()) > EltSize / 2) {
557 get<0>(t&: MatchInfo) = false;
558 get<1>(t&: MatchInfo) = MI.getOperand(i: 1).getReg();
559 get<2>(t&: MatchInfo) = MI.getOperand(i: 2).getReg();
560 return true;
561 }
562
563 return false;
564}
565
566void applyExtMulToMULL(MachineInstr &MI, MachineRegisterInfo &MRI,
567 MachineIRBuilder &B, GISelChangeObserver &Observer,
568 std::tuple<bool, Register, Register> &MatchInfo) {
569 assert(MI.getOpcode() == TargetOpcode::G_MUL &&
570 "Expected a G_MUL instruction");
571
572 // Get the instructions that defined the source operand
573 LLT DstTy = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
574 bool IsZExt = get<0>(t&: MatchInfo);
575 Register Src1Reg = get<1>(t&: MatchInfo);
576 Register Src2Reg = get<2>(t&: MatchInfo);
577 LLT Src1Ty = MRI.getType(Reg: Src1Reg);
578 LLT Src2Ty = MRI.getType(Reg: Src2Reg);
579 LLT HalfDstTy = DstTy.changeElementSize(NewEltSize: DstTy.getScalarSizeInBits() / 2);
580 unsigned ExtOpc = IsZExt ? TargetOpcode::G_ZEXT : TargetOpcode::G_SEXT;
581
582 if (Src1Ty.getScalarSizeInBits() * 2 != DstTy.getScalarSizeInBits())
583 Src1Reg = B.buildExtOrTrunc(ExtOpc, Res: {HalfDstTy}, Op: {Src1Reg}).getReg(Idx: 0);
584 if (Src2Ty.getScalarSizeInBits() * 2 != DstTy.getScalarSizeInBits())
585 Src2Reg = B.buildExtOrTrunc(ExtOpc, Res: {HalfDstTy}, Op: {Src2Reg}).getReg(Idx: 0);
586
587 B.buildInstr(Opc: IsZExt ? AArch64::G_UMULL : AArch64::G_SMULL,
588 DstOps: {MI.getOperand(i: 0).getReg()}, SrcOps: {Src1Reg, Src2Reg});
589 MI.eraseFromParent();
590}
591
592static bool matchSubAddMulReassoc(Register Mul1, Register Mul2, Register Sub,
593 Register Src, MachineRegisterInfo &MRI) {
594 if (!MRI.hasOneUse(RegNo: Sub))
595 return false;
596 if (getIConstantVRegValWithLookThrough(VReg: Src, MRI))
597 return false;
598 MachineInstr *M1 = getDefIgnoringCopies(Reg: Mul1, MRI);
599 if (M1->getOpcode() != AArch64::G_MUL &&
600 M1->getOpcode() != AArch64::G_SMULL &&
601 M1->getOpcode() != AArch64::G_UMULL)
602 return false;
603 MachineInstr *M2 = getDefIgnoringCopies(Reg: Mul2, MRI);
604 if (M2->getOpcode() != AArch64::G_MUL &&
605 M2->getOpcode() != AArch64::G_SMULL &&
606 M2->getOpcode() != AArch64::G_UMULL)
607 return false;
608 return true;
609}
610
611static void applySubAddMulReassoc(MachineInstr &MI, MachineInstr &Sub,
612 MachineRegisterInfo &MRI, MachineIRBuilder &B,
613 GISelChangeObserver &Observer) {
614 Register Src = MI.getOperand(i: 1).getReg();
615 Register Tmp = MI.getOperand(i: 2).getReg();
616 Register Mul1 = Sub.getOperand(i: 1).getReg();
617 Register Mul2 = Sub.getOperand(i: 2).getReg();
618 Observer.changingInstr(MI);
619 B.buildInstr(Opc: AArch64::G_SUB, DstOps: {Tmp}, SrcOps: {Src, Mul1});
620 MI.getOperand(i: 1).setReg(Tmp);
621 MI.getOperand(i: 2).setReg(Mul2);
622 Sub.eraseFromParent();
623 Observer.changedInstr(MI);
624}
625
626class AArch64PostLegalizerCombinerImpl : public Combiner {
627protected:
628 const CombinerHelper Helper;
629 const AArch64PostLegalizerCombinerImplRuleConfig &RuleConfig;
630 const AArch64Subtarget &STI;
631
632public:
633 AArch64PostLegalizerCombinerImpl(
634 MachineFunction &MF, CombinerInfo &CInfo, GISelValueTracking &VT,
635 GISelCSEInfo *CSEInfo,
636 const AArch64PostLegalizerCombinerImplRuleConfig &RuleConfig,
637 const AArch64Subtarget &STI, MachineDominatorTree *MDT,
638 const LegalizerInfo *LI);
639
640 static const char *getName() { return "AArch64PostLegalizerCombiner"; }
641
642 bool tryCombineAll(MachineInstr &I) const override;
643
644private:
645#define GET_GICOMBINER_CLASS_MEMBERS
646#include "AArch64GenPostLegalizeGICombiner.inc"
647#undef GET_GICOMBINER_CLASS_MEMBERS
648};
649
650#define GET_GICOMBINER_IMPL
651#include "AArch64GenPostLegalizeGICombiner.inc"
652#undef GET_GICOMBINER_IMPL
653
654AArch64PostLegalizerCombinerImpl::AArch64PostLegalizerCombinerImpl(
655 MachineFunction &MF, CombinerInfo &CInfo, GISelValueTracking &VT,
656 GISelCSEInfo *CSEInfo,
657 const AArch64PostLegalizerCombinerImplRuleConfig &RuleConfig,
658 const AArch64Subtarget &STI, MachineDominatorTree *MDT,
659 const LegalizerInfo *LI)
660 : Combiner(MF, CInfo, &VT, CSEInfo),
661 Helper(Observer, B, /*IsPreLegalize*/ false, &VT, MDT, LI),
662 RuleConfig(RuleConfig), STI(STI),
663#define GET_GICOMBINER_CONSTRUCTOR_INITS
664#include "AArch64GenPostLegalizeGICombiner.inc"
665#undef GET_GICOMBINER_CONSTRUCTOR_INITS
666{
667}
668
669struct StoreInfo {
670 GStore *St = nullptr;
671 // The G_PTR_ADD that's used by the store. We keep this to cache the
672 // MachineInstr def.
673 GPtrAdd *Ptr = nullptr;
674 // The signed offset to the Ptr instruction.
675 int64_t Offset = 0;
676 LLT StoredType;
677};
678
679static bool tryOptimizeConsecStores(SmallVectorImpl<StoreInfo> &Stores,
680 CSEMIRBuilder &MIB) {
681 if (Stores.size() <= 2)
682 return false;
683
684 // Profitabity checks:
685 int64_t BaseOffset = Stores[0].Offset;
686 unsigned NumPairsExpected = Stores.size() / 2;
687 unsigned TotalInstsExpected = NumPairsExpected + (Stores.size() % 2);
688 // Size savings will depend on whether we can fold the offset, as an
689 // immediate of an ADD.
690 auto &TLI = *MIB.getMF().getSubtarget().getTargetLowering();
691 if (!TLI.isLegalAddImmediate(BaseOffset))
692 TotalInstsExpected++;
693 int SavingsExpected = Stores.size() - TotalInstsExpected;
694 if (SavingsExpected <= 0)
695 return false;
696
697 auto &MRI = MIB.getMF().getRegInfo();
698
699 // We have a series of consecutive stores. Factor out the common base
700 // pointer and rewrite the offsets.
701 Register NewBase = Stores[0].Ptr->getReg(Idx: 0);
702 for (auto &SInfo : Stores) {
703 // Compute a new pointer with the new base ptr and adjusted offset.
704 MIB.setInstrAndDebugLoc(*SInfo.St);
705 auto NewOff =
706 MIB.buildConstant(Res: LLT::integer(SizeInBits: 64), Val: SInfo.Offset - BaseOffset);
707 auto NewPtr = MIB.buildPtrAdd(Res: MRI.getType(Reg: SInfo.St->getPointerReg()),
708 Op0: NewBase, Op1: NewOff);
709 if (MIB.getObserver())
710 MIB.getObserver()->changingInstr(MI&: *SInfo.St);
711 SInfo.St->getOperand(i: 1).setReg(NewPtr.getReg(Idx: 0));
712 if (MIB.getObserver())
713 MIB.getObserver()->changedInstr(MI&: *SInfo.St);
714 }
715 LLVM_DEBUG(dbgs() << "Split a series of " << Stores.size()
716 << " stores into a base pointer and offsets.\n");
717 return true;
718}
719
720static cl::opt<bool>
721 EnableConsecutiveMemOpOpt("aarch64-postlegalizer-consecutive-memops",
722 cl::init(Val: true), cl::Hidden,
723 cl::desc("Enable consecutive memop optimization "
724 "in AArch64PostLegalizerCombiner"));
725
726static bool optimizeConsecutiveMemOpAddressing(MachineFunction &MF,
727 CSEMIRBuilder &MIB) {
728 // This combine needs to run after all reassociations/folds on pointer
729 // addressing have been done, specifically those that combine two G_PTR_ADDs
730 // with constant offsets into a single G_PTR_ADD with a combined offset.
731 // The goal of this optimization is to undo that combine in the case where
732 // doing so has prevented the formation of pair stores due to illegal
733 // addressing modes of STP. The reason that we do it here is because
734 // it's much easier to undo the transformation of a series consecutive
735 // mem ops, than it is to detect when doing it would be a bad idea looking
736 // at a single G_PTR_ADD in the reassociation/ptradd_immed_chain combine.
737 //
738 // An example:
739 // G_STORE %11:_(<2 x s64>), %base:_(p0) :: (store (<2 x s64>), align 1)
740 // %off1:_(s64) = G_CONSTANT i64 4128
741 // %p1:_(p0) = G_PTR_ADD %0:_, %off1:_(s64)
742 // G_STORE %11:_(<2 x s64>), %p1:_(p0) :: (store (<2 x s64>), align 1)
743 // %off2:_(s64) = G_CONSTANT i64 4144
744 // %p2:_(p0) = G_PTR_ADD %0:_, %off2:_(s64)
745 // G_STORE %11:_(<2 x s64>), %p2:_(p0) :: (store (<2 x s64>), align 1)
746 // %off3:_(s64) = G_CONSTANT i64 4160
747 // %p3:_(p0) = G_PTR_ADD %0:_, %off3:_(s64)
748 // G_STORE %11:_(<2 x s64>), %17:_(p0) :: (store (<2 x s64>), align 1)
749 bool Changed = false;
750 auto &MRI = MF.getRegInfo();
751
752 if (!EnableConsecutiveMemOpOpt)
753 return Changed;
754
755 SmallVector<StoreInfo, 8> Stores;
756 // If we see a load, then we keep track of any values defined by it.
757 // In the following example, STP formation will fail anyway because
758 // the latter store is using a load result that appears after the
759 // the prior store. In this situation if we factor out the offset then
760 // we increase code size for no benefit.
761 // G_STORE %v1:_(s64), %base:_(p0) :: (store (s64))
762 // %v2:_(s64) = G_LOAD %ldptr:_(p0) :: (load (s64))
763 // G_STORE %v2:_(s64), %base:_(p0) :: (store (s64))
764 SmallVector<Register> LoadValsSinceLastStore;
765
766 auto storeIsValid = [&](StoreInfo &Last, StoreInfo New) {
767 // Check if this store is consecutive to the last one.
768 if (Last.Ptr->getBaseReg() != New.Ptr->getBaseReg() ||
769 (Last.Offset + static_cast<int64_t>(Last.StoredType.getSizeInBytes()) !=
770 New.Offset) ||
771 Last.StoredType != New.StoredType)
772 return false;
773
774 // Check if this store is using a load result that appears after the
775 // last store. If so, bail out.
776 if (any_of(Range&: LoadValsSinceLastStore, P: [&](Register LoadVal) {
777 return New.St->getValueReg() == LoadVal;
778 }))
779 return false;
780
781 // Check if the current offset would be too large for STP.
782 // If not, then STP formation should be able to handle it, so we don't
783 // need to do anything.
784 int64_t MaxLegalOffset;
785 switch (New.StoredType.getSizeInBits()) {
786 case 32:
787 MaxLegalOffset = 252;
788 break;
789 case 64:
790 MaxLegalOffset = 504;
791 break;
792 case 128:
793 MaxLegalOffset = 1008;
794 break;
795 default:
796 llvm_unreachable("Unexpected stored type size");
797 }
798 if (New.Offset < MaxLegalOffset)
799 return false;
800
801 // If factoring it out still wouldn't help then don't bother.
802 return New.Offset - Stores[0].Offset <= MaxLegalOffset;
803 };
804
805 auto resetState = [&]() {
806 Stores.clear();
807 LoadValsSinceLastStore.clear();
808 };
809
810 for (auto &MBB : MF) {
811 // We're looking inside a single BB at a time since the memset pattern
812 // should only be in a single block.
813 resetState();
814 for (auto &MI : MBB) {
815 // Skip for scalable vectors
816 if (auto *LdSt = dyn_cast<GLoadStore>(Val: &MI);
817 LdSt && MRI.getType(Reg: LdSt->getOperand(i: 0).getReg()).isScalableVector())
818 continue;
819
820 if (auto *St = dyn_cast<GStore>(Val: &MI)) {
821 Register PtrBaseReg;
822 APInt Offset;
823 LLT StoredValTy = MRI.getType(Reg: St->getValueReg());
824 unsigned ValSize = StoredValTy.getSizeInBits();
825 if (ValSize < 32 || St->getMMO().getSizeInBits() != ValSize)
826 continue;
827
828 Register PtrReg = St->getPointerReg();
829 if (mi_match(
830 R: PtrReg, MRI,
831 P: m_OneNonDBGUse(SP: m_GPtrAdd(L: m_Reg(R&: PtrBaseReg), R: m_ICst(Cst&: Offset))))) {
832 GPtrAdd *PtrAdd = cast<GPtrAdd>(Val: MRI.getVRegDef(Reg: PtrReg));
833 StoreInfo New = {.St: St, .Ptr: PtrAdd, .Offset: Offset.getSExtValue(), .StoredType: StoredValTy};
834
835 if (Stores.empty()) {
836 Stores.push_back(Elt: New);
837 continue;
838 }
839
840 // Check if this store is a valid continuation of the sequence.
841 auto &Last = Stores.back();
842 if (storeIsValid(Last, New)) {
843 Stores.push_back(Elt: New);
844 LoadValsSinceLastStore.clear(); // Reset the load value tracking.
845 } else {
846 // The store isn't a valid to consider for the prior sequence,
847 // so try to optimize what we have so far and start a new sequence.
848 Changed |= tryOptimizeConsecStores(Stores, MIB);
849 resetState();
850 Stores.push_back(Elt: New);
851 }
852 }
853 } else if (auto *Ld = dyn_cast<GLoad>(Val: &MI)) {
854 LoadValsSinceLastStore.push_back(Elt: Ld->getDstReg());
855 }
856 }
857 Changed |= tryOptimizeConsecStores(Stores, MIB);
858 resetState();
859 }
860
861 return Changed;
862}
863
864bool runCombiner(MachineFunction &MF, GISelCSEInfo *CSEInfo,
865 GISelValueTracking *VT, MachineDominatorTree *MDT,
866 const AArch64PostLegalizerCombinerImplRuleConfig &RuleConfig,
867 bool EnableOpt, bool IsOptNone) {
868 if (MF.getProperties().hasFailedISel())
869 return false;
870 const Function &F = MF.getFunction();
871
872 const AArch64Subtarget &ST = MF.getSubtarget<AArch64Subtarget>();
873 const LegalizerInfo *LI = ST.getLegalizerInfo();
874
875 CombinerInfo CInfo(/*AllowIllegalOps=*/false, /*ShouldLegalizeIllegal=*/false,
876 /*LegalizerInfo=*/LI, EnableOpt, F.hasOptSize(),
877 F.hasMinSize());
878 // Disable fixed-point iteration to reduce compile-time
879 CInfo.MaxIterations = 1;
880 CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass;
881 // Legalizer performs DCE, so a full DCE pass is unnecessary.
882 CInfo.EnableFullDCE = false;
883 AArch64PostLegalizerCombinerImpl Impl(MF, CInfo, *VT, CSEInfo, RuleConfig, ST,
884 MDT, LI);
885 bool Changed = Impl.combineMachineInstrs();
886
887 CSEMIRBuilder MIB(MF);
888 MIB.setCSEInfo(CSEInfo);
889 Changed |= optimizeConsecutiveMemOpAddressing(MF, MIB);
890 return Changed;
891}
892
893class AArch64PostLegalizerCombinerLegacy : public MachineFunctionPass {
894public:
895 static char ID;
896
897 AArch64PostLegalizerCombinerLegacy(bool IsOptNone = false);
898
899 StringRef getPassName() const override {
900 return "AArch64PostLegalizerCombiner";
901 }
902
903 bool runOnMachineFunction(MachineFunction &MF) override;
904 void getAnalysisUsage(AnalysisUsage &AU) const override;
905
906 MachineFunctionProperties getRequiredProperties() const override {
907 return MachineFunctionProperties().set(
908 MachineFunctionProperties::Property::Legalized);
909 }
910
911private:
912 bool IsOptNone;
913 AArch64PostLegalizerCombinerImplRuleConfig RuleConfig;
914};
915} // end anonymous namespace
916
917void AArch64PostLegalizerCombinerLegacy::getAnalysisUsage(
918 AnalysisUsage &AU) const {
919 AU.setPreservesCFG();
920 getSelectionDAGFallbackAnalysisUsage(AU);
921 AU.addRequired<GISelValueTrackingAnalysisLegacy>();
922 AU.addPreserved<GISelValueTrackingAnalysisLegacy>();
923 if (!IsOptNone) {
924 AU.addRequired<MachineDominatorTreeWrapperPass>();
925 AU.addRequired<GISelCSEAnalysisWrapperPass>();
926 AU.addPreserved<GISelCSEAnalysisWrapperPass>();
927 }
928 MachineFunctionPass::getAnalysisUsage(AU);
929}
930
931AArch64PostLegalizerCombinerLegacy::AArch64PostLegalizerCombinerLegacy(
932 bool IsOptNone)
933 : MachineFunctionPass(ID), IsOptNone(IsOptNone) {
934 if (!RuleConfig.parseCommandLineOption())
935 reportFatalUsageError(reason: "Invalid rule identifier");
936}
937
938bool AArch64PostLegalizerCombinerLegacy::runOnMachineFunction(
939 MachineFunction &MF) {
940 if (MF.getProperties().hasFailedISel())
941 return false;
942
943 GISelValueTracking *VT =
944 &getAnalysis<GISelValueTrackingAnalysisLegacy>().get(MF);
945 MachineDominatorTree *MDT =
946 IsOptNone ? nullptr
947 : &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
948 GISelCSEAnalysisWrapper &Wrapper =
949 getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
950 auto *CSEInfo =
951 &Wrapper.get(CSEOpt: getStandardCSEConfigForOpt(Level: MF.getTarget().getOptLevel()));
952
953 bool EnableOpt = MF.getTarget().getOptLevel() != CodeGenOptLevel::None &&
954 !skipFunction(F: MF.getFunction());
955
956 return runCombiner(MF, CSEInfo, VT, MDT, RuleConfig, EnableOpt, IsOptNone);
957}
958
959char AArch64PostLegalizerCombinerLegacy::ID = 0;
960INITIALIZE_PASS_BEGIN(AArch64PostLegalizerCombinerLegacy, DEBUG_TYPE,
961 "Combine AArch64 MachineInstrs after legalization", false,
962 false)
963INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy)
964INITIALIZE_PASS_END(AArch64PostLegalizerCombinerLegacy, DEBUG_TYPE,
965 "Combine AArch64 MachineInstrs after legalization", false,
966 false)
967
968AArch64PostLegalizerCombinerPass::AArch64PostLegalizerCombinerPass(
969 const AArch64TargetMachine *TM)
970 : RuleConfig(
971 std::make_unique<AArch64PostLegalizerCombinerImplRuleConfig>()),
972 TM(TM) {
973 if (!RuleConfig->parseCommandLineOption())
974 reportFatalUsageError(reason: "invalid rule identifier");
975}
976
977AArch64PostLegalizerCombinerPass::AArch64PostLegalizerCombinerPass(
978 AArch64PostLegalizerCombinerPass &&) = default;
979
980AArch64PostLegalizerCombinerPass::~AArch64PostLegalizerCombinerPass() = default;
981
982PreservedAnalyses
983AArch64PostLegalizerCombinerPass::run(MachineFunction &MF,
984 MachineFunctionAnalysisManager &MFAM) {
985 if (MF.getProperties().hasFailedISel())
986 return PreservedAnalyses::all();
987
988 const bool IsOptNone = TM->isGlobalISelOptNone();
989 bool EnableOpt = !IsOptNone;
990
991 GISelValueTracking *VT = &MFAM.getResult<GISelValueTrackingAnalysis>(IR&: MF);
992 MachineDominatorTree *MDT =
993 IsOptNone ? nullptr : &MFAM.getResult<MachineDominatorTreeAnalysis>(IR&: MF);
994 GISelCSEInfo *CSEInfo = MFAM.getResult<GISelCSEAnalysis>(IR&: MF).get();
995
996 if (!runCombiner(MF, CSEInfo, VT, MDT, RuleConfig: *RuleConfig, EnableOpt, IsOptNone))
997 return PreservedAnalyses::all();
998
999 PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
1000 PA.preserveSet<CFGAnalyses>();
1001 PA.preserve<GISelValueTrackingAnalysis>();
1002 PA.preserve<GISelCSEAnalysis>();
1003 return PA;
1004}
1005
1006namespace llvm {
1007FunctionPass *createAArch64PostLegalizerCombinerLegacy(bool IsOptNone) {
1008 return new AArch64PostLegalizerCombinerLegacy(IsOptNone);
1009}
1010} // end namespace llvm
1011