1//=== AArch64PostLegalizerCombiner.cpp --------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// Post-legalization combines on generic MachineInstrs.
11///
12/// The combines here must preserve instruction legality.
13///
14/// Lowering combines (e.g. pseudo matching) should be handled by
15/// AArch64PostLegalizerLowering.
16///
17/// Combines which don't rely on instruction legality should go in the
18/// AArch64PreLegalizerCombiner.
19///
20//===----------------------------------------------------------------------===//
21
22#include "AArch64.h"
23#include "AArch64TargetMachine.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
26#include "llvm/CodeGen/GlobalISel/CSEMIRBuilder.h"
27#include "llvm/CodeGen/GlobalISel/Combiner.h"
28#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
29#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
30#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
31#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
32#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h"
33#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
34#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
35#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
36#include "llvm/CodeGen/GlobalISel/Utils.h"
37#include "llvm/CodeGen/MachineDominators.h"
38#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
39#include "llvm/CodeGen/MachineFunctionPass.h"
40#include "llvm/CodeGen/MachinePassManager.h"
41#include "llvm/CodeGen/MachineRegisterInfo.h"
42#include "llvm/CodeGen/TargetOpcodes.h"
43#include "llvm/Support/Debug.h"
44
45#define GET_GICOMBINER_DEPS
46#include "AArch64GenPostLegalizeGICombiner.inc"
47#undef GET_GICOMBINER_DEPS
48
49#define DEBUG_TYPE "aarch64-postlegalizer-combiner"
50
51using namespace llvm;
52using namespace MIPatternMatch;
53
54#define GET_GICOMBINER_TYPES
55#include "AArch64GenPostLegalizeGICombiner.inc"
56#undef GET_GICOMBINER_TYPES
57
58namespace {
59
60/// This combine tries do what performExtractVectorEltCombine does in SDAG.
61/// Rewrite for pairwise fadd pattern
62/// (s32 (g_extract_vector_elt
63/// (g_fadd (vXs32 Other)
64/// (g_vector_shuffle (vXs32 Other) undef <1,X,...> )) 0))
65/// ->
66/// (s32 (g_fadd (g_extract_vector_elt (vXs32 Other) 0)
67/// (g_extract_vector_elt (vXs32 Other) 1))
68bool matchExtractVecEltPairwiseAdd(
69 MachineInstr &MI, MachineRegisterInfo &MRI,
70 std::tuple<unsigned, LLT, Register> &MatchInfo) {
71 Register Src1 = MI.getOperand(i: 1).getReg();
72 Register Src2 = MI.getOperand(i: 2).getReg();
73 LLT DstTy = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
74
75 auto Cst = getIConstantVRegValWithLookThrough(VReg: Src2, MRI);
76 if (!Cst || Cst->Value != 0)
77 return false;
78 // SDAG also checks for FullFP16, but this looks to be beneficial anyway.
79
80 // Now check for an fadd operation. TODO: expand this for integer add?
81 auto *FAddMI = getOpcodeDef(Opcode: TargetOpcode::G_FADD, Reg: Src1, MRI);
82 if (!FAddMI)
83 return false;
84
85 // If we add support for integer add, must restrict these types to just s64.
86 unsigned DstSize = DstTy.getSizeInBits();
87 if (DstSize != 16 && DstSize != 32 && DstSize != 64)
88 return false;
89
90 Register Src1Op1 = FAddMI->getOperand(i: 1).getReg();
91 Register Src1Op2 = FAddMI->getOperand(i: 2).getReg();
92 MachineInstr *Shuffle =
93 getOpcodeDef(Opcode: TargetOpcode::G_SHUFFLE_VECTOR, Reg: Src1Op2, MRI);
94 MachineInstr *Other = MRI.getVRegDef(Reg: Src1Op1);
95 if (!Shuffle) {
96 Shuffle = getOpcodeDef(Opcode: TargetOpcode::G_SHUFFLE_VECTOR, Reg: Src1Op1, MRI);
97 Other = MRI.getVRegDef(Reg: Src1Op2);
98 }
99
100 // We're looking for a shuffle that moves the second element to index 0.
101 if (Shuffle && Shuffle->getOperand(i: 3).getShuffleMask()[0] == 1 &&
102 Other == MRI.getVRegDef(Reg: Shuffle->getOperand(i: 1).getReg())) {
103 std::get<0>(t&: MatchInfo) = TargetOpcode::G_FADD;
104 std::get<1>(t&: MatchInfo) = DstTy;
105 std::get<2>(t&: MatchInfo) = Other->getOperand(i: 0).getReg();
106 return true;
107 }
108 return false;
109}
110
111void applyExtractVecEltPairwiseAdd(
112 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
113 std::tuple<unsigned, LLT, Register> &MatchInfo) {
114 unsigned Opc = std::get<0>(t&: MatchInfo);
115 assert(Opc == TargetOpcode::G_FADD && "Unexpected opcode!");
116 // We want to generate two extracts of elements 0 and 1, and add them.
117 LLT Ty = std::get<1>(t&: MatchInfo);
118 Register Src = std::get<2>(t&: MatchInfo);
119 LLT s64 = LLT::integer(SizeInBits: 64);
120 B.setInstrAndDebugLoc(MI);
121 auto Elt0 = B.buildExtractVectorElement(Res: Ty, Val: Src, Idx: B.buildConstant(Res: s64, Val: 0));
122 auto Elt1 = B.buildExtractVectorElement(Res: Ty, Val: Src, Idx: B.buildConstant(Res: s64, Val: 1));
123 B.buildInstr(Opc, DstOps: {MI.getOperand(i: 0).getReg()}, SrcOps: {Elt0, Elt1});
124 MI.eraseFromParent();
125}
126
127bool isSignExtended(Register R, MachineRegisterInfo &MRI) {
128 // TODO: check if extended build vector as well.
129 return mi_match(R, MRI, P: m_GSExt(Src: m_Reg())) ||
130 mi_match(R, MRI, P: m_GSExtInReg(Src: m_Reg()));
131}
132
133bool isZeroExtended(Register R, MachineRegisterInfo &MRI) {
134 // TODO: check if extended build vector as well.
135 return mi_match(R, MRI, P: m_GZExt(Src: m_Reg()));
136}
137
138bool matchAArch64MulConstCombine(
139 MachineInstr &MI, MachineRegisterInfo &MRI,
140 std::function<void(MachineIRBuilder &B, Register DstReg)> &ApplyFn) {
141 assert(MI.getOpcode() == TargetOpcode::G_MUL);
142 Register LHS = MI.getOperand(i: 1).getReg();
143 Register RHS = MI.getOperand(i: 2).getReg();
144 Register Dst = MI.getOperand(i: 0).getReg();
145 const LLT Ty = MRI.getType(Reg: LHS);
146
147 // The below optimizations require a constant RHS.
148 auto Const = getIConstantVRegValWithLookThrough(VReg: RHS, MRI);
149 if (!Const)
150 return false;
151
152 APInt ConstValue = Const->Value.sext(width: Ty.getSizeInBits());
153 // The following code is ported from AArch64ISelLowering.
154 // Multiplication of a power of two plus/minus one can be done more
155 // cheaply as shift+add/sub. For now, this is true unilaterally. If
156 // future CPUs have a cheaper MADD instruction, this may need to be
157 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
158 // 64-bit is 5 cycles, so this is always a win.
159 // More aggressively, some multiplications N0 * C can be lowered to
160 // shift+add+shift if the constant C = A * B where A = 2^N + 1 and B = 2^M,
161 // e.g. 6=3*2=(2+1)*2.
162 // TODO: consider lowering more cases, e.g. C = 14, -6, -14 or even 45
163 // which equals to (1+2)*16-(1+2).
164 // TrailingZeroes is used to test if the mul can be lowered to
165 // shift+add+shift.
166 unsigned TrailingZeroes = ConstValue.countr_zero();
167 if (TrailingZeroes) {
168 // Conservatively do not lower to shift+add+shift if the mul might be
169 // folded into smul or umul.
170 if (MRI.hasOneNonDBGUse(RegNo: LHS) &&
171 (isSignExtended(R: LHS, MRI) || isZeroExtended(R: LHS, MRI)))
172 return false;
173 // Conservatively do not lower to shift+add+shift if the mul might be
174 // folded into madd or msub.
175 if (MRI.hasOneNonDBGUse(RegNo: Dst)) {
176 MachineInstr &UseMI = *MRI.use_instr_begin(RegNo: Dst);
177 unsigned UseOpc = UseMI.getOpcode();
178 if (UseOpc == TargetOpcode::G_ADD || UseOpc == TargetOpcode::G_PTR_ADD ||
179 UseOpc == TargetOpcode::G_SUB)
180 return false;
181 }
182 }
183 // Use ShiftedConstValue instead of ConstValue to support both shift+add/sub
184 // and shift+add+shift.
185 APInt ShiftedConstValue = ConstValue.ashr(ShiftAmt: TrailingZeroes);
186
187 unsigned ShiftAmt, AddSubOpc;
188 // Is the shifted value the LHS operand of the add/sub?
189 bool ShiftValUseIsLHS = true;
190 // Do we need to negate the result?
191 bool NegateResult = false;
192
193 if (ConstValue.isNonNegative()) {
194 // (mul x, 2^N + 1) => (add (shl x, N), x)
195 // (mul x, 2^N - 1) => (sub (shl x, N), x)
196 // (mul x, (2^N + 1) * 2^M) => (shl (add (shl x, N), x), M)
197 APInt SCVMinus1 = ShiftedConstValue - 1;
198 APInt CVPlus1 = ConstValue + 1;
199 if (SCVMinus1.isPowerOf2()) {
200 ShiftAmt = SCVMinus1.logBase2();
201 AddSubOpc = TargetOpcode::G_ADD;
202 } else if (CVPlus1.isPowerOf2()) {
203 ShiftAmt = CVPlus1.logBase2();
204 AddSubOpc = TargetOpcode::G_SUB;
205 } else
206 return false;
207 } else {
208 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
209 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
210 APInt CVNegPlus1 = -ConstValue + 1;
211 APInt CVNegMinus1 = -ConstValue - 1;
212 if (CVNegPlus1.isPowerOf2()) {
213 ShiftAmt = CVNegPlus1.logBase2();
214 AddSubOpc = TargetOpcode::G_SUB;
215 ShiftValUseIsLHS = false;
216 } else if (CVNegMinus1.isPowerOf2()) {
217 ShiftAmt = CVNegMinus1.logBase2();
218 AddSubOpc = TargetOpcode::G_ADD;
219 NegateResult = true;
220 } else
221 return false;
222 }
223
224 if (NegateResult && TrailingZeroes)
225 return false;
226
227 ApplyFn = [=](MachineIRBuilder &B, Register DstReg) {
228 auto Shift = B.buildConstant(Res: LLT::integer(SizeInBits: 64), Val: ShiftAmt);
229 auto ShiftedVal = B.buildShl(Dst: Ty, Src0: LHS, Src1: Shift);
230
231 Register AddSubLHS = ShiftValUseIsLHS ? ShiftedVal.getReg(Idx: 0) : LHS;
232 Register AddSubRHS = ShiftValUseIsLHS ? LHS : ShiftedVal.getReg(Idx: 0);
233 auto Res = B.buildInstr(Opc: AddSubOpc, DstOps: {Ty}, SrcOps: {AddSubLHS, AddSubRHS});
234 assert(!(NegateResult && TrailingZeroes) &&
235 "NegateResult and TrailingZeroes cannot both be true for now.");
236 // Negate the result.
237 if (NegateResult) {
238 B.buildSub(Dst: DstReg, Src0: B.buildConstant(Res: Ty, Val: 0), Src1: Res);
239 return;
240 }
241 // Shift the result.
242 if (TrailingZeroes) {
243 B.buildShl(Dst: DstReg, Src0: Res,
244 Src1: B.buildConstant(Res: LLT::integer(SizeInBits: 64), Val: TrailingZeroes));
245 return;
246 }
247 B.buildCopy(Res: DstReg, Op: Res.getReg(Idx: 0));
248 };
249 return true;
250}
251
252void applyAArch64MulConstCombine(
253 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
254 std::function<void(MachineIRBuilder &B, Register DstReg)> &ApplyFn) {
255 B.setInstrAndDebugLoc(MI);
256 ApplyFn(B, MI.getOperand(i: 0).getReg());
257 MI.eraseFromParent();
258}
259
260/// Match a 128b store of zero and split it into two 64 bit stores, for
261/// size/performance reasons.
262bool matchSplitStoreZero128(MachineInstr &MI, MachineRegisterInfo &MRI) {
263 GStore &Store = cast<GStore>(Val&: MI);
264 if (!Store.isSimple())
265 return false;
266 LLT ValTy = MRI.getType(Reg: Store.getValueReg());
267 if (ValTy.isScalableVector())
268 return false;
269 if (!ValTy.isVector() || ValTy.getSizeInBits() != 128)
270 return false;
271 if (Store.getMemSizeInBits() != ValTy.getSizeInBits())
272 return false; // Don't split truncating stores.
273 if (!MRI.hasOneNonDBGUse(RegNo: Store.getValueReg()))
274 return false;
275 auto MaybeCst = isConstantOrConstantSplatVector(Def: Store.getValueReg(), MRI);
276 return MaybeCst && MaybeCst->isZero();
277}
278
279void applySplitStoreZero128(MachineInstr &MI, MachineRegisterInfo &MRI,
280 MachineIRBuilder &B,
281 GISelChangeObserver &Observer) {
282 B.setInstrAndDebugLoc(MI);
283 GStore &Store = cast<GStore>(Val&: MI);
284 assert(MRI.getType(Store.getValueReg()).isVector() &&
285 "Expected a vector store value");
286 LLT NewTy = LLT::integer(SizeInBits: 64);
287 Register PtrReg = Store.getPointerReg();
288 auto Zero = B.buildConstant(Res: NewTy, Val: 0);
289 auto HighPtr =
290 B.buildPtrAdd(Res: MRI.getType(Reg: PtrReg), Op0: PtrReg, Op1: B.buildConstant(Res: NewTy, Val: 8));
291 auto &MF = *MI.getMF();
292 auto *LowMMO = MF.getMachineMemOperand(MMO: &Store.getMMO(), Offset: 0, Ty: NewTy);
293 auto *HighMMO = MF.getMachineMemOperand(MMO: &Store.getMMO(), Offset: 8, Ty: NewTy);
294 B.buildStore(Val: Zero, Addr: PtrReg, MMO&: *LowMMO);
295 B.buildStore(Val: Zero, Addr: HighPtr, MMO&: *HighMMO);
296 Store.eraseFromParent();
297}
298
299bool matchOrToBSP(MachineInstr &MI, MachineRegisterInfo &MRI,
300 std::tuple<Register, Register, Register> &MatchInfo) {
301 const LLT DstTy = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
302 if (!DstTy.isVector())
303 return false;
304
305 Register AO1, AO2, BVO1, BVO2;
306 if (!mi_match(MI, MRI,
307 P: m_GOr(L: m_GAnd(L: m_Reg(R&: AO1), R: m_Reg(R&: BVO1)),
308 R: m_GAnd(L: m_Reg(R&: AO2), R: m_Reg(R&: BVO2)))))
309 return false;
310
311 auto *BV1 = getOpcodeDef<GBuildVector>(Reg: BVO1, MRI);
312 auto *BV2 = getOpcodeDef<GBuildVector>(Reg: BVO2, MRI);
313 if (!BV1 || !BV2)
314 return false;
315
316 for (int I = 0, E = DstTy.getNumElements(); I < E; I++) {
317 auto ValAndVReg1 =
318 getIConstantVRegValWithLookThrough(VReg: BV1->getSourceReg(I), MRI);
319 auto ValAndVReg2 =
320 getIConstantVRegValWithLookThrough(VReg: BV2->getSourceReg(I), MRI);
321 if (!ValAndVReg1 || !ValAndVReg2 ||
322 ValAndVReg1->Value != ~ValAndVReg2->Value)
323 return false;
324 }
325
326 MatchInfo = {AO1, AO2, BVO1};
327 return true;
328}
329
330void applyOrToBSP(MachineInstr &MI, MachineRegisterInfo &MRI,
331 MachineIRBuilder &B,
332 std::tuple<Register, Register, Register> &MatchInfo) {
333 B.setInstrAndDebugLoc(MI);
334 B.buildInstr(
335 Opc: AArch64::G_BSP, DstOps: {MI.getOperand(i: 0).getReg()},
336 SrcOps: {std::get<2>(t&: MatchInfo), std::get<0>(t&: MatchInfo), std::get<1>(t&: MatchInfo)});
337 MI.eraseFromParent();
338}
339
340/// Match G_TRUNC (G_OR X, Y) => G_ADDHN X, Y when both inputs are sign
341/// extended from the result element type. The high half of the addition then
342/// equals the truncation of the OR.
343bool matchTruncOrToADDHN(MachineInstr &MI, MachineRegisterInfo &MRI,
344 GISelValueTracking *VT, Register Dst, Register Or,
345 Register Src0, Register Src1) {
346 if (!MRI.hasOneUse(RegNo: Or))
347 return false;
348
349 LLT DstTy = MRI.getType(Reg: Dst);
350 LLT SrcTy = MRI.getType(Reg: Or);
351 if (!((DstTy == LLT::fixed_vector(NumElements: 8, ScalarSizeInBits: 8) &&
352 SrcTy == LLT::fixed_vector(NumElements: 8, ScalarSizeInBits: 16)) ||
353 (DstTy == LLT::fixed_vector(NumElements: 4, ScalarSizeInBits: 16) &&
354 SrcTy == LLT::fixed_vector(NumElements: 4, ScalarSizeInBits: 32)) ||
355 (DstTy == LLT::fixed_vector(NumElements: 2, ScalarSizeInBits: 32) &&
356 SrcTy == LLT::fixed_vector(NumElements: 2, ScalarSizeInBits: 64))))
357 return false;
358
359 // If the narrow result is immediately any-extended back to the original type,
360 // the G_OR is cheaper than G_ADDHN followed by a vector widen.
361 if (MRI.hasOneNonDBGUse(RegNo: Dst)) {
362 MachineInstr &UseMI = *MRI.use_nodbg_instructions(Reg: Dst).begin();
363 if (UseMI.getOpcode() == TargetOpcode::G_ANYEXT &&
364 MRI.getType(Reg: UseMI.getOperand(i: 0).getReg()) == SrcTy)
365 return false;
366 }
367
368 unsigned EltSize = SrcTy.getScalarSizeInBits();
369 if (VT->computeNumSignBits(R: Src0) != EltSize ||
370 VT->computeNumSignBits(R: Src1) != EltSize)
371 return false;
372
373 return true;
374}
375
376// Combines Mul(And(Srl(X, 15), 0x10001), 0xffff) into CMLTz
377bool matchCombineMulCMLT(MachineInstr &MI, MachineRegisterInfo &MRI,
378 Register &SrcReg) {
379 LLT DstTy = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
380
381 if (DstTy != LLT::fixed_vector(NumElements: 2, ScalarSizeInBits: 64) && DstTy != LLT::fixed_vector(NumElements: 2, ScalarSizeInBits: 32) &&
382 DstTy != LLT::fixed_vector(NumElements: 4, ScalarSizeInBits: 32) && DstTy != LLT::fixed_vector(NumElements: 4, ScalarSizeInBits: 16) &&
383 DstTy != LLT::fixed_vector(NumElements: 8, ScalarSizeInBits: 16))
384 return false;
385
386 auto AndMI = getDefIgnoringCopies(Reg: MI.getOperand(i: 1).getReg(), MRI);
387 if (AndMI->getOpcode() != TargetOpcode::G_AND)
388 return false;
389 auto LShrMI = getDefIgnoringCopies(Reg: AndMI->getOperand(i: 1).getReg(), MRI);
390 if (LShrMI->getOpcode() != TargetOpcode::G_LSHR)
391 return false;
392
393 // Check the constant splat values
394 auto V1 = isConstantOrConstantSplatVector(Def: MI.getOperand(i: 2).getReg(), MRI);
395 auto V2 = isConstantOrConstantSplatVector(Def: AndMI->getOperand(i: 2).getReg(), MRI);
396 auto V3 =
397 isConstantOrConstantSplatVector(Def: LShrMI->getOperand(i: 2).getReg(), MRI);
398 if (!V1.has_value() || !V2.has_value() || !V3.has_value())
399 return false;
400 unsigned HalfSize = DstTy.getScalarSizeInBits() / 2;
401 if (!V1.value().isMask(numBits: HalfSize) || V2.value() != (1ULL | 1ULL << HalfSize) ||
402 V3 != (HalfSize - 1))
403 return false;
404
405 SrcReg = LShrMI->getOperand(i: 1).getReg();
406
407 return true;
408}
409
410void applyCombineMulCMLT(MachineInstr &MI, MachineRegisterInfo &MRI,
411 MachineIRBuilder &B, Register &SrcReg) {
412 Register DstReg = MI.getOperand(i: 0).getReg();
413 LLT DstTy = MRI.getType(Reg: DstReg);
414 LLT HalfTy = DstTy.changeElementCount(EC: DstTy.getElementCount() * 2)
415 .changeElementSize(NewEltSize: DstTy.getScalarSizeInBits() / 2);
416
417 Register ZeroVec = B.buildConstant(Res: HalfTy, Val: 0).getReg(Idx: 0);
418 Register CastReg =
419 B.buildInstr(Opc: TargetOpcode::G_BITCAST, DstOps: {HalfTy}, SrcOps: {SrcReg}).getReg(Idx: 0);
420 Register CMLTReg =
421 B.buildICmp(Pred: CmpInst::Predicate::ICMP_SLT, Res: HalfTy, Op0: CastReg, Op1: ZeroVec)
422 .getReg(Idx: 0);
423
424 B.buildInstr(Opc: TargetOpcode::G_BITCAST, DstOps: {DstReg}, SrcOps: {CMLTReg}).getReg(Idx: 0);
425 MI.eraseFromParent();
426}
427
428// Match mul({z/s}ext , {z/s}ext) => {u/s}mull
429bool matchExtMulToMULL(MachineInstr &MI, MachineRegisterInfo &MRI,
430 GISelValueTracking *KB,
431 std::tuple<bool, Register, Register> &MatchInfo) {
432 // Get the instructions that defined the source operand
433 LLT DstTy = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
434 MachineInstr *I1 = getDefIgnoringCopies(Reg: MI.getOperand(i: 1).getReg(), MRI);
435 MachineInstr *I2 = getDefIgnoringCopies(Reg: MI.getOperand(i: 2).getReg(), MRI);
436 unsigned I1Opc = I1->getOpcode();
437 unsigned I2Opc = I2->getOpcode();
438 unsigned EltSize = DstTy.getScalarSizeInBits();
439
440 if (!DstTy.isVector() || I1->getNumOperands() < 2 || I2->getNumOperands() < 2)
441 return false;
442
443 auto IsAtLeastDoubleExtend = [&](Register R) {
444 LLT Ty = MRI.getType(Reg: R);
445 return EltSize >= Ty.getScalarSizeInBits() * 2;
446 };
447
448 // If the source operands were EXTENDED before, then {U/S}MULL can be used
449 bool IsZExt1 =
450 I1Opc == TargetOpcode::G_ZEXT || I1Opc == TargetOpcode::G_ANYEXT;
451 bool IsZExt2 =
452 I2Opc == TargetOpcode::G_ZEXT || I2Opc == TargetOpcode::G_ANYEXT;
453 if (IsZExt1 && IsZExt2 && IsAtLeastDoubleExtend(I1->getOperand(i: 1).getReg()) &&
454 IsAtLeastDoubleExtend(I2->getOperand(i: 1).getReg())) {
455 get<0>(t&: MatchInfo) = true;
456 get<1>(t&: MatchInfo) = I1->getOperand(i: 1).getReg();
457 get<2>(t&: MatchInfo) = I2->getOperand(i: 1).getReg();
458 return true;
459 }
460
461 bool IsSExt1 =
462 I1Opc == TargetOpcode::G_SEXT || I1Opc == TargetOpcode::G_ANYEXT;
463 bool IsSExt2 =
464 I2Opc == TargetOpcode::G_SEXT || I2Opc == TargetOpcode::G_ANYEXT;
465 if (IsSExt1 && IsSExt2 && IsAtLeastDoubleExtend(I1->getOperand(i: 1).getReg()) &&
466 IsAtLeastDoubleExtend(I2->getOperand(i: 1).getReg())) {
467 get<0>(t&: MatchInfo) = false;
468 get<1>(t&: MatchInfo) = I1->getOperand(i: 1).getReg();
469 get<2>(t&: MatchInfo) = I2->getOperand(i: 1).getReg();
470 return true;
471 }
472
473 // Select UMULL if we can replace the other operand with an extend.
474 APInt Mask = APInt::getHighBitsSet(numBits: EltSize, hiBitsSet: EltSize / 2);
475 if (KB && (IsZExt1 || IsZExt2) &&
476 IsAtLeastDoubleExtend(IsZExt1 ? I1->getOperand(i: 1).getReg()
477 : I2->getOperand(i: 1).getReg())) {
478 Register ZExtOp =
479 IsZExt1 ? MI.getOperand(i: 2).getReg() : MI.getOperand(i: 1).getReg();
480 if (KB->maskedValueIsZero(Val: ZExtOp, Mask)) {
481 get<0>(t&: MatchInfo) = true;
482 get<1>(t&: MatchInfo) = IsZExt1 ? I1->getOperand(i: 1).getReg() : ZExtOp;
483 get<2>(t&: MatchInfo) = IsZExt1 ? ZExtOp : I2->getOperand(i: 1).getReg();
484 return true;
485 }
486 } else if (KB && DstTy == LLT::fixed_vector(NumElements: 2, ScalarSizeInBits: 64) &&
487 KB->maskedValueIsZero(Val: MI.getOperand(i: 1).getReg(), Mask) &&
488 KB->maskedValueIsZero(Val: MI.getOperand(i: 2).getReg(), Mask)) {
489 get<0>(t&: MatchInfo) = true;
490 get<1>(t&: MatchInfo) = MI.getOperand(i: 1).getReg();
491 get<2>(t&: MatchInfo) = MI.getOperand(i: 2).getReg();
492 return true;
493 }
494
495 if (KB && (IsSExt1 || IsSExt2) &&
496 IsAtLeastDoubleExtend(IsSExt1 ? I1->getOperand(i: 1).getReg()
497 : I2->getOperand(i: 1).getReg())) {
498 Register SExtOp =
499 IsSExt1 ? MI.getOperand(i: 2).getReg() : MI.getOperand(i: 1).getReg();
500 if (KB->computeNumSignBits(R: SExtOp) > EltSize / 2) {
501 get<0>(t&: MatchInfo) = false;
502 get<1>(t&: MatchInfo) = IsSExt1 ? I1->getOperand(i: 1).getReg() : SExtOp;
503 get<2>(t&: MatchInfo) = IsSExt1 ? SExtOp : I2->getOperand(i: 1).getReg();
504 return true;
505 }
506 } else if (KB && DstTy == LLT::fixed_vector(NumElements: 2, ScalarSizeInBits: 64) &&
507 KB->computeNumSignBits(R: MI.getOperand(i: 1).getReg()) > EltSize / 2 &&
508 KB->computeNumSignBits(R: MI.getOperand(i: 2).getReg()) > EltSize / 2) {
509 get<0>(t&: MatchInfo) = false;
510 get<1>(t&: MatchInfo) = MI.getOperand(i: 1).getReg();
511 get<2>(t&: MatchInfo) = MI.getOperand(i: 2).getReg();
512 return true;
513 }
514
515 return false;
516}
517
518void applyExtMulToMULL(MachineInstr &MI, MachineRegisterInfo &MRI,
519 MachineIRBuilder &B, GISelChangeObserver &Observer,
520 std::tuple<bool, Register, Register> &MatchInfo) {
521 assert(MI.getOpcode() == TargetOpcode::G_MUL &&
522 "Expected a G_MUL instruction");
523
524 // Get the instructions that defined the source operand
525 LLT DstTy = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
526 bool IsZExt = get<0>(t&: MatchInfo);
527 Register Src1Reg = get<1>(t&: MatchInfo);
528 Register Src2Reg = get<2>(t&: MatchInfo);
529 LLT Src1Ty = MRI.getType(Reg: Src1Reg);
530 LLT Src2Ty = MRI.getType(Reg: Src2Reg);
531 LLT HalfDstTy = DstTy.changeElementSize(NewEltSize: DstTy.getScalarSizeInBits() / 2);
532 unsigned ExtOpc = IsZExt ? TargetOpcode::G_ZEXT : TargetOpcode::G_SEXT;
533
534 if (Src1Ty.getScalarSizeInBits() * 2 != DstTy.getScalarSizeInBits())
535 Src1Reg = B.buildExtOrTrunc(ExtOpc, Res: {HalfDstTy}, Op: {Src1Reg}).getReg(Idx: 0);
536 if (Src2Ty.getScalarSizeInBits() * 2 != DstTy.getScalarSizeInBits())
537 Src2Reg = B.buildExtOrTrunc(ExtOpc, Res: {HalfDstTy}, Op: {Src2Reg}).getReg(Idx: 0);
538
539 B.buildInstr(Opc: IsZExt ? AArch64::G_UMULL : AArch64::G_SMULL,
540 DstOps: {MI.getOperand(i: 0).getReg()}, SrcOps: {Src1Reg, Src2Reg});
541 MI.eraseFromParent();
542}
543
544static bool matchSubAddMulReassoc(Register Mul1, Register Mul2, Register Sub,
545 Register Src, MachineRegisterInfo &MRI) {
546 if (!MRI.hasOneUse(RegNo: Sub))
547 return false;
548 if (getIConstantVRegValWithLookThrough(VReg: Src, MRI))
549 return false;
550 MachineInstr *M1 = getDefIgnoringCopies(Reg: Mul1, MRI);
551 if (M1->getOpcode() != AArch64::G_MUL &&
552 M1->getOpcode() != AArch64::G_SMULL &&
553 M1->getOpcode() != AArch64::G_UMULL)
554 return false;
555 MachineInstr *M2 = getDefIgnoringCopies(Reg: Mul2, MRI);
556 if (M2->getOpcode() != AArch64::G_MUL &&
557 M2->getOpcode() != AArch64::G_SMULL &&
558 M2->getOpcode() != AArch64::G_UMULL)
559 return false;
560 return true;
561}
562
563class AArch64PostLegalizerCombinerImpl : public Combiner {
564protected:
565 const CombinerHelper Helper;
566 const AArch64PostLegalizerCombinerImplRuleConfig &RuleConfig;
567 const AArch64Subtarget &STI;
568
569public:
570 AArch64PostLegalizerCombinerImpl(
571 MachineFunction &MF, CombinerInfo &CInfo, GISelValueTracking &VT,
572 GISelCSEInfo *CSEInfo,
573 const AArch64PostLegalizerCombinerImplRuleConfig &RuleConfig,
574 const AArch64Subtarget &STI, MachineDominatorTree *MDT,
575 const LegalizerInfo *LI);
576
577 static const char *getName() { return "AArch64PostLegalizerCombiner"; }
578
579 bool tryCombineAll(MachineInstr &I) const override;
580
581private:
582#define GET_GICOMBINER_CLASS_MEMBERS
583#include "AArch64GenPostLegalizeGICombiner.inc"
584#undef GET_GICOMBINER_CLASS_MEMBERS
585};
586
587#define GET_GICOMBINER_IMPL
588#include "AArch64GenPostLegalizeGICombiner.inc"
589#undef GET_GICOMBINER_IMPL
590
591AArch64PostLegalizerCombinerImpl::AArch64PostLegalizerCombinerImpl(
592 MachineFunction &MF, CombinerInfo &CInfo, GISelValueTracking &VT,
593 GISelCSEInfo *CSEInfo,
594 const AArch64PostLegalizerCombinerImplRuleConfig &RuleConfig,
595 const AArch64Subtarget &STI, MachineDominatorTree *MDT,
596 const LegalizerInfo *LI)
597 : Combiner(MF, CInfo, &VT, CSEInfo),
598 Helper(Observer, B, /*IsPreLegalize*/ false, &VT, MDT, LI),
599 RuleConfig(RuleConfig), STI(STI),
600#define GET_GICOMBINER_CONSTRUCTOR_INITS
601#include "AArch64GenPostLegalizeGICombiner.inc"
602#undef GET_GICOMBINER_CONSTRUCTOR_INITS
603{
604}
605
606struct StoreInfo {
607 GStore *St = nullptr;
608 // The G_PTR_ADD that's used by the store. We keep this to cache the
609 // MachineInstr def.
610 GPtrAdd *Ptr = nullptr;
611 // The signed offset to the Ptr instruction.
612 int64_t Offset = 0;
613 LLT StoredType;
614};
615
616static bool tryOptimizeConsecStores(SmallVectorImpl<StoreInfo> &Stores,
617 CSEMIRBuilder &MIB) {
618 if (Stores.size() <= 2)
619 return false;
620
621 // Profitabity checks:
622 int64_t BaseOffset = Stores[0].Offset;
623 unsigned NumPairsExpected = Stores.size() / 2;
624 unsigned TotalInstsExpected = NumPairsExpected + (Stores.size() % 2);
625 // Size savings will depend on whether we can fold the offset, as an
626 // immediate of an ADD.
627 auto &TLI = *MIB.getMF().getSubtarget().getTargetLowering();
628 if (!TLI.isLegalAddImmediate(BaseOffset))
629 TotalInstsExpected++;
630 int SavingsExpected = Stores.size() - TotalInstsExpected;
631 if (SavingsExpected <= 0)
632 return false;
633
634 auto &MRI = MIB.getMF().getRegInfo();
635
636 // We have a series of consecutive stores. Factor out the common base
637 // pointer and rewrite the offsets.
638 Register NewBase = Stores[0].Ptr->getReg(Idx: 0);
639 for (auto &SInfo : Stores) {
640 // Compute a new pointer with the new base ptr and adjusted offset.
641 MIB.setInstrAndDebugLoc(*SInfo.St);
642 auto NewOff =
643 MIB.buildConstant(Res: LLT::integer(SizeInBits: 64), Val: SInfo.Offset - BaseOffset);
644 auto NewPtr = MIB.buildPtrAdd(Res: MRI.getType(Reg: SInfo.St->getPointerReg()),
645 Op0: NewBase, Op1: NewOff);
646 if (MIB.getObserver())
647 MIB.getObserver()->changingInstr(MI&: *SInfo.St);
648 SInfo.St->getOperand(i: 1).setReg(NewPtr.getReg(Idx: 0));
649 if (MIB.getObserver())
650 MIB.getObserver()->changedInstr(MI&: *SInfo.St);
651 }
652 LLVM_DEBUG(dbgs() << "Split a series of " << Stores.size()
653 << " stores into a base pointer and offsets.\n");
654 return true;
655}
656
657static bool optimizeConsecutiveMemOpAddressing(MachineFunction &MF,
658 CSEMIRBuilder &MIB) {
659 // This combine needs to run after all reassociations/folds on pointer
660 // addressing have been done, specifically those that combine two G_PTR_ADDs
661 // with constant offsets into a single G_PTR_ADD with a combined offset.
662 // The goal of this optimization is to undo that combine in the case where
663 // doing so has prevented the formation of pair stores due to illegal
664 // addressing modes of STP. The reason that we do it here is because
665 // it's much easier to undo the transformation of a series consecutive
666 // mem ops, than it is to detect when doing it would be a bad idea looking
667 // at a single G_PTR_ADD in the reassociation/ptradd_immed_chain combine.
668 //
669 // An example:
670 // G_STORE %11:_(<2 x s64>), %base:_(p0) :: (store (<2 x s64>), align 1)
671 // %off1:_(s64) = G_CONSTANT i64 4128
672 // %p1:_(p0) = G_PTR_ADD %0:_, %off1:_(s64)
673 // G_STORE %11:_(<2 x s64>), %p1:_(p0) :: (store (<2 x s64>), align 1)
674 // %off2:_(s64) = G_CONSTANT i64 4144
675 // %p2:_(p0) = G_PTR_ADD %0:_, %off2:_(s64)
676 // G_STORE %11:_(<2 x s64>), %p2:_(p0) :: (store (<2 x s64>), align 1)
677 // %off3:_(s64) = G_CONSTANT i64 4160
678 // %p3:_(p0) = G_PTR_ADD %0:_, %off3:_(s64)
679 // G_STORE %11:_(<2 x s64>), %17:_(p0) :: (store (<2 x s64>), align 1)
680 bool Changed = false;
681 auto &MRI = MF.getRegInfo();
682
683 if (!MF.getSubtarget<AArch64Subtarget>()
684 .getCLOpts()
685 .postlegalizer_consecutive_memops)
686 return Changed;
687
688 SmallVector<StoreInfo, 8> Stores;
689 // If we see a load, then we keep track of any values defined by it.
690 // In the following example, STP formation will fail anyway because
691 // the latter store is using a load result that appears after the
692 // the prior store. In this situation if we factor out the offset then
693 // we increase code size for no benefit.
694 // G_STORE %v1:_(s64), %base:_(p0) :: (store (s64))
695 // %v2:_(s64) = G_LOAD %ldptr:_(p0) :: (load (s64))
696 // G_STORE %v2:_(s64), %base:_(p0) :: (store (s64))
697 SmallVector<Register> LoadValsSinceLastStore;
698
699 auto storeIsValid = [&](StoreInfo &Last, StoreInfo New) {
700 // Check if this store is consecutive to the last one.
701 if (Last.Ptr->getBaseReg() != New.Ptr->getBaseReg() ||
702 (Last.Offset + static_cast<int64_t>(Last.StoredType.getSizeInBytes()) !=
703 New.Offset) ||
704 Last.StoredType != New.StoredType)
705 return false;
706
707 // Check if this store is using a load result that appears after the
708 // last store. If so, bail out.
709 if (any_of(Range&: LoadValsSinceLastStore, P: [&](Register LoadVal) {
710 return New.St->getValueReg() == LoadVal;
711 }))
712 return false;
713
714 // Check if the current offset would be too large for STP.
715 // If not, then STP formation should be able to handle it, so we don't
716 // need to do anything.
717 int64_t MaxLegalOffset;
718 switch (New.StoredType.getSizeInBits()) {
719 case 32:
720 MaxLegalOffset = 252;
721 break;
722 case 64:
723 MaxLegalOffset = 504;
724 break;
725 case 128:
726 MaxLegalOffset = 1008;
727 break;
728 default:
729 llvm_unreachable("Unexpected stored type size");
730 }
731 if (New.Offset < MaxLegalOffset)
732 return false;
733
734 // If factoring it out still wouldn't help then don't bother.
735 return New.Offset - Stores[0].Offset <= MaxLegalOffset;
736 };
737
738 auto resetState = [&]() {
739 Stores.clear();
740 LoadValsSinceLastStore.clear();
741 };
742
743 for (auto &MBB : MF) {
744 // We're looking inside a single BB at a time since the memset pattern
745 // should only be in a single block.
746 resetState();
747 for (auto &MI : MBB) {
748 // Skip for scalable vectors
749 if (auto *LdSt = dyn_cast<GLoadStore>(Val: &MI);
750 LdSt && MRI.getType(Reg: LdSt->getOperand(i: 0).getReg()).isScalableVector())
751 continue;
752
753 if (auto *St = dyn_cast<GStore>(Val: &MI)) {
754 Register PtrBaseReg;
755 APInt Offset;
756 LLT StoredValTy = MRI.getType(Reg: St->getValueReg());
757 unsigned ValSize = StoredValTy.getSizeInBits();
758 if (ValSize < 32 || St->getMMO().getSizeInBits() != ValSize)
759 continue;
760
761 Register PtrReg = St->getPointerReg();
762 if (mi_match(
763 R: PtrReg, MRI,
764 P: m_OneNonDBGUse(SP: m_GPtrAdd(L: m_Reg(R&: PtrBaseReg), R: m_ICst(Cst&: Offset))))) {
765 GPtrAdd *PtrAdd = cast<GPtrAdd>(Val: MRI.getVRegDef(Reg: PtrReg));
766 StoreInfo New = {.St: St, .Ptr: PtrAdd, .Offset: Offset.getSExtValue(), .StoredType: StoredValTy};
767
768 if (Stores.empty()) {
769 Stores.push_back(Elt: New);
770 continue;
771 }
772
773 // Check if this store is a valid continuation of the sequence.
774 auto &Last = Stores.back();
775 if (storeIsValid(Last, New)) {
776 Stores.push_back(Elt: New);
777 LoadValsSinceLastStore.clear(); // Reset the load value tracking.
778 } else {
779 // The store isn't a valid to consider for the prior sequence,
780 // so try to optimize what we have so far and start a new sequence.
781 Changed |= tryOptimizeConsecStores(Stores, MIB);
782 resetState();
783 Stores.push_back(Elt: New);
784 }
785 }
786 } else if (auto *Ld = dyn_cast<GLoad>(Val: &MI)) {
787 LoadValsSinceLastStore.push_back(Elt: Ld->getDstReg());
788 }
789 }
790 Changed |= tryOptimizeConsecStores(Stores, MIB);
791 resetState();
792 }
793
794 return Changed;
795}
796
797bool runCombiner(MachineFunction &MF, GISelCSEInfo *CSEInfo,
798 GISelValueTracking *VT, MachineDominatorTree *MDT,
799 const AArch64PostLegalizerCombinerImplRuleConfig &RuleConfig,
800 bool EnableOpt, bool IsOptNone) {
801 if (MF.getProperties().hasFailedISel())
802 return false;
803 const Function &F = MF.getFunction();
804
805 const AArch64Subtarget &ST = MF.getSubtarget<AArch64Subtarget>();
806 const LegalizerInfo *LI = ST.getLegalizerInfo();
807
808 CombinerInfo CInfo(/*AllowIllegalOps=*/false, /*ShouldLegalizeIllegal=*/false,
809 /*LegalizerInfo=*/LI, EnableOpt, F.hasOptSize(),
810 F.hasMinSize());
811 // Disable fixed-point iteration to reduce compile-time
812 CInfo.MaxIterations = 1;
813 CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass;
814 // Legalizer performs DCE, so a full DCE pass is unnecessary.
815 CInfo.EnableFullDCE = false;
816 AArch64PostLegalizerCombinerImpl Impl(MF, CInfo, *VT, CSEInfo, RuleConfig, ST,
817 MDT, LI);
818 bool Changed = Impl.combineMachineInstrs();
819
820 CSEMIRBuilder MIB(MF);
821 MIB.setCSEInfo(CSEInfo);
822 Changed |= optimizeConsecutiveMemOpAddressing(MF, MIB);
823 return Changed;
824}
825
826class AArch64PostLegalizerCombinerLegacy : public MachineFunctionPass {
827public:
828 static char ID;
829
830 AArch64PostLegalizerCombinerLegacy(bool IsOptNone = false);
831
832 StringRef getPassName() const override {
833 return "AArch64PostLegalizerCombiner";
834 }
835
836 bool runOnMachineFunction(MachineFunction &MF) override;
837 void getAnalysisUsage(AnalysisUsage &AU) const override;
838
839 MachineFunctionProperties getRequiredProperties() const override {
840 return MachineFunctionProperties().set(
841 MachineFunctionProperties::Property::Legalized);
842 }
843
844private:
845 bool IsOptNone;
846 AArch64PostLegalizerCombinerImplRuleConfig RuleConfig;
847};
848} // end anonymous namespace
849
850void AArch64PostLegalizerCombinerLegacy::getAnalysisUsage(
851 AnalysisUsage &AU) const {
852 AU.setPreservesCFG();
853 getSelectionDAGFallbackAnalysisUsage(AU);
854 AU.addRequired<GISelValueTrackingAnalysisLegacy>();
855 AU.addPreserved<GISelValueTrackingAnalysisLegacy>();
856 if (!IsOptNone) {
857 AU.addRequired<MachineDominatorTreeWrapperPass>();
858 AU.addRequired<GISelCSEAnalysisWrapperPass>();
859 AU.addPreserved<GISelCSEAnalysisWrapperPass>();
860 }
861 MachineFunctionPass::getAnalysisUsage(AU);
862}
863
864AArch64PostLegalizerCombinerLegacy::AArch64PostLegalizerCombinerLegacy(
865 bool IsOptNone)
866 : MachineFunctionPass(ID), IsOptNone(IsOptNone) {
867 if (!RuleConfig.parseCommandLineOption())
868 reportFatalUsageError(reason: "Invalid rule identifier");
869}
870
871bool AArch64PostLegalizerCombinerLegacy::runOnMachineFunction(
872 MachineFunction &MF) {
873 if (MF.getProperties().hasFailedISel())
874 return false;
875
876 GISelValueTracking *VT =
877 &getAnalysis<GISelValueTrackingAnalysisLegacy>().get(MF);
878 MachineDominatorTree *MDT =
879 IsOptNone ? nullptr
880 : &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
881 GISelCSEAnalysisWrapper &Wrapper =
882 getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
883 auto *CSEInfo =
884 &Wrapper.get(CSEOpt: getStandardCSEConfigForOpt(Level: MF.getTarget().getOptLevel()));
885
886 bool EnableOpt = MF.getTarget().getOptLevel() != CodeGenOptLevel::None &&
887 !skipFunction(F: MF.getFunction());
888
889 return runCombiner(MF, CSEInfo, VT, MDT, RuleConfig, EnableOpt, IsOptNone);
890}
891
892char AArch64PostLegalizerCombinerLegacy::ID = 0;
893INITIALIZE_PASS_BEGIN(AArch64PostLegalizerCombinerLegacy, DEBUG_TYPE,
894 "Combine AArch64 MachineInstrs after legalization", false,
895 false)
896INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy)
897INITIALIZE_PASS_END(AArch64PostLegalizerCombinerLegacy, DEBUG_TYPE,
898 "Combine AArch64 MachineInstrs after legalization", false,
899 false)
900
901AArch64PostLegalizerCombinerPass::AArch64PostLegalizerCombinerPass(
902 const AArch64TargetMachine *TM)
903 : RuleConfig(
904 std::make_unique<AArch64PostLegalizerCombinerImplRuleConfig>()),
905 TM(TM) {
906 if (!RuleConfig->parseCommandLineOption())
907 reportFatalUsageError(reason: "invalid rule identifier");
908}
909
910AArch64PostLegalizerCombinerPass::AArch64PostLegalizerCombinerPass(
911 AArch64PostLegalizerCombinerPass &&) = default;
912
913AArch64PostLegalizerCombinerPass::~AArch64PostLegalizerCombinerPass() = default;
914
915PreservedAnalyses
916AArch64PostLegalizerCombinerPass::run(MachineFunction &MF,
917 MachineFunctionAnalysisManager &MFAM) {
918 if (MF.getProperties().hasFailedISel())
919 return PreservedAnalyses::all();
920
921 const bool IsOptNone = TM->isGlobalISelOptNone();
922 bool EnableOpt =
923 !IsOptNone && !shouldSkipOptimizationForOptBisect(IR: MF.getFunction());
924
925 GISelValueTracking *VT = &MFAM.getResult<GISelValueTrackingAnalysis>(IR&: MF);
926 MachineDominatorTree *MDT =
927 IsOptNone ? nullptr : &MFAM.getResult<MachineDominatorTreeAnalysis>(IR&: MF);
928 GISelCSEInfo *CSEInfo = MFAM.getResult<GISelCSEAnalysis>(IR&: MF).get();
929
930 if (!runCombiner(MF, CSEInfo, VT, MDT, RuleConfig: *RuleConfig, EnableOpt, IsOptNone))
931 return PreservedAnalyses::all();
932
933 PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
934 PA.preserveSet<CFGAnalyses>();
935 PA.preserve<GISelValueTrackingAnalysis>();
936 PA.preserve<GISelCSEAnalysis>();
937 return PA;
938}
939
940namespace llvm {
941FunctionPass *createAArch64PostLegalizerCombinerLegacy(bool IsOptNone) {
942 return new AArch64PostLegalizerCombinerLegacy(IsOptNone);
943}
944} // end namespace llvm
945