1//===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7// \file
8//===----------------------------------------------------------------------===//
9
10#include "AMDGPUInstPrinter.h"
11#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12#include "SIDefines.h"
13#include "Utils/AMDGPUAsmUtils.h"
14#include "Utils/AMDGPUBaseInfo.h"
15#include "llvm/ADT/StringExtras.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCExpr.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCInstrDesc.h"
20#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/TargetParser/AMDGPUTargetParser.h"
24
25using namespace llvm;
26using namespace llvm::AMDGPU;
27
28void AMDGPUInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) {
29 // FIXME: The current implementation of
30 // AsmParser::parseRegisterOrRegisterNumber in MC implies we either emit this
31 // as an integer or we provide a name which represents a physical register.
32 // For CFI instructions we really want to emit a name for the DWARF register
33 // instead, because there may be multiple DWARF registers corresponding to a
34 // single physical register. One case where this problem manifests is with
35 // wave32/wave64 where using the physical register name is ambiguous: if we
36 // write e.g. `.cfi_undefined v0` we lose information about the wavefront
37 // size which we need to encode the register in the final DWARF. Ideally we
38 // would extend MC to support parsing DWARF register names so we could do
39 // something like `.cfi_undefined dwarf_wave32_v0`. For now we just live with
40 // non-pretty DWARF register names in assembly text.
41 OS << Reg.id();
42}
43
44void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address,
45 StringRef Annot, const MCSubtargetInfo &STI,
46 raw_ostream &OS) {
47 printInstruction(MI, Address, STI, O&: OS);
48 printAnnotation(OS, Annot);
49}
50
51void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
52 const MCSubtargetInfo &STI,
53 raw_ostream &O) {
54 const MCOperand &Op = MI->getOperand(i: OpNo);
55 if (Op.isExpr()) {
56 MAI.printExpr(O, *Op.getExpr());
57 return;
58 }
59
60 // It's possible to end up with a 32-bit literal used with a 16-bit operand
61 // with ignored high bits. Print as 32-bit anyway in that case.
62 int64_t Imm = Op.getImm();
63 if (isInt<16>(x: Imm) || isUInt<16>(x: Imm))
64 O << formatHex(Value: static_cast<uint64_t>(Imm & 0xffff));
65 else
66 printU32ImmOperand(MI, OpNo, STI, O);
67}
68
69void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
70 raw_ostream &O) {
71 O << formatDec(Value: MI->getOperand(i: OpNo).getImm() & 0xffff);
72}
73
74void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
75 const MCSubtargetInfo &STI,
76 raw_ostream &O) {
77 const MCOperand &Op = MI->getOperand(i: OpNo);
78 if (Op.isExpr()) {
79 MAI.printExpr(O, *Op.getExpr());
80 return;
81 }
82
83 O << formatHex(Value: Op.getImm() & 0xffffffff);
84}
85
86void AMDGPUInstPrinter::printFP64ImmOperand(const MCInst *MI, unsigned OpNo,
87 const MCSubtargetInfo &STI,
88 raw_ostream &O) {
89 // KIMM64
90 const MCOperand &Op = MI->getOperand(i: OpNo);
91 if (Op.isExpr()) {
92 MAI.printExpr(O, *Op.getExpr());
93 return;
94 }
95
96 printLiteral64(Imm: Op.getImm(), O, /*IsFP=*/true);
97}
98
99void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
100 raw_ostream &O, StringRef BitName) {
101 if (MI->getOperand(i: OpNo).getImm()) {
102 O << ' ' << BitName;
103 }
104}
105
106void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
107 const MCSubtargetInfo &STI,
108 raw_ostream &O) {
109 uint32_t Imm = MI->getOperand(i: OpNo).getImm();
110 if (Imm != 0) {
111 O << " offset:";
112
113 // GFX12+ uses a 24-bit signed offset for VBUFFER.
114 bool IsVBuffer = SIInstrFlags::isBuffer(O: MII, O: *MI);
115 if (IsVBuffer && AMDGPU::isGFX12Plus(STI))
116 O << formatDec(Value: SignExtend32<24>(X: Imm));
117 else
118 printU16ImmDecOperand(MI, OpNo, O);
119 }
120}
121
122void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
123 const MCSubtargetInfo &STI,
124 raw_ostream &O) {
125 uint32_t Imm = MI->getOperand(i: OpNo).getImm();
126 if (Imm != 0) {
127 O << " offset:";
128
129 bool AllowNegative = SIInstrFlags::isSegmentSpecificFLAT(O: MII, O: *MI) ||
130 STI.hasFeature(Feature: AMDGPU::FeatureFlatSignedOffset);
131
132 if (AllowNegative) // Signed offset
133 O << formatDec(Value: SignExtend32(X: Imm, B: AMDGPU::getNumFlatOffsetBits(ST: STI)));
134 else // Unsigned offset
135 printU16ImmDecOperand(MI, OpNo, O);
136 }
137}
138
139void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
140 const MCSubtargetInfo &STI,
141 raw_ostream &O) {
142 printU32ImmOperand(MI, OpNo, STI, O);
143}
144
145void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
146 const MCSubtargetInfo &STI,
147 raw_ostream &O) {
148 O << formatHex(Value: MI->getOperand(i: OpNo).getImm());
149}
150
151void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
152 const MCSubtargetInfo &STI,
153 raw_ostream &O) {
154 printU32ImmOperand(MI, OpNo, STI, O);
155}
156
157void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo,
158 const MCSubtargetInfo &STI, raw_ostream &O) {
159 auto Imm = MI->getOperand(i: OpNo).getImm();
160
161 if (AMDGPU::isGFX12Plus(STI)) {
162 const int64_t TH = Imm & CPol::TH;
163 const int64_t Scope = Imm & CPol::SCOPE;
164
165 if (Imm & CPol::SCAL)
166 O << " scale_offset";
167
168 printTH(MI, TH, Scope, O);
169 printScope(Scope, O);
170
171 if (Imm & CPol::NV)
172 O << " nv";
173
174 return;
175 }
176
177 if (Imm & CPol::GLC)
178 O << ((AMDGPU::isGFX940(STI) && !SIInstrFlags::isSMRD(O: MII, O: *MI)) ? " sc0"
179 : " glc");
180 if (Imm & CPol::SLC)
181 O << (AMDGPU::isGFX940(STI) ? " nt" : " slc");
182 if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI))
183 O << " dlc";
184 if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI))
185 O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc");
186 if (Imm & ~CPol::ALL_pregfx12)
187 O << " /* unexpected cache policy bit */";
188}
189
190void AMDGPUInstPrinter::printTH(const MCInst *MI, int64_t TH, int64_t Scope,
191 raw_ostream &O) {
192 // For th = 0 do not print this field
193 if (TH == 0)
194 return;
195
196 const unsigned Opcode = MI->getOpcode();
197 const MCInstrDesc &TID = MII.get(Opcode);
198 unsigned THType = AMDGPU::getTemporalHintType(TID);
199 bool IsStore = (THType == AMDGPU::CPol::TH_TYPE_STORE);
200
201 O << " th:";
202
203 if (THType == AMDGPU::CPol::TH_TYPE_ATOMIC) {
204 O << "TH_ATOMIC_";
205 if (TH & AMDGPU::CPol::TH_ATOMIC_CASCADE) {
206 if (Scope >= AMDGPU::CPol::SCOPE_DEV)
207 O << "CASCADE" << (TH & AMDGPU::CPol::TH_ATOMIC_NT ? "_NT" : "_RT");
208 else
209 O << formatHex(Value: TH);
210 } else if (TH & AMDGPU::CPol::TH_ATOMIC_NT)
211 O << "NT" << (TH & AMDGPU::CPol::TH_ATOMIC_RETURN ? "_RETURN" : "");
212 else if (TH & AMDGPU::CPol::TH_ATOMIC_RETURN)
213 O << "RETURN";
214 else
215 O << formatHex(Value: TH);
216 } else {
217 if (!IsStore && TH == AMDGPU::CPol::TH_RESERVED)
218 O << formatHex(Value: TH);
219 else {
220 O << (IsStore ? "TH_STORE_" : "TH_LOAD_");
221 switch (TH) {
222 case AMDGPU::CPol::TH_NT:
223 O << "NT";
224 break;
225 case AMDGPU::CPol::TH_HT:
226 O << "HT";
227 break;
228 case AMDGPU::CPol::TH_BYPASS: // or LU or WB
229 O << (Scope == AMDGPU::CPol::SCOPE_SYS ? "BYPASS"
230 : (IsStore ? "WB" : "LU"));
231 break;
232 case AMDGPU::CPol::TH_NT_RT:
233 O << "NT_RT";
234 break;
235 case AMDGPU::CPol::TH_RT_NT:
236 O << "RT_NT";
237 break;
238 case AMDGPU::CPol::TH_NT_HT:
239 O << "NT_HT";
240 break;
241 case AMDGPU::CPol::TH_NT_WB:
242 O << "NT_WB";
243 break;
244 default:
245 llvm_unreachable("unexpected th value");
246 }
247 }
248 }
249}
250
251void AMDGPUInstPrinter::printScope(int64_t Scope, raw_ostream &O) {
252 if (Scope == CPol::SCOPE_CU)
253 return;
254
255 O << " scope:";
256
257 if (Scope == CPol::SCOPE_SE)
258 O << "SCOPE_SE";
259 else if (Scope == CPol::SCOPE_DEV)
260 O << "SCOPE_DEV";
261 else if (Scope == CPol::SCOPE_SYS)
262 O << "SCOPE_SYS";
263 else
264 llvm_unreachable("unexpected scope policy value");
265}
266
267void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
268 const MCSubtargetInfo &STI, raw_ostream &O) {
269 unsigned Dim = MI->getOperand(i: OpNo).getImm();
270 O << " dim:SQ_RSRC_IMG_";
271
272 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(DimEnc: Dim);
273 if (DimInfo)
274 O << AMDGPU::getMIMGDimInfoStr(DimInfo->AsmSuffix);
275 else
276 O << Dim;
277}
278
279void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo,
280 const MCSubtargetInfo &STI, raw_ostream &O) {
281 if (STI.hasFeature(Feature: AMDGPU::FeatureR128A16))
282 printNamedBit(MI, OpNo, O, BitName: "a16");
283 else
284 printNamedBit(MI, OpNo, O, BitName: "r128");
285}
286
287void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo,
288 const MCSubtargetInfo &STI,
289 raw_ostream &O) {
290}
291
292void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
293 const MCSubtargetInfo &STI,
294 raw_ostream &O) {
295 using namespace llvm::AMDGPU::MTBUFFormat;
296
297 int OpNo =
298 AMDGPU::getNamedOperandIdx(Opcode: MI->getOpcode(), Name: AMDGPU::OpName::format);
299 assert(OpNo != -1);
300
301 unsigned Val = MI->getOperand(i: OpNo).getImm();
302 if (AMDGPU::isGFX10Plus(STI)) {
303 if (Val == UFMT_DEFAULT)
304 return;
305 if (isValidUnifiedFormat(Val, STI)) {
306 O << " format:[" << getUnifiedFormatName(Id: Val, STI) << ']';
307 } else {
308 O << " format:" << Val;
309 }
310 } else {
311 if (Val == DFMT_NFMT_DEFAULT)
312 return;
313 if (isValidDfmtNfmt(Val, STI)) {
314 unsigned Dfmt;
315 unsigned Nfmt;
316 decodeDfmtNfmt(Format: Val, Dfmt, Nfmt);
317 O << " format:[";
318 if (Dfmt != DFMT_DEFAULT) {
319 O << getDfmtName(Id: Dfmt);
320 if (Nfmt != NFMT_DEFAULT) {
321 O << ',';
322 }
323 }
324 if (Nfmt != NFMT_DEFAULT) {
325 O << getNfmtName(Id: Nfmt, STI);
326 }
327 O << ']';
328 } else {
329 O << " format:" << Val;
330 }
331 }
332}
333
334// \returns a low 256 vgpr representing a high vgpr \p Reg [v256..v1023] or
335// \p Reg itself otherwise.
336static MCRegister getRegForPrinting(MCRegister Reg, const MCRegisterInfo &MRI) {
337 unsigned Enc = MRI.getEncodingValue(Reg);
338 unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;
339 if (Idx < 0x100)
340 return Reg;
341
342 unsigned RegNo = Idx % 0x100;
343 const MCRegisterClass *RC = getVGPRPhysRegClass(Reg, MRI);
344 if (RC->getID() == AMDGPU::VGPR_16RegClassID) {
345 // This class has 2048 registers with interleaved lo16 and hi16.
346 RegNo *= 2;
347 if (Enc & AMDGPU::HWEncoding::IS_HI16)
348 ++RegNo;
349 }
350
351 return RC->getRegister(i: RegNo);
352}
353
354// Restore MSBs of a VGPR above 255 from the MCInstrAnalysis.
355static MCRegister getRegFromMIA(MCRegister Reg, unsigned OpNo,
356 const MCInstrDesc &Desc,
357 const MCRegisterInfo &MRI,
358 const AMDGPUMCInstrAnalysis &MIA) {
359 unsigned VgprMSBs = MIA.getVgprMSBs();
360 if (!VgprMSBs)
361 return Reg;
362
363 unsigned Enc = MRI.getEncodingValue(Reg);
364 if (!(Enc & AMDGPU::HWEncoding::IS_VGPR))
365 return Reg;
366
367 auto Ops = AMDGPU::getVGPRLoweringOperandTables(Desc);
368 if (!Ops.first)
369 return Reg;
370 unsigned Opc = Desc.getOpcode();
371 unsigned I;
372 for (I = 0; I < 4; ++I) {
373 if (Ops.first[I] != AMDGPU::OpName::NUM_OPERAND_NAMES &&
374 (unsigned)AMDGPU::getNamedOperandIdx(Opcode: Opc, Name: Ops.first[I]) == OpNo)
375 break;
376 if (Ops.second && Ops.second[I] != AMDGPU::OpName::NUM_OPERAND_NAMES &&
377 (unsigned)AMDGPU::getNamedOperandIdx(Opcode: Opc, Name: Ops.second[I]) == OpNo)
378 break;
379 }
380 if (I == 4)
381 return Reg;
382 unsigned OpMSBs = (VgprMSBs >> (I * 2)) & 3;
383 if (!OpMSBs)
384 return Reg;
385 if (MCRegister NewReg = AMDGPU::getVGPRWithMSBs(Reg, MSBs: OpMSBs, MRI))
386 return NewReg;
387 return Reg;
388}
389
390void AMDGPUInstPrinter::printRsrcReg(const MCInst *MI, unsigned OpNo,
391 const MCSubtargetInfo &STI,
392 raw_ostream &O) {
393 MCRegister Reg = MI->getOperand(i: OpNo).getReg();
394 bool IsIndexReg = AMDGPU::isRsrcIndexReg(Reg, MRI);
395 if (IsIndexReg)
396 O << "rsrcidx(";
397 printRegOperand(Reg, Opc: MI->getOpcode(), OpNo, O, MRI);
398 if (IsIndexReg)
399 O << ')';
400}
401
402void AMDGPUInstPrinter::printRegOperand(MCRegister Reg, raw_ostream &O,
403 const MCRegisterInfo &MRI) {
404#if !defined(NDEBUG)
405 switch (Reg.id()) {
406 case AMDGPU::FP_REG:
407 case AMDGPU::SP_REG:
408 case AMDGPU::PRIVATE_RSRC_REG:
409 llvm_unreachable("pseudo-register should not ever be emitted");
410 default:
411 break;
412 }
413#endif
414
415 MCRegister PrintReg = getRegForPrinting(Reg, MRI);
416 O << getRegisterName(Reg: PrintReg);
417
418 if (PrintReg != Reg)
419 O << " /*" << getRegisterName(Reg) << "*/";
420}
421
422void AMDGPUInstPrinter::printRegOperand(MCRegister Reg, unsigned Opc,
423 unsigned OpNo, raw_ostream &O,
424 const MCRegisterInfo &MRI) {
425 if (MIA)
426 Reg = getRegFromMIA(Reg, OpNo, Desc: MII.get(Opcode: Opc), MRI,
427 MIA: *static_cast<const AMDGPUMCInstrAnalysis *>(MIA));
428 printRegOperand(Reg, O, MRI);
429}
430
431void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
432 const MCSubtargetInfo &STI, raw_ostream &O) {
433 auto Opcode = MI->getOpcode();
434 if (OpNo == 0) {
435 if (SIInstrFlags::isVOP3(O: MII, O: *MI) && SIInstrFlags::isDPP(O: MII, O: *MI))
436 O << "_e64_dpp";
437 else if (SIInstrFlags::isVOP3(O: MII, O: *MI)) {
438 if (!getVOP3IsSingle(Opc: Opcode))
439 O << "_e64";
440 } else if (SIInstrFlags::isDPP(O: MII, O: *MI))
441 O << "_dpp";
442 else if (SIInstrFlags::isSDWA(O: MII, O: *MI))
443 O << "_sdwa";
444 else if ((SIInstrFlags::isVOP1(O: MII, O: *MI) && !getVOP1IsSingle(Opc: Opcode)) ||
445 (SIInstrFlags::isVOP2(O: MII, O: *MI) && !getVOP2IsSingle(Opc: Opcode)))
446 O << "_e32";
447 O << " ";
448 }
449
450 printRegularOperand(MI, OpNo, STI, O);
451
452 // Print default vcc/vcc_lo operand.
453 switch (Opcode) {
454 default: break;
455
456 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
457 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
458 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
459 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
460 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
461 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
462 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
463 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
464 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
465 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
466 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
467 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
468 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
469 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
470 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
471 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
472 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
473 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
474 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
475 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
476 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
477 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx12:
478 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx12:
479 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx12:
480 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx12:
481 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx12:
482 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx12:
483 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx12:
484 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx12:
485 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx12:
486 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx13:
487 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx13:
488 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx13:
489 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx13:
490 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx13:
491 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx13:
492 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx13:
493 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx13:
494 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx13:
495 printDefaultVccOperand(FirstOperand: false, STI, O);
496 break;
497 }
498}
499
500void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
501 const MCSubtargetInfo &STI, raw_ostream &O) {
502 if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI))
503 O << " ";
504 else
505 O << "_e32 ";
506
507 printRegularOperand(MI, OpNo, STI, O);
508}
509
510void AMDGPUInstPrinter::printAVLdSt32Align2RegOp(const MCInst *MI,
511 unsigned OpNo,
512 const MCSubtargetInfo &STI,
513 raw_ostream &O) {
514 MCRegister Reg = MI->getOperand(i: OpNo).getReg();
515
516 // On targets with an even alignment requirement
517 if (MCRegister SubReg = MRI.getSubReg(Reg, Idx: AMDGPU::sub0))
518 Reg = SubReg;
519 printRegOperand(Reg, O, MRI);
520}
521
522void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm,
523 const MCSubtargetInfo &STI,
524 raw_ostream &O) {
525 int32_t SImm = static_cast<int32_t>(Imm);
526 if (isInlinableIntLiteral(Literal: SImm)) {
527 O << SImm;
528 return;
529 }
530
531 if (printImmediateFloat32(Imm, STI, O))
532 return;
533
534 O << formatHex(Value: static_cast<uint64_t>(Imm & 0xffff));
535}
536
537static bool printImmediateFP16(uint32_t Imm, const MCSubtargetInfo &STI,
538 raw_ostream &O) {
539 if (Imm == 0x3C00)
540 O << "1.0";
541 else if (Imm == 0xBC00)
542 O << "-1.0";
543 else if (Imm == 0x3800)
544 O << "0.5";
545 else if (Imm == 0xB800)
546 O << "-0.5";
547 else if (Imm == 0x4000)
548 O << "2.0";
549 else if (Imm == 0xC000)
550 O << "-2.0";
551 else if (Imm == 0x4400)
552 O << "4.0";
553 else if (Imm == 0xC400)
554 O << "-4.0";
555 else if (Imm == 0x3118 && STI.hasFeature(Feature: AMDGPU::FeatureInv2PiInlineImm))
556 O << "0.15915494";
557 else
558 return false;
559
560 return true;
561}
562
563static bool printImmediateBFloat16(uint32_t Imm, const MCSubtargetInfo &STI,
564 raw_ostream &O) {
565 if (Imm == 0x3F80)
566 O << "1.0";
567 else if (Imm == 0xBF80)
568 O << "-1.0";
569 else if (Imm == 0x3F00)
570 O << "0.5";
571 else if (Imm == 0xBF00)
572 O << "-0.5";
573 else if (Imm == 0x4000)
574 O << "2.0";
575 else if (Imm == 0xC000)
576 O << "-2.0";
577 else if (Imm == 0x4080)
578 O << "4.0";
579 else if (Imm == 0xC080)
580 O << "-4.0";
581 else if (Imm == 0x3E22 && STI.hasFeature(Feature: AMDGPU::FeatureInv2PiInlineImm))
582 O << "0.15915494";
583 else
584 return false;
585
586 return true;
587}
588
589void AMDGPUInstPrinter::printImmediateBF16(uint32_t Imm,
590 const MCSubtargetInfo &STI,
591 raw_ostream &O) {
592 int16_t SImm = static_cast<int16_t>(Imm);
593 if (isInlinableIntLiteral(Literal: SImm)) {
594 O << SImm;
595 return;
596 }
597
598 if (printImmediateBFloat16(Imm: static_cast<uint16_t>(Imm), STI, O))
599 return;
600
601 O << formatHex(Value: static_cast<uint64_t>(Imm));
602}
603
604void AMDGPUInstPrinter::printImmediateF16(uint32_t Imm,
605 const MCSubtargetInfo &STI,
606 raw_ostream &O) {
607 int16_t SImm = static_cast<int16_t>(Imm);
608 if (isInlinableIntLiteral(Literal: SImm)) {
609 O << SImm;
610 return;
611 }
612
613 uint16_t HImm = static_cast<uint16_t>(Imm);
614 if (printImmediateFP16(Imm: HImm, STI, O))
615 return;
616
617 uint64_t Imm16 = static_cast<uint16_t>(Imm);
618 O << formatHex(Value: Imm16);
619}
620
621void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm, uint8_t OpType,
622 const MCSubtargetInfo &STI,
623 raw_ostream &O) {
624 int32_t SImm = static_cast<int32_t>(Imm);
625 if (isInlinableIntLiteral(Literal: SImm)) {
626 O << SImm;
627 return;
628 }
629
630 switch (OpType) {
631 case AMDGPU::OPERAND_REG_IMM_V2INT16:
632 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
633 if (printImmediateFloat32(Imm, STI, O))
634 return;
635 break;
636 case AMDGPU::OPERAND_REG_IMM_V2FP16:
637 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
638 if (isUInt<16>(x: Imm) &&
639 printImmediateFP16(Imm: static_cast<uint16_t>(Imm), STI, O))
640 return;
641 break;
642 case AMDGPU::OPERAND_REG_IMM_V2FP16_SPLAT: {
643 if (AMDGPU::isGFX11Plus(STI)) {
644 // For GFX11+, the inline constant is duplicated to both channels, so we
645 // need to check if the low and high 16 bits are the same, and then if
646 // they can be printed as inline constant values.
647 uint16_t Lo16 = static_cast<uint16_t>(Imm & 0xFFFF);
648 uint16_t Hi16 = static_cast<uint16_t>((Imm >> 16) & 0xFFFF);
649 if (Lo16 == Hi16 &&
650 printImmediateFP16(Imm: static_cast<uint16_t>(Imm), STI, O))
651 return;
652 } else {
653 // For pre-GFX11, the inline constant is in the low 16 bits, so we need
654 // to check if it can be printed as inline constant value.
655 if (isUInt<16>(x: Imm) &&
656 printImmediateFP16(Imm: static_cast<uint16_t>(Imm), STI, O))
657 return;
658 }
659 break;
660 }
661 case AMDGPU::OPERAND_REG_IMM_V2BF16:
662 case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
663 if (isUInt<16>(x: Imm) &&
664 printImmediateBFloat16(Imm: static_cast<uint16_t>(Imm), STI, O))
665 return;
666 break;
667 case AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16:
668 break;
669 default:
670 llvm_unreachable("bad operand type");
671 }
672
673 O << formatHex(Value: static_cast<uint64_t>(Imm));
674}
675
676bool AMDGPUInstPrinter::printImmediateFloat32(uint32_t Imm,
677 const MCSubtargetInfo &STI,
678 raw_ostream &O) {
679 if (Imm == llvm::bit_cast<uint32_t>(from: 0.0f))
680 O << "0.0";
681 else if (Imm == llvm::bit_cast<uint32_t>(from: 1.0f))
682 O << "1.0";
683 else if (Imm == llvm::bit_cast<uint32_t>(from: -1.0f))
684 O << "-1.0";
685 else if (Imm == llvm::bit_cast<uint32_t>(from: 0.5f))
686 O << "0.5";
687 else if (Imm == llvm::bit_cast<uint32_t>(from: -0.5f))
688 O << "-0.5";
689 else if (Imm == llvm::bit_cast<uint32_t>(from: 2.0f))
690 O << "2.0";
691 else if (Imm == llvm::bit_cast<uint32_t>(from: -2.0f))
692 O << "-2.0";
693 else if (Imm == llvm::bit_cast<uint32_t>(from: 4.0f))
694 O << "4.0";
695 else if (Imm == llvm::bit_cast<uint32_t>(from: -4.0f))
696 O << "-4.0";
697 else if (Imm == 0x3e22f983 &&
698 STI.hasFeature(Feature: AMDGPU::FeatureInv2PiInlineImm))
699 O << "0.15915494";
700 else
701 return false;
702
703 return true;
704}
705
706void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
707 const MCSubtargetInfo &STI,
708 raw_ostream &O) {
709 int32_t SImm = static_cast<int32_t>(Imm);
710 if (isInlinableIntLiteral(Literal: SImm)) {
711 O << SImm;
712 return;
713 }
714
715 if (printImmediateFloat32(Imm, STI, O))
716 return;
717
718 O << formatHex(Value: static_cast<uint64_t>(Imm));
719}
720
721void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
722 const MCSubtargetInfo &STI,
723 raw_ostream &O, bool IsFP) {
724 int64_t SImm = static_cast<int64_t>(Imm);
725 if (SImm >= -16 && SImm <= 64) {
726 O << SImm;
727 return;
728 }
729
730 if (Imm == llvm::bit_cast<uint64_t>(from: 0.0))
731 O << "0.0";
732 else if (Imm == llvm::bit_cast<uint64_t>(from: 1.0))
733 O << "1.0";
734 else if (Imm == llvm::bit_cast<uint64_t>(from: -1.0))
735 O << "-1.0";
736 else if (Imm == llvm::bit_cast<uint64_t>(from: 0.5))
737 O << "0.5";
738 else if (Imm == llvm::bit_cast<uint64_t>(from: -0.5))
739 O << "-0.5";
740 else if (Imm == llvm::bit_cast<uint64_t>(from: 2.0))
741 O << "2.0";
742 else if (Imm == llvm::bit_cast<uint64_t>(from: -2.0))
743 O << "-2.0";
744 else if (Imm == llvm::bit_cast<uint64_t>(from: 4.0))
745 O << "4.0";
746 else if (Imm == llvm::bit_cast<uint64_t>(from: -4.0))
747 O << "-4.0";
748 else if (Imm == 0x3fc45f306dc9c882 &&
749 STI.hasFeature(Feature: AMDGPU::FeatureInv2PiInlineImm))
750 O << "0.15915494309189532";
751 else
752 printLiteral64(Imm, O, IsFP);
753}
754
755void AMDGPUInstPrinter::printLiteral64(uint64_t Imm, raw_ostream &O,
756 bool IsFP) {
757 if (IsFP && Lo_32(Value: Imm) == 0)
758 O << formatHex(Value: static_cast<uint64_t>(Hi_32(Value: Imm)));
759 else
760 O << formatHex(Value: Imm);
761}
762
763void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
764 const MCSubtargetInfo &STI,
765 raw_ostream &O) {
766 unsigned Imm = MI->getOperand(i: OpNo).getImm();
767 if (!Imm)
768 return;
769
770 if (AMDGPU::isGFX940(STI)) {
771 switch (MI->getOpcode()) {
772 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd:
773 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd:
774 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd:
775 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd:
776 O << " neg:[" << (Imm & 1) << ',' << ((Imm >> 1) & 1) << ','
777 << ((Imm >> 2) & 1) << ']';
778 return;
779 }
780 }
781
782 O << " blgp:" << Imm;
783}
784
785void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand,
786 const MCSubtargetInfo &STI,
787 raw_ostream &O) {
788 if (!FirstOperand)
789 O << ", ";
790 printRegOperand(Reg: STI.hasFeature(Feature: AMDGPU::FeatureWavefrontSize32)
791 ? AMDGPU::VCC_LO
792 : AMDGPU::VCC,
793 O, MRI);
794 if (FirstOperand)
795 O << ", ";
796}
797
798bool AMDGPUInstPrinter::needsImpliedVcc(const MCInstrDesc &Desc,
799 unsigned OpNo) const {
800 return OpNo == 0 && SIInstrFlags::isDPP(O: Desc) && SIInstrFlags::isVOPC(O: Desc) &&
801 !isVOPCAsmOnly(Opc: Desc.getOpcode()) &&
802 (Desc.hasImplicitDefOfPhysReg(Reg: AMDGPU::VCC) ||
803 Desc.hasImplicitDefOfPhysReg(Reg: AMDGPU::VCC_LO));
804}
805
806// Print default vcc/vcc_lo operand of VOPC.
807void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
808 const MCSubtargetInfo &STI,
809 raw_ostream &O) {
810 unsigned Opc = MI->getOpcode();
811 const MCInstrDesc &Desc = MII.get(Opcode: Opc);
812 int ModIdx = AMDGPU::getNamedOperandIdx(Opcode: Opc, Name: AMDGPU::OpName::src0_modifiers);
813 // 0, 1 and 2 are the first printed operands in different cases
814 // If there are printed modifiers, printOperandAndFPInputMods or
815 // printOperandAndIntInputMods will be called instead
816 if ((OpNo == 0 || (OpNo == 1 && SIInstrFlags::isDPP(O: Desc) && ModIdx != -1)) &&
817 SIInstrFlags::isVOPC(O: Desc) && !isVOPCAsmOnly(Opc: Desc.getOpcode()) &&
818 (Desc.hasImplicitDefOfPhysReg(Reg: AMDGPU::VCC) ||
819 Desc.hasImplicitDefOfPhysReg(Reg: AMDGPU::VCC_LO)))
820 printDefaultVccOperand(FirstOperand: true, STI, O);
821
822 printRegularOperand(MI, OpNo, STI, O);
823}
824
825// Print operands after vcc or modifier handling.
826void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
827 const MCSubtargetInfo &STI,
828 raw_ostream &O) {
829 const MCInstrDesc &Desc = MII.get(Opcode: MI->getOpcode());
830
831 if (OpNo >= MI->getNumOperands()) {
832 O << "/*Missing OP" << OpNo << "*/";
833 return;
834 }
835
836 const MCOperand &Op = MI->getOperand(i: OpNo);
837 if (Op.isReg()) {
838 printRegOperand(Reg: Op.getReg(), Opc: MI->getOpcode(), OpNo, O, MRI);
839
840 // Check if operand register class contains register used.
841 // Intention: print disassembler message when invalid code is decoded,
842 // for example sgpr register used in VReg or VISrc(VReg or imm) operand.
843 const MCOperandInfo &OpInfo = Desc.operands()[OpNo];
844 if (OpInfo.RegClass != -1) {
845 int16_t RCID = MII.getOpRegClassID(
846 OpInfo, HwModeId: STI.getHwMode(type: MCSubtargetInfo::HwMode_RegInfo));
847 const MCRegisterClass &RC = MRI.getRegClass(i: RCID);
848 auto Reg = mc2PseudoReg(Reg: Op.getReg());
849 if (!RC.contains(Reg) && !isInlineValue(Reg)) {
850 bool IsWaveSizeOp = OpInfo.isLookupRegClassByHwMode() &&
851 (OpInfo.RegClass == AMDGPU::SReg_1 ||
852 OpInfo.RegClass == AMDGPU::SReg_1_XEXEC);
853 // Suppress this comment for a mismatched wavesize. Some users expect to
854 // be able to assemble and disassemble modules with mixed wavesizes, but
855 // we do not know the subtarget in different functions in MC.
856 //
857 // TODO: Should probably print it anyway, maybe a more specific version.
858 if (!IsWaveSizeOp) {
859 O << "/*Invalid register, operand has \'" << MRI.getRegClassName(Class: &RC)
860 << "\' register class*/";
861 }
862 }
863 }
864 } else if (Op.isImm()) {
865 const uint8_t OpTy = Desc.operands()[OpNo].OperandType;
866 switch (OpTy) {
867 case AMDGPU::OPERAND_REG_IMM_INT32:
868 case AMDGPU::OPERAND_REG_IMM_FP32:
869 case AMDGPU::OPERAND_REG_INLINE_C_INT32:
870 case AMDGPU::OPERAND_REG_INLINE_C_FP32:
871 case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
872 case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
873 case AMDGPU::OPERAND_REG_IMM_V2INT32:
874 case AMDGPU::OPERAND_REG_IMM_V2FP32:
875 case MCOI::OPERAND_IMMEDIATE:
876 case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:
877 printImmediate32(Imm: Op.getImm(), STI, O);
878 break;
879 case AMDGPU::OPERAND_REG_IMM_INT64:
880 case AMDGPU::OPERAND_REG_INLINE_C_INT64:
881 case AMDGPU::OPERAND_REG_IMM_V2INT64:
882 printImmediate64(Imm: Op.getImm(), STI, O, IsFP: false);
883 break;
884 case AMDGPU::OPERAND_REG_IMM_FP64:
885 case AMDGPU::OPERAND_REG_INLINE_C_FP64:
886 case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
887 case AMDGPU::OPERAND_REG_IMM_V2FP64:
888 printImmediate64(Imm: Op.getImm(), STI, O, IsFP: true);
889 break;
890 case AMDGPU::OPERAND_REG_INLINE_C_INT16:
891 case AMDGPU::OPERAND_REG_IMM_INT16:
892 printImmediateInt16(Imm: Op.getImm(), STI, O);
893 break;
894 case AMDGPU::OPERAND_REG_INLINE_C_FP16:
895 case AMDGPU::OPERAND_REG_IMM_FP16:
896 case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
897 printImmediateF16(Imm: Op.getImm(), STI, O);
898 break;
899 case AMDGPU::OPERAND_REG_INLINE_C_BF16:
900 case AMDGPU::OPERAND_REG_IMM_BF16:
901 printImmediateBF16(Imm: Op.getImm(), STI, O);
902 break;
903 case AMDGPU::OPERAND_REG_IMM_V2INT16:
904 case AMDGPU::OPERAND_REG_IMM_V2BF16:
905 case AMDGPU::OPERAND_REG_IMM_V2FP16:
906 case AMDGPU::OPERAND_REG_IMM_V2FP16_SPLAT:
907 case AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16:
908 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
909 case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
910 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
911 printImmediateV216(Imm: Op.getImm(), OpType: OpTy, STI, O);
912 break;
913 case MCOI::OPERAND_UNKNOWN:
914 case MCOI::OPERAND_PCREL:
915 O << formatDec(Value: Op.getImm());
916 break;
917 case MCOI::OPERAND_REGISTER:
918 // Disassembler does not fail when operand should not allow immediate
919 // operands but decodes them into 32bit immediate operand.
920 printImmediate32(Imm: Op.getImm(), STI, O);
921 O << "/*Invalid immediate*/";
922 break;
923 default:
924 // We hit this for the immediate instruction bits that don't yet have a
925 // custom printer.
926 llvm_unreachable("unexpected immediate operand type");
927 }
928 } else if (Op.isExpr()) {
929 const MCExpr *Exp = Op.getExpr();
930 MAI.printExpr(O, *Exp);
931 } else {
932 O << "/*INV_OP*/";
933 }
934
935 // Print default vcc/vcc_lo operand of v_cndmask_b32_e32.
936 switch (MI->getOpcode()) {
937 default: break;
938
939 case AMDGPU::V_CNDMASK_B32_e32_gfx10:
940 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
941 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
942 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
943 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
944 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
945 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
946 case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
947 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
948 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
949 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
950 case AMDGPU::V_CNDMASK_B32_e32_gfx11:
951 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
952 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
953 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
954 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
955 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
956 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
957 case AMDGPU::V_CNDMASK_B32_dpp8_gfx11:
958 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
959 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
960 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
961 case AMDGPU::V_CNDMASK_B32_e32_gfx12:
962 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx12:
963 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx12:
964 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx12:
965 case AMDGPU::V_CNDMASK_B32_dpp_gfx12:
966 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx12:
967 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx12:
968 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx12:
969 case AMDGPU::V_CNDMASK_B32_dpp8_gfx12:
970 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx12:
971 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx12:
972 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx12:
973 case AMDGPU::V_CNDMASK_B32_e32_gfx13:
974 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx13:
975 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx13:
976 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx13:
977 case AMDGPU::V_CNDMASK_B32_dpp_gfx13:
978 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx13:
979 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx13:
980 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx13:
981 case AMDGPU::V_CNDMASK_B32_dpp8_gfx13:
982 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx13:
983 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx13:
984 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx13:
985
986 case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
987 case AMDGPU::V_CNDMASK_B32_e32_vi:
988 if ((int)OpNo == AMDGPU::getNamedOperandIdx(Opcode: MI->getOpcode(),
989 Name: AMDGPU::OpName::src1))
990 printDefaultVccOperand(FirstOperand: OpNo == 0, STI, O);
991 break;
992 }
993
994 if (SIInstrFlags::isMTBUF(O: Desc)) {
995 int SOffsetIdx =
996 AMDGPU::getNamedOperandIdx(Opcode: MI->getOpcode(), Name: AMDGPU::OpName::soffset);
997 assert(SOffsetIdx != -1);
998 if ((int)OpNo == SOffsetIdx)
999 printSymbolicFormat(MI, STI, O);
1000 }
1001}
1002
1003void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
1004 unsigned OpNo,
1005 const MCSubtargetInfo &STI,
1006 raw_ostream &O) {
1007 const MCInstrDesc &Desc = MII.get(Opcode: MI->getOpcode());
1008 if (needsImpliedVcc(Desc, OpNo))
1009 printDefaultVccOperand(FirstOperand: true, STI, O);
1010
1011 unsigned InputModifiers = MI->getOperand(i: OpNo).getImm();
1012
1013 // Use 'neg(...)' instead of '-' to avoid ambiguity.
1014 // This is important for integer literals because
1015 // -1 is not the same value as neg(1).
1016 bool NegMnemo = false;
1017
1018 if (InputModifiers & SISrcMods::NEG) {
1019 if (OpNo + 1 < MI->getNumOperands() &&
1020 (InputModifiers & SISrcMods::ABS) == 0) {
1021 const MCOperand &Op = MI->getOperand(i: OpNo + 1);
1022 NegMnemo = Op.isImm();
1023 }
1024 if (NegMnemo) {
1025 O << "neg(";
1026 } else {
1027 O << '-';
1028 }
1029 }
1030
1031 if (InputModifiers & SISrcMods::ABS)
1032 O << '|';
1033 printRegularOperand(MI, OpNo: OpNo + 1, STI, O);
1034 if (InputModifiers & SISrcMods::ABS)
1035 O << '|';
1036
1037 if (NegMnemo) {
1038 O << ')';
1039 }
1040
1041 // Print default vcc/vcc_lo operand of VOP2b.
1042 switch (MI->getOpcode()) {
1043 default:
1044 break;
1045
1046 case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
1047 case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
1048 case AMDGPU::V_CNDMASK_B32_dpp_gfx11:
1049 if ((int)OpNo + 1 ==
1050 AMDGPU::getNamedOperandIdx(Opcode: MI->getOpcode(), Name: AMDGPU::OpName::src1))
1051 printDefaultVccOperand(FirstOperand: OpNo == 0, STI, O);
1052 break;
1053 }
1054}
1055
1056void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
1057 unsigned OpNo,
1058 const MCSubtargetInfo &STI,
1059 raw_ostream &O) {
1060 const MCInstrDesc &Desc = MII.get(Opcode: MI->getOpcode());
1061 if (needsImpliedVcc(Desc, OpNo))
1062 printDefaultVccOperand(FirstOperand: true, STI, O);
1063
1064 unsigned InputModifiers = MI->getOperand(i: OpNo).getImm();
1065 if (InputModifiers & SISrcMods::SEXT)
1066 O << "sext(";
1067 printRegularOperand(MI, OpNo: OpNo + 1, STI, O);
1068 if (InputModifiers & SISrcMods::SEXT)
1069 O << ')';
1070
1071 // Print default vcc/vcc_lo operand of VOP2b.
1072 switch (MI->getOpcode()) {
1073 default: break;
1074
1075 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
1076 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
1077 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
1078 if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(Opcode: MI->getOpcode(),
1079 Name: AMDGPU::OpName::src1))
1080 printDefaultVccOperand(FirstOperand: OpNo == 0, STI, O);
1081 break;
1082 }
1083}
1084
1085void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo,
1086 const MCSubtargetInfo &STI,
1087 raw_ostream &O) {
1088 if (!AMDGPU::isGFX10Plus(STI))
1089 llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10");
1090
1091 unsigned Imm = MI->getOperand(i: OpNo).getImm();
1092 O << "dpp8:[" << formatDec(Value: Imm & 0x7);
1093 for (size_t i = 1; i < 8; ++i) {
1094 O << ',' << formatDec(Value: (Imm >> (3 * i)) & 0x7);
1095 }
1096 O << ']';
1097}
1098
1099void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
1100 const MCSubtargetInfo &STI,
1101 raw_ostream &O) {
1102 using namespace AMDGPU::DPP;
1103
1104 unsigned Imm = MI->getOperand(i: OpNo).getImm();
1105 const MCInstrDesc &Desc = MII.get(Opcode: MI->getOpcode());
1106
1107 if (!AMDGPU::isLegalDPALU_DPPControl(ST: STI, DC: Imm) &&
1108 STI.hasFeature(Feature: AMDGPU::FeatureDPALU_DPP) &&
1109 AMDGPU::isDPALU_DPP(OpDesc: Desc, MII, ST: STI)) {
1110 O << " /* DP ALU dpp only supports "
1111 << (isGFX12(STI) ? "row_share" : "row_newbcast") << " */";
1112 return;
1113 }
1114 if (Imm <= DppCtrl::QUAD_PERM_LAST) {
1115 O << "quad_perm:[";
1116 O << formatDec(Value: Imm & 0x3) << ',';
1117 O << formatDec(Value: (Imm & 0xc) >> 2) << ',';
1118 O << formatDec(Value: (Imm & 0x30) >> 4) << ',';
1119 O << formatDec(Value: (Imm & 0xc0) >> 6) << ']';
1120 } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
1121 (Imm <= DppCtrl::ROW_SHL_LAST)) {
1122 O << "row_shl:" << formatDec(Value: Imm - DppCtrl::ROW_SHL0);
1123 } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
1124 (Imm <= DppCtrl::ROW_SHR_LAST)) {
1125 O << "row_shr:" << formatDec(Value: Imm - DppCtrl::ROW_SHR0);
1126 } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
1127 (Imm <= DppCtrl::ROW_ROR_LAST)) {
1128 O << "row_ror:" << formatDec(Value: Imm - DppCtrl::ROW_ROR0);
1129 } else if (Imm == DppCtrl::WAVE_SHL1) {
1130 if (AMDGPU::isGFX10Plus(STI)) {
1131 O << "/* wave_shl is not supported starting from GFX10 */";
1132 return;
1133 }
1134 O << "wave_shl:1";
1135 } else if (Imm == DppCtrl::WAVE_ROL1) {
1136 if (AMDGPU::isGFX10Plus(STI)) {
1137 O << "/* wave_rol is not supported starting from GFX10 */";
1138 return;
1139 }
1140 O << "wave_rol:1";
1141 } else if (Imm == DppCtrl::WAVE_SHR1) {
1142 if (AMDGPU::isGFX10Plus(STI)) {
1143 O << "/* wave_shr is not supported starting from GFX10 */";
1144 return;
1145 }
1146 O << "wave_shr:1";
1147 } else if (Imm == DppCtrl::WAVE_ROR1) {
1148 if (AMDGPU::isGFX10Plus(STI)) {
1149 O << "/* wave_ror is not supported starting from GFX10 */";
1150 return;
1151 }
1152 O << "wave_ror:1";
1153 } else if (Imm == DppCtrl::ROW_MIRROR) {
1154 O << "row_mirror";
1155 } else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
1156 O << "row_half_mirror";
1157 } else if (Imm == DppCtrl::BCAST15) {
1158 if (AMDGPU::isGFX10Plus(STI)) {
1159 O << "/* row_bcast is not supported starting from GFX10 */";
1160 return;
1161 }
1162 O << "row_bcast:15";
1163 } else if (Imm == DppCtrl::BCAST31) {
1164 if (AMDGPU::isGFX10Plus(STI)) {
1165 O << "/* row_bcast is not supported starting from GFX10 */";
1166 return;
1167 }
1168 O << "row_bcast:31";
1169 } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
1170 (Imm <= DppCtrl::ROW_SHARE_LAST)) {
1171 if (AMDGPU::isGFX90A(STI)) {
1172 O << "row_newbcast:";
1173 } else if (AMDGPU::isGFX10Plus(STI)) {
1174 O << "row_share:";
1175 } else {
1176 O << " /* row_newbcast/row_share is not supported on ASICs earlier "
1177 "than GFX90A/GFX10 */";
1178 return;
1179 }
1180 O << formatDec(Value: Imm - DppCtrl::ROW_SHARE_FIRST);
1181 } else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
1182 (Imm <= DppCtrl::ROW_XMASK_LAST)) {
1183 if (!AMDGPU::isGFX10Plus(STI)) {
1184 O << "/* row_xmask is not supported on ASICs earlier than GFX10 */";
1185 return;
1186 }
1187 O << "row_xmask:" << formatDec(Value: Imm - DppCtrl::ROW_XMASK_FIRST);
1188 } else {
1189 O << "/* Invalid dpp_ctrl value */";
1190 }
1191}
1192
1193void AMDGPUInstPrinter::printDppBoundCtrl(const MCInst *MI, unsigned OpNo,
1194 const MCSubtargetInfo &STI,
1195 raw_ostream &O) {
1196 unsigned Imm = MI->getOperand(i: OpNo).getImm();
1197 if (Imm) {
1198 O << " bound_ctrl:1";
1199 }
1200}
1201
1202void AMDGPUInstPrinter::printDppFI(const MCInst *MI, unsigned OpNo,
1203 const MCSubtargetInfo &STI, raw_ostream &O) {
1204 using namespace llvm::AMDGPU::DPP;
1205 unsigned Imm = MI->getOperand(i: OpNo).getImm();
1206 if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
1207 O << " fi:1";
1208 }
1209}
1210
1211void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
1212 raw_ostream &O) {
1213 using namespace llvm::AMDGPU::SDWA;
1214
1215 unsigned Imm = MI->getOperand(i: OpNo).getImm();
1216 switch (Imm) {
1217 case SdwaSel::BYTE_0: O << "BYTE_0"; break;
1218 case SdwaSel::BYTE_1: O << "BYTE_1"; break;
1219 case SdwaSel::BYTE_2: O << "BYTE_2"; break;
1220 case SdwaSel::BYTE_3: O << "BYTE_3"; break;
1221 case SdwaSel::WORD_0: O << "WORD_0"; break;
1222 case SdwaSel::WORD_1: O << "WORD_1"; break;
1223 case SdwaSel::DWORD: O << "DWORD"; break;
1224 default: llvm_unreachable("Invalid SDWA data select operand");
1225 }
1226}
1227
1228void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo,
1229 const MCSubtargetInfo &STI,
1230 raw_ostream &O) {
1231 O << "dst_sel:";
1232 printSDWASel(MI, OpNo, O);
1233}
1234
1235void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
1236 const MCSubtargetInfo &STI,
1237 raw_ostream &O) {
1238 O << "src0_sel:";
1239 printSDWASel(MI, OpNo, O);
1240}
1241
1242void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
1243 const MCSubtargetInfo &STI,
1244 raw_ostream &O) {
1245 O << "src1_sel:";
1246 printSDWASel(MI, OpNo, O);
1247}
1248
1249void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
1250 const MCSubtargetInfo &STI,
1251 raw_ostream &O) {
1252 using namespace llvm::AMDGPU::SDWA;
1253
1254 O << "dst_unused:";
1255 unsigned Imm = MI->getOperand(i: OpNo).getImm();
1256 switch (Imm) {
1257 case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break;
1258 case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break;
1259 case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break;
1260 default: llvm_unreachable("Invalid SDWA dest_unused operand");
1261 }
1262}
1263
1264void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo,
1265 const MCSubtargetInfo &STI, raw_ostream &O,
1266 unsigned N) {
1267 unsigned Opc = MI->getOpcode();
1268 int EnIdx = AMDGPU::getNamedOperandIdx(Opcode: Opc, Name: AMDGPU::OpName::en);
1269 unsigned En = MI->getOperand(i: EnIdx).getImm();
1270
1271 int ComprIdx = AMDGPU::getNamedOperandIdx(Opcode: Opc, Name: AMDGPU::OpName::compr);
1272
1273 // If compr is set, print as src0, src0, src1, src1
1274 if (MI->getOperand(i: ComprIdx).getImm())
1275 OpNo = OpNo - N + N / 2;
1276
1277 if (En & (1 << N))
1278 printRegOperand(Reg: MI->getOperand(i: OpNo).getReg(), Opc, OpNo, O, MRI);
1279 else
1280 O << "off";
1281}
1282
1283void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo,
1284 const MCSubtargetInfo &STI,
1285 raw_ostream &O) {
1286 printExpSrcN(MI, OpNo, STI, O, N: 0);
1287}
1288
1289void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo,
1290 const MCSubtargetInfo &STI,
1291 raw_ostream &O) {
1292 printExpSrcN(MI, OpNo, STI, O, N: 1);
1293}
1294
1295void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo,
1296 const MCSubtargetInfo &STI,
1297 raw_ostream &O) {
1298 printExpSrcN(MI, OpNo, STI, O, N: 2);
1299}
1300
1301void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo,
1302 const MCSubtargetInfo &STI,
1303 raw_ostream &O) {
1304 printExpSrcN(MI, OpNo, STI, O, N: 3);
1305}
1306
1307void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
1308 const MCSubtargetInfo &STI,
1309 raw_ostream &O) {
1310 using namespace llvm::AMDGPU::Exp;
1311
1312 // This is really a 6 bit field.
1313 unsigned Id = MI->getOperand(i: OpNo).getImm() & ((1 << 6) - 1);
1314
1315 int Index;
1316 StringRef TgtName;
1317 if (getTgtName(Id, Name&: TgtName, Index) && isSupportedTgtId(Id, STI)) {
1318 O << ' ' << TgtName;
1319 if (Index >= 0)
1320 O << Index;
1321 } else {
1322 O << " invalid_target_" << Id;
1323 }
1324}
1325
1326static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
1327 bool IsPacked, bool HasDstSel) {
1328 int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1);
1329
1330 for (int I = 0; I < NumOps; ++I) {
1331 if (!!(Ops[I] & Mod) != DefaultValue)
1332 return false;
1333 }
1334
1335 if (HasDstSel && (Ops[0] & SISrcMods::DST_OP_SEL) != 0)
1336 return false;
1337
1338 return true;
1339}
1340
1341void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
1342 StringRef Name,
1343 unsigned Mod,
1344 raw_ostream &O) {
1345 unsigned Opc = MI->getOpcode();
1346 int NumOps = 0;
1347 int Ops[3];
1348
1349 std::pair<AMDGPU::OpName, AMDGPU::OpName> MOps[] = {
1350 {AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src0},
1351 {AMDGPU::OpName::src1_modifiers, AMDGPU::OpName::src1},
1352 {AMDGPU::OpName::src2_modifiers, AMDGPU::OpName::src2}};
1353 int DefaultValue = (Mod == SISrcMods::OP_SEL_1);
1354
1355 for (auto [SrcMod, Src] : MOps) {
1356 if (!AMDGPU::hasNamedOperand(Opcode: Opc, NamedIdx: Src))
1357 break;
1358
1359 int ModIdx = AMDGPU::getNamedOperandIdx(Opcode: Opc, Name: SrcMod);
1360 Ops[NumOps++] =
1361 (ModIdx != -1) ? MI->getOperand(i: ModIdx).getImm() : DefaultValue;
1362 }
1363
1364 // Some instructions, e.g. v_interp_p2_f16 in GFX9, have src0, src2, but no
1365 // src1.
1366 if (NumOps == 1 && AMDGPU::hasNamedOperand(Opcode: Opc, NamedIdx: AMDGPU::OpName::src2) &&
1367 !AMDGPU::hasNamedOperand(Opcode: Opc, NamedIdx: AMDGPU::OpName::src1)) {
1368 Ops[NumOps++] = DefaultValue; // Set src1_modifiers to default.
1369 int Mod2Idx =
1370 AMDGPU::getNamedOperandIdx(Opcode: Opc, Name: AMDGPU::OpName::src2_modifiers);
1371 assert(Mod2Idx != -1);
1372 Ops[NumOps++] = MI->getOperand(i: Mod2Idx).getImm();
1373 }
1374
1375 const bool HasDst =
1376 (AMDGPU::getNamedOperandIdx(Opcode: Opc, Name: AMDGPU::OpName::vdst) != -1) ||
1377 (AMDGPU::getNamedOperandIdx(Opcode: Opc, Name: AMDGPU::OpName::sdst) != -1);
1378
1379 // Print three values of neg/opsel for wmma instructions (prints 0 when there
1380 // is no src_modifier operand instead of not printing anything).
1381 if (SIInstrFlags::isSWMMAC(O: MII, O: *MI) || SIInstrFlags::isWMMA(O: MII, O: *MI)) {
1382 NumOps = 0;
1383 int DefaultValue = Mod == SISrcMods::OP_SEL_1;
1384 for (AMDGPU::OpName OpName :
1385 {AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src1_modifiers,
1386 AMDGPU::OpName::src2_modifiers}) {
1387 int Idx = AMDGPU::getNamedOperandIdx(Opcode: Opc, Name: OpName);
1388 if (Idx != -1)
1389 Ops[NumOps++] = MI->getOperand(i: Idx).getImm();
1390 else
1391 Ops[NumOps++] = DefaultValue;
1392 }
1393 }
1394
1395 const bool HasDstSel = HasDst && NumOps > 0 && Mod == SISrcMods::OP_SEL_0 &&
1396 SIInstrFlags::hasVOP3OpSel(O: MII, O: *MI);
1397
1398 const bool IsPacked = SIInstrFlags::isPacked(O: MII, O: *MI);
1399
1400 if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel))
1401 return;
1402
1403 O << Name;
1404 ListSeparator Sep(",");
1405 for (int I = 0; I < NumOps; ++I)
1406 O << Sep << !!(Ops[I] & Mod);
1407
1408 if (HasDstSel) {
1409 O << ',' << !!(Ops[0] & SISrcMods::DST_OP_SEL);
1410 }
1411
1412 O << ']';
1413}
1414
1415void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
1416 const MCSubtargetInfo &STI,
1417 raw_ostream &O) {
1418 unsigned Opc = MI->getOpcode();
1419 if (isCvt_F32_Fp8_Bf8_e64(Opc)) {
1420 auto SrcMod =
1421 AMDGPU::getNamedOperandIdx(Opcode: Opc, Name: AMDGPU::OpName::src0_modifiers);
1422 unsigned Mod = MI->getOperand(i: SrcMod).getImm();
1423 unsigned Index0 = !!(Mod & SISrcMods::OP_SEL_0);
1424 unsigned Index1 = !!(Mod & SISrcMods::OP_SEL_1);
1425 if (Index0 || Index1)
1426 O << " op_sel:[" << Index0 << ',' << Index1 << ']';
1427 return;
1428 }
1429 if (isPermlane16(Opc)) {
1430 auto FIN = AMDGPU::getNamedOperandIdx(Opcode: Opc, Name: AMDGPU::OpName::src0_modifiers);
1431 auto BCN = AMDGPU::getNamedOperandIdx(Opcode: Opc, Name: AMDGPU::OpName::src1_modifiers);
1432 unsigned FI = !!(MI->getOperand(i: FIN).getImm() & SISrcMods::OP_SEL_0);
1433 unsigned BC = !!(MI->getOperand(i: BCN).getImm() & SISrcMods::OP_SEL_0);
1434 if (FI || BC)
1435 O << " op_sel:[" << FI << ',' << BC << ']';
1436 return;
1437 }
1438
1439 printPackedModifier(MI, Name: " op_sel:[", Mod: SISrcMods::OP_SEL_0, O);
1440}
1441
1442void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo,
1443 const MCSubtargetInfo &STI,
1444 raw_ostream &O) {
1445 printPackedModifier(MI, Name: " op_sel_hi:[", Mod: SISrcMods::OP_SEL_1, O);
1446}
1447
1448void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo,
1449 const MCSubtargetInfo &STI,
1450 raw_ostream &O) {
1451 printPackedModifier(MI, Name: " neg_lo:[", Mod: SISrcMods::NEG, O);
1452}
1453
1454void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo,
1455 const MCSubtargetInfo &STI,
1456 raw_ostream &O) {
1457 printPackedModifier(MI, Name: " neg_hi:[", Mod: SISrcMods::NEG_HI, O);
1458}
1459
1460void AMDGPUInstPrinter::printIndexKey8bit(const MCInst *MI, unsigned OpNo,
1461 const MCSubtargetInfo &STI,
1462 raw_ostream &O) {
1463 auto Imm = MI->getOperand(i: OpNo).getImm() & 0x7;
1464 if (Imm == 0)
1465 return;
1466
1467 O << " index_key:" << Imm;
1468}
1469
1470void AMDGPUInstPrinter::printIndexKey16bit(const MCInst *MI, unsigned OpNo,
1471 const MCSubtargetInfo &STI,
1472 raw_ostream &O) {
1473 auto Imm = MI->getOperand(i: OpNo).getImm() & 0x7;
1474 if (Imm == 0)
1475 return;
1476
1477 O << " index_key:" << Imm;
1478}
1479
1480void AMDGPUInstPrinter::printIndexKey32bit(const MCInst *MI, unsigned OpNo,
1481 const MCSubtargetInfo &STI,
1482 raw_ostream &O) {
1483 auto Imm = MI->getOperand(i: OpNo).getImm() & 0x7;
1484 if (Imm == 0)
1485 return;
1486
1487 O << " index_key:" << Imm;
1488}
1489
1490void AMDGPUInstPrinter::printMatrixFMT(const MCInst *MI, unsigned OpNo,
1491 const MCSubtargetInfo &STI,
1492 raw_ostream &O, char AorB) {
1493 auto Imm = MI->getOperand(i: OpNo).getImm() & 0x7;
1494 if (Imm == 0)
1495 return;
1496
1497 O << " matrix_" << AorB << "_fmt:";
1498 if (Imm < static_cast<int64_t>(std::size(WMMAMods::ModMatrixFmt)))
1499 O << WMMAMods::ModMatrixFmt[Imm];
1500 else
1501 O << Imm;
1502}
1503
1504void AMDGPUInstPrinter::printMatrixAFMT(const MCInst *MI, unsigned OpNo,
1505 const MCSubtargetInfo &STI,
1506 raw_ostream &O) {
1507 printMatrixFMT(MI, OpNo, STI, O, AorB: 'a');
1508}
1509
1510void AMDGPUInstPrinter::printMatrixBFMT(const MCInst *MI, unsigned OpNo,
1511 const MCSubtargetInfo &STI,
1512 raw_ostream &O) {
1513 printMatrixFMT(MI, OpNo, STI, O, AorB: 'b');
1514}
1515
1516void AMDGPUInstPrinter::printMatrixScale(const MCInst *MI, unsigned OpNo,
1517 const MCSubtargetInfo &STI,
1518 raw_ostream &O, char AorB) {
1519 auto Imm = MI->getOperand(i: OpNo).getImm() & 1;
1520 if (Imm == 0)
1521 return;
1522
1523 O << " matrix_" << AorB << "_scale:";
1524 if (Imm < static_cast<int64_t>(std::size(WMMAMods::ModMatrixScale)))
1525 O << WMMAMods::ModMatrixScale[Imm];
1526 else
1527 O << Imm;
1528}
1529
1530void AMDGPUInstPrinter::printMatrixAScale(const MCInst *MI, unsigned OpNo,
1531 const MCSubtargetInfo &STI,
1532 raw_ostream &O) {
1533 printMatrixScale(MI, OpNo, STI, O, AorB: 'a');
1534}
1535
1536void AMDGPUInstPrinter::printMatrixBScale(const MCInst *MI, unsigned OpNo,
1537 const MCSubtargetInfo &STI,
1538 raw_ostream &O) {
1539 printMatrixScale(MI, OpNo, STI, O, AorB: 'b');
1540}
1541
1542void AMDGPUInstPrinter::printMatrixScaleFmt(const MCInst *MI, unsigned OpNo,
1543 const MCSubtargetInfo &STI,
1544 raw_ostream &O, char AorB) {
1545 auto Imm = MI->getOperand(i: OpNo).getImm() & 3;
1546 if (Imm == 0)
1547 return;
1548
1549 O << " matrix_" << AorB << "_scale_fmt:";
1550 if (Imm < static_cast<int64_t>(std::size(WMMAMods::ModMatrixScaleFmt)))
1551 O << WMMAMods::ModMatrixScaleFmt[Imm];
1552 else
1553 O << Imm;
1554}
1555
1556void AMDGPUInstPrinter::printMatrixAScaleFmt(const MCInst *MI, unsigned OpNo,
1557 const MCSubtargetInfo &STI,
1558 raw_ostream &O) {
1559 printMatrixScaleFmt(MI, OpNo, STI, O, AorB: 'a');
1560}
1561
1562void AMDGPUInstPrinter::printMatrixBScaleFmt(const MCInst *MI, unsigned OpNo,
1563 const MCSubtargetInfo &STI,
1564 raw_ostream &O) {
1565 printMatrixScaleFmt(MI, OpNo, STI, O, AorB: 'b');
1566}
1567
1568void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
1569 const MCSubtargetInfo &STI,
1570 raw_ostream &O) {
1571 unsigned Imm = MI->getOperand(i: OpNum).getImm();
1572 switch (Imm) {
1573 case 0:
1574 O << "p10";
1575 break;
1576 case 1:
1577 O << "p20";
1578 break;
1579 case 2:
1580 O << "p0";
1581 break;
1582 default:
1583 O << "invalid_param_" << Imm;
1584 }
1585}
1586
1587void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum,
1588 const MCSubtargetInfo &STI,
1589 raw_ostream &O) {
1590 unsigned Attr = MI->getOperand(i: OpNum).getImm();
1591 O << "attr" << Attr;
1592}
1593
1594void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
1595 const MCSubtargetInfo &STI,
1596 raw_ostream &O) {
1597 unsigned Chan = MI->getOperand(i: OpNum).getImm();
1598 O << '.' << "xyzw"[Chan & 0x3];
1599}
1600
1601void AMDGPUInstPrinter::printGPRIdxMode(const MCInst *MI, unsigned OpNo,
1602 const MCSubtargetInfo &STI,
1603 raw_ostream &O) {
1604 using namespace llvm::AMDGPU::VGPRIndexMode;
1605 unsigned Val = MI->getOperand(i: OpNo).getImm();
1606
1607 if ((Val & ~ENABLE_MASK) != 0) {
1608 O << formatHex(Value: static_cast<uint64_t>(Val));
1609 } else {
1610 O << "gpr_idx(";
1611 ListSeparator Sep(",");
1612 for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
1613 if (Val & (1 << ModeId))
1614 O << Sep << IdSymbolic[ModeId];
1615 }
1616 O << ')';
1617 }
1618}
1619
1620void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1621 const MCSubtargetInfo &STI,
1622 raw_ostream &O) {
1623 printRegularOperand(MI, OpNo, STI, O);
1624 O << ", ";
1625 printRegularOperand(MI, OpNo: OpNo + 1, STI, O);
1626}
1627
1628void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1629 raw_ostream &O, StringRef Asm,
1630 StringRef Default) {
1631 const MCOperand &Op = MI->getOperand(i: OpNo);
1632 assert(Op.isImm());
1633 if (Op.getImm() == 1) {
1634 O << Asm;
1635 } else {
1636 O << Default;
1637 }
1638}
1639
1640void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1641 raw_ostream &O, char Asm) {
1642 const MCOperand &Op = MI->getOperand(i: OpNo);
1643 assert(Op.isImm());
1644 if (Op.getImm() == 1)
1645 O << Asm;
1646}
1647
1648void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
1649 const MCSubtargetInfo &STI,
1650 raw_ostream &O) {
1651 int Imm = MI->getOperand(i: OpNo).getImm();
1652 if (Imm == SIOutMods::MUL2)
1653 O << " mul:2";
1654 else if (Imm == SIOutMods::MUL4)
1655 O << " mul:4";
1656 else if (Imm == SIOutMods::DIV2)
1657 O << " div:2";
1658}
1659
1660void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
1661 const MCSubtargetInfo &STI,
1662 raw_ostream &O) {
1663 using namespace llvm::AMDGPU::SendMsg;
1664
1665 const unsigned Imm16 = MI->getOperand(i: OpNo).getImm();
1666
1667 uint16_t MsgId;
1668 uint16_t OpId;
1669 uint16_t StreamId;
1670 decodeMsg(Val: Imm16, MsgId, OpId, StreamId, STI);
1671
1672 StringRef MsgName = getMsgName(Encoding: MsgId, STI);
1673
1674 if (!MsgName.empty() && isValidMsgOp(MsgId, OpId, STI) &&
1675 isValidMsgStream(MsgId, OpId, StreamId, STI)) {
1676 O << "sendmsg(" << MsgName;
1677 if (msgRequiresOp(MsgId, STI)) {
1678 O << ", " << getMsgOpName(MsgId, Encoding: OpId, STI);
1679 if (msgSupportsStream(MsgId, OpId, STI)) {
1680 O << ", " << StreamId;
1681 }
1682 }
1683 O << ')';
1684 } else if (encodeMsg(MsgId, OpId, StreamId) == Imm16) {
1685 O << "sendmsg(" << MsgId << ", " << OpId << ", " << StreamId << ')';
1686 } else {
1687 O << Imm16; // Unknown imm16 code.
1688 }
1689}
1690
1691void AMDGPUInstPrinter::printWaitEvent(const MCInst *MI, unsigned OpNo,
1692 const MCSubtargetInfo &STI,
1693 raw_ostream &O) {
1694 using namespace llvm::AMDGPU::WaitEvent;
1695 const uint16_t Imm16 = static_cast<uint16_t>(MI->getOperand(i: OpNo).getImm());
1696
1697 StringRef EventName = getWaitEventMaskName(Encoding: Imm16, STI);
1698 if (EventName.empty())
1699 O << formatHex(Value: static_cast<uint64_t>(Imm16));
1700 else
1701 O << EventName;
1702}
1703
1704static void printSwizzleBitmask(const uint16_t AndMask,
1705 const uint16_t OrMask,
1706 const uint16_t XorMask,
1707 raw_ostream &O) {
1708 using namespace llvm::AMDGPU::Swizzle;
1709
1710 uint16_t Probe0 = ((0 & AndMask) | OrMask) ^ XorMask;
1711 uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
1712
1713 O << "\"";
1714
1715 for (unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1716 uint16_t p0 = Probe0 & Mask;
1717 uint16_t p1 = Probe1 & Mask;
1718
1719 if (p0 == p1) {
1720 if (p0 == 0) {
1721 O << "0";
1722 } else {
1723 O << "1";
1724 }
1725 } else {
1726 if (p0 == 0) {
1727 O << "p";
1728 } else {
1729 O << "i";
1730 }
1731 }
1732 }
1733
1734 O << "\"";
1735}
1736
1737void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
1738 const MCSubtargetInfo &STI,
1739 raw_ostream &O) {
1740 using namespace llvm::AMDGPU::Swizzle;
1741
1742 uint16_t Imm = MI->getOperand(i: OpNo).getImm();
1743 if (Imm == 0) {
1744 return;
1745 }
1746
1747 O << " offset:";
1748
1749 // Rotate and FFT modes
1750 if (Imm >= ROTATE_MODE_LO && AMDGPU::isGFX9Plus(STI)) {
1751 if (Imm >= FFT_MODE_LO) {
1752 O << "swizzle(" << IdSymbolic[ID_FFT] << ',' << (Imm & FFT_SWIZZLE_MASK)
1753 << ')';
1754 } else if (Imm >= ROTATE_MODE_LO) {
1755 O << "swizzle(" << IdSymbolic[ID_ROTATE] << ','
1756 << ((Imm >> ROTATE_DIR_SHIFT) & ROTATE_DIR_MASK) << ','
1757 << ((Imm >> ROTATE_SIZE_SHIFT) & ROTATE_SIZE_MASK) << ')';
1758 }
1759 return;
1760 }
1761
1762 // Basic mode
1763 if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1764 O << "swizzle(" << IdSymbolic[ID_QUAD_PERM];
1765 for (unsigned I = 0; I < LANE_NUM; ++I) {
1766 O << ",";
1767 O << formatDec(Value: Imm & LANE_MASK);
1768 Imm >>= LANE_SHIFT;
1769 }
1770 O << ")";
1771
1772 } else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1773
1774 uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1775 uint16_t OrMask = (Imm >> BITMASK_OR_SHIFT) & BITMASK_MASK;
1776 uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1777
1778 if (AndMask == BITMASK_MAX && OrMask == 0 && llvm::popcount(Value: XorMask) == 1) {
1779
1780 O << "swizzle(" << IdSymbolic[ID_SWAP];
1781 O << ",";
1782 O << formatDec(Value: XorMask);
1783 O << ")";
1784
1785 } else if (AndMask == BITMASK_MAX && OrMask == 0 && XorMask > 0 &&
1786 isPowerOf2_64(Value: XorMask + 1)) {
1787
1788 O << "swizzle(" << IdSymbolic[ID_REVERSE];
1789 O << ",";
1790 O << formatDec(Value: XorMask + 1);
1791 O << ")";
1792
1793 } else {
1794
1795 uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1796 if (GroupSize > 1 &&
1797 isPowerOf2_64(Value: GroupSize) &&
1798 OrMask < GroupSize &&
1799 XorMask == 0) {
1800
1801 O << "swizzle(" << IdSymbolic[ID_BROADCAST];
1802 O << ",";
1803 O << formatDec(Value: GroupSize);
1804 O << ",";
1805 O << formatDec(Value: OrMask);
1806 O << ")";
1807
1808 } else {
1809 O << "swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1810 O << ",";
1811 printSwizzleBitmask(AndMask, OrMask, XorMask, O);
1812 O << ")";
1813 }
1814 }
1815 } else {
1816 printU16ImmDecOperand(MI, OpNo, O);
1817 }
1818}
1819
1820void AMDGPUInstPrinter::printSWaitCnt(const MCInst *MI, unsigned OpNo,
1821 const MCSubtargetInfo &STI,
1822 raw_ostream &O) {
1823 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(GPU: STI.getCPU());
1824
1825 unsigned SImm16 = MI->getOperand(i: OpNo).getImm();
1826 unsigned Vmcnt, Expcnt, Lgkmcnt;
1827 decodeWaitcnt(Version: ISA, Waitcnt: SImm16, Vmcnt, Expcnt, Lgkmcnt);
1828
1829 bool IsDefaultVmcnt = Vmcnt == getVmcntBitMask(Version: ISA);
1830 bool IsDefaultExpcnt = Expcnt == getExpcntBitMask(Version: ISA);
1831 bool IsDefaultLgkmcnt = Lgkmcnt == getLgkmcntBitMask(Version: ISA);
1832 bool PrintAll = IsDefaultVmcnt && IsDefaultExpcnt && IsDefaultLgkmcnt;
1833
1834 ListSeparator Sep(" ");
1835
1836 if (!IsDefaultVmcnt || PrintAll)
1837 O << Sep << "vmcnt(" << Vmcnt << ')';
1838
1839 if (!IsDefaultExpcnt || PrintAll)
1840 O << Sep << "expcnt(" << Expcnt << ')';
1841
1842 if (!IsDefaultLgkmcnt || PrintAll)
1843 O << Sep << "lgkmcnt(" << Lgkmcnt << ')';
1844}
1845
1846void AMDGPUInstPrinter::printDepCtr(const MCInst *MI, unsigned OpNo,
1847 const MCSubtargetInfo &STI,
1848 raw_ostream &O) {
1849 using namespace llvm::AMDGPU::DepCtr;
1850
1851 uint64_t Imm16 = MI->getOperand(i: OpNo).getImm() & 0xffff;
1852
1853 bool HasNonDefaultVal = false;
1854 if (isSymbolicDepCtrEncoding(Code: Imm16, HasNonDefaultVal, STI)) {
1855 int Id = 0;
1856 StringRef Name;
1857 unsigned Val;
1858 bool IsDefault;
1859 ListSeparator Sep(" ");
1860 while (decodeDepCtr(Code: Imm16, Id, Name, Val, IsDefault, STI)) {
1861 if (!IsDefault || !HasNonDefaultVal)
1862 O << Sep << Name << '(' << Val << ')';
1863 }
1864 } else {
1865 O << formatHex(Value: Imm16);
1866 }
1867}
1868
1869void AMDGPUInstPrinter::printSDelayALU(const MCInst *MI, unsigned OpNo,
1870 const MCSubtargetInfo &STI,
1871 raw_ostream &O) {
1872 const char *BadInstId = "/* invalid instid value */";
1873 static const std::array<const char *, 12> InstIds = {
1874 "NO_DEP", "VALU_DEP_1", "VALU_DEP_2",
1875 "VALU_DEP_3", "VALU_DEP_4", "TRANS32_DEP_1",
1876 "TRANS32_DEP_2", "TRANS32_DEP_3", "FMA_ACCUM_CYCLE_1",
1877 "SALU_CYCLE_1", "SALU_CYCLE_2", "SALU_CYCLE_3"};
1878
1879 const char *BadInstSkip = "/* invalid instskip value */";
1880 static const std::array<const char *, 6> InstSkips = {
1881 "SAME", "NEXT", "SKIP_1", "SKIP_2", "SKIP_3", "SKIP_4"};
1882
1883 unsigned SImm16 = MI->getOperand(i: OpNo).getImm();
1884 const char *Prefix = "";
1885
1886 unsigned Value = SImm16 & 0xF;
1887 if (Value) {
1888 const char *Name = Value < InstIds.size() ? InstIds[Value] : BadInstId;
1889 O << Prefix << "instid0(" << Name << ')';
1890 Prefix = " | ";
1891 }
1892
1893 Value = (SImm16 >> 4) & 7;
1894 if (Value) {
1895 const char *Name =
1896 Value < InstSkips.size() ? InstSkips[Value] : BadInstSkip;
1897 O << Prefix << "instskip(" << Name << ')';
1898 Prefix = " | ";
1899 }
1900
1901 Value = (SImm16 >> 7) & 0xF;
1902 if (Value) {
1903 const char *Name = Value < InstIds.size() ? InstIds[Value] : BadInstId;
1904 O << Prefix << "instid1(" << Name << ')';
1905 Prefix = " | ";
1906 }
1907
1908 if (!*Prefix)
1909 O << "0";
1910}
1911
1912void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
1913 const MCSubtargetInfo &STI, raw_ostream &O) {
1914 using namespace llvm::AMDGPU::Hwreg;
1915 unsigned Val = MI->getOperand(i: OpNo).getImm();
1916 auto [Id, Offset, Width] = HwregEncoding::decode(Encoded: Val);
1917 StringRef HwRegName = getHwreg(Encoding: Id, STI);
1918
1919 O << "hwreg(";
1920 if (!HwRegName.empty()) {
1921 O << HwRegName;
1922 } else {
1923 O << Id;
1924 }
1925 if (Width != HwregSize::Default || Offset != HwregOffset::Default)
1926 O << ", " << Offset << ", " << Width;
1927 O << ')';
1928}
1929
1930void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
1931 const MCSubtargetInfo &STI,
1932 raw_ostream &O) {
1933 uint16_t Imm = MI->getOperand(i: OpNo).getImm();
1934 if (Imm == 0) {
1935 return;
1936 }
1937
1938 O << ' ' << formatDec(Value: Imm);
1939}
1940
1941void AMDGPUInstPrinter::printNamedInt(const MCInst *MI, unsigned OpNo,
1942 const MCSubtargetInfo &STI,
1943 raw_ostream &O, StringRef Prefix,
1944 bool PrintInHex, bool AlwaysPrint) {
1945 int64_t V = MI->getOperand(i: OpNo).getImm();
1946 if (AlwaysPrint || V != 0)
1947 O << ' ' << Prefix << ':' << (PrintInHex ? formatHex(Value: V) : formatDec(Value: V));
1948}
1949
1950void AMDGPUInstPrinter::printBitOp3(const MCInst *MI, unsigned OpNo,
1951 const MCSubtargetInfo &STI,
1952 raw_ostream &O) {
1953 uint8_t Imm = MI->getOperand(i: OpNo).getImm();
1954 if (!Imm)
1955 return;
1956
1957 O << " bitop3:";
1958 if (Imm <= 10)
1959 O << formatDec(Value: Imm);
1960 else
1961 O << formatHex(Value: static_cast<uint64_t>(Imm));
1962}
1963
1964#include "AMDGPUGenAsmWriter.inc"
1965