1//===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// R600 DAG Lowering interface definition
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_R600ISELLOWERING_H
15#define LLVM_LIB_TARGET_AMDGPU_R600ISELLOWERING_H
16
17#include "AMDGPUISelLowering.h"
18#include "llvm/CodeGen/MachineFunction.h"
19
20namespace llvm {
21
22class R600Subtarget;
23
24class R600TargetLowering final : public AMDGPUTargetLowering {
25
26 const R600Subtarget *Subtarget;
27public:
28 R600TargetLowering(const TargetMachine &TM, const R600Subtarget &STI);
29
30 MachineBasicBlock *
31 EmitInstrWithCustomInserter(MachineInstr &MI,
32 MachineBasicBlock *BB) const override;
33 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
34 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
35 void ReplaceNodeResults(SDNode * N,
36 SmallVectorImpl<SDValue> &Results,
37 SelectionDAG &DAG) const override;
38 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
39 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
40 bool isVarArg,
41 const SmallVectorImpl<ISD::InputArg> &Ins,
42 const SDLoc &DL, SelectionDAG &DAG,
43 SmallVectorImpl<SDValue> &InVals) const override;
44 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
45 EVT VT) const override;
46
47 bool canMergeStoresTo(unsigned AS, EVT MemVT,
48 const MachineFunction &MF) const override;
49
50 bool allowsMisalignedMemoryAccesses(
51 EVT VT, unsigned AS, Align Alignment,
52 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
53 unsigned *IsFast = nullptr) const override;
54
55 bool canCombineTruncStore(EVT ValVT, EVT MemVT, Align Alignment,
56 unsigned AddrSpace,
57 bool LegalOperations) const override {
58 // R600 has "custom" lowering for truncating stores despite not supporting
59 // those instructions. If we allow that custom lowering in the DAG combiner
60 // then all truncates are merged into truncating stores, giving worse code
61 // generation. This hook prevents the DAG combiner performing that combine.
62 return isTruncStoreLegal(ValVT, MemVT, Alignment, AddrSpace);
63 }
64
65private:
66 unsigned Gen;
67 /// Each OpenCL kernel has nine implicit parameters that are stored in the
68 /// first nine dwords of a Vertex Buffer. These implicit parameters are
69 /// lowered to load instructions which retrieve the values from the Vertex
70 /// Buffer.
71 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT, const SDLoc &DL,
72 unsigned DwordOffset) const;
73
74 SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[],
75 SelectionDAG &DAG, const SDLoc &DL) const;
76 SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
77
78 SDValue lowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
79 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
80 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
81 SDValue LowerGlobalAddress(AMDGPUMachineFunctionInfo *MFI, SDValue Op,
82 SelectionDAG &DAG) const override;
83 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
84
85 SDValue lowerPrivateTruncStore(StoreSDNode *Store, SelectionDAG &DAG) const;
86 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
87 SDValue lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
88 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
89
90 SDValue lowerPrivateExtLoad(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
92 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
93 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
94 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
95 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
96 SDValue LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
97 unsigned mainop, unsigned ovf) const;
98
99 void getStackAddress(unsigned StackWidth, unsigned ElemIdx,
100 unsigned &Channel, unsigned &PtrIncr) const;
101 bool isZero(SDValue Op) const;
102 bool isHWTrueValue(SDValue Op) const;
103 bool isHWFalseValue(SDValue Op) const;
104
105 bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src,
106 SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm,
107 SelectionDAG &DAG) const;
108 SDValue constBufferLoad(LoadSDNode *LoadNode, int Block,
109 SelectionDAG &DAG) const;
110
111 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
112
113 TargetLowering::AtomicExpansionKind
114 shouldExpandAtomicRMWInIR(const AtomicRMWInst *RMW) const override;
115};
116
117} // End namespace llvm;
118
119#endif
120