1//=====-- R600Subtarget.h - Define Subtarget for AMDGPU R600 ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//==-----------------------------------------------------------------------===//
8//
9/// \file
10/// AMDGPU R600 specific subclass of TargetSubtarget.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H
15#define LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H
16
17#include "AMDGPUSubtarget.h"
18#include "R600FrameLowering.h"
19#include "R600ISelLowering.h"
20#include "R600InstrInfo.h"
21#include "Utils/AMDGPUBaseInfo.h"
22
23#define GET_SUBTARGETINFO_HEADER
24#include "R600GenSubtargetInfo.inc"
25
26namespace llvm {
27
28class R600Subtarget final : public R600GenSubtargetInfo,
29 public AMDGPUSubtarget {
30
31#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
32 bool ATTRIBUTE = DEFAULT;
33#include "R600GenSubtargetInfo.inc"
34
35private:
36 R600InstrInfo InstrInfo;
37 R600FrameLowering FrameLowering;
38 short TexVTXClauseSize = 0;
39 Generation Gen = R600;
40 R600TargetLowering TLInfo;
41 InstrItineraryData InstrItins;
42 std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
43
44public:
45 R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
46 const TargetMachine &TM);
47
48 ~R600Subtarget() override;
49
50 const R600InstrInfo *getInstrInfo() const override { return &InstrInfo; }
51
52 const R600FrameLowering *getFrameLowering() const override {
53 return &FrameLowering;
54 }
55
56 const R600TargetLowering *getTargetLowering() const override {
57 return &TLInfo;
58 }
59
60 const R600RegisterInfo *getRegisterInfo() const override {
61 return &InstrInfo.getRegisterInfo();
62 }
63
64 const InstrItineraryData *getInstrItineraryData() const override {
65 return &InstrItins;
66 }
67
68 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
69
70 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
71
72 Generation getGeneration() const {
73 return Gen;
74 }
75
76 Align getStackAlignment() const { return Align(4); }
77
78 R600Subtarget &initializeSubtargetDependencies(const Triple &TT,
79 StringRef GPU, StringRef FS);
80
81 bool hasBFE() const {
82 return (getGeneration() >= EVERGREEN);
83 }
84
85 bool hasBFI() const {
86 return (getGeneration() >= EVERGREEN);
87 }
88
89 bool hasBCNT(unsigned Size) const {
90 if (Size == 32)
91 return (getGeneration() >= EVERGREEN);
92
93 return false;
94 }
95
96 bool hasBORROW() const {
97 return (getGeneration() >= EVERGREEN);
98 }
99
100 bool hasCARRY() const {
101 return (getGeneration() >= EVERGREEN);
102 }
103
104 bool hasCaymanISA() const { return HasCaymanISA; }
105
106 bool hasFFBL() const {
107 return (getGeneration() >= EVERGREEN);
108 }
109
110 bool hasFFBH() const {
111 return (getGeneration() >= EVERGREEN);
112 }
113
114 bool hasFMA() const override { return HasFMA; }
115
116 bool hasMadMacF32Insts() const override { return HasMadMacF32Insts; }
117
118 bool enablePromoteAlloca() const override { return EnablePromoteAlloca; }
119
120 bool hasFP64() const override { return HasFP64; }
121
122 bool hasCFALUBug() const { return HasCFALUBug; }
123
124 bool hasVertexCache() const { return HasVertexCache; }
125
126 short getTexVTXClauseSize() const { return TexVTXClauseSize; }
127
128 bool enableMachineScheduler() const override {
129 return true;
130 }
131
132 bool enableSubRegLiveness() const override {
133 return true;
134 }
135
136 /// \returns Maximum number of work groups per compute unit supported by the
137 /// subtarget and limited by given \p FlatWorkGroupSize.
138 unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const override {
139 return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(STI: this, FlatWorkGroupSize);
140 }
141
142 /// \returns Minimum flat work group size supported by the subtarget.
143 unsigned getMinFlatWorkGroupSize() const override {
144 return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(STI: this);
145 }
146
147 /// \returns Maximum flat work group size supported by the subtarget.
148 unsigned getMaxFlatWorkGroupSize() const override {
149 return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(STI: this);
150 }
151
152 /// \returns Number of waves per execution unit required to support the given
153 /// \p FlatWorkGroupSize.
154 unsigned
155 getWavesPerEUForWorkGroup(unsigned FlatWorkGroupSize) const override {
156 return AMDGPU::IsaInfo::getWavesPerEUForWorkGroup(STI: this, FlatWorkGroupSize);
157 }
158
159 /// \returns Minimum number of waves per execution unit supported by the
160 /// subtarget.
161 unsigned getMinWavesPerEU() const override {
162 return AMDGPU::IsaInfo::getMinWavesPerEU(STI: this);
163 }
164
165 bool requiresDisjointEarlyClobberAndUndef() const override {
166 // AMDGPU doesn't care if early-clobber and undef operands are allocated
167 // to the same register.
168 return false;
169 }
170};
171
172} // end namespace llvm
173
174#endif // LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H
175