1//===-- SIFixVGPRCopies.cpp - Fix VGPR Copies after regalloc --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Add implicit use of exec to vector register copies.
11///
12//===----------------------------------------------------------------------===//
13
14#include "SIFixVGPRCopies.h"
15#include "AMDGPU.h"
16#include "GCNSubtarget.h"
17#include "llvm/CodeGen/MachineFunctionPass.h"
18
19using namespace llvm;
20
21#define DEBUG_TYPE "si-fix-vgpr-copies"
22
23namespace {
24
25class SIFixVGPRCopiesLegacy : public MachineFunctionPass {
26public:
27 static char ID;
28
29 SIFixVGPRCopiesLegacy() : MachineFunctionPass(ID) {}
30
31 void getAnalysisUsage(AnalysisUsage &AU) const override {
32 AU.setPreservesAll();
33 MachineFunctionPass::getAnalysisUsage(AU);
34 }
35
36 bool runOnMachineFunction(MachineFunction &MF) override;
37
38 StringRef getPassName() const override { return "SI Fix VGPR copies"; }
39};
40
41class SIFixVGPRCopies {
42public:
43 bool run(MachineFunction &MF);
44};
45
46} // End anonymous namespace.
47
48INITIALIZE_PASS(SIFixVGPRCopiesLegacy, DEBUG_TYPE, "SI Fix VGPR copies", false,
49 false)
50
51char SIFixVGPRCopiesLegacy::ID = 0;
52
53char &llvm::SIFixVGPRCopiesID = SIFixVGPRCopiesLegacy::ID;
54
55PreservedAnalyses SIFixVGPRCopiesPass::run(MachineFunction &MF,
56 MachineFunctionAnalysisManager &) {
57 SIFixVGPRCopies().run(MF);
58 return PreservedAnalyses::all();
59}
60
61bool SIFixVGPRCopiesLegacy::runOnMachineFunction(MachineFunction &MF) {
62 return SIFixVGPRCopies().run(MF);
63}
64
65bool SIFixVGPRCopies::run(MachineFunction &MF) {
66 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
67 const SIRegisterInfo *TRI = ST.getRegisterInfo();
68 const SIInstrInfo *TII = ST.getInstrInfo();
69 bool Changed = false;
70
71 for (MachineBasicBlock &MBB : MF) {
72 for (MachineInstr &MI : MBB) {
73 switch (MI.getOpcode()) {
74 case AMDGPU::COPY:
75 if (TII->isVGPRCopy(MI) && !MI.readsRegister(Reg: AMDGPU::EXEC, TRI)) {
76 MI.addOperand(MF,
77 Op: MachineOperand::CreateReg(Reg: AMDGPU::EXEC, isDef: false, isImp: true));
78 LLVM_DEBUG(dbgs() << "Add exec use to " << MI);
79 Changed = true;
80 }
81 break;
82 default:
83 break;
84 }
85 }
86 }
87
88 return Changed;
89}
90