1//===-- SIFixVGPRCopies.cpp - Fix VGPR Copies after regalloc --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Add implicit use of exec to vector register copies.
11///
12//===----------------------------------------------------------------------===//
13
14#include "SIFixVGPRCopies.h"
15#include "AMDGPU.h"
16#include "GCNSubtarget.h"
17#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
18#include "llvm/CodeGen/MachineFunctionPass.h"
19
20using namespace llvm;
21
22#define DEBUG_TYPE "si-fix-vgpr-copies"
23
24namespace {
25
26class SIFixVGPRCopiesLegacy : public MachineFunctionPass {
27public:
28 static char ID;
29
30 SIFixVGPRCopiesLegacy() : MachineFunctionPass(ID) {}
31
32 void getAnalysisUsage(AnalysisUsage &AU) const override {
33 AU.setPreservesAll();
34 MachineFunctionPass::getAnalysisUsage(AU);
35 }
36
37 bool runOnMachineFunction(MachineFunction &MF) override;
38
39 StringRef getPassName() const override { return "SI Fix VGPR copies"; }
40};
41
42class SIFixVGPRCopies {
43public:
44 bool run(MachineFunction &MF);
45};
46
47} // End anonymous namespace.
48
49INITIALIZE_PASS(SIFixVGPRCopiesLegacy, DEBUG_TYPE, "SI Fix VGPR copies", false,
50 false)
51
52char SIFixVGPRCopiesLegacy::ID = 0;
53
54char &llvm::SIFixVGPRCopiesID = SIFixVGPRCopiesLegacy::ID;
55
56PreservedAnalyses SIFixVGPRCopiesPass::run(MachineFunction &MF,
57 MachineFunctionAnalysisManager &) {
58 SIFixVGPRCopies().run(MF);
59 return PreservedAnalyses::all();
60}
61
62bool SIFixVGPRCopiesLegacy::runOnMachineFunction(MachineFunction &MF) {
63 return SIFixVGPRCopies().run(MF);
64}
65
66bool SIFixVGPRCopies::run(MachineFunction &MF) {
67 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
68 const SIRegisterInfo *TRI = ST.getRegisterInfo();
69 const SIInstrInfo *TII = ST.getInstrInfo();
70 bool Changed = false;
71
72 for (MachineBasicBlock &MBB : MF) {
73 for (MachineInstr &MI : MBB) {
74 switch (MI.getOpcode()) {
75 case AMDGPU::COPY:
76 if (TII->isVGPRCopy(MI) && !MI.readsRegister(Reg: AMDGPU::EXEC, TRI)) {
77 MI.addOperand(MF,
78 Op: MachineOperand::CreateReg(Reg: AMDGPU::EXEC, isDef: false, isImp: true));
79 LLVM_DEBUG(dbgs() << "Add exec use to " << MI);
80 Changed = true;
81 }
82 break;
83 default:
84 break;
85 }
86 }
87 }
88
89 return Changed;
90}
91