1//===-- SILowerI1Copies.h --------------------------------------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Interface definition of the PhiLoweringHelper class that implements lane
11/// mask merging algorithm for divergent i1 phis.
12//
13//===----------------------------------------------------------------------===//
14
15#include "AMDGPULaneMaskUtils.h"
16#include "GCNSubtarget.h"
17#include "llvm/CodeGen/MachineBasicBlock.h"
18#include "llvm/CodeGen/MachinePostDominators.h"
19#include "llvm/CodeGen/MachineRegisterInfo.h"
20#include "llvm/CodeGen/MachineSSAUpdater.h"
21
22namespace llvm {
23
24/// Incoming for lane mask phi as machine instruction, incoming register \p Reg
25/// and incoming block \p Block are taken from machine instruction.
26/// \p UpdatedReg (if valid) is \p Reg lane mask merged with another lane mask.
27struct Incoming {
28 Register Reg;
29 MachineBasicBlock *Block;
30 Register UpdatedReg;
31
32 Incoming(Register Reg, MachineBasicBlock *Block, Register UpdatedReg)
33 : Reg(Reg), Block(Block), UpdatedReg(UpdatedReg) {}
34};
35
36Register createLaneMaskReg(MachineRegisterInfo *MRI,
37 MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs);
38
39class PhiLoweringHelper {
40public:
41 PhiLoweringHelper(MachineFunction *MF, MachineDominatorTree *DT,
42 MachinePostDominatorTree *PDT);
43 virtual ~PhiLoweringHelper() = default;
44
45protected:
46 bool IsWave32 = false;
47 MachineFunction *MF = nullptr;
48 MachineDominatorTree *DT = nullptr;
49 MachinePostDominatorTree *PDT = nullptr;
50 MachineRegisterInfo *MRI = nullptr;
51 const GCNSubtarget *ST = nullptr;
52 const SIInstrInfo *TII = nullptr;
53 MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs;
54 const AMDGPU::LaneMaskConstants *LMC = nullptr;
55
56#ifndef NDEBUG
57 DenseSet<Register> PhiRegisters;
58#endif
59
60public:
61 bool lowerPhis();
62 bool isConstantLaneMask(Register Reg, bool &Val) const;
63 MachineBasicBlock::iterator
64 getSaluInsertionAtEnd(MachineBasicBlock &MBB) const;
65
66 void initializeLaneMaskRegisterAttributes(Register LaneMask) {
67 LaneMaskRegAttrs = MRI->getVRegAttrs(Reg: LaneMask);
68 }
69
70 void
71 initializeLaneMaskRegisterAttributes(MachineRegisterInfo::VRegAttrs Attrs) {
72 LaneMaskRegAttrs = Attrs;
73 }
74
75 bool isLaneMaskReg(Register Reg) const {
76 return TII->getRegisterInfo().isSGPRReg(MRI: *MRI, Reg) &&
77 TII->getRegisterInfo().getRegSizeInBits(Reg, MRI: *MRI) ==
78 ST->getWavefrontSize();
79 }
80
81 // Helpers from lowerPhis that are different between sdag and global-isel.
82
83 virtual void markAsLaneMask(Register DstReg) const = 0;
84 virtual void getCandidatesForLowering(
85 SmallVectorImpl<MachineInstr *> &Vreg1Phis) const = 0;
86 virtual void
87 collectIncomingValuesFromPhi(const MachineInstr *MI,
88 SmallVectorImpl<Incoming> &Incomings) const = 0;
89 virtual void replaceDstReg(Register NewReg, Register OldReg,
90 MachineBasicBlock *MBB) = 0;
91 virtual void buildMergeLaneMasks(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator I,
93 const DebugLoc &DL, Register DstReg,
94 Register PrevReg, Register CurReg) = 0;
95 virtual void constrainAsLaneMask(Incoming &In) = 0;
96};
97
98} // end namespace llvm
99