1//===-- SILowerI1Copies.h --------------------------------------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Interface definition of the PhiLoweringHelper class that implements lane
11/// mask merging algorithm for divergent i1 phis.
12//
13//===----------------------------------------------------------------------===//
14
15#include "AMDGPULaneMaskUtils.h"
16#include "GCNSubtarget.h"
17#include "llvm/CodeGen/MachineBasicBlock.h"
18#include "llvm/CodeGen/MachinePostDominators.h"
19#include "llvm/CodeGen/MachineRegisterInfo.h"
20#include "llvm/CodeGen/MachineSSAUpdater.h"
21
22namespace llvm {
23class MachineIDFSSAUpdater;
24namespace AMDGPU {
25class LoopFinder;
26class PhiIncomingAnalysis;
27/// Incoming for lane mask phi as machine instruction, incoming register \p Reg
28/// and incoming block \p Block are taken from machine instruction.
29/// \p UpdatedReg (if valid) is \p Reg lane mask merged with another lane mask.
30struct Incoming {
31 Register Reg;
32 MachineBasicBlock *Block;
33 Register UpdatedReg;
34
35 Incoming(Register Reg, MachineBasicBlock *Block, Register UpdatedReg)
36 : Reg(Reg), Block(Block), UpdatedReg(UpdatedReg) {}
37};
38
39Register createLaneMaskReg(MachineRegisterInfo *MRI,
40 MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs);
41
42class PhiLoweringHelper {
43public:
44 PhiLoweringHelper(MachineFunction &MF, MachineDominatorTree &DT,
45 MachinePostDominatorTree &PDT);
46 virtual ~PhiLoweringHelper() = default;
47
48protected:
49 bool IsWave32 = false;
50 MachineFunction &MF;
51 MachineDominatorTree &DT;
52 MachinePostDominatorTree &PDT;
53 MachineRegisterInfo *MRI = nullptr;
54 const GCNSubtarget *ST = nullptr;
55 const SIInstrInfo *TII = nullptr;
56 MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs;
57 const AMDGPU::LaneMaskConstants *LMC = nullptr;
58
59#ifndef NDEBUG
60 DenseSet<Register> PhiRegisters;
61#endif
62
63public:
64 bool lowerPhis();
65 bool isConstantLaneMask(Register Reg, bool &Val) const;
66
67 /// Merge the \p Incomings lane masks into \p DstReg, the value owned by \p
68 /// MBB. Builds the per-predecessor merges and leaves \p SSAUpdater calculated
69 /// so the caller can query the merged value with getValueInMiddleOfBlock. \p
70 /// Incomings is sorted and its UpdatedReg fields are filled in.
71 void mergeIncomingLaneMasks(Register DstReg, MachineBasicBlock &MBB,
72 SmallVectorImpl<Incoming> &Incomings,
73 MachineIDFSSAUpdater &SSAUpdater, LoopFinder &LF,
74 PhiIncomingAnalysis &PIA);
75 MachineBasicBlock::iterator
76 getSaluInsertionAtEnd(MachineBasicBlock &MBB) const;
77
78 void initializeLaneMaskRegisterAttributes(Register LaneMask) {
79 LaneMaskRegAttrs = MRI->getVRegAttrs(Reg: LaneMask);
80 }
81
82 void
83 initializeLaneMaskRegisterAttributes(MachineRegisterInfo::VRegAttrs Attrs) {
84 LaneMaskRegAttrs = Attrs;
85 }
86
87 bool isLaneMaskReg(Register Reg) const {
88 return TII->getRegisterInfo().isSGPRReg(MRI: *MRI, Reg) &&
89 TII->getRegisterInfo().getRegSizeInBits(Reg, MRI: *MRI) ==
90 ST->getWavefrontSize();
91 }
92
93 // Helpers from lowerPhis that are different between sdag and global-isel.
94
95 virtual void markAsLaneMask(Register DstReg) const = 0;
96 virtual void getCandidatesForLowering(
97 SmallVectorImpl<MachineInstr *> &Vreg1Phis) const = 0;
98 virtual void
99 collectIncomingValuesFromPhi(const MachineInstr *MI,
100 SmallVectorImpl<Incoming> &Incomings) const = 0;
101 virtual void replaceDstReg(Register NewReg, Register OldReg,
102 MachineBasicBlock *MBB) = 0;
103 virtual void buildMergeLaneMasks(MachineBasicBlock &MBB,
104 MachineBasicBlock::iterator I,
105 const DebugLoc &DL, Register DstReg,
106 Register PrevReg, Register CurReg) = 0;
107 virtual void constrainAsLaneMask(Incoming &In) = 0;
108};
109} // namespace AMDGPU
110} // end namespace llvm
111