1//===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements the targeting of the Machinelegalizer class for ARM.
10/// \todo This should be generated by TableGen.
11//===----------------------------------------------------------------------===//
12
13#include "ARMLegalizerInfo.h"
14#include "ARMCallLowering.h"
15#include "ARMSubtarget.h"
16#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
17#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
18#include "llvm/CodeGen/LowLevelTypeUtils.h"
19#include "llvm/CodeGen/MachineRegisterInfo.h"
20#include "llvm/CodeGen/TargetOpcodes.h"
21#include "llvm/CodeGen/ValueTypes.h"
22#include "llvm/IR/DerivedTypes.h"
23#include "llvm/IR/Type.h"
24
25using namespace llvm;
26using namespace LegalizeActions;
27
28static bool AEABI(const ARMSubtarget &ST) {
29 return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI();
30}
31
32ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) : ST(ST) {
33 using namespace TargetOpcode;
34
35 const LLT p0 = LLT::pointer(AddressSpace: 0, SizeInBits: 32);
36
37 const LLT s1 = LLT::scalar(SizeInBits: 1);
38 const LLT s8 = LLT::scalar(SizeInBits: 8);
39 const LLT s16 = LLT::scalar(SizeInBits: 16);
40 const LLT s32 = LLT::scalar(SizeInBits: 32);
41 const LLT s64 = LLT::scalar(SizeInBits: 64);
42
43 if (ST.isThumb1Only()) {
44 // Thumb1 is not supported yet.
45 verify(MII: *ST.getInstrInfo());
46 return;
47 }
48
49 getActionDefinitionsBuilder(Opcodes: {G_SEXT, G_ZEXT, G_ANYEXT})
50 .legalForCartesianProduct(Types0: {s8, s16, s32}, Types1: {s1, s8, s16});
51
52 getActionDefinitionsBuilder(Opcode: G_TRUNC).legalForCartesianProduct(Types0: {s1, s8, s16},
53 Types1: {s8, s16, s32});
54
55 getActionDefinitionsBuilder(Opcode: G_SEXT_INREG).lower();
56
57 getActionDefinitionsBuilder(Opcodes: {G_MUL, G_AND, G_OR, G_XOR})
58 .legalFor(Types: {s32})
59 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
60
61 if (ST.hasNEON())
62 getActionDefinitionsBuilder(Opcodes: {G_ADD, G_SUB})
63 .legalFor(Types: {s32, s64})
64 .minScalar(TypeIdx: 0, Ty: s32);
65 else
66 getActionDefinitionsBuilder(Opcodes: {G_ADD, G_SUB})
67 .legalFor(Types: {s32})
68 .minScalar(TypeIdx: 0, Ty: s32);
69
70 getActionDefinitionsBuilder(Opcodes: {G_ASHR, G_LSHR, G_SHL})
71 .legalFor(Types: {{s32, s32}})
72 .minScalar(TypeIdx: 0, Ty: s32)
73 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s32);
74
75 bool HasHWDivide = (!ST.isThumb() && ST.hasDivideInARMMode()) ||
76 (ST.isThumb() && ST.hasDivideInThumbMode());
77 if (HasHWDivide)
78 getActionDefinitionsBuilder(Opcodes: {G_SDIV, G_UDIV})
79 .legalFor(Types: {s32})
80 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
81 else
82 getActionDefinitionsBuilder(Opcodes: {G_SDIV, G_UDIV})
83 .libcallFor(Types: {s32})
84 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
85
86 auto &REMBuilder =
87 getActionDefinitionsBuilder(Opcodes: {G_SREM, G_UREM}).minScalar(TypeIdx: 0, Ty: s32);
88 if (HasHWDivide)
89 REMBuilder.lowerFor(Types: {s32});
90 else if (AEABI(ST))
91 REMBuilder.customFor(Types: {s32});
92 else
93 REMBuilder.libcallFor(Types: {s32});
94
95 getActionDefinitionsBuilder(Opcode: G_INTTOPTR)
96 .legalFor(Types: {{p0, s32}})
97 .minScalar(TypeIdx: 1, Ty: s32);
98 getActionDefinitionsBuilder(Opcode: G_PTRTOINT)
99 .legalFor(Types: {{s32, p0}})
100 .minScalar(TypeIdx: 0, Ty: s32);
101
102 getActionDefinitionsBuilder(Opcode: G_CONSTANT)
103 .customFor(Types: {s32, p0})
104 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
105
106 getActionDefinitionsBuilder(Opcode: G_CONSTANT_POOL).legalFor(Types: {p0});
107
108 getActionDefinitionsBuilder(Opcode: G_ICMP)
109 .legalForCartesianProduct(Types0: {s1}, Types1: {s32, p0})
110 .minScalar(TypeIdx: 1, Ty: s32);
111
112 getActionDefinitionsBuilder(Opcode: G_SELECT)
113 .legalForCartesianProduct(Types0: {s32, p0}, Types1: {s1})
114 .minScalar(TypeIdx: 0, Ty: s32);
115
116 // We're keeping these builders around because we'll want to add support for
117 // floating point to them.
118 auto &LoadStoreBuilder = getActionDefinitionsBuilder(Opcodes: {G_LOAD, G_STORE})
119 .legalForTypesWithMemDesc(TypesAndMemDesc: {{.Type0: s8, .Type1: p0, .MemTy: s8, .Align: 8},
120 {.Type0: s16, .Type1: p0, .MemTy: s16, .Align: 8},
121 {.Type0: s32, .Type1: p0, .MemTy: s32, .Align: 8},
122 {.Type0: p0, .Type1: p0, .MemTy: p0, .Align: 8}})
123 .unsupportedIfMemSizeNotPow2();
124
125 getActionDefinitionsBuilder(Opcode: G_FRAME_INDEX).legalFor(Types: {p0});
126 getActionDefinitionsBuilder(Opcode: G_GLOBAL_VALUE).legalFor(Types: {p0});
127
128 auto &PhiBuilder =
129 getActionDefinitionsBuilder(Opcode: G_PHI)
130 .legalFor(Types: {s32, p0})
131 .minScalar(TypeIdx: 0, Ty: s32);
132
133 getActionDefinitionsBuilder(Opcode: G_PTR_ADD)
134 .legalFor(Types: {{p0, s32}})
135 .minScalar(TypeIdx: 1, Ty: s32);
136
137 getActionDefinitionsBuilder(Opcode: G_BR).alwaysLegal();
138 getActionDefinitionsBuilder(Opcode: G_BRCOND).legalFor(Types: {s1});
139
140 if (!ST.useSoftFloat() && ST.hasVFP2Base()) {
141 getActionDefinitionsBuilder(
142 Opcodes: {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG})
143 .legalFor(Types: {s32, s64});
144
145 LoadStoreBuilder
146 .legalForTypesWithMemDesc(TypesAndMemDesc: {{.Type0: s64, .Type1: p0, .MemTy: s64, .Align: 32}})
147 .maxScalar(TypeIdx: 0, Ty: s32);
148 PhiBuilder.legalFor(Types: {s64});
149
150 getActionDefinitionsBuilder(Opcode: G_FCMP).legalForCartesianProduct(Types0: {s1},
151 Types1: {s32, s64});
152
153 getActionDefinitionsBuilder(Opcode: G_MERGE_VALUES).legalFor(Types: {{s64, s32}});
154 getActionDefinitionsBuilder(Opcode: G_UNMERGE_VALUES).legalFor(Types: {{s32, s64}});
155
156 getActionDefinitionsBuilder(Opcode: G_FPEXT).legalFor(Types: {{s64, s32}});
157 getActionDefinitionsBuilder(Opcode: G_FPTRUNC).legalFor(Types: {{s32, s64}});
158
159 getActionDefinitionsBuilder(Opcodes: {G_FPTOSI, G_FPTOUI})
160 .legalForCartesianProduct(Types0: {s32}, Types1: {s32, s64});
161 getActionDefinitionsBuilder(Opcodes: {G_SITOFP, G_UITOFP})
162 .legalForCartesianProduct(Types0: {s32, s64}, Types1: {s32});
163
164 getActionDefinitionsBuilder(Opcodes: {G_GET_FPENV, G_SET_FPENV, G_GET_FPMODE})
165 .legalFor(Types: {s32});
166 getActionDefinitionsBuilder(Opcode: G_RESET_FPENV).alwaysLegal();
167 getActionDefinitionsBuilder(Opcode: G_SET_FPMODE).customFor(Types: {s32});
168 getActionDefinitionsBuilder(Opcode: G_RESET_FPMODE).custom();
169 } else {
170 getActionDefinitionsBuilder(Opcodes: {G_FADD, G_FSUB, G_FMUL, G_FDIV})
171 .libcallFor(Types: {s32, s64});
172
173 LoadStoreBuilder.maxScalar(TypeIdx: 0, Ty: s32);
174
175 getActionDefinitionsBuilder(Opcode: G_FNEG).lowerFor(Types: {s32, s64});
176
177 getActionDefinitionsBuilder(Opcode: G_FCONSTANT).customFor(Types: {s32, s64});
178
179 getActionDefinitionsBuilder(Opcode: G_FCMP).customForCartesianProduct(Types0: {s1},
180 Types1: {s32, s64});
181
182 if (AEABI(ST))
183 setFCmpLibcallsAEABI();
184 else
185 setFCmpLibcallsGNU();
186
187 getActionDefinitionsBuilder(Opcode: G_FPEXT).libcallFor(Types: {{s64, s32}});
188 getActionDefinitionsBuilder(Opcode: G_FPTRUNC).libcallFor(Types: {{s32, s64}});
189
190 getActionDefinitionsBuilder(Opcodes: {G_FPTOSI, G_FPTOUI})
191 .libcallForCartesianProduct(Types0: {s32}, Types1: {s32, s64});
192 getActionDefinitionsBuilder(Opcodes: {G_SITOFP, G_UITOFP})
193 .libcallForCartesianProduct(Types0: {s32, s64}, Types1: {s32});
194
195 getActionDefinitionsBuilder(Opcodes: {G_GET_FPENV, G_SET_FPENV, G_RESET_FPENV})
196 .libcall();
197 getActionDefinitionsBuilder(Opcodes: {G_GET_FPMODE, G_SET_FPMODE, G_RESET_FPMODE})
198 .libcall();
199 }
200
201 // Just expand whatever loads and stores are left.
202 LoadStoreBuilder.lower();
203
204 if (!ST.useSoftFloat() && ST.hasVFP4Base())
205 getActionDefinitionsBuilder(Opcode: G_FMA).legalFor(Types: {s32, s64});
206 else
207 getActionDefinitionsBuilder(Opcode: G_FMA).libcallFor(Types: {s32, s64});
208
209 getActionDefinitionsBuilder(Opcodes: {G_FREM, G_FPOW}).libcallFor(Types: {s32, s64});
210
211 if (ST.hasV5TOps() && !ST.isThumb1Only()) {
212 getActionDefinitionsBuilder(Opcode: G_CTLZ)
213 .legalFor(Types: {s32, s32})
214 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s32)
215 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
216 getActionDefinitionsBuilder(Opcode: G_CTLZ_ZERO_POISON)
217 .lowerFor(Types: {s32, s32})
218 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s32)
219 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
220 } else {
221 getActionDefinitionsBuilder(Opcode: G_CTLZ_ZERO_POISON)
222 .libcallFor(Types: {s32, s32})
223 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s32)
224 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
225 getActionDefinitionsBuilder(Opcode: G_CTLZ)
226 .lowerFor(Types: {s32, s32})
227 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s32)
228 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
229 }
230
231 verify(MII: *ST.getInstrInfo());
232}
233
234void ARMLegalizerInfo::setFCmpLibcallsAEABI() {
235 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
236 // default-initialized.
237 FCmp32Libcalls.resize(S: CmpInst::LAST_FCMP_PREDICATE + 1);
238 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {
239 {.LibcallID: RTLIB::OEQ_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
240 FCmp32Libcalls[CmpInst::FCMP_OGE] = {
241 {.LibcallID: RTLIB::OGE_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
242 FCmp32Libcalls[CmpInst::FCMP_OGT] = {
243 {.LibcallID: RTLIB::OGT_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
244 FCmp32Libcalls[CmpInst::FCMP_OLE] = {
245 {.LibcallID: RTLIB::OLE_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
246 FCmp32Libcalls[CmpInst::FCMP_OLT] = {
247 {.LibcallID: RTLIB::OLT_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
248 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{.LibcallID: RTLIB::UO_F32, .Predicate: CmpInst::ICMP_EQ}};
249 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{.LibcallID: RTLIB::OLT_F32, .Predicate: CmpInst::ICMP_EQ}};
250 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{.LibcallID: RTLIB::OLE_F32, .Predicate: CmpInst::ICMP_EQ}};
251 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{.LibcallID: RTLIB::OGT_F32, .Predicate: CmpInst::ICMP_EQ}};
252 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{.LibcallID: RTLIB::OGE_F32, .Predicate: CmpInst::ICMP_EQ}};
253 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{.LibcallID: RTLIB::UNE_F32, .Predicate: CmpInst::ICMP_EQ}};
254 FCmp32Libcalls[CmpInst::FCMP_UNO] = {
255 {.LibcallID: RTLIB::UO_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
256 FCmp32Libcalls[CmpInst::FCMP_ONE] = {
257 {.LibcallID: RTLIB::OGT_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE},
258 {.LibcallID: RTLIB::OLT_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
259 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {
260 {.LibcallID: RTLIB::OEQ_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE},
261 {.LibcallID: RTLIB::UO_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
262
263 FCmp64Libcalls.resize(S: CmpInst::LAST_FCMP_PREDICATE + 1);
264 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {
265 {.LibcallID: RTLIB::OEQ_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
266 FCmp64Libcalls[CmpInst::FCMP_OGE] = {
267 {.LibcallID: RTLIB::OGE_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
268 FCmp64Libcalls[CmpInst::FCMP_OGT] = {
269 {.LibcallID: RTLIB::OGT_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
270 FCmp64Libcalls[CmpInst::FCMP_OLE] = {
271 {.LibcallID: RTLIB::OLE_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
272 FCmp64Libcalls[CmpInst::FCMP_OLT] = {
273 {.LibcallID: RTLIB::OLT_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
274 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{.LibcallID: RTLIB::UO_F64, .Predicate: CmpInst::ICMP_EQ}};
275 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{.LibcallID: RTLIB::OLT_F64, .Predicate: CmpInst::ICMP_EQ}};
276 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{.LibcallID: RTLIB::OLE_F64, .Predicate: CmpInst::ICMP_EQ}};
277 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{.LibcallID: RTLIB::OGT_F64, .Predicate: CmpInst::ICMP_EQ}};
278 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{.LibcallID: RTLIB::OGE_F64, .Predicate: CmpInst::ICMP_EQ}};
279 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{.LibcallID: RTLIB::UNE_F64, .Predicate: CmpInst::ICMP_EQ}};
280 FCmp64Libcalls[CmpInst::FCMP_UNO] = {
281 {.LibcallID: RTLIB::UO_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
282 FCmp64Libcalls[CmpInst::FCMP_ONE] = {
283 {.LibcallID: RTLIB::OGT_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE},
284 {.LibcallID: RTLIB::OLT_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
285 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {
286 {.LibcallID: RTLIB::OEQ_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE},
287 {.LibcallID: RTLIB::UO_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
288}
289
290void ARMLegalizerInfo::setFCmpLibcallsGNU() {
291 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
292 // default-initialized.
293 FCmp32Libcalls.resize(S: CmpInst::LAST_FCMP_PREDICATE + 1);
294 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{.LibcallID: RTLIB::OEQ_F32, .Predicate: CmpInst::ICMP_EQ}};
295 FCmp32Libcalls[CmpInst::FCMP_OGE] = {{.LibcallID: RTLIB::OGE_F32, .Predicate: CmpInst::ICMP_SGE}};
296 FCmp32Libcalls[CmpInst::FCMP_OGT] = {{.LibcallID: RTLIB::OGT_F32, .Predicate: CmpInst::ICMP_SGT}};
297 FCmp32Libcalls[CmpInst::FCMP_OLE] = {{.LibcallID: RTLIB::OLE_F32, .Predicate: CmpInst::ICMP_SLE}};
298 FCmp32Libcalls[CmpInst::FCMP_OLT] = {{.LibcallID: RTLIB::OLT_F32, .Predicate: CmpInst::ICMP_SLT}};
299 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{.LibcallID: RTLIB::UO_F32, .Predicate: CmpInst::ICMP_EQ}};
300 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{.LibcallID: RTLIB::OLT_F32, .Predicate: CmpInst::ICMP_SGE}};
301 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{.LibcallID: RTLIB::OLE_F32, .Predicate: CmpInst::ICMP_SGT}};
302 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{.LibcallID: RTLIB::OGT_F32, .Predicate: CmpInst::ICMP_SLE}};
303 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{.LibcallID: RTLIB::OGE_F32, .Predicate: CmpInst::ICMP_SLT}};
304 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{.LibcallID: RTLIB::UNE_F32, .Predicate: CmpInst::ICMP_NE}};
305 FCmp32Libcalls[CmpInst::FCMP_UNO] = {{.LibcallID: RTLIB::UO_F32, .Predicate: CmpInst::ICMP_NE}};
306 FCmp32Libcalls[CmpInst::FCMP_ONE] = {{.LibcallID: RTLIB::OGT_F32, .Predicate: CmpInst::ICMP_SGT},
307 {.LibcallID: RTLIB::OLT_F32, .Predicate: CmpInst::ICMP_SLT}};
308 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{.LibcallID: RTLIB::OEQ_F32, .Predicate: CmpInst::ICMP_EQ},
309 {.LibcallID: RTLIB::UO_F32, .Predicate: CmpInst::ICMP_NE}};
310
311 FCmp64Libcalls.resize(S: CmpInst::LAST_FCMP_PREDICATE + 1);
312 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{.LibcallID: RTLIB::OEQ_F64, .Predicate: CmpInst::ICMP_EQ}};
313 FCmp64Libcalls[CmpInst::FCMP_OGE] = {{.LibcallID: RTLIB::OGE_F64, .Predicate: CmpInst::ICMP_SGE}};
314 FCmp64Libcalls[CmpInst::FCMP_OGT] = {{.LibcallID: RTLIB::OGT_F64, .Predicate: CmpInst::ICMP_SGT}};
315 FCmp64Libcalls[CmpInst::FCMP_OLE] = {{.LibcallID: RTLIB::OLE_F64, .Predicate: CmpInst::ICMP_SLE}};
316 FCmp64Libcalls[CmpInst::FCMP_OLT] = {{.LibcallID: RTLIB::OLT_F64, .Predicate: CmpInst::ICMP_SLT}};
317 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{.LibcallID: RTLIB::UO_F64, .Predicate: CmpInst::ICMP_EQ}};
318 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{.LibcallID: RTLIB::OLT_F64, .Predicate: CmpInst::ICMP_SGE}};
319 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{.LibcallID: RTLIB::OLE_F64, .Predicate: CmpInst::ICMP_SGT}};
320 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{.LibcallID: RTLIB::OGT_F64, .Predicate: CmpInst::ICMP_SLE}};
321 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{.LibcallID: RTLIB::OGE_F64, .Predicate: CmpInst::ICMP_SLT}};
322 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{.LibcallID: RTLIB::UNE_F64, .Predicate: CmpInst::ICMP_NE}};
323 FCmp64Libcalls[CmpInst::FCMP_UNO] = {{.LibcallID: RTLIB::UO_F64, .Predicate: CmpInst::ICMP_NE}};
324 FCmp64Libcalls[CmpInst::FCMP_ONE] = {{.LibcallID: RTLIB::OGT_F64, .Predicate: CmpInst::ICMP_SGT},
325 {.LibcallID: RTLIB::OLT_F64, .Predicate: CmpInst::ICMP_SLT}};
326 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{.LibcallID: RTLIB::OEQ_F64, .Predicate: CmpInst::ICMP_EQ},
327 {.LibcallID: RTLIB::UO_F64, .Predicate: CmpInst::ICMP_NE}};
328}
329
330ARMLegalizerInfo::FCmpLibcallsList
331ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate,
332 unsigned Size) const {
333 assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate");
334 if (Size == 32)
335 return FCmp32Libcalls[Predicate];
336 if (Size == 64)
337 return FCmp64Libcalls[Predicate];
338 llvm_unreachable("Unsupported size for FCmp predicate");
339}
340
341bool ARMLegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
342 LostDebugLocObserver &LocObserver) const {
343 using namespace TargetOpcode;
344
345 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
346 MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
347 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
348
349 switch (MI.getOpcode()) {
350 default:
351 return false;
352 case G_SREM:
353 case G_UREM: {
354 Register OriginalResult = MI.getOperand(i: 0).getReg();
355 auto Size = MRI.getType(Reg: OriginalResult).getSizeInBits();
356 if (Size != 32)
357 return false;
358
359 auto Libcall =
360 MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
361
362 // Our divmod libcalls return a struct containing the quotient and the
363 // remainder. Create a new, unused register for the quotient and use the
364 // destination of the original instruction for the remainder.
365 Type *ArgTy = Type::getInt32Ty(C&: Ctx);
366 StructType *RetTy = StructType::get(Context&: Ctx, Elements: {ArgTy, ArgTy}, /* Packed */ isPacked: true);
367 Register RetRegs[] = {MRI.createGenericVirtualRegister(Ty: LLT::scalar(SizeInBits: 32)),
368 OriginalResult};
369 auto Status = Helper.createLibcall(Libcall, Result: {RetRegs, RetTy, 0},
370 Args: {{MI.getOperand(i: 1).getReg(), ArgTy, 0},
371 {MI.getOperand(i: 2).getReg(), ArgTy, 0}},
372 LocObserver, MI: &MI);
373 if (Status != LegalizerHelper::Legalized)
374 return false;
375 break;
376 }
377 case G_FCMP: {
378 assert(MRI.getType(MI.getOperand(2).getReg()) ==
379 MRI.getType(MI.getOperand(3).getReg()) &&
380 "Mismatched operands for G_FCMP");
381 auto OpSize = MRI.getType(Reg: MI.getOperand(i: 2).getReg()).getSizeInBits();
382
383 auto OriginalResult = MI.getOperand(i: 0).getReg();
384 auto Predicate =
385 static_cast<CmpInst::Predicate>(MI.getOperand(i: 1).getPredicate());
386 auto Libcalls = getFCmpLibcalls(Predicate, Size: OpSize);
387
388 if (Libcalls.empty()) {
389 assert((Predicate == CmpInst::FCMP_TRUE ||
390 Predicate == CmpInst::FCMP_FALSE) &&
391 "Predicate needs libcalls, but none specified");
392 MIRBuilder.buildConstant(Res: OriginalResult,
393 Val: Predicate == CmpInst::FCMP_TRUE ? 1 : 0);
394 MI.eraseFromParent();
395 return true;
396 }
397
398 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size");
399 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(C&: Ctx) : Type::getDoubleTy(C&: Ctx);
400 auto *RetTy = Type::getInt32Ty(C&: Ctx);
401
402 SmallVector<Register, 2> Results;
403 for (auto Libcall : Libcalls) {
404 auto LibcallResult = MRI.createGenericVirtualRegister(Ty: LLT::scalar(SizeInBits: 32));
405 auto Status =
406 Helper.createLibcall(Libcall: Libcall.LibcallID, Result: {LibcallResult, RetTy, 0},
407 Args: {{MI.getOperand(i: 2).getReg(), ArgTy, 0},
408 {MI.getOperand(i: 3).getReg(), ArgTy, 0}},
409 LocObserver, MI: &MI);
410
411 if (Status != LegalizerHelper::Legalized)
412 return false;
413
414 auto ProcessedResult =
415 Libcalls.size() == 1
416 ? OriginalResult
417 : MRI.createGenericVirtualRegister(Ty: MRI.getType(Reg: OriginalResult));
418
419 // We have a result, but we need to transform it into a proper 1-bit 0 or
420 // 1, taking into account the different peculiarities of the values
421 // returned by the comparison functions.
422 CmpInst::Predicate ResultPred = Libcall.Predicate;
423 if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) {
424 // We have a nice 0 or 1, and we just need to truncate it back to 1 bit
425 // to keep the types consistent.
426 MIRBuilder.buildTrunc(Res: ProcessedResult, Op: LibcallResult);
427 } else {
428 // We need to compare against 0.
429 assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate");
430 auto Zero = MIRBuilder.buildConstant(Res: LLT::scalar(SizeInBits: 32), Val: 0);
431 MIRBuilder.buildICmp(Pred: ResultPred, Res: ProcessedResult, Op0: LibcallResult, Op1: Zero);
432 }
433 Results.push_back(Elt: ProcessedResult);
434 }
435
436 if (Results.size() != 1) {
437 assert(Results.size() == 2 && "Unexpected number of results");
438 MIRBuilder.buildOr(Dst: OriginalResult, Src0: Results[0], Src1: Results[1]);
439 }
440 break;
441 }
442 case G_CONSTANT: {
443 const ConstantInt *ConstVal = MI.getOperand(i: 1).getCImm();
444 uint64_t ImmVal = ConstVal->getZExtValue();
445 if (ConstantMaterializationCost(Val: ImmVal, Subtarget: &ST) > 2 && !ST.genExecuteOnly())
446 return Helper.lowerConstant(MI) == LegalizerHelper::Legalized;
447 return true;
448 }
449 case G_FCONSTANT: {
450 // Convert to integer constants, while preserving the binary representation.
451 auto AsInteger =
452 MI.getOperand(i: 1).getFPImm()->getValueAPF().bitcastToAPInt();
453 MIRBuilder.buildConstant(Res: MI.getOperand(i: 0),
454 Val: *ConstantInt::get(Context&: Ctx, V: AsInteger));
455 break;
456 }
457 case G_SET_FPMODE: {
458 // New FPSCR = (FPSCR & FPStatusBits) | (Modes & ~FPStatusBits)
459 LLT FPEnvTy = LLT::scalar(SizeInBits: 32);
460 auto FPEnv = MRI.createGenericVirtualRegister(Ty: FPEnvTy);
461 Register Modes = MI.getOperand(i: 0).getReg();
462 MIRBuilder.buildGetFPEnv(Dst: FPEnv);
463 auto StatusBitMask = MIRBuilder.buildConstant(Res: FPEnvTy, Val: ARM::FPStatusBits);
464 auto StatusBits = MIRBuilder.buildAnd(Dst: FPEnvTy, Src0: FPEnv, Src1: StatusBitMask);
465 auto NotStatusBitMask =
466 MIRBuilder.buildConstant(Res: FPEnvTy, Val: ~ARM::FPStatusBits);
467 auto FPModeBits = MIRBuilder.buildAnd(Dst: FPEnvTy, Src0: Modes, Src1: NotStatusBitMask);
468 auto NewFPSCR = MIRBuilder.buildOr(Dst: FPEnvTy, Src0: StatusBits, Src1: FPModeBits);
469 MIRBuilder.buildSetFPEnv(Src: NewFPSCR);
470 break;
471 }
472 case G_RESET_FPMODE: {
473 // To get the default FP mode all control bits are cleared:
474 // FPSCR = FPSCR & (FPStatusBits | FPReservedBits)
475 LLT FPEnvTy = LLT::scalar(SizeInBits: 32);
476 auto FPEnv = MIRBuilder.buildGetFPEnv(Dst: FPEnvTy);
477 auto NotModeBitMask = MIRBuilder.buildConstant(
478 Res: FPEnvTy, Val: ARM::FPStatusBits | ARM::FPReservedBits);
479 auto NewFPSCR = MIRBuilder.buildAnd(Dst: FPEnvTy, Src0: FPEnv, Src1: NotModeBitMask);
480 MIRBuilder.buildSetFPEnv(Src: NewFPSCR);
481 break;
482 }
483 }
484
485 MI.eraseFromParent();
486 return true;
487}
488