1//===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements the targeting of the Machinelegalizer class for ARM.
10/// \todo This should be generated by TableGen.
11//===----------------------------------------------------------------------===//
12
13#include "ARMLegalizerInfo.h"
14#include "ARMCallLowering.h"
15#include "ARMSubtarget.h"
16#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
17#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
18#include "llvm/CodeGen/LowLevelTypeUtils.h"
19#include "llvm/CodeGen/MachineRegisterInfo.h"
20#include "llvm/CodeGen/TargetOpcodes.h"
21#include "llvm/CodeGen/ValueTypes.h"
22#include "llvm/IR/DerivedTypes.h"
23#include "llvm/IR/Type.h"
24
25using namespace llvm;
26using namespace LegalizeActions;
27
28static bool AEABI(const ARMSubtarget &ST) {
29 return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI();
30}
31
32ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) : ST(ST) {
33 using namespace TargetOpcode;
34
35 const LLT p0 = LLT::pointer(AddressSpace: 0, SizeInBits: 32);
36
37 const LLT s1 = LLT::scalar(SizeInBits: 1);
38 const LLT s8 = LLT::scalar(SizeInBits: 8);
39 const LLT s16 = LLT::scalar(SizeInBits: 16);
40 const LLT s32 = LLT::scalar(SizeInBits: 32);
41 const LLT s64 = LLT::scalar(SizeInBits: 64);
42
43 auto &LegacyInfo = getLegacyLegalizerInfo();
44 if (ST.isThumb1Only()) {
45 // Thumb1 is not supported yet.
46 LegacyInfo.computeTables();
47 verify(MII: *ST.getInstrInfo());
48 return;
49 }
50
51 getActionDefinitionsBuilder(Opcodes: {G_SEXT, G_ZEXT, G_ANYEXT})
52 .legalForCartesianProduct(Types0: {s8, s16, s32}, Types1: {s1, s8, s16});
53
54 getActionDefinitionsBuilder(Opcode: G_TRUNC).legalForCartesianProduct(Types0: {s1, s8, s16},
55 Types1: {s8, s16, s32});
56
57 getActionDefinitionsBuilder(Opcode: G_SEXT_INREG).lower();
58
59 getActionDefinitionsBuilder(Opcodes: {G_MUL, G_AND, G_OR, G_XOR})
60 .legalFor(Types: {s32})
61 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
62
63 if (ST.hasNEON())
64 getActionDefinitionsBuilder(Opcodes: {G_ADD, G_SUB})
65 .legalFor(Types: {s32, s64})
66 .minScalar(TypeIdx: 0, Ty: s32);
67 else
68 getActionDefinitionsBuilder(Opcodes: {G_ADD, G_SUB})
69 .legalFor(Types: {s32})
70 .minScalar(TypeIdx: 0, Ty: s32);
71
72 getActionDefinitionsBuilder(Opcodes: {G_ASHR, G_LSHR, G_SHL})
73 .legalFor(Types: {{s32, s32}})
74 .minScalar(TypeIdx: 0, Ty: s32)
75 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s32);
76
77 bool HasHWDivide = (!ST.isThumb() && ST.hasDivideInARMMode()) ||
78 (ST.isThumb() && ST.hasDivideInThumbMode());
79 if (HasHWDivide)
80 getActionDefinitionsBuilder(Opcodes: {G_SDIV, G_UDIV})
81 .legalFor(Types: {s32})
82 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
83 else
84 getActionDefinitionsBuilder(Opcodes: {G_SDIV, G_UDIV})
85 .libcallFor(Types: {s32})
86 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
87
88 auto &REMBuilder =
89 getActionDefinitionsBuilder(Opcodes: {G_SREM, G_UREM}).minScalar(TypeIdx: 0, Ty: s32);
90 if (HasHWDivide)
91 REMBuilder.lowerFor(Types: {s32});
92 else if (AEABI(ST))
93 REMBuilder.customFor(Types: {s32});
94 else
95 REMBuilder.libcallFor(Types: {s32});
96
97 getActionDefinitionsBuilder(Opcode: G_INTTOPTR)
98 .legalFor(Types: {{p0, s32}})
99 .minScalar(TypeIdx: 1, Ty: s32);
100 getActionDefinitionsBuilder(Opcode: G_PTRTOINT)
101 .legalFor(Types: {{s32, p0}})
102 .minScalar(TypeIdx: 0, Ty: s32);
103
104 getActionDefinitionsBuilder(Opcode: G_CONSTANT)
105 .customFor(Types: {s32, p0})
106 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
107
108 getActionDefinitionsBuilder(Opcode: G_CONSTANT_POOL).legalFor(Types: {p0});
109
110 getActionDefinitionsBuilder(Opcode: G_ICMP)
111 .legalForCartesianProduct(Types0: {s1}, Types1: {s32, p0})
112 .minScalar(TypeIdx: 1, Ty: s32);
113
114 getActionDefinitionsBuilder(Opcode: G_SELECT)
115 .legalForCartesianProduct(Types0: {s32, p0}, Types1: {s1})
116 .minScalar(TypeIdx: 0, Ty: s32);
117
118 // We're keeping these builders around because we'll want to add support for
119 // floating point to them.
120 auto &LoadStoreBuilder = getActionDefinitionsBuilder(Opcodes: {G_LOAD, G_STORE})
121 .legalForTypesWithMemDesc(TypesAndMemDesc: {{.Type0: s8, .Type1: p0, .MemTy: s8, .Align: 8},
122 {.Type0: s16, .Type1: p0, .MemTy: s16, .Align: 8},
123 {.Type0: s32, .Type1: p0, .MemTy: s32, .Align: 8},
124 {.Type0: p0, .Type1: p0, .MemTy: p0, .Align: 8}})
125 .unsupportedIfMemSizeNotPow2();
126
127 getActionDefinitionsBuilder(Opcode: G_FRAME_INDEX).legalFor(Types: {p0});
128 getActionDefinitionsBuilder(Opcode: G_GLOBAL_VALUE).legalFor(Types: {p0});
129
130 auto &PhiBuilder =
131 getActionDefinitionsBuilder(Opcode: G_PHI)
132 .legalFor(Types: {s32, p0})
133 .minScalar(TypeIdx: 0, Ty: s32);
134
135 getActionDefinitionsBuilder(Opcode: G_PTR_ADD)
136 .legalFor(Types: {{p0, s32}})
137 .minScalar(TypeIdx: 1, Ty: s32);
138
139 getActionDefinitionsBuilder(Opcode: G_BR).alwaysLegal();
140 getActionDefinitionsBuilder(Opcode: G_BRCOND).legalFor(Types: {s1});
141
142 if (!ST.useSoftFloat() && ST.hasVFP2Base()) {
143 getActionDefinitionsBuilder(
144 Opcodes: {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG})
145 .legalFor(Types: {s32, s64});
146
147 LoadStoreBuilder
148 .legalForTypesWithMemDesc(TypesAndMemDesc: {{.Type0: s64, .Type1: p0, .MemTy: s64, .Align: 32}})
149 .maxScalar(TypeIdx: 0, Ty: s32);
150 PhiBuilder.legalFor(Types: {s64});
151
152 getActionDefinitionsBuilder(Opcode: G_FCMP).legalForCartesianProduct(Types0: {s1},
153 Types1: {s32, s64});
154
155 getActionDefinitionsBuilder(Opcode: G_MERGE_VALUES).legalFor(Types: {{s64, s32}});
156 getActionDefinitionsBuilder(Opcode: G_UNMERGE_VALUES).legalFor(Types: {{s32, s64}});
157
158 getActionDefinitionsBuilder(Opcode: G_FPEXT).legalFor(Types: {{s64, s32}});
159 getActionDefinitionsBuilder(Opcode: G_FPTRUNC).legalFor(Types: {{s32, s64}});
160
161 getActionDefinitionsBuilder(Opcodes: {G_FPTOSI, G_FPTOUI})
162 .legalForCartesianProduct(Types0: {s32}, Types1: {s32, s64});
163 getActionDefinitionsBuilder(Opcodes: {G_SITOFP, G_UITOFP})
164 .legalForCartesianProduct(Types0: {s32, s64}, Types1: {s32});
165
166 getActionDefinitionsBuilder(Opcodes: {G_GET_FPENV, G_SET_FPENV, G_GET_FPMODE})
167 .legalFor(Types: {s32});
168 getActionDefinitionsBuilder(Opcode: G_RESET_FPENV).alwaysLegal();
169 getActionDefinitionsBuilder(Opcode: G_SET_FPMODE).customFor(Types: {s32});
170 getActionDefinitionsBuilder(Opcode: G_RESET_FPMODE).custom();
171 } else {
172 getActionDefinitionsBuilder(Opcodes: {G_FADD, G_FSUB, G_FMUL, G_FDIV})
173 .libcallFor(Types: {s32, s64});
174
175 LoadStoreBuilder.maxScalar(TypeIdx: 0, Ty: s32);
176
177 getActionDefinitionsBuilder(Opcode: G_FNEG).lowerFor(Types: {s32, s64});
178
179 getActionDefinitionsBuilder(Opcode: G_FCONSTANT).customFor(Types: {s32, s64});
180
181 getActionDefinitionsBuilder(Opcode: G_FCMP).customForCartesianProduct(Types0: {s1},
182 Types1: {s32, s64});
183
184 if (AEABI(ST))
185 setFCmpLibcallsAEABI();
186 else
187 setFCmpLibcallsGNU();
188
189 getActionDefinitionsBuilder(Opcode: G_FPEXT).libcallFor(Types: {{s64, s32}});
190 getActionDefinitionsBuilder(Opcode: G_FPTRUNC).libcallFor(Types: {{s32, s64}});
191
192 getActionDefinitionsBuilder(Opcodes: {G_FPTOSI, G_FPTOUI})
193 .libcallForCartesianProduct(Types0: {s32}, Types1: {s32, s64});
194 getActionDefinitionsBuilder(Opcodes: {G_SITOFP, G_UITOFP})
195 .libcallForCartesianProduct(Types0: {s32, s64}, Types1: {s32});
196
197 getActionDefinitionsBuilder(Opcodes: {G_GET_FPENV, G_SET_FPENV, G_RESET_FPENV})
198 .libcall();
199 getActionDefinitionsBuilder(Opcodes: {G_GET_FPMODE, G_SET_FPMODE, G_RESET_FPMODE})
200 .libcall();
201 }
202
203 // Just expand whatever loads and stores are left.
204 LoadStoreBuilder.lower();
205
206 if (!ST.useSoftFloat() && ST.hasVFP4Base())
207 getActionDefinitionsBuilder(Opcode: G_FMA).legalFor(Types: {s32, s64});
208 else
209 getActionDefinitionsBuilder(Opcode: G_FMA).libcallFor(Types: {s32, s64});
210
211 getActionDefinitionsBuilder(Opcodes: {G_FREM, G_FPOW}).libcallFor(Types: {s32, s64});
212
213 if (ST.hasV5TOps() && !ST.isThumb1Only()) {
214 getActionDefinitionsBuilder(Opcode: G_CTLZ)
215 .legalFor(Types: {s32, s32})
216 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s32)
217 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
218 getActionDefinitionsBuilder(Opcode: G_CTLZ_ZERO_POISON)
219 .lowerFor(Types: {s32, s32})
220 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s32)
221 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
222 } else {
223 getActionDefinitionsBuilder(Opcode: G_CTLZ_ZERO_POISON)
224 .libcallFor(Types: {s32, s32})
225 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s32)
226 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
227 getActionDefinitionsBuilder(Opcode: G_CTLZ)
228 .lowerFor(Types: {s32, s32})
229 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s32)
230 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
231 }
232
233 LegacyInfo.computeTables();
234 verify(MII: *ST.getInstrInfo());
235}
236
237void ARMLegalizerInfo::setFCmpLibcallsAEABI() {
238 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
239 // default-initialized.
240 FCmp32Libcalls.resize(S: CmpInst::LAST_FCMP_PREDICATE + 1);
241 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {
242 {.LibcallID: RTLIB::OEQ_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
243 FCmp32Libcalls[CmpInst::FCMP_OGE] = {
244 {.LibcallID: RTLIB::OGE_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
245 FCmp32Libcalls[CmpInst::FCMP_OGT] = {
246 {.LibcallID: RTLIB::OGT_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
247 FCmp32Libcalls[CmpInst::FCMP_OLE] = {
248 {.LibcallID: RTLIB::OLE_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
249 FCmp32Libcalls[CmpInst::FCMP_OLT] = {
250 {.LibcallID: RTLIB::OLT_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
251 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{.LibcallID: RTLIB::UO_F32, .Predicate: CmpInst::ICMP_EQ}};
252 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{.LibcallID: RTLIB::OLT_F32, .Predicate: CmpInst::ICMP_EQ}};
253 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{.LibcallID: RTLIB::OLE_F32, .Predicate: CmpInst::ICMP_EQ}};
254 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{.LibcallID: RTLIB::OGT_F32, .Predicate: CmpInst::ICMP_EQ}};
255 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{.LibcallID: RTLIB::OGE_F32, .Predicate: CmpInst::ICMP_EQ}};
256 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{.LibcallID: RTLIB::UNE_F32, .Predicate: CmpInst::ICMP_EQ}};
257 FCmp32Libcalls[CmpInst::FCMP_UNO] = {
258 {.LibcallID: RTLIB::UO_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
259 FCmp32Libcalls[CmpInst::FCMP_ONE] = {
260 {.LibcallID: RTLIB::OGT_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE},
261 {.LibcallID: RTLIB::OLT_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
262 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {
263 {.LibcallID: RTLIB::OEQ_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE},
264 {.LibcallID: RTLIB::UO_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
265
266 FCmp64Libcalls.resize(S: CmpInst::LAST_FCMP_PREDICATE + 1);
267 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {
268 {.LibcallID: RTLIB::OEQ_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
269 FCmp64Libcalls[CmpInst::FCMP_OGE] = {
270 {.LibcallID: RTLIB::OGE_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
271 FCmp64Libcalls[CmpInst::FCMP_OGT] = {
272 {.LibcallID: RTLIB::OGT_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
273 FCmp64Libcalls[CmpInst::FCMP_OLE] = {
274 {.LibcallID: RTLIB::OLE_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
275 FCmp64Libcalls[CmpInst::FCMP_OLT] = {
276 {.LibcallID: RTLIB::OLT_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
277 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{.LibcallID: RTLIB::UO_F64, .Predicate: CmpInst::ICMP_EQ}};
278 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{.LibcallID: RTLIB::OLT_F64, .Predicate: CmpInst::ICMP_EQ}};
279 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{.LibcallID: RTLIB::OLE_F64, .Predicate: CmpInst::ICMP_EQ}};
280 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{.LibcallID: RTLIB::OGT_F64, .Predicate: CmpInst::ICMP_EQ}};
281 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{.LibcallID: RTLIB::OGE_F64, .Predicate: CmpInst::ICMP_EQ}};
282 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{.LibcallID: RTLIB::UNE_F64, .Predicate: CmpInst::ICMP_EQ}};
283 FCmp64Libcalls[CmpInst::FCMP_UNO] = {
284 {.LibcallID: RTLIB::UO_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
285 FCmp64Libcalls[CmpInst::FCMP_ONE] = {
286 {.LibcallID: RTLIB::OGT_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE},
287 {.LibcallID: RTLIB::OLT_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
288 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {
289 {.LibcallID: RTLIB::OEQ_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE},
290 {.LibcallID: RTLIB::UO_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
291}
292
293void ARMLegalizerInfo::setFCmpLibcallsGNU() {
294 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
295 // default-initialized.
296 FCmp32Libcalls.resize(S: CmpInst::LAST_FCMP_PREDICATE + 1);
297 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{.LibcallID: RTLIB::OEQ_F32, .Predicate: CmpInst::ICMP_EQ}};
298 FCmp32Libcalls[CmpInst::FCMP_OGE] = {{.LibcallID: RTLIB::OGE_F32, .Predicate: CmpInst::ICMP_SGE}};
299 FCmp32Libcalls[CmpInst::FCMP_OGT] = {{.LibcallID: RTLIB::OGT_F32, .Predicate: CmpInst::ICMP_SGT}};
300 FCmp32Libcalls[CmpInst::FCMP_OLE] = {{.LibcallID: RTLIB::OLE_F32, .Predicate: CmpInst::ICMP_SLE}};
301 FCmp32Libcalls[CmpInst::FCMP_OLT] = {{.LibcallID: RTLIB::OLT_F32, .Predicate: CmpInst::ICMP_SLT}};
302 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{.LibcallID: RTLIB::UO_F32, .Predicate: CmpInst::ICMP_EQ}};
303 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{.LibcallID: RTLIB::OLT_F32, .Predicate: CmpInst::ICMP_SGE}};
304 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{.LibcallID: RTLIB::OLE_F32, .Predicate: CmpInst::ICMP_SGT}};
305 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{.LibcallID: RTLIB::OGT_F32, .Predicate: CmpInst::ICMP_SLE}};
306 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{.LibcallID: RTLIB::OGE_F32, .Predicate: CmpInst::ICMP_SLT}};
307 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{.LibcallID: RTLIB::UNE_F32, .Predicate: CmpInst::ICMP_NE}};
308 FCmp32Libcalls[CmpInst::FCMP_UNO] = {{.LibcallID: RTLIB::UO_F32, .Predicate: CmpInst::ICMP_NE}};
309 FCmp32Libcalls[CmpInst::FCMP_ONE] = {{.LibcallID: RTLIB::OGT_F32, .Predicate: CmpInst::ICMP_SGT},
310 {.LibcallID: RTLIB::OLT_F32, .Predicate: CmpInst::ICMP_SLT}};
311 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{.LibcallID: RTLIB::OEQ_F32, .Predicate: CmpInst::ICMP_EQ},
312 {.LibcallID: RTLIB::UO_F32, .Predicate: CmpInst::ICMP_NE}};
313
314 FCmp64Libcalls.resize(S: CmpInst::LAST_FCMP_PREDICATE + 1);
315 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{.LibcallID: RTLIB::OEQ_F64, .Predicate: CmpInst::ICMP_EQ}};
316 FCmp64Libcalls[CmpInst::FCMP_OGE] = {{.LibcallID: RTLIB::OGE_F64, .Predicate: CmpInst::ICMP_SGE}};
317 FCmp64Libcalls[CmpInst::FCMP_OGT] = {{.LibcallID: RTLIB::OGT_F64, .Predicate: CmpInst::ICMP_SGT}};
318 FCmp64Libcalls[CmpInst::FCMP_OLE] = {{.LibcallID: RTLIB::OLE_F64, .Predicate: CmpInst::ICMP_SLE}};
319 FCmp64Libcalls[CmpInst::FCMP_OLT] = {{.LibcallID: RTLIB::OLT_F64, .Predicate: CmpInst::ICMP_SLT}};
320 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{.LibcallID: RTLIB::UO_F64, .Predicate: CmpInst::ICMP_EQ}};
321 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{.LibcallID: RTLIB::OLT_F64, .Predicate: CmpInst::ICMP_SGE}};
322 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{.LibcallID: RTLIB::OLE_F64, .Predicate: CmpInst::ICMP_SGT}};
323 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{.LibcallID: RTLIB::OGT_F64, .Predicate: CmpInst::ICMP_SLE}};
324 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{.LibcallID: RTLIB::OGE_F64, .Predicate: CmpInst::ICMP_SLT}};
325 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{.LibcallID: RTLIB::UNE_F64, .Predicate: CmpInst::ICMP_NE}};
326 FCmp64Libcalls[CmpInst::FCMP_UNO] = {{.LibcallID: RTLIB::UO_F64, .Predicate: CmpInst::ICMP_NE}};
327 FCmp64Libcalls[CmpInst::FCMP_ONE] = {{.LibcallID: RTLIB::OGT_F64, .Predicate: CmpInst::ICMP_SGT},
328 {.LibcallID: RTLIB::OLT_F64, .Predicate: CmpInst::ICMP_SLT}};
329 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{.LibcallID: RTLIB::OEQ_F64, .Predicate: CmpInst::ICMP_EQ},
330 {.LibcallID: RTLIB::UO_F64, .Predicate: CmpInst::ICMP_NE}};
331}
332
333ARMLegalizerInfo::FCmpLibcallsList
334ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate,
335 unsigned Size) const {
336 assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate");
337 if (Size == 32)
338 return FCmp32Libcalls[Predicate];
339 if (Size == 64)
340 return FCmp64Libcalls[Predicate];
341 llvm_unreachable("Unsupported size for FCmp predicate");
342}
343
344bool ARMLegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
345 LostDebugLocObserver &LocObserver) const {
346 using namespace TargetOpcode;
347
348 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
349 MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
350 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
351
352 switch (MI.getOpcode()) {
353 default:
354 return false;
355 case G_SREM:
356 case G_UREM: {
357 Register OriginalResult = MI.getOperand(i: 0).getReg();
358 auto Size = MRI.getType(Reg: OriginalResult).getSizeInBits();
359 if (Size != 32)
360 return false;
361
362 auto Libcall =
363 MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
364
365 // Our divmod libcalls return a struct containing the quotient and the
366 // remainder. Create a new, unused register for the quotient and use the
367 // destination of the original instruction for the remainder.
368 Type *ArgTy = Type::getInt32Ty(C&: Ctx);
369 StructType *RetTy = StructType::get(Context&: Ctx, Elements: {ArgTy, ArgTy}, /* Packed */ isPacked: true);
370 Register RetRegs[] = {MRI.createGenericVirtualRegister(Ty: LLT::scalar(SizeInBits: 32)),
371 OriginalResult};
372 auto Status = Helper.createLibcall(Libcall, Result: {RetRegs, RetTy, 0},
373 Args: {{MI.getOperand(i: 1).getReg(), ArgTy, 0},
374 {MI.getOperand(i: 2).getReg(), ArgTy, 0}},
375 LocObserver, MI: &MI);
376 if (Status != LegalizerHelper::Legalized)
377 return false;
378 break;
379 }
380 case G_FCMP: {
381 assert(MRI.getType(MI.getOperand(2).getReg()) ==
382 MRI.getType(MI.getOperand(3).getReg()) &&
383 "Mismatched operands for G_FCMP");
384 auto OpSize = MRI.getType(Reg: MI.getOperand(i: 2).getReg()).getSizeInBits();
385
386 auto OriginalResult = MI.getOperand(i: 0).getReg();
387 auto Predicate =
388 static_cast<CmpInst::Predicate>(MI.getOperand(i: 1).getPredicate());
389 auto Libcalls = getFCmpLibcalls(Predicate, Size: OpSize);
390
391 if (Libcalls.empty()) {
392 assert((Predicate == CmpInst::FCMP_TRUE ||
393 Predicate == CmpInst::FCMP_FALSE) &&
394 "Predicate needs libcalls, but none specified");
395 MIRBuilder.buildConstant(Res: OriginalResult,
396 Val: Predicate == CmpInst::FCMP_TRUE ? 1 : 0);
397 MI.eraseFromParent();
398 return true;
399 }
400
401 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size");
402 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(C&: Ctx) : Type::getDoubleTy(C&: Ctx);
403 auto *RetTy = Type::getInt32Ty(C&: Ctx);
404
405 SmallVector<Register, 2> Results;
406 for (auto Libcall : Libcalls) {
407 auto LibcallResult = MRI.createGenericVirtualRegister(Ty: LLT::scalar(SizeInBits: 32));
408 auto Status =
409 Helper.createLibcall(Libcall: Libcall.LibcallID, Result: {LibcallResult, RetTy, 0},
410 Args: {{MI.getOperand(i: 2).getReg(), ArgTy, 0},
411 {MI.getOperand(i: 3).getReg(), ArgTy, 0}},
412 LocObserver, MI: &MI);
413
414 if (Status != LegalizerHelper::Legalized)
415 return false;
416
417 auto ProcessedResult =
418 Libcalls.size() == 1
419 ? OriginalResult
420 : MRI.createGenericVirtualRegister(Ty: MRI.getType(Reg: OriginalResult));
421
422 // We have a result, but we need to transform it into a proper 1-bit 0 or
423 // 1, taking into account the different peculiarities of the values
424 // returned by the comparison functions.
425 CmpInst::Predicate ResultPred = Libcall.Predicate;
426 if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) {
427 // We have a nice 0 or 1, and we just need to truncate it back to 1 bit
428 // to keep the types consistent.
429 MIRBuilder.buildTrunc(Res: ProcessedResult, Op: LibcallResult);
430 } else {
431 // We need to compare against 0.
432 assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate");
433 auto Zero = MIRBuilder.buildConstant(Res: LLT::scalar(SizeInBits: 32), Val: 0);
434 MIRBuilder.buildICmp(Pred: ResultPred, Res: ProcessedResult, Op0: LibcallResult, Op1: Zero);
435 }
436 Results.push_back(Elt: ProcessedResult);
437 }
438
439 if (Results.size() != 1) {
440 assert(Results.size() == 2 && "Unexpected number of results");
441 MIRBuilder.buildOr(Dst: OriginalResult, Src0: Results[0], Src1: Results[1]);
442 }
443 break;
444 }
445 case G_CONSTANT: {
446 const ConstantInt *ConstVal = MI.getOperand(i: 1).getCImm();
447 uint64_t ImmVal = ConstVal->getZExtValue();
448 if (ConstantMaterializationCost(Val: ImmVal, Subtarget: &ST) > 2 && !ST.genExecuteOnly())
449 return Helper.lowerConstant(MI) == LegalizerHelper::Legalized;
450 return true;
451 }
452 case G_FCONSTANT: {
453 // Convert to integer constants, while preserving the binary representation.
454 auto AsInteger =
455 MI.getOperand(i: 1).getFPImm()->getValueAPF().bitcastToAPInt();
456 MIRBuilder.buildConstant(Res: MI.getOperand(i: 0),
457 Val: *ConstantInt::get(Context&: Ctx, V: AsInteger));
458 break;
459 }
460 case G_SET_FPMODE: {
461 // New FPSCR = (FPSCR & FPStatusBits) | (Modes & ~FPStatusBits)
462 LLT FPEnvTy = LLT::scalar(SizeInBits: 32);
463 auto FPEnv = MRI.createGenericVirtualRegister(Ty: FPEnvTy);
464 Register Modes = MI.getOperand(i: 0).getReg();
465 MIRBuilder.buildGetFPEnv(Dst: FPEnv);
466 auto StatusBitMask = MIRBuilder.buildConstant(Res: FPEnvTy, Val: ARM::FPStatusBits);
467 auto StatusBits = MIRBuilder.buildAnd(Dst: FPEnvTy, Src0: FPEnv, Src1: StatusBitMask);
468 auto NotStatusBitMask =
469 MIRBuilder.buildConstant(Res: FPEnvTy, Val: ~ARM::FPStatusBits);
470 auto FPModeBits = MIRBuilder.buildAnd(Dst: FPEnvTy, Src0: Modes, Src1: NotStatusBitMask);
471 auto NewFPSCR = MIRBuilder.buildOr(Dst: FPEnvTy, Src0: StatusBits, Src1: FPModeBits);
472 MIRBuilder.buildSetFPEnv(Src: NewFPSCR);
473 break;
474 }
475 case G_RESET_FPMODE: {
476 // To get the default FP mode all control bits are cleared:
477 // FPSCR = FPSCR & (FPStatusBits | FPReservedBits)
478 LLT FPEnvTy = LLT::scalar(SizeInBits: 32);
479 auto FPEnv = MIRBuilder.buildGetFPEnv(Dst: FPEnvTy);
480 auto NotModeBitMask = MIRBuilder.buildConstant(
481 Res: FPEnvTy, Val: ARM::FPStatusBits | ARM::FPReservedBits);
482 auto NewFPSCR = MIRBuilder.buildAnd(Dst: FPEnvTy, Src0: FPEnv, Src1: NotModeBitMask);
483 MIRBuilder.buildSetFPEnv(Src: NewFPSCR);
484 break;
485 }
486 }
487
488 MI.eraseFromParent();
489 return true;
490}
491