1//===-- AVRFrameLowering.cpp - AVR Frame Information ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the AVR implementation of TargetFrameLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AVRFrameLowering.h"
14
15#include "AVR.h"
16#include "AVRInstrInfo.h"
17#include "AVRMachineFunctionInfo.h"
18#include "AVRTargetMachine.h"
19#include "MCTargetDesc/AVRMCTargetDesc.h"
20
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineFunction.h"
23#include "llvm/CodeGen/MachineFunctionPass.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/TargetFrameLowering.h"
27#include "llvm/CodeGen/TargetRegisterInfo.h"
28#include "llvm/Support/ErrorHandling.h"
29
30namespace llvm {
31
32AVRFrameLowering::AVRFrameLowering()
33 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(1), -2) {}
34
35bool AVRFrameLowering::canSimplifyCallFramePseudos(
36 const MachineFunction &MF) const {
37 // Always simplify call frame pseudo instructions, even when
38 // hasReservedCallFrame is false.
39 return true;
40}
41
42bool AVRFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
43 // Reserve call frame memory in function prologue under the following
44 // conditions:
45 // - Y pointer is reserved to be the frame pointer.
46 // - The function does not contain variable sized objects.
47
48 const MachineFrameInfo &MFI = MF.getFrameInfo();
49 return hasFP(MF) && !MFI.hasVarSizedObjects();
50}
51
52void AVRFrameLowering::emitPrologue(MachineFunction &MF,
53 MachineBasicBlock &MBB) const {
54 MachineBasicBlock::iterator MBBI = MBB.begin();
55 DebugLoc DL = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
56 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
57 const AVRInstrInfo &TII = *STI.getInstrInfo();
58 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
59 const MachineRegisterInfo &MRI = MF.getRegInfo();
60 bool HasFP = hasFP(MF);
61
62 // Interrupt handlers re-enable interrupts in function entry.
63 if (AFI->isInterruptHandler()) {
64 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::BSETs))
65 .addImm(Val: 0x07)
66 .setMIFlag(MachineInstr::FrameSetup);
67 }
68
69 // Emit special prologue code to save R1, R0 and SREG in interrupt/signal
70 // handlers before saving any other registers.
71 if (AFI->isInterruptOrSignalHandler()) {
72 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::PUSHRr))
73 .addReg(RegNo: STI.getTmpRegister(), Flags: RegState::Kill)
74 .setMIFlag(MachineInstr::FrameSetup);
75
76 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::INRdA), DestReg: STI.getTmpRegister())
77 .addImm(Val: STI.getIORegSREG())
78 .setMIFlag(MachineInstr::FrameSetup);
79 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::PUSHRr))
80 .addReg(RegNo: STI.getTmpRegister(), Flags: RegState::Kill)
81 .setMIFlag(MachineInstr::FrameSetup);
82 if (!MRI.reg_empty(RegNo: STI.getZeroRegister())) {
83 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::PUSHRr))
84 .addReg(RegNo: STI.getZeroRegister(), Flags: RegState::Kill)
85 .setMIFlag(MachineInstr::FrameSetup);
86 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::EORRdRr))
87 .addReg(RegNo: STI.getZeroRegister(), Flags: RegState::Define)
88 .addReg(RegNo: STI.getZeroRegister(), Flags: RegState::Kill)
89 .addReg(RegNo: STI.getZeroRegister(), Flags: RegState::Kill)
90 .setMIFlag(MachineInstr::FrameSetup);
91 }
92 }
93
94 // Early exit if the frame pointer is not needed in this function.
95 if (!HasFP) {
96 return;
97 }
98
99 const MachineFrameInfo &MFI = MF.getFrameInfo();
100 unsigned FrameSize = MFI.getStackSize() - AFI->getCalleeSavedFrameSize();
101
102 // Skip the callee-saved push instructions.
103 while (
104 (MBBI != MBB.end()) && MBBI->getFlag(Flag: MachineInstr::FrameSetup) &&
105 (MBBI->getOpcode() == AVR::PUSHRr || MBBI->getOpcode() == AVR::PUSHWRr)) {
106 ++MBBI;
107 }
108
109 // Update Y with the new base value.
110 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::SPREAD), DestReg: AVR::R29R28)
111 .addReg(RegNo: AVR::SP)
112 .setMIFlag(MachineInstr::FrameSetup);
113
114 // Mark the FramePtr as live-in in every block except the entry.
115 for (MachineBasicBlock &MBBJ : llvm::drop_begin(RangeOrContainer&: MF)) {
116 MBBJ.addLiveIn(PhysReg: AVR::R29R28);
117 }
118
119 if (!FrameSize) {
120 return;
121 }
122
123 // Reserve the necessary frame memory by doing FP -= <size>.
124 unsigned Opcode = (isUInt<6>(x: FrameSize) && STI.hasADDSUBIW()) ? AVR::SBIWRdK
125 : AVR::SUBIWRdK;
126
127 MachineInstr *MI = BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode), DestReg: AVR::R29R28)
128 .addReg(RegNo: AVR::R29R28, Flags: RegState::Kill)
129 .addImm(Val: FrameSize)
130 .setMIFlag(MachineInstr::FrameSetup);
131 // The SREG implicit def is dead.
132 MI->getOperand(i: 3).setIsDead();
133
134 // Write back R29R28 to SP and temporarily disable interrupts.
135 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::SPWRITE), DestReg: AVR::SP)
136 .addReg(RegNo: AVR::R29R28)
137 .setMIFlag(MachineInstr::FrameSetup);
138}
139
140static void restoreStatusRegister(MachineFunction &MF, MachineBasicBlock &MBB) {
141 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
142 const MachineRegisterInfo &MRI = MF.getRegInfo();
143
144 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
145
146 DebugLoc DL = MBBI->getDebugLoc();
147 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
148 const AVRInstrInfo &TII = *STI.getInstrInfo();
149
150 // Emit special epilogue code to restore R1, R0 and SREG in interrupt/signal
151 // handlers at the very end of the function, just before reti.
152 if (AFI->isInterruptOrSignalHandler()) {
153 if (!MRI.reg_empty(RegNo: STI.getZeroRegister())) {
154 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::POPRd), DestReg: STI.getZeroRegister());
155 }
156 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::POPRd), DestReg: STI.getTmpRegister());
157 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::OUTARr))
158 .addImm(Val: STI.getIORegSREG())
159 .addReg(RegNo: STI.getTmpRegister(), Flags: RegState::Kill);
160 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::POPRd), DestReg: STI.getTmpRegister());
161 }
162}
163
164void AVRFrameLowering::emitEpilogue(MachineFunction &MF,
165 MachineBasicBlock &MBB) const {
166 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
167
168 // Early exit if the frame pointer is not needed in this function except for
169 // signal/interrupt handlers where special code generation is required.
170 if (!hasFP(MF) && !AFI->isInterruptOrSignalHandler()) {
171 return;
172 }
173
174 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
175 assert(MBBI->getDesc().isReturn() &&
176 "Can only insert epilog into returning blocks");
177
178 DebugLoc DL = MBBI->getDebugLoc();
179 const MachineFrameInfo &MFI = MF.getFrameInfo();
180 unsigned FrameSize = MFI.getStackSize() - AFI->getCalleeSavedFrameSize();
181 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
182 const AVRInstrInfo &TII = *STI.getInstrInfo();
183
184 // Early exit if there is no need to restore the frame pointer.
185 if (!FrameSize && !MF.getFrameInfo().hasVarSizedObjects()) {
186 restoreStatusRegister(MF, MBB);
187 return;
188 }
189
190 // Skip the callee-saved pop instructions.
191 while (MBBI != MBB.begin()) {
192 MachineBasicBlock::iterator PI = std::prev(x: MBBI);
193 int Opc = PI->getOpcode();
194
195 if (Opc != AVR::POPRd && Opc != AVR::POPWRd && !PI->isTerminator()) {
196 break;
197 }
198
199 --MBBI;
200 }
201
202 if (FrameSize) {
203 // Restore the frame pointer by doing FP += <size>.
204 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::ADIWRdKP), DestReg: AVR::R29R28)
205 .addReg(RegNo: AVR::R29R28, Flags: RegState::Kill)
206 .addImm(Val: FrameSize)
207 .setOperandDead(3); // implicit-def $sreg
208 }
209
210 // Write back R29R28 to SP and temporarily disable interrupts.
211 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::SPWRITE), DestReg: AVR::SP)
212 .addReg(RegNo: AVR::R29R28, Flags: RegState::Kill);
213
214 restoreStatusRegister(MF, MBB);
215}
216
217StackOffset AVRFrameLowering::getFrameIndexReference(const MachineFunction &MF,
218 int FI,
219 Register &FrameReg) const {
220 int64_t Offset;
221 const MachineFrameInfo &MFI = MF.getFrameInfo();
222
223 switch (MFI.getStackID(ObjectIdx: FI)) {
224 case TargetStackID::Default:
225 Offset = MFI.getObjectOffset(ObjectIdx: FI) + MFI.getOffsetAdjustment() +
226 MFI.getStackSize() - getOffsetOfLocalArea() + 1;
227
228 assert(Offset > 0);
229 break;
230
231 case TargetStackID::AvrAlign:
232 Offset = MFI.getObjectOffset(ObjectIdx: FI);
233 assert(Offset >= 0);
234 break;
235
236 default:
237 llvm_unreachable("Unsupported stack!");
238 }
239
240 // Frame indices are addressed relative to the frame register (see
241 // AVRRegisterInfo::eliminateFrameIndex); callers such as the DWARF
242 // debug info emitter rely on it being reported back here.
243 FrameReg = MF.getSubtarget().getRegisterInfo()->getFrameRegister(MF);
244
245 return StackOffset::getFixed(Fixed: Offset);
246}
247
248// Return true if the specified function should have a dedicated frame
249// pointer register. This is true if the function meets any of the following
250// conditions:
251// - a register has been spilled
252// - has allocas
253// - input arguments are passed using the stack
254// - has variable sized objects
255// - the frame address is taken (llvm.frameaddress)
256// - the return address is taken (llvm.returnaddress)
257//
258// Notice that strictly this is not a frame pointer because it contains SP after
259// frame allocation instead of having the original SP in function entry.
260bool AVRFrameLowering::hasFPImpl(const MachineFunction &MF) const {
261 const MachineFrameInfo &MFI = MF.getFrameInfo();
262 const AVRMachineFunctionInfo *FuncInfo = MF.getInfo<AVRMachineFunctionInfo>();
263
264 // Note that reading the return address requires a frame index, and that frame
265 // indexes are always referenced through Y (see
266 // AVRRegisterInfo::eliminateFrameIndex).
267 return (FuncInfo->getHasSpills() || FuncInfo->getHasAllocas() ||
268 FuncInfo->getHasStackArgs() || MFI.hasVarSizedObjects() ||
269 MFI.isFrameAddressTaken() || MFI.isReturnAddressTaken());
270}
271
272bool AVRFrameLowering::spillCalleeSavedRegisters(
273 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
274 ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
275 if (CSI.empty()) {
276 return false;
277 }
278
279 unsigned CalleeFrameSize = 0;
280 DebugLoc DL = MBB.findDebugLoc(MBBI: MI);
281 MachineFunction &MF = *MBB.getParent();
282 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
283 const TargetInstrInfo &TII = *STI.getInstrInfo();
284 AVRMachineFunctionInfo *AVRFI = MF.getInfo<AVRMachineFunctionInfo>();
285
286 for (const CalleeSavedInfo &I : llvm::reverse(C&: CSI)) {
287 MCRegister Reg = I.getReg();
288 bool IsNotLiveIn = !MBB.isLiveIn(Reg);
289
290 // Check if Reg is a sub register of a 16-bit livein register, and then
291 // add it to the livein list.
292 if (IsNotLiveIn)
293 for (const auto &LiveIn : MBB.liveins())
294 if (STI.getRegisterInfo()->isSubRegister(RegA: LiveIn.PhysReg, RegB: Reg)) {
295 IsNotLiveIn = false;
296 MBB.addLiveIn(PhysReg: Reg);
297 break;
298 }
299
300 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 &&
301 "Invalid register size");
302
303 // Add the callee-saved register as live-in only if it is not already a
304 // live-in register, this usually happens with arguments that are passed
305 // through callee-saved registers.
306 if (IsNotLiveIn) {
307 MBB.addLiveIn(PhysReg: Reg);
308 }
309
310 // Do not kill the register when it is an input argument.
311 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: TII.get(Opcode: AVR::PUSHRr))
312 .addReg(RegNo: Reg, Flags: getKillRegState(B: IsNotLiveIn))
313 .setMIFlag(MachineInstr::FrameSetup);
314 ++CalleeFrameSize;
315 }
316
317 AVRFI->setCalleeSavedFrameSize(CalleeFrameSize);
318
319 return true;
320}
321
322bool AVRFrameLowering::restoreCalleeSavedRegisters(
323 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
324 MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
325 if (CSI.empty()) {
326 return false;
327 }
328
329 DebugLoc DL = MBB.findDebugLoc(MBBI: MI);
330 const MachineFunction &MF = *MBB.getParent();
331 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
332 const TargetInstrInfo &TII = *STI.getInstrInfo();
333
334 for (const CalleeSavedInfo &CCSI : CSI) {
335 MCRegister Reg = CCSI.getReg();
336
337 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 &&
338 "Invalid register size");
339
340 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: TII.get(Opcode: AVR::POPRd), DestReg: Reg);
341 }
342
343 return true;
344}
345
346/// Replace pseudo store instructions that pass arguments through the stack with
347/// real instructions.
348static void fixStackStores(MachineBasicBlock &MBB,
349 MachineBasicBlock::iterator StartMI,
350 const TargetInstrInfo &TII) {
351 // Iterate through the BB until we hit a call instruction or we reach the end.
352 for (MachineInstr &MI :
353 llvm::make_early_inc_range(Range: llvm::make_range(x: StartMI, y: MBB.end()))) {
354 if (MI.isCall())
355 break;
356
357 unsigned Opcode = MI.getOpcode();
358
359 // Only care of pseudo store instructions where SP is the base pointer.
360 if (Opcode != AVR::STDSPQRr && Opcode != AVR::STDWSPQRr)
361 continue;
362
363 assert(MI.getOperand(0).getReg() == AVR::SP &&
364 "SP is expected as base pointer");
365
366 // Replace this instruction with a regular store. Use Y as the base
367 // pointer since it is guaranteed to contain a copy of SP.
368 unsigned STOpc =
369 (Opcode == AVR::STDWSPQRr) ? AVR::STDWPtrQRr : AVR::STDPtrQRr;
370
371 MI.setDesc(TII.get(Opcode: STOpc));
372 MI.getOperand(i: 0).setReg(AVR::R31R30);
373 }
374}
375
376MachineBasicBlock::iterator AVRFrameLowering::eliminateCallFramePseudoInstr(
377 MachineFunction &MF, MachineBasicBlock &MBB,
378 MachineBasicBlock::iterator MI) const {
379 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
380 const AVRInstrInfo &TII = *STI.getInstrInfo();
381
382 if (hasReservedCallFrame(MF)) {
383 return MBB.erase(I: MI);
384 }
385
386 DebugLoc DL = MI->getDebugLoc();
387 unsigned int Opcode = MI->getOpcode();
388 int Amount = TII.getFrameSize(I: *MI);
389
390 if (Amount == 0) {
391 return MBB.erase(I: MI);
392 }
393
394 assert(getStackAlign() == Align(1) && "Unsupported stack alignment");
395
396 if (Opcode == TII.getCallFrameSetupOpcode()) {
397 // Update the stack pointer.
398 // In many cases this can be done far more efficiently by pushing the
399 // relevant values directly to the stack. However, doing that correctly
400 // (in the right order, possibly skipping some empty space for undef
401 // values, etc) is tricky and thus left to be optimized in the future.
402 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: TII.get(Opcode: AVR::SPREAD), DestReg: AVR::R31R30).addReg(RegNo: AVR::SP);
403
404 MachineInstr *New =
405 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: TII.get(Opcode: AVR::SUBIWRdK), DestReg: AVR::R31R30)
406 .addReg(RegNo: AVR::R31R30, Flags: RegState::Kill)
407 .addImm(Val: Amount);
408 New->getOperand(i: 3).setIsDead();
409
410 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: TII.get(Opcode: AVR::SPWRITE), DestReg: AVR::SP).addReg(RegNo: AVR::R31R30);
411
412 // Make sure the remaining stack stores are converted to real store
413 // instructions.
414 fixStackStores(MBB, StartMI: MI, TII);
415 } else {
416 assert(Opcode == TII.getCallFrameDestroyOpcode());
417
418 // Note that small stack changes could be implemented more efficiently
419 // with a few pop instructions instead of the 8-9 instructions now
420 // required.
421
422 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: TII.get(Opcode: AVR::SPREAD), DestReg: AVR::R31R30).addReg(RegNo: AVR::SP);
423
424 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: TII.get(Opcode: AVR::ADIWRdKP), DestReg: AVR::R31R30)
425 .addReg(RegNo: AVR::R31R30, Flags: RegState::Kill)
426 .addImm(Val: Amount)
427 .setOperandDead(3); // implicit-def $sreg
428
429 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: TII.get(Opcode: AVR::SPWRITE), DestReg: AVR::SP)
430 .addReg(RegNo: AVR::R31R30, Flags: RegState::Kill);
431 }
432
433 return MBB.erase(I: MI);
434}
435
436void AVRFrameLowering::determineCalleeSaves(MachineFunction &MF,
437 BitVector &SavedRegs,
438 RegScavenger *RS) const {
439 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
440
441 // If we have a frame pointer, the Y register needs to be saved as well.
442 if (hasFP(MF)) {
443 SavedRegs.set(AVR::R29);
444 SavedRegs.set(AVR::R28);
445 }
446}
447
448/// The frame analyzer pass.
449///
450/// Scans the function for allocas and used arguments
451/// that are passed through the stack.
452struct AVRFrameAnalyzer : public MachineFunctionPass {
453 static char ID;
454 AVRFrameAnalyzer() : MachineFunctionPass(ID) {}
455
456 bool runOnMachineFunction(MachineFunction &MF) override {
457 const MachineFrameInfo &MFI = MF.getFrameInfo();
458 AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
459
460 // If there are no fixed frame indexes during this stage it means there
461 // are allocas present in the function.
462 if (MFI.getNumObjects() != MFI.getNumFixedObjects()) {
463 // Check for the type of allocas present in the function. We only care
464 // about fixed size allocas so do not give false positives if only
465 // variable sized allocas are present.
466 for (unsigned i = 0, e = MFI.getObjectIndexEnd(); i != e; ++i) {
467 if (!MFI.isVariableSizedObjectIndex(ObjectIdx: i) && !MFI.isDeadObjectIndex(ObjectIdx: i)) {
468 AFI->setHasAllocas(true);
469 break;
470 }
471 }
472 }
473
474 // If there are fixed frame indexes present, scan the function to see if
475 // they are really being used.
476 if (MFI.getNumFixedObjects() == 0) {
477 return false;
478 }
479
480 // Ok fixed frame indexes present, now scan the function to see if they
481 // are really being used, otherwise we can ignore them.
482 for (const MachineBasicBlock &BB : MF) {
483 for (const MachineInstr &MI : BB) {
484 int Opcode = MI.getOpcode();
485
486 if ((Opcode != AVR::LDDRdPtrQ) && (Opcode != AVR::LDDWRdPtrQ) &&
487 (Opcode != AVR::STDPtrQRr) && (Opcode != AVR::STDWPtrQRr) &&
488 (Opcode != AVR::FRMIDX)) {
489 continue;
490 }
491
492 for (const MachineOperand &MO : MI.operands()) {
493 if (!MO.isFI()) {
494 continue;
495 }
496
497 if (MFI.isFixedObjectIndex(ObjectIdx: MO.getIndex())) {
498 AFI->setHasStackArgs(true);
499 return false;
500 }
501 }
502 }
503 }
504
505 return false;
506 }
507
508 StringRef getPassName() const override { return "AVR Frame Analyzer"; }
509};
510
511char AVRFrameAnalyzer::ID = 0;
512
513/// Creates instance of the frame analyzer pass.
514FunctionPass *createAVRFrameAnalyzerPass() { return new AVRFrameAnalyzer(); }
515
516} // end of namespace llvm
517