1//===-- AVRFrameLowering.cpp - AVR Frame Information ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the AVR implementation of TargetFrameLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AVRFrameLowering.h"
14
15#include "AVR.h"
16#include "AVRInstrInfo.h"
17#include "AVRMachineFunctionInfo.h"
18#include "AVRTargetMachine.h"
19#include "MCTargetDesc/AVRMCTargetDesc.h"
20
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineFunction.h"
23#include "llvm/CodeGen/MachineFunctionPass.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/TargetFrameLowering.h"
27#include "llvm/Support/ErrorHandling.h"
28
29namespace llvm {
30
31AVRFrameLowering::AVRFrameLowering()
32 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(1), -2) {}
33
34bool AVRFrameLowering::canSimplifyCallFramePseudos(
35 const MachineFunction &MF) const {
36 // Always simplify call frame pseudo instructions, even when
37 // hasReservedCallFrame is false.
38 return true;
39}
40
41bool AVRFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
42 // Reserve call frame memory in function prologue under the following
43 // conditions:
44 // - Y pointer is reserved to be the frame pointer.
45 // - The function does not contain variable sized objects.
46
47 const MachineFrameInfo &MFI = MF.getFrameInfo();
48 return hasFP(MF) && !MFI.hasVarSizedObjects();
49}
50
51void AVRFrameLowering::emitPrologue(MachineFunction &MF,
52 MachineBasicBlock &MBB) const {
53 MachineBasicBlock::iterator MBBI = MBB.begin();
54 DebugLoc DL = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
55 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
56 const AVRInstrInfo &TII = *STI.getInstrInfo();
57 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
58 const MachineRegisterInfo &MRI = MF.getRegInfo();
59 bool HasFP = hasFP(MF);
60
61 // Interrupt handlers re-enable interrupts in function entry.
62 if (AFI->isInterruptHandler()) {
63 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::BSETs))
64 .addImm(Val: 0x07)
65 .setMIFlag(MachineInstr::FrameSetup);
66 }
67
68 // Emit special prologue code to save R1, R0 and SREG in interrupt/signal
69 // handlers before saving any other registers.
70 if (AFI->isInterruptOrSignalHandler()) {
71 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::PUSHRr))
72 .addReg(RegNo: STI.getTmpRegister(), Flags: RegState::Kill)
73 .setMIFlag(MachineInstr::FrameSetup);
74
75 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::INRdA), DestReg: STI.getTmpRegister())
76 .addImm(Val: STI.getIORegSREG())
77 .setMIFlag(MachineInstr::FrameSetup);
78 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::PUSHRr))
79 .addReg(RegNo: STI.getTmpRegister(), Flags: RegState::Kill)
80 .setMIFlag(MachineInstr::FrameSetup);
81 if (!MRI.reg_empty(RegNo: STI.getZeroRegister())) {
82 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::PUSHRr))
83 .addReg(RegNo: STI.getZeroRegister(), Flags: RegState::Kill)
84 .setMIFlag(MachineInstr::FrameSetup);
85 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::EORRdRr))
86 .addReg(RegNo: STI.getZeroRegister(), Flags: RegState::Define)
87 .addReg(RegNo: STI.getZeroRegister(), Flags: RegState::Kill)
88 .addReg(RegNo: STI.getZeroRegister(), Flags: RegState::Kill)
89 .setMIFlag(MachineInstr::FrameSetup);
90 }
91 }
92
93 // Early exit if the frame pointer is not needed in this function.
94 if (!HasFP) {
95 return;
96 }
97
98 const MachineFrameInfo &MFI = MF.getFrameInfo();
99 unsigned FrameSize = MFI.getStackSize() - AFI->getCalleeSavedFrameSize();
100
101 // Skip the callee-saved push instructions.
102 while (
103 (MBBI != MBB.end()) && MBBI->getFlag(Flag: MachineInstr::FrameSetup) &&
104 (MBBI->getOpcode() == AVR::PUSHRr || MBBI->getOpcode() == AVR::PUSHWRr)) {
105 ++MBBI;
106 }
107
108 // Update Y with the new base value.
109 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::SPREAD), DestReg: AVR::R29R28)
110 .addReg(RegNo: AVR::SP)
111 .setMIFlag(MachineInstr::FrameSetup);
112
113 // Mark the FramePtr as live-in in every block except the entry.
114 for (MachineBasicBlock &MBBJ : llvm::drop_begin(RangeOrContainer&: MF)) {
115 MBBJ.addLiveIn(PhysReg: AVR::R29R28);
116 }
117
118 if (!FrameSize) {
119 return;
120 }
121
122 // Reserve the necessary frame memory by doing FP -= <size>.
123 unsigned Opcode = (isUInt<6>(x: FrameSize) && STI.hasADDSUBIW()) ? AVR::SBIWRdK
124 : AVR::SUBIWRdK;
125
126 MachineInstr *MI = BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode), DestReg: AVR::R29R28)
127 .addReg(RegNo: AVR::R29R28, Flags: RegState::Kill)
128 .addImm(Val: FrameSize)
129 .setMIFlag(MachineInstr::FrameSetup);
130 // The SREG implicit def is dead.
131 MI->getOperand(i: 3).setIsDead();
132
133 // Write back R29R28 to SP and temporarily disable interrupts.
134 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::SPWRITE), DestReg: AVR::SP)
135 .addReg(RegNo: AVR::R29R28)
136 .setMIFlag(MachineInstr::FrameSetup);
137}
138
139static void restoreStatusRegister(MachineFunction &MF, MachineBasicBlock &MBB) {
140 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
141 const MachineRegisterInfo &MRI = MF.getRegInfo();
142
143 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
144
145 DebugLoc DL = MBBI->getDebugLoc();
146 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
147 const AVRInstrInfo &TII = *STI.getInstrInfo();
148
149 // Emit special epilogue code to restore R1, R0 and SREG in interrupt/signal
150 // handlers at the very end of the function, just before reti.
151 if (AFI->isInterruptOrSignalHandler()) {
152 if (!MRI.reg_empty(RegNo: STI.getZeroRegister())) {
153 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::POPRd), DestReg: STI.getZeroRegister());
154 }
155 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::POPRd), DestReg: STI.getTmpRegister());
156 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::OUTARr))
157 .addImm(Val: STI.getIORegSREG())
158 .addReg(RegNo: STI.getTmpRegister(), Flags: RegState::Kill);
159 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::POPRd), DestReg: STI.getTmpRegister());
160 }
161}
162
163void AVRFrameLowering::emitEpilogue(MachineFunction &MF,
164 MachineBasicBlock &MBB) const {
165 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
166
167 // Early exit if the frame pointer is not needed in this function except for
168 // signal/interrupt handlers where special code generation is required.
169 if (!hasFP(MF) && !AFI->isInterruptOrSignalHandler()) {
170 return;
171 }
172
173 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
174 assert(MBBI->getDesc().isReturn() &&
175 "Can only insert epilog into returning blocks");
176
177 DebugLoc DL = MBBI->getDebugLoc();
178 const MachineFrameInfo &MFI = MF.getFrameInfo();
179 unsigned FrameSize = MFI.getStackSize() - AFI->getCalleeSavedFrameSize();
180 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
181 const AVRInstrInfo &TII = *STI.getInstrInfo();
182
183 // Early exit if there is no need to restore the frame pointer.
184 if (!FrameSize && !MF.getFrameInfo().hasVarSizedObjects()) {
185 restoreStatusRegister(MF, MBB);
186 return;
187 }
188
189 // Skip the callee-saved pop instructions.
190 while (MBBI != MBB.begin()) {
191 MachineBasicBlock::iterator PI = std::prev(x: MBBI);
192 int Opc = PI->getOpcode();
193
194 if (Opc != AVR::POPRd && Opc != AVR::POPWRd && !PI->isTerminator()) {
195 break;
196 }
197
198 --MBBI;
199 }
200
201 if (FrameSize) {
202 // Restore the frame pointer by doing FP += <size>.
203 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::ADIWRdKP), DestReg: AVR::R29R28)
204 .addReg(RegNo: AVR::R29R28, Flags: RegState::Kill)
205 .addImm(Val: FrameSize)
206 .setOperandDead(3); // implicit-def $sreg
207 }
208
209 // Write back R29R28 to SP and temporarily disable interrupts.
210 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: AVR::SPWRITE), DestReg: AVR::SP)
211 .addReg(RegNo: AVR::R29R28, Flags: RegState::Kill);
212
213 restoreStatusRegister(MF, MBB);
214}
215
216StackOffset AVRFrameLowering::getFrameIndexReference(const MachineFunction &MF,
217 int FI,
218 Register &FrameReg) const {
219 int64_t Offset;
220 const MachineFrameInfo &MFI = MF.getFrameInfo();
221
222 switch (MFI.getStackID(ObjectIdx: FI)) {
223 case TargetStackID::Default:
224 Offset = MFI.getObjectOffset(ObjectIdx: FI) + MFI.getOffsetAdjustment() +
225 MFI.getStackSize() - getOffsetOfLocalArea() + 1;
226
227 assert(Offset > 0);
228 break;
229
230 case TargetStackID::AvrAlign:
231 Offset = MFI.getObjectOffset(ObjectIdx: FI);
232 assert(Offset >= 0);
233 break;
234
235 default:
236 llvm_unreachable("Unsupported stack!");
237 }
238
239 return StackOffset::getFixed(Fixed: Offset);
240}
241
242// Return true if the specified function should have a dedicated frame
243// pointer register. This is true if the function meets any of the following
244// conditions:
245// - a register has been spilled
246// - has allocas
247// - input arguments are passed using the stack
248//
249// Notice that strictly this is not a frame pointer because it contains SP after
250// frame allocation instead of having the original SP in function entry.
251bool AVRFrameLowering::hasFPImpl(const MachineFunction &MF) const {
252 const AVRMachineFunctionInfo *FuncInfo = MF.getInfo<AVRMachineFunctionInfo>();
253
254 return (FuncInfo->getHasSpills() || FuncInfo->getHasAllocas() ||
255 FuncInfo->getHasStackArgs() ||
256 MF.getFrameInfo().hasVarSizedObjects());
257}
258
259bool AVRFrameLowering::spillCalleeSavedRegisters(
260 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
261 ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
262 if (CSI.empty()) {
263 return false;
264 }
265
266 unsigned CalleeFrameSize = 0;
267 DebugLoc DL = MBB.findDebugLoc(MBBI: MI);
268 MachineFunction &MF = *MBB.getParent();
269 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
270 const TargetInstrInfo &TII = *STI.getInstrInfo();
271 AVRMachineFunctionInfo *AVRFI = MF.getInfo<AVRMachineFunctionInfo>();
272
273 for (const CalleeSavedInfo &I : llvm::reverse(C&: CSI)) {
274 MCRegister Reg = I.getReg();
275 bool IsNotLiveIn = !MBB.isLiveIn(Reg);
276
277 // Check if Reg is a sub register of a 16-bit livein register, and then
278 // add it to the livein list.
279 if (IsNotLiveIn)
280 for (const auto &LiveIn : MBB.liveins())
281 if (STI.getRegisterInfo()->isSubRegister(RegA: LiveIn.PhysReg, RegB: Reg)) {
282 IsNotLiveIn = false;
283 MBB.addLiveIn(PhysReg: Reg);
284 break;
285 }
286
287 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 &&
288 "Invalid register size");
289
290 // Add the callee-saved register as live-in only if it is not already a
291 // live-in register, this usually happens with arguments that are passed
292 // through callee-saved registers.
293 if (IsNotLiveIn) {
294 MBB.addLiveIn(PhysReg: Reg);
295 }
296
297 // Do not kill the register when it is an input argument.
298 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: TII.get(Opcode: AVR::PUSHRr))
299 .addReg(RegNo: Reg, Flags: getKillRegState(B: IsNotLiveIn))
300 .setMIFlag(MachineInstr::FrameSetup);
301 ++CalleeFrameSize;
302 }
303
304 AVRFI->setCalleeSavedFrameSize(CalleeFrameSize);
305
306 return true;
307}
308
309bool AVRFrameLowering::restoreCalleeSavedRegisters(
310 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
311 MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
312 if (CSI.empty()) {
313 return false;
314 }
315
316 DebugLoc DL = MBB.findDebugLoc(MBBI: MI);
317 const MachineFunction &MF = *MBB.getParent();
318 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
319 const TargetInstrInfo &TII = *STI.getInstrInfo();
320
321 for (const CalleeSavedInfo &CCSI : CSI) {
322 MCRegister Reg = CCSI.getReg();
323
324 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 &&
325 "Invalid register size");
326
327 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: TII.get(Opcode: AVR::POPRd), DestReg: Reg);
328 }
329
330 return true;
331}
332
333/// Replace pseudo store instructions that pass arguments through the stack with
334/// real instructions.
335static void fixStackStores(MachineBasicBlock &MBB,
336 MachineBasicBlock::iterator StartMI,
337 const TargetInstrInfo &TII) {
338 // Iterate through the BB until we hit a call instruction or we reach the end.
339 for (MachineInstr &MI :
340 llvm::make_early_inc_range(Range: llvm::make_range(x: StartMI, y: MBB.end()))) {
341 if (MI.isCall())
342 break;
343
344 unsigned Opcode = MI.getOpcode();
345
346 // Only care of pseudo store instructions where SP is the base pointer.
347 if (Opcode != AVR::STDSPQRr && Opcode != AVR::STDWSPQRr)
348 continue;
349
350 assert(MI.getOperand(0).getReg() == AVR::SP &&
351 "SP is expected as base pointer");
352
353 // Replace this instruction with a regular store. Use Y as the base
354 // pointer since it is guaranteed to contain a copy of SP.
355 unsigned STOpc =
356 (Opcode == AVR::STDWSPQRr) ? AVR::STDWPtrQRr : AVR::STDPtrQRr;
357
358 MI.setDesc(TII.get(Opcode: STOpc));
359 MI.getOperand(i: 0).setReg(AVR::R31R30);
360 }
361}
362
363MachineBasicBlock::iterator AVRFrameLowering::eliminateCallFramePseudoInstr(
364 MachineFunction &MF, MachineBasicBlock &MBB,
365 MachineBasicBlock::iterator MI) const {
366 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
367 const AVRInstrInfo &TII = *STI.getInstrInfo();
368
369 if (hasReservedCallFrame(MF)) {
370 return MBB.erase(I: MI);
371 }
372
373 DebugLoc DL = MI->getDebugLoc();
374 unsigned int Opcode = MI->getOpcode();
375 int Amount = TII.getFrameSize(I: *MI);
376
377 if (Amount == 0) {
378 return MBB.erase(I: MI);
379 }
380
381 assert(getStackAlign() == Align(1) && "Unsupported stack alignment");
382
383 if (Opcode == TII.getCallFrameSetupOpcode()) {
384 // Update the stack pointer.
385 // In many cases this can be done far more efficiently by pushing the
386 // relevant values directly to the stack. However, doing that correctly
387 // (in the right order, possibly skipping some empty space for undef
388 // values, etc) is tricky and thus left to be optimized in the future.
389 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: TII.get(Opcode: AVR::SPREAD), DestReg: AVR::R31R30).addReg(RegNo: AVR::SP);
390
391 MachineInstr *New =
392 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: TII.get(Opcode: AVR::SUBIWRdK), DestReg: AVR::R31R30)
393 .addReg(RegNo: AVR::R31R30, Flags: RegState::Kill)
394 .addImm(Val: Amount);
395 New->getOperand(i: 3).setIsDead();
396
397 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: TII.get(Opcode: AVR::SPWRITE), DestReg: AVR::SP).addReg(RegNo: AVR::R31R30);
398
399 // Make sure the remaining stack stores are converted to real store
400 // instructions.
401 fixStackStores(MBB, StartMI: MI, TII);
402 } else {
403 assert(Opcode == TII.getCallFrameDestroyOpcode());
404
405 // Note that small stack changes could be implemented more efficiently
406 // with a few pop instructions instead of the 8-9 instructions now
407 // required.
408
409 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: TII.get(Opcode: AVR::SPREAD), DestReg: AVR::R31R30).addReg(RegNo: AVR::SP);
410
411 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: TII.get(Opcode: AVR::ADIWRdKP), DestReg: AVR::R31R30)
412 .addReg(RegNo: AVR::R31R30, Flags: RegState::Kill)
413 .addImm(Val: Amount)
414 .setOperandDead(3); // implicit-def $sreg
415
416 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: TII.get(Opcode: AVR::SPWRITE), DestReg: AVR::SP)
417 .addReg(RegNo: AVR::R31R30, Flags: RegState::Kill);
418 }
419
420 return MBB.erase(I: MI);
421}
422
423void AVRFrameLowering::determineCalleeSaves(MachineFunction &MF,
424 BitVector &SavedRegs,
425 RegScavenger *RS) const {
426 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
427
428 // If we have a frame pointer, the Y register needs to be saved as well.
429 if (hasFP(MF)) {
430 SavedRegs.set(AVR::R29);
431 SavedRegs.set(AVR::R28);
432 }
433}
434
435/// The frame analyzer pass.
436///
437/// Scans the function for allocas and used arguments
438/// that are passed through the stack.
439struct AVRFrameAnalyzer : public MachineFunctionPass {
440 static char ID;
441 AVRFrameAnalyzer() : MachineFunctionPass(ID) {}
442
443 bool runOnMachineFunction(MachineFunction &MF) override {
444 const MachineFrameInfo &MFI = MF.getFrameInfo();
445 AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
446
447 // If there are no fixed frame indexes during this stage it means there
448 // are allocas present in the function.
449 if (MFI.getNumObjects() != MFI.getNumFixedObjects()) {
450 // Check for the type of allocas present in the function. We only care
451 // about fixed size allocas so do not give false positives if only
452 // variable sized allocas are present.
453 for (unsigned i = 0, e = MFI.getObjectIndexEnd(); i != e; ++i) {
454 if (!MFI.isVariableSizedObjectIndex(ObjectIdx: i) && !MFI.isDeadObjectIndex(ObjectIdx: i)) {
455 AFI->setHasAllocas(true);
456 break;
457 }
458 }
459 }
460
461 // If there are fixed frame indexes present, scan the function to see if
462 // they are really being used.
463 if (MFI.getNumFixedObjects() == 0) {
464 return false;
465 }
466
467 // Ok fixed frame indexes present, now scan the function to see if they
468 // are really being used, otherwise we can ignore them.
469 for (const MachineBasicBlock &BB : MF) {
470 for (const MachineInstr &MI : BB) {
471 int Opcode = MI.getOpcode();
472
473 if ((Opcode != AVR::LDDRdPtrQ) && (Opcode != AVR::LDDWRdPtrQ) &&
474 (Opcode != AVR::STDPtrQRr) && (Opcode != AVR::STDWPtrQRr) &&
475 (Opcode != AVR::FRMIDX)) {
476 continue;
477 }
478
479 for (const MachineOperand &MO : MI.operands()) {
480 if (!MO.isFI()) {
481 continue;
482 }
483
484 if (MFI.isFixedObjectIndex(ObjectIdx: MO.getIndex())) {
485 AFI->setHasStackArgs(true);
486 return false;
487 }
488 }
489 }
490 }
491
492 return false;
493 }
494
495 StringRef getPassName() const override { return "AVR Frame Analyzer"; }
496};
497
498char AVRFrameAnalyzer::ID = 0;
499
500/// Creates instance of the frame analyzer pass.
501FunctionPass *createAVRFrameAnalyzerPass() { return new AVRFrameAnalyzer(); }
502
503} // end of namespace llvm
504