1//===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that AVR uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AVRISelLowering.h"
15
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/StringSwitch.h"
18#include "llvm/CodeGen/CallingConvLower.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/SelectionDAG.h"
23#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
24#include "llvm/IR/Function.h"
25#include "llvm/Support/ErrorHandling.h"
26
27#include "AVR.h"
28#include "AVRMachineFunctionInfo.h"
29#include "AVRSubtarget.h"
30#include "AVRTargetMachine.h"
31#include "MCTargetDesc/AVRMCTargetDesc.h"
32
33namespace llvm {
34
35AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM,
36 const AVRSubtarget &STI)
37 : TargetLowering(TM, STI), Subtarget(STI) {
38 // Set up the register classes.
39 addRegisterClass(VT: MVT::i8, RC: &AVR::GPR8RegClass);
40 addRegisterClass(VT: MVT::i16, RC: &AVR::DREGSRegClass);
41
42 // Compute derived properties from the register classes.
43 computeRegisterProperties(TRI: Subtarget.getRegisterInfo());
44
45 setBooleanContents(ZeroOrOneBooleanContent);
46 setBooleanVectorContents(ZeroOrOneBooleanContent);
47 setSchedulingPreference(Sched::RegPressure);
48 setStackPointerRegisterToSaveRestore(AVR::SP);
49 setSupportsUnalignedAtomics(true);
50
51 setOperationAction(Op: ISD::GlobalAddress, VT: MVT::i16, Action: Custom);
52 setOperationAction(Op: ISD::BlockAddress, VT: MVT::i16, Action: Custom);
53
54 setOperationAction(Op: ISD::STACKSAVE, VT: MVT::Other, Action: Expand);
55 setOperationAction(Op: ISD::STACKRESTORE, VT: MVT::Other, Action: Expand);
56 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: MVT::i8, Action: Expand);
57 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: MVT::i16, Action: Expand);
58
59 setOperationAction(Op: ISD::INLINEASM, VT: MVT::Other, Action: Custom);
60
61 for (MVT VT : MVT::integer_valuetypes()) {
62 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
63 setLoadExtAction(ExtType: N, ValVT: VT, MemVT: MVT::i1, Action: Promote);
64 setLoadExtAction(ExtType: N, ValVT: VT, MemVT: MVT::i8, Action: Expand);
65 }
66 }
67
68 setTruncStoreAction(ValVT: MVT::i16, MemVT: MVT::i8, Action: Expand);
69
70 for (MVT VT : MVT::integer_valuetypes()) {
71 setOperationAction(Op: ISD::ADDC, VT, Action: Legal);
72 setOperationAction(Op: ISD::SUBC, VT, Action: Legal);
73 setOperationAction(Op: ISD::ADDE, VT, Action: Legal);
74 setOperationAction(Op: ISD::SUBE, VT, Action: Legal);
75 }
76
77 // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types
78 // revert into a sub since we don't have an add with immediate instruction.
79 setOperationAction(Op: ISD::ADD, VT: MVT::i32, Action: Custom);
80 setOperationAction(Op: ISD::ADD, VT: MVT::i64, Action: Custom);
81
82 // our shift instructions are only able to shift 1 bit at a time, so handle
83 // this in a custom way.
84 setOperationAction(Op: ISD::SRA, VT: MVT::i8, Action: Custom);
85 setOperationAction(Op: ISD::SHL, VT: MVT::i8, Action: Custom);
86 setOperationAction(Op: ISD::SRL, VT: MVT::i8, Action: Custom);
87 setOperationAction(Op: ISD::SRA, VT: MVT::i16, Action: Custom);
88 setOperationAction(Op: ISD::SHL, VT: MVT::i16, Action: Custom);
89 setOperationAction(Op: ISD::SRL, VT: MVT::i16, Action: Custom);
90 setOperationAction(Op: ISD::SRA, VT: MVT::i32, Action: Custom);
91 setOperationAction(Op: ISD::SHL, VT: MVT::i32, Action: Custom);
92 setOperationAction(Op: ISD::SRL, VT: MVT::i32, Action: Custom);
93 setOperationAction(Op: ISD::SHL_PARTS, VT: MVT::i16, Action: Expand);
94 setOperationAction(Op: ISD::SRA_PARTS, VT: MVT::i16, Action: Expand);
95 setOperationAction(Op: ISD::SRL_PARTS, VT: MVT::i16, Action: Expand);
96
97 setOperationAction(Op: ISD::ROTL, VT: MVT::i8, Action: Custom);
98 setOperationAction(Op: ISD::ROTL, VT: MVT::i16, Action: Expand);
99 setOperationAction(Op: ISD::ROTR, VT: MVT::i8, Action: Custom);
100 setOperationAction(Op: ISD::ROTR, VT: MVT::i16, Action: Expand);
101
102 setOperationAction(Op: ISD::BR_CC, VT: MVT::i8, Action: Custom);
103 setOperationAction(Op: ISD::BR_CC, VT: MVT::i16, Action: Custom);
104 setOperationAction(Op: ISD::BR_CC, VT: MVT::i32, Action: Custom);
105 setOperationAction(Op: ISD::BR_CC, VT: MVT::i64, Action: Custom);
106 setOperationAction(Op: ISD::BRCOND, VT: MVT::Other, Action: Expand);
107
108 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i8, Action: Custom);
109 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i16, Action: Custom);
110 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i32, Action: Expand);
111 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i64, Action: Expand);
112 setOperationAction(Op: ISD::SETCC, VT: MVT::i8, Action: Custom);
113 setOperationAction(Op: ISD::SETCC, VT: MVT::i16, Action: Custom);
114 setOperationAction(Op: ISD::SETCC, VT: MVT::i32, Action: Custom);
115 setOperationAction(Op: ISD::SETCC, VT: MVT::i64, Action: Custom);
116 setOperationAction(Op: ISD::SELECT, VT: MVT::i8, Action: Expand);
117 setOperationAction(Op: ISD::SELECT, VT: MVT::i16, Action: Expand);
118
119 setOperationAction(Op: ISD::BSWAP, VT: MVT::i16, Action: Expand);
120
121 // Add support for postincrement and predecrement load/stores.
122 setIndexedLoadAction(IdxModes: ISD::POST_INC, VT: MVT::i8, Action: Legal);
123 setIndexedLoadAction(IdxModes: ISD::POST_INC, VT: MVT::i16, Action: Legal);
124 setIndexedLoadAction(IdxModes: ISD::PRE_DEC, VT: MVT::i8, Action: Legal);
125 setIndexedLoadAction(IdxModes: ISD::PRE_DEC, VT: MVT::i16, Action: Legal);
126 setIndexedStoreAction(IdxModes: ISD::POST_INC, VT: MVT::i8, Action: Legal);
127 setIndexedStoreAction(IdxModes: ISD::POST_INC, VT: MVT::i16, Action: Legal);
128 setIndexedStoreAction(IdxModes: ISD::PRE_DEC, VT: MVT::i8, Action: Legal);
129 setIndexedStoreAction(IdxModes: ISD::PRE_DEC, VT: MVT::i16, Action: Legal);
130
131 setOperationAction(Op: ISD::BR_JT, VT: MVT::Other, Action: Expand);
132
133 setOperationAction(Op: ISD::VASTART, VT: MVT::Other, Action: Custom);
134 setOperationAction(Op: ISD::VAEND, VT: MVT::Other, Action: Expand);
135 setOperationAction(Op: ISD::VAARG, VT: MVT::Other, Action: Expand);
136 setOperationAction(Op: ISD::VACOPY, VT: MVT::Other, Action: Expand);
137
138 // Atomic operations which must be lowered to rtlib calls
139 for (MVT VT : MVT::integer_valuetypes()) {
140 setOperationAction(Op: ISD::ATOMIC_SWAP, VT, Action: Expand);
141 setOperationAction(Op: ISD::ATOMIC_CMP_SWAP, VT, Action: Expand);
142 setOperationAction(Op: ISD::ATOMIC_LOAD_NAND, VT, Action: Expand);
143 setOperationAction(Op: ISD::ATOMIC_LOAD_MAX, VT, Action: Expand);
144 setOperationAction(Op: ISD::ATOMIC_LOAD_MIN, VT, Action: Expand);
145 setOperationAction(Op: ISD::ATOMIC_LOAD_UMAX, VT, Action: Expand);
146 setOperationAction(Op: ISD::ATOMIC_LOAD_UMIN, VT, Action: Expand);
147 }
148
149 // Division/remainder
150 setOperationAction(Op: ISD::UDIV, VT: MVT::i8, Action: Expand);
151 setOperationAction(Op: ISD::UDIV, VT: MVT::i16, Action: Expand);
152 setOperationAction(Op: ISD::UREM, VT: MVT::i8, Action: Expand);
153 setOperationAction(Op: ISD::UREM, VT: MVT::i16, Action: Expand);
154 setOperationAction(Op: ISD::SDIV, VT: MVT::i8, Action: Expand);
155 setOperationAction(Op: ISD::SDIV, VT: MVT::i16, Action: Expand);
156 setOperationAction(Op: ISD::SREM, VT: MVT::i8, Action: Expand);
157 setOperationAction(Op: ISD::SREM, VT: MVT::i16, Action: Expand);
158
159 // Make division and modulus custom
160 setOperationAction(Op: ISD::UDIVREM, VT: MVT::i8, Action: Custom);
161 setOperationAction(Op: ISD::UDIVREM, VT: MVT::i16, Action: Custom);
162 setOperationAction(Op: ISD::UDIVREM, VT: MVT::i32, Action: Custom);
163 setOperationAction(Op: ISD::SDIVREM, VT: MVT::i8, Action: Custom);
164 setOperationAction(Op: ISD::SDIVREM, VT: MVT::i16, Action: Custom);
165 setOperationAction(Op: ISD::SDIVREM, VT: MVT::i32, Action: Custom);
166
167 // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
168 setOperationAction(Op: ISD::MUL, VT: MVT::i8, Action: Expand);
169 setOperationAction(Op: ISD::MUL, VT: MVT::i16, Action: Expand);
170
171 // Expand 16 bit multiplications.
172 setOperationAction(Op: ISD::SMUL_LOHI, VT: MVT::i16, Action: Expand);
173 setOperationAction(Op: ISD::UMUL_LOHI, VT: MVT::i16, Action: Expand);
174
175 // Expand multiplications to libcalls when there is
176 // no hardware MUL.
177 if (!Subtarget.supportsMultiplication()) {
178 setOperationAction(Op: ISD::SMUL_LOHI, VT: MVT::i8, Action: Expand);
179 setOperationAction(Op: ISD::UMUL_LOHI, VT: MVT::i8, Action: Expand);
180 }
181
182 for (MVT VT : MVT::integer_valuetypes()) {
183 setOperationAction(Op: ISD::MULHS, VT, Action: Expand);
184 setOperationAction(Op: ISD::MULHU, VT, Action: Expand);
185 }
186
187 for (MVT VT : MVT::integer_valuetypes()) {
188 setOperationAction(Op: ISD::CTPOP, VT, Action: Expand);
189 setOperationAction(Op: ISD::CTLZ, VT, Action: Expand);
190 setOperationAction(Op: ISD::CTTZ, VT, Action: Expand);
191 }
192
193 for (MVT VT : MVT::integer_valuetypes()) {
194 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT, Action: Expand);
195 // TODO: The generated code is pretty poor. Investigate using the
196 // same "shift and subtract with carry" trick that we do for
197 // extending 8-bit to 16-bit. This may require infrastructure
198 // improvements in how we treat 16-bit "registers" to be feasible.
199 }
200
201 setMinFunctionAlignment(Align(2));
202 setMinimumJumpTableEntries(UINT_MAX);
203}
204
205EVT AVRTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
206 EVT VT) const {
207 assert(!VT.isVector() && "No AVR SetCC type for vectors!");
208 return MVT::i8;
209}
210
211SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
212 unsigned Opc8;
213 const SDNode *N = Op.getNode();
214 EVT VT = Op.getValueType();
215 SDLoc dl(N);
216 assert(llvm::has_single_bit<uint32_t>(VT.getSizeInBits()) &&
217 "Expected power-of-2 shift amount");
218
219 if (VT.getSizeInBits() == 32) {
220 if (!isa<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
221 // 32-bit shifts are converted to a loop in IR.
222 // This should be unreachable.
223 report_fatal_error(reason: "Expected a constant shift amount!");
224 }
225 SDVTList ResTys = DAG.getVTList(VT1: MVT::i16, VT2: MVT::i16);
226 SDValue SrcLo =
227 DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL: dl, VT: MVT::i16, N1: Op.getOperand(i: 0),
228 N2: DAG.getConstant(Val: 0, DL: dl, VT: MVT::i16));
229 SDValue SrcHi =
230 DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL: dl, VT: MVT::i16, N1: Op.getOperand(i: 0),
231 N2: DAG.getConstant(Val: 1, DL: dl, VT: MVT::i16));
232 uint64_t ShiftAmount = N->getConstantOperandVal(Num: 1);
233 if (ShiftAmount == 16) {
234 // Special case these two operations because they appear to be used by the
235 // generic codegen parts to lower 32-bit numbers.
236 // TODO: perhaps we can lower shift amounts bigger than 16 to a 16-bit
237 // shift of a part of the 32-bit value?
238 switch (Op.getOpcode()) {
239 case ISD::SHL: {
240 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT: MVT::i16);
241 return DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i32, N1: Zero, N2: SrcLo);
242 }
243 case ISD::SRL: {
244 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT: MVT::i16);
245 return DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i32, N1: SrcHi, N2: Zero);
246 }
247 }
248 }
249 SDValue Cnt = DAG.getTargetConstant(Val: ShiftAmount, DL: dl, VT: MVT::i8);
250 unsigned Opc;
251 switch (Op.getOpcode()) {
252 default:
253 llvm_unreachable("Invalid 32-bit shift opcode!");
254 case ISD::SHL:
255 Opc = AVRISD::LSLW;
256 break;
257 case ISD::SRL:
258 Opc = AVRISD::LSRW;
259 break;
260 case ISD::SRA:
261 Opc = AVRISD::ASRW;
262 break;
263 }
264 SDValue Result = DAG.getNode(Opcode: Opc, DL: dl, VTList: ResTys, N1: SrcLo, N2: SrcHi, N3: Cnt);
265 return DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i32, N1: Result.getValue(R: 0),
266 N2: Result.getValue(R: 1));
267 }
268
269 // Expand non-constant shifts to loops.
270 if (!isa<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
271 switch (Op.getOpcode()) {
272 default:
273 llvm_unreachable("Invalid shift opcode!");
274 case ISD::SHL:
275 return DAG.getNode(Opcode: AVRISD::LSLLOOP, DL: dl, VT, N1: N->getOperand(Num: 0),
276 N2: N->getOperand(Num: 1));
277 case ISD::SRL:
278 return DAG.getNode(Opcode: AVRISD::LSRLOOP, DL: dl, VT, N1: N->getOperand(Num: 0),
279 N2: N->getOperand(Num: 1));
280 case ISD::ROTL: {
281 SDValue Amt = N->getOperand(Num: 1);
282 EVT AmtVT = Amt.getValueType();
283 Amt = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: AmtVT, N1: Amt,
284 N2: DAG.getConstant(Val: VT.getSizeInBits() - 1, DL: dl, VT: AmtVT));
285 return DAG.getNode(Opcode: AVRISD::ROLLOOP, DL: dl, VT, N1: N->getOperand(Num: 0), N2: Amt);
286 }
287 case ISD::ROTR: {
288 SDValue Amt = N->getOperand(Num: 1);
289 EVT AmtVT = Amt.getValueType();
290 Amt = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: AmtVT, N1: Amt,
291 N2: DAG.getConstant(Val: VT.getSizeInBits() - 1, DL: dl, VT: AmtVT));
292 return DAG.getNode(Opcode: AVRISD::RORLOOP, DL: dl, VT, N1: N->getOperand(Num: 0), N2: Amt);
293 }
294 case ISD::SRA:
295 return DAG.getNode(Opcode: AVRISD::ASRLOOP, DL: dl, VT, N1: N->getOperand(Num: 0),
296 N2: N->getOperand(Num: 1));
297 }
298 }
299
300 uint64_t ShiftAmount = N->getConstantOperandVal(Num: 1);
301 SDValue Victim = N->getOperand(Num: 0);
302
303 switch (Op.getOpcode()) {
304 case ISD::SRA:
305 Opc8 = AVRISD::ASR;
306 break;
307 case ISD::ROTL:
308 Opc8 = AVRISD::ROL;
309 ShiftAmount = ShiftAmount % VT.getSizeInBits();
310 break;
311 case ISD::ROTR:
312 Opc8 = AVRISD::ROR;
313 ShiftAmount = ShiftAmount % VT.getSizeInBits();
314 break;
315 case ISD::SRL:
316 Opc8 = AVRISD::LSR;
317 break;
318 case ISD::SHL:
319 Opc8 = AVRISD::LSL;
320 break;
321 default:
322 llvm_unreachable("Invalid shift opcode");
323 }
324
325 // Optimize int8/int16 shifts.
326 if (VT.getSizeInBits() == 8) {
327 if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) {
328 // Optimize LSL when 4 <= ShiftAmount <= 6.
329 Victim = DAG.getNode(Opcode: AVRISD::SWAP, DL: dl, VT, Operand: Victim);
330 Victim =
331 DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: Victim, N2: DAG.getConstant(Val: 0xf0, DL: dl, VT));
332 ShiftAmount -= 4;
333 } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount &&
334 ShiftAmount < 7) {
335 // Optimize LSR when 4 <= ShiftAmount <= 6.
336 Victim = DAG.getNode(Opcode: AVRISD::SWAP, DL: dl, VT, Operand: Victim);
337 Victim =
338 DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: Victim, N2: DAG.getConstant(Val: 0x0f, DL: dl, VT));
339 ShiftAmount -= 4;
340 } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) {
341 // Optimize LSL when ShiftAmount == 7.
342 Victim = DAG.getNode(Opcode: AVRISD::LSLBN, DL: dl, VT, N1: Victim,
343 N2: DAG.getConstant(Val: 7, DL: dl, VT));
344 ShiftAmount = 0;
345 } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) {
346 // Optimize LSR when ShiftAmount == 7.
347 Victim = DAG.getNode(Opcode: AVRISD::LSRBN, DL: dl, VT, N1: Victim,
348 N2: DAG.getConstant(Val: 7, DL: dl, VT));
349 ShiftAmount = 0;
350 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 6) {
351 // Optimize ASR when ShiftAmount == 6.
352 Victim = DAG.getNode(Opcode: AVRISD::ASRBN, DL: dl, VT, N1: Victim,
353 N2: DAG.getConstant(Val: 6, DL: dl, VT));
354 ShiftAmount = 0;
355 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) {
356 // Optimize ASR when ShiftAmount == 7.
357 Victim = DAG.getNode(Opcode: AVRISD::ASRBN, DL: dl, VT, N1: Victim,
358 N2: DAG.getConstant(Val: 7, DL: dl, VT));
359 ShiftAmount = 0;
360 } else if (Op.getOpcode() == ISD::ROTL && ShiftAmount == 3) {
361 // Optimize left rotation 3 bits to swap then right rotation 1 bit.
362 Victim = DAG.getNode(Opcode: AVRISD::SWAP, DL: dl, VT, Operand: Victim);
363 Victim = DAG.getNode(Opcode: AVRISD::ROR, DL: dl, VT, Operand: Victim);
364 ShiftAmount = 0;
365 } else if (Op.getOpcode() == ISD::ROTR && ShiftAmount == 3) {
366 // Optimize right rotation 3 bits to swap then left rotation 1 bit.
367 Victim = DAG.getNode(Opcode: AVRISD::SWAP, DL: dl, VT, Operand: Victim);
368 Victim = DAG.getNode(Opcode: AVRISD::ROL, DL: dl, VT, Operand: Victim);
369 ShiftAmount = 0;
370 } else if (Op.getOpcode() == ISD::ROTL && ShiftAmount == 7) {
371 // Optimize left rotation 7 bits to right rotation 1 bit.
372 Victim = DAG.getNode(Opcode: AVRISD::ROR, DL: dl, VT, Operand: Victim);
373 ShiftAmount = 0;
374 } else if (Op.getOpcode() == ISD::ROTR && ShiftAmount == 7) {
375 // Optimize right rotation 7 bits to left rotation 1 bit.
376 Victim = DAG.getNode(Opcode: AVRISD::ROL, DL: dl, VT, Operand: Victim);
377 ShiftAmount = 0;
378 } else if ((Op.getOpcode() == ISD::ROTR || Op.getOpcode() == ISD::ROTL) &&
379 ShiftAmount >= 4) {
380 // Optimize left/right rotation with the SWAP instruction.
381 Victim = DAG.getNode(Opcode: AVRISD::SWAP, DL: dl, VT, Operand: Victim);
382 ShiftAmount -= 4;
383 }
384 } else if (VT.getSizeInBits() == 16) {
385 if (Op.getOpcode() == ISD::SRA)
386 // Special optimization for int16 arithmetic right shift.
387 switch (ShiftAmount) {
388 case 15:
389 Victim = DAG.getNode(Opcode: AVRISD::ASRWN, DL: dl, VT, N1: Victim,
390 N2: DAG.getConstant(Val: 15, DL: dl, VT));
391 ShiftAmount = 0;
392 break;
393 case 14:
394 Victim = DAG.getNode(Opcode: AVRISD::ASRWN, DL: dl, VT, N1: Victim,
395 N2: DAG.getConstant(Val: 14, DL: dl, VT));
396 ShiftAmount = 0;
397 break;
398 case 7:
399 Victim = DAG.getNode(Opcode: AVRISD::ASRWN, DL: dl, VT, N1: Victim,
400 N2: DAG.getConstant(Val: 7, DL: dl, VT));
401 ShiftAmount = 0;
402 break;
403 default:
404 break;
405 }
406 if (4 <= ShiftAmount && ShiftAmount < 8)
407 switch (Op.getOpcode()) {
408 case ISD::SHL:
409 Victim = DAG.getNode(Opcode: AVRISD::LSLWN, DL: dl, VT, N1: Victim,
410 N2: DAG.getConstant(Val: 4, DL: dl, VT));
411 ShiftAmount -= 4;
412 break;
413 case ISD::SRL:
414 Victim = DAG.getNode(Opcode: AVRISD::LSRWN, DL: dl, VT, N1: Victim,
415 N2: DAG.getConstant(Val: 4, DL: dl, VT));
416 ShiftAmount -= 4;
417 break;
418 default:
419 break;
420 }
421 else if (8 <= ShiftAmount && ShiftAmount < 12)
422 switch (Op.getOpcode()) {
423 case ISD::SHL:
424 Victim = DAG.getNode(Opcode: AVRISD::LSLWN, DL: dl, VT, N1: Victim,
425 N2: DAG.getConstant(Val: 8, DL: dl, VT));
426 ShiftAmount -= 8;
427 // Only operate on the higher byte for remaining shift bits.
428 Opc8 = AVRISD::LSLHI;
429 break;
430 case ISD::SRL:
431 Victim = DAG.getNode(Opcode: AVRISD::LSRWN, DL: dl, VT, N1: Victim,
432 N2: DAG.getConstant(Val: 8, DL: dl, VT));
433 ShiftAmount -= 8;
434 // Only operate on the lower byte for remaining shift bits.
435 Opc8 = AVRISD::LSRLO;
436 break;
437 case ISD::SRA:
438 Victim = DAG.getNode(Opcode: AVRISD::ASRWN, DL: dl, VT, N1: Victim,
439 N2: DAG.getConstant(Val: 8, DL: dl, VT));
440 ShiftAmount -= 8;
441 // Only operate on the lower byte for remaining shift bits.
442 Opc8 = AVRISD::ASRLO;
443 break;
444 default:
445 break;
446 }
447 else if (12 <= ShiftAmount)
448 switch (Op.getOpcode()) {
449 case ISD::SHL:
450 Victim = DAG.getNode(Opcode: AVRISD::LSLWN, DL: dl, VT, N1: Victim,
451 N2: DAG.getConstant(Val: 12, DL: dl, VT));
452 ShiftAmount -= 12;
453 // Only operate on the higher byte for remaining shift bits.
454 Opc8 = AVRISD::LSLHI;
455 break;
456 case ISD::SRL:
457 Victim = DAG.getNode(Opcode: AVRISD::LSRWN, DL: dl, VT, N1: Victim,
458 N2: DAG.getConstant(Val: 12, DL: dl, VT));
459 ShiftAmount -= 12;
460 // Only operate on the lower byte for remaining shift bits.
461 Opc8 = AVRISD::LSRLO;
462 break;
463 case ISD::SRA:
464 Victim = DAG.getNode(Opcode: AVRISD::ASRWN, DL: dl, VT, N1: Victim,
465 N2: DAG.getConstant(Val: 8, DL: dl, VT));
466 ShiftAmount -= 8;
467 // Only operate on the lower byte for remaining shift bits.
468 Opc8 = AVRISD::ASRLO;
469 break;
470 default:
471 break;
472 }
473 }
474
475 while (ShiftAmount--) {
476 Victim = DAG.getNode(Opcode: Opc8, DL: dl, VT, Operand: Victim);
477 }
478
479 return Victim;
480}
481
482SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
483 unsigned Opcode = Op->getOpcode();
484 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
485 "Invalid opcode for Div/Rem lowering");
486 bool IsSigned = (Opcode == ISD::SDIVREM);
487 EVT VT = Op->getValueType(ResNo: 0);
488 Type *Ty = VT.getTypeForEVT(Context&: *DAG.getContext());
489
490 RTLIB::Libcall LC;
491 switch (VT.getSimpleVT().SimpleTy) {
492 default:
493 llvm_unreachable("Unexpected request for libcall!");
494 case MVT::i8:
495 LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
496 break;
497 case MVT::i16:
498 LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
499 break;
500 case MVT::i32:
501 LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
502 break;
503 }
504
505 SDValue InChain = DAG.getEntryNode();
506
507 TargetLowering::ArgListTy Args;
508 for (SDValue const &Value : Op->op_values()) {
509 TargetLowering::ArgListEntry Entry(
510 Value, Value.getValueType().getTypeForEVT(Context&: *DAG.getContext()));
511 Entry.IsSExt = IsSigned;
512 Entry.IsZExt = !IsSigned;
513 Args.push_back(x: Entry);
514 }
515
516 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
517 if (LCImpl == RTLIB::Unsupported)
518 return SDValue();
519
520 SDValue Callee =
521 DAG.getExternalSymbol(LCImpl, VT: getPointerTy(DL: DAG.getDataLayout()));
522
523 Type *RetTy = (Type *)StructType::get(elt1: Ty, elts: Ty);
524
525 SDLoc dl(Op);
526 TargetLowering::CallLoweringInfo CLI(DAG);
527 CLI.setDebugLoc(dl)
528 .setChain(InChain)
529 .setLibCallee(CC: DAG.getLibcalls().getLibcallImplCallingConv(Call: LCImpl), ResultType: RetTy,
530 Target: Callee, ArgsList: std::move(Args))
531 .setInRegister()
532 .setSExtResult(IsSigned)
533 .setZExtResult(!IsSigned);
534
535 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
536 return CallInfo.first;
537}
538
539SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op,
540 SelectionDAG &DAG) const {
541 auto DL = DAG.getDataLayout();
542
543 const GlobalValue *GV = cast<GlobalAddressSDNode>(Val&: Op)->getGlobal();
544 int64_t Offset = cast<GlobalAddressSDNode>(Val&: Op)->getOffset();
545
546 // Create the TargetGlobalAddress node, folding in the constant offset.
547 SDValue Result =
548 DAG.getTargetGlobalAddress(GV, DL: SDLoc(Op), VT: getPointerTy(DL), offset: Offset);
549 return DAG.getNode(Opcode: AVRISD::WRAPPER, DL: SDLoc(Op), VT: getPointerTy(DL), Operand: Result);
550}
551
552SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op,
553 SelectionDAG &DAG) const {
554 auto DL = DAG.getDataLayout();
555 const BlockAddress *BA = cast<BlockAddressSDNode>(Val&: Op)->getBlockAddress();
556
557 SDValue Result = DAG.getTargetBlockAddress(BA, VT: getPointerTy(DL));
558
559 return DAG.getNode(Opcode: AVRISD::WRAPPER, DL: SDLoc(Op), VT: getPointerTy(DL), Operand: Result);
560}
561
562/// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
563static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC) {
564 switch (CC) {
565 default:
566 llvm_unreachable("Unknown condition code!");
567 case ISD::SETEQ:
568 return AVRCC::COND_EQ;
569 case ISD::SETNE:
570 return AVRCC::COND_NE;
571 case ISD::SETGE:
572 return AVRCC::COND_GE;
573 case ISD::SETLT:
574 return AVRCC::COND_LT;
575 case ISD::SETUGE:
576 return AVRCC::COND_SH;
577 case ISD::SETULT:
578 return AVRCC::COND_LO;
579 }
580}
581
582/// Returns appropriate CP/CPI/CPC nodes code for the given 8/16-bit operands.
583SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS,
584 SelectionDAG &DAG, SDLoc DL) const {
585 assert((LHS.getSimpleValueType() == RHS.getSimpleValueType()) &&
586 "LHS and RHS have different types");
587 assert(((LHS.getSimpleValueType() == MVT::i16) ||
588 (LHS.getSimpleValueType() == MVT::i8)) &&
589 "invalid comparison type");
590
591 SDValue Cmp;
592
593 if (LHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(Val: RHS)) {
594 uint64_t Imm = RHS->getAsZExtVal();
595 // Generate a CPI/CPC pair if RHS is a 16-bit constant. Use the zero
596 // register for the constant RHS if its lower or higher byte is zero.
597 SDValue LHSlo = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: LHS,
598 N2: DAG.getIntPtrConstant(Val: 0, DL));
599 SDValue LHShi = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: LHS,
600 N2: DAG.getIntPtrConstant(Val: 1, DL));
601 SDValue RHSlo = (Imm & 0xff) == 0
602 ? DAG.getRegister(Reg: Subtarget.getZeroRegister(), VT: MVT::i8)
603 : DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: RHS,
604 N2: DAG.getIntPtrConstant(Val: 0, DL));
605 SDValue RHShi = (Imm & 0xff00) == 0
606 ? DAG.getRegister(Reg: Subtarget.getZeroRegister(), VT: MVT::i8)
607 : DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: RHS,
608 N2: DAG.getIntPtrConstant(Val: 1, DL));
609 Cmp = DAG.getNode(Opcode: AVRISD::CMP, DL, VT: MVT::Glue, N1: LHSlo, N2: RHSlo);
610 Cmp = DAG.getNode(Opcode: AVRISD::CMPC, DL, VT: MVT::Glue, N1: LHShi, N2: RHShi, N3: Cmp);
611 } else if (RHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(Val: LHS)) {
612 // Generate a CPI/CPC pair if LHS is a 16-bit constant. Use the zero
613 // register for the constant LHS if its lower or higher byte is zero.
614 uint64_t Imm = LHS->getAsZExtVal();
615 SDValue LHSlo = (Imm & 0xff) == 0
616 ? DAG.getRegister(Reg: Subtarget.getZeroRegister(), VT: MVT::i8)
617 : DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: LHS,
618 N2: DAG.getIntPtrConstant(Val: 0, DL));
619 SDValue LHShi = (Imm & 0xff00) == 0
620 ? DAG.getRegister(Reg: Subtarget.getZeroRegister(), VT: MVT::i8)
621 : DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: LHS,
622 N2: DAG.getIntPtrConstant(Val: 1, DL));
623 SDValue RHSlo = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: RHS,
624 N2: DAG.getIntPtrConstant(Val: 0, DL));
625 SDValue RHShi = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: RHS,
626 N2: DAG.getIntPtrConstant(Val: 1, DL));
627 Cmp = DAG.getNode(Opcode: AVRISD::CMP, DL, VT: MVT::Glue, N1: LHSlo, N2: RHSlo);
628 Cmp = DAG.getNode(Opcode: AVRISD::CMPC, DL, VT: MVT::Glue, N1: LHShi, N2: RHShi, N3: Cmp);
629 } else {
630 // Generate ordinary 16-bit comparison.
631 Cmp = DAG.getNode(Opcode: AVRISD::CMP, DL, VT: MVT::Glue, N1: LHS, N2: RHS);
632 }
633
634 return Cmp;
635}
636
637/// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for
638/// the given operands.
639SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
640 SDValue &AVRcc, SelectionDAG &DAG,
641 SDLoc DL) const {
642 SDValue Cmp;
643 EVT VT = LHS.getValueType();
644 bool UseTest = false;
645
646 switch (CC) {
647 default:
648 break;
649 case ISD::SETLE: {
650 // Swap operands and reverse the branching condition.
651 std::swap(a&: LHS, b&: RHS);
652 CC = ISD::SETGE;
653 break;
654 }
655 case ISD::SETGT: {
656 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: RHS)) {
657 switch (C->getSExtValue()) {
658 case -1: {
659 // When doing lhs > -1 use a tst instruction on the top part of lhs
660 // and use brpl instead of using a chain of cp/cpc.
661 UseTest = true;
662 AVRcc = DAG.getConstant(Val: AVRCC::COND_PL, DL, VT: MVT::i8);
663 break;
664 }
665 case 0: {
666 // Turn lhs > 0 into 0 < lhs since 0 can be materialized with
667 // __zero_reg__ in lhs.
668 RHS = LHS;
669 LHS = DAG.getConstant(Val: 0, DL, VT);
670 CC = ISD::SETLT;
671 break;
672 }
673 default: {
674 if (C->getConstantIntValue()->isMaxValue(IsSigned: true)) {
675 // Applying this optimization requires calculating rhs+1, which we
676 // can't do if that overflows. Swap operands and reverse the
677 // branching condition instead.
678 std::swap(a&: LHS, b&: RHS);
679 CC = ISD::SETLT;
680 break;
681 }
682
683 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows
684 // us to fold the constant into the cmp instruction.
685 RHS = DAG.getSignedConstant(Val: C->getSExtValue() + 1, DL, VT);
686 CC = ISD::SETGE;
687 break;
688 }
689 }
690 break;
691 }
692 // Swap operands and reverse the branching condition.
693 std::swap(a&: LHS, b&: RHS);
694 CC = ISD::SETLT;
695 break;
696 }
697 case ISD::SETLT: {
698 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: RHS)) {
699 switch (C->getSExtValue()) {
700 case 1: {
701 // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with
702 // __zero_reg__ in lhs.
703 RHS = LHS;
704 LHS = DAG.getConstant(Val: 0, DL, VT);
705 CC = ISD::SETGE;
706 break;
707 }
708 case 0: {
709 // When doing lhs < 0 use a tst instruction on the top part of lhs
710 // and use brmi instead of using a chain of cp/cpc.
711 UseTest = true;
712 AVRcc = DAG.getConstant(Val: AVRCC::COND_MI, DL, VT: MVT::i8);
713 break;
714 }
715 }
716 }
717 break;
718 }
719 case ISD::SETULE: {
720 // Swap operands and reverse the branching condition.
721 std::swap(a&: LHS, b&: RHS);
722 CC = ISD::SETUGE;
723 break;
724 }
725 case ISD::SETUGT: {
726 // Turn `lhs > rhs` with constant rhs into `lhs >= rhs + 1`, because this
727 // allows us to fold the constant into the cmp instruction.
728 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: RHS)) {
729 if (C->getConstantIntValue()->isMaxValue(IsSigned: false)) {
730 // Applying this optimization requires calculating rhs+1, which we can't
731 // do if that overflows; it can happen during i128->i64 lowering.
732 } else {
733 RHS = DAG.getConstant(Val: C->getZExtValue() + 1, DL, VT);
734 CC = ISD::SETUGE;
735 break;
736 }
737 }
738 // Swap operands and reverse the branching condition.
739 std::swap(a&: LHS, b&: RHS);
740 CC = ISD::SETULT;
741 break;
742 }
743 }
744
745 // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of
746 // using the default and/or/xor expansion code which is much longer.
747 if (VT == MVT::i32) {
748 SDValue LHSlo = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: LHS,
749 N2: DAG.getIntPtrConstant(Val: 0, DL));
750 SDValue LHShi = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: LHS,
751 N2: DAG.getIntPtrConstant(Val: 1, DL));
752 SDValue RHSlo = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: RHS,
753 N2: DAG.getIntPtrConstant(Val: 0, DL));
754 SDValue RHShi = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: RHS,
755 N2: DAG.getIntPtrConstant(Val: 1, DL));
756
757 if (UseTest) {
758 // When using tst we only care about the highest part.
759 SDValue Top = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: LHShi,
760 N2: DAG.getIntPtrConstant(Val: 1, DL));
761 Cmp = DAG.getNode(Opcode: AVRISD::TST, DL, VT: MVT::Glue, Operand: Top);
762 } else {
763 Cmp = getAVRCmp(LHS: LHSlo, RHS: RHSlo, DAG, DL);
764 Cmp = DAG.getNode(Opcode: AVRISD::CMPC, DL, VT: MVT::Glue, N1: LHShi, N2: RHShi, N3: Cmp);
765 }
766 } else if (VT == MVT::i64) {
767 SDValue LHS_0 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i32, N1: LHS,
768 N2: DAG.getIntPtrConstant(Val: 0, DL));
769 SDValue LHS_1 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i32, N1: LHS,
770 N2: DAG.getIntPtrConstant(Val: 1, DL));
771
772 SDValue LHS0 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: LHS_0,
773 N2: DAG.getIntPtrConstant(Val: 0, DL));
774 SDValue LHS1 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: LHS_0,
775 N2: DAG.getIntPtrConstant(Val: 1, DL));
776 SDValue LHS2 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: LHS_1,
777 N2: DAG.getIntPtrConstant(Val: 0, DL));
778 SDValue LHS3 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: LHS_1,
779 N2: DAG.getIntPtrConstant(Val: 1, DL));
780
781 SDValue RHS_0 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i32, N1: RHS,
782 N2: DAG.getIntPtrConstant(Val: 0, DL));
783 SDValue RHS_1 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i32, N1: RHS,
784 N2: DAG.getIntPtrConstant(Val: 1, DL));
785
786 SDValue RHS0 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: RHS_0,
787 N2: DAG.getIntPtrConstant(Val: 0, DL));
788 SDValue RHS1 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: RHS_0,
789 N2: DAG.getIntPtrConstant(Val: 1, DL));
790 SDValue RHS2 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: RHS_1,
791 N2: DAG.getIntPtrConstant(Val: 0, DL));
792 SDValue RHS3 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: RHS_1,
793 N2: DAG.getIntPtrConstant(Val: 1, DL));
794
795 if (UseTest) {
796 // When using tst we only care about the highest part.
797 SDValue Top = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: LHS3,
798 N2: DAG.getIntPtrConstant(Val: 1, DL));
799 Cmp = DAG.getNode(Opcode: AVRISD::TST, DL, VT: MVT::Glue, Operand: Top);
800 } else {
801 Cmp = getAVRCmp(LHS: LHS0, RHS: RHS0, DAG, DL);
802 Cmp = DAG.getNode(Opcode: AVRISD::CMPC, DL, VT: MVT::Glue, N1: LHS1, N2: RHS1, N3: Cmp);
803 Cmp = DAG.getNode(Opcode: AVRISD::CMPC, DL, VT: MVT::Glue, N1: LHS2, N2: RHS2, N3: Cmp);
804 Cmp = DAG.getNode(Opcode: AVRISD::CMPC, DL, VT: MVT::Glue, N1: LHS3, N2: RHS3, N3: Cmp);
805 }
806 } else if (VT == MVT::i8 || VT == MVT::i16) {
807 if (UseTest) {
808 // When using tst we only care about the highest part.
809 Cmp = DAG.getNode(Opcode: AVRISD::TST, DL, VT: MVT::Glue,
810 Operand: (VT == MVT::i8)
811 ? LHS
812 : DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8,
813 N1: LHS, N2: DAG.getIntPtrConstant(Val: 1, DL)));
814 } else {
815 Cmp = getAVRCmp(LHS, RHS, DAG, DL);
816 }
817 } else {
818 llvm_unreachable("Invalid comparison size");
819 }
820
821 // When using a test instruction AVRcc is already set.
822 if (!UseTest) {
823 AVRcc = DAG.getConstant(Val: intCCToAVRCC(CC), DL, VT: MVT::i8);
824 }
825
826 return Cmp;
827}
828
829SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
830 SDValue Chain = Op.getOperand(i: 0);
831 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 1))->get();
832 SDValue LHS = Op.getOperand(i: 2);
833 SDValue RHS = Op.getOperand(i: 3);
834 SDValue Dest = Op.getOperand(i: 4);
835 SDLoc dl(Op);
836
837 SDValue TargetCC;
838 SDValue Cmp = getAVRCmp(LHS, RHS, CC, AVRcc&: TargetCC, DAG, DL: dl);
839
840 return DAG.getNode(Opcode: AVRISD::BRCOND, DL: dl, VT: MVT::Other, N1: Chain, N2: Dest, N3: TargetCC,
841 N4: Cmp);
842}
843
844SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
845 SDValue LHS = Op.getOperand(i: 0);
846 SDValue RHS = Op.getOperand(i: 1);
847 SDValue TrueV = Op.getOperand(i: 2);
848 SDValue FalseV = Op.getOperand(i: 3);
849 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 4))->get();
850 SDLoc dl(Op);
851
852 SDValue TargetCC;
853 SDValue Cmp = getAVRCmp(LHS, RHS, CC, AVRcc&: TargetCC, DAG, DL: dl);
854
855 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
856
857 return DAG.getNode(Opcode: AVRISD::SELECT_CC, DL: dl, VT: Op.getValueType(), Ops);
858}
859
860SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
861 SDValue LHS = Op.getOperand(i: 0);
862 SDValue RHS = Op.getOperand(i: 1);
863 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 2))->get();
864 SDLoc DL(Op);
865
866 SDValue TargetCC;
867 SDValue Cmp = getAVRCmp(LHS, RHS, CC, AVRcc&: TargetCC, DAG, DL);
868
869 SDValue TrueV = DAG.getConstant(Val: 1, DL, VT: Op.getValueType());
870 SDValue FalseV = DAG.getConstant(Val: 0, DL, VT: Op.getValueType());
871 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
872
873 return DAG.getNode(Opcode: AVRISD::SELECT_CC, DL, VT: Op.getValueType(), Ops);
874}
875
876SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
877 const MachineFunction &MF = DAG.getMachineFunction();
878 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
879 const Value *SV = cast<SrcValueSDNode>(Val: Op.getOperand(i: 2))->getValue();
880 auto DL = DAG.getDataLayout();
881 SDLoc dl(Op);
882
883 // Vastart just stores the address of the VarArgsFrameIndex slot into the
884 // memory location argument.
885 SDValue FI = DAG.getFrameIndex(FI: AFI->getVarArgsFrameIndex(), VT: getPointerTy(DL));
886
887 return DAG.getStore(Chain: Op.getOperand(i: 0), dl, Val: FI, Ptr: Op.getOperand(i: 1),
888 PtrInfo: MachinePointerInfo(SV));
889}
890
891// Modify the existing ISD::INLINEASM node to add the implicit zero register.
892SDValue AVRTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
893 SDValue ZeroReg = DAG.getRegister(Reg: Subtarget.getZeroRegister(), VT: MVT::i8);
894 if (Op.getOperand(i: Op.getNumOperands() - 1) == ZeroReg ||
895 Op.getOperand(i: Op.getNumOperands() - 2) == ZeroReg) {
896 // Zero register has already been added. Don't add it again.
897 // If this isn't handled, we get called over and over again.
898 return Op;
899 }
900
901 // Get a list of operands to the new INLINEASM node. This is mostly a copy,
902 // with some edits.
903 // Add the following operands at the end (but before the glue node, if it's
904 // there):
905 // - The flags of the implicit zero register operand.
906 // - The implicit zero register operand itself.
907 SDLoc dl(Op);
908 SmallVector<SDValue, 8> Ops;
909 SDNode *N = Op.getNode();
910 SDValue Glue;
911 for (unsigned I = 0; I < N->getNumOperands(); I++) {
912 SDValue Operand = N->getOperand(Num: I);
913 if (Operand.getValueType() == MVT::Glue) {
914 // The glue operand always needs to be at the end, so we need to treat it
915 // specially.
916 Glue = Operand;
917 } else {
918 Ops.push_back(Elt: Operand);
919 }
920 }
921 InlineAsm::Flag Flags(InlineAsm::Kind::RegUse, 1);
922 Ops.push_back(Elt: DAG.getTargetConstant(Val: Flags, DL: dl, VT: MVT::i32));
923 Ops.push_back(Elt: ZeroReg);
924 if (Glue) {
925 Ops.push_back(Elt: Glue);
926 }
927
928 // Replace the current INLINEASM node with a new one that has the zero
929 // register as implicit parameter.
930 SDValue New = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: N->getVTList(), Ops);
931 DAG.ReplaceAllUsesOfValueWith(From: Op, To: New);
932 DAG.ReplaceAllUsesOfValueWith(From: Op.getValue(R: 1), To: New.getValue(R: 1));
933
934 return New;
935}
936
937SDValue AVRTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
938 switch (Op.getOpcode()) {
939 default:
940 llvm_unreachable("Don't know how to custom lower this!");
941 case ISD::SHL:
942 case ISD::SRA:
943 case ISD::SRL:
944 case ISD::ROTL:
945 case ISD::ROTR:
946 return LowerShifts(Op, DAG);
947 case ISD::GlobalAddress:
948 return LowerGlobalAddress(Op, DAG);
949 case ISD::BlockAddress:
950 return LowerBlockAddress(Op, DAG);
951 case ISD::BR_CC:
952 return LowerBR_CC(Op, DAG);
953 case ISD::SELECT_CC:
954 return LowerSELECT_CC(Op, DAG);
955 case ISD::SETCC:
956 return LowerSETCC(Op, DAG);
957 case ISD::VASTART:
958 return LowerVASTART(Op, DAG);
959 case ISD::SDIVREM:
960 case ISD::UDIVREM:
961 return LowerDivRem(Op, DAG);
962 case ISD::INLINEASM:
963 return LowerINLINEASM(Op, DAG);
964 }
965
966 return SDValue();
967}
968
969/// Replace a node with an illegal result type
970/// with a new node built out of custom code.
971void AVRTargetLowering::ReplaceNodeResults(SDNode *N,
972 SmallVectorImpl<SDValue> &Results,
973 SelectionDAG &DAG) const {
974 SDLoc DL(N);
975
976 switch (N->getOpcode()) {
977 case ISD::ADD: {
978 // Convert add (x, imm) into sub (x, -imm).
979 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
980 SDValue Sub = DAG.getNode(
981 Opcode: ISD::SUB, DL, VT: N->getValueType(ResNo: 0), N1: N->getOperand(Num: 0),
982 N2: DAG.getConstant(Val: -C->getAPIntValue(), DL, VT: C->getValueType(ResNo: 0)));
983 Results.push_back(Elt: Sub);
984 }
985 break;
986 }
987 default: {
988 SDValue Res = LowerOperation(Op: SDValue(N, 0), DAG);
989
990 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
991 Results.push_back(Elt: Res.getValue(R: I));
992
993 break;
994 }
995 }
996}
997
998/// Return true if the addressing mode represented
999/// by AM is legal for this target, for a load/store of the specified type.
1000bool AVRTargetLowering::isLegalAddressingMode(const DataLayout &DL,
1001 const AddrMode &AM, Type *Ty,
1002 unsigned AS,
1003 Instruction *I) const {
1004 int64_t Offs = AM.BaseOffs;
1005
1006 // Allow absolute addresses.
1007 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) {
1008 return true;
1009 }
1010
1011 // Flash memory instructions only allow zero offsets.
1012 if (isa<PointerType>(Val: Ty) && AS == AVR::ProgramMemory) {
1013 return false;
1014 }
1015
1016 // Allow reg+<6bit> offset.
1017 if (Offs < 0)
1018 Offs = -Offs;
1019 if (AM.BaseGV == nullptr && AM.HasBaseReg && AM.Scale == 0 &&
1020 isUInt<6>(x: Offs)) {
1021 return true;
1022 }
1023
1024 return false;
1025}
1026
1027/// Returns true by value, base pointer and
1028/// offset pointer and addressing mode by reference if the node's address
1029/// can be legally represented as pre-indexed load / store address.
1030bool AVRTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1031 SDValue &Offset,
1032 ISD::MemIndexedMode &AM,
1033 SelectionDAG &DAG) const {
1034 EVT VT;
1035 const SDNode *Op;
1036 SDLoc DL(N);
1037
1038 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(Val: N)) {
1039 VT = LD->getMemoryVT();
1040 Op = LD->getBasePtr().getNode();
1041 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1042 return false;
1043 if (AVR::isProgramMemoryAccess(N: LD)) {
1044 return false;
1045 }
1046 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(Val: N)) {
1047 VT = ST->getMemoryVT();
1048 Op = ST->getBasePtr().getNode();
1049 if (AVR::isProgramMemoryAccess(N: ST)) {
1050 return false;
1051 }
1052 } else {
1053 return false;
1054 }
1055
1056 if (VT != MVT::i8 && VT != MVT::i16) {
1057 return false;
1058 }
1059
1060 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
1061 return false;
1062 }
1063
1064 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Val: Op->getOperand(Num: 1))) {
1065 int RHSC = RHS->getSExtValue();
1066 if (Op->getOpcode() == ISD::SUB)
1067 RHSC = -RHSC;
1068
1069 if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
1070 return false;
1071 }
1072
1073 Base = Op->getOperand(Num: 0);
1074 Offset = DAG.getSignedConstant(Val: RHSC, DL, VT: MVT::i8);
1075 AM = ISD::PRE_DEC;
1076
1077 return true;
1078 }
1079
1080 return false;
1081}
1082
1083/// Returns true by value, base pointer and
1084/// offset pointer and addressing mode by reference if this node can be
1085/// combined with a load / store to form a post-indexed load / store.
1086bool AVRTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1087 SDValue &Base,
1088 SDValue &Offset,
1089 ISD::MemIndexedMode &AM,
1090 SelectionDAG &DAG) const {
1091 EVT VT;
1092 SDValue Ptr;
1093 SDLoc DL(N);
1094
1095 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(Val: N)) {
1096 VT = LD->getMemoryVT();
1097 Ptr = LD->getBasePtr();
1098 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1099 return false;
1100 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(Val: N)) {
1101 VT = ST->getMemoryVT();
1102 Ptr = ST->getBasePtr();
1103 // We can not store to program memory.
1104 if (AVR::isProgramMemoryAccess(N: ST))
1105 return false;
1106 // Since the high byte need to be stored first, we can not emit
1107 // i16 post increment store like:
1108 // st X+, r24
1109 // st X+, r25
1110 if (VT == MVT::i16 && !Subtarget.hasLowByteFirst())
1111 return false;
1112 } else {
1113 return false;
1114 }
1115
1116 if (VT != MVT::i8 && VT != MVT::i16) {
1117 return false;
1118 }
1119
1120 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
1121 return false;
1122 }
1123
1124 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Val: Op->getOperand(Num: 1))) {
1125 int RHSC = RHS->getSExtValue();
1126 if (Op->getOpcode() == ISD::SUB)
1127 RHSC = -RHSC;
1128 if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) {
1129 return false;
1130 }
1131
1132 // FIXME: We temporarily disable post increment load from program memory,
1133 // due to bug https://github.com/llvm/llvm-project/issues/59914.
1134 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(Val: N))
1135 if (AVR::isProgramMemoryAccess(N: LD))
1136 return false;
1137
1138 Base = Op->getOperand(Num: 0);
1139
1140 // Post-indexing updates the base, so it's not a valid transform
1141 // if that's not the same as the load's pointer.
1142 if (Ptr != Base)
1143 return false;
1144
1145 Offset = DAG.getConstant(Val: RHSC, DL, VT: MVT::i8);
1146 AM = ISD::POST_INC;
1147
1148 return true;
1149 }
1150
1151 return false;
1152}
1153
1154bool AVRTargetLowering::isOffsetFoldingLegal(
1155 const GlobalAddressSDNode *GA) const {
1156 return true;
1157}
1158
1159//===----------------------------------------------------------------------===//
1160// Formal Arguments Calling Convention Implementation
1161//===----------------------------------------------------------------------===//
1162
1163#define GET_CALLING_CONV_IMPL
1164#include "AVRGenCallingConv.inc"
1165
1166/// Registers for calling conventions, ordered in reverse as required by ABI.
1167/// Both arrays must be of the same length.
1168static const MCPhysReg RegList8AVR[] = {
1169 AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20,
1170 AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
1171 AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8};
1172static const MCPhysReg RegList8Tiny[] = {AVR::R25, AVR::R24, AVR::R23,
1173 AVR::R22, AVR::R21, AVR::R20};
1174static const MCPhysReg RegList16AVR[] = {
1175 AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, AVR::R22R21,
1176 AVR::R21R20, AVR::R20R19, AVR::R19R18, AVR::R18R17, AVR::R17R16,
1177 AVR::R16R15, AVR::R15R14, AVR::R14R13, AVR::R13R12, AVR::R12R11,
1178 AVR::R11R10, AVR::R10R9, AVR::R9R8};
1179static const MCPhysReg RegList16Tiny[] = {AVR::R26R25, AVR::R25R24,
1180 AVR::R24R23, AVR::R23R22,
1181 AVR::R22R21, AVR::R21R20};
1182
1183static_assert(std::size(RegList8AVR) == std::size(RegList16AVR),
1184 "8-bit and 16-bit register arrays must be of equal length");
1185static_assert(std::size(RegList8Tiny) == std::size(RegList16Tiny),
1186 "8-bit and 16-bit register arrays must be of equal length");
1187
1188/// Analyze incoming and outgoing function arguments. We need custom C++ code
1189/// to handle special constraints in the ABI.
1190/// In addition, all pieces of a certain argument have to be passed either
1191/// using registers or the stack but never mixing both.
1192template <typename ArgT>
1193static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI,
1194 const Function *F, const DataLayout *TD,
1195 const SmallVectorImpl<ArgT> &Args,
1196 SmallVectorImpl<CCValAssign> &ArgLocs,
1197 CCState &CCInfo, bool Tiny) {
1198 // Choose the proper register list for argument passing according to the ABI.
1199 ArrayRef<MCPhysReg> RegList8;
1200 ArrayRef<MCPhysReg> RegList16;
1201 if (Tiny) {
1202 RegList8 = ArrayRef(RegList8Tiny);
1203 RegList16 = ArrayRef(RegList16Tiny);
1204 } else {
1205 RegList8 = ArrayRef(RegList8AVR);
1206 RegList16 = ArrayRef(RegList16AVR);
1207 }
1208
1209 unsigned NumArgs = Args.size();
1210 // This is the index of the last used register, in RegList*.
1211 // -1 means R26 (R26 is never actually used in CC).
1212 int RegLastIdx = -1;
1213 // Once a value is passed to the stack it will always be used
1214 bool UseStack = false;
1215 for (unsigned i = 0; i != NumArgs;) {
1216 MVT VT = Args[i].VT;
1217 // We have to count the number of bytes for each function argument, that is
1218 // those Args with the same OrigArgIndex. This is important in case the
1219 // function takes an aggregate type.
1220 // Current argument will be between [i..j).
1221 unsigned ArgIndex = Args[i].OrigArgIndex;
1222 unsigned TotalBytes = VT.getStoreSize();
1223 unsigned j = i + 1;
1224 for (; j != NumArgs; ++j) {
1225 if (Args[j].OrigArgIndex != ArgIndex)
1226 break;
1227 TotalBytes += Args[j].VT.getStoreSize();
1228 }
1229 // Round up to even number of bytes.
1230 TotalBytes = alignTo(Value: TotalBytes, Align: 2);
1231 // Skip zero sized arguments
1232 if (TotalBytes == 0)
1233 continue;
1234 // The index of the first register to be used
1235 unsigned RegIdx = RegLastIdx + TotalBytes;
1236 RegLastIdx = RegIdx;
1237 // If there are not enough registers, use the stack
1238 if (RegIdx >= RegList8.size()) {
1239 UseStack = true;
1240 }
1241 for (; i != j; ++i) {
1242 MVT VT = Args[i].VT;
1243
1244 if (UseStack) {
1245 auto evt = EVT(VT).getTypeForEVT(Context&: CCInfo.getContext());
1246 unsigned Offset = CCInfo.AllocateStack(Size: TD->getTypeAllocSize(Ty: evt),
1247 Alignment: TD->getABITypeAlign(Ty: evt));
1248 CCInfo.addLoc(
1249 V: CCValAssign::getMem(ValNo: i, ValVT: VT, Offset, LocVT: VT, HTP: CCValAssign::Full));
1250 } else {
1251 unsigned Reg;
1252 if (VT == MVT::i8) {
1253 Reg = CCInfo.AllocateReg(Reg: RegList8[RegIdx]);
1254 } else if (VT == MVT::i16) {
1255 Reg = CCInfo.AllocateReg(Reg: RegList16[RegIdx]);
1256 } else {
1257 llvm_unreachable(
1258 "calling convention can only manage i8 and i16 types");
1259 }
1260 assert(Reg && "register not available in calling convention");
1261 CCInfo.addLoc(V: CCValAssign::getReg(ValNo: i, ValVT: VT, Reg, LocVT: VT, HTP: CCValAssign::Full));
1262 // Registers inside a particular argument are sorted in increasing order
1263 // (remember the array is reversed).
1264 RegIdx -= VT.getStoreSize();
1265 }
1266 }
1267 }
1268}
1269
1270/// Count the total number of bytes needed to pass or return these arguments.
1271template <typename ArgT>
1272static unsigned
1273getTotalArgumentsSizeInBytes(const SmallVectorImpl<ArgT> &Args) {
1274 unsigned TotalBytes = 0;
1275
1276 for (const ArgT &Arg : Args) {
1277 TotalBytes += Arg.VT.getStoreSize();
1278 }
1279 return TotalBytes;
1280}
1281
1282/// Analyze incoming and outgoing value of returning from a function.
1283/// The algorithm is similar to analyzeArguments, but there can only be
1284/// one value, possibly an aggregate, and it is limited to 8 bytes.
1285template <typename ArgT>
1286static void analyzeReturnValues(const SmallVectorImpl<ArgT> &Args,
1287 CCState &CCInfo, bool Tiny) {
1288 unsigned NumArgs = Args.size();
1289 unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args);
1290 // CanLowerReturn() guarantees this assertion.
1291 if (Tiny)
1292 assert(TotalBytes <= 4 &&
1293 "return values greater than 4 bytes cannot be lowered on AVRTiny");
1294 else
1295 assert(TotalBytes <= 8 &&
1296 "return values greater than 8 bytes cannot be lowered on AVR");
1297
1298 // Choose the proper register list for argument passing according to the ABI.
1299 ArrayRef<MCPhysReg> RegList8;
1300 ArrayRef<MCPhysReg> RegList16;
1301 if (Tiny) {
1302 RegList8 = ArrayRef(RegList8Tiny);
1303 RegList16 = ArrayRef(RegList16Tiny);
1304 } else {
1305 RegList8 = ArrayRef(RegList8AVR);
1306 RegList16 = ArrayRef(RegList16AVR);
1307 }
1308
1309 // GCC-ABI says that the size is rounded up to the next even number,
1310 // but actually once it is more than 4 it will always round up to 8.
1311 if (TotalBytes > 4) {
1312 TotalBytes = 8;
1313 } else {
1314 TotalBytes = alignTo(Value: TotalBytes, Align: 2);
1315 }
1316
1317 // The index of the first register to use.
1318 int RegIdx = TotalBytes - 1;
1319 for (unsigned i = 0; i != NumArgs; ++i) {
1320 MVT VT = Args[i].VT;
1321 unsigned Reg;
1322 if (VT == MVT::i8) {
1323 Reg = CCInfo.AllocateReg(Reg: RegList8[RegIdx]);
1324 } else if (VT == MVT::i16) {
1325 Reg = CCInfo.AllocateReg(Reg: RegList16[RegIdx]);
1326 } else {
1327 llvm_unreachable("calling convention can only manage i8 and i16 types");
1328 }
1329 assert(Reg && "register not available in calling convention");
1330 CCInfo.addLoc(V: CCValAssign::getReg(ValNo: i, ValVT: VT, Reg, LocVT: VT, HTP: CCValAssign::Full));
1331 // Registers sort in increasing order
1332 RegIdx -= VT.getStoreSize();
1333 }
1334}
1335
1336SDValue AVRTargetLowering::LowerFormalArguments(
1337 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1338 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1339 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1340 MachineFunction &MF = DAG.getMachineFunction();
1341 MachineFrameInfo &MFI = MF.getFrameInfo();
1342 auto DL = DAG.getDataLayout();
1343
1344 // Assign locations to all of the incoming arguments.
1345 SmallVector<CCValAssign, 16> ArgLocs;
1346 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1347 *DAG.getContext());
1348
1349 // Variadic functions do not need all the analysis below.
1350 if (isVarArg) {
1351 CCInfo.AnalyzeFormalArguments(Ins, Fn: ArgCC_AVR_Vararg);
1352 } else {
1353 analyzeArguments(CLI: nullptr, F: &MF.getFunction(), TD: &DL, Args: Ins, ArgLocs, CCInfo,
1354 Tiny: Subtarget.hasTinyEncoding());
1355 }
1356
1357 SDValue ArgValue;
1358 for (CCValAssign &VA : ArgLocs) {
1359
1360 // Arguments stored on registers.
1361 if (VA.isRegLoc()) {
1362 EVT RegVT = VA.getLocVT();
1363 const TargetRegisterClass *RC;
1364 if (RegVT == MVT::i8) {
1365 RC = &AVR::GPR8RegClass;
1366 } else if (RegVT == MVT::i16) {
1367 RC = &AVR::DREGSRegClass;
1368 } else {
1369 llvm_unreachable("Unknown argument type!");
1370 }
1371
1372 Register Reg = MF.addLiveIn(PReg: VA.getLocReg(), RC);
1373 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, VT: RegVT);
1374
1375 // :NOTE: Clang should not promote any i8 into i16 but for safety the
1376 // following code will handle zexts or sexts generated by other
1377 // front ends. Otherwise:
1378 // If this is an 8 bit value, it is really passed promoted
1379 // to 16 bits. Insert an assert[sz]ext to capture this, then
1380 // truncate to the right size.
1381 switch (VA.getLocInfo()) {
1382 default:
1383 llvm_unreachable("Unknown loc info!");
1384 case CCValAssign::Full:
1385 break;
1386 case CCValAssign::BCvt:
1387 ArgValue = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: VA.getValVT(), Operand: ArgValue);
1388 break;
1389 case CCValAssign::SExt:
1390 ArgValue = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: RegVT, N1: ArgValue,
1391 N2: DAG.getValueType(VA.getValVT()));
1392 ArgValue = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: VA.getValVT(), Operand: ArgValue);
1393 break;
1394 case CCValAssign::ZExt:
1395 ArgValue = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: RegVT, N1: ArgValue,
1396 N2: DAG.getValueType(VA.getValVT()));
1397 ArgValue = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: VA.getValVT(), Operand: ArgValue);
1398 break;
1399 }
1400
1401 InVals.push_back(Elt: ArgValue);
1402 } else {
1403 // Only arguments passed on the stack should make it here.
1404 assert(VA.isMemLoc());
1405
1406 EVT LocVT = VA.getLocVT();
1407
1408 // Create the frame index object for this incoming parameter.
1409 int FI = MFI.CreateFixedObject(Size: LocVT.getSizeInBits() / 8,
1410 SPOffset: VA.getLocMemOffset(), IsImmutable: true);
1411
1412 // Create the SelectionDAG nodes corresponding to a load
1413 // from this parameter.
1414 SDValue FIN = DAG.getFrameIndex(FI, VT: getPointerTy(DL));
1415 InVals.push_back(Elt: DAG.getLoad(VT: LocVT, dl, Chain, Ptr: FIN,
1416 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)));
1417 }
1418 }
1419
1420 // If the function takes variable number of arguments, make a frame index for
1421 // the start of the first vararg value... for expansion of llvm.va_start.
1422 if (isVarArg) {
1423 unsigned StackSize = CCInfo.getStackSize();
1424 AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1425
1426 AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(Size: 2, SPOffset: StackSize, IsImmutable: true));
1427 }
1428
1429 return Chain;
1430}
1431
1432//===----------------------------------------------------------------------===//
1433// Call Calling Convention Implementation
1434//===----------------------------------------------------------------------===//
1435
1436SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1437 SmallVectorImpl<SDValue> &InVals) const {
1438 SelectionDAG &DAG = CLI.DAG;
1439 SDLoc &DL = CLI.DL;
1440 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1441 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1442 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1443 SDValue Chain = CLI.Chain;
1444 SDValue Callee = CLI.Callee;
1445 bool &isTailCall = CLI.IsTailCall;
1446 CallingConv::ID CallConv = CLI.CallConv;
1447 bool isVarArg = CLI.IsVarArg;
1448
1449 MachineFunction &MF = DAG.getMachineFunction();
1450
1451 // AVR does not yet support tail call optimization.
1452 isTailCall = false;
1453
1454 // Analyze operands of the call, assigning locations to each operand.
1455 SmallVector<CCValAssign, 16> ArgLocs;
1456 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1457 *DAG.getContext());
1458
1459 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1460 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1461 // node so that legalize doesn't hack it.
1462 const Function *F = nullptr;
1463 if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee)) {
1464 const GlobalValue *GV = G->getGlobal();
1465 if (isa<Function>(Val: GV))
1466 F = cast<Function>(Val: GV);
1467 Callee =
1468 DAG.getTargetGlobalAddress(GV, DL, VT: getPointerTy(DL: DAG.getDataLayout()));
1469 } else if (const ExternalSymbolSDNode *ES =
1470 dyn_cast<ExternalSymbolSDNode>(Val&: Callee)) {
1471 Callee = DAG.getTargetExternalSymbol(Sym: ES->getSymbol(),
1472 VT: getPointerTy(DL: DAG.getDataLayout()));
1473 }
1474
1475 // Variadic functions do not need all the analysis below.
1476 if (isVarArg) {
1477 CCInfo.AnalyzeCallOperands(Outs, Fn: ArgCC_AVR_Vararg);
1478 } else {
1479 analyzeArguments(CLI: &CLI, F, TD: &DAG.getDataLayout(), Args: Outs, ArgLocs, CCInfo,
1480 Tiny: Subtarget.hasTinyEncoding());
1481 }
1482
1483 // Get a count of how many bytes are to be pushed on the stack.
1484 unsigned NumBytes = CCInfo.getStackSize();
1485
1486 Chain = DAG.getCALLSEQ_START(Chain, InSize: NumBytes, OutSize: 0, DL);
1487
1488 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1489
1490 // First, walk the register assignments, inserting copies.
1491 unsigned AI, AE;
1492 bool HasStackArgs = false;
1493 for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1494 CCValAssign &VA = ArgLocs[AI];
1495 EVT RegVT = VA.getLocVT();
1496 SDValue Arg = OutVals[AI];
1497
1498 // Promote the value if needed. With Clang this should not happen.
1499 switch (VA.getLocInfo()) {
1500 default:
1501 llvm_unreachable("Unknown loc info!");
1502 case CCValAssign::Full:
1503 break;
1504 case CCValAssign::SExt:
1505 Arg = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: RegVT, Operand: Arg);
1506 break;
1507 case CCValAssign::ZExt:
1508 Arg = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: RegVT, Operand: Arg);
1509 break;
1510 case CCValAssign::AExt:
1511 Arg = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: RegVT, Operand: Arg);
1512 break;
1513 case CCValAssign::BCvt:
1514 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: RegVT, Operand: Arg);
1515 break;
1516 }
1517
1518 // Stop when we encounter a stack argument, we need to process them
1519 // in reverse order in the loop below.
1520 if (VA.isMemLoc()) {
1521 HasStackArgs = true;
1522 break;
1523 }
1524
1525 // Arguments that can be passed on registers must be kept in the RegsToPass
1526 // vector.
1527 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Arg));
1528 }
1529
1530 // Second, stack arguments have to walked.
1531 // Previously this code created chained stores but those chained stores appear
1532 // to be unchained in the legalization phase. Therefore, do not attempt to
1533 // chain them here. In fact, chaining them here somehow causes the first and
1534 // second store to be reversed which is the exact opposite of the intended
1535 // effect.
1536 if (HasStackArgs) {
1537 SmallVector<SDValue, 8> MemOpChains;
1538 for (; AI != AE; AI++) {
1539 CCValAssign &VA = ArgLocs[AI];
1540 SDValue Arg = OutVals[AI];
1541
1542 assert(VA.isMemLoc());
1543
1544 // SP points to one stack slot further so add one to adjust it.
1545 SDValue PtrOff = DAG.getNode(
1546 Opcode: ISD::ADD, DL, VT: getPointerTy(DL: DAG.getDataLayout()),
1547 N1: DAG.getRegister(Reg: AVR::SP, VT: getPointerTy(DL: DAG.getDataLayout())),
1548 N2: DAG.getIntPtrConstant(Val: VA.getLocMemOffset() + 1, DL));
1549
1550 MemOpChains.push_back(
1551 Elt: DAG.getStore(Chain, dl: DL, Val: Arg, Ptr: PtrOff,
1552 PtrInfo: MachinePointerInfo::getStack(MF, Offset: VA.getLocMemOffset())));
1553 }
1554
1555 if (!MemOpChains.empty())
1556 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: MemOpChains);
1557 }
1558
1559 // Build a sequence of copy-to-reg nodes chained together with token chain and
1560 // flag operands which copy the outgoing args into registers. The InGlue in
1561 // necessary since all emited instructions must be stuck together.
1562 SDValue InGlue;
1563 for (auto Reg : RegsToPass) {
1564 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: Reg.first, N: Reg.second, Glue: InGlue);
1565 InGlue = Chain.getValue(R: 1);
1566 }
1567
1568 // Returns a chain & a flag for retval copy to use.
1569 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
1570 SmallVector<SDValue, 8> Ops;
1571 Ops.push_back(Elt: Chain);
1572 Ops.push_back(Elt: Callee);
1573
1574 // Add argument registers to the end of the list so that they are known live
1575 // into the call.
1576 for (auto Reg : RegsToPass) {
1577 Ops.push_back(Elt: DAG.getRegister(Reg: Reg.first, VT: Reg.second.getValueType()));
1578 }
1579
1580 // The zero register (usually R1) must be passed as an implicit register so
1581 // that this register is correctly zeroed in interrupts.
1582 Ops.push_back(Elt: DAG.getRegister(Reg: Subtarget.getZeroRegister(), VT: MVT::i8));
1583
1584 // Add a register mask operand representing the call-preserved registers.
1585 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1586 const uint32_t *Mask =
1587 TRI->getCallPreservedMask(MF: DAG.getMachineFunction(), CallConv);
1588 assert(Mask && "Missing call preserved mask for calling convention");
1589 Ops.push_back(Elt: DAG.getRegisterMask(RegMask: Mask));
1590
1591 if (InGlue.getNode()) {
1592 Ops.push_back(Elt: InGlue);
1593 }
1594
1595 Chain = DAG.getNode(Opcode: AVRISD::CALL, DL, VTList: NodeTys, Ops);
1596 InGlue = Chain.getValue(R: 1);
1597
1598 // Create the CALLSEQ_END node.
1599 Chain = DAG.getCALLSEQ_END(Chain, Size1: NumBytes, Size2: 0, Glue: InGlue, DL);
1600
1601 if (!Ins.empty()) {
1602 InGlue = Chain.getValue(R: 1);
1603 }
1604
1605 // Handle result values, copying them out of physregs into vregs that we
1606 // return.
1607 return LowerCallResult(Chain, InGlue, CallConv, isVarArg, Ins, dl: DL, DAG,
1608 InVals);
1609}
1610
1611/// Lower the result values of a call into the
1612/// appropriate copies out of appropriate physical registers.
1613///
1614SDValue AVRTargetLowering::LowerCallResult(
1615 SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool isVarArg,
1616 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1617 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1618
1619 // Assign locations to each value returned by this call.
1620 SmallVector<CCValAssign, 16> RVLocs;
1621 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1622 *DAG.getContext());
1623
1624 // Handle runtime calling convs.
1625 if (CallConv == CallingConv::AVR_BUILTIN) {
1626 CCInfo.AnalyzeCallResult(Ins, Fn: RetCC_AVR_BUILTIN);
1627 } else {
1628 analyzeReturnValues(Args: Ins, CCInfo, Tiny: Subtarget.hasTinyEncoding());
1629 }
1630
1631 // Copy all of the result registers out of their specified physreg.
1632 for (CCValAssign const &RVLoc : RVLocs) {
1633 Chain = DAG.getCopyFromReg(Chain, dl, Reg: RVLoc.getLocReg(), VT: RVLoc.getValVT(),
1634 Glue: InGlue)
1635 .getValue(R: 1);
1636 InGlue = Chain.getValue(R: 2);
1637 InVals.push_back(Elt: Chain.getValue(R: 0));
1638 }
1639
1640 return Chain;
1641}
1642
1643//===----------------------------------------------------------------------===//
1644// Return Value Calling Convention Implementation
1645//===----------------------------------------------------------------------===//
1646
1647bool AVRTargetLowering::CanLowerReturn(
1648 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
1649 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
1650 const Type *RetTy) const {
1651 if (CallConv == CallingConv::AVR_BUILTIN) {
1652 SmallVector<CCValAssign, 16> RVLocs;
1653 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1654 return CCInfo.CheckReturn(Outs, Fn: RetCC_AVR_BUILTIN);
1655 }
1656
1657 unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args: Outs);
1658 return TotalBytes <= (unsigned)(Subtarget.hasTinyEncoding() ? 4 : 8);
1659}
1660
1661SDValue
1662AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1663 bool isVarArg,
1664 const SmallVectorImpl<ISD::OutputArg> &Outs,
1665 const SmallVectorImpl<SDValue> &OutVals,
1666 const SDLoc &dl, SelectionDAG &DAG) const {
1667 // CCValAssign - represent the assignment of the return value to locations.
1668 SmallVector<CCValAssign, 16> RVLocs;
1669
1670 // CCState - Info about the registers and stack slot.
1671 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1672 *DAG.getContext());
1673
1674 MachineFunction &MF = DAG.getMachineFunction();
1675
1676 // Analyze return values.
1677 if (CallConv == CallingConv::AVR_BUILTIN) {
1678 CCInfo.AnalyzeReturn(Outs, Fn: RetCC_AVR_BUILTIN);
1679 } else {
1680 analyzeReturnValues(Args: Outs, CCInfo, Tiny: Subtarget.hasTinyEncoding());
1681 }
1682
1683 SDValue Glue;
1684 SmallVector<SDValue, 4> RetOps(1, Chain);
1685 // Copy the result values into the output registers.
1686 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1687 CCValAssign &VA = RVLocs[i];
1688 assert(VA.isRegLoc() && "Can only return in registers!");
1689
1690 Chain = DAG.getCopyToReg(Chain, dl, Reg: VA.getLocReg(), N: OutVals[i], Glue);
1691
1692 // Guarantee that all emitted copies are stuck together with flags.
1693 Glue = Chain.getValue(R: 1);
1694 RetOps.push_back(Elt: DAG.getRegister(Reg: VA.getLocReg(), VT: VA.getLocVT()));
1695 }
1696
1697 // Don't emit the ret/reti instruction when the naked attribute is present in
1698 // the function being compiled.
1699 if (MF.getFunction().getAttributes().hasFnAttr(Kind: Attribute::Naked)) {
1700 return Chain;
1701 }
1702
1703 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1704
1705 if (!AFI->isInterruptOrSignalHandler()) {
1706 // The return instruction has an implicit zero register operand: it must
1707 // contain zero on return.
1708 // This is not needed in interrupts however, where the zero register is
1709 // handled specially (only pushed/popped when needed).
1710 RetOps.push_back(Elt: DAG.getRegister(Reg: Subtarget.getZeroRegister(), VT: MVT::i8));
1711 }
1712
1713 unsigned RetOpc =
1714 AFI->isInterruptOrSignalHandler() ? AVRISD::RETI_GLUE : AVRISD::RET_GLUE;
1715
1716 RetOps[0] = Chain; // Update chain.
1717
1718 if (Glue.getNode()) {
1719 RetOps.push_back(Elt: Glue);
1720 }
1721
1722 return DAG.getNode(Opcode: RetOpc, DL: dl, VT: MVT::Other, Ops: RetOps);
1723}
1724
1725//===----------------------------------------------------------------------===//
1726// Custom Inserters
1727//===----------------------------------------------------------------------===//
1728
1729MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
1730 MachineBasicBlock *BB,
1731 bool Tiny) const {
1732 unsigned Opc;
1733 const TargetRegisterClass *RC;
1734 bool HasRepeatedOperand = false;
1735 MachineFunction *F = BB->getParent();
1736 MachineRegisterInfo &RI = F->getRegInfo();
1737 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1738 DebugLoc dl = MI.getDebugLoc();
1739
1740 switch (MI.getOpcode()) {
1741 default:
1742 llvm_unreachable("Invalid shift opcode!");
1743 case AVR::Lsl8:
1744 Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd
1745 RC = &AVR::GPR8RegClass;
1746 HasRepeatedOperand = true;
1747 break;
1748 case AVR::Lsl16:
1749 Opc = AVR::LSLWRd;
1750 RC = &AVR::DREGSRegClass;
1751 break;
1752 case AVR::Asr8:
1753 Opc = AVR::ASRRd;
1754 RC = &AVR::GPR8RegClass;
1755 break;
1756 case AVR::Asr16:
1757 Opc = AVR::ASRWRd;
1758 RC = &AVR::DREGSRegClass;
1759 break;
1760 case AVR::Lsr8:
1761 Opc = AVR::LSRRd;
1762 RC = &AVR::GPR8RegClass;
1763 break;
1764 case AVR::Lsr16:
1765 Opc = AVR::LSRWRd;
1766 RC = &AVR::DREGSRegClass;
1767 break;
1768 case AVR::Rol8:
1769 Opc = Tiny ? AVR::ROLBRdR17 : AVR::ROLBRdR1;
1770 RC = &AVR::GPR8RegClass;
1771 break;
1772 case AVR::Rol16:
1773 Opc = AVR::ROLWRd;
1774 RC = &AVR::DREGSRegClass;
1775 break;
1776 case AVR::Ror8:
1777 Opc = AVR::RORBRd;
1778 RC = &AVR::GPR8RegClass;
1779 break;
1780 case AVR::Ror16:
1781 Opc = AVR::RORWRd;
1782 RC = &AVR::DREGSRegClass;
1783 break;
1784 }
1785
1786 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1787
1788 MachineFunction::iterator I;
1789 for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I)
1790 ;
1791 if (I != F->end())
1792 ++I;
1793
1794 // Create loop block.
1795 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
1796 MachineBasicBlock *CheckBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
1797 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
1798
1799 F->insert(MBBI: I, MBB: LoopBB);
1800 F->insert(MBBI: I, MBB: CheckBB);
1801 F->insert(MBBI: I, MBB: RemBB);
1802
1803 // Update machine-CFG edges by transferring all successors of the current
1804 // block to the block containing instructions after shift.
1805 RemBB->splice(Where: RemBB->begin(), Other: BB, From: std::next(x: MachineBasicBlock::iterator(MI)),
1806 To: BB->end());
1807 RemBB->transferSuccessorsAndUpdatePHIs(FromMBB: BB);
1808
1809 // Add edges BB => LoopBB => CheckBB => RemBB, CheckBB => LoopBB.
1810 BB->addSuccessor(Succ: CheckBB);
1811 LoopBB->addSuccessor(Succ: CheckBB);
1812 CheckBB->addSuccessor(Succ: LoopBB);
1813 CheckBB->addSuccessor(Succ: RemBB);
1814
1815 Register ShiftAmtReg = RI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
1816 Register ShiftAmtReg2 = RI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
1817 Register ShiftReg = RI.createVirtualRegister(RegClass: RC);
1818 Register ShiftReg2 = RI.createVirtualRegister(RegClass: RC);
1819 Register ShiftAmtSrcReg = MI.getOperand(i: 2).getReg();
1820 Register SrcReg = MI.getOperand(i: 1).getReg();
1821 Register DstReg = MI.getOperand(i: 0).getReg();
1822
1823 // BB:
1824 // rjmp CheckBB
1825 BuildMI(BB, MIMD: dl, MCID: TII.get(Opcode: AVR::RJMPk)).addMBB(MBB: CheckBB);
1826
1827 // LoopBB:
1828 // ShiftReg2 = shift ShiftReg
1829 auto ShiftMI = BuildMI(BB: LoopBB, MIMD: dl, MCID: TII.get(Opcode: Opc), DestReg: ShiftReg2).addReg(RegNo: ShiftReg);
1830 if (HasRepeatedOperand)
1831 ShiftMI.addReg(RegNo: ShiftReg);
1832
1833 // CheckBB:
1834 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1835 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1836 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1837 // ShiftAmt2 = ShiftAmt - 1;
1838 // if (ShiftAmt2 >= 0) goto LoopBB;
1839 BuildMI(BB: CheckBB, MIMD: dl, MCID: TII.get(Opcode: AVR::PHI), DestReg: ShiftReg)
1840 .addReg(RegNo: SrcReg)
1841 .addMBB(MBB: BB)
1842 .addReg(RegNo: ShiftReg2)
1843 .addMBB(MBB: LoopBB);
1844 BuildMI(BB: CheckBB, MIMD: dl, MCID: TII.get(Opcode: AVR::PHI), DestReg: ShiftAmtReg)
1845 .addReg(RegNo: ShiftAmtSrcReg)
1846 .addMBB(MBB: BB)
1847 .addReg(RegNo: ShiftAmtReg2)
1848 .addMBB(MBB: LoopBB);
1849 BuildMI(BB: CheckBB, MIMD: dl, MCID: TII.get(Opcode: AVR::PHI), DestReg: DstReg)
1850 .addReg(RegNo: SrcReg)
1851 .addMBB(MBB: BB)
1852 .addReg(RegNo: ShiftReg2)
1853 .addMBB(MBB: LoopBB);
1854
1855 BuildMI(BB: CheckBB, MIMD: dl, MCID: TII.get(Opcode: AVR::DECRd), DestReg: ShiftAmtReg2).addReg(RegNo: ShiftAmtReg);
1856 BuildMI(BB: CheckBB, MIMD: dl, MCID: TII.get(Opcode: AVR::BRPLk)).addMBB(MBB: LoopBB);
1857
1858 MI.eraseFromParent(); // The pseudo instruction is gone now.
1859 return RemBB;
1860}
1861
1862// Do a multibyte AVR shift. Insert shift instructions and put the output
1863// registers in the Regs array.
1864// Because AVR does not have a normal shift instruction (only a single bit shift
1865// instruction), we have to emulate this behavior with other instructions.
1866// It first tries large steps (moving registers around) and then smaller steps
1867// like single bit shifts.
1868// Large shifts actually reduce the number of shifted registers, so the below
1869// algorithms have to work independently of the number of registers that are
1870// shifted.
1871// For more information and background, see this blogpost:
1872// https://aykevl.nl/2021/02/avr-bitshift
1873static void insertMultibyteShift(MachineInstr &MI, MachineBasicBlock *BB,
1874 MutableArrayRef<std::pair<Register, int>> Regs,
1875 ISD::NodeType Opc, int64_t ShiftAmt) {
1876 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
1877 const AVRSubtarget &STI = BB->getParent()->getSubtarget<AVRSubtarget>();
1878 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
1879 const DebugLoc &dl = MI.getDebugLoc();
1880
1881 const bool ShiftLeft = Opc == ISD::SHL;
1882 const bool ArithmeticShift = Opc == ISD::SRA;
1883
1884 // Zero a register, for use in later operations.
1885 Register ZeroReg = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
1886 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::COPY), DestReg: ZeroReg)
1887 .addReg(RegNo: STI.getZeroRegister());
1888
1889 // Do a shift modulo 6 or 7. This is a bit more complicated than most shifts
1890 // and is hard to compose with the rest, so these are special cased.
1891 // The basic idea is to shift one or two bits in the opposite direction and
1892 // then move registers around to get the correct end result.
1893 if (ShiftLeft && (ShiftAmt % 8) >= 6) {
1894 // Left shift modulo 6 or 7.
1895
1896 // Create a slice of the registers we're going to modify, to ease working
1897 // with them.
1898 size_t ShiftRegsOffset = ShiftAmt / 8;
1899 size_t ShiftRegsSize = Regs.size() - ShiftRegsOffset;
1900 MutableArrayRef<std::pair<Register, int>> ShiftRegs =
1901 Regs.slice(N: ShiftRegsOffset, M: ShiftRegsSize);
1902
1903 // Shift one to the right, keeping the least significant bit as the carry
1904 // bit.
1905 insertMultibyteShift(MI, BB, Regs: ShiftRegs, Opc: ISD::SRL, ShiftAmt: 1);
1906
1907 // Rotate the least significant bit from the carry bit into a new register
1908 // (that starts out zero).
1909 Register LowByte = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
1910 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::RORRd), DestReg: LowByte).addReg(RegNo: ZeroReg);
1911
1912 // Shift one more to the right if this is a modulo-6 shift.
1913 if (ShiftAmt % 8 == 6) {
1914 insertMultibyteShift(MI, BB, Regs: ShiftRegs, Opc: ISD::SRL, ShiftAmt: 1);
1915 Register NewLowByte = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
1916 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::RORRd), DestReg: NewLowByte).addReg(RegNo: LowByte);
1917 LowByte = NewLowByte;
1918 }
1919
1920 // Move all registers to the left, zeroing the bottom registers as needed.
1921 for (size_t I = 0; I < Regs.size(); I++) {
1922 int ShiftRegsIdx = I + 1;
1923 if (ShiftRegsIdx < (int)ShiftRegs.size()) {
1924 Regs[I] = ShiftRegs[ShiftRegsIdx];
1925 } else if (ShiftRegsIdx == (int)ShiftRegs.size()) {
1926 Regs[I] = std::pair(LowByte, 0);
1927 } else {
1928 Regs[I] = std::pair(ZeroReg, 0);
1929 }
1930 }
1931
1932 return;
1933 }
1934
1935 // Right shift modulo 6 or 7.
1936 if (!ShiftLeft && (ShiftAmt % 8) >= 6) {
1937 // Create a view on the registers we're going to modify, to ease working
1938 // with them.
1939 size_t ShiftRegsSize = Regs.size() - (ShiftAmt / 8);
1940 MutableArrayRef<std::pair<Register, int>> ShiftRegs =
1941 Regs.slice(N: 0, M: ShiftRegsSize);
1942
1943 // Shift one to the left.
1944 insertMultibyteShift(MI, BB, Regs: ShiftRegs, Opc: ISD::SHL, ShiftAmt: 1);
1945
1946 // Sign or zero extend the most significant register into a new register.
1947 // The HighByte is the byte that still has one (or two) bits from the
1948 // original value. The ExtByte is purely a zero/sign extend byte (all bits
1949 // are either 0 or 1).
1950 Register HighByte = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
1951 Register ExtByte = 0;
1952 if (ArithmeticShift) {
1953 // Sign-extend bit that was shifted out last.
1954 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::SBCRdRr), DestReg: HighByte)
1955 .addReg(RegNo: HighByte, Flags: RegState::Undef)
1956 .addReg(RegNo: HighByte, Flags: RegState::Undef);
1957 ExtByte = HighByte;
1958 // The highest bit of the original value is the same as the zero-extend
1959 // byte, so HighByte and ExtByte are the same.
1960 } else {
1961 // Use the zero register for zero extending.
1962 ExtByte = ZeroReg;
1963 // Rotate most significant bit into a new register (that starts out zero).
1964 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::ADCRdRr), DestReg: HighByte)
1965 .addReg(RegNo: ExtByte)
1966 .addReg(RegNo: ExtByte);
1967 }
1968
1969 // Shift one more to the left for modulo 6 shifts.
1970 if (ShiftAmt % 8 == 6) {
1971 insertMultibyteShift(MI, BB, Regs: ShiftRegs, Opc: ISD::SHL, ShiftAmt: 1);
1972 // Shift the topmost bit into the HighByte.
1973 Register NewExt = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
1974 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::ADCRdRr), DestReg: NewExt)
1975 .addReg(RegNo: HighByte)
1976 .addReg(RegNo: HighByte);
1977 HighByte = NewExt;
1978 }
1979
1980 // Move all to the right, while sign or zero extending.
1981 for (int I = Regs.size() - 1; I >= 0; I--) {
1982 int ShiftRegsIdx = I - (Regs.size() - ShiftRegs.size()) - 1;
1983 if (ShiftRegsIdx >= 0) {
1984 Regs[I] = ShiftRegs[ShiftRegsIdx];
1985 } else if (ShiftRegsIdx == -1) {
1986 Regs[I] = std::pair(HighByte, 0);
1987 } else {
1988 Regs[I] = std::pair(ExtByte, 0);
1989 }
1990 }
1991
1992 return;
1993 }
1994
1995 // For shift amounts of at least one register, simply rename the registers and
1996 // zero the bottom registers.
1997 while (ShiftLeft && ShiftAmt >= 8) {
1998 // Move all registers one to the left.
1999 for (size_t I = 0; I < Regs.size() - 1; I++) {
2000 Regs[I] = Regs[I + 1];
2001 }
2002
2003 // Zero the least significant register.
2004 Regs[Regs.size() - 1] = std::pair(ZeroReg, 0);
2005
2006 // Continue shifts with the leftover registers.
2007 Regs = Regs.drop_back(N: 1);
2008
2009 ShiftAmt -= 8;
2010 }
2011
2012 // And again, the same for right shifts.
2013 Register ShrExtendReg = 0;
2014 if (!ShiftLeft && ShiftAmt >= 8) {
2015 if (ArithmeticShift) {
2016 // Sign extend the most significant register into ShrExtendReg.
2017 ShrExtendReg = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
2018 Register Tmp = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
2019 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::ADDRdRr), DestReg: Tmp)
2020 .addReg(RegNo: Regs[0].first, Flags: {}, SubReg: Regs[0].second)
2021 .addReg(RegNo: Regs[0].first, Flags: {}, SubReg: Regs[0].second);
2022 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::SBCRdRr), DestReg: ShrExtendReg)
2023 .addReg(RegNo: Tmp)
2024 .addReg(RegNo: Tmp);
2025 } else {
2026 ShrExtendReg = ZeroReg;
2027 }
2028 for (; ShiftAmt >= 8; ShiftAmt -= 8) {
2029 // Move all registers one to the right.
2030 for (size_t I = Regs.size() - 1; I != 0; I--) {
2031 Regs[I] = Regs[I - 1];
2032 }
2033
2034 // Zero or sign extend the most significant register.
2035 Regs[0] = std::pair(ShrExtendReg, 0);
2036
2037 // Continue shifts with the leftover registers.
2038 Regs = Regs.drop_front(N: 1);
2039 }
2040 }
2041
2042 // The bigger shifts are already handled above.
2043 assert((ShiftAmt < 8) && "Unexpect shift amount");
2044
2045 // Shift by four bits, using a complicated swap/eor/andi/eor sequence.
2046 // It only works for logical shifts because the bits shifted in are all
2047 // zeroes.
2048 // To shift a single byte right, it produces code like this:
2049 // swap r0
2050 // andi r0, 0x0f
2051 // For a two-byte (16-bit) shift, it adds the following instructions to shift
2052 // the upper byte into the lower byte:
2053 // swap r1
2054 // eor r0, r1
2055 // andi r1, 0x0f
2056 // eor r0, r1
2057 // For bigger shifts, it repeats the above sequence. For example, for a 3-byte
2058 // (24-bit) shift it adds:
2059 // swap r2
2060 // eor r1, r2
2061 // andi r2, 0x0f
2062 // eor r1, r2
2063 if (!ArithmeticShift && ShiftAmt >= 4) {
2064 Register Prev = 0;
2065 for (size_t I = 0; I < Regs.size(); I++) {
2066 size_t Idx = ShiftLeft ? I : Regs.size() - I - 1;
2067 Register SwapReg = MRI.createVirtualRegister(RegClass: &AVR::LD8RegClass);
2068 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::SWAPRd), DestReg: SwapReg)
2069 .addReg(RegNo: Regs[Idx].first, Flags: {}, SubReg: Regs[Idx].second);
2070 if (I != 0) {
2071 Register R = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
2072 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::EORRdRr), DestReg: R)
2073 .addReg(RegNo: Prev)
2074 .addReg(RegNo: SwapReg);
2075 Prev = R;
2076 }
2077 Register AndReg = MRI.createVirtualRegister(RegClass: &AVR::LD8RegClass);
2078 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::ANDIRdK), DestReg: AndReg)
2079 .addReg(RegNo: SwapReg)
2080 .addImm(Val: ShiftLeft ? 0xf0 : 0x0f);
2081 if (I != 0) {
2082 Register R = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
2083 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::EORRdRr), DestReg: R)
2084 .addReg(RegNo: Prev)
2085 .addReg(RegNo: AndReg);
2086 size_t PrevIdx = ShiftLeft ? Idx - 1 : Idx + 1;
2087 Regs[PrevIdx] = std::pair(R, 0);
2088 }
2089 Prev = AndReg;
2090 Regs[Idx] = std::pair(AndReg, 0);
2091 }
2092 ShiftAmt -= 4;
2093 }
2094
2095 // Shift by one. This is the fallback that always works, and the shift
2096 // operation that is used for 1, 2, and 3 bit shifts.
2097 while (ShiftLeft && ShiftAmt) {
2098 // Shift one to the left.
2099 for (ssize_t I = Regs.size() - 1; I >= 0; I--) {
2100 Register Out = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
2101 Register In = Regs[I].first;
2102 Register InSubreg = Regs[I].second;
2103 if (I == (ssize_t)Regs.size() - 1) { // first iteration
2104 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::ADDRdRr), DestReg: Out)
2105 .addReg(RegNo: In, Flags: {}, SubReg: InSubreg)
2106 .addReg(RegNo: In, Flags: {}, SubReg: InSubreg);
2107 } else {
2108 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::ADCRdRr), DestReg: Out)
2109 .addReg(RegNo: In, Flags: {}, SubReg: InSubreg)
2110 .addReg(RegNo: In, Flags: {}, SubReg: InSubreg);
2111 }
2112 Regs[I] = std::pair(Out, 0);
2113 }
2114 ShiftAmt--;
2115 }
2116 while (!ShiftLeft && ShiftAmt) {
2117 // Shift one to the right.
2118 for (size_t I = 0; I < Regs.size(); I++) {
2119 Register Out = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
2120 Register In = Regs[I].first;
2121 Register InSubreg = Regs[I].second;
2122 if (I == 0) {
2123 unsigned Opc = ArithmeticShift ? AVR::ASRRd : AVR::LSRRd;
2124 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: Opc), DestReg: Out).addReg(RegNo: In, Flags: {}, SubReg: InSubreg);
2125 } else {
2126 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::RORRd), DestReg: Out).addReg(RegNo: In, Flags: {}, SubReg: InSubreg);
2127 }
2128 Regs[I] = std::pair(Out, 0);
2129 }
2130 ShiftAmt--;
2131 }
2132
2133 if (ShiftAmt != 0) {
2134 llvm_unreachable("don't know how to shift!"); // sanity check
2135 }
2136}
2137
2138// Do a wide (32-bit) shift.
2139MachineBasicBlock *
2140AVRTargetLowering::insertWideShift(MachineInstr &MI,
2141 MachineBasicBlock *BB) const {
2142 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2143 const DebugLoc &dl = MI.getDebugLoc();
2144
2145 // How much to shift to the right (meaning: a negative number indicates a left
2146 // shift).
2147 int64_t ShiftAmt = MI.getOperand(i: 4).getImm();
2148 ISD::NodeType Opc;
2149 switch (MI.getOpcode()) {
2150 case AVR::Lsl32:
2151 Opc = ISD::SHL;
2152 break;
2153 case AVR::Lsr32:
2154 Opc = ISD::SRL;
2155 break;
2156 case AVR::Asr32:
2157 Opc = ISD::SRA;
2158 break;
2159 }
2160
2161 // Read the input registers, with the most significant register at index 0.
2162 std::array<std::pair<Register, int>, 4> Registers = {
2163 std::pair(MI.getOperand(i: 3).getReg(), AVR::sub_hi),
2164 std::pair(MI.getOperand(i: 3).getReg(), AVR::sub_lo),
2165 std::pair(MI.getOperand(i: 2).getReg(), AVR::sub_hi),
2166 std::pair(MI.getOperand(i: 2).getReg(), AVR::sub_lo),
2167 };
2168
2169 // Do the shift. The registers are modified in-place.
2170 insertMultibyteShift(MI, BB, Regs: Registers, Opc, ShiftAmt);
2171
2172 // Combine the 8-bit registers into 16-bit register pairs.
2173 // This done either from LSB to MSB or from MSB to LSB, depending on the
2174 // shift. It's an optimization so that the register allocator will use the
2175 // fewest movs possible (which order we use isn't a correctness issue, just an
2176 // optimization issue).
2177 // - lsl prefers starting from the most significant byte (2nd case).
2178 // - lshr prefers starting from the least significant byte (1st case).
2179 // - for ashr it depends on the number of shifted bytes.
2180 // Some shift operations still don't get the most optimal mov sequences even
2181 // with this distinction. TODO: figure out why and try to fix it (but we're
2182 // already equal to or faster than avr-gcc in all cases except ashr 8).
2183 if (Opc != ISD::SHL &&
2184 (Opc != ISD::SRA || (ShiftAmt < 16 || ShiftAmt >= 22))) {
2185 // Use the resulting registers starting with the least significant byte.
2186 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::REG_SEQUENCE), DestReg: MI.getOperand(i: 0).getReg())
2187 .addReg(RegNo: Registers[3].first, Flags: {}, SubReg: Registers[3].second)
2188 .addImm(Val: AVR::sub_lo)
2189 .addReg(RegNo: Registers[2].first, Flags: {}, SubReg: Registers[2].second)
2190 .addImm(Val: AVR::sub_hi);
2191 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::REG_SEQUENCE), DestReg: MI.getOperand(i: 1).getReg())
2192 .addReg(RegNo: Registers[1].first, Flags: {}, SubReg: Registers[1].second)
2193 .addImm(Val: AVR::sub_lo)
2194 .addReg(RegNo: Registers[0].first, Flags: {}, SubReg: Registers[0].second)
2195 .addImm(Val: AVR::sub_hi);
2196 } else {
2197 // Use the resulting registers starting with the most significant byte.
2198 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::REG_SEQUENCE), DestReg: MI.getOperand(i: 1).getReg())
2199 .addReg(RegNo: Registers[0].first, Flags: {}, SubReg: Registers[0].second)
2200 .addImm(Val: AVR::sub_hi)
2201 .addReg(RegNo: Registers[1].first, Flags: {}, SubReg: Registers[1].second)
2202 .addImm(Val: AVR::sub_lo);
2203 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::REG_SEQUENCE), DestReg: MI.getOperand(i: 0).getReg())
2204 .addReg(RegNo: Registers[2].first, Flags: {}, SubReg: Registers[2].second)
2205 .addImm(Val: AVR::sub_hi)
2206 .addReg(RegNo: Registers[3].first, Flags: {}, SubReg: Registers[3].second)
2207 .addImm(Val: AVR::sub_lo);
2208 }
2209
2210 // Remove the pseudo instruction.
2211 MI.eraseFromParent();
2212 return BB;
2213}
2214
2215static bool isCopyMulResult(MachineBasicBlock::iterator const &I) {
2216 if (I->getOpcode() == AVR::COPY) {
2217 Register SrcReg = I->getOperand(i: 1).getReg();
2218 return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
2219 }
2220
2221 return false;
2222}
2223
2224// The mul instructions wreak havock on our zero_reg R1. We need to clear it
2225// after the result has been evacuated. This is probably not the best way to do
2226// it, but it works for now.
2227MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
2228 MachineBasicBlock *BB) const {
2229 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2230 MachineBasicBlock::iterator I(MI);
2231 ++I; // in any case insert *after* the mul instruction
2232 if (isCopyMulResult(I))
2233 ++I;
2234 if (isCopyMulResult(I))
2235 ++I;
2236 BuildMI(BB&: *BB, I, MIMD: MI.getDebugLoc(), MCID: TII.get(Opcode: AVR::EORRdRr), DestReg: AVR::R1)
2237 .addReg(RegNo: AVR::R1)
2238 .addReg(RegNo: AVR::R1);
2239 return BB;
2240}
2241
2242// Insert a read from the zero register.
2243MachineBasicBlock *
2244AVRTargetLowering::insertCopyZero(MachineInstr &MI,
2245 MachineBasicBlock *BB) const {
2246 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2247 MachineBasicBlock::iterator I(MI);
2248 BuildMI(BB&: *BB, I, MIMD: MI.getDebugLoc(), MCID: TII.get(Opcode: AVR::COPY))
2249 .add(MO: MI.getOperand(i: 0))
2250 .addReg(RegNo: Subtarget.getZeroRegister());
2251 MI.eraseFromParent();
2252 return BB;
2253}
2254
2255// Lower atomicrmw operation to disable interrupts, do operation, and restore
2256// interrupts. This works because all AVR microcontrollers are single core.
2257MachineBasicBlock *AVRTargetLowering::insertAtomicArithmeticOp(
2258 MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode, int Width) const {
2259 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
2260 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2261 MachineBasicBlock::iterator I(MI);
2262 DebugLoc dl = MI.getDebugLoc();
2263
2264 // Example instruction sequence, for an atomic 8-bit add:
2265 // ldi r25, 5
2266 // in r0, SREG
2267 // cli
2268 // ld r24, X
2269 // add r25, r24
2270 // st X, r25
2271 // out SREG, r0
2272
2273 const TargetRegisterClass *RC =
2274 (Width == 8) ? &AVR::GPR8RegClass : &AVR::DREGSNOZRegClass;
2275 unsigned LoadOpcode = (Width == 8) ? AVR::LDRdPtr : AVR::LDWRdPtr;
2276 unsigned StoreOpcode = (Width == 8) ? AVR::STPtrRr : AVR::STWPtrRr;
2277
2278 // Disable interrupts.
2279 BuildMI(BB&: *BB, I, MIMD: dl, MCID: TII.get(Opcode: AVR::INRdA), DestReg: Subtarget.getTmpRegister())
2280 .addImm(Val: Subtarget.getIORegSREG());
2281 BuildMI(BB&: *BB, I, MIMD: dl, MCID: TII.get(Opcode: AVR::BCLRs)).addImm(Val: 7);
2282
2283 // Load the original value.
2284 BuildMI(BB&: *BB, I, MIMD: dl, MCID: TII.get(Opcode: LoadOpcode), DestReg: MI.getOperand(i: 0).getReg())
2285 .add(MO: MI.getOperand(i: 1));
2286
2287 // Do the arithmetic operation.
2288 Register Result = MRI.createVirtualRegister(RegClass: RC);
2289 BuildMI(BB&: *BB, I, MIMD: dl, MCID: TII.get(Opcode), DestReg: Result)
2290 .addReg(RegNo: MI.getOperand(i: 0).getReg())
2291 .add(MO: MI.getOperand(i: 2));
2292
2293 // Store the result.
2294 BuildMI(BB&: *BB, I, MIMD: dl, MCID: TII.get(Opcode: StoreOpcode))
2295 .add(MO: MI.getOperand(i: 1))
2296 .addReg(RegNo: Result);
2297
2298 // Restore interrupts.
2299 BuildMI(BB&: *BB, I, MIMD: dl, MCID: TII.get(Opcode: AVR::OUTARr))
2300 .addImm(Val: Subtarget.getIORegSREG())
2301 .addReg(RegNo: Subtarget.getTmpRegister());
2302
2303 // Remove the pseudo instruction.
2304 MI.eraseFromParent();
2305 return BB;
2306}
2307
2308MachineBasicBlock *
2309AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
2310 MachineBasicBlock *MBB) const {
2311 int Opc = MI.getOpcode();
2312 const AVRSubtarget &STI = MBB->getParent()->getSubtarget<AVRSubtarget>();
2313
2314 // Pseudo shift instructions with a non constant shift amount are expanded
2315 // into a loop.
2316 switch (Opc) {
2317 case AVR::Lsl8:
2318 case AVR::Lsl16:
2319 case AVR::Lsr8:
2320 case AVR::Lsr16:
2321 case AVR::Rol8:
2322 case AVR::Rol16:
2323 case AVR::Ror8:
2324 case AVR::Ror16:
2325 case AVR::Asr8:
2326 case AVR::Asr16:
2327 return insertShift(MI, BB: MBB, Tiny: STI.hasTinyEncoding());
2328 case AVR::Lsl32:
2329 case AVR::Lsr32:
2330 case AVR::Asr32:
2331 return insertWideShift(MI, BB: MBB);
2332 case AVR::MULRdRr:
2333 case AVR::MULSRdRr:
2334 return insertMul(MI, BB: MBB);
2335 case AVR::CopyZero:
2336 return insertCopyZero(MI, BB: MBB);
2337 case AVR::AtomicLoadAdd8:
2338 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::ADDRdRr, Width: 8);
2339 case AVR::AtomicLoadAdd16:
2340 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::ADDWRdRr, Width: 16);
2341 case AVR::AtomicLoadSub8:
2342 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::SUBRdRr, Width: 8);
2343 case AVR::AtomicLoadSub16:
2344 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::SUBWRdRr, Width: 16);
2345 case AVR::AtomicLoadAnd8:
2346 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::ANDRdRr, Width: 8);
2347 case AVR::AtomicLoadAnd16:
2348 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::ANDWRdRr, Width: 16);
2349 case AVR::AtomicLoadOr8:
2350 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::ORRdRr, Width: 8);
2351 case AVR::AtomicLoadOr16:
2352 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::ORWRdRr, Width: 16);
2353 case AVR::AtomicLoadXor8:
2354 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::EORRdRr, Width: 8);
2355 case AVR::AtomicLoadXor16:
2356 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::EORWRdRr, Width: 16);
2357 }
2358
2359 assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&
2360 "Unexpected instr type to insert");
2361
2362 const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
2363 ->getParent()
2364 ->getSubtarget()
2365 .getInstrInfo();
2366 DebugLoc dl = MI.getDebugLoc();
2367
2368 // To "insert" a SELECT instruction, we insert the diamond
2369 // control-flow pattern. The incoming instruction knows the
2370 // destination vreg to set, the condition code register to branch
2371 // on, the true/false values to select between, and a branch opcode
2372 // to use.
2373
2374 MachineFunction *MF = MBB->getParent();
2375 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
2376 MachineBasicBlock *FallThrough = MBB->getFallThrough();
2377
2378 // If the current basic block falls through to another basic block,
2379 // we must insert an unconditional branch to the fallthrough destination
2380 // if we are to insert basic blocks at the prior fallthrough point.
2381 if (FallThrough != nullptr) {
2382 BuildMI(BB: MBB, MIMD: dl, MCID: TII.get(Opcode: AVR::RJMPk)).addMBB(MBB: FallThrough);
2383 }
2384
2385 MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(BB: LLVM_BB);
2386 MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(BB: LLVM_BB);
2387
2388 MachineFunction::iterator I;
2389 for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I)
2390 ;
2391 if (I != MF->end())
2392 ++I;
2393 MF->insert(MBBI: I, MBB: trueMBB);
2394 MF->insert(MBBI: I, MBB: falseMBB);
2395
2396 // Set the call frame size on entry to the new basic blocks.
2397 unsigned CallFrameSize = TII.getCallFrameSizeAt(MI);
2398 trueMBB->setCallFrameSize(CallFrameSize);
2399 falseMBB->setCallFrameSize(CallFrameSize);
2400
2401 // Transfer remaining instructions and all successors of the current
2402 // block to the block which will contain the Phi node for the
2403 // select.
2404 trueMBB->splice(Where: trueMBB->begin(), Other: MBB,
2405 From: std::next(x: MachineBasicBlock::iterator(MI)), To: MBB->end());
2406 trueMBB->transferSuccessorsAndUpdatePHIs(FromMBB: MBB);
2407
2408 AVRCC::CondCodes CC = (AVRCC::CondCodes)MI.getOperand(i: 3).getImm();
2409 BuildMI(BB: MBB, MIMD: dl, MCID: TII.getBrCond(CC)).addMBB(MBB: trueMBB);
2410 BuildMI(BB: MBB, MIMD: dl, MCID: TII.get(Opcode: AVR::RJMPk)).addMBB(MBB: falseMBB);
2411 MBB->addSuccessor(Succ: falseMBB);
2412 MBB->addSuccessor(Succ: trueMBB);
2413
2414 // Unconditionally flow back to the true block
2415 BuildMI(BB: falseMBB, MIMD: dl, MCID: TII.get(Opcode: AVR::RJMPk)).addMBB(MBB: trueMBB);
2416 falseMBB->addSuccessor(Succ: trueMBB);
2417
2418 // Set up the Phi node to determine where we came from
2419 BuildMI(BB&: *trueMBB, I: trueMBB->begin(), MIMD: dl, MCID: TII.get(Opcode: AVR::PHI),
2420 DestReg: MI.getOperand(i: 0).getReg())
2421 .addReg(RegNo: MI.getOperand(i: 1).getReg())
2422 .addMBB(MBB)
2423 .addReg(RegNo: MI.getOperand(i: 2).getReg())
2424 .addMBB(MBB: falseMBB);
2425
2426 MI.eraseFromParent(); // The pseudo instruction is gone now.
2427 return trueMBB;
2428}
2429
2430//===----------------------------------------------------------------------===//
2431// Inline Asm Support
2432//===----------------------------------------------------------------------===//
2433
2434AVRTargetLowering::ConstraintType
2435AVRTargetLowering::getConstraintType(StringRef Constraint) const {
2436 if (Constraint.size() == 1) {
2437 // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
2438 switch (Constraint[0]) {
2439 default:
2440 break;
2441 case 'a': // Simple upper registers
2442 case 'b': // Base pointer registers pairs
2443 case 'd': // Upper register
2444 case 'l': // Lower registers
2445 case 'e': // Pointer register pairs
2446 case 'q': // Stack pointer register
2447 case 'r': // Any register
2448 case 'w': // Special upper register pairs
2449 return C_RegisterClass;
2450 case 't': // Temporary register
2451 case 'x':
2452 case 'X': // Pointer register pair X
2453 case 'y':
2454 case 'Y': // Pointer register pair Y
2455 case 'z':
2456 case 'Z': // Pointer register pair Z
2457 return C_Register;
2458 case 'Q': // A memory address based on Y or Z pointer with displacement.
2459 return C_Memory;
2460 case 'G': // Floating point constant
2461 case 'I': // 6-bit positive integer constant
2462 case 'J': // 6-bit negative integer constant
2463 case 'K': // Integer constant (Range: 2)
2464 case 'L': // Integer constant (Range: 0)
2465 case 'M': // 8-bit integer constant
2466 case 'N': // Integer constant (Range: -1)
2467 case 'O': // Integer constant (Range: 8, 16, 24)
2468 case 'P': // Integer constant (Range: 1)
2469 case 'R': // Integer constant (Range: -6 to 5)x
2470 return C_Immediate;
2471 }
2472 }
2473
2474 return TargetLowering::getConstraintType(Constraint);
2475}
2476
2477InlineAsm::ConstraintCode
2478AVRTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
2479 // Not sure if this is actually the right thing to do, but we got to do
2480 // *something* [agnat]
2481 switch (ConstraintCode[0]) {
2482 case 'Q':
2483 return InlineAsm::ConstraintCode::Q;
2484 }
2485 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
2486}
2487
2488AVRTargetLowering::ConstraintWeight
2489AVRTargetLowering::getSingleConstraintMatchWeight(
2490 AsmOperandInfo &info, const char *constraint) const {
2491 ConstraintWeight weight = CW_Invalid;
2492 Value *CallOperandVal = info.CallOperandVal;
2493
2494 // If we don't have a value, we can't do a match,
2495 // but allow it at the lowest weight.
2496 // (this behaviour has been copied from the ARM backend)
2497 if (!CallOperandVal) {
2498 return CW_Default;
2499 }
2500
2501 // Look at the constraint type.
2502 switch (*constraint) {
2503 default:
2504 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
2505 break;
2506 case 'd':
2507 case 'r':
2508 case 'l':
2509 weight = CW_Register;
2510 break;
2511 case 'a':
2512 case 'b':
2513 case 'e':
2514 case 'q':
2515 case 't':
2516 case 'w':
2517 case 'x':
2518 case 'X':
2519 case 'y':
2520 case 'Y':
2521 case 'z':
2522 case 'Z':
2523 weight = CW_SpecificReg;
2524 break;
2525 case 'G':
2526 if (const ConstantFP *C = dyn_cast<ConstantFP>(Val: CallOperandVal)) {
2527 if (C->isZero()) {
2528 weight = CW_Constant;
2529 }
2530 }
2531 break;
2532 case 'I':
2533 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2534 if (isUInt<6>(x: C->getZExtValue())) {
2535 weight = CW_Constant;
2536 }
2537 }
2538 break;
2539 case 'J':
2540 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2541 if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) {
2542 weight = CW_Constant;
2543 }
2544 }
2545 break;
2546 case 'K':
2547 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2548 if (C->getZExtValue() == 2) {
2549 weight = CW_Constant;
2550 }
2551 }
2552 break;
2553 case 'L':
2554 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2555 if (C->getZExtValue() == 0) {
2556 weight = CW_Constant;
2557 }
2558 }
2559 break;
2560 case 'M':
2561 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2562 if (isUInt<8>(x: C->getZExtValue())) {
2563 weight = CW_Constant;
2564 }
2565 }
2566 break;
2567 case 'N':
2568 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2569 if (C->getSExtValue() == -1) {
2570 weight = CW_Constant;
2571 }
2572 }
2573 break;
2574 case 'O':
2575 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2576 if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) ||
2577 (C->getZExtValue() == 24)) {
2578 weight = CW_Constant;
2579 }
2580 }
2581 break;
2582 case 'P':
2583 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2584 if (C->getZExtValue() == 1) {
2585 weight = CW_Constant;
2586 }
2587 }
2588 break;
2589 case 'R':
2590 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2591 if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) {
2592 weight = CW_Constant;
2593 }
2594 }
2595 break;
2596 case 'Q':
2597 weight = CW_Memory;
2598 break;
2599 }
2600
2601 return weight;
2602}
2603
2604std::pair<unsigned, const TargetRegisterClass *>
2605AVRTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2606 StringRef Constraint,
2607 MVT VT) const {
2608 if (Constraint.size() == 1) {
2609 switch (Constraint[0]) {
2610 case 'a': // Simple upper registers r16..r23.
2611 if (VT == MVT::i8)
2612 return std::make_pair(x: 0U, y: &AVR::LD8loRegClass);
2613 else if (VT == MVT::i16)
2614 return std::make_pair(x: 0U, y: &AVR::DREGSLD8loRegClass);
2615 break;
2616 case 'b': // Base pointer registers: y, z.
2617 if (VT == MVT::i8 || VT == MVT::i16)
2618 return std::make_pair(x: 0U, y: &AVR::PTRDISPREGSRegClass);
2619 break;
2620 case 'd': // Upper registers r16..r31.
2621 if (VT == MVT::i8)
2622 return std::make_pair(x: 0U, y: &AVR::LD8RegClass);
2623 else if (VT == MVT::i16)
2624 return std::make_pair(x: 0U, y: &AVR::DLDREGSRegClass);
2625 break;
2626 case 'l': // Lower registers r0..r15.
2627 if (VT == MVT::i8)
2628 return std::make_pair(x: 0U, y: &AVR::GPR8loRegClass);
2629 else if (VT == MVT::i16)
2630 return std::make_pair(x: 0U, y: &AVR::DREGSloRegClass);
2631 break;
2632 case 'e': // Pointer register pairs: x, y, z.
2633 if (VT == MVT::i8 || VT == MVT::i16)
2634 return std::make_pair(x: 0U, y: &AVR::PTRREGSRegClass);
2635 break;
2636 case 'q': // Stack pointer register: SPH:SPL.
2637 return std::make_pair(x: 0U, y: &AVR::GPRSPRegClass);
2638 case 'r': // Any register: r0..r31.
2639 if (VT == MVT::i8)
2640 return std::make_pair(x: 0U, y: &AVR::GPR8RegClass);
2641 else if (VT == MVT::i16)
2642 return std::make_pair(x: 0U, y: &AVR::DREGSRegClass);
2643 break;
2644 case 't': // Temporary register: r0.
2645 if (VT == MVT::i8)
2646 return std::make_pair(x: unsigned(Subtarget.getTmpRegister()),
2647 y: &AVR::GPR8RegClass);
2648 break;
2649 case 'w': // Special upper register pairs: r24, r26, r28, r30.
2650 if (VT == MVT::i8 || VT == MVT::i16)
2651 return std::make_pair(x: 0U, y: &AVR::IWREGSRegClass);
2652 break;
2653 case 'x': // Pointer register pair X: r27:r26.
2654 case 'X':
2655 if (VT == MVT::i8 || VT == MVT::i16)
2656 return std::make_pair(x: unsigned(AVR::R27R26), y: &AVR::PTRREGSRegClass);
2657 break;
2658 case 'y': // Pointer register pair Y: r29:r28.
2659 case 'Y':
2660 if (VT == MVT::i8 || VT == MVT::i16)
2661 return std::make_pair(x: unsigned(AVR::R29R28), y: &AVR::PTRREGSRegClass);
2662 break;
2663 case 'z': // Pointer register pair Z: r31:r30.
2664 case 'Z':
2665 if (VT == MVT::i8 || VT == MVT::i16)
2666 return std::make_pair(x: unsigned(AVR::R31R30), y: &AVR::PTRREGSRegClass);
2667 break;
2668 default:
2669 break;
2670 }
2671 }
2672
2673 return TargetLowering::getRegForInlineAsmConstraint(
2674 TRI: Subtarget.getRegisterInfo(), Constraint, VT);
2675}
2676
2677void AVRTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2678 StringRef Constraint,
2679 std::vector<SDValue> &Ops,
2680 SelectionDAG &DAG) const {
2681 SDValue Result;
2682 SDLoc DL(Op);
2683 EVT Ty = Op.getValueType();
2684
2685 // Currently only support length 1 constraints.
2686 if (Constraint.size() != 1) {
2687 return;
2688 }
2689
2690 char ConstraintLetter = Constraint[0];
2691 switch (ConstraintLetter) {
2692 default:
2693 break;
2694 // Deal with integers first:
2695 case 'I':
2696 case 'J':
2697 case 'K':
2698 case 'L':
2699 case 'M':
2700 case 'N':
2701 case 'O':
2702 case 'P':
2703 case 'R': {
2704 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: Op);
2705 if (!C) {
2706 return;
2707 }
2708
2709 int64_t CVal64 = C->getSExtValue();
2710 uint64_t CUVal64 = C->getZExtValue();
2711 switch (ConstraintLetter) {
2712 case 'I': // 0..63
2713 if (!isUInt<6>(x: CUVal64))
2714 return;
2715 Result = DAG.getTargetConstant(Val: CUVal64, DL, VT: Ty);
2716 break;
2717 case 'J': // -63..0
2718 if (CVal64 < -63 || CVal64 > 0)
2719 return;
2720 Result = DAG.getTargetConstant(Val: CVal64, DL, VT: Ty);
2721 break;
2722 case 'K': // 2
2723 if (CUVal64 != 2)
2724 return;
2725 Result = DAG.getTargetConstant(Val: CUVal64, DL, VT: Ty);
2726 break;
2727 case 'L': // 0
2728 if (CUVal64 != 0)
2729 return;
2730 Result = DAG.getTargetConstant(Val: CUVal64, DL, VT: Ty);
2731 break;
2732 case 'M': // 0..255
2733 if (!isUInt<8>(x: CUVal64))
2734 return;
2735 // i8 type may be printed as a negative number,
2736 // e.g. 254 would be printed as -2,
2737 // so we force it to i16 at least.
2738 if (Ty.getSimpleVT() == MVT::i8) {
2739 Ty = MVT::i16;
2740 }
2741 Result = DAG.getTargetConstant(Val: CUVal64, DL, VT: Ty);
2742 break;
2743 case 'N': // -1
2744 if (CVal64 != -1)
2745 return;
2746 Result = DAG.getTargetConstant(Val: CVal64, DL, VT: Ty);
2747 break;
2748 case 'O': // 8, 16, 24
2749 if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
2750 return;
2751 Result = DAG.getTargetConstant(Val: CUVal64, DL, VT: Ty);
2752 break;
2753 case 'P': // 1
2754 if (CUVal64 != 1)
2755 return;
2756 Result = DAG.getTargetConstant(Val: CUVal64, DL, VT: Ty);
2757 break;
2758 case 'R': // -6..5
2759 if (CVal64 < -6 || CVal64 > 5)
2760 return;
2761 Result = DAG.getTargetConstant(Val: CVal64, DL, VT: Ty);
2762 break;
2763 }
2764
2765 break;
2766 }
2767 case 'G':
2768 const ConstantFPSDNode *FC = dyn_cast<ConstantFPSDNode>(Val&: Op);
2769 if (!FC || !FC->isZero())
2770 return;
2771 // Soften float to i8 0
2772 Result = DAG.getTargetConstant(Val: 0, DL, VT: MVT::i8);
2773 break;
2774 }
2775
2776 if (Result.getNode()) {
2777 Ops.push_back(x: Result);
2778 return;
2779 }
2780
2781 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2782}
2783
2784Register AVRTargetLowering::getRegisterByName(const char *RegName, LLT VT,
2785 const MachineFunction &MF) const {
2786 Register Reg;
2787
2788 if (VT == LLT::scalar(SizeInBits: 8)) {
2789 Reg = StringSwitch<unsigned>(RegName)
2790 .Case(S: "r0", Value: AVR::R0)
2791 .Case(S: "r1", Value: AVR::R1)
2792 .Default(Value: 0);
2793 } else {
2794 Reg = StringSwitch<unsigned>(RegName)
2795 .Case(S: "r0", Value: AVR::R1R0)
2796 .Case(S: "sp", Value: AVR::SP)
2797 .Default(Value: 0);
2798 }
2799
2800 if (Reg)
2801 return Reg;
2802
2803 report_fatal_error(
2804 reason: Twine("Invalid register name \"" + StringRef(RegName) + "\"."));
2805}
2806
2807} // end of namespace llvm
2808