1//===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that AVR uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AVRISelLowering.h"
15
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/StringSwitch.h"
18#include "llvm/CodeGen/CallingConvLower.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/SelectionDAG.h"
23#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
24#include "llvm/IR/Function.h"
25#include "llvm/Support/ErrorHandling.h"
26
27#include "AVR.h"
28#include "AVRMachineFunctionInfo.h"
29#include "AVRSubtarget.h"
30#include "AVRTargetMachine.h"
31#include "MCTargetDesc/AVRMCTargetDesc.h"
32
33namespace llvm {
34
35AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM,
36 const AVRSubtarget &STI)
37 : TargetLowering(TM, STI), Subtarget(STI) {
38 // Set up the register classes.
39 addRegisterClass(VT: MVT::i8, RC: &AVR::GPR8RegClass);
40 addRegisterClass(VT: MVT::i16, RC: &AVR::DREGSRegClass);
41
42 // Compute derived properties from the register classes.
43 computeRegisterProperties(TRI: Subtarget.getRegisterInfo());
44
45 setBooleanContents(ZeroOrOneBooleanContent);
46 setBooleanVectorContents(ZeroOrOneBooleanContent);
47 setSchedulingPreference(Sched::RegPressure);
48 setStackPointerRegisterToSaveRestore(AVR::SP);
49 setSupportsUnalignedAtomics(true);
50
51 setOperationAction(Op: ISD::GlobalAddress, VT: MVT::i16, Action: Custom);
52 setOperationAction(Op: ISD::BlockAddress, VT: MVT::i16, Action: Custom);
53
54 setOperationAction(Op: ISD::STACKSAVE, VT: MVT::Other, Action: Expand);
55 setOperationAction(Op: ISD::STACKRESTORE, VT: MVT::Other, Action: Expand);
56 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: MVT::i8, Action: Expand);
57 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: MVT::i16, Action: Expand);
58
59 setOperationAction(Op: ISD::INLINEASM, VT: MVT::Other, Action: Custom);
60
61 for (MVT VT : MVT::integer_valuetypes()) {
62 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
63 setLoadExtAction(ExtType: N, ValVT: VT, MemVT: MVT::i1, Action: Promote);
64 setLoadExtAction(ExtType: N, ValVT: VT, MemVT: MVT::i8, Action: Expand);
65 }
66 }
67
68 setTruncStoreAction(ValVT: MVT::i16, MemVT: MVT::i8, Action: Expand);
69
70 for (MVT VT : MVT::integer_valuetypes()) {
71 setOperationAction(Op: ISD::ADDC, VT, Action: Legal);
72 setOperationAction(Op: ISD::SUBC, VT, Action: Legal);
73 setOperationAction(Op: ISD::ADDE, VT, Action: Legal);
74 setOperationAction(Op: ISD::SUBE, VT, Action: Legal);
75 }
76
77 // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types
78 // revert into a sub since we don't have an add with immediate instruction.
79 setOperationAction(Op: ISD::ADD, VT: MVT::i32, Action: Custom);
80 setOperationAction(Op: ISD::ADD, VT: MVT::i64, Action: Custom);
81
82 // our shift instructions are only able to shift 1 bit at a time, so handle
83 // this in a custom way.
84 setOperationAction(Op: ISD::SRA, VT: MVT::i8, Action: Custom);
85 setOperationAction(Op: ISD::SHL, VT: MVT::i8, Action: Custom);
86 setOperationAction(Op: ISD::SRL, VT: MVT::i8, Action: Custom);
87 setOperationAction(Op: ISD::SRA, VT: MVT::i16, Action: Custom);
88 setOperationAction(Op: ISD::SHL, VT: MVT::i16, Action: Custom);
89 setOperationAction(Op: ISD::SRL, VT: MVT::i16, Action: Custom);
90 setOperationAction(Op: ISD::SRA, VT: MVT::i32, Action: Custom);
91 setOperationAction(Op: ISD::SHL, VT: MVT::i32, Action: Custom);
92 setOperationAction(Op: ISD::SRL, VT: MVT::i32, Action: Custom);
93 setOperationAction(Op: ISD::SHL_PARTS, VT: MVT::i16, Action: Expand);
94 setOperationAction(Op: ISD::SRA_PARTS, VT: MVT::i16, Action: Expand);
95 setOperationAction(Op: ISD::SRL_PARTS, VT: MVT::i16, Action: Expand);
96
97 setOperationAction(Op: ISD::ROTL, VT: MVT::i8, Action: Custom);
98 setOperationAction(Op: ISD::ROTL, VT: MVT::i16, Action: Expand);
99 setOperationAction(Op: ISD::ROTR, VT: MVT::i8, Action: Custom);
100 setOperationAction(Op: ISD::ROTR, VT: MVT::i16, Action: Expand);
101
102 setOperationAction(Op: ISD::BR_CC, VT: MVT::i8, Action: Custom);
103 setOperationAction(Op: ISD::BR_CC, VT: MVT::i16, Action: Custom);
104 setOperationAction(Op: ISD::BR_CC, VT: MVT::i32, Action: Custom);
105 setOperationAction(Op: ISD::BR_CC, VT: MVT::i64, Action: Custom);
106 setOperationAction(Op: ISD::BRCOND, VT: MVT::Other, Action: Expand);
107
108 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i8, Action: Custom);
109 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i16, Action: Custom);
110 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i32, Action: Expand);
111 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i64, Action: Expand);
112 setOperationAction(Op: ISD::SETCC, VT: MVT::i8, Action: Custom);
113 setOperationAction(Op: ISD::SETCC, VT: MVT::i16, Action: Custom);
114 setOperationAction(Op: ISD::SETCC, VT: MVT::i32, Action: Custom);
115 setOperationAction(Op: ISD::SETCC, VT: MVT::i64, Action: Custom);
116 setOperationAction(Op: ISD::SELECT, VT: MVT::i8, Action: Expand);
117 setOperationAction(Op: ISD::SELECT, VT: MVT::i16, Action: Expand);
118
119 setOperationAction(Op: ISD::BSWAP, VT: MVT::i16, Action: Expand);
120
121 // Add support for postincrement and predecrement load/stores.
122 setIndexedLoadAction(IdxModes: ISD::POST_INC, VT: MVT::i8, Action: Legal);
123 setIndexedLoadAction(IdxModes: ISD::POST_INC, VT: MVT::i16, Action: Legal);
124 setIndexedLoadAction(IdxModes: ISD::PRE_DEC, VT: MVT::i8, Action: Legal);
125 setIndexedLoadAction(IdxModes: ISD::PRE_DEC, VT: MVT::i16, Action: Legal);
126 setIndexedStoreAction(IdxModes: ISD::POST_INC, VT: MVT::i8, Action: Legal);
127 setIndexedStoreAction(IdxModes: ISD::POST_INC, VT: MVT::i16, Action: Legal);
128 setIndexedStoreAction(IdxModes: ISD::PRE_DEC, VT: MVT::i8, Action: Legal);
129 setIndexedStoreAction(IdxModes: ISD::PRE_DEC, VT: MVT::i16, Action: Legal);
130
131 setOperationAction(Op: ISD::BR_JT, VT: MVT::Other, Action: Expand);
132
133 setOperationAction(Op: ISD::VASTART, VT: MVT::Other, Action: Custom);
134 setOperationAction(Op: ISD::VAEND, VT: MVT::Other, Action: Expand);
135 setOperationAction(Op: ISD::VAARG, VT: MVT::Other, Action: Expand);
136 setOperationAction(Op: ISD::VACOPY, VT: MVT::Other, Action: Expand);
137
138 // Atomic operations which must be lowered to rtlib calls
139 for (MVT VT : MVT::integer_valuetypes()) {
140 setOperationAction(Op: ISD::ATOMIC_SWAP, VT, Action: Expand);
141 setOperationAction(Op: ISD::ATOMIC_CMP_SWAP, VT, Action: Expand);
142 setOperationAction(Op: ISD::ATOMIC_LOAD_NAND, VT, Action: Expand);
143 setOperationAction(Op: ISD::ATOMIC_LOAD_MAX, VT, Action: Expand);
144 setOperationAction(Op: ISD::ATOMIC_LOAD_MIN, VT, Action: Expand);
145 setOperationAction(Op: ISD::ATOMIC_LOAD_UMAX, VT, Action: Expand);
146 setOperationAction(Op: ISD::ATOMIC_LOAD_UMIN, VT, Action: Expand);
147 }
148
149 // Division/remainder
150 setOperationAction(Op: ISD::UDIV, VT: MVT::i8, Action: Expand);
151 setOperationAction(Op: ISD::UDIV, VT: MVT::i16, Action: Expand);
152 setOperationAction(Op: ISD::UREM, VT: MVT::i8, Action: Expand);
153 setOperationAction(Op: ISD::UREM, VT: MVT::i16, Action: Expand);
154 setOperationAction(Op: ISD::SDIV, VT: MVT::i8, Action: Expand);
155 setOperationAction(Op: ISD::SDIV, VT: MVT::i16, Action: Expand);
156 setOperationAction(Op: ISD::SREM, VT: MVT::i8, Action: Expand);
157 setOperationAction(Op: ISD::SREM, VT: MVT::i16, Action: Expand);
158
159 // Make division and modulus custom
160 setOperationAction(Op: ISD::UDIVREM, VT: MVT::i8, Action: Custom);
161 setOperationAction(Op: ISD::UDIVREM, VT: MVT::i16, Action: Custom);
162 setOperationAction(Op: ISD::UDIVREM, VT: MVT::i32, Action: Custom);
163 setOperationAction(Op: ISD::SDIVREM, VT: MVT::i8, Action: Custom);
164 setOperationAction(Op: ISD::SDIVREM, VT: MVT::i16, Action: Custom);
165 setOperationAction(Op: ISD::SDIVREM, VT: MVT::i32, Action: Custom);
166
167 // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
168 setOperationAction(Op: ISD::MUL, VT: MVT::i8, Action: Expand);
169 setOperationAction(Op: ISD::MUL, VT: MVT::i16, Action: Expand);
170
171 // Expand 16 bit multiplications.
172 setOperationAction(Op: ISD::SMUL_LOHI, VT: MVT::i16, Action: Expand);
173 setOperationAction(Op: ISD::UMUL_LOHI, VT: MVT::i16, Action: Expand);
174
175 // Expand multiplications to libcalls when there is
176 // no hardware MUL.
177 if (!Subtarget.supportsMultiplication()) {
178 setOperationAction(Op: ISD::SMUL_LOHI, VT: MVT::i8, Action: Expand);
179 setOperationAction(Op: ISD::UMUL_LOHI, VT: MVT::i8, Action: Expand);
180 }
181
182 for (MVT VT : MVT::integer_valuetypes()) {
183 setOperationAction(Op: ISD::MULHS, VT, Action: Expand);
184 setOperationAction(Op: ISD::MULHU, VT, Action: Expand);
185 }
186
187 for (MVT VT : MVT::integer_valuetypes()) {
188 setOperationAction(Op: ISD::CTPOP, VT, Action: Expand);
189 setOperationAction(Op: ISD::CTLZ, VT, Action: Expand);
190 setOperationAction(Op: ISD::CTTZ, VT, Action: Expand);
191 }
192
193 for (MVT VT : MVT::integer_valuetypes()) {
194 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT, Action: Expand);
195 // TODO: The generated code is pretty poor. Investigate using the
196 // same "shift and subtract with carry" trick that we do for
197 // extending 8-bit to 16-bit. This may require infrastructure
198 // improvements in how we treat 16-bit "registers" to be feasible.
199 }
200
201 setMinFunctionAlignment(Align(2));
202 setMinimumJumpTableEntries(UINT_MAX);
203}
204
205EVT AVRTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
206 EVT VT) const {
207 assert(!VT.isVector() && "No AVR SetCC type for vectors!");
208 return MVT::i8;
209}
210
211SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
212 unsigned Opc8;
213 const SDNode *N = Op.getNode();
214 EVT VT = Op.getValueType();
215 SDLoc dl(N);
216 assert(llvm::has_single_bit<uint32_t>(VT.getSizeInBits()) &&
217 "Expected power-of-2 shift amount");
218
219 if (VT.getSizeInBits() == 32) {
220 if (!isa<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
221 // 32-bit shifts are converted to a loop in IR.
222 // This should be unreachable.
223 report_fatal_error(reason: "Expected a constant shift amount!");
224 }
225 SDVTList ResTys = DAG.getVTList(VT1: MVT::i16, VT2: MVT::i16);
226 SDValue SrcLo =
227 DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL: dl, VT: MVT::i16, N1: Op.getOperand(i: 0),
228 N2: DAG.getConstant(Val: 0, DL: dl, VT: MVT::i16));
229 SDValue SrcHi =
230 DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL: dl, VT: MVT::i16, N1: Op.getOperand(i: 0),
231 N2: DAG.getConstant(Val: 1, DL: dl, VT: MVT::i16));
232 uint64_t ShiftAmount = N->getConstantOperandVal(Num: 1);
233 if (ShiftAmount == 16) {
234 // Special case these two operations because they appear to be used by the
235 // generic codegen parts to lower 32-bit numbers.
236 // TODO: perhaps we can lower shift amounts bigger than 16 to a 16-bit
237 // shift of a part of the 32-bit value?
238 switch (Op.getOpcode()) {
239 case ISD::SHL: {
240 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT: MVT::i16);
241 return DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i32, N1: Zero, N2: SrcLo);
242 }
243 case ISD::SRL: {
244 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT: MVT::i16);
245 return DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i32, N1: SrcHi, N2: Zero);
246 }
247 }
248 }
249 SDValue Cnt = DAG.getTargetConstant(Val: ShiftAmount, DL: dl, VT: MVT::i8);
250 unsigned Opc;
251 switch (Op.getOpcode()) {
252 default:
253 llvm_unreachable("Invalid 32-bit shift opcode!");
254 case ISD::SHL:
255 Opc = AVRISD::LSLW;
256 break;
257 case ISD::SRL:
258 Opc = AVRISD::LSRW;
259 break;
260 case ISD::SRA:
261 Opc = AVRISD::ASRW;
262 break;
263 }
264 SDValue Result = DAG.getNode(Opcode: Opc, DL: dl, VTList: ResTys, N1: SrcLo, N2: SrcHi, N3: Cnt);
265 return DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i32, N1: Result.getValue(R: 0),
266 N2: Result.getValue(R: 1));
267 }
268
269 // Expand non-constant shifts to loops.
270 if (!isa<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
271 switch (Op.getOpcode()) {
272 default:
273 llvm_unreachable("Invalid shift opcode!");
274 case ISD::SHL:
275 return DAG.getNode(Opcode: AVRISD::LSLLOOP, DL: dl, VT, N1: N->getOperand(Num: 0),
276 N2: N->getOperand(Num: 1));
277 case ISD::SRL:
278 return DAG.getNode(Opcode: AVRISD::LSRLOOP, DL: dl, VT, N1: N->getOperand(Num: 0),
279 N2: N->getOperand(Num: 1));
280 case ISD::ROTL: {
281 SDValue Amt = N->getOperand(Num: 1);
282 EVT AmtVT = Amt.getValueType();
283 Amt = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: AmtVT, N1: Amt,
284 N2: DAG.getConstant(Val: VT.getSizeInBits() - 1, DL: dl, VT: AmtVT));
285 return DAG.getNode(Opcode: AVRISD::ROLLOOP, DL: dl, VT, N1: N->getOperand(Num: 0), N2: Amt);
286 }
287 case ISD::ROTR: {
288 SDValue Amt = N->getOperand(Num: 1);
289 EVT AmtVT = Amt.getValueType();
290 Amt = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: AmtVT, N1: Amt,
291 N2: DAG.getConstant(Val: VT.getSizeInBits() - 1, DL: dl, VT: AmtVT));
292 return DAG.getNode(Opcode: AVRISD::RORLOOP, DL: dl, VT, N1: N->getOperand(Num: 0), N2: Amt);
293 }
294 case ISD::SRA:
295 return DAG.getNode(Opcode: AVRISD::ASRLOOP, DL: dl, VT, N1: N->getOperand(Num: 0),
296 N2: N->getOperand(Num: 1));
297 }
298 }
299
300 uint64_t ShiftAmount = N->getConstantOperandVal(Num: 1);
301 SDValue Victim = N->getOperand(Num: 0);
302
303 switch (Op.getOpcode()) {
304 case ISD::SRA:
305 Opc8 = AVRISD::ASR;
306 break;
307 case ISD::ROTL:
308 Opc8 = AVRISD::ROL;
309 ShiftAmount = ShiftAmount % VT.getSizeInBits();
310 break;
311 case ISD::ROTR:
312 Opc8 = AVRISD::ROR;
313 ShiftAmount = ShiftAmount % VT.getSizeInBits();
314 break;
315 case ISD::SRL:
316 Opc8 = AVRISD::LSR;
317 break;
318 case ISD::SHL:
319 Opc8 = AVRISD::LSL;
320 break;
321 default:
322 llvm_unreachable("Invalid shift opcode");
323 }
324
325 // Optimize int8/int16 shifts.
326 if (VT.getSizeInBits() == 8) {
327 if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) {
328 // Optimize LSL when 4 <= ShiftAmount <= 6.
329 Victim = DAG.getNode(Opcode: AVRISD::SWAP, DL: dl, VT, Operand: Victim);
330 Victim =
331 DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: Victim, N2: DAG.getConstant(Val: 0xf0, DL: dl, VT));
332 ShiftAmount -= 4;
333 } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount &&
334 ShiftAmount < 7) {
335 // Optimize LSR when 4 <= ShiftAmount <= 6.
336 Victim = DAG.getNode(Opcode: AVRISD::SWAP, DL: dl, VT, Operand: Victim);
337 Victim =
338 DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: Victim, N2: DAG.getConstant(Val: 0x0f, DL: dl, VT));
339 ShiftAmount -= 4;
340 } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) {
341 // Optimize LSL when ShiftAmount == 7.
342 Victim = DAG.getNode(Opcode: AVRISD::LSLBN, DL: dl, VT, N1: Victim,
343 N2: DAG.getConstant(Val: 7, DL: dl, VT));
344 ShiftAmount = 0;
345 } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) {
346 // Optimize LSR when ShiftAmount == 7.
347 Victim = DAG.getNode(Opcode: AVRISD::LSRBN, DL: dl, VT, N1: Victim,
348 N2: DAG.getConstant(Val: 7, DL: dl, VT));
349 ShiftAmount = 0;
350 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 6) {
351 // Optimize ASR when ShiftAmount == 6.
352 Victim = DAG.getNode(Opcode: AVRISD::ASRBN, DL: dl, VT, N1: Victim,
353 N2: DAG.getConstant(Val: 6, DL: dl, VT));
354 ShiftAmount = 0;
355 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) {
356 // Optimize ASR when ShiftAmount == 7.
357 Victim = DAG.getNode(Opcode: AVRISD::ASRBN, DL: dl, VT, N1: Victim,
358 N2: DAG.getConstant(Val: 7, DL: dl, VT));
359 ShiftAmount = 0;
360 } else if (Op.getOpcode() == ISD::ROTL && ShiftAmount == 3) {
361 // Optimize left rotation 3 bits to swap then right rotation 1 bit.
362 Victim = DAG.getNode(Opcode: AVRISD::SWAP, DL: dl, VT, Operand: Victim);
363 Victim = DAG.getNode(Opcode: AVRISD::ROR, DL: dl, VT, Operand: Victim);
364 ShiftAmount = 0;
365 } else if (Op.getOpcode() == ISD::ROTR && ShiftAmount == 3) {
366 // Optimize right rotation 3 bits to swap then left rotation 1 bit.
367 Victim = DAG.getNode(Opcode: AVRISD::SWAP, DL: dl, VT, Operand: Victim);
368 Victim = DAG.getNode(Opcode: AVRISD::ROL, DL: dl, VT, Operand: Victim);
369 ShiftAmount = 0;
370 } else if (Op.getOpcode() == ISD::ROTL && ShiftAmount == 7) {
371 // Optimize left rotation 7 bits to right rotation 1 bit.
372 Victim = DAG.getNode(Opcode: AVRISD::ROR, DL: dl, VT, Operand: Victim);
373 ShiftAmount = 0;
374 } else if (Op.getOpcode() == ISD::ROTR && ShiftAmount == 7) {
375 // Optimize right rotation 7 bits to left rotation 1 bit.
376 Victim = DAG.getNode(Opcode: AVRISD::ROL, DL: dl, VT, Operand: Victim);
377 ShiftAmount = 0;
378 } else if ((Op.getOpcode() == ISD::ROTR || Op.getOpcode() == ISD::ROTL) &&
379 ShiftAmount >= 4) {
380 // Optimize left/right rotation with the SWAP instruction.
381 Victim = DAG.getNode(Opcode: AVRISD::SWAP, DL: dl, VT, Operand: Victim);
382 ShiftAmount -= 4;
383 }
384 } else if (VT.getSizeInBits() == 16) {
385 if (Op.getOpcode() == ISD::SRA)
386 // Special optimization for int16 arithmetic right shift.
387 switch (ShiftAmount) {
388 case 15:
389 Victim = DAG.getNode(Opcode: AVRISD::ASRWN, DL: dl, VT, N1: Victim,
390 N2: DAG.getConstant(Val: 15, DL: dl, VT));
391 ShiftAmount = 0;
392 break;
393 case 14:
394 Victim = DAG.getNode(Opcode: AVRISD::ASRWN, DL: dl, VT, N1: Victim,
395 N2: DAG.getConstant(Val: 14, DL: dl, VT));
396 ShiftAmount = 0;
397 break;
398 case 7:
399 Victim = DAG.getNode(Opcode: AVRISD::ASRWN, DL: dl, VT, N1: Victim,
400 N2: DAG.getConstant(Val: 7, DL: dl, VT));
401 ShiftAmount = 0;
402 break;
403 default:
404 break;
405 }
406 if (4 <= ShiftAmount && ShiftAmount < 8)
407 switch (Op.getOpcode()) {
408 case ISD::SHL:
409 Victim = DAG.getNode(Opcode: AVRISD::LSLWN, DL: dl, VT, N1: Victim,
410 N2: DAG.getConstant(Val: 4, DL: dl, VT));
411 ShiftAmount -= 4;
412 break;
413 case ISD::SRL:
414 Victim = DAG.getNode(Opcode: AVRISD::LSRWN, DL: dl, VT, N1: Victim,
415 N2: DAG.getConstant(Val: 4, DL: dl, VT));
416 ShiftAmount -= 4;
417 break;
418 default:
419 break;
420 }
421 else if (8 <= ShiftAmount && ShiftAmount < 12)
422 switch (Op.getOpcode()) {
423 case ISD::SHL:
424 Victim = DAG.getNode(Opcode: AVRISD::LSLWN, DL: dl, VT, N1: Victim,
425 N2: DAG.getConstant(Val: 8, DL: dl, VT));
426 ShiftAmount -= 8;
427 // Only operate on the higher byte for remaining shift bits.
428 Opc8 = AVRISD::LSLHI;
429 break;
430 case ISD::SRL:
431 Victim = DAG.getNode(Opcode: AVRISD::LSRWN, DL: dl, VT, N1: Victim,
432 N2: DAG.getConstant(Val: 8, DL: dl, VT));
433 ShiftAmount -= 8;
434 // Only operate on the lower byte for remaining shift bits.
435 Opc8 = AVRISD::LSRLO;
436 break;
437 case ISD::SRA:
438 Victim = DAG.getNode(Opcode: AVRISD::ASRWN, DL: dl, VT, N1: Victim,
439 N2: DAG.getConstant(Val: 8, DL: dl, VT));
440 ShiftAmount -= 8;
441 // Only operate on the lower byte for remaining shift bits.
442 Opc8 = AVRISD::ASRLO;
443 break;
444 default:
445 break;
446 }
447 else if (12 <= ShiftAmount)
448 switch (Op.getOpcode()) {
449 case ISD::SHL:
450 Victim = DAG.getNode(Opcode: AVRISD::LSLWN, DL: dl, VT, N1: Victim,
451 N2: DAG.getConstant(Val: 12, DL: dl, VT));
452 ShiftAmount -= 12;
453 // Only operate on the higher byte for remaining shift bits.
454 Opc8 = AVRISD::LSLHI;
455 break;
456 case ISD::SRL:
457 Victim = DAG.getNode(Opcode: AVRISD::LSRWN, DL: dl, VT, N1: Victim,
458 N2: DAG.getConstant(Val: 12, DL: dl, VT));
459 ShiftAmount -= 12;
460 // Only operate on the lower byte for remaining shift bits.
461 Opc8 = AVRISD::LSRLO;
462 break;
463 case ISD::SRA:
464 Victim = DAG.getNode(Opcode: AVRISD::ASRWN, DL: dl, VT, N1: Victim,
465 N2: DAG.getConstant(Val: 8, DL: dl, VT));
466 ShiftAmount -= 8;
467 // Only operate on the lower byte for remaining shift bits.
468 Opc8 = AVRISD::ASRLO;
469 break;
470 default:
471 break;
472 }
473 }
474
475 while (ShiftAmount--) {
476 Victim = DAG.getNode(Opcode: Opc8, DL: dl, VT, Operand: Victim);
477 }
478
479 return Victim;
480}
481
482SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
483 unsigned Opcode = Op->getOpcode();
484 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
485 "Invalid opcode for Div/Rem lowering");
486 bool IsSigned = (Opcode == ISD::SDIVREM);
487 EVT VT = Op->getValueType(ResNo: 0);
488 Type *Ty = VT.getTypeForEVT(Context&: *DAG.getContext());
489
490 RTLIB::Libcall LC;
491 switch (VT.getSimpleVT().SimpleTy) {
492 default:
493 llvm_unreachable("Unexpected request for libcall!");
494 case MVT::i8:
495 LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
496 break;
497 case MVT::i16:
498 LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
499 break;
500 case MVT::i32:
501 LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
502 break;
503 }
504
505 SDValue InChain = DAG.getEntryNode();
506
507 TargetLowering::ArgListTy Args;
508 for (SDValue const &Value : Op->op_values()) {
509 TargetLowering::ArgListEntry Entry(
510 Value, Value.getValueType().getTypeForEVT(Context&: *DAG.getContext()));
511 Entry.IsSExt = IsSigned;
512 Entry.IsZExt = !IsSigned;
513 Args.push_back(x: Entry);
514 }
515
516 RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(Call: LC);
517 if (LCImpl == RTLIB::Unsupported)
518 return SDValue();
519
520 SDValue Callee =
521 DAG.getExternalSymbol(LCImpl, VT: getPointerTy(DL: DAG.getDataLayout()));
522
523 Type *RetTy = (Type *)StructType::get(elt1: Ty, elts: Ty);
524
525 SDLoc dl(Op);
526 TargetLowering::CallLoweringInfo CLI(DAG);
527 CLI.setDebugLoc(dl)
528 .setChain(InChain)
529 .setLibCallee(CC: DAG.getLibcalls().getLibcallImplCallingConv(Call: LCImpl), ResultType: RetTy,
530 Target: Callee, ArgsList: std::move(Args))
531 .setInRegister()
532 .setSExtResult(IsSigned)
533 .setZExtResult(!IsSigned);
534
535 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
536 return CallInfo.first;
537}
538
539SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op,
540 SelectionDAG &DAG) const {
541 auto DL = DAG.getDataLayout();
542
543 const GlobalValue *GV = cast<GlobalAddressSDNode>(Val&: Op)->getGlobal();
544 int64_t Offset = cast<GlobalAddressSDNode>(Val&: Op)->getOffset();
545
546 // Create the TargetGlobalAddress node, folding in the constant offset.
547 SDValue Result =
548 DAG.getTargetGlobalAddress(GV, DL: SDLoc(Op), VT: getPointerTy(DL), offset: Offset);
549 return DAG.getNode(Opcode: AVRISD::WRAPPER, DL: SDLoc(Op), VT: getPointerTy(DL), Operand: Result);
550}
551
552SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op,
553 SelectionDAG &DAG) const {
554 auto DL = DAG.getDataLayout();
555 const BlockAddress *BA = cast<BlockAddressSDNode>(Val&: Op)->getBlockAddress();
556
557 SDValue Result = DAG.getTargetBlockAddress(BA, VT: getPointerTy(DL));
558
559 return DAG.getNode(Opcode: AVRISD::WRAPPER, DL: SDLoc(Op), VT: getPointerTy(DL), Operand: Result);
560}
561
562/// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
563static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC) {
564 switch (CC) {
565 default:
566 llvm_unreachable("Unknown condition code!");
567 case ISD::SETEQ:
568 return AVRCC::COND_EQ;
569 case ISD::SETNE:
570 return AVRCC::COND_NE;
571 case ISD::SETGE:
572 return AVRCC::COND_GE;
573 case ISD::SETLT:
574 return AVRCC::COND_LT;
575 case ISD::SETUGE:
576 return AVRCC::COND_SH;
577 case ISD::SETULT:
578 return AVRCC::COND_LO;
579 }
580}
581
582/// Returns appropriate CP/CPI/CPC nodes code for the given 8/16-bit operands.
583SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS,
584 SelectionDAG &DAG, SDLoc DL) const {
585 assert((LHS.getSimpleValueType() == RHS.getSimpleValueType()) &&
586 "LHS and RHS have different types");
587 assert(((LHS.getSimpleValueType() == MVT::i16) ||
588 (LHS.getSimpleValueType() == MVT::i8)) &&
589 "invalid comparison type");
590
591 SDValue Cmp;
592
593 if (LHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(Val: RHS)) {
594 uint64_t Imm = RHS->getAsZExtVal();
595 // Generate a CPI/CPC pair if RHS is a 16-bit constant. Use the zero
596 // register for the constant RHS if its lower or higher byte is zero.
597 SDValue LHSlo = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: LHS,
598 N2: DAG.getIntPtrConstant(Val: 0, DL));
599 SDValue LHShi = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: LHS,
600 N2: DAG.getIntPtrConstant(Val: 1, DL));
601 SDValue RHSlo = (Imm & 0xff) == 0
602 ? DAG.getRegister(Reg: Subtarget.getZeroRegister(), VT: MVT::i8)
603 : DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: RHS,
604 N2: DAG.getIntPtrConstant(Val: 0, DL));
605 SDValue RHShi = (Imm & 0xff00) == 0
606 ? DAG.getRegister(Reg: Subtarget.getZeroRegister(), VT: MVT::i8)
607 : DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: RHS,
608 N2: DAG.getIntPtrConstant(Val: 1, DL));
609 Cmp = DAG.getNode(Opcode: AVRISD::CMP, DL, VT: MVT::Glue, N1: LHSlo, N2: RHSlo);
610 Cmp = DAG.getNode(Opcode: AVRISD::CMPC, DL, VT: MVT::Glue, N1: LHShi, N2: RHShi, N3: Cmp);
611 } else if (RHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(Val: LHS)) {
612 // Generate a CPI/CPC pair if LHS is a 16-bit constant. Use the zero
613 // register for the constant LHS if its lower or higher byte is zero.
614 uint64_t Imm = LHS->getAsZExtVal();
615 SDValue LHSlo = (Imm & 0xff) == 0
616 ? DAG.getRegister(Reg: Subtarget.getZeroRegister(), VT: MVT::i8)
617 : DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: LHS,
618 N2: DAG.getIntPtrConstant(Val: 0, DL));
619 SDValue LHShi = (Imm & 0xff00) == 0
620 ? DAG.getRegister(Reg: Subtarget.getZeroRegister(), VT: MVT::i8)
621 : DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: LHS,
622 N2: DAG.getIntPtrConstant(Val: 1, DL));
623 SDValue RHSlo = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: RHS,
624 N2: DAG.getIntPtrConstant(Val: 0, DL));
625 SDValue RHShi = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: RHS,
626 N2: DAG.getIntPtrConstant(Val: 1, DL));
627 Cmp = DAG.getNode(Opcode: AVRISD::CMP, DL, VT: MVT::Glue, N1: LHSlo, N2: RHSlo);
628 Cmp = DAG.getNode(Opcode: AVRISD::CMPC, DL, VT: MVT::Glue, N1: LHShi, N2: RHShi, N3: Cmp);
629 } else {
630 // Generate ordinary 16-bit comparison.
631 Cmp = DAG.getNode(Opcode: AVRISD::CMP, DL, VT: MVT::Glue, N1: LHS, N2: RHS);
632 }
633
634 return Cmp;
635}
636
637/// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for
638/// the given operands.
639SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
640 SDValue &AVRcc, SelectionDAG &DAG,
641 SDLoc DL) const {
642 SDValue Cmp;
643 EVT VT = LHS.getValueType();
644 bool UseTest = false;
645
646 switch (CC) {
647 default:
648 break;
649 case ISD::SETLE: {
650 // Swap operands and reverse the branching condition.
651 std::swap(a&: LHS, b&: RHS);
652 CC = ISD::SETGE;
653 break;
654 }
655 case ISD::SETGT: {
656 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: RHS)) {
657 switch (C->getSExtValue()) {
658 case -1: {
659 // When doing lhs > -1 use a tst instruction on the top part of lhs
660 // and use brpl instead of using a chain of cp/cpc.
661 UseTest = true;
662 AVRcc = DAG.getConstant(Val: AVRCC::COND_PL, DL, VT: MVT::i8);
663 break;
664 }
665 case 0: {
666 // Turn lhs > 0 into 0 < lhs since 0 can be materialized with
667 // __zero_reg__ in lhs.
668 RHS = LHS;
669 LHS = DAG.getConstant(Val: 0, DL, VT);
670 CC = ISD::SETLT;
671 break;
672 }
673 default: {
674 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows
675 // us to fold the constant into the cmp instruction.
676 RHS = DAG.getSignedConstant(Val: C->getSExtValue() + 1, DL, VT);
677 CC = ISD::SETGE;
678 break;
679 }
680 }
681 break;
682 }
683 // Swap operands and reverse the branching condition.
684 std::swap(a&: LHS, b&: RHS);
685 CC = ISD::SETLT;
686 break;
687 }
688 case ISD::SETLT: {
689 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: RHS)) {
690 switch (C->getSExtValue()) {
691 case 1: {
692 // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with
693 // __zero_reg__ in lhs.
694 RHS = LHS;
695 LHS = DAG.getConstant(Val: 0, DL, VT);
696 CC = ISD::SETGE;
697 break;
698 }
699 case 0: {
700 // When doing lhs < 0 use a tst instruction on the top part of lhs
701 // and use brmi instead of using a chain of cp/cpc.
702 UseTest = true;
703 AVRcc = DAG.getConstant(Val: AVRCC::COND_MI, DL, VT: MVT::i8);
704 break;
705 }
706 }
707 }
708 break;
709 }
710 case ISD::SETULE: {
711 // Swap operands and reverse the branching condition.
712 std::swap(a&: LHS, b&: RHS);
713 CC = ISD::SETUGE;
714 break;
715 }
716 case ISD::SETUGT: {
717 // Turn `lhs > rhs` with constant rhs into `lhs >= rhs + 1`, because this
718 // allows us to fold the constant into the cmp instruction.
719 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: RHS)) {
720 if (C->getConstantIntValue()->isMaxValue(IsSigned: false)) {
721 // Applying this optimization requires calculating rhs+1, which we can't
722 // do if that overflows; it can happen during i128->i64 lowering.
723 } else {
724 RHS = DAG.getConstant(Val: C->getZExtValue() + 1, DL, VT);
725 CC = ISD::SETUGE;
726 break;
727 }
728 }
729 // Swap operands and reverse the branching condition.
730 std::swap(a&: LHS, b&: RHS);
731 CC = ISD::SETULT;
732 break;
733 }
734 }
735
736 // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of
737 // using the default and/or/xor expansion code which is much longer.
738 if (VT == MVT::i32) {
739 SDValue LHSlo = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: LHS,
740 N2: DAG.getIntPtrConstant(Val: 0, DL));
741 SDValue LHShi = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: LHS,
742 N2: DAG.getIntPtrConstant(Val: 1, DL));
743 SDValue RHSlo = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: RHS,
744 N2: DAG.getIntPtrConstant(Val: 0, DL));
745 SDValue RHShi = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: RHS,
746 N2: DAG.getIntPtrConstant(Val: 1, DL));
747
748 if (UseTest) {
749 // When using tst we only care about the highest part.
750 SDValue Top = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: LHShi,
751 N2: DAG.getIntPtrConstant(Val: 1, DL));
752 Cmp = DAG.getNode(Opcode: AVRISD::TST, DL, VT: MVT::Glue, Operand: Top);
753 } else {
754 Cmp = getAVRCmp(LHS: LHSlo, RHS: RHSlo, DAG, DL);
755 Cmp = DAG.getNode(Opcode: AVRISD::CMPC, DL, VT: MVT::Glue, N1: LHShi, N2: RHShi, N3: Cmp);
756 }
757 } else if (VT == MVT::i64) {
758 SDValue LHS_0 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i32, N1: LHS,
759 N2: DAG.getIntPtrConstant(Val: 0, DL));
760 SDValue LHS_1 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i32, N1: LHS,
761 N2: DAG.getIntPtrConstant(Val: 1, DL));
762
763 SDValue LHS0 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: LHS_0,
764 N2: DAG.getIntPtrConstant(Val: 0, DL));
765 SDValue LHS1 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: LHS_0,
766 N2: DAG.getIntPtrConstant(Val: 1, DL));
767 SDValue LHS2 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: LHS_1,
768 N2: DAG.getIntPtrConstant(Val: 0, DL));
769 SDValue LHS3 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: LHS_1,
770 N2: DAG.getIntPtrConstant(Val: 1, DL));
771
772 SDValue RHS_0 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i32, N1: RHS,
773 N2: DAG.getIntPtrConstant(Val: 0, DL));
774 SDValue RHS_1 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i32, N1: RHS,
775 N2: DAG.getIntPtrConstant(Val: 1, DL));
776
777 SDValue RHS0 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: RHS_0,
778 N2: DAG.getIntPtrConstant(Val: 0, DL));
779 SDValue RHS1 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: RHS_0,
780 N2: DAG.getIntPtrConstant(Val: 1, DL));
781 SDValue RHS2 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: RHS_1,
782 N2: DAG.getIntPtrConstant(Val: 0, DL));
783 SDValue RHS3 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: RHS_1,
784 N2: DAG.getIntPtrConstant(Val: 1, DL));
785
786 if (UseTest) {
787 // When using tst we only care about the highest part.
788 SDValue Top = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: LHS3,
789 N2: DAG.getIntPtrConstant(Val: 1, DL));
790 Cmp = DAG.getNode(Opcode: AVRISD::TST, DL, VT: MVT::Glue, Operand: Top);
791 } else {
792 Cmp = getAVRCmp(LHS: LHS0, RHS: RHS0, DAG, DL);
793 Cmp = DAG.getNode(Opcode: AVRISD::CMPC, DL, VT: MVT::Glue, N1: LHS1, N2: RHS1, N3: Cmp);
794 Cmp = DAG.getNode(Opcode: AVRISD::CMPC, DL, VT: MVT::Glue, N1: LHS2, N2: RHS2, N3: Cmp);
795 Cmp = DAG.getNode(Opcode: AVRISD::CMPC, DL, VT: MVT::Glue, N1: LHS3, N2: RHS3, N3: Cmp);
796 }
797 } else if (VT == MVT::i8 || VT == MVT::i16) {
798 if (UseTest) {
799 // When using tst we only care about the highest part.
800 Cmp = DAG.getNode(Opcode: AVRISD::TST, DL, VT: MVT::Glue,
801 Operand: (VT == MVT::i8)
802 ? LHS
803 : DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8,
804 N1: LHS, N2: DAG.getIntPtrConstant(Val: 1, DL)));
805 } else {
806 Cmp = getAVRCmp(LHS, RHS, DAG, DL);
807 }
808 } else {
809 llvm_unreachable("Invalid comparison size");
810 }
811
812 // When using a test instruction AVRcc is already set.
813 if (!UseTest) {
814 AVRcc = DAG.getConstant(Val: intCCToAVRCC(CC), DL, VT: MVT::i8);
815 }
816
817 return Cmp;
818}
819
820SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
821 SDValue Chain = Op.getOperand(i: 0);
822 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 1))->get();
823 SDValue LHS = Op.getOperand(i: 2);
824 SDValue RHS = Op.getOperand(i: 3);
825 SDValue Dest = Op.getOperand(i: 4);
826 SDLoc dl(Op);
827
828 SDValue TargetCC;
829 SDValue Cmp = getAVRCmp(LHS, RHS, CC, AVRcc&: TargetCC, DAG, DL: dl);
830
831 return DAG.getNode(Opcode: AVRISD::BRCOND, DL: dl, VT: MVT::Other, N1: Chain, N2: Dest, N3: TargetCC,
832 N4: Cmp);
833}
834
835SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
836 SDValue LHS = Op.getOperand(i: 0);
837 SDValue RHS = Op.getOperand(i: 1);
838 SDValue TrueV = Op.getOperand(i: 2);
839 SDValue FalseV = Op.getOperand(i: 3);
840 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 4))->get();
841 SDLoc dl(Op);
842
843 SDValue TargetCC;
844 SDValue Cmp = getAVRCmp(LHS, RHS, CC, AVRcc&: TargetCC, DAG, DL: dl);
845
846 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
847
848 return DAG.getNode(Opcode: AVRISD::SELECT_CC, DL: dl, VT: Op.getValueType(), Ops);
849}
850
851SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
852 SDValue LHS = Op.getOperand(i: 0);
853 SDValue RHS = Op.getOperand(i: 1);
854 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 2))->get();
855 SDLoc DL(Op);
856
857 SDValue TargetCC;
858 SDValue Cmp = getAVRCmp(LHS, RHS, CC, AVRcc&: TargetCC, DAG, DL);
859
860 SDValue TrueV = DAG.getConstant(Val: 1, DL, VT: Op.getValueType());
861 SDValue FalseV = DAG.getConstant(Val: 0, DL, VT: Op.getValueType());
862 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
863
864 return DAG.getNode(Opcode: AVRISD::SELECT_CC, DL, VT: Op.getValueType(), Ops);
865}
866
867SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
868 const MachineFunction &MF = DAG.getMachineFunction();
869 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
870 const Value *SV = cast<SrcValueSDNode>(Val: Op.getOperand(i: 2))->getValue();
871 auto DL = DAG.getDataLayout();
872 SDLoc dl(Op);
873
874 // Vastart just stores the address of the VarArgsFrameIndex slot into the
875 // memory location argument.
876 SDValue FI = DAG.getFrameIndex(FI: AFI->getVarArgsFrameIndex(), VT: getPointerTy(DL));
877
878 return DAG.getStore(Chain: Op.getOperand(i: 0), dl, Val: FI, Ptr: Op.getOperand(i: 1),
879 PtrInfo: MachinePointerInfo(SV));
880}
881
882// Modify the existing ISD::INLINEASM node to add the implicit zero register.
883SDValue AVRTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
884 SDValue ZeroReg = DAG.getRegister(Reg: Subtarget.getZeroRegister(), VT: MVT::i8);
885 if (Op.getOperand(i: Op.getNumOperands() - 1) == ZeroReg ||
886 Op.getOperand(i: Op.getNumOperands() - 2) == ZeroReg) {
887 // Zero register has already been added. Don't add it again.
888 // If this isn't handled, we get called over and over again.
889 return Op;
890 }
891
892 // Get a list of operands to the new INLINEASM node. This is mostly a copy,
893 // with some edits.
894 // Add the following operands at the end (but before the glue node, if it's
895 // there):
896 // - The flags of the implicit zero register operand.
897 // - The implicit zero register operand itself.
898 SDLoc dl(Op);
899 SmallVector<SDValue, 8> Ops;
900 SDNode *N = Op.getNode();
901 SDValue Glue;
902 for (unsigned I = 0; I < N->getNumOperands(); I++) {
903 SDValue Operand = N->getOperand(Num: I);
904 if (Operand.getValueType() == MVT::Glue) {
905 // The glue operand always needs to be at the end, so we need to treat it
906 // specially.
907 Glue = Operand;
908 } else {
909 Ops.push_back(Elt: Operand);
910 }
911 }
912 InlineAsm::Flag Flags(InlineAsm::Kind::RegUse, 1);
913 Ops.push_back(Elt: DAG.getTargetConstant(Val: Flags, DL: dl, VT: MVT::i32));
914 Ops.push_back(Elt: ZeroReg);
915 if (Glue) {
916 Ops.push_back(Elt: Glue);
917 }
918
919 // Replace the current INLINEASM node with a new one that has the zero
920 // register as implicit parameter.
921 SDValue New = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: N->getVTList(), Ops);
922 DAG.ReplaceAllUsesOfValueWith(From: Op, To: New);
923 DAG.ReplaceAllUsesOfValueWith(From: Op.getValue(R: 1), To: New.getValue(R: 1));
924
925 return New;
926}
927
928SDValue AVRTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
929 switch (Op.getOpcode()) {
930 default:
931 llvm_unreachable("Don't know how to custom lower this!");
932 case ISD::SHL:
933 case ISD::SRA:
934 case ISD::SRL:
935 case ISD::ROTL:
936 case ISD::ROTR:
937 return LowerShifts(Op, DAG);
938 case ISD::GlobalAddress:
939 return LowerGlobalAddress(Op, DAG);
940 case ISD::BlockAddress:
941 return LowerBlockAddress(Op, DAG);
942 case ISD::BR_CC:
943 return LowerBR_CC(Op, DAG);
944 case ISD::SELECT_CC:
945 return LowerSELECT_CC(Op, DAG);
946 case ISD::SETCC:
947 return LowerSETCC(Op, DAG);
948 case ISD::VASTART:
949 return LowerVASTART(Op, DAG);
950 case ISD::SDIVREM:
951 case ISD::UDIVREM:
952 return LowerDivRem(Op, DAG);
953 case ISD::INLINEASM:
954 return LowerINLINEASM(Op, DAG);
955 }
956
957 return SDValue();
958}
959
960/// Replace a node with an illegal result type
961/// with a new node built out of custom code.
962void AVRTargetLowering::ReplaceNodeResults(SDNode *N,
963 SmallVectorImpl<SDValue> &Results,
964 SelectionDAG &DAG) const {
965 SDLoc DL(N);
966
967 switch (N->getOpcode()) {
968 case ISD::ADD: {
969 // Convert add (x, imm) into sub (x, -imm).
970 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
971 SDValue Sub = DAG.getNode(
972 Opcode: ISD::SUB, DL, VT: N->getValueType(ResNo: 0), N1: N->getOperand(Num: 0),
973 N2: DAG.getConstant(Val: -C->getAPIntValue(), DL, VT: C->getValueType(ResNo: 0)));
974 Results.push_back(Elt: Sub);
975 }
976 break;
977 }
978 default: {
979 SDValue Res = LowerOperation(Op: SDValue(N, 0), DAG);
980
981 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
982 Results.push_back(Elt: Res.getValue(R: I));
983
984 break;
985 }
986 }
987}
988
989/// Return true if the addressing mode represented
990/// by AM is legal for this target, for a load/store of the specified type.
991bool AVRTargetLowering::isLegalAddressingMode(const DataLayout &DL,
992 const AddrMode &AM, Type *Ty,
993 unsigned AS,
994 Instruction *I) const {
995 int64_t Offs = AM.BaseOffs;
996
997 // Allow absolute addresses.
998 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) {
999 return true;
1000 }
1001
1002 // Flash memory instructions only allow zero offsets.
1003 if (isa<PointerType>(Val: Ty) && AS == AVR::ProgramMemory) {
1004 return false;
1005 }
1006
1007 // Allow reg+<6bit> offset.
1008 if (Offs < 0)
1009 Offs = -Offs;
1010 if (AM.BaseGV == nullptr && AM.HasBaseReg && AM.Scale == 0 &&
1011 isUInt<6>(x: Offs)) {
1012 return true;
1013 }
1014
1015 return false;
1016}
1017
1018/// Returns true by value, base pointer and
1019/// offset pointer and addressing mode by reference if the node's address
1020/// can be legally represented as pre-indexed load / store address.
1021bool AVRTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1022 SDValue &Offset,
1023 ISD::MemIndexedMode &AM,
1024 SelectionDAG &DAG) const {
1025 EVT VT;
1026 const SDNode *Op;
1027 SDLoc DL(N);
1028
1029 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(Val: N)) {
1030 VT = LD->getMemoryVT();
1031 Op = LD->getBasePtr().getNode();
1032 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1033 return false;
1034 if (AVR::isProgramMemoryAccess(N: LD)) {
1035 return false;
1036 }
1037 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(Val: N)) {
1038 VT = ST->getMemoryVT();
1039 Op = ST->getBasePtr().getNode();
1040 if (AVR::isProgramMemoryAccess(N: ST)) {
1041 return false;
1042 }
1043 } else {
1044 return false;
1045 }
1046
1047 if (VT != MVT::i8 && VT != MVT::i16) {
1048 return false;
1049 }
1050
1051 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
1052 return false;
1053 }
1054
1055 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Val: Op->getOperand(Num: 1))) {
1056 int RHSC = RHS->getSExtValue();
1057 if (Op->getOpcode() == ISD::SUB)
1058 RHSC = -RHSC;
1059
1060 if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
1061 return false;
1062 }
1063
1064 Base = Op->getOperand(Num: 0);
1065 Offset = DAG.getSignedConstant(Val: RHSC, DL, VT: MVT::i8);
1066 AM = ISD::PRE_DEC;
1067
1068 return true;
1069 }
1070
1071 return false;
1072}
1073
1074/// Returns true by value, base pointer and
1075/// offset pointer and addressing mode by reference if this node can be
1076/// combined with a load / store to form a post-indexed load / store.
1077bool AVRTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1078 SDValue &Base,
1079 SDValue &Offset,
1080 ISD::MemIndexedMode &AM,
1081 SelectionDAG &DAG) const {
1082 EVT VT;
1083 SDValue Ptr;
1084 SDLoc DL(N);
1085
1086 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(Val: N)) {
1087 VT = LD->getMemoryVT();
1088 Ptr = LD->getBasePtr();
1089 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1090 return false;
1091 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(Val: N)) {
1092 VT = ST->getMemoryVT();
1093 Ptr = ST->getBasePtr();
1094 // We can not store to program memory.
1095 if (AVR::isProgramMemoryAccess(N: ST))
1096 return false;
1097 // Since the high byte need to be stored first, we can not emit
1098 // i16 post increment store like:
1099 // st X+, r24
1100 // st X+, r25
1101 if (VT == MVT::i16 && !Subtarget.hasLowByteFirst())
1102 return false;
1103 } else {
1104 return false;
1105 }
1106
1107 if (VT != MVT::i8 && VT != MVT::i16) {
1108 return false;
1109 }
1110
1111 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
1112 return false;
1113 }
1114
1115 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Val: Op->getOperand(Num: 1))) {
1116 int RHSC = RHS->getSExtValue();
1117 if (Op->getOpcode() == ISD::SUB)
1118 RHSC = -RHSC;
1119 if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) {
1120 return false;
1121 }
1122
1123 // FIXME: We temporarily disable post increment load from program memory,
1124 // due to bug https://github.com/llvm/llvm-project/issues/59914.
1125 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(Val: N))
1126 if (AVR::isProgramMemoryAccess(N: LD))
1127 return false;
1128
1129 Base = Op->getOperand(Num: 0);
1130
1131 // Post-indexing updates the base, so it's not a valid transform
1132 // if that's not the same as the load's pointer.
1133 if (Ptr != Base)
1134 return false;
1135
1136 Offset = DAG.getConstant(Val: RHSC, DL, VT: MVT::i8);
1137 AM = ISD::POST_INC;
1138
1139 return true;
1140 }
1141
1142 return false;
1143}
1144
1145bool AVRTargetLowering::isOffsetFoldingLegal(
1146 const GlobalAddressSDNode *GA) const {
1147 return true;
1148}
1149
1150//===----------------------------------------------------------------------===//
1151// Formal Arguments Calling Convention Implementation
1152//===----------------------------------------------------------------------===//
1153
1154#include "AVRGenCallingConv.inc"
1155
1156/// Registers for calling conventions, ordered in reverse as required by ABI.
1157/// Both arrays must be of the same length.
1158static const MCPhysReg RegList8AVR[] = {
1159 AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20,
1160 AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
1161 AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8};
1162static const MCPhysReg RegList8Tiny[] = {AVR::R25, AVR::R24, AVR::R23,
1163 AVR::R22, AVR::R21, AVR::R20};
1164static const MCPhysReg RegList16AVR[] = {
1165 AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, AVR::R22R21,
1166 AVR::R21R20, AVR::R20R19, AVR::R19R18, AVR::R18R17, AVR::R17R16,
1167 AVR::R16R15, AVR::R15R14, AVR::R14R13, AVR::R13R12, AVR::R12R11,
1168 AVR::R11R10, AVR::R10R9, AVR::R9R8};
1169static const MCPhysReg RegList16Tiny[] = {AVR::R26R25, AVR::R25R24,
1170 AVR::R24R23, AVR::R23R22,
1171 AVR::R22R21, AVR::R21R20};
1172
1173static_assert(std::size(RegList8AVR) == std::size(RegList16AVR),
1174 "8-bit and 16-bit register arrays must be of equal length");
1175static_assert(std::size(RegList8Tiny) == std::size(RegList16Tiny),
1176 "8-bit and 16-bit register arrays must be of equal length");
1177
1178/// Analyze incoming and outgoing function arguments. We need custom C++ code
1179/// to handle special constraints in the ABI.
1180/// In addition, all pieces of a certain argument have to be passed either
1181/// using registers or the stack but never mixing both.
1182template <typename ArgT>
1183static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI,
1184 const Function *F, const DataLayout *TD,
1185 const SmallVectorImpl<ArgT> &Args,
1186 SmallVectorImpl<CCValAssign> &ArgLocs,
1187 CCState &CCInfo, bool Tiny) {
1188 // Choose the proper register list for argument passing according to the ABI.
1189 ArrayRef<MCPhysReg> RegList8;
1190 ArrayRef<MCPhysReg> RegList16;
1191 if (Tiny) {
1192 RegList8 = ArrayRef(RegList8Tiny);
1193 RegList16 = ArrayRef(RegList16Tiny);
1194 } else {
1195 RegList8 = ArrayRef(RegList8AVR);
1196 RegList16 = ArrayRef(RegList16AVR);
1197 }
1198
1199 unsigned NumArgs = Args.size();
1200 // This is the index of the last used register, in RegList*.
1201 // -1 means R26 (R26 is never actually used in CC).
1202 int RegLastIdx = -1;
1203 // Once a value is passed to the stack it will always be used
1204 bool UseStack = false;
1205 for (unsigned i = 0; i != NumArgs;) {
1206 MVT VT = Args[i].VT;
1207 // We have to count the number of bytes for each function argument, that is
1208 // those Args with the same OrigArgIndex. This is important in case the
1209 // function takes an aggregate type.
1210 // Current argument will be between [i..j).
1211 unsigned ArgIndex = Args[i].OrigArgIndex;
1212 unsigned TotalBytes = VT.getStoreSize();
1213 unsigned j = i + 1;
1214 for (; j != NumArgs; ++j) {
1215 if (Args[j].OrigArgIndex != ArgIndex)
1216 break;
1217 TotalBytes += Args[j].VT.getStoreSize();
1218 }
1219 // Round up to even number of bytes.
1220 TotalBytes = alignTo(Value: TotalBytes, Align: 2);
1221 // Skip zero sized arguments
1222 if (TotalBytes == 0)
1223 continue;
1224 // The index of the first register to be used
1225 unsigned RegIdx = RegLastIdx + TotalBytes;
1226 RegLastIdx = RegIdx;
1227 // If there are not enough registers, use the stack
1228 if (RegIdx >= RegList8.size()) {
1229 UseStack = true;
1230 }
1231 for (; i != j; ++i) {
1232 MVT VT = Args[i].VT;
1233
1234 if (UseStack) {
1235 auto evt = EVT(VT).getTypeForEVT(Context&: CCInfo.getContext());
1236 unsigned Offset = CCInfo.AllocateStack(Size: TD->getTypeAllocSize(Ty: evt),
1237 Alignment: TD->getABITypeAlign(Ty: evt));
1238 CCInfo.addLoc(
1239 V: CCValAssign::getMem(ValNo: i, ValVT: VT, Offset, LocVT: VT, HTP: CCValAssign::Full));
1240 } else {
1241 unsigned Reg;
1242 if (VT == MVT::i8) {
1243 Reg = CCInfo.AllocateReg(Reg: RegList8[RegIdx]);
1244 } else if (VT == MVT::i16) {
1245 Reg = CCInfo.AllocateReg(Reg: RegList16[RegIdx]);
1246 } else {
1247 llvm_unreachable(
1248 "calling convention can only manage i8 and i16 types");
1249 }
1250 assert(Reg && "register not available in calling convention");
1251 CCInfo.addLoc(V: CCValAssign::getReg(ValNo: i, ValVT: VT, Reg, LocVT: VT, HTP: CCValAssign::Full));
1252 // Registers inside a particular argument are sorted in increasing order
1253 // (remember the array is reversed).
1254 RegIdx -= VT.getStoreSize();
1255 }
1256 }
1257 }
1258}
1259
1260/// Count the total number of bytes needed to pass or return these arguments.
1261template <typename ArgT>
1262static unsigned
1263getTotalArgumentsSizeInBytes(const SmallVectorImpl<ArgT> &Args) {
1264 unsigned TotalBytes = 0;
1265
1266 for (const ArgT &Arg : Args) {
1267 TotalBytes += Arg.VT.getStoreSize();
1268 }
1269 return TotalBytes;
1270}
1271
1272/// Analyze incoming and outgoing value of returning from a function.
1273/// The algorithm is similar to analyzeArguments, but there can only be
1274/// one value, possibly an aggregate, and it is limited to 8 bytes.
1275template <typename ArgT>
1276static void analyzeReturnValues(const SmallVectorImpl<ArgT> &Args,
1277 CCState &CCInfo, bool Tiny) {
1278 unsigned NumArgs = Args.size();
1279 unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args);
1280 // CanLowerReturn() guarantees this assertion.
1281 if (Tiny)
1282 assert(TotalBytes <= 4 &&
1283 "return values greater than 4 bytes cannot be lowered on AVRTiny");
1284 else
1285 assert(TotalBytes <= 8 &&
1286 "return values greater than 8 bytes cannot be lowered on AVR");
1287
1288 // Choose the proper register list for argument passing according to the ABI.
1289 ArrayRef<MCPhysReg> RegList8;
1290 ArrayRef<MCPhysReg> RegList16;
1291 if (Tiny) {
1292 RegList8 = ArrayRef(RegList8Tiny);
1293 RegList16 = ArrayRef(RegList16Tiny);
1294 } else {
1295 RegList8 = ArrayRef(RegList8AVR);
1296 RegList16 = ArrayRef(RegList16AVR);
1297 }
1298
1299 // GCC-ABI says that the size is rounded up to the next even number,
1300 // but actually once it is more than 4 it will always round up to 8.
1301 if (TotalBytes > 4) {
1302 TotalBytes = 8;
1303 } else {
1304 TotalBytes = alignTo(Value: TotalBytes, Align: 2);
1305 }
1306
1307 // The index of the first register to use.
1308 int RegIdx = TotalBytes - 1;
1309 for (unsigned i = 0; i != NumArgs; ++i) {
1310 MVT VT = Args[i].VT;
1311 unsigned Reg;
1312 if (VT == MVT::i8) {
1313 Reg = CCInfo.AllocateReg(Reg: RegList8[RegIdx]);
1314 } else if (VT == MVT::i16) {
1315 Reg = CCInfo.AllocateReg(Reg: RegList16[RegIdx]);
1316 } else {
1317 llvm_unreachable("calling convention can only manage i8 and i16 types");
1318 }
1319 assert(Reg && "register not available in calling convention");
1320 CCInfo.addLoc(V: CCValAssign::getReg(ValNo: i, ValVT: VT, Reg, LocVT: VT, HTP: CCValAssign::Full));
1321 // Registers sort in increasing order
1322 RegIdx -= VT.getStoreSize();
1323 }
1324}
1325
1326SDValue AVRTargetLowering::LowerFormalArguments(
1327 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1328 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1329 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1330 MachineFunction &MF = DAG.getMachineFunction();
1331 MachineFrameInfo &MFI = MF.getFrameInfo();
1332 auto DL = DAG.getDataLayout();
1333
1334 // Assign locations to all of the incoming arguments.
1335 SmallVector<CCValAssign, 16> ArgLocs;
1336 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1337 *DAG.getContext());
1338
1339 // Variadic functions do not need all the analysis below.
1340 if (isVarArg) {
1341 CCInfo.AnalyzeFormalArguments(Ins, Fn: ArgCC_AVR_Vararg);
1342 } else {
1343 analyzeArguments(CLI: nullptr, F: &MF.getFunction(), TD: &DL, Args: Ins, ArgLocs, CCInfo,
1344 Tiny: Subtarget.hasTinyEncoding());
1345 }
1346
1347 SDValue ArgValue;
1348 for (CCValAssign &VA : ArgLocs) {
1349
1350 // Arguments stored on registers.
1351 if (VA.isRegLoc()) {
1352 EVT RegVT = VA.getLocVT();
1353 const TargetRegisterClass *RC;
1354 if (RegVT == MVT::i8) {
1355 RC = &AVR::GPR8RegClass;
1356 } else if (RegVT == MVT::i16) {
1357 RC = &AVR::DREGSRegClass;
1358 } else {
1359 llvm_unreachable("Unknown argument type!");
1360 }
1361
1362 Register Reg = MF.addLiveIn(PReg: VA.getLocReg(), RC);
1363 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, VT: RegVT);
1364
1365 // :NOTE: Clang should not promote any i8 into i16 but for safety the
1366 // following code will handle zexts or sexts generated by other
1367 // front ends. Otherwise:
1368 // If this is an 8 bit value, it is really passed promoted
1369 // to 16 bits. Insert an assert[sz]ext to capture this, then
1370 // truncate to the right size.
1371 switch (VA.getLocInfo()) {
1372 default:
1373 llvm_unreachable("Unknown loc info!");
1374 case CCValAssign::Full:
1375 break;
1376 case CCValAssign::BCvt:
1377 ArgValue = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: VA.getValVT(), Operand: ArgValue);
1378 break;
1379 case CCValAssign::SExt:
1380 ArgValue = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: RegVT, N1: ArgValue,
1381 N2: DAG.getValueType(VA.getValVT()));
1382 ArgValue = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: VA.getValVT(), Operand: ArgValue);
1383 break;
1384 case CCValAssign::ZExt:
1385 ArgValue = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: RegVT, N1: ArgValue,
1386 N2: DAG.getValueType(VA.getValVT()));
1387 ArgValue = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: VA.getValVT(), Operand: ArgValue);
1388 break;
1389 }
1390
1391 InVals.push_back(Elt: ArgValue);
1392 } else {
1393 // Only arguments passed on the stack should make it here.
1394 assert(VA.isMemLoc());
1395
1396 EVT LocVT = VA.getLocVT();
1397
1398 // Create the frame index object for this incoming parameter.
1399 int FI = MFI.CreateFixedObject(Size: LocVT.getSizeInBits() / 8,
1400 SPOffset: VA.getLocMemOffset(), IsImmutable: true);
1401
1402 // Create the SelectionDAG nodes corresponding to a load
1403 // from this parameter.
1404 SDValue FIN = DAG.getFrameIndex(FI, VT: getPointerTy(DL));
1405 InVals.push_back(Elt: DAG.getLoad(VT: LocVT, dl, Chain, Ptr: FIN,
1406 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)));
1407 }
1408 }
1409
1410 // If the function takes variable number of arguments, make a frame index for
1411 // the start of the first vararg value... for expansion of llvm.va_start.
1412 if (isVarArg) {
1413 unsigned StackSize = CCInfo.getStackSize();
1414 AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1415
1416 AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(Size: 2, SPOffset: StackSize, IsImmutable: true));
1417 }
1418
1419 return Chain;
1420}
1421
1422//===----------------------------------------------------------------------===//
1423// Call Calling Convention Implementation
1424//===----------------------------------------------------------------------===//
1425
1426SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1427 SmallVectorImpl<SDValue> &InVals) const {
1428 SelectionDAG &DAG = CLI.DAG;
1429 SDLoc &DL = CLI.DL;
1430 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1431 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1432 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1433 SDValue Chain = CLI.Chain;
1434 SDValue Callee = CLI.Callee;
1435 bool &isTailCall = CLI.IsTailCall;
1436 CallingConv::ID CallConv = CLI.CallConv;
1437 bool isVarArg = CLI.IsVarArg;
1438
1439 MachineFunction &MF = DAG.getMachineFunction();
1440
1441 // AVR does not yet support tail call optimization.
1442 isTailCall = false;
1443
1444 // Analyze operands of the call, assigning locations to each operand.
1445 SmallVector<CCValAssign, 16> ArgLocs;
1446 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1447 *DAG.getContext());
1448
1449 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1450 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1451 // node so that legalize doesn't hack it.
1452 const Function *F = nullptr;
1453 if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee)) {
1454 const GlobalValue *GV = G->getGlobal();
1455 if (isa<Function>(Val: GV))
1456 F = cast<Function>(Val: GV);
1457 Callee =
1458 DAG.getTargetGlobalAddress(GV, DL, VT: getPointerTy(DL: DAG.getDataLayout()));
1459 } else if (const ExternalSymbolSDNode *ES =
1460 dyn_cast<ExternalSymbolSDNode>(Val&: Callee)) {
1461 Callee = DAG.getTargetExternalSymbol(Sym: ES->getSymbol(),
1462 VT: getPointerTy(DL: DAG.getDataLayout()));
1463 }
1464
1465 // Variadic functions do not need all the analysis below.
1466 if (isVarArg) {
1467 CCInfo.AnalyzeCallOperands(Outs, Fn: ArgCC_AVR_Vararg);
1468 } else {
1469 analyzeArguments(CLI: &CLI, F, TD: &DAG.getDataLayout(), Args: Outs, ArgLocs, CCInfo,
1470 Tiny: Subtarget.hasTinyEncoding());
1471 }
1472
1473 // Get a count of how many bytes are to be pushed on the stack.
1474 unsigned NumBytes = CCInfo.getStackSize();
1475
1476 Chain = DAG.getCALLSEQ_START(Chain, InSize: NumBytes, OutSize: 0, DL);
1477
1478 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1479
1480 // First, walk the register assignments, inserting copies.
1481 unsigned AI, AE;
1482 bool HasStackArgs = false;
1483 for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1484 CCValAssign &VA = ArgLocs[AI];
1485 EVT RegVT = VA.getLocVT();
1486 SDValue Arg = OutVals[AI];
1487
1488 // Promote the value if needed. With Clang this should not happen.
1489 switch (VA.getLocInfo()) {
1490 default:
1491 llvm_unreachable("Unknown loc info!");
1492 case CCValAssign::Full:
1493 break;
1494 case CCValAssign::SExt:
1495 Arg = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: RegVT, Operand: Arg);
1496 break;
1497 case CCValAssign::ZExt:
1498 Arg = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: RegVT, Operand: Arg);
1499 break;
1500 case CCValAssign::AExt:
1501 Arg = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: RegVT, Operand: Arg);
1502 break;
1503 case CCValAssign::BCvt:
1504 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: RegVT, Operand: Arg);
1505 break;
1506 }
1507
1508 // Stop when we encounter a stack argument, we need to process them
1509 // in reverse order in the loop below.
1510 if (VA.isMemLoc()) {
1511 HasStackArgs = true;
1512 break;
1513 }
1514
1515 // Arguments that can be passed on registers must be kept in the RegsToPass
1516 // vector.
1517 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Arg));
1518 }
1519
1520 // Second, stack arguments have to walked.
1521 // Previously this code created chained stores but those chained stores appear
1522 // to be unchained in the legalization phase. Therefore, do not attempt to
1523 // chain them here. In fact, chaining them here somehow causes the first and
1524 // second store to be reversed which is the exact opposite of the intended
1525 // effect.
1526 if (HasStackArgs) {
1527 SmallVector<SDValue, 8> MemOpChains;
1528 for (; AI != AE; AI++) {
1529 CCValAssign &VA = ArgLocs[AI];
1530 SDValue Arg = OutVals[AI];
1531
1532 assert(VA.isMemLoc());
1533
1534 // SP points to one stack slot further so add one to adjust it.
1535 SDValue PtrOff = DAG.getNode(
1536 Opcode: ISD::ADD, DL, VT: getPointerTy(DL: DAG.getDataLayout()),
1537 N1: DAG.getRegister(Reg: AVR::SP, VT: getPointerTy(DL: DAG.getDataLayout())),
1538 N2: DAG.getIntPtrConstant(Val: VA.getLocMemOffset() + 1, DL));
1539
1540 MemOpChains.push_back(
1541 Elt: DAG.getStore(Chain, dl: DL, Val: Arg, Ptr: PtrOff,
1542 PtrInfo: MachinePointerInfo::getStack(MF, Offset: VA.getLocMemOffset())));
1543 }
1544
1545 if (!MemOpChains.empty())
1546 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: MemOpChains);
1547 }
1548
1549 // Build a sequence of copy-to-reg nodes chained together with token chain and
1550 // flag operands which copy the outgoing args into registers. The InGlue in
1551 // necessary since all emited instructions must be stuck together.
1552 SDValue InGlue;
1553 for (auto Reg : RegsToPass) {
1554 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: Reg.first, N: Reg.second, Glue: InGlue);
1555 InGlue = Chain.getValue(R: 1);
1556 }
1557
1558 // Returns a chain & a flag for retval copy to use.
1559 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
1560 SmallVector<SDValue, 8> Ops;
1561 Ops.push_back(Elt: Chain);
1562 Ops.push_back(Elt: Callee);
1563
1564 // Add argument registers to the end of the list so that they are known live
1565 // into the call.
1566 for (auto Reg : RegsToPass) {
1567 Ops.push_back(Elt: DAG.getRegister(Reg: Reg.first, VT: Reg.second.getValueType()));
1568 }
1569
1570 // The zero register (usually R1) must be passed as an implicit register so
1571 // that this register is correctly zeroed in interrupts.
1572 Ops.push_back(Elt: DAG.getRegister(Reg: Subtarget.getZeroRegister(), VT: MVT::i8));
1573
1574 // Add a register mask operand representing the call-preserved registers.
1575 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1576 const uint32_t *Mask =
1577 TRI->getCallPreservedMask(MF: DAG.getMachineFunction(), CallConv);
1578 assert(Mask && "Missing call preserved mask for calling convention");
1579 Ops.push_back(Elt: DAG.getRegisterMask(RegMask: Mask));
1580
1581 if (InGlue.getNode()) {
1582 Ops.push_back(Elt: InGlue);
1583 }
1584
1585 Chain = DAG.getNode(Opcode: AVRISD::CALL, DL, VTList: NodeTys, Ops);
1586 InGlue = Chain.getValue(R: 1);
1587
1588 // Create the CALLSEQ_END node.
1589 Chain = DAG.getCALLSEQ_END(Chain, Size1: NumBytes, Size2: 0, Glue: InGlue, DL);
1590
1591 if (!Ins.empty()) {
1592 InGlue = Chain.getValue(R: 1);
1593 }
1594
1595 // Handle result values, copying them out of physregs into vregs that we
1596 // return.
1597 return LowerCallResult(Chain, InGlue, CallConv, isVarArg, Ins, dl: DL, DAG,
1598 InVals);
1599}
1600
1601/// Lower the result values of a call into the
1602/// appropriate copies out of appropriate physical registers.
1603///
1604SDValue AVRTargetLowering::LowerCallResult(
1605 SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool isVarArg,
1606 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1607 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1608
1609 // Assign locations to each value returned by this call.
1610 SmallVector<CCValAssign, 16> RVLocs;
1611 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1612 *DAG.getContext());
1613
1614 // Handle runtime calling convs.
1615 if (CallConv == CallingConv::AVR_BUILTIN) {
1616 CCInfo.AnalyzeCallResult(Ins, Fn: RetCC_AVR_BUILTIN);
1617 } else {
1618 analyzeReturnValues(Args: Ins, CCInfo, Tiny: Subtarget.hasTinyEncoding());
1619 }
1620
1621 // Copy all of the result registers out of their specified physreg.
1622 for (CCValAssign const &RVLoc : RVLocs) {
1623 Chain = DAG.getCopyFromReg(Chain, dl, Reg: RVLoc.getLocReg(), VT: RVLoc.getValVT(),
1624 Glue: InGlue)
1625 .getValue(R: 1);
1626 InGlue = Chain.getValue(R: 2);
1627 InVals.push_back(Elt: Chain.getValue(R: 0));
1628 }
1629
1630 return Chain;
1631}
1632
1633//===----------------------------------------------------------------------===//
1634// Return Value Calling Convention Implementation
1635//===----------------------------------------------------------------------===//
1636
1637bool AVRTargetLowering::CanLowerReturn(
1638 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
1639 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
1640 const Type *RetTy) const {
1641 if (CallConv == CallingConv::AVR_BUILTIN) {
1642 SmallVector<CCValAssign, 16> RVLocs;
1643 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1644 return CCInfo.CheckReturn(Outs, Fn: RetCC_AVR_BUILTIN);
1645 }
1646
1647 unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args: Outs);
1648 return TotalBytes <= (unsigned)(Subtarget.hasTinyEncoding() ? 4 : 8);
1649}
1650
1651SDValue
1652AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1653 bool isVarArg,
1654 const SmallVectorImpl<ISD::OutputArg> &Outs,
1655 const SmallVectorImpl<SDValue> &OutVals,
1656 const SDLoc &dl, SelectionDAG &DAG) const {
1657 // CCValAssign - represent the assignment of the return value to locations.
1658 SmallVector<CCValAssign, 16> RVLocs;
1659
1660 // CCState - Info about the registers and stack slot.
1661 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1662 *DAG.getContext());
1663
1664 MachineFunction &MF = DAG.getMachineFunction();
1665
1666 // Analyze return values.
1667 if (CallConv == CallingConv::AVR_BUILTIN) {
1668 CCInfo.AnalyzeReturn(Outs, Fn: RetCC_AVR_BUILTIN);
1669 } else {
1670 analyzeReturnValues(Args: Outs, CCInfo, Tiny: Subtarget.hasTinyEncoding());
1671 }
1672
1673 SDValue Glue;
1674 SmallVector<SDValue, 4> RetOps(1, Chain);
1675 // Copy the result values into the output registers.
1676 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1677 CCValAssign &VA = RVLocs[i];
1678 assert(VA.isRegLoc() && "Can only return in registers!");
1679
1680 Chain = DAG.getCopyToReg(Chain, dl, Reg: VA.getLocReg(), N: OutVals[i], Glue);
1681
1682 // Guarantee that all emitted copies are stuck together with flags.
1683 Glue = Chain.getValue(R: 1);
1684 RetOps.push_back(Elt: DAG.getRegister(Reg: VA.getLocReg(), VT: VA.getLocVT()));
1685 }
1686
1687 // Don't emit the ret/reti instruction when the naked attribute is present in
1688 // the function being compiled.
1689 if (MF.getFunction().getAttributes().hasFnAttr(Kind: Attribute::Naked)) {
1690 return Chain;
1691 }
1692
1693 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1694
1695 if (!AFI->isInterruptOrSignalHandler()) {
1696 // The return instruction has an implicit zero register operand: it must
1697 // contain zero on return.
1698 // This is not needed in interrupts however, where the zero register is
1699 // handled specially (only pushed/popped when needed).
1700 RetOps.push_back(Elt: DAG.getRegister(Reg: Subtarget.getZeroRegister(), VT: MVT::i8));
1701 }
1702
1703 unsigned RetOpc =
1704 AFI->isInterruptOrSignalHandler() ? AVRISD::RETI_GLUE : AVRISD::RET_GLUE;
1705
1706 RetOps[0] = Chain; // Update chain.
1707
1708 if (Glue.getNode()) {
1709 RetOps.push_back(Elt: Glue);
1710 }
1711
1712 return DAG.getNode(Opcode: RetOpc, DL: dl, VT: MVT::Other, Ops: RetOps);
1713}
1714
1715//===----------------------------------------------------------------------===//
1716// Custom Inserters
1717//===----------------------------------------------------------------------===//
1718
1719MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
1720 MachineBasicBlock *BB,
1721 bool Tiny) const {
1722 unsigned Opc;
1723 const TargetRegisterClass *RC;
1724 bool HasRepeatedOperand = false;
1725 MachineFunction *F = BB->getParent();
1726 MachineRegisterInfo &RI = F->getRegInfo();
1727 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1728 DebugLoc dl = MI.getDebugLoc();
1729
1730 switch (MI.getOpcode()) {
1731 default:
1732 llvm_unreachable("Invalid shift opcode!");
1733 case AVR::Lsl8:
1734 Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd
1735 RC = &AVR::GPR8RegClass;
1736 HasRepeatedOperand = true;
1737 break;
1738 case AVR::Lsl16:
1739 Opc = AVR::LSLWRd;
1740 RC = &AVR::DREGSRegClass;
1741 break;
1742 case AVR::Asr8:
1743 Opc = AVR::ASRRd;
1744 RC = &AVR::GPR8RegClass;
1745 break;
1746 case AVR::Asr16:
1747 Opc = AVR::ASRWRd;
1748 RC = &AVR::DREGSRegClass;
1749 break;
1750 case AVR::Lsr8:
1751 Opc = AVR::LSRRd;
1752 RC = &AVR::GPR8RegClass;
1753 break;
1754 case AVR::Lsr16:
1755 Opc = AVR::LSRWRd;
1756 RC = &AVR::DREGSRegClass;
1757 break;
1758 case AVR::Rol8:
1759 Opc = Tiny ? AVR::ROLBRdR17 : AVR::ROLBRdR1;
1760 RC = &AVR::GPR8RegClass;
1761 break;
1762 case AVR::Rol16:
1763 Opc = AVR::ROLWRd;
1764 RC = &AVR::DREGSRegClass;
1765 break;
1766 case AVR::Ror8:
1767 Opc = AVR::RORBRd;
1768 RC = &AVR::GPR8RegClass;
1769 break;
1770 case AVR::Ror16:
1771 Opc = AVR::RORWRd;
1772 RC = &AVR::DREGSRegClass;
1773 break;
1774 }
1775
1776 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1777
1778 MachineFunction::iterator I;
1779 for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I)
1780 ;
1781 if (I != F->end())
1782 ++I;
1783
1784 // Create loop block.
1785 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
1786 MachineBasicBlock *CheckBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
1787 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
1788
1789 F->insert(MBBI: I, MBB: LoopBB);
1790 F->insert(MBBI: I, MBB: CheckBB);
1791 F->insert(MBBI: I, MBB: RemBB);
1792
1793 // Update machine-CFG edges by transferring all successors of the current
1794 // block to the block containing instructions after shift.
1795 RemBB->splice(Where: RemBB->begin(), Other: BB, From: std::next(x: MachineBasicBlock::iterator(MI)),
1796 To: BB->end());
1797 RemBB->transferSuccessorsAndUpdatePHIs(FromMBB: BB);
1798
1799 // Add edges BB => LoopBB => CheckBB => RemBB, CheckBB => LoopBB.
1800 BB->addSuccessor(Succ: CheckBB);
1801 LoopBB->addSuccessor(Succ: CheckBB);
1802 CheckBB->addSuccessor(Succ: LoopBB);
1803 CheckBB->addSuccessor(Succ: RemBB);
1804
1805 Register ShiftAmtReg = RI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
1806 Register ShiftAmtReg2 = RI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
1807 Register ShiftReg = RI.createVirtualRegister(RegClass: RC);
1808 Register ShiftReg2 = RI.createVirtualRegister(RegClass: RC);
1809 Register ShiftAmtSrcReg = MI.getOperand(i: 2).getReg();
1810 Register SrcReg = MI.getOperand(i: 1).getReg();
1811 Register DstReg = MI.getOperand(i: 0).getReg();
1812
1813 // BB:
1814 // rjmp CheckBB
1815 BuildMI(BB, MIMD: dl, MCID: TII.get(Opcode: AVR::RJMPk)).addMBB(MBB: CheckBB);
1816
1817 // LoopBB:
1818 // ShiftReg2 = shift ShiftReg
1819 auto ShiftMI = BuildMI(BB: LoopBB, MIMD: dl, MCID: TII.get(Opcode: Opc), DestReg: ShiftReg2).addReg(RegNo: ShiftReg);
1820 if (HasRepeatedOperand)
1821 ShiftMI.addReg(RegNo: ShiftReg);
1822
1823 // CheckBB:
1824 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1825 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1826 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1827 // ShiftAmt2 = ShiftAmt - 1;
1828 // if (ShiftAmt2 >= 0) goto LoopBB;
1829 BuildMI(BB: CheckBB, MIMD: dl, MCID: TII.get(Opcode: AVR::PHI), DestReg: ShiftReg)
1830 .addReg(RegNo: SrcReg)
1831 .addMBB(MBB: BB)
1832 .addReg(RegNo: ShiftReg2)
1833 .addMBB(MBB: LoopBB);
1834 BuildMI(BB: CheckBB, MIMD: dl, MCID: TII.get(Opcode: AVR::PHI), DestReg: ShiftAmtReg)
1835 .addReg(RegNo: ShiftAmtSrcReg)
1836 .addMBB(MBB: BB)
1837 .addReg(RegNo: ShiftAmtReg2)
1838 .addMBB(MBB: LoopBB);
1839 BuildMI(BB: CheckBB, MIMD: dl, MCID: TII.get(Opcode: AVR::PHI), DestReg: DstReg)
1840 .addReg(RegNo: SrcReg)
1841 .addMBB(MBB: BB)
1842 .addReg(RegNo: ShiftReg2)
1843 .addMBB(MBB: LoopBB);
1844
1845 BuildMI(BB: CheckBB, MIMD: dl, MCID: TII.get(Opcode: AVR::DECRd), DestReg: ShiftAmtReg2).addReg(RegNo: ShiftAmtReg);
1846 BuildMI(BB: CheckBB, MIMD: dl, MCID: TII.get(Opcode: AVR::BRPLk)).addMBB(MBB: LoopBB);
1847
1848 MI.eraseFromParent(); // The pseudo instruction is gone now.
1849 return RemBB;
1850}
1851
1852// Do a multibyte AVR shift. Insert shift instructions and put the output
1853// registers in the Regs array.
1854// Because AVR does not have a normal shift instruction (only a single bit shift
1855// instruction), we have to emulate this behavior with other instructions.
1856// It first tries large steps (moving registers around) and then smaller steps
1857// like single bit shifts.
1858// Large shifts actually reduce the number of shifted registers, so the below
1859// algorithms have to work independently of the number of registers that are
1860// shifted.
1861// For more information and background, see this blogpost:
1862// https://aykevl.nl/2021/02/avr-bitshift
1863static void insertMultibyteShift(MachineInstr &MI, MachineBasicBlock *BB,
1864 MutableArrayRef<std::pair<Register, int>> Regs,
1865 ISD::NodeType Opc, int64_t ShiftAmt) {
1866 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
1867 const AVRSubtarget &STI = BB->getParent()->getSubtarget<AVRSubtarget>();
1868 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
1869 const DebugLoc &dl = MI.getDebugLoc();
1870
1871 const bool ShiftLeft = Opc == ISD::SHL;
1872 const bool ArithmeticShift = Opc == ISD::SRA;
1873
1874 // Zero a register, for use in later operations.
1875 Register ZeroReg = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
1876 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::COPY), DestReg: ZeroReg)
1877 .addReg(RegNo: STI.getZeroRegister());
1878
1879 // Do a shift modulo 6 or 7. This is a bit more complicated than most shifts
1880 // and is hard to compose with the rest, so these are special cased.
1881 // The basic idea is to shift one or two bits in the opposite direction and
1882 // then move registers around to get the correct end result.
1883 if (ShiftLeft && (ShiftAmt % 8) >= 6) {
1884 // Left shift modulo 6 or 7.
1885
1886 // Create a slice of the registers we're going to modify, to ease working
1887 // with them.
1888 size_t ShiftRegsOffset = ShiftAmt / 8;
1889 size_t ShiftRegsSize = Regs.size() - ShiftRegsOffset;
1890 MutableArrayRef<std::pair<Register, int>> ShiftRegs =
1891 Regs.slice(N: ShiftRegsOffset, M: ShiftRegsSize);
1892
1893 // Shift one to the right, keeping the least significant bit as the carry
1894 // bit.
1895 insertMultibyteShift(MI, BB, Regs: ShiftRegs, Opc: ISD::SRL, ShiftAmt: 1);
1896
1897 // Rotate the least significant bit from the carry bit into a new register
1898 // (that starts out zero).
1899 Register LowByte = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
1900 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::RORRd), DestReg: LowByte).addReg(RegNo: ZeroReg);
1901
1902 // Shift one more to the right if this is a modulo-6 shift.
1903 if (ShiftAmt % 8 == 6) {
1904 insertMultibyteShift(MI, BB, Regs: ShiftRegs, Opc: ISD::SRL, ShiftAmt: 1);
1905 Register NewLowByte = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
1906 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::RORRd), DestReg: NewLowByte).addReg(RegNo: LowByte);
1907 LowByte = NewLowByte;
1908 }
1909
1910 // Move all registers to the left, zeroing the bottom registers as needed.
1911 for (size_t I = 0; I < Regs.size(); I++) {
1912 int ShiftRegsIdx = I + 1;
1913 if (ShiftRegsIdx < (int)ShiftRegs.size()) {
1914 Regs[I] = ShiftRegs[ShiftRegsIdx];
1915 } else if (ShiftRegsIdx == (int)ShiftRegs.size()) {
1916 Regs[I] = std::pair(LowByte, 0);
1917 } else {
1918 Regs[I] = std::pair(ZeroReg, 0);
1919 }
1920 }
1921
1922 return;
1923 }
1924
1925 // Right shift modulo 6 or 7.
1926 if (!ShiftLeft && (ShiftAmt % 8) >= 6) {
1927 // Create a view on the registers we're going to modify, to ease working
1928 // with them.
1929 size_t ShiftRegsSize = Regs.size() - (ShiftAmt / 8);
1930 MutableArrayRef<std::pair<Register, int>> ShiftRegs =
1931 Regs.slice(N: 0, M: ShiftRegsSize);
1932
1933 // Shift one to the left.
1934 insertMultibyteShift(MI, BB, Regs: ShiftRegs, Opc: ISD::SHL, ShiftAmt: 1);
1935
1936 // Sign or zero extend the most significant register into a new register.
1937 // The HighByte is the byte that still has one (or two) bits from the
1938 // original value. The ExtByte is purely a zero/sign extend byte (all bits
1939 // are either 0 or 1).
1940 Register HighByte = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
1941 Register ExtByte = 0;
1942 if (ArithmeticShift) {
1943 // Sign-extend bit that was shifted out last.
1944 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::SBCRdRr), DestReg: HighByte)
1945 .addReg(RegNo: HighByte, Flags: RegState::Undef)
1946 .addReg(RegNo: HighByte, Flags: RegState::Undef);
1947 ExtByte = HighByte;
1948 // The highest bit of the original value is the same as the zero-extend
1949 // byte, so HighByte and ExtByte are the same.
1950 } else {
1951 // Use the zero register for zero extending.
1952 ExtByte = ZeroReg;
1953 // Rotate most significant bit into a new register (that starts out zero).
1954 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::ADCRdRr), DestReg: HighByte)
1955 .addReg(RegNo: ExtByte)
1956 .addReg(RegNo: ExtByte);
1957 }
1958
1959 // Shift one more to the left for modulo 6 shifts.
1960 if (ShiftAmt % 8 == 6) {
1961 insertMultibyteShift(MI, BB, Regs: ShiftRegs, Opc: ISD::SHL, ShiftAmt: 1);
1962 // Shift the topmost bit into the HighByte.
1963 Register NewExt = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
1964 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::ADCRdRr), DestReg: NewExt)
1965 .addReg(RegNo: HighByte)
1966 .addReg(RegNo: HighByte);
1967 HighByte = NewExt;
1968 }
1969
1970 // Move all to the right, while sign or zero extending.
1971 for (int I = Regs.size() - 1; I >= 0; I--) {
1972 int ShiftRegsIdx = I - (Regs.size() - ShiftRegs.size()) - 1;
1973 if (ShiftRegsIdx >= 0) {
1974 Regs[I] = ShiftRegs[ShiftRegsIdx];
1975 } else if (ShiftRegsIdx == -1) {
1976 Regs[I] = std::pair(HighByte, 0);
1977 } else {
1978 Regs[I] = std::pair(ExtByte, 0);
1979 }
1980 }
1981
1982 return;
1983 }
1984
1985 // For shift amounts of at least one register, simply rename the registers and
1986 // zero the bottom registers.
1987 while (ShiftLeft && ShiftAmt >= 8) {
1988 // Move all registers one to the left.
1989 for (size_t I = 0; I < Regs.size() - 1; I++) {
1990 Regs[I] = Regs[I + 1];
1991 }
1992
1993 // Zero the least significant register.
1994 Regs[Regs.size() - 1] = std::pair(ZeroReg, 0);
1995
1996 // Continue shifts with the leftover registers.
1997 Regs = Regs.drop_back(N: 1);
1998
1999 ShiftAmt -= 8;
2000 }
2001
2002 // And again, the same for right shifts.
2003 Register ShrExtendReg = 0;
2004 if (!ShiftLeft && ShiftAmt >= 8) {
2005 if (ArithmeticShift) {
2006 // Sign extend the most significant register into ShrExtendReg.
2007 ShrExtendReg = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
2008 Register Tmp = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
2009 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::ADDRdRr), DestReg: Tmp)
2010 .addReg(RegNo: Regs[0].first, Flags: {}, SubReg: Regs[0].second)
2011 .addReg(RegNo: Regs[0].first, Flags: {}, SubReg: Regs[0].second);
2012 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::SBCRdRr), DestReg: ShrExtendReg)
2013 .addReg(RegNo: Tmp)
2014 .addReg(RegNo: Tmp);
2015 } else {
2016 ShrExtendReg = ZeroReg;
2017 }
2018 for (; ShiftAmt >= 8; ShiftAmt -= 8) {
2019 // Move all registers one to the right.
2020 for (size_t I = Regs.size() - 1; I != 0; I--) {
2021 Regs[I] = Regs[I - 1];
2022 }
2023
2024 // Zero or sign extend the most significant register.
2025 Regs[0] = std::pair(ShrExtendReg, 0);
2026
2027 // Continue shifts with the leftover registers.
2028 Regs = Regs.drop_front(N: 1);
2029 }
2030 }
2031
2032 // The bigger shifts are already handled above.
2033 assert((ShiftAmt < 8) && "Unexpect shift amount");
2034
2035 // Shift by four bits, using a complicated swap/eor/andi/eor sequence.
2036 // It only works for logical shifts because the bits shifted in are all
2037 // zeroes.
2038 // To shift a single byte right, it produces code like this:
2039 // swap r0
2040 // andi r0, 0x0f
2041 // For a two-byte (16-bit) shift, it adds the following instructions to shift
2042 // the upper byte into the lower byte:
2043 // swap r1
2044 // eor r0, r1
2045 // andi r1, 0x0f
2046 // eor r0, r1
2047 // For bigger shifts, it repeats the above sequence. For example, for a 3-byte
2048 // (24-bit) shift it adds:
2049 // swap r2
2050 // eor r1, r2
2051 // andi r2, 0x0f
2052 // eor r1, r2
2053 if (!ArithmeticShift && ShiftAmt >= 4) {
2054 Register Prev = 0;
2055 for (size_t I = 0; I < Regs.size(); I++) {
2056 size_t Idx = ShiftLeft ? I : Regs.size() - I - 1;
2057 Register SwapReg = MRI.createVirtualRegister(RegClass: &AVR::LD8RegClass);
2058 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::SWAPRd), DestReg: SwapReg)
2059 .addReg(RegNo: Regs[Idx].first, Flags: {}, SubReg: Regs[Idx].second);
2060 if (I != 0) {
2061 Register R = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
2062 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::EORRdRr), DestReg: R)
2063 .addReg(RegNo: Prev)
2064 .addReg(RegNo: SwapReg);
2065 Prev = R;
2066 }
2067 Register AndReg = MRI.createVirtualRegister(RegClass: &AVR::LD8RegClass);
2068 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::ANDIRdK), DestReg: AndReg)
2069 .addReg(RegNo: SwapReg)
2070 .addImm(Val: ShiftLeft ? 0xf0 : 0x0f);
2071 if (I != 0) {
2072 Register R = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
2073 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::EORRdRr), DestReg: R)
2074 .addReg(RegNo: Prev)
2075 .addReg(RegNo: AndReg);
2076 size_t PrevIdx = ShiftLeft ? Idx - 1 : Idx + 1;
2077 Regs[PrevIdx] = std::pair(R, 0);
2078 }
2079 Prev = AndReg;
2080 Regs[Idx] = std::pair(AndReg, 0);
2081 }
2082 ShiftAmt -= 4;
2083 }
2084
2085 // Shift by one. This is the fallback that always works, and the shift
2086 // operation that is used for 1, 2, and 3 bit shifts.
2087 while (ShiftLeft && ShiftAmt) {
2088 // Shift one to the left.
2089 for (ssize_t I = Regs.size() - 1; I >= 0; I--) {
2090 Register Out = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
2091 Register In = Regs[I].first;
2092 Register InSubreg = Regs[I].second;
2093 if (I == (ssize_t)Regs.size() - 1) { // first iteration
2094 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::ADDRdRr), DestReg: Out)
2095 .addReg(RegNo: In, Flags: {}, SubReg: InSubreg)
2096 .addReg(RegNo: In, Flags: {}, SubReg: InSubreg);
2097 } else {
2098 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::ADCRdRr), DestReg: Out)
2099 .addReg(RegNo: In, Flags: {}, SubReg: InSubreg)
2100 .addReg(RegNo: In, Flags: {}, SubReg: InSubreg);
2101 }
2102 Regs[I] = std::pair(Out, 0);
2103 }
2104 ShiftAmt--;
2105 }
2106 while (!ShiftLeft && ShiftAmt) {
2107 // Shift one to the right.
2108 for (size_t I = 0; I < Regs.size(); I++) {
2109 Register Out = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
2110 Register In = Regs[I].first;
2111 Register InSubreg = Regs[I].second;
2112 if (I == 0) {
2113 unsigned Opc = ArithmeticShift ? AVR::ASRRd : AVR::LSRRd;
2114 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: Opc), DestReg: Out).addReg(RegNo: In, Flags: {}, SubReg: InSubreg);
2115 } else {
2116 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::RORRd), DestReg: Out).addReg(RegNo: In, Flags: {}, SubReg: InSubreg);
2117 }
2118 Regs[I] = std::pair(Out, 0);
2119 }
2120 ShiftAmt--;
2121 }
2122
2123 if (ShiftAmt != 0) {
2124 llvm_unreachable("don't know how to shift!"); // sanity check
2125 }
2126}
2127
2128// Do a wide (32-bit) shift.
2129MachineBasicBlock *
2130AVRTargetLowering::insertWideShift(MachineInstr &MI,
2131 MachineBasicBlock *BB) const {
2132 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2133 const DebugLoc &dl = MI.getDebugLoc();
2134
2135 // How much to shift to the right (meaning: a negative number indicates a left
2136 // shift).
2137 int64_t ShiftAmt = MI.getOperand(i: 4).getImm();
2138 ISD::NodeType Opc;
2139 switch (MI.getOpcode()) {
2140 case AVR::Lsl32:
2141 Opc = ISD::SHL;
2142 break;
2143 case AVR::Lsr32:
2144 Opc = ISD::SRL;
2145 break;
2146 case AVR::Asr32:
2147 Opc = ISD::SRA;
2148 break;
2149 }
2150
2151 // Read the input registers, with the most significant register at index 0.
2152 std::array<std::pair<Register, int>, 4> Registers = {
2153 std::pair(MI.getOperand(i: 3).getReg(), AVR::sub_hi),
2154 std::pair(MI.getOperand(i: 3).getReg(), AVR::sub_lo),
2155 std::pair(MI.getOperand(i: 2).getReg(), AVR::sub_hi),
2156 std::pair(MI.getOperand(i: 2).getReg(), AVR::sub_lo),
2157 };
2158
2159 // Do the shift. The registers are modified in-place.
2160 insertMultibyteShift(MI, BB, Regs: Registers, Opc, ShiftAmt);
2161
2162 // Combine the 8-bit registers into 16-bit register pairs.
2163 // This done either from LSB to MSB or from MSB to LSB, depending on the
2164 // shift. It's an optimization so that the register allocator will use the
2165 // fewest movs possible (which order we use isn't a correctness issue, just an
2166 // optimization issue).
2167 // - lsl prefers starting from the most significant byte (2nd case).
2168 // - lshr prefers starting from the least significant byte (1st case).
2169 // - for ashr it depends on the number of shifted bytes.
2170 // Some shift operations still don't get the most optimal mov sequences even
2171 // with this distinction. TODO: figure out why and try to fix it (but we're
2172 // already equal to or faster than avr-gcc in all cases except ashr 8).
2173 if (Opc != ISD::SHL &&
2174 (Opc != ISD::SRA || (ShiftAmt < 16 || ShiftAmt >= 22))) {
2175 // Use the resulting registers starting with the least significant byte.
2176 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::REG_SEQUENCE), DestReg: MI.getOperand(i: 0).getReg())
2177 .addReg(RegNo: Registers[3].first, Flags: {}, SubReg: Registers[3].second)
2178 .addImm(Val: AVR::sub_lo)
2179 .addReg(RegNo: Registers[2].first, Flags: {}, SubReg: Registers[2].second)
2180 .addImm(Val: AVR::sub_hi);
2181 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::REG_SEQUENCE), DestReg: MI.getOperand(i: 1).getReg())
2182 .addReg(RegNo: Registers[1].first, Flags: {}, SubReg: Registers[1].second)
2183 .addImm(Val: AVR::sub_lo)
2184 .addReg(RegNo: Registers[0].first, Flags: {}, SubReg: Registers[0].second)
2185 .addImm(Val: AVR::sub_hi);
2186 } else {
2187 // Use the resulting registers starting with the most significant byte.
2188 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::REG_SEQUENCE), DestReg: MI.getOperand(i: 1).getReg())
2189 .addReg(RegNo: Registers[0].first, Flags: {}, SubReg: Registers[0].second)
2190 .addImm(Val: AVR::sub_hi)
2191 .addReg(RegNo: Registers[1].first, Flags: {}, SubReg: Registers[1].second)
2192 .addImm(Val: AVR::sub_lo);
2193 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::REG_SEQUENCE), DestReg: MI.getOperand(i: 0).getReg())
2194 .addReg(RegNo: Registers[2].first, Flags: {}, SubReg: Registers[2].second)
2195 .addImm(Val: AVR::sub_hi)
2196 .addReg(RegNo: Registers[3].first, Flags: {}, SubReg: Registers[3].second)
2197 .addImm(Val: AVR::sub_lo);
2198 }
2199
2200 // Remove the pseudo instruction.
2201 MI.eraseFromParent();
2202 return BB;
2203}
2204
2205static bool isCopyMulResult(MachineBasicBlock::iterator const &I) {
2206 if (I->getOpcode() == AVR::COPY) {
2207 Register SrcReg = I->getOperand(i: 1).getReg();
2208 return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
2209 }
2210
2211 return false;
2212}
2213
2214// The mul instructions wreak havock on our zero_reg R1. We need to clear it
2215// after the result has been evacuated. This is probably not the best way to do
2216// it, but it works for now.
2217MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
2218 MachineBasicBlock *BB) const {
2219 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2220 MachineBasicBlock::iterator I(MI);
2221 ++I; // in any case insert *after* the mul instruction
2222 if (isCopyMulResult(I))
2223 ++I;
2224 if (isCopyMulResult(I))
2225 ++I;
2226 BuildMI(BB&: *BB, I, MIMD: MI.getDebugLoc(), MCID: TII.get(Opcode: AVR::EORRdRr), DestReg: AVR::R1)
2227 .addReg(RegNo: AVR::R1)
2228 .addReg(RegNo: AVR::R1);
2229 return BB;
2230}
2231
2232// Insert a read from the zero register.
2233MachineBasicBlock *
2234AVRTargetLowering::insertCopyZero(MachineInstr &MI,
2235 MachineBasicBlock *BB) const {
2236 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2237 MachineBasicBlock::iterator I(MI);
2238 BuildMI(BB&: *BB, I, MIMD: MI.getDebugLoc(), MCID: TII.get(Opcode: AVR::COPY))
2239 .add(MO: MI.getOperand(i: 0))
2240 .addReg(RegNo: Subtarget.getZeroRegister());
2241 MI.eraseFromParent();
2242 return BB;
2243}
2244
2245// Lower atomicrmw operation to disable interrupts, do operation, and restore
2246// interrupts. This works because all AVR microcontrollers are single core.
2247MachineBasicBlock *AVRTargetLowering::insertAtomicArithmeticOp(
2248 MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode, int Width) const {
2249 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
2250 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2251 MachineBasicBlock::iterator I(MI);
2252 DebugLoc dl = MI.getDebugLoc();
2253
2254 // Example instruction sequence, for an atomic 8-bit add:
2255 // ldi r25, 5
2256 // in r0, SREG
2257 // cli
2258 // ld r24, X
2259 // add r25, r24
2260 // st X, r25
2261 // out SREG, r0
2262
2263 const TargetRegisterClass *RC =
2264 (Width == 8) ? &AVR::GPR8RegClass : &AVR::DREGSRegClass;
2265 unsigned LoadOpcode = (Width == 8) ? AVR::LDRdPtr : AVR::LDWRdPtr;
2266 unsigned StoreOpcode = (Width == 8) ? AVR::STPtrRr : AVR::STWPtrRr;
2267
2268 // Disable interrupts.
2269 BuildMI(BB&: *BB, I, MIMD: dl, MCID: TII.get(Opcode: AVR::INRdA), DestReg: Subtarget.getTmpRegister())
2270 .addImm(Val: Subtarget.getIORegSREG());
2271 BuildMI(BB&: *BB, I, MIMD: dl, MCID: TII.get(Opcode: AVR::BCLRs)).addImm(Val: 7);
2272
2273 // Load the original value.
2274 BuildMI(BB&: *BB, I, MIMD: dl, MCID: TII.get(Opcode: LoadOpcode), DestReg: MI.getOperand(i: 0).getReg())
2275 .add(MO: MI.getOperand(i: 1));
2276
2277 // Do the arithmetic operation.
2278 Register Result = MRI.createVirtualRegister(RegClass: RC);
2279 BuildMI(BB&: *BB, I, MIMD: dl, MCID: TII.get(Opcode), DestReg: Result)
2280 .addReg(RegNo: MI.getOperand(i: 0).getReg())
2281 .add(MO: MI.getOperand(i: 2));
2282
2283 // Store the result.
2284 BuildMI(BB&: *BB, I, MIMD: dl, MCID: TII.get(Opcode: StoreOpcode))
2285 .add(MO: MI.getOperand(i: 1))
2286 .addReg(RegNo: Result);
2287
2288 // Restore interrupts.
2289 BuildMI(BB&: *BB, I, MIMD: dl, MCID: TII.get(Opcode: AVR::OUTARr))
2290 .addImm(Val: Subtarget.getIORegSREG())
2291 .addReg(RegNo: Subtarget.getTmpRegister());
2292
2293 // Remove the pseudo instruction.
2294 MI.eraseFromParent();
2295 return BB;
2296}
2297
2298MachineBasicBlock *
2299AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
2300 MachineBasicBlock *MBB) const {
2301 int Opc = MI.getOpcode();
2302 const AVRSubtarget &STI = MBB->getParent()->getSubtarget<AVRSubtarget>();
2303
2304 // Pseudo shift instructions with a non constant shift amount are expanded
2305 // into a loop.
2306 switch (Opc) {
2307 case AVR::Lsl8:
2308 case AVR::Lsl16:
2309 case AVR::Lsr8:
2310 case AVR::Lsr16:
2311 case AVR::Rol8:
2312 case AVR::Rol16:
2313 case AVR::Ror8:
2314 case AVR::Ror16:
2315 case AVR::Asr8:
2316 case AVR::Asr16:
2317 return insertShift(MI, BB: MBB, Tiny: STI.hasTinyEncoding());
2318 case AVR::Lsl32:
2319 case AVR::Lsr32:
2320 case AVR::Asr32:
2321 return insertWideShift(MI, BB: MBB);
2322 case AVR::MULRdRr:
2323 case AVR::MULSRdRr:
2324 return insertMul(MI, BB: MBB);
2325 case AVR::CopyZero:
2326 return insertCopyZero(MI, BB: MBB);
2327 case AVR::AtomicLoadAdd8:
2328 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::ADDRdRr, Width: 8);
2329 case AVR::AtomicLoadAdd16:
2330 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::ADDWRdRr, Width: 16);
2331 case AVR::AtomicLoadSub8:
2332 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::SUBRdRr, Width: 8);
2333 case AVR::AtomicLoadSub16:
2334 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::SUBWRdRr, Width: 16);
2335 case AVR::AtomicLoadAnd8:
2336 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::ANDRdRr, Width: 8);
2337 case AVR::AtomicLoadAnd16:
2338 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::ANDWRdRr, Width: 16);
2339 case AVR::AtomicLoadOr8:
2340 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::ORRdRr, Width: 8);
2341 case AVR::AtomicLoadOr16:
2342 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::ORWRdRr, Width: 16);
2343 case AVR::AtomicLoadXor8:
2344 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::EORRdRr, Width: 8);
2345 case AVR::AtomicLoadXor16:
2346 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::EORWRdRr, Width: 16);
2347 }
2348
2349 assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&
2350 "Unexpected instr type to insert");
2351
2352 const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
2353 ->getParent()
2354 ->getSubtarget()
2355 .getInstrInfo();
2356 DebugLoc dl = MI.getDebugLoc();
2357
2358 // To "insert" a SELECT instruction, we insert the diamond
2359 // control-flow pattern. The incoming instruction knows the
2360 // destination vreg to set, the condition code register to branch
2361 // on, the true/false values to select between, and a branch opcode
2362 // to use.
2363
2364 MachineFunction *MF = MBB->getParent();
2365 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
2366 MachineBasicBlock *FallThrough = MBB->getFallThrough();
2367
2368 // If the current basic block falls through to another basic block,
2369 // we must insert an unconditional branch to the fallthrough destination
2370 // if we are to insert basic blocks at the prior fallthrough point.
2371 if (FallThrough != nullptr) {
2372 BuildMI(BB: MBB, MIMD: dl, MCID: TII.get(Opcode: AVR::RJMPk)).addMBB(MBB: FallThrough);
2373 }
2374
2375 MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(BB: LLVM_BB);
2376 MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(BB: LLVM_BB);
2377
2378 MachineFunction::iterator I;
2379 for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I)
2380 ;
2381 if (I != MF->end())
2382 ++I;
2383 MF->insert(MBBI: I, MBB: trueMBB);
2384 MF->insert(MBBI: I, MBB: falseMBB);
2385
2386 // Set the call frame size on entry to the new basic blocks.
2387 unsigned CallFrameSize = TII.getCallFrameSizeAt(MI);
2388 trueMBB->setCallFrameSize(CallFrameSize);
2389 falseMBB->setCallFrameSize(CallFrameSize);
2390
2391 // Transfer remaining instructions and all successors of the current
2392 // block to the block which will contain the Phi node for the
2393 // select.
2394 trueMBB->splice(Where: trueMBB->begin(), Other: MBB,
2395 From: std::next(x: MachineBasicBlock::iterator(MI)), To: MBB->end());
2396 trueMBB->transferSuccessorsAndUpdatePHIs(FromMBB: MBB);
2397
2398 AVRCC::CondCodes CC = (AVRCC::CondCodes)MI.getOperand(i: 3).getImm();
2399 BuildMI(BB: MBB, MIMD: dl, MCID: TII.getBrCond(CC)).addMBB(MBB: trueMBB);
2400 BuildMI(BB: MBB, MIMD: dl, MCID: TII.get(Opcode: AVR::RJMPk)).addMBB(MBB: falseMBB);
2401 MBB->addSuccessor(Succ: falseMBB);
2402 MBB->addSuccessor(Succ: trueMBB);
2403
2404 // Unconditionally flow back to the true block
2405 BuildMI(BB: falseMBB, MIMD: dl, MCID: TII.get(Opcode: AVR::RJMPk)).addMBB(MBB: trueMBB);
2406 falseMBB->addSuccessor(Succ: trueMBB);
2407
2408 // Set up the Phi node to determine where we came from
2409 BuildMI(BB&: *trueMBB, I: trueMBB->begin(), MIMD: dl, MCID: TII.get(Opcode: AVR::PHI),
2410 DestReg: MI.getOperand(i: 0).getReg())
2411 .addReg(RegNo: MI.getOperand(i: 1).getReg())
2412 .addMBB(MBB)
2413 .addReg(RegNo: MI.getOperand(i: 2).getReg())
2414 .addMBB(MBB: falseMBB);
2415
2416 MI.eraseFromParent(); // The pseudo instruction is gone now.
2417 return trueMBB;
2418}
2419
2420//===----------------------------------------------------------------------===//
2421// Inline Asm Support
2422//===----------------------------------------------------------------------===//
2423
2424AVRTargetLowering::ConstraintType
2425AVRTargetLowering::getConstraintType(StringRef Constraint) const {
2426 if (Constraint.size() == 1) {
2427 // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
2428 switch (Constraint[0]) {
2429 default:
2430 break;
2431 case 'a': // Simple upper registers
2432 case 'b': // Base pointer registers pairs
2433 case 'd': // Upper register
2434 case 'l': // Lower registers
2435 case 'e': // Pointer register pairs
2436 case 'q': // Stack pointer register
2437 case 'r': // Any register
2438 case 'w': // Special upper register pairs
2439 return C_RegisterClass;
2440 case 't': // Temporary register
2441 case 'x':
2442 case 'X': // Pointer register pair X
2443 case 'y':
2444 case 'Y': // Pointer register pair Y
2445 case 'z':
2446 case 'Z': // Pointer register pair Z
2447 return C_Register;
2448 case 'Q': // A memory address based on Y or Z pointer with displacement.
2449 return C_Memory;
2450 case 'G': // Floating point constant
2451 case 'I': // 6-bit positive integer constant
2452 case 'J': // 6-bit negative integer constant
2453 case 'K': // Integer constant (Range: 2)
2454 case 'L': // Integer constant (Range: 0)
2455 case 'M': // 8-bit integer constant
2456 case 'N': // Integer constant (Range: -1)
2457 case 'O': // Integer constant (Range: 8, 16, 24)
2458 case 'P': // Integer constant (Range: 1)
2459 case 'R': // Integer constant (Range: -6 to 5)x
2460 return C_Immediate;
2461 }
2462 }
2463
2464 return TargetLowering::getConstraintType(Constraint);
2465}
2466
2467InlineAsm::ConstraintCode
2468AVRTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
2469 // Not sure if this is actually the right thing to do, but we got to do
2470 // *something* [agnat]
2471 switch (ConstraintCode[0]) {
2472 case 'Q':
2473 return InlineAsm::ConstraintCode::Q;
2474 }
2475 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
2476}
2477
2478AVRTargetLowering::ConstraintWeight
2479AVRTargetLowering::getSingleConstraintMatchWeight(
2480 AsmOperandInfo &info, const char *constraint) const {
2481 ConstraintWeight weight = CW_Invalid;
2482 Value *CallOperandVal = info.CallOperandVal;
2483
2484 // If we don't have a value, we can't do a match,
2485 // but allow it at the lowest weight.
2486 // (this behaviour has been copied from the ARM backend)
2487 if (!CallOperandVal) {
2488 return CW_Default;
2489 }
2490
2491 // Look at the constraint type.
2492 switch (*constraint) {
2493 default:
2494 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
2495 break;
2496 case 'd':
2497 case 'r':
2498 case 'l':
2499 weight = CW_Register;
2500 break;
2501 case 'a':
2502 case 'b':
2503 case 'e':
2504 case 'q':
2505 case 't':
2506 case 'w':
2507 case 'x':
2508 case 'X':
2509 case 'y':
2510 case 'Y':
2511 case 'z':
2512 case 'Z':
2513 weight = CW_SpecificReg;
2514 break;
2515 case 'G':
2516 if (const ConstantFP *C = dyn_cast<ConstantFP>(Val: CallOperandVal)) {
2517 if (C->isZero()) {
2518 weight = CW_Constant;
2519 }
2520 }
2521 break;
2522 case 'I':
2523 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2524 if (isUInt<6>(x: C->getZExtValue())) {
2525 weight = CW_Constant;
2526 }
2527 }
2528 break;
2529 case 'J':
2530 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2531 if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) {
2532 weight = CW_Constant;
2533 }
2534 }
2535 break;
2536 case 'K':
2537 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2538 if (C->getZExtValue() == 2) {
2539 weight = CW_Constant;
2540 }
2541 }
2542 break;
2543 case 'L':
2544 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2545 if (C->getZExtValue() == 0) {
2546 weight = CW_Constant;
2547 }
2548 }
2549 break;
2550 case 'M':
2551 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2552 if (isUInt<8>(x: C->getZExtValue())) {
2553 weight = CW_Constant;
2554 }
2555 }
2556 break;
2557 case 'N':
2558 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2559 if (C->getSExtValue() == -1) {
2560 weight = CW_Constant;
2561 }
2562 }
2563 break;
2564 case 'O':
2565 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2566 if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) ||
2567 (C->getZExtValue() == 24)) {
2568 weight = CW_Constant;
2569 }
2570 }
2571 break;
2572 case 'P':
2573 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2574 if (C->getZExtValue() == 1) {
2575 weight = CW_Constant;
2576 }
2577 }
2578 break;
2579 case 'R':
2580 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2581 if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) {
2582 weight = CW_Constant;
2583 }
2584 }
2585 break;
2586 case 'Q':
2587 weight = CW_Memory;
2588 break;
2589 }
2590
2591 return weight;
2592}
2593
2594std::pair<unsigned, const TargetRegisterClass *>
2595AVRTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2596 StringRef Constraint,
2597 MVT VT) const {
2598 if (Constraint.size() == 1) {
2599 switch (Constraint[0]) {
2600 case 'a': // Simple upper registers r16..r23.
2601 if (VT == MVT::i8)
2602 return std::make_pair(x: 0U, y: &AVR::LD8loRegClass);
2603 else if (VT == MVT::i16)
2604 return std::make_pair(x: 0U, y: &AVR::DREGSLD8loRegClass);
2605 break;
2606 case 'b': // Base pointer registers: y, z.
2607 if (VT == MVT::i8 || VT == MVT::i16)
2608 return std::make_pair(x: 0U, y: &AVR::PTRDISPREGSRegClass);
2609 break;
2610 case 'd': // Upper registers r16..r31.
2611 if (VT == MVT::i8)
2612 return std::make_pair(x: 0U, y: &AVR::LD8RegClass);
2613 else if (VT == MVT::i16)
2614 return std::make_pair(x: 0U, y: &AVR::DLDREGSRegClass);
2615 break;
2616 case 'l': // Lower registers r0..r15.
2617 if (VT == MVT::i8)
2618 return std::make_pair(x: 0U, y: &AVR::GPR8loRegClass);
2619 else if (VT == MVT::i16)
2620 return std::make_pair(x: 0U, y: &AVR::DREGSloRegClass);
2621 break;
2622 case 'e': // Pointer register pairs: x, y, z.
2623 if (VT == MVT::i8 || VT == MVT::i16)
2624 return std::make_pair(x: 0U, y: &AVR::PTRREGSRegClass);
2625 break;
2626 case 'q': // Stack pointer register: SPH:SPL.
2627 return std::make_pair(x: 0U, y: &AVR::GPRSPRegClass);
2628 case 'r': // Any register: r0..r31.
2629 if (VT == MVT::i8)
2630 return std::make_pair(x: 0U, y: &AVR::GPR8RegClass);
2631 else if (VT == MVT::i16)
2632 return std::make_pair(x: 0U, y: &AVR::DREGSRegClass);
2633 break;
2634 case 't': // Temporary register: r0.
2635 if (VT == MVT::i8)
2636 return std::make_pair(x: unsigned(Subtarget.getTmpRegister()),
2637 y: &AVR::GPR8RegClass);
2638 break;
2639 case 'w': // Special upper register pairs: r24, r26, r28, r30.
2640 if (VT == MVT::i8 || VT == MVT::i16)
2641 return std::make_pair(x: 0U, y: &AVR::IWREGSRegClass);
2642 break;
2643 case 'x': // Pointer register pair X: r27:r26.
2644 case 'X':
2645 if (VT == MVT::i8 || VT == MVT::i16)
2646 return std::make_pair(x: unsigned(AVR::R27R26), y: &AVR::PTRREGSRegClass);
2647 break;
2648 case 'y': // Pointer register pair Y: r29:r28.
2649 case 'Y':
2650 if (VT == MVT::i8 || VT == MVT::i16)
2651 return std::make_pair(x: unsigned(AVR::R29R28), y: &AVR::PTRREGSRegClass);
2652 break;
2653 case 'z': // Pointer register pair Z: r31:r30.
2654 case 'Z':
2655 if (VT == MVT::i8 || VT == MVT::i16)
2656 return std::make_pair(x: unsigned(AVR::R31R30), y: &AVR::PTRREGSRegClass);
2657 break;
2658 default:
2659 break;
2660 }
2661 }
2662
2663 return TargetLowering::getRegForInlineAsmConstraint(
2664 TRI: Subtarget.getRegisterInfo(), Constraint, VT);
2665}
2666
2667void AVRTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2668 StringRef Constraint,
2669 std::vector<SDValue> &Ops,
2670 SelectionDAG &DAG) const {
2671 SDValue Result;
2672 SDLoc DL(Op);
2673 EVT Ty = Op.getValueType();
2674
2675 // Currently only support length 1 constraints.
2676 if (Constraint.size() != 1) {
2677 return;
2678 }
2679
2680 char ConstraintLetter = Constraint[0];
2681 switch (ConstraintLetter) {
2682 default:
2683 break;
2684 // Deal with integers first:
2685 case 'I':
2686 case 'J':
2687 case 'K':
2688 case 'L':
2689 case 'M':
2690 case 'N':
2691 case 'O':
2692 case 'P':
2693 case 'R': {
2694 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: Op);
2695 if (!C) {
2696 return;
2697 }
2698
2699 int64_t CVal64 = C->getSExtValue();
2700 uint64_t CUVal64 = C->getZExtValue();
2701 switch (ConstraintLetter) {
2702 case 'I': // 0..63
2703 if (!isUInt<6>(x: CUVal64))
2704 return;
2705 Result = DAG.getTargetConstant(Val: CUVal64, DL, VT: Ty);
2706 break;
2707 case 'J': // -63..0
2708 if (CVal64 < -63 || CVal64 > 0)
2709 return;
2710 Result = DAG.getTargetConstant(Val: CVal64, DL, VT: Ty);
2711 break;
2712 case 'K': // 2
2713 if (CUVal64 != 2)
2714 return;
2715 Result = DAG.getTargetConstant(Val: CUVal64, DL, VT: Ty);
2716 break;
2717 case 'L': // 0
2718 if (CUVal64 != 0)
2719 return;
2720 Result = DAG.getTargetConstant(Val: CUVal64, DL, VT: Ty);
2721 break;
2722 case 'M': // 0..255
2723 if (!isUInt<8>(x: CUVal64))
2724 return;
2725 // i8 type may be printed as a negative number,
2726 // e.g. 254 would be printed as -2,
2727 // so we force it to i16 at least.
2728 if (Ty.getSimpleVT() == MVT::i8) {
2729 Ty = MVT::i16;
2730 }
2731 Result = DAG.getTargetConstant(Val: CUVal64, DL, VT: Ty);
2732 break;
2733 case 'N': // -1
2734 if (CVal64 != -1)
2735 return;
2736 Result = DAG.getTargetConstant(Val: CVal64, DL, VT: Ty);
2737 break;
2738 case 'O': // 8, 16, 24
2739 if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
2740 return;
2741 Result = DAG.getTargetConstant(Val: CUVal64, DL, VT: Ty);
2742 break;
2743 case 'P': // 1
2744 if (CUVal64 != 1)
2745 return;
2746 Result = DAG.getTargetConstant(Val: CUVal64, DL, VT: Ty);
2747 break;
2748 case 'R': // -6..5
2749 if (CVal64 < -6 || CVal64 > 5)
2750 return;
2751 Result = DAG.getTargetConstant(Val: CVal64, DL, VT: Ty);
2752 break;
2753 }
2754
2755 break;
2756 }
2757 case 'G':
2758 const ConstantFPSDNode *FC = dyn_cast<ConstantFPSDNode>(Val&: Op);
2759 if (!FC || !FC->isZero())
2760 return;
2761 // Soften float to i8 0
2762 Result = DAG.getTargetConstant(Val: 0, DL, VT: MVT::i8);
2763 break;
2764 }
2765
2766 if (Result.getNode()) {
2767 Ops.push_back(x: Result);
2768 return;
2769 }
2770
2771 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2772}
2773
2774Register AVRTargetLowering::getRegisterByName(const char *RegName, LLT VT,
2775 const MachineFunction &MF) const {
2776 Register Reg;
2777
2778 if (VT == LLT::scalar(SizeInBits: 8)) {
2779 Reg = StringSwitch<unsigned>(RegName)
2780 .Case(S: "r0", Value: AVR::R0)
2781 .Case(S: "r1", Value: AVR::R1)
2782 .Default(Value: 0);
2783 } else {
2784 Reg = StringSwitch<unsigned>(RegName)
2785 .Case(S: "r0", Value: AVR::R1R0)
2786 .Case(S: "sp", Value: AVR::SP)
2787 .Default(Value: 0);
2788 }
2789
2790 if (Reg)
2791 return Reg;
2792
2793 report_fatal_error(
2794 reason: Twine("Invalid register name \"" + StringRef(RegName) + "\"."));
2795}
2796
2797} // end of namespace llvm
2798