1//===-- MSP430ISelDAGToDAG.cpp - A dag to dag inst selector for MSP430 ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines an instruction selector for the MSP430 target.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MSP430.h"
14#include "MSP430SelectionDAGInfo.h"
15#include "MSP430TargetMachine.h"
16#include "llvm/CodeGen/MachineFrameInfo.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/SelectionDAG.h"
19#include "llvm/CodeGen/SelectionDAGISel.h"
20#include "llvm/Config/llvm-config.h"
21#include "llvm/IR/Constants.h"
22#include "llvm/IR/Function.h"
23#include "llvm/Support/Debug.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/raw_ostream.h"
26using namespace llvm;
27
28#define DEBUG_TYPE "msp430-isel"
29#define PASS_NAME "MSP430 DAG->DAG Pattern Instruction Selection"
30
31namespace {
32 struct MSP430ISelAddressMode {
33 enum {
34 RegBase,
35 FrameIndexBase
36 } BaseType = RegBase;
37
38 struct { // This is really a union, discriminated by BaseType!
39 SDValue Reg;
40 int FrameIndex = 0;
41 } Base;
42
43 int16_t Disp = 0;
44 const GlobalValue *GV = nullptr;
45 const Constant *CP = nullptr;
46 const BlockAddress *BlockAddr = nullptr;
47 const char *ES = nullptr;
48 int JT = -1;
49 Align Alignment; // CP alignment.
50
51 MSP430ISelAddressMode() = default;
52
53 bool hasSymbolicDisplacement() const {
54 return GV != nullptr || CP != nullptr || ES != nullptr || JT != -1;
55 }
56
57#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
58 LLVM_DUMP_METHOD void dump() {
59 errs() << "MSP430ISelAddressMode " << this << '\n';
60 if (BaseType == RegBase && Base.Reg.getNode() != nullptr) {
61 errs() << "Base.Reg ";
62 Base.Reg.getNode()->dump();
63 } else if (BaseType == FrameIndexBase) {
64 errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
65 }
66 errs() << " Disp " << Disp << '\n';
67 if (GV) {
68 errs() << "GV ";
69 GV->dump();
70 } else if (CP) {
71 errs() << " CP ";
72 CP->dump();
73 errs() << " Align" << Alignment.value() << '\n';
74 } else if (ES) {
75 errs() << "ES ";
76 errs() << ES << '\n';
77 } else if (JT != -1)
78 errs() << " JT" << JT << " Align" << Alignment.value() << '\n';
79 }
80#endif
81 };
82}
83
84/// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
85/// instructions for SelectionDAG operations.
86///
87namespace {
88 class MSP430DAGToDAGISel : public SelectionDAGISel {
89 public:
90 MSP430DAGToDAGISel() = delete;
91
92 MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOptLevel OptLevel)
93 : SelectionDAGISel(TM, OptLevel) {}
94
95 private:
96 bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
97 bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
98 bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
99
100 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
101 InlineAsm::ConstraintCode ConstraintID,
102 std::vector<SDValue> &OutOps) override;
103
104 // Include the pieces autogenerated from the target description.
105 #include "MSP430GenDAGISel.inc"
106
107 // Main method to transform nodes into machine nodes.
108 void Select(SDNode *N) override;
109
110 bool tryIndexedLoad(SDNode *Op);
111 bool tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, unsigned Opc8,
112 unsigned Opc16);
113
114 bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
115 };
116
117 class MSP430DAGToDAGISelLegacy : public SelectionDAGISelLegacy {
118 public:
119 static char ID;
120 MSP430DAGToDAGISelLegacy(MSP430TargetMachine &TM, CodeGenOptLevel OptLevel)
121 : SelectionDAGISelLegacy(
122 ID, std::make_unique<MSP430DAGToDAGISel>(args&: TM, args&: OptLevel)) {}
123 };
124} // end anonymous namespace
125
126char MSP430DAGToDAGISelLegacy::ID;
127
128INITIALIZE_PASS(MSP430DAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
129
130/// createMSP430ISelDag - This pass converts a legalized DAG into a
131/// MSP430-specific DAG, ready for instruction scheduling.
132///
133FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM,
134 CodeGenOptLevel OptLevel) {
135 return new MSP430DAGToDAGISelLegacy(TM, OptLevel);
136}
137
138MSP430ISelDAGToDAGPass::MSP430ISelDAGToDAGPass(MSP430TargetMachine &TM,
139 CodeGenOptLevel OptLevel)
140 : SelectionDAGISelPass(std::make_unique<MSP430DAGToDAGISel>(args&: TM, args&: OptLevel)) {
141}
142
143/// MatchWrapper - Try to match MSP430ISD::Wrapper node into an addressing mode.
144/// These wrap things that will resolve down into a symbol reference. If no
145/// match is possible, this returns true, otherwise it returns false.
146bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) {
147 // If the addressing mode already has a symbol as the displacement, we can
148 // never match another symbol.
149 if (AM.hasSymbolicDisplacement())
150 return true;
151
152 SDValue N0 = N.getOperand(i: 0);
153
154 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: N0)) {
155 AM.GV = G->getGlobal();
156 AM.Disp += G->getOffset();
157 //AM.SymbolFlags = G->getTargetFlags();
158 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Val&: N0)) {
159 AM.CP = CP->getConstVal();
160 AM.Alignment = CP->getAlign();
161 AM.Disp += CP->getOffset();
162 //AM.SymbolFlags = CP->getTargetFlags();
163 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Val&: N0)) {
164 AM.ES = S->getSymbol();
165 //AM.SymbolFlags = S->getTargetFlags();
166 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(Val&: N0)) {
167 AM.JT = J->getIndex();
168 //AM.SymbolFlags = J->getTargetFlags();
169 } else {
170 AM.BlockAddr = cast<BlockAddressSDNode>(Val&: N0)->getBlockAddress();
171 //AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
172 }
173 return false;
174}
175
176/// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
177/// specified addressing mode without any further recursion.
178bool MSP430DAGToDAGISel::MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM) {
179 // Is the base register already occupied?
180 if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
181 // If so, we cannot select it.
182 return true;
183 }
184
185 // Default, generate it as a register.
186 AM.BaseType = MSP430ISelAddressMode::RegBase;
187 AM.Base.Reg = N;
188 return false;
189}
190
191bool MSP430DAGToDAGISel::MatchAddress(SDValue N, MSP430ISelAddressMode &AM) {
192 LLVM_DEBUG(errs() << "MatchAddress: "; AM.dump());
193
194 switch (N.getOpcode()) {
195 default: break;
196 case ISD::Constant: {
197 uint64_t Val = cast<ConstantSDNode>(Val&: N)->getSExtValue();
198 AM.Disp += Val;
199 return false;
200 }
201
202 case MSP430ISD::Wrapper:
203 if (!MatchWrapper(N, AM))
204 return false;
205 break;
206
207 case ISD::FrameIndex:
208 if (AM.BaseType == MSP430ISelAddressMode::RegBase
209 && AM.Base.Reg.getNode() == nullptr) {
210 AM.BaseType = MSP430ISelAddressMode::FrameIndexBase;
211 AM.Base.FrameIndex = cast<FrameIndexSDNode>(Val&: N)->getIndex();
212 return false;
213 }
214 break;
215
216 case ISD::ADD: {
217 MSP430ISelAddressMode Backup = AM;
218 if (!MatchAddress(N: N.getNode()->getOperand(Num: 0), AM) &&
219 !MatchAddress(N: N.getNode()->getOperand(Num: 1), AM))
220 return false;
221 AM = Backup;
222 if (!MatchAddress(N: N.getNode()->getOperand(Num: 1), AM) &&
223 !MatchAddress(N: N.getNode()->getOperand(Num: 0), AM))
224 return false;
225 AM = Backup;
226
227 break;
228 }
229
230 case ISD::OR:
231 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
232 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val: N.getOperand(i: 1))) {
233 MSP430ISelAddressMode Backup = AM;
234 uint64_t Offset = CN->getSExtValue();
235 // Start with the LHS as an addr mode.
236 if (!MatchAddress(N: N.getOperand(i: 0), AM) &&
237 // Address could not have picked a GV address for the displacement.
238 AM.GV == nullptr &&
239 // Check to see if the LHS & C is zero.
240 CurDAG->MaskedValueIsZero(Op: N.getOperand(i: 0), Mask: CN->getAPIntValue())) {
241 AM.Disp += Offset;
242 return false;
243 }
244 AM = Backup;
245 }
246 break;
247 }
248
249 return MatchAddressBase(N, AM);
250}
251
252/// SelectAddr - returns true if it is able pattern match an addressing mode.
253/// It returns the operands which make up the maximal addressing mode it can
254/// match by reference.
255bool MSP430DAGToDAGISel::SelectAddr(SDValue N,
256 SDValue &Base, SDValue &Disp) {
257 MSP430ISelAddressMode AM;
258
259 if (MatchAddress(N, AM))
260 return false;
261
262 if (AM.BaseType == MSP430ISelAddressMode::RegBase)
263 if (!AM.Base.Reg.getNode())
264 AM.Base.Reg = CurDAG->getRegister(Reg: MSP430::SR, VT: MVT::i16);
265
266 Base = (AM.BaseType == MSP430ISelAddressMode::FrameIndexBase)
267 ? CurDAG->getTargetFrameIndex(
268 FI: AM.Base.FrameIndex,
269 VT: N.getValueType())
270 : AM.Base.Reg;
271
272 if (AM.GV)
273 Disp = CurDAG->getTargetGlobalAddress(GV: AM.GV, DL: SDLoc(N),
274 VT: MVT::i16, offset: AM.Disp,
275 TargetFlags: 0/*AM.SymbolFlags*/);
276 else if (AM.CP)
277 Disp = CurDAG->getTargetConstantPool(C: AM.CP, VT: MVT::i16, Align: AM.Alignment, Offset: AM.Disp,
278 TargetFlags: 0 /*AM.SymbolFlags*/);
279 else if (AM.ES)
280 Disp = CurDAG->getTargetExternalSymbol(Sym: AM.ES, VT: MVT::i16, TargetFlags: 0/*AM.SymbolFlags*/);
281 else if (AM.JT != -1)
282 Disp = CurDAG->getTargetJumpTable(JTI: AM.JT, VT: MVT::i16, TargetFlags: 0/*AM.SymbolFlags*/);
283 else if (AM.BlockAddr)
284 Disp = CurDAG->getTargetBlockAddress(BA: AM.BlockAddr, VT: MVT::i32, Offset: 0,
285 TargetFlags: 0/*AM.SymbolFlags*/);
286 else
287 Disp = CurDAG->getSignedTargetConstant(Val: AM.Disp, DL: SDLoc(N), VT: MVT::i16);
288
289 return true;
290}
291
292bool MSP430DAGToDAGISel::SelectInlineAsmMemoryOperand(
293 const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
294 std::vector<SDValue> &OutOps) {
295 SDValue Op0, Op1;
296 switch (ConstraintID) {
297 default: return true;
298 case InlineAsm::ConstraintCode::m: // memory
299 if (!SelectAddr(N: Op, Base&: Op0, Disp&: Op1))
300 return true;
301 break;
302 }
303
304 OutOps.push_back(x: Op0);
305 OutOps.push_back(x: Op1);
306 return false;
307}
308
309static bool isValidIndexedLoad(const LoadSDNode *LD) {
310 ISD::MemIndexedMode AM = LD->getAddressingMode();
311 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD)
312 return false;
313
314 EVT VT = LD->getMemoryVT();
315
316 switch (VT.getSimpleVT().SimpleTy) {
317 case MVT::i8:
318 if (LD->getOffset()->getAsZExtVal() != 1)
319 return false;
320
321 break;
322 case MVT::i16:
323 if (LD->getOffset()->getAsZExtVal() != 2)
324 return false;
325
326 break;
327 default:
328 return false;
329 }
330
331 return true;
332}
333
334bool MSP430DAGToDAGISel::tryIndexedLoad(SDNode *N) {
335 LoadSDNode *LD = cast<LoadSDNode>(Val: N);
336 if (!isValidIndexedLoad(LD))
337 return false;
338
339 MVT VT = LD->getMemoryVT().getSimpleVT();
340
341 unsigned Opcode = 0;
342 switch (VT.SimpleTy) {
343 case MVT::i8:
344 Opcode = MSP430::MOV8rp;
345 break;
346 case MVT::i16:
347 Opcode = MSP430::MOV16rp;
348 break;
349 default:
350 return false;
351 }
352
353 ReplaceNode(F: N,
354 T: CurDAG->getMachineNode(Opcode, dl: SDLoc(N), VT1: VT, VT2: MVT::i16, VT3: MVT::Other,
355 Op1: LD->getBasePtr(), Op2: LD->getChain()));
356 return true;
357}
358
359bool MSP430DAGToDAGISel::tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
360 unsigned Opc8, unsigned Opc16) {
361 if (N1.getOpcode() == ISD::LOAD &&
362 N1.hasOneUse() &&
363 IsLegalToFold(N: N1, U: Op, Root: Op, OptLevel)) {
364 LoadSDNode *LD = cast<LoadSDNode>(Val&: N1);
365 if (!isValidIndexedLoad(LD))
366 return false;
367
368 MVT VT = LD->getMemoryVT().getSimpleVT();
369 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
370 MachineMemOperand *MemRef = cast<MemSDNode>(Val&: N1)->getMemOperand();
371 SDValue Ops0[] = { N2, LD->getBasePtr(), LD->getChain() };
372 SDNode *ResNode =
373 CurDAG->SelectNodeTo(N: Op, MachineOpc: Opc, VT1: VT, VT2: MVT::i16, VT3: MVT::Other, Ops: Ops0);
374 CurDAG->setNodeMemRefs(N: cast<MachineSDNode>(Val: ResNode), NewMemRefs: {MemRef});
375 // Transfer chain.
376 ReplaceUses(F: SDValue(N1.getNode(), 2), T: SDValue(ResNode, 2));
377 // Transfer writeback.
378 ReplaceUses(F: SDValue(N1.getNode(), 1), T: SDValue(ResNode, 1));
379 return true;
380 }
381
382 return false;
383}
384
385
386void MSP430DAGToDAGISel::Select(SDNode *Node) {
387 SDLoc dl(Node);
388
389 // If we have a custom node, we already have selected!
390 if (Node->isMachineOpcode()) {
391 LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
392 Node->setNodeId(-1);
393 return;
394 }
395
396 // Few custom selection stuff.
397 switch (Node->getOpcode()) {
398 default: break;
399 case ISD::FrameIndex: {
400 assert(Node->getValueType(0) == MVT::i16);
401 int FI = cast<FrameIndexSDNode>(Val: Node)->getIndex();
402 SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT: MVT::i16);
403 if (Node->hasOneUse()) {
404 CurDAG->SelectNodeTo(N: Node, MachineOpc: MSP430::ADDframe, VT: MVT::i16, Op1: TFI,
405 Op2: CurDAG->getTargetConstant(Val: 0, DL: dl, VT: MVT::i16));
406 return;
407 }
408 ReplaceNode(F: Node, T: CurDAG->getMachineNode(
409 Opcode: MSP430::ADDframe, dl, VT: MVT::i16, Op1: TFI,
410 Op2: CurDAG->getTargetConstant(Val: 0, DL: dl, VT: MVT::i16)));
411 return;
412 }
413 case ISD::LOAD:
414 if (tryIndexedLoad(N: Node))
415 return;
416 // Other cases are autogenerated.
417 break;
418 case ISD::ADD:
419 if (tryIndexedBinOp(Op: Node, N1: Node->getOperand(Num: 0), N2: Node->getOperand(Num: 1),
420 Opc8: MSP430::ADD8rp, Opc16: MSP430::ADD16rp))
421 return;
422 else if (tryIndexedBinOp(Op: Node, N1: Node->getOperand(Num: 1), N2: Node->getOperand(Num: 0),
423 Opc8: MSP430::ADD8rp, Opc16: MSP430::ADD16rp))
424 return;
425
426 // Other cases are autogenerated.
427 break;
428 case ISD::SUB:
429 if (tryIndexedBinOp(Op: Node, N1: Node->getOperand(Num: 0), N2: Node->getOperand(Num: 1),
430 Opc8: MSP430::SUB8rp, Opc16: MSP430::SUB16rp))
431 return;
432
433 // Other cases are autogenerated.
434 break;
435 case ISD::AND:
436 if (tryIndexedBinOp(Op: Node, N1: Node->getOperand(Num: 0), N2: Node->getOperand(Num: 1),
437 Opc8: MSP430::AND8rp, Opc16: MSP430::AND16rp))
438 return;
439 else if (tryIndexedBinOp(Op: Node, N1: Node->getOperand(Num: 1), N2: Node->getOperand(Num: 0),
440 Opc8: MSP430::AND8rp, Opc16: MSP430::AND16rp))
441 return;
442
443 // Other cases are autogenerated.
444 break;
445 case ISD::OR:
446 if (tryIndexedBinOp(Op: Node, N1: Node->getOperand(Num: 0), N2: Node->getOperand(Num: 1),
447 Opc8: MSP430::BIS8rp, Opc16: MSP430::BIS16rp))
448 return;
449 else if (tryIndexedBinOp(Op: Node, N1: Node->getOperand(Num: 1), N2: Node->getOperand(Num: 0),
450 Opc8: MSP430::BIS8rp, Opc16: MSP430::BIS16rp))
451 return;
452
453 // Other cases are autogenerated.
454 break;
455 case ISD::XOR:
456 if (tryIndexedBinOp(Op: Node, N1: Node->getOperand(Num: 0), N2: Node->getOperand(Num: 1),
457 Opc8: MSP430::XOR8rp, Opc16: MSP430::XOR16rp))
458 return;
459 else if (tryIndexedBinOp(Op: Node, N1: Node->getOperand(Num: 1), N2: Node->getOperand(Num: 0),
460 Opc8: MSP430::XOR8rp, Opc16: MSP430::XOR16rp))
461 return;
462
463 // Other cases are autogenerated.
464 break;
465 }
466
467 // Select the default instruction
468 SelectCode(N: Node);
469}
470