1//===-- MSP430InstrInfo.cpp - MSP430 Instruction Information --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the MSP430 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MSP430InstrInfo.h"
14#include "MSP430.h"
15#include "MSP430Subtarget.h"
16#include "llvm/CodeGen/MachineFrameInfo.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/Support/ErrorHandling.h"
19
20using namespace llvm;
21
22#define GET_INSTRINFO_CTOR_DTOR
23#include "MSP430GenInstrInfo.inc"
24
25// Pin the vtable to this file.
26void MSP430InstrInfo::anchor() {}
27
28MSP430InstrInfo::MSP430InstrInfo(const MSP430Subtarget &STI)
29 : MSP430GenInstrInfo(STI, RI, MSP430::ADJCALLSTACKDOWN,
30 MSP430::ADJCALLSTACKUP),
31 RI() {}
32
33void MSP430InstrInfo::storeRegToStackSlot(
34 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
35 bool isKill, int FrameIdx, const TargetRegisterClass *RC, Register VReg,
36 MachineInstr::MIFlag Flags) const {
37 DebugLoc DL;
38 if (MI != MBB.end()) DL = MI->getDebugLoc();
39 MachineFunction &MF = *MBB.getParent();
40 MachineFrameInfo &MFI = MF.getFrameInfo();
41
42 MachineMemOperand *MMO = MF.getMachineMemOperand(
43 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI: FrameIdx),
44 F: MachineMemOperand::MOStore, Size: MFI.getObjectSize(ObjectIdx: FrameIdx),
45 BaseAlignment: MFI.getObjectAlign(ObjectIdx: FrameIdx));
46
47 if (RC == &MSP430::GR16RegClass)
48 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: get(Opcode: MSP430::MOV16mr))
49 .addFrameIndex(Idx: FrameIdx).addImm(Val: 0)
50 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill)).addMemOperand(MMO);
51 else if (RC == &MSP430::GR8RegClass)
52 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: get(Opcode: MSP430::MOV8mr))
53 .addFrameIndex(Idx: FrameIdx).addImm(Val: 0)
54 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill)).addMemOperand(MMO);
55 else
56 llvm_unreachable("Cannot store this register to stack slot!");
57}
58
59void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator MI,
61 Register DestReg, int FrameIdx,
62 const TargetRegisterClass *RC,
63 Register VReg, unsigned SubReg,
64 MachineInstr::MIFlag Flags) const {
65 DebugLoc DL;
66 if (MI != MBB.end()) DL = MI->getDebugLoc();
67 MachineFunction &MF = *MBB.getParent();
68 MachineFrameInfo &MFI = MF.getFrameInfo();
69
70 MachineMemOperand *MMO = MF.getMachineMemOperand(
71 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI: FrameIdx),
72 F: MachineMemOperand::MOLoad, Size: MFI.getObjectSize(ObjectIdx: FrameIdx),
73 BaseAlignment: MFI.getObjectAlign(ObjectIdx: FrameIdx));
74
75 if (RC == &MSP430::GR16RegClass)
76 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: get(Opcode: MSP430::MOV16rm))
77 .addReg(RegNo: DestReg, Flags: getDefRegState(B: true)).addFrameIndex(Idx: FrameIdx)
78 .addImm(Val: 0).addMemOperand(MMO);
79 else if (RC == &MSP430::GR8RegClass)
80 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: get(Opcode: MSP430::MOV8rm))
81 .addReg(RegNo: DestReg, Flags: getDefRegState(B: true)).addFrameIndex(Idx: FrameIdx)
82 .addImm(Val: 0).addMemOperand(MMO);
83 else
84 llvm_unreachable("Cannot store this register to stack slot!");
85}
86
87void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
88 MachineBasicBlock::iterator I,
89 const DebugLoc &DL, Register DestReg,
90 Register SrcReg, bool KillSrc,
91 bool RenamableDest, bool RenamableSrc) const {
92 unsigned Opc;
93 if (MSP430::GR16RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
94 Opc = MSP430::MOV16rr;
95 else if (MSP430::GR8RegClass.contains(Reg1: DestReg, Reg2: SrcReg))
96 Opc = MSP430::MOV8rr;
97 else
98 llvm_unreachable("Impossible reg-to-reg copy");
99
100 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Opc), DestReg)
101 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc));
102}
103
104unsigned MSP430InstrInfo::removeBranch(MachineBasicBlock &MBB,
105 int *BytesRemoved) const {
106 assert(!BytesRemoved && "code size not handled");
107
108 MachineBasicBlock::iterator I = MBB.end();
109 unsigned Count = 0;
110
111 while (I != MBB.begin()) {
112 --I;
113 if (I->isDebugInstr())
114 continue;
115 if (I->getOpcode() != MSP430::JMP &&
116 I->getOpcode() != MSP430::JCC &&
117 I->getOpcode() != MSP430::Bi &&
118 I->getOpcode() != MSP430::Br &&
119 I->getOpcode() != MSP430::Bm)
120 break;
121 // Remove the branch.
122 I->eraseFromParent();
123 I = MBB.end();
124 ++Count;
125 }
126
127 return Count;
128}
129
130bool MSP430InstrInfo::
131reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
132 assert(Cond.size() == 1 && "Invalid Xbranch condition!");
133
134 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
135
136 switch (CC) {
137 default: llvm_unreachable("Invalid branch condition!");
138 case MSP430CC::COND_E:
139 CC = MSP430CC::COND_NE;
140 break;
141 case MSP430CC::COND_NE:
142 CC = MSP430CC::COND_E;
143 break;
144 case MSP430CC::COND_L:
145 CC = MSP430CC::COND_GE;
146 break;
147 case MSP430CC::COND_GE:
148 CC = MSP430CC::COND_L;
149 break;
150 case MSP430CC::COND_HS:
151 CC = MSP430CC::COND_LO;
152 break;
153 case MSP430CC::COND_LO:
154 CC = MSP430CC::COND_HS;
155 break;
156 }
157
158 Cond[0].setImm(CC);
159 return false;
160}
161
162bool MSP430InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
163 MachineBasicBlock *&TBB,
164 MachineBasicBlock *&FBB,
165 SmallVectorImpl<MachineOperand> &Cond,
166 bool AllowModify) const {
167 // Start from the bottom of the block and work up, examining the
168 // terminator instructions.
169 MachineBasicBlock::iterator I = MBB.end();
170 while (I != MBB.begin()) {
171 --I;
172 if (I->isDebugInstr())
173 continue;
174
175 // Working from the bottom, when we see a non-terminator
176 // instruction, we're done.
177 if (!isUnpredicatedTerminator(MI: *I))
178 break;
179
180 // A terminator that isn't a branch can't easily be handled
181 // by this analysis.
182 if (!I->isBranch())
183 return true;
184
185 // Cannot handle indirect branches.
186 if (I->getOpcode() == MSP430::Br ||
187 I->getOpcode() == MSP430::Bm)
188 return true;
189
190 // Handle unconditional branches.
191 if (I->getOpcode() == MSP430::JMP || I->getOpcode() == MSP430::Bi) {
192 if (!AllowModify) {
193 TBB = I->getOperand(i: 0).getMBB();
194 continue;
195 }
196
197 // If the block has any instructions after a JMP, delete them.
198 MBB.erase(I: std::next(x: I), E: MBB.end());
199 Cond.clear();
200 FBB = nullptr;
201
202 // Delete the JMP if it's equivalent to a fall-through.
203 if (MBB.isLayoutSuccessor(MBB: I->getOperand(i: 0).getMBB())) {
204 TBB = nullptr;
205 I->eraseFromParent();
206 I = MBB.end();
207 continue;
208 }
209
210 // TBB is used to indicate the unconditinal destination.
211 TBB = I->getOperand(i: 0).getMBB();
212 continue;
213 }
214
215 // Handle conditional branches.
216 assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");
217 MSP430CC::CondCodes BranchCode =
218 static_cast<MSP430CC::CondCodes>(I->getOperand(i: 1).getImm());
219 if (BranchCode == MSP430CC::COND_INVALID)
220 return true; // Can't handle weird stuff.
221
222 // Working from the bottom, handle the first conditional branch.
223 if (Cond.empty()) {
224 FBB = TBB;
225 TBB = I->getOperand(i: 0).getMBB();
226 Cond.push_back(Elt: MachineOperand::CreateImm(Val: BranchCode));
227 continue;
228 }
229
230 // Handle subsequent conditional branches. Only handle the case where all
231 // conditional branches branch to the same destination.
232 assert(Cond.size() == 1);
233 assert(TBB);
234
235 // Only handle the case where all conditional branches branch to
236 // the same destination.
237 if (TBB != I->getOperand(i: 0).getMBB())
238 return true;
239
240 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
241 // If the conditions are the same, we can leave them alone.
242 if (OldBranchCode == BranchCode)
243 continue;
244
245 return true;
246 }
247
248 return false;
249}
250
251unsigned MSP430InstrInfo::insertBranch(MachineBasicBlock &MBB,
252 MachineBasicBlock *TBB,
253 MachineBasicBlock *FBB,
254 ArrayRef<MachineOperand> Cond,
255 const DebugLoc &DL,
256 int *BytesAdded) const {
257 // Shouldn't be a fall through.
258 assert(TBB && "insertBranch must not be told to insert a fallthrough");
259 assert((Cond.size() == 1 || Cond.size() == 0) &&
260 "MSP430 branch conditions have one component!");
261 assert(!BytesAdded && "code size not handled");
262
263 if (Cond.empty()) {
264 // Unconditional branch?
265 assert(!FBB && "Unconditional branch with multiple successors!");
266 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: MSP430::JMP)).addMBB(MBB: TBB);
267 return 1;
268 }
269
270 // Conditional branch.
271 unsigned Count = 0;
272 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: MSP430::JCC)).addMBB(MBB: TBB).addImm(Val: Cond[0].getImm());
273 ++Count;
274
275 if (FBB) {
276 // Two-way Conditional branch. Insert the second branch.
277 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: MSP430::JMP)).addMBB(MBB: FBB);
278 ++Count;
279 }
280 return Count;
281}
282
283/// GetInstSize - Return the number of bytes of code the specified
284/// instruction may be. This returns the maximum number of bytes.
285///
286unsigned MSP430InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
287 const MCInstrDesc &Desc = MI.getDesc();
288
289 switch (Desc.getOpcode()) {
290 case TargetOpcode::CFI_INSTRUCTION:
291 case TargetOpcode::EH_LABEL:
292 case TargetOpcode::IMPLICIT_DEF:
293 case TargetOpcode::KILL:
294 case TargetOpcode::DBG_VALUE:
295 return 0;
296 case TargetOpcode::INLINEASM:
297 case TargetOpcode::INLINEASM_BR: {
298 const MachineFunction *MF = MI.getParent()->getParent();
299 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
300 return TII.getInlineAsmLength(Str: MI.getOperand(i: 0).getSymbolName(),
301 MAI: *MF->getTarget().getMCAsmInfo());
302 }
303 }
304
305 return Desc.getSize();
306}
307