1//===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file is part of the Mips Disassembler.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/MipsMCTargetDesc.h"
14#include "TargetInfo/MipsTargetInfo.h"
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCDecoder.h"
18#include "llvm/MC/MCDecoderOps.h"
19#include "llvm/MC/MCDisassembler/MCDisassembler.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/MC/TargetRegistry.h"
24#include "llvm/Support/Compiler.h"
25#include "llvm/Support/Debug.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/MathExtras.h"
28#include "llvm/Support/raw_ostream.h"
29#include <cassert>
30#include <cstdint>
31
32using namespace llvm;
33using namespace llvm::MCD;
34
35#define DEBUG_TYPE "mips-disassembler"
36
37using DecodeStatus = MCDisassembler::DecodeStatus;
38
39namespace {
40
41class MipsDisassembler : public MCDisassembler {
42 bool IsMicroMips;
43 bool IsBigEndian;
44
45public:
46 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
47 : MCDisassembler(STI, Ctx),
48 IsMicroMips(STI.hasFeature(Feature: Mips::FeatureMicroMips)),
49 IsBigEndian(IsBigEndian) {}
50
51 bool hasMips2() const { return STI.hasFeature(Feature: Mips::FeatureMips2); }
52 bool hasMips3() const { return STI.hasFeature(Feature: Mips::FeatureMips3); }
53 bool hasMips32() const { return STI.hasFeature(Feature: Mips::FeatureMips32); }
54
55 bool hasMips32r6() const {
56 return STI.hasFeature(Feature: Mips::FeatureMips32r6);
57 }
58
59 bool isFP64() const { return STI.hasFeature(Feature: Mips::FeatureFP64Bit); }
60
61 bool isGP64() const { return STI.hasFeature(Feature: Mips::FeatureGP64Bit); }
62
63 bool isPTR64() const { return STI.hasFeature(Feature: Mips::FeaturePTR64Bit); }
64
65 bool hasCnMips() const { return STI.hasFeature(Feature: Mips::FeatureCnMips); }
66
67 bool hasCnMipsP() const { return STI.hasFeature(Feature: Mips::FeatureCnMipsP); }
68
69 bool hasCOP3() const {
70 // Only present in MIPS-I and MIPS-II
71 return !hasMips32() && !hasMips3();
72 }
73
74 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
75 ArrayRef<uint8_t> Bytes, uint64_t Address,
76 raw_ostream &CStream) const override;
77};
78
79} // end anonymous namespace
80
81static MCDisassembler *createMipsDisassembler(const Target &T,
82 const MCSubtargetInfo &STI,
83 MCContext &Ctx) {
84 return new MipsDisassembler(STI, Ctx, true);
85}
86
87static MCDisassembler *createMipselDisassembler(const Target &T,
88 const MCSubtargetInfo &STI,
89 MCContext &Ctx) {
90 return new MipsDisassembler(STI, Ctx, false);
91}
92
93extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
94LLVMInitializeMipsDisassembler() {
95 // Register the disassembler.
96 TargetRegistry::RegisterMCDisassembler(T&: getTheMipsTarget(),
97 Fn: createMipsDisassembler);
98 TargetRegistry::RegisterMCDisassembler(T&: getTheMipselTarget(),
99 Fn: createMipselDisassembler);
100 TargetRegistry::RegisterMCDisassembler(T&: getTheMips64Target(),
101 Fn: createMipsDisassembler);
102 TargetRegistry::RegisterMCDisassembler(T&: getTheMips64elTarget(),
103 Fn: createMipselDisassembler);
104}
105
106static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo) {
107 const MCRegisterInfo *RegInfo = D->getContext().getRegisterInfo();
108 return RegInfo->getRegClass(i: RC).getRegister(i: RegNo);
109}
110static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo,
111 uint64_t Address,
112 const MCDisassembler *Decoder) {
113 // Currently only hardware register 29 is supported.
114 if (RegNo != 29)
115 return MCDisassembler::Fail;
116 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::HWR29));
117 return MCDisassembler::Success;
118}
119
120static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
121 uint64_t Address,
122 const MCDisassembler *Decoder) {
123 if (RegNo > 30 || RegNo % 2)
124 return MCDisassembler::Fail;
125
126 MCRegister Reg = getReg(D: Decoder, RC: Mips::AFGR64RegClassID, RegNo: RegNo / 2);
127 Inst.addOperand(Op: MCOperand::createReg(Reg));
128 return MCDisassembler::Success;
129}
130
131static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo,
132 uint64_t Address,
133 const MCDisassembler *Decoder) {
134 if (RegNo >= 4)
135 return MCDisassembler::Fail;
136
137 MCRegister Reg = getReg(D: Decoder, RC: Mips::ACC64DSPRegClassID, RegNo);
138 Inst.addOperand(Op: MCOperand::createReg(Reg));
139 return MCDisassembler::Success;
140}
141
142static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
143 uint64_t Address,
144 const MCDisassembler *Decoder) {
145 if (RegNo >= 4)
146 return MCDisassembler::Fail;
147
148 MCRegister Reg = getReg(D: Decoder, RC: Mips::HI32DSPRegClassID, RegNo);
149 Inst.addOperand(Op: MCOperand::createReg(Reg));
150 return MCDisassembler::Success;
151}
152
153static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
154 uint64_t Address,
155 const MCDisassembler *Decoder) {
156 if (RegNo >= 4)
157 return MCDisassembler::Fail;
158
159 MCRegister Reg = getReg(D: Decoder, RC: Mips::LO32DSPRegClassID, RegNo);
160 Inst.addOperand(Op: MCOperand::createReg(Reg));
161 return MCDisassembler::Success;
162}
163
164static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo,
165 uint64_t Address,
166 const MCDisassembler *Decoder) {
167 if (RegNo > 31)
168 return MCDisassembler::Fail;
169
170 MCRegister Reg = getReg(D: Decoder, RC: Mips::MSA128BRegClassID, RegNo);
171 Inst.addOperand(Op: MCOperand::createReg(Reg));
172 return MCDisassembler::Success;
173}
174
175static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo,
176 uint64_t Address,
177 const MCDisassembler *Decoder) {
178 if (RegNo > 31)
179 return MCDisassembler::Fail;
180
181 MCRegister Reg = getReg(D: Decoder, RC: Mips::MSA128HRegClassID, RegNo);
182 Inst.addOperand(Op: MCOperand::createReg(Reg));
183 return MCDisassembler::Success;
184}
185
186static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo,
187 uint64_t Address,
188 const MCDisassembler *Decoder) {
189 if (RegNo > 31)
190 return MCDisassembler::Fail;
191
192 MCRegister Reg = getReg(D: Decoder, RC: Mips::MSA128WRegClassID, RegNo);
193 Inst.addOperand(Op: MCOperand::createReg(Reg));
194 return MCDisassembler::Success;
195}
196
197static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo,
198 uint64_t Address,
199 const MCDisassembler *Decoder) {
200 if (RegNo > 31)
201 return MCDisassembler::Fail;
202
203 MCRegister Reg = getReg(D: Decoder, RC: Mips::MSA128DRegClassID, RegNo);
204 Inst.addOperand(Op: MCOperand::createReg(Reg));
205 return MCDisassembler::Success;
206}
207
208static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo,
209 uint64_t Address,
210 const MCDisassembler *Decoder) {
211 if (RegNo > 7)
212 return MCDisassembler::Fail;
213
214 MCRegister Reg = getReg(D: Decoder, RC: Mips::MSACtrlRegClassID, RegNo);
215 Inst.addOperand(Op: MCOperand::createReg(Reg));
216 return MCDisassembler::Success;
217}
218
219static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo,
220 uint64_t Address,
221 const MCDisassembler *Decoder) {
222 if (RegNo > 31)
223 return MCDisassembler::Fail;
224
225 MCRegister Reg = getReg(D: Decoder, RC: Mips::COP0RegClassID, RegNo);
226 Inst.addOperand(Op: MCOperand::createReg(Reg));
227 return MCDisassembler::Success;
228}
229
230static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo,
231 uint64_t Address,
232 const MCDisassembler *Decoder) {
233 if (RegNo > 31)
234 return MCDisassembler::Fail;
235
236 MCRegister Reg = getReg(D: Decoder, RC: Mips::COP2RegClassID, RegNo);
237 Inst.addOperand(Op: MCOperand::createReg(Reg));
238 return MCDisassembler::Success;
239}
240
241static DecodeStatus DecodeCOP3RegisterClass(MCInst &Inst, unsigned RegNo,
242 uint64_t Address,
243 const MCDisassembler *Decoder) {
244 if (RegNo > 31)
245 return MCDisassembler::Fail;
246 Inst.addOperand(
247 Op: MCOperand::createReg(Reg: getReg(D: Decoder, RC: Mips::COP3RegClassID, RegNo)));
248 return MCDisassembler::Success;
249}
250
251static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned RegListEncoding,
252 uint64_t Address,
253 const MCDisassembler *Decoder) {
254 unsigned Regs[] = {Mips::R16, Mips::R17, Mips::R18, Mips::R19, Mips::R20,
255 Mips::R21, Mips::R22, Mips::R23, Mips::FP};
256 unsigned RegNum;
257
258 unsigned RegLst = RegListEncoding;
259
260 // Empty register lists are not allowed.
261 if (RegLst == 0)
262 return MCDisassembler::Fail;
263
264 RegNum = RegLst & 0xf;
265
266 // RegLst values 10-15, and 26-31 are reserved.
267 if (RegNum > 9)
268 return MCDisassembler::Fail;
269
270 for (unsigned i = 0; i < RegNum; i++)
271 Inst.addOperand(Op: MCOperand::createReg(Reg: Regs[i]));
272
273 if (RegLst & 0x10)
274 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::RA));
275
276 return MCDisassembler::Success;
277}
278
279static DecodeStatus DecodeRegListOperand16(MCInst &Inst,
280 unsigned RegListEncoding,
281 uint64_t Address,
282 const MCDisassembler *Decoder) {
283 unsigned Regs[] = {Mips::R16, Mips::R17, Mips::R18, Mips::R19};
284 unsigned RegLst = RegListEncoding;
285 unsigned RegNum = RegLst & 0x3;
286
287 for (unsigned i = 0; i <= RegNum; i++)
288 Inst.addOperand(Op: MCOperand::createReg(Reg: Regs[i]));
289
290 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::RA));
291
292 return MCDisassembler::Success;
293}
294
295template <typename InsnType>
296static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
297 const MCDisassembler *Decoder) {
298 using DecodeFN =
299 DecodeStatus (*)(MCInst &, unsigned, uint64_t, const MCDisassembler *);
300
301 // The size of the n field depends on the element size
302 // The register class also depends on this.
303 InsnType tmp = fieldFromInstruction(insn, 17, 5);
304 unsigned NSize = 0;
305 DecodeFN RegDecoder = nullptr;
306 if ((tmp & 0x18) == 0x00) { // INSVE_B
307 NSize = 4;
308 RegDecoder = DecodeMSA128BRegisterClass;
309 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
310 NSize = 3;
311 RegDecoder = DecodeMSA128HRegisterClass;
312 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
313 NSize = 2;
314 RegDecoder = DecodeMSA128WRegisterClass;
315 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
316 NSize = 1;
317 RegDecoder = DecodeMSA128DRegisterClass;
318 } else
319 llvm_unreachable("Invalid encoding");
320
321 assert(NSize != 0 && RegDecoder != nullptr);
322
323 // $wd
324 tmp = fieldFromInstruction(insn, 6, 5);
325 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
326 return MCDisassembler::Fail;
327 // $wd_in
328 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
329 return MCDisassembler::Fail;
330 // $n
331 tmp = fieldFromInstruction(insn, 16, NSize);
332 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
333 // $ws
334 tmp = fieldFromInstruction(insn, 11, 5);
335 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
336 return MCDisassembler::Fail;
337 // $n2
338 MI.addOperand(Op: MCOperand::createImm(Val: 0));
339
340 return MCDisassembler::Success;
341}
342
343template <typename InsnType>
344static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
345 const MCDisassembler *Decoder) {
346 InsnType Rs = fieldFromInstruction(insn, 21, 5);
347 InsnType Imm = fieldFromInstruction(insn, 0, 16);
348 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR64RegClassID,
349 Rs)));
350 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR64RegClassID,
351 Rs)));
352 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
353
354 return MCDisassembler::Success;
355}
356
357template <typename InsnType>
358static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
359 uint64_t Address,
360 const MCDisassembler *Decoder) {
361 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
362 // (otherwise we would have matched the ADDI instruction from the earlier
363 // ISA's instead).
364 //
365 // We have:
366 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
367 // BOVC if rs >= rt
368 // BEQZALC if rs == 0 && rt != 0
369 // BEQC if rs < rt && rs != 0
370
371 InsnType Rs = fieldFromInstruction(insn, 21, 5);
372 InsnType Rt = fieldFromInstruction(insn, 16, 5);
373 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
374 bool HasRs = false;
375
376 if (Rs >= Rt) {
377 MI.setOpcode(Mips::BOVC);
378 HasRs = true;
379 } else if (Rs != 0 && Rs < Rt) {
380 MI.setOpcode(Mips::BEQC);
381 HasRs = true;
382 } else
383 MI.setOpcode(Mips::BEQZALC);
384
385 if (HasRs)
386 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
387 Rs)));
388
389 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
390 Rt)));
391 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
392
393 return MCDisassembler::Success;
394}
395
396template <typename InsnType>
397static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn,
398 uint64_t Address,
399 const MCDisassembler *Decoder) {
400 InsnType Rt = fieldFromInstruction(insn, 21, 5);
401 InsnType Rs = fieldFromInstruction(insn, 16, 5);
402 int64_t Imm = 0;
403
404 if (Rs >= Rt) {
405 MI.setOpcode(Mips::BOVC_MMR6);
406 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
407 Rt)));
408 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
409 Rs)));
410 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
411 } else if (Rs != 0 && Rs < Rt) {
412 MI.setOpcode(Mips::BEQC_MMR6);
413 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
414 Rs)));
415 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
416 Rt)));
417 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
418 } else {
419 MI.setOpcode(Mips::BEQZALC_MMR6);
420 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
421 Rt)));
422 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
423 }
424
425 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
426
427 return MCDisassembler::Success;
428}
429
430template <typename InsnType>
431static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
432 uint64_t Address,
433 const MCDisassembler *Decoder) {
434 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
435 // (otherwise we would have matched the ADDI instruction from the earlier
436 // ISA's instead).
437 //
438 // We have:
439 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
440 // BNVC if rs >= rt
441 // BNEZALC if rs == 0 && rt != 0
442 // BNEC if rs < rt && rs != 0
443
444 InsnType Rs = fieldFromInstruction(insn, 21, 5);
445 InsnType Rt = fieldFromInstruction(insn, 16, 5);
446 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
447 bool HasRs = false;
448
449 if (Rs >= Rt) {
450 MI.setOpcode(Mips::BNVC);
451 HasRs = true;
452 } else if (Rs != 0 && Rs < Rt) {
453 MI.setOpcode(Mips::BNEC);
454 HasRs = true;
455 } else
456 MI.setOpcode(Mips::BNEZALC);
457
458 if (HasRs)
459 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
460 Rs)));
461
462 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
463 Rt)));
464 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
465
466 return MCDisassembler::Success;
467}
468
469template <typename InsnType>
470static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn,
471 uint64_t Address,
472 const MCDisassembler *Decoder) {
473 InsnType Rt = fieldFromInstruction(insn, 21, 5);
474 InsnType Rs = fieldFromInstruction(insn, 16, 5);
475 int64_t Imm = 0;
476
477 if (Rs >= Rt) {
478 MI.setOpcode(Mips::BNVC_MMR6);
479 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
480 Rt)));
481 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
482 Rs)));
483 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
484 } else if (Rs != 0 && Rs < Rt) {
485 MI.setOpcode(Mips::BNEC_MMR6);
486 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
487 Rs)));
488 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
489 Rt)));
490 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
491 } else {
492 MI.setOpcode(Mips::BNEZALC_MMR6);
493 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
494 Rt)));
495 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
496 }
497
498 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
499
500 return MCDisassembler::Success;
501}
502
503template <typename InsnType>
504static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn,
505 uint64_t Address,
506 const MCDisassembler *Decoder) {
507 // We have:
508 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii
509 // Invalid if rt == 0
510 // BGTZC_MMR6 if rs == 0 && rt != 0
511 // BLTZC_MMR6 if rs == rt && rt != 0
512 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0
513
514 InsnType Rt = fieldFromInstruction(insn, 21, 5);
515 InsnType Rs = fieldFromInstruction(insn, 16, 5);
516 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
517 bool HasRs = false;
518
519 if (Rt == 0)
520 return MCDisassembler::Fail;
521 else if (Rs == 0)
522 MI.setOpcode(Mips::BGTZC_MMR6);
523 else if (Rs == Rt)
524 MI.setOpcode(Mips::BLTZC_MMR6);
525 else {
526 MI.setOpcode(Mips::BLTC_MMR6);
527 HasRs = true;
528 }
529
530 if (HasRs)
531 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
532 Rs)));
533
534 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
535 Rt)));
536
537 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
538
539 return MCDisassembler::Success;
540}
541
542template <typename InsnType>
543static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn,
544 uint64_t Address,
545 const MCDisassembler *Decoder) {
546 // We have:
547 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii
548 // Invalid if rt == 0
549 // BLEZC_MMR6 if rs == 0 && rt != 0
550 // BGEZC_MMR6 if rs == rt && rt != 0
551 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0
552
553 InsnType Rt = fieldFromInstruction(insn, 21, 5);
554 InsnType Rs = fieldFromInstruction(insn, 16, 5);
555 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
556 bool HasRs = false;
557
558 if (Rt == 0)
559 return MCDisassembler::Fail;
560 else if (Rs == 0)
561 MI.setOpcode(Mips::BLEZC_MMR6);
562 else if (Rs == Rt)
563 MI.setOpcode(Mips::BGEZC_MMR6);
564 else {
565 HasRs = true;
566 MI.setOpcode(Mips::BGEC_MMR6);
567 }
568
569 if (HasRs)
570 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
571 Rs)));
572
573 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
574 Rt)));
575
576 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
577
578 return MCDisassembler::Success;
579}
580
581template <typename InsnType>
582static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
583 uint64_t Address,
584 const MCDisassembler *Decoder) {
585 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
586 // (otherwise we would have matched the BLEZL instruction from the earlier
587 // ISA's instead).
588 //
589 // We have:
590 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
591 // Invalid if rs == 0
592 // BLEZC if rs == 0 && rt != 0
593 // BGEZC if rs == rt && rt != 0
594 // BGEC if rs != rt && rs != 0 && rt != 0
595
596 InsnType Rs = fieldFromInstruction(insn, 21, 5);
597 InsnType Rt = fieldFromInstruction(insn, 16, 5);
598 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
599 bool HasRs = false;
600
601 if (Rt == 0)
602 return MCDisassembler::Fail;
603 else if (Rs == 0)
604 MI.setOpcode(Mips::BLEZC);
605 else if (Rs == Rt)
606 MI.setOpcode(Mips::BGEZC);
607 else {
608 HasRs = true;
609 MI.setOpcode(Mips::BGEC);
610 }
611
612 if (HasRs)
613 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
614 Rs)));
615
616 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
617 Rt)));
618
619 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
620
621 return MCDisassembler::Success;
622}
623
624template <typename InsnType>
625static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
626 uint64_t Address,
627 const MCDisassembler *Decoder) {
628 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
629 // (otherwise we would have matched the BGTZL instruction from the earlier
630 // ISA's instead).
631 //
632 // We have:
633 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
634 // Invalid if rs == 0
635 // BGTZC if rs == 0 && rt != 0
636 // BLTZC if rs == rt && rt != 0
637 // BLTC if rs != rt && rs != 0 && rt != 0
638
639 bool HasRs = false;
640
641 InsnType Rs = fieldFromInstruction(insn, 21, 5);
642 InsnType Rt = fieldFromInstruction(insn, 16, 5);
643 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
644
645 if (Rt == 0)
646 return MCDisassembler::Fail;
647 else if (Rs == 0)
648 MI.setOpcode(Mips::BGTZC);
649 else if (Rs == Rt)
650 MI.setOpcode(Mips::BLTZC);
651 else {
652 MI.setOpcode(Mips::BLTC);
653 HasRs = true;
654 }
655
656 if (HasRs)
657 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
658 Rs)));
659
660 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
661 Rt)));
662
663 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
664
665 return MCDisassembler::Success;
666}
667
668template <typename InsnType>
669static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
670 uint64_t Address,
671 const MCDisassembler *Decoder) {
672 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
673 // (otherwise we would have matched the BGTZ instruction from the earlier
674 // ISA's instead).
675 //
676 // We have:
677 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
678 // BGTZ if rt == 0
679 // BGTZALC if rs == 0 && rt != 0
680 // BLTZALC if rs != 0 && rs == rt
681 // BLTUC if rs != 0 && rs != rt
682
683 InsnType Rs = fieldFromInstruction(insn, 21, 5);
684 InsnType Rt = fieldFromInstruction(insn, 16, 5);
685 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
686 bool HasRs = false;
687 bool HasRt = false;
688
689 if (Rt == 0) {
690 MI.setOpcode(Mips::BGTZ);
691 HasRs = true;
692 } else if (Rs == 0) {
693 MI.setOpcode(Mips::BGTZALC);
694 HasRt = true;
695 } else if (Rs == Rt) {
696 MI.setOpcode(Mips::BLTZALC);
697 HasRs = true;
698 } else {
699 MI.setOpcode(Mips::BLTUC);
700 HasRs = true;
701 HasRt = true;
702 }
703
704 if (HasRs)
705 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
706 Rs)));
707
708 if (HasRt)
709 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
710 Rt)));
711
712 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
713
714 return MCDisassembler::Success;
715}
716
717template <typename InsnType>
718static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
719 uint64_t Address,
720 const MCDisassembler *Decoder) {
721 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
722 // (otherwise we would have matched the BLEZL instruction from the earlier
723 // ISA's instead).
724 //
725 // We have:
726 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
727 // Invalid if rs == 0
728 // BLEZALC if rs == 0 && rt != 0
729 // BGEZALC if rs == rt && rt != 0
730 // BGEUC if rs != rt && rs != 0 && rt != 0
731
732 InsnType Rs = fieldFromInstruction(insn, 21, 5);
733 InsnType Rt = fieldFromInstruction(insn, 16, 5);
734 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
735 bool HasRs = false;
736
737 if (Rt == 0)
738 return MCDisassembler::Fail;
739 else if (Rs == 0)
740 MI.setOpcode(Mips::BLEZALC);
741 else if (Rs == Rt)
742 MI.setOpcode(Mips::BGEZALC);
743 else {
744 HasRs = true;
745 MI.setOpcode(Mips::BGEUC);
746 }
747
748 if (HasRs)
749 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
750 Rs)));
751 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
752 Rt)));
753
754 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
755
756 return MCDisassembler::Success;
757}
758
759// Override the generated disassembler to produce DEXT all the time. This is
760// for feature / behaviour parity with binutils.
761template <typename InsnType>
762static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
763 const MCDisassembler *Decoder) {
764 unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
765 unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
766 unsigned Size = 0;
767 unsigned Pos = 0;
768
769 switch (MI.getOpcode()) {
770 case Mips::DEXT:
771 Pos = Lsb;
772 Size = Msbd + 1;
773 break;
774 case Mips::DEXTM:
775 Pos = Lsb;
776 Size = Msbd + 1 + 32;
777 break;
778 case Mips::DEXTU:
779 Pos = Lsb + 32;
780 Size = Msbd + 1;
781 break;
782 default:
783 llvm_unreachable("Unknown DEXT instruction!");
784 }
785
786 MI.setOpcode(Mips::DEXT);
787
788 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
789 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
790
791 MI.addOperand(
792 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR64RegClassID, Rt)));
793 MI.addOperand(
794 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR64RegClassID, Rs)));
795 MI.addOperand(Op: MCOperand::createImm(Val: Pos));
796 MI.addOperand(Op: MCOperand::createImm(Val: Size));
797
798 return MCDisassembler::Success;
799}
800
801// Override the generated disassembler to produce DINS all the time. This is
802// for feature / behaviour parity with binutils.
803template <typename InsnType>
804static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
805 const MCDisassembler *Decoder) {
806 unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
807 unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
808 unsigned Size = 0;
809 unsigned Pos = 0;
810
811 switch (MI.getOpcode()) {
812 case Mips::DINS:
813 Pos = Lsb;
814 Size = Msbd + 1 - Pos;
815 break;
816 case Mips::DINSM:
817 Pos = Lsb;
818 Size = Msbd + 33 - Pos;
819 break;
820 case Mips::DINSU:
821 Pos = Lsb + 32;
822 // mbsd = pos + size - 33
823 // mbsd - pos + 33 = size
824 Size = Msbd + 33 - Pos;
825 break;
826 default:
827 llvm_unreachable("Unknown DINS instruction!");
828 }
829
830 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
831 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
832
833 MI.setOpcode(Mips::DINS);
834 MI.addOperand(
835 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR64RegClassID, Rt)));
836 MI.addOperand(
837 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR64RegClassID, Rs)));
838 MI.addOperand(Op: MCOperand::createImm(Val: Pos));
839 MI.addOperand(Op: MCOperand::createImm(Val: Size));
840
841 return MCDisassembler::Success;
842}
843
844// Auto-generated decoder wouldn't add the third operand for CRC32*.
845template <typename InsnType>
846static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
847 const MCDisassembler *Decoder) {
848 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
849 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
850 MI.addOperand(
851 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID, Rt)));
852 MI.addOperand(
853 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID, Rs)));
854 MI.addOperand(
855 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID, Rt)));
856 return MCDisassembler::Success;
857}
858
859static DecodeStatus
860DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
861 const MCDisassembler *Decoder) {
862 return MCDisassembler::Fail;
863}
864
865static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
866 uint64_t Address,
867 const MCDisassembler *Decoder) {
868 if (RegNo > 31)
869 return MCDisassembler::Fail;
870
871 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPR64RegClassID, RegNo);
872 Inst.addOperand(Op: MCOperand::createReg(Reg));
873 return MCDisassembler::Success;
874}
875
876static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo,
877 uint64_t Address,
878 const MCDisassembler *Decoder) {
879 if (RegNo > 7)
880 return MCDisassembler::Fail;
881 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPRMM16RegClassID, RegNo);
882 Inst.addOperand(Op: MCOperand::createReg(Reg));
883 return MCDisassembler::Success;
884}
885
886static DecodeStatus
887DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
888 const MCDisassembler *Decoder) {
889 if (RegNo > 7)
890 return MCDisassembler::Fail;
891 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPRMM16ZeroRegClassID, RegNo);
892 Inst.addOperand(Op: MCOperand::createReg(Reg));
893 return MCDisassembler::Success;
894}
895
896static DecodeStatus
897DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
898 const MCDisassembler *Decoder) {
899 if (RegNo > 7)
900 return MCDisassembler::Fail;
901 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPRMM16MovePRegClassID, RegNo);
902 Inst.addOperand(Op: MCOperand::createReg(Reg));
903 return MCDisassembler::Success;
904}
905
906// Tablegen emits references to these unimplemented functions due to usage of
907// RegClassByHwMode - it does not detect that the RegClassByHwMode decoders are
908// unused, which in turn use these register class decoders.
909static DecodeStatus DecodeGP32RegisterClass(MCInst &Inst, unsigned RegNo,
910 uint64_t Address,
911 const MCDisassembler *Decoder) {
912 llvm_unreachable("this is unused");
913}
914
915static DecodeStatus DecodeGP64RegisterClass(MCInst &Inst, unsigned RegNo,
916 uint64_t Address,
917 const MCDisassembler *Decoder) {
918 llvm_unreachable("this is unused");
919}
920
921static DecodeStatus DecodeSP32RegisterClass(MCInst &Inst, unsigned RegNo,
922 uint64_t Address,
923 const MCDisassembler *Decoder) {
924 llvm_unreachable("this is unused");
925}
926
927static DecodeStatus DecodeSP64RegisterClass(MCInst &Inst, unsigned RegNo,
928 uint64_t Address,
929 const MCDisassembler *Decoder) {
930 llvm_unreachable("this is unused");
931}
932
933static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
934 uint64_t Address,
935 const MCDisassembler *Decoder) {
936 if (RegNo > 31)
937 return MCDisassembler::Fail;
938 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo);
939 Inst.addOperand(Op: MCOperand::createReg(Reg));
940 return MCDisassembler::Success;
941}
942
943static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo,
944 uint64_t Address,
945 const MCDisassembler *Decoder) {
946 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
947 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
948
949 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
950}
951
952template <unsigned RegNo>
953static DecodeStatus DecodeFixedPtrRegister(MCInst &Inst,
954 const MCDisassembler *Decoder) {
955 return DecodePtrRegisterClass(Inst, RegNo, Address: 0, Decoder);
956}
957
958static DecodeStatus DecodeLBU16Offset(MCInst &Inst, unsigned Value,
959 uint64_t Address,
960 const MCDisassembler *Decoder) {
961 Inst.addOperand(Op: MCOperand::createImm(Val: Value == 15 ? -1 : int64_t(Value)));
962 return MCDisassembler::Success;
963}
964
965static DecodeStatus DecodeGPR32Pair(MCInst &Inst, unsigned RegNo,
966 uint64_t Address,
967 const MCDisassembler *Decoder) {
968 if (RegNo >= 31)
969 return MCDisassembler::Fail;
970 DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
971 return DecodeGPR32RegisterClass(Inst, RegNo: RegNo + 1, Address, Decoder);
972}
973
974static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo,
975 uint64_t Address,
976 const MCDisassembler *Decoder) {
977 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
978}
979
980static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
981 uint64_t Address,
982 const MCDisassembler *Decoder) {
983 if (RegNo > 31)
984 return MCDisassembler::Fail;
985
986 MCRegister Reg = getReg(D: Decoder, RC: Mips::FGR64RegClassID, RegNo);
987 Inst.addOperand(Op: MCOperand::createReg(Reg));
988 return MCDisassembler::Success;
989}
990
991static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo,
992 uint64_t Address,
993 const MCDisassembler *Decoder) {
994 if (RegNo > 31)
995 return MCDisassembler::Fail;
996
997 MCRegister Reg = getReg(D: Decoder, RC: Mips::FGR32RegClassID, RegNo);
998 Inst.addOperand(Op: MCOperand::createReg(Reg));
999 return MCDisassembler::Success;
1000}
1001
1002static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo,
1003 uint64_t Address,
1004 const MCDisassembler *Decoder) {
1005 if (RegNo > 31)
1006 return MCDisassembler::Fail;
1007 MCRegister Reg = getReg(D: Decoder, RC: Mips::CCRRegClassID, RegNo);
1008 Inst.addOperand(Op: MCOperand::createReg(Reg));
1009 return MCDisassembler::Success;
1010}
1011
1012static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo,
1013 uint64_t Address,
1014 const MCDisassembler *Decoder) {
1015 if (RegNo > 7)
1016 return MCDisassembler::Fail;
1017 MCRegister Reg = getReg(D: Decoder, RC: Mips::FCCRegClassID, RegNo);
1018 Inst.addOperand(Op: MCOperand::createReg(Reg));
1019 return MCDisassembler::Success;
1020}
1021
1022static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset,
1023 uint64_t Address,
1024 const MCDisassembler *Decoder) {
1025 int32_t BranchOffset = (SignExtend32<16>(X: Offset) * 4) + 4;
1026 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1027 return MCDisassembler::Success;
1028}
1029
1030static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset,
1031 uint64_t Address,
1032 const MCDisassembler *Decoder) {
1033 int32_t BranchOffset = (SignExtend32<16>(X: Offset) * 2);
1034 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1035 return MCDisassembler::Success;
1036}
1037
1038static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn,
1039 uint64_t Address,
1040 const MCDisassembler *Decoder) {
1041 unsigned JumpOffset = fieldFromInstruction(Insn, StartBit: 0, NumBits: 26) << 2;
1042 Inst.addOperand(Op: MCOperand::createImm(Val: JumpOffset));
1043 return MCDisassembler::Success;
1044}
1045
1046static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset,
1047 uint64_t Address,
1048 const MCDisassembler *Decoder) {
1049 int32_t BranchOffset = SignExtend32<21>(X: Offset) * 4 + 4;
1050
1051 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1052 return MCDisassembler::Success;
1053}
1054
1055static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset,
1056 uint64_t Address,
1057 const MCDisassembler *Decoder) {
1058 int32_t BranchOffset = SignExtend32<21>(X: Offset) * 4 + 4;
1059
1060 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1061 return MCDisassembler::Success;
1062}
1063
1064static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset,
1065 uint64_t Address,
1066 const MCDisassembler *Decoder) {
1067 int32_t BranchOffset = SignExtend32<26>(X: Offset) * 4 + 4;
1068
1069 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1070 return MCDisassembler::Success;
1071}
1072
1073static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset,
1074 uint64_t Address,
1075 const MCDisassembler *Decoder) {
1076 int32_t BranchOffset = SignExtend32<8>(X: Offset << 1);
1077 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1078 return MCDisassembler::Success;
1079}
1080
1081static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset,
1082 uint64_t Address,
1083 const MCDisassembler *Decoder) {
1084 int32_t BranchOffset = SignExtend32<11>(X: Offset << 1);
1085 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1086 return MCDisassembler::Success;
1087}
1088
1089static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset,
1090 uint64_t Address,
1091 const MCDisassembler *Decoder) {
1092 int32_t BranchOffset = SignExtend32<16>(X: Offset) * 2 + 4;
1093 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1094 return MCDisassembler::Success;
1095}
1096
1097static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset,
1098 uint64_t Address,
1099 const MCDisassembler *Decoder) {
1100 int32_t BranchOffset = SignExtend32<27>(X: Offset << 1);
1101
1102 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1103 return MCDisassembler::Success;
1104}
1105
1106static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn,
1107 uint64_t Address,
1108 const MCDisassembler *Decoder) {
1109 unsigned JumpOffset = fieldFromInstruction(Insn, StartBit: 0, NumBits: 26) << 1;
1110 Inst.addOperand(Op: MCOperand::createImm(Val: JumpOffset));
1111 return MCDisassembler::Success;
1112}
1113
1114static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn,
1115 uint64_t Address,
1116 const MCDisassembler *Decoder) {
1117 unsigned JumpOffset = fieldFromInstruction(Insn, StartBit: 0, NumBits: 26) << 2;
1118 Inst.addOperand(Op: MCOperand::createImm(Val: JumpOffset));
1119 return MCDisassembler::Success;
1120}
1121
1122static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value,
1123 uint64_t Address,
1124 const MCDisassembler *Decoder) {
1125 if (Value == 0)
1126 Inst.addOperand(Op: MCOperand::createImm(Val: 1));
1127 else if (Value == 0x7)
1128 Inst.addOperand(Op: MCOperand::createImm(Val: -1));
1129 else
1130 Inst.addOperand(Op: MCOperand::createImm(Val: Value << 2));
1131 return MCDisassembler::Success;
1132}
1133
1134static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value,
1135 uint64_t Address,
1136 const MCDisassembler *Decoder) {
1137 if (Value == 0x7F)
1138 Inst.addOperand(Op: MCOperand::createImm(Val: -1));
1139 else
1140 Inst.addOperand(Op: MCOperand::createImm(Val: Value));
1141 return MCDisassembler::Success;
1142}
1143
1144static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value,
1145 uint64_t Address,
1146 const MCDisassembler *Decoder) {
1147 Inst.addOperand(Op: MCOperand::createImm(Val: Value == 0x0 ? 8 : Value));
1148 return MCDisassembler::Success;
1149}
1150
1151template <unsigned Bits, int Offset, int Scale>
1152static DecodeStatus
1153DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address,
1154 const MCDisassembler *Decoder) {
1155 Value &= ((1 << Bits) - 1);
1156 Value *= Scale;
1157 Inst.addOperand(Op: MCOperand::createImm(Val: Value + Offset));
1158 return MCDisassembler::Success;
1159}
1160
1161template <unsigned Bits, int Offset = 0, int ScaleBy = 1>
1162static DecodeStatus
1163DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address,
1164 const MCDisassembler *Decoder) {
1165 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy;
1166 Inst.addOperand(Op: MCOperand::createImm(Val: Imm + Offset));
1167 return MCDisassembler::Success;
1168}
1169
1170template <unsigned Bits, int Offset>
1171static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
1172 uint64_t Address,
1173 const MCDisassembler *Decoder) {
1174 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address,
1175 Decoder);
1176}
1177
1178static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address,
1179 const MCDisassembler *Decoder) {
1180 // First we need to grab the pos(lsb) from MCInst.
1181 // This function only handles the 32 bit variants of ins, as dins
1182 // variants are handled differently.
1183 int Pos = Inst.getOperand(i: 2).getImm();
1184 int Size = (int) Insn - Pos + 1;
1185 Inst.addOperand(Op: MCOperand::createImm(Val: SignExtend32<16>(X: Size)));
1186 return MCDisassembler::Success;
1187}
1188
1189static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1190 uint64_t Address,
1191 const MCDisassembler *Decoder) {
1192 Inst.addOperand(Op: MCOperand::createImm(Val: SignExtend32<19>(X: Insn) * 4));
1193 return MCDisassembler::Success;
1194}
1195
1196static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1197 uint64_t Address,
1198 const MCDisassembler *Decoder) {
1199 Inst.addOperand(Op: MCOperand::createImm(Val: SignExtend32<18>(X: Insn) * 8));
1200 return MCDisassembler::Success;
1201}
1202
1203static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address,
1204 const MCDisassembler *Decoder) {
1205 int32_t DecodedValue;
1206 switch (Insn) {
1207 case 0: DecodedValue = 256; break;
1208 case 1: DecodedValue = 257; break;
1209 case 510: DecodedValue = -258; break;
1210 case 511: DecodedValue = -257; break;
1211 default: DecodedValue = SignExtend32<9>(X: Insn); break;
1212 }
1213 Inst.addOperand(Op: MCOperand::createImm(Val: DecodedValue * 4));
1214 return MCDisassembler::Success;
1215}
1216
1217static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1218 uint64_t Address,
1219 const MCDisassembler *Decoder) {
1220 // Insn must be >= 0, since it is unsigned that condition is always true.
1221 assert(Insn < 16);
1222 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15,
1223 16, 31, 32, 63, 64, 255, 32768, 65535};
1224 Inst.addOperand(Op: MCOperand::createImm(Val: DecodedValues[Insn]));
1225 return MCDisassembler::Success;
1226}
1227
1228static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
1229 uint64_t Address,
1230 const MCDisassembler *Decoder) {
1231 switch (RegPair) {
1232 default:
1233 return MCDisassembler::Fail;
1234 case 0:
1235 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::R5));
1236 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::R6));
1237 break;
1238 case 1:
1239 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::R5));
1240 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::R7));
1241 break;
1242 case 2:
1243 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::R6));
1244 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::R7));
1245 break;
1246 case 3:
1247 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::R4));
1248 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::R21));
1249 break;
1250 case 4:
1251 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::R4));
1252 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::R22));
1253 break;
1254 case 5:
1255 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::R4));
1256 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::R5));
1257 break;
1258 case 6:
1259 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::R4));
1260 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::R6));
1261 break;
1262 case 7:
1263 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::R4));
1264 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::R7));
1265 break;
1266 }
1267
1268 return MCDisassembler::Success;
1269}
1270
1271static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
1272 uint64_t Address,
1273 const MCDisassembler *Decoder) {
1274 unsigned RegPair = fieldFromInstruction(Insn, StartBit: 7, NumBits: 3);
1275 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) ==
1276 MCDisassembler::Fail)
1277 return MCDisassembler::Fail;
1278
1279 unsigned RegRs;
1280 if (static_cast<const MipsDisassembler *>(Decoder)->hasMips32r6())
1281 RegRs = fieldFromInstruction(Insn, StartBit: 0, NumBits: 2) |
1282 (fieldFromInstruction(Insn, StartBit: 3, NumBits: 1) << 2);
1283 else
1284 RegRs = fieldFromInstruction(Insn, StartBit: 1, NumBits: 3);
1285 if (DecodeGPRMM16MovePRegisterClass(Inst, RegNo: RegRs, Address, Decoder) ==
1286 MCDisassembler::Fail)
1287 return MCDisassembler::Fail;
1288
1289 unsigned RegRt = fieldFromInstruction(Insn, StartBit: 4, NumBits: 3);
1290 if (DecodeGPRMM16MovePRegisterClass(Inst, RegNo: RegRt, Address, Decoder) ==
1291 MCDisassembler::Fail)
1292 return MCDisassembler::Fail;
1293
1294 return MCDisassembler::Success;
1295}
1296
1297static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
1298 uint64_t Address,
1299 const MCDisassembler *Decoder) {
1300 Inst.addOperand(Op: MCOperand::createImm(Val: SignExtend32<25>(X: Insn << 2)));
1301 return MCDisassembler::Success;
1302}
1303
1304template <typename InsnType>
1305static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn,
1306 uint64_t Address,
1307 const MCDisassembler *Decoder) {
1308 // We have:
1309 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii
1310 // Invalid if rt == 0
1311 // BGTZALC_MMR6 if rs == 0 && rt != 0
1312 // BLTZALC_MMR6 if rs != 0 && rs == rt
1313 // BLTUC_MMR6 if rs != 0 && rs != rt
1314
1315 InsnType Rt = fieldFromInstruction(insn, 21, 5);
1316 InsnType Rs = fieldFromInstruction(insn, 16, 5);
1317 InsnType Imm = 0;
1318 bool HasRs = false;
1319 bool HasRt = false;
1320
1321 if (Rt == 0)
1322 return MCDisassembler::Fail;
1323 else if (Rs == 0) {
1324 MI.setOpcode(Mips::BGTZALC_MMR6);
1325 HasRt = true;
1326 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1327 }
1328 else if (Rs == Rt) {
1329 MI.setOpcode(Mips::BLTZALC_MMR6);
1330 HasRs = true;
1331 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1332 }
1333 else {
1334 MI.setOpcode(Mips::BLTUC_MMR6);
1335 HasRs = true;
1336 HasRt = true;
1337 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
1338 }
1339
1340 if (HasRs)
1341 MI.addOperand(
1342 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID, Rs)));
1343
1344 if (HasRt)
1345 MI.addOperand(
1346 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID, Rt)));
1347
1348 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
1349
1350 return MCDisassembler::Success;
1351}
1352
1353template <typename InsnType>
1354static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn,
1355 uint64_t Address,
1356 const MCDisassembler *Decoder) {
1357 // We have:
1358 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii
1359 // Invalid if rt == 0
1360 // BLEZALC_MMR6 if rs == 0 && rt != 0
1361 // BGEZALC_MMR6 if rs == rt && rt != 0
1362 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0
1363
1364 InsnType Rt = fieldFromInstruction(insn, 21, 5);
1365 InsnType Rs = fieldFromInstruction(insn, 16, 5);
1366 InsnType Imm = 0;
1367 bool HasRs = false;
1368
1369 if (Rt == 0)
1370 return MCDisassembler::Fail;
1371 else if (Rs == 0) {
1372 MI.setOpcode(Mips::BLEZALC_MMR6);
1373 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1374 }
1375 else if (Rs == Rt) {
1376 MI.setOpcode(Mips::BGEZALC_MMR6);
1377 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1378 }
1379 else {
1380 HasRs = true;
1381 MI.setOpcode(Mips::BGEUC_MMR6);
1382 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
1383 }
1384
1385 if (HasRs)
1386 MI.addOperand(
1387 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID, Rs)));
1388 MI.addOperand(
1389 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID, Rt)));
1390
1391 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
1392
1393 return MCDisassembler::Success;
1394}
1395
1396// This instruction does not have a working decoder, and needs to be
1397// fixed. This "fixme" function was introduced to keep the backend compiling,
1398// while making changes to tablegen code.
1399static DecodeStatus DecodeFIXMEInstruction(MCInst &Inst, unsigned Insn,
1400 uint64_t Address,
1401 const MCDisassembler *Decoder) {
1402 return MCDisassembler::Fail;
1403}
1404
1405#include "MipsGenDisassemblerTables.inc"
1406
1407/// Read two bytes from the ArrayRef and return 16 bit halfword sorted
1408/// according to the given endianness.
1409static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
1410 uint64_t &Size, uint32_t &Insn,
1411 bool IsBigEndian) {
1412 // We want to read exactly 2 Bytes of data.
1413 if (Bytes.size() < 2) {
1414 Size = 0;
1415 return MCDisassembler::Fail;
1416 }
1417
1418 if (IsBigEndian) {
1419 Insn = (Bytes[0] << 8) | Bytes[1];
1420 } else {
1421 Insn = (Bytes[1] << 8) | Bytes[0];
1422 }
1423
1424 return MCDisassembler::Success;
1425}
1426
1427/// Read four bytes from the ArrayRef and return 32 bit word sorted
1428/// according to the given endianness.
1429static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
1430 uint64_t &Size, uint32_t &Insn,
1431 bool IsBigEndian, bool IsMicroMips) {
1432 // We want to read exactly 4 Bytes of data.
1433 if (Bytes.size() < 4) {
1434 Size = 0;
1435 return MCDisassembler::Fail;
1436 }
1437
1438 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
1439 // always precede the low 16 bits in the instruction stream (that is, they
1440 // are placed at lower addresses in the instruction stream).
1441 //
1442 // microMIPS byte ordering:
1443 // Big-endian: 0 | 1 | 2 | 3
1444 // Little-endian: 1 | 0 | 3 | 2
1445
1446 if (IsBigEndian) {
1447 // Encoded as a big-endian 32-bit word in the stream.
1448 Insn =
1449 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
1450 } else {
1451 if (IsMicroMips) {
1452 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
1453 (Bytes[1] << 24);
1454 } else {
1455 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
1456 (Bytes[3] << 24);
1457 }
1458 }
1459
1460 return MCDisassembler::Success;
1461}
1462
1463DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
1464 ArrayRef<uint8_t> Bytes,
1465 uint64_t Address,
1466 raw_ostream &CStream) const {
1467 uint32_t Insn;
1468 DecodeStatus Result;
1469 Size = 0;
1470
1471 if (IsMicroMips) {
1472 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
1473 if (Result == MCDisassembler::Fail)
1474 return MCDisassembler::Fail;
1475
1476 if (hasMips32r6()) {
1477 LLVM_DEBUG(
1478 dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
1479 // Calling the auto-generated decoder function for microMIPS32R6
1480 // 16-bit instructions.
1481 Result = decodeInstruction(DecodeTable: DecoderTableMicroMipsR616, MI&: Instr, insn: Insn,
1482 Address, DisAsm: this, STI);
1483 if (Result != MCDisassembler::Fail) {
1484 Size = 2;
1485 return Result;
1486 }
1487 }
1488
1489 LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
1490 // Calling the auto-generated decoder function for microMIPS 16-bit
1491 // instructions.
1492 Result = decodeInstruction(DecodeTable: DecoderTableMicroMips16, MI&: Instr, insn: Insn, Address,
1493 DisAsm: this, STI);
1494 if (Result != MCDisassembler::Fail) {
1495 Size = 2;
1496 return Result;
1497 }
1498
1499 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, IsMicroMips: true);
1500 if (Result == MCDisassembler::Fail)
1501 return MCDisassembler::Fail;
1502
1503 if (hasMips32r6()) {
1504 LLVM_DEBUG(
1505 dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
1506 // Calling the auto-generated decoder function.
1507 Result = decodeInstruction(DecodeTable: DecoderTableMicroMipsR632, MI&: Instr, insn: Insn,
1508 Address, DisAsm: this, STI);
1509 if (Result != MCDisassembler::Fail) {
1510 Size = 4;
1511 return Result;
1512 }
1513 }
1514
1515 LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
1516 // Calling the auto-generated decoder function.
1517 Result = decodeInstruction(DecodeTable: DecoderTableMicroMips32, MI&: Instr, insn: Insn, Address,
1518 DisAsm: this, STI);
1519 if (Result != MCDisassembler::Fail) {
1520 Size = 4;
1521 return Result;
1522 }
1523
1524 if (isFP64()) {
1525 LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n");
1526 Result = decodeInstruction(DecodeTable: DecoderTableMicroMipsFP6432, MI&: Instr, insn: Insn,
1527 Address, DisAsm: this, STI);
1528 if (Result != MCDisassembler::Fail) {
1529 Size = 4;
1530 return Result;
1531 }
1532 }
1533
1534 // This is an invalid instruction. Claim that the Size is 2 bytes. Since
1535 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes
1536 // could form a valid instruction. The two bytes we rejected as an
1537 // instruction could have actually beeen an inline constant pool that is
1538 // unconditionally branched over.
1539 Size = 2;
1540 return MCDisassembler::Fail;
1541 }
1542
1543 // Attempt to read the instruction so that we can attempt to decode it. If
1544 // the buffer is not 4 bytes long, let the higher level logic figure out
1545 // what to do with a size of zero and MCDisassembler::Fail.
1546 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, IsMicroMips: false);
1547 if (Result == MCDisassembler::Fail)
1548 return MCDisassembler::Fail;
1549
1550 // The only instruction size for standard encoded MIPS.
1551 Size = 4;
1552
1553 if (hasCOP3()) {
1554 LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
1555 Result =
1556 decodeInstruction(DecodeTable: DecoderTableCOP3_32, MI&: Instr, insn: Insn, Address, DisAsm: this, STI);
1557 if (Result != MCDisassembler::Fail)
1558 return Result;
1559 }
1560
1561 if (hasMips32r6() && isGP64()) {
1562 LLVM_DEBUG(
1563 dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
1564 Result = decodeInstruction(DecodeTable: DecoderTableMips32r6_64r6_GP6432, MI&: Instr, insn: Insn,
1565 Address, DisAsm: this, STI);
1566 if (Result != MCDisassembler::Fail)
1567 return Result;
1568 }
1569
1570 if (hasMips32r6() && isPTR64()) {
1571 LLVM_DEBUG(
1572 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1573 Result = decodeInstruction(DecodeTable: DecoderTableMips32r6_64r6_PTR6432, MI&: Instr, insn: Insn,
1574 Address, DisAsm: this, STI);
1575 if (Result != MCDisassembler::Fail)
1576 return Result;
1577 }
1578
1579 if (hasMips32r6()) {
1580 LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
1581 Result = decodeInstruction(DecodeTable: DecoderTableMips32r6_64r632, MI&: Instr, insn: Insn,
1582 Address, DisAsm: this, STI);
1583 if (Result != MCDisassembler::Fail)
1584 return Result;
1585 }
1586
1587 if (hasMips2() && isPTR64()) {
1588 LLVM_DEBUG(
1589 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1590 Result = decodeInstruction(DecodeTable: DecoderTableMips32_64_PTR6432, MI&: Instr, insn: Insn,
1591 Address, DisAsm: this, STI);
1592 if (Result != MCDisassembler::Fail)
1593 return Result;
1594 }
1595
1596 if (hasCnMips()) {
1597 LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
1598 Result = decodeInstruction(DecodeTable: DecoderTableCnMips32, MI&: Instr, insn: Insn, Address, DisAsm: this,
1599 STI);
1600 if (Result != MCDisassembler::Fail)
1601 return Result;
1602 }
1603
1604 if (hasCnMipsP()) {
1605 LLVM_DEBUG(dbgs() << "Trying CnMipsP table (32-bit opcodes):\n");
1606 Result = decodeInstruction(DecodeTable: DecoderTableCnMipsP32, MI&: Instr, insn: Insn, Address,
1607 DisAsm: this, STI);
1608 if (Result != MCDisassembler::Fail)
1609 return Result;
1610 }
1611
1612 if (isGP64()) {
1613 LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
1614 Result = decodeInstruction(DecodeTable: DecoderTableMips6432, MI&: Instr, insn: Insn, Address, DisAsm: this,
1615 STI);
1616 if (Result != MCDisassembler::Fail)
1617 return Result;
1618 }
1619
1620 if (isFP64()) {
1621 LLVM_DEBUG(
1622 dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n");
1623 Result = decodeInstruction(DecodeTable: DecoderTableMipsFP6432, MI&: Instr, insn: Insn, Address,
1624 DisAsm: this, STI);
1625 if (Result != MCDisassembler::Fail)
1626 return Result;
1627 }
1628
1629 LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
1630 // Calling the auto-generated decoder function.
1631 Result =
1632 decodeInstruction(DecodeTable: DecoderTableMips32, MI&: Instr, insn: Insn, Address, DisAsm: this, STI);
1633 if (Result != MCDisassembler::Fail)
1634 return Result;
1635
1636 return MCDisassembler::Fail;
1637}
1638