1//===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file is part of the Mips Disassembler.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/MipsMCTargetDesc.h"
14#include "TargetInfo/MipsTargetInfo.h"
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCDecoder.h"
18#include "llvm/MC/MCDecoderOps.h"
19#include "llvm/MC/MCDisassembler/MCDisassembler.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/MC/TargetRegistry.h"
24#include "llvm/Support/Compiler.h"
25#include "llvm/Support/Debug.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/MathExtras.h"
28#include "llvm/Support/raw_ostream.h"
29#include <cassert>
30#include <cstdint>
31
32using namespace llvm;
33using namespace llvm::MCD;
34
35#define DEBUG_TYPE "mips-disassembler"
36
37using DecodeStatus = MCDisassembler::DecodeStatus;
38
39namespace {
40
41class MipsDisassembler : public MCDisassembler {
42 bool IsMicroMips;
43 bool IsBigEndian;
44
45public:
46 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
47 : MCDisassembler(STI, Ctx),
48 IsMicroMips(STI.hasFeature(Feature: Mips::FeatureMicroMips)),
49 IsBigEndian(IsBigEndian) {}
50
51 bool hasMips2() const { return STI.hasFeature(Feature: Mips::FeatureMips2); }
52 bool hasMips3() const { return STI.hasFeature(Feature: Mips::FeatureMips3); }
53 bool hasMips32() const { return STI.hasFeature(Feature: Mips::FeatureMips32); }
54
55 bool hasMips32r6() const {
56 return STI.hasFeature(Feature: Mips::FeatureMips32r6);
57 }
58
59 bool isFP64() const { return STI.hasFeature(Feature: Mips::FeatureFP64Bit); }
60
61 bool isGP64() const { return STI.hasFeature(Feature: Mips::FeatureGP64Bit); }
62
63 bool isPTR64() const { return STI.hasFeature(Feature: Mips::FeaturePTR64Bit); }
64
65 bool hasCnMips() const { return STI.hasFeature(Feature: Mips::FeatureCnMips); }
66
67 bool hasCnMipsP() const { return STI.hasFeature(Feature: Mips::FeatureCnMipsP); }
68
69 bool hasCOP3() const {
70 // Only present in MIPS-I and MIPS-II
71 return !hasMips32() && !hasMips3();
72 }
73
74 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
75 ArrayRef<uint8_t> Bytes, uint64_t Address,
76 raw_ostream &CStream) const override;
77};
78
79} // end anonymous namespace
80
81static MCDisassembler *createMipsDisassembler(const Target &T,
82 const MCSubtargetInfo &STI,
83 MCContext &Ctx) {
84 return new MipsDisassembler(STI, Ctx, true);
85}
86
87static MCDisassembler *createMipselDisassembler(const Target &T,
88 const MCSubtargetInfo &STI,
89 MCContext &Ctx) {
90 return new MipsDisassembler(STI, Ctx, false);
91}
92
93extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
94LLVMInitializeMipsDisassembler() {
95 // Register the disassembler.
96 TargetRegistry::RegisterMCDisassembler(T&: getTheMipsTarget(),
97 Fn: createMipsDisassembler);
98 TargetRegistry::RegisterMCDisassembler(T&: getTheMipselTarget(),
99 Fn: createMipselDisassembler);
100 TargetRegistry::RegisterMCDisassembler(T&: getTheMips64Target(),
101 Fn: createMipsDisassembler);
102 TargetRegistry::RegisterMCDisassembler(T&: getTheMips64elTarget(),
103 Fn: createMipselDisassembler);
104}
105
106static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo) {
107 const MCRegisterInfo *RegInfo = D->getContext().getRegisterInfo();
108 return RegInfo->getRegClass(i: RC).getRegister(i: RegNo);
109}
110static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo,
111 uint64_t Address,
112 const MCDisassembler *Decoder) {
113 // Currently only hardware register 29 is supported.
114 if (RegNo != 29)
115 return MCDisassembler::Fail;
116 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::HWR29));
117 return MCDisassembler::Success;
118}
119
120static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
121 uint64_t Address,
122 const MCDisassembler *Decoder) {
123 if (RegNo > 30 || RegNo % 2)
124 return MCDisassembler::Fail;
125
126 MCRegister Reg = getReg(D: Decoder, RC: Mips::AFGR64RegClassID, RegNo: RegNo / 2);
127 Inst.addOperand(Op: MCOperand::createReg(Reg));
128 return MCDisassembler::Success;
129}
130
131static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo,
132 uint64_t Address,
133 const MCDisassembler *Decoder) {
134 if (RegNo >= 4)
135 return MCDisassembler::Fail;
136
137 MCRegister Reg = getReg(D: Decoder, RC: Mips::ACC64DSPRegClassID, RegNo);
138 Inst.addOperand(Op: MCOperand::createReg(Reg));
139 return MCDisassembler::Success;
140}
141
142static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
143 uint64_t Address,
144 const MCDisassembler *Decoder) {
145 if (RegNo >= 4)
146 return MCDisassembler::Fail;
147
148 MCRegister Reg = getReg(D: Decoder, RC: Mips::HI32DSPRegClassID, RegNo);
149 Inst.addOperand(Op: MCOperand::createReg(Reg));
150 return MCDisassembler::Success;
151}
152
153static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
154 uint64_t Address,
155 const MCDisassembler *Decoder) {
156 if (RegNo >= 4)
157 return MCDisassembler::Fail;
158
159 MCRegister Reg = getReg(D: Decoder, RC: Mips::LO32DSPRegClassID, RegNo);
160 Inst.addOperand(Op: MCOperand::createReg(Reg));
161 return MCDisassembler::Success;
162}
163
164static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo,
165 uint64_t Address,
166 const MCDisassembler *Decoder) {
167 if (RegNo > 31)
168 return MCDisassembler::Fail;
169
170 MCRegister Reg = getReg(D: Decoder, RC: Mips::MSA128BRegClassID, RegNo);
171 Inst.addOperand(Op: MCOperand::createReg(Reg));
172 return MCDisassembler::Success;
173}
174
175static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo,
176 uint64_t Address,
177 const MCDisassembler *Decoder) {
178 if (RegNo > 31)
179 return MCDisassembler::Fail;
180
181 MCRegister Reg = getReg(D: Decoder, RC: Mips::MSA128HRegClassID, RegNo);
182 Inst.addOperand(Op: MCOperand::createReg(Reg));
183 return MCDisassembler::Success;
184}
185
186static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo,
187 uint64_t Address,
188 const MCDisassembler *Decoder) {
189 if (RegNo > 31)
190 return MCDisassembler::Fail;
191
192 MCRegister Reg = getReg(D: Decoder, RC: Mips::MSA128WRegClassID, RegNo);
193 Inst.addOperand(Op: MCOperand::createReg(Reg));
194 return MCDisassembler::Success;
195}
196
197static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo,
198 uint64_t Address,
199 const MCDisassembler *Decoder) {
200 if (RegNo > 31)
201 return MCDisassembler::Fail;
202
203 MCRegister Reg = getReg(D: Decoder, RC: Mips::MSA128DRegClassID, RegNo);
204 Inst.addOperand(Op: MCOperand::createReg(Reg));
205 return MCDisassembler::Success;
206}
207
208static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo,
209 uint64_t Address,
210 const MCDisassembler *Decoder) {
211 if (RegNo > 7)
212 return MCDisassembler::Fail;
213
214 MCRegister Reg = getReg(D: Decoder, RC: Mips::MSACtrlRegClassID, RegNo);
215 Inst.addOperand(Op: MCOperand::createReg(Reg));
216 return MCDisassembler::Success;
217}
218
219static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo,
220 uint64_t Address,
221 const MCDisassembler *Decoder) {
222 if (RegNo > 31)
223 return MCDisassembler::Fail;
224
225 MCRegister Reg = getReg(D: Decoder, RC: Mips::COP0RegClassID, RegNo);
226 Inst.addOperand(Op: MCOperand::createReg(Reg));
227 return MCDisassembler::Success;
228}
229
230static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo,
231 uint64_t Address,
232 const MCDisassembler *Decoder) {
233 if (RegNo > 31)
234 return MCDisassembler::Fail;
235
236 MCRegister Reg = getReg(D: Decoder, RC: Mips::COP2RegClassID, RegNo);
237 Inst.addOperand(Op: MCOperand::createReg(Reg));
238 return MCDisassembler::Success;
239}
240
241static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
242 uint64_t Address,
243 const MCDisassembler *Decoder) {
244 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4,
245 Mips::S5, Mips::S6, Mips::S7, Mips::FP};
246 unsigned RegNum;
247
248 unsigned RegLst = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
249
250 // Empty register lists are not allowed.
251 if (RegLst == 0)
252 return MCDisassembler::Fail;
253
254 RegNum = RegLst & 0xf;
255
256 // RegLst values 10-15, and 26-31 are reserved.
257 if (RegNum > 9)
258 return MCDisassembler::Fail;
259
260 for (unsigned i = 0; i < RegNum; i++)
261 Inst.addOperand(Op: MCOperand::createReg(Reg: Regs[i]));
262
263 if (RegLst & 0x10)
264 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::RA));
265
266 return MCDisassembler::Success;
267}
268
269static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
270 uint64_t Address,
271 const MCDisassembler *Decoder) {
272 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
273 unsigned RegLst;
274 switch (Inst.getOpcode()) {
275 default:
276 RegLst = fieldFromInstruction(Insn, StartBit: 4, NumBits: 2);
277 break;
278 case Mips::LWM16_MMR6:
279 case Mips::SWM16_MMR6:
280 RegLst = fieldFromInstruction(Insn, StartBit: 8, NumBits: 2);
281 break;
282 }
283 unsigned RegNum = RegLst & 0x3;
284
285 for (unsigned i = 0; i <= RegNum; i++)
286 Inst.addOperand(Op: MCOperand::createReg(Reg: Regs[i]));
287
288 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::RA));
289
290 return MCDisassembler::Success;
291}
292
293template <typename InsnType>
294static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
295 const MCDisassembler *Decoder) {
296 using DecodeFN =
297 DecodeStatus (*)(MCInst &, unsigned, uint64_t, const MCDisassembler *);
298
299 // The size of the n field depends on the element size
300 // The register class also depends on this.
301 InsnType tmp = fieldFromInstruction(insn, 17, 5);
302 unsigned NSize = 0;
303 DecodeFN RegDecoder = nullptr;
304 if ((tmp & 0x18) == 0x00) { // INSVE_B
305 NSize = 4;
306 RegDecoder = DecodeMSA128BRegisterClass;
307 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
308 NSize = 3;
309 RegDecoder = DecodeMSA128HRegisterClass;
310 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
311 NSize = 2;
312 RegDecoder = DecodeMSA128WRegisterClass;
313 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
314 NSize = 1;
315 RegDecoder = DecodeMSA128DRegisterClass;
316 } else
317 llvm_unreachable("Invalid encoding");
318
319 assert(NSize != 0 && RegDecoder != nullptr);
320
321 // $wd
322 tmp = fieldFromInstruction(insn, 6, 5);
323 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
324 return MCDisassembler::Fail;
325 // $wd_in
326 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
327 return MCDisassembler::Fail;
328 // $n
329 tmp = fieldFromInstruction(insn, 16, NSize);
330 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
331 // $ws
332 tmp = fieldFromInstruction(insn, 11, 5);
333 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
334 return MCDisassembler::Fail;
335 // $n2
336 MI.addOperand(Op: MCOperand::createImm(Val: 0));
337
338 return MCDisassembler::Success;
339}
340
341template <typename InsnType>
342static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
343 const MCDisassembler *Decoder) {
344 InsnType Rs = fieldFromInstruction(insn, 21, 5);
345 InsnType Imm = fieldFromInstruction(insn, 0, 16);
346 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR64RegClassID,
347 Rs)));
348 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR64RegClassID,
349 Rs)));
350 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
351
352 return MCDisassembler::Success;
353}
354
355template <typename InsnType>
356static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
357 uint64_t Address,
358 const MCDisassembler *Decoder) {
359 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
360 // (otherwise we would have matched the ADDI instruction from the earlier
361 // ISA's instead).
362 //
363 // We have:
364 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
365 // BOVC if rs >= rt
366 // BEQZALC if rs == 0 && rt != 0
367 // BEQC if rs < rt && rs != 0
368
369 InsnType Rs = fieldFromInstruction(insn, 21, 5);
370 InsnType Rt = fieldFromInstruction(insn, 16, 5);
371 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
372 bool HasRs = false;
373
374 if (Rs >= Rt) {
375 MI.setOpcode(Mips::BOVC);
376 HasRs = true;
377 } else if (Rs != 0 && Rs < Rt) {
378 MI.setOpcode(Mips::BEQC);
379 HasRs = true;
380 } else
381 MI.setOpcode(Mips::BEQZALC);
382
383 if (HasRs)
384 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
385 Rs)));
386
387 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
388 Rt)));
389 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
390
391 return MCDisassembler::Success;
392}
393
394template <typename InsnType>
395static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn,
396 uint64_t Address,
397 const MCDisassembler *Decoder) {
398 InsnType Rt = fieldFromInstruction(insn, 21, 5);
399 InsnType Rs = fieldFromInstruction(insn, 16, 5);
400 int64_t Imm = 0;
401
402 if (Rs >= Rt) {
403 MI.setOpcode(Mips::BOVC_MMR6);
404 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
405 Rt)));
406 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
407 Rs)));
408 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
409 } else if (Rs != 0 && Rs < Rt) {
410 MI.setOpcode(Mips::BEQC_MMR6);
411 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
412 Rs)));
413 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
414 Rt)));
415 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
416 } else {
417 MI.setOpcode(Mips::BEQZALC_MMR6);
418 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
419 Rt)));
420 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
421 }
422
423 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
424
425 return MCDisassembler::Success;
426}
427
428template <typename InsnType>
429static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
430 uint64_t Address,
431 const MCDisassembler *Decoder) {
432 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
433 // (otherwise we would have matched the ADDI instruction from the earlier
434 // ISA's instead).
435 //
436 // We have:
437 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
438 // BNVC if rs >= rt
439 // BNEZALC if rs == 0 && rt != 0
440 // BNEC if rs < rt && rs != 0
441
442 InsnType Rs = fieldFromInstruction(insn, 21, 5);
443 InsnType Rt = fieldFromInstruction(insn, 16, 5);
444 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
445 bool HasRs = false;
446
447 if (Rs >= Rt) {
448 MI.setOpcode(Mips::BNVC);
449 HasRs = true;
450 } else if (Rs != 0 && Rs < Rt) {
451 MI.setOpcode(Mips::BNEC);
452 HasRs = true;
453 } else
454 MI.setOpcode(Mips::BNEZALC);
455
456 if (HasRs)
457 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
458 Rs)));
459
460 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
461 Rt)));
462 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
463
464 return MCDisassembler::Success;
465}
466
467template <typename InsnType>
468static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn,
469 uint64_t Address,
470 const MCDisassembler *Decoder) {
471 InsnType Rt = fieldFromInstruction(insn, 21, 5);
472 InsnType Rs = fieldFromInstruction(insn, 16, 5);
473 int64_t Imm = 0;
474
475 if (Rs >= Rt) {
476 MI.setOpcode(Mips::BNVC_MMR6);
477 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
478 Rt)));
479 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
480 Rs)));
481 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
482 } else if (Rs != 0 && Rs < Rt) {
483 MI.setOpcode(Mips::BNEC_MMR6);
484 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
485 Rs)));
486 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
487 Rt)));
488 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
489 } else {
490 MI.setOpcode(Mips::BNEZALC_MMR6);
491 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
492 Rt)));
493 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
494 }
495
496 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
497
498 return MCDisassembler::Success;
499}
500
501template <typename InsnType>
502static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn,
503 uint64_t Address,
504 const MCDisassembler *Decoder) {
505 // We have:
506 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii
507 // Invalid if rt == 0
508 // BGTZC_MMR6 if rs == 0 && rt != 0
509 // BLTZC_MMR6 if rs == rt && rt != 0
510 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0
511
512 InsnType Rt = fieldFromInstruction(insn, 21, 5);
513 InsnType Rs = fieldFromInstruction(insn, 16, 5);
514 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
515 bool HasRs = false;
516
517 if (Rt == 0)
518 return MCDisassembler::Fail;
519 else if (Rs == 0)
520 MI.setOpcode(Mips::BGTZC_MMR6);
521 else if (Rs == Rt)
522 MI.setOpcode(Mips::BLTZC_MMR6);
523 else {
524 MI.setOpcode(Mips::BLTC_MMR6);
525 HasRs = true;
526 }
527
528 if (HasRs)
529 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
530 Rs)));
531
532 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
533 Rt)));
534
535 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
536
537 return MCDisassembler::Success;
538}
539
540template <typename InsnType>
541static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn,
542 uint64_t Address,
543 const MCDisassembler *Decoder) {
544 // We have:
545 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii
546 // Invalid if rt == 0
547 // BLEZC_MMR6 if rs == 0 && rt != 0
548 // BGEZC_MMR6 if rs == rt && rt != 0
549 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0
550
551 InsnType Rt = fieldFromInstruction(insn, 21, 5);
552 InsnType Rs = fieldFromInstruction(insn, 16, 5);
553 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
554 bool HasRs = false;
555
556 if (Rt == 0)
557 return MCDisassembler::Fail;
558 else if (Rs == 0)
559 MI.setOpcode(Mips::BLEZC_MMR6);
560 else if (Rs == Rt)
561 MI.setOpcode(Mips::BGEZC_MMR6);
562 else {
563 HasRs = true;
564 MI.setOpcode(Mips::BGEC_MMR6);
565 }
566
567 if (HasRs)
568 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
569 Rs)));
570
571 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
572 Rt)));
573
574 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
575
576 return MCDisassembler::Success;
577}
578
579template <typename InsnType>
580static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
581 uint64_t Address,
582 const MCDisassembler *Decoder) {
583 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
584 // (otherwise we would have matched the BLEZL instruction from the earlier
585 // ISA's instead).
586 //
587 // We have:
588 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
589 // Invalid if rs == 0
590 // BLEZC if rs == 0 && rt != 0
591 // BGEZC if rs == rt && rt != 0
592 // BGEC if rs != rt && rs != 0 && rt != 0
593
594 InsnType Rs = fieldFromInstruction(insn, 21, 5);
595 InsnType Rt = fieldFromInstruction(insn, 16, 5);
596 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
597 bool HasRs = false;
598
599 if (Rt == 0)
600 return MCDisassembler::Fail;
601 else if (Rs == 0)
602 MI.setOpcode(Mips::BLEZC);
603 else if (Rs == Rt)
604 MI.setOpcode(Mips::BGEZC);
605 else {
606 HasRs = true;
607 MI.setOpcode(Mips::BGEC);
608 }
609
610 if (HasRs)
611 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
612 Rs)));
613
614 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
615 Rt)));
616
617 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
618
619 return MCDisassembler::Success;
620}
621
622template <typename InsnType>
623static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
624 uint64_t Address,
625 const MCDisassembler *Decoder) {
626 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
627 // (otherwise we would have matched the BGTZL instruction from the earlier
628 // ISA's instead).
629 //
630 // We have:
631 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
632 // Invalid if rs == 0
633 // BGTZC if rs == 0 && rt != 0
634 // BLTZC if rs == rt && rt != 0
635 // BLTC if rs != rt && rs != 0 && rt != 0
636
637 bool HasRs = false;
638
639 InsnType Rs = fieldFromInstruction(insn, 21, 5);
640 InsnType Rt = fieldFromInstruction(insn, 16, 5);
641 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
642
643 if (Rt == 0)
644 return MCDisassembler::Fail;
645 else if (Rs == 0)
646 MI.setOpcode(Mips::BGTZC);
647 else if (Rs == Rt)
648 MI.setOpcode(Mips::BLTZC);
649 else {
650 MI.setOpcode(Mips::BLTC);
651 HasRs = true;
652 }
653
654 if (HasRs)
655 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
656 Rs)));
657
658 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
659 Rt)));
660
661 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
662
663 return MCDisassembler::Success;
664}
665
666template <typename InsnType>
667static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
668 uint64_t Address,
669 const MCDisassembler *Decoder) {
670 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
671 // (otherwise we would have matched the BGTZ instruction from the earlier
672 // ISA's instead).
673 //
674 // We have:
675 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
676 // BGTZ if rt == 0
677 // BGTZALC if rs == 0 && rt != 0
678 // BLTZALC if rs != 0 && rs == rt
679 // BLTUC if rs != 0 && rs != rt
680
681 InsnType Rs = fieldFromInstruction(insn, 21, 5);
682 InsnType Rt = fieldFromInstruction(insn, 16, 5);
683 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
684 bool HasRs = false;
685 bool HasRt = false;
686
687 if (Rt == 0) {
688 MI.setOpcode(Mips::BGTZ);
689 HasRs = true;
690 } else if (Rs == 0) {
691 MI.setOpcode(Mips::BGTZALC);
692 HasRt = true;
693 } else if (Rs == Rt) {
694 MI.setOpcode(Mips::BLTZALC);
695 HasRs = true;
696 } else {
697 MI.setOpcode(Mips::BLTUC);
698 HasRs = true;
699 HasRt = true;
700 }
701
702 if (HasRs)
703 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
704 Rs)));
705
706 if (HasRt)
707 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
708 Rt)));
709
710 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
711
712 return MCDisassembler::Success;
713}
714
715template <typename InsnType>
716static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
717 uint64_t Address,
718 const MCDisassembler *Decoder) {
719 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
720 // (otherwise we would have matched the BLEZL instruction from the earlier
721 // ISA's instead).
722 //
723 // We have:
724 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
725 // Invalid if rs == 0
726 // BLEZALC if rs == 0 && rt != 0
727 // BGEZALC if rs == rt && rt != 0
728 // BGEUC if rs != rt && rs != 0 && rt != 0
729
730 InsnType Rs = fieldFromInstruction(insn, 21, 5);
731 InsnType Rt = fieldFromInstruction(insn, 16, 5);
732 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
733 bool HasRs = false;
734
735 if (Rt == 0)
736 return MCDisassembler::Fail;
737 else if (Rs == 0)
738 MI.setOpcode(Mips::BLEZALC);
739 else if (Rs == Rt)
740 MI.setOpcode(Mips::BGEZALC);
741 else {
742 HasRs = true;
743 MI.setOpcode(Mips::BGEUC);
744 }
745
746 if (HasRs)
747 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
748 Rs)));
749 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
750 Rt)));
751
752 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
753
754 return MCDisassembler::Success;
755}
756
757// Override the generated disassembler to produce DEXT all the time. This is
758// for feature / behaviour parity with binutils.
759template <typename InsnType>
760static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
761 const MCDisassembler *Decoder) {
762 unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
763 unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
764 unsigned Size = 0;
765 unsigned Pos = 0;
766
767 switch (MI.getOpcode()) {
768 case Mips::DEXT:
769 Pos = Lsb;
770 Size = Msbd + 1;
771 break;
772 case Mips::DEXTM:
773 Pos = Lsb;
774 Size = Msbd + 1 + 32;
775 break;
776 case Mips::DEXTU:
777 Pos = Lsb + 32;
778 Size = Msbd + 1;
779 break;
780 default:
781 llvm_unreachable("Unknown DEXT instruction!");
782 }
783
784 MI.setOpcode(Mips::DEXT);
785
786 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
787 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
788
789 MI.addOperand(
790 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR64RegClassID, Rt)));
791 MI.addOperand(
792 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR64RegClassID, Rs)));
793 MI.addOperand(Op: MCOperand::createImm(Val: Pos));
794 MI.addOperand(Op: MCOperand::createImm(Val: Size));
795
796 return MCDisassembler::Success;
797}
798
799// Override the generated disassembler to produce DINS all the time. This is
800// for feature / behaviour parity with binutils.
801template <typename InsnType>
802static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
803 const MCDisassembler *Decoder) {
804 unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
805 unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
806 unsigned Size = 0;
807 unsigned Pos = 0;
808
809 switch (MI.getOpcode()) {
810 case Mips::DINS:
811 Pos = Lsb;
812 Size = Msbd + 1 - Pos;
813 break;
814 case Mips::DINSM:
815 Pos = Lsb;
816 Size = Msbd + 33 - Pos;
817 break;
818 case Mips::DINSU:
819 Pos = Lsb + 32;
820 // mbsd = pos + size - 33
821 // mbsd - pos + 33 = size
822 Size = Msbd + 33 - Pos;
823 break;
824 default:
825 llvm_unreachable("Unknown DINS instruction!");
826 }
827
828 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
829 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
830
831 MI.setOpcode(Mips::DINS);
832 MI.addOperand(
833 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR64RegClassID, Rt)));
834 MI.addOperand(
835 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR64RegClassID, Rs)));
836 MI.addOperand(Op: MCOperand::createImm(Val: Pos));
837 MI.addOperand(Op: MCOperand::createImm(Val: Size));
838
839 return MCDisassembler::Success;
840}
841
842// Auto-generated decoder wouldn't add the third operand for CRC32*.
843template <typename InsnType>
844static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
845 const MCDisassembler *Decoder) {
846 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
847 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
848 MI.addOperand(
849 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID, Rt)));
850 MI.addOperand(
851 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID, Rs)));
852 MI.addOperand(
853 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID, Rt)));
854 return MCDisassembler::Success;
855}
856
857static DecodeStatus
858DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
859 const MCDisassembler *Decoder) {
860 return MCDisassembler::Fail;
861}
862
863static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
864 uint64_t Address,
865 const MCDisassembler *Decoder) {
866 if (RegNo > 31)
867 return MCDisassembler::Fail;
868
869 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPR64RegClassID, RegNo);
870 Inst.addOperand(Op: MCOperand::createReg(Reg));
871 return MCDisassembler::Success;
872}
873
874static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo,
875 uint64_t Address,
876 const MCDisassembler *Decoder) {
877 if (RegNo > 7)
878 return MCDisassembler::Fail;
879 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPRMM16RegClassID, RegNo);
880 Inst.addOperand(Op: MCOperand::createReg(Reg));
881 return MCDisassembler::Success;
882}
883
884static DecodeStatus
885DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
886 const MCDisassembler *Decoder) {
887 if (RegNo > 7)
888 return MCDisassembler::Fail;
889 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPRMM16ZeroRegClassID, RegNo);
890 Inst.addOperand(Op: MCOperand::createReg(Reg));
891 return MCDisassembler::Success;
892}
893
894static DecodeStatus
895DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
896 const MCDisassembler *Decoder) {
897 if (RegNo > 7)
898 return MCDisassembler::Fail;
899 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPRMM16MovePRegClassID, RegNo);
900 Inst.addOperand(Op: MCOperand::createReg(Reg));
901 return MCDisassembler::Success;
902}
903
904// Tablegen emits references to these unimplemented functions due to usage of
905// RegClassByHwMode - it does not detect that the RegClassByHwMode decoders are
906// unused, which in turn use these register class decoders.
907static DecodeStatus DecodeGP32RegisterClass(MCInst &Inst, unsigned RegNo,
908 uint64_t Address,
909 const MCDisassembler *Decoder) {
910 llvm_unreachable("this is unused");
911}
912
913static DecodeStatus DecodeGP64RegisterClass(MCInst &Inst, unsigned RegNo,
914 uint64_t Address,
915 const MCDisassembler *Decoder) {
916 llvm_unreachable("this is unused");
917}
918
919static DecodeStatus DecodeSP32RegisterClass(MCInst &Inst, unsigned RegNo,
920 uint64_t Address,
921 const MCDisassembler *Decoder) {
922 llvm_unreachable("this is unused");
923}
924
925static DecodeStatus DecodeSP64RegisterClass(MCInst &Inst, unsigned RegNo,
926 uint64_t Address,
927 const MCDisassembler *Decoder) {
928 llvm_unreachable("this is unused");
929}
930
931static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
932 uint64_t Address,
933 const MCDisassembler *Decoder) {
934 if (RegNo > 31)
935 return MCDisassembler::Fail;
936 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo);
937 Inst.addOperand(Op: MCOperand::createReg(Reg));
938 return MCDisassembler::Success;
939}
940
941static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo,
942 uint64_t Address,
943 const MCDisassembler *Decoder) {
944 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
945 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
946
947 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
948}
949
950static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo,
951 uint64_t Address,
952 const MCDisassembler *Decoder) {
953 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
954}
955
956static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
957 uint64_t Address,
958 const MCDisassembler *Decoder) {
959 if (RegNo > 31)
960 return MCDisassembler::Fail;
961
962 MCRegister Reg = getReg(D: Decoder, RC: Mips::FGR64RegClassID, RegNo);
963 Inst.addOperand(Op: MCOperand::createReg(Reg));
964 return MCDisassembler::Success;
965}
966
967static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo,
968 uint64_t Address,
969 const MCDisassembler *Decoder) {
970 if (RegNo > 31)
971 return MCDisassembler::Fail;
972
973 MCRegister Reg = getReg(D: Decoder, RC: Mips::FGR32RegClassID, RegNo);
974 Inst.addOperand(Op: MCOperand::createReg(Reg));
975 return MCDisassembler::Success;
976}
977
978static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo,
979 uint64_t Address,
980 const MCDisassembler *Decoder) {
981 if (RegNo > 31)
982 return MCDisassembler::Fail;
983 MCRegister Reg = getReg(D: Decoder, RC: Mips::CCRRegClassID, RegNo);
984 Inst.addOperand(Op: MCOperand::createReg(Reg));
985 return MCDisassembler::Success;
986}
987
988static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo,
989 uint64_t Address,
990 const MCDisassembler *Decoder) {
991 if (RegNo > 7)
992 return MCDisassembler::Fail;
993 MCRegister Reg = getReg(D: Decoder, RC: Mips::FCCRegClassID, RegNo);
994 Inst.addOperand(Op: MCOperand::createReg(Reg));
995 return MCDisassembler::Success;
996}
997
998static DecodeStatus DecodeFGR32CCRegisterClass(MCInst &Inst, unsigned RegNo,
999 uint64_t Address,
1000 const MCDisassembler *Decoder) {
1001 if (RegNo > 31)
1002 return MCDisassembler::Fail;
1003
1004 MCRegister Reg = getReg(D: Decoder, RC: Mips::FGR32CCRegClassID, RegNo);
1005 Inst.addOperand(Op: MCOperand::createReg(Reg));
1006 return MCDisassembler::Success;
1007}
1008
1009static DecodeStatus DecodeFGR64CCRegisterClass(MCInst &Inst, unsigned RegNo,
1010 uint64_t Address,
1011 const MCDisassembler *Decoder) {
1012 if (RegNo > 31)
1013 return MCDisassembler::Fail;
1014
1015 MCRegister Reg = getReg(D: Decoder, RC: Mips::FGR64CCRegClassID, RegNo);
1016 Inst.addOperand(Op: MCOperand::createReg(Reg));
1017 return MCDisassembler::Success;
1018}
1019
1020static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address,
1021 const MCDisassembler *Decoder) {
1022 int Offset = SignExtend32<16>(X: Insn & 0xffff);
1023 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1024 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1025
1026 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo);
1027 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1028
1029 if (Inst.getOpcode() == Mips::SC || Inst.getOpcode() == Mips::SC64 ||
1030 Inst.getOpcode() == Mips::SCD)
1031 Inst.addOperand(Op: MCOperand::createReg(Reg));
1032
1033 Inst.addOperand(Op: MCOperand::createReg(Reg));
1034 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1035 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1036
1037 return MCDisassembler::Success;
1038}
1039
1040static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address,
1041 const MCDisassembler *Decoder) {
1042 int Offset = SignExtend32<9>(X: Insn >> 7);
1043 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1044 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1045
1046 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo);
1047 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1048
1049 if (Inst.getOpcode() == Mips::SCE)
1050 Inst.addOperand(Op: MCOperand::createReg(Reg));
1051
1052 Inst.addOperand(Op: MCOperand::createReg(Reg));
1053 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1054 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1055
1056 return MCDisassembler::Success;
1057}
1058
1059static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn,
1060 uint64_t Address,
1061 const MCDisassembler *Decoder) {
1062 int Offset = SignExtend32<16>(X: Insn & 0xffff);
1063 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1064 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1065
1066 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1067 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo);
1068
1069 Inst.addOperand(Op: MCOperand::createReg(Reg));
1070 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1071 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1072
1073 return MCDisassembler::Success;
1074}
1075
1076static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
1077 const MCDisassembler *Decoder) {
1078 int Offset = SignExtend32<16>(X: Insn & 0xffff);
1079 unsigned Hint = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1080 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1081
1082 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1083
1084 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1085 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1086 Inst.addOperand(Op: MCOperand::createImm(Val: Hint));
1087
1088 return MCDisassembler::Success;
1089}
1090
1091static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn,
1092 uint64_t Address,
1093 const MCDisassembler *Decoder) {
1094 int Offset = SignExtend32<12>(X: Insn & 0xfff);
1095 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1096 unsigned Hint = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1097
1098 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1099
1100 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1101 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1102 Inst.addOperand(Op: MCOperand::createImm(Val: Hint));
1103
1104 return MCDisassembler::Success;
1105}
1106
1107static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn,
1108 uint64_t Address,
1109 const MCDisassembler *Decoder) {
1110 int Offset = SignExtend32<9>(X: Insn & 0x1ff);
1111 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1112 unsigned Hint = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1113
1114 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1115
1116 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1117 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1118 Inst.addOperand(Op: MCOperand::createImm(Val: Hint));
1119
1120 return MCDisassembler::Success;
1121}
1122
1123static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn,
1124 uint64_t Address,
1125 const MCDisassembler *Decoder) {
1126 int Offset = SignExtend32<9>(X: Insn >> 7);
1127 unsigned Hint = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1128 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1129
1130 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1131
1132 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1133 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1134 Inst.addOperand(Op: MCOperand::createImm(Val: Hint));
1135
1136 return MCDisassembler::Success;
1137}
1138
1139static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address,
1140 const MCDisassembler *Decoder) {
1141 int Offset = SignExtend32<16>(X: Insn & 0xffff);
1142 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1143
1144 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1145
1146 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1147 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1148
1149 return MCDisassembler::Success;
1150}
1151
1152static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn,
1153 uint64_t Address,
1154 const MCDisassembler *Decoder) {
1155 int Offset = SignExtend32<16>(X: Insn & 0xffff);
1156 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1157
1158 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1159
1160 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1161 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1162
1163 return MCDisassembler::Success;
1164}
1165
1166static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address,
1167 const MCDisassembler *Decoder) {
1168 int Immediate = SignExtend32<16>(X: Insn & 0xffff);
1169 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1170
1171 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1172
1173 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1174 Inst.addOperand(Op: MCOperand::createImm(Val: Immediate));
1175
1176 return MCDisassembler::Success;
1177}
1178
1179static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1180 uint64_t Address,
1181 const MCDisassembler *Decoder) {
1182 int Offset = SignExtend32<10>(X: fieldFromInstruction(Insn, StartBit: 16, NumBits: 10));
1183 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 6, NumBits: 5);
1184 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 11, NumBits: 5);
1185
1186 MCRegister Reg = getReg(D: Decoder, RC: Mips::MSA128BRegClassID, RegNo);
1187 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1188
1189 Inst.addOperand(Op: MCOperand::createReg(Reg));
1190 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1191
1192 // The immediate field of an LD/ST instruction is scaled which means it must
1193 // be multiplied (when decoding) by the size (in bytes) of the instructions'
1194 // data format.
1195 // .b - 1 byte
1196 // .h - 2 bytes
1197 // .w - 4 bytes
1198 // .d - 8 bytes
1199 switch(Inst.getOpcode())
1200 {
1201 default:
1202 assert(false && "Unexpected instruction");
1203 return MCDisassembler::Fail;
1204 break;
1205 case Mips::LD_B:
1206 case Mips::ST_B:
1207 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1208 break;
1209 case Mips::LD_H:
1210 case Mips::ST_H:
1211 Inst.addOperand(Op: MCOperand::createImm(Val: Offset * 2));
1212 break;
1213 case Mips::LD_W:
1214 case Mips::ST_W:
1215 Inst.addOperand(Op: MCOperand::createImm(Val: Offset * 4));
1216 break;
1217 case Mips::LD_D:
1218 case Mips::ST_D:
1219 Inst.addOperand(Op: MCOperand::createImm(Val: Offset * 8));
1220 break;
1221 }
1222
1223 return MCDisassembler::Success;
1224}
1225
1226static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn,
1227 uint64_t Address,
1228 const MCDisassembler *Decoder) {
1229 unsigned Offset = Insn & 0xf;
1230 unsigned Reg = fieldFromInstruction(Insn, StartBit: 7, NumBits: 3);
1231 unsigned Base = fieldFromInstruction(Insn, StartBit: 4, NumBits: 3);
1232
1233 switch (Inst.getOpcode()) {
1234 case Mips::LBU16_MM:
1235 case Mips::LHU16_MM:
1236 case Mips::LW16_MM:
1237 if (DecodeGPRMM16RegisterClass(Inst, RegNo: Reg, Address, Decoder)
1238 == MCDisassembler::Fail)
1239 return MCDisassembler::Fail;
1240 break;
1241 case Mips::SB16_MM:
1242 case Mips::SB16_MMR6:
1243 case Mips::SH16_MM:
1244 case Mips::SH16_MMR6:
1245 case Mips::SW16_MM:
1246 case Mips::SW16_MMR6:
1247 if (DecodeGPRMM16ZeroRegisterClass(Inst, RegNo: Reg, Address, Decoder)
1248 == MCDisassembler::Fail)
1249 return MCDisassembler::Fail;
1250 break;
1251 }
1252
1253 if (DecodeGPRMM16RegisterClass(Inst, RegNo: Base, Address, Decoder)
1254 == MCDisassembler::Fail)
1255 return MCDisassembler::Fail;
1256
1257 switch (Inst.getOpcode()) {
1258 case Mips::LBU16_MM:
1259 if (Offset == 0xf)
1260 Inst.addOperand(Op: MCOperand::createImm(Val: -1));
1261 else
1262 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1263 break;
1264 case Mips::SB16_MM:
1265 case Mips::SB16_MMR6:
1266 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1267 break;
1268 case Mips::LHU16_MM:
1269 case Mips::SH16_MM:
1270 case Mips::SH16_MMR6:
1271 Inst.addOperand(Op: MCOperand::createImm(Val: Offset << 1));
1272 break;
1273 case Mips::LW16_MM:
1274 case Mips::SW16_MM:
1275 case Mips::SW16_MMR6:
1276 Inst.addOperand(Op: MCOperand::createImm(Val: Offset << 2));
1277 break;
1278 }
1279
1280 return MCDisassembler::Success;
1281}
1282
1283static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn,
1284 uint64_t Address,
1285 const MCDisassembler *Decoder) {
1286 unsigned Offset = Insn & 0x1F;
1287 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 5, NumBits: 5);
1288
1289 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo);
1290
1291 Inst.addOperand(Op: MCOperand::createReg(Reg));
1292 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::SP));
1293 Inst.addOperand(Op: MCOperand::createImm(Val: Offset << 2));
1294
1295 return MCDisassembler::Success;
1296}
1297
1298static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn,
1299 uint64_t Address,
1300 const MCDisassembler *Decoder) {
1301 unsigned Offset = Insn & 0x7F;
1302 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 7, NumBits: 3);
1303
1304 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo);
1305
1306 Inst.addOperand(Op: MCOperand::createReg(Reg));
1307 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::GP));
1308 Inst.addOperand(Op: MCOperand::createImm(Val: Offset << 2));
1309
1310 return MCDisassembler::Success;
1311}
1312
1313static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn,
1314 uint64_t Address,
1315 const MCDisassembler *Decoder) {
1316 int Offset;
1317 switch (Inst.getOpcode()) {
1318 case Mips::LWM16_MMR6:
1319 case Mips::SWM16_MMR6:
1320 Offset = fieldFromInstruction(Insn, StartBit: 4, NumBits: 4);
1321 break;
1322 default:
1323 Offset = SignExtend32<4>(X: Insn & 0xf);
1324 break;
1325 }
1326
1327 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1328 == MCDisassembler::Fail)
1329 return MCDisassembler::Fail;
1330
1331 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::SP));
1332 Inst.addOperand(Op: MCOperand::createImm(Val: Offset << 2));
1333
1334 return MCDisassembler::Success;
1335}
1336
1337static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn,
1338 uint64_t Address,
1339 const MCDisassembler *Decoder) {
1340 int Offset = SignExtend32<9>(X: Insn & 0x1ff);
1341 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1342 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1343
1344 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo);
1345 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1346
1347 if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6)
1348 Inst.addOperand(Op: MCOperand::createReg(Reg));
1349
1350 Inst.addOperand(Op: MCOperand::createReg(Reg));
1351 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1352 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1353
1354 return MCDisassembler::Success;
1355}
1356
1357static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn,
1358 uint64_t Address,
1359 const MCDisassembler *Decoder) {
1360 int Offset = SignExtend32<12>(X: Insn & 0x0fff);
1361 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1362 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1363
1364 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo);
1365 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1366
1367 switch (Inst.getOpcode()) {
1368 case Mips::SWM32_MM:
1369 case Mips::LWM32_MM:
1370 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1371 == MCDisassembler::Fail)
1372 return MCDisassembler::Fail;
1373 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1374 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1375 break;
1376 case Mips::SC_MM:
1377 Inst.addOperand(Op: MCOperand::createReg(Reg));
1378 [[fallthrough]];
1379 default:
1380 Inst.addOperand(Op: MCOperand::createReg(Reg));
1381 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1382 Inst.addOperand(Op: MCOperand::createReg(Reg: Reg+1));
1383
1384 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1385 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1386 }
1387
1388 return MCDisassembler::Success;
1389}
1390
1391static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn,
1392 uint64_t Address,
1393 const MCDisassembler *Decoder) {
1394 int Offset = SignExtend32<16>(X: Insn & 0xffff);
1395 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1396 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1397
1398 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo);
1399 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1400
1401 Inst.addOperand(Op: MCOperand::createReg(Reg));
1402 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1403 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1404
1405 return MCDisassembler::Success;
1406}
1407
1408static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address,
1409 const MCDisassembler *Decoder) {
1410 int Offset = SignExtend32<16>(X: Insn & 0xffff);
1411 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1412 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1413
1414 MCRegister Reg = getReg(D: Decoder, RC: Mips::FGR64RegClassID, RegNo);
1415 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1416
1417 Inst.addOperand(Op: MCOperand::createReg(Reg));
1418 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1419 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1420
1421 return MCDisassembler::Success;
1422}
1423
1424static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
1425 uint64_t Address,
1426 const MCDisassembler *Decoder) {
1427 // This function is the same as DecodeFMem but with the Reg and Base fields
1428 // swapped according to microMIPS spec.
1429 int Offset = SignExtend32<16>(X: Insn & 0xffff);
1430 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1431 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1432
1433 MCRegister Reg = getReg(D: Decoder, RC: Mips::FGR64RegClassID, RegNo);
1434 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1435
1436 Inst.addOperand(Op: MCOperand::createReg(Reg));
1437 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1438 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1439
1440 return MCDisassembler::Success;
1441}
1442
1443static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,
1444 const MCDisassembler *Decoder) {
1445 int Offset = SignExtend32<16>(X: Insn & 0xffff);
1446 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1447 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1448
1449 MCRegister Reg = getReg(D: Decoder, RC: Mips::COP2RegClassID, RegNo);
1450 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1451
1452 Inst.addOperand(Op: MCOperand::createReg(Reg));
1453 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1454 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1455
1456 return MCDisassembler::Success;
1457}
1458
1459static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,
1460 const MCDisassembler *Decoder) {
1461 int Offset = SignExtend32<16>(X: Insn & 0xffff);
1462 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1463 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1464
1465 MCRegister Reg = getReg(D: Decoder, RC: Mips::COP3RegClassID, RegNo);
1466 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1467
1468 Inst.addOperand(Op: MCOperand::createReg(Reg));
1469 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1470 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1471
1472 return MCDisassembler::Success;
1473}
1474
1475static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
1476 uint64_t Address,
1477 const MCDisassembler *Decoder) {
1478 int Offset = SignExtend32<11>(X: Insn & 0x07ff);
1479 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1480 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 11, NumBits: 5);
1481
1482 MCRegister Reg = getReg(D: Decoder, RC: Mips::COP2RegClassID, RegNo);
1483 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1484
1485 Inst.addOperand(Op: MCOperand::createReg(Reg));
1486 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1487 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1488
1489 return MCDisassembler::Success;
1490}
1491
1492static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
1493 uint64_t Address,
1494 const MCDisassembler *Decoder) {
1495 int Offset = SignExtend32<11>(X: Insn & 0x07ff);
1496 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1497 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1498
1499 MCRegister Reg = getReg(D: Decoder, RC: Mips::COP2RegClassID, RegNo);
1500 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1501
1502 Inst.addOperand(Op: MCOperand::createReg(Reg));
1503 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1504 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1505
1506 return MCDisassembler::Success;
1507}
1508
1509static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn,
1510 uint64_t Address,
1511 const MCDisassembler *Decoder) {
1512 int64_t Offset = SignExtend64<9>(x: (Insn >> 7) & 0x1ff);
1513 unsigned RtNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1514 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1515
1516 MCRegister Rt = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: RtNo);
1517 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1518
1519 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1520 Inst.addOperand(Op: MCOperand::createReg(Reg: Rt));
1521 }
1522
1523 Inst.addOperand(Op: MCOperand::createReg(Reg: Rt));
1524 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1525 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1526
1527 return MCDisassembler::Success;
1528}
1529
1530static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset,
1531 uint64_t Address,
1532 const MCDisassembler *Decoder) {
1533 int32_t BranchOffset = (SignExtend32<16>(X: Offset) * 4) + 4;
1534 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1535 return MCDisassembler::Success;
1536}
1537
1538static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset,
1539 uint64_t Address,
1540 const MCDisassembler *Decoder) {
1541 int32_t BranchOffset = (SignExtend32<16>(X: Offset) * 2);
1542 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1543 return MCDisassembler::Success;
1544}
1545
1546static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn,
1547 uint64_t Address,
1548 const MCDisassembler *Decoder) {
1549 unsigned JumpOffset = fieldFromInstruction(Insn, StartBit: 0, NumBits: 26) << 2;
1550 Inst.addOperand(Op: MCOperand::createImm(Val: JumpOffset));
1551 return MCDisassembler::Success;
1552}
1553
1554static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset,
1555 uint64_t Address,
1556 const MCDisassembler *Decoder) {
1557 int32_t BranchOffset = SignExtend32<21>(X: Offset) * 4 + 4;
1558
1559 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1560 return MCDisassembler::Success;
1561}
1562
1563static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset,
1564 uint64_t Address,
1565 const MCDisassembler *Decoder) {
1566 int32_t BranchOffset = SignExtend32<21>(X: Offset) * 4 + 4;
1567
1568 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1569 return MCDisassembler::Success;
1570}
1571
1572static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset,
1573 uint64_t Address,
1574 const MCDisassembler *Decoder) {
1575 int32_t BranchOffset = SignExtend32<26>(X: Offset) * 4 + 4;
1576
1577 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1578 return MCDisassembler::Success;
1579}
1580
1581static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset,
1582 uint64_t Address,
1583 const MCDisassembler *Decoder) {
1584 int32_t BranchOffset = SignExtend32<8>(X: Offset << 1);
1585 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1586 return MCDisassembler::Success;
1587}
1588
1589static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset,
1590 uint64_t Address,
1591 const MCDisassembler *Decoder) {
1592 int32_t BranchOffset = SignExtend32<11>(X: Offset << 1);
1593 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1594 return MCDisassembler::Success;
1595}
1596
1597static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset,
1598 uint64_t Address,
1599 const MCDisassembler *Decoder) {
1600 int32_t BranchOffset = SignExtend32<16>(X: Offset) * 2 + 4;
1601 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1602 return MCDisassembler::Success;
1603}
1604
1605static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset,
1606 uint64_t Address,
1607 const MCDisassembler *Decoder) {
1608 int32_t BranchOffset = SignExtend32<27>(X: Offset << 1);
1609
1610 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1611 return MCDisassembler::Success;
1612}
1613
1614static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn,
1615 uint64_t Address,
1616 const MCDisassembler *Decoder) {
1617 unsigned JumpOffset = fieldFromInstruction(Insn, StartBit: 0, NumBits: 26) << 1;
1618 Inst.addOperand(Op: MCOperand::createImm(Val: JumpOffset));
1619 return MCDisassembler::Success;
1620}
1621
1622static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn,
1623 uint64_t Address,
1624 const MCDisassembler *Decoder) {
1625 unsigned JumpOffset = fieldFromInstruction(Insn, StartBit: 0, NumBits: 26) << 2;
1626 Inst.addOperand(Op: MCOperand::createImm(Val: JumpOffset));
1627 return MCDisassembler::Success;
1628}
1629
1630static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value,
1631 uint64_t Address,
1632 const MCDisassembler *Decoder) {
1633 if (Value == 0)
1634 Inst.addOperand(Op: MCOperand::createImm(Val: 1));
1635 else if (Value == 0x7)
1636 Inst.addOperand(Op: MCOperand::createImm(Val: -1));
1637 else
1638 Inst.addOperand(Op: MCOperand::createImm(Val: Value << 2));
1639 return MCDisassembler::Success;
1640}
1641
1642static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value,
1643 uint64_t Address,
1644 const MCDisassembler *Decoder) {
1645 if (Value == 0x7F)
1646 Inst.addOperand(Op: MCOperand::createImm(Val: -1));
1647 else
1648 Inst.addOperand(Op: MCOperand::createImm(Val: Value));
1649 return MCDisassembler::Success;
1650}
1651
1652static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value,
1653 uint64_t Address,
1654 const MCDisassembler *Decoder) {
1655 Inst.addOperand(Op: MCOperand::createImm(Val: Value == 0x0 ? 8 : Value));
1656 return MCDisassembler::Success;
1657}
1658
1659template <unsigned Bits, int Offset, int Scale>
1660static DecodeStatus
1661DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address,
1662 const MCDisassembler *Decoder) {
1663 Value &= ((1 << Bits) - 1);
1664 Value *= Scale;
1665 Inst.addOperand(Op: MCOperand::createImm(Val: Value + Offset));
1666 return MCDisassembler::Success;
1667}
1668
1669template <unsigned Bits, int Offset = 0, int ScaleBy = 1>
1670static DecodeStatus
1671DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address,
1672 const MCDisassembler *Decoder) {
1673 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy;
1674 Inst.addOperand(Op: MCOperand::createImm(Val: Imm + Offset));
1675 return MCDisassembler::Success;
1676}
1677
1678template <unsigned Bits, int Offset>
1679static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
1680 uint64_t Address,
1681 const MCDisassembler *Decoder) {
1682 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address,
1683 Decoder);
1684}
1685
1686static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address,
1687 const MCDisassembler *Decoder) {
1688 // First we need to grab the pos(lsb) from MCInst.
1689 // This function only handles the 32 bit variants of ins, as dins
1690 // variants are handled differently.
1691 int Pos = Inst.getOperand(i: 2).getImm();
1692 int Size = (int) Insn - Pos + 1;
1693 Inst.addOperand(Op: MCOperand::createImm(Val: SignExtend32<16>(X: Size)));
1694 return MCDisassembler::Success;
1695}
1696
1697static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1698 uint64_t Address,
1699 const MCDisassembler *Decoder) {
1700 Inst.addOperand(Op: MCOperand::createImm(Val: SignExtend32<19>(X: Insn) * 4));
1701 return MCDisassembler::Success;
1702}
1703
1704static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1705 uint64_t Address,
1706 const MCDisassembler *Decoder) {
1707 Inst.addOperand(Op: MCOperand::createImm(Val: SignExtend32<18>(X: Insn) * 8));
1708 return MCDisassembler::Success;
1709}
1710
1711static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address,
1712 const MCDisassembler *Decoder) {
1713 int32_t DecodedValue;
1714 switch (Insn) {
1715 case 0: DecodedValue = 256; break;
1716 case 1: DecodedValue = 257; break;
1717 case 510: DecodedValue = -258; break;
1718 case 511: DecodedValue = -257; break;
1719 default: DecodedValue = SignExtend32<9>(X: Insn); break;
1720 }
1721 Inst.addOperand(Op: MCOperand::createImm(Val: DecodedValue * 4));
1722 return MCDisassembler::Success;
1723}
1724
1725static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1726 uint64_t Address,
1727 const MCDisassembler *Decoder) {
1728 // Insn must be >= 0, since it is unsigned that condition is always true.
1729 assert(Insn < 16);
1730 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15,
1731 16, 31, 32, 63, 64, 255, 32768, 65535};
1732 Inst.addOperand(Op: MCOperand::createImm(Val: DecodedValues[Insn]));
1733 return MCDisassembler::Success;
1734}
1735
1736static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
1737 uint64_t Address,
1738 const MCDisassembler *Decoder) {
1739 switch (RegPair) {
1740 default:
1741 return MCDisassembler::Fail;
1742 case 0:
1743 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A1));
1744 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A2));
1745 break;
1746 case 1:
1747 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A1));
1748 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A3));
1749 break;
1750 case 2:
1751 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A2));
1752 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A3));
1753 break;
1754 case 3:
1755 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A0));
1756 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::S5));
1757 break;
1758 case 4:
1759 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A0));
1760 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::S6));
1761 break;
1762 case 5:
1763 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A0));
1764 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A1));
1765 break;
1766 case 6:
1767 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A0));
1768 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A2));
1769 break;
1770 case 7:
1771 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A0));
1772 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A3));
1773 break;
1774 }
1775
1776 return MCDisassembler::Success;
1777}
1778
1779static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
1780 uint64_t Address,
1781 const MCDisassembler *Decoder) {
1782 unsigned RegPair = fieldFromInstruction(Insn, StartBit: 7, NumBits: 3);
1783 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) ==
1784 MCDisassembler::Fail)
1785 return MCDisassembler::Fail;
1786
1787 unsigned RegRs;
1788 if (static_cast<const MipsDisassembler *>(Decoder)->hasMips32r6())
1789 RegRs = fieldFromInstruction(Insn, StartBit: 0, NumBits: 2) |
1790 (fieldFromInstruction(Insn, StartBit: 3, NumBits: 1) << 2);
1791 else
1792 RegRs = fieldFromInstruction(Insn, StartBit: 1, NumBits: 3);
1793 if (DecodeGPRMM16MovePRegisterClass(Inst, RegNo: RegRs, Address, Decoder) ==
1794 MCDisassembler::Fail)
1795 return MCDisassembler::Fail;
1796
1797 unsigned RegRt = fieldFromInstruction(Insn, StartBit: 4, NumBits: 3);
1798 if (DecodeGPRMM16MovePRegisterClass(Inst, RegNo: RegRt, Address, Decoder) ==
1799 MCDisassembler::Fail)
1800 return MCDisassembler::Fail;
1801
1802 return MCDisassembler::Success;
1803}
1804
1805static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
1806 uint64_t Address,
1807 const MCDisassembler *Decoder) {
1808 Inst.addOperand(Op: MCOperand::createImm(Val: SignExtend32<25>(X: Insn << 2)));
1809 return MCDisassembler::Success;
1810}
1811
1812template <typename InsnType>
1813static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn,
1814 uint64_t Address,
1815 const MCDisassembler *Decoder) {
1816 // We have:
1817 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii
1818 // Invalid if rt == 0
1819 // BGTZALC_MMR6 if rs == 0 && rt != 0
1820 // BLTZALC_MMR6 if rs != 0 && rs == rt
1821 // BLTUC_MMR6 if rs != 0 && rs != rt
1822
1823 InsnType Rt = fieldFromInstruction(insn, 21, 5);
1824 InsnType Rs = fieldFromInstruction(insn, 16, 5);
1825 InsnType Imm = 0;
1826 bool HasRs = false;
1827 bool HasRt = false;
1828
1829 if (Rt == 0)
1830 return MCDisassembler::Fail;
1831 else if (Rs == 0) {
1832 MI.setOpcode(Mips::BGTZALC_MMR6);
1833 HasRt = true;
1834 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1835 }
1836 else if (Rs == Rt) {
1837 MI.setOpcode(Mips::BLTZALC_MMR6);
1838 HasRs = true;
1839 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1840 }
1841 else {
1842 MI.setOpcode(Mips::BLTUC_MMR6);
1843 HasRs = true;
1844 HasRt = true;
1845 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
1846 }
1847
1848 if (HasRs)
1849 MI.addOperand(
1850 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID, Rs)));
1851
1852 if (HasRt)
1853 MI.addOperand(
1854 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID, Rt)));
1855
1856 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
1857
1858 return MCDisassembler::Success;
1859}
1860
1861template <typename InsnType>
1862static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn,
1863 uint64_t Address,
1864 const MCDisassembler *Decoder) {
1865 // We have:
1866 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii
1867 // Invalid if rt == 0
1868 // BLEZALC_MMR6 if rs == 0 && rt != 0
1869 // BGEZALC_MMR6 if rs == rt && rt != 0
1870 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0
1871
1872 InsnType Rt = fieldFromInstruction(insn, 21, 5);
1873 InsnType Rs = fieldFromInstruction(insn, 16, 5);
1874 InsnType Imm = 0;
1875 bool HasRs = false;
1876
1877 if (Rt == 0)
1878 return MCDisassembler::Fail;
1879 else if (Rs == 0) {
1880 MI.setOpcode(Mips::BLEZALC_MMR6);
1881 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1882 }
1883 else if (Rs == Rt) {
1884 MI.setOpcode(Mips::BGEZALC_MMR6);
1885 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1886 }
1887 else {
1888 HasRs = true;
1889 MI.setOpcode(Mips::BGEUC_MMR6);
1890 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
1891 }
1892
1893 if (HasRs)
1894 MI.addOperand(
1895 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID, Rs)));
1896 MI.addOperand(
1897 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID, Rt)));
1898
1899 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
1900
1901 return MCDisassembler::Success;
1902}
1903
1904// This instruction does not have a working decoder, and needs to be
1905// fixed. This "fixme" function was introduced to keep the backend compiling,
1906// while making changes to tablegen code.
1907static DecodeStatus DecodeFIXMEInstruction(MCInst &Inst, unsigned Insn,
1908 uint64_t Address,
1909 const MCDisassembler *Decoder) {
1910 return MCDisassembler::Fail;
1911}
1912
1913#include "MipsGenDisassemblerTables.inc"
1914
1915/// Read two bytes from the ArrayRef and return 16 bit halfword sorted
1916/// according to the given endianness.
1917static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
1918 uint64_t &Size, uint32_t &Insn,
1919 bool IsBigEndian) {
1920 // We want to read exactly 2 Bytes of data.
1921 if (Bytes.size() < 2) {
1922 Size = 0;
1923 return MCDisassembler::Fail;
1924 }
1925
1926 if (IsBigEndian) {
1927 Insn = (Bytes[0] << 8) | Bytes[1];
1928 } else {
1929 Insn = (Bytes[1] << 8) | Bytes[0];
1930 }
1931
1932 return MCDisassembler::Success;
1933}
1934
1935/// Read four bytes from the ArrayRef and return 32 bit word sorted
1936/// according to the given endianness.
1937static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
1938 uint64_t &Size, uint32_t &Insn,
1939 bool IsBigEndian, bool IsMicroMips) {
1940 // We want to read exactly 4 Bytes of data.
1941 if (Bytes.size() < 4) {
1942 Size = 0;
1943 return MCDisassembler::Fail;
1944 }
1945
1946 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
1947 // always precede the low 16 bits in the instruction stream (that is, they
1948 // are placed at lower addresses in the instruction stream).
1949 //
1950 // microMIPS byte ordering:
1951 // Big-endian: 0 | 1 | 2 | 3
1952 // Little-endian: 1 | 0 | 3 | 2
1953
1954 if (IsBigEndian) {
1955 // Encoded as a big-endian 32-bit word in the stream.
1956 Insn =
1957 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
1958 } else {
1959 if (IsMicroMips) {
1960 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
1961 (Bytes[1] << 24);
1962 } else {
1963 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
1964 (Bytes[3] << 24);
1965 }
1966 }
1967
1968 return MCDisassembler::Success;
1969}
1970
1971DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
1972 ArrayRef<uint8_t> Bytes,
1973 uint64_t Address,
1974 raw_ostream &CStream) const {
1975 uint32_t Insn;
1976 DecodeStatus Result;
1977 Size = 0;
1978
1979 if (IsMicroMips) {
1980 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
1981 if (Result == MCDisassembler::Fail)
1982 return MCDisassembler::Fail;
1983
1984 if (hasMips32r6()) {
1985 LLVM_DEBUG(
1986 dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
1987 // Calling the auto-generated decoder function for microMIPS32R6
1988 // 16-bit instructions.
1989 Result = decodeInstruction(DecodeTable: DecoderTableMicroMipsR616, MI&: Instr, insn: Insn,
1990 Address, DisAsm: this, STI);
1991 if (Result != MCDisassembler::Fail) {
1992 Size = 2;
1993 return Result;
1994 }
1995 }
1996
1997 LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
1998 // Calling the auto-generated decoder function for microMIPS 16-bit
1999 // instructions.
2000 Result = decodeInstruction(DecodeTable: DecoderTableMicroMips16, MI&: Instr, insn: Insn, Address,
2001 DisAsm: this, STI);
2002 if (Result != MCDisassembler::Fail) {
2003 Size = 2;
2004 return Result;
2005 }
2006
2007 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, IsMicroMips: true);
2008 if (Result == MCDisassembler::Fail)
2009 return MCDisassembler::Fail;
2010
2011 if (hasMips32r6()) {
2012 LLVM_DEBUG(
2013 dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
2014 // Calling the auto-generated decoder function.
2015 Result = decodeInstruction(DecodeTable: DecoderTableMicroMipsR632, MI&: Instr, insn: Insn,
2016 Address, DisAsm: this, STI);
2017 if (Result != MCDisassembler::Fail) {
2018 Size = 4;
2019 return Result;
2020 }
2021 }
2022
2023 LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
2024 // Calling the auto-generated decoder function.
2025 Result = decodeInstruction(DecodeTable: DecoderTableMicroMips32, MI&: Instr, insn: Insn, Address,
2026 DisAsm: this, STI);
2027 if (Result != MCDisassembler::Fail) {
2028 Size = 4;
2029 return Result;
2030 }
2031
2032 if (isFP64()) {
2033 LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n");
2034 Result = decodeInstruction(DecodeTable: DecoderTableMicroMipsFP6432, MI&: Instr, insn: Insn,
2035 Address, DisAsm: this, STI);
2036 if (Result != MCDisassembler::Fail) {
2037 Size = 4;
2038 return Result;
2039 }
2040 }
2041
2042 // This is an invalid instruction. Claim that the Size is 2 bytes. Since
2043 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes
2044 // could form a valid instruction. The two bytes we rejected as an
2045 // instruction could have actually beeen an inline constant pool that is
2046 // unconditionally branched over.
2047 Size = 2;
2048 return MCDisassembler::Fail;
2049 }
2050
2051 // Attempt to read the instruction so that we can attempt to decode it. If
2052 // the buffer is not 4 bytes long, let the higher level logic figure out
2053 // what to do with a size of zero and MCDisassembler::Fail.
2054 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, IsMicroMips: false);
2055 if (Result == MCDisassembler::Fail)
2056 return MCDisassembler::Fail;
2057
2058 // The only instruction size for standard encoded MIPS.
2059 Size = 4;
2060
2061 if (hasCOP3()) {
2062 LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
2063 Result =
2064 decodeInstruction(DecodeTable: DecoderTableCOP3_32, MI&: Instr, insn: Insn, Address, DisAsm: this, STI);
2065 if (Result != MCDisassembler::Fail)
2066 return Result;
2067 }
2068
2069 if (hasMips32r6() && isGP64()) {
2070 LLVM_DEBUG(
2071 dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
2072 Result = decodeInstruction(DecodeTable: DecoderTableMips32r6_64r6_GP6432, MI&: Instr, insn: Insn,
2073 Address, DisAsm: this, STI);
2074 if (Result != MCDisassembler::Fail)
2075 return Result;
2076 }
2077
2078 if (hasMips32r6() && isPTR64()) {
2079 LLVM_DEBUG(
2080 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
2081 Result = decodeInstruction(DecodeTable: DecoderTableMips32r6_64r6_PTR6432, MI&: Instr, insn: Insn,
2082 Address, DisAsm: this, STI);
2083 if (Result != MCDisassembler::Fail)
2084 return Result;
2085 }
2086
2087 if (hasMips32r6()) {
2088 LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
2089 Result = decodeInstruction(DecodeTable: DecoderTableMips32r6_64r632, MI&: Instr, insn: Insn,
2090 Address, DisAsm: this, STI);
2091 if (Result != MCDisassembler::Fail)
2092 return Result;
2093 }
2094
2095 if (hasMips2() && isPTR64()) {
2096 LLVM_DEBUG(
2097 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
2098 Result = decodeInstruction(DecodeTable: DecoderTableMips32_64_PTR6432, MI&: Instr, insn: Insn,
2099 Address, DisAsm: this, STI);
2100 if (Result != MCDisassembler::Fail)
2101 return Result;
2102 }
2103
2104 if (hasCnMips()) {
2105 LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
2106 Result = decodeInstruction(DecodeTable: DecoderTableCnMips32, MI&: Instr, insn: Insn, Address, DisAsm: this,
2107 STI);
2108 if (Result != MCDisassembler::Fail)
2109 return Result;
2110 }
2111
2112 if (hasCnMipsP()) {
2113 LLVM_DEBUG(dbgs() << "Trying CnMipsP table (32-bit opcodes):\n");
2114 Result = decodeInstruction(DecodeTable: DecoderTableCnMipsP32, MI&: Instr, insn: Insn, Address,
2115 DisAsm: this, STI);
2116 if (Result != MCDisassembler::Fail)
2117 return Result;
2118 }
2119
2120 if (isGP64()) {
2121 LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
2122 Result = decodeInstruction(DecodeTable: DecoderTableMips6432, MI&: Instr, insn: Insn, Address, DisAsm: this,
2123 STI);
2124 if (Result != MCDisassembler::Fail)
2125 return Result;
2126 }
2127
2128 if (isFP64()) {
2129 LLVM_DEBUG(
2130 dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n");
2131 Result = decodeInstruction(DecodeTable: DecoderTableMipsFP6432, MI&: Instr, insn: Insn, Address,
2132 DisAsm: this, STI);
2133 if (Result != MCDisassembler::Fail)
2134 return Result;
2135 }
2136
2137 LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
2138 // Calling the auto-generated decoder function.
2139 Result =
2140 decodeInstruction(DecodeTable: DecoderTableMips32, MI&: Instr, insn: Insn, Address, DisAsm: this, STI);
2141 if (Result != MCDisassembler::Fail)
2142 return Result;
2143
2144 return MCDisassembler::Fail;
2145}
2146