1//===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file is part of the Mips Disassembler.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/MipsMCTargetDesc.h"
14#include "TargetInfo/MipsTargetInfo.h"
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCDecoder.h"
18#include "llvm/MC/MCDecoderOps.h"
19#include "llvm/MC/MCDisassembler/MCDisassembler.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/MC/TargetRegistry.h"
24#include "llvm/Support/Compiler.h"
25#include "llvm/Support/Debug.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/MathExtras.h"
28#include "llvm/Support/raw_ostream.h"
29#include <cassert>
30#include <cstdint>
31
32using namespace llvm;
33using namespace llvm::MCD;
34
35#define DEBUG_TYPE "mips-disassembler"
36
37using DecodeStatus = MCDisassembler::DecodeStatus;
38
39namespace {
40
41class MipsDisassembler : public MCDisassembler {
42 bool IsMicroMips;
43 bool IsBigEndian;
44
45public:
46 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
47 : MCDisassembler(STI, Ctx),
48 IsMicroMips(STI.hasFeature(Feature: Mips::FeatureMicroMips)),
49 IsBigEndian(IsBigEndian) {}
50
51 bool hasMips2() const { return STI.hasFeature(Feature: Mips::FeatureMips2); }
52 bool hasMips3() const { return STI.hasFeature(Feature: Mips::FeatureMips3); }
53 bool hasMips32() const { return STI.hasFeature(Feature: Mips::FeatureMips32); }
54
55 bool hasMips32r6() const {
56 return STI.hasFeature(Feature: Mips::FeatureMips32r6);
57 }
58
59 bool isFP64() const { return STI.hasFeature(Feature: Mips::FeatureFP64Bit); }
60
61 bool isGP64() const { return STI.hasFeature(Feature: Mips::FeatureGP64Bit); }
62
63 bool isPTR64() const { return STI.hasFeature(Feature: Mips::FeaturePTR64Bit); }
64
65 bool hasCnMips() const { return STI.hasFeature(Feature: Mips::FeatureCnMips); }
66
67 bool hasCnMipsP() const { return STI.hasFeature(Feature: Mips::FeatureCnMipsP); }
68
69 bool hasCOP3() const {
70 // Only present in MIPS-I and MIPS-II
71 return !hasMips32() && !hasMips3();
72 }
73
74 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
75 ArrayRef<uint8_t> Bytes, uint64_t Address,
76 raw_ostream &CStream) const override;
77};
78
79} // end anonymous namespace
80
81static MCDisassembler *createMipsDisassembler(const Target &T,
82 const MCSubtargetInfo &STI,
83 MCContext &Ctx) {
84 return new MipsDisassembler(STI, Ctx, true);
85}
86
87static MCDisassembler *createMipselDisassembler(const Target &T,
88 const MCSubtargetInfo &STI,
89 MCContext &Ctx) {
90 return new MipsDisassembler(STI, Ctx, false);
91}
92
93extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
94LLVMInitializeMipsDisassembler() {
95 // Register the disassembler.
96 TargetRegistry::RegisterMCDisassembler(T&: getTheMipsTarget(),
97 Fn: createMipsDisassembler);
98 TargetRegistry::RegisterMCDisassembler(T&: getTheMipselTarget(),
99 Fn: createMipselDisassembler);
100 TargetRegistry::RegisterMCDisassembler(T&: getTheMips64Target(),
101 Fn: createMipsDisassembler);
102 TargetRegistry::RegisterMCDisassembler(T&: getTheMips64elTarget(),
103 Fn: createMipselDisassembler);
104}
105
106static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo) {
107 const MCRegisterInfo *RegInfo = D->getContext().getRegisterInfo();
108 return RegInfo->getRegClass(i: RC).getRegister(i: RegNo);
109}
110static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo,
111 uint64_t Address,
112 const MCDisassembler *Decoder) {
113 // Currently only hardware register 29 is supported.
114 if (RegNo != 29)
115 return MCDisassembler::Fail;
116 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::HWR29));
117 return MCDisassembler::Success;
118}
119
120static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
121 uint64_t Address,
122 const MCDisassembler *Decoder) {
123 if (RegNo > 30 || RegNo % 2)
124 return MCDisassembler::Fail;
125
126 MCRegister Reg = getReg(D: Decoder, RC: Mips::AFGR64RegClassID, RegNo: RegNo / 2);
127 Inst.addOperand(Op: MCOperand::createReg(Reg));
128 return MCDisassembler::Success;
129}
130
131static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo,
132 uint64_t Address,
133 const MCDisassembler *Decoder) {
134 if (RegNo >= 4)
135 return MCDisassembler::Fail;
136
137 MCRegister Reg = getReg(D: Decoder, RC: Mips::ACC64DSPRegClassID, RegNo);
138 Inst.addOperand(Op: MCOperand::createReg(Reg));
139 return MCDisassembler::Success;
140}
141
142static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
143 uint64_t Address,
144 const MCDisassembler *Decoder) {
145 if (RegNo >= 4)
146 return MCDisassembler::Fail;
147
148 MCRegister Reg = getReg(D: Decoder, RC: Mips::HI32DSPRegClassID, RegNo);
149 Inst.addOperand(Op: MCOperand::createReg(Reg));
150 return MCDisassembler::Success;
151}
152
153static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
154 uint64_t Address,
155 const MCDisassembler *Decoder) {
156 if (RegNo >= 4)
157 return MCDisassembler::Fail;
158
159 MCRegister Reg = getReg(D: Decoder, RC: Mips::LO32DSPRegClassID, RegNo);
160 Inst.addOperand(Op: MCOperand::createReg(Reg));
161 return MCDisassembler::Success;
162}
163
164static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo,
165 uint64_t Address,
166 const MCDisassembler *Decoder) {
167 if (RegNo > 31)
168 return MCDisassembler::Fail;
169
170 MCRegister Reg = getReg(D: Decoder, RC: Mips::MSA128BRegClassID, RegNo);
171 Inst.addOperand(Op: MCOperand::createReg(Reg));
172 return MCDisassembler::Success;
173}
174
175static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo,
176 uint64_t Address,
177 const MCDisassembler *Decoder) {
178 if (RegNo > 31)
179 return MCDisassembler::Fail;
180
181 MCRegister Reg = getReg(D: Decoder, RC: Mips::MSA128HRegClassID, RegNo);
182 Inst.addOperand(Op: MCOperand::createReg(Reg));
183 return MCDisassembler::Success;
184}
185
186static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo,
187 uint64_t Address,
188 const MCDisassembler *Decoder) {
189 if (RegNo > 31)
190 return MCDisassembler::Fail;
191
192 MCRegister Reg = getReg(D: Decoder, RC: Mips::MSA128WRegClassID, RegNo);
193 Inst.addOperand(Op: MCOperand::createReg(Reg));
194 return MCDisassembler::Success;
195}
196
197static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo,
198 uint64_t Address,
199 const MCDisassembler *Decoder) {
200 if (RegNo > 31)
201 return MCDisassembler::Fail;
202
203 MCRegister Reg = getReg(D: Decoder, RC: Mips::MSA128DRegClassID, RegNo);
204 Inst.addOperand(Op: MCOperand::createReg(Reg));
205 return MCDisassembler::Success;
206}
207
208static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo,
209 uint64_t Address,
210 const MCDisassembler *Decoder) {
211 if (RegNo > 7)
212 return MCDisassembler::Fail;
213
214 MCRegister Reg = getReg(D: Decoder, RC: Mips::MSACtrlRegClassID, RegNo);
215 Inst.addOperand(Op: MCOperand::createReg(Reg));
216 return MCDisassembler::Success;
217}
218
219static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo,
220 uint64_t Address,
221 const MCDisassembler *Decoder) {
222 if (RegNo > 31)
223 return MCDisassembler::Fail;
224
225 MCRegister Reg = getReg(D: Decoder, RC: Mips::COP0RegClassID, RegNo);
226 Inst.addOperand(Op: MCOperand::createReg(Reg));
227 return MCDisassembler::Success;
228}
229
230static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo,
231 uint64_t Address,
232 const MCDisassembler *Decoder) {
233 if (RegNo > 31)
234 return MCDisassembler::Fail;
235
236 MCRegister Reg = getReg(D: Decoder, RC: Mips::COP2RegClassID, RegNo);
237 Inst.addOperand(Op: MCOperand::createReg(Reg));
238 return MCDisassembler::Success;
239}
240
241static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
242 uint64_t Address,
243 const MCDisassembler *Decoder) {
244 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4,
245 Mips::S5, Mips::S6, Mips::S7, Mips::FP};
246 unsigned RegNum;
247
248 unsigned RegLst = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
249
250 // Empty register lists are not allowed.
251 if (RegLst == 0)
252 return MCDisassembler::Fail;
253
254 RegNum = RegLst & 0xf;
255
256 // RegLst values 10-15, and 26-31 are reserved.
257 if (RegNum > 9)
258 return MCDisassembler::Fail;
259
260 for (unsigned i = 0; i < RegNum; i++)
261 Inst.addOperand(Op: MCOperand::createReg(Reg: Regs[i]));
262
263 if (RegLst & 0x10)
264 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::RA));
265
266 return MCDisassembler::Success;
267}
268
269static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
270 uint64_t Address,
271 const MCDisassembler *Decoder) {
272 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
273 unsigned RegLst;
274 switch (Inst.getOpcode()) {
275 default:
276 RegLst = fieldFromInstruction(Insn, StartBit: 4, NumBits: 2);
277 break;
278 case Mips::LWM16_MMR6:
279 case Mips::SWM16_MMR6:
280 RegLst = fieldFromInstruction(Insn, StartBit: 8, NumBits: 2);
281 break;
282 }
283 unsigned RegNum = RegLst & 0x3;
284
285 for (unsigned i = 0; i <= RegNum; i++)
286 Inst.addOperand(Op: MCOperand::createReg(Reg: Regs[i]));
287
288 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::RA));
289
290 return MCDisassembler::Success;
291}
292
293template <typename InsnType>
294static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
295 const MCDisassembler *Decoder) {
296 using DecodeFN =
297 DecodeStatus (*)(MCInst &, unsigned, uint64_t, const MCDisassembler *);
298
299 // The size of the n field depends on the element size
300 // The register class also depends on this.
301 InsnType tmp = fieldFromInstruction(insn, 17, 5);
302 unsigned NSize = 0;
303 DecodeFN RegDecoder = nullptr;
304 if ((tmp & 0x18) == 0x00) { // INSVE_B
305 NSize = 4;
306 RegDecoder = DecodeMSA128BRegisterClass;
307 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
308 NSize = 3;
309 RegDecoder = DecodeMSA128HRegisterClass;
310 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
311 NSize = 2;
312 RegDecoder = DecodeMSA128WRegisterClass;
313 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
314 NSize = 1;
315 RegDecoder = DecodeMSA128DRegisterClass;
316 } else
317 llvm_unreachable("Invalid encoding");
318
319 assert(NSize != 0 && RegDecoder != nullptr);
320
321 // $wd
322 tmp = fieldFromInstruction(insn, 6, 5);
323 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
324 return MCDisassembler::Fail;
325 // $wd_in
326 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
327 return MCDisassembler::Fail;
328 // $n
329 tmp = fieldFromInstruction(insn, 16, NSize);
330 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
331 // $ws
332 tmp = fieldFromInstruction(insn, 11, 5);
333 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
334 return MCDisassembler::Fail;
335 // $n2
336 MI.addOperand(Op: MCOperand::createImm(Val: 0));
337
338 return MCDisassembler::Success;
339}
340
341template <typename InsnType>
342static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn,
343 uint64_t Address,
344 const MCDisassembler *Decoder) {
345 InsnType Rs = fieldFromInstruction(insn, 16, 5);
346 InsnType Imm = fieldFromInstruction(insn, 0, 16);
347 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR64RegClassID,
348 Rs)));
349 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR64RegClassID,
350 Rs)));
351 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
352
353 return MCDisassembler::Success;
354}
355
356template <typename InsnType>
357static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
358 const MCDisassembler *Decoder) {
359 InsnType Rs = fieldFromInstruction(insn, 21, 5);
360 InsnType Imm = fieldFromInstruction(insn, 0, 16);
361 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR64RegClassID,
362 Rs)));
363 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR64RegClassID,
364 Rs)));
365 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
366
367 return MCDisassembler::Success;
368}
369
370template <typename InsnType>
371static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
372 uint64_t Address,
373 const MCDisassembler *Decoder) {
374 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
375 // (otherwise we would have matched the ADDI instruction from the earlier
376 // ISA's instead).
377 //
378 // We have:
379 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
380 // BOVC if rs >= rt
381 // BEQZALC if rs == 0 && rt != 0
382 // BEQC if rs < rt && rs != 0
383
384 InsnType Rs = fieldFromInstruction(insn, 21, 5);
385 InsnType Rt = fieldFromInstruction(insn, 16, 5);
386 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
387 bool HasRs = false;
388
389 if (Rs >= Rt) {
390 MI.setOpcode(Mips::BOVC);
391 HasRs = true;
392 } else if (Rs != 0 && Rs < Rt) {
393 MI.setOpcode(Mips::BEQC);
394 HasRs = true;
395 } else
396 MI.setOpcode(Mips::BEQZALC);
397
398 if (HasRs)
399 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
400 Rs)));
401
402 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
403 Rt)));
404 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
405
406 return MCDisassembler::Success;
407}
408
409template <typename InsnType>
410static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn,
411 uint64_t Address,
412 const MCDisassembler *Decoder) {
413 InsnType Rt = fieldFromInstruction(insn, 21, 5);
414 InsnType Rs = fieldFromInstruction(insn, 16, 5);
415 int64_t Imm = 0;
416
417 if (Rs >= Rt) {
418 MI.setOpcode(Mips::BOVC_MMR6);
419 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
420 Rt)));
421 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
422 Rs)));
423 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
424 } else if (Rs != 0 && Rs < Rt) {
425 MI.setOpcode(Mips::BEQC_MMR6);
426 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
427 Rs)));
428 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
429 Rt)));
430 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
431 } else {
432 MI.setOpcode(Mips::BEQZALC_MMR6);
433 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
434 Rt)));
435 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
436 }
437
438 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
439
440 return MCDisassembler::Success;
441}
442
443template <typename InsnType>
444static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
445 uint64_t Address,
446 const MCDisassembler *Decoder) {
447 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
448 // (otherwise we would have matched the ADDI instruction from the earlier
449 // ISA's instead).
450 //
451 // We have:
452 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
453 // BNVC if rs >= rt
454 // BNEZALC if rs == 0 && rt != 0
455 // BNEC if rs < rt && rs != 0
456
457 InsnType Rs = fieldFromInstruction(insn, 21, 5);
458 InsnType Rt = fieldFromInstruction(insn, 16, 5);
459 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
460 bool HasRs = false;
461
462 if (Rs >= Rt) {
463 MI.setOpcode(Mips::BNVC);
464 HasRs = true;
465 } else if (Rs != 0 && Rs < Rt) {
466 MI.setOpcode(Mips::BNEC);
467 HasRs = true;
468 } else
469 MI.setOpcode(Mips::BNEZALC);
470
471 if (HasRs)
472 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
473 Rs)));
474
475 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
476 Rt)));
477 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
478
479 return MCDisassembler::Success;
480}
481
482template <typename InsnType>
483static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn,
484 uint64_t Address,
485 const MCDisassembler *Decoder) {
486 InsnType Rt = fieldFromInstruction(insn, 21, 5);
487 InsnType Rs = fieldFromInstruction(insn, 16, 5);
488 int64_t Imm = 0;
489
490 if (Rs >= Rt) {
491 MI.setOpcode(Mips::BNVC_MMR6);
492 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
493 Rt)));
494 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
495 Rs)));
496 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
497 } else if (Rs != 0 && Rs < Rt) {
498 MI.setOpcode(Mips::BNEC_MMR6);
499 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
500 Rs)));
501 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
502 Rt)));
503 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
504 } else {
505 MI.setOpcode(Mips::BNEZALC_MMR6);
506 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
507 Rt)));
508 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
509 }
510
511 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
512
513 return MCDisassembler::Success;
514}
515
516template <typename InsnType>
517static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn,
518 uint64_t Address,
519 const MCDisassembler *Decoder) {
520 // We have:
521 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii
522 // Invalid if rt == 0
523 // BGTZC_MMR6 if rs == 0 && rt != 0
524 // BLTZC_MMR6 if rs == rt && rt != 0
525 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0
526
527 InsnType Rt = fieldFromInstruction(insn, 21, 5);
528 InsnType Rs = fieldFromInstruction(insn, 16, 5);
529 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
530 bool HasRs = false;
531
532 if (Rt == 0)
533 return MCDisassembler::Fail;
534 else if (Rs == 0)
535 MI.setOpcode(Mips::BGTZC_MMR6);
536 else if (Rs == Rt)
537 MI.setOpcode(Mips::BLTZC_MMR6);
538 else {
539 MI.setOpcode(Mips::BLTC_MMR6);
540 HasRs = true;
541 }
542
543 if (HasRs)
544 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
545 Rs)));
546
547 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
548 Rt)));
549
550 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
551
552 return MCDisassembler::Success;
553}
554
555template <typename InsnType>
556static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn,
557 uint64_t Address,
558 const MCDisassembler *Decoder) {
559 // We have:
560 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii
561 // Invalid if rt == 0
562 // BLEZC_MMR6 if rs == 0 && rt != 0
563 // BGEZC_MMR6 if rs == rt && rt != 0
564 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0
565
566 InsnType Rt = fieldFromInstruction(insn, 21, 5);
567 InsnType Rs = fieldFromInstruction(insn, 16, 5);
568 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
569 bool HasRs = false;
570
571 if (Rt == 0)
572 return MCDisassembler::Fail;
573 else if (Rs == 0)
574 MI.setOpcode(Mips::BLEZC_MMR6);
575 else if (Rs == Rt)
576 MI.setOpcode(Mips::BGEZC_MMR6);
577 else {
578 HasRs = true;
579 MI.setOpcode(Mips::BGEC_MMR6);
580 }
581
582 if (HasRs)
583 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
584 Rs)));
585
586 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
587 Rt)));
588
589 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
590
591 return MCDisassembler::Success;
592}
593
594template <typename InsnType>
595static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
596 uint64_t Address,
597 const MCDisassembler *Decoder) {
598 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
599 // (otherwise we would have matched the BLEZL instruction from the earlier
600 // ISA's instead).
601 //
602 // We have:
603 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
604 // Invalid if rs == 0
605 // BLEZC if rs == 0 && rt != 0
606 // BGEZC if rs == rt && rt != 0
607 // BGEC if rs != rt && rs != 0 && rt != 0
608
609 InsnType Rs = fieldFromInstruction(insn, 21, 5);
610 InsnType Rt = fieldFromInstruction(insn, 16, 5);
611 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
612 bool HasRs = false;
613
614 if (Rt == 0)
615 return MCDisassembler::Fail;
616 else if (Rs == 0)
617 MI.setOpcode(Mips::BLEZC);
618 else if (Rs == Rt)
619 MI.setOpcode(Mips::BGEZC);
620 else {
621 HasRs = true;
622 MI.setOpcode(Mips::BGEC);
623 }
624
625 if (HasRs)
626 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
627 Rs)));
628
629 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
630 Rt)));
631
632 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
633
634 return MCDisassembler::Success;
635}
636
637template <typename InsnType>
638static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
639 uint64_t Address,
640 const MCDisassembler *Decoder) {
641 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
642 // (otherwise we would have matched the BGTZL instruction from the earlier
643 // ISA's instead).
644 //
645 // We have:
646 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
647 // Invalid if rs == 0
648 // BGTZC if rs == 0 && rt != 0
649 // BLTZC if rs == rt && rt != 0
650 // BLTC if rs != rt && rs != 0 && rt != 0
651
652 bool HasRs = false;
653
654 InsnType Rs = fieldFromInstruction(insn, 21, 5);
655 InsnType Rt = fieldFromInstruction(insn, 16, 5);
656 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
657
658 if (Rt == 0)
659 return MCDisassembler::Fail;
660 else if (Rs == 0)
661 MI.setOpcode(Mips::BGTZC);
662 else if (Rs == Rt)
663 MI.setOpcode(Mips::BLTZC);
664 else {
665 MI.setOpcode(Mips::BLTC);
666 HasRs = true;
667 }
668
669 if (HasRs)
670 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
671 Rs)));
672
673 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
674 Rt)));
675
676 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
677
678 return MCDisassembler::Success;
679}
680
681template <typename InsnType>
682static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
683 uint64_t Address,
684 const MCDisassembler *Decoder) {
685 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
686 // (otherwise we would have matched the BGTZ instruction from the earlier
687 // ISA's instead).
688 //
689 // We have:
690 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
691 // BGTZ if rt == 0
692 // BGTZALC if rs == 0 && rt != 0
693 // BLTZALC if rs != 0 && rs == rt
694 // BLTUC if rs != 0 && rs != rt
695
696 InsnType Rs = fieldFromInstruction(insn, 21, 5);
697 InsnType Rt = fieldFromInstruction(insn, 16, 5);
698 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
699 bool HasRs = false;
700 bool HasRt = false;
701
702 if (Rt == 0) {
703 MI.setOpcode(Mips::BGTZ);
704 HasRs = true;
705 } else if (Rs == 0) {
706 MI.setOpcode(Mips::BGTZALC);
707 HasRt = true;
708 } else if (Rs == Rt) {
709 MI.setOpcode(Mips::BLTZALC);
710 HasRs = true;
711 } else {
712 MI.setOpcode(Mips::BLTUC);
713 HasRs = true;
714 HasRt = true;
715 }
716
717 if (HasRs)
718 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
719 Rs)));
720
721 if (HasRt)
722 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
723 Rt)));
724
725 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
726
727 return MCDisassembler::Success;
728}
729
730template <typename InsnType>
731static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
732 uint64_t Address,
733 const MCDisassembler *Decoder) {
734 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
735 // (otherwise we would have matched the BLEZL instruction from the earlier
736 // ISA's instead).
737 //
738 // We have:
739 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
740 // Invalid if rs == 0
741 // BLEZALC if rs == 0 && rt != 0
742 // BGEZALC if rs == rt && rt != 0
743 // BGEUC if rs != rt && rs != 0 && rt != 0
744
745 InsnType Rs = fieldFromInstruction(insn, 21, 5);
746 InsnType Rt = fieldFromInstruction(insn, 16, 5);
747 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
748 bool HasRs = false;
749
750 if (Rt == 0)
751 return MCDisassembler::Fail;
752 else if (Rs == 0)
753 MI.setOpcode(Mips::BLEZALC);
754 else if (Rs == Rt)
755 MI.setOpcode(Mips::BGEZALC);
756 else {
757 HasRs = true;
758 MI.setOpcode(Mips::BGEUC);
759 }
760
761 if (HasRs)
762 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
763 Rs)));
764 MI.addOperand(Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID,
765 Rt)));
766
767 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
768
769 return MCDisassembler::Success;
770}
771
772// Override the generated disassembler to produce DEXT all the time. This is
773// for feature / behaviour parity with binutils.
774template <typename InsnType>
775static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
776 const MCDisassembler *Decoder) {
777 unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
778 unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
779 unsigned Size = 0;
780 unsigned Pos = 0;
781
782 switch (MI.getOpcode()) {
783 case Mips::DEXT:
784 Pos = Lsb;
785 Size = Msbd + 1;
786 break;
787 case Mips::DEXTM:
788 Pos = Lsb;
789 Size = Msbd + 1 + 32;
790 break;
791 case Mips::DEXTU:
792 Pos = Lsb + 32;
793 Size = Msbd + 1;
794 break;
795 default:
796 llvm_unreachable("Unknown DEXT instruction!");
797 }
798
799 MI.setOpcode(Mips::DEXT);
800
801 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
802 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
803
804 MI.addOperand(
805 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR64RegClassID, Rt)));
806 MI.addOperand(
807 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR64RegClassID, Rs)));
808 MI.addOperand(Op: MCOperand::createImm(Val: Pos));
809 MI.addOperand(Op: MCOperand::createImm(Val: Size));
810
811 return MCDisassembler::Success;
812}
813
814// Override the generated disassembler to produce DINS all the time. This is
815// for feature / behaviour parity with binutils.
816template <typename InsnType>
817static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
818 const MCDisassembler *Decoder) {
819 unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
820 unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
821 unsigned Size = 0;
822 unsigned Pos = 0;
823
824 switch (MI.getOpcode()) {
825 case Mips::DINS:
826 Pos = Lsb;
827 Size = Msbd + 1 - Pos;
828 break;
829 case Mips::DINSM:
830 Pos = Lsb;
831 Size = Msbd + 33 - Pos;
832 break;
833 case Mips::DINSU:
834 Pos = Lsb + 32;
835 // mbsd = pos + size - 33
836 // mbsd - pos + 33 = size
837 Size = Msbd + 33 - Pos;
838 break;
839 default:
840 llvm_unreachable("Unknown DINS instruction!");
841 }
842
843 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
844 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
845
846 MI.setOpcode(Mips::DINS);
847 MI.addOperand(
848 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR64RegClassID, Rt)));
849 MI.addOperand(
850 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR64RegClassID, Rs)));
851 MI.addOperand(Op: MCOperand::createImm(Val: Pos));
852 MI.addOperand(Op: MCOperand::createImm(Val: Size));
853
854 return MCDisassembler::Success;
855}
856
857// Auto-generated decoder wouldn't add the third operand for CRC32*.
858template <typename InsnType>
859static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
860 const MCDisassembler *Decoder) {
861 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
862 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
863 MI.addOperand(
864 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID, Rt)));
865 MI.addOperand(
866 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID, Rs)));
867 MI.addOperand(
868 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID, Rt)));
869 return MCDisassembler::Success;
870}
871
872static DecodeStatus
873DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
874 const MCDisassembler *Decoder) {
875 return MCDisassembler::Fail;
876}
877
878static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
879 uint64_t Address,
880 const MCDisassembler *Decoder) {
881 if (RegNo > 31)
882 return MCDisassembler::Fail;
883
884 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPR64RegClassID, RegNo);
885 Inst.addOperand(Op: MCOperand::createReg(Reg));
886 return MCDisassembler::Success;
887}
888
889static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo,
890 uint64_t Address,
891 const MCDisassembler *Decoder) {
892 if (RegNo > 7)
893 return MCDisassembler::Fail;
894 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPRMM16RegClassID, RegNo);
895 Inst.addOperand(Op: MCOperand::createReg(Reg));
896 return MCDisassembler::Success;
897}
898
899static DecodeStatus
900DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
901 const MCDisassembler *Decoder) {
902 if (RegNo > 7)
903 return MCDisassembler::Fail;
904 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPRMM16ZeroRegClassID, RegNo);
905 Inst.addOperand(Op: MCOperand::createReg(Reg));
906 return MCDisassembler::Success;
907}
908
909static DecodeStatus
910DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
911 const MCDisassembler *Decoder) {
912 if (RegNo > 7)
913 return MCDisassembler::Fail;
914 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPRMM16MovePRegClassID, RegNo);
915 Inst.addOperand(Op: MCOperand::createReg(Reg));
916 return MCDisassembler::Success;
917}
918
919// Tablegen emits references to these unimplemented functions due to usage of
920// RegClassByHwMode - it does not detect that the RegClassByHwMode decoders are
921// unused, which in turn use these register class decoders.
922static DecodeStatus DecodeGP32RegisterClass(MCInst &Inst, unsigned RegNo,
923 uint64_t Address,
924 const MCDisassembler *Decoder) {
925 llvm_unreachable("this is unused");
926}
927
928static DecodeStatus DecodeGP64RegisterClass(MCInst &Inst, unsigned RegNo,
929 uint64_t Address,
930 const MCDisassembler *Decoder) {
931 llvm_unreachable("this is unused");
932}
933
934static DecodeStatus DecodeSP32RegisterClass(MCInst &Inst, unsigned RegNo,
935 uint64_t Address,
936 const MCDisassembler *Decoder) {
937 llvm_unreachable("this is unused");
938}
939
940static DecodeStatus DecodeSP64RegisterClass(MCInst &Inst, unsigned RegNo,
941 uint64_t Address,
942 const MCDisassembler *Decoder) {
943 llvm_unreachable("this is unused");
944}
945
946static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
947 uint64_t Address,
948 const MCDisassembler *Decoder) {
949 if (RegNo > 31)
950 return MCDisassembler::Fail;
951 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo);
952 Inst.addOperand(Op: MCOperand::createReg(Reg));
953 return MCDisassembler::Success;
954}
955
956static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo,
957 uint64_t Address,
958 const MCDisassembler *Decoder) {
959 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
960 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
961
962 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
963}
964
965static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo,
966 uint64_t Address,
967 const MCDisassembler *Decoder) {
968 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
969}
970
971static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
972 uint64_t Address,
973 const MCDisassembler *Decoder) {
974 if (RegNo > 31)
975 return MCDisassembler::Fail;
976
977 MCRegister Reg = getReg(D: Decoder, RC: Mips::FGR64RegClassID, RegNo);
978 Inst.addOperand(Op: MCOperand::createReg(Reg));
979 return MCDisassembler::Success;
980}
981
982static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo,
983 uint64_t Address,
984 const MCDisassembler *Decoder) {
985 if (RegNo > 31)
986 return MCDisassembler::Fail;
987
988 MCRegister Reg = getReg(D: Decoder, RC: Mips::FGR32RegClassID, RegNo);
989 Inst.addOperand(Op: MCOperand::createReg(Reg));
990 return MCDisassembler::Success;
991}
992
993static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo,
994 uint64_t Address,
995 const MCDisassembler *Decoder) {
996 if (RegNo > 31)
997 return MCDisassembler::Fail;
998 MCRegister Reg = getReg(D: Decoder, RC: Mips::CCRRegClassID, RegNo);
999 Inst.addOperand(Op: MCOperand::createReg(Reg));
1000 return MCDisassembler::Success;
1001}
1002
1003static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo,
1004 uint64_t Address,
1005 const MCDisassembler *Decoder) {
1006 if (RegNo > 7)
1007 return MCDisassembler::Fail;
1008 MCRegister Reg = getReg(D: Decoder, RC: Mips::FCCRegClassID, RegNo);
1009 Inst.addOperand(Op: MCOperand::createReg(Reg));
1010 return MCDisassembler::Success;
1011}
1012
1013static DecodeStatus DecodeFGR32CCRegisterClass(MCInst &Inst, unsigned RegNo,
1014 uint64_t Address,
1015 const MCDisassembler *Decoder) {
1016 if (RegNo > 31)
1017 return MCDisassembler::Fail;
1018
1019 MCRegister Reg = getReg(D: Decoder, RC: Mips::FGR32CCRegClassID, RegNo);
1020 Inst.addOperand(Op: MCOperand::createReg(Reg));
1021 return MCDisassembler::Success;
1022}
1023
1024static DecodeStatus DecodeFGR64CCRegisterClass(MCInst &Inst, unsigned RegNo,
1025 uint64_t Address,
1026 const MCDisassembler *Decoder) {
1027 if (RegNo > 31)
1028 return MCDisassembler::Fail;
1029
1030 MCRegister Reg = getReg(D: Decoder, RC: Mips::FGR64CCRegClassID, RegNo);
1031 Inst.addOperand(Op: MCOperand::createReg(Reg));
1032 return MCDisassembler::Success;
1033}
1034
1035static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address,
1036 const MCDisassembler *Decoder) {
1037 int Offset = SignExtend32<16>(X: Insn & 0xffff);
1038 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1039 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1040
1041 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo);
1042 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1043
1044 if (Inst.getOpcode() == Mips::SC || Inst.getOpcode() == Mips::SC64 ||
1045 Inst.getOpcode() == Mips::SCD)
1046 Inst.addOperand(Op: MCOperand::createReg(Reg));
1047
1048 Inst.addOperand(Op: MCOperand::createReg(Reg));
1049 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1050 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1051
1052 return MCDisassembler::Success;
1053}
1054
1055static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address,
1056 const MCDisassembler *Decoder) {
1057 int Offset = SignExtend32<9>(X: Insn >> 7);
1058 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1059 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1060
1061 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo);
1062 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1063
1064 if (Inst.getOpcode() == Mips::SCE)
1065 Inst.addOperand(Op: MCOperand::createReg(Reg));
1066
1067 Inst.addOperand(Op: MCOperand::createReg(Reg));
1068 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1069 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1070
1071 return MCDisassembler::Success;
1072}
1073
1074static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn,
1075 uint64_t Address,
1076 const MCDisassembler *Decoder) {
1077 int Offset = SignExtend32<16>(X: Insn & 0xffff);
1078 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1079 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1080
1081 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1082 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo);
1083
1084 Inst.addOperand(Op: MCOperand::createReg(Reg));
1085 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1086 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1087
1088 return MCDisassembler::Success;
1089}
1090
1091static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
1092 const MCDisassembler *Decoder) {
1093 int Offset = SignExtend32<16>(X: Insn & 0xffff);
1094 unsigned Hint = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1095 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1096
1097 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1098
1099 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1100 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1101 Inst.addOperand(Op: MCOperand::createImm(Val: Hint));
1102
1103 return MCDisassembler::Success;
1104}
1105
1106static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn,
1107 uint64_t Address,
1108 const MCDisassembler *Decoder) {
1109 int Offset = SignExtend32<12>(X: Insn & 0xfff);
1110 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1111 unsigned Hint = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1112
1113 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1114
1115 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1116 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1117 Inst.addOperand(Op: MCOperand::createImm(Val: Hint));
1118
1119 return MCDisassembler::Success;
1120}
1121
1122static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn,
1123 uint64_t Address,
1124 const MCDisassembler *Decoder) {
1125 int Offset = SignExtend32<9>(X: Insn & 0x1ff);
1126 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1127 unsigned Hint = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1128
1129 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1130
1131 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1132 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1133 Inst.addOperand(Op: MCOperand::createImm(Val: Hint));
1134
1135 return MCDisassembler::Success;
1136}
1137
1138static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn,
1139 uint64_t Address,
1140 const MCDisassembler *Decoder) {
1141 int Offset = SignExtend32<9>(X: Insn >> 7);
1142 unsigned Hint = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1143 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1144
1145 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1146
1147 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1148 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1149 Inst.addOperand(Op: MCOperand::createImm(Val: Hint));
1150
1151 return MCDisassembler::Success;
1152}
1153
1154static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address,
1155 const MCDisassembler *Decoder) {
1156 int Offset = SignExtend32<16>(X: Insn & 0xffff);
1157 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1158
1159 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1160
1161 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1162 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1163
1164 return MCDisassembler::Success;
1165}
1166
1167static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn,
1168 uint64_t Address,
1169 const MCDisassembler *Decoder) {
1170 int Offset = SignExtend32<16>(X: Insn & 0xffff);
1171 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1172
1173 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1174
1175 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1176 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1177
1178 return MCDisassembler::Success;
1179}
1180
1181static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address,
1182 const MCDisassembler *Decoder) {
1183 int Immediate = SignExtend32<16>(X: Insn & 0xffff);
1184 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1185
1186 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1187
1188 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1189 Inst.addOperand(Op: MCOperand::createImm(Val: Immediate));
1190
1191 return MCDisassembler::Success;
1192}
1193
1194static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1195 uint64_t Address,
1196 const MCDisassembler *Decoder) {
1197 int Offset = SignExtend32<10>(X: fieldFromInstruction(Insn, StartBit: 16, NumBits: 10));
1198 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 6, NumBits: 5);
1199 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 11, NumBits: 5);
1200
1201 MCRegister Reg = getReg(D: Decoder, RC: Mips::MSA128BRegClassID, RegNo);
1202 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1203
1204 Inst.addOperand(Op: MCOperand::createReg(Reg));
1205 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1206
1207 // The immediate field of an LD/ST instruction is scaled which means it must
1208 // be multiplied (when decoding) by the size (in bytes) of the instructions'
1209 // data format.
1210 // .b - 1 byte
1211 // .h - 2 bytes
1212 // .w - 4 bytes
1213 // .d - 8 bytes
1214 switch(Inst.getOpcode())
1215 {
1216 default:
1217 assert(false && "Unexpected instruction");
1218 return MCDisassembler::Fail;
1219 break;
1220 case Mips::LD_B:
1221 case Mips::ST_B:
1222 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1223 break;
1224 case Mips::LD_H:
1225 case Mips::ST_H:
1226 Inst.addOperand(Op: MCOperand::createImm(Val: Offset * 2));
1227 break;
1228 case Mips::LD_W:
1229 case Mips::ST_W:
1230 Inst.addOperand(Op: MCOperand::createImm(Val: Offset * 4));
1231 break;
1232 case Mips::LD_D:
1233 case Mips::ST_D:
1234 Inst.addOperand(Op: MCOperand::createImm(Val: Offset * 8));
1235 break;
1236 }
1237
1238 return MCDisassembler::Success;
1239}
1240
1241static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn,
1242 uint64_t Address,
1243 const MCDisassembler *Decoder) {
1244 unsigned Offset = Insn & 0xf;
1245 unsigned Reg = fieldFromInstruction(Insn, StartBit: 7, NumBits: 3);
1246 unsigned Base = fieldFromInstruction(Insn, StartBit: 4, NumBits: 3);
1247
1248 switch (Inst.getOpcode()) {
1249 case Mips::LBU16_MM:
1250 case Mips::LHU16_MM:
1251 case Mips::LW16_MM:
1252 if (DecodeGPRMM16RegisterClass(Inst, RegNo: Reg, Address, Decoder)
1253 == MCDisassembler::Fail)
1254 return MCDisassembler::Fail;
1255 break;
1256 case Mips::SB16_MM:
1257 case Mips::SB16_MMR6:
1258 case Mips::SH16_MM:
1259 case Mips::SH16_MMR6:
1260 case Mips::SW16_MM:
1261 case Mips::SW16_MMR6:
1262 if (DecodeGPRMM16ZeroRegisterClass(Inst, RegNo: Reg, Address, Decoder)
1263 == MCDisassembler::Fail)
1264 return MCDisassembler::Fail;
1265 break;
1266 }
1267
1268 if (DecodeGPRMM16RegisterClass(Inst, RegNo: Base, Address, Decoder)
1269 == MCDisassembler::Fail)
1270 return MCDisassembler::Fail;
1271
1272 switch (Inst.getOpcode()) {
1273 case Mips::LBU16_MM:
1274 if (Offset == 0xf)
1275 Inst.addOperand(Op: MCOperand::createImm(Val: -1));
1276 else
1277 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1278 break;
1279 case Mips::SB16_MM:
1280 case Mips::SB16_MMR6:
1281 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1282 break;
1283 case Mips::LHU16_MM:
1284 case Mips::SH16_MM:
1285 case Mips::SH16_MMR6:
1286 Inst.addOperand(Op: MCOperand::createImm(Val: Offset << 1));
1287 break;
1288 case Mips::LW16_MM:
1289 case Mips::SW16_MM:
1290 case Mips::SW16_MMR6:
1291 Inst.addOperand(Op: MCOperand::createImm(Val: Offset << 2));
1292 break;
1293 }
1294
1295 return MCDisassembler::Success;
1296}
1297
1298static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn,
1299 uint64_t Address,
1300 const MCDisassembler *Decoder) {
1301 unsigned Offset = Insn & 0x1F;
1302 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 5, NumBits: 5);
1303
1304 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo);
1305
1306 Inst.addOperand(Op: MCOperand::createReg(Reg));
1307 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::SP));
1308 Inst.addOperand(Op: MCOperand::createImm(Val: Offset << 2));
1309
1310 return MCDisassembler::Success;
1311}
1312
1313static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn,
1314 uint64_t Address,
1315 const MCDisassembler *Decoder) {
1316 unsigned Offset = Insn & 0x7F;
1317 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 7, NumBits: 3);
1318
1319 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo);
1320
1321 Inst.addOperand(Op: MCOperand::createReg(Reg));
1322 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::GP));
1323 Inst.addOperand(Op: MCOperand::createImm(Val: Offset << 2));
1324
1325 return MCDisassembler::Success;
1326}
1327
1328static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn,
1329 uint64_t Address,
1330 const MCDisassembler *Decoder) {
1331 int Offset;
1332 switch (Inst.getOpcode()) {
1333 case Mips::LWM16_MMR6:
1334 case Mips::SWM16_MMR6:
1335 Offset = fieldFromInstruction(Insn, StartBit: 4, NumBits: 4);
1336 break;
1337 default:
1338 Offset = SignExtend32<4>(X: Insn & 0xf);
1339 break;
1340 }
1341
1342 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1343 == MCDisassembler::Fail)
1344 return MCDisassembler::Fail;
1345
1346 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::SP));
1347 Inst.addOperand(Op: MCOperand::createImm(Val: Offset << 2));
1348
1349 return MCDisassembler::Success;
1350}
1351
1352static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn,
1353 uint64_t Address,
1354 const MCDisassembler *Decoder) {
1355 int Offset = SignExtend32<9>(X: Insn & 0x1ff);
1356 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1357 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1358
1359 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo);
1360 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1361
1362 if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6)
1363 Inst.addOperand(Op: MCOperand::createReg(Reg));
1364
1365 Inst.addOperand(Op: MCOperand::createReg(Reg));
1366 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1367 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1368
1369 return MCDisassembler::Success;
1370}
1371
1372static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn,
1373 uint64_t Address,
1374 const MCDisassembler *Decoder) {
1375 int Offset = SignExtend32<12>(X: Insn & 0x0fff);
1376 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1377 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1378
1379 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo);
1380 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1381
1382 switch (Inst.getOpcode()) {
1383 case Mips::SWM32_MM:
1384 case Mips::LWM32_MM:
1385 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1386 == MCDisassembler::Fail)
1387 return MCDisassembler::Fail;
1388 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1389 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1390 break;
1391 case Mips::SC_MM:
1392 Inst.addOperand(Op: MCOperand::createReg(Reg));
1393 [[fallthrough]];
1394 default:
1395 Inst.addOperand(Op: MCOperand::createReg(Reg));
1396 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1397 Inst.addOperand(Op: MCOperand::createReg(Reg: Reg+1));
1398
1399 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1400 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1401 }
1402
1403 return MCDisassembler::Success;
1404}
1405
1406static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn,
1407 uint64_t Address,
1408 const MCDisassembler *Decoder) {
1409 int Offset = SignExtend32<16>(X: Insn & 0xffff);
1410 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1411 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1412
1413 MCRegister Reg = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo);
1414 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1415
1416 Inst.addOperand(Op: MCOperand::createReg(Reg));
1417 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1418 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1419
1420 return MCDisassembler::Success;
1421}
1422
1423static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address,
1424 const MCDisassembler *Decoder) {
1425 int Offset = SignExtend32<16>(X: Insn & 0xffff);
1426 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1427 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1428
1429 MCRegister Reg = getReg(D: Decoder, RC: Mips::FGR64RegClassID, RegNo);
1430 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1431
1432 Inst.addOperand(Op: MCOperand::createReg(Reg));
1433 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1434 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1435
1436 return MCDisassembler::Success;
1437}
1438
1439static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
1440 uint64_t Address,
1441 const MCDisassembler *Decoder) {
1442 // This function is the same as DecodeFMem but with the Reg and Base fields
1443 // swapped according to microMIPS spec.
1444 int Offset = SignExtend32<16>(X: Insn & 0xffff);
1445 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1446 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1447
1448 MCRegister Reg = getReg(D: Decoder, RC: Mips::FGR64RegClassID, RegNo);
1449 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1450
1451 Inst.addOperand(Op: MCOperand::createReg(Reg));
1452 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1453 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1454
1455 return MCDisassembler::Success;
1456}
1457
1458static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,
1459 const MCDisassembler *Decoder) {
1460 int Offset = SignExtend32<16>(X: Insn & 0xffff);
1461 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1462 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1463
1464 MCRegister Reg = getReg(D: Decoder, RC: Mips::COP2RegClassID, RegNo);
1465 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1466
1467 Inst.addOperand(Op: MCOperand::createReg(Reg));
1468 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1469 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1470
1471 return MCDisassembler::Success;
1472}
1473
1474static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,
1475 const MCDisassembler *Decoder) {
1476 int Offset = SignExtend32<16>(X: Insn & 0xffff);
1477 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1478 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1479
1480 MCRegister Reg = getReg(D: Decoder, RC: Mips::COP3RegClassID, RegNo);
1481 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1482
1483 Inst.addOperand(Op: MCOperand::createReg(Reg));
1484 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1485 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1486
1487 return MCDisassembler::Success;
1488}
1489
1490static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
1491 uint64_t Address,
1492 const MCDisassembler *Decoder) {
1493 int Offset = SignExtend32<11>(X: Insn & 0x07ff);
1494 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1495 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 11, NumBits: 5);
1496
1497 MCRegister Reg = getReg(D: Decoder, RC: Mips::COP2RegClassID, RegNo);
1498 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1499
1500 Inst.addOperand(Op: MCOperand::createReg(Reg));
1501 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1502 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1503
1504 return MCDisassembler::Success;
1505}
1506
1507static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
1508 uint64_t Address,
1509 const MCDisassembler *Decoder) {
1510 int Offset = SignExtend32<11>(X: Insn & 0x07ff);
1511 unsigned RegNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1512 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1513
1514 MCRegister Reg = getReg(D: Decoder, RC: Mips::COP2RegClassID, RegNo);
1515 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1516
1517 Inst.addOperand(Op: MCOperand::createReg(Reg));
1518 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1519 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1520
1521 return MCDisassembler::Success;
1522}
1523
1524static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn,
1525 uint64_t Address,
1526 const MCDisassembler *Decoder) {
1527 int64_t Offset = SignExtend64<9>(x: (Insn >> 7) & 0x1ff);
1528 unsigned RtNo = fieldFromInstruction(Insn, StartBit: 16, NumBits: 5);
1529 unsigned BaseNo = fieldFromInstruction(Insn, StartBit: 21, NumBits: 5);
1530
1531 MCRegister Rt = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: RtNo);
1532 MCRegister Base = getReg(D: Decoder, RC: Mips::GPR32RegClassID, RegNo: BaseNo);
1533
1534 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1535 Inst.addOperand(Op: MCOperand::createReg(Reg: Rt));
1536 }
1537
1538 Inst.addOperand(Op: MCOperand::createReg(Reg: Rt));
1539 Inst.addOperand(Op: MCOperand::createReg(Reg: Base));
1540 Inst.addOperand(Op: MCOperand::createImm(Val: Offset));
1541
1542 return MCDisassembler::Success;
1543}
1544
1545static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset,
1546 uint64_t Address,
1547 const MCDisassembler *Decoder) {
1548 int32_t BranchOffset = (SignExtend32<16>(X: Offset) * 4) + 4;
1549 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1550 return MCDisassembler::Success;
1551}
1552
1553static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset,
1554 uint64_t Address,
1555 const MCDisassembler *Decoder) {
1556 int32_t BranchOffset = (SignExtend32<16>(X: Offset) * 2);
1557 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1558 return MCDisassembler::Success;
1559}
1560
1561static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn,
1562 uint64_t Address,
1563 const MCDisassembler *Decoder) {
1564 unsigned JumpOffset = fieldFromInstruction(Insn, StartBit: 0, NumBits: 26) << 2;
1565 Inst.addOperand(Op: MCOperand::createImm(Val: JumpOffset));
1566 return MCDisassembler::Success;
1567}
1568
1569static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset,
1570 uint64_t Address,
1571 const MCDisassembler *Decoder) {
1572 int32_t BranchOffset = SignExtend32<21>(X: Offset) * 4 + 4;
1573
1574 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1575 return MCDisassembler::Success;
1576}
1577
1578static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset,
1579 uint64_t Address,
1580 const MCDisassembler *Decoder) {
1581 int32_t BranchOffset = SignExtend32<21>(X: Offset) * 4 + 4;
1582
1583 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1584 return MCDisassembler::Success;
1585}
1586
1587static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset,
1588 uint64_t Address,
1589 const MCDisassembler *Decoder) {
1590 int32_t BranchOffset = SignExtend32<26>(X: Offset) * 4 + 4;
1591
1592 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1593 return MCDisassembler::Success;
1594}
1595
1596static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset,
1597 uint64_t Address,
1598 const MCDisassembler *Decoder) {
1599 int32_t BranchOffset = SignExtend32<8>(X: Offset << 1);
1600 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1601 return MCDisassembler::Success;
1602}
1603
1604static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset,
1605 uint64_t Address,
1606 const MCDisassembler *Decoder) {
1607 int32_t BranchOffset = SignExtend32<11>(X: Offset << 1);
1608 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1609 return MCDisassembler::Success;
1610}
1611
1612static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset,
1613 uint64_t Address,
1614 const MCDisassembler *Decoder) {
1615 int32_t BranchOffset = SignExtend32<16>(X: Offset) * 2 + 4;
1616 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1617 return MCDisassembler::Success;
1618}
1619
1620static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset,
1621 uint64_t Address,
1622 const MCDisassembler *Decoder) {
1623 int32_t BranchOffset = SignExtend32<27>(X: Offset << 1);
1624
1625 Inst.addOperand(Op: MCOperand::createImm(Val: BranchOffset));
1626 return MCDisassembler::Success;
1627}
1628
1629static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn,
1630 uint64_t Address,
1631 const MCDisassembler *Decoder) {
1632 unsigned JumpOffset = fieldFromInstruction(Insn, StartBit: 0, NumBits: 26) << 1;
1633 Inst.addOperand(Op: MCOperand::createImm(Val: JumpOffset));
1634 return MCDisassembler::Success;
1635}
1636
1637static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn,
1638 uint64_t Address,
1639 const MCDisassembler *Decoder) {
1640 unsigned JumpOffset = fieldFromInstruction(Insn, StartBit: 0, NumBits: 26) << 2;
1641 Inst.addOperand(Op: MCOperand::createImm(Val: JumpOffset));
1642 return MCDisassembler::Success;
1643}
1644
1645static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value,
1646 uint64_t Address,
1647 const MCDisassembler *Decoder) {
1648 if (Value == 0)
1649 Inst.addOperand(Op: MCOperand::createImm(Val: 1));
1650 else if (Value == 0x7)
1651 Inst.addOperand(Op: MCOperand::createImm(Val: -1));
1652 else
1653 Inst.addOperand(Op: MCOperand::createImm(Val: Value << 2));
1654 return MCDisassembler::Success;
1655}
1656
1657static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value,
1658 uint64_t Address,
1659 const MCDisassembler *Decoder) {
1660 if (Value == 0x7F)
1661 Inst.addOperand(Op: MCOperand::createImm(Val: -1));
1662 else
1663 Inst.addOperand(Op: MCOperand::createImm(Val: Value));
1664 return MCDisassembler::Success;
1665}
1666
1667static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value,
1668 uint64_t Address,
1669 const MCDisassembler *Decoder) {
1670 Inst.addOperand(Op: MCOperand::createImm(Val: Value == 0x0 ? 8 : Value));
1671 return MCDisassembler::Success;
1672}
1673
1674template <unsigned Bits, int Offset, int Scale>
1675static DecodeStatus
1676DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address,
1677 const MCDisassembler *Decoder) {
1678 Value &= ((1 << Bits) - 1);
1679 Value *= Scale;
1680 Inst.addOperand(Op: MCOperand::createImm(Val: Value + Offset));
1681 return MCDisassembler::Success;
1682}
1683
1684template <unsigned Bits, int Offset = 0, int ScaleBy = 1>
1685static DecodeStatus
1686DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address,
1687 const MCDisassembler *Decoder) {
1688 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy;
1689 Inst.addOperand(Op: MCOperand::createImm(Val: Imm + Offset));
1690 return MCDisassembler::Success;
1691}
1692
1693template <unsigned Bits, int Offset>
1694static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
1695 uint64_t Address,
1696 const MCDisassembler *Decoder) {
1697 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address,
1698 Decoder);
1699}
1700
1701static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address,
1702 const MCDisassembler *Decoder) {
1703 // First we need to grab the pos(lsb) from MCInst.
1704 // This function only handles the 32 bit variants of ins, as dins
1705 // variants are handled differently.
1706 int Pos = Inst.getOperand(i: 2).getImm();
1707 int Size = (int) Insn - Pos + 1;
1708 Inst.addOperand(Op: MCOperand::createImm(Val: SignExtend32<16>(X: Size)));
1709 return MCDisassembler::Success;
1710}
1711
1712static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1713 uint64_t Address,
1714 const MCDisassembler *Decoder) {
1715 Inst.addOperand(Op: MCOperand::createImm(Val: SignExtend32<19>(X: Insn) * 4));
1716 return MCDisassembler::Success;
1717}
1718
1719static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1720 uint64_t Address,
1721 const MCDisassembler *Decoder) {
1722 Inst.addOperand(Op: MCOperand::createImm(Val: SignExtend32<18>(X: Insn) * 8));
1723 return MCDisassembler::Success;
1724}
1725
1726static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address,
1727 const MCDisassembler *Decoder) {
1728 int32_t DecodedValue;
1729 switch (Insn) {
1730 case 0: DecodedValue = 256; break;
1731 case 1: DecodedValue = 257; break;
1732 case 510: DecodedValue = -258; break;
1733 case 511: DecodedValue = -257; break;
1734 default: DecodedValue = SignExtend32<9>(X: Insn); break;
1735 }
1736 Inst.addOperand(Op: MCOperand::createImm(Val: DecodedValue * 4));
1737 return MCDisassembler::Success;
1738}
1739
1740static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1741 uint64_t Address,
1742 const MCDisassembler *Decoder) {
1743 // Insn must be >= 0, since it is unsigned that condition is always true.
1744 assert(Insn < 16);
1745 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15,
1746 16, 31, 32, 63, 64, 255, 32768, 65535};
1747 Inst.addOperand(Op: MCOperand::createImm(Val: DecodedValues[Insn]));
1748 return MCDisassembler::Success;
1749}
1750
1751static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
1752 uint64_t Address,
1753 const MCDisassembler *Decoder) {
1754 switch (RegPair) {
1755 default:
1756 return MCDisassembler::Fail;
1757 case 0:
1758 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A1));
1759 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A2));
1760 break;
1761 case 1:
1762 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A1));
1763 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A3));
1764 break;
1765 case 2:
1766 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A2));
1767 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A3));
1768 break;
1769 case 3:
1770 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A0));
1771 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::S5));
1772 break;
1773 case 4:
1774 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A0));
1775 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::S6));
1776 break;
1777 case 5:
1778 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A0));
1779 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A1));
1780 break;
1781 case 6:
1782 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A0));
1783 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A2));
1784 break;
1785 case 7:
1786 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A0));
1787 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::A3));
1788 break;
1789 }
1790
1791 return MCDisassembler::Success;
1792}
1793
1794static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
1795 uint64_t Address,
1796 const MCDisassembler *Decoder) {
1797 unsigned RegPair = fieldFromInstruction(Insn, StartBit: 7, NumBits: 3);
1798 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) ==
1799 MCDisassembler::Fail)
1800 return MCDisassembler::Fail;
1801
1802 unsigned RegRs;
1803 if (static_cast<const MipsDisassembler *>(Decoder)->hasMips32r6())
1804 RegRs = fieldFromInstruction(Insn, StartBit: 0, NumBits: 2) |
1805 (fieldFromInstruction(Insn, StartBit: 3, NumBits: 1) << 2);
1806 else
1807 RegRs = fieldFromInstruction(Insn, StartBit: 1, NumBits: 3);
1808 if (DecodeGPRMM16MovePRegisterClass(Inst, RegNo: RegRs, Address, Decoder) ==
1809 MCDisassembler::Fail)
1810 return MCDisassembler::Fail;
1811
1812 unsigned RegRt = fieldFromInstruction(Insn, StartBit: 4, NumBits: 3);
1813 if (DecodeGPRMM16MovePRegisterClass(Inst, RegNo: RegRt, Address, Decoder) ==
1814 MCDisassembler::Fail)
1815 return MCDisassembler::Fail;
1816
1817 return MCDisassembler::Success;
1818}
1819
1820static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
1821 uint64_t Address,
1822 const MCDisassembler *Decoder) {
1823 Inst.addOperand(Op: MCOperand::createImm(Val: SignExtend32<25>(X: Insn << 2)));
1824 return MCDisassembler::Success;
1825}
1826
1827template <typename InsnType>
1828static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn,
1829 uint64_t Address,
1830 const MCDisassembler *Decoder) {
1831 // We have:
1832 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii
1833 // Invalid if rt == 0
1834 // BGTZALC_MMR6 if rs == 0 && rt != 0
1835 // BLTZALC_MMR6 if rs != 0 && rs == rt
1836 // BLTUC_MMR6 if rs != 0 && rs != rt
1837
1838 InsnType Rt = fieldFromInstruction(insn, 21, 5);
1839 InsnType Rs = fieldFromInstruction(insn, 16, 5);
1840 InsnType Imm = 0;
1841 bool HasRs = false;
1842 bool HasRt = false;
1843
1844 if (Rt == 0)
1845 return MCDisassembler::Fail;
1846 else if (Rs == 0) {
1847 MI.setOpcode(Mips::BGTZALC_MMR6);
1848 HasRt = true;
1849 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1850 }
1851 else if (Rs == Rt) {
1852 MI.setOpcode(Mips::BLTZALC_MMR6);
1853 HasRs = true;
1854 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1855 }
1856 else {
1857 MI.setOpcode(Mips::BLTUC_MMR6);
1858 HasRs = true;
1859 HasRt = true;
1860 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
1861 }
1862
1863 if (HasRs)
1864 MI.addOperand(
1865 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID, Rs)));
1866
1867 if (HasRt)
1868 MI.addOperand(
1869 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID, Rt)));
1870
1871 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
1872
1873 return MCDisassembler::Success;
1874}
1875
1876template <typename InsnType>
1877static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn,
1878 uint64_t Address,
1879 const MCDisassembler *Decoder) {
1880 // We have:
1881 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii
1882 // Invalid if rt == 0
1883 // BLEZALC_MMR6 if rs == 0 && rt != 0
1884 // BGEZALC_MMR6 if rs == rt && rt != 0
1885 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0
1886
1887 InsnType Rt = fieldFromInstruction(insn, 21, 5);
1888 InsnType Rs = fieldFromInstruction(insn, 16, 5);
1889 InsnType Imm = 0;
1890 bool HasRs = false;
1891
1892 if (Rt == 0)
1893 return MCDisassembler::Fail;
1894 else if (Rs == 0) {
1895 MI.setOpcode(Mips::BLEZALC_MMR6);
1896 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1897 }
1898 else if (Rs == Rt) {
1899 MI.setOpcode(Mips::BGEZALC_MMR6);
1900 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1901 }
1902 else {
1903 HasRs = true;
1904 MI.setOpcode(Mips::BGEUC_MMR6);
1905 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
1906 }
1907
1908 if (HasRs)
1909 MI.addOperand(
1910 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID, Rs)));
1911 MI.addOperand(
1912 Op: MCOperand::createReg(Reg: getReg(Decoder, Mips::GPR32RegClassID, Rt)));
1913
1914 MI.addOperand(Op: MCOperand::createImm(Val: Imm));
1915
1916 return MCDisassembler::Success;
1917}
1918
1919// This instruction does not have a working decoder, and needs to be
1920// fixed. This "fixme" function was introduced to keep the backend compiling,
1921// while making changes to tablegen code.
1922static DecodeStatus DecodeFIXMEInstruction(MCInst &Inst, unsigned Insn,
1923 uint64_t Address,
1924 const MCDisassembler *Decoder) {
1925 return MCDisassembler::Fail;
1926}
1927
1928#include "MipsGenDisassemblerTables.inc"
1929
1930/// Read two bytes from the ArrayRef and return 16 bit halfword sorted
1931/// according to the given endianness.
1932static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
1933 uint64_t &Size, uint32_t &Insn,
1934 bool IsBigEndian) {
1935 // We want to read exactly 2 Bytes of data.
1936 if (Bytes.size() < 2) {
1937 Size = 0;
1938 return MCDisassembler::Fail;
1939 }
1940
1941 if (IsBigEndian) {
1942 Insn = (Bytes[0] << 8) | Bytes[1];
1943 } else {
1944 Insn = (Bytes[1] << 8) | Bytes[0];
1945 }
1946
1947 return MCDisassembler::Success;
1948}
1949
1950/// Read four bytes from the ArrayRef and return 32 bit word sorted
1951/// according to the given endianness.
1952static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
1953 uint64_t &Size, uint32_t &Insn,
1954 bool IsBigEndian, bool IsMicroMips) {
1955 // We want to read exactly 4 Bytes of data.
1956 if (Bytes.size() < 4) {
1957 Size = 0;
1958 return MCDisassembler::Fail;
1959 }
1960
1961 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
1962 // always precede the low 16 bits in the instruction stream (that is, they
1963 // are placed at lower addresses in the instruction stream).
1964 //
1965 // microMIPS byte ordering:
1966 // Big-endian: 0 | 1 | 2 | 3
1967 // Little-endian: 1 | 0 | 3 | 2
1968
1969 if (IsBigEndian) {
1970 // Encoded as a big-endian 32-bit word in the stream.
1971 Insn =
1972 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
1973 } else {
1974 if (IsMicroMips) {
1975 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
1976 (Bytes[1] << 24);
1977 } else {
1978 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
1979 (Bytes[3] << 24);
1980 }
1981 }
1982
1983 return MCDisassembler::Success;
1984}
1985
1986DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
1987 ArrayRef<uint8_t> Bytes,
1988 uint64_t Address,
1989 raw_ostream &CStream) const {
1990 uint32_t Insn;
1991 DecodeStatus Result;
1992 Size = 0;
1993
1994 if (IsMicroMips) {
1995 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
1996 if (Result == MCDisassembler::Fail)
1997 return MCDisassembler::Fail;
1998
1999 if (hasMips32r6()) {
2000 LLVM_DEBUG(
2001 dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
2002 // Calling the auto-generated decoder function for microMIPS32R6
2003 // 16-bit instructions.
2004 Result = decodeInstruction(DecodeTable: DecoderTableMicroMipsR616, MI&: Instr, insn: Insn,
2005 Address, DisAsm: this, STI);
2006 if (Result != MCDisassembler::Fail) {
2007 Size = 2;
2008 return Result;
2009 }
2010 }
2011
2012 LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
2013 // Calling the auto-generated decoder function for microMIPS 16-bit
2014 // instructions.
2015 Result = decodeInstruction(DecodeTable: DecoderTableMicroMips16, MI&: Instr, insn: Insn, Address,
2016 DisAsm: this, STI);
2017 if (Result != MCDisassembler::Fail) {
2018 Size = 2;
2019 return Result;
2020 }
2021
2022 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, IsMicroMips: true);
2023 if (Result == MCDisassembler::Fail)
2024 return MCDisassembler::Fail;
2025
2026 if (hasMips32r6()) {
2027 LLVM_DEBUG(
2028 dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
2029 // Calling the auto-generated decoder function.
2030 Result = decodeInstruction(DecodeTable: DecoderTableMicroMipsR632, MI&: Instr, insn: Insn,
2031 Address, DisAsm: this, STI);
2032 if (Result != MCDisassembler::Fail) {
2033 Size = 4;
2034 return Result;
2035 }
2036 }
2037
2038 LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
2039 // Calling the auto-generated decoder function.
2040 Result = decodeInstruction(DecodeTable: DecoderTableMicroMips32, MI&: Instr, insn: Insn, Address,
2041 DisAsm: this, STI);
2042 if (Result != MCDisassembler::Fail) {
2043 Size = 4;
2044 return Result;
2045 }
2046
2047 if (isFP64()) {
2048 LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n");
2049 Result = decodeInstruction(DecodeTable: DecoderTableMicroMipsFP6432, MI&: Instr, insn: Insn,
2050 Address, DisAsm: this, STI);
2051 if (Result != MCDisassembler::Fail) {
2052 Size = 4;
2053 return Result;
2054 }
2055 }
2056
2057 // This is an invalid instruction. Claim that the Size is 2 bytes. Since
2058 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes
2059 // could form a valid instruction. The two bytes we rejected as an
2060 // instruction could have actually beeen an inline constant pool that is
2061 // unconditionally branched over.
2062 Size = 2;
2063 return MCDisassembler::Fail;
2064 }
2065
2066 // Attempt to read the instruction so that we can attempt to decode it. If
2067 // the buffer is not 4 bytes long, let the higher level logic figure out
2068 // what to do with a size of zero and MCDisassembler::Fail.
2069 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, IsMicroMips: false);
2070 if (Result == MCDisassembler::Fail)
2071 return MCDisassembler::Fail;
2072
2073 // The only instruction size for standard encoded MIPS.
2074 Size = 4;
2075
2076 if (hasCOP3()) {
2077 LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
2078 Result =
2079 decodeInstruction(DecodeTable: DecoderTableCOP3_32, MI&: Instr, insn: Insn, Address, DisAsm: this, STI);
2080 if (Result != MCDisassembler::Fail)
2081 return Result;
2082 }
2083
2084 if (hasMips32r6() && isGP64()) {
2085 LLVM_DEBUG(
2086 dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
2087 Result = decodeInstruction(DecodeTable: DecoderTableMips32r6_64r6_GP6432, MI&: Instr, insn: Insn,
2088 Address, DisAsm: this, STI);
2089 if (Result != MCDisassembler::Fail)
2090 return Result;
2091 }
2092
2093 if (hasMips32r6() && isPTR64()) {
2094 LLVM_DEBUG(
2095 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
2096 Result = decodeInstruction(DecodeTable: DecoderTableMips32r6_64r6_PTR6432, MI&: Instr, insn: Insn,
2097 Address, DisAsm: this, STI);
2098 if (Result != MCDisassembler::Fail)
2099 return Result;
2100 }
2101
2102 if (hasMips32r6()) {
2103 LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
2104 Result = decodeInstruction(DecodeTable: DecoderTableMips32r6_64r632, MI&: Instr, insn: Insn,
2105 Address, DisAsm: this, STI);
2106 if (Result != MCDisassembler::Fail)
2107 return Result;
2108 }
2109
2110 if (hasMips2() && isPTR64()) {
2111 LLVM_DEBUG(
2112 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
2113 Result = decodeInstruction(DecodeTable: DecoderTableMips32_64_PTR6432, MI&: Instr, insn: Insn,
2114 Address, DisAsm: this, STI);
2115 if (Result != MCDisassembler::Fail)
2116 return Result;
2117 }
2118
2119 if (hasCnMips()) {
2120 LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
2121 Result = decodeInstruction(DecodeTable: DecoderTableCnMips32, MI&: Instr, insn: Insn, Address, DisAsm: this,
2122 STI);
2123 if (Result != MCDisassembler::Fail)
2124 return Result;
2125 }
2126
2127 if (hasCnMipsP()) {
2128 LLVM_DEBUG(dbgs() << "Trying CnMipsP table (32-bit opcodes):\n");
2129 Result = decodeInstruction(DecodeTable: DecoderTableCnMipsP32, MI&: Instr, insn: Insn, Address,
2130 DisAsm: this, STI);
2131 if (Result != MCDisassembler::Fail)
2132 return Result;
2133 }
2134
2135 if (isGP64()) {
2136 LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
2137 Result = decodeInstruction(DecodeTable: DecoderTableMips6432, MI&: Instr, insn: Insn, Address, DisAsm: this,
2138 STI);
2139 if (Result != MCDisassembler::Fail)
2140 return Result;
2141 }
2142
2143 if (isFP64()) {
2144 LLVM_DEBUG(
2145 dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n");
2146 Result = decodeInstruction(DecodeTable: DecoderTableMipsFP6432, MI&: Instr, insn: Insn, Address,
2147 DisAsm: this, STI);
2148 if (Result != MCDisassembler::Fail)
2149 return Result;
2150 }
2151
2152 LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
2153 // Calling the auto-generated decoder function.
2154 Result =
2155 decodeInstruction(DecodeTable: DecoderTableMips32, MI&: Instr, insn: Insn, Address, DisAsm: this, STI);
2156 if (Result != MCDisassembler::Fail)
2157 return Result;
2158
2159 return MCDisassembler::Fail;
2160}
2161