1//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This class prints an Mips MCInst to a .s file.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MipsInstPrinter.h"
14#include "Mips.h"
15#include "llvm/ADT/StringExtras.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCExpr.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCInstrInfo.h"
20#include "llvm/MC/MCSubtargetInfo.h"
21#include "llvm/MC/MCSymbol.h"
22#include "llvm/Support/ErrorHandling.h"
23#include "llvm/Support/raw_ostream.h"
24using namespace llvm;
25
26#define DEBUG_TYPE "asm-printer"
27
28#define PRINT_ALIAS_INSTR
29#include "MipsGenAsmWriter.inc"
30
31template<unsigned R>
32static bool isReg(const MCInst &MI, unsigned OpNo) {
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
34 return MI.getOperand(i: OpNo).getReg() == R;
35}
36
37const char* Mips::MipsFCCToString(Mips::CondCode CC) {
38 switch (CC) {
39 case FCOND_F:
40 case FCOND_T: return "f";
41 case FCOND_UN:
42 case FCOND_OR: return "un";
43 case FCOND_OEQ:
44 case FCOND_UNE: return "eq";
45 case FCOND_UEQ:
46 case FCOND_ONE: return "ueq";
47 case FCOND_OLT:
48 case FCOND_UGE: return "olt";
49 case FCOND_ULT:
50 case FCOND_OGE: return "ult";
51 case FCOND_OLE:
52 case FCOND_UGT: return "ole";
53 case FCOND_ULE:
54 case FCOND_OGT: return "ule";
55 case FCOND_SF:
56 case FCOND_ST: return "sf";
57 case FCOND_NGLE:
58 case FCOND_GLE: return "ngle";
59 case FCOND_SEQ:
60 case FCOND_SNE: return "seq";
61 case FCOND_NGL:
62 case FCOND_GL: return "ngl";
63 case FCOND_LT:
64 case FCOND_NLT: return "lt";
65 case FCOND_NGE:
66 case FCOND_GE: return "nge";
67 case FCOND_LE:
68 case FCOND_NLE: return "le";
69 case FCOND_NGT:
70 case FCOND_GT: return "ngt";
71 }
72 llvm_unreachable("Impossible condition code!");
73}
74
75void MipsInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) {
76 markup(OS, M: Markup::Register)
77 << '$' << StringRef(getRegisterName(Reg)).lower();
78}
79
80void MipsInstPrinter::printInst(const MCInst *MI, uint64_t Address,
81 StringRef Annot, const MCSubtargetInfo &STI,
82 raw_ostream &O) {
83 switch (MI->getOpcode()) {
84 default:
85 break;
86 case Mips::RDHWR:
87 case Mips::RDHWR64:
88 O << "\t.set\tpush\n";
89 O << "\t.set\tmips32r2\n";
90 break;
91 case Mips::Save16:
92 O << "\tsave\t";
93 printSaveRestore(MI, STI, O);
94 O << " # 16 bit inst\n";
95 return;
96 case Mips::SaveX16:
97 O << "\tsave\t";
98 printSaveRestore(MI, STI, O);
99 O << "\n";
100 return;
101 case Mips::Restore16:
102 O << "\trestore\t";
103 printSaveRestore(MI, STI, O);
104 O << " # 16 bit inst\n";
105 return;
106 case Mips::RestoreX16:
107 O << "\trestore\t";
108 printSaveRestore(MI, STI, O);
109 O << "\n";
110 return;
111 }
112
113 // Try to print any aliases first.
114 if (!printAliasInstr(MI, Address, STI, OS&: O) &&
115 !printAlias(MI: *MI, Address, STI, OS&: O))
116 printInstruction(MI, Address, STI, O);
117 printAnnotation(OS&: O, Annot);
118
119 switch (MI->getOpcode()) {
120 default:
121 break;
122 case Mips::RDHWR:
123 case Mips::RDHWR64:
124 O << "\n\t.set\tpop";
125 }
126}
127
128void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
129 const MCSubtargetInfo &STI, raw_ostream &O) {
130 const MCOperand &Op = MI->getOperand(i: OpNo);
131 if (Op.isReg()) {
132 printRegName(OS&: O, Reg: Op.getReg());
133 return;
134 }
135
136 if (Op.isImm()) {
137 markup(OS&: O, M: Markup::Immediate) << formatImm(Value: Op.getImm());
138 return;
139 }
140
141 assert(Op.isExpr() && "unknown operand kind in printOperand");
142 MAI.printExpr(O, *Op.getExpr());
143}
144
145template <unsigned FromEnd>
146void MipsInstPrinter::printOperandFromEnd(const MCInst *MI, int OpNo,
147 const MCSubtargetInfo &STI,
148 raw_ostream &O) {
149 printOperand(MI, OpNo: MI->getNumOperands() - FromEnd, STI, O);
150}
151
152void MipsInstPrinter::printJumpOperand(const MCInst *MI, unsigned OpNo,
153 const MCSubtargetInfo &STI,
154 raw_ostream &O) {
155 const MCOperand &Op = MI->getOperand(i: OpNo);
156 if (!Op.isImm())
157 return printOperand(MI, OpNo, STI, O);
158
159 if (PrintBranchImmAsAddress)
160 markup(OS&: O, M: Markup::Immediate) << formatHex(Value: Op.getImm());
161 else
162 markup(OS&: O, M: Markup::Immediate) << formatImm(Value: Op.getImm());
163}
164
165void MipsInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
166 unsigned OpNo,
167 const MCSubtargetInfo &STI,
168 raw_ostream &O) {
169 const MCOperand &Op = MI->getOperand(i: OpNo);
170 if (!Op.isImm())
171 return printOperand(MI, OpNo, STI, O);
172
173 if (PrintBranchImmAsAddress) {
174 uint64_t Target = Address + Op.getImm();
175 if (STI.hasFeature(Feature: Mips::FeatureMips32))
176 Target &= 0xffffffff;
177 else if (STI.hasFeature(Feature: Mips::FeatureMips16))
178 Target &= 0xffff;
179 markup(OS&: O, M: Markup::Immediate) << formatHex(Value: Target);
180 } else {
181 markup(OS&: O, M: Markup::Immediate) << formatImm(Value: Op.getImm());
182 }
183}
184
185template <unsigned Bits, unsigned Offset>
186void MipsInstPrinter::printUImm(const MCInst *MI, int opNum,
187 const MCSubtargetInfo &STI, raw_ostream &O) {
188 const MCOperand &MO = MI->getOperand(i: opNum);
189 if (MO.isImm()) {
190 uint64_t Imm = MO.getImm();
191 Imm -= Offset;
192 Imm &= (1 << Bits) - 1;
193 Imm += Offset;
194 markup(OS&: O, M: Markup::Immediate) << formatImm(Value: Imm);
195 return;
196 }
197
198 printOperand(MI, OpNo: opNum, STI, O);
199}
200
201void MipsInstPrinter::printMemOperand(const MCInst *MI, int opNum,
202 const MCSubtargetInfo &STI,
203 raw_ostream &O) {
204 // Load/Store memory operands -- imm($reg)
205 // If PIC target the target is loaded as the
206 // pattern lw $25,%call16($28)
207
208 WithMarkup M = markup(OS&: O, M: Markup::Memory);
209 printOperand(MI, OpNo: opNum + 1, STI, O);
210 O << "(";
211 printOperand(MI, OpNo: opNum, STI, O);
212 O << ")";
213}
214
215void MipsInstPrinter::printFCCOperand(const MCInst *MI, int opNum,
216 const MCSubtargetInfo & /* STI */,
217 raw_ostream &O) {
218 const MCOperand &MO = MI->getOperand(i: opNum);
219 O << MipsFCCToString(CC: (Mips::CondCode)MO.getImm());
220}
221
222void MipsInstPrinter::
223printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) {
224 llvm_unreachable("TODO");
225}
226
227bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
228 uint64_t Address, unsigned OpNo,
229 const MCSubtargetInfo &STI, raw_ostream &OS,
230 bool IsBranch) {
231 OS << "\t" << Str << "\t";
232 if (IsBranch)
233 printBranchOperand(MI: &MI, Address, OpNo, STI, O&: OS);
234 else
235 printOperand(MI: &MI, OpNo, STI, O&: OS);
236 return true;
237}
238
239bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
240 uint64_t Address, unsigned OpNo0,
241 unsigned OpNo1, const MCSubtargetInfo &STI,
242 raw_ostream &OS, bool IsBranch) {
243 printAlias(Str, MI, Address, OpNo: OpNo0, STI, OS, IsBranch);
244 OS << ", ";
245 if (IsBranch)
246 printBranchOperand(MI: &MI, Address, OpNo: OpNo1, STI, O&: OS);
247 else
248 printOperand(MI: &MI, OpNo: OpNo1, STI, O&: OS);
249 return true;
250}
251
252bool MipsInstPrinter::printAlias(const MCInst &MI, uint64_t Address,
253 const MCSubtargetInfo &STI, raw_ostream &OS) {
254 switch (MI.getOpcode()) {
255 case Mips::BEQ:
256 case Mips::BEQ_MM:
257 // beq $zero, $zero, $L2 => b $L2
258 // beq $r0, $zero, $L2 => beqz $r0, $L2
259 return (isReg<Mips::R0>(MI, OpNo: 0) && isReg<Mips::R0>(MI, OpNo: 1) &&
260 printAlias(Str: "b", MI, Address, OpNo: 2, STI, OS, IsBranch: true)) ||
261 (isReg<Mips::R0>(MI, OpNo: 1) &&
262 printAlias(Str: "beqz", MI, Address, OpNo0: 0, OpNo1: 2, STI, OS, IsBranch: true));
263 case Mips::BEQ64:
264 // beq $r0, $zero, $L2 => beqz $r0, $L2
265 return isReg<Mips::R0_64>(MI, OpNo: 1) &&
266 printAlias(Str: "beqz", MI, Address, OpNo0: 0, OpNo1: 2, STI, OS, IsBranch: true);
267 case Mips::BNE:
268 case Mips::BNE_MM:
269 // bne $r0, $zero, $L2 => bnez $r0, $L2
270 return isReg<Mips::R0>(MI, OpNo: 1) &&
271 printAlias(Str: "bnez", MI, Address, OpNo0: 0, OpNo1: 2, STI, OS, IsBranch: true);
272 case Mips::BNE64:
273 // bne $r0, $zero, $L2 => bnez $r0, $L2
274 return isReg<Mips::R0_64>(MI, OpNo: 1) &&
275 printAlias(Str: "bnez", MI, Address, OpNo0: 0, OpNo1: 2, STI, OS, IsBranch: true);
276 case Mips::BGEZAL:
277 // bgezal $zero, $L1 => bal $L1
278 return isReg<Mips::R0>(MI, OpNo: 0) &&
279 printAlias(Str: "bal", MI, Address, OpNo: 1, STI, OS, IsBranch: true);
280 case Mips::BC1T:
281 // bc1t $fcc0, $L1 => bc1t $L1
282 return isReg<Mips::FCC0>(MI, OpNo: 0) &&
283 printAlias(Str: "bc1t", MI, Address, OpNo: 1, STI, OS, IsBranch: true);
284 case Mips::BC1F:
285 // bc1f $fcc0, $L1 => bc1f $L1
286 return isReg<Mips::FCC0>(MI, OpNo: 0) &&
287 printAlias(Str: "bc1f", MI, Address, OpNo: 1, STI, OS, IsBranch: true);
288 case Mips::JALR:
289 // jalr $zero, $r1 => jr $r1
290 // jalr $ra, $r1 => jalr $r1
291 return (isReg<Mips::R0>(MI, OpNo: 0) &&
292 printAlias(Str: "jr", MI, Address, OpNo: 1, STI, OS)) ||
293 (isReg<Mips::RA>(MI, OpNo: 0) &&
294 printAlias(Str: "jalr", MI, Address, OpNo: 1, STI, OS));
295 case Mips::JALR64:
296 // jalr $zero, $r1 => jr $r1
297 // jalr $ra, $r1 => jalr $r1
298 return (isReg<Mips::R0_64>(MI, OpNo: 0) &&
299 printAlias(Str: "jr", MI, Address, OpNo: 1, STI, OS)) ||
300 (isReg<Mips::RA_64>(MI, OpNo: 0) &&
301 printAlias(Str: "jalr", MI, Address, OpNo: 1, STI, OS));
302 case Mips::NOR:
303 case Mips::NOR_MM:
304 case Mips::NOR_MMR6:
305 // nor $r0, $r1, $zero => not $r0, $r1
306 return isReg<Mips::R0>(MI, OpNo: 2) &&
307 printAlias(Str: "not", MI, Address, OpNo0: 0, OpNo1: 1, STI, OS);
308 case Mips::NOR64:
309 // nor $r0, $r1, $zero => not $r0, $r1
310 return isReg<Mips::R0_64>(MI, OpNo: 2) &&
311 printAlias(Str: "not", MI, Address, OpNo0: 0, OpNo1: 1, STI, OS);
312 case Mips::OR:
313 case Mips::ADDu:
314 // or $r0, $r1, $zero => move $r0, $r1
315 // addu $r0, $r1, $zero => move $r0, $r1
316 return isReg<Mips::R0>(MI, OpNo: 2) &&
317 printAlias(Str: "move", MI, Address, OpNo0: 0, OpNo1: 1, STI, OS);
318 default:
319 return false;
320 }
321}
322
323void MipsInstPrinter::printSaveRestore(const MCInst *MI,
324 const MCSubtargetInfo &STI,
325 raw_ostream &O) {
326 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
327 if (i != 0) O << ", ";
328 if (MI->getOperand(i).isReg())
329 printRegName(OS&: O, Reg: MI->getOperand(i).getReg());
330 else
331 printUImm<16>(MI, opNum: i, STI, O);
332 }
333}
334
335void MipsInstPrinter::printRegisterList(const MCInst *MI, int opNum,
336 const MCSubtargetInfo & /* STI */,
337 raw_ostream &O) {
338 // - 2 because register List is always first operand of instruction and it is
339 // always followed by memory operand (base + offset).
340 for (int i = opNum, e = MI->getNumOperands() - 2; i != e; ++i) {
341 if (i != opNum)
342 O << ", ";
343 printRegName(OS&: O, Reg: MI->getOperand(i).getReg());
344 }
345}
346