1//===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides Mips specific target streamer methods.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MipsTargetStreamer.h"
14#include "MCTargetDesc/MipsABIInfo.h"
15#include "MCTargetDesc/MipsMCAsmInfo.h"
16#include "MipsBaseInfo.h"
17#include "MipsELFStreamer.h"
18#include "MipsInstPrinter.h"
19#include "MipsMCTargetDesc.h"
20#include "llvm/BinaryFormat/ELF.h"
21#include "llvm/MC/MCAsmInfo.h"
22#include "llvm/MC/MCAssembler.h"
23#include "llvm/MC/MCContext.h"
24#include "llvm/MC/MCELFObjectWriter.h"
25#include "llvm/MC/MCObjectFileInfo.h"
26#include "llvm/MC/MCSectionELF.h"
27#include "llvm/MC/MCSubtargetInfo.h"
28#include "llvm/MC/MCSymbolELF.h"
29#include "llvm/Support/ErrorHandling.h"
30#include "llvm/Support/FormattedStream.h"
31
32using namespace llvm;
33
34static bool isMicroMips(const MCSubtargetInfo *STI) {
35 return STI->hasFeature(Feature: Mips::FeatureMicroMips);
36}
37
38static bool isMips32r6(const MCSubtargetInfo *STI) {
39 return STI->hasFeature(Feature: Mips::FeatureMips32r6);
40}
41
42MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
43 : MCTargetStreamer(S), GPReg(Mips::GP), ModuleDirectiveAllowed(true) {
44 GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
45}
46
47void MipsTargetStreamer::emitGPRel32Value(const MCExpr *) {}
48void MipsTargetStreamer::emitGPRel64Value(const MCExpr *) {}
49void MipsTargetStreamer::emitDTPRel32Value(const MCExpr *) {}
50void MipsTargetStreamer::emitDTPRel64Value(const MCExpr *) {}
51void MipsTargetStreamer::emitTPRel32Value(const MCExpr *) {}
52void MipsTargetStreamer::emitTPRel64Value(const MCExpr *) {}
53void MipsTargetStreamer::emitDirectiveSetMicroMips() {}
54void MipsTargetStreamer::emitDirectiveSetNoMicroMips() {}
55void MipsTargetStreamer::setUsesMicroMips() {}
56void MipsTargetStreamer::emitDirectiveSetMips16() {}
57void MipsTargetStreamer::emitDirectiveSetNoMips16() { forbidModuleDirective(); }
58void MipsTargetStreamer::emitDirectiveSetReorder() { forbidModuleDirective(); }
59void MipsTargetStreamer::emitDirectiveSetNoReorder() {}
60void MipsTargetStreamer::emitDirectiveSetMacro() { forbidModuleDirective(); }
61void MipsTargetStreamer::emitDirectiveSetNoMacro() { forbidModuleDirective(); }
62void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); }
63void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); }
64void MipsTargetStreamer::emitDirectiveSetMt() {}
65void MipsTargetStreamer::emitDirectiveSetNoMt() { forbidModuleDirective(); }
66void MipsTargetStreamer::emitDirectiveSetCRC() {}
67void MipsTargetStreamer::emitDirectiveSetNoCRC() {}
68void MipsTargetStreamer::emitDirectiveSetVirt() {}
69void MipsTargetStreamer::emitDirectiveSetNoVirt() {}
70void MipsTargetStreamer::emitDirectiveSetGINV() {}
71void MipsTargetStreamer::emitDirectiveSetNoGINV() {}
72void MipsTargetStreamer::emitDirectiveSetEVA() {}
73void MipsTargetStreamer::emitDirectiveSetNoEVA() {}
74void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
75void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
76 forbidModuleDirective();
77}
78void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); }
79void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {}
80void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {}
81void MipsTargetStreamer::emitDirectiveAbiCalls() {}
82void MipsTargetStreamer::emitDirectiveNaN2008() {}
83void MipsTargetStreamer::emitDirectiveNaNLegacy() {}
84void MipsTargetStreamer::emitDirectiveOptionPic0() {}
85void MipsTargetStreamer::emitDirectiveOptionPic2() {}
86void MipsTargetStreamer::emitDirectiveInsn() { forbidModuleDirective(); }
87void MipsTargetStreamer::emitFrame(MCRegister StackReg, unsigned StackSize,
88 MCRegister ReturnReg) {}
89void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
90void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
91}
92void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
93 forbidModuleDirective();
94}
95void MipsTargetStreamer::emitDirectiveSetMips0() { forbidModuleDirective(); }
96void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
97void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
98void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
99void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
100void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
101void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
102void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
103void MipsTargetStreamer::emitDirectiveSetMips32R3() { forbidModuleDirective(); }
104void MipsTargetStreamer::emitDirectiveSetMips32R5() { forbidModuleDirective(); }
105void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
106void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); }
107void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); }
108void MipsTargetStreamer::emitDirectiveSetMips64R3() { forbidModuleDirective(); }
109void MipsTargetStreamer::emitDirectiveSetMips64R5() { forbidModuleDirective(); }
110void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); }
111void MipsTargetStreamer::emitDirectiveSetPop() { forbidModuleDirective(); }
112void MipsTargetStreamer::emitDirectiveSetPush() { forbidModuleDirective(); }
113void MipsTargetStreamer::emitDirectiveSetSoftFloat() {
114 forbidModuleDirective();
115}
116void MipsTargetStreamer::emitDirectiveSetHardFloat() {
117 forbidModuleDirective();
118}
119void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
120void MipsTargetStreamer::emitDirectiveSetDspr2() { forbidModuleDirective(); }
121void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
122void MipsTargetStreamer::emitDirectiveSetMips3D() { forbidModuleDirective(); }
123void MipsTargetStreamer::emitDirectiveSetNoMips3D() { forbidModuleDirective(); }
124void MipsTargetStreamer::emitDirectiveCpAdd(MCRegister Reg) {}
125void MipsTargetStreamer::emitDirectiveCpLoad(MCRegister Reg) {}
126void MipsTargetStreamer::emitDirectiveCpLocal(MCRegister Reg) {
127 // .cplocal $reg
128 // This directive forces to use the alternate register for context pointer.
129 // For example
130 // .cplocal $4
131 // jal foo
132 // expands to
133 // ld $25, %call16(foo)($4)
134 // jalr $25
135
136 if (!getABI().IsN32() && !getABI().IsN64())
137 return;
138
139 GPReg = Reg;
140
141 forbidModuleDirective();
142}
143bool MipsTargetStreamer::emitDirectiveCpRestore(
144 int Offset, function_ref<MCRegister()> GetATReg, SMLoc IDLoc,
145 const MCSubtargetInfo *STI) {
146 forbidModuleDirective();
147 return true;
148}
149void MipsTargetStreamer::emitDirectiveCpsetup(MCRegister Reg, int RegOrOffset,
150 const MCSymbol &Sym, bool IsReg) {
151}
152void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
153 bool SaveLocationIsRegister) {}
154
155void MipsTargetStreamer::emitDirectiveModuleFP() {}
156
157void MipsTargetStreamer::emitDirectiveModuleOddSPReg() {
158 if (!ABIFlagsSection.OddSPReg && !ABIFlagsSection.Is32BitABI)
159 report_fatal_error(reason: "+nooddspreg is only valid for O32");
160}
161void MipsTargetStreamer::emitDirectiveModuleSoftFloat() {}
162void MipsTargetStreamer::emitDirectiveModuleHardFloat() {}
163void MipsTargetStreamer::emitDirectiveModuleMT() {}
164void MipsTargetStreamer::emitDirectiveModuleCRC() {}
165void MipsTargetStreamer::emitDirectiveModuleNoCRC() {}
166void MipsTargetStreamer::emitDirectiveModuleVirt() {}
167void MipsTargetStreamer::emitDirectiveModuleNoVirt() {}
168void MipsTargetStreamer::emitDirectiveModuleGINV() {}
169void MipsTargetStreamer::emitDirectiveModuleNoGINV() {}
170void MipsTargetStreamer::emitDirectiveSetFp(
171 MipsABIFlagsSection::FpABIKind Value) {
172 forbidModuleDirective();
173}
174void MipsTargetStreamer::emitDirectiveSetOddSPReg() { forbidModuleDirective(); }
175void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
176 forbidModuleDirective();
177}
178
179void MipsTargetStreamer::emitR(unsigned Opcode, MCRegister Reg0, SMLoc IDLoc,
180 const MCSubtargetInfo *STI) {
181 MCInst TmpInst;
182 TmpInst.setOpcode(Opcode);
183 TmpInst.addOperand(Op: MCOperand::createReg(Reg: Reg0));
184 TmpInst.setLoc(IDLoc);
185 getStreamer().emitInstruction(Inst: TmpInst, STI: *STI);
186}
187
188void MipsTargetStreamer::emitRX(unsigned Opcode, MCRegister Reg0, MCOperand Op1,
189 SMLoc IDLoc, const MCSubtargetInfo *STI) {
190 MCInst TmpInst;
191 TmpInst.setOpcode(Opcode);
192 TmpInst.addOperand(Op: MCOperand::createReg(Reg: Reg0));
193 TmpInst.addOperand(Op: Op1);
194 TmpInst.setLoc(IDLoc);
195 getStreamer().emitInstruction(Inst: TmpInst, STI: *STI);
196}
197
198void MipsTargetStreamer::emitRI(unsigned Opcode, MCRegister Reg0, int32_t Imm,
199 SMLoc IDLoc, const MCSubtargetInfo *STI) {
200 emitRX(Opcode, Reg0, Op1: MCOperand::createImm(Val: Imm), IDLoc, STI);
201}
202
203void MipsTargetStreamer::emitRR(unsigned Opcode, MCRegister Reg0,
204 MCRegister Reg1, SMLoc IDLoc,
205 const MCSubtargetInfo *STI) {
206 emitRX(Opcode, Reg0, Op1: MCOperand::createReg(Reg: Reg1), IDLoc, STI);
207}
208
209void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
210 SMLoc IDLoc, const MCSubtargetInfo *STI) {
211 MCInst TmpInst;
212 TmpInst.setOpcode(Opcode);
213 TmpInst.addOperand(Op: MCOperand::createImm(Val: Imm1));
214 TmpInst.addOperand(Op: MCOperand::createImm(Val: Imm2));
215 TmpInst.setLoc(IDLoc);
216 getStreamer().emitInstruction(Inst: TmpInst, STI: *STI);
217}
218
219void MipsTargetStreamer::emitRRX(unsigned Opcode, MCRegister Reg0,
220 MCRegister Reg1, MCOperand Op2, SMLoc IDLoc,
221 const MCSubtargetInfo *STI) {
222 MCInst TmpInst;
223 TmpInst.setOpcode(Opcode);
224 TmpInst.addOperand(Op: MCOperand::createReg(Reg: Reg0));
225 TmpInst.addOperand(Op: MCOperand::createReg(Reg: Reg1));
226 TmpInst.addOperand(Op: Op2);
227 TmpInst.setLoc(IDLoc);
228 getStreamer().emitInstruction(Inst: TmpInst, STI: *STI);
229}
230
231void MipsTargetStreamer::emitRRR(unsigned Opcode, MCRegister Reg0,
232 MCRegister Reg1, MCRegister Reg2, SMLoc IDLoc,
233 const MCSubtargetInfo *STI) {
234 emitRRX(Opcode, Reg0, Reg1, Op2: MCOperand::createReg(Reg: Reg2), IDLoc, STI);
235}
236
237void MipsTargetStreamer::emitRRRX(unsigned Opcode, MCRegister Reg0,
238 MCRegister Reg1, MCRegister Reg2,
239 MCOperand Op3, SMLoc IDLoc,
240 const MCSubtargetInfo *STI) {
241 MCInst TmpInst;
242 TmpInst.setOpcode(Opcode);
243 TmpInst.addOperand(Op: MCOperand::createReg(Reg: Reg0));
244 TmpInst.addOperand(Op: MCOperand::createReg(Reg: Reg1));
245 TmpInst.addOperand(Op: MCOperand::createReg(Reg: Reg2));
246 TmpInst.addOperand(Op: Op3);
247 TmpInst.setLoc(IDLoc);
248 getStreamer().emitInstruction(Inst: TmpInst, STI: *STI);
249}
250
251void MipsTargetStreamer::emitRRI(unsigned Opcode, MCRegister Reg0,
252 MCRegister Reg1, int16_t Imm, SMLoc IDLoc,
253 const MCSubtargetInfo *STI) {
254 emitRRX(Opcode, Reg0, Reg1, Op2: MCOperand::createImm(Val: Imm), IDLoc, STI);
255}
256
257void MipsTargetStreamer::emitRRIII(unsigned Opcode, MCRegister Reg0,
258 MCRegister Reg1, int16_t Imm0, int16_t Imm1,
259 int16_t Imm2, SMLoc IDLoc,
260 const MCSubtargetInfo *STI) {
261 MCInst TmpInst;
262 TmpInst.setOpcode(Opcode);
263 TmpInst.addOperand(Op: MCOperand::createReg(Reg: Reg0));
264 TmpInst.addOperand(Op: MCOperand::createReg(Reg: Reg1));
265 TmpInst.addOperand(Op: MCOperand::createImm(Val: Imm0));
266 TmpInst.addOperand(Op: MCOperand::createImm(Val: Imm1));
267 TmpInst.addOperand(Op: MCOperand::createImm(Val: Imm2));
268 TmpInst.setLoc(IDLoc);
269 getStreamer().emitInstruction(Inst: TmpInst, STI: *STI);
270}
271
272void MipsTargetStreamer::emitAddu(MCRegister DstReg, MCRegister SrcReg,
273 MCRegister TrgReg, bool Is64Bit,
274 const MCSubtargetInfo *STI) {
275 emitRRR(Opcode: Is64Bit ? Mips::DADDu : Mips::ADDu, Reg0: DstReg, Reg1: SrcReg, Reg2: TrgReg, IDLoc: SMLoc(),
276 STI);
277}
278
279void MipsTargetStreamer::emitDSLL(MCRegister DstReg, MCRegister SrcReg,
280 int16_t ShiftAmount, SMLoc IDLoc,
281 const MCSubtargetInfo *STI) {
282 if (ShiftAmount >= 32) {
283 emitRRI(Opcode: Mips::DSLL32, Reg0: DstReg, Reg1: SrcReg, Imm: ShiftAmount - 32, IDLoc, STI);
284 return;
285 }
286
287 emitRRI(Opcode: Mips::DSLL, Reg0: DstReg, Reg1: SrcReg, Imm: ShiftAmount, IDLoc, STI);
288}
289
290void MipsTargetStreamer::emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc,
291 const MCSubtargetInfo *STI) {
292 // The default case of `nop` is `sll $zero, $zero, 0`.
293 unsigned Opc = Mips::SLL;
294 if (isMicroMips(STI) && hasShortDelaySlot) {
295 Opc = isMips32r6(STI) ? Mips::MOVE16_MMR6 : Mips::MOVE16_MM;
296 emitRR(Opcode: Opc, Reg0: Mips::R0, Reg1: Mips::R0, IDLoc, STI);
297 return;
298 }
299
300 if (isMicroMips(STI))
301 Opc = isMips32r6(STI) ? Mips::SLL_MMR6 : Mips::SLL_MM;
302
303 emitRRI(Opcode: Opc, Reg0: Mips::R0, Reg1: Mips::R0, Imm: 0, IDLoc, STI);
304}
305
306void MipsTargetStreamer::emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) {
307 if (isMicroMips(STI))
308 emitRR(Opcode: Mips::MOVE16_MM, Reg0: Mips::R0, Reg1: Mips::R0, IDLoc, STI);
309 else
310 emitRRI(Opcode: Mips::SLL, Reg0: Mips::R0, Reg1: Mips::R0, Imm: 0, IDLoc, STI);
311}
312
313/// Emit the $gp restore operation for .cprestore.
314void MipsTargetStreamer::emitGPRestore(int Offset, SMLoc IDLoc,
315 const MCSubtargetInfo *STI) {
316 emitLoadWithImmOffset(Opcode: Mips::LW, DstReg: GPReg, BaseReg: Mips::SP, Offset, TmpReg: GPReg, IDLoc, STI);
317}
318
319/// Emit a store instruction with an immediate offset.
320void MipsTargetStreamer::emitStoreWithImmOffset(
321 unsigned Opcode, MCRegister SrcReg, MCRegister BaseReg, int64_t Offset,
322 function_ref<MCRegister()> GetATReg, SMLoc IDLoc,
323 const MCSubtargetInfo *STI) {
324 if (isInt<16>(x: Offset)) {
325 emitRRI(Opcode, Reg0: SrcReg, Reg1: BaseReg, Imm: Offset, IDLoc, STI);
326 return;
327 }
328
329 // sw $8, offset($8) => lui $at, %hi(offset)
330 // add $at, $at, $8
331 // sw $8, %lo(offset)($at)
332
333 MCRegister ATReg = GetATReg();
334 if (!ATReg)
335 return;
336
337 unsigned LoOffset = Offset & 0x0000ffff;
338 unsigned HiOffset = (Offset & 0xffff0000) >> 16;
339
340 // If msb of LoOffset is 1(negative number) we must increment HiOffset
341 // to account for the sign-extension of the low part.
342 if (LoOffset & 0x8000)
343 HiOffset++;
344
345 // Generate the base address in ATReg.
346 emitRI(Opcode: Mips::LUi, Reg0: ATReg, Imm: HiOffset, IDLoc, STI);
347 if (BaseReg != Mips::R0)
348 emitRRR(Opcode: Mips::ADDu, Reg0: ATReg, Reg1: ATReg, Reg2: BaseReg, IDLoc, STI);
349 // Emit the store with the adjusted base and offset.
350 emitRRI(Opcode, Reg0: SrcReg, Reg1: ATReg, Imm: LoOffset, IDLoc, STI);
351}
352
353/// Emit a load instruction with an immediate offset. DstReg and TmpReg are
354/// permitted to be the same register iff DstReg is distinct from BaseReg and
355/// DstReg is a GPR. It is the callers responsibility to identify such cases
356/// and pass the appropriate register in TmpReg.
357void MipsTargetStreamer::emitLoadWithImmOffset(
358 unsigned Opcode, MCRegister DstReg, MCRegister BaseReg, int64_t Offset,
359 MCRegister TmpReg, SMLoc IDLoc, const MCSubtargetInfo *STI) {
360 if (isInt<16>(x: Offset)) {
361 emitRRI(Opcode, Reg0: DstReg, Reg1: BaseReg, Imm: Offset, IDLoc, STI);
362 return;
363 }
364
365 // 1) lw $8, offset($9) => lui $8, %hi(offset)
366 // add $8, $8, $9
367 // lw $8, %lo(offset)($9)
368 // 2) lw $8, offset($8) => lui $at, %hi(offset)
369 // add $at, $at, $8
370 // lw $8, %lo(offset)($at)
371
372 unsigned LoOffset = Offset & 0x0000ffff;
373 unsigned HiOffset = (Offset & 0xffff0000) >> 16;
374
375 // If msb of LoOffset is 1(negative number) we must increment HiOffset
376 // to account for the sign-extension of the low part.
377 if (LoOffset & 0x8000)
378 HiOffset++;
379
380 // Generate the base address in TmpReg.
381 emitRI(Opcode: Mips::LUi, Reg0: TmpReg, Imm: HiOffset, IDLoc, STI);
382 if (BaseReg != Mips::R0)
383 emitRRR(Opcode: Mips::ADDu, Reg0: TmpReg, Reg1: TmpReg, Reg2: BaseReg, IDLoc, STI);
384 // Emit the load with the adjusted base and offset.
385 emitRRI(Opcode, Reg0: DstReg, Reg1: TmpReg, Imm: LoOffset, IDLoc, STI);
386}
387
388MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S,
389 formatted_raw_ostream &OS)
390 : MipsTargetStreamer(S), OS(OS) {}
391
392void MipsTargetAsmStreamer::emitDTPRel32Value(const MCExpr *Value) {
393 auto &MAI = getStreamer().getContext().getAsmInfo();
394 OS << "\t.dtprelword\t";
395 MAI.printExpr(OS, *Value);
396 OS << '\n';
397}
398
399void MipsTargetAsmStreamer::emitDTPRel64Value(const MCExpr *Value) {
400 auto &MAI = getStreamer().getContext().getAsmInfo();
401 OS << "\t.dtpreldword\t";
402 MAI.printExpr(OS, *Value);
403 OS << '\n';
404}
405
406void MipsTargetAsmStreamer::emitTPRel32Value(const MCExpr *Value) {
407 auto &MAI = getStreamer().getContext().getAsmInfo();
408 OS << "\t.tprelword\t";
409 MAI.printExpr(OS, *Value);
410 OS << '\n';
411}
412
413void MipsTargetAsmStreamer::emitTPRel64Value(const MCExpr *Value) {
414 auto &MAI = getStreamer().getContext().getAsmInfo();
415 OS << "\t.tpreldword\t";
416 MAI.printExpr(OS, *Value);
417 OS << '\n';
418}
419
420void MipsTargetAsmStreamer::emitGPRel32Value(const MCExpr *Value) {
421 auto &MAI = getStreamer().getContext().getAsmInfo();
422 OS << "\t.gpword\t";
423 MAI.printExpr(OS, *Value);
424 OS << '\n';
425}
426
427void MipsTargetAsmStreamer::emitGPRel64Value(const MCExpr *Value) {
428 auto &MAI = getStreamer().getContext().getAsmInfo();
429 OS << "\t.gpdword\t";
430 MAI.printExpr(OS, *Value);
431 OS << '\n';
432}
433
434void MipsTargetAsmStreamer::emitDirectiveSetMicroMips() {
435 OS << "\t.set\tmicromips\n";
436 forbidModuleDirective();
437}
438
439void MipsTargetAsmStreamer::emitDirectiveSetNoMicroMips() {
440 OS << "\t.set\tnomicromips\n";
441 forbidModuleDirective();
442}
443
444void MipsTargetAsmStreamer::emitDirectiveSetMips16() {
445 OS << "\t.set\tmips16\n";
446 forbidModuleDirective();
447}
448
449void MipsTargetAsmStreamer::emitDirectiveSetNoMips16() {
450 OS << "\t.set\tnomips16\n";
451 MipsTargetStreamer::emitDirectiveSetNoMips16();
452}
453
454void MipsTargetAsmStreamer::emitDirectiveSetReorder() {
455 OS << "\t.set\treorder\n";
456 MipsTargetStreamer::emitDirectiveSetReorder();
457}
458
459void MipsTargetAsmStreamer::emitDirectiveSetNoReorder() {
460 OS << "\t.set\tnoreorder\n";
461 forbidModuleDirective();
462}
463
464void MipsTargetAsmStreamer::emitDirectiveSetMacro() {
465 OS << "\t.set\tmacro\n";
466 MipsTargetStreamer::emitDirectiveSetMacro();
467}
468
469void MipsTargetAsmStreamer::emitDirectiveSetNoMacro() {
470 OS << "\t.set\tnomacro\n";
471 MipsTargetStreamer::emitDirectiveSetNoMacro();
472}
473
474void MipsTargetAsmStreamer::emitDirectiveSetMsa() {
475 OS << "\t.set\tmsa\n";
476 MipsTargetStreamer::emitDirectiveSetMsa();
477}
478
479void MipsTargetAsmStreamer::emitDirectiveSetNoMsa() {
480 OS << "\t.set\tnomsa\n";
481 MipsTargetStreamer::emitDirectiveSetNoMsa();
482}
483
484void MipsTargetAsmStreamer::emitDirectiveSetMt() {
485 OS << "\t.set\tmt\n";
486 MipsTargetStreamer::emitDirectiveSetMt();
487}
488
489void MipsTargetAsmStreamer::emitDirectiveSetNoMt() {
490 OS << "\t.set\tnomt\n";
491 MipsTargetStreamer::emitDirectiveSetNoMt();
492}
493
494void MipsTargetAsmStreamer::emitDirectiveSetCRC() {
495 OS << "\t.set\tcrc\n";
496 MipsTargetStreamer::emitDirectiveSetCRC();
497}
498
499void MipsTargetAsmStreamer::emitDirectiveSetNoCRC() {
500 OS << "\t.set\tnocrc\n";
501 MipsTargetStreamer::emitDirectiveSetNoCRC();
502}
503
504void MipsTargetAsmStreamer::emitDirectiveSetVirt() {
505 OS << "\t.set\tvirt\n";
506 MipsTargetStreamer::emitDirectiveSetVirt();
507}
508
509void MipsTargetAsmStreamer::emitDirectiveSetNoVirt() {
510 OS << "\t.set\tnovirt\n";
511 MipsTargetStreamer::emitDirectiveSetNoVirt();
512}
513
514void MipsTargetAsmStreamer::emitDirectiveSetGINV() {
515 OS << "\t.set\tginv\n";
516 MipsTargetStreamer::emitDirectiveSetGINV();
517}
518
519void MipsTargetAsmStreamer::emitDirectiveSetNoGINV() {
520 OS << "\t.set\tnoginv\n";
521 MipsTargetStreamer::emitDirectiveSetNoGINV();
522}
523
524void MipsTargetAsmStreamer::emitDirectiveSetEVA() {
525 OS << "\t.set\teva\n";
526 MipsTargetStreamer::emitDirectiveSetEVA();
527}
528
529void MipsTargetAsmStreamer::emitDirectiveSetNoEVA() {
530 OS << "\t.set\tnoeva\n";
531 MipsTargetStreamer::emitDirectiveSetNoEVA();
532}
533
534void MipsTargetAsmStreamer::emitDirectiveSetAt() {
535 OS << "\t.set\tat\n";
536 MipsTargetStreamer::emitDirectiveSetAt();
537}
538
539void MipsTargetAsmStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
540 OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
541 MipsTargetStreamer::emitDirectiveSetAtWithArg(RegNo);
542}
543
544void MipsTargetAsmStreamer::emitDirectiveSetNoAt() {
545 OS << "\t.set\tnoat\n";
546 MipsTargetStreamer::emitDirectiveSetNoAt();
547}
548
549void MipsTargetAsmStreamer::emitDirectiveEnd(StringRef Name) {
550 OS << "\t.end\t" << Name << '\n';
551}
552
553void MipsTargetAsmStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
554 OS << "\t.ent\t" << Symbol.getName() << '\n';
555}
556
557void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
558
559void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
560
561void MipsTargetAsmStreamer::emitDirectiveNaNLegacy() {
562 OS << "\t.nan\tlegacy\n";
563}
564
565void MipsTargetAsmStreamer::emitDirectiveOptionPic0() {
566 OS << "\t.option\tpic0\n";
567}
568
569void MipsTargetAsmStreamer::emitDirectiveOptionPic2() {
570 OS << "\t.option\tpic2\n";
571}
572
573void MipsTargetAsmStreamer::emitDirectiveInsn() {
574 MipsTargetStreamer::emitDirectiveInsn();
575 OS << "\t.insn\n";
576}
577
578void MipsTargetAsmStreamer::emitFrame(MCRegister StackReg, unsigned StackSize,
579 MCRegister ReturnReg) {
580 OS << "\t.frame\t$"
581 << StringRef(MipsInstPrinter::getRegisterName(Reg: StackReg)).lower() << ","
582 << StackSize << ",$"
583 << StringRef(MipsInstPrinter::getRegisterName(Reg: ReturnReg)).lower() << '\n';
584}
585
586void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
587 OS << "\t.set arch=" << Arch << "\n";
588 MipsTargetStreamer::emitDirectiveSetArch(Arch);
589}
590
591void MipsTargetAsmStreamer::emitDirectiveSetMips0() {
592 OS << "\t.set\tmips0\n";
593 MipsTargetStreamer::emitDirectiveSetMips0();
594}
595
596void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
597 OS << "\t.set\tmips1\n";
598 MipsTargetStreamer::emitDirectiveSetMips1();
599}
600
601void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
602 OS << "\t.set\tmips2\n";
603 MipsTargetStreamer::emitDirectiveSetMips2();
604}
605
606void MipsTargetAsmStreamer::emitDirectiveSetMips3() {
607 OS << "\t.set\tmips3\n";
608 MipsTargetStreamer::emitDirectiveSetMips3();
609}
610
611void MipsTargetAsmStreamer::emitDirectiveSetMips4() {
612 OS << "\t.set\tmips4\n";
613 MipsTargetStreamer::emitDirectiveSetMips4();
614}
615
616void MipsTargetAsmStreamer::emitDirectiveSetMips5() {
617 OS << "\t.set\tmips5\n";
618 MipsTargetStreamer::emitDirectiveSetMips5();
619}
620
621void MipsTargetAsmStreamer::emitDirectiveSetMips32() {
622 OS << "\t.set\tmips32\n";
623 MipsTargetStreamer::emitDirectiveSetMips32();
624}
625
626void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
627 OS << "\t.set\tmips32r2\n";
628 MipsTargetStreamer::emitDirectiveSetMips32R2();
629}
630
631void MipsTargetAsmStreamer::emitDirectiveSetMips32R3() {
632 OS << "\t.set\tmips32r3\n";
633 MipsTargetStreamer::emitDirectiveSetMips32R3();
634}
635
636void MipsTargetAsmStreamer::emitDirectiveSetMips32R5() {
637 OS << "\t.set\tmips32r5\n";
638 MipsTargetStreamer::emitDirectiveSetMips32R5();
639}
640
641void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() {
642 OS << "\t.set\tmips32r6\n";
643 MipsTargetStreamer::emitDirectiveSetMips32R6();
644}
645
646void MipsTargetAsmStreamer::emitDirectiveSetMips64() {
647 OS << "\t.set\tmips64\n";
648 MipsTargetStreamer::emitDirectiveSetMips64();
649}
650
651void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
652 OS << "\t.set\tmips64r2\n";
653 MipsTargetStreamer::emitDirectiveSetMips64R2();
654}
655
656void MipsTargetAsmStreamer::emitDirectiveSetMips64R3() {
657 OS << "\t.set\tmips64r3\n";
658 MipsTargetStreamer::emitDirectiveSetMips64R3();
659}
660
661void MipsTargetAsmStreamer::emitDirectiveSetMips64R5() {
662 OS << "\t.set\tmips64r5\n";
663 MipsTargetStreamer::emitDirectiveSetMips64R5();
664}
665
666void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() {
667 OS << "\t.set\tmips64r6\n";
668 MipsTargetStreamer::emitDirectiveSetMips64R6();
669}
670
671void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
672 OS << "\t.set\tdsp\n";
673 MipsTargetStreamer::emitDirectiveSetDsp();
674}
675
676void MipsTargetAsmStreamer::emitDirectiveSetDspr2() {
677 OS << "\t.set\tdspr2\n";
678 MipsTargetStreamer::emitDirectiveSetDspr2();
679}
680
681void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
682 OS << "\t.set\tnodsp\n";
683 MipsTargetStreamer::emitDirectiveSetNoDsp();
684}
685
686void MipsTargetAsmStreamer::emitDirectiveSetMips3D() {
687 OS << "\t.set\tmips3d\n";
688 MipsTargetStreamer::emitDirectiveSetMips3D();
689}
690
691void MipsTargetAsmStreamer::emitDirectiveSetNoMips3D() {
692 OS << "\t.set\tnomips3d\n";
693 MipsTargetStreamer::emitDirectiveSetNoMips3D();
694}
695
696void MipsTargetAsmStreamer::emitDirectiveSetPop() {
697 OS << "\t.set\tpop\n";
698 MipsTargetStreamer::emitDirectiveSetPop();
699}
700
701void MipsTargetAsmStreamer::emitDirectiveSetPush() {
702 OS << "\t.set\tpush\n";
703 MipsTargetStreamer::emitDirectiveSetPush();
704}
705
706void MipsTargetAsmStreamer::emitDirectiveSetSoftFloat() {
707 OS << "\t.set\tsoftfloat\n";
708 MipsTargetStreamer::emitDirectiveSetSoftFloat();
709}
710
711void MipsTargetAsmStreamer::emitDirectiveSetHardFloat() {
712 OS << "\t.set\thardfloat\n";
713 MipsTargetStreamer::emitDirectiveSetHardFloat();
714}
715
716// Print a 32 bit hex number with all numbers.
717static void printHex32(unsigned Value, raw_ostream &OS) {
718 OS << "0x";
719 for (int i = 7; i >= 0; i--)
720 OS.write_hex(N: (Value & (0xF << (i * 4))) >> (i * 4));
721}
722
723void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
724 int CPUTopSavedRegOff) {
725 OS << "\t.mask \t";
726 printHex32(Value: CPUBitmask, OS);
727 OS << ',' << CPUTopSavedRegOff << '\n';
728}
729
730void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
731 int FPUTopSavedRegOff) {
732 OS << "\t.fmask\t";
733 printHex32(Value: FPUBitmask, OS);
734 OS << "," << FPUTopSavedRegOff << '\n';
735}
736
737void MipsTargetAsmStreamer::emitDirectiveCpAdd(MCRegister Reg) {
738 OS << "\t.cpadd\t$"
739 << StringRef(MipsInstPrinter::getRegisterName(Reg)).lower() << "\n";
740 forbidModuleDirective();
741}
742
743void MipsTargetAsmStreamer::emitDirectiveCpLoad(MCRegister Reg) {
744 OS << "\t.cpload\t$"
745 << StringRef(MipsInstPrinter::getRegisterName(Reg)).lower() << "\n";
746 forbidModuleDirective();
747}
748
749void MipsTargetAsmStreamer::emitDirectiveCpLocal(MCRegister Reg) {
750 OS << "\t.cplocal\t$"
751 << StringRef(MipsInstPrinter::getRegisterName(Reg)).lower() << "\n";
752 MipsTargetStreamer::emitDirectiveCpLocal(Reg);
753}
754
755bool MipsTargetAsmStreamer::emitDirectiveCpRestore(
756 int Offset, function_ref<MCRegister()> GetATReg, SMLoc IDLoc,
757 const MCSubtargetInfo *STI) {
758 MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
759 OS << "\t.cprestore\t" << Offset << "\n";
760 return true;
761}
762
763void MipsTargetAsmStreamer::emitDirectiveCpsetup(MCRegister Reg,
764 int RegOrOffset,
765 const MCSymbol &Sym,
766 bool IsReg) {
767 OS << "\t.cpsetup\t$"
768 << StringRef(MipsInstPrinter::getRegisterName(Reg)).lower() << ", ";
769
770 if (IsReg)
771 OS << "$"
772 << StringRef(MipsInstPrinter::getRegisterName(Reg: RegOrOffset)).lower();
773 else
774 OS << RegOrOffset;
775
776 OS << ", ";
777
778 OS << Sym.getName();
779 forbidModuleDirective();
780}
781
782void MipsTargetAsmStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
783 bool SaveLocationIsRegister) {
784 OS << "\t.cpreturn";
785 forbidModuleDirective();
786}
787
788void MipsTargetAsmStreamer::emitDirectiveModuleFP() {
789 MipsABIFlagsSection::FpABIKind FpABI = ABIFlagsSection.getFpABI();
790 if (FpABI == MipsABIFlagsSection::FpABIKind::SOFT)
791 OS << "\t.module\tsoftfloat\n";
792 else
793 OS << "\t.module\tfp=" << ABIFlagsSection.getFpABIString(Value: FpABI) << "\n";
794}
795
796void MipsTargetAsmStreamer::emitDirectiveSetFp(
797 MipsABIFlagsSection::FpABIKind Value) {
798 MipsTargetStreamer::emitDirectiveSetFp(Value);
799
800 OS << "\t.set\tfp=";
801 OS << ABIFlagsSection.getFpABIString(Value) << "\n";
802}
803
804void MipsTargetAsmStreamer::emitDirectiveModuleOddSPReg() {
805 MipsTargetStreamer::emitDirectiveModuleOddSPReg();
806
807 OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? "" : "no") << "oddspreg\n";
808}
809
810void MipsTargetAsmStreamer::emitDirectiveSetOddSPReg() {
811 MipsTargetStreamer::emitDirectiveSetOddSPReg();
812 OS << "\t.set\toddspreg\n";
813}
814
815void MipsTargetAsmStreamer::emitDirectiveSetNoOddSPReg() {
816 MipsTargetStreamer::emitDirectiveSetNoOddSPReg();
817 OS << "\t.set\tnooddspreg\n";
818}
819
820void MipsTargetAsmStreamer::emitDirectiveModuleSoftFloat() {
821 OS << "\t.module\tsoftfloat\n";
822}
823
824void MipsTargetAsmStreamer::emitDirectiveModuleHardFloat() {
825 OS << "\t.module\thardfloat\n";
826}
827
828void MipsTargetAsmStreamer::emitDirectiveModuleMT() {
829 OS << "\t.module\tmt\n";
830}
831
832void MipsTargetAsmStreamer::emitDirectiveModuleCRC() {
833 OS << "\t.module\tcrc\n";
834}
835
836void MipsTargetAsmStreamer::emitDirectiveModuleNoCRC() {
837 OS << "\t.module\tnocrc\n";
838}
839
840void MipsTargetAsmStreamer::emitDirectiveModuleVirt() {
841 OS << "\t.module\tvirt\n";
842}
843
844void MipsTargetAsmStreamer::emitDirectiveModuleNoVirt() {
845 OS << "\t.module\tnovirt\n";
846}
847
848void MipsTargetAsmStreamer::emitDirectiveModuleGINV() {
849 OS << "\t.module\tginv\n";
850}
851
852void MipsTargetAsmStreamer::emitDirectiveModuleNoGINV() {
853 OS << "\t.module\tnoginv\n";
854}
855
856// This part is for ELF object output.
857MipsTargetELFStreamer::ISAMode
858MipsTargetELFStreamer::getISAMode(const MCSubtargetInfo &STI) {
859 if (STI.hasFeature(Feature: Mips::FeatureMips16))
860 return ISAMode::Mips16;
861 if (STI.hasFeature(Feature: Mips::FeatureMicroMips))
862 return ISAMode::MicroMips;
863 return ISAMode::Standard;
864}
865
866MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
867 const MCSubtargetInfo &STI)
868 : MipsTargetStreamer(S),
869 CLOpts(MIPS_MC::getCLOpts(Options: S.getContext().getTargetOptions())),
870 Mode(getISAMode(STI)), STI(STI) {
871 MCAssembler &MCA = getStreamer().getAssembler();
872 ELFObjectWriter &W = getStreamer().getWriter();
873
874 // It's possible that MCObjectFileInfo isn't fully initialized at this point
875 // due to an initialization order problem where CodeGenTargetMachineImpl
876 // creates the target streamer before TargetLoweringObjectFile calls
877 // InitializeMCObjectFileInfo. There doesn't seem to be a single place that
878 // covers all cases so this statement covers most cases and direct object
879 // emission must call setPic() once MCObjectFileInfo has been initialized. The
880 // cases we don't handle here are covered by MipsAsmPrinter.
881 Pic = MCA.getContext().getObjectFileInfo()->isPositionIndependent();
882
883 const FeatureBitset &Features = STI.getFeatureBits();
884
885 // Set the header flags that we can in the constructor.
886 // FIXME: This is a fairly terrible hack. We set the rest
887 // of these in the destructor. The problem here is two-fold:
888 //
889 // a: Some of the eflags can be set/reset by directives.
890 // b: There aren't any usage paths that initialize the ABI
891 // pointer until after we initialize either an assembler
892 // or the target machine.
893 // We can fix this by making the target streamer construct
894 // the ABI, but this is fraught with wide ranging dependency
895 // issues as well.
896 unsigned EFlags = W.getELFHeaderEFlags();
897
898 // FIXME: Fix a dependency issue by instantiating the ABI object to some
899 // default based off the triple. The triple doesn't describe the target
900 // fully, but any external user of the API that uses the MCTargetStreamer
901 // would otherwise crash on assertion failure.
902
903 ABI = MipsABIInfo(STI.getTargetTriple().isMIPS32() ? MipsABIInfo::O32()
904 : MipsABIInfo::N64());
905
906 // Architecture
907 if (Features[Mips::FeatureMips64r6])
908 EFlags |= ELF::EF_MIPS_ARCH_64R6;
909 else if (Features[Mips::FeatureMips64r2] ||
910 Features[Mips::FeatureMips64r3] ||
911 Features[Mips::FeatureMips64r5])
912 EFlags |= ELF::EF_MIPS_ARCH_64R2;
913 else if (Features[Mips::FeatureMips64])
914 EFlags |= ELF::EF_MIPS_ARCH_64;
915 else if (Features[Mips::FeatureMips5])
916 EFlags |= ELF::EF_MIPS_ARCH_5;
917 else if (Features[Mips::FeatureMips4])
918 EFlags |= ELF::EF_MIPS_ARCH_4;
919 else if (Features[Mips::FeatureMips3])
920 EFlags |= ELF::EF_MIPS_ARCH_3;
921 else if (Features[Mips::FeatureMips32r6])
922 EFlags |= ELF::EF_MIPS_ARCH_32R6;
923 else if (Features[Mips::FeatureMips32r2] ||
924 Features[Mips::FeatureMips32r3] ||
925 Features[Mips::FeatureMips32r5])
926 EFlags |= ELF::EF_MIPS_ARCH_32R2;
927 else if (Features[Mips::FeatureMips32])
928 EFlags |= ELF::EF_MIPS_ARCH_32;
929 else if (Features[Mips::FeatureMips2])
930 EFlags |= ELF::EF_MIPS_ARCH_2;
931 else
932 EFlags |= ELF::EF_MIPS_ARCH_1;
933
934 // Machine
935 if (Features[Mips::FeatureCnMips])
936 EFlags |= ELF::EF_MIPS_MACH_OCTEON;
937 else if (Features[Mips::FeatureR5900])
938 EFlags |= ELF::EF_MIPS_MACH_5900;
939
940 // Other options.
941 if (isMips16Enabled())
942 EFlags |= ELF::EF_MIPS_ARCH_ASE_M16;
943 if (Features[Mips::FeatureNaN2008])
944 EFlags |= ELF::EF_MIPS_NAN2008;
945
946 W.setELFHeaderEFlags(EFlags);
947}
948
949void MipsTargetELFStreamer::emitLabel(MCSymbol *S) {
950 auto *Symbol = static_cast<MCSymbolELF *>(S);
951 getStreamer().getAssembler().registerSymbol(Symbol: *Symbol);
952 uint8_t Type = Symbol->getType();
953 if (Type != ELF::STT_FUNC)
954 return;
955
956 if (isMicroMipsEnabled())
957 Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
958 else if (isMips16Enabled())
959 Symbol->setOther(ELF::STO_MIPS_MIPS16);
960}
961
962void MipsTargetELFStreamer::finish() {
963 MCAssembler &MCA = getStreamer().getAssembler();
964 ELFObjectWriter &W = getStreamer().getWriter();
965 const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
966 MCELFStreamer &S = getStreamer();
967
968 // .bss, .text and .data are always at least 16-byte aligned.
969 MCSection &TextSection = *OFI.getTextSection();
970 S.switchSection(Section: &TextSection);
971 MCSection &DataSection = *OFI.getDataSection();
972 S.switchSection(Section: &DataSection);
973 MCSection &BSSSection = *OFI.getBSSSection();
974 S.switchSection(Section: &BSSSection);
975
976 TextSection.ensureMinAlignment(MinAlignment: Align(16));
977 DataSection.ensureMinAlignment(MinAlignment: Align(16));
978 BSSSection.ensureMinAlignment(MinAlignment: Align(16));
979
980 if (CLOpts.round_section_sizes) {
981 // Make sections sizes a multiple of the alignment. This is useful for
982 // verifying the output of IAS against the output of other assemblers but
983 // it's not necessary to produce a correct object and increases section
984 // size.
985 for (MCSection &Sec : MCA) {
986 MCSectionELF &Section = static_cast<MCSectionELF &>(Sec);
987
988 Align Alignment = Section.getAlign();
989 S.switchSection(Section: &Section);
990 if (getContext().getAsmInfo().useCodeAlign(Sec: Section))
991 S.emitCodeAlignment(ByteAlignment: Alignment, STI, MaxBytesToEmit: Alignment.value());
992 else
993 S.emitValueToAlignment(Alignment, Fill: 0, FillLen: 1, MaxBytesToEmit: Alignment.value());
994 }
995 }
996
997 const FeatureBitset &Features = STI.getFeatureBits();
998
999 // Update e_header flags. See the FIXME and comment above in
1000 // the constructor for a full rundown on this.
1001 unsigned EFlags = W.getELFHeaderEFlags();
1002
1003 // ABI
1004 // N64 does not require any ABI bits.
1005 if (getABI().IsO32())
1006 EFlags |= ELF::EF_MIPS_ABI_O32;
1007 else if (getABI().IsN32())
1008 EFlags |= ELF::EF_MIPS_ABI2;
1009
1010 if (Features[Mips::FeatureGP64Bit]) {
1011 if (getABI().IsO32())
1012 EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
1013 } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
1014 EFlags |= ELF::EF_MIPS_32BITMODE;
1015
1016 // -mplt is not implemented but we should act as if it was
1017 // given.
1018 if (!Features[Mips::FeatureNoABICalls])
1019 EFlags |= ELF::EF_MIPS_CPIC;
1020
1021 if (Pic)
1022 EFlags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
1023
1024 W.setELFHeaderEFlags(EFlags);
1025
1026 // Emit all the option records.
1027 // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
1028 // .reginfo.
1029 MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
1030 MEF.EmitMipsOptionRecords();
1031
1032 emitMipsAbiFlags();
1033}
1034
1035void MipsTargetELFStreamer::emitAssignment(MCSymbol *S, const MCExpr *Value) {
1036 auto *Symbol = static_cast<MCSymbolELF *>(S);
1037 // Propagate the ISA mode of a symbol to its alias.
1038 if (Value->getKind() != MCExpr::SymbolRef)
1039 return;
1040 auto &RhsSym = static_cast<const MCSymbolELF &>(
1041 static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
1042
1043 // Copy the target-specific flags directly; visibility is stored separately.
1044 Symbol->setOther(RhsSym.getOther());
1045}
1046
1047MCELFStreamer &MipsTargetELFStreamer::getStreamer() {
1048 return static_cast<MCELFStreamer &>(Streamer);
1049}
1050
1051void MipsTargetELFStreamer::emitGPRel32Value(const MCExpr *Value) {
1052 auto &S = getStreamer();
1053 S.ensureHeadroom(Headroom: 4);
1054 S.addFixup(Value, Kind: Mips::fixup_Mips_GPREL32);
1055 S.appendContents(Num: 4, Elt: 0);
1056}
1057
1058void MipsTargetELFStreamer::emitGPRel64Value(const MCExpr *Value) {
1059 auto &S = getStreamer();
1060 S.ensureHeadroom(Headroom: 8);
1061 // fixup_Mips_GPREL32 desginates R_MIPS_GPREL32+R_MIPS_64 on MIPS64.
1062 S.addFixup(Value, Kind: Mips::fixup_Mips_GPREL32);
1063 S.appendContents(Num: 8, Elt: 0);
1064}
1065
1066void MipsTargetELFStreamer::emitDTPRel32Value(const MCExpr *Value) {
1067 auto &S = getStreamer();
1068 S.ensureHeadroom(Headroom: 4);
1069 S.addFixup(Value, Kind: Mips::fixup_Mips_DTPREL32);
1070 S.appendContents(Num: 4, Elt: 0);
1071}
1072
1073void MipsTargetELFStreamer::emitDTPRel64Value(const MCExpr *Value) {
1074 auto &S = getStreamer();
1075 S.ensureHeadroom(Headroom: 8);
1076 S.addFixup(Value, Kind: Mips::fixup_Mips_DTPREL64);
1077 S.appendContents(Num: 8, Elt: 0);
1078}
1079
1080void MipsTargetELFStreamer::emitTPRel32Value(const MCExpr *Value) {
1081 auto &S = getStreamer();
1082 S.ensureHeadroom(Headroom: 4);
1083 S.addFixup(Value, Kind: Mips::fixup_Mips_TPREL32);
1084 S.appendContents(Num: 4, Elt: 0);
1085}
1086
1087void MipsTargetELFStreamer::emitTPRel64Value(const MCExpr *Value) {
1088 auto &S = getStreamer();
1089 S.ensureHeadroom(Headroom: 8);
1090 S.addFixup(Value, Kind: Mips::fixup_Mips_TPREL64);
1091 S.appendContents(Num: 8, Elt: 0);
1092}
1093
1094void MipsTargetELFStreamer::emitDirectiveSetMicroMips() {
1095 Mode = ISAMode::MicroMips;
1096 forbidModuleDirective();
1097}
1098
1099void MipsTargetELFStreamer::emitDirectiveSetNoMicroMips() {
1100 if (isMicroMipsEnabled())
1101 Mode = ISAMode::Standard;
1102 forbidModuleDirective();
1103}
1104
1105void MipsTargetELFStreamer::emitDirectiveSetPush() {
1106 ModeStack.push_back(Elt: Mode);
1107 MipsTargetStreamer::emitDirectiveSetPush();
1108}
1109
1110void MipsTargetELFStreamer::emitDirectiveSetPop() {
1111 assert(!ModeStack.empty() && "unmatched .set pop");
1112 Mode = ModeStack.pop_back_val();
1113 MipsTargetStreamer::emitDirectiveSetPop();
1114}
1115
1116void MipsTargetELFStreamer::emitDirectiveSetMips0() {
1117 Mode = getISAMode(STI);
1118 MipsTargetStreamer::emitDirectiveSetMips0();
1119}
1120
1121void MipsTargetELFStreamer::setUsesMicroMips() {
1122 ELFObjectWriter &W = getStreamer().getWriter();
1123 unsigned Flags = W.getELFHeaderEFlags();
1124 Flags |= ELF::EF_MIPS_MICROMIPS;
1125 W.setELFHeaderEFlags(Flags);
1126}
1127
1128void MipsTargetELFStreamer::emitDirectiveSetMips16() {
1129 Mode = ISAMode::Mips16;
1130 ELFObjectWriter &W = getStreamer().getWriter();
1131 unsigned Flags = W.getELFHeaderEFlags();
1132 Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
1133 W.setELFHeaderEFlags(Flags);
1134 forbidModuleDirective();
1135}
1136
1137void MipsTargetELFStreamer::emitDirectiveSetNoMips16() {
1138 if (isMips16Enabled())
1139 Mode = ISAMode::Standard;
1140 MipsTargetStreamer::emitDirectiveSetNoMips16();
1141}
1142
1143void MipsTargetELFStreamer::emitDirectiveSetNoReorder() {
1144 ELFObjectWriter &W = getStreamer().getWriter();
1145 unsigned Flags = W.getELFHeaderEFlags();
1146 Flags |= ELF::EF_MIPS_NOREORDER;
1147 W.setELFHeaderEFlags(Flags);
1148 forbidModuleDirective();
1149}
1150
1151void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) {
1152 MCAssembler &MCA = getStreamer().getAssembler();
1153 MCContext &Context = MCA.getContext();
1154 MCStreamer &OS = getStreamer();
1155
1156 OS.pushSection();
1157 MCSectionELF *Sec = Context.getELFSection(Section: ".pdr", Type: ELF::SHT_PROGBITS, Flags: 0);
1158 OS.switchSection(Section: Sec);
1159 Sec->setAlignment(Align(4));
1160
1161 MCSymbol *Sym = Context.getOrCreateSymbol(Name);
1162 const auto *ExprRef = MCSymbolRefExpr::create(Symbol: Sym, Ctx&: Context);
1163 OS.emitValueImpl(Value: ExprRef, Size: 4);
1164
1165 OS.emitIntValue(Value: GPRInfoSet ? GPRBitMask : 0, Size: 4); // reg_mask
1166 OS.emitIntValue(Value: GPRInfoSet ? GPROffset : 0, Size: 4); // reg_offset
1167
1168 OS.emitIntValue(Value: FPRInfoSet ? FPRBitMask : 0, Size: 4); // fpreg_mask
1169 OS.emitIntValue(Value: FPRInfoSet ? FPROffset : 0, Size: 4); // fpreg_offset
1170
1171 OS.emitIntValue(Value: FrameInfoSet ? FrameOffset : 0, Size: 4); // frame_offset
1172 OS.emitIntValue(Value: FrameInfoSet ? FrameReg : 0, Size: 4); // frame_reg
1173 OS.emitIntValue(Value: FrameInfoSet ? ReturnReg : 0, Size: 4); // return_reg
1174
1175 // The .end directive marks the end of a procedure. Invalidate
1176 // the information gathered up until this point.
1177 GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1178
1179 OS.popSection();
1180
1181 // .end also implicitly sets the size.
1182 MCSymbol *CurPCSym = Context.createTempSymbol();
1183 OS.emitLabel(Symbol: CurPCSym);
1184 const MCExpr *Size = MCBinaryExpr::createSub(
1185 LHS: MCSymbolRefExpr::create(Symbol: CurPCSym, Ctx&: Context), RHS: ExprRef, Ctx&: Context);
1186
1187 // The ELFObjectWriter can determine the absolute size as it has access to
1188 // the layout information of the assembly file, so a size expression rather
1189 // than an absolute value is ok here.
1190 static_cast<MCSymbolELF *>(Sym)->setSize(Size);
1191}
1192
1193void MipsTargetELFStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
1194 GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1195
1196 // .ent also acts like an implicit '.type symbol, STT_FUNC'
1197 static_cast<const MCSymbolELF &>(Symbol).setType(ELF::STT_FUNC);
1198}
1199
1200void MipsTargetELFStreamer::emitDirectiveAbiCalls() {
1201 ELFObjectWriter &W = getStreamer().getWriter();
1202 unsigned Flags = W.getELFHeaderEFlags();
1203 Flags |= ELF::EF_MIPS_CPIC | ELF::EF_MIPS_PIC;
1204 W.setELFHeaderEFlags(Flags);
1205}
1206
1207void MipsTargetELFStreamer::emitDirectiveNaN2008() {
1208 ELFObjectWriter &W = getStreamer().getWriter();
1209 unsigned Flags = W.getELFHeaderEFlags();
1210 Flags |= ELF::EF_MIPS_NAN2008;
1211 W.setELFHeaderEFlags(Flags);
1212}
1213
1214void MipsTargetELFStreamer::emitDirectiveNaNLegacy() {
1215 ELFObjectWriter &W = getStreamer().getWriter();
1216 unsigned Flags = W.getELFHeaderEFlags();
1217 Flags &= ~ELF::EF_MIPS_NAN2008;
1218 W.setELFHeaderEFlags(Flags);
1219}
1220
1221void MipsTargetELFStreamer::emitDirectiveOptionPic0() {
1222 ELFObjectWriter &W = getStreamer().getWriter();
1223 unsigned Flags = W.getELFHeaderEFlags();
1224 // This option overrides other PIC options like -KPIC.
1225 Pic = false;
1226 Flags &= ~ELF::EF_MIPS_PIC;
1227 W.setELFHeaderEFlags(Flags);
1228}
1229
1230void MipsTargetELFStreamer::emitDirectiveOptionPic2() {
1231 ELFObjectWriter &W = getStreamer().getWriter();
1232 unsigned Flags = W.getELFHeaderEFlags();
1233 Pic = true;
1234 // NOTE: We are following the GAS behaviour here which means the directive
1235 // 'pic2' also sets the CPIC bit in the ELF header. This is different from
1236 // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
1237 // EF_MIPS_CPIC to be mutually exclusive.
1238 Flags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
1239 W.setELFHeaderEFlags(Flags);
1240}
1241
1242void MipsTargetELFStreamer::emitDirectiveInsn() {
1243 MipsTargetStreamer::emitDirectiveInsn();
1244 MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
1245 MEF.createPendingLabelRelocs();
1246}
1247
1248void MipsTargetELFStreamer::emitFrame(MCRegister StackReg, unsigned StackSize,
1249 MCRegister ReturnReg_) {
1250 MCContext &Context = getStreamer().getAssembler().getContext();
1251 const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
1252
1253 FrameInfoSet = true;
1254 FrameReg = RegInfo->getEncodingValue(Reg: StackReg);
1255 FrameOffset = StackSize;
1256 ReturnReg = RegInfo->getEncodingValue(Reg: ReturnReg_);
1257}
1258
1259void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
1260 int CPUTopSavedRegOff) {
1261 GPRInfoSet = true;
1262 GPRBitMask = CPUBitmask;
1263 GPROffset = CPUTopSavedRegOff;
1264}
1265
1266void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
1267 int FPUTopSavedRegOff) {
1268 FPRInfoSet = true;
1269 FPRBitMask = FPUBitmask;
1270 FPROffset = FPUTopSavedRegOff;
1271}
1272
1273void MipsTargetELFStreamer::emitDirectiveCpAdd(MCRegister Reg) {
1274 // .cpadd $reg
1275 // This directive inserts code to add $gp to the argument's register
1276 // when support for position independent code is enabled.
1277 if (!Pic)
1278 return;
1279
1280 emitAddu(DstReg: Reg, SrcReg: Reg, TrgReg: GPReg, Is64Bit: getABI().IsN64(), STI: &STI);
1281 forbidModuleDirective();
1282}
1283
1284void MipsTargetELFStreamer::emitDirectiveCpLoad(MCRegister Reg) {
1285 // .cpload $reg
1286 // This directive expands to:
1287 // lui $gp, %hi(_gp_disp)
1288 // addui $gp, $gp, %lo(_gp_disp)
1289 // addu $gp, $gp, $reg
1290 // when support for position independent code is enabled.
1291 if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1292 return;
1293
1294 // There's a GNU extension controlled by -mno-shared that allows
1295 // locally-binding symbols to be accessed using absolute addresses.
1296 // This is currently not supported. When supported -mno-shared makes
1297 // .cpload expand to:
1298 // lui $gp, %hi(__gnu_local_gp)
1299 // addiu $gp, $gp, %lo(__gnu_local_gp)
1300
1301 StringRef SymName("_gp_disp");
1302 MCAssembler &MCA = getStreamer().getAssembler();
1303 MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(Name: SymName);
1304 MCA.registerSymbol(Symbol: *GP_Disp);
1305
1306 MCInst TmpInst;
1307 TmpInst.setOpcode(Mips::LUi);
1308 TmpInst.addOperand(Op: MCOperand::createReg(Reg: GPReg));
1309 auto *HiSym = MCSpecifierExpr::create(Sym: GP_Disp, S: Mips::S_HI, Ctx&: MCA.getContext());
1310 TmpInst.addOperand(Op: MCOperand::createExpr(Val: HiSym));
1311 getStreamer().emitInstruction(Inst: TmpInst, STI);
1312
1313 TmpInst.clear();
1314
1315 TmpInst.setOpcode(Mips::ADDiu);
1316 TmpInst.addOperand(Op: MCOperand::createReg(Reg: GPReg));
1317 TmpInst.addOperand(Op: MCOperand::createReg(Reg: GPReg));
1318 auto *LoSym = MCSpecifierExpr::create(Sym: GP_Disp, S: Mips::S_LO, Ctx&: MCA.getContext());
1319 TmpInst.addOperand(Op: MCOperand::createExpr(Val: LoSym));
1320 getStreamer().emitInstruction(Inst: TmpInst, STI);
1321
1322 TmpInst.clear();
1323
1324 TmpInst.setOpcode(Mips::ADDu);
1325 TmpInst.addOperand(Op: MCOperand::createReg(Reg: GPReg));
1326 TmpInst.addOperand(Op: MCOperand::createReg(Reg: GPReg));
1327 TmpInst.addOperand(Op: MCOperand::createReg(Reg));
1328 getStreamer().emitInstruction(Inst: TmpInst, STI);
1329
1330 forbidModuleDirective();
1331}
1332
1333void MipsTargetELFStreamer::emitDirectiveCpLocal(MCRegister Reg) {
1334 if (Pic)
1335 MipsTargetStreamer::emitDirectiveCpLocal(Reg);
1336}
1337
1338bool MipsTargetELFStreamer::emitDirectiveCpRestore(
1339 int Offset, function_ref<MCRegister()> GetATReg, SMLoc IDLoc,
1340 const MCSubtargetInfo *STI) {
1341 MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
1342 // .cprestore offset
1343 // When PIC mode is enabled and the O32 ABI is used, this directive expands
1344 // to:
1345 // sw $gp, offset($sp)
1346 // and adds a corresponding LW after every JAL.
1347
1348 // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
1349 // is used in non-PIC mode.
1350 if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1351 return true;
1352
1353 // Store the $gp on the stack.
1354 emitStoreWithImmOffset(Opcode: Mips::SW, SrcReg: GPReg, BaseReg: Mips::SP, Offset, GetATReg, IDLoc,
1355 STI);
1356 return true;
1357}
1358
1359void MipsTargetELFStreamer::emitDirectiveCpsetup(MCRegister Reg,
1360 int RegOrOffset,
1361 const MCSymbol &Sym,
1362 bool IsReg) {
1363 // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
1364 if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1365 return;
1366
1367 forbidModuleDirective();
1368
1369 MCAssembler &MCA = getStreamer().getAssembler();
1370 MCInst Inst;
1371
1372 // Either store the old $gp in a register or on the stack
1373 if (IsReg) {
1374 // move $save, $gpreg
1375 emitRRR(Opcode: Mips::OR64, Reg0: RegOrOffset, Reg1: GPReg, Reg2: Mips::R0, IDLoc: SMLoc(), STI: &STI);
1376 } else {
1377 // sd $gpreg, offset($sp)
1378 emitRRI(Opcode: Mips::SD, Reg0: GPReg, Reg1: Mips::SP, Imm: RegOrOffset, IDLoc: SMLoc(), STI: &STI);
1379 }
1380
1381 auto *HiExpr =
1382 Mips::createGpOff(Expr: MCSymbolRefExpr::create(Symbol: &Sym, Ctx&: MCA.getContext()),
1383 S: Mips::S_HI, Ctx&: MCA.getContext());
1384 auto *LoExpr =
1385 Mips::createGpOff(Expr: MCSymbolRefExpr::create(Symbol: &Sym, Ctx&: MCA.getContext()),
1386 S: Mips::S_LO, Ctx&: MCA.getContext());
1387
1388 // lui $gp, %hi(%neg(%gp_rel(funcSym)))
1389 emitRX(Opcode: Mips::LUi, Reg0: GPReg, Op1: MCOperand::createExpr(Val: HiExpr), IDLoc: SMLoc(), STI: &STI);
1390
1391 // addiu $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
1392 emitRRX(Opcode: Mips::ADDiu, Reg0: GPReg, Reg1: GPReg, Op2: MCOperand::createExpr(Val: LoExpr), IDLoc: SMLoc(),
1393 STI: &STI);
1394
1395 // (d)addu $gp, $gp, $funcreg
1396 if (getABI().IsN32())
1397 emitRRR(Opcode: Mips::ADDu, Reg0: GPReg, Reg1: GPReg, Reg2: Reg, IDLoc: SMLoc(), STI: &STI);
1398 else
1399 emitRRR(Opcode: Mips::DADDu, Reg0: GPReg, Reg1: GPReg, Reg2: Reg, IDLoc: SMLoc(), STI: &STI);
1400}
1401
1402void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
1403 bool SaveLocationIsRegister) {
1404 // Only N32 and N64 emit anything for .cpreturn iff PIC is set.
1405 if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1406 return;
1407
1408 MCInst Inst;
1409 // Either restore the old $gp from a register or on the stack
1410 if (SaveLocationIsRegister) {
1411 Inst.setOpcode(Mips::OR);
1412 Inst.addOperand(Op: MCOperand::createReg(Reg: GPReg));
1413 Inst.addOperand(Op: MCOperand::createReg(Reg: SaveLocation));
1414 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::R0));
1415 } else {
1416 Inst.setOpcode(Mips::LD);
1417 Inst.addOperand(Op: MCOperand::createReg(Reg: GPReg));
1418 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::SP));
1419 Inst.addOperand(Op: MCOperand::createImm(Val: SaveLocation));
1420 }
1421 getStreamer().emitInstruction(Inst, STI);
1422
1423 forbidModuleDirective();
1424}
1425
1426void MipsTargetELFStreamer::emitMipsAbiFlags() {
1427 MCAssembler &MCA = getStreamer().getAssembler();
1428 MCContext &Context = MCA.getContext();
1429 MCStreamer &OS = getStreamer();
1430 MCSectionELF *Sec = Context.getELFSection(
1431 Section: ".MIPS.abiflags", Type: ELF::SHT_MIPS_ABIFLAGS, Flags: ELF::SHF_ALLOC, EntrySize: 24);
1432 OS.switchSection(Section: Sec);
1433 Sec->setAlignment(Align(8));
1434
1435 OS << ABIFlagsSection;
1436}
1437