1//===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides Mips specific target streamer methods.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MipsTargetStreamer.h"
14#include "MCTargetDesc/MipsABIInfo.h"
15#include "MCTargetDesc/MipsMCAsmInfo.h"
16#include "MipsBaseInfo.h"
17#include "MipsELFStreamer.h"
18#include "MipsInstPrinter.h"
19#include "MipsMCTargetDesc.h"
20#include "llvm/BinaryFormat/ELF.h"
21#include "llvm/MC/MCAsmInfo.h"
22#include "llvm/MC/MCAssembler.h"
23#include "llvm/MC/MCContext.h"
24#include "llvm/MC/MCELFObjectWriter.h"
25#include "llvm/MC/MCObjectFileInfo.h"
26#include "llvm/MC/MCSectionELF.h"
27#include "llvm/MC/MCSubtargetInfo.h"
28#include "llvm/MC/MCSymbolELF.h"
29#include "llvm/Support/CommandLine.h"
30#include "llvm/Support/ErrorHandling.h"
31#include "llvm/Support/FormattedStream.h"
32
33using namespace llvm;
34
35namespace {
36static cl::opt<bool> RoundSectionSizes(
37 "mips-round-section-sizes", cl::init(Val: false),
38 cl::desc("Round section sizes up to the section alignment"), cl::Hidden);
39} // end anonymous namespace
40
41static bool isMicroMips(const MCSubtargetInfo *STI) {
42 return STI->hasFeature(Feature: Mips::FeatureMicroMips);
43}
44
45static bool isMips32r6(const MCSubtargetInfo *STI) {
46 return STI->hasFeature(Feature: Mips::FeatureMips32r6);
47}
48
49MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
50 : MCTargetStreamer(S), GPReg(Mips::GP), ModuleDirectiveAllowed(true) {
51 GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
52}
53
54void MipsTargetStreamer::emitGPRel32Value(const MCExpr *) {}
55void MipsTargetStreamer::emitGPRel64Value(const MCExpr *) {}
56void MipsTargetStreamer::emitDTPRel32Value(const MCExpr *) {}
57void MipsTargetStreamer::emitDTPRel64Value(const MCExpr *) {}
58void MipsTargetStreamer::emitTPRel32Value(const MCExpr *) {}
59void MipsTargetStreamer::emitTPRel64Value(const MCExpr *) {}
60void MipsTargetStreamer::emitDirectiveSetMicroMips() {}
61void MipsTargetStreamer::emitDirectiveSetNoMicroMips() {}
62void MipsTargetStreamer::setUsesMicroMips() {}
63void MipsTargetStreamer::emitDirectiveSetMips16() {}
64void MipsTargetStreamer::emitDirectiveSetNoMips16() { forbidModuleDirective(); }
65void MipsTargetStreamer::emitDirectiveSetReorder() { forbidModuleDirective(); }
66void MipsTargetStreamer::emitDirectiveSetNoReorder() {}
67void MipsTargetStreamer::emitDirectiveSetMacro() { forbidModuleDirective(); }
68void MipsTargetStreamer::emitDirectiveSetNoMacro() { forbidModuleDirective(); }
69void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); }
70void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); }
71void MipsTargetStreamer::emitDirectiveSetMt() {}
72void MipsTargetStreamer::emitDirectiveSetNoMt() { forbidModuleDirective(); }
73void MipsTargetStreamer::emitDirectiveSetCRC() {}
74void MipsTargetStreamer::emitDirectiveSetNoCRC() {}
75void MipsTargetStreamer::emitDirectiveSetVirt() {}
76void MipsTargetStreamer::emitDirectiveSetNoVirt() {}
77void MipsTargetStreamer::emitDirectiveSetGINV() {}
78void MipsTargetStreamer::emitDirectiveSetNoGINV() {}
79void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
80void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
81 forbidModuleDirective();
82}
83void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); }
84void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {}
85void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {}
86void MipsTargetStreamer::emitDirectiveAbiCalls() {}
87void MipsTargetStreamer::emitDirectiveNaN2008() {}
88void MipsTargetStreamer::emitDirectiveNaNLegacy() {}
89void MipsTargetStreamer::emitDirectiveOptionPic0() {}
90void MipsTargetStreamer::emitDirectiveOptionPic2() {}
91void MipsTargetStreamer::emitDirectiveInsn() { forbidModuleDirective(); }
92void MipsTargetStreamer::emitFrame(MCRegister StackReg, unsigned StackSize,
93 MCRegister ReturnReg) {}
94void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
95void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
96}
97void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
98 forbidModuleDirective();
99}
100void MipsTargetStreamer::emitDirectiveSetMips0() { forbidModuleDirective(); }
101void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
102void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
103void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
104void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
105void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
106void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
107void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
108void MipsTargetStreamer::emitDirectiveSetMips32R3() { forbidModuleDirective(); }
109void MipsTargetStreamer::emitDirectiveSetMips32R5() { forbidModuleDirective(); }
110void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
111void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); }
112void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); }
113void MipsTargetStreamer::emitDirectiveSetMips64R3() { forbidModuleDirective(); }
114void MipsTargetStreamer::emitDirectiveSetMips64R5() { forbidModuleDirective(); }
115void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); }
116void MipsTargetStreamer::emitDirectiveSetPop() { forbidModuleDirective(); }
117void MipsTargetStreamer::emitDirectiveSetPush() { forbidModuleDirective(); }
118void MipsTargetStreamer::emitDirectiveSetSoftFloat() {
119 forbidModuleDirective();
120}
121void MipsTargetStreamer::emitDirectiveSetHardFloat() {
122 forbidModuleDirective();
123}
124void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
125void MipsTargetStreamer::emitDirectiveSetDspr2() { forbidModuleDirective(); }
126void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
127void MipsTargetStreamer::emitDirectiveSetMips3D() { forbidModuleDirective(); }
128void MipsTargetStreamer::emitDirectiveSetNoMips3D() { forbidModuleDirective(); }
129void MipsTargetStreamer::emitDirectiveCpAdd(MCRegister Reg) {}
130void MipsTargetStreamer::emitDirectiveCpLoad(MCRegister Reg) {}
131void MipsTargetStreamer::emitDirectiveCpLocal(MCRegister Reg) {
132 // .cplocal $reg
133 // This directive forces to use the alternate register for context pointer.
134 // For example
135 // .cplocal $4
136 // jal foo
137 // expands to
138 // ld $25, %call16(foo)($4)
139 // jalr $25
140
141 if (!getABI().IsN32() && !getABI().IsN64())
142 return;
143
144 GPReg = Reg;
145
146 forbidModuleDirective();
147}
148bool MipsTargetStreamer::emitDirectiveCpRestore(
149 int Offset, function_ref<MCRegister()> GetATReg, SMLoc IDLoc,
150 const MCSubtargetInfo *STI) {
151 forbidModuleDirective();
152 return true;
153}
154void MipsTargetStreamer::emitDirectiveCpsetup(MCRegister Reg, int RegOrOffset,
155 const MCSymbol &Sym, bool IsReg) {
156}
157void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
158 bool SaveLocationIsRegister) {}
159
160void MipsTargetStreamer::emitDirectiveModuleFP() {}
161
162void MipsTargetStreamer::emitDirectiveModuleOddSPReg() {
163 if (!ABIFlagsSection.OddSPReg && !ABIFlagsSection.Is32BitABI)
164 report_fatal_error(reason: "+nooddspreg is only valid for O32");
165}
166void MipsTargetStreamer::emitDirectiveModuleSoftFloat() {}
167void MipsTargetStreamer::emitDirectiveModuleHardFloat() {}
168void MipsTargetStreamer::emitDirectiveModuleMT() {}
169void MipsTargetStreamer::emitDirectiveModuleCRC() {}
170void MipsTargetStreamer::emitDirectiveModuleNoCRC() {}
171void MipsTargetStreamer::emitDirectiveModuleVirt() {}
172void MipsTargetStreamer::emitDirectiveModuleNoVirt() {}
173void MipsTargetStreamer::emitDirectiveModuleGINV() {}
174void MipsTargetStreamer::emitDirectiveModuleNoGINV() {}
175void MipsTargetStreamer::emitDirectiveSetFp(
176 MipsABIFlagsSection::FpABIKind Value) {
177 forbidModuleDirective();
178}
179void MipsTargetStreamer::emitDirectiveSetOddSPReg() { forbidModuleDirective(); }
180void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
181 forbidModuleDirective();
182}
183
184void MipsTargetStreamer::emitR(unsigned Opcode, MCRegister Reg0, SMLoc IDLoc,
185 const MCSubtargetInfo *STI) {
186 MCInst TmpInst;
187 TmpInst.setOpcode(Opcode);
188 TmpInst.addOperand(Op: MCOperand::createReg(Reg: Reg0));
189 TmpInst.setLoc(IDLoc);
190 getStreamer().emitInstruction(Inst: TmpInst, STI: *STI);
191}
192
193void MipsTargetStreamer::emitRX(unsigned Opcode, MCRegister Reg0, MCOperand Op1,
194 SMLoc IDLoc, const MCSubtargetInfo *STI) {
195 MCInst TmpInst;
196 TmpInst.setOpcode(Opcode);
197 TmpInst.addOperand(Op: MCOperand::createReg(Reg: Reg0));
198 TmpInst.addOperand(Op: Op1);
199 TmpInst.setLoc(IDLoc);
200 getStreamer().emitInstruction(Inst: TmpInst, STI: *STI);
201}
202
203void MipsTargetStreamer::emitRI(unsigned Opcode, MCRegister Reg0, int32_t Imm,
204 SMLoc IDLoc, const MCSubtargetInfo *STI) {
205 emitRX(Opcode, Reg0, Op1: MCOperand::createImm(Val: Imm), IDLoc, STI);
206}
207
208void MipsTargetStreamer::emitRR(unsigned Opcode, MCRegister Reg0,
209 MCRegister Reg1, SMLoc IDLoc,
210 const MCSubtargetInfo *STI) {
211 emitRX(Opcode, Reg0, Op1: MCOperand::createReg(Reg: Reg1), IDLoc, STI);
212}
213
214void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
215 SMLoc IDLoc, const MCSubtargetInfo *STI) {
216 MCInst TmpInst;
217 TmpInst.setOpcode(Opcode);
218 TmpInst.addOperand(Op: MCOperand::createImm(Val: Imm1));
219 TmpInst.addOperand(Op: MCOperand::createImm(Val: Imm2));
220 TmpInst.setLoc(IDLoc);
221 getStreamer().emitInstruction(Inst: TmpInst, STI: *STI);
222}
223
224void MipsTargetStreamer::emitRRX(unsigned Opcode, MCRegister Reg0,
225 MCRegister Reg1, MCOperand Op2, SMLoc IDLoc,
226 const MCSubtargetInfo *STI) {
227 MCInst TmpInst;
228 TmpInst.setOpcode(Opcode);
229 TmpInst.addOperand(Op: MCOperand::createReg(Reg: Reg0));
230 TmpInst.addOperand(Op: MCOperand::createReg(Reg: Reg1));
231 TmpInst.addOperand(Op: Op2);
232 TmpInst.setLoc(IDLoc);
233 getStreamer().emitInstruction(Inst: TmpInst, STI: *STI);
234}
235
236void MipsTargetStreamer::emitRRR(unsigned Opcode, MCRegister Reg0,
237 MCRegister Reg1, MCRegister Reg2, SMLoc IDLoc,
238 const MCSubtargetInfo *STI) {
239 emitRRX(Opcode, Reg0, Reg1, Op2: MCOperand::createReg(Reg: Reg2), IDLoc, STI);
240}
241
242void MipsTargetStreamer::emitRRRX(unsigned Opcode, MCRegister Reg0,
243 MCRegister Reg1, MCRegister Reg2,
244 MCOperand Op3, SMLoc IDLoc,
245 const MCSubtargetInfo *STI) {
246 MCInst TmpInst;
247 TmpInst.setOpcode(Opcode);
248 TmpInst.addOperand(Op: MCOperand::createReg(Reg: Reg0));
249 TmpInst.addOperand(Op: MCOperand::createReg(Reg: Reg1));
250 TmpInst.addOperand(Op: MCOperand::createReg(Reg: Reg2));
251 TmpInst.addOperand(Op: Op3);
252 TmpInst.setLoc(IDLoc);
253 getStreamer().emitInstruction(Inst: TmpInst, STI: *STI);
254}
255
256void MipsTargetStreamer::emitRRI(unsigned Opcode, MCRegister Reg0,
257 MCRegister Reg1, int16_t Imm, SMLoc IDLoc,
258 const MCSubtargetInfo *STI) {
259 emitRRX(Opcode, Reg0, Reg1, Op2: MCOperand::createImm(Val: Imm), IDLoc, STI);
260}
261
262void MipsTargetStreamer::emitRRIII(unsigned Opcode, MCRegister Reg0,
263 MCRegister Reg1, int16_t Imm0, int16_t Imm1,
264 int16_t Imm2, SMLoc IDLoc,
265 const MCSubtargetInfo *STI) {
266 MCInst TmpInst;
267 TmpInst.setOpcode(Opcode);
268 TmpInst.addOperand(Op: MCOperand::createReg(Reg: Reg0));
269 TmpInst.addOperand(Op: MCOperand::createReg(Reg: Reg1));
270 TmpInst.addOperand(Op: MCOperand::createImm(Val: Imm0));
271 TmpInst.addOperand(Op: MCOperand::createImm(Val: Imm1));
272 TmpInst.addOperand(Op: MCOperand::createImm(Val: Imm2));
273 TmpInst.setLoc(IDLoc);
274 getStreamer().emitInstruction(Inst: TmpInst, STI: *STI);
275}
276
277void MipsTargetStreamer::emitAddu(MCRegister DstReg, MCRegister SrcReg,
278 MCRegister TrgReg, bool Is64Bit,
279 const MCSubtargetInfo *STI) {
280 emitRRR(Opcode: Is64Bit ? Mips::DADDu : Mips::ADDu, Reg0: DstReg, Reg1: SrcReg, Reg2: TrgReg, IDLoc: SMLoc(),
281 STI);
282}
283
284void MipsTargetStreamer::emitDSLL(MCRegister DstReg, MCRegister SrcReg,
285 int16_t ShiftAmount, SMLoc IDLoc,
286 const MCSubtargetInfo *STI) {
287 if (ShiftAmount >= 32) {
288 emitRRI(Opcode: Mips::DSLL32, Reg0: DstReg, Reg1: SrcReg, Imm: ShiftAmount - 32, IDLoc, STI);
289 return;
290 }
291
292 emitRRI(Opcode: Mips::DSLL, Reg0: DstReg, Reg1: SrcReg, Imm: ShiftAmount, IDLoc, STI);
293}
294
295void MipsTargetStreamer::emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc,
296 const MCSubtargetInfo *STI) {
297 // The default case of `nop` is `sll $zero, $zero, 0`.
298 unsigned Opc = Mips::SLL;
299 if (isMicroMips(STI) && hasShortDelaySlot) {
300 Opc = isMips32r6(STI) ? Mips::MOVE16_MMR6 : Mips::MOVE16_MM;
301 emitRR(Opcode: Opc, Reg0: Mips::ZERO, Reg1: Mips::ZERO, IDLoc, STI);
302 return;
303 }
304
305 if (isMicroMips(STI))
306 Opc = isMips32r6(STI) ? Mips::SLL_MMR6 : Mips::SLL_MM;
307
308 emitRRI(Opcode: Opc, Reg0: Mips::ZERO, Reg1: Mips::ZERO, Imm: 0, IDLoc, STI);
309}
310
311void MipsTargetStreamer::emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) {
312 if (isMicroMips(STI))
313 emitRR(Opcode: Mips::MOVE16_MM, Reg0: Mips::ZERO, Reg1: Mips::ZERO, IDLoc, STI);
314 else
315 emitRRI(Opcode: Mips::SLL, Reg0: Mips::ZERO, Reg1: Mips::ZERO, Imm: 0, IDLoc, STI);
316}
317
318/// Emit the $gp restore operation for .cprestore.
319void MipsTargetStreamer::emitGPRestore(int Offset, SMLoc IDLoc,
320 const MCSubtargetInfo *STI) {
321 emitLoadWithImmOffset(Opcode: Mips::LW, DstReg: GPReg, BaseReg: Mips::SP, Offset, TmpReg: GPReg, IDLoc, STI);
322}
323
324/// Emit a store instruction with an immediate offset.
325void MipsTargetStreamer::emitStoreWithImmOffset(
326 unsigned Opcode, MCRegister SrcReg, MCRegister BaseReg, int64_t Offset,
327 function_ref<MCRegister()> GetATReg, SMLoc IDLoc,
328 const MCSubtargetInfo *STI) {
329 if (isInt<16>(x: Offset)) {
330 emitRRI(Opcode, Reg0: SrcReg, Reg1: BaseReg, Imm: Offset, IDLoc, STI);
331 return;
332 }
333
334 // sw $8, offset($8) => lui $at, %hi(offset)
335 // add $at, $at, $8
336 // sw $8, %lo(offset)($at)
337
338 MCRegister ATReg = GetATReg();
339 if (!ATReg)
340 return;
341
342 unsigned LoOffset = Offset & 0x0000ffff;
343 unsigned HiOffset = (Offset & 0xffff0000) >> 16;
344
345 // If msb of LoOffset is 1(negative number) we must increment HiOffset
346 // to account for the sign-extension of the low part.
347 if (LoOffset & 0x8000)
348 HiOffset++;
349
350 // Generate the base address in ATReg.
351 emitRI(Opcode: Mips::LUi, Reg0: ATReg, Imm: HiOffset, IDLoc, STI);
352 if (BaseReg != Mips::ZERO)
353 emitRRR(Opcode: Mips::ADDu, Reg0: ATReg, Reg1: ATReg, Reg2: BaseReg, IDLoc, STI);
354 // Emit the store with the adjusted base and offset.
355 emitRRI(Opcode, Reg0: SrcReg, Reg1: ATReg, Imm: LoOffset, IDLoc, STI);
356}
357
358/// Emit a load instruction with an immediate offset. DstReg and TmpReg are
359/// permitted to be the same register iff DstReg is distinct from BaseReg and
360/// DstReg is a GPR. It is the callers responsibility to identify such cases
361/// and pass the appropriate register in TmpReg.
362void MipsTargetStreamer::emitLoadWithImmOffset(
363 unsigned Opcode, MCRegister DstReg, MCRegister BaseReg, int64_t Offset,
364 MCRegister TmpReg, SMLoc IDLoc, const MCSubtargetInfo *STI) {
365 if (isInt<16>(x: Offset)) {
366 emitRRI(Opcode, Reg0: DstReg, Reg1: BaseReg, Imm: Offset, IDLoc, STI);
367 return;
368 }
369
370 // 1) lw $8, offset($9) => lui $8, %hi(offset)
371 // add $8, $8, $9
372 // lw $8, %lo(offset)($9)
373 // 2) lw $8, offset($8) => lui $at, %hi(offset)
374 // add $at, $at, $8
375 // lw $8, %lo(offset)($at)
376
377 unsigned LoOffset = Offset & 0x0000ffff;
378 unsigned HiOffset = (Offset & 0xffff0000) >> 16;
379
380 // If msb of LoOffset is 1(negative number) we must increment HiOffset
381 // to account for the sign-extension of the low part.
382 if (LoOffset & 0x8000)
383 HiOffset++;
384
385 // Generate the base address in TmpReg.
386 emitRI(Opcode: Mips::LUi, Reg0: TmpReg, Imm: HiOffset, IDLoc, STI);
387 if (BaseReg != Mips::ZERO)
388 emitRRR(Opcode: Mips::ADDu, Reg0: TmpReg, Reg1: TmpReg, Reg2: BaseReg, IDLoc, STI);
389 // Emit the load with the adjusted base and offset.
390 emitRRI(Opcode, Reg0: DstReg, Reg1: TmpReg, Imm: LoOffset, IDLoc, STI);
391}
392
393MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S,
394 formatted_raw_ostream &OS)
395 : MipsTargetStreamer(S), OS(OS) {}
396
397void MipsTargetAsmStreamer::emitDTPRel32Value(const MCExpr *Value) {
398 auto *MAI = getStreamer().getContext().getAsmInfo();
399 OS << "\t.dtprelword\t";
400 MAI->printExpr(OS, *Value);
401 OS << '\n';
402}
403
404void MipsTargetAsmStreamer::emitDTPRel64Value(const MCExpr *Value) {
405 auto *MAI = getStreamer().getContext().getAsmInfo();
406 OS << "\t.dtpreldword\t";
407 MAI->printExpr(OS, *Value);
408 OS << '\n';
409}
410
411void MipsTargetAsmStreamer::emitTPRel32Value(const MCExpr *Value) {
412 auto *MAI = getStreamer().getContext().getAsmInfo();
413 OS << "\t.tprelword\t";
414 MAI->printExpr(OS, *Value);
415 OS << '\n';
416}
417
418void MipsTargetAsmStreamer::emitTPRel64Value(const MCExpr *Value) {
419 auto *MAI = getStreamer().getContext().getAsmInfo();
420 OS << "\t.tpreldword\t";
421 MAI->printExpr(OS, *Value);
422 OS << '\n';
423}
424
425void MipsTargetAsmStreamer::emitGPRel32Value(const MCExpr *Value) {
426 auto *MAI = getStreamer().getContext().getAsmInfo();
427 OS << "\t.gpword\t";
428 MAI->printExpr(OS, *Value);
429 OS << '\n';
430}
431
432void MipsTargetAsmStreamer::emitGPRel64Value(const MCExpr *Value) {
433 auto *MAI = getStreamer().getContext().getAsmInfo();
434 OS << "\t.gpdword\t";
435 MAI->printExpr(OS, *Value);
436 OS << '\n';
437}
438
439void MipsTargetAsmStreamer::emitDirectiveSetMicroMips() {
440 OS << "\t.set\tmicromips\n";
441 forbidModuleDirective();
442}
443
444void MipsTargetAsmStreamer::emitDirectiveSetNoMicroMips() {
445 OS << "\t.set\tnomicromips\n";
446 forbidModuleDirective();
447}
448
449void MipsTargetAsmStreamer::emitDirectiveSetMips16() {
450 OS << "\t.set\tmips16\n";
451 forbidModuleDirective();
452}
453
454void MipsTargetAsmStreamer::emitDirectiveSetNoMips16() {
455 OS << "\t.set\tnomips16\n";
456 MipsTargetStreamer::emitDirectiveSetNoMips16();
457}
458
459void MipsTargetAsmStreamer::emitDirectiveSetReorder() {
460 OS << "\t.set\treorder\n";
461 MipsTargetStreamer::emitDirectiveSetReorder();
462}
463
464void MipsTargetAsmStreamer::emitDirectiveSetNoReorder() {
465 OS << "\t.set\tnoreorder\n";
466 forbidModuleDirective();
467}
468
469void MipsTargetAsmStreamer::emitDirectiveSetMacro() {
470 OS << "\t.set\tmacro\n";
471 MipsTargetStreamer::emitDirectiveSetMacro();
472}
473
474void MipsTargetAsmStreamer::emitDirectiveSetNoMacro() {
475 OS << "\t.set\tnomacro\n";
476 MipsTargetStreamer::emitDirectiveSetNoMacro();
477}
478
479void MipsTargetAsmStreamer::emitDirectiveSetMsa() {
480 OS << "\t.set\tmsa\n";
481 MipsTargetStreamer::emitDirectiveSetMsa();
482}
483
484void MipsTargetAsmStreamer::emitDirectiveSetNoMsa() {
485 OS << "\t.set\tnomsa\n";
486 MipsTargetStreamer::emitDirectiveSetNoMsa();
487}
488
489void MipsTargetAsmStreamer::emitDirectiveSetMt() {
490 OS << "\t.set\tmt\n";
491 MipsTargetStreamer::emitDirectiveSetMt();
492}
493
494void MipsTargetAsmStreamer::emitDirectiveSetNoMt() {
495 OS << "\t.set\tnomt\n";
496 MipsTargetStreamer::emitDirectiveSetNoMt();
497}
498
499void MipsTargetAsmStreamer::emitDirectiveSetCRC() {
500 OS << "\t.set\tcrc\n";
501 MipsTargetStreamer::emitDirectiveSetCRC();
502}
503
504void MipsTargetAsmStreamer::emitDirectiveSetNoCRC() {
505 OS << "\t.set\tnocrc\n";
506 MipsTargetStreamer::emitDirectiveSetNoCRC();
507}
508
509void MipsTargetAsmStreamer::emitDirectiveSetVirt() {
510 OS << "\t.set\tvirt\n";
511 MipsTargetStreamer::emitDirectiveSetVirt();
512}
513
514void MipsTargetAsmStreamer::emitDirectiveSetNoVirt() {
515 OS << "\t.set\tnovirt\n";
516 MipsTargetStreamer::emitDirectiveSetNoVirt();
517}
518
519void MipsTargetAsmStreamer::emitDirectiveSetGINV() {
520 OS << "\t.set\tginv\n";
521 MipsTargetStreamer::emitDirectiveSetGINV();
522}
523
524void MipsTargetAsmStreamer::emitDirectiveSetNoGINV() {
525 OS << "\t.set\tnoginv\n";
526 MipsTargetStreamer::emitDirectiveSetNoGINV();
527}
528
529void MipsTargetAsmStreamer::emitDirectiveSetAt() {
530 OS << "\t.set\tat\n";
531 MipsTargetStreamer::emitDirectiveSetAt();
532}
533
534void MipsTargetAsmStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
535 OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
536 MipsTargetStreamer::emitDirectiveSetAtWithArg(RegNo);
537}
538
539void MipsTargetAsmStreamer::emitDirectiveSetNoAt() {
540 OS << "\t.set\tnoat\n";
541 MipsTargetStreamer::emitDirectiveSetNoAt();
542}
543
544void MipsTargetAsmStreamer::emitDirectiveEnd(StringRef Name) {
545 OS << "\t.end\t" << Name << '\n';
546}
547
548void MipsTargetAsmStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
549 OS << "\t.ent\t" << Symbol.getName() << '\n';
550}
551
552void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
553
554void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
555
556void MipsTargetAsmStreamer::emitDirectiveNaNLegacy() {
557 OS << "\t.nan\tlegacy\n";
558}
559
560void MipsTargetAsmStreamer::emitDirectiveOptionPic0() {
561 OS << "\t.option\tpic0\n";
562}
563
564void MipsTargetAsmStreamer::emitDirectiveOptionPic2() {
565 OS << "\t.option\tpic2\n";
566}
567
568void MipsTargetAsmStreamer::emitDirectiveInsn() {
569 MipsTargetStreamer::emitDirectiveInsn();
570 OS << "\t.insn\n";
571}
572
573void MipsTargetAsmStreamer::emitFrame(MCRegister StackReg, unsigned StackSize,
574 MCRegister ReturnReg) {
575 OS << "\t.frame\t$"
576 << StringRef(MipsInstPrinter::getRegisterName(Reg: StackReg)).lower() << ","
577 << StackSize << ",$"
578 << StringRef(MipsInstPrinter::getRegisterName(Reg: ReturnReg)).lower() << '\n';
579}
580
581void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
582 OS << "\t.set arch=" << Arch << "\n";
583 MipsTargetStreamer::emitDirectiveSetArch(Arch);
584}
585
586void MipsTargetAsmStreamer::emitDirectiveSetMips0() {
587 OS << "\t.set\tmips0\n";
588 MipsTargetStreamer::emitDirectiveSetMips0();
589}
590
591void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
592 OS << "\t.set\tmips1\n";
593 MipsTargetStreamer::emitDirectiveSetMips1();
594}
595
596void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
597 OS << "\t.set\tmips2\n";
598 MipsTargetStreamer::emitDirectiveSetMips2();
599}
600
601void MipsTargetAsmStreamer::emitDirectiveSetMips3() {
602 OS << "\t.set\tmips3\n";
603 MipsTargetStreamer::emitDirectiveSetMips3();
604}
605
606void MipsTargetAsmStreamer::emitDirectiveSetMips4() {
607 OS << "\t.set\tmips4\n";
608 MipsTargetStreamer::emitDirectiveSetMips4();
609}
610
611void MipsTargetAsmStreamer::emitDirectiveSetMips5() {
612 OS << "\t.set\tmips5\n";
613 MipsTargetStreamer::emitDirectiveSetMips5();
614}
615
616void MipsTargetAsmStreamer::emitDirectiveSetMips32() {
617 OS << "\t.set\tmips32\n";
618 MipsTargetStreamer::emitDirectiveSetMips32();
619}
620
621void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
622 OS << "\t.set\tmips32r2\n";
623 MipsTargetStreamer::emitDirectiveSetMips32R2();
624}
625
626void MipsTargetAsmStreamer::emitDirectiveSetMips32R3() {
627 OS << "\t.set\tmips32r3\n";
628 MipsTargetStreamer::emitDirectiveSetMips32R3();
629}
630
631void MipsTargetAsmStreamer::emitDirectiveSetMips32R5() {
632 OS << "\t.set\tmips32r5\n";
633 MipsTargetStreamer::emitDirectiveSetMips32R5();
634}
635
636void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() {
637 OS << "\t.set\tmips32r6\n";
638 MipsTargetStreamer::emitDirectiveSetMips32R6();
639}
640
641void MipsTargetAsmStreamer::emitDirectiveSetMips64() {
642 OS << "\t.set\tmips64\n";
643 MipsTargetStreamer::emitDirectiveSetMips64();
644}
645
646void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
647 OS << "\t.set\tmips64r2\n";
648 MipsTargetStreamer::emitDirectiveSetMips64R2();
649}
650
651void MipsTargetAsmStreamer::emitDirectiveSetMips64R3() {
652 OS << "\t.set\tmips64r3\n";
653 MipsTargetStreamer::emitDirectiveSetMips64R3();
654}
655
656void MipsTargetAsmStreamer::emitDirectiveSetMips64R5() {
657 OS << "\t.set\tmips64r5\n";
658 MipsTargetStreamer::emitDirectiveSetMips64R5();
659}
660
661void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() {
662 OS << "\t.set\tmips64r6\n";
663 MipsTargetStreamer::emitDirectiveSetMips64R6();
664}
665
666void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
667 OS << "\t.set\tdsp\n";
668 MipsTargetStreamer::emitDirectiveSetDsp();
669}
670
671void MipsTargetAsmStreamer::emitDirectiveSetDspr2() {
672 OS << "\t.set\tdspr2\n";
673 MipsTargetStreamer::emitDirectiveSetDspr2();
674}
675
676void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
677 OS << "\t.set\tnodsp\n";
678 MipsTargetStreamer::emitDirectiveSetNoDsp();
679}
680
681void MipsTargetAsmStreamer::emitDirectiveSetMips3D() {
682 OS << "\t.set\tmips3d\n";
683 MipsTargetStreamer::emitDirectiveSetMips3D();
684}
685
686void MipsTargetAsmStreamer::emitDirectiveSetNoMips3D() {
687 OS << "\t.set\tnomips3d\n";
688 MipsTargetStreamer::emitDirectiveSetNoMips3D();
689}
690
691void MipsTargetAsmStreamer::emitDirectiveSetPop() {
692 OS << "\t.set\tpop\n";
693 MipsTargetStreamer::emitDirectiveSetPop();
694}
695
696void MipsTargetAsmStreamer::emitDirectiveSetPush() {
697 OS << "\t.set\tpush\n";
698 MipsTargetStreamer::emitDirectiveSetPush();
699}
700
701void MipsTargetAsmStreamer::emitDirectiveSetSoftFloat() {
702 OS << "\t.set\tsoftfloat\n";
703 MipsTargetStreamer::emitDirectiveSetSoftFloat();
704}
705
706void MipsTargetAsmStreamer::emitDirectiveSetHardFloat() {
707 OS << "\t.set\thardfloat\n";
708 MipsTargetStreamer::emitDirectiveSetHardFloat();
709}
710
711// Print a 32 bit hex number with all numbers.
712static void printHex32(unsigned Value, raw_ostream &OS) {
713 OS << "0x";
714 for (int i = 7; i >= 0; i--)
715 OS.write_hex(N: (Value & (0xF << (i * 4))) >> (i * 4));
716}
717
718void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
719 int CPUTopSavedRegOff) {
720 OS << "\t.mask \t";
721 printHex32(Value: CPUBitmask, OS);
722 OS << ',' << CPUTopSavedRegOff << '\n';
723}
724
725void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
726 int FPUTopSavedRegOff) {
727 OS << "\t.fmask\t";
728 printHex32(Value: FPUBitmask, OS);
729 OS << "," << FPUTopSavedRegOff << '\n';
730}
731
732void MipsTargetAsmStreamer::emitDirectiveCpAdd(MCRegister Reg) {
733 OS << "\t.cpadd\t$"
734 << StringRef(MipsInstPrinter::getRegisterName(Reg)).lower() << "\n";
735 forbidModuleDirective();
736}
737
738void MipsTargetAsmStreamer::emitDirectiveCpLoad(MCRegister Reg) {
739 OS << "\t.cpload\t$"
740 << StringRef(MipsInstPrinter::getRegisterName(Reg)).lower() << "\n";
741 forbidModuleDirective();
742}
743
744void MipsTargetAsmStreamer::emitDirectiveCpLocal(MCRegister Reg) {
745 OS << "\t.cplocal\t$"
746 << StringRef(MipsInstPrinter::getRegisterName(Reg)).lower() << "\n";
747 MipsTargetStreamer::emitDirectiveCpLocal(Reg);
748}
749
750bool MipsTargetAsmStreamer::emitDirectiveCpRestore(
751 int Offset, function_ref<MCRegister()> GetATReg, SMLoc IDLoc,
752 const MCSubtargetInfo *STI) {
753 MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
754 OS << "\t.cprestore\t" << Offset << "\n";
755 return true;
756}
757
758void MipsTargetAsmStreamer::emitDirectiveCpsetup(MCRegister Reg,
759 int RegOrOffset,
760 const MCSymbol &Sym,
761 bool IsReg) {
762 OS << "\t.cpsetup\t$"
763 << StringRef(MipsInstPrinter::getRegisterName(Reg)).lower() << ", ";
764
765 if (IsReg)
766 OS << "$"
767 << StringRef(MipsInstPrinter::getRegisterName(Reg: RegOrOffset)).lower();
768 else
769 OS << RegOrOffset;
770
771 OS << ", ";
772
773 OS << Sym.getName();
774 forbidModuleDirective();
775}
776
777void MipsTargetAsmStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
778 bool SaveLocationIsRegister) {
779 OS << "\t.cpreturn";
780 forbidModuleDirective();
781}
782
783void MipsTargetAsmStreamer::emitDirectiveModuleFP() {
784 MipsABIFlagsSection::FpABIKind FpABI = ABIFlagsSection.getFpABI();
785 if (FpABI == MipsABIFlagsSection::FpABIKind::SOFT)
786 OS << "\t.module\tsoftfloat\n";
787 else
788 OS << "\t.module\tfp=" << ABIFlagsSection.getFpABIString(Value: FpABI) << "\n";
789}
790
791void MipsTargetAsmStreamer::emitDirectiveSetFp(
792 MipsABIFlagsSection::FpABIKind Value) {
793 MipsTargetStreamer::emitDirectiveSetFp(Value);
794
795 OS << "\t.set\tfp=";
796 OS << ABIFlagsSection.getFpABIString(Value) << "\n";
797}
798
799void MipsTargetAsmStreamer::emitDirectiveModuleOddSPReg() {
800 MipsTargetStreamer::emitDirectiveModuleOddSPReg();
801
802 OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? "" : "no") << "oddspreg\n";
803}
804
805void MipsTargetAsmStreamer::emitDirectiveSetOddSPReg() {
806 MipsTargetStreamer::emitDirectiveSetOddSPReg();
807 OS << "\t.set\toddspreg\n";
808}
809
810void MipsTargetAsmStreamer::emitDirectiveSetNoOddSPReg() {
811 MipsTargetStreamer::emitDirectiveSetNoOddSPReg();
812 OS << "\t.set\tnooddspreg\n";
813}
814
815void MipsTargetAsmStreamer::emitDirectiveModuleSoftFloat() {
816 OS << "\t.module\tsoftfloat\n";
817}
818
819void MipsTargetAsmStreamer::emitDirectiveModuleHardFloat() {
820 OS << "\t.module\thardfloat\n";
821}
822
823void MipsTargetAsmStreamer::emitDirectiveModuleMT() {
824 OS << "\t.module\tmt\n";
825}
826
827void MipsTargetAsmStreamer::emitDirectiveModuleCRC() {
828 OS << "\t.module\tcrc\n";
829}
830
831void MipsTargetAsmStreamer::emitDirectiveModuleNoCRC() {
832 OS << "\t.module\tnocrc\n";
833}
834
835void MipsTargetAsmStreamer::emitDirectiveModuleVirt() {
836 OS << "\t.module\tvirt\n";
837}
838
839void MipsTargetAsmStreamer::emitDirectiveModuleNoVirt() {
840 OS << "\t.module\tnovirt\n";
841}
842
843void MipsTargetAsmStreamer::emitDirectiveModuleGINV() {
844 OS << "\t.module\tginv\n";
845}
846
847void MipsTargetAsmStreamer::emitDirectiveModuleNoGINV() {
848 OS << "\t.module\tnoginv\n";
849}
850
851// This part is for ELF object output.
852MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
853 const MCSubtargetInfo &STI)
854 : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
855 MCAssembler &MCA = getStreamer().getAssembler();
856 ELFObjectWriter &W = getStreamer().getWriter();
857
858 // It's possible that MCObjectFileInfo isn't fully initialized at this point
859 // due to an initialization order problem where CodeGenTargetMachineImpl
860 // creates the target streamer before TargetLoweringObjectFile calls
861 // InitializeMCObjectFileInfo. There doesn't seem to be a single place that
862 // covers all cases so this statement covers most cases and direct object
863 // emission must call setPic() once MCObjectFileInfo has been initialized. The
864 // cases we don't handle here are covered by MipsAsmPrinter.
865 Pic = MCA.getContext().getObjectFileInfo()->isPositionIndependent();
866
867 const FeatureBitset &Features = STI.getFeatureBits();
868
869 // Set the header flags that we can in the constructor.
870 // FIXME: This is a fairly terrible hack. We set the rest
871 // of these in the destructor. The problem here is two-fold:
872 //
873 // a: Some of the eflags can be set/reset by directives.
874 // b: There aren't any usage paths that initialize the ABI
875 // pointer until after we initialize either an assembler
876 // or the target machine.
877 // We can fix this by making the target streamer construct
878 // the ABI, but this is fraught with wide ranging dependency
879 // issues as well.
880 unsigned EFlags = W.getELFHeaderEFlags();
881
882 // FIXME: Fix a dependency issue by instantiating the ABI object to some
883 // default based off the triple. The triple doesn't describe the target
884 // fully, but any external user of the API that uses the MCTargetStreamer
885 // would otherwise crash on assertion failure.
886
887 ABI = MipsABIInfo(
888 STI.getTargetTriple().getArch() == Triple::ArchType::mipsel ||
889 STI.getTargetTriple().getArch() == Triple::ArchType::mips
890 ? MipsABIInfo::O32()
891 : MipsABIInfo::N64());
892
893 // Architecture
894 if (Features[Mips::FeatureMips64r6])
895 EFlags |= ELF::EF_MIPS_ARCH_64R6;
896 else if (Features[Mips::FeatureMips64r2] ||
897 Features[Mips::FeatureMips64r3] ||
898 Features[Mips::FeatureMips64r5])
899 EFlags |= ELF::EF_MIPS_ARCH_64R2;
900 else if (Features[Mips::FeatureMips64])
901 EFlags |= ELF::EF_MIPS_ARCH_64;
902 else if (Features[Mips::FeatureMips5])
903 EFlags |= ELF::EF_MIPS_ARCH_5;
904 else if (Features[Mips::FeatureMips4])
905 EFlags |= ELF::EF_MIPS_ARCH_4;
906 else if (Features[Mips::FeatureMips3])
907 EFlags |= ELF::EF_MIPS_ARCH_3;
908 else if (Features[Mips::FeatureMips32r6])
909 EFlags |= ELF::EF_MIPS_ARCH_32R6;
910 else if (Features[Mips::FeatureMips32r2] ||
911 Features[Mips::FeatureMips32r3] ||
912 Features[Mips::FeatureMips32r5])
913 EFlags |= ELF::EF_MIPS_ARCH_32R2;
914 else if (Features[Mips::FeatureMips32])
915 EFlags |= ELF::EF_MIPS_ARCH_32;
916 else if (Features[Mips::FeatureMips2])
917 EFlags |= ELF::EF_MIPS_ARCH_2;
918 else
919 EFlags |= ELF::EF_MIPS_ARCH_1;
920
921 // Machine
922 if (Features[Mips::FeatureCnMips])
923 EFlags |= ELF::EF_MIPS_MACH_OCTEON;
924 else if (Features[Mips::FeatureR5900])
925 EFlags |= ELF::EF_MIPS_MACH_5900;
926
927 // Other options.
928 if (Features[Mips::FeatureNaN2008])
929 EFlags |= ELF::EF_MIPS_NAN2008;
930
931 W.setELFHeaderEFlags(EFlags);
932}
933
934void MipsTargetELFStreamer::emitLabel(MCSymbol *S) {
935 auto *Symbol = static_cast<MCSymbolELF *>(S);
936 getStreamer().getAssembler().registerSymbol(Symbol: *Symbol);
937 uint8_t Type = Symbol->getType();
938 if (Type != ELF::STT_FUNC)
939 return;
940
941 if (isMicroMipsEnabled())
942 Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
943}
944
945void MipsTargetELFStreamer::finish() {
946 MCAssembler &MCA = getStreamer().getAssembler();
947 ELFObjectWriter &W = getStreamer().getWriter();
948 const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
949 MCELFStreamer &S = getStreamer();
950
951 // .bss, .text and .data are always at least 16-byte aligned.
952 MCSection &TextSection = *OFI.getTextSection();
953 S.switchSection(Section: &TextSection);
954 MCSection &DataSection = *OFI.getDataSection();
955 S.switchSection(Section: &DataSection);
956 MCSection &BSSSection = *OFI.getBSSSection();
957 S.switchSection(Section: &BSSSection);
958
959 TextSection.ensureMinAlignment(MinAlignment: Align(16));
960 DataSection.ensureMinAlignment(MinAlignment: Align(16));
961 BSSSection.ensureMinAlignment(MinAlignment: Align(16));
962
963 if (RoundSectionSizes) {
964 // Make sections sizes a multiple of the alignment. This is useful for
965 // verifying the output of IAS against the output of other assemblers but
966 // it's not necessary to produce a correct object and increases section
967 // size.
968 for (MCSection &Sec : MCA) {
969 MCSectionELF &Section = static_cast<MCSectionELF &>(Sec);
970
971 Align Alignment = Section.getAlign();
972 S.switchSection(Section: &Section);
973 if (getContext().getAsmInfo()->useCodeAlign(Sec: Section))
974 S.emitCodeAlignment(ByteAlignment: Alignment, STI: &STI, MaxBytesToEmit: Alignment.value());
975 else
976 S.emitValueToAlignment(Alignment, Fill: 0, FillLen: 1, MaxBytesToEmit: Alignment.value());
977 }
978 }
979
980 const FeatureBitset &Features = STI.getFeatureBits();
981
982 // Update e_header flags. See the FIXME and comment above in
983 // the constructor for a full rundown on this.
984 unsigned EFlags = W.getELFHeaderEFlags();
985
986 // ABI
987 // N64 does not require any ABI bits.
988 if (getABI().IsO32())
989 EFlags |= ELF::EF_MIPS_ABI_O32;
990 else if (getABI().IsN32())
991 EFlags |= ELF::EF_MIPS_ABI2;
992
993 if (Features[Mips::FeatureGP64Bit]) {
994 if (getABI().IsO32())
995 EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
996 } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
997 EFlags |= ELF::EF_MIPS_32BITMODE;
998
999 // -mplt is not implemented but we should act as if it was
1000 // given.
1001 if (!Features[Mips::FeatureNoABICalls])
1002 EFlags |= ELF::EF_MIPS_CPIC;
1003
1004 if (Pic)
1005 EFlags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
1006
1007 W.setELFHeaderEFlags(EFlags);
1008
1009 // Emit all the option records.
1010 // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
1011 // .reginfo.
1012 MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
1013 MEF.EmitMipsOptionRecords();
1014
1015 emitMipsAbiFlags();
1016}
1017
1018void MipsTargetELFStreamer::emitAssignment(MCSymbol *S, const MCExpr *Value) {
1019 auto *Symbol = static_cast<MCSymbolELF *>(S);
1020 // If on rhs is micromips symbol then mark Symbol as microMips.
1021 if (Value->getKind() != MCExpr::SymbolRef)
1022 return;
1023 auto &RhsSym = static_cast<const MCSymbolELF &>(
1024 static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
1025
1026 if (!(RhsSym.getOther() & ELF::STO_MIPS_MICROMIPS))
1027 return;
1028
1029 Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
1030}
1031
1032MCELFStreamer &MipsTargetELFStreamer::getStreamer() {
1033 return static_cast<MCELFStreamer &>(Streamer);
1034}
1035
1036void MipsTargetELFStreamer::emitGPRel32Value(const MCExpr *Value) {
1037 auto &S = getStreamer();
1038 S.ensureHeadroom(Headroom: 4);
1039 S.addFixup(Value, Kind: Mips::fixup_Mips_GPREL32);
1040 S.appendContents(Num: 4, Elt: 0);
1041}
1042
1043void MipsTargetELFStreamer::emitGPRel64Value(const MCExpr *Value) {
1044 auto &S = getStreamer();
1045 S.ensureHeadroom(Headroom: 8);
1046 // fixup_Mips_GPREL32 desginates R_MIPS_GPREL32+R_MIPS_64 on MIPS64.
1047 S.addFixup(Value, Kind: Mips::fixup_Mips_GPREL32);
1048 S.appendContents(Num: 8, Elt: 0);
1049}
1050
1051void MipsTargetELFStreamer::emitDTPRel32Value(const MCExpr *Value) {
1052 auto &S = getStreamer();
1053 S.ensureHeadroom(Headroom: 4);
1054 S.addFixup(Value, Kind: Mips::fixup_Mips_DTPREL32);
1055 S.appendContents(Num: 4, Elt: 0);
1056}
1057
1058void MipsTargetELFStreamer::emitDTPRel64Value(const MCExpr *Value) {
1059 auto &S = getStreamer();
1060 S.ensureHeadroom(Headroom: 8);
1061 S.addFixup(Value, Kind: Mips::fixup_Mips_DTPREL64);
1062 S.appendContents(Num: 8, Elt: 0);
1063}
1064
1065void MipsTargetELFStreamer::emitTPRel32Value(const MCExpr *Value) {
1066 auto &S = getStreamer();
1067 S.ensureHeadroom(Headroom: 4);
1068 S.addFixup(Value, Kind: Mips::fixup_Mips_TPREL32);
1069 S.appendContents(Num: 4, Elt: 0);
1070}
1071
1072void MipsTargetELFStreamer::emitTPRel64Value(const MCExpr *Value) {
1073 auto &S = getStreamer();
1074 S.ensureHeadroom(Headroom: 8);
1075 S.addFixup(Value, Kind: Mips::fixup_Mips_TPREL64);
1076 S.appendContents(Num: 8, Elt: 0);
1077}
1078
1079void MipsTargetELFStreamer::emitDirectiveSetMicroMips() {
1080 MicroMipsEnabled = true;
1081 forbidModuleDirective();
1082}
1083
1084void MipsTargetELFStreamer::emitDirectiveSetNoMicroMips() {
1085 MicroMipsEnabled = false;
1086 forbidModuleDirective();
1087}
1088
1089void MipsTargetELFStreamer::setUsesMicroMips() {
1090 ELFObjectWriter &W = getStreamer().getWriter();
1091 unsigned Flags = W.getELFHeaderEFlags();
1092 Flags |= ELF::EF_MIPS_MICROMIPS;
1093 W.setELFHeaderEFlags(Flags);
1094}
1095
1096void MipsTargetELFStreamer::emitDirectiveSetMips16() {
1097 ELFObjectWriter &W = getStreamer().getWriter();
1098 unsigned Flags = W.getELFHeaderEFlags();
1099 Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
1100 W.setELFHeaderEFlags(Flags);
1101 forbidModuleDirective();
1102}
1103
1104void MipsTargetELFStreamer::emitDirectiveSetNoReorder() {
1105 ELFObjectWriter &W = getStreamer().getWriter();
1106 unsigned Flags = W.getELFHeaderEFlags();
1107 Flags |= ELF::EF_MIPS_NOREORDER;
1108 W.setELFHeaderEFlags(Flags);
1109 forbidModuleDirective();
1110}
1111
1112void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) {
1113 MCAssembler &MCA = getStreamer().getAssembler();
1114 MCContext &Context = MCA.getContext();
1115 MCStreamer &OS = getStreamer();
1116
1117 OS.pushSection();
1118 MCSectionELF *Sec = Context.getELFSection(Section: ".pdr", Type: ELF::SHT_PROGBITS, Flags: 0);
1119 OS.switchSection(Section: Sec);
1120 Sec->setAlignment(Align(4));
1121
1122 MCSymbol *Sym = Context.getOrCreateSymbol(Name);
1123 const auto *ExprRef = MCSymbolRefExpr::create(Symbol: Sym, Ctx&: Context);
1124 OS.emitValueImpl(Value: ExprRef, Size: 4);
1125
1126 OS.emitIntValue(Value: GPRInfoSet ? GPRBitMask : 0, Size: 4); // reg_mask
1127 OS.emitIntValue(Value: GPRInfoSet ? GPROffset : 0, Size: 4); // reg_offset
1128
1129 OS.emitIntValue(Value: FPRInfoSet ? FPRBitMask : 0, Size: 4); // fpreg_mask
1130 OS.emitIntValue(Value: FPRInfoSet ? FPROffset : 0, Size: 4); // fpreg_offset
1131
1132 OS.emitIntValue(Value: FrameInfoSet ? FrameOffset : 0, Size: 4); // frame_offset
1133 OS.emitIntValue(Value: FrameInfoSet ? FrameReg : 0, Size: 4); // frame_reg
1134 OS.emitIntValue(Value: FrameInfoSet ? ReturnReg : 0, Size: 4); // return_reg
1135
1136 // The .end directive marks the end of a procedure. Invalidate
1137 // the information gathered up until this point.
1138 GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1139
1140 OS.popSection();
1141
1142 // .end also implicitly sets the size.
1143 MCSymbol *CurPCSym = Context.createTempSymbol();
1144 OS.emitLabel(Symbol: CurPCSym);
1145 const MCExpr *Size = MCBinaryExpr::createSub(
1146 LHS: MCSymbolRefExpr::create(Symbol: CurPCSym, Ctx&: Context), RHS: ExprRef, Ctx&: Context);
1147
1148 // The ELFObjectWriter can determine the absolute size as it has access to
1149 // the layout information of the assembly file, so a size expression rather
1150 // than an absolute value is ok here.
1151 static_cast<MCSymbolELF *>(Sym)->setSize(Size);
1152}
1153
1154void MipsTargetELFStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
1155 GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1156
1157 // .ent also acts like an implicit '.type symbol, STT_FUNC'
1158 static_cast<const MCSymbolELF &>(Symbol).setType(ELF::STT_FUNC);
1159}
1160
1161void MipsTargetELFStreamer::emitDirectiveAbiCalls() {
1162 ELFObjectWriter &W = getStreamer().getWriter();
1163 unsigned Flags = W.getELFHeaderEFlags();
1164 Flags |= ELF::EF_MIPS_CPIC | ELF::EF_MIPS_PIC;
1165 W.setELFHeaderEFlags(Flags);
1166}
1167
1168void MipsTargetELFStreamer::emitDirectiveNaN2008() {
1169 ELFObjectWriter &W = getStreamer().getWriter();
1170 unsigned Flags = W.getELFHeaderEFlags();
1171 Flags |= ELF::EF_MIPS_NAN2008;
1172 W.setELFHeaderEFlags(Flags);
1173}
1174
1175void MipsTargetELFStreamer::emitDirectiveNaNLegacy() {
1176 ELFObjectWriter &W = getStreamer().getWriter();
1177 unsigned Flags = W.getELFHeaderEFlags();
1178 Flags &= ~ELF::EF_MIPS_NAN2008;
1179 W.setELFHeaderEFlags(Flags);
1180}
1181
1182void MipsTargetELFStreamer::emitDirectiveOptionPic0() {
1183 ELFObjectWriter &W = getStreamer().getWriter();
1184 unsigned Flags = W.getELFHeaderEFlags();
1185 // This option overrides other PIC options like -KPIC.
1186 Pic = false;
1187 Flags &= ~ELF::EF_MIPS_PIC;
1188 W.setELFHeaderEFlags(Flags);
1189}
1190
1191void MipsTargetELFStreamer::emitDirectiveOptionPic2() {
1192 ELFObjectWriter &W = getStreamer().getWriter();
1193 unsigned Flags = W.getELFHeaderEFlags();
1194 Pic = true;
1195 // NOTE: We are following the GAS behaviour here which means the directive
1196 // 'pic2' also sets the CPIC bit in the ELF header. This is different from
1197 // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
1198 // EF_MIPS_CPIC to be mutually exclusive.
1199 Flags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
1200 W.setELFHeaderEFlags(Flags);
1201}
1202
1203void MipsTargetELFStreamer::emitDirectiveInsn() {
1204 MipsTargetStreamer::emitDirectiveInsn();
1205 MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
1206 MEF.createPendingLabelRelocs();
1207}
1208
1209void MipsTargetELFStreamer::emitFrame(MCRegister StackReg, unsigned StackSize,
1210 MCRegister ReturnReg_) {
1211 MCContext &Context = getStreamer().getAssembler().getContext();
1212 const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
1213
1214 FrameInfoSet = true;
1215 FrameReg = RegInfo->getEncodingValue(Reg: StackReg);
1216 FrameOffset = StackSize;
1217 ReturnReg = RegInfo->getEncodingValue(Reg: ReturnReg_);
1218}
1219
1220void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
1221 int CPUTopSavedRegOff) {
1222 GPRInfoSet = true;
1223 GPRBitMask = CPUBitmask;
1224 GPROffset = CPUTopSavedRegOff;
1225}
1226
1227void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
1228 int FPUTopSavedRegOff) {
1229 FPRInfoSet = true;
1230 FPRBitMask = FPUBitmask;
1231 FPROffset = FPUTopSavedRegOff;
1232}
1233
1234void MipsTargetELFStreamer::emitDirectiveCpAdd(MCRegister Reg) {
1235 // .cpadd $reg
1236 // This directive inserts code to add $gp to the argument's register
1237 // when support for position independent code is enabled.
1238 if (!Pic)
1239 return;
1240
1241 emitAddu(DstReg: Reg, SrcReg: Reg, TrgReg: GPReg, Is64Bit: getABI().IsN64(), STI: &STI);
1242 forbidModuleDirective();
1243}
1244
1245void MipsTargetELFStreamer::emitDirectiveCpLoad(MCRegister Reg) {
1246 // .cpload $reg
1247 // This directive expands to:
1248 // lui $gp, %hi(_gp_disp)
1249 // addui $gp, $gp, %lo(_gp_disp)
1250 // addu $gp, $gp, $reg
1251 // when support for position independent code is enabled.
1252 if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1253 return;
1254
1255 // There's a GNU extension controlled by -mno-shared that allows
1256 // locally-binding symbols to be accessed using absolute addresses.
1257 // This is currently not supported. When supported -mno-shared makes
1258 // .cpload expand to:
1259 // lui $gp, %hi(__gnu_local_gp)
1260 // addiu $gp, $gp, %lo(__gnu_local_gp)
1261
1262 StringRef SymName("_gp_disp");
1263 MCAssembler &MCA = getStreamer().getAssembler();
1264 MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(Name: SymName);
1265 MCA.registerSymbol(Symbol: *GP_Disp);
1266
1267 MCInst TmpInst;
1268 TmpInst.setOpcode(Mips::LUi);
1269 TmpInst.addOperand(Op: MCOperand::createReg(Reg: GPReg));
1270 auto *HiSym = MCSpecifierExpr::create(Sym: GP_Disp, S: Mips::S_HI, Ctx&: MCA.getContext());
1271 TmpInst.addOperand(Op: MCOperand::createExpr(Val: HiSym));
1272 getStreamer().emitInstruction(Inst: TmpInst, STI);
1273
1274 TmpInst.clear();
1275
1276 TmpInst.setOpcode(Mips::ADDiu);
1277 TmpInst.addOperand(Op: MCOperand::createReg(Reg: GPReg));
1278 TmpInst.addOperand(Op: MCOperand::createReg(Reg: GPReg));
1279 auto *LoSym = MCSpecifierExpr::create(Sym: GP_Disp, S: Mips::S_LO, Ctx&: MCA.getContext());
1280 TmpInst.addOperand(Op: MCOperand::createExpr(Val: LoSym));
1281 getStreamer().emitInstruction(Inst: TmpInst, STI);
1282
1283 TmpInst.clear();
1284
1285 TmpInst.setOpcode(Mips::ADDu);
1286 TmpInst.addOperand(Op: MCOperand::createReg(Reg: GPReg));
1287 TmpInst.addOperand(Op: MCOperand::createReg(Reg: GPReg));
1288 TmpInst.addOperand(Op: MCOperand::createReg(Reg));
1289 getStreamer().emitInstruction(Inst: TmpInst, STI);
1290
1291 forbidModuleDirective();
1292}
1293
1294void MipsTargetELFStreamer::emitDirectiveCpLocal(MCRegister Reg) {
1295 if (Pic)
1296 MipsTargetStreamer::emitDirectiveCpLocal(Reg);
1297}
1298
1299bool MipsTargetELFStreamer::emitDirectiveCpRestore(
1300 int Offset, function_ref<MCRegister()> GetATReg, SMLoc IDLoc,
1301 const MCSubtargetInfo *STI) {
1302 MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
1303 // .cprestore offset
1304 // When PIC mode is enabled and the O32 ABI is used, this directive expands
1305 // to:
1306 // sw $gp, offset($sp)
1307 // and adds a corresponding LW after every JAL.
1308
1309 // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
1310 // is used in non-PIC mode.
1311 if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1312 return true;
1313
1314 // Store the $gp on the stack.
1315 emitStoreWithImmOffset(Opcode: Mips::SW, SrcReg: GPReg, BaseReg: Mips::SP, Offset, GetATReg, IDLoc,
1316 STI);
1317 return true;
1318}
1319
1320void MipsTargetELFStreamer::emitDirectiveCpsetup(MCRegister Reg,
1321 int RegOrOffset,
1322 const MCSymbol &Sym,
1323 bool IsReg) {
1324 // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
1325 if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1326 return;
1327
1328 forbidModuleDirective();
1329
1330 MCAssembler &MCA = getStreamer().getAssembler();
1331 MCInst Inst;
1332
1333 // Either store the old $gp in a register or on the stack
1334 if (IsReg) {
1335 // move $save, $gpreg
1336 emitRRR(Opcode: Mips::OR64, Reg0: RegOrOffset, Reg1: GPReg, Reg2: Mips::ZERO, IDLoc: SMLoc(), STI: &STI);
1337 } else {
1338 // sd $gpreg, offset($sp)
1339 emitRRI(Opcode: Mips::SD, Reg0: GPReg, Reg1: Mips::SP, Imm: RegOrOffset, IDLoc: SMLoc(), STI: &STI);
1340 }
1341
1342 auto *HiExpr =
1343 Mips::createGpOff(Expr: MCSymbolRefExpr::create(Symbol: &Sym, Ctx&: MCA.getContext()),
1344 S: Mips::S_HI, Ctx&: MCA.getContext());
1345 auto *LoExpr =
1346 Mips::createGpOff(Expr: MCSymbolRefExpr::create(Symbol: &Sym, Ctx&: MCA.getContext()),
1347 S: Mips::S_LO, Ctx&: MCA.getContext());
1348
1349 // lui $gp, %hi(%neg(%gp_rel(funcSym)))
1350 emitRX(Opcode: Mips::LUi, Reg0: GPReg, Op1: MCOperand::createExpr(Val: HiExpr), IDLoc: SMLoc(), STI: &STI);
1351
1352 // addiu $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
1353 emitRRX(Opcode: Mips::ADDiu, Reg0: GPReg, Reg1: GPReg, Op2: MCOperand::createExpr(Val: LoExpr), IDLoc: SMLoc(),
1354 STI: &STI);
1355
1356 // (d)addu $gp, $gp, $funcreg
1357 if (getABI().IsN32())
1358 emitRRR(Opcode: Mips::ADDu, Reg0: GPReg, Reg1: GPReg, Reg2: Reg, IDLoc: SMLoc(), STI: &STI);
1359 else
1360 emitRRR(Opcode: Mips::DADDu, Reg0: GPReg, Reg1: GPReg, Reg2: Reg, IDLoc: SMLoc(), STI: &STI);
1361}
1362
1363void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
1364 bool SaveLocationIsRegister) {
1365 // Only N32 and N64 emit anything for .cpreturn iff PIC is set.
1366 if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1367 return;
1368
1369 MCInst Inst;
1370 // Either restore the old $gp from a register or on the stack
1371 if (SaveLocationIsRegister) {
1372 Inst.setOpcode(Mips::OR);
1373 Inst.addOperand(Op: MCOperand::createReg(Reg: GPReg));
1374 Inst.addOperand(Op: MCOperand::createReg(Reg: SaveLocation));
1375 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::ZERO));
1376 } else {
1377 Inst.setOpcode(Mips::LD);
1378 Inst.addOperand(Op: MCOperand::createReg(Reg: GPReg));
1379 Inst.addOperand(Op: MCOperand::createReg(Reg: Mips::SP));
1380 Inst.addOperand(Op: MCOperand::createImm(Val: SaveLocation));
1381 }
1382 getStreamer().emitInstruction(Inst, STI);
1383
1384 forbidModuleDirective();
1385}
1386
1387void MipsTargetELFStreamer::emitMipsAbiFlags() {
1388 MCAssembler &MCA = getStreamer().getAssembler();
1389 MCContext &Context = MCA.getContext();
1390 MCStreamer &OS = getStreamer();
1391 MCSectionELF *Sec = Context.getELFSection(
1392 Section: ".MIPS.abiflags", Type: ELF::SHT_MIPS_ABIFLAGS, Flags: ELF::SHF_ALLOC, EntrySize: 24);
1393 OS.switchSection(Section: Sec);
1394 Sec->setAlignment(Align(8));
1395
1396 OS << ABIFlagsSection;
1397}
1398