1//===- NVPTXSubtarget.cpp - NVPTX Subtarget Information -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the NVPTX specific subclass of TargetSubtarget.
10//
11//===----------------------------------------------------------------------===//
12
13#include "NVPTXSubtarget.h"
14#include "NVPTXSelectionDAGInfo.h"
15#include "NVPTXTargetMachine.h"
16#include "llvm/Support/ErrorHandling.h"
17#include "llvm/Support/FormatVariadic.h"
18
19using namespace llvm;
20
21#define DEBUG_TYPE "nvptx-subtarget"
22
23#define GET_SUBTARGETINFO_TARGET_DESC
24#define GET_SUBTARGETINFO_CTOR
25#include "NVPTXGenSubtargetInfo.inc"
26
27static cl::opt<bool>
28 NoF16Math("nvptx-no-f16-math", cl::Hidden,
29 cl::desc("NVPTX Specific: Disable generation of f16 math ops."),
30 cl::init(Val: false));
31
32static cl::opt<bool> NoF32x2("nvptx-no-f32x2", cl::Hidden,
33 cl::desc("NVPTX Specific: Disable generation of "
34 "f32x2 instructions and registers."),
35 cl::init(Val: false));
36
37// Pin the vtable to this file.
38void NVPTXSubtarget::anchor() {}
39
40// Returns the minimum PTX version required for a given SM target.
41// This must be kept in sync with the "Supported Targets" column of the
42// "PTX Release History" table in the PTX ISA documentation:
43// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#release-notes-ptx-release-history
44//
45// Note: LLVM's minimum supported PTX version is 3.2 (see FeaturePTX in
46// NVPTX.td), so older SMs that supported earlier PTX versions instead use 3.2
47// as their effective minimum.
48//
49// Note: sm_110* is the PTX ISA 9.0 spelling of sm_101*, which was introduced in
50// PTX ISA 8.6 (sm_101f in 8.8) and renamed in 9.0. Since getTargetName()
51// rewrites the new spelling back to the old one when emitting older PTX, the
52// sm_110* names work with any PTX version that supported sm_101*, so they take
53// sm_101*'s minimum PTX version rather than the 9.0 of the rename.
54static unsigned minPTXVersion(NVPTX::GPUKind Arch) {
55 switch (Arch) {
56 case NVPTX::GK_NONE:
57 llvm_unreachable("architecture is resolved before this is reached");
58 case NVPTX::GK_SM_20:
59 case NVPTX::GK_SM_21:
60 case NVPTX::GK_SM_30:
61 case NVPTX::GK_SM_35:
62 return 32;
63 case NVPTX::GK_SM_32_:
64 case NVPTX::GK_SM_50:
65 return 40;
66 case NVPTX::GK_SM_37:
67 case NVPTX::GK_SM_52:
68 return 41;
69 case NVPTX::GK_SM_53:
70 return 42;
71 case NVPTX::GK_SM_60:
72 case NVPTX::GK_SM_61:
73 case NVPTX::GK_SM_62:
74 return 50;
75 case NVPTX::GK_SM_70:
76 return 60;
77 case NVPTX::GK_SM_72:
78 return 61;
79 case NVPTX::GK_SM_75:
80 return 63;
81 case NVPTX::GK_SM_80:
82 return 70;
83 case NVPTX::GK_SM_86:
84 return 71;
85 case NVPTX::GK_SM_87:
86 return 74;
87 case NVPTX::GK_SM_89:
88 case NVPTX::GK_SM_90:
89 return 78;
90 case NVPTX::GK_SM_90a:
91 return 80;
92 case NVPTX::GK_SM_100:
93 case NVPTX::GK_SM_100a:
94 case NVPTX::GK_SM_101:
95 case NVPTX::GK_SM_101a:
96 case NVPTX::GK_SM_110:
97 case NVPTX::GK_SM_110a:
98 return 86;
99 case NVPTX::GK_SM_120:
100 case NVPTX::GK_SM_120a:
101 return 87;
102 case NVPTX::GK_SM_100f:
103 case NVPTX::GK_SM_101f:
104 case NVPTX::GK_SM_103:
105 case NVPTX::GK_SM_103f:
106 case NVPTX::GK_SM_103a:
107 case NVPTX::GK_SM_110f:
108 case NVPTX::GK_SM_120f:
109 case NVPTX::GK_SM_121:
110 case NVPTX::GK_SM_121f:
111 case NVPTX::GK_SM_121a:
112 return 88;
113 case NVPTX::GK_SM_88:
114 return 90;
115 case NVPTX::GK_SM_107:
116 case NVPTX::GK_SM_107f:
117 case NVPTX::GK_SM_107a:
118 return 94;
119 }
120 llvm_unreachable("invalid NVPTX GPUKind");
121}
122
123StringRef NVPTXSubtarget::getTargetName() const {
124 // Spell sm_110* as sm_101* when emitting PTX older than 9.0, which does not
125 // know the new names. See the note above minPTXVersion().
126 if (!hasFeature(Feature: NVPTX::PTX90))
127 switch (Arch) {
128 case NVPTX::GK_SM_110:
129 return "sm_101";
130 case NVPTX::GK_SM_110f:
131 return "sm_101f";
132 case NVPTX::GK_SM_110a:
133 return "sm_101a";
134 default:
135 break;
136 }
137
138 return NVPTX::getArchName(Kind: Arch);
139}
140
141NVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU,
142 StringRef FS) {
143 // If the user did not provide a target we default to the `sm_75` target.
144 StringRef RequestedCPU = CPU.empty() ? StringRef("sm_75") : CPU;
145 ParseSubtargetFeatures(CPU: RequestedCPU, /*TuneCPU=*/RequestedCPU, FS);
146
147 Arch = NVPTX::parseArch(CPU: RequestedCPU);
148
149 // An unrecognized name has already been diagnosed and its features dropped,
150 // leaving the subtarget at the oldest architecture, so name it that.
151 if (Arch == NVPTX::GK_NONE)
152 Arch = NVPTX::GK_SM_20;
153
154 unsigned MinPTX = minPTXVersion(Arch);
155
156 if (PTXVersion == 0) {
157 // User didn't request a specific PTX version; use the minimum for this SM.
158 ApplyFeatureFlag(FS: ("+ptx" + Twine(MinPTX)).str());
159 PTXVersion = MinPTX;
160 } else if (PTXVersion < MinPTX) {
161 // User explicitly requested an insufficient PTX version.
162 reportFatalUsageError(
163 reason: formatv(Fmt: "PTX version {0}.{1} does not support target '{2}'. "
164 "Minimum required PTX version is {3}.{4}. "
165 "Either remove the PTX version to use the default, "
166 "or increase it to at least {3}.{4}.",
167 Vals: PTXVersion / 10, Vals: PTXVersion % 10, Vals&: RequestedCPU, Vals: MinPTX / 10,
168 Vals: MinPTX % 10));
169 }
170
171 return *this;
172}
173
174NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
175 const NVPTXTargetMachine &TM)
176 : NVPTXGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), PTXVersion(0),
177 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
178 TSInfo(std::make_unique<NVPTXSelectionDAGInfo>()) {}
179
180NVPTXSubtarget::~NVPTXSubtarget() = default;
181
182bool NVPTXSubtarget::allowFP16Math() const {
183 return hasFP16Math() && NoF16Math == false;
184}
185
186bool NVPTXSubtarget::hasF32x2Instructions() const {
187 return hasFeature(Feature: NVPTX::SM100) && !NoF32x2;
188}
189
190bool NVPTXSubtarget::hasNativeBF16Support(unsigned Opcode) const {
191 if (!hasBF16Math())
192 return false;
193
194 switch (Opcode) {
195 // Several BF16 instructions are available on sm_90 only.
196 case ISD::FADD:
197 case ISD::FMUL:
198 case ISD::FSUB:
199 case ISD::SELECT:
200 case ISD::SELECT_CC:
201 case ISD::SETCC:
202 case ISD::FEXP2:
203 case ISD::FTANH:
204 case ISD::FCEIL:
205 case ISD::FFLOOR:
206 case ISD::FNEARBYINT:
207 case ISD::FRINT:
208 case ISD::FROUNDEVEN:
209 case ISD::FTRUNC:
210 return hasFeature(Feature: NVPTX::SM90);
211 // Several BF16 instructions are available on sm_80 only.
212 case ISD::FMINNUM:
213 case ISD::FMAXNUM:
214 case ISD::FMAXNUM_IEEE:
215 case ISD::FMINNUM_IEEE:
216 case ISD::FMAXIMUM:
217 case ISD::FMINIMUM:
218 return hasFeature(Feature: NVPTX::SM80);
219 }
220 return true;
221}
222