1//===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Top-level implementation for the NVPTX target.
10//
11//===----------------------------------------------------------------------===//
12
13#include "NVPTXTargetMachine.h"
14#include "NVPTX.h"
15#include "NVPTXAliasAnalysis.h"
16#include "NVPTXAllocaHoisting.h"
17#include "NVPTXAtomicLower.h"
18#include "NVPTXCtorDtorLowering.h"
19#include "NVPTXLowerAggrCopies.h"
20#include "NVPTXMachineFunctionInfo.h"
21#include "NVPTXTargetObjectFile.h"
22#include "NVPTXTargetTransformInfo.h"
23#include "TargetInfo/NVPTXTargetInfo.h"
24#include "llvm/Analysis/KernelInfo.h"
25#include "llvm/Analysis/TargetTransformInfo.h"
26#include "llvm/CodeGen/Passes.h"
27#include "llvm/CodeGen/TargetPassConfig.h"
28#include "llvm/IR/IntrinsicsNVPTX.h"
29#include "llvm/MC/TargetRegistry.h"
30#include "llvm/Pass.h"
31#include "llvm/Passes/PassBuilder.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/Compiler.h"
34#include "llvm/Target/TargetMachine.h"
35#include "llvm/Target/TargetOptions.h"
36#include "llvm/TargetParser/Triple.h"
37#include "llvm/Transforms/IPO/ExpandVariadics.h"
38#include "llvm/Transforms/Scalar.h"
39#include "llvm/Transforms/Scalar/GVN.h"
40#include "llvm/Transforms/Vectorize/LoadStoreVectorizer.h"
41#include <cassert>
42#include <optional>
43#include <string>
44
45using namespace llvm;
46
47// LSV is still relatively new; this switch lets us turn it off in case we
48// encounter (or suspect) a bug.
49static cl::opt<bool>
50 DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer",
51 cl::desc("Disable load/store vectorizer"),
52 cl::init(Val: false), cl::Hidden);
53
54// NVPTX IR Peephole is a new pass; this option will lets us turn it off in case
55// we encounter some issues.
56static cl::opt<bool>
57 DisableNVPTXIRPeephole("disable-nvptx-ir-peephole",
58 cl::desc("Disable NVPTX IR Peephole"),
59 cl::init(Val: false), cl::Hidden);
60
61// TODO: Remove this flag when we are confident with no regressions.
62static cl::opt<bool> DisableRequireStructuredCFG(
63 "disable-nvptx-require-structured-cfg",
64 cl::desc("Transitional flag to turn off NVPTX's requirement on preserving "
65 "structured CFG. The requirement should be disabled only when "
66 "unexpected regressions happen."),
67 cl::init(Val: false), cl::Hidden);
68
69static cl::opt<bool> UseShortPointersOpt(
70 "nvptx-short-ptr",
71 cl::desc(
72 "Use 32-bit pointers for accessing const/local/shared address spaces."),
73 cl::init(Val: false), cl::Hidden);
74
75// byval arguments in NVPTX are special. We're only allowed to read from them
76// using a special instruction, and if we ever need to write to them or take an
77// address, we must make a local copy and use it, instead.
78//
79// The problem is that local copies are very expensive, and we create them very
80// late in the compilation pipeline, so LLVM does not have much of a chance to
81// eliminate them, if they turn out to be unnecessary.
82//
83// One way around that is to create such copies early on, and let them percolate
84// through the optimizations. The copying itself will never trigger creation of
85// another copy later on, as the reads are allowed. If LLVM can eliminate it,
86// it's a win. It the full optimization pipeline can't remove the copy, that's
87// as good as it gets in terms of the effort we could've done, and it's
88// certainly a much better effort than what we do now.
89//
90// This early injection of the copies has potential to create undesireable
91// side-effects, so it's disabled by default, for now, until it sees more
92// testing.
93static cl::opt<bool> EarlyByValArgsCopy(
94 "nvptx-early-byval-copy",
95 cl::desc("Create a copy of byval function arguments early."),
96 cl::init(Val: false), cl::Hidden);
97
98extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTarget() {
99 // Register the target.
100 RegisterTargetMachine<NVPTXTargetMachine32> X(getTheNVPTXTarget32());
101 RegisterTargetMachine<NVPTXTargetMachine64> Y(getTheNVPTXTarget64());
102
103 PassRegistry &PR = *PassRegistry::getPassRegistry();
104 // FIXME: This pass is really intended to be invoked during IR optimization,
105 // but it's very NVPTX-specific.
106 initializeNVVMReflectLegacyPassPass(PR);
107 initializeNVVMIntrRangePass(PR);
108 initializeGenericToNVVMLegacyPassPass(PR);
109 initializeNVPTXAllocaHoistingPass(PR);
110 initializeNVPTXAsmPrinterPass(PR);
111 initializeNVPTXAssignValidGlobalNamesPass(PR);
112 initializeNVPTXAtomicLowerPass(PR);
113 initializeNVPTXLowerArgsLegacyPassPass(PR);
114 initializeNVPTXLowerAllocaPass(PR);
115 initializeNVPTXLowerUnreachablePass(PR);
116 initializeNVPTXCtorDtorLoweringLegacyPass(PR);
117 initializeNVPTXLowerAggrCopiesPass(PR);
118 initializeNVPTXProxyRegErasurePass(PR);
119 initializeNVPTXForwardParamsPassPass(PR);
120 initializeNVPTXDAGToDAGISelLegacyPass(PR);
121 initializeNVPTXAAWrapperPassPass(PR);
122 initializeNVPTXExternalAAWrapperPass(PR);
123 initializeNVPTXPeepholePass(PR);
124 initializeNVPTXTagInvariantLoadLegacyPassPass(PR);
125 initializeNVPTXIRPeepholePass(PR);
126 initializeNVPTXPrologEpilogPassPass(PR);
127}
128
129NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,
130 StringRef CPU, StringRef FS,
131 const TargetOptions &Options,
132 std::optional<Reloc::Model> RM,
133 std::optional<CodeModel::Model> CM,
134 CodeGenOptLevel OL, bool is64bit)
135 // The pic relocation model is used regardless of what the client has
136 // specified, as it is the only relocation model currently supported.
137 : CodeGenTargetMachineImpl(
138 T, TT.computeDataLayout(ABIName: UseShortPointersOpt ? "shortptr" : ""), TT,
139 CPU, FS, Options, Reloc::PIC_,
140 getEffectiveCodeModel(CM, Default: CodeModel::Small), OL),
141 is64bit(is64bit), TLOF(std::make_unique<NVPTXTargetObjectFile>()),
142 Subtarget(TT, std::string(CPU), std::string(FS), *this),
143 StrPool(StrAlloc) {
144 if (TT.getOS() == Triple::NVCL)
145 drvInterface = NVPTX::NVCL;
146 else
147 drvInterface = NVPTX::CUDA;
148 if (!DisableRequireStructuredCFG)
149 setRequiresStructuredCFG(true);
150 initAsmInfo();
151}
152
153NVPTXTargetMachine::~NVPTXTargetMachine() = default;
154
155void NVPTXTargetMachine32::anchor() {}
156
157NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, const Triple &TT,
158 StringRef CPU, StringRef FS,
159 const TargetOptions &Options,
160 std::optional<Reloc::Model> RM,
161 std::optional<CodeModel::Model> CM,
162 CodeGenOptLevel OL, bool JIT)
163 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
164
165void NVPTXTargetMachine64::anchor() {}
166
167NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, const Triple &TT,
168 StringRef CPU, StringRef FS,
169 const TargetOptions &Options,
170 std::optional<Reloc::Model> RM,
171 std::optional<CodeModel::Model> CM,
172 CodeGenOptLevel OL, bool JIT)
173 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
174
175namespace {
176
177class NVPTXPassConfig : public TargetPassConfig {
178public:
179 NVPTXPassConfig(NVPTXTargetMachine &TM, PassManagerBase &PM)
180 : TargetPassConfig(TM, PM) {}
181
182 NVPTXTargetMachine &getNVPTXTargetMachine() const {
183 return getTM<NVPTXTargetMachine>();
184 }
185
186 void addIRPasses() override;
187 bool addInstSelector() override;
188 void addPreRegAlloc() override;
189 void addPostRegAlloc() override;
190 void addMachineSSAOptimization() override;
191
192 FunctionPass *createTargetRegisterAllocator(bool) override;
193 void addFastRegAlloc() override;
194 void addOptimizedRegAlloc() override;
195
196 bool addRegAssignAndRewriteFast() override {
197 llvm_unreachable("should not be used");
198 }
199
200 bool addRegAssignAndRewriteOptimized() override {
201 llvm_unreachable("should not be used");
202 }
203
204private:
205 // If the opt level is aggressive, add GVN; otherwise, add EarlyCSE. This
206 // function is only called in opt mode.
207 void addEarlyCSEOrGVNPass();
208
209 // Add passes that propagate special memory spaces.
210 void addAddressSpaceInferencePasses();
211
212 // Add passes that perform straight-line scalar optimizations.
213 void addStraightLineScalarOptimizationPasses();
214};
215
216} // end anonymous namespace
217
218TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
219 return new NVPTXPassConfig(*this, PM);
220}
221
222MachineFunctionInfo *NVPTXTargetMachine::createMachineFunctionInfo(
223 BumpPtrAllocator &Allocator, const Function &F,
224 const TargetSubtargetInfo *STI) const {
225 return NVPTXMachineFunctionInfo::create<NVPTXMachineFunctionInfo>(Allocator,
226 F, STI);
227}
228
229void NVPTXTargetMachine::registerEarlyDefaultAliasAnalyses(AAManager &AAM) {
230 AAM.registerFunctionAnalysis<NVPTXAA>();
231}
232
233void NVPTXTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
234#define GET_PASS_REGISTRY "NVPTXPassRegistry.def"
235#include "llvm/Passes/TargetPassRegistry.inc"
236
237 PB.registerPipelineStartEPCallback(
238 C: [this](ModulePassManager &PM, OptimizationLevel Level) {
239 // We do not want to fold out calls to nvvm.reflect early if the user
240 // has not provided a target architecture just yet.
241 if (Subtarget.hasTargetName())
242 PM.addPass(Pass: NVVMReflectPass(Subtarget.getSmVersion()));
243
244 FunctionPassManager FPM;
245 // Note: NVVMIntrRangePass was causing numerical discrepancies at one
246 // point, if issues crop up, consider disabling.
247 FPM.addPass(Pass: NVVMIntrRangePass());
248 if (EarlyByValArgsCopy)
249 FPM.addPass(Pass: NVPTXCopyByValArgsPass());
250 PM.addPass(Pass: createModuleToFunctionPassAdaptor(Pass: std::move(FPM)));
251 });
252
253 if (!NoKernelInfoEndLTO) {
254 PB.registerFullLinkTimeOptimizationLastEPCallback(
255 C: [this](ModulePassManager &PM, OptimizationLevel Level) {
256 FunctionPassManager FPM;
257 FPM.addPass(Pass: KernelInfoPrinter(this));
258 PM.addPass(Pass: createModuleToFunctionPassAdaptor(Pass: std::move(FPM)));
259 });
260 }
261}
262
263TargetTransformInfo
264NVPTXTargetMachine::getTargetTransformInfo(const Function &F) const {
265 return TargetTransformInfo(std::make_unique<NVPTXTTIImpl>(args: this, args: F));
266}
267
268std::pair<const Value *, unsigned>
269NVPTXTargetMachine::getPredicatedAddrSpace(const Value *V) const {
270 if (auto *II = dyn_cast<IntrinsicInst>(Val: V)) {
271 switch (II->getIntrinsicID()) {
272 case Intrinsic::nvvm_isspacep_const:
273 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_CONST);
274 case Intrinsic::nvvm_isspacep_global:
275 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_GLOBAL);
276 case Intrinsic::nvvm_isspacep_local:
277 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_LOCAL);
278 case Intrinsic::nvvm_isspacep_shared:
279 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_SHARED);
280 case Intrinsic::nvvm_isspacep_shared_cluster:
281 return std::make_pair(x: II->getArgOperand(i: 0),
282 y: llvm::ADDRESS_SPACE_SHARED_CLUSTER);
283 default:
284 break;
285 }
286 }
287 return std::make_pair(x: nullptr, y: -1);
288}
289
290void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
291 if (getOptLevel() == CodeGenOptLevel::Aggressive)
292 addPass(P: createGVNPass());
293 else
294 addPass(P: createEarlyCSEPass());
295}
296
297void NVPTXPassConfig::addAddressSpaceInferencePasses() {
298 // NVPTXLowerArgs emits alloca for byval parameters which can often
299 // be eliminated by SROA.
300 addPass(P: createSROAPass());
301 addPass(P: createNVPTXLowerAllocaPass());
302 // TODO: Consider running InferAddressSpaces during opt, earlier in the
303 // compilation flow.
304 addPass(P: createInferAddressSpacesPass());
305 addPass(P: createNVPTXAtomicLowerPass());
306}
307
308void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() {
309 addPass(P: createSeparateConstOffsetFromGEPPass());
310 addPass(P: createSpeculativeExecutionPass());
311 // ReassociateGEPs exposes more opportunites for SLSR. See
312 // the example in reassociate-geps-and-slsr.ll.
313 addPass(P: createStraightLineStrengthReducePass());
314 // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
315 // EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE
316 // for some of our benchmarks.
317 addEarlyCSEOrGVNPass();
318 // Run NaryReassociate after EarlyCSE/GVN to be more effective.
319 addPass(P: createNaryReassociatePass());
320 // NaryReassociate on GEPs creates redundant common expressions, so run
321 // EarlyCSE after it.
322 addPass(P: createEarlyCSEPass());
323}
324
325void NVPTXPassConfig::addIRPasses() {
326 // The following passes are known to not play well with virtual regs hanging
327 // around after register allocation (which in our case, is *all* registers).
328 // We explicitly disable them here. We do, however, need some functionality
329 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
330 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
331 disablePass(PassID: &PrologEpilogCodeInserterID);
332 disablePass(PassID: &MachineLateInstrsCleanupID);
333 disablePass(PassID: &MachineCopyPropagationID);
334 disablePass(PassID: &TailDuplicateLegacyID);
335 disablePass(PassID: &StackMapLivenessID);
336 disablePass(PassID: &PostRAMachineSinkingID);
337 disablePass(PassID: &PostRASchedulerID);
338 disablePass(PassID: &FuncletLayoutID);
339 disablePass(PassID: &PatchableFunctionID);
340 disablePass(PassID: &ShrinkWrapID);
341 disablePass(PassID: &RemoveLoadsIntoFakeUsesID);
342
343 addPass(P: createNVPTXAAWrapperPass());
344 addPass(P: createNVPTXExternalAAWrapperPass());
345
346 // NVVMReflectPass is added in addEarlyAsPossiblePasses, so hopefully running
347 // it here does nothing. But since we need it for correctness when lowering
348 // to NVPTX, run it here too, in case whoever built our pass pipeline didn't
349 // call addEarlyAsPossiblePasses.
350 const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
351 addPass(P: createNVVMReflectPass(SmVersion: ST.getSmVersion()));
352
353 if (getOptLevel() != CodeGenOptLevel::None)
354 addPass(P: createNVPTXImageOptimizerPass());
355 addPass(P: createNVPTXAssignValidGlobalNamesPass());
356 addPass(P: createGenericToNVVMLegacyPass());
357
358 // NVPTXLowerArgs is required for correctness and should be run right
359 // before the address space inference passes.
360 addPass(P: createNVPTXLowerArgsPass());
361 if (getOptLevel() != CodeGenOptLevel::None) {
362 addAddressSpaceInferencePasses();
363 addStraightLineScalarOptimizationPasses();
364 }
365
366 addPass(P: createAtomicExpandLegacyPass());
367 addPass(P: createExpandVariadicsPass(ExpandVariadicsMode::Lowering));
368 addPass(P: createNVPTXCtorDtorLoweringLegacyPass());
369
370 // === LSR and other generic IR passes ===
371 TargetPassConfig::addIRPasses();
372 // EarlyCSE is not always strong enough to clean up what LSR produces. For
373 // example, GVN can combine
374 //
375 // %0 = add %a, %b
376 // %1 = add %b, %a
377 //
378 // and
379 //
380 // %0 = shl nsw %a, 2
381 // %1 = shl %a, 2
382 //
383 // but EarlyCSE can do neither of them.
384 if (getOptLevel() != CodeGenOptLevel::None) {
385 addEarlyCSEOrGVNPass();
386 if (!DisableLoadStoreVectorizer)
387 addPass(P: createLoadStoreVectorizerPass());
388 addPass(P: createSROAPass());
389 addPass(P: createNVPTXTagInvariantLoadsPass());
390 if (!DisableNVPTXIRPeephole)
391 addPass(P: createNVPTXIRPeepholePass());
392 }
393
394 if (ST.hasPTXASUnreachableBug()) {
395 // Run LowerUnreachable to WAR a ptxas bug. See the commit description of
396 // 1ee4d880e8760256c606fe55b7af85a4f70d006d for more details.
397 const auto &Options = getNVPTXTargetMachine().Options;
398 addPass(P: createNVPTXLowerUnreachablePass(TrapUnreachable: Options.TrapUnreachable,
399 NoTrapAfterNoreturn: Options.NoTrapAfterNoreturn));
400 }
401}
402
403bool NVPTXPassConfig::addInstSelector() {
404 addPass(P: createLowerAggrCopies());
405 addPass(P: createAllocaHoisting());
406 addPass(P: createNVPTXISelDag(TM&: getNVPTXTargetMachine(), OptLevel: getOptLevel()));
407 addPass(P: createNVPTXReplaceImageHandlesPass());
408
409 return false;
410}
411
412void NVPTXPassConfig::addPreRegAlloc() {
413 addPass(P: createNVPTXForwardParamsPass());
414 // Remove Proxy Register pseudo instructions used to keep `callseq_end` alive.
415 addPass(P: createNVPTXProxyRegErasurePass());
416}
417
418void NVPTXPassConfig::addPostRegAlloc() {
419 addPass(P: createNVPTXPrologEpilogPass());
420 if (getOptLevel() != CodeGenOptLevel::None) {
421 // NVPTXPrologEpilogPass calculates frame object offset and replace frame
422 // index with VRFrame register. NVPTXPeephole need to be run after that and
423 // will replace VRFrame with VRFrameLocal when possible.
424 addPass(P: createNVPTXPeephole());
425 }
426}
427
428FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
429 return nullptr; // No reg alloc
430}
431
432void NVPTXPassConfig::addFastRegAlloc() {
433 addPass(PassID: &PHIEliminationID);
434 addPass(PassID: &TwoAddressInstructionPassID);
435}
436
437void NVPTXPassConfig::addOptimizedRegAlloc() {
438 addPass(PassID: &ProcessImplicitDefsID);
439 addPass(PassID: &LiveVariablesID);
440 addPass(PassID: &MachineLoopInfoID);
441 addPass(PassID: &PHIEliminationID);
442
443 addPass(PassID: &TwoAddressInstructionPassID);
444 addPass(PassID: &RegisterCoalescerID);
445
446 // PreRA instruction scheduling.
447 if (addPass(PassID: &MachineSchedulerID))
448 printAndVerify(Banner: "After Machine Scheduling");
449
450 addPass(PassID: &StackSlotColoringID);
451
452 // FIXME: Needs physical registers
453 // addPass(&MachineLICMID);
454
455 printAndVerify(Banner: "After StackSlotColoring");
456}
457
458void NVPTXPassConfig::addMachineSSAOptimization() {
459 // Pre-ra tail duplication.
460 if (addPass(PassID: &EarlyTailDuplicateLegacyID))
461 printAndVerify(Banner: "After Pre-RegAlloc TailDuplicate");
462
463 // Optimize PHIs before DCE: removing dead PHI cycles may make more
464 // instructions dead.
465 addPass(PassID: &OptimizePHIsLegacyID);
466
467 // This pass merges large allocas. StackSlotColoring is a different pass
468 // which merges spill slots.
469 addPass(PassID: &StackColoringLegacyID);
470
471 // If the target requests it, assign local variables to stack slots relative
472 // to one another and simplify frame index references where possible.
473 addPass(PassID: &LocalStackSlotAllocationID);
474
475 // With optimization, dead code should already be eliminated. However
476 // there is one known exception: lowered code for arguments that are only
477 // used by tail calls, where the tail calls reuse the incoming stack
478 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
479 addPass(PassID: &DeadMachineInstructionElimID);
480 printAndVerify(Banner: "After codegen DCE pass");
481
482 // Allow targets to insert passes that improve instruction level parallelism,
483 // like if-conversion. Such passes will typically need dominator trees and
484 // loop info, just like LICM and CSE below.
485 if (addILPOpts())
486 printAndVerify(Banner: "After ILP optimizations");
487
488 addPass(PassID: &EarlyMachineLICMID);
489 addPass(PassID: &MachineCSELegacyID);
490
491 addPass(PassID: &MachineSinkingLegacyID);
492 printAndVerify(Banner: "After Machine LICM, CSE and Sinking passes");
493
494 addPass(PassID: &PeepholeOptimizerLegacyID);
495 printAndVerify(Banner: "After codegen peephole optimization pass");
496}
497