1//===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Top-level implementation for the NVPTX target.
10//
11//===----------------------------------------------------------------------===//
12
13#include "NVPTXTargetMachine.h"
14#include "NVPTX.h"
15#include "NVPTXAliasAnalysis.h"
16#include "NVPTXAllocaHoisting.h"
17#include "NVPTXAtomicLower.h"
18#include "NVPTXCtorDtorLowering.h"
19#include "NVPTXLowerAggrCopies.h"
20#include "NVPTXMachineFunctionInfo.h"
21#include "NVPTXTargetObjectFile.h"
22#include "NVPTXTargetTransformInfo.h"
23#include "TargetInfo/NVPTXTargetInfo.h"
24#include "llvm/Analysis/KernelInfo.h"
25#include "llvm/Analysis/TargetTransformInfo.h"
26#include "llvm/CodeGen/Passes.h"
27#include "llvm/CodeGen/TargetPassConfig.h"
28#include "llvm/IR/IntrinsicsNVPTX.h"
29#include "llvm/MC/TargetRegistry.h"
30#include "llvm/Pass.h"
31#include "llvm/Passes/PassBuilder.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/Compiler.h"
34#include "llvm/Target/TargetMachine.h"
35#include "llvm/Target/TargetOptions.h"
36#include "llvm/TargetParser/Triple.h"
37#include "llvm/Transforms/IPO/ExpandVariadics.h"
38#include "llvm/Transforms/Scalar.h"
39#include "llvm/Transforms/Scalar/GVN.h"
40#include "llvm/Transforms/Vectorize/LoadStoreVectorizer.h"
41#include <cassert>
42#include <optional>
43#include <string>
44
45using namespace llvm;
46
47// LSV is still relatively new; this switch lets us turn it off in case we
48// encounter (or suspect) a bug.
49static cl::opt<bool>
50 DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer",
51 cl::desc("Disable load/store vectorizer"),
52 cl::init(Val: false), cl::Hidden);
53
54// NVPTX IR Peephole is a new pass; this option will lets us turn it off in case
55// we encounter some issues.
56static cl::opt<bool>
57 DisableNVPTXIRPeephole("disable-nvptx-ir-peephole",
58 cl::desc("Disable NVPTX IR Peephole"),
59 cl::init(Val: false), cl::Hidden);
60
61// TODO: Remove this flag when we are confident with no regressions.
62static cl::opt<bool> DisableRequireStructuredCFG(
63 "disable-nvptx-require-structured-cfg",
64 cl::desc("Transitional flag to turn off NVPTX's requirement on preserving "
65 "structured CFG. The requirement should be disabled only when "
66 "unexpected regressions happen."),
67 cl::init(Val: false), cl::Hidden);
68
69static cl::opt<bool> UseShortPointersOpt(
70 "nvptx-short-ptr",
71 cl::desc(
72 "Use 32-bit pointers for accessing const/local/shared address spaces."),
73 cl::init(Val: false), cl::Hidden);
74
75// byval arguments in NVPTX are special. We're only allowed to read from them
76// using a special instruction, and if we ever need to write to them or take an
77// address, we must make a local copy and use it, instead.
78//
79// The problem is that local copies are very expensive, and we create them very
80// late in the compilation pipeline, so LLVM does not have much of a chance to
81// eliminate them, if they turn out to be unnecessary.
82//
83// One way around that is to create such copies early on, and let them percolate
84// through the optimizations. The copying itself will never trigger creation of
85// another copy later on, as the reads are allowed. If LLVM can eliminate it,
86// it's a win. It the full optimization pipeline can't remove the copy, that's
87// as good as it gets in terms of the effort we could've done, and it's
88// certainly a much better effort than what we do now.
89//
90// This early injection of the copies has potential to create undesireable
91// side-effects, so it's disabled by default, for now, until it sees more
92// testing.
93static cl::opt<bool> EarlyByValArgsCopy(
94 "nvptx-early-byval-copy",
95 cl::desc("Create a copy of byval function arguments early."),
96 cl::init(Val: false), cl::Hidden);
97
98extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTarget() {
99 // Register the target.
100 RegisterTargetMachine<NVPTXTargetMachine32> X(getTheNVPTXTarget32());
101 RegisterTargetMachine<NVPTXTargetMachine64> Y(getTheNVPTXTarget64());
102
103 PassRegistry &PR = *PassRegistry::getPassRegistry();
104 // FIXME: This pass is really intended to be invoked during IR optimization,
105 // but it's very NVPTX-specific.
106 initializeNVVMReflectLegacyPassPass(PR);
107 initializeNVVMIntrRangePass(PR);
108 initializeGenericToNVVMLegacyPassPass(PR);
109 initializeNVPTXAllocaHoistingPass(PR);
110 initializeNVPTXAsmPrinterPass(PR);
111 initializeNVPTXAssignValidGlobalNamesPass(PR);
112 initializeNVPTXAtomicLowerPass(PR);
113 initializeNVPTXLowerArgsLegacyPassPass(PR);
114 initializeNVPTXSetByValParamAlignLegacyPassPass(PR);
115 initializeNVPTXMarkKernelPtrsGlobalLegacyPassPass(PR);
116 initializeNVPTXLowerAllocaPass(PR);
117 initializeNVPTXLowerUnreachablePass(PR);
118 initializeNVPTXCtorDtorLoweringLegacyPass(PR);
119 initializeNVPTXLowerAggrCopiesPass(PR);
120 initializeNVPTXProxyRegErasurePass(PR);
121 initializeNVPTXForwardParamsPassPass(PR);
122 initializeNVPTXAddressFolderPassPass(PR);
123 initializeNVPTXDAGToDAGISelLegacyPass(PR);
124 initializeNVPTXAAWrapperPassPass(PR);
125 initializeNVPTXExternalAAWrapperPass(PR);
126 initializeNVPTXPeepholePass(PR);
127 initializeNVPTXTagInvariantLoadLegacyPassPass(PR);
128 initializeNVPTXIRPeepholePass(PR);
129 initializeNVPTXPrologEpilogPassPass(PR);
130}
131
132NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,
133 StringRef CPU, StringRef FS,
134 const TargetOptions &Options,
135 std::optional<Reloc::Model> RM,
136 std::optional<CodeModel::Model> CM,
137 CodeGenOptLevel OL, bool is64bit)
138 // The pic relocation model is used regardless of what the client has
139 // specified, as it is the only relocation model currently supported.
140 : CodeGenTargetMachineImpl(
141 T, TT.computeDataLayout(ABIName: UseShortPointersOpt ? "shortptr" : ""), TT,
142 CPU, FS, Options, Reloc::PIC_,
143 getEffectiveCodeModel(CM, Default: CodeModel::Small), OL),
144 is64bit(is64bit), TLOF(std::make_unique<NVPTXTargetObjectFile>()),
145 Subtarget(TT, std::string(CPU), std::string(FS), *this),
146 StrPool(StrAlloc) {
147 if (TT.getOS() == Triple::NVCL)
148 drvInterface = NVPTX::NVCL;
149 else
150 drvInterface = NVPTX::CUDA;
151 if (!DisableRequireStructuredCFG)
152 setRequiresStructuredCFG(true);
153 initAsmInfo();
154}
155
156NVPTXTargetMachine::~NVPTXTargetMachine() = default;
157
158void NVPTXTargetMachine32::anchor() {}
159
160NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, const Triple &TT,
161 StringRef CPU, StringRef FS,
162 const TargetOptions &Options,
163 std::optional<Reloc::Model> RM,
164 std::optional<CodeModel::Model> CM,
165 CodeGenOptLevel OL, bool JIT)
166 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
167
168void NVPTXTargetMachine64::anchor() {}
169
170NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, const Triple &TT,
171 StringRef CPU, StringRef FS,
172 const TargetOptions &Options,
173 std::optional<Reloc::Model> RM,
174 std::optional<CodeModel::Model> CM,
175 CodeGenOptLevel OL, bool JIT)
176 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
177
178namespace {
179
180class NVPTXPassConfig : public TargetPassConfig {
181public:
182 NVPTXPassConfig(NVPTXTargetMachine &TM, PassManagerBase &PM)
183 : TargetPassConfig(TM, PM) {}
184
185 NVPTXTargetMachine &getNVPTXTargetMachine() const {
186 return getTM<NVPTXTargetMachine>();
187 }
188
189 void addIRPasses() override;
190 bool addInstSelector() override;
191 void addPreRegAlloc() override;
192 void addPostRegAlloc() override;
193 void addMachineSSAOptimization() override;
194
195 FunctionPass *createTargetRegisterAllocator(bool) override;
196 void addFastRegAlloc() override;
197 void addOptimizedRegAlloc() override;
198
199 bool addRegAssignAndRewriteFast() override {
200 llvm_unreachable("should not be used");
201 }
202
203 bool addRegAssignAndRewriteOptimized() override {
204 llvm_unreachable("should not be used");
205 }
206
207private:
208 // If the opt level is aggressive, add GVN; otherwise, add EarlyCSE. This
209 // function is only called in opt mode.
210 void addEarlyCSEOrGVNPass();
211
212 // Add passes that propagate special memory spaces.
213 void addAddressSpaceInferencePasses();
214
215 // Add passes that perform straight-line scalar optimizations.
216 void addStraightLineScalarOptimizationPasses();
217};
218
219} // end anonymous namespace
220
221TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
222 return new NVPTXPassConfig(*this, PM);
223}
224
225MachineFunctionInfo *NVPTXTargetMachine::createMachineFunctionInfo(
226 BumpPtrAllocator &Allocator, const Function &F,
227 const TargetSubtargetInfo *STI) const {
228 return NVPTXMachineFunctionInfo::create<NVPTXMachineFunctionInfo>(Allocator,
229 F, STI);
230}
231
232void NVPTXTargetMachine::registerEarlyDefaultAliasAnalyses(AAManager &AAM) {
233 AAM.registerFunctionAnalysis<NVPTXAA>();
234}
235
236void NVPTXTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
237#define GET_PASS_REGISTRY "NVPTXPassRegistry.def"
238#include "llvm/Passes/TargetPassRegistry.inc"
239
240 PB.registerPipelineStartEPCallback(
241 C: [this](ModulePassManager &PM, OptimizationLevel Level) {
242 // We do not want to fold out calls to nvvm.reflect early if the user
243 // has not provided a target architecture just yet.
244 if (Subtarget.hasTargetName())
245 PM.addPass(Pass: NVVMReflectPass(Subtarget.getSmVersion()));
246
247 FunctionPassManager FPM;
248 // Note: NVVMIntrRangePass was causing numerical discrepancies at one
249 // point, if issues crop up, consider disabling.
250 FPM.addPass(Pass: NVVMIntrRangePass());
251 if (EarlyByValArgsCopy)
252 FPM.addPass(Pass: NVPTXCopyByValArgsPass());
253 PM.addPass(Pass: createModuleToFunctionPassAdaptor(Pass: std::move(FPM)));
254 });
255
256 if (!NoKernelInfoEndLTO) {
257 PB.registerFullLinkTimeOptimizationLastEPCallback(
258 C: [this](ModulePassManager &PM, OptimizationLevel Level) {
259 FunctionPassManager FPM;
260 FPM.addPass(Pass: KernelInfoPrinter(this));
261 PM.addPass(Pass: createModuleToFunctionPassAdaptor(Pass: std::move(FPM)));
262 });
263 }
264}
265
266TargetTransformInfo
267NVPTXTargetMachine::getTargetTransformInfo(const Function &F) const {
268 return TargetTransformInfo(std::make_unique<NVPTXTTIImpl>(args: this, args: F));
269}
270
271std::pair<const Value *, unsigned>
272NVPTXTargetMachine::getPredicatedAddrSpace(const Value *V) const {
273 if (auto *II = dyn_cast<IntrinsicInst>(Val: V)) {
274 switch (II->getIntrinsicID()) {
275 case Intrinsic::nvvm_isspacep_const:
276 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_CONST);
277 case Intrinsic::nvvm_isspacep_global:
278 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_GLOBAL);
279 case Intrinsic::nvvm_isspacep_local:
280 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_LOCAL);
281 case Intrinsic::nvvm_isspacep_shared:
282 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_SHARED);
283 case Intrinsic::nvvm_isspacep_shared_cluster:
284 return std::make_pair(x: II->getArgOperand(i: 0),
285 y: llvm::ADDRESS_SPACE_SHARED_CLUSTER);
286 default:
287 break;
288 }
289 }
290 return std::make_pair(x: nullptr, y: -1);
291}
292
293void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
294 if (getOptLevel() == CodeGenOptLevel::Aggressive)
295 // Disable scalar PRE due to Register Pressure increase
296 addPass(P: createGVNPass(/*ScalarPRE=*/false));
297 else
298 addPass(P: createEarlyCSEPass());
299}
300
301void NVPTXPassConfig::addAddressSpaceInferencePasses() {
302 // NVPTXLowerArgs emits alloca for byval parameters which can often
303 // be eliminated by SROA.
304 addPass(P: createSROAPass(/*PreserveCFG=*/true,
305 /*AggregateToVector=*/true));
306 addPass(P: createNVPTXLowerAllocaPass());
307 // TODO: Consider running InferAddressSpaces during opt, earlier in the
308 // compilation flow.
309 addPass(P: createInferAddressSpacesPass());
310 addPass(P: createNVPTXAtomicLowerPass());
311}
312
313void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() {
314 addPass(P: createSeparateConstOffsetFromGEPPass());
315 addPass(P: createSpeculativeExecutionPass());
316 // ReassociateGEPs exposes more opportunites for SLSR. See
317 // the example in reassociate-geps-and-slsr.ll.
318 addPass(P: createStraightLineStrengthReducePass());
319 // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
320 // EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE
321 // for some of our benchmarks.
322 addEarlyCSEOrGVNPass();
323 // Run NaryReassociate after EarlyCSE/GVN to be more effective.
324 addPass(P: createNaryReassociatePass());
325 // NaryReassociate on GEPs creates redundant common expressions, so run
326 // EarlyCSE after it.
327 addPass(P: createEarlyCSEPass());
328}
329
330void NVPTXPassConfig::addIRPasses() {
331 // The following passes are known to not play well with virtual regs hanging
332 // around after register allocation (which in our case, is *all* registers).
333 // We explicitly disable them here. We do, however, need some functionality
334 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
335 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
336 disablePass(PassID: &PrologEpilogCodeInserterID);
337 disablePass(PassID: &MachineLateInstrsCleanupID);
338 disablePass(PassID: &MachineCopyPropagationID);
339 disablePass(PassID: &TailDuplicateLegacyID);
340 disablePass(PassID: &StackMapLivenessID);
341 disablePass(PassID: &PostRAMachineSinkingID);
342 disablePass(PassID: &PostRASchedulerID);
343 disablePass(PassID: &FuncletLayoutID);
344 disablePass(PassID: &PatchableFunctionID);
345 disablePass(PassID: &ShrinkWrapID);
346 disablePass(PassID: &RemoveLoadsIntoFakeUsesID);
347
348 addPass(P: createNVPTXAAWrapperPass());
349 addPass(P: createNVPTXExternalAAWrapperPass());
350
351 // NVVMReflectPass is added in addEarlyAsPossiblePasses, so hopefully running
352 // it here does nothing. But since we need it for correctness when lowering
353 // to NVPTX, run it here too, in case whoever built our pass pipeline didn't
354 // call addEarlyAsPossiblePasses.
355 const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
356 addPass(P: createNVVMReflectPass(SmVersion: ST.getSmVersion()));
357
358 if (getOptLevel() != CodeGenOptLevel::None)
359 addPass(P: createNVPTXImageOptimizerPass());
360 addPass(P: createNVPTXAssignValidGlobalNamesPass());
361 addPass(P: createGenericToNVVMLegacyPass());
362
363 // Lower variadic calls before address space inference.
364 addPass(P: createExpandVariadicsPass(ExpandVariadicsMode::Lowering));
365
366 // NVPTXLowerArgs is required for correctness and should be run right
367 // before the address space inference passes.
368 if (getNVPTXTargetMachine().getDrvInterface() == NVPTX::CUDA)
369 addPass(P: createNVPTXMarkKernelPtrsGlobalPass());
370 addPass(P: createNVPTXSetByValParamAlignPass());
371 addPass(P: createNVPTXLowerArgsPass());
372 if (getOptLevel() != CodeGenOptLevel::None) {
373 addAddressSpaceInferencePasses();
374 addStraightLineScalarOptimizationPasses();
375 }
376
377 addPass(P: createAtomicExpandLegacyPass());
378 addPass(P: createNVPTXCtorDtorLoweringLegacyPass());
379
380 // === LSR and other generic IR passes ===
381 TargetPassConfig::addIRPasses();
382 // EarlyCSE is not always strong enough to clean up what LSR produces. For
383 // example, GVN can combine
384 //
385 // %0 = add %a, %b
386 // %1 = add %b, %a
387 //
388 // and
389 //
390 // %0 = shl nsw %a, 2
391 // %1 = shl %a, 2
392 //
393 // but EarlyCSE can do neither of them.
394 if (getOptLevel() != CodeGenOptLevel::None) {
395 addEarlyCSEOrGVNPass();
396 if (!DisableLoadStoreVectorizer)
397 addPass(P: createLoadStoreVectorizerPass());
398 addPass(P: createSROAPass(/*PreserveCFG=*/true,
399 /*AggregateToVector=*/true));
400 addPass(P: createNVPTXTagInvariantLoadsPass());
401 if (!DisableNVPTXIRPeephole)
402 addPass(P: createNVPTXIRPeepholePass());
403 }
404
405 if (ST.hasPTXASUnreachableBug()) {
406 // Run LowerUnreachable to WAR a ptxas bug. See the commit description of
407 // 1ee4d880e8760256c606fe55b7af85a4f70d006d for more details.
408 const auto &Options = getNVPTXTargetMachine().Options;
409 addPass(P: createNVPTXLowerUnreachablePass(TrapUnreachable: Options.TrapUnreachable,
410 NoTrapAfterNoreturn: Options.NoTrapAfterNoreturn));
411 }
412}
413
414bool NVPTXPassConfig::addInstSelector() {
415 addPass(P: createLowerAggrCopies());
416 addPass(P: createAllocaHoisting());
417 addPass(P: createNVPTXISelDag(TM&: getNVPTXTargetMachine(), OptLevel: getOptLevel()));
418 addPass(P: createNVPTXReplaceImageHandlesPass());
419
420 return false;
421}
422
423void NVPTXPassConfig::addPreRegAlloc() {
424 addPass(P: createNVPTXForwardParamsPass());
425 if (getOptLevel() != CodeGenOptLevel::None)
426 addPass(P: createNVPTXAddressFolderPass());
427 // Remove Proxy Register pseudo instructions used to keep `callseq_end` alive.
428 addPass(P: createNVPTXProxyRegErasurePass());
429}
430
431void NVPTXPassConfig::addPostRegAlloc() {
432 addPass(P: createNVPTXPrologEpilogPass());
433 if (getOptLevel() != CodeGenOptLevel::None) {
434 // NVPTXPrologEpilogPass calculates frame object offset and replace frame
435 // index with VRFrame register. NVPTXPeephole need to be run after that and
436 // will replace VRFrame with VRFrameLocal when possible.
437 addPass(P: createNVPTXPeephole());
438 }
439}
440
441FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
442 return nullptr; // No reg alloc
443}
444
445void NVPTXPassConfig::addFastRegAlloc() {
446 addPass(PassID: &PHIEliminationID);
447 addPass(PassID: &TwoAddressInstructionPassID);
448}
449
450void NVPTXPassConfig::addOptimizedRegAlloc() {
451 addPass(PassID: &ProcessImplicitDefsID);
452 addPass(PassID: &LiveVariablesID);
453 addPass(PassID: &MachineLoopInfoID);
454 addPass(PassID: &PHIEliminationID);
455
456 addPass(PassID: &TwoAddressInstructionPassID);
457 addPass(PassID: &RegisterCoalescerID);
458
459 // PreRA instruction scheduling.
460 if (addPass(PassID: &MachineSchedulerID))
461 printAndVerify(Banner: "After Machine Scheduling");
462
463 addPass(PassID: &StackSlotColoringID);
464
465 // FIXME: Needs physical registers
466 // addPass(&MachineLICMID);
467
468 printAndVerify(Banner: "After StackSlotColoring");
469}
470
471void NVPTXPassConfig::addMachineSSAOptimization() {
472 // Pre-ra tail duplication.
473 if (addPass(PassID: &EarlyTailDuplicateLegacyID))
474 printAndVerify(Banner: "After Pre-RegAlloc TailDuplicate");
475
476 // Optimize PHIs before DCE: removing dead PHI cycles may make more
477 // instructions dead.
478 addPass(PassID: &OptimizePHIsLegacyID);
479
480 // This pass merges large allocas. StackSlotColoring is a different pass
481 // which merges spill slots.
482 addPass(PassID: &StackColoringLegacyID);
483
484 // If the target requests it, assign local variables to stack slots relative
485 // to one another and simplify frame index references where possible.
486 addPass(PassID: &LocalStackSlotAllocationID);
487
488 // With optimization, dead code should already be eliminated. However
489 // there is one known exception: lowered code for arguments that are only
490 // used by tail calls, where the tail calls reuse the incoming stack
491 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
492 addPass(PassID: &DeadMachineInstructionElimID);
493 printAndVerify(Banner: "After codegen DCE pass");
494
495 // Allow targets to insert passes that improve instruction level parallelism,
496 // like if-conversion. Such passes will typically need dominator trees and
497 // loop info, just like LICM and CSE below.
498 if (addILPOpts())
499 printAndVerify(Banner: "After ILP optimizations");
500
501 addPass(PassID: &EarlyMachineLICMID);
502 addPass(PassID: &MachineCSELegacyID);
503
504 addPass(PassID: &MachineSinkingLegacyID);
505 printAndVerify(Banner: "After Machine LICM, CSE and Sinking passes");
506
507 addPass(PassID: &PeepholeOptimizerLegacyID);
508 printAndVerify(Banner: "After codegen peephole optimization pass");
509}
510