1//===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Top-level implementation for the NVPTX target.
10//
11//===----------------------------------------------------------------------===//
12
13#include "NVPTXTargetMachine.h"
14#include "NVPTX.h"
15#include "NVPTXAliasAnalysis.h"
16#include "NVPTXMachineFunctionInfo.h"
17#include "NVPTXTargetObjectFile.h"
18#include "NVPTXTargetTransformInfo.h"
19#include "TargetInfo/NVPTXTargetInfo.h"
20#include "llvm/Analysis/TargetTransformInfo.h"
21#include "llvm/CodeGen/Passes.h"
22#include "llvm/CodeGen/TargetPassConfig.h"
23#include "llvm/IR/IntrinsicsNVPTX.h"
24#include "llvm/MC/TargetRegistry.h"
25#include "llvm/Pass.h"
26#include "llvm/Support/CommandLine.h"
27#include "llvm/Support/Compiler.h"
28#include "llvm/Target/TargetMachine.h"
29#include "llvm/Target/TargetOptions.h"
30#include "llvm/TargetParser/Triple.h"
31#include "llvm/Transforms/IPO/ExpandVariadics.h"
32#include "llvm/Transforms/Scalar.h"
33#include "llvm/Transforms/Scalar/GVN.h"
34#include "llvm/Transforms/Vectorize/LoadStoreVectorizer.h"
35#include <cassert>
36#include <optional>
37#include <string>
38
39using namespace llvm;
40
41// LSV is still relatively new; this switch lets us turn it off in case we
42// encounter (or suspect) a bug.
43cl::opt<bool>
44 DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer",
45 cl::desc("Disable load/store vectorizer"),
46 cl::init(Val: false), cl::Hidden);
47
48// NVPTX IR Peephole is a new pass; this option will lets us turn it off in case
49// we encounter some issues.
50cl::opt<bool> DisableNVPTXIRPeephole("disable-nvptx-ir-peephole",
51 cl::desc("Disable NVPTX IR Peephole"),
52 cl::init(Val: false), cl::Hidden);
53
54// TODO: Remove this flag when we are confident with no regressions.
55static cl::opt<bool> DisableRequireStructuredCFG(
56 "disable-nvptx-require-structured-cfg",
57 cl::desc("Transitional flag to turn off NVPTX's requirement on preserving "
58 "structured CFG. The requirement should be disabled only when "
59 "unexpected regressions happen."),
60 cl::init(Val: false), cl::Hidden);
61
62extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTarget() {
63 // Register the target.
64 RegisterTargetMachine<NVPTXTargetMachine> X(getTheNVPTXTarget32());
65 RegisterTargetMachine<NVPTXTargetMachine> Y(getTheNVPTXTarget64());
66
67 PassRegistry &PR = *PassRegistry::getPassRegistry();
68 // FIXME: This pass is really intended to be invoked during IR optimization,
69 // but it's very NVPTX-specific.
70 initializeNVVMReflectLegacyPassPass(PR);
71 initializeNVVMIntrRangePass(PR);
72 initializeGenericToNVVMLegacyPassPass(PR);
73 initializeNVPTXAllocaHoistingLegacyPassPass(PR);
74 initializeNVPTXAsmPrinterPass(PR);
75 initializeNVPTXAssignValidGlobalNamesLegacyPassPass(PR);
76 initializeNVPTXAtomicLowerLegacyPassPass(PR);
77 initializeNVPTXLowerArgsLegacyPassPass(PR);
78 initializeNVPTXPromoteParamAlignLegacyPassPass(PR);
79 initializeNVPTXMarkKernelPtrsGlobalLegacyPassPass(PR);
80 initializeNVPTXLowerAllocaLegacyPassPass(PR);
81 initializeNVPTXLowerUnreachableLegacyPassPass(PR);
82 initializeNVPTXCtorDtorLoweringLegacyPass(PR);
83 initializeNVPTXLowerAggrCopiesLegacyPassPass(PR);
84 initializeNVPTXProxyRegErasureLegacyPassPass(PR);
85 initializeNVPTXForwardParamsLegacyPassPass(PR);
86 initializeNVPTXAddressFolderLegacyPassPass(PR);
87 initializeNVPTXDAGToDAGISelLegacyPass(PR);
88 initializeNVPTXAAWrapperPassPass(PR);
89 initializeNVPTXExternalAAWrapperPass(PR);
90 initializeNVPTXPeepholeLegacyPassPass(PR);
91 initializeNVPTXTagInvariantLoadLegacyPassPass(PR);
92 initializeNVPTXIRPeepholePass(PR);
93 initializeNVPTXPrologEpilogLegacyPassPass(PR);
94}
95
96NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,
97 StringRef CPU, StringRef FS,
98 const TargetOptions &Options,
99 std::optional<Reloc::Model> RM,
100 std::optional<CodeModel::Model> CM,
101 CodeGenOptLevel OL, bool JIT)
102 // The pic relocation model is used regardless of what the client has
103 // specified, as it is the only relocation model currently supported.
104 : CodeGenTargetMachineImpl(T, TT, CPU, FS, Options, Reloc::PIC_,
105 getEffectiveCodeModel(CM, Default: CodeModel::Small), OL),
106 TLOF(std::make_unique<NVPTXTargetObjectFile>()),
107 Subtarget(TT, CPU, FS, *this) {
108 if (!DisableRequireStructuredCFG)
109 setRequiresStructuredCFG(true);
110 // NVPTX does not produce verifier-clean MIR yet; see isMachineVerifierClean()
111 // for the legacy pass manager equivalent.
112 setEnableDefaultMachineVerifier(false);
113 initAsmInfo();
114}
115
116NVPTXTargetMachine::~NVPTXTargetMachine() = default;
117
118namespace {
119
120/// NVPTXPassConfig mirrors the NewPM implementation in NVPTXCodeGenPassBuilder
121/// in NVPTXCodeGenPassBuilder.cpp; the two must be kept in sync until this path
122/// is removed.
123class NVPTXPassConfig : public TargetPassConfig {
124public:
125 NVPTXPassConfig(NVPTXTargetMachine &TM, PassManagerBase &PM)
126 : TargetPassConfig(TM, PM) {}
127
128 NVPTXTargetMachine &getNVPTXTargetMachine() const {
129 return getTM<NVPTXTargetMachine>();
130 }
131
132 void addIRPasses() override;
133 bool addInstSelector() override;
134 void addPreRegAlloc() override;
135 void addPostRegAlloc() override;
136
137 FunctionPass *createTargetRegisterAllocator(bool) override;
138 void addFastRegAlloc() override;
139 void addOptimizedRegAlloc() override;
140
141 bool addRegAssignAndRewriteFast() override {
142 llvm_unreachable("should not be used");
143 }
144
145 bool addRegAssignAndRewriteOptimized() override {
146 llvm_unreachable("should not be used");
147 }
148
149private:
150 // If the opt level is aggressive, add GVN; otherwise, add EarlyCSE. This
151 // function is only called in opt mode.
152 void addEarlyCSEOrGVNPass();
153
154 // Add passes that propagate special memory spaces.
155 void addAddressSpaceInferencePasses();
156
157 // Add passes that perform straight-line scalar optimizations.
158 void addStraightLineScalarOptimizationPasses();
159};
160
161} // end anonymous namespace
162
163TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
164 return new NVPTXPassConfig(*this, PM);
165}
166
167MachineFunctionInfo *NVPTXTargetMachine::createMachineFunctionInfo(
168 BumpPtrAllocator &Allocator, const Function &F,
169 const TargetSubtargetInfo *STI) const {
170 return NVPTXMachineFunctionInfo::create<NVPTXMachineFunctionInfo>(Allocator,
171 F, STI);
172}
173
174void NVPTXTargetMachine::registerEarlyDefaultAliasAnalyses(AAManager &AAM) {
175 AAM.registerFunctionAnalysis<NVPTXAA>();
176}
177
178TargetTransformInfo
179NVPTXTargetMachine::getTargetTransformInfo(const Function &F) const {
180 return TargetTransformInfo(std::make_unique<NVPTXTTIImpl>(args: this, args: F));
181}
182
183std::pair<const Value *, unsigned>
184NVPTXTargetMachine::getPredicatedAddrSpace(const Value *V) const {
185 if (auto *II = dyn_cast<IntrinsicInst>(Val: V)) {
186 switch (II->getIntrinsicID()) {
187 case Intrinsic::nvvm_isspacep_const:
188 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_CONST);
189 case Intrinsic::nvvm_isspacep_global:
190 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_GLOBAL);
191 case Intrinsic::nvvm_isspacep_local:
192 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_LOCAL);
193 case Intrinsic::nvvm_isspacep_shared:
194 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_SHARED);
195 case Intrinsic::nvvm_isspacep_shared_cluster:
196 return std::make_pair(x: II->getArgOperand(i: 0),
197 y: llvm::ADDRESS_SPACE_SHARED_CLUSTER);
198 default:
199 break;
200 }
201 }
202 return std::make_pair(x: nullptr, y: -1);
203}
204
205void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
206 if (getOptLevel() == CodeGenOptLevel::Aggressive)
207 // Disable scalar PRE due to Register Pressure increase
208 addPass(P: createGVNPass(/*ScalarPRE=*/false));
209 else
210 addPass(P: createEarlyCSEPass());
211}
212
213void NVPTXPassConfig::addAddressSpaceInferencePasses() {
214 // NVPTXLowerArgs emits alloca for byval parameters which can often
215 // be eliminated by SROA.
216 addPass(P: createSROAPass(/*PreserveCFG=*/true,
217 /*AggregateToVector=*/true));
218 addPass(P: createNVPTXLowerAllocaLegacyPass());
219 // TODO: Consider running InferAddressSpaces during opt, earlier in the
220 // compilation flow.
221 addPass(P: createInferAddressSpacesPass());
222 addPass(P: createNVPTXAtomicLowerLegacyPass());
223}
224
225void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() {
226 addPass(P: createSeparateConstOffsetFromGEPPass());
227 addPass(P: createSpeculativeExecutionPass());
228 // ReassociateGEPs exposes more opportunites for SLSR. See
229 // the example in reassociate-geps-and-slsr.ll.
230 addPass(P: createStraightLineStrengthReducePass());
231 // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
232 // EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE
233 // for some of our benchmarks.
234 addEarlyCSEOrGVNPass();
235 // Run NaryReassociate after EarlyCSE/GVN to be more effective.
236 addPass(P: createNaryReassociatePass());
237 // NaryReassociate on GEPs creates redundant common expressions, so run
238 // EarlyCSE after it.
239 addPass(P: createEarlyCSEPass());
240}
241
242void NVPTXPassConfig::addIRPasses() {
243 // The following passes are known to not play well with virtual regs hanging
244 // around after register allocation (which in our case, is *all* registers).
245 // We explicitly disable them here. We do, however, need some functionality
246 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
247 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
248 disablePass(PassID: &PrologEpilogCodeInserterID);
249 disablePass(PassID: &MachineLateInstrsCleanupID);
250 disablePass(PassID: &MachineCopyPropagationID);
251 disablePass(PassID: &TailDuplicateLegacyID);
252 disablePass(PassID: &StackMapLivenessID);
253 disablePass(PassID: &PostRAMachineSinkingID);
254 disablePass(PassID: &PostRASchedulerID);
255 disablePass(PassID: &FuncletLayoutID);
256 disablePass(PassID: &PatchableFunctionID);
257 disablePass(PassID: &ShrinkWrapID);
258 disablePass(PassID: &RemoveLoadsIntoFakeUsesID);
259
260 addPass(P: createNVPTXAAWrapperPass());
261 addPass(P: createNVPTXExternalAAWrapperPass());
262
263 // NVVMReflectPass is added in addEarlyAsPossiblePasses, so hopefully running
264 // it here does nothing. But since we need it for correctness when lowering
265 // to NVPTX, run it here too, in case whoever built our pass pipeline didn't
266 // call addEarlyAsPossiblePasses.
267 const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
268 addPass(P: createNVVMReflectPass(SmVersion: ST.getSmVersion()));
269
270 if (getOptLevel() != CodeGenOptLevel::None)
271 addPass(P: createNVPTXImageOptimizerLegacyPass());
272 addPass(P: createNVPTXAssignValidGlobalNamesLegacyPass());
273 addPass(P: createGenericToNVVMLegacyPass());
274
275 // Lower variadic calls before address space inference.
276 addPass(P: createExpandVariadicsPass(ExpandVariadicsMode::Lowering));
277
278 // NVPTXLowerArgs is required for correctness and should be run right
279 // before the address space inference passes.
280 if (getNVPTXTargetMachine().getDrvInterface() == NVPTX::CUDA)
281 addPass(P: createNVPTXMarkKernelPtrsGlobalPass());
282 addPass(P: createNVPTXPromoteParamAlignPass());
283 addPass(P: createNVPTXLowerArgsPass());
284 if (getOptLevel() != CodeGenOptLevel::None) {
285 addAddressSpaceInferencePasses();
286 addStraightLineScalarOptimizationPasses();
287 } else {
288 // Required for correct stack lowering
289 addPass(P: createNVPTXLowerAllocaLegacyPass());
290 }
291
292 addPass(P: createAtomicExpandLegacyPass());
293 addPass(P: createNVPTXCtorDtorLoweringLegacyPass());
294
295 // === LSR and other generic IR passes ===
296 TargetPassConfig::addIRPasses();
297 // EarlyCSE is not always strong enough to clean up what LSR produces. For
298 // example, GVN can combine
299 //
300 // %0 = add %a, %b
301 // %1 = add %b, %a
302 //
303 // and
304 //
305 // %0 = shl nsw %a, 2
306 // %1 = shl %a, 2
307 //
308 // but EarlyCSE can do neither of them.
309 if (getOptLevel() != CodeGenOptLevel::None) {
310 addEarlyCSEOrGVNPass();
311 if (!DisableLoadStoreVectorizer)
312 addPass(P: createLoadStoreVectorizerPass());
313 addPass(P: createSROAPass(/*PreserveCFG=*/true,
314 /*AggregateToVector=*/true));
315 addPass(P: createNVPTXTagInvariantLoadsPass());
316 if (!DisableNVPTXIRPeephole)
317 addPass(P: createNVPTXIRPeepholePass());
318 }
319
320 if (ST.hasPTXASUnreachableBug()) {
321 // Run LowerUnreachable to WAR a ptxas bug. See the commit description of
322 // 1ee4d880e8760256c606fe55b7af85a4f70d006d for more details.
323 const auto &Options = getNVPTXTargetMachine().Options;
324 addPass(P: createNVPTXLowerUnreachableLegacyPass(TrapUnreachable: Options.TrapUnreachable,
325 NoTrapAfterNoreturn: Options.NoTrapAfterNoreturn));
326 }
327}
328
329bool NVPTXPassConfig::addInstSelector() {
330 addPass(P: createNVPTXLowerAggrCopiesLegacyPass());
331 addPass(P: createNVPTXAllocaHoistingLegacyPass());
332 addPass(P: createNVPTXISelDag(TM&: getNVPTXTargetMachine(), OptLevel: getOptLevel()));
333 addPass(P: createNVPTXReplaceImageHandlesLegacyPass());
334
335 return false;
336}
337
338void NVPTXPassConfig::addPreRegAlloc() {
339 addPass(P: createNVPTXForwardParamsLegacyPass());
340 if (getOptLevel() != CodeGenOptLevel::None)
341 addPass(P: createNVPTXAddressFolderLegacyPass());
342 // Remove Proxy Register pseudo instructions used to keep `callseq_end` alive.
343 addPass(P: createNVPTXProxyRegErasureLegacyPass());
344}
345
346void NVPTXPassConfig::addPostRegAlloc() {
347 addPass(P: createNVPTXPrologEpilogLegacyPass());
348 if (getOptLevel() != CodeGenOptLevel::None) {
349 // NVPTXPrologEpilogPass calculates frame object offset and replace frame
350 // index with VRFrame register. NVPTXPeephole need to be run after that and
351 // will replace VRFrame with VRFrameLocal when possible.
352 addPass(P: createNVPTXPeepholeLegacyPass());
353 }
354}
355
356FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
357 return nullptr; // No reg alloc
358}
359
360void NVPTXPassConfig::addFastRegAlloc() {
361 addPass(PassID: &PHIEliminationID);
362 addPass(PassID: &TwoAddressInstructionPassID);
363}
364
365void NVPTXPassConfig::addOptimizedRegAlloc() {
366 addPass(PassID: &ProcessImplicitDefsID);
367 addPass(PassID: &MachineLoopInfoID);
368 addPass(PassID: &PHIEliminationID);
369
370 addPass(PassID: &TwoAddressInstructionPassID);
371 addPass(PassID: &RegisterCoalescerID);
372
373 // PreRA instruction scheduling.
374 if (addPass(PassID: &MachineSchedulerID))
375 printAndVerify(Banner: "After Machine Scheduling");
376
377 addPass(PassID: &StackSlotColoringID);
378
379 // FIXME: Needs physical registers
380 // addPass(&MachineLICMID);
381
382 printAndVerify(Banner: "After StackSlotColoring");
383}
384