1//===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Top-level implementation for the NVPTX target.
10//
11//===----------------------------------------------------------------------===//
12
13#include "NVPTXTargetMachine.h"
14#include "NVPTX.h"
15#include "NVPTXAliasAnalysis.h"
16#include "NVPTXMachineFunctionInfo.h"
17#include "NVPTXTargetObjectFile.h"
18#include "NVPTXTargetTransformInfo.h"
19#include "TargetInfo/NVPTXTargetInfo.h"
20#include "llvm/Analysis/TargetTransformInfo.h"
21#include "llvm/CodeGen/Passes.h"
22#include "llvm/CodeGen/TargetPassConfig.h"
23#include "llvm/IR/IntrinsicsNVPTX.h"
24#include "llvm/MC/TargetRegistry.h"
25#include "llvm/Pass.h"
26#include "llvm/Support/CommandLine.h"
27#include "llvm/Support/Compiler.h"
28#include "llvm/Target/TargetMachine.h"
29#include "llvm/Target/TargetOptions.h"
30#include "llvm/TargetParser/Triple.h"
31#include "llvm/Transforms/IPO/ExpandVariadics.h"
32#include "llvm/Transforms/Scalar.h"
33#include "llvm/Transforms/Scalar/GVN.h"
34#include "llvm/Transforms/Vectorize/LoadStoreVectorizer.h"
35#include <cassert>
36#include <optional>
37#include <string>
38
39using namespace llvm;
40
41// LSV is still relatively new; this switch lets us turn it off in case we
42// encounter (or suspect) a bug.
43cl::opt<bool>
44 DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer",
45 cl::desc("Disable load/store vectorizer"),
46 cl::init(Val: false), cl::Hidden);
47
48// NVPTX IR Peephole is a new pass; this option will lets us turn it off in case
49// we encounter some issues.
50cl::opt<bool> DisableNVPTXIRPeephole("disable-nvptx-ir-peephole",
51 cl::desc("Disable NVPTX IR Peephole"),
52 cl::init(Val: false), cl::Hidden);
53
54// TODO: Remove this flag when we are confident with no regressions.
55static cl::opt<bool> DisableRequireStructuredCFG(
56 "disable-nvptx-require-structured-cfg",
57 cl::desc("Transitional flag to turn off NVPTX's requirement on preserving "
58 "structured CFG. The requirement should be disabled only when "
59 "unexpected regressions happen."),
60 cl::init(Val: false), cl::Hidden);
61
62extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTarget() {
63 // Register the target.
64 RegisterTargetMachine<NVPTXTargetMachine> X(getTheNVPTXTarget32());
65 RegisterTargetMachine<NVPTXTargetMachine> Y(getTheNVPTXTarget64());
66
67 PassRegistry &PR = *PassRegistry::getPassRegistry();
68 // FIXME: This pass is really intended to be invoked during IR optimization,
69 // but it's very NVPTX-specific.
70 initializeNVVMReflectLegacyPassPass(PR);
71 initializeNVVMIntrRangePass(PR);
72 initializeGenericToNVVMLegacyPassPass(PR);
73 initializeNVPTXAllocaHoistingLegacyPassPass(PR);
74 initializeNVPTXAsmPrinterPass(PR);
75 initializeNVPTXAssignValidGlobalNamesLegacyPassPass(PR);
76 initializeNVPTXAtomicLowerLegacyPassPass(PR);
77 initializeNVPTXLowerArgsLegacyPassPass(PR);
78 initializeNVPTXPromoteParamAlignLegacyPassPass(PR);
79 initializeNVPTXMarkKernelPtrsGlobalLegacyPassPass(PR);
80 initializeNVPTXLowerAllocaLegacyPassPass(PR);
81 initializeNVPTXLowerUnreachableLegacyPassPass(PR);
82 initializeNVPTXCtorDtorLoweringLegacyPass(PR);
83 initializeNVPTXLowerAggrCopiesLegacyPassPass(PR);
84 initializeNVPTXProxyRegErasureLegacyPassPass(PR);
85 initializeNVPTXForwardParamsLegacyPassPass(PR);
86 initializeNVPTXAddressFolderLegacyPassPass(PR);
87 initializeNVPTXDAGToDAGISelLegacyPass(PR);
88 initializeNVPTXAAWrapperPassPass(PR);
89 initializeNVPTXExternalAAWrapperPass(PR);
90 initializeNVPTXPeepholeLegacyPassPass(PR);
91 initializeNVPTXTagInvariantLoadLegacyPassPass(PR);
92 initializeNVPTXIRPeepholePass(PR);
93 initializeNVPTXPrologEpilogLegacyPassPass(PR);
94}
95
96NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,
97 StringRef CPU, StringRef FS,
98 const TargetOptions &Options,
99 std::optional<Reloc::Model> RM,
100 std::optional<CodeModel::Model> CM,
101 CodeGenOptLevel OL, bool JIT)
102 // The pic relocation model is used regardless of what the client has
103 // specified, as it is the only relocation model currently supported.
104 : CodeGenTargetMachineImpl(T,
105 TT.computeDataLayout(ABIName: Options.MCOptions.ABIName),
106 TT, CPU, FS, Options, Reloc::PIC_,
107 getEffectiveCodeModel(CM, Default: CodeModel::Small), OL),
108 TLOF(std::make_unique<NVPTXTargetObjectFile>()),
109 Subtarget(TT, CPU, FS, *this) {
110 if (!DisableRequireStructuredCFG)
111 setRequiresStructuredCFG(true);
112 // NVPTX does not produce verifier-clean MIR yet; see isMachineVerifierClean()
113 // for the legacy pass manager equivalent.
114 setEnableDefaultMachineVerifier(false);
115 initAsmInfo();
116}
117
118NVPTXTargetMachine::~NVPTXTargetMachine() = default;
119
120namespace {
121
122/// NVPTXPassConfig mirrors the NewPM implementation in NVPTXCodeGenPassBuilder
123/// in NVPTXCodeGenPassBuilder.cpp; the two must be kept in sync until this path
124/// is removed.
125class NVPTXPassConfig : public TargetPassConfig {
126public:
127 NVPTXPassConfig(NVPTXTargetMachine &TM, PassManagerBase &PM)
128 : TargetPassConfig(TM, PM) {}
129
130 NVPTXTargetMachine &getNVPTXTargetMachine() const {
131 return getTM<NVPTXTargetMachine>();
132 }
133
134 void addIRPasses() override;
135 bool addInstSelector() override;
136 void addPreRegAlloc() override;
137 void addPostRegAlloc() override;
138
139 FunctionPass *createTargetRegisterAllocator(bool) override;
140 void addFastRegAlloc() override;
141 void addOptimizedRegAlloc() override;
142
143 bool addRegAssignAndRewriteFast() override {
144 llvm_unreachable("should not be used");
145 }
146
147 bool addRegAssignAndRewriteOptimized() override {
148 llvm_unreachable("should not be used");
149 }
150
151private:
152 // If the opt level is aggressive, add GVN; otherwise, add EarlyCSE. This
153 // function is only called in opt mode.
154 void addEarlyCSEOrGVNPass();
155
156 // Add passes that propagate special memory spaces.
157 void addAddressSpaceInferencePasses();
158
159 // Add passes that perform straight-line scalar optimizations.
160 void addStraightLineScalarOptimizationPasses();
161};
162
163} // end anonymous namespace
164
165TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
166 return new NVPTXPassConfig(*this, PM);
167}
168
169MachineFunctionInfo *NVPTXTargetMachine::createMachineFunctionInfo(
170 BumpPtrAllocator &Allocator, const Function &F,
171 const TargetSubtargetInfo *STI) const {
172 return NVPTXMachineFunctionInfo::create<NVPTXMachineFunctionInfo>(Allocator,
173 F, STI);
174}
175
176void NVPTXTargetMachine::registerEarlyDefaultAliasAnalyses(AAManager &AAM) {
177 AAM.registerFunctionAnalysis<NVPTXAA>();
178}
179
180TargetTransformInfo
181NVPTXTargetMachine::getTargetTransformInfo(const Function &F) const {
182 return TargetTransformInfo(std::make_unique<NVPTXTTIImpl>(args: this, args: F));
183}
184
185std::pair<const Value *, unsigned>
186NVPTXTargetMachine::getPredicatedAddrSpace(const Value *V) const {
187 if (auto *II = dyn_cast<IntrinsicInst>(Val: V)) {
188 switch (II->getIntrinsicID()) {
189 case Intrinsic::nvvm_isspacep_const:
190 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_CONST);
191 case Intrinsic::nvvm_isspacep_global:
192 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_GLOBAL);
193 case Intrinsic::nvvm_isspacep_local:
194 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_LOCAL);
195 case Intrinsic::nvvm_isspacep_shared:
196 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_SHARED);
197 case Intrinsic::nvvm_isspacep_shared_cluster:
198 return std::make_pair(x: II->getArgOperand(i: 0),
199 y: llvm::ADDRESS_SPACE_SHARED_CLUSTER);
200 default:
201 break;
202 }
203 }
204 return std::make_pair(x: nullptr, y: -1);
205}
206
207void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
208 if (getOptLevel() == CodeGenOptLevel::Aggressive)
209 // Disable scalar PRE due to Register Pressure increase
210 addPass(P: createGVNPass(/*ScalarPRE=*/false));
211 else
212 addPass(P: createEarlyCSEPass());
213}
214
215void NVPTXPassConfig::addAddressSpaceInferencePasses() {
216 // NVPTXLowerArgs emits alloca for byval parameters which can often
217 // be eliminated by SROA.
218 addPass(P: createSROAPass(/*PreserveCFG=*/true,
219 /*AggregateToVector=*/true));
220 addPass(P: createNVPTXLowerAllocaLegacyPass());
221 // TODO: Consider running InferAddressSpaces during opt, earlier in the
222 // compilation flow.
223 addPass(P: createInferAddressSpacesPass());
224 addPass(P: createNVPTXAtomicLowerLegacyPass());
225}
226
227void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() {
228 addPass(P: createSeparateConstOffsetFromGEPPass());
229 addPass(P: createSpeculativeExecutionPass());
230 // ReassociateGEPs exposes more opportunites for SLSR. See
231 // the example in reassociate-geps-and-slsr.ll.
232 addPass(P: createStraightLineStrengthReducePass());
233 // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
234 // EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE
235 // for some of our benchmarks.
236 addEarlyCSEOrGVNPass();
237 // Run NaryReassociate after EarlyCSE/GVN to be more effective.
238 addPass(P: createNaryReassociatePass());
239 // NaryReassociate on GEPs creates redundant common expressions, so run
240 // EarlyCSE after it.
241 addPass(P: createEarlyCSEPass());
242}
243
244void NVPTXPassConfig::addIRPasses() {
245 // The following passes are known to not play well with virtual regs hanging
246 // around after register allocation (which in our case, is *all* registers).
247 // We explicitly disable them here. We do, however, need some functionality
248 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
249 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
250 disablePass(PassID: &PrologEpilogCodeInserterID);
251 disablePass(PassID: &MachineLateInstrsCleanupID);
252 disablePass(PassID: &MachineCopyPropagationID);
253 disablePass(PassID: &TailDuplicateLegacyID);
254 disablePass(PassID: &StackMapLivenessID);
255 disablePass(PassID: &PostRAMachineSinkingID);
256 disablePass(PassID: &PostRASchedulerID);
257 disablePass(PassID: &FuncletLayoutID);
258 disablePass(PassID: &PatchableFunctionID);
259 disablePass(PassID: &ShrinkWrapID);
260 disablePass(PassID: &RemoveLoadsIntoFakeUsesID);
261
262 addPass(P: createNVPTXAAWrapperPass());
263 addPass(P: createNVPTXExternalAAWrapperPass());
264
265 // NVVMReflectPass is added in addEarlyAsPossiblePasses, so hopefully running
266 // it here does nothing. But since we need it for correctness when lowering
267 // to NVPTX, run it here too, in case whoever built our pass pipeline didn't
268 // call addEarlyAsPossiblePasses.
269 const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
270 addPass(P: createNVVMReflectPass(SmVersion: ST.getSmVersion()));
271
272 if (getOptLevel() != CodeGenOptLevel::None)
273 addPass(P: createNVPTXImageOptimizerLegacyPass());
274 addPass(P: createNVPTXAssignValidGlobalNamesLegacyPass());
275 addPass(P: createGenericToNVVMLegacyPass());
276
277 // Lower variadic calls before address space inference.
278 addPass(P: createExpandVariadicsPass(ExpandVariadicsMode::Lowering));
279
280 // NVPTXLowerArgs is required for correctness and should be run right
281 // before the address space inference passes.
282 if (getNVPTXTargetMachine().getDrvInterface() == NVPTX::CUDA)
283 addPass(P: createNVPTXMarkKernelPtrsGlobalPass());
284 addPass(P: createNVPTXPromoteParamAlignPass());
285 addPass(P: createNVPTXLowerArgsPass());
286 if (getOptLevel() != CodeGenOptLevel::None) {
287 addAddressSpaceInferencePasses();
288 addStraightLineScalarOptimizationPasses();
289 } else {
290 // Required for correct stack lowering
291 addPass(P: createNVPTXLowerAllocaLegacyPass());
292 }
293
294 addPass(P: createAtomicExpandLegacyPass());
295 addPass(P: createNVPTXCtorDtorLoweringLegacyPass());
296
297 // === LSR and other generic IR passes ===
298 TargetPassConfig::addIRPasses();
299 // EarlyCSE is not always strong enough to clean up what LSR produces. For
300 // example, GVN can combine
301 //
302 // %0 = add %a, %b
303 // %1 = add %b, %a
304 //
305 // and
306 //
307 // %0 = shl nsw %a, 2
308 // %1 = shl %a, 2
309 //
310 // but EarlyCSE can do neither of them.
311 if (getOptLevel() != CodeGenOptLevel::None) {
312 addEarlyCSEOrGVNPass();
313 if (!DisableLoadStoreVectorizer)
314 addPass(P: createLoadStoreVectorizerPass());
315 addPass(P: createSROAPass(/*PreserveCFG=*/true,
316 /*AggregateToVector=*/true));
317 addPass(P: createNVPTXTagInvariantLoadsPass());
318 if (!DisableNVPTXIRPeephole)
319 addPass(P: createNVPTXIRPeepholePass());
320 }
321
322 if (ST.hasPTXASUnreachableBug()) {
323 // Run LowerUnreachable to WAR a ptxas bug. See the commit description of
324 // 1ee4d880e8760256c606fe55b7af85a4f70d006d for more details.
325 const auto &Options = getNVPTXTargetMachine().Options;
326 addPass(P: createNVPTXLowerUnreachableLegacyPass(TrapUnreachable: Options.TrapUnreachable,
327 NoTrapAfterNoreturn: Options.NoTrapAfterNoreturn));
328 }
329}
330
331bool NVPTXPassConfig::addInstSelector() {
332 addPass(P: createNVPTXLowerAggrCopiesLegacyPass());
333 addPass(P: createNVPTXAllocaHoistingLegacyPass());
334 addPass(P: createNVPTXISelDag(TM&: getNVPTXTargetMachine(), OptLevel: getOptLevel()));
335 addPass(P: createNVPTXReplaceImageHandlesLegacyPass());
336
337 return false;
338}
339
340void NVPTXPassConfig::addPreRegAlloc() {
341 addPass(P: createNVPTXForwardParamsLegacyPass());
342 if (getOptLevel() != CodeGenOptLevel::None)
343 addPass(P: createNVPTXAddressFolderLegacyPass());
344 // Remove Proxy Register pseudo instructions used to keep `callseq_end` alive.
345 addPass(P: createNVPTXProxyRegErasureLegacyPass());
346}
347
348void NVPTXPassConfig::addPostRegAlloc() {
349 addPass(P: createNVPTXPrologEpilogLegacyPass());
350 if (getOptLevel() != CodeGenOptLevel::None) {
351 // NVPTXPrologEpilogPass calculates frame object offset and replace frame
352 // index with VRFrame register. NVPTXPeephole need to be run after that and
353 // will replace VRFrame with VRFrameLocal when possible.
354 addPass(P: createNVPTXPeepholeLegacyPass());
355 }
356}
357
358FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
359 return nullptr; // No reg alloc
360}
361
362void NVPTXPassConfig::addFastRegAlloc() {
363 addPass(PassID: &PHIEliminationID);
364 addPass(PassID: &TwoAddressInstructionPassID);
365}
366
367void NVPTXPassConfig::addOptimizedRegAlloc() {
368 addPass(PassID: &ProcessImplicitDefsID);
369 addPass(PassID: &LiveVariablesID);
370 addPass(PassID: &MachineLoopInfoID);
371 addPass(PassID: &PHIEliminationID);
372
373 addPass(PassID: &TwoAddressInstructionPassID);
374 addPass(PassID: &RegisterCoalescerID);
375
376 // PreRA instruction scheduling.
377 if (addPass(PassID: &MachineSchedulerID))
378 printAndVerify(Banner: "After Machine Scheduling");
379
380 addPass(PassID: &StackSlotColoringID);
381
382 // FIXME: Needs physical registers
383 // addPass(&MachineLICMID);
384
385 printAndVerify(Banner: "After StackSlotColoring");
386}
387