1//===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Top-level implementation for the NVPTX target.
10//
11//===----------------------------------------------------------------------===//
12
13#include "NVPTXTargetMachine.h"
14#include "NVPTX.h"
15#include "NVPTXAliasAnalysis.h"
16#include "NVPTXAllocaHoisting.h"
17#include "NVPTXAtomicLower.h"
18#include "NVPTXCtorDtorLowering.h"
19#include "NVPTXLowerAggrCopies.h"
20#include "NVPTXMachineFunctionInfo.h"
21#include "NVPTXTargetObjectFile.h"
22#include "NVPTXTargetTransformInfo.h"
23#include "TargetInfo/NVPTXTargetInfo.h"
24#include "llvm/Analysis/KernelInfo.h"
25#include "llvm/Analysis/TargetTransformInfo.h"
26#include "llvm/CodeGen/Passes.h"
27#include "llvm/CodeGen/TargetPassConfig.h"
28#include "llvm/IR/IntrinsicsNVPTX.h"
29#include "llvm/MC/TargetRegistry.h"
30#include "llvm/Pass.h"
31#include "llvm/Passes/PassBuilder.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/Compiler.h"
34#include "llvm/Target/TargetMachine.h"
35#include "llvm/Target/TargetOptions.h"
36#include "llvm/TargetParser/Triple.h"
37#include "llvm/Transforms/IPO/ExpandVariadics.h"
38#include "llvm/Transforms/Scalar.h"
39#include "llvm/Transforms/Scalar/GVN.h"
40#include "llvm/Transforms/Vectorize/LoadStoreVectorizer.h"
41#include <cassert>
42#include <optional>
43#include <string>
44
45using namespace llvm;
46
47// LSV is still relatively new; this switch lets us turn it off in case we
48// encounter (or suspect) a bug.
49static cl::opt<bool>
50 DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer",
51 cl::desc("Disable load/store vectorizer"),
52 cl::init(Val: false), cl::Hidden);
53
54// NVPTX IR Peephole is a new pass; this option will lets us turn it off in case
55// we encounter some issues.
56static cl::opt<bool>
57 DisableNVPTXIRPeephole("disable-nvptx-ir-peephole",
58 cl::desc("Disable NVPTX IR Peephole"),
59 cl::init(Val: false), cl::Hidden);
60
61// TODO: Remove this flag when we are confident with no regressions.
62static cl::opt<bool> DisableRequireStructuredCFG(
63 "disable-nvptx-require-structured-cfg",
64 cl::desc("Transitional flag to turn off NVPTX's requirement on preserving "
65 "structured CFG. The requirement should be disabled only when "
66 "unexpected regressions happen."),
67 cl::init(Val: false), cl::Hidden);
68
69static cl::opt<bool> UseShortPointersOpt(
70 "nvptx-short-ptr",
71 cl::desc(
72 "Use 32-bit pointers for accessing const/local/shared address spaces."),
73 cl::init(Val: false), cl::Hidden);
74
75// byval arguments in NVPTX are special. We're only allowed to read from them
76// using a special instruction, and if we ever need to write to them or take an
77// address, we must make a local copy and use it, instead.
78//
79// The problem is that local copies are very expensive, and we create them very
80// late in the compilation pipeline, so LLVM does not have much of a chance to
81// eliminate them, if they turn out to be unnecessary.
82//
83// One way around that is to create such copies early on, and let them percolate
84// through the optimizations. The copying itself will never trigger creation of
85// another copy later on, as the reads are allowed. If LLVM can eliminate it,
86// it's a win. It the full optimization pipeline can't remove the copy, that's
87// as good as it gets in terms of the effort we could've done, and it's
88// certainly a much better effort than what we do now.
89//
90// This early injection of the copies has potential to create undesireable
91// side-effects, so it's disabled by default, for now, until it sees more
92// testing.
93static cl::opt<bool> EarlyByValArgsCopy(
94 "nvptx-early-byval-copy",
95 cl::desc("Create a copy of byval function arguments early."),
96 cl::init(Val: false), cl::Hidden);
97
98extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTarget() {
99 // Register the target.
100 RegisterTargetMachine<NVPTXTargetMachine32> X(getTheNVPTXTarget32());
101 RegisterTargetMachine<NVPTXTargetMachine64> Y(getTheNVPTXTarget64());
102
103 PassRegistry &PR = *PassRegistry::getPassRegistry();
104 // FIXME: This pass is really intended to be invoked during IR optimization,
105 // but it's very NVPTX-specific.
106 initializeNVVMReflectLegacyPassPass(PR);
107 initializeNVVMIntrRangePass(PR);
108 initializeGenericToNVVMLegacyPassPass(PR);
109 initializeNVPTXAllocaHoistingPass(PR);
110 initializeNVPTXAsmPrinterPass(PR);
111 initializeNVPTXAssignValidGlobalNamesPass(PR);
112 initializeNVPTXAtomicLowerPass(PR);
113 initializeNVPTXLowerArgsLegacyPassPass(PR);
114 initializeNVPTXSetByValParamAlignLegacyPassPass(PR);
115 initializeNVPTXMarkKernelPtrsGlobalLegacyPassPass(PR);
116 initializeNVPTXLowerAllocaPass(PR);
117 initializeNVPTXLowerUnreachablePass(PR);
118 initializeNVPTXCtorDtorLoweringLegacyPass(PR);
119 initializeNVPTXLowerAggrCopiesPass(PR);
120 initializeNVPTXProxyRegErasurePass(PR);
121 initializeNVPTXForwardParamsPassPass(PR);
122 initializeNVPTXDAGToDAGISelLegacyPass(PR);
123 initializeNVPTXAAWrapperPassPass(PR);
124 initializeNVPTXExternalAAWrapperPass(PR);
125 initializeNVPTXPeepholePass(PR);
126 initializeNVPTXTagInvariantLoadLegacyPassPass(PR);
127 initializeNVPTXIRPeepholePass(PR);
128 initializeNVPTXPrologEpilogPassPass(PR);
129}
130
131NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,
132 StringRef CPU, StringRef FS,
133 const TargetOptions &Options,
134 std::optional<Reloc::Model> RM,
135 std::optional<CodeModel::Model> CM,
136 CodeGenOptLevel OL, bool is64bit)
137 // The pic relocation model is used regardless of what the client has
138 // specified, as it is the only relocation model currently supported.
139 : CodeGenTargetMachineImpl(
140 T, TT.computeDataLayout(ABIName: UseShortPointersOpt ? "shortptr" : ""), TT,
141 CPU, FS, Options, Reloc::PIC_,
142 getEffectiveCodeModel(CM, Default: CodeModel::Small), OL),
143 is64bit(is64bit), TLOF(std::make_unique<NVPTXTargetObjectFile>()),
144 Subtarget(TT, std::string(CPU), std::string(FS), *this),
145 StrPool(StrAlloc) {
146 if (TT.getOS() == Triple::NVCL)
147 drvInterface = NVPTX::NVCL;
148 else
149 drvInterface = NVPTX::CUDA;
150 if (!DisableRequireStructuredCFG)
151 setRequiresStructuredCFG(true);
152 initAsmInfo();
153}
154
155NVPTXTargetMachine::~NVPTXTargetMachine() = default;
156
157void NVPTXTargetMachine32::anchor() {}
158
159NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, const Triple &TT,
160 StringRef CPU, StringRef FS,
161 const TargetOptions &Options,
162 std::optional<Reloc::Model> RM,
163 std::optional<CodeModel::Model> CM,
164 CodeGenOptLevel OL, bool JIT)
165 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
166
167void NVPTXTargetMachine64::anchor() {}
168
169NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, const Triple &TT,
170 StringRef CPU, StringRef FS,
171 const TargetOptions &Options,
172 std::optional<Reloc::Model> RM,
173 std::optional<CodeModel::Model> CM,
174 CodeGenOptLevel OL, bool JIT)
175 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
176
177namespace {
178
179class NVPTXPassConfig : public TargetPassConfig {
180public:
181 NVPTXPassConfig(NVPTXTargetMachine &TM, PassManagerBase &PM)
182 : TargetPassConfig(TM, PM) {}
183
184 NVPTXTargetMachine &getNVPTXTargetMachine() const {
185 return getTM<NVPTXTargetMachine>();
186 }
187
188 void addIRPasses() override;
189 bool addInstSelector() override;
190 void addPreRegAlloc() override;
191 void addPostRegAlloc() override;
192 void addMachineSSAOptimization() override;
193
194 FunctionPass *createTargetRegisterAllocator(bool) override;
195 void addFastRegAlloc() override;
196 void addOptimizedRegAlloc() override;
197
198 bool addRegAssignAndRewriteFast() override {
199 llvm_unreachable("should not be used");
200 }
201
202 bool addRegAssignAndRewriteOptimized() override {
203 llvm_unreachable("should not be used");
204 }
205
206private:
207 // If the opt level is aggressive, add GVN; otherwise, add EarlyCSE. This
208 // function is only called in opt mode.
209 void addEarlyCSEOrGVNPass();
210
211 // Add passes that propagate special memory spaces.
212 void addAddressSpaceInferencePasses();
213
214 // Add passes that perform straight-line scalar optimizations.
215 void addStraightLineScalarOptimizationPasses();
216};
217
218} // end anonymous namespace
219
220TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
221 return new NVPTXPassConfig(*this, PM);
222}
223
224MachineFunctionInfo *NVPTXTargetMachine::createMachineFunctionInfo(
225 BumpPtrAllocator &Allocator, const Function &F,
226 const TargetSubtargetInfo *STI) const {
227 return NVPTXMachineFunctionInfo::create<NVPTXMachineFunctionInfo>(Allocator,
228 F, STI);
229}
230
231void NVPTXTargetMachine::registerEarlyDefaultAliasAnalyses(AAManager &AAM) {
232 AAM.registerFunctionAnalysis<NVPTXAA>();
233}
234
235void NVPTXTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
236#define GET_PASS_REGISTRY "NVPTXPassRegistry.def"
237#include "llvm/Passes/TargetPassRegistry.inc"
238
239 PB.registerPipelineStartEPCallback(
240 C: [this](ModulePassManager &PM, OptimizationLevel Level) {
241 // We do not want to fold out calls to nvvm.reflect early if the user
242 // has not provided a target architecture just yet.
243 if (Subtarget.hasTargetName())
244 PM.addPass(Pass: NVVMReflectPass(Subtarget.getSmVersion()));
245
246 FunctionPassManager FPM;
247 // Note: NVVMIntrRangePass was causing numerical discrepancies at one
248 // point, if issues crop up, consider disabling.
249 FPM.addPass(Pass: NVVMIntrRangePass());
250 if (EarlyByValArgsCopy)
251 FPM.addPass(Pass: NVPTXCopyByValArgsPass());
252 PM.addPass(Pass: createModuleToFunctionPassAdaptor(Pass: std::move(FPM)));
253 });
254
255 if (!NoKernelInfoEndLTO) {
256 PB.registerFullLinkTimeOptimizationLastEPCallback(
257 C: [this](ModulePassManager &PM, OptimizationLevel Level) {
258 FunctionPassManager FPM;
259 FPM.addPass(Pass: KernelInfoPrinter(this));
260 PM.addPass(Pass: createModuleToFunctionPassAdaptor(Pass: std::move(FPM)));
261 });
262 }
263}
264
265TargetTransformInfo
266NVPTXTargetMachine::getTargetTransformInfo(const Function &F) const {
267 return TargetTransformInfo(std::make_unique<NVPTXTTIImpl>(args: this, args: F));
268}
269
270std::pair<const Value *, unsigned>
271NVPTXTargetMachine::getPredicatedAddrSpace(const Value *V) const {
272 if (auto *II = dyn_cast<IntrinsicInst>(Val: V)) {
273 switch (II->getIntrinsicID()) {
274 case Intrinsic::nvvm_isspacep_const:
275 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_CONST);
276 case Intrinsic::nvvm_isspacep_global:
277 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_GLOBAL);
278 case Intrinsic::nvvm_isspacep_local:
279 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_LOCAL);
280 case Intrinsic::nvvm_isspacep_shared:
281 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_SHARED);
282 case Intrinsic::nvvm_isspacep_shared_cluster:
283 return std::make_pair(x: II->getArgOperand(i: 0),
284 y: llvm::ADDRESS_SPACE_SHARED_CLUSTER);
285 default:
286 break;
287 }
288 }
289 return std::make_pair(x: nullptr, y: -1);
290}
291
292void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
293 if (getOptLevel() == CodeGenOptLevel::Aggressive)
294 addPass(P: createGVNPass());
295 else
296 addPass(P: createEarlyCSEPass());
297}
298
299void NVPTXPassConfig::addAddressSpaceInferencePasses() {
300 // NVPTXLowerArgs emits alloca for byval parameters which can often
301 // be eliminated by SROA.
302 addPass(P: createSROAPass());
303 addPass(P: createNVPTXLowerAllocaPass());
304 // TODO: Consider running InferAddressSpaces during opt, earlier in the
305 // compilation flow.
306 addPass(P: createInferAddressSpacesPass());
307 addPass(P: createNVPTXAtomicLowerPass());
308}
309
310void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() {
311 addPass(P: createSeparateConstOffsetFromGEPPass());
312 addPass(P: createSpeculativeExecutionPass());
313 // ReassociateGEPs exposes more opportunites for SLSR. See
314 // the example in reassociate-geps-and-slsr.ll.
315 addPass(P: createStraightLineStrengthReducePass());
316 // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
317 // EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE
318 // for some of our benchmarks.
319 addEarlyCSEOrGVNPass();
320 // Run NaryReassociate after EarlyCSE/GVN to be more effective.
321 addPass(P: createNaryReassociatePass());
322 // NaryReassociate on GEPs creates redundant common expressions, so run
323 // EarlyCSE after it.
324 addPass(P: createEarlyCSEPass());
325}
326
327void NVPTXPassConfig::addIRPasses() {
328 // The following passes are known to not play well with virtual regs hanging
329 // around after register allocation (which in our case, is *all* registers).
330 // We explicitly disable them here. We do, however, need some functionality
331 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
332 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
333 disablePass(PassID: &PrologEpilogCodeInserterID);
334 disablePass(PassID: &MachineLateInstrsCleanupID);
335 disablePass(PassID: &MachineCopyPropagationID);
336 disablePass(PassID: &TailDuplicateLegacyID);
337 disablePass(PassID: &StackMapLivenessID);
338 disablePass(PassID: &PostRAMachineSinkingID);
339 disablePass(PassID: &PostRASchedulerID);
340 disablePass(PassID: &FuncletLayoutID);
341 disablePass(PassID: &PatchableFunctionID);
342 disablePass(PassID: &ShrinkWrapID);
343 disablePass(PassID: &RemoveLoadsIntoFakeUsesID);
344
345 addPass(P: createNVPTXAAWrapperPass());
346 addPass(P: createNVPTXExternalAAWrapperPass());
347
348 // NVVMReflectPass is added in addEarlyAsPossiblePasses, so hopefully running
349 // it here does nothing. But since we need it for correctness when lowering
350 // to NVPTX, run it here too, in case whoever built our pass pipeline didn't
351 // call addEarlyAsPossiblePasses.
352 const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
353 addPass(P: createNVVMReflectPass(SmVersion: ST.getSmVersion()));
354
355 if (getOptLevel() != CodeGenOptLevel::None)
356 addPass(P: createNVPTXImageOptimizerPass());
357 addPass(P: createNVPTXAssignValidGlobalNamesPass());
358 addPass(P: createGenericToNVVMLegacyPass());
359
360 // NVPTXLowerArgs is required for correctness and should be run right
361 // before the address space inference passes.
362 if (getNVPTXTargetMachine().getDrvInterface() == NVPTX::CUDA)
363 addPass(P: createNVPTXMarkKernelPtrsGlobalPass());
364 addPass(P: createNVPTXSetByValParamAlignPass());
365 addPass(P: createNVPTXLowerArgsPass());
366 if (getOptLevel() != CodeGenOptLevel::None) {
367 addAddressSpaceInferencePasses();
368 addStraightLineScalarOptimizationPasses();
369 }
370
371 addPass(P: createAtomicExpandLegacyPass());
372 addPass(P: createExpandVariadicsPass(ExpandVariadicsMode::Lowering));
373 addPass(P: createNVPTXCtorDtorLoweringLegacyPass());
374
375 // === LSR and other generic IR passes ===
376 TargetPassConfig::addIRPasses();
377 // EarlyCSE is not always strong enough to clean up what LSR produces. For
378 // example, GVN can combine
379 //
380 // %0 = add %a, %b
381 // %1 = add %b, %a
382 //
383 // and
384 //
385 // %0 = shl nsw %a, 2
386 // %1 = shl %a, 2
387 //
388 // but EarlyCSE can do neither of them.
389 if (getOptLevel() != CodeGenOptLevel::None) {
390 addEarlyCSEOrGVNPass();
391 if (!DisableLoadStoreVectorizer)
392 addPass(P: createLoadStoreVectorizerPass());
393 addPass(P: createSROAPass());
394 addPass(P: createNVPTXTagInvariantLoadsPass());
395 if (!DisableNVPTXIRPeephole)
396 addPass(P: createNVPTXIRPeepholePass());
397 }
398
399 if (ST.hasPTXASUnreachableBug()) {
400 // Run LowerUnreachable to WAR a ptxas bug. See the commit description of
401 // 1ee4d880e8760256c606fe55b7af85a4f70d006d for more details.
402 const auto &Options = getNVPTXTargetMachine().Options;
403 addPass(P: createNVPTXLowerUnreachablePass(TrapUnreachable: Options.TrapUnreachable,
404 NoTrapAfterNoreturn: Options.NoTrapAfterNoreturn));
405 }
406}
407
408bool NVPTXPassConfig::addInstSelector() {
409 addPass(P: createLowerAggrCopies());
410 addPass(P: createAllocaHoisting());
411 addPass(P: createNVPTXISelDag(TM&: getNVPTXTargetMachine(), OptLevel: getOptLevel()));
412 addPass(P: createNVPTXReplaceImageHandlesPass());
413
414 return false;
415}
416
417void NVPTXPassConfig::addPreRegAlloc() {
418 addPass(P: createNVPTXForwardParamsPass());
419 // Remove Proxy Register pseudo instructions used to keep `callseq_end` alive.
420 addPass(P: createNVPTXProxyRegErasurePass());
421}
422
423void NVPTXPassConfig::addPostRegAlloc() {
424 addPass(P: createNVPTXPrologEpilogPass());
425 if (getOptLevel() != CodeGenOptLevel::None) {
426 // NVPTXPrologEpilogPass calculates frame object offset and replace frame
427 // index with VRFrame register. NVPTXPeephole need to be run after that and
428 // will replace VRFrame with VRFrameLocal when possible.
429 addPass(P: createNVPTXPeephole());
430 }
431}
432
433FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
434 return nullptr; // No reg alloc
435}
436
437void NVPTXPassConfig::addFastRegAlloc() {
438 addPass(PassID: &PHIEliminationID);
439 addPass(PassID: &TwoAddressInstructionPassID);
440}
441
442void NVPTXPassConfig::addOptimizedRegAlloc() {
443 addPass(PassID: &ProcessImplicitDefsID);
444 addPass(PassID: &LiveVariablesID);
445 addPass(PassID: &MachineLoopInfoID);
446 addPass(PassID: &PHIEliminationID);
447
448 addPass(PassID: &TwoAddressInstructionPassID);
449 addPass(PassID: &RegisterCoalescerID);
450
451 // PreRA instruction scheduling.
452 if (addPass(PassID: &MachineSchedulerID))
453 printAndVerify(Banner: "After Machine Scheduling");
454
455 addPass(PassID: &StackSlotColoringID);
456
457 // FIXME: Needs physical registers
458 // addPass(&MachineLICMID);
459
460 printAndVerify(Banner: "After StackSlotColoring");
461}
462
463void NVPTXPassConfig::addMachineSSAOptimization() {
464 // Pre-ra tail duplication.
465 if (addPass(PassID: &EarlyTailDuplicateLegacyID))
466 printAndVerify(Banner: "After Pre-RegAlloc TailDuplicate");
467
468 // Optimize PHIs before DCE: removing dead PHI cycles may make more
469 // instructions dead.
470 addPass(PassID: &OptimizePHIsLegacyID);
471
472 // This pass merges large allocas. StackSlotColoring is a different pass
473 // which merges spill slots.
474 addPass(PassID: &StackColoringLegacyID);
475
476 // If the target requests it, assign local variables to stack slots relative
477 // to one another and simplify frame index references where possible.
478 addPass(PassID: &LocalStackSlotAllocationID);
479
480 // With optimization, dead code should already be eliminated. However
481 // there is one known exception: lowered code for arguments that are only
482 // used by tail calls, where the tail calls reuse the incoming stack
483 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
484 addPass(PassID: &DeadMachineInstructionElimID);
485 printAndVerify(Banner: "After codegen DCE pass");
486
487 // Allow targets to insert passes that improve instruction level parallelism,
488 // like if-conversion. Such passes will typically need dominator trees and
489 // loop info, just like LICM and CSE below.
490 if (addILPOpts())
491 printAndVerify(Banner: "After ILP optimizations");
492
493 addPass(PassID: &EarlyMachineLICMID);
494 addPass(PassID: &MachineCSELegacyID);
495
496 addPass(PassID: &MachineSinkingLegacyID);
497 printAndVerify(Banner: "After Machine LICM, CSE and Sinking passes");
498
499 addPass(PassID: &PeepholeOptimizerLegacyID);
500 printAndVerify(Banner: "After codegen peephole optimization pass");
501}
502