1//===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Top-level implementation for the NVPTX target.
10//
11//===----------------------------------------------------------------------===//
12
13#include "NVPTXTargetMachine.h"
14#include "NVPTX.h"
15#include "NVPTXAliasAnalysis.h"
16#include "NVPTXAsmPrinter.h"
17#include "NVPTXMachineFunctionInfo.h"
18#include "NVPTXTargetObjectFile.h"
19#include "NVPTXTargetTransformInfo.h"
20#include "TargetInfo/NVPTXTargetInfo.h"
21#include "llvm/Analysis/TargetTransformInfo.h"
22#include "llvm/CodeGen/Passes.h"
23#include "llvm/CodeGen/TargetPassConfig.h"
24#include "llvm/IR/IntrinsicsNVPTX.h"
25#include "llvm/MC/TargetRegistry.h"
26#include "llvm/Pass.h"
27#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Compiler.h"
29#include "llvm/Target/TargetMachine.h"
30#include "llvm/Target/TargetOptions.h"
31#include "llvm/TargetParser/Triple.h"
32#include "llvm/Transforms/IPO/ExpandVariadics.h"
33#include "llvm/Transforms/Scalar.h"
34#include "llvm/Transforms/Scalar/GVN.h"
35#include "llvm/Transforms/Vectorize/LoadStoreVectorizer.h"
36#include <cassert>
37#include <optional>
38#include <string>
39
40using namespace llvm;
41
42// LSV is still relatively new; this switch lets us turn it off in case we
43// encounter (or suspect) a bug.
44cl::opt<bool>
45 DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer",
46 cl::desc("Disable load/store vectorizer"),
47 cl::init(Val: false), cl::Hidden);
48
49// NVPTX IR Peephole is a new pass; this option will lets us turn it off in case
50// we encounter some issues.
51cl::opt<bool> DisableNVPTXIRPeephole("disable-nvptx-ir-peephole",
52 cl::desc("Disable NVPTX IR Peephole"),
53 cl::init(Val: false), cl::Hidden);
54
55// TODO: Remove this flag when we are confident with no regressions.
56static cl::opt<bool> DisableRequireStructuredCFG(
57 "disable-nvptx-require-structured-cfg",
58 cl::desc("Transitional flag to turn off NVPTX's requirement on preserving "
59 "structured CFG. The requirement should be disabled only when "
60 "unexpected regressions happen."),
61 cl::init(Val: false), cl::Hidden);
62
63extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTarget() {
64 // Register the target.
65 RegisterTargetMachine<NVPTXTargetMachine> X(getTheNVPTXTarget32());
66 RegisterTargetMachine<NVPTXTargetMachine> Y(getTheNVPTXTarget64());
67
68 PassRegistry &PR = *PassRegistry::getPassRegistry();
69 // FIXME: This pass is really intended to be invoked during IR optimization,
70 // but it's very NVPTX-specific.
71 initializeNVVMReflectLegacyPassPass(PR);
72 initializeNVVMIntrRangePass(PR);
73 initializeGenericToNVVMLegacyPassPass(PR);
74 initializeNVPTXAllocaHoistingLegacyPassPass(PR);
75 initializeNVPTXAsmPrinterPass(PR);
76 initializeNVPTXAssignValidGlobalNamesLegacyPassPass(PR);
77 initializeNVPTXAtomicLowerLegacyPassPass(PR);
78 initializeNVPTXLowerArgsLegacyPassPass(PR);
79 initializeNVPTXPromoteParamAlignLegacyPassPass(PR);
80 initializeNVPTXMarkKernelPtrsGlobalLegacyPassPass(PR);
81 initializeNVPTXLowerAllocaLegacyPassPass(PR);
82 initializeNVPTXLowerUnreachableLegacyPassPass(PR);
83 initializeNVPTXCtorDtorLoweringLegacyPass(PR);
84 initializeNVPTXLowerAggrCopiesLegacyPassPass(PR);
85 initializeNVPTXProxyRegErasureLegacyPassPass(PR);
86 initializeNVPTXForwardParamsLegacyPassPass(PR);
87 initializeNVPTXAddressFolderLegacyPassPass(PR);
88 initializeNVPTXDAGToDAGISelLegacyPass(PR);
89 initializeNVPTXAAWrapperPassPass(PR);
90 initializeNVPTXExternalAAWrapperPass(PR);
91 initializeNVPTXPeepholeLegacyPassPass(PR);
92 initializeNVPTXTagInvariantLoadLegacyPassPass(PR);
93 initializeNVPTXIRPeepholePass(PR);
94 initializeNVPTXPrologEpilogLegacyPassPass(PR);
95}
96
97NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,
98 StringRef CPU, StringRef FS,
99 const TargetOptions &Options,
100 std::optional<Reloc::Model> RM,
101 std::optional<CodeModel::Model> CM,
102 CodeGenOptLevel OL, bool JIT)
103 // The pic relocation model is used regardless of what the client has
104 // specified, as it is the only relocation model currently supported.
105 : CodeGenTargetMachineImpl(T,
106 TT.computeDataLayout(ABIName: Options.MCOptions.ABIName),
107 TT, CPU, FS, Options, Reloc::PIC_,
108 getEffectiveCodeModel(CM, Default: CodeModel::Small), OL),
109 TLOF(std::make_unique<NVPTXTargetObjectFile>()),
110 Subtarget(TT, CPU, FS, *this), StrPool(StrAlloc) {
111 if (!DisableRequireStructuredCFG)
112 setRequiresStructuredCFG(true);
113 // NVPTX does not produce verifier-clean MIR yet; see isMachineVerifierClean()
114 // for the legacy pass manager equivalent.
115 setEnableDefaultMachineVerifier(false);
116 initAsmInfo();
117}
118
119NVPTXTargetMachine::~NVPTXTargetMachine() = default;
120
121namespace {
122
123/// NVPTXPassConfig mirrors the NewPM implementation in NVPTXCodeGenPassBuilder
124/// in NVPTXCodeGenPassBuilder.cpp; the two must be kept in sync until this path
125/// is removed.
126class NVPTXPassConfig : public TargetPassConfig {
127public:
128 NVPTXPassConfig(NVPTXTargetMachine &TM, PassManagerBase &PM)
129 : TargetPassConfig(TM, PM) {}
130
131 NVPTXTargetMachine &getNVPTXTargetMachine() const {
132 return getTM<NVPTXTargetMachine>();
133 }
134
135 void addIRPasses() override;
136 bool addInstSelector() override;
137 void addPreRegAlloc() override;
138 void addPostRegAlloc() override;
139
140 FunctionPass *createTargetRegisterAllocator(bool) override;
141 void addFastRegAlloc() override;
142 void addOptimizedRegAlloc() override;
143
144 bool addRegAssignAndRewriteFast() override {
145 llvm_unreachable("should not be used");
146 }
147
148 bool addRegAssignAndRewriteOptimized() override {
149 llvm_unreachable("should not be used");
150 }
151
152private:
153 // If the opt level is aggressive, add GVN; otherwise, add EarlyCSE. This
154 // function is only called in opt mode.
155 void addEarlyCSEOrGVNPass();
156
157 // Add passes that propagate special memory spaces.
158 void addAddressSpaceInferencePasses();
159
160 // Add passes that perform straight-line scalar optimizations.
161 void addStraightLineScalarOptimizationPasses();
162};
163
164} // end anonymous namespace
165
166TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
167 return new NVPTXPassConfig(*this, PM);
168}
169
170MachineFunctionInfo *NVPTXTargetMachine::createMachineFunctionInfo(
171 BumpPtrAllocator &Allocator, const Function &F,
172 const TargetSubtargetInfo *STI) const {
173 return NVPTXMachineFunctionInfo::create<NVPTXMachineFunctionInfo>(Allocator,
174 F, STI);
175}
176
177void NVPTXTargetMachine::registerEarlyDefaultAliasAnalyses(AAManager &AAM) {
178 AAM.registerFunctionAnalysis<NVPTXAA>();
179}
180
181TargetTransformInfo
182NVPTXTargetMachine::getTargetTransformInfo(const Function &F) const {
183 return TargetTransformInfo(std::make_unique<NVPTXTTIImpl>(args: this, args: F));
184}
185
186std::pair<const Value *, unsigned>
187NVPTXTargetMachine::getPredicatedAddrSpace(const Value *V) const {
188 if (auto *II = dyn_cast<IntrinsicInst>(Val: V)) {
189 switch (II->getIntrinsicID()) {
190 case Intrinsic::nvvm_isspacep_const:
191 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_CONST);
192 case Intrinsic::nvvm_isspacep_global:
193 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_GLOBAL);
194 case Intrinsic::nvvm_isspacep_local:
195 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_LOCAL);
196 case Intrinsic::nvvm_isspacep_shared:
197 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_SHARED);
198 case Intrinsic::nvvm_isspacep_shared_cluster:
199 return std::make_pair(x: II->getArgOperand(i: 0),
200 y: llvm::ADDRESS_SPACE_SHARED_CLUSTER);
201 default:
202 break;
203 }
204 }
205 return std::make_pair(x: nullptr, y: -1);
206}
207
208void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
209 if (getOptLevel() == CodeGenOptLevel::Aggressive)
210 // Disable scalar PRE due to Register Pressure increase
211 addPass(P: createGVNPass(/*ScalarPRE=*/false));
212 else
213 addPass(P: createEarlyCSEPass());
214}
215
216void NVPTXPassConfig::addAddressSpaceInferencePasses() {
217 // NVPTXLowerArgs emits alloca for byval parameters which can often
218 // be eliminated by SROA.
219 addPass(P: createSROAPass(/*PreserveCFG=*/true,
220 /*AggregateToVector=*/true));
221 addPass(P: createNVPTXLowerAllocaLegacyPass());
222 // TODO: Consider running InferAddressSpaces during opt, earlier in the
223 // compilation flow.
224 addPass(P: createInferAddressSpacesPass());
225 addPass(P: createNVPTXAtomicLowerLegacyPass());
226}
227
228void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() {
229 addPass(P: createSeparateConstOffsetFromGEPPass());
230 addPass(P: createSpeculativeExecutionPass());
231 // ReassociateGEPs exposes more opportunites for SLSR. See
232 // the example in reassociate-geps-and-slsr.ll.
233 addPass(P: createStraightLineStrengthReducePass());
234 // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
235 // EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE
236 // for some of our benchmarks.
237 addEarlyCSEOrGVNPass();
238 // Run NaryReassociate after EarlyCSE/GVN to be more effective.
239 addPass(P: createNaryReassociatePass());
240 // NaryReassociate on GEPs creates redundant common expressions, so run
241 // EarlyCSE after it.
242 addPass(P: createEarlyCSEPass());
243}
244
245void NVPTXPassConfig::addIRPasses() {
246 // The following passes are known to not play well with virtual regs hanging
247 // around after register allocation (which in our case, is *all* registers).
248 // We explicitly disable them here. We do, however, need some functionality
249 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
250 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
251 disablePass(PassID: &PrologEpilogCodeInserterID);
252 disablePass(PassID: &MachineLateInstrsCleanupID);
253 disablePass(PassID: &MachineCopyPropagationID);
254 disablePass(PassID: &TailDuplicateLegacyID);
255 disablePass(PassID: &StackMapLivenessID);
256 disablePass(PassID: &PostRAMachineSinkingID);
257 disablePass(PassID: &PostRASchedulerID);
258 disablePass(PassID: &FuncletLayoutID);
259 disablePass(PassID: &PatchableFunctionID);
260 disablePass(PassID: &ShrinkWrapID);
261 disablePass(PassID: &RemoveLoadsIntoFakeUsesID);
262
263 addPass(P: createNVPTXAAWrapperPass());
264 addPass(P: createNVPTXExternalAAWrapperPass());
265
266 // NVVMReflectPass is added in addEarlyAsPossiblePasses, so hopefully running
267 // it here does nothing. But since we need it for correctness when lowering
268 // to NVPTX, run it here too, in case whoever built our pass pipeline didn't
269 // call addEarlyAsPossiblePasses.
270 const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
271 addPass(P: createNVVMReflectPass(SmVersion: ST.getSmVersion()));
272
273 if (getOptLevel() != CodeGenOptLevel::None)
274 addPass(P: createNVPTXImageOptimizerLegacyPass());
275 addPass(P: createNVPTXAssignValidGlobalNamesLegacyPass());
276 addPass(P: createGenericToNVVMLegacyPass());
277
278 // Lower variadic calls before address space inference.
279 addPass(P: createExpandVariadicsPass(ExpandVariadicsMode::Lowering));
280
281 // NVPTXLowerArgs is required for correctness and should be run right
282 // before the address space inference passes.
283 if (getNVPTXTargetMachine().getDrvInterface() == NVPTX::CUDA)
284 addPass(P: createNVPTXMarkKernelPtrsGlobalPass());
285 addPass(P: createNVPTXPromoteParamAlignPass());
286 addPass(P: createNVPTXLowerArgsPass());
287 if (getOptLevel() != CodeGenOptLevel::None) {
288 addAddressSpaceInferencePasses();
289 addStraightLineScalarOptimizationPasses();
290 } else {
291 // Required for correct stack lowering
292 addPass(P: createNVPTXLowerAllocaLegacyPass());
293 }
294
295 addPass(P: createAtomicExpandLegacyPass());
296 addPass(P: createNVPTXCtorDtorLoweringLegacyPass());
297
298 // === LSR and other generic IR passes ===
299 TargetPassConfig::addIRPasses();
300 // EarlyCSE is not always strong enough to clean up what LSR produces. For
301 // example, GVN can combine
302 //
303 // %0 = add %a, %b
304 // %1 = add %b, %a
305 //
306 // and
307 //
308 // %0 = shl nsw %a, 2
309 // %1 = shl %a, 2
310 //
311 // but EarlyCSE can do neither of them.
312 if (getOptLevel() != CodeGenOptLevel::None) {
313 addEarlyCSEOrGVNPass();
314 if (!DisableLoadStoreVectorizer)
315 addPass(P: createLoadStoreVectorizerPass());
316 addPass(P: createSROAPass(/*PreserveCFG=*/true,
317 /*AggregateToVector=*/true));
318 addPass(P: createNVPTXTagInvariantLoadsPass());
319 if (!DisableNVPTXIRPeephole)
320 addPass(P: createNVPTXIRPeepholePass());
321 }
322
323 if (ST.hasPTXASUnreachableBug()) {
324 // Run LowerUnreachable to WAR a ptxas bug. See the commit description of
325 // 1ee4d880e8760256c606fe55b7af85a4f70d006d for more details.
326 const auto &Options = getNVPTXTargetMachine().Options;
327 addPass(P: createNVPTXLowerUnreachableLegacyPass(TrapUnreachable: Options.TrapUnreachable,
328 NoTrapAfterNoreturn: Options.NoTrapAfterNoreturn));
329 }
330}
331
332bool NVPTXPassConfig::addInstSelector() {
333 addPass(P: createNVPTXLowerAggrCopiesLegacyPass());
334 addPass(P: createNVPTXAllocaHoistingLegacyPass());
335 addPass(P: createNVPTXISelDag(TM&: getNVPTXTargetMachine(), OptLevel: getOptLevel()));
336 addPass(P: createNVPTXReplaceImageHandlesLegacyPass());
337
338 return false;
339}
340
341void NVPTXPassConfig::addPreRegAlloc() {
342 addPass(P: createNVPTXForwardParamsLegacyPass());
343 if (getOptLevel() != CodeGenOptLevel::None)
344 addPass(P: createNVPTXAddressFolderLegacyPass());
345 // Remove Proxy Register pseudo instructions used to keep `callseq_end` alive.
346 addPass(P: createNVPTXProxyRegErasureLegacyPass());
347}
348
349void NVPTXPassConfig::addPostRegAlloc() {
350 addPass(P: createNVPTXPrologEpilogLegacyPass());
351 if (getOptLevel() != CodeGenOptLevel::None) {
352 // NVPTXPrologEpilogPass calculates frame object offset and replace frame
353 // index with VRFrame register. NVPTXPeephole need to be run after that and
354 // will replace VRFrame with VRFrameLocal when possible.
355 addPass(P: createNVPTXPeepholeLegacyPass());
356 }
357}
358
359FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
360 return nullptr; // No reg alloc
361}
362
363void NVPTXPassConfig::addFastRegAlloc() {
364 addPass(PassID: &PHIEliminationID);
365 addPass(PassID: &TwoAddressInstructionPassID);
366}
367
368void NVPTXPassConfig::addOptimizedRegAlloc() {
369 addPass(PassID: &ProcessImplicitDefsID);
370 addPass(PassID: &LiveVariablesID);
371 addPass(PassID: &MachineLoopInfoID);
372 addPass(PassID: &PHIEliminationID);
373
374 addPass(PassID: &TwoAddressInstructionPassID);
375 addPass(PassID: &RegisterCoalescerID);
376
377 // PreRA instruction scheduling.
378 if (addPass(PassID: &MachineSchedulerID))
379 printAndVerify(Banner: "After Machine Scheduling");
380
381 addPass(PassID: &StackSlotColoringID);
382
383 // FIXME: Needs physical registers
384 // addPass(&MachineLICMID);
385
386 printAndVerify(Banner: "After StackSlotColoring");
387}
388