1//===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Top-level implementation for the NVPTX target.
10//
11//===----------------------------------------------------------------------===//
12
13#include "NVPTXTargetMachine.h"
14#include "NVPTX.h"
15#include "NVPTXAliasAnalysis.h"
16#include "NVPTXAllocaHoisting.h"
17#include "NVPTXAtomicLower.h"
18#include "NVPTXCtorDtorLowering.h"
19#include "NVPTXLowerAggrCopies.h"
20#include "NVPTXMachineFunctionInfo.h"
21#include "NVPTXTargetObjectFile.h"
22#include "NVPTXTargetTransformInfo.h"
23#include "TargetInfo/NVPTXTargetInfo.h"
24#include "llvm/Analysis/KernelInfo.h"
25#include "llvm/Analysis/TargetTransformInfo.h"
26#include "llvm/CodeGen/Passes.h"
27#include "llvm/CodeGen/TargetPassConfig.h"
28#include "llvm/IR/IntrinsicsNVPTX.h"
29#include "llvm/MC/TargetRegistry.h"
30#include "llvm/Pass.h"
31#include "llvm/Passes/PassBuilder.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/Compiler.h"
34#include "llvm/Target/TargetMachine.h"
35#include "llvm/Target/TargetOptions.h"
36#include "llvm/TargetParser/Triple.h"
37#include "llvm/Transforms/IPO/ExpandVariadics.h"
38#include "llvm/Transforms/Scalar.h"
39#include "llvm/Transforms/Scalar/GVN.h"
40#include "llvm/Transforms/Vectorize/LoadStoreVectorizer.h"
41#include <cassert>
42#include <optional>
43#include <string>
44
45using namespace llvm;
46
47// LSV is still relatively new; this switch lets us turn it off in case we
48// encounter (or suspect) a bug.
49static cl::opt<bool>
50 DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer",
51 cl::desc("Disable load/store vectorizer"),
52 cl::init(Val: false), cl::Hidden);
53
54// NVPTX IR Peephole is a new pass; this option will lets us turn it off in case
55// we encounter some issues.
56static cl::opt<bool>
57 DisableNVPTXIRPeephole("disable-nvptx-ir-peephole",
58 cl::desc("Disable NVPTX IR Peephole"),
59 cl::init(Val: false), cl::Hidden);
60
61// TODO: Remove this flag when we are confident with no regressions.
62static cl::opt<bool> DisableRequireStructuredCFG(
63 "disable-nvptx-require-structured-cfg",
64 cl::desc("Transitional flag to turn off NVPTX's requirement on preserving "
65 "structured CFG. The requirement should be disabled only when "
66 "unexpected regressions happen."),
67 cl::init(Val: false), cl::Hidden);
68
69static cl::opt<bool> UseShortPointersOpt(
70 "nvptx-short-ptr",
71 cl::desc(
72 "Use 32-bit pointers for accessing const/local/shared address spaces."),
73 cl::init(Val: false), cl::Hidden);
74
75// byval arguments in NVPTX are special. We're only allowed to read from them
76// using a special instruction, and if we ever need to write to them or take an
77// address, we must make a local copy and use it, instead.
78//
79// The problem is that local copies are very expensive, and we create them very
80// late in the compilation pipeline, so LLVM does not have much of a chance to
81// eliminate them, if they turn out to be unnecessary.
82//
83// One way around that is to create such copies early on, and let them percolate
84// through the optimizations. The copying itself will never trigger creation of
85// another copy later on, as the reads are allowed. If LLVM can eliminate it,
86// it's a win. It the full optimization pipeline can't remove the copy, that's
87// as good as it gets in terms of the effort we could've done, and it's
88// certainly a much better effort than what we do now.
89//
90// This early injection of the copies has potential to create undesireable
91// side-effects, so it's disabled by default, for now, until it sees more
92// testing.
93static cl::opt<bool> EarlyByValArgsCopy(
94 "nvptx-early-byval-copy",
95 cl::desc("Create a copy of byval function arguments early."),
96 cl::init(Val: false), cl::Hidden);
97
98extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTarget() {
99 // Register the target.
100 RegisterTargetMachine<NVPTXTargetMachine32> X(getTheNVPTXTarget32());
101 RegisterTargetMachine<NVPTXTargetMachine64> Y(getTheNVPTXTarget64());
102
103 PassRegistry &PR = *PassRegistry::getPassRegistry();
104 // FIXME: This pass is really intended to be invoked during IR optimization,
105 // but it's very NVPTX-specific.
106 initializeNVVMReflectLegacyPassPass(PR);
107 initializeNVVMIntrRangePass(PR);
108 initializeGenericToNVVMLegacyPassPass(PR);
109 initializeNVPTXAllocaHoistingPass(PR);
110 initializeNVPTXAsmPrinterPass(PR);
111 initializeNVPTXAssignValidGlobalNamesPass(PR);
112 initializeNVPTXAtomicLowerPass(PR);
113 initializeNVPTXLowerArgsLegacyPassPass(PR);
114 initializeNVPTXMarkKernelPtrsGlobalLegacyPassPass(PR);
115 initializeNVPTXLowerAllocaPass(PR);
116 initializeNVPTXLowerUnreachablePass(PR);
117 initializeNVPTXCtorDtorLoweringLegacyPass(PR);
118 initializeNVPTXLowerAggrCopiesPass(PR);
119 initializeNVPTXProxyRegErasurePass(PR);
120 initializeNVPTXForwardParamsPassPass(PR);
121 initializeNVPTXDAGToDAGISelLegacyPass(PR);
122 initializeNVPTXAAWrapperPassPass(PR);
123 initializeNVPTXExternalAAWrapperPass(PR);
124 initializeNVPTXPeepholePass(PR);
125 initializeNVPTXTagInvariantLoadLegacyPassPass(PR);
126 initializeNVPTXIRPeepholePass(PR);
127 initializeNVPTXPrologEpilogPassPass(PR);
128}
129
130NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,
131 StringRef CPU, StringRef FS,
132 const TargetOptions &Options,
133 std::optional<Reloc::Model> RM,
134 std::optional<CodeModel::Model> CM,
135 CodeGenOptLevel OL, bool is64bit)
136 // The pic relocation model is used regardless of what the client has
137 // specified, as it is the only relocation model currently supported.
138 : CodeGenTargetMachineImpl(
139 T, TT.computeDataLayout(ABIName: UseShortPointersOpt ? "shortptr" : ""), TT,
140 CPU, FS, Options, Reloc::PIC_,
141 getEffectiveCodeModel(CM, Default: CodeModel::Small), OL),
142 is64bit(is64bit), TLOF(std::make_unique<NVPTXTargetObjectFile>()),
143 Subtarget(TT, std::string(CPU), std::string(FS), *this),
144 StrPool(StrAlloc) {
145 if (TT.getOS() == Triple::NVCL)
146 drvInterface = NVPTX::NVCL;
147 else
148 drvInterface = NVPTX::CUDA;
149 if (!DisableRequireStructuredCFG)
150 setRequiresStructuredCFG(true);
151 initAsmInfo();
152}
153
154NVPTXTargetMachine::~NVPTXTargetMachine() = default;
155
156void NVPTXTargetMachine32::anchor() {}
157
158NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, const Triple &TT,
159 StringRef CPU, StringRef FS,
160 const TargetOptions &Options,
161 std::optional<Reloc::Model> RM,
162 std::optional<CodeModel::Model> CM,
163 CodeGenOptLevel OL, bool JIT)
164 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
165
166void NVPTXTargetMachine64::anchor() {}
167
168NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, const Triple &TT,
169 StringRef CPU, StringRef FS,
170 const TargetOptions &Options,
171 std::optional<Reloc::Model> RM,
172 std::optional<CodeModel::Model> CM,
173 CodeGenOptLevel OL, bool JIT)
174 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
175
176namespace {
177
178class NVPTXPassConfig : public TargetPassConfig {
179public:
180 NVPTXPassConfig(NVPTXTargetMachine &TM, PassManagerBase &PM)
181 : TargetPassConfig(TM, PM) {}
182
183 NVPTXTargetMachine &getNVPTXTargetMachine() const {
184 return getTM<NVPTXTargetMachine>();
185 }
186
187 void addIRPasses() override;
188 bool addInstSelector() override;
189 void addPreRegAlloc() override;
190 void addPostRegAlloc() override;
191 void addMachineSSAOptimization() override;
192
193 FunctionPass *createTargetRegisterAllocator(bool) override;
194 void addFastRegAlloc() override;
195 void addOptimizedRegAlloc() override;
196
197 bool addRegAssignAndRewriteFast() override {
198 llvm_unreachable("should not be used");
199 }
200
201 bool addRegAssignAndRewriteOptimized() override {
202 llvm_unreachable("should not be used");
203 }
204
205private:
206 // If the opt level is aggressive, add GVN; otherwise, add EarlyCSE. This
207 // function is only called in opt mode.
208 void addEarlyCSEOrGVNPass();
209
210 // Add passes that propagate special memory spaces.
211 void addAddressSpaceInferencePasses();
212
213 // Add passes that perform straight-line scalar optimizations.
214 void addStraightLineScalarOptimizationPasses();
215};
216
217} // end anonymous namespace
218
219TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
220 return new NVPTXPassConfig(*this, PM);
221}
222
223MachineFunctionInfo *NVPTXTargetMachine::createMachineFunctionInfo(
224 BumpPtrAllocator &Allocator, const Function &F,
225 const TargetSubtargetInfo *STI) const {
226 return NVPTXMachineFunctionInfo::create<NVPTXMachineFunctionInfo>(Allocator,
227 F, STI);
228}
229
230void NVPTXTargetMachine::registerEarlyDefaultAliasAnalyses(AAManager &AAM) {
231 AAM.registerFunctionAnalysis<NVPTXAA>();
232}
233
234void NVPTXTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
235#define GET_PASS_REGISTRY "NVPTXPassRegistry.def"
236#include "llvm/Passes/TargetPassRegistry.inc"
237
238 PB.registerPipelineStartEPCallback(
239 C: [this](ModulePassManager &PM, OptimizationLevel Level) {
240 // We do not want to fold out calls to nvvm.reflect early if the user
241 // has not provided a target architecture just yet.
242 if (Subtarget.hasTargetName())
243 PM.addPass(Pass: NVVMReflectPass(Subtarget.getSmVersion()));
244
245 FunctionPassManager FPM;
246 // Note: NVVMIntrRangePass was causing numerical discrepancies at one
247 // point, if issues crop up, consider disabling.
248 FPM.addPass(Pass: NVVMIntrRangePass());
249 if (EarlyByValArgsCopy)
250 FPM.addPass(Pass: NVPTXCopyByValArgsPass());
251 PM.addPass(Pass: createModuleToFunctionPassAdaptor(Pass: std::move(FPM)));
252 });
253
254 if (!NoKernelInfoEndLTO) {
255 PB.registerFullLinkTimeOptimizationLastEPCallback(
256 C: [this](ModulePassManager &PM, OptimizationLevel Level) {
257 FunctionPassManager FPM;
258 FPM.addPass(Pass: KernelInfoPrinter(this));
259 PM.addPass(Pass: createModuleToFunctionPassAdaptor(Pass: std::move(FPM)));
260 });
261 }
262}
263
264TargetTransformInfo
265NVPTXTargetMachine::getTargetTransformInfo(const Function &F) const {
266 return TargetTransformInfo(std::make_unique<NVPTXTTIImpl>(args: this, args: F));
267}
268
269std::pair<const Value *, unsigned>
270NVPTXTargetMachine::getPredicatedAddrSpace(const Value *V) const {
271 if (auto *II = dyn_cast<IntrinsicInst>(Val: V)) {
272 switch (II->getIntrinsicID()) {
273 case Intrinsic::nvvm_isspacep_const:
274 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_CONST);
275 case Intrinsic::nvvm_isspacep_global:
276 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_GLOBAL);
277 case Intrinsic::nvvm_isspacep_local:
278 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_LOCAL);
279 case Intrinsic::nvvm_isspacep_shared:
280 return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_SHARED);
281 case Intrinsic::nvvm_isspacep_shared_cluster:
282 return std::make_pair(x: II->getArgOperand(i: 0),
283 y: llvm::ADDRESS_SPACE_SHARED_CLUSTER);
284 default:
285 break;
286 }
287 }
288 return std::make_pair(x: nullptr, y: -1);
289}
290
291void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
292 if (getOptLevel() == CodeGenOptLevel::Aggressive)
293 addPass(P: createGVNPass());
294 else
295 addPass(P: createEarlyCSEPass());
296}
297
298void NVPTXPassConfig::addAddressSpaceInferencePasses() {
299 // NVPTXLowerArgs emits alloca for byval parameters which can often
300 // be eliminated by SROA.
301 addPass(P: createSROAPass());
302 addPass(P: createNVPTXLowerAllocaPass());
303 // TODO: Consider running InferAddressSpaces during opt, earlier in the
304 // compilation flow.
305 addPass(P: createInferAddressSpacesPass());
306 addPass(P: createNVPTXAtomicLowerPass());
307}
308
309void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() {
310 addPass(P: createSeparateConstOffsetFromGEPPass());
311 addPass(P: createSpeculativeExecutionPass());
312 // ReassociateGEPs exposes more opportunites for SLSR. See
313 // the example in reassociate-geps-and-slsr.ll.
314 addPass(P: createStraightLineStrengthReducePass());
315 // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
316 // EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE
317 // for some of our benchmarks.
318 addEarlyCSEOrGVNPass();
319 // Run NaryReassociate after EarlyCSE/GVN to be more effective.
320 addPass(P: createNaryReassociatePass());
321 // NaryReassociate on GEPs creates redundant common expressions, so run
322 // EarlyCSE after it.
323 addPass(P: createEarlyCSEPass());
324}
325
326void NVPTXPassConfig::addIRPasses() {
327 // The following passes are known to not play well with virtual regs hanging
328 // around after register allocation (which in our case, is *all* registers).
329 // We explicitly disable them here. We do, however, need some functionality
330 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
331 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
332 disablePass(PassID: &PrologEpilogCodeInserterID);
333 disablePass(PassID: &MachineLateInstrsCleanupID);
334 disablePass(PassID: &MachineCopyPropagationID);
335 disablePass(PassID: &TailDuplicateLegacyID);
336 disablePass(PassID: &StackMapLivenessID);
337 disablePass(PassID: &PostRAMachineSinkingID);
338 disablePass(PassID: &PostRASchedulerID);
339 disablePass(PassID: &FuncletLayoutID);
340 disablePass(PassID: &PatchableFunctionID);
341 disablePass(PassID: &ShrinkWrapID);
342 disablePass(PassID: &RemoveLoadsIntoFakeUsesID);
343
344 addPass(P: createNVPTXAAWrapperPass());
345 addPass(P: createNVPTXExternalAAWrapperPass());
346
347 // NVVMReflectPass is added in addEarlyAsPossiblePasses, so hopefully running
348 // it here does nothing. But since we need it for correctness when lowering
349 // to NVPTX, run it here too, in case whoever built our pass pipeline didn't
350 // call addEarlyAsPossiblePasses.
351 const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
352 addPass(P: createNVVMReflectPass(SmVersion: ST.getSmVersion()));
353
354 if (getOptLevel() != CodeGenOptLevel::None)
355 addPass(P: createNVPTXImageOptimizerPass());
356 addPass(P: createNVPTXAssignValidGlobalNamesPass());
357 addPass(P: createGenericToNVVMLegacyPass());
358
359 // NVPTXLowerArgs is required for correctness and should be run right
360 // before the address space inference passes.
361 if (getNVPTXTargetMachine().getDrvInterface() == NVPTX::CUDA)
362 addPass(P: createNVPTXMarkKernelPtrsGlobalPass());
363 addPass(P: createNVPTXLowerArgsPass());
364 if (getOptLevel() != CodeGenOptLevel::None) {
365 addAddressSpaceInferencePasses();
366 addStraightLineScalarOptimizationPasses();
367 }
368
369 addPass(P: createAtomicExpandLegacyPass());
370 addPass(P: createExpandVariadicsPass(ExpandVariadicsMode::Lowering));
371 addPass(P: createNVPTXCtorDtorLoweringLegacyPass());
372
373 // === LSR and other generic IR passes ===
374 TargetPassConfig::addIRPasses();
375 // EarlyCSE is not always strong enough to clean up what LSR produces. For
376 // example, GVN can combine
377 //
378 // %0 = add %a, %b
379 // %1 = add %b, %a
380 //
381 // and
382 //
383 // %0 = shl nsw %a, 2
384 // %1 = shl %a, 2
385 //
386 // but EarlyCSE can do neither of them.
387 if (getOptLevel() != CodeGenOptLevel::None) {
388 addEarlyCSEOrGVNPass();
389 if (!DisableLoadStoreVectorizer)
390 addPass(P: createLoadStoreVectorizerPass());
391 addPass(P: createSROAPass());
392 addPass(P: createNVPTXTagInvariantLoadsPass());
393 if (!DisableNVPTXIRPeephole)
394 addPass(P: createNVPTXIRPeepholePass());
395 }
396
397 if (ST.hasPTXASUnreachableBug()) {
398 // Run LowerUnreachable to WAR a ptxas bug. See the commit description of
399 // 1ee4d880e8760256c606fe55b7af85a4f70d006d for more details.
400 const auto &Options = getNVPTXTargetMachine().Options;
401 addPass(P: createNVPTXLowerUnreachablePass(TrapUnreachable: Options.TrapUnreachable,
402 NoTrapAfterNoreturn: Options.NoTrapAfterNoreturn));
403 }
404}
405
406bool NVPTXPassConfig::addInstSelector() {
407 addPass(P: createLowerAggrCopies());
408 addPass(P: createAllocaHoisting());
409 addPass(P: createNVPTXISelDag(TM&: getNVPTXTargetMachine(), OptLevel: getOptLevel()));
410 addPass(P: createNVPTXReplaceImageHandlesPass());
411
412 return false;
413}
414
415void NVPTXPassConfig::addPreRegAlloc() {
416 addPass(P: createNVPTXForwardParamsPass());
417 // Remove Proxy Register pseudo instructions used to keep `callseq_end` alive.
418 addPass(P: createNVPTXProxyRegErasurePass());
419}
420
421void NVPTXPassConfig::addPostRegAlloc() {
422 addPass(P: createNVPTXPrologEpilogPass());
423 if (getOptLevel() != CodeGenOptLevel::None) {
424 // NVPTXPrologEpilogPass calculates frame object offset and replace frame
425 // index with VRFrame register. NVPTXPeephole need to be run after that and
426 // will replace VRFrame with VRFrameLocal when possible.
427 addPass(P: createNVPTXPeephole());
428 }
429}
430
431FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
432 return nullptr; // No reg alloc
433}
434
435void NVPTXPassConfig::addFastRegAlloc() {
436 addPass(PassID: &PHIEliminationID);
437 addPass(PassID: &TwoAddressInstructionPassID);
438}
439
440void NVPTXPassConfig::addOptimizedRegAlloc() {
441 addPass(PassID: &ProcessImplicitDefsID);
442 addPass(PassID: &LiveVariablesID);
443 addPass(PassID: &MachineLoopInfoID);
444 addPass(PassID: &PHIEliminationID);
445
446 addPass(PassID: &TwoAddressInstructionPassID);
447 addPass(PassID: &RegisterCoalescerID);
448
449 // PreRA instruction scheduling.
450 if (addPass(PassID: &MachineSchedulerID))
451 printAndVerify(Banner: "After Machine Scheduling");
452
453 addPass(PassID: &StackSlotColoringID);
454
455 // FIXME: Needs physical registers
456 // addPass(&MachineLICMID);
457
458 printAndVerify(Banner: "After StackSlotColoring");
459}
460
461void NVPTXPassConfig::addMachineSSAOptimization() {
462 // Pre-ra tail duplication.
463 if (addPass(PassID: &EarlyTailDuplicateLegacyID))
464 printAndVerify(Banner: "After Pre-RegAlloc TailDuplicate");
465
466 // Optimize PHIs before DCE: removing dead PHI cycles may make more
467 // instructions dead.
468 addPass(PassID: &OptimizePHIsLegacyID);
469
470 // This pass merges large allocas. StackSlotColoring is a different pass
471 // which merges spill slots.
472 addPass(PassID: &StackColoringLegacyID);
473
474 // If the target requests it, assign local variables to stack slots relative
475 // to one another and simplify frame index references where possible.
476 addPass(PassID: &LocalStackSlotAllocationID);
477
478 // With optimization, dead code should already be eliminated. However
479 // there is one known exception: lowered code for arguments that are only
480 // used by tail calls, where the tail calls reuse the incoming stack
481 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
482 addPass(PassID: &DeadMachineInstructionElimID);
483 printAndVerify(Banner: "After codegen DCE pass");
484
485 // Allow targets to insert passes that improve instruction level parallelism,
486 // like if-conversion. Such passes will typically need dominator trees and
487 // loop info, just like LICM and CSE below.
488 if (addILPOpts())
489 printAndVerify(Banner: "After ILP optimizations");
490
491 addPass(PassID: &EarlyMachineLICMID);
492 addPass(PassID: &MachineCSELegacyID);
493
494 addPass(PassID: &MachineSinkingLegacyID);
495 printAndVerify(Banner: "After Machine LICM, CSE and Sinking passes");
496
497 addPass(PassID: &PeepholeOptimizerLegacyID);
498 printAndVerify(Banner: "After codegen peephole optimization pass");
499}
500