1//===-- SPIRVGlobalRegistry.cpp - SPIR-V Global Registry --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the implementation of the SPIRVGlobalRegistry class,
10// which is used to maintain rich type information required for SPIR-V even
11// after lowering from LLVM IR to GMIR. It can convert an llvm::Type into
12// an OpTypeXXX instruction, and map it to a virtual register. Also it builds
13// and supports consistency of constants and global variables.
14//
15//===----------------------------------------------------------------------===//
16
17#include "SPIRVGlobalRegistry.h"
18#include "SPIRV.h"
19#include "SPIRVBuiltins.h"
20#include "SPIRVSubtarget.h"
21#include "SPIRVUtils.h"
22#include "llvm/ADT/APInt.h"
23#include "llvm/IR/Constants.h"
24#include "llvm/IR/DiagnosticInfo.h"
25#include "llvm/IR/Function.h"
26#include "llvm/IR/IntrinsicInst.h"
27#include "llvm/IR/Intrinsics.h"
28#include "llvm/IR/IntrinsicsSPIRV.h"
29#include "llvm/IR/Type.h"
30#include "llvm/Support/Casting.h"
31#include "llvm/Support/MathExtras.h"
32#include <cassert>
33#include <functional>
34
35using namespace llvm;
36
37static bool allowEmitFakeUse(const Value *Arg) {
38 if (isSpvIntrinsic(Arg))
39 return false;
40 if (isa<AtomicCmpXchgInst, InsertValueInst, UndefValue>(Val: Arg))
41 return false;
42 if (const auto *LI = dyn_cast<LoadInst>(Val: Arg))
43 if (LI->getType()->isAggregateType())
44 return false;
45 return true;
46}
47
48static unsigned typeToAddressSpace(const Type *Ty) {
49 if (auto PType = dyn_cast<TypedPointerType>(Val: Ty))
50 return PType->getAddressSpace();
51 if (auto PType = dyn_cast<PointerType>(Val: Ty))
52 return PType->getAddressSpace();
53 if (auto *ExtTy = dyn_cast<TargetExtType>(Val: Ty);
54 ExtTy && isTypedPointerWrapper(ExtTy))
55 return ExtTy->getIntParameter(i: 0);
56 reportFatalInternalError(reason: "Unable to convert LLVM type to SPIRVType");
57}
58
59static bool
60storageClassRequiresExplictLayout(SPIRV::StorageClass::StorageClass SC) {
61 switch (SC) {
62 case SPIRV::StorageClass::Uniform:
63 case SPIRV::StorageClass::PushConstant:
64 case SPIRV::StorageClass::StorageBuffer:
65 case SPIRV::StorageClass::PhysicalStorageBufferEXT:
66 return true;
67 case SPIRV::StorageClass::UniformConstant:
68 case SPIRV::StorageClass::Input:
69 case SPIRV::StorageClass::Output:
70 case SPIRV::StorageClass::Workgroup:
71 case SPIRV::StorageClass::CrossWorkgroup:
72 case SPIRV::StorageClass::Private:
73 case SPIRV::StorageClass::Function:
74 case SPIRV::StorageClass::Generic:
75 case SPIRV::StorageClass::AtomicCounter:
76 case SPIRV::StorageClass::Image:
77 case SPIRV::StorageClass::CallableDataNV:
78 case SPIRV::StorageClass::IncomingCallableDataNV:
79 case SPIRV::StorageClass::RayPayloadNV:
80 case SPIRV::StorageClass::HitAttributeNV:
81 case SPIRV::StorageClass::IncomingRayPayloadNV:
82 case SPIRV::StorageClass::ShaderRecordBufferNV:
83 case SPIRV::StorageClass::CodeSectionINTEL:
84 case SPIRV::StorageClass::DeviceOnlyINTEL:
85 case SPIRV::StorageClass::HostOnlyINTEL:
86 return false;
87 }
88 llvm_unreachable("Unknown SPIRV::StorageClass enum");
89}
90
91SPIRVGlobalRegistry::SPIRVGlobalRegistry(DataLayout DL)
92 : DL(DL), Bound(0), CurMF(nullptr) {}
93
94SPIRVTypeInst
95SPIRVGlobalRegistry::assignIntTypeToVReg(unsigned BitWidth, Register VReg,
96 MachineInstr &I,
97 const SPIRVInstrInfo &TII) {
98 SPIRVTypeInst SpirvType = getOrCreateSPIRVIntegerType(BitWidth, I, TII);
99 assignSPIRVTypeToVReg(Type: SpirvType, VReg, MF: *CurMF);
100 return SpirvType;
101}
102
103SPIRVTypeInst
104SPIRVGlobalRegistry::assignFloatTypeToVReg(unsigned BitWidth, Register VReg,
105 MachineInstr &I,
106 const SPIRVInstrInfo &TII) {
107 SPIRVTypeInst SpirvType = getOrCreateSPIRVFloatType(BitWidth, I, TII);
108 assignSPIRVTypeToVReg(Type: SpirvType, VReg, MF: *CurMF);
109 return SpirvType;
110}
111
112SPIRVTypeInst SPIRVGlobalRegistry::assignVectTypeToVReg(
113 SPIRVTypeInst BaseType, unsigned NumElements, Register VReg,
114 MachineInstr &I, const SPIRVInstrInfo &TII) {
115 SPIRVTypeInst SpirvType =
116 getOrCreateSPIRVVectorType(BaseType, NumElements, I, TII);
117 assignSPIRVTypeToVReg(Type: SpirvType, VReg, MF: *CurMF);
118 return SpirvType;
119}
120
121SPIRVTypeInst SPIRVGlobalRegistry::assignTypeToVReg(
122 const Type *Type, Register VReg, MachineIRBuilder &MIRBuilder,
123 SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR) {
124 SPIRVTypeInst SpirvType =
125 getOrCreateSPIRVType(Type, MIRBuilder, AQ: AccessQual, EmitIR);
126 assignSPIRVTypeToVReg(Type: SpirvType, VReg, MF: MIRBuilder.getMF());
127 return SpirvType;
128}
129
130void SPIRVGlobalRegistry::assignSPIRVTypeToVReg(SPIRVTypeInst SpirvType,
131 Register VReg,
132 const MachineFunction &MF) {
133 VRegToTypeMap[&MF][VReg] = SpirvType;
134}
135
136static Register createTypeVReg(MachineRegisterInfo &MRI) {
137 auto Res = MRI.createGenericVirtualRegister(Ty: LLT::scalar(SizeInBits: 64));
138 MRI.setRegClass(Reg: Res, RC: &SPIRV::TYPERegClass);
139 return Res;
140}
141
142inline Register createTypeVReg(MachineIRBuilder &MIRBuilder) {
143 return createTypeVReg(MRI&: MIRBuilder.getMF().getRegInfo());
144}
145
146SPIRVTypeInst SPIRVGlobalRegistry::getOpTypeBool(MachineIRBuilder &MIRBuilder) {
147 return createConstOrTypeAtFunctionEntry(
148 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
149 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeBool)
150 .addDef(RegNo: createTypeVReg(MIRBuilder));
151 });
152}
153
154unsigned SPIRVGlobalRegistry::adjustOpTypeIntWidth(unsigned Width) const {
155 const SPIRVSubtarget &ST = cast<SPIRVSubtarget>(Val: CurMF->getSubtarget());
156 if (ST.canUseExtension(
157 E: SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers) ||
158 (Width == 4 && ST.canUseExtension(E: SPIRV::Extension::SPV_INTEL_int4)))
159 return Width;
160 if (Width <= 8)
161 return 8;
162 else if (Width <= 16)
163 return 16;
164 else if (Width <= 32)
165 return 32;
166 else if (Width <= 64)
167 return 64;
168 else if (Width <= 128)
169 return 128;
170 reportFatalUsageError(reason: "Unsupported Integer width!");
171}
172
173SPIRVTypeInst SPIRVGlobalRegistry::getOpTypeInt(unsigned Width,
174 MachineIRBuilder &MIRBuilder,
175 bool IsSigned) {
176 Width = adjustOpTypeIntWidth(Width);
177 const SPIRVSubtarget &ST =
178 cast<SPIRVSubtarget>(Val: MIRBuilder.getMF().getSubtarget());
179 return createConstOrTypeAtFunctionEntry(MIRBuilder, Op: [&](MachineIRBuilder
180 &MIRBuilder) {
181 if (Width == 4 && ST.canUseExtension(E: SPIRV::Extension::SPV_INTEL_int4)) {
182 MIRBuilder.buildInstr(Opcode: SPIRV::OpExtension)
183 .addImm(Val: SPIRV::Extension::SPV_INTEL_int4);
184 MIRBuilder.buildInstr(Opcode: SPIRV::OpCapability)
185 .addImm(Val: SPIRV::Capability::Int4TypeINTEL);
186 } else if ((!isPowerOf2_32(Value: Width) || Width < 8) &&
187 ST.canUseExtension(
188 E: SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers)) {
189 MIRBuilder.buildInstr(Opcode: SPIRV::OpExtension)
190 .addImm(Val: SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers);
191 MIRBuilder.buildInstr(Opcode: SPIRV::OpCapability)
192 .addImm(Val: SPIRV::Capability::ArbitraryPrecisionIntegersALTERA);
193 }
194 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeInt)
195 .addDef(RegNo: createTypeVReg(MIRBuilder))
196 .addImm(Val: Width)
197 .addImm(Val: IsSigned ? 1 : 0);
198 });
199}
200
201SPIRVTypeInst
202SPIRVGlobalRegistry::getOpTypeFloat(uint32_t Width,
203 MachineIRBuilder &MIRBuilder) {
204 return createConstOrTypeAtFunctionEntry(MIRBuilder, Op: [&](MachineIRBuilder
205 &MIRBuilder) {
206 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeFloat)
207 .addDef(RegNo: createTypeVReg(MIRBuilder))
208 .addImm(Val: Width);
209 });
210}
211
212SPIRVTypeInst
213SPIRVGlobalRegistry::getOpTypeFloat(uint32_t Width,
214 MachineIRBuilder &MIRBuilder,
215 SPIRV::FPEncoding::FPEncoding FPEncode) {
216 return createConstOrTypeAtFunctionEntry(MIRBuilder, Op: [&](MachineIRBuilder
217 &MIRBuilder) {
218 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeFloat)
219 .addDef(RegNo: createTypeVReg(MIRBuilder))
220 .addImm(Val: Width)
221 .addImm(Val: FPEncode);
222 });
223}
224
225SPIRVTypeInst SPIRVGlobalRegistry::getOpTypeVoid(MachineIRBuilder &MIRBuilder) {
226 return createConstOrTypeAtFunctionEntry(
227 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
228 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeVoid)
229 .addDef(RegNo: createTypeVReg(MIRBuilder));
230 });
231}
232
233void SPIRVGlobalRegistry::invalidateMachineInstr(MachineInstr *MI) {
234 // Other maps that may hold MachineInstr*:
235 // - VRegToTypeMap: We cannot remove the definitions of `MI` from
236 // VRegToTypeMap because some calls to invalidateMachineInstr are replacing MI
237 // with another instruction defining the same register. We expect that if MI
238 // is a type instruction, and it is still referenced in VRegToTypeMap, then
239 // those registers are dead or the VRegToTypeMap is out-of-date. We do not
240 // expect passes to ask for the SPIR-V type of a dead register. If the
241 // VRegToTypeMap is out-of-date already, then there was an error before. We
242 // cannot add an assert to verify this because the VRegToTypeMap can be
243 // out-of-date.
244 // - FunctionToInstr & FunctionToInstrRev: At this point, we should not be
245 // deleting functions. No need to update.
246 // - AliasInstMDMap: Would require a linear search, and the Intel Alias
247 // instruction are not instructions instruction selection will be able to
248 // remove.
249
250 const SPIRVSubtarget &ST = MI->getMF()->getSubtarget<SPIRVSubtarget>();
251 [[maybe_unused]] const SPIRVInstrInfo *TII = ST.getInstrInfo();
252 assert(!TII->isAliasingInstr(*MI) &&
253 "Cannot invalidate aliasing instructions.");
254 assert(MI->getOpcode() != SPIRV::OpFunction &&
255 "Cannot invalidate OpFunction.");
256
257 if (MI->getOpcode() == SPIRV::OpFunctionCall) {
258 if (const auto *F = dyn_cast<Function>(Val: MI->getOperand(i: 2).getGlobal())) {
259 auto It = ForwardCalls.find(Val: F);
260 if (It != ForwardCalls.end()) {
261 It->second.erase(Ptr: MI);
262 if (It->second.empty())
263 ForwardCalls.erase(I: It);
264 }
265 }
266 }
267
268 const MachineFunction *MF = MI->getMF();
269 auto It = LastInsertedTypeMap.find(Val: MF);
270 if (It != LastInsertedTypeMap.end() && It->second == MI)
271 LastInsertedTypeMap.erase(Val: MF);
272 // remove from the duplicate tracker to avoid incorrect reuse
273 erase(MI);
274}
275
276const MachineInstr *SPIRVGlobalRegistry::createConstOrTypeAtFunctionEntry(
277 MachineIRBuilder &MIRBuilder,
278 std::function<MachineInstr *(MachineIRBuilder &)> Op) {
279 auto oldInsertPoint = MIRBuilder.getInsertPt();
280 MachineBasicBlock *OldMBB = &MIRBuilder.getMBB();
281 MachineBasicBlock *NewMBB = &*MIRBuilder.getMF().begin();
282
283 auto LastInsertedType = LastInsertedTypeMap.find(Val: CurMF);
284 if (LastInsertedType != LastInsertedTypeMap.end()) {
285 auto It = LastInsertedType->second->getIterator();
286 // It might happen that this instruction was removed from the first MBB,
287 // hence the Parent's check.
288 MachineBasicBlock::iterator InsertAt;
289 if (It->getParent() != NewMBB)
290 InsertAt = oldInsertPoint->getParent() == NewMBB
291 ? oldInsertPoint
292 : getInsertPtValidEnd(MBB: NewMBB);
293 else if (It->getNextNode())
294 InsertAt = It->getNextNode()->getIterator();
295 else
296 InsertAt = getInsertPtValidEnd(MBB: NewMBB);
297 MIRBuilder.setInsertPt(MBB&: *NewMBB, II: InsertAt);
298 } else {
299 MIRBuilder.setInsertPt(MBB&: *NewMBB, II: NewMBB->begin());
300 auto Result = LastInsertedTypeMap.try_emplace(Key: CurMF, Args: nullptr);
301 assert(Result.second);
302 LastInsertedType = Result.first;
303 }
304
305 MachineInstr *ConstOrType = Op(MIRBuilder);
306 // We expect all users of this function to insert definitions at the insertion
307 // point set above that is always the first MBB.
308 assert(ConstOrType->getParent() == NewMBB);
309 LastInsertedType->second = ConstOrType;
310 // Advance past any continued instructions so that the next type/constant
311 // is inserted after the full group, preserving required adjacency.
312 while (auto *Next = LastInsertedType->second->getNextNode()) {
313 unsigned Opc = Next->getOpcode();
314 if (Opc == SPIRV::OpTypeStructContinuedINTEL ||
315 Opc == SPIRV::OpConstantCompositeContinuedINTEL ||
316 Opc == SPIRV::OpSpecConstantCompositeContinuedINTEL ||
317 Opc == SPIRV::OpCompositeConstructContinuedINTEL)
318 LastInsertedType->second = Next;
319 else
320 break;
321 }
322
323 MIRBuilder.setInsertPt(MBB&: *OldMBB, II: oldInsertPoint);
324 return ConstOrType;
325}
326
327SPIRVTypeInst
328SPIRVGlobalRegistry::getOpTypeVector(uint32_t NumElems, SPIRVTypeInst ElemType,
329 MachineIRBuilder &MIRBuilder) {
330 auto EleOpc = ElemType->getOpcode();
331 assert(NumElems >= 2 && "SPIR-V OpTypeVector requires at least 2 components");
332
333 if (EleOpc == SPIRV::OpTypePointer) {
334 if (!cast<SPIRVSubtarget>(Val: MIRBuilder.getMF().getSubtarget())
335 .canUseExtension(
336 E: SPIRV::Extension::SPV_INTEL_masked_gather_scatter)) {
337 const Function &F = MIRBuilder.getMF().getFunction();
338 F.getContext().diagnose(DI: DiagnosticInfoUnsupported(
339 F,
340 "Vector of pointers requires SPV_INTEL_masked_gather_scatter "
341 "extension",
342 DebugLoc(), DS_Error));
343 }
344 } else {
345 assert((EleOpc == SPIRV::OpTypeInt || EleOpc == SPIRV::OpTypeFloat ||
346 EleOpc == SPIRV::OpTypeBool) &&
347 "Invalid vector element type");
348 }
349
350 return createConstOrTypeAtFunctionEntry(
351 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
352 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeVector)
353 .addDef(RegNo: createTypeVReg(MIRBuilder))
354 .addUse(RegNo: getSPIRVTypeID(SpirvType: ElemType))
355 .addImm(Val: NumElems);
356 });
357}
358
359Register SPIRVGlobalRegistry::getOrCreateConstFP(APFloat Val, MachineInstr &I,
360 SPIRVTypeInst SpvType,
361 const SPIRVInstrInfo &TII,
362 bool ZeroAsNull) {
363 LLVMContext &Ctx = CurMF->getFunction().getContext();
364 auto *const CF = ConstantFP::get(Context&: Ctx, V: Val);
365 const MachineInstr *MI = findMI(Obj: CF, MF: CurMF);
366 if (MI && (MI->getOpcode() == SPIRV::OpConstantNull ||
367 MI->getOpcode() == SPIRV::OpConstantF))
368 return MI->getOperand(i: 0).getReg();
369 return createConstFP(CF, I, SpvType, TII, ZeroAsNull);
370}
371
372Register SPIRVGlobalRegistry::createConstFP(const ConstantFP *CF,
373 MachineInstr &I,
374 SPIRVTypeInst SpvType,
375 const SPIRVInstrInfo &TII,
376 bool ZeroAsNull) {
377 unsigned BitWidth = getScalarOrVectorBitWidth(Type: SpvType);
378 LLT LLTy = LLT::scalar(SizeInBits: BitWidth);
379 Register Res = CurMF->getRegInfo().createGenericVirtualRegister(Ty: LLTy);
380 CurMF->getRegInfo().setRegClass(Reg: Res, RC: &SPIRV::fIDRegClass);
381 assignSPIRVTypeToVReg(SpirvType: SpvType, VReg: Res, MF: *CurMF);
382
383 MachineInstr *DepMI =
384 const_cast<MachineInstr *>(static_cast<const MachineInstr *>(SpvType));
385 MachineIRBuilder MIRBuilder(*DepMI->getParent(), DepMI->getIterator());
386 const MachineInstr *Const = createConstOrTypeAtFunctionEntry(
387 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
388 MachineInstrBuilder MIB;
389 // In OpenCL OpConstantNull - Scalar floating point: +0.0 (all bits 0)
390 if (CF->getValue().isPosZero() && ZeroAsNull) {
391 MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantNull)
392 .addDef(RegNo: Res)
393 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
394 } else {
395 MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantF)
396 .addDef(RegNo: Res)
397 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
398 addNumImm(Imm: APInt(BitWidth,
399 CF->getValueAPF().bitcastToAPInt().getZExtValue()),
400 MIB);
401 }
402 const auto &ST = CurMF->getSubtarget();
403 constrainSelectedInstRegOperands(I&: *MIB, TII: *ST.getInstrInfo(),
404 TRI: *ST.getRegisterInfo(),
405 RBI: *ST.getRegBankInfo());
406 return MIB;
407 });
408 add(V: CF, MI: Const);
409 return Res;
410}
411
412Register SPIRVGlobalRegistry::getOrCreateConstInt(uint64_t Val, MachineInstr &I,
413 SPIRVTypeInst SpvType,
414 const SPIRVInstrInfo &TII,
415 bool ZeroAsNull) {
416 return getOrCreateConstInt(Val: APInt(getScalarOrVectorBitWidth(Type: SpvType), Val), I,
417 SpvType, TII, ZeroAsNull);
418}
419
420Register SPIRVGlobalRegistry::getOrCreateConstInt(const APInt &Val,
421 MachineInstr &I,
422 SPIRVTypeInst SpvType,
423 const SPIRVInstrInfo &TII,
424 bool ZeroAsNull) {
425 auto *const CI = ConstantInt::get(
426 Context&: cast<IntegerType>(Val: getTypeForSPIRVType(Ty: SpvType))->getContext(), V: Val);
427 const MachineInstr *MI = findMI(Obj: CI, MF: CurMF);
428 if (MI && (MI->getOpcode() == SPIRV::OpConstantNull ||
429 MI->getOpcode() == SPIRV::OpConstantI))
430 return MI->getOperand(i: 0).getReg();
431 return createConstInt(CI, I, SpvType, TII, ZeroAsNull);
432}
433
434Register SPIRVGlobalRegistry::createConstInt(const ConstantInt *CI,
435 MachineInstr &I,
436 SPIRVTypeInst SpvType,
437 const SPIRVInstrInfo &TII,
438 bool ZeroAsNull) {
439 unsigned BitWidth = getScalarOrVectorBitWidth(Type: SpvType);
440 LLT LLTy = LLT::scalar(SizeInBits: BitWidth);
441 Register Res = CurMF->getRegInfo().createGenericVirtualRegister(Ty: LLTy);
442 CurMF->getRegInfo().setRegClass(Reg: Res, RC: &SPIRV::iIDRegClass);
443 assignIntTypeToVReg(BitWidth, VReg: Res, I, TII);
444
445 MachineInstr *DepMI =
446 const_cast<MachineInstr *>(static_cast<const MachineInstr *>(SpvType));
447 MachineIRBuilder MIRBuilder(*DepMI->getParent(), DepMI->getIterator());
448 const MachineInstr *Const = createConstOrTypeAtFunctionEntry(
449 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
450 MachineInstrBuilder MIB;
451 if (BitWidth == 1) {
452 MIB = MIRBuilder
453 .buildInstr(Opcode: CI->isZero() ? SPIRV::OpConstantFalse
454 : SPIRV::OpConstantTrue)
455 .addDef(RegNo: Res)
456 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
457 } else if (!CI->isZero() || !ZeroAsNull) {
458 MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantI)
459 .addDef(RegNo: Res)
460 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
461 addNumImm(Imm: CI->getValue(), MIB);
462 } else {
463 MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantNull)
464 .addDef(RegNo: Res)
465 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
466 }
467 const auto &ST = CurMF->getSubtarget();
468 constrainSelectedInstRegOperands(I&: *MIB, TII: *ST.getInstrInfo(),
469 TRI: *ST.getRegisterInfo(),
470 RBI: *ST.getRegBankInfo());
471 return MIB;
472 });
473 add(V: CI, MI: Const);
474 return Res;
475}
476
477Register SPIRVGlobalRegistry::buildConstantInt(uint64_t Val,
478 MachineIRBuilder &MIRBuilder,
479 SPIRVTypeInst SpvType,
480 bool EmitIR, bool ZeroAsNull) {
481 assert(SpvType);
482 auto &MF = MIRBuilder.getMF();
483 const IntegerType *Ty = cast<IntegerType>(Val: getTypeForSPIRVType(Ty: SpvType));
484 // TODO: Avoid implicit trunc?
485 // See https://github.com/llvm/llvm-project/issues/112510.
486 auto *const CI = ConstantInt::get(Ty: const_cast<IntegerType *>(Ty), V: Val,
487 /*IsSigned=*/false, /*ImplicitTrunc=*/true);
488 Register Res = find(V: CI, MF: &MF);
489 if (Res.isValid())
490 return Res;
491
492 unsigned BitWidth = getScalarOrVectorBitWidth(Type: SpvType);
493 LLT LLTy = LLT::scalar(SizeInBits: BitWidth);
494 MachineRegisterInfo &MRI = MF.getRegInfo();
495 Res = MRI.createGenericVirtualRegister(Ty: LLTy);
496 MRI.setRegClass(Reg: Res, RC: &SPIRV::iIDRegClass);
497 assignTypeToVReg(Type: Ty, VReg: Res, MIRBuilder, AccessQual: SPIRV::AccessQualifier::ReadWrite,
498 EmitIR);
499
500 const MachineInstr *Const = createConstOrTypeAtFunctionEntry(
501 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
502 if (EmitIR)
503 return MIRBuilder.buildConstant(Res, Val: *CI);
504 Register SpvTypeReg = getSPIRVTypeID(SpirvType: SpvType);
505 MachineInstrBuilder MIB;
506 if (Val || !ZeroAsNull) {
507 MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantI)
508 .addDef(RegNo: Res)
509 .addUse(RegNo: SpvTypeReg);
510 addNumImm(Imm: APInt(BitWidth, Val), MIB);
511 } else {
512 MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantNull)
513 .addDef(RegNo: Res)
514 .addUse(RegNo: SpvTypeReg);
515 }
516 const auto &Subtarget = CurMF->getSubtarget();
517 constrainSelectedInstRegOperands(I&: *MIB, TII: *Subtarget.getInstrInfo(),
518 TRI: *Subtarget.getRegisterInfo(),
519 RBI: *Subtarget.getRegBankInfo());
520 return MIB;
521 });
522 add(V: CI, MI: Const);
523 return Res;
524}
525
526Register SPIRVGlobalRegistry::buildConstantFP(APFloat Val,
527 MachineIRBuilder &MIRBuilder,
528 SPIRVTypeInst SpvType) {
529 auto &MF = MIRBuilder.getMF();
530 LLVMContext &Ctx = MF.getFunction().getContext();
531 if (!SpvType)
532 SpvType = getOrCreateSPIRVType(Type: Type::getFloatTy(C&: Ctx), MIRBuilder,
533 AQ: SPIRV::AccessQualifier::ReadWrite, EmitIR: true);
534 auto *const CF = ConstantFP::get(Context&: Ctx, V: Val);
535 Register Res = find(V: CF, MF: &MF);
536 if (Res.isValid())
537 return Res;
538
539 LLT LLTy = LLT::scalar(SizeInBits: getScalarOrVectorBitWidth(Type: SpvType));
540 Res = MF.getRegInfo().createGenericVirtualRegister(Ty: LLTy);
541 MF.getRegInfo().setRegClass(Reg: Res, RC: &SPIRV::fIDRegClass);
542 assignSPIRVTypeToVReg(SpirvType: SpvType, VReg: Res, MF);
543
544 const MachineInstr *Const = createConstOrTypeAtFunctionEntry(
545 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
546 MachineInstrBuilder MIB;
547 MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantF)
548 .addDef(RegNo: Res)
549 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
550 addNumImm(Imm: CF->getValueAPF().bitcastToAPInt(), MIB);
551 return MIB;
552 });
553 add(V: CF, MI: Const);
554 return Res;
555}
556
557Register SPIRVGlobalRegistry::getOrCreateBaseRegister(
558 Constant *Val, MachineInstr &I, SPIRVTypeInst SpvType,
559 const SPIRVInstrInfo &TII, unsigned BitWidth, bool ZeroAsNull) {
560 SPIRVTypeInst Type = SpvType;
561 if (SpvType->getOpcode() == SPIRV::OpTypeVector ||
562 SpvType->getOpcode() == SPIRV::OpTypeArray) {
563 auto EleTypeReg = SpvType->getOperand(i: 1).getReg();
564 Type = getSPIRVTypeForVReg(VReg: EleTypeReg);
565 }
566 if (Type->getOpcode() == SPIRV::OpTypeFloat) {
567 SPIRVTypeInst SpvBaseType = getOrCreateSPIRVFloatType(BitWidth, I, TII);
568 return getOrCreateConstFP(Val: cast<ConstantFP>(Val)->getValue(), I, SpvType: SpvBaseType,
569 TII, ZeroAsNull);
570 }
571 assert(Type->getOpcode() == SPIRV::OpTypeInt);
572 SPIRVTypeInst SpvBaseType = getOrCreateSPIRVIntegerType(BitWidth, I, TII);
573 return getOrCreateConstInt(Val: Val->getUniqueInteger(), I, SpvType: SpvBaseType, TII,
574 ZeroAsNull);
575}
576
577Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(
578 Constant *Val, MachineInstr &I, SPIRVTypeInst SpvType,
579 const SPIRVInstrInfo &TII, Constant *CA, unsigned BitWidth,
580 unsigned ElemCnt, bool ZeroAsNull) {
581 if (Register R = find(V: CA, MF: CurMF); R.isValid())
582 return R;
583
584 bool IsNull = Val->isNullValue() && ZeroAsNull;
585 Register ElemReg;
586 if (!IsNull)
587 ElemReg =
588 getOrCreateBaseRegister(Val, I, SpvType, TII, BitWidth, ZeroAsNull);
589
590 LLT LLTy = LLT::scalar(SizeInBits: 64);
591 Register Res = CurMF->getRegInfo().createGenericVirtualRegister(Ty: LLTy);
592 CurMF->getRegInfo().setRegClass(Reg: Res, RC: getRegClass(SpvType));
593 assignSPIRVTypeToVReg(SpirvType: SpvType, VReg: Res, MF: *CurMF);
594
595 MachineInstr *DepMI =
596 const_cast<MachineInstr *>(static_cast<const MachineInstr *>(SpvType));
597 MachineIRBuilder MIRBuilder(*DepMI->getParent(), DepMI->getIterator());
598 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
599 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
600 MachineInstrBuilder MIB;
601 if (!IsNull) {
602 MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantComposite)
603 .addDef(RegNo: Res)
604 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
605 for (unsigned i = 0; i < ElemCnt; ++i)
606 MIB.addUse(RegNo: ElemReg);
607 } else {
608 MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantNull)
609 .addDef(RegNo: Res)
610 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
611 }
612 const auto &Subtarget = CurMF->getSubtarget();
613 constrainSelectedInstRegOperands(I&: *MIB, TII: *Subtarget.getInstrInfo(),
614 TRI: *Subtarget.getRegisterInfo(),
615 RBI: *Subtarget.getRegBankInfo());
616 return MIB;
617 });
618 add(V: CA, MI: NewMI);
619 return Res;
620}
621
622Register SPIRVGlobalRegistry::getOrCreateConstVector(uint64_t Val,
623 MachineInstr &I,
624 SPIRVTypeInst SpvType,
625 const SPIRVInstrInfo &TII,
626 bool ZeroAsNull) {
627 return getOrCreateConstVector(Val: APInt(getScalarOrVectorBitWidth(Type: SpvType), Val),
628 I, SpvType, TII, ZeroAsNull);
629}
630
631Register SPIRVGlobalRegistry::getOrCreateConstVector(const APInt &Val,
632 MachineInstr &I,
633 SPIRVTypeInst SpvType,
634 const SPIRVInstrInfo &TII,
635 bool ZeroAsNull) {
636 const Type *LLVMTy = getTypeForSPIRVType(Ty: SpvType);
637 assert(LLVMTy->isVectorTy() &&
638 "Expected vector type for constant vector creation");
639 const FixedVectorType *LLVMVecTy = cast<FixedVectorType>(Val: LLVMTy);
640 Type *LLVMBaseTy = LLVMVecTy->getElementType();
641 assert(LLVMBaseTy->isIntegerTy() &&
642 "Expected integer element type for APInt constant vector");
643 auto *ConstVal = cast<ConstantInt>(Val: ConstantInt::get(Ty: LLVMBaseTy, V: Val));
644 auto *ConstVec =
645 ConstantVector::getSplat(EC: LLVMVecTy->getElementCount(), Elt: ConstVal);
646 unsigned BW = getScalarOrVectorBitWidth(Type: SpvType);
647 return getOrCreateCompositeOrNull(Val: ConstVal, I, SpvType, TII, CA: ConstVec, BitWidth: BW,
648 ElemCnt: getScalarOrVectorComponentCount(Type: SpvType),
649 ZeroAsNull);
650}
651
652Register SPIRVGlobalRegistry::getOrCreateConstVector(APFloat Val,
653 MachineInstr &I,
654 SPIRVTypeInst SpvType,
655 const SPIRVInstrInfo &TII,
656 bool ZeroAsNull) {
657 const Type *LLVMTy = getTypeForSPIRVType(Ty: SpvType);
658 assert(LLVMTy->isVectorTy());
659 const FixedVectorType *LLVMVecTy = cast<FixedVectorType>(Val: LLVMTy);
660 Type *LLVMBaseTy = LLVMVecTy->getElementType();
661 assert(LLVMBaseTy->isFloatingPointTy());
662 auto *ConstVal = ConstantFP::get(Ty: LLVMBaseTy, V: Val);
663 auto *ConstVec =
664 ConstantVector::getSplat(EC: LLVMVecTy->getElementCount(), Elt: ConstVal);
665 unsigned BW = getScalarOrVectorBitWidth(Type: SpvType);
666 return getOrCreateCompositeOrNull(Val: ConstVal, I, SpvType, TII, CA: ConstVec, BitWidth: BW,
667 ElemCnt: getScalarOrVectorComponentCount(Type: SpvType),
668 ZeroAsNull);
669}
670
671Register SPIRVGlobalRegistry::getOrCreateConstIntArray(
672 uint64_t Val, size_t Num, MachineInstr &I, SPIRVTypeInst SpvType,
673 const SPIRVInstrInfo &TII) {
674 const Type *LLVMTy = getTypeForSPIRVType(Ty: SpvType);
675 assert(LLVMTy->isArrayTy());
676 const ArrayType *LLVMArrTy = cast<ArrayType>(Val: LLVMTy);
677 Type *LLVMBaseTy = LLVMArrTy->getElementType();
678 Constant *CI = ConstantInt::get(Ty: LLVMBaseTy, V: Val);
679 SPIRVTypeInst SpvBaseTy =
680 getSPIRVTypeForVReg(VReg: SpvType->getOperand(i: 1).getReg());
681 unsigned BW = getScalarOrVectorBitWidth(Type: SpvBaseTy);
682 // The following is reasonably unique key that is better that [Val]. The naive
683 // alternative would be something along the lines of:
684 // SmallVector<Constant *> NumCI(Num, CI);
685 // Constant *UniqueKey =
686 // ConstantArray::get(const_cast<ArrayType*>(LLVMArrTy), NumCI);
687 // that would be a truly unique but dangerous key, because it could lead to
688 // the creation of constants of arbitrary length (that is, the parameter of
689 // memset) which were missing in the original module.
690 Type *I64Ty = Type::getInt64Ty(C&: LLVMBaseTy->getContext());
691 Constant *UniqueKey = ConstantStruct::getAnon(
692 V: {PoisonValue::get(T: const_cast<ArrayType *>(LLVMArrTy)),
693 ConstantInt::get(Ty: LLVMBaseTy, V: Val), ConstantInt::get(Ty: I64Ty, V: Num)});
694 return getOrCreateCompositeOrNull(Val: CI, I, SpvType, TII, CA: UniqueKey, BitWidth: BW,
695 ElemCnt: LLVMArrTy->getNumElements());
696}
697
698Register SPIRVGlobalRegistry::getOrCreateIntCompositeOrNull(
699 uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVTypeInst SpvType,
700 bool EmitIR, Constant *CA, unsigned BitWidth, unsigned ElemCnt) {
701 if (Register R = find(V: CA, MF: CurMF); R.isValid())
702 return R;
703
704 Register ElemReg;
705 if (Val || EmitIR) {
706 SPIRVTypeInst SpvBaseType =
707 getOrCreateSPIRVIntegerType(BitWidth, MIRBuilder);
708 ElemReg = buildConstantInt(Val, MIRBuilder, SpvType: SpvBaseType, EmitIR);
709 }
710 LLT LLTy = EmitIR ? LLT::fixed_vector(NumElements: ElemCnt, ScalarSizeInBits: BitWidth) : LLT::scalar(SizeInBits: 64);
711 Register Res = CurMF->getRegInfo().createGenericVirtualRegister(Ty: LLTy);
712 CurMF->getRegInfo().setRegClass(Reg: Res, RC: &SPIRV::iIDRegClass);
713 assignSPIRVTypeToVReg(SpirvType: SpvType, VReg: Res, MF: *CurMF);
714
715 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
716 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
717 if (EmitIR)
718 return MIRBuilder.buildSplatBuildVector(Res, Src: ElemReg);
719
720 if (Val) {
721 auto MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantComposite)
722 .addDef(RegNo: Res)
723 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
724 for (unsigned i = 0; i < ElemCnt; ++i)
725 MIB.addUse(RegNo: ElemReg);
726 return MIB;
727 }
728
729 return MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantNull)
730 .addDef(RegNo: Res)
731 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
732 });
733 add(V: CA, MI: NewMI);
734 return Res;
735}
736
737Register SPIRVGlobalRegistry::getOrCreateConsIntVector(
738 uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVTypeInst SpvType,
739 bool EmitIR) {
740 const Type *LLVMTy = getTypeForSPIRVType(Ty: SpvType);
741 assert(LLVMTy->isVectorTy());
742 const FixedVectorType *LLVMVecTy = cast<FixedVectorType>(Val: LLVMTy);
743 Type *LLVMBaseTy = LLVMVecTy->getElementType();
744 const auto ConstInt = ConstantInt::get(Ty: LLVMBaseTy, V: Val);
745 auto ConstVec =
746 ConstantVector::getSplat(EC: LLVMVecTy->getElementCount(), Elt: ConstInt);
747 unsigned BW = getScalarOrVectorBitWidth(Type: SpvType);
748 return getOrCreateIntCompositeOrNull(
749 Val, MIRBuilder, SpvType, EmitIR, CA: ConstVec, BitWidth: BW,
750 ElemCnt: getScalarOrVectorComponentCount(Type: SpvType));
751}
752
753Register
754SPIRVGlobalRegistry::getOrCreateConstNullPtr(MachineIRBuilder &MIRBuilder,
755 SPIRVTypeInst SpvType) {
756 const Type *Ty = getTypeForSPIRVType(Ty: SpvType);
757 unsigned AddressSpace = typeToAddressSpace(Ty);
758 Type *ElemTy = ::getPointeeType(Ty);
759 assert(ElemTy);
760 const Constant *CP = ConstantTargetNone::get(
761 T: dyn_cast<TargetExtType>(Val: getTypedPointerWrapper(ElemTy, AS: AddressSpace)));
762 Register Res = find(V: CP, MF: CurMF);
763 if (Res.isValid())
764 return Res;
765
766 LLT LLTy = LLT::pointer(AddressSpace, SizeInBits: getPointerSize());
767 Res = CurMF->getRegInfo().createGenericVirtualRegister(Ty: LLTy);
768 CurMF->getRegInfo().setRegClass(Reg: Res, RC: &SPIRV::pIDRegClass);
769 assignSPIRVTypeToVReg(SpirvType: SpvType, VReg: Res, MF: *CurMF);
770
771 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
772 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
773 return MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantNull)
774 .addDef(RegNo: Res)
775 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
776 });
777 add(V: CP, MI: NewMI);
778 return Res;
779}
780
781Register
782SPIRVGlobalRegistry::buildConstantSampler(Register ResReg, unsigned AddrMode,
783 unsigned Param, unsigned FilerMode,
784 MachineIRBuilder &MIRBuilder) {
785 auto Sampler =
786 ResReg.isValid()
787 ? ResReg
788 : MIRBuilder.getMRI()->createVirtualRegister(RegClass: &SPIRV::iIDRegClass);
789 SPIRVTypeInst TypeSampler = getOrCreateOpTypeSampler(MIRBuilder);
790 Register TypeSamplerReg = getSPIRVTypeID(SpirvType: TypeSampler);
791 // We cannot use createOpType() logic here, because of the
792 // GlobalISel/IRTranslator.cpp check for a tail call that expects that
793 // MIRBuilder.getInsertPt() has a previous instruction. If this constant is
794 // inserted as a result of "__translate_sampler_initializer()" this would
795 // break this IRTranslator assumption.
796 MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantSampler)
797 .addDef(RegNo: Sampler)
798 .addUse(RegNo: TypeSamplerReg)
799 .addImm(Val: AddrMode)
800 .addImm(Val: Param)
801 .addImm(Val: FilerMode);
802 return Sampler;
803}
804
805Register SPIRVGlobalRegistry::buildGlobalVariable(
806 Register ResVReg, SPIRVTypeInst BaseType, StringRef Name,
807 const GlobalValue *GV, SPIRV::StorageClass::StorageClass Storage,
808 const MachineInstr *Init, bool IsConst,
809 const std::optional<SPIRV::LinkageType::LinkageType> &LinkageType,
810 MachineIRBuilder &MIRBuilder, bool IsInstSelector) {
811 const GlobalVariable *GVar = nullptr;
812 if (GV) {
813 GVar = cast<const GlobalVariable>(Val: GV);
814 } else {
815 // If GV is not passed explicitly, use the name to find or construct
816 // the global variable.
817 Module *M = MIRBuilder.getMF().getFunction().getParent();
818 GVar = M->getGlobalVariable(Name);
819 if (GVar == nullptr) {
820 const Type *Ty = getTypeForSPIRVType(Ty: BaseType); // TODO: check type.
821 if (auto *TPTy = dyn_cast<TypedPointerType>(Val: Ty))
822 Ty = PointerType::get(C&: M->getContext(), AddressSpace: TPTy->getAddressSpace());
823 // Module takes ownership of the global var.
824 GVar = new GlobalVariable(*M, const_cast<Type *>(Ty), false,
825 GlobalValue::ExternalLinkage, nullptr,
826 Twine(Name));
827 }
828 GV = GVar;
829 }
830
831 const MachineFunction *MF = &MIRBuilder.getMF();
832 Register Reg = find(V: GVar, MF);
833 if (Reg.isValid()) {
834 if (Reg != ResVReg)
835 MIRBuilder.buildCopy(Res: ResVReg, Op: Reg);
836 return ResVReg;
837 }
838
839 // Emit the OpVariable into the entry block to ensure the def dominates
840 // all uses across all MBBs.
841 MachineBasicBlock &EntryBB = MIRBuilder.getMF().front();
842 MachineIRBuilder GVBuilder(MIRBuilder.getState());
843 if (&GVBuilder.getMBB() != &EntryBB)
844 GVBuilder.setInsertPt(MBB&: EntryBB, II: EntryBB.getFirstTerminator());
845
846 auto MIB = GVBuilder.buildInstr(Opcode: SPIRV::OpVariable)
847 .addDef(RegNo: ResVReg)
848 .addUse(RegNo: getSPIRVTypeID(SpirvType: BaseType))
849 .addImm(Val: static_cast<uint32_t>(Storage));
850 if (Init)
851 MIB.addUse(RegNo: Init->getOperand(i: 0).getReg());
852 // ISel may introduce a new register on this step, so we need to add it to
853 // DT and correct its type avoiding fails on the next stage.
854 if (IsInstSelector) {
855 const auto &Subtarget = CurMF->getSubtarget();
856 constrainSelectedInstRegOperands(I&: *MIB, TII: *Subtarget.getInstrInfo(),
857 TRI: *Subtarget.getRegisterInfo(),
858 RBI: *Subtarget.getRegBankInfo());
859 }
860 add(V: GVar, MI: MIB);
861
862 Reg = MIB->getOperand(i: 0).getReg();
863 addGlobalObject(V: GVar, MF, R: Reg);
864
865 // Set to Reg the same type as ResVReg has.
866 auto MRI = MIRBuilder.getMRI();
867 if (Reg != ResVReg) {
868 LLT RegLLTy =
869 LLT::pointer(AddressSpace: MRI->getType(Reg: ResVReg).getAddressSpace(), SizeInBits: getPointerSize());
870 MRI->setType(VReg: Reg, Ty: RegLLTy);
871 assignSPIRVTypeToVReg(SpirvType: BaseType, VReg: Reg, MF: MIRBuilder.getMF());
872 } else {
873 // Our knowledge about the type may be updated.
874 // If that's the case, we need to update a type
875 // associated with the register.
876 SPIRVTypeInst DefType = getSPIRVTypeForVReg(VReg: ResVReg);
877 if (!DefType || DefType != SPIRVTypeInst(BaseType))
878 assignSPIRVTypeToVReg(SpirvType: BaseType, VReg: Reg, MF: MIRBuilder.getMF());
879 }
880
881 // If it's a global variable with name, output OpName for it.
882 if (GVar && GVar->hasName())
883 buildOpName(Target: Reg, Name: GVar->getName(), MIRBuilder);
884
885 // Output decorations for the GV.
886 // TODO: maybe move to GenerateDecorations pass.
887 const SPIRVSubtarget &ST =
888 cast<SPIRVSubtarget>(Val: MIRBuilder.getMF().getSubtarget());
889 if (IsConst && !ST.isShader())
890 buildOpDecorate(Reg, MIRBuilder, Dec: SPIRV::Decoration::Constant, DecArgs: {});
891
892 if (GVar && GVar->getAlign().valueOrOne().value() != 1 && !ST.isShader()) {
893 unsigned Alignment = (unsigned)GVar->getAlign().valueOrOne().value();
894 buildOpDecorate(Reg, MIRBuilder, Dec: SPIRV::Decoration::Alignment, DecArgs: {Alignment});
895 }
896
897 if (LinkageType)
898 buildOpDecorate(Reg, MIRBuilder, Dec: SPIRV::Decoration::LinkageAttributes,
899 DecArgs: {static_cast<uint32_t>(*LinkageType)}, StrImm: Name);
900
901 SPIRV::BuiltIn::BuiltIn BuiltInId;
902 if (getSpirvBuiltInIdByName(Name, BI&: BuiltInId))
903 buildOpDecorate(Reg, MIRBuilder, Dec: SPIRV::Decoration::BuiltIn,
904 DecArgs: {static_cast<uint32_t>(BuiltInId)});
905
906 // If it's a global variable with "spirv.Decorations" metadata node
907 // recognize it as a SPIR-V friendly LLVM IR and parse "spirv.Decorations"
908 // arguments.
909 MDNode *GVarMD = nullptr;
910 if (GVar && (GVarMD = GVar->getMetadata(Kind: "spirv.Decorations")) != nullptr)
911 buildOpSpirvDecorations(Reg, MIRBuilder, GVarMD, ST);
912
913 return Reg;
914}
915
916// Returns a name based on the Type. Notes that this does not look at
917// decorations, and will return the same string for two types that are the same
918// except for decorations.
919Register SPIRVGlobalRegistry::getOrCreateGlobalVariableWithBinding(
920 SPIRVTypeInst VarType, uint32_t Set, uint32_t Binding, StringRef Name,
921 MachineIRBuilder &MIRBuilder) {
922 Register VarReg =
923 MIRBuilder.getMRI()->createVirtualRegister(RegClass: &SPIRV::iIDRegClass);
924
925 buildGlobalVariable(ResVReg: VarReg, BaseType: VarType, Name, GV: nullptr,
926 Storage: getPointerStorageClass(Type: VarType), Init: nullptr, IsConst: false,
927 LinkageType: std::nullopt, MIRBuilder, IsInstSelector: false);
928
929 buildOpDecorate(Reg: VarReg, MIRBuilder, Dec: SPIRV::Decoration::DescriptorSet, DecArgs: {Set});
930 buildOpDecorate(Reg: VarReg, MIRBuilder, Dec: SPIRV::Decoration::Binding, DecArgs: {Binding});
931 return VarReg;
932}
933
934// TODO: Double check the calls to getOpTypeArray to make sure that `ElemType`
935// is explicitly laid out when required.
936SPIRVTypeInst SPIRVGlobalRegistry::getOpTypeArray(uint32_t NumElems,
937 SPIRVTypeInst ElemType,
938 MachineIRBuilder &MIRBuilder,
939 bool ExplicitLayoutRequired,
940 bool EmitIR) {
941 assert((ElemType->getOpcode() != SPIRV::OpTypeVoid) &&
942 "Invalid array element type");
943 SPIRVTypeInst SpvTypeInt32 = getOrCreateSPIRVIntegerType(BitWidth: 32, MIRBuilder);
944 SPIRVTypeInst ArrayType = nullptr;
945 const SPIRVSubtarget &ST =
946 cast<SPIRVSubtarget>(Val: MIRBuilder.getMF().getSubtarget());
947 if (NumElems != 0) {
948 Register NumElementsVReg =
949 buildConstantInt(Val: NumElems, MIRBuilder, SpvType: SpvTypeInt32, EmitIR);
950 ArrayType = createConstOrTypeAtFunctionEntry(
951 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
952 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeArray)
953 .addDef(RegNo: createTypeVReg(MIRBuilder))
954 .addUse(RegNo: getSPIRVTypeID(SpirvType: ElemType))
955 .addUse(RegNo: NumElementsVReg);
956 });
957 } else if (ST.getTargetTriple().getVendor() == Triple::VendorType::AMD) {
958 // We set the array size to the token UINT64_MAX value, which is generally
959 // illegal (the maximum legal size is 61-bits) for the foreseeable future.
960 SPIRVTypeInst SpvTypeInt64 = getOrCreateSPIRVIntegerType(BitWidth: 64, MIRBuilder);
961 Register NumElementsVReg =
962 buildConstantInt(UINT64_MAX, MIRBuilder, SpvType: SpvTypeInt64, EmitIR);
963 ArrayType = createConstOrTypeAtFunctionEntry(
964 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
965 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeArray)
966 .addDef(RegNo: createTypeVReg(MIRBuilder))
967 .addUse(RegNo: getSPIRVTypeID(SpirvType: ElemType))
968 .addUse(RegNo: NumElementsVReg);
969 });
970 } else {
971 if (!ST.isShader()) {
972 llvm::reportFatalUsageError(
973 reason: "Runtime arrays are not allowed in non-shader "
974 "SPIR-V modules");
975 return nullptr;
976 }
977 ArrayType = createConstOrTypeAtFunctionEntry(
978 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
979 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeRuntimeArray)
980 .addDef(RegNo: createTypeVReg(MIRBuilder))
981 .addUse(RegNo: getSPIRVTypeID(SpirvType: ElemType));
982 });
983 }
984
985 if (ExplicitLayoutRequired && !isResourceType(Type: ElemType)) {
986 Type *ET = const_cast<Type *>(getTypeForSPIRVType(Ty: ElemType));
987 addArrayStrideDecorations(Reg: ArrayType->defs().begin()->getReg(), ElementType: ET,
988 MIRBuilder);
989 }
990
991 return ArrayType;
992}
993
994SPIRVTypeInst
995SPIRVGlobalRegistry::getOpTypeOpaque(const StructType *Ty,
996 MachineIRBuilder &MIRBuilder) {
997 assert(Ty->hasName());
998 const StringRef Name = Ty->hasName() ? Ty->getName() : "";
999 Register ResVReg = createTypeVReg(MIRBuilder);
1000 return createConstOrTypeAtFunctionEntry(
1001 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1002 auto MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeOpaque).addDef(RegNo: ResVReg);
1003 addStringImm(Str: Name, MIB);
1004 buildOpName(Target: ResVReg, Name, MIRBuilder);
1005 return MIB;
1006 });
1007}
1008
1009SPIRVTypeInst SPIRVGlobalRegistry::getOpTypeStruct(
1010 const StructType *Ty, MachineIRBuilder &MIRBuilder,
1011 SPIRV::AccessQualifier::AccessQualifier AccQual,
1012 StructOffsetDecorator Decorator, bool EmitIR) {
1013 Type *OriginalElementType = nullptr;
1014 uint64_t TotalSize = 0;
1015 if (matchPeeledArrayPattern(Ty, OriginalElementType, TotalSize)) {
1016 SPIRVTypeInst ElementSPIRVType = findSPIRVType(
1017 Ty: OriginalElementType, MIRBuilder, accessQual: AccQual,
1018 /* ExplicitLayoutRequired= */ Decorator != nullptr, EmitIR);
1019 return getOpTypeArray(NumElems: TotalSize, ElemType: ElementSPIRVType, MIRBuilder,
1020 /*ExplicitLayoutRequired=*/Decorator != nullptr,
1021 EmitIR);
1022 }
1023
1024 const SPIRVSubtarget &ST =
1025 cast<SPIRVSubtarget>(Val: MIRBuilder.getMF().getSubtarget());
1026 SmallVector<Register, 4> FieldTypes;
1027 constexpr unsigned MaxWordCount = UINT16_MAX;
1028 const size_t NumElements = Ty->getNumElements();
1029
1030 size_t MaxNumElements = MaxWordCount - 2;
1031 size_t SPIRVStructNumElements = NumElements;
1032 if (NumElements > MaxNumElements) {
1033 // Do adjustments for continued instructions.
1034 SPIRVStructNumElements = MaxNumElements;
1035 MaxNumElements = MaxWordCount - 1;
1036 }
1037
1038 for (const auto &Elem : Ty->elements()) {
1039 SPIRVTypeInst ElemTy = findSPIRVType(
1040 Ty: toTypedPointer(Ty: Elem), MIRBuilder, accessQual: AccQual,
1041 /* ExplicitLayoutRequired= */ Decorator != nullptr, EmitIR);
1042 assert(ElemTy && ElemTy->getOpcode() != SPIRV::OpTypeVoid &&
1043 "Invalid struct element type");
1044 FieldTypes.push_back(Elt: getSPIRVTypeID(SpirvType: ElemTy));
1045 }
1046 Register ResVReg = createTypeVReg(MIRBuilder);
1047 if (Ty->hasName())
1048 buildOpName(Target: ResVReg, Name: Ty->getName(), MIRBuilder);
1049 if (Ty->isPacked() && !ST.isShader())
1050 buildOpDecorate(Reg: ResVReg, MIRBuilder, Dec: SPIRV::Decoration::CPacked, DecArgs: {});
1051
1052 SPIRVTypeInst SPVType = createConstOrTypeAtFunctionEntry(
1053 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1054 auto MIBStruct =
1055 MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeStruct).addDef(RegNo: ResVReg);
1056 for (size_t I = 0; I < SPIRVStructNumElements; ++I)
1057 MIBStruct.addUse(RegNo: FieldTypes[I]);
1058 for (size_t I = SPIRVStructNumElements; I < NumElements;
1059 I += MaxNumElements) {
1060 auto MIBCont =
1061 MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeStructContinuedINTEL);
1062 for (size_t J = I; J < std::min(a: I + MaxNumElements, b: NumElements); ++J)
1063 MIBCont.addUse(RegNo: FieldTypes[J]);
1064 }
1065 return MIBStruct;
1066 });
1067
1068 if (Decorator)
1069 Decorator(SPVType->defs().begin()->getReg());
1070
1071 return SPVType;
1072}
1073
1074SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateSpecialType(
1075 const Type *Ty, MachineIRBuilder &MIRBuilder,
1076 SPIRV::AccessQualifier::AccessQualifier AccQual) {
1077 assert(isSpecialOpaqueType(Ty) && "Not a special opaque builtin type");
1078 return SPIRV::lowerBuiltinType(Type: Ty, AccessQual: AccQual, MIRBuilder, GR: this);
1079}
1080
1081SPIRVTypeInst SPIRVGlobalRegistry::getOpTypePointer(
1082 SPIRV::StorageClass::StorageClass SC, SPIRVTypeInst ElemType,
1083 MachineIRBuilder &MIRBuilder, Register Reg) {
1084 if (!Reg.isValid())
1085 Reg = createTypeVReg(MIRBuilder);
1086
1087 return createConstOrTypeAtFunctionEntry(MIRBuilder, Op: [&](MachineIRBuilder
1088 &MIRBuilder) {
1089 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypePointer)
1090 .addDef(RegNo: Reg)
1091 .addImm(Val: static_cast<uint32_t>(SC))
1092 .addUse(RegNo: getSPIRVTypeID(SpirvType: ElemType));
1093 });
1094}
1095
1096SPIRVTypeInst SPIRVGlobalRegistry::getOpTypeForwardPointer(
1097 SPIRV::StorageClass::StorageClass SC, MachineIRBuilder &MIRBuilder) {
1098 return createConstOrTypeAtFunctionEntry(MIRBuilder, Op: [&](MachineIRBuilder
1099 &MIRBuilder) {
1100 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeForwardPointer)
1101 .addUse(RegNo: createTypeVReg(MIRBuilder))
1102 .addImm(Val: static_cast<uint32_t>(SC));
1103 });
1104}
1105
1106SPIRVTypeInst SPIRVGlobalRegistry::getOpTypeFunction(
1107 const FunctionType *Ty, SPIRVTypeInst RetType,
1108 const SmallVectorImpl<SPIRVTypeInst> &ArgTypes,
1109 MachineIRBuilder &MIRBuilder) {
1110 const SPIRVSubtarget *ST =
1111 static_cast<const SPIRVSubtarget *>(&MIRBuilder.getMF().getSubtarget());
1112 if (Ty->isVarArg() && ST->isShader()) {
1113 Function &Fn = MIRBuilder.getMF().getFunction();
1114 Ty->getContext().diagnose(DI: DiagnosticInfoUnsupported(
1115 Fn, "SPIR-V shaders do not support variadic functions",
1116 MIRBuilder.getDebugLoc()));
1117 }
1118 return createConstOrTypeAtFunctionEntry(MIRBuilder, Op: [&](MachineIRBuilder
1119 &MIRBuilder) {
1120 auto MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeFunction)
1121 .addDef(RegNo: createTypeVReg(MIRBuilder))
1122 .addUse(RegNo: getSPIRVTypeID(SpirvType: RetType));
1123 for (auto &ArgType : ArgTypes)
1124 MIB.addUse(RegNo: getSPIRVTypeID(SpirvType: ArgType));
1125 return MIB;
1126 });
1127}
1128
1129SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateOpTypeFunctionWithArgs(
1130 const Type *Ty, SPIRVTypeInst RetType,
1131 const SmallVectorImpl<SPIRVTypeInst> &ArgTypes,
1132 MachineIRBuilder &MIRBuilder) {
1133 if (const MachineInstr *MI = findMI(T: Ty, RequiresExplicitLayout: false, MF: &MIRBuilder.getMF()))
1134 return MI;
1135 const MachineInstr *NewMI =
1136 getOpTypeFunction(Ty: cast<FunctionType>(Val: Ty), RetType, ArgTypes, MIRBuilder);
1137 add(T: Ty, RequiresExplicitLayout: false, MI: NewMI);
1138 return finishCreatingSPIRVType(LLVMTy: Ty, SpirvType: NewMI);
1139}
1140
1141SPIRVTypeInst SPIRVGlobalRegistry::findSPIRVType(
1142 const Type *Ty, MachineIRBuilder &MIRBuilder,
1143 SPIRV::AccessQualifier::AccessQualifier AccQual,
1144 bool ExplicitLayoutRequired, bool EmitIR) {
1145 // Treat <1 x T> as T.
1146 if (auto *FVT = dyn_cast<FixedVectorType>(Val: Ty);
1147 FVT && FVT->getNumElements() == 1)
1148 return findSPIRVType(Ty: FVT->getElementType(), MIRBuilder, AccQual,
1149 ExplicitLayoutRequired, EmitIR);
1150 Ty = adjustIntTypeByWidth(Ty);
1151 // TODO: findMI needs to know if a layout is required.
1152 if (const MachineInstr *MI =
1153 findMI(T: Ty, RequiresExplicitLayout: ExplicitLayoutRequired, MF: &MIRBuilder.getMF()))
1154 return MI;
1155 if (auto It = ForwardPointerTypes.find(Val: Ty); It != ForwardPointerTypes.end())
1156 return It->second;
1157 return restOfCreateSPIRVType(Type: Ty, MIRBuilder, AccessQual: AccQual, ExplicitLayoutRequired,
1158 EmitIR);
1159}
1160
1161Register SPIRVGlobalRegistry::getSPIRVTypeID(SPIRVTypeInst SpirvType) const {
1162 assert(SpirvType && "Attempting to get type id for nullptr type.");
1163 if (SpirvType->getOpcode() == SPIRV::OpTypeForwardPointer ||
1164 SpirvType->getOpcode() == SPIRV::OpTypeStructContinuedINTEL)
1165 return SpirvType->uses().begin()->getReg();
1166 return SpirvType->defs().begin()->getReg();
1167}
1168
1169// We need to use a new LLVM integer type if there is a mismatch between
1170// number of bits in LLVM and SPIRV integer types to let DuplicateTracker
1171// ensure uniqueness of a SPIRV type by the corresponding LLVM type. Without
1172// such an adjustment SPIRVGlobalRegistry::getOpTypeInt() could create the
1173// same "OpTypeInt 8" type for a series of LLVM integer types with number of
1174// bits less than 8. This would lead to duplicate type definitions
1175// eventually due to the method that DuplicateTracker utilizes to reason
1176// about uniqueness of type records.
1177const Type *SPIRVGlobalRegistry::adjustIntTypeByWidth(const Type *Ty) const {
1178 if (auto IType = dyn_cast<IntegerType>(Val: Ty)) {
1179 unsigned SrcBitWidth = IType->getBitWidth();
1180 if (SrcBitWidth > 1) {
1181 unsigned BitWidth = adjustOpTypeIntWidth(Width: SrcBitWidth);
1182 // Maybe change source LLVM type to keep DuplicateTracker consistent.
1183 if (SrcBitWidth != BitWidth)
1184 Ty = IntegerType::get(C&: Ty->getContext(), NumBits: BitWidth);
1185 }
1186 }
1187 return Ty;
1188}
1189
1190SPIRVTypeInst SPIRVGlobalRegistry::createSPIRVType(
1191 const Type *Ty, MachineIRBuilder &MIRBuilder,
1192 SPIRV::AccessQualifier::AccessQualifier AccQual,
1193 bool ExplicitLayoutRequired, bool EmitIR) {
1194 if (isSpecialOpaqueType(Ty))
1195 return getOrCreateSpecialType(Ty, MIRBuilder, AccQual);
1196
1197 if (const MachineInstr *MI =
1198 findMI(T: Ty, RequiresExplicitLayout: ExplicitLayoutRequired, MF: &MIRBuilder.getMF()))
1199 return MI;
1200
1201 if (auto IType = dyn_cast<IntegerType>(Val: Ty)) {
1202 const unsigned Width = IType->getBitWidth();
1203 return Width == 1 ? getOpTypeBool(MIRBuilder)
1204 : getOpTypeInt(Width, MIRBuilder, IsSigned: false);
1205 }
1206 if (Ty->isFloatingPointTy()) {
1207 if (Ty->isBFloatTy()) {
1208 return getOpTypeFloat(Width: Ty->getPrimitiveSizeInBits(), MIRBuilder,
1209 FPEncode: SPIRV::FPEncoding::BFloat16KHR);
1210 } else {
1211 return getOpTypeFloat(Width: Ty->getPrimitiveSizeInBits(), MIRBuilder);
1212 }
1213 }
1214 if (Ty->isVoidTy())
1215 return getOpTypeVoid(MIRBuilder);
1216 if (Ty->isVectorTy()) {
1217 SPIRVTypeInst El =
1218 findSPIRVType(Ty: cast<FixedVectorType>(Val: Ty)->getElementType(), MIRBuilder,
1219 AccQual, ExplicitLayoutRequired, EmitIR);
1220 return getOpTypeVector(NumElems: cast<FixedVectorType>(Val: Ty)->getNumElements(), ElemType: El,
1221 MIRBuilder);
1222 }
1223 if (Ty->isArrayTy()) {
1224 SPIRVTypeInst El = findSPIRVType(Ty: Ty->getArrayElementType(), MIRBuilder,
1225 AccQual, ExplicitLayoutRequired, EmitIR);
1226 return getOpTypeArray(NumElems: Ty->getArrayNumElements(), ElemType: El, MIRBuilder,
1227 ExplicitLayoutRequired, EmitIR);
1228 }
1229 if (auto SType = dyn_cast<StructType>(Val: Ty)) {
1230 if (SType->isOpaque())
1231 return getOpTypeOpaque(Ty: SType, MIRBuilder);
1232
1233 StructOffsetDecorator Decorator = nullptr;
1234 if (ExplicitLayoutRequired) {
1235 Decorator = [&MIRBuilder, SType, this](Register Reg) {
1236 addStructOffsetDecorations(Reg, Ty: const_cast<StructType *>(SType),
1237 MIRBuilder);
1238 };
1239 }
1240 return getOpTypeStruct(Ty: SType, MIRBuilder, AccQual, Decorator: std::move(Decorator),
1241 EmitIR);
1242 }
1243 if (auto FType = dyn_cast<FunctionType>(Val: Ty)) {
1244 SPIRVTypeInst RetTy =
1245 findSPIRVType(Ty: FType->getReturnType(), MIRBuilder, AccQual,
1246 ExplicitLayoutRequired, EmitIR);
1247 SmallVector<SPIRVTypeInst, 4> ParamTypes;
1248 for (const auto &ParamTy : FType->params())
1249 ParamTypes.push_back(Elt: findSPIRVType(Ty: ParamTy, MIRBuilder, AccQual,
1250 ExplicitLayoutRequired, EmitIR));
1251 return getOpTypeFunction(Ty: FType, RetType: RetTy, ArgTypes: ParamTypes, MIRBuilder);
1252 }
1253
1254 unsigned AddrSpace = typeToAddressSpace(Ty);
1255
1256 // Get access to information about available extensions
1257 const SPIRVSubtarget *ST =
1258 static_cast<const SPIRVSubtarget *>(&MIRBuilder.getMF().getSubtarget());
1259 auto SC = addressSpaceToStorageClass(AddrSpace, STI: *ST);
1260
1261 SPIRVTypeInst SpvElementType = nullptr;
1262 Type *ElemTy = ::getPointeeType(Ty);
1263 if (ElemTy && isa<FunctionType>(Val: ElemTy) &&
1264 !ST->canUseExtension(E: SPIRV::Extension::SPV_INTEL_function_pointers))
1265 ElemTy = nullptr;
1266 if (ElemTy)
1267 SpvElementType = getOrCreateSPIRVType(Type: ElemTy, MIRBuilder, AQ: AccQual, EmitIR);
1268 else
1269 SpvElementType = getOrCreateSPIRVIntegerType(BitWidth: 8, MIRBuilder);
1270
1271 if (!ElemTy) {
1272 ElemTy = Type::getInt8Ty(C&: MIRBuilder.getContext());
1273 }
1274
1275 // If we have forward pointer associated with this type, use its register
1276 // operand to create OpTypePointer.
1277 if (auto It = ForwardPointerTypes.find(Val: Ty); It != ForwardPointerTypes.end()) {
1278 Register Reg = getSPIRVTypeID(SpirvType: It->second);
1279 // TODO: what does getOpTypePointer do?
1280 return getOpTypePointer(SC, ElemType: SpvElementType, MIRBuilder, Reg);
1281 }
1282
1283 return getOrCreateSPIRVPointerType(BaseType: ElemTy, MIRBuilder, SC);
1284}
1285
1286SPIRVTypeInst SPIRVGlobalRegistry::restOfCreateSPIRVType(
1287 const Type *Ty, MachineIRBuilder &MIRBuilder,
1288 SPIRV::AccessQualifier::AccessQualifier AccessQual,
1289 bool ExplicitLayoutRequired, bool EmitIR) {
1290 // TODO: Could this create a problem if one requires an explicit layout, and
1291 // the next time it does not?
1292 if (TypesInProcessing.count(Ptr: Ty) && !isPointerTyOrWrapper(Ty))
1293 return nullptr;
1294 TypesInProcessing.insert(Ptr: Ty);
1295 SPIRVTypeInst SpirvType = createSPIRVType(Ty, MIRBuilder, AccQual: AccessQual,
1296 ExplicitLayoutRequired, EmitIR);
1297 TypesInProcessing.erase(Ptr: Ty);
1298 VRegToTypeMap[&MIRBuilder.getMF()][getSPIRVTypeID(SpirvType)] = SpirvType;
1299
1300 // TODO: We could end up with two SPIR-V types pointing to the same llvm type.
1301 // Is that a problem?
1302 SPIRVToLLVMType[SpirvType] = unifyPtrType(Ty);
1303
1304 if (SpirvType->getOpcode() == SPIRV::OpTypeForwardPointer ||
1305 findMI(T: Ty, RequiresExplicitLayout: false, MF: &MIRBuilder.getMF()) || isSpecialOpaqueType(Ty))
1306 return SpirvType;
1307
1308 if (auto *ExtTy = dyn_cast<TargetExtType>(Val: Ty);
1309 ExtTy && isTypedPointerWrapper(ExtTy))
1310 add(PointeeTy: ExtTy->getTypeParameter(i: 0), AddressSpace: ExtTy->getIntParameter(i: 0), MI: SpirvType);
1311 else if (!isPointerTy(T: Ty))
1312 add(T: Ty, RequiresExplicitLayout: ExplicitLayoutRequired, MI: SpirvType);
1313 else if (isTypedPointerTy(T: Ty))
1314 add(PointeeTy: cast<TypedPointerType>(Val: Ty)->getElementType(),
1315 AddressSpace: getPointerAddressSpace(T: Ty), MI: SpirvType);
1316 else
1317 add(PointeeTy: Type::getInt8Ty(C&: MIRBuilder.getMF().getFunction().getContext()),
1318 AddressSpace: getPointerAddressSpace(T: Ty), MI: SpirvType);
1319 return SpirvType;
1320}
1321
1322SPIRVTypeInst
1323SPIRVGlobalRegistry::getSPIRVTypeForVReg(Register VReg,
1324 const MachineFunction *MF) const {
1325 auto t = VRegToTypeMap.find(Val: MF ? MF : CurMF);
1326 if (t != VRegToTypeMap.end()) {
1327 auto tt = t->second.find(Val: VReg);
1328 if (tt != t->second.end())
1329 return tt->second;
1330 }
1331 return nullptr;
1332}
1333
1334SPIRVTypeInst SPIRVGlobalRegistry::getResultType(Register VReg,
1335 MachineFunction *MF) {
1336 if (!MF)
1337 MF = CurMF;
1338 MachineInstr *Instr = getVRegDef(MRI&: MF->getRegInfo(), Reg: VReg);
1339 return getSPIRVTypeForVReg(VReg: Instr->getOperand(i: 1).getReg(), MF);
1340}
1341
1342SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateSPIRVType(
1343 const Type *Ty, MachineIRBuilder &MIRBuilder,
1344 SPIRV::AccessQualifier::AccessQualifier AccessQual,
1345 bool ExplicitLayoutRequired, bool EmitIR) {
1346 // SPIR-V doesn't support single-element vectors. Treat <1 x T> as T.
1347 if (auto *FVT = dyn_cast<FixedVectorType>(Val: Ty);
1348 FVT && FVT->getNumElements() == 1)
1349 return getOrCreateSPIRVType(Ty: FVT->getElementType(), MIRBuilder, AccessQual,
1350 ExplicitLayoutRequired, EmitIR);
1351 const MachineFunction *MF = &MIRBuilder.getMF();
1352 Register Reg;
1353 if (auto *ExtTy = dyn_cast<TargetExtType>(Val: Ty);
1354 ExtTy && isTypedPointerWrapper(ExtTy))
1355 Reg = find(PointeeTy: ExtTy->getTypeParameter(i: 0), AddressSpace: ExtTy->getIntParameter(i: 0), MF);
1356 else if (!isPointerTy(T: Ty))
1357 Reg = find(T: Ty = adjustIntTypeByWidth(Ty), RequiresExplicitLayout: ExplicitLayoutRequired, MF);
1358 else if (isTypedPointerTy(T: Ty))
1359 Reg = find(PointeeTy: cast<TypedPointerType>(Val: Ty)->getElementType(),
1360 AddressSpace: getPointerAddressSpace(T: Ty), MF);
1361 else
1362 Reg = find(PointeeTy: Type::getInt8Ty(C&: MIRBuilder.getMF().getFunction().getContext()),
1363 AddressSpace: getPointerAddressSpace(T: Ty), MF);
1364 if (Reg.isValid() && !isSpecialOpaqueType(Ty))
1365 return getSPIRVTypeForVReg(VReg: Reg);
1366
1367 TypesInProcessing.clear();
1368 SPIRVTypeInst STy = restOfCreateSPIRVType(Ty, MIRBuilder, AccessQual,
1369 ExplicitLayoutRequired, EmitIR);
1370 // Create normal pointer types for the corresponding OpTypeForwardPointers.
1371 for (auto &CU : ForwardPointerTypes) {
1372 // Pointer type themselves do not require an explicit layout. The types
1373 // they pointer to might, but that is taken care of when creating the type.
1374 bool PtrNeedsLayout = false;
1375 const Type *Ty2 = CU.first;
1376 SPIRVTypeInst STy2 = CU.second;
1377 if ((Reg = find(T: Ty2, RequiresExplicitLayout: PtrNeedsLayout, MF)).isValid())
1378 STy2 = getSPIRVTypeForVReg(VReg: Reg);
1379 else
1380 STy2 = restOfCreateSPIRVType(Ty: Ty2, MIRBuilder, AccessQual, ExplicitLayoutRequired: PtrNeedsLayout,
1381 EmitIR);
1382 if (Ty == Ty2)
1383 STy = STy2;
1384 }
1385 ForwardPointerTypes.clear();
1386 return STy;
1387}
1388
1389bool SPIRVGlobalRegistry::isScalarOfType(Register VReg,
1390 unsigned TypeOpcode) const {
1391 SPIRVTypeInst Type = getSPIRVTypeForVReg(VReg);
1392 assert(Type && "isScalarOfType VReg has no type assigned");
1393 return Type->getOpcode() == TypeOpcode;
1394}
1395
1396bool SPIRVGlobalRegistry::isScalarOrVectorOfType(Register VReg,
1397 unsigned TypeOpcode) const {
1398 SPIRVTypeInst Type = getSPIRVTypeForVReg(VReg);
1399 assert(Type && "isScalarOrVectorOfType VReg has no type assigned");
1400 if (Type->getOpcode() == TypeOpcode)
1401 return true;
1402 if (Type->getOpcode() == SPIRV::OpTypeVector) {
1403 Register ScalarTypeVReg = Type->getOperand(i: 1).getReg();
1404 SPIRVTypeInst ScalarType = getSPIRVTypeForVReg(VReg: ScalarTypeVReg);
1405 return ScalarType->getOpcode() == TypeOpcode;
1406 }
1407 return false;
1408}
1409
1410bool SPIRVGlobalRegistry::isResourceType(SPIRVTypeInst Type) const {
1411 switch (Type->getOpcode()) {
1412 case SPIRV::OpTypeImage:
1413 case SPIRV::OpTypeSampler:
1414 case SPIRV::OpTypeSampledImage:
1415 return true;
1416 case SPIRV::OpTypeStruct:
1417 return hasBlockDecoration(Type);
1418 default:
1419 return false;
1420 }
1421 return false;
1422}
1423unsigned
1424SPIRVGlobalRegistry::getScalarOrVectorComponentCount(Register VReg) const {
1425 return getScalarOrVectorComponentCount(Type: getSPIRVTypeForVReg(VReg));
1426}
1427
1428unsigned
1429SPIRVGlobalRegistry::getScalarOrVectorComponentCount(SPIRVTypeInst Type) const {
1430 if (!Type)
1431 return 0;
1432 return Type->getOpcode() == SPIRV::OpTypeVector
1433 ? static_cast<unsigned>(Type->getOperand(i: 2).getImm())
1434 : 1;
1435}
1436
1437SPIRVTypeInst
1438SPIRVGlobalRegistry::getScalarOrVectorComponentType(SPIRVTypeInst Type) const {
1439 if (!Type)
1440 return nullptr;
1441 Register ScalarReg = Type->getOpcode() == SPIRV::OpTypeVector
1442 ? Type->getOperand(i: 1).getReg()
1443 : Type->getOperand(i: 0).getReg();
1444 SPIRVTypeInst ScalarType = getSPIRVTypeForVReg(VReg: ScalarReg);
1445 assert(isScalarOrVectorOfType(Type->getOperand(0).getReg(),
1446 ScalarType->getOpcode()));
1447 return ScalarType;
1448}
1449
1450unsigned
1451SPIRVGlobalRegistry::getScalarOrVectorBitWidth(SPIRVTypeInst Type) const {
1452 assert(Type && "Invalid Type pointer");
1453 SPIRVTypeInst ScalarType = getScalarOrVectorComponentType(Type);
1454 if (ScalarType->getOpcode() == SPIRV::OpTypeInt ||
1455 ScalarType->getOpcode() == SPIRV::OpTypeFloat)
1456 return ScalarType->getOperand(i: 1).getImm();
1457 if (ScalarType->getOpcode() == SPIRV::OpTypeBool)
1458 return 1;
1459 llvm_unreachable("Attempting to get bit width of non-integer/float type.");
1460}
1461
1462unsigned SPIRVGlobalRegistry::getNumScalarOrVectorTotalBitWidth(
1463 SPIRVTypeInst Type) const {
1464 assert(Type && "Invalid Type pointer");
1465 unsigned NumElements = getScalarOrVectorComponentCount(Type);
1466 SPIRVTypeInst ScalarType = getScalarOrVectorComponentType(Type);
1467 return ScalarType->getOpcode() == SPIRV::OpTypeInt ||
1468 ScalarType->getOpcode() == SPIRV::OpTypeFloat
1469 ? NumElements * ScalarType->getOperand(i: 1).getImm()
1470 : 0;
1471}
1472
1473SPIRVTypeInst
1474SPIRVGlobalRegistry::retrieveScalarOrVectorIntType(SPIRVTypeInst Type) const {
1475 SPIRVTypeInst ScalarType = getScalarOrVectorComponentType(Type);
1476 return ScalarType && ScalarType->getOpcode() == SPIRV::OpTypeInt ? ScalarType
1477 : nullptr;
1478}
1479
1480bool SPIRVGlobalRegistry::isScalarOrVectorSigned(SPIRVTypeInst Type) const {
1481 SPIRVTypeInst IntType = retrieveScalarOrVectorIntType(Type);
1482 return IntType && IntType->getOperand(i: 2).getImm() != 0;
1483}
1484
1485SPIRVTypeInst SPIRVGlobalRegistry::getPointeeType(SPIRVTypeInst PtrType) {
1486 return PtrType && PtrType->getOpcode() == SPIRV::OpTypePointer
1487 ? getSPIRVTypeForVReg(VReg: PtrType->getOperand(i: 2).getReg())
1488 : nullptr;
1489}
1490
1491unsigned SPIRVGlobalRegistry::getPointeeTypeOp(Register PtrReg) {
1492 SPIRVTypeInst ElemType = getPointeeType(PtrType: getSPIRVTypeForVReg(VReg: PtrReg));
1493 return ElemType ? ElemType->getOpcode() : 0;
1494}
1495
1496bool SPIRVGlobalRegistry::isBitcastCompatible(SPIRVTypeInst Type1,
1497 SPIRVTypeInst Type2) const {
1498 if (!Type1 || !Type2)
1499 return false;
1500 auto Op1 = Type1->getOpcode(), Op2 = Type2->getOpcode();
1501 // Ignore difference between <1.5 and >=1.5 protocol versions:
1502 // it's valid if either Result Type or Operand is a pointer, and the other
1503 // is a pointer, an integer scalar, or an integer vector.
1504 if (Op1 == SPIRV::OpTypePointer &&
1505 (Op2 == SPIRV::OpTypePointer || retrieveScalarOrVectorIntType(Type: Type2)))
1506 return true;
1507 if (Op2 == SPIRV::OpTypePointer &&
1508 (Op1 == SPIRV::OpTypePointer || retrieveScalarOrVectorIntType(Type: Type1)))
1509 return true;
1510 unsigned Bits1 = getNumScalarOrVectorTotalBitWidth(Type: Type1),
1511 Bits2 = getNumScalarOrVectorTotalBitWidth(Type: Type2);
1512 return Bits1 > 0 && Bits1 == Bits2;
1513}
1514
1515SPIRV::StorageClass::StorageClass
1516SPIRVGlobalRegistry::getPointerStorageClass(Register VReg) const {
1517 SPIRVTypeInst Type = getSPIRVTypeForVReg(VReg);
1518 assert(Type && Type->getOpcode() == SPIRV::OpTypePointer &&
1519 Type->getOperand(1).isImm() && "Pointer type is expected");
1520 return getPointerStorageClass(Type);
1521}
1522
1523SPIRV::StorageClass::StorageClass
1524SPIRVGlobalRegistry::getPointerStorageClass(SPIRVTypeInst Type) const {
1525 return static_cast<SPIRV::StorageClass::StorageClass>(
1526 Type->getOperand(i: 1).getImm());
1527}
1528
1529SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateVulkanBufferType(
1530 MachineIRBuilder &MIRBuilder, Type *ElemType,
1531 SPIRV::StorageClass::StorageClass SC, bool IsWritable, bool EmitIr) {
1532 auto Key = SPIRV::irhandle_vkbuffer(ElementType: ElemType, SC, IsWriteable: IsWritable);
1533 if (const MachineInstr *MI = findMI(Handle: Key, MF: &MIRBuilder.getMF()))
1534 return MI;
1535
1536 bool ExplicitLayoutRequired = storageClassRequiresExplictLayout(SC);
1537 // We need to get the SPIR-V type for the element here, so we can add the
1538 // decoration to it.
1539 auto *T = StructType::create(Elements: ElemType);
1540 SPIRVTypeInst BlockType =
1541 getOrCreateSPIRVType(Ty: T, MIRBuilder, AccessQual: SPIRV::AccessQualifier::None,
1542 ExplicitLayoutRequired, EmitIR: EmitIr);
1543
1544 buildOpDecorate(Reg: BlockType->defs().begin()->getReg(), MIRBuilder,
1545 Dec: SPIRV::Decoration::Block, DecArgs: {});
1546
1547 if (!IsWritable) {
1548 buildOpMemberDecorate(Reg: BlockType->defs().begin()->getReg(), MIRBuilder,
1549 Dec: SPIRV::Decoration::NonWritable, Member: 0, DecArgs: {});
1550 }
1551
1552 SPIRVTypeInst R =
1553 getOrCreateSPIRVPointerTypeInternal(BaseType: BlockType, MIRBuilder, SC);
1554 add(Handle: Key, MI: R);
1555 return R;
1556}
1557
1558SPIRVTypeInst
1559SPIRVGlobalRegistry::getOrCreatePaddingType(MachineIRBuilder &MIRBuilder) {
1560 auto Key = SPIRV::irhandle_padding();
1561 if (const MachineInstr *MI = findMI(Handle: Key, MF: &MIRBuilder.getMF()))
1562 return MI;
1563 auto *T = Type::getInt8Ty(C&: MIRBuilder.getContext());
1564 SPIRVTypeInst R = getOrCreateSPIRVIntegerType(BitWidth: 8, MIRBuilder);
1565 finishCreatingSPIRVType(LLVMTy: T, SpirvType: R);
1566 add(Handle: Key, MI: R);
1567 return R;
1568}
1569
1570SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateVulkanPushConstantType(
1571 MachineIRBuilder &MIRBuilder, Type *T) {
1572 const auto SC = SPIRV::StorageClass::PushConstant;
1573
1574 auto Key = SPIRV::irhandle_vkbuffer(ElementType: T, SC, /* IsWritable= */ IsWriteable: false);
1575 if (const MachineInstr *MI = findMI(Handle: Key, MF: &MIRBuilder.getMF()))
1576 return MI;
1577
1578 // We need to get the SPIR-V type for the element here, so we can add the
1579 // decoration to it.
1580 SPIRVTypeInst BlockType = getOrCreateSPIRVType(
1581 Ty: T, MIRBuilder, AccessQual: SPIRV::AccessQualifier::None,
1582 /* ExplicitLayoutRequired= */ true, /* EmitIr= */ EmitIR: false);
1583
1584 buildOpDecorate(Reg: BlockType->defs().begin()->getReg(), MIRBuilder,
1585 Dec: SPIRV::Decoration::Block, DecArgs: {});
1586 SPIRVTypeInst R = BlockType;
1587 add(Handle: Key, MI: R);
1588 return R;
1589}
1590
1591SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateLayoutType(
1592 MachineIRBuilder &MIRBuilder, const TargetExtType *T, bool EmitIr) {
1593 auto Key = SPIRV::handle(Ty: T);
1594 if (const MachineInstr *MI = findMI(Handle: Key, MF: &MIRBuilder.getMF()))
1595 return MI;
1596
1597 StructType *ST = cast<StructType>(Val: T->getTypeParameter(i: 0));
1598 ArrayRef<uint32_t> Offsets = T->int_params().slice(N: 1);
1599 assert(ST->getNumElements() == Offsets.size());
1600
1601 StructOffsetDecorator Decorator = [&MIRBuilder, &Offsets](Register Reg) {
1602 for (uint32_t I = 0; I < Offsets.size(); ++I) {
1603 buildOpMemberDecorate(Reg, MIRBuilder, Dec: SPIRV::Decoration::Offset, Member: I,
1604 DecArgs: {Offsets[I]});
1605 }
1606 };
1607
1608 // We need a new OpTypeStruct instruction because decorations will be
1609 // different from a struct with an explicit layout created from a different
1610 // entry point.
1611 SPIRVTypeInst SPIRVStructType =
1612 getOpTypeStruct(Ty: ST, MIRBuilder, AccQual: SPIRV::AccessQualifier::None,
1613 Decorator: std::move(Decorator), EmitIR: EmitIr);
1614 add(Handle: Key, MI: SPIRVStructType);
1615 return SPIRVStructType;
1616}
1617
1618SPIRVTypeInst SPIRVGlobalRegistry::getImageType(
1619 const TargetExtType *ExtensionType,
1620 const SPIRV::AccessQualifier::AccessQualifier Qualifier,
1621 MachineIRBuilder &MIRBuilder) {
1622 assert(ExtensionType->getNumTypeParameters() == 1 &&
1623 "SPIR-V image builtin type must have sampled type parameter!");
1624 const SPIRVTypeInst SampledType =
1625 getOrCreateSPIRVType(Type: ExtensionType->getTypeParameter(i: 0), MIRBuilder,
1626 AQ: SPIRV::AccessQualifier::ReadWrite, EmitIR: true);
1627 assert((ExtensionType->getNumIntParameters() == 7 ||
1628 ExtensionType->getNumIntParameters() == 6) &&
1629 "Invalid number of parameters for SPIR-V image builtin!");
1630
1631 SPIRV::AccessQualifier::AccessQualifier accessQualifier =
1632 SPIRV::AccessQualifier::None;
1633 if (ExtensionType->getNumIntParameters() == 7) {
1634 accessQualifier = Qualifier == SPIRV::AccessQualifier::WriteOnly
1635 ? SPIRV::AccessQualifier::WriteOnly
1636 : SPIRV::AccessQualifier::AccessQualifier(
1637 ExtensionType->getIntParameter(i: 6));
1638 }
1639
1640 // Create or get an existing type from GlobalRegistry.
1641 SPIRVTypeInst R = getOrCreateOpTypeImage(
1642 MIRBuilder, SampledType,
1643 Dim: SPIRV::Dim::Dim(ExtensionType->getIntParameter(i: 0)),
1644 Depth: ExtensionType->getIntParameter(i: 1), Arrayed: ExtensionType->getIntParameter(i: 2),
1645 Multisampled: ExtensionType->getIntParameter(i: 3), Sampled: ExtensionType->getIntParameter(i: 4),
1646 ImageFormat: SPIRV::ImageFormat::ImageFormat(ExtensionType->getIntParameter(i: 5)),
1647 AccQual: accessQualifier);
1648 SPIRVToLLVMType[R] = ExtensionType;
1649 return R;
1650}
1651
1652SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateOpTypeImage(
1653 MachineIRBuilder &MIRBuilder, SPIRVTypeInst SampledType,
1654 SPIRV::Dim::Dim Dim, uint32_t Depth, uint32_t Arrayed,
1655 uint32_t Multisampled, uint32_t Sampled,
1656 SPIRV::ImageFormat::ImageFormat ImageFormat,
1657 SPIRV::AccessQualifier::AccessQualifier AccessQual) {
1658 auto Key = SPIRV::irhandle_image(SampledTy: SPIRVToLLVMType.lookup(Val: SampledType), Dim,
1659 Depth, Arrayed, MS: Multisampled, Sampled,
1660 ImageFormat, AQ: AccessQual);
1661 if (const MachineInstr *MI = findMI(Handle: Key, MF: &MIRBuilder.getMF()))
1662 return MI;
1663 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
1664 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1665 auto MIB =
1666 MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeImage)
1667 .addDef(RegNo: createTypeVReg(MIRBuilder))
1668 .addUse(RegNo: getSPIRVTypeID(SpirvType: SampledType))
1669 .addImm(Val: Dim)
1670 .addImm(Val: Depth) // Depth (whether or not it is a Depth image).
1671 .addImm(Val: Arrayed) // Arrayed.
1672 .addImm(Val: Multisampled) // Multisampled (0 = only single-sample).
1673 .addImm(Val: Sampled) // Sampled (0 = usage known at runtime).
1674 .addImm(Val: ImageFormat);
1675 if (AccessQual != SPIRV::AccessQualifier::None)
1676 MIB.addImm(Val: AccessQual);
1677 return MIB;
1678 });
1679 add(Handle: Key, MI: NewMI);
1680 return NewMI;
1681}
1682
1683SPIRVTypeInst
1684SPIRVGlobalRegistry::getOrCreateOpTypeSampler(MachineIRBuilder &MIRBuilder) {
1685 auto Key = SPIRV::irhandle_sampler();
1686 const MachineFunction *MF = &MIRBuilder.getMF();
1687 if (const MachineInstr *MI = findMI(Handle: Key, MF))
1688 return MI;
1689 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
1690 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1691 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeSampler)
1692 .addDef(RegNo: createTypeVReg(MIRBuilder));
1693 });
1694 add(Handle: Key, MI: NewMI);
1695 return NewMI;
1696}
1697
1698SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateOpTypePipe(
1699 MachineIRBuilder &MIRBuilder,
1700 SPIRV::AccessQualifier::AccessQualifier AccessQual) {
1701 auto Key = SPIRV::irhandle_pipe(AQ: AccessQual);
1702 if (const MachineInstr *MI = findMI(Handle: Key, MF: &MIRBuilder.getMF()))
1703 return MI;
1704 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
1705 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1706 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypePipe)
1707 .addDef(RegNo: createTypeVReg(MIRBuilder))
1708 .addImm(Val: AccessQual);
1709 });
1710 add(Handle: Key, MI: NewMI);
1711 return NewMI;
1712}
1713
1714SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateOpTypeDeviceEvent(
1715 MachineIRBuilder &MIRBuilder) {
1716 auto Key = SPIRV::irhandle_event();
1717 if (const MachineInstr *MI = findMI(Handle: Key, MF: &MIRBuilder.getMF()))
1718 return MI;
1719 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
1720 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1721 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeDeviceEvent)
1722 .addDef(RegNo: createTypeVReg(MIRBuilder));
1723 });
1724 add(Handle: Key, MI: NewMI);
1725 return NewMI;
1726}
1727
1728SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateOpTypeSampledImage(
1729 SPIRVTypeInst ImageType, MachineIRBuilder &MIRBuilder) {
1730 auto Key = SPIRV::irhandle_sampled_image(
1731 SampledTy: SPIRVToLLVMType.lookup(Val: MIRBuilder.getMF().getRegInfo().getVRegDef(
1732 Reg: ImageType->getOperand(i: 1).getReg())),
1733 ImageTy: ImageType);
1734 if (const MachineInstr *MI = findMI(Handle: Key, MF: &MIRBuilder.getMF()))
1735 return MI;
1736 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
1737 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1738 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeSampledImage)
1739 .addDef(RegNo: createTypeVReg(MIRBuilder))
1740 .addUse(RegNo: getSPIRVTypeID(SpirvType: ImageType));
1741 });
1742 add(Handle: Key, MI: NewMI);
1743 return NewMI;
1744}
1745
1746SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateOpTypeCoopMatr(
1747 MachineIRBuilder &MIRBuilder, const TargetExtType *ExtensionType,
1748 SPIRVTypeInst ElemType, uint32_t Scope, uint32_t Rows, uint32_t Columns,
1749 uint32_t Use, bool EmitIR) {
1750 if (const MachineInstr *MI =
1751 findMI(T: ExtensionType, RequiresExplicitLayout: false, MF: &MIRBuilder.getMF()))
1752 return MI;
1753 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
1754 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1755 SPIRVTypeInst SpvTypeInt32 =
1756 getOrCreateSPIRVIntegerType(BitWidth: 32, MIRBuilder);
1757 const Type *ET = getTypeForSPIRVType(Ty: ElemType);
1758 if (ET->isIntegerTy() && ET->getIntegerBitWidth() == 4 &&
1759 cast<SPIRVSubtarget>(Val: MIRBuilder.getMF().getSubtarget())
1760 .canUseExtension(E: SPIRV::Extension::SPV_INTEL_int4)) {
1761 MIRBuilder.buildInstr(Opcode: SPIRV::OpCapability)
1762 .addImm(Val: SPIRV::Capability::Int4CooperativeMatrixINTEL);
1763 }
1764 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeCooperativeMatrixKHR)
1765 .addDef(RegNo: createTypeVReg(MIRBuilder))
1766 .addUse(RegNo: getSPIRVTypeID(SpirvType: ElemType))
1767 .addUse(RegNo: buildConstantInt(Val: Scope, MIRBuilder, SpvType: SpvTypeInt32, EmitIR))
1768 .addUse(RegNo: buildConstantInt(Val: Rows, MIRBuilder, SpvType: SpvTypeInt32, EmitIR))
1769 .addUse(RegNo: buildConstantInt(Val: Columns, MIRBuilder, SpvType: SpvTypeInt32, EmitIR))
1770 .addUse(RegNo: buildConstantInt(Val: Use, MIRBuilder, SpvType: SpvTypeInt32, EmitIR));
1771 });
1772 add(T: ExtensionType, RequiresExplicitLayout: false, MI: NewMI);
1773 return NewMI;
1774}
1775
1776SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateOpTypeByOpcode(
1777 const Type *Ty, MachineIRBuilder &MIRBuilder, unsigned Opcode) {
1778 if (const MachineInstr *MI = findMI(T: Ty, RequiresExplicitLayout: false, MF: &MIRBuilder.getMF()))
1779 return MI;
1780 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
1781 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1782 return MIRBuilder.buildInstr(Opcode).addDef(RegNo: createTypeVReg(MIRBuilder));
1783 });
1784 add(T: Ty, RequiresExplicitLayout: false, MI: NewMI);
1785 return NewMI;
1786}
1787
1788SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateUnknownType(
1789 const Type *Ty, MachineIRBuilder &MIRBuilder, unsigned Opcode,
1790 const ArrayRef<MCOperand> Operands) {
1791 if (const MachineInstr *MI = findMI(T: Ty, RequiresExplicitLayout: false, MF: &MIRBuilder.getMF()))
1792 return MI;
1793 Register ResVReg = createTypeVReg(MIRBuilder);
1794 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
1795 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1796 MachineInstrBuilder MIB = MIRBuilder.buildInstr(Opcode: SPIRV::UNKNOWN_type)
1797 .addDef(RegNo: ResVReg)
1798 .addImm(Val: Opcode);
1799 for (MCOperand Operand : Operands) {
1800 if (Operand.isReg()) {
1801 MIB.addUse(RegNo: Operand.getReg());
1802 } else if (Operand.isImm()) {
1803 MIB.addImm(Val: Operand.getImm());
1804 }
1805 }
1806 return MIB;
1807 });
1808 add(T: Ty, RequiresExplicitLayout: false, MI: NewMI);
1809 return NewMI;
1810}
1811
1812// Returns nullptr if unable to recognize SPIRV type name
1813SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateSPIRVTypeByName(
1814 StringRef TypeStr, MachineIRBuilder &MIRBuilder, bool EmitIR,
1815 SPIRV::StorageClass::StorageClass SC,
1816 SPIRV::AccessQualifier::AccessQualifier AQ) {
1817 unsigned VecElts = 0;
1818 auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
1819
1820 // Parse strings representing either a SPIR-V or OpenCL builtin type.
1821 if (hasBuiltinTypePrefix(Name: TypeStr))
1822 return getOrCreateSPIRVType(Ty: SPIRV::parseBuiltinTypeNameToTargetExtType(
1823 TypeName: TypeStr.str(), Context&: MIRBuilder.getContext()),
1824 MIRBuilder, AccessQual: AQ, ExplicitLayoutRequired: false, EmitIR: true);
1825
1826 // Parse type name in either "typeN" or "type vector[N]" format, where
1827 // N is the number of elements of the vector.
1828 Type *Ty;
1829
1830 Ty = parseBasicTypeName(TypeName&: TypeStr, Ctx);
1831 if (!Ty)
1832 // Unable to recognize SPIRV type name
1833 return nullptr;
1834
1835 SPIRVTypeInst SpirvTy = getOrCreateSPIRVType(Ty, MIRBuilder, AccessQual: AQ, ExplicitLayoutRequired: false, EmitIR: true);
1836
1837 // Handle "type*" or "type* vector[N]".
1838 if (TypeStr.consume_front(Prefix: "*"))
1839 SpirvTy = getOrCreateSPIRVPointerType(BaseType: Ty, MIRBuilder, SC);
1840
1841 // Handle "typeN*" or "type vector[N]*".
1842 bool IsPtrToVec = TypeStr.consume_back(Suffix: "*");
1843
1844 if (TypeStr.consume_front(Prefix: " vector[")) {
1845 TypeStr = TypeStr.substr(Start: 0, N: TypeStr.find(C: ']'));
1846 }
1847 TypeStr.getAsInteger(Radix: 10, Result&: VecElts);
1848 if (VecElts > 0)
1849 SpirvTy = getOrCreateSPIRVVectorType(BaseType: SpirvTy, NumElements: VecElts, MIRBuilder, EmitIR);
1850
1851 if (IsPtrToVec)
1852 SpirvTy = getOrCreateSPIRVPointerType(BaseType: SpirvTy, MIRBuilder, SC);
1853
1854 return SpirvTy;
1855}
1856
1857SPIRVTypeInst
1858SPIRVGlobalRegistry::getOrCreateSPIRVIntegerType(unsigned BitWidth,
1859 MachineIRBuilder &MIRBuilder) {
1860 return getOrCreateSPIRVType(
1861 Ty: IntegerType::get(C&: MIRBuilder.getMF().getFunction().getContext(), NumBits: BitWidth),
1862 MIRBuilder, AccessQual: SPIRV::AccessQualifier::ReadWrite, ExplicitLayoutRequired: false, EmitIR: true);
1863}
1864
1865SPIRVTypeInst
1866SPIRVGlobalRegistry::finishCreatingSPIRVType(const Type *LLVMTy,
1867 SPIRVTypeInst SpirvType) {
1868 assert(CurMF == SpirvType->getMF());
1869 VRegToTypeMap[CurMF][getSPIRVTypeID(SpirvType)] = SpirvType;
1870 SPIRVToLLVMType[SpirvType] = unifyPtrType(Ty: LLVMTy);
1871 return SpirvType;
1872}
1873
1874SPIRVTypeInst
1875SPIRVGlobalRegistry::getOrCreateSPIRVType(unsigned BitWidth, MachineInstr &I,
1876 const SPIRVInstrInfo &TII,
1877 unsigned SPIRVOPcode, Type *Ty) {
1878 if (const MachineInstr *MI = findMI(T: Ty, RequiresExplicitLayout: false, MF: CurMF))
1879 return MI;
1880 MachineBasicBlock &DepMBB = I.getMF()->front();
1881 MachineIRBuilder MIRBuilder(DepMBB, DepMBB.getFirstNonPHI());
1882 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
1883 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1884 auto NewTypeMI = BuildMI(BB&: MIRBuilder.getMBB(), I&: *MIRBuilder.getInsertPt(),
1885 MIMD: MIRBuilder.getDL(), MCID: TII.get(Opcode: SPIRVOPcode))
1886 .addDef(RegNo: createTypeVReg(MRI&: CurMF->getRegInfo()))
1887 .addImm(Val: BitWidth);
1888 // Don't add Encoding to FP type
1889 if (!Ty->isFloatTy()) {
1890 return NewTypeMI.addImm(Val: 0);
1891 } else {
1892 return NewTypeMI;
1893 }
1894 });
1895 add(T: Ty, RequiresExplicitLayout: false, MI: NewMI);
1896 return finishCreatingSPIRVType(LLVMTy: Ty, SpirvType: NewMI);
1897}
1898
1899SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateSPIRVIntegerType(
1900 unsigned BitWidth, MachineInstr &I, const SPIRVInstrInfo &TII) {
1901 // Maybe adjust bit width to keep DuplicateTracker consistent. Without
1902 // such an adjustment SPIRVGlobalRegistry::getOpTypeInt() could create, for
1903 // example, the same "OpTypeInt 8" type for a series of LLVM integer types
1904 // with number of bits less than 8, causing duplicate type definitions.
1905 if (BitWidth > 1)
1906 BitWidth = adjustOpTypeIntWidth(Width: BitWidth);
1907 Type *LLVMTy = IntegerType::get(C&: CurMF->getFunction().getContext(), NumBits: BitWidth);
1908 return getOrCreateSPIRVType(BitWidth, I, TII, SPIRVOPcode: SPIRV::OpTypeInt, Ty: LLVMTy);
1909}
1910
1911SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateSPIRVFloatType(
1912 unsigned BitWidth, MachineInstr &I, const SPIRVInstrInfo &TII) {
1913 LLVMContext &Ctx = CurMF->getFunction().getContext();
1914 Type *LLVMTy;
1915 switch (BitWidth) {
1916 case 16:
1917 LLVMTy = Type::getHalfTy(C&: Ctx);
1918 break;
1919 case 32:
1920 LLVMTy = Type::getFloatTy(C&: Ctx);
1921 break;
1922 case 64:
1923 LLVMTy = Type::getDoubleTy(C&: Ctx);
1924 break;
1925 default:
1926 llvm_unreachable("Bit width is of unexpected size.");
1927 }
1928 return getOrCreateSPIRVType(BitWidth, I, TII, SPIRVOPcode: SPIRV::OpTypeFloat, Ty: LLVMTy);
1929}
1930
1931SPIRVTypeInst
1932SPIRVGlobalRegistry::getOrCreateSPIRVBoolType(MachineIRBuilder &MIRBuilder,
1933 bool EmitIR) {
1934 return getOrCreateSPIRVType(
1935 Ty: IntegerType::get(C&: MIRBuilder.getMF().getFunction().getContext(), NumBits: 1),
1936 MIRBuilder, AccessQual: SPIRV::AccessQualifier::ReadWrite, ExplicitLayoutRequired: false, EmitIR);
1937}
1938
1939SPIRVTypeInst
1940SPIRVGlobalRegistry::getOrCreateSPIRVBoolType(MachineInstr &I,
1941 const SPIRVInstrInfo &TII) {
1942 Type *Ty = IntegerType::get(C&: CurMF->getFunction().getContext(), NumBits: 1);
1943 if (const MachineInstr *MI = findMI(T: Ty, RequiresExplicitLayout: false, MF: CurMF))
1944 return MI;
1945 MachineBasicBlock &DepMBB = I.getMF()->front();
1946 MachineIRBuilder MIRBuilder(DepMBB, DepMBB.getFirstNonPHI());
1947 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
1948 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1949 return BuildMI(BB&: MIRBuilder.getMBB(), I&: *MIRBuilder.getInsertPt(),
1950 MIMD: MIRBuilder.getDL(), MCID: TII.get(Opcode: SPIRV::OpTypeBool))
1951 .addDef(RegNo: createTypeVReg(MRI&: CurMF->getRegInfo()));
1952 });
1953 add(T: Ty, RequiresExplicitLayout: false, MI: NewMI);
1954 return finishCreatingSPIRVType(LLVMTy: Ty, SpirvType: NewMI);
1955}
1956
1957SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateSPIRVVectorType(
1958 SPIRVTypeInst BaseType, unsigned NumElements, MachineIRBuilder &MIRBuilder,
1959 bool EmitIR) {
1960 return getOrCreateSPIRVType(
1961 Ty: FixedVectorType::get(ElementType: const_cast<Type *>(getTypeForSPIRVType(Ty: BaseType)),
1962 NumElts: NumElements),
1963 MIRBuilder, AccessQual: SPIRV::AccessQualifier::ReadWrite, ExplicitLayoutRequired: false, EmitIR);
1964}
1965
1966SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateSPIRVVectorType(
1967 SPIRVTypeInst BaseType, unsigned NumElements, MachineInstr &I,
1968 const SPIRVInstrInfo &TII) {
1969 // At this point of time all 1-element vectors are resolved. Add assertion
1970 // to fire if anything changes.
1971 assert(NumElements >= 2 && "SPIR-V vectors must have at least 2 components");
1972 Type *Ty = FixedVectorType::get(
1973 ElementType: const_cast<Type *>(getTypeForSPIRVType(Ty: BaseType)), NumElts: NumElements);
1974 if (const MachineInstr *MI = findMI(T: Ty, RequiresExplicitLayout: false, MF: CurMF))
1975 return MI;
1976 MachineInstr *DepMI =
1977 const_cast<MachineInstr *>(static_cast<const MachineInstr *>(BaseType));
1978 MachineIRBuilder MIRBuilder(*DepMI->getParent(), DepMI->getIterator());
1979 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
1980 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1981 return BuildMI(BB&: MIRBuilder.getMBB(), I&: *MIRBuilder.getInsertPt(),
1982 MIMD: MIRBuilder.getDL(), MCID: TII.get(Opcode: SPIRV::OpTypeVector))
1983 .addDef(RegNo: createTypeVReg(MRI&: CurMF->getRegInfo()))
1984 .addUse(RegNo: getSPIRVTypeID(SpirvType: BaseType))
1985 .addImm(Val: NumElements);
1986 });
1987 add(T: Ty, RequiresExplicitLayout: false, MI: NewMI);
1988 return finishCreatingSPIRVType(LLVMTy: Ty, SpirvType: NewMI);
1989}
1990
1991SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateSPIRVPointerType(
1992 const Type *BaseType, MachineInstr &I,
1993 SPIRV::StorageClass::StorageClass SC) {
1994 MachineIRBuilder MIRBuilder(I);
1995 return getOrCreateSPIRVPointerType(BaseType, MIRBuilder, SC);
1996}
1997
1998SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateSPIRVPointerType(
1999 const Type *BaseType, MachineIRBuilder &MIRBuilder,
2000 SPIRV::StorageClass::StorageClass SC) {
2001 // TODO: Need to check if EmitIr should always be true.
2002 SPIRVTypeInst SpirvBaseType = getOrCreateSPIRVType(
2003 Ty: BaseType, MIRBuilder, AccessQual: SPIRV::AccessQualifier::ReadWrite,
2004 ExplicitLayoutRequired: storageClassRequiresExplictLayout(SC), EmitIR: true);
2005 assert(SpirvBaseType);
2006 return getOrCreateSPIRVPointerTypeInternal(BaseType: SpirvBaseType, MIRBuilder, SC);
2007}
2008
2009SPIRVTypeInst SPIRVGlobalRegistry::changePointerStorageClass(
2010 SPIRVTypeInst PtrType, SPIRV::StorageClass::StorageClass SC,
2011 MachineInstr &I) {
2012 [[maybe_unused]] SPIRV::StorageClass::StorageClass OldSC =
2013 getPointerStorageClass(Type: PtrType);
2014 assert(storageClassRequiresExplictLayout(OldSC) ==
2015 storageClassRequiresExplictLayout(SC));
2016
2017 SPIRVTypeInst PointeeType = getPointeeType(PtrType);
2018 MachineIRBuilder MIRBuilder(I);
2019 return getOrCreateSPIRVPointerTypeInternal(BaseType: PointeeType, MIRBuilder, SC);
2020}
2021
2022SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateSPIRVPointerType(
2023 SPIRVTypeInst BaseType, MachineIRBuilder &MIRBuilder,
2024 SPIRV::StorageClass::StorageClass SC) {
2025 const Type *LLVMType = getTypeForSPIRVType(Ty: BaseType);
2026 assert(!storageClassRequiresExplictLayout(SC));
2027 SPIRVTypeInst R = getOrCreateSPIRVPointerType(BaseType: LLVMType, MIRBuilder, SC);
2028 assert(
2029 getPointeeType(R) == BaseType &&
2030 "The base type was not correctly laid out for the given storage class.");
2031 return R;
2032}
2033
2034SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateSPIRVPointerTypeInternal(
2035 SPIRVTypeInst BaseType, MachineIRBuilder &MIRBuilder,
2036 SPIRV::StorageClass::StorageClass SC) {
2037 const Type *PointerElementType = getTypeForSPIRVType(Ty: BaseType);
2038 unsigned AddressSpace = storageClassToAddressSpace(SC);
2039 if (const MachineInstr *MI = findMI(PointeeTy: PointerElementType, AddressSpace, MF: CurMF))
2040 return MI;
2041 Type *Ty = TypedPointerType::get(ElementType: const_cast<Type *>(PointerElementType),
2042 AddressSpace);
2043 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
2044 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
2045 return BuildMI(BB&: MIRBuilder.getMBB(), I: MIRBuilder.getInsertPt(),
2046 MIMD: MIRBuilder.getDebugLoc(),
2047 MCID: MIRBuilder.getTII().get(Opcode: SPIRV::OpTypePointer))
2048 .addDef(RegNo: createTypeVReg(MRI&: CurMF->getRegInfo()))
2049 .addImm(Val: static_cast<uint32_t>(SC))
2050 .addUse(RegNo: getSPIRVTypeID(SpirvType: BaseType));
2051 });
2052 add(PointeeTy: PointerElementType, AddressSpace, MI: NewMI);
2053 return finishCreatingSPIRVType(LLVMTy: Ty, SpirvType: NewMI);
2054}
2055
2056Register SPIRVGlobalRegistry::getOrCreateUndef(MachineInstr &I,
2057 SPIRVTypeInst SpvType,
2058 const SPIRVInstrInfo &TII) {
2059 UndefValue *UV =
2060 UndefValue::get(T: const_cast<Type *>(getTypeForSPIRVType(Ty: SpvType)));
2061 Register Res = find(V: UV, MF: CurMF);
2062 if (Res.isValid())
2063 return Res;
2064
2065 LLT LLTy = LLT::scalar(SizeInBits: 64);
2066 Res = CurMF->getRegInfo().createGenericVirtualRegister(Ty: LLTy);
2067 CurMF->getRegInfo().setRegClass(Reg: Res, RC: &SPIRV::iIDRegClass);
2068 assignSPIRVTypeToVReg(SpirvType: SpvType, VReg: Res, MF: *CurMF);
2069
2070 MachineInstr *DepMI =
2071 const_cast<MachineInstr *>(static_cast<const MachineInstr *>(SpvType));
2072 MachineIRBuilder MIRBuilder(*DepMI->getParent(), DepMI->getIterator());
2073 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
2074 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
2075 auto MIB = BuildMI(BB&: MIRBuilder.getMBB(), I&: *MIRBuilder.getInsertPt(),
2076 MIMD: MIRBuilder.getDL(), MCID: TII.get(Opcode: SPIRV::OpUndef))
2077 .addDef(RegNo: Res)
2078 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
2079 const auto &ST = CurMF->getSubtarget();
2080 constrainSelectedInstRegOperands(I&: *MIB, TII: *ST.getInstrInfo(),
2081 TRI: *ST.getRegisterInfo(),
2082 RBI: *ST.getRegBankInfo());
2083 return MIB;
2084 });
2085 add(V: UV, MI: NewMI);
2086 return Res;
2087}
2088
2089const TargetRegisterClass *
2090SPIRVGlobalRegistry::getRegClass(SPIRVTypeInst SpvType) const {
2091 unsigned Opcode = SpvType->getOpcode();
2092 switch (Opcode) {
2093 case SPIRV::OpTypeFloat:
2094 return &SPIRV::fIDRegClass;
2095 case SPIRV::OpTypePointer:
2096 return &SPIRV::pIDRegClass;
2097 case SPIRV::OpTypeVector: {
2098 SPIRVTypeInst ElemType = getScalarOrVectorComponentType(Type: SpvType);
2099 unsigned ElemOpcode = ElemType ? ElemType->getOpcode() : 0;
2100 if (ElemOpcode == SPIRV::OpTypeFloat)
2101 return &SPIRV::vfIDRegClass;
2102 if (ElemOpcode == SPIRV::OpTypePointer)
2103 return &SPIRV::vpIDRegClass;
2104 return &SPIRV::viIDRegClass;
2105 }
2106 }
2107 return &SPIRV::iIDRegClass;
2108}
2109
2110inline unsigned getAS(SPIRVTypeInst SpvType) {
2111 return storageClassToAddressSpace(
2112 SC: static_cast<SPIRV::StorageClass::StorageClass>(
2113 SpvType->getOperand(i: 1).getImm()));
2114}
2115
2116LLT SPIRVGlobalRegistry::getRegType(SPIRVTypeInst SpvType) const {
2117 unsigned Opcode = SpvType ? SpvType->getOpcode() : 0;
2118 switch (Opcode) {
2119 case SPIRV::OpTypeInt:
2120 case SPIRV::OpTypeFloat:
2121 case SPIRV::OpTypeBool:
2122 return LLT::scalar(SizeInBits: getScalarOrVectorBitWidth(Type: SpvType));
2123 case SPIRV::OpTypePointer:
2124 return LLT::pointer(AddressSpace: getAS(SpvType), SizeInBits: getPointerSize());
2125 case SPIRV::OpTypeVector: {
2126 SPIRVTypeInst ElemType = getScalarOrVectorComponentType(Type: SpvType);
2127 LLT ET;
2128 switch (ElemType ? ElemType->getOpcode() : 0) {
2129 case SPIRV::OpTypePointer:
2130 ET = LLT::pointer(AddressSpace: getAS(SpvType: ElemType), SizeInBits: getPointerSize());
2131 break;
2132 case SPIRV::OpTypeInt:
2133 case SPIRV::OpTypeFloat:
2134 case SPIRV::OpTypeBool:
2135 ET = LLT::scalar(SizeInBits: getScalarOrVectorBitWidth(Type: ElemType));
2136 break;
2137 default:
2138 ET = LLT::scalar(SizeInBits: 64);
2139 }
2140 return LLT::fixed_vector(NumElements: getScalarOrVectorComponentCount(Type: SpvType), ScalarTy: ET);
2141 }
2142 }
2143 return LLT::scalar(SizeInBits: 64);
2144}
2145
2146// Aliasing list MD contains several scope MD nodes whithin it. Each scope MD
2147// has a selfreference and an extra MD node for aliasing domain and also it
2148// can contain an optional string operand. Domain MD contains a self-reference
2149// with an optional string operand. Here we unfold the list, creating SPIR-V
2150// aliasing instructions.
2151// TODO: add support for an optional string operand.
2152MachineInstr *SPIRVGlobalRegistry::getOrAddMemAliasingINTELInst(
2153 MachineIRBuilder &MIRBuilder, const MDNode *AliasingListMD) {
2154 if (AliasingListMD->getNumOperands() == 0)
2155 return nullptr;
2156 if (auto L = AliasInstMDMap.find(Val: AliasingListMD); L != AliasInstMDMap.end())
2157 return L->second;
2158
2159 SmallVector<MachineInstr *> ScopeList;
2160 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
2161 for (const MDOperand &MDListOp : AliasingListMD->operands()) {
2162 if (MDNode *ScopeMD = dyn_cast<MDNode>(Val: MDListOp)) {
2163 if (ScopeMD->getNumOperands() < 2)
2164 return nullptr;
2165 MDNode *DomainMD = dyn_cast<MDNode>(Val: ScopeMD->getOperand(I: 1));
2166 if (!DomainMD)
2167 return nullptr;
2168 auto *Domain = [&] {
2169 auto D = AliasInstMDMap.find(Val: DomainMD);
2170 if (D != AliasInstMDMap.end())
2171 return D->second;
2172 const Register Ret = MRI->createVirtualRegister(RegClass: &SPIRV::IDRegClass);
2173 auto MIB =
2174 MIRBuilder.buildInstr(Opcode: SPIRV::OpAliasDomainDeclINTEL).addDef(RegNo: Ret);
2175 return MIB.getInstr();
2176 }();
2177 AliasInstMDMap.insert(KV: std::make_pair(x&: DomainMD, y&: Domain));
2178 auto *Scope = [&] {
2179 auto S = AliasInstMDMap.find(Val: ScopeMD);
2180 if (S != AliasInstMDMap.end())
2181 return S->second;
2182 const Register Ret = MRI->createVirtualRegister(RegClass: &SPIRV::IDRegClass);
2183 auto MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpAliasScopeDeclINTEL)
2184 .addDef(RegNo: Ret)
2185 .addUse(RegNo: Domain->getOperand(i: 0).getReg());
2186 return MIB.getInstr();
2187 }();
2188 AliasInstMDMap.insert(KV: std::make_pair(x&: ScopeMD, y&: Scope));
2189 ScopeList.push_back(Elt: Scope);
2190 }
2191 }
2192
2193 const Register Ret = MRI->createVirtualRegister(RegClass: &SPIRV::IDRegClass);
2194 auto MIB =
2195 MIRBuilder.buildInstr(Opcode: SPIRV::OpAliasScopeListDeclINTEL).addDef(RegNo: Ret);
2196 for (auto *Scope : ScopeList)
2197 MIB.addUse(RegNo: Scope->getOperand(i: 0).getReg());
2198 auto List = MIB.getInstr();
2199 AliasInstMDMap.insert(KV: std::make_pair(x&: AliasingListMD, y&: List));
2200 return List;
2201}
2202
2203void SPIRVGlobalRegistry::buildMemAliasingOpDecorate(
2204 Register Reg, MachineIRBuilder &MIRBuilder, uint32_t Dec,
2205 const MDNode *AliasingListMD) {
2206 MachineInstr *AliasList =
2207 getOrAddMemAliasingINTELInst(MIRBuilder, AliasingListMD);
2208 if (!AliasList)
2209 return;
2210 MIRBuilder.buildInstr(Opcode: SPIRV::OpDecorateId)
2211 .addUse(RegNo: Reg)
2212 .addImm(Val: Dec)
2213 .addUse(RegNo: AliasList->getOperand(i: 0).getReg());
2214}
2215void SPIRVGlobalRegistry::replaceAllUsesWith(Value *Old, Value *New,
2216 bool DeleteOld) {
2217 Old->replaceAllUsesWith(V: New);
2218 updateIfExistDeducedElementType(OldVal: Old, NewVal: New, DeleteOld);
2219 updateIfExistAssignPtrTypeInstr(OldVal: Old, NewVal: New, DeleteOld);
2220}
2221
2222void SPIRVGlobalRegistry::buildAssignType(IRBuilder<> &B, Type *Ty,
2223 Value *Arg) {
2224 Value *OfType = getNormalizedPoisonValue(Ty);
2225 CallInst *AssignCI = nullptr;
2226 if (Arg->getType()->isAggregateType() && Ty->isAggregateType() &&
2227 allowEmitFakeUse(Arg)) {
2228 LLVMContext &Ctx = Arg->getContext();
2229 SmallVector<Metadata *, 2> ArgMDs{
2230 MDNode::get(Context&: Ctx, MDs: ValueAsMetadata::getConstant(C: OfType)),
2231 MDString::get(Context&: Ctx, Str: Arg->getName())};
2232 B.CreateIntrinsic(ID: Intrinsic::spv_value_md,
2233 Args: {MetadataAsValue::get(Context&: Ctx, MD: MDTuple::get(Context&: Ctx, MDs: ArgMDs))});
2234 AssignCI = B.CreateIntrinsicWithoutFolding(ID: Intrinsic::fake_use, Args: {Arg});
2235 } else {
2236 AssignCI = buildIntrWithMD(IntrID: Intrinsic::spv_assign_type, Types: {Arg->getType()},
2237 Arg: OfType, Arg2: Arg, Imms: {}, B);
2238 }
2239 addAssignPtrTypeInstr(Val: Arg, AssignPtrTyCI: AssignCI);
2240}
2241
2242void SPIRVGlobalRegistry::buildAssignPtr(IRBuilder<> &B, Type *ElemTy,
2243 Value *Arg) {
2244 Value *OfType = PoisonValue::get(T: ElemTy);
2245 CallInst *AssignPtrTyCI = findAssignPtrTypeInstr(Val: Arg);
2246 Function *CurrF =
2247 B.GetInsertBlock() ? B.GetInsertBlock()->getParent() : nullptr;
2248 if (AssignPtrTyCI == nullptr ||
2249 AssignPtrTyCI->getParent()->getParent() != CurrF) {
2250 AssignPtrTyCI = buildIntrWithMD(
2251 IntrID: Intrinsic::spv_assign_ptr_type, Types: {Arg->getType()}, Arg: OfType, Arg2: Arg,
2252 Imms: {B.getInt32(C: getPointerAddressSpace(T: Arg->getType()))}, B);
2253 addDeducedElementType(Val: AssignPtrTyCI, Ty: ElemTy);
2254 addDeducedElementType(Val: Arg, Ty: ElemTy);
2255 addAssignPtrTypeInstr(Val: Arg, AssignPtrTyCI);
2256 } else {
2257 updateAssignType(AssignCI: AssignPtrTyCI, Arg, OfType);
2258 }
2259}
2260
2261void SPIRVGlobalRegistry::updateAssignType(CallInst *AssignCI, Value *Arg,
2262 Value *OfType) {
2263 AssignCI->setArgOperand(i: 1, v: buildMD(Arg: OfType));
2264 if (cast<IntrinsicInst>(Val: AssignCI)->getIntrinsicID() !=
2265 Intrinsic::spv_assign_ptr_type)
2266 return;
2267
2268 // update association with the pointee type
2269 Type *ElemTy = OfType->getType();
2270 addDeducedElementType(Val: AssignCI, Ty: ElemTy);
2271 addDeducedElementType(Val: Arg, Ty: ElemTy);
2272}
2273
2274void SPIRVGlobalRegistry::addStructOffsetDecorations(
2275 Register Reg, StructType *Ty, MachineIRBuilder &MIRBuilder) {
2276 ArrayRef<TypeSize> Offsets = DL.getStructLayout(Ty)->getMemberOffsets();
2277 for (uint32_t I = 0; I < Ty->getNumElements(); ++I) {
2278 buildOpMemberDecorate(Reg, MIRBuilder, Dec: SPIRV::Decoration::Offset, Member: I,
2279 DecArgs: {static_cast<uint32_t>(Offsets[I])});
2280 }
2281}
2282
2283void SPIRVGlobalRegistry::addArrayStrideDecorations(
2284 Register Reg, Type *ElementType, MachineIRBuilder &MIRBuilder) {
2285 uint32_t SizeInBytes = DL.getTypeSizeInBits(Ty: ElementType) / 8;
2286 buildOpDecorate(Reg, MIRBuilder, Dec: SPIRV::Decoration::ArrayStride,
2287 DecArgs: {SizeInBytes});
2288}
2289
2290bool SPIRVGlobalRegistry::hasBlockDecoration(SPIRVTypeInst Type) const {
2291 Register Def = getSPIRVTypeID(SpirvType: Type);
2292 for (const MachineInstr &Use :
2293 Type->getMF()->getRegInfo().use_instructions(Reg: Def)) {
2294 if (Use.getOpcode() != SPIRV::OpDecorate)
2295 continue;
2296
2297 if (Use.getOperand(i: 1).getImm() == SPIRV::Decoration::Block)
2298 return true;
2299 }
2300 return false;
2301}
2302