1//===-- SPIRVGlobalRegistry.cpp - SPIR-V Global Registry --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the implementation of the SPIRVGlobalRegistry class,
10// which is used to maintain rich type information required for SPIR-V even
11// after lowering from LLVM IR to GMIR. It can convert an llvm::Type into
12// an OpTypeXXX instruction, and map it to a virtual register. Also it builds
13// and supports consistency of constants and global variables.
14//
15//===----------------------------------------------------------------------===//
16
17#include "SPIRVGlobalRegistry.h"
18#include "SPIRV.h"
19#include "SPIRVBuiltins.h"
20#include "SPIRVSubtarget.h"
21#include "SPIRVUtils.h"
22#include "llvm/ADT/APInt.h"
23#include "llvm/IR/Constants.h"
24#include "llvm/IR/DiagnosticInfo.h"
25#include "llvm/IR/Function.h"
26#include "llvm/IR/IntrinsicInst.h"
27#include "llvm/IR/Intrinsics.h"
28#include "llvm/IR/IntrinsicsSPIRV.h"
29#include "llvm/IR/Type.h"
30#include "llvm/Support/Casting.h"
31#include "llvm/Support/MathExtras.h"
32#include <cassert>
33#include <functional>
34
35using namespace llvm;
36
37static bool allowEmitFakeUse(const Value *Arg) {
38 if (isSpvIntrinsic(Arg))
39 return false;
40 if (isa<AtomicCmpXchgInst, InsertValueInst, UndefValue>(Val: Arg))
41 return false;
42 if (const auto *LI = dyn_cast<LoadInst>(Val: Arg))
43 if (LI->getType()->isAggregateType())
44 return false;
45 return true;
46}
47
48static unsigned typeToAddressSpace(const Type *Ty) {
49 if (auto PType = dyn_cast<TypedPointerType>(Val: Ty))
50 return PType->getAddressSpace();
51 if (auto PType = dyn_cast<PointerType>(Val: Ty))
52 return PType->getAddressSpace();
53 if (auto *ExtTy = dyn_cast<TargetExtType>(Val: Ty);
54 ExtTy && isTypedPointerWrapper(ExtTy))
55 return ExtTy->getIntParameter(i: 0);
56 reportFatalInternalError(reason: "Unable to convert LLVM type to SPIRVType");
57}
58
59static bool
60storageClassRequiresExplictLayout(SPIRV::StorageClass::StorageClass SC) {
61 switch (SC) {
62 case SPIRV::StorageClass::Uniform:
63 case SPIRV::StorageClass::PushConstant:
64 case SPIRV::StorageClass::StorageBuffer:
65 case SPIRV::StorageClass::PhysicalStorageBufferEXT:
66 return true;
67 case SPIRV::StorageClass::UniformConstant:
68 case SPIRV::StorageClass::Input:
69 case SPIRV::StorageClass::Output:
70 case SPIRV::StorageClass::Workgroup:
71 case SPIRV::StorageClass::CrossWorkgroup:
72 case SPIRV::StorageClass::Private:
73 case SPIRV::StorageClass::Function:
74 case SPIRV::StorageClass::Generic:
75 case SPIRV::StorageClass::AtomicCounter:
76 case SPIRV::StorageClass::Image:
77 case SPIRV::StorageClass::CallableDataNV:
78 case SPIRV::StorageClass::IncomingCallableDataNV:
79 case SPIRV::StorageClass::RayPayloadNV:
80 case SPIRV::StorageClass::HitAttributeNV:
81 case SPIRV::StorageClass::IncomingRayPayloadNV:
82 case SPIRV::StorageClass::ShaderRecordBufferNV:
83 case SPIRV::StorageClass::CodeSectionINTEL:
84 case SPIRV::StorageClass::DeviceOnlyINTEL:
85 case SPIRV::StorageClass::HostOnlyINTEL:
86 return false;
87 }
88 llvm_unreachable("Unknown SPIRV::StorageClass enum");
89}
90
91SPIRVGlobalRegistry::SPIRVGlobalRegistry(unsigned PointerSize)
92 : PointerSize(PointerSize), Bound(0), CurMF(nullptr) {}
93
94SPIRVTypeInst
95SPIRVGlobalRegistry::assignIntTypeToVReg(unsigned BitWidth, Register VReg,
96 MachineInstr &I,
97 const SPIRVInstrInfo &TII) {
98 SPIRVTypeInst SpirvType = getOrCreateSPIRVIntegerType(BitWidth, I, TII);
99 assignSPIRVTypeToVReg(Type: SpirvType, VReg, MF: *CurMF);
100 return SpirvType;
101}
102
103SPIRVTypeInst
104SPIRVGlobalRegistry::assignFloatTypeToVReg(unsigned BitWidth, Register VReg,
105 MachineInstr &I,
106 const SPIRVInstrInfo &TII) {
107 SPIRVTypeInst SpirvType = getOrCreateSPIRVFloatType(BitWidth, I, TII);
108 assignSPIRVTypeToVReg(Type: SpirvType, VReg, MF: *CurMF);
109 return SpirvType;
110}
111
112SPIRVTypeInst SPIRVGlobalRegistry::assignVectTypeToVReg(
113 SPIRVTypeInst BaseType, unsigned NumElements, Register VReg,
114 MachineInstr &I, const SPIRVInstrInfo &TII) {
115 SPIRVTypeInst SpirvType =
116 getOrCreateSPIRVVectorType(BaseType, NumElements, I, TII);
117 assignSPIRVTypeToVReg(Type: SpirvType, VReg, MF: *CurMF);
118 return SpirvType;
119}
120
121SPIRVTypeInst SPIRVGlobalRegistry::assignTypeToVReg(
122 const Type *Type, Register VReg, MachineIRBuilder &MIRBuilder,
123 SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR) {
124 SPIRVTypeInst SpirvType =
125 getOrCreateSPIRVType(Type, MIRBuilder, AQ: AccessQual, EmitIR);
126 assignSPIRVTypeToVReg(Type: SpirvType, VReg, MF: MIRBuilder.getMF());
127 return SpirvType;
128}
129
130void SPIRVGlobalRegistry::assignSPIRVTypeToVReg(SPIRVTypeInst SpirvType,
131 Register VReg,
132 const MachineFunction &MF) {
133 VRegToTypeMap[&MF][VReg] = SpirvType;
134}
135
136static Register createTypeVReg(MachineRegisterInfo &MRI) {
137 auto Res = MRI.createGenericVirtualRegister(Ty: LLT::scalar(SizeInBits: 64));
138 MRI.setRegClass(Reg: Res, RC: &SPIRV::TYPERegClass);
139 return Res;
140}
141
142inline Register createTypeVReg(MachineIRBuilder &MIRBuilder) {
143 return createTypeVReg(MRI&: MIRBuilder.getMF().getRegInfo());
144}
145
146SPIRVTypeInst SPIRVGlobalRegistry::getOpTypeBool(MachineIRBuilder &MIRBuilder) {
147 return createConstOrTypeAtFunctionEntry(
148 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
149 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeBool)
150 .addDef(RegNo: createTypeVReg(MIRBuilder));
151 });
152}
153
154unsigned SPIRVGlobalRegistry::adjustOpTypeIntWidth(unsigned Width) const {
155 const SPIRVSubtarget &ST = cast<SPIRVSubtarget>(Val: CurMF->getSubtarget());
156 if (ST.canUseExtension(
157 E: SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers) ||
158 (Width == 4 && ST.canUseExtension(E: SPIRV::Extension::SPV_INTEL_int4)))
159 return Width;
160 if (Width <= 8)
161 return 8;
162 else if (Width <= 16)
163 return 16;
164 else if (Width <= 32)
165 return 32;
166 else if (Width <= 64)
167 return 64;
168 else if (Width <= 128)
169 return 128;
170 reportFatalUsageError(reason: "Unsupported Integer width!");
171}
172
173SPIRVTypeInst SPIRVGlobalRegistry::getOpTypeInt(unsigned Width,
174 MachineIRBuilder &MIRBuilder,
175 bool IsSigned) {
176 Width = adjustOpTypeIntWidth(Width);
177 const SPIRVSubtarget &ST =
178 cast<SPIRVSubtarget>(Val: MIRBuilder.getMF().getSubtarget());
179 return createConstOrTypeAtFunctionEntry(MIRBuilder, Op: [&](MachineIRBuilder
180 &MIRBuilder) {
181 if (Width == 4 && ST.canUseExtension(E: SPIRV::Extension::SPV_INTEL_int4)) {
182 MIRBuilder.buildInstr(Opcode: SPIRV::OpExtension)
183 .addImm(Val: SPIRV::Extension::SPV_INTEL_int4);
184 MIRBuilder.buildInstr(Opcode: SPIRV::OpCapability)
185 .addImm(Val: SPIRV::Capability::Int4TypeINTEL);
186 } else if ((!isPowerOf2_32(Value: Width) || Width < 8) &&
187 ST.canUseExtension(
188 E: SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers)) {
189 MIRBuilder.buildInstr(Opcode: SPIRV::OpExtension)
190 .addImm(Val: SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers);
191 MIRBuilder.buildInstr(Opcode: SPIRV::OpCapability)
192 .addImm(Val: SPIRV::Capability::ArbitraryPrecisionIntegersALTERA);
193 }
194 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeInt)
195 .addDef(RegNo: createTypeVReg(MIRBuilder))
196 .addImm(Val: Width)
197 .addImm(Val: IsSigned ? 1 : 0);
198 });
199}
200
201SPIRVTypeInst
202SPIRVGlobalRegistry::getOpTypeFloat(uint32_t Width,
203 MachineIRBuilder &MIRBuilder) {
204 return createConstOrTypeAtFunctionEntry(MIRBuilder, Op: [&](MachineIRBuilder
205 &MIRBuilder) {
206 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeFloat)
207 .addDef(RegNo: createTypeVReg(MIRBuilder))
208 .addImm(Val: Width);
209 });
210}
211
212SPIRVTypeInst
213SPIRVGlobalRegistry::getOpTypeFloat(uint32_t Width,
214 MachineIRBuilder &MIRBuilder,
215 SPIRV::FPEncoding::FPEncoding FPEncode) {
216 return createConstOrTypeAtFunctionEntry(MIRBuilder, Op: [&](MachineIRBuilder
217 &MIRBuilder) {
218 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeFloat)
219 .addDef(RegNo: createTypeVReg(MIRBuilder))
220 .addImm(Val: Width)
221 .addImm(Val: FPEncode);
222 });
223}
224
225SPIRVTypeInst SPIRVGlobalRegistry::getOpTypeVoid(MachineIRBuilder &MIRBuilder) {
226 return createConstOrTypeAtFunctionEntry(
227 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
228 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeVoid)
229 .addDef(RegNo: createTypeVReg(MIRBuilder));
230 });
231}
232
233void SPIRVGlobalRegistry::invalidateMachineInstr(MachineInstr *MI) {
234 // Other maps that may hold MachineInstr*:
235 // - VRegToTypeMap: We cannot remove the definitions of `MI` from
236 // VRegToTypeMap because some calls to invalidateMachineInstr are replacing MI
237 // with another instruction defining the same register. We expect that if MI
238 // is a type instruction, and it is still referenced in VRegToTypeMap, then
239 // those registers are dead or the VRegToTypeMap is out-of-date. We do not
240 // expect passes to ask for the SPIR-V type of a dead register. If the
241 // VRegToTypeMap is out-of-date already, then there was an error before. We
242 // cannot add an assert to verify this because the VRegToTypeMap can be
243 // out-of-date.
244 // - FunctionToInstr & FunctionToInstrRev: At this point, we should not be
245 // deleting functions. No need to update.
246 // - AliasInstMDMap: Would require a linear search, and the Intel Alias
247 // instruction are not instructions instruction selection will be able to
248 // remove.
249
250 const SPIRVSubtarget &ST = MI->getMF()->getSubtarget<SPIRVSubtarget>();
251 [[maybe_unused]] const SPIRVInstrInfo *TII = ST.getInstrInfo();
252 assert(!TII->isAliasingInstr(*MI) &&
253 "Cannot invalidate aliasing instructions.");
254 assert(MI->getOpcode() != SPIRV::OpFunction &&
255 "Cannot invalidate OpFunction.");
256
257 if (MI->getOpcode() == SPIRV::OpFunctionCall) {
258 if (const auto *F = dyn_cast<Function>(Val: MI->getOperand(i: 2).getGlobal())) {
259 auto It = ForwardCalls.find(Val: F);
260 if (It != ForwardCalls.end()) {
261 It->second.erase(Ptr: MI);
262 if (It->second.empty())
263 ForwardCalls.erase(I: It);
264 }
265 }
266 }
267
268 const MachineFunction *MF = MI->getMF();
269 auto It = LastInsertedTypeMap.find(Val: MF);
270 if (It != LastInsertedTypeMap.end() && It->second == MI)
271 LastInsertedTypeMap.erase(Val: MF);
272 // remove from the duplicate tracker to avoid incorrect reuse
273 erase(MI);
274}
275
276const MachineInstr *SPIRVGlobalRegistry::createConstOrTypeAtFunctionEntry(
277 MachineIRBuilder &MIRBuilder,
278 std::function<MachineInstr *(MachineIRBuilder &)> Op) {
279 auto oldInsertPoint = MIRBuilder.getInsertPt();
280 MachineBasicBlock *OldMBB = &MIRBuilder.getMBB();
281 MachineBasicBlock *NewMBB = &*MIRBuilder.getMF().begin();
282
283 auto LastInsertedType = LastInsertedTypeMap.find(Val: CurMF);
284 if (LastInsertedType != LastInsertedTypeMap.end()) {
285 auto It = LastInsertedType->second->getIterator();
286 // It might happen that this instruction was removed from the first MBB,
287 // hence the Parent's check.
288 MachineBasicBlock::iterator InsertAt;
289 if (It->getParent() != NewMBB)
290 InsertAt = oldInsertPoint->getParent() == NewMBB
291 ? oldInsertPoint
292 : getInsertPtValidEnd(MBB: NewMBB);
293 else if (It->getNextNode())
294 InsertAt = It->getNextNode()->getIterator();
295 else
296 InsertAt = getInsertPtValidEnd(MBB: NewMBB);
297 MIRBuilder.setInsertPt(MBB&: *NewMBB, II: InsertAt);
298 } else {
299 MIRBuilder.setInsertPt(MBB&: *NewMBB, II: NewMBB->begin());
300 auto Result = LastInsertedTypeMap.try_emplace(Key: CurMF, Args: nullptr);
301 assert(Result.second);
302 LastInsertedType = Result.first;
303 }
304
305 MachineInstr *ConstOrType = Op(MIRBuilder);
306 // We expect all users of this function to insert definitions at the insertion
307 // point set above that is always the first MBB.
308 assert(ConstOrType->getParent() == NewMBB);
309 LastInsertedType->second = ConstOrType;
310 // Advance past any continued instructions so that the next type/constant
311 // is inserted after the full group, preserving required adjacency.
312 while (auto *Next = LastInsertedType->second->getNextNode()) {
313 unsigned Opc = Next->getOpcode();
314 if (Opc == SPIRV::OpTypeStructContinuedINTEL ||
315 Opc == SPIRV::OpConstantCompositeContinuedINTEL ||
316 Opc == SPIRV::OpSpecConstantCompositeContinuedINTEL ||
317 Opc == SPIRV::OpCompositeConstructContinuedINTEL)
318 LastInsertedType->second = Next;
319 else
320 break;
321 }
322
323 MIRBuilder.setInsertPt(MBB&: *OldMBB, II: oldInsertPoint);
324 return ConstOrType;
325}
326
327SPIRVTypeInst
328SPIRVGlobalRegistry::getOpTypeVector(uint32_t NumElems, SPIRVTypeInst ElemType,
329 MachineIRBuilder &MIRBuilder) {
330 auto EleOpc = ElemType->getOpcode();
331 assert(NumElems >= 2 && "SPIR-V OpTypeVector requires at least 2 components");
332
333 if (EleOpc == SPIRV::OpTypePointer) {
334 if (!cast<SPIRVSubtarget>(Val: MIRBuilder.getMF().getSubtarget())
335 .canUseExtension(
336 E: SPIRV::Extension::SPV_INTEL_masked_gather_scatter)) {
337 const Function &F = MIRBuilder.getMF().getFunction();
338 F.getContext().diagnose(DI: DiagnosticInfoUnsupported(
339 F,
340 "Vector of pointers requires SPV_INTEL_masked_gather_scatter "
341 "extension",
342 DebugLoc(), DS_Error));
343 }
344 } else {
345 assert((EleOpc == SPIRV::OpTypeInt || EleOpc == SPIRV::OpTypeFloat ||
346 EleOpc == SPIRV::OpTypeBool) &&
347 "Invalid vector element type");
348 }
349
350 return createConstOrTypeAtFunctionEntry(
351 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
352 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeVector)
353 .addDef(RegNo: createTypeVReg(MIRBuilder))
354 .addUse(RegNo: getSPIRVTypeID(SpirvType: ElemType))
355 .addImm(Val: NumElems);
356 });
357}
358
359Register SPIRVGlobalRegistry::getOrCreateConstFP(APFloat Val, MachineInstr &I,
360 SPIRVTypeInst SpvType,
361 const SPIRVInstrInfo &TII,
362 bool ZeroAsNull) {
363 LLVMContext &Ctx = CurMF->getFunction().getContext();
364 auto *const CF = ConstantFP::get(Context&: Ctx, V: Val);
365 const MachineInstr *MI = findMI(Obj: CF, MF: CurMF);
366 if (MI && (MI->getOpcode() == SPIRV::OpConstantNull ||
367 MI->getOpcode() == SPIRV::OpConstantF))
368 return MI->getOperand(i: 0).getReg();
369 return createConstFP(CF, I, SpvType, TII, ZeroAsNull);
370}
371
372Register SPIRVGlobalRegistry::createConstFP(const ConstantFP *CF,
373 MachineInstr &I,
374 SPIRVTypeInst SpvType,
375 const SPIRVInstrInfo &TII,
376 bool ZeroAsNull) {
377 unsigned BitWidth = getScalarOrVectorBitWidth(Type: SpvType);
378 LLT LLTy = LLT::scalar(SizeInBits: BitWidth);
379 Register Res = CurMF->getRegInfo().createGenericVirtualRegister(Ty: LLTy);
380 CurMF->getRegInfo().setRegClass(Reg: Res, RC: &SPIRV::fIDRegClass);
381 assignSPIRVTypeToVReg(SpirvType: SpvType, VReg: Res, MF: *CurMF);
382
383 MachineInstr *DepMI =
384 const_cast<MachineInstr *>(static_cast<const MachineInstr *>(SpvType));
385 MachineIRBuilder MIRBuilder(*DepMI->getParent(), DepMI->getIterator());
386 const MachineInstr *Const = createConstOrTypeAtFunctionEntry(
387 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
388 MachineInstrBuilder MIB;
389 // In OpenCL OpConstantNull - Scalar floating point: +0.0 (all bits 0)
390 if (CF->getValue().isPosZero() && ZeroAsNull) {
391 MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantNull)
392 .addDef(RegNo: Res)
393 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
394 } else {
395 MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantF)
396 .addDef(RegNo: Res)
397 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
398 addNumImm(Imm: APInt(BitWidth,
399 CF->getValueAPF().bitcastToAPInt().getZExtValue()),
400 MIB);
401 }
402 const auto &ST = CurMF->getSubtarget();
403 constrainSelectedInstRegOperands(I&: *MIB, TII: *ST.getInstrInfo(),
404 TRI: *ST.getRegisterInfo(),
405 RBI: *ST.getRegBankInfo());
406 return MIB;
407 });
408 add(V: CF, MI: Const);
409 return Res;
410}
411
412Register SPIRVGlobalRegistry::getOrCreateConstInt(uint64_t Val, MachineInstr &I,
413 SPIRVTypeInst SpvType,
414 const SPIRVInstrInfo &TII,
415 bool ZeroAsNull) {
416 return getOrCreateConstInt(Val: APInt(getScalarOrVectorBitWidth(Type: SpvType), Val), I,
417 SpvType, TII, ZeroAsNull);
418}
419
420Register SPIRVGlobalRegistry::getOrCreateConstInt(const APInt &Val,
421 MachineInstr &I,
422 SPIRVTypeInst SpvType,
423 const SPIRVInstrInfo &TII,
424 bool ZeroAsNull) {
425 auto *const CI = ConstantInt::get(
426 Context&: cast<IntegerType>(Val: getTypeForSPIRVType(Ty: SpvType))->getContext(), V: Val);
427 const MachineInstr *MI = findMI(Obj: CI, MF: CurMF);
428 if (MI && (MI->getOpcode() == SPIRV::OpConstantNull ||
429 MI->getOpcode() == SPIRV::OpConstantI))
430 return MI->getOperand(i: 0).getReg();
431 return createConstInt(CI, I, SpvType, TII, ZeroAsNull);
432}
433
434Register SPIRVGlobalRegistry::createConstInt(const ConstantInt *CI,
435 MachineInstr &I,
436 SPIRVTypeInst SpvType,
437 const SPIRVInstrInfo &TII,
438 bool ZeroAsNull) {
439 unsigned BitWidth = getScalarOrVectorBitWidth(Type: SpvType);
440 LLT LLTy = LLT::scalar(SizeInBits: BitWidth);
441 Register Res = CurMF->getRegInfo().createGenericVirtualRegister(Ty: LLTy);
442 CurMF->getRegInfo().setRegClass(Reg: Res, RC: &SPIRV::iIDRegClass);
443 assignIntTypeToVReg(BitWidth, VReg: Res, I, TII);
444
445 MachineInstr *DepMI =
446 const_cast<MachineInstr *>(static_cast<const MachineInstr *>(SpvType));
447 MachineIRBuilder MIRBuilder(*DepMI->getParent(), DepMI->getIterator());
448 const MachineInstr *Const = createConstOrTypeAtFunctionEntry(
449 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
450 MachineInstrBuilder MIB;
451 if (BitWidth == 1) {
452 MIB = MIRBuilder
453 .buildInstr(Opcode: CI->isZero() ? SPIRV::OpConstantFalse
454 : SPIRV::OpConstantTrue)
455 .addDef(RegNo: Res)
456 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
457 } else if (!CI->isZero() || !ZeroAsNull) {
458 MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantI)
459 .addDef(RegNo: Res)
460 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
461 addNumImm(Imm: CI->getValue(), MIB);
462 } else {
463 MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantNull)
464 .addDef(RegNo: Res)
465 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
466 }
467 const auto &ST = CurMF->getSubtarget();
468 constrainSelectedInstRegOperands(I&: *MIB, TII: *ST.getInstrInfo(),
469 TRI: *ST.getRegisterInfo(),
470 RBI: *ST.getRegBankInfo());
471 return MIB;
472 });
473 add(V: CI, MI: Const);
474 return Res;
475}
476
477Register SPIRVGlobalRegistry::buildConstantInt(uint64_t Val,
478 MachineIRBuilder &MIRBuilder,
479 SPIRVTypeInst SpvType,
480 bool EmitIR, bool ZeroAsNull) {
481 assert(SpvType);
482 auto &MF = MIRBuilder.getMF();
483 const IntegerType *Ty = cast<IntegerType>(Val: getTypeForSPIRVType(Ty: SpvType));
484 // TODO: Avoid implicit trunc?
485 // See https://github.com/llvm/llvm-project/issues/112510.
486 auto *const CI = ConstantInt::get(Ty: const_cast<IntegerType *>(Ty), V: Val,
487 /*IsSigned=*/false, /*ImplicitTrunc=*/true);
488 Register Res = find(V: CI, MF: &MF);
489 if (Res.isValid())
490 return Res;
491
492 unsigned BitWidth = getScalarOrVectorBitWidth(Type: SpvType);
493 LLT LLTy = LLT::scalar(SizeInBits: BitWidth);
494 MachineRegisterInfo &MRI = MF.getRegInfo();
495 Res = MRI.createGenericVirtualRegister(Ty: LLTy);
496 MRI.setRegClass(Reg: Res, RC: &SPIRV::iIDRegClass);
497 assignTypeToVReg(Type: Ty, VReg: Res, MIRBuilder, AccessQual: SPIRV::AccessQualifier::ReadWrite,
498 EmitIR);
499
500 const MachineInstr *Const = createConstOrTypeAtFunctionEntry(
501 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
502 if (EmitIR)
503 return MIRBuilder.buildConstant(Res, Val: *CI);
504 Register SpvTypeReg = getSPIRVTypeID(SpirvType: SpvType);
505 MachineInstrBuilder MIB;
506 if (Val || !ZeroAsNull) {
507 MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantI)
508 .addDef(RegNo: Res)
509 .addUse(RegNo: SpvTypeReg);
510 addNumImm(Imm: APInt(BitWidth, Val), MIB);
511 } else {
512 MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantNull)
513 .addDef(RegNo: Res)
514 .addUse(RegNo: SpvTypeReg);
515 }
516 const auto &Subtarget = CurMF->getSubtarget();
517 constrainSelectedInstRegOperands(I&: *MIB, TII: *Subtarget.getInstrInfo(),
518 TRI: *Subtarget.getRegisterInfo(),
519 RBI: *Subtarget.getRegBankInfo());
520 return MIB;
521 });
522 add(V: CI, MI: Const);
523 return Res;
524}
525
526Register SPIRVGlobalRegistry::buildConstantFP(APFloat Val,
527 MachineIRBuilder &MIRBuilder,
528 SPIRVTypeInst SpvType) {
529 auto &MF = MIRBuilder.getMF();
530 LLVMContext &Ctx = MF.getFunction().getContext();
531 if (!SpvType)
532 SpvType = getOrCreateSPIRVType(Type: Type::getFloatTy(C&: Ctx), MIRBuilder,
533 AQ: SPIRV::AccessQualifier::ReadWrite, EmitIR: true);
534 auto *const CF = ConstantFP::get(Context&: Ctx, V: Val);
535 Register Res = find(V: CF, MF: &MF);
536 if (Res.isValid())
537 return Res;
538
539 LLT LLTy = LLT::scalar(SizeInBits: getScalarOrVectorBitWidth(Type: SpvType));
540 Res = MF.getRegInfo().createGenericVirtualRegister(Ty: LLTy);
541 MF.getRegInfo().setRegClass(Reg: Res, RC: &SPIRV::fIDRegClass);
542 assignSPIRVTypeToVReg(SpirvType: SpvType, VReg: Res, MF);
543
544 const MachineInstr *Const = createConstOrTypeAtFunctionEntry(
545 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
546 MachineInstrBuilder MIB;
547 MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantF)
548 .addDef(RegNo: Res)
549 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
550 addNumImm(Imm: CF->getValueAPF().bitcastToAPInt(), MIB);
551 return MIB;
552 });
553 add(V: CF, MI: Const);
554 return Res;
555}
556
557Register SPIRVGlobalRegistry::getOrCreateBaseRegister(
558 Constant *Val, MachineInstr &I, SPIRVTypeInst SpvType,
559 const SPIRVInstrInfo &TII, unsigned BitWidth, bool ZeroAsNull) {
560 SPIRVTypeInst Type = SpvType;
561 if (SpvType->getOpcode() == SPIRV::OpTypeVector ||
562 SpvType->getOpcode() == SPIRV::OpTypeArray) {
563 auto EleTypeReg = SpvType->getOperand(i: 1).getReg();
564 Type = getSPIRVTypeForVReg(VReg: EleTypeReg);
565 }
566 if (Type->getOpcode() == SPIRV::OpTypeFloat) {
567 SPIRVTypeInst SpvBaseType = getOrCreateSPIRVFloatType(BitWidth, I, TII);
568 return getOrCreateConstFP(Val: cast<ConstantFP>(Val)->getValue(), I, SpvType: SpvBaseType,
569 TII, ZeroAsNull);
570 }
571 assert(Type->getOpcode() == SPIRV::OpTypeInt);
572 SPIRVTypeInst SpvBaseType = getOrCreateSPIRVIntegerType(BitWidth, I, TII);
573 return getOrCreateConstInt(Val: Val->getUniqueInteger(), I, SpvType: SpvBaseType, TII,
574 ZeroAsNull);
575}
576
577Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(
578 Constant *Val, MachineInstr &I, SPIRVTypeInst SpvType,
579 const SPIRVInstrInfo &TII, Constant *CA, unsigned BitWidth,
580 unsigned ElemCnt, bool ZeroAsNull) {
581 if (Register R = find(V: CA, MF: CurMF); R.isValid())
582 return R;
583
584 bool IsNull = Val->isNullValue() && ZeroAsNull;
585 Register ElemReg;
586 if (!IsNull)
587 ElemReg =
588 getOrCreateBaseRegister(Val, I, SpvType, TII, BitWidth, ZeroAsNull);
589
590 LLT LLTy = LLT::scalar(SizeInBits: 64);
591 Register Res = CurMF->getRegInfo().createGenericVirtualRegister(Ty: LLTy);
592 CurMF->getRegInfo().setRegClass(Reg: Res, RC: getRegClass(SpvType));
593 assignSPIRVTypeToVReg(SpirvType: SpvType, VReg: Res, MF: *CurMF);
594
595 MachineInstr *DepMI =
596 const_cast<MachineInstr *>(static_cast<const MachineInstr *>(SpvType));
597 MachineIRBuilder MIRBuilder(*DepMI->getParent(), DepMI->getIterator());
598 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
599 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
600 MachineInstrBuilder MIB;
601 if (!IsNull) {
602 MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantComposite)
603 .addDef(RegNo: Res)
604 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
605 for (unsigned i = 0; i < ElemCnt; ++i)
606 MIB.addUse(RegNo: ElemReg);
607 } else {
608 MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantNull)
609 .addDef(RegNo: Res)
610 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
611 }
612 const auto &Subtarget = CurMF->getSubtarget();
613 constrainSelectedInstRegOperands(I&: *MIB, TII: *Subtarget.getInstrInfo(),
614 TRI: *Subtarget.getRegisterInfo(),
615 RBI: *Subtarget.getRegBankInfo());
616 return MIB;
617 });
618 add(V: CA, MI: NewMI);
619 return Res;
620}
621
622Register SPIRVGlobalRegistry::getOrCreateConstVector(uint64_t Val,
623 MachineInstr &I,
624 SPIRVTypeInst SpvType,
625 const SPIRVInstrInfo &TII,
626 bool ZeroAsNull) {
627 return getOrCreateConstVector(Val: APInt(getScalarOrVectorBitWidth(Type: SpvType), Val),
628 I, SpvType, TII, ZeroAsNull);
629}
630
631Register SPIRVGlobalRegistry::getOrCreateConstVector(const APInt &Val,
632 MachineInstr &I,
633 SPIRVTypeInst SpvType,
634 const SPIRVInstrInfo &TII,
635 bool ZeroAsNull) {
636 const Type *LLVMTy = getTypeForSPIRVType(Ty: SpvType);
637 assert(LLVMTy->isVectorTy() &&
638 "Expected vector type for constant vector creation");
639 const FixedVectorType *LLVMVecTy = cast<FixedVectorType>(Val: LLVMTy);
640 Type *LLVMBaseTy = LLVMVecTy->getElementType();
641 assert(LLVMBaseTy->isIntegerTy() &&
642 "Expected integer element type for APInt constant vector");
643 auto *ConstVal = cast<ConstantInt>(Val: ConstantInt::get(Ty: LLVMBaseTy, V: Val));
644 auto *ConstVec =
645 ConstantVector::getSplat(EC: LLVMVecTy->getElementCount(), Elt: ConstVal);
646 unsigned BW = getScalarOrVectorBitWidth(Type: SpvType);
647 return getOrCreateCompositeOrNull(Val: ConstVal, I, SpvType, TII, CA: ConstVec, BitWidth: BW,
648 ElemCnt: SpvType->getOperand(i: 2).getImm(),
649 ZeroAsNull);
650}
651
652Register SPIRVGlobalRegistry::getOrCreateConstVector(APFloat Val,
653 MachineInstr &I,
654 SPIRVTypeInst SpvType,
655 const SPIRVInstrInfo &TII,
656 bool ZeroAsNull) {
657 const Type *LLVMTy = getTypeForSPIRVType(Ty: SpvType);
658 assert(LLVMTy->isVectorTy());
659 const FixedVectorType *LLVMVecTy = cast<FixedVectorType>(Val: LLVMTy);
660 Type *LLVMBaseTy = LLVMVecTy->getElementType();
661 assert(LLVMBaseTy->isFloatingPointTy());
662 auto *ConstVal = ConstantFP::get(Ty: LLVMBaseTy, V: Val);
663 auto *ConstVec =
664 ConstantVector::getSplat(EC: LLVMVecTy->getElementCount(), Elt: ConstVal);
665 unsigned BW = getScalarOrVectorBitWidth(Type: SpvType);
666 return getOrCreateCompositeOrNull(Val: ConstVal, I, SpvType, TII, CA: ConstVec, BitWidth: BW,
667 ElemCnt: SpvType->getOperand(i: 2).getImm(),
668 ZeroAsNull);
669}
670
671Register SPIRVGlobalRegistry::getOrCreateConstIntArray(
672 uint64_t Val, size_t Num, MachineInstr &I, SPIRVTypeInst SpvType,
673 const SPIRVInstrInfo &TII) {
674 const Type *LLVMTy = getTypeForSPIRVType(Ty: SpvType);
675 assert(LLVMTy->isArrayTy());
676 const ArrayType *LLVMArrTy = cast<ArrayType>(Val: LLVMTy);
677 Type *LLVMBaseTy = LLVMArrTy->getElementType();
678 Constant *CI = ConstantInt::get(Ty: LLVMBaseTy, V: Val);
679 SPIRVTypeInst SpvBaseTy =
680 getSPIRVTypeForVReg(VReg: SpvType->getOperand(i: 1).getReg());
681 unsigned BW = getScalarOrVectorBitWidth(Type: SpvBaseTy);
682 // The following is reasonably unique key that is better that [Val]. The naive
683 // alternative would be something along the lines of:
684 // SmallVector<Constant *> NumCI(Num, CI);
685 // Constant *UniqueKey =
686 // ConstantArray::get(const_cast<ArrayType*>(LLVMArrTy), NumCI);
687 // that would be a truly unique but dangerous key, because it could lead to
688 // the creation of constants of arbitrary length (that is, the parameter of
689 // memset) which were missing in the original module.
690 Type *I64Ty = Type::getInt64Ty(C&: LLVMBaseTy->getContext());
691 Constant *UniqueKey = ConstantStruct::getAnon(
692 V: {PoisonValue::get(T: const_cast<ArrayType *>(LLVMArrTy)),
693 ConstantInt::get(Ty: LLVMBaseTy, V: Val), ConstantInt::get(Ty: I64Ty, V: Num)});
694 return getOrCreateCompositeOrNull(Val: CI, I, SpvType, TII, CA: UniqueKey, BitWidth: BW,
695 ElemCnt: LLVMArrTy->getNumElements());
696}
697
698Register SPIRVGlobalRegistry::getOrCreateIntCompositeOrNull(
699 uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVTypeInst SpvType,
700 bool EmitIR, Constant *CA, unsigned BitWidth, unsigned ElemCnt) {
701 if (Register R = find(V: CA, MF: CurMF); R.isValid())
702 return R;
703
704 Register ElemReg;
705 if (Val || EmitIR) {
706 SPIRVTypeInst SpvBaseType =
707 getOrCreateSPIRVIntegerType(BitWidth, MIRBuilder);
708 ElemReg = buildConstantInt(Val, MIRBuilder, SpvType: SpvBaseType, EmitIR);
709 }
710 LLT LLTy = EmitIR ? LLT::fixed_vector(NumElements: ElemCnt, ScalarSizeInBits: BitWidth) : LLT::scalar(SizeInBits: 64);
711 Register Res = CurMF->getRegInfo().createGenericVirtualRegister(Ty: LLTy);
712 CurMF->getRegInfo().setRegClass(Reg: Res, RC: &SPIRV::iIDRegClass);
713 assignSPIRVTypeToVReg(SpirvType: SpvType, VReg: Res, MF: *CurMF);
714
715 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
716 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
717 if (EmitIR)
718 return MIRBuilder.buildSplatBuildVector(Res, Src: ElemReg);
719
720 if (Val) {
721 auto MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantComposite)
722 .addDef(RegNo: Res)
723 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
724 for (unsigned i = 0; i < ElemCnt; ++i)
725 MIB.addUse(RegNo: ElemReg);
726 return MIB;
727 }
728
729 return MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantNull)
730 .addDef(RegNo: Res)
731 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
732 });
733 add(V: CA, MI: NewMI);
734 return Res;
735}
736
737Register SPIRVGlobalRegistry::getOrCreateConsIntVector(
738 uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVTypeInst SpvType,
739 bool EmitIR) {
740 const Type *LLVMTy = getTypeForSPIRVType(Ty: SpvType);
741 assert(LLVMTy->isVectorTy());
742 const FixedVectorType *LLVMVecTy = cast<FixedVectorType>(Val: LLVMTy);
743 Type *LLVMBaseTy = LLVMVecTy->getElementType();
744 const auto ConstInt = ConstantInt::get(Ty: LLVMBaseTy, V: Val);
745 auto ConstVec =
746 ConstantVector::getSplat(EC: LLVMVecTy->getElementCount(), Elt: ConstInt);
747 unsigned BW = getScalarOrVectorBitWidth(Type: SpvType);
748 return getOrCreateIntCompositeOrNull(Val, MIRBuilder, SpvType, EmitIR,
749 CA: ConstVec, BitWidth: BW,
750 ElemCnt: SpvType->getOperand(i: 2).getImm());
751}
752
753Register
754SPIRVGlobalRegistry::getOrCreateConstNullPtr(MachineIRBuilder &MIRBuilder,
755 SPIRVTypeInst SpvType) {
756 const Type *Ty = getTypeForSPIRVType(Ty: SpvType);
757 unsigned AddressSpace = typeToAddressSpace(Ty);
758 Type *ElemTy = ::getPointeeType(Ty);
759 assert(ElemTy);
760 const Constant *CP = ConstantTargetNone::get(
761 T: dyn_cast<TargetExtType>(Val: getTypedPointerWrapper(ElemTy, AS: AddressSpace)));
762 Register Res = find(V: CP, MF: CurMF);
763 if (Res.isValid())
764 return Res;
765
766 LLT LLTy = LLT::pointer(AddressSpace, SizeInBits: PointerSize);
767 Res = CurMF->getRegInfo().createGenericVirtualRegister(Ty: LLTy);
768 CurMF->getRegInfo().setRegClass(Reg: Res, RC: &SPIRV::pIDRegClass);
769 assignSPIRVTypeToVReg(SpirvType: SpvType, VReg: Res, MF: *CurMF);
770
771 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
772 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
773 return MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantNull)
774 .addDef(RegNo: Res)
775 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
776 });
777 add(V: CP, MI: NewMI);
778 return Res;
779}
780
781Register
782SPIRVGlobalRegistry::buildConstantSampler(Register ResReg, unsigned AddrMode,
783 unsigned Param, unsigned FilerMode,
784 MachineIRBuilder &MIRBuilder) {
785 auto Sampler =
786 ResReg.isValid()
787 ? ResReg
788 : MIRBuilder.getMRI()->createVirtualRegister(RegClass: &SPIRV::iIDRegClass);
789 SPIRVTypeInst TypeSampler = getOrCreateOpTypeSampler(MIRBuilder);
790 Register TypeSamplerReg = getSPIRVTypeID(SpirvType: TypeSampler);
791 // We cannot use createOpType() logic here, because of the
792 // GlobalISel/IRTranslator.cpp check for a tail call that expects that
793 // MIRBuilder.getInsertPt() has a previous instruction. If this constant is
794 // inserted as a result of "__translate_sampler_initializer()" this would
795 // break this IRTranslator assumption.
796 MIRBuilder.buildInstr(Opcode: SPIRV::OpConstantSampler)
797 .addDef(RegNo: Sampler)
798 .addUse(RegNo: TypeSamplerReg)
799 .addImm(Val: AddrMode)
800 .addImm(Val: Param)
801 .addImm(Val: FilerMode);
802 return Sampler;
803}
804
805Register SPIRVGlobalRegistry::buildGlobalVariable(
806 Register ResVReg, SPIRVTypeInst BaseType, StringRef Name,
807 const GlobalValue *GV, SPIRV::StorageClass::StorageClass Storage,
808 const MachineInstr *Init, bool IsConst,
809 const std::optional<SPIRV::LinkageType::LinkageType> &LinkageType,
810 MachineIRBuilder &MIRBuilder, bool IsInstSelector) {
811 const GlobalVariable *GVar = nullptr;
812 if (GV) {
813 GVar = cast<const GlobalVariable>(Val: GV);
814 } else {
815 // If GV is not passed explicitly, use the name to find or construct
816 // the global variable.
817 Module *M = MIRBuilder.getMF().getFunction().getParent();
818 GVar = M->getGlobalVariable(Name);
819 if (GVar == nullptr) {
820 const Type *Ty = getTypeForSPIRVType(Ty: BaseType); // TODO: check type.
821 // Module takes ownership of the global var.
822 GVar = new GlobalVariable(*M, const_cast<Type *>(Ty), false,
823 GlobalValue::ExternalLinkage, nullptr,
824 Twine(Name));
825 }
826 GV = GVar;
827 }
828
829 const MachineFunction *MF = &MIRBuilder.getMF();
830 Register Reg = find(V: GVar, MF);
831 if (Reg.isValid()) {
832 if (Reg != ResVReg)
833 MIRBuilder.buildCopy(Res: ResVReg, Op: Reg);
834 return ResVReg;
835 }
836
837 // Emit the OpVariable into the entry block to ensure the def dominates
838 // all uses across all MBBs.
839 MachineBasicBlock &EntryBB = MIRBuilder.getMF().front();
840 MachineIRBuilder GVBuilder(MIRBuilder.getState());
841 if (&GVBuilder.getMBB() != &EntryBB)
842 GVBuilder.setInsertPt(MBB&: EntryBB, II: EntryBB.getFirstTerminator());
843
844 auto MIB = GVBuilder.buildInstr(Opcode: SPIRV::OpVariable)
845 .addDef(RegNo: ResVReg)
846 .addUse(RegNo: getSPIRVTypeID(SpirvType: BaseType))
847 .addImm(Val: static_cast<uint32_t>(Storage));
848 if (Init)
849 MIB.addUse(RegNo: Init->getOperand(i: 0).getReg());
850 // ISel may introduce a new register on this step, so we need to add it to
851 // DT and correct its type avoiding fails on the next stage.
852 if (IsInstSelector) {
853 const auto &Subtarget = CurMF->getSubtarget();
854 constrainSelectedInstRegOperands(I&: *MIB, TII: *Subtarget.getInstrInfo(),
855 TRI: *Subtarget.getRegisterInfo(),
856 RBI: *Subtarget.getRegBankInfo());
857 }
858 add(V: GVar, MI: MIB);
859
860 Reg = MIB->getOperand(i: 0).getReg();
861 addGlobalObject(V: GVar, MF, R: Reg);
862
863 // Set to Reg the same type as ResVReg has.
864 auto MRI = MIRBuilder.getMRI();
865 if (Reg != ResVReg) {
866 LLT RegLLTy =
867 LLT::pointer(AddressSpace: MRI->getType(Reg: ResVReg).getAddressSpace(), SizeInBits: getPointerSize());
868 MRI->setType(VReg: Reg, Ty: RegLLTy);
869 assignSPIRVTypeToVReg(SpirvType: BaseType, VReg: Reg, MF: MIRBuilder.getMF());
870 } else {
871 // Our knowledge about the type may be updated.
872 // If that's the case, we need to update a type
873 // associated with the register.
874 SPIRVTypeInst DefType = getSPIRVTypeForVReg(VReg: ResVReg);
875 if (!DefType || DefType != SPIRVTypeInst(BaseType))
876 assignSPIRVTypeToVReg(SpirvType: BaseType, VReg: Reg, MF: MIRBuilder.getMF());
877 }
878
879 // If it's a global variable with name, output OpName for it.
880 if (GVar && GVar->hasName())
881 buildOpName(Target: Reg, Name: GVar->getName(), MIRBuilder);
882
883 // Output decorations for the GV.
884 // TODO: maybe move to GenerateDecorations pass.
885 const SPIRVSubtarget &ST =
886 cast<SPIRVSubtarget>(Val: MIRBuilder.getMF().getSubtarget());
887 if (IsConst && !ST.isShader())
888 buildOpDecorate(Reg, MIRBuilder, Dec: SPIRV::Decoration::Constant, DecArgs: {});
889
890 if (GVar && GVar->getAlign().valueOrOne().value() != 1 && !ST.isShader()) {
891 unsigned Alignment = (unsigned)GVar->getAlign().valueOrOne().value();
892 buildOpDecorate(Reg, MIRBuilder, Dec: SPIRV::Decoration::Alignment, DecArgs: {Alignment});
893 }
894
895 if (LinkageType)
896 buildOpDecorate(Reg, MIRBuilder, Dec: SPIRV::Decoration::LinkageAttributes,
897 DecArgs: {static_cast<uint32_t>(*LinkageType)}, StrImm: Name);
898
899 SPIRV::BuiltIn::BuiltIn BuiltInId;
900 if (getSpirvBuiltInIdByName(Name, BI&: BuiltInId))
901 buildOpDecorate(Reg, MIRBuilder, Dec: SPIRV::Decoration::BuiltIn,
902 DecArgs: {static_cast<uint32_t>(BuiltInId)});
903
904 // If it's a global variable with "spirv.Decorations" metadata node
905 // recognize it as a SPIR-V friendly LLVM IR and parse "spirv.Decorations"
906 // arguments.
907 MDNode *GVarMD = nullptr;
908 if (GVar && (GVarMD = GVar->getMetadata(Kind: "spirv.Decorations")) != nullptr)
909 buildOpSpirvDecorations(Reg, MIRBuilder, GVarMD, ST);
910
911 return Reg;
912}
913
914// Returns a name based on the Type. Notes that this does not look at
915// decorations, and will return the same string for two types that are the same
916// except for decorations.
917Register SPIRVGlobalRegistry::getOrCreateGlobalVariableWithBinding(
918 SPIRVTypeInst VarType, uint32_t Set, uint32_t Binding, StringRef Name,
919 MachineIRBuilder &MIRBuilder) {
920 Register VarReg =
921 MIRBuilder.getMRI()->createVirtualRegister(RegClass: &SPIRV::iIDRegClass);
922
923 buildGlobalVariable(ResVReg: VarReg, BaseType: VarType, Name, GV: nullptr,
924 Storage: getPointerStorageClass(Type: VarType), Init: nullptr, IsConst: false,
925 LinkageType: std::nullopt, MIRBuilder, IsInstSelector: false);
926
927 buildOpDecorate(Reg: VarReg, MIRBuilder, Dec: SPIRV::Decoration::DescriptorSet, DecArgs: {Set});
928 buildOpDecorate(Reg: VarReg, MIRBuilder, Dec: SPIRV::Decoration::Binding, DecArgs: {Binding});
929 return VarReg;
930}
931
932// TODO: Double check the calls to getOpTypeArray to make sure that `ElemType`
933// is explicitly laid out when required.
934SPIRVTypeInst SPIRVGlobalRegistry::getOpTypeArray(uint32_t NumElems,
935 SPIRVTypeInst ElemType,
936 MachineIRBuilder &MIRBuilder,
937 bool ExplicitLayoutRequired,
938 bool EmitIR) {
939 assert((ElemType->getOpcode() != SPIRV::OpTypeVoid) &&
940 "Invalid array element type");
941 SPIRVTypeInst SpvTypeInt32 = getOrCreateSPIRVIntegerType(BitWidth: 32, MIRBuilder);
942 SPIRVTypeInst ArrayType = nullptr;
943 const SPIRVSubtarget &ST =
944 cast<SPIRVSubtarget>(Val: MIRBuilder.getMF().getSubtarget());
945 if (NumElems != 0) {
946 Register NumElementsVReg =
947 buildConstantInt(Val: NumElems, MIRBuilder, SpvType: SpvTypeInt32, EmitIR);
948 ArrayType = createConstOrTypeAtFunctionEntry(
949 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
950 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeArray)
951 .addDef(RegNo: createTypeVReg(MIRBuilder))
952 .addUse(RegNo: getSPIRVTypeID(SpirvType: ElemType))
953 .addUse(RegNo: NumElementsVReg);
954 });
955 } else if (ST.getTargetTriple().getVendor() == Triple::VendorType::AMD) {
956 // We set the array size to the token UINT64_MAX value, which is generally
957 // illegal (the maximum legal size is 61-bits) for the foreseeable future.
958 SPIRVTypeInst SpvTypeInt64 = getOrCreateSPIRVIntegerType(BitWidth: 64, MIRBuilder);
959 Register NumElementsVReg =
960 buildConstantInt(UINT64_MAX, MIRBuilder, SpvType: SpvTypeInt64, EmitIR);
961 ArrayType = createConstOrTypeAtFunctionEntry(
962 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
963 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeArray)
964 .addDef(RegNo: createTypeVReg(MIRBuilder))
965 .addUse(RegNo: getSPIRVTypeID(SpirvType: ElemType))
966 .addUse(RegNo: NumElementsVReg);
967 });
968 } else {
969 if (!ST.isShader()) {
970 llvm::reportFatalUsageError(
971 reason: "Runtime arrays are not allowed in non-shader "
972 "SPIR-V modules");
973 return nullptr;
974 }
975 ArrayType = createConstOrTypeAtFunctionEntry(
976 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
977 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeRuntimeArray)
978 .addDef(RegNo: createTypeVReg(MIRBuilder))
979 .addUse(RegNo: getSPIRVTypeID(SpirvType: ElemType));
980 });
981 }
982
983 if (ExplicitLayoutRequired && !isResourceType(Type: ElemType)) {
984 Type *ET = const_cast<Type *>(getTypeForSPIRVType(Ty: ElemType));
985 addArrayStrideDecorations(Reg: ArrayType->defs().begin()->getReg(), ElementType: ET,
986 MIRBuilder);
987 }
988
989 return ArrayType;
990}
991
992SPIRVTypeInst
993SPIRVGlobalRegistry::getOpTypeOpaque(const StructType *Ty,
994 MachineIRBuilder &MIRBuilder) {
995 assert(Ty->hasName());
996 const StringRef Name = Ty->hasName() ? Ty->getName() : "";
997 Register ResVReg = createTypeVReg(MIRBuilder);
998 return createConstOrTypeAtFunctionEntry(
999 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1000 auto MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeOpaque).addDef(RegNo: ResVReg);
1001 addStringImm(Str: Name, MIB);
1002 buildOpName(Target: ResVReg, Name, MIRBuilder);
1003 return MIB;
1004 });
1005}
1006
1007SPIRVTypeInst SPIRVGlobalRegistry::getOpTypeStruct(
1008 const StructType *Ty, MachineIRBuilder &MIRBuilder,
1009 SPIRV::AccessQualifier::AccessQualifier AccQual,
1010 StructOffsetDecorator Decorator, bool EmitIR) {
1011 Type *OriginalElementType = nullptr;
1012 uint64_t TotalSize = 0;
1013 if (matchPeeledArrayPattern(Ty, OriginalElementType, TotalSize)) {
1014 SPIRVTypeInst ElementSPIRVType = findSPIRVType(
1015 Ty: OriginalElementType, MIRBuilder, accessQual: AccQual,
1016 /* ExplicitLayoutRequired= */ Decorator != nullptr, EmitIR);
1017 return getOpTypeArray(NumElems: TotalSize, ElemType: ElementSPIRVType, MIRBuilder,
1018 /*ExplicitLayoutRequired=*/Decorator != nullptr,
1019 EmitIR);
1020 }
1021
1022 const SPIRVSubtarget &ST =
1023 cast<SPIRVSubtarget>(Val: MIRBuilder.getMF().getSubtarget());
1024 SmallVector<Register, 4> FieldTypes;
1025 constexpr unsigned MaxWordCount = UINT16_MAX;
1026 const size_t NumElements = Ty->getNumElements();
1027
1028 size_t MaxNumElements = MaxWordCount - 2;
1029 size_t SPIRVStructNumElements = NumElements;
1030 if (NumElements > MaxNumElements) {
1031 // Do adjustments for continued instructions.
1032 SPIRVStructNumElements = MaxNumElements;
1033 MaxNumElements = MaxWordCount - 1;
1034 }
1035
1036 for (const auto &Elem : Ty->elements()) {
1037 SPIRVTypeInst ElemTy = findSPIRVType(
1038 Ty: toTypedPointer(Ty: Elem), MIRBuilder, accessQual: AccQual,
1039 /* ExplicitLayoutRequired= */ Decorator != nullptr, EmitIR);
1040 assert(ElemTy && ElemTy->getOpcode() != SPIRV::OpTypeVoid &&
1041 "Invalid struct element type");
1042 FieldTypes.push_back(Elt: getSPIRVTypeID(SpirvType: ElemTy));
1043 }
1044 Register ResVReg = createTypeVReg(MIRBuilder);
1045 if (Ty->hasName())
1046 buildOpName(Target: ResVReg, Name: Ty->getName(), MIRBuilder);
1047 if (Ty->isPacked() && !ST.isShader())
1048 buildOpDecorate(Reg: ResVReg, MIRBuilder, Dec: SPIRV::Decoration::CPacked, DecArgs: {});
1049
1050 SPIRVTypeInst SPVType = createConstOrTypeAtFunctionEntry(
1051 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1052 auto MIBStruct =
1053 MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeStruct).addDef(RegNo: ResVReg);
1054 for (size_t I = 0; I < SPIRVStructNumElements; ++I)
1055 MIBStruct.addUse(RegNo: FieldTypes[I]);
1056 for (size_t I = SPIRVStructNumElements; I < NumElements;
1057 I += MaxNumElements) {
1058 auto MIBCont =
1059 MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeStructContinuedINTEL);
1060 for (size_t J = I; J < std::min(a: I + MaxNumElements, b: NumElements); ++J)
1061 MIBCont.addUse(RegNo: FieldTypes[J]);
1062 }
1063 return MIBStruct;
1064 });
1065
1066 if (Decorator)
1067 Decorator(SPVType->defs().begin()->getReg());
1068
1069 return SPVType;
1070}
1071
1072SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateSpecialType(
1073 const Type *Ty, MachineIRBuilder &MIRBuilder,
1074 SPIRV::AccessQualifier::AccessQualifier AccQual) {
1075 assert(isSpecialOpaqueType(Ty) && "Not a special opaque builtin type");
1076 return SPIRV::lowerBuiltinType(Type: Ty, AccessQual: AccQual, MIRBuilder, GR: this);
1077}
1078
1079SPIRVTypeInst SPIRVGlobalRegistry::getOpTypePointer(
1080 SPIRV::StorageClass::StorageClass SC, SPIRVTypeInst ElemType,
1081 MachineIRBuilder &MIRBuilder, Register Reg) {
1082 if (!Reg.isValid())
1083 Reg = createTypeVReg(MIRBuilder);
1084
1085 return createConstOrTypeAtFunctionEntry(MIRBuilder, Op: [&](MachineIRBuilder
1086 &MIRBuilder) {
1087 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypePointer)
1088 .addDef(RegNo: Reg)
1089 .addImm(Val: static_cast<uint32_t>(SC))
1090 .addUse(RegNo: getSPIRVTypeID(SpirvType: ElemType));
1091 });
1092}
1093
1094SPIRVTypeInst SPIRVGlobalRegistry::getOpTypeForwardPointer(
1095 SPIRV::StorageClass::StorageClass SC, MachineIRBuilder &MIRBuilder) {
1096 return createConstOrTypeAtFunctionEntry(MIRBuilder, Op: [&](MachineIRBuilder
1097 &MIRBuilder) {
1098 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeForwardPointer)
1099 .addUse(RegNo: createTypeVReg(MIRBuilder))
1100 .addImm(Val: static_cast<uint32_t>(SC));
1101 });
1102}
1103
1104SPIRVTypeInst SPIRVGlobalRegistry::getOpTypeFunction(
1105 const FunctionType *Ty, SPIRVTypeInst RetType,
1106 const SmallVectorImpl<SPIRVTypeInst> &ArgTypes,
1107 MachineIRBuilder &MIRBuilder) {
1108 const SPIRVSubtarget *ST =
1109 static_cast<const SPIRVSubtarget *>(&MIRBuilder.getMF().getSubtarget());
1110 if (Ty->isVarArg() && ST->isShader()) {
1111 Function &Fn = MIRBuilder.getMF().getFunction();
1112 Ty->getContext().diagnose(DI: DiagnosticInfoUnsupported(
1113 Fn, "SPIR-V shaders do not support variadic functions",
1114 MIRBuilder.getDebugLoc()));
1115 }
1116 return createConstOrTypeAtFunctionEntry(MIRBuilder, Op: [&](MachineIRBuilder
1117 &MIRBuilder) {
1118 auto MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeFunction)
1119 .addDef(RegNo: createTypeVReg(MIRBuilder))
1120 .addUse(RegNo: getSPIRVTypeID(SpirvType: RetType));
1121 for (auto &ArgType : ArgTypes)
1122 MIB.addUse(RegNo: getSPIRVTypeID(SpirvType: ArgType));
1123 return MIB;
1124 });
1125}
1126
1127SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateOpTypeFunctionWithArgs(
1128 const Type *Ty, SPIRVTypeInst RetType,
1129 const SmallVectorImpl<SPIRVTypeInst> &ArgTypes,
1130 MachineIRBuilder &MIRBuilder) {
1131 if (const MachineInstr *MI = findMI(T: Ty, RequiresExplicitLayout: false, MF: &MIRBuilder.getMF()))
1132 return MI;
1133 const MachineInstr *NewMI =
1134 getOpTypeFunction(Ty: cast<FunctionType>(Val: Ty), RetType, ArgTypes, MIRBuilder);
1135 add(T: Ty, RequiresExplicitLayout: false, MI: NewMI);
1136 return finishCreatingSPIRVType(LLVMTy: Ty, SpirvType: NewMI);
1137}
1138
1139SPIRVTypeInst SPIRVGlobalRegistry::findSPIRVType(
1140 const Type *Ty, MachineIRBuilder &MIRBuilder,
1141 SPIRV::AccessQualifier::AccessQualifier AccQual,
1142 bool ExplicitLayoutRequired, bool EmitIR) {
1143 // Treat <1 x T> as T.
1144 if (auto *FVT = dyn_cast<FixedVectorType>(Val: Ty);
1145 FVT && FVT->getNumElements() == 1)
1146 return findSPIRVType(Ty: FVT->getElementType(), MIRBuilder, AccQual,
1147 ExplicitLayoutRequired, EmitIR);
1148 Ty = adjustIntTypeByWidth(Ty);
1149 // TODO: findMI needs to know if a layout is required.
1150 if (const MachineInstr *MI =
1151 findMI(T: Ty, RequiresExplicitLayout: ExplicitLayoutRequired, MF: &MIRBuilder.getMF()))
1152 return MI;
1153 if (auto It = ForwardPointerTypes.find(Val: Ty); It != ForwardPointerTypes.end())
1154 return It->second;
1155 return restOfCreateSPIRVType(Type: Ty, MIRBuilder, AccessQual: AccQual, ExplicitLayoutRequired,
1156 EmitIR);
1157}
1158
1159Register SPIRVGlobalRegistry::getSPIRVTypeID(SPIRVTypeInst SpirvType) const {
1160 assert(SpirvType && "Attempting to get type id for nullptr type.");
1161 if (SpirvType->getOpcode() == SPIRV::OpTypeForwardPointer ||
1162 SpirvType->getOpcode() == SPIRV::OpTypeStructContinuedINTEL)
1163 return SpirvType->uses().begin()->getReg();
1164 return SpirvType->defs().begin()->getReg();
1165}
1166
1167// We need to use a new LLVM integer type if there is a mismatch between
1168// number of bits in LLVM and SPIRV integer types to let DuplicateTracker
1169// ensure uniqueness of a SPIRV type by the corresponding LLVM type. Without
1170// such an adjustment SPIRVGlobalRegistry::getOpTypeInt() could create the
1171// same "OpTypeInt 8" type for a series of LLVM integer types with number of
1172// bits less than 8. This would lead to duplicate type definitions
1173// eventually due to the method that DuplicateTracker utilizes to reason
1174// about uniqueness of type records.
1175const Type *SPIRVGlobalRegistry::adjustIntTypeByWidth(const Type *Ty) const {
1176 if (auto IType = dyn_cast<IntegerType>(Val: Ty)) {
1177 unsigned SrcBitWidth = IType->getBitWidth();
1178 if (SrcBitWidth > 1) {
1179 unsigned BitWidth = adjustOpTypeIntWidth(Width: SrcBitWidth);
1180 // Maybe change source LLVM type to keep DuplicateTracker consistent.
1181 if (SrcBitWidth != BitWidth)
1182 Ty = IntegerType::get(C&: Ty->getContext(), NumBits: BitWidth);
1183 }
1184 }
1185 return Ty;
1186}
1187
1188SPIRVTypeInst SPIRVGlobalRegistry::createSPIRVType(
1189 const Type *Ty, MachineIRBuilder &MIRBuilder,
1190 SPIRV::AccessQualifier::AccessQualifier AccQual,
1191 bool ExplicitLayoutRequired, bool EmitIR) {
1192 if (isSpecialOpaqueType(Ty))
1193 return getOrCreateSpecialType(Ty, MIRBuilder, AccQual);
1194
1195 if (const MachineInstr *MI =
1196 findMI(T: Ty, RequiresExplicitLayout: ExplicitLayoutRequired, MF: &MIRBuilder.getMF()))
1197 return MI;
1198
1199 if (auto IType = dyn_cast<IntegerType>(Val: Ty)) {
1200 const unsigned Width = IType->getBitWidth();
1201 return Width == 1 ? getOpTypeBool(MIRBuilder)
1202 : getOpTypeInt(Width, MIRBuilder, IsSigned: false);
1203 }
1204 if (Ty->isFloatingPointTy()) {
1205 if (Ty->isBFloatTy()) {
1206 return getOpTypeFloat(Width: Ty->getPrimitiveSizeInBits(), MIRBuilder,
1207 FPEncode: SPIRV::FPEncoding::BFloat16KHR);
1208 } else {
1209 return getOpTypeFloat(Width: Ty->getPrimitiveSizeInBits(), MIRBuilder);
1210 }
1211 }
1212 if (Ty->isVoidTy())
1213 return getOpTypeVoid(MIRBuilder);
1214 if (Ty->isVectorTy()) {
1215 SPIRVTypeInst El =
1216 findSPIRVType(Ty: cast<FixedVectorType>(Val: Ty)->getElementType(), MIRBuilder,
1217 AccQual, ExplicitLayoutRequired, EmitIR);
1218 return getOpTypeVector(NumElems: cast<FixedVectorType>(Val: Ty)->getNumElements(), ElemType: El,
1219 MIRBuilder);
1220 }
1221 if (Ty->isArrayTy()) {
1222 SPIRVTypeInst El = findSPIRVType(Ty: Ty->getArrayElementType(), MIRBuilder,
1223 AccQual, ExplicitLayoutRequired, EmitIR);
1224 return getOpTypeArray(NumElems: Ty->getArrayNumElements(), ElemType: El, MIRBuilder,
1225 ExplicitLayoutRequired, EmitIR);
1226 }
1227 if (auto SType = dyn_cast<StructType>(Val: Ty)) {
1228 if (SType->isOpaque())
1229 return getOpTypeOpaque(Ty: SType, MIRBuilder);
1230
1231 StructOffsetDecorator Decorator = nullptr;
1232 if (ExplicitLayoutRequired) {
1233 Decorator = [&MIRBuilder, SType, this](Register Reg) {
1234 addStructOffsetDecorations(Reg, Ty: const_cast<StructType *>(SType),
1235 MIRBuilder);
1236 };
1237 }
1238 return getOpTypeStruct(Ty: SType, MIRBuilder, AccQual, Decorator: std::move(Decorator),
1239 EmitIR);
1240 }
1241 if (auto FType = dyn_cast<FunctionType>(Val: Ty)) {
1242 SPIRVTypeInst RetTy =
1243 findSPIRVType(Ty: FType->getReturnType(), MIRBuilder, AccQual,
1244 ExplicitLayoutRequired, EmitIR);
1245 SmallVector<SPIRVTypeInst, 4> ParamTypes;
1246 for (const auto &ParamTy : FType->params())
1247 ParamTypes.push_back(Elt: findSPIRVType(Ty: ParamTy, MIRBuilder, AccQual,
1248 ExplicitLayoutRequired, EmitIR));
1249 return getOpTypeFunction(Ty: FType, RetType: RetTy, ArgTypes: ParamTypes, MIRBuilder);
1250 }
1251
1252 unsigned AddrSpace = typeToAddressSpace(Ty);
1253
1254 // Get access to information about available extensions
1255 const SPIRVSubtarget *ST =
1256 static_cast<const SPIRVSubtarget *>(&MIRBuilder.getMF().getSubtarget());
1257 auto SC = addressSpaceToStorageClass(AddrSpace, STI: *ST);
1258
1259 SPIRVTypeInst SpvElementType = nullptr;
1260 Type *ElemTy = ::getPointeeType(Ty);
1261 if (ElemTy && isa<FunctionType>(Val: ElemTy) &&
1262 !ST->canUseExtension(E: SPIRV::Extension::SPV_INTEL_function_pointers))
1263 ElemTy = nullptr;
1264 if (ElemTy)
1265 SpvElementType = getOrCreateSPIRVType(Type: ElemTy, MIRBuilder, AQ: AccQual, EmitIR);
1266 else
1267 SpvElementType = getOrCreateSPIRVIntegerType(BitWidth: 8, MIRBuilder);
1268
1269 if (!ElemTy) {
1270 ElemTy = Type::getInt8Ty(C&: MIRBuilder.getContext());
1271 }
1272
1273 // If we have forward pointer associated with this type, use its register
1274 // operand to create OpTypePointer.
1275 if (auto It = ForwardPointerTypes.find(Val: Ty); It != ForwardPointerTypes.end()) {
1276 Register Reg = getSPIRVTypeID(SpirvType: It->second);
1277 // TODO: what does getOpTypePointer do?
1278 return getOpTypePointer(SC, ElemType: SpvElementType, MIRBuilder, Reg);
1279 }
1280
1281 return getOrCreateSPIRVPointerType(BaseType: ElemTy, MIRBuilder, SC);
1282}
1283
1284SPIRVTypeInst SPIRVGlobalRegistry::restOfCreateSPIRVType(
1285 const Type *Ty, MachineIRBuilder &MIRBuilder,
1286 SPIRV::AccessQualifier::AccessQualifier AccessQual,
1287 bool ExplicitLayoutRequired, bool EmitIR) {
1288 // TODO: Could this create a problem if one requires an explicit layout, and
1289 // the next time it does not?
1290 if (TypesInProcessing.count(Ptr: Ty) && !isPointerTyOrWrapper(Ty))
1291 return nullptr;
1292 TypesInProcessing.insert(Ptr: Ty);
1293 SPIRVTypeInst SpirvType = createSPIRVType(Ty, MIRBuilder, AccQual: AccessQual,
1294 ExplicitLayoutRequired, EmitIR);
1295 TypesInProcessing.erase(Ptr: Ty);
1296 VRegToTypeMap[&MIRBuilder.getMF()][getSPIRVTypeID(SpirvType)] = SpirvType;
1297
1298 // TODO: We could end up with two SPIR-V types pointing to the same llvm type.
1299 // Is that a problem?
1300 SPIRVToLLVMType[SpirvType] = unifyPtrType(Ty);
1301
1302 if (SpirvType->getOpcode() == SPIRV::OpTypeForwardPointer ||
1303 findMI(T: Ty, RequiresExplicitLayout: false, MF: &MIRBuilder.getMF()) || isSpecialOpaqueType(Ty))
1304 return SpirvType;
1305
1306 if (auto *ExtTy = dyn_cast<TargetExtType>(Val: Ty);
1307 ExtTy && isTypedPointerWrapper(ExtTy))
1308 add(PointeeTy: ExtTy->getTypeParameter(i: 0), AddressSpace: ExtTy->getIntParameter(i: 0), MI: SpirvType);
1309 else if (!isPointerTy(T: Ty))
1310 add(T: Ty, RequiresExplicitLayout: ExplicitLayoutRequired, MI: SpirvType);
1311 else if (isTypedPointerTy(T: Ty))
1312 add(PointeeTy: cast<TypedPointerType>(Val: Ty)->getElementType(),
1313 AddressSpace: getPointerAddressSpace(T: Ty), MI: SpirvType);
1314 else
1315 add(PointeeTy: Type::getInt8Ty(C&: MIRBuilder.getMF().getFunction().getContext()),
1316 AddressSpace: getPointerAddressSpace(T: Ty), MI: SpirvType);
1317 return SpirvType;
1318}
1319
1320SPIRVTypeInst
1321SPIRVGlobalRegistry::getSPIRVTypeForVReg(Register VReg,
1322 const MachineFunction *MF) const {
1323 auto t = VRegToTypeMap.find(Val: MF ? MF : CurMF);
1324 if (t != VRegToTypeMap.end()) {
1325 auto tt = t->second.find(Val: VReg);
1326 if (tt != t->second.end())
1327 return tt->second;
1328 }
1329 return nullptr;
1330}
1331
1332SPIRVTypeInst SPIRVGlobalRegistry::getResultType(Register VReg,
1333 MachineFunction *MF) {
1334 if (!MF)
1335 MF = CurMF;
1336 MachineInstr *Instr = getVRegDef(MRI&: MF->getRegInfo(), Reg: VReg);
1337 return getSPIRVTypeForVReg(VReg: Instr->getOperand(i: 1).getReg(), MF);
1338}
1339
1340SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateSPIRVType(
1341 const Type *Ty, MachineIRBuilder &MIRBuilder,
1342 SPIRV::AccessQualifier::AccessQualifier AccessQual,
1343 bool ExplicitLayoutRequired, bool EmitIR) {
1344 // SPIR-V doesn't support single-element vectors. Treat <1 x T> as T.
1345 if (auto *FVT = dyn_cast<FixedVectorType>(Val: Ty);
1346 FVT && FVT->getNumElements() == 1)
1347 return getOrCreateSPIRVType(Ty: FVT->getElementType(), MIRBuilder, AccessQual,
1348 ExplicitLayoutRequired, EmitIR);
1349 const MachineFunction *MF = &MIRBuilder.getMF();
1350 Register Reg;
1351 if (auto *ExtTy = dyn_cast<TargetExtType>(Val: Ty);
1352 ExtTy && isTypedPointerWrapper(ExtTy))
1353 Reg = find(PointeeTy: ExtTy->getTypeParameter(i: 0), AddressSpace: ExtTy->getIntParameter(i: 0), MF);
1354 else if (!isPointerTy(T: Ty))
1355 Reg = find(T: Ty = adjustIntTypeByWidth(Ty), RequiresExplicitLayout: ExplicitLayoutRequired, MF);
1356 else if (isTypedPointerTy(T: Ty))
1357 Reg = find(PointeeTy: cast<TypedPointerType>(Val: Ty)->getElementType(),
1358 AddressSpace: getPointerAddressSpace(T: Ty), MF);
1359 else
1360 Reg = find(PointeeTy: Type::getInt8Ty(C&: MIRBuilder.getMF().getFunction().getContext()),
1361 AddressSpace: getPointerAddressSpace(T: Ty), MF);
1362 if (Reg.isValid() && !isSpecialOpaqueType(Ty))
1363 return getSPIRVTypeForVReg(VReg: Reg);
1364
1365 TypesInProcessing.clear();
1366 SPIRVTypeInst STy = restOfCreateSPIRVType(Ty, MIRBuilder, AccessQual,
1367 ExplicitLayoutRequired, EmitIR);
1368 // Create normal pointer types for the corresponding OpTypeForwardPointers.
1369 for (auto &CU : ForwardPointerTypes) {
1370 // Pointer type themselves do not require an explicit layout. The types
1371 // they pointer to might, but that is taken care of when creating the type.
1372 bool PtrNeedsLayout = false;
1373 const Type *Ty2 = CU.first;
1374 SPIRVTypeInst STy2 = CU.second;
1375 if ((Reg = find(T: Ty2, RequiresExplicitLayout: PtrNeedsLayout, MF)).isValid())
1376 STy2 = getSPIRVTypeForVReg(VReg: Reg);
1377 else
1378 STy2 = restOfCreateSPIRVType(Ty: Ty2, MIRBuilder, AccessQual, ExplicitLayoutRequired: PtrNeedsLayout,
1379 EmitIR);
1380 if (Ty == Ty2)
1381 STy = STy2;
1382 }
1383 ForwardPointerTypes.clear();
1384 return STy;
1385}
1386
1387bool SPIRVGlobalRegistry::isScalarOfType(Register VReg,
1388 unsigned TypeOpcode) const {
1389 SPIRVTypeInst Type = getSPIRVTypeForVReg(VReg);
1390 assert(Type && "isScalarOfType VReg has no type assigned");
1391 return Type->getOpcode() == TypeOpcode;
1392}
1393
1394bool SPIRVGlobalRegistry::isScalarOrVectorOfType(Register VReg,
1395 unsigned TypeOpcode) const {
1396 SPIRVTypeInst Type = getSPIRVTypeForVReg(VReg);
1397 assert(Type && "isScalarOrVectorOfType VReg has no type assigned");
1398 if (Type->getOpcode() == TypeOpcode)
1399 return true;
1400 if (Type->getOpcode() == SPIRV::OpTypeVector) {
1401 Register ScalarTypeVReg = Type->getOperand(i: 1).getReg();
1402 SPIRVTypeInst ScalarType = getSPIRVTypeForVReg(VReg: ScalarTypeVReg);
1403 return ScalarType->getOpcode() == TypeOpcode;
1404 }
1405 return false;
1406}
1407
1408bool SPIRVGlobalRegistry::isResourceType(SPIRVTypeInst Type) const {
1409 switch (Type->getOpcode()) {
1410 case SPIRV::OpTypeImage:
1411 case SPIRV::OpTypeSampler:
1412 case SPIRV::OpTypeSampledImage:
1413 return true;
1414 case SPIRV::OpTypeStruct:
1415 return hasBlockDecoration(Type);
1416 default:
1417 return false;
1418 }
1419 return false;
1420}
1421unsigned
1422SPIRVGlobalRegistry::getScalarOrVectorComponentCount(Register VReg) const {
1423 return getScalarOrVectorComponentCount(Type: getSPIRVTypeForVReg(VReg));
1424}
1425
1426unsigned
1427SPIRVGlobalRegistry::getScalarOrVectorComponentCount(SPIRVTypeInst Type) const {
1428 if (!Type)
1429 return 0;
1430 return Type->getOpcode() == SPIRV::OpTypeVector
1431 ? static_cast<unsigned>(Type->getOperand(i: 2).getImm())
1432 : 1;
1433}
1434
1435SPIRVTypeInst
1436SPIRVGlobalRegistry::getScalarOrVectorComponentType(SPIRVTypeInst Type) const {
1437 if (!Type)
1438 return nullptr;
1439 Register ScalarReg = Type->getOpcode() == SPIRV::OpTypeVector
1440 ? Type->getOperand(i: 1).getReg()
1441 : Type->getOperand(i: 0).getReg();
1442 SPIRVTypeInst ScalarType = getSPIRVTypeForVReg(VReg: ScalarReg);
1443 assert(isScalarOrVectorOfType(Type->getOperand(0).getReg(),
1444 ScalarType->getOpcode()));
1445 return ScalarType;
1446}
1447
1448unsigned
1449SPIRVGlobalRegistry::getScalarOrVectorBitWidth(SPIRVTypeInst Type) const {
1450 assert(Type && "Invalid Type pointer");
1451 if (Type->getOpcode() == SPIRV::OpTypeVector) {
1452 auto EleTypeReg = Type->getOperand(i: 1).getReg();
1453 Type = getSPIRVTypeForVReg(VReg: EleTypeReg);
1454 }
1455 if (Type->getOpcode() == SPIRV::OpTypeInt ||
1456 Type->getOpcode() == SPIRV::OpTypeFloat)
1457 return Type->getOperand(i: 1).getImm();
1458 if (Type->getOpcode() == SPIRV::OpTypeBool)
1459 return 1;
1460 llvm_unreachable("Attempting to get bit width of non-integer/float type.");
1461}
1462
1463unsigned SPIRVGlobalRegistry::getNumScalarOrVectorTotalBitWidth(
1464 SPIRVTypeInst Type) const {
1465 assert(Type && "Invalid Type pointer");
1466 unsigned NumElements = 1;
1467 if (Type->getOpcode() == SPIRV::OpTypeVector) {
1468 NumElements = static_cast<unsigned>(Type->getOperand(i: 2).getImm());
1469 Type = getSPIRVTypeForVReg(VReg: Type->getOperand(i: 1).getReg());
1470 }
1471 return Type->getOpcode() == SPIRV::OpTypeInt ||
1472 Type->getOpcode() == SPIRV::OpTypeFloat
1473 ? NumElements * Type->getOperand(i: 1).getImm()
1474 : 0;
1475}
1476
1477SPIRVTypeInst
1478SPIRVGlobalRegistry::retrieveScalarOrVectorIntType(SPIRVTypeInst Type) const {
1479 if (Type && Type->getOpcode() == SPIRV::OpTypeVector)
1480 Type = getSPIRVTypeForVReg(VReg: Type->getOperand(i: 1).getReg());
1481 return Type && Type->getOpcode() == SPIRV::OpTypeInt ? Type : nullptr;
1482}
1483
1484bool SPIRVGlobalRegistry::isScalarOrVectorSigned(SPIRVTypeInst Type) const {
1485 SPIRVTypeInst IntType = retrieveScalarOrVectorIntType(Type);
1486 return IntType && IntType->getOperand(i: 2).getImm() != 0;
1487}
1488
1489SPIRVTypeInst SPIRVGlobalRegistry::getPointeeType(SPIRVTypeInst PtrType) {
1490 return PtrType && PtrType->getOpcode() == SPIRV::OpTypePointer
1491 ? getSPIRVTypeForVReg(VReg: PtrType->getOperand(i: 2).getReg())
1492 : nullptr;
1493}
1494
1495unsigned SPIRVGlobalRegistry::getPointeeTypeOp(Register PtrReg) {
1496 SPIRVTypeInst ElemType = getPointeeType(PtrType: getSPIRVTypeForVReg(VReg: PtrReg));
1497 return ElemType ? ElemType->getOpcode() : 0;
1498}
1499
1500bool SPIRVGlobalRegistry::isBitcastCompatible(SPIRVTypeInst Type1,
1501 SPIRVTypeInst Type2) const {
1502 if (!Type1 || !Type2)
1503 return false;
1504 auto Op1 = Type1->getOpcode(), Op2 = Type2->getOpcode();
1505 // Ignore difference between <1.5 and >=1.5 protocol versions:
1506 // it's valid if either Result Type or Operand is a pointer, and the other
1507 // is a pointer, an integer scalar, or an integer vector.
1508 if (Op1 == SPIRV::OpTypePointer &&
1509 (Op2 == SPIRV::OpTypePointer || retrieveScalarOrVectorIntType(Type: Type2)))
1510 return true;
1511 if (Op2 == SPIRV::OpTypePointer &&
1512 (Op1 == SPIRV::OpTypePointer || retrieveScalarOrVectorIntType(Type: Type1)))
1513 return true;
1514 unsigned Bits1 = getNumScalarOrVectorTotalBitWidth(Type: Type1),
1515 Bits2 = getNumScalarOrVectorTotalBitWidth(Type: Type2);
1516 return Bits1 > 0 && Bits1 == Bits2;
1517}
1518
1519SPIRV::StorageClass::StorageClass
1520SPIRVGlobalRegistry::getPointerStorageClass(Register VReg) const {
1521 SPIRVTypeInst Type = getSPIRVTypeForVReg(VReg);
1522 assert(Type && Type->getOpcode() == SPIRV::OpTypePointer &&
1523 Type->getOperand(1).isImm() && "Pointer type is expected");
1524 return getPointerStorageClass(Type);
1525}
1526
1527SPIRV::StorageClass::StorageClass
1528SPIRVGlobalRegistry::getPointerStorageClass(SPIRVTypeInst Type) const {
1529 return static_cast<SPIRV::StorageClass::StorageClass>(
1530 Type->getOperand(i: 1).getImm());
1531}
1532
1533SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateVulkanBufferType(
1534 MachineIRBuilder &MIRBuilder, Type *ElemType,
1535 SPIRV::StorageClass::StorageClass SC, bool IsWritable, bool EmitIr) {
1536 auto Key = SPIRV::irhandle_vkbuffer(ElementType: ElemType, SC, IsWriteable: IsWritable);
1537 if (const MachineInstr *MI = findMI(Handle: Key, MF: &MIRBuilder.getMF()))
1538 return MI;
1539
1540 bool ExplicitLayoutRequired = storageClassRequiresExplictLayout(SC);
1541 // We need to get the SPIR-V type for the element here, so we can add the
1542 // decoration to it.
1543 auto *T = StructType::create(Elements: ElemType);
1544 SPIRVTypeInst BlockType =
1545 getOrCreateSPIRVType(Ty: T, MIRBuilder, AccessQual: SPIRV::AccessQualifier::None,
1546 ExplicitLayoutRequired, EmitIR: EmitIr);
1547
1548 buildOpDecorate(Reg: BlockType->defs().begin()->getReg(), MIRBuilder,
1549 Dec: SPIRV::Decoration::Block, DecArgs: {});
1550
1551 if (!IsWritable) {
1552 buildOpMemberDecorate(Reg: BlockType->defs().begin()->getReg(), MIRBuilder,
1553 Dec: SPIRV::Decoration::NonWritable, Member: 0, DecArgs: {});
1554 }
1555
1556 SPIRVTypeInst R =
1557 getOrCreateSPIRVPointerTypeInternal(BaseType: BlockType, MIRBuilder, SC);
1558 add(Handle: Key, MI: R);
1559 return R;
1560}
1561
1562SPIRVTypeInst
1563SPIRVGlobalRegistry::getOrCreatePaddingType(MachineIRBuilder &MIRBuilder) {
1564 auto Key = SPIRV::irhandle_padding();
1565 if (const MachineInstr *MI = findMI(Handle: Key, MF: &MIRBuilder.getMF()))
1566 return MI;
1567 auto *T = Type::getInt8Ty(C&: MIRBuilder.getContext());
1568 SPIRVTypeInst R = getOrCreateSPIRVIntegerType(BitWidth: 8, MIRBuilder);
1569 finishCreatingSPIRVType(LLVMTy: T, SpirvType: R);
1570 add(Handle: Key, MI: R);
1571 return R;
1572}
1573
1574SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateVulkanPushConstantType(
1575 MachineIRBuilder &MIRBuilder, Type *T) {
1576 const auto SC = SPIRV::StorageClass::PushConstant;
1577
1578 auto Key = SPIRV::irhandle_vkbuffer(ElementType: T, SC, /* IsWritable= */ IsWriteable: false);
1579 if (const MachineInstr *MI = findMI(Handle: Key, MF: &MIRBuilder.getMF()))
1580 return MI;
1581
1582 // We need to get the SPIR-V type for the element here, so we can add the
1583 // decoration to it.
1584 SPIRVTypeInst BlockType = getOrCreateSPIRVType(
1585 Ty: T, MIRBuilder, AccessQual: SPIRV::AccessQualifier::None,
1586 /* ExplicitLayoutRequired= */ true, /* EmitIr= */ EmitIR: false);
1587
1588 buildOpDecorate(Reg: BlockType->defs().begin()->getReg(), MIRBuilder,
1589 Dec: SPIRV::Decoration::Block, DecArgs: {});
1590 SPIRVTypeInst R = BlockType;
1591 add(Handle: Key, MI: R);
1592 return R;
1593}
1594
1595SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateLayoutType(
1596 MachineIRBuilder &MIRBuilder, const TargetExtType *T, bool EmitIr) {
1597 auto Key = SPIRV::handle(Ty: T);
1598 if (const MachineInstr *MI = findMI(Handle: Key, MF: &MIRBuilder.getMF()))
1599 return MI;
1600
1601 StructType *ST = cast<StructType>(Val: T->getTypeParameter(i: 0));
1602 ArrayRef<uint32_t> Offsets = T->int_params().slice(N: 1);
1603 assert(ST->getNumElements() == Offsets.size());
1604
1605 StructOffsetDecorator Decorator = [&MIRBuilder, &Offsets](Register Reg) {
1606 for (uint32_t I = 0; I < Offsets.size(); ++I) {
1607 buildOpMemberDecorate(Reg, MIRBuilder, Dec: SPIRV::Decoration::Offset, Member: I,
1608 DecArgs: {Offsets[I]});
1609 }
1610 };
1611
1612 // We need a new OpTypeStruct instruction because decorations will be
1613 // different from a struct with an explicit layout created from a different
1614 // entry point.
1615 SPIRVTypeInst SPIRVStructType =
1616 getOpTypeStruct(Ty: ST, MIRBuilder, AccQual: SPIRV::AccessQualifier::None,
1617 Decorator: std::move(Decorator), EmitIR: EmitIr);
1618 add(Handle: Key, MI: SPIRVStructType);
1619 return SPIRVStructType;
1620}
1621
1622SPIRVTypeInst SPIRVGlobalRegistry::getImageType(
1623 const TargetExtType *ExtensionType,
1624 const SPIRV::AccessQualifier::AccessQualifier Qualifier,
1625 MachineIRBuilder &MIRBuilder) {
1626 assert(ExtensionType->getNumTypeParameters() == 1 &&
1627 "SPIR-V image builtin type must have sampled type parameter!");
1628 const SPIRVTypeInst SampledType =
1629 getOrCreateSPIRVType(Type: ExtensionType->getTypeParameter(i: 0), MIRBuilder,
1630 AQ: SPIRV::AccessQualifier::ReadWrite, EmitIR: true);
1631 assert((ExtensionType->getNumIntParameters() == 7 ||
1632 ExtensionType->getNumIntParameters() == 6) &&
1633 "Invalid number of parameters for SPIR-V image builtin!");
1634
1635 SPIRV::AccessQualifier::AccessQualifier accessQualifier =
1636 SPIRV::AccessQualifier::None;
1637 if (ExtensionType->getNumIntParameters() == 7) {
1638 accessQualifier = Qualifier == SPIRV::AccessQualifier::WriteOnly
1639 ? SPIRV::AccessQualifier::WriteOnly
1640 : SPIRV::AccessQualifier::AccessQualifier(
1641 ExtensionType->getIntParameter(i: 6));
1642 }
1643
1644 // Create or get an existing type from GlobalRegistry.
1645 SPIRVTypeInst R = getOrCreateOpTypeImage(
1646 MIRBuilder, SampledType,
1647 Dim: SPIRV::Dim::Dim(ExtensionType->getIntParameter(i: 0)),
1648 Depth: ExtensionType->getIntParameter(i: 1), Arrayed: ExtensionType->getIntParameter(i: 2),
1649 Multisampled: ExtensionType->getIntParameter(i: 3), Sampled: ExtensionType->getIntParameter(i: 4),
1650 ImageFormat: SPIRV::ImageFormat::ImageFormat(ExtensionType->getIntParameter(i: 5)),
1651 AccQual: accessQualifier);
1652 SPIRVToLLVMType[R] = ExtensionType;
1653 return R;
1654}
1655
1656SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateOpTypeImage(
1657 MachineIRBuilder &MIRBuilder, SPIRVTypeInst SampledType,
1658 SPIRV::Dim::Dim Dim, uint32_t Depth, uint32_t Arrayed,
1659 uint32_t Multisampled, uint32_t Sampled,
1660 SPIRV::ImageFormat::ImageFormat ImageFormat,
1661 SPIRV::AccessQualifier::AccessQualifier AccessQual) {
1662 auto Key = SPIRV::irhandle_image(SampledTy: SPIRVToLLVMType.lookup(Val: SampledType), Dim,
1663 Depth, Arrayed, MS: Multisampled, Sampled,
1664 ImageFormat, AQ: AccessQual);
1665 if (const MachineInstr *MI = findMI(Handle: Key, MF: &MIRBuilder.getMF()))
1666 return MI;
1667 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
1668 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1669 auto MIB =
1670 MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeImage)
1671 .addDef(RegNo: createTypeVReg(MIRBuilder))
1672 .addUse(RegNo: getSPIRVTypeID(SpirvType: SampledType))
1673 .addImm(Val: Dim)
1674 .addImm(Val: Depth) // Depth (whether or not it is a Depth image).
1675 .addImm(Val: Arrayed) // Arrayed.
1676 .addImm(Val: Multisampled) // Multisampled (0 = only single-sample).
1677 .addImm(Val: Sampled) // Sampled (0 = usage known at runtime).
1678 .addImm(Val: ImageFormat);
1679 if (AccessQual != SPIRV::AccessQualifier::None)
1680 MIB.addImm(Val: AccessQual);
1681 return MIB;
1682 });
1683 add(Handle: Key, MI: NewMI);
1684 return NewMI;
1685}
1686
1687SPIRVTypeInst
1688SPIRVGlobalRegistry::getOrCreateOpTypeSampler(MachineIRBuilder &MIRBuilder) {
1689 auto Key = SPIRV::irhandle_sampler();
1690 const MachineFunction *MF = &MIRBuilder.getMF();
1691 if (const MachineInstr *MI = findMI(Handle: Key, MF))
1692 return MI;
1693 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
1694 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1695 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeSampler)
1696 .addDef(RegNo: createTypeVReg(MIRBuilder));
1697 });
1698 add(Handle: Key, MI: NewMI);
1699 return NewMI;
1700}
1701
1702SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateOpTypePipe(
1703 MachineIRBuilder &MIRBuilder,
1704 SPIRV::AccessQualifier::AccessQualifier AccessQual) {
1705 auto Key = SPIRV::irhandle_pipe(AQ: AccessQual);
1706 if (const MachineInstr *MI = findMI(Handle: Key, MF: &MIRBuilder.getMF()))
1707 return MI;
1708 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
1709 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1710 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypePipe)
1711 .addDef(RegNo: createTypeVReg(MIRBuilder))
1712 .addImm(Val: AccessQual);
1713 });
1714 add(Handle: Key, MI: NewMI);
1715 return NewMI;
1716}
1717
1718SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateOpTypeDeviceEvent(
1719 MachineIRBuilder &MIRBuilder) {
1720 auto Key = SPIRV::irhandle_event();
1721 if (const MachineInstr *MI = findMI(Handle: Key, MF: &MIRBuilder.getMF()))
1722 return MI;
1723 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
1724 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1725 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeDeviceEvent)
1726 .addDef(RegNo: createTypeVReg(MIRBuilder));
1727 });
1728 add(Handle: Key, MI: NewMI);
1729 return NewMI;
1730}
1731
1732SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateOpTypeSampledImage(
1733 SPIRVTypeInst ImageType, MachineIRBuilder &MIRBuilder) {
1734 auto Key = SPIRV::irhandle_sampled_image(
1735 SampledTy: SPIRVToLLVMType.lookup(Val: MIRBuilder.getMF().getRegInfo().getVRegDef(
1736 Reg: ImageType->getOperand(i: 1).getReg())),
1737 ImageTy: ImageType);
1738 if (const MachineInstr *MI = findMI(Handle: Key, MF: &MIRBuilder.getMF()))
1739 return MI;
1740 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
1741 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1742 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeSampledImage)
1743 .addDef(RegNo: createTypeVReg(MIRBuilder))
1744 .addUse(RegNo: getSPIRVTypeID(SpirvType: ImageType));
1745 });
1746 add(Handle: Key, MI: NewMI);
1747 return NewMI;
1748}
1749
1750SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateOpTypeCoopMatr(
1751 MachineIRBuilder &MIRBuilder, const TargetExtType *ExtensionType,
1752 SPIRVTypeInst ElemType, uint32_t Scope, uint32_t Rows, uint32_t Columns,
1753 uint32_t Use, bool EmitIR) {
1754 if (const MachineInstr *MI =
1755 findMI(T: ExtensionType, RequiresExplicitLayout: false, MF: &MIRBuilder.getMF()))
1756 return MI;
1757 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
1758 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1759 SPIRVTypeInst SpvTypeInt32 =
1760 getOrCreateSPIRVIntegerType(BitWidth: 32, MIRBuilder);
1761 const Type *ET = getTypeForSPIRVType(Ty: ElemType);
1762 if (ET->isIntegerTy() && ET->getIntegerBitWidth() == 4 &&
1763 cast<SPIRVSubtarget>(Val: MIRBuilder.getMF().getSubtarget())
1764 .canUseExtension(E: SPIRV::Extension::SPV_INTEL_int4)) {
1765 MIRBuilder.buildInstr(Opcode: SPIRV::OpCapability)
1766 .addImm(Val: SPIRV::Capability::Int4CooperativeMatrixINTEL);
1767 }
1768 return MIRBuilder.buildInstr(Opcode: SPIRV::OpTypeCooperativeMatrixKHR)
1769 .addDef(RegNo: createTypeVReg(MIRBuilder))
1770 .addUse(RegNo: getSPIRVTypeID(SpirvType: ElemType))
1771 .addUse(RegNo: buildConstantInt(Val: Scope, MIRBuilder, SpvType: SpvTypeInt32, EmitIR))
1772 .addUse(RegNo: buildConstantInt(Val: Rows, MIRBuilder, SpvType: SpvTypeInt32, EmitIR))
1773 .addUse(RegNo: buildConstantInt(Val: Columns, MIRBuilder, SpvType: SpvTypeInt32, EmitIR))
1774 .addUse(RegNo: buildConstantInt(Val: Use, MIRBuilder, SpvType: SpvTypeInt32, EmitIR));
1775 });
1776 add(T: ExtensionType, RequiresExplicitLayout: false, MI: NewMI);
1777 return NewMI;
1778}
1779
1780SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateOpTypeByOpcode(
1781 const Type *Ty, MachineIRBuilder &MIRBuilder, unsigned Opcode) {
1782 if (const MachineInstr *MI = findMI(T: Ty, RequiresExplicitLayout: false, MF: &MIRBuilder.getMF()))
1783 return MI;
1784 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
1785 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1786 return MIRBuilder.buildInstr(Opcode).addDef(RegNo: createTypeVReg(MIRBuilder));
1787 });
1788 add(T: Ty, RequiresExplicitLayout: false, MI: NewMI);
1789 return NewMI;
1790}
1791
1792SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateUnknownType(
1793 const Type *Ty, MachineIRBuilder &MIRBuilder, unsigned Opcode,
1794 const ArrayRef<MCOperand> Operands) {
1795 if (const MachineInstr *MI = findMI(T: Ty, RequiresExplicitLayout: false, MF: &MIRBuilder.getMF()))
1796 return MI;
1797 Register ResVReg = createTypeVReg(MIRBuilder);
1798 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
1799 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1800 MachineInstrBuilder MIB = MIRBuilder.buildInstr(Opcode: SPIRV::UNKNOWN_type)
1801 .addDef(RegNo: ResVReg)
1802 .addImm(Val: Opcode);
1803 for (MCOperand Operand : Operands) {
1804 if (Operand.isReg()) {
1805 MIB.addUse(RegNo: Operand.getReg());
1806 } else if (Operand.isImm()) {
1807 MIB.addImm(Val: Operand.getImm());
1808 }
1809 }
1810 return MIB;
1811 });
1812 add(T: Ty, RequiresExplicitLayout: false, MI: NewMI);
1813 return NewMI;
1814}
1815
1816// Returns nullptr if unable to recognize SPIRV type name
1817SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateSPIRVTypeByName(
1818 StringRef TypeStr, MachineIRBuilder &MIRBuilder, bool EmitIR,
1819 SPIRV::StorageClass::StorageClass SC,
1820 SPIRV::AccessQualifier::AccessQualifier AQ) {
1821 unsigned VecElts = 0;
1822 auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
1823
1824 // Parse strings representing either a SPIR-V or OpenCL builtin type.
1825 if (hasBuiltinTypePrefix(Name: TypeStr))
1826 return getOrCreateSPIRVType(Ty: SPIRV::parseBuiltinTypeNameToTargetExtType(
1827 TypeName: TypeStr.str(), Context&: MIRBuilder.getContext()),
1828 MIRBuilder, AccessQual: AQ, ExplicitLayoutRequired: false, EmitIR: true);
1829
1830 // Parse type name in either "typeN" or "type vector[N]" format, where
1831 // N is the number of elements of the vector.
1832 Type *Ty;
1833
1834 Ty = parseBasicTypeName(TypeName&: TypeStr, Ctx);
1835 if (!Ty)
1836 // Unable to recognize SPIRV type name
1837 return nullptr;
1838
1839 SPIRVTypeInst SpirvTy = getOrCreateSPIRVType(Ty, MIRBuilder, AccessQual: AQ, ExplicitLayoutRequired: false, EmitIR: true);
1840
1841 // Handle "type*" or "type* vector[N]".
1842 if (TypeStr.consume_front(Prefix: "*"))
1843 SpirvTy = getOrCreateSPIRVPointerType(BaseType: Ty, MIRBuilder, SC);
1844
1845 // Handle "typeN*" or "type vector[N]*".
1846 bool IsPtrToVec = TypeStr.consume_back(Suffix: "*");
1847
1848 if (TypeStr.consume_front(Prefix: " vector[")) {
1849 TypeStr = TypeStr.substr(Start: 0, N: TypeStr.find(C: ']'));
1850 }
1851 TypeStr.getAsInteger(Radix: 10, Result&: VecElts);
1852 if (VecElts > 0)
1853 SpirvTy = getOrCreateSPIRVVectorType(BaseType: SpirvTy, NumElements: VecElts, MIRBuilder, EmitIR);
1854
1855 if (IsPtrToVec)
1856 SpirvTy = getOrCreateSPIRVPointerType(BaseType: SpirvTy, MIRBuilder, SC);
1857
1858 return SpirvTy;
1859}
1860
1861SPIRVTypeInst
1862SPIRVGlobalRegistry::getOrCreateSPIRVIntegerType(unsigned BitWidth,
1863 MachineIRBuilder &MIRBuilder) {
1864 return getOrCreateSPIRVType(
1865 Ty: IntegerType::get(C&: MIRBuilder.getMF().getFunction().getContext(), NumBits: BitWidth),
1866 MIRBuilder, AccessQual: SPIRV::AccessQualifier::ReadWrite, ExplicitLayoutRequired: false, EmitIR: true);
1867}
1868
1869SPIRVTypeInst
1870SPIRVGlobalRegistry::finishCreatingSPIRVType(const Type *LLVMTy,
1871 SPIRVTypeInst SpirvType) {
1872 assert(CurMF == SpirvType->getMF());
1873 VRegToTypeMap[CurMF][getSPIRVTypeID(SpirvType)] = SpirvType;
1874 SPIRVToLLVMType[SpirvType] = unifyPtrType(Ty: LLVMTy);
1875 return SpirvType;
1876}
1877
1878SPIRVTypeInst
1879SPIRVGlobalRegistry::getOrCreateSPIRVType(unsigned BitWidth, MachineInstr &I,
1880 const SPIRVInstrInfo &TII,
1881 unsigned SPIRVOPcode, Type *Ty) {
1882 if (const MachineInstr *MI = findMI(T: Ty, RequiresExplicitLayout: false, MF: CurMF))
1883 return MI;
1884 MachineBasicBlock &DepMBB = I.getMF()->front();
1885 MachineIRBuilder MIRBuilder(DepMBB, DepMBB.getFirstNonPHI());
1886 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
1887 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1888 auto NewTypeMI = BuildMI(BB&: MIRBuilder.getMBB(), I&: *MIRBuilder.getInsertPt(),
1889 MIMD: MIRBuilder.getDL(), MCID: TII.get(Opcode: SPIRVOPcode))
1890 .addDef(RegNo: createTypeVReg(MRI&: CurMF->getRegInfo()))
1891 .addImm(Val: BitWidth);
1892 // Don't add Encoding to FP type
1893 if (!Ty->isFloatTy()) {
1894 return NewTypeMI.addImm(Val: 0);
1895 } else {
1896 return NewTypeMI;
1897 }
1898 });
1899 add(T: Ty, RequiresExplicitLayout: false, MI: NewMI);
1900 return finishCreatingSPIRVType(LLVMTy: Ty, SpirvType: NewMI);
1901}
1902
1903SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateSPIRVIntegerType(
1904 unsigned BitWidth, MachineInstr &I, const SPIRVInstrInfo &TII) {
1905 // Maybe adjust bit width to keep DuplicateTracker consistent. Without
1906 // such an adjustment SPIRVGlobalRegistry::getOpTypeInt() could create, for
1907 // example, the same "OpTypeInt 8" type for a series of LLVM integer types
1908 // with number of bits less than 8, causing duplicate type definitions.
1909 if (BitWidth > 1)
1910 BitWidth = adjustOpTypeIntWidth(Width: BitWidth);
1911 Type *LLVMTy = IntegerType::get(C&: CurMF->getFunction().getContext(), NumBits: BitWidth);
1912 return getOrCreateSPIRVType(BitWidth, I, TII, SPIRVOPcode: SPIRV::OpTypeInt, Ty: LLVMTy);
1913}
1914
1915SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateSPIRVFloatType(
1916 unsigned BitWidth, MachineInstr &I, const SPIRVInstrInfo &TII) {
1917 LLVMContext &Ctx = CurMF->getFunction().getContext();
1918 Type *LLVMTy;
1919 switch (BitWidth) {
1920 case 16:
1921 LLVMTy = Type::getHalfTy(C&: Ctx);
1922 break;
1923 case 32:
1924 LLVMTy = Type::getFloatTy(C&: Ctx);
1925 break;
1926 case 64:
1927 LLVMTy = Type::getDoubleTy(C&: Ctx);
1928 break;
1929 default:
1930 llvm_unreachable("Bit width is of unexpected size.");
1931 }
1932 return getOrCreateSPIRVType(BitWidth, I, TII, SPIRVOPcode: SPIRV::OpTypeFloat, Ty: LLVMTy);
1933}
1934
1935SPIRVTypeInst
1936SPIRVGlobalRegistry::getOrCreateSPIRVBoolType(MachineIRBuilder &MIRBuilder,
1937 bool EmitIR) {
1938 return getOrCreateSPIRVType(
1939 Ty: IntegerType::get(C&: MIRBuilder.getMF().getFunction().getContext(), NumBits: 1),
1940 MIRBuilder, AccessQual: SPIRV::AccessQualifier::ReadWrite, ExplicitLayoutRequired: false, EmitIR);
1941}
1942
1943SPIRVTypeInst
1944SPIRVGlobalRegistry::getOrCreateSPIRVBoolType(MachineInstr &I,
1945 const SPIRVInstrInfo &TII) {
1946 Type *Ty = IntegerType::get(C&: CurMF->getFunction().getContext(), NumBits: 1);
1947 if (const MachineInstr *MI = findMI(T: Ty, RequiresExplicitLayout: false, MF: CurMF))
1948 return MI;
1949 MachineBasicBlock &DepMBB = I.getMF()->front();
1950 MachineIRBuilder MIRBuilder(DepMBB, DepMBB.getFirstNonPHI());
1951 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
1952 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1953 return BuildMI(BB&: MIRBuilder.getMBB(), I&: *MIRBuilder.getInsertPt(),
1954 MIMD: MIRBuilder.getDL(), MCID: TII.get(Opcode: SPIRV::OpTypeBool))
1955 .addDef(RegNo: createTypeVReg(MRI&: CurMF->getRegInfo()));
1956 });
1957 add(T: Ty, RequiresExplicitLayout: false, MI: NewMI);
1958 return finishCreatingSPIRVType(LLVMTy: Ty, SpirvType: NewMI);
1959}
1960
1961SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateSPIRVVectorType(
1962 SPIRVTypeInst BaseType, unsigned NumElements, MachineIRBuilder &MIRBuilder,
1963 bool EmitIR) {
1964 return getOrCreateSPIRVType(
1965 Ty: FixedVectorType::get(ElementType: const_cast<Type *>(getTypeForSPIRVType(Ty: BaseType)),
1966 NumElts: NumElements),
1967 MIRBuilder, AccessQual: SPIRV::AccessQualifier::ReadWrite, ExplicitLayoutRequired: false, EmitIR);
1968}
1969
1970SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateSPIRVVectorType(
1971 SPIRVTypeInst BaseType, unsigned NumElements, MachineInstr &I,
1972 const SPIRVInstrInfo &TII) {
1973 // At this point of time all 1-element vectors are resolved. Add assertion
1974 // to fire if anything changes.
1975 assert(NumElements >= 2 && "SPIR-V vectors must have at least 2 components");
1976 Type *Ty = FixedVectorType::get(
1977 ElementType: const_cast<Type *>(getTypeForSPIRVType(Ty: BaseType)), NumElts: NumElements);
1978 if (const MachineInstr *MI = findMI(T: Ty, RequiresExplicitLayout: false, MF: CurMF))
1979 return MI;
1980 MachineInstr *DepMI =
1981 const_cast<MachineInstr *>(static_cast<const MachineInstr *>(BaseType));
1982 MachineIRBuilder MIRBuilder(*DepMI->getParent(), DepMI->getIterator());
1983 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
1984 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
1985 return BuildMI(BB&: MIRBuilder.getMBB(), I&: *MIRBuilder.getInsertPt(),
1986 MIMD: MIRBuilder.getDL(), MCID: TII.get(Opcode: SPIRV::OpTypeVector))
1987 .addDef(RegNo: createTypeVReg(MRI&: CurMF->getRegInfo()))
1988 .addUse(RegNo: getSPIRVTypeID(SpirvType: BaseType))
1989 .addImm(Val: NumElements);
1990 });
1991 add(T: Ty, RequiresExplicitLayout: false, MI: NewMI);
1992 return finishCreatingSPIRVType(LLVMTy: Ty, SpirvType: NewMI);
1993}
1994
1995SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateSPIRVPointerType(
1996 const Type *BaseType, MachineInstr &I,
1997 SPIRV::StorageClass::StorageClass SC) {
1998 MachineIRBuilder MIRBuilder(I);
1999 return getOrCreateSPIRVPointerType(BaseType, MIRBuilder, SC);
2000}
2001
2002SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateSPIRVPointerType(
2003 const Type *BaseType, MachineIRBuilder &MIRBuilder,
2004 SPIRV::StorageClass::StorageClass SC) {
2005 // TODO: Need to check if EmitIr should always be true.
2006 SPIRVTypeInst SpirvBaseType = getOrCreateSPIRVType(
2007 Ty: BaseType, MIRBuilder, AccessQual: SPIRV::AccessQualifier::ReadWrite,
2008 ExplicitLayoutRequired: storageClassRequiresExplictLayout(SC), EmitIR: true);
2009 assert(SpirvBaseType);
2010 return getOrCreateSPIRVPointerTypeInternal(BaseType: SpirvBaseType, MIRBuilder, SC);
2011}
2012
2013SPIRVTypeInst SPIRVGlobalRegistry::changePointerStorageClass(
2014 SPIRVTypeInst PtrType, SPIRV::StorageClass::StorageClass SC,
2015 MachineInstr &I) {
2016 [[maybe_unused]] SPIRV::StorageClass::StorageClass OldSC =
2017 getPointerStorageClass(Type: PtrType);
2018 assert(storageClassRequiresExplictLayout(OldSC) ==
2019 storageClassRequiresExplictLayout(SC));
2020
2021 SPIRVTypeInst PointeeType = getPointeeType(PtrType);
2022 MachineIRBuilder MIRBuilder(I);
2023 return getOrCreateSPIRVPointerTypeInternal(BaseType: PointeeType, MIRBuilder, SC);
2024}
2025
2026SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateSPIRVPointerType(
2027 SPIRVTypeInst BaseType, MachineIRBuilder &MIRBuilder,
2028 SPIRV::StorageClass::StorageClass SC) {
2029 const Type *LLVMType = getTypeForSPIRVType(Ty: BaseType);
2030 assert(!storageClassRequiresExplictLayout(SC));
2031 SPIRVTypeInst R = getOrCreateSPIRVPointerType(BaseType: LLVMType, MIRBuilder, SC);
2032 assert(
2033 getPointeeType(R) == BaseType &&
2034 "The base type was not correctly laid out for the given storage class.");
2035 return R;
2036}
2037
2038SPIRVTypeInst SPIRVGlobalRegistry::getOrCreateSPIRVPointerTypeInternal(
2039 SPIRVTypeInst BaseType, MachineIRBuilder &MIRBuilder,
2040 SPIRV::StorageClass::StorageClass SC) {
2041 const Type *PointerElementType = getTypeForSPIRVType(Ty: BaseType);
2042 unsigned AddressSpace = storageClassToAddressSpace(SC);
2043 if (const MachineInstr *MI = findMI(PointeeTy: PointerElementType, AddressSpace, MF: CurMF))
2044 return MI;
2045 Type *Ty = TypedPointerType::get(ElementType: const_cast<Type *>(PointerElementType),
2046 AddressSpace);
2047 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
2048 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
2049 return BuildMI(BB&: MIRBuilder.getMBB(), I: MIRBuilder.getInsertPt(),
2050 MIMD: MIRBuilder.getDebugLoc(),
2051 MCID: MIRBuilder.getTII().get(Opcode: SPIRV::OpTypePointer))
2052 .addDef(RegNo: createTypeVReg(MRI&: CurMF->getRegInfo()))
2053 .addImm(Val: static_cast<uint32_t>(SC))
2054 .addUse(RegNo: getSPIRVTypeID(SpirvType: BaseType));
2055 });
2056 add(PointeeTy: PointerElementType, AddressSpace, MI: NewMI);
2057 return finishCreatingSPIRVType(LLVMTy: Ty, SpirvType: NewMI);
2058}
2059
2060Register SPIRVGlobalRegistry::getOrCreateUndef(MachineInstr &I,
2061 SPIRVTypeInst SpvType,
2062 const SPIRVInstrInfo &TII) {
2063 UndefValue *UV =
2064 UndefValue::get(T: const_cast<Type *>(getTypeForSPIRVType(Ty: SpvType)));
2065 Register Res = find(V: UV, MF: CurMF);
2066 if (Res.isValid())
2067 return Res;
2068
2069 LLT LLTy = LLT::scalar(SizeInBits: 64);
2070 Res = CurMF->getRegInfo().createGenericVirtualRegister(Ty: LLTy);
2071 CurMF->getRegInfo().setRegClass(Reg: Res, RC: &SPIRV::iIDRegClass);
2072 assignSPIRVTypeToVReg(SpirvType: SpvType, VReg: Res, MF: *CurMF);
2073
2074 MachineInstr *DepMI =
2075 const_cast<MachineInstr *>(static_cast<const MachineInstr *>(SpvType));
2076 MachineIRBuilder MIRBuilder(*DepMI->getParent(), DepMI->getIterator());
2077 const MachineInstr *NewMI = createConstOrTypeAtFunctionEntry(
2078 MIRBuilder, Op: [&](MachineIRBuilder &MIRBuilder) {
2079 auto MIB = BuildMI(BB&: MIRBuilder.getMBB(), I&: *MIRBuilder.getInsertPt(),
2080 MIMD: MIRBuilder.getDL(), MCID: TII.get(Opcode: SPIRV::OpUndef))
2081 .addDef(RegNo: Res)
2082 .addUse(RegNo: getSPIRVTypeID(SpirvType: SpvType));
2083 const auto &ST = CurMF->getSubtarget();
2084 constrainSelectedInstRegOperands(I&: *MIB, TII: *ST.getInstrInfo(),
2085 TRI: *ST.getRegisterInfo(),
2086 RBI: *ST.getRegBankInfo());
2087 return MIB;
2088 });
2089 add(V: UV, MI: NewMI);
2090 return Res;
2091}
2092
2093const TargetRegisterClass *
2094SPIRVGlobalRegistry::getRegClass(SPIRVTypeInst SpvType) const {
2095 unsigned Opcode = SpvType->getOpcode();
2096 switch (Opcode) {
2097 case SPIRV::OpTypeFloat:
2098 return &SPIRV::fIDRegClass;
2099 case SPIRV::OpTypePointer:
2100 return &SPIRV::pIDRegClass;
2101 case SPIRV::OpTypeVector: {
2102 SPIRVTypeInst ElemType =
2103 getSPIRVTypeForVReg(VReg: SpvType->getOperand(i: 1).getReg());
2104 unsigned ElemOpcode = ElemType ? ElemType->getOpcode() : 0;
2105 if (ElemOpcode == SPIRV::OpTypeFloat)
2106 return &SPIRV::vfIDRegClass;
2107 if (ElemOpcode == SPIRV::OpTypePointer)
2108 return &SPIRV::vpIDRegClass;
2109 return &SPIRV::vIDRegClass;
2110 }
2111 }
2112 return &SPIRV::iIDRegClass;
2113}
2114
2115inline unsigned getAS(SPIRVTypeInst SpvType) {
2116 return storageClassToAddressSpace(
2117 SC: static_cast<SPIRV::StorageClass::StorageClass>(
2118 SpvType->getOperand(i: 1).getImm()));
2119}
2120
2121LLT SPIRVGlobalRegistry::getRegType(SPIRVTypeInst SpvType) const {
2122 unsigned Opcode = SpvType ? SpvType->getOpcode() : 0;
2123 switch (Opcode) {
2124 case SPIRV::OpTypeInt:
2125 case SPIRV::OpTypeFloat:
2126 case SPIRV::OpTypeBool:
2127 return LLT::scalar(SizeInBits: getScalarOrVectorBitWidth(Type: SpvType));
2128 case SPIRV::OpTypePointer:
2129 return LLT::pointer(AddressSpace: getAS(SpvType), SizeInBits: getPointerSize());
2130 case SPIRV::OpTypeVector: {
2131 SPIRVTypeInst ElemType =
2132 getSPIRVTypeForVReg(VReg: SpvType->getOperand(i: 1).getReg());
2133 LLT ET;
2134 switch (ElemType ? ElemType->getOpcode() : 0) {
2135 case SPIRV::OpTypePointer:
2136 ET = LLT::pointer(AddressSpace: getAS(SpvType: ElemType), SizeInBits: getPointerSize());
2137 break;
2138 case SPIRV::OpTypeInt:
2139 case SPIRV::OpTypeFloat:
2140 case SPIRV::OpTypeBool:
2141 ET = LLT::scalar(SizeInBits: getScalarOrVectorBitWidth(Type: ElemType));
2142 break;
2143 default:
2144 ET = LLT::scalar(SizeInBits: 64);
2145 }
2146 return LLT::fixed_vector(
2147 NumElements: static_cast<unsigned>(SpvType->getOperand(i: 2).getImm()), ScalarTy: ET);
2148 }
2149 }
2150 return LLT::scalar(SizeInBits: 64);
2151}
2152
2153// Aliasing list MD contains several scope MD nodes whithin it. Each scope MD
2154// has a selfreference and an extra MD node for aliasing domain and also it
2155// can contain an optional string operand. Domain MD contains a self-reference
2156// with an optional string operand. Here we unfold the list, creating SPIR-V
2157// aliasing instructions.
2158// TODO: add support for an optional string operand.
2159MachineInstr *SPIRVGlobalRegistry::getOrAddMemAliasingINTELInst(
2160 MachineIRBuilder &MIRBuilder, const MDNode *AliasingListMD) {
2161 if (AliasingListMD->getNumOperands() == 0)
2162 return nullptr;
2163 if (auto L = AliasInstMDMap.find(x: AliasingListMD); L != AliasInstMDMap.end())
2164 return L->second;
2165
2166 SmallVector<MachineInstr *> ScopeList;
2167 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
2168 for (const MDOperand &MDListOp : AliasingListMD->operands()) {
2169 if (MDNode *ScopeMD = dyn_cast<MDNode>(Val: MDListOp)) {
2170 if (ScopeMD->getNumOperands() < 2)
2171 return nullptr;
2172 MDNode *DomainMD = dyn_cast<MDNode>(Val: ScopeMD->getOperand(I: 1));
2173 if (!DomainMD)
2174 return nullptr;
2175 auto *Domain = [&] {
2176 auto D = AliasInstMDMap.find(x: DomainMD);
2177 if (D != AliasInstMDMap.end())
2178 return D->second;
2179 const Register Ret = MRI->createVirtualRegister(RegClass: &SPIRV::IDRegClass);
2180 auto MIB =
2181 MIRBuilder.buildInstr(Opcode: SPIRV::OpAliasDomainDeclINTEL).addDef(RegNo: Ret);
2182 return MIB.getInstr();
2183 }();
2184 AliasInstMDMap.insert(x: std::make_pair(x&: DomainMD, y&: Domain));
2185 auto *Scope = [&] {
2186 auto S = AliasInstMDMap.find(x: ScopeMD);
2187 if (S != AliasInstMDMap.end())
2188 return S->second;
2189 const Register Ret = MRI->createVirtualRegister(RegClass: &SPIRV::IDRegClass);
2190 auto MIB = MIRBuilder.buildInstr(Opcode: SPIRV::OpAliasScopeDeclINTEL)
2191 .addDef(RegNo: Ret)
2192 .addUse(RegNo: Domain->getOperand(i: 0).getReg());
2193 return MIB.getInstr();
2194 }();
2195 AliasInstMDMap.insert(x: std::make_pair(x&: ScopeMD, y&: Scope));
2196 ScopeList.push_back(Elt: Scope);
2197 }
2198 }
2199
2200 const Register Ret = MRI->createVirtualRegister(RegClass: &SPIRV::IDRegClass);
2201 auto MIB =
2202 MIRBuilder.buildInstr(Opcode: SPIRV::OpAliasScopeListDeclINTEL).addDef(RegNo: Ret);
2203 for (auto *Scope : ScopeList)
2204 MIB.addUse(RegNo: Scope->getOperand(i: 0).getReg());
2205 auto List = MIB.getInstr();
2206 AliasInstMDMap.insert(x: std::make_pair(x&: AliasingListMD, y&: List));
2207 return List;
2208}
2209
2210void SPIRVGlobalRegistry::buildMemAliasingOpDecorate(
2211 Register Reg, MachineIRBuilder &MIRBuilder, uint32_t Dec,
2212 const MDNode *AliasingListMD) {
2213 MachineInstr *AliasList =
2214 getOrAddMemAliasingINTELInst(MIRBuilder, AliasingListMD);
2215 if (!AliasList)
2216 return;
2217 MIRBuilder.buildInstr(Opcode: SPIRV::OpDecorate)
2218 .addUse(RegNo: Reg)
2219 .addImm(Val: Dec)
2220 .addUse(RegNo: AliasList->getOperand(i: 0).getReg());
2221}
2222void SPIRVGlobalRegistry::replaceAllUsesWith(Value *Old, Value *New,
2223 bool DeleteOld) {
2224 Old->replaceAllUsesWith(V: New);
2225 updateIfExistDeducedElementType(OldVal: Old, NewVal: New, DeleteOld);
2226 updateIfExistAssignPtrTypeInstr(OldVal: Old, NewVal: New, DeleteOld);
2227}
2228
2229void SPIRVGlobalRegistry::buildAssignType(IRBuilder<> &B, Type *Ty,
2230 Value *Arg) {
2231 Value *OfType = getNormalizedPoisonValue(Ty);
2232 CallInst *AssignCI = nullptr;
2233 if (Arg->getType()->isAggregateType() && Ty->isAggregateType() &&
2234 allowEmitFakeUse(Arg)) {
2235 LLVMContext &Ctx = Arg->getContext();
2236 SmallVector<Metadata *, 2> ArgMDs{
2237 MDNode::get(Context&: Ctx, MDs: ValueAsMetadata::getConstant(C: OfType)),
2238 MDString::get(Context&: Ctx, Str: Arg->getName())};
2239 B.CreateIntrinsic(ID: Intrinsic::spv_value_md,
2240 Args: {MetadataAsValue::get(Context&: Ctx, MD: MDTuple::get(Context&: Ctx, MDs: ArgMDs))});
2241 AssignCI = B.CreateIntrinsic(ID: Intrinsic::fake_use, Args: {Arg});
2242 } else {
2243 AssignCI = buildIntrWithMD(IntrID: Intrinsic::spv_assign_type, Types: {Arg->getType()},
2244 Arg: OfType, Arg2: Arg, Imms: {}, B);
2245 }
2246 addAssignPtrTypeInstr(Val: Arg, AssignPtrTyCI: AssignCI);
2247}
2248
2249void SPIRVGlobalRegistry::buildAssignPtr(IRBuilder<> &B, Type *ElemTy,
2250 Value *Arg) {
2251 Value *OfType = PoisonValue::get(T: ElemTy);
2252 CallInst *AssignPtrTyCI = findAssignPtrTypeInstr(Val: Arg);
2253 Function *CurrF =
2254 B.GetInsertBlock() ? B.GetInsertBlock()->getParent() : nullptr;
2255 if (AssignPtrTyCI == nullptr ||
2256 AssignPtrTyCI->getParent()->getParent() != CurrF) {
2257 AssignPtrTyCI = buildIntrWithMD(
2258 IntrID: Intrinsic::spv_assign_ptr_type, Types: {Arg->getType()}, Arg: OfType, Arg2: Arg,
2259 Imms: {B.getInt32(C: getPointerAddressSpace(T: Arg->getType()))}, B);
2260 addDeducedElementType(Val: AssignPtrTyCI, Ty: ElemTy);
2261 addDeducedElementType(Val: Arg, Ty: ElemTy);
2262 addAssignPtrTypeInstr(Val: Arg, AssignPtrTyCI);
2263 } else {
2264 updateAssignType(AssignCI: AssignPtrTyCI, Arg, OfType);
2265 }
2266}
2267
2268void SPIRVGlobalRegistry::updateAssignType(CallInst *AssignCI, Value *Arg,
2269 Value *OfType) {
2270 AssignCI->setArgOperand(i: 1, v: buildMD(Arg: OfType));
2271 if (cast<IntrinsicInst>(Val: AssignCI)->getIntrinsicID() !=
2272 Intrinsic::spv_assign_ptr_type)
2273 return;
2274
2275 // update association with the pointee type
2276 Type *ElemTy = OfType->getType();
2277 addDeducedElementType(Val: AssignCI, Ty: ElemTy);
2278 addDeducedElementType(Val: Arg, Ty: ElemTy);
2279}
2280
2281void SPIRVGlobalRegistry::addStructOffsetDecorations(
2282 Register Reg, StructType *Ty, MachineIRBuilder &MIRBuilder) {
2283 DataLayout DL;
2284 ArrayRef<TypeSize> Offsets = DL.getStructLayout(Ty)->getMemberOffsets();
2285 for (uint32_t I = 0; I < Ty->getNumElements(); ++I) {
2286 buildOpMemberDecorate(Reg, MIRBuilder, Dec: SPIRV::Decoration::Offset, Member: I,
2287 DecArgs: {static_cast<uint32_t>(Offsets[I])});
2288 }
2289}
2290
2291void SPIRVGlobalRegistry::addArrayStrideDecorations(
2292 Register Reg, Type *ElementType, MachineIRBuilder &MIRBuilder) {
2293 uint32_t SizeInBytes = DataLayout().getTypeSizeInBits(Ty: ElementType) / 8;
2294 buildOpDecorate(Reg, MIRBuilder, Dec: SPIRV::Decoration::ArrayStride,
2295 DecArgs: {SizeInBytes});
2296}
2297
2298bool SPIRVGlobalRegistry::hasBlockDecoration(SPIRVTypeInst Type) const {
2299 Register Def = getSPIRVTypeID(SpirvType: Type);
2300 for (const MachineInstr &Use :
2301 Type->getMF()->getRegInfo().use_instructions(Reg: Def)) {
2302 if (Use.getOpcode() != SPIRV::OpDecorate)
2303 continue;
2304
2305 if (Use.getOperand(i: 1).getImm() == SPIRV::Decoration::Block)
2306 return true;
2307 }
2308 return false;
2309}
2310