1//=- SPIRVMCInstLower.cpp - Convert SPIR-V MachineInstr to MCInst -*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains code to lower SPIR-V MachineInstrs to their corresponding
10// MCInst records.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SPIRVMCInstLower.h"
15#include "SPIRVModuleAnalysis.h"
16#include "SPIRVUtils.h"
17#include "llvm/CodeGen/MachineInstr.h"
18#include "llvm/IR/Constants.h"
19
20using namespace llvm;
21
22void SPIRVMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI,
23 SPIRV::ModuleAnalysisInfo *MAI) const {
24 OutMI.setOpcode(MI->getOpcode());
25 // Propagate previously set flags
26 if (MI->getAsmPrinterFlags() & SPIRV::ASM_PRINTER_WIDTH16)
27 OutMI.setFlags(SPIRV::INST_PRINTER_WIDTH16);
28 if (MI->getAsmPrinterFlags() & SPIRV::ASM_PRINTER_WIDTH64)
29 OutMI.setFlags(SPIRV::INST_PRINTER_WIDTH64);
30 const MachineFunction *MF = MI->getMF();
31 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
32 const MachineOperand &MO = MI->getOperand(i);
33 MCOperand MCOp;
34 switch (MO.getType()) {
35 default:
36 llvm_unreachable("unknown operand type");
37 case MachineOperand::MO_GlobalAddress: {
38 MCRegister FuncReg = MAI->getFuncReg(F: dyn_cast<Function>(Val: MO.getGlobal()));
39 if (!FuncReg.isValid()) {
40 std::string DiagMsg;
41 raw_string_ostream OS(DiagMsg);
42 MI->print(OS);
43 DiagMsg = "Unknown function in:" + DiagMsg;
44 report_fatal_error(reason: DiagMsg.c_str());
45 }
46 MCOp = MCOperand::createReg(Reg: FuncReg);
47 break;
48 }
49 case MachineOperand::MO_MachineBasicBlock:
50 MCOp = MCOperand::createReg(Reg: MAI->getOrCreateMBBRegister(MBB: *MO.getMBB()));
51 break;
52 case MachineOperand::MO_Register: {
53 MCRegister NewReg = MAI->getRegisterAlias(MF, Reg: MO.getReg());
54 MCOp = MCOperand::createReg(Reg: NewReg.isValid() ? NewReg
55 : MO.getReg().asMCReg());
56 break;
57 }
58 case MachineOperand::MO_Immediate:
59 if (MI->getOpcode() == SPIRV::OpExtInst && i == 2) {
60 MCRegister Reg = MAI->getExtInstSetReg(SetNum: MO.getImm());
61 MCOp = MCOperand::createReg(Reg);
62 } else {
63 MCOp = MCOperand::createImm(Val: MO.getImm());
64 }
65 break;
66 case MachineOperand::MO_FPImmediate:
67 MCOp = MCOperand::createDFPImm(
68 Val: MO.getFPImm()->getValueAPF().convertToFloat());
69 break;
70 }
71
72 OutMI.addOperand(Op: MCOp);
73 }
74}
75