1//===-- SystemZAsmPrinter.cpp - SystemZ LLVM assembly printer -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Streams SystemZ assembly language and associated data, in the form of
10// MCInsts and MCExprs respectively.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SystemZAsmPrinter.h"
15#include "MCTargetDesc/SystemZGNUInstPrinter.h"
16#include "MCTargetDesc/SystemZHLASMInstPrinter.h"
17#include "MCTargetDesc/SystemZMCAsmInfo.h"
18#include "MCTargetDesc/SystemZMCTargetDesc.h"
19#include "SystemZConstantPoolValue.h"
20#include "SystemZMCInstLower.h"
21#include "TargetInfo/SystemZTargetInfo.h"
22#include "llvm/ADT/StringExtras.h"
23#include "llvm/BinaryFormat/ELF.h"
24#include "llvm/BinaryFormat/GOFF.h"
25#include "llvm/CodeGen/MachineModuleInfoImpls.h"
26#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
27#include "llvm/IR/Mangler.h"
28#include "llvm/IR/Module.h"
29#include "llvm/MC/MCDirectives.h"
30#include "llvm/MC/MCExpr.h"
31#include "llvm/MC/MCInstBuilder.h"
32#include "llvm/MC/MCSectionELF.h"
33#include "llvm/MC/MCStreamer.h"
34#include "llvm/MC/MCSymbolGOFF.h"
35#include "llvm/MC/TargetRegistry.h"
36#include "llvm/Support/Chrono.h"
37#include "llvm/Support/Compiler.h"
38#include "llvm/Support/ConvertEBCDIC.h"
39#include "llvm/Support/FormatVariadic.h"
40
41using namespace llvm;
42
43// Return an RI instruction like MI with opcode Opcode, but with the
44// GR64 register operands turned into GR32s.
45static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) {
46 if (MI->isCompare())
47 return MCInstBuilder(Opcode)
48 .addReg(Reg: SystemZMC::getRegAsGR32(Reg: MI->getOperand(i: 0).getReg()))
49 .addImm(Val: MI->getOperand(i: 1).getImm());
50 else
51 return MCInstBuilder(Opcode)
52 .addReg(Reg: SystemZMC::getRegAsGR32(Reg: MI->getOperand(i: 0).getReg()))
53 .addReg(Reg: SystemZMC::getRegAsGR32(Reg: MI->getOperand(i: 1).getReg()))
54 .addImm(Val: MI->getOperand(i: 2).getImm());
55}
56
57// Return an RI instruction like MI with opcode Opcode, but with the
58// GR64 register operands turned into GRH32s.
59static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode) {
60 if (MI->isCompare())
61 return MCInstBuilder(Opcode)
62 .addReg(Reg: SystemZMC::getRegAsGRH32(Reg: MI->getOperand(i: 0).getReg()))
63 .addImm(Val: MI->getOperand(i: 1).getImm());
64 else
65 return MCInstBuilder(Opcode)
66 .addReg(Reg: SystemZMC::getRegAsGRH32(Reg: MI->getOperand(i: 0).getReg()))
67 .addReg(Reg: SystemZMC::getRegAsGRH32(Reg: MI->getOperand(i: 1).getReg()))
68 .addImm(Val: MI->getOperand(i: 2).getImm());
69}
70
71// Return an RI instruction like MI with opcode Opcode, but with the
72// R2 register turned into a GR64.
73static MCInst lowerRIEfLow(const MachineInstr *MI, unsigned Opcode) {
74 return MCInstBuilder(Opcode)
75 .addReg(Reg: MI->getOperand(i: 0).getReg())
76 .addReg(Reg: MI->getOperand(i: 1).getReg())
77 .addReg(Reg: SystemZMC::getRegAsGR64(Reg: MI->getOperand(i: 2).getReg()))
78 .addImm(Val: MI->getOperand(i: 3).getImm())
79 .addImm(Val: MI->getOperand(i: 4).getImm())
80 .addImm(Val: MI->getOperand(i: 5).getImm());
81}
82
83static const MCSymbolRefExpr *getTLSGetOffset(MCContext &Context) {
84 StringRef Name = "__tls_get_offset";
85 return MCSymbolRefExpr::create(Symbol: Context.getOrCreateSymbol(Name),
86 specifier: SystemZ::S_PLT, Ctx&: Context);
87}
88
89static const MCSymbolRefExpr *getGlobalOffsetTable(MCContext &Context) {
90 StringRef Name = "_GLOBAL_OFFSET_TABLE_";
91 return MCSymbolRefExpr::create(Symbol: Context.getOrCreateSymbol(Name),
92 Ctx&: Context);
93}
94
95// MI is an instruction that accepts an optional alignment hint,
96// and which was already lowered to LoweredMI. If the alignment
97// of the original memory operand is known, update LoweredMI to
98// an instruction with the corresponding hint set.
99static void lowerAlignmentHint(const MachineInstr *MI, MCInst &LoweredMI,
100 unsigned Opcode) {
101 if (MI->memoperands_empty())
102 return;
103
104 Align Alignment = Align(16);
105 for (MachineInstr::mmo_iterator MMOI = MI->memoperands_begin(),
106 EE = MI->memoperands_end(); MMOI != EE; ++MMOI)
107 if ((*MMOI)->getAlign() < Alignment)
108 Alignment = (*MMOI)->getAlign();
109
110 unsigned AlignmentHint = 0;
111 if (Alignment >= Align(16))
112 AlignmentHint = 4;
113 else if (Alignment >= Align(8))
114 AlignmentHint = 3;
115 if (AlignmentHint == 0)
116 return;
117
118 LoweredMI.setOpcode(Opcode);
119 LoweredMI.addOperand(Op: MCOperand::createImm(Val: AlignmentHint));
120}
121
122// MI loads the high part of a vector from memory. Return an instruction
123// that uses replicating vector load Opcode to do the same thing.
124static MCInst lowerSubvectorLoad(const MachineInstr *MI, unsigned Opcode) {
125 return MCInstBuilder(Opcode)
126 .addReg(Reg: SystemZMC::getRegAsVR128(Reg: MI->getOperand(i: 0).getReg()))
127 .addReg(Reg: MI->getOperand(i: 1).getReg())
128 .addImm(Val: MI->getOperand(i: 2).getImm())
129 .addReg(Reg: MI->getOperand(i: 3).getReg());
130}
131
132// MI stores the high part of a vector to memory. Return an instruction
133// that uses elemental vector store Opcode to do the same thing.
134static MCInst lowerSubvectorStore(const MachineInstr *MI, unsigned Opcode) {
135 return MCInstBuilder(Opcode)
136 .addReg(Reg: SystemZMC::getRegAsVR128(Reg: MI->getOperand(i: 0).getReg()))
137 .addReg(Reg: MI->getOperand(i: 1).getReg())
138 .addImm(Val: MI->getOperand(i: 2).getImm())
139 .addReg(Reg: MI->getOperand(i: 3).getReg())
140 .addImm(Val: 0);
141}
142
143// MI extracts the first element of the source vector.
144static MCInst lowerVecEltExtraction(const MachineInstr *MI, unsigned Opcode) {
145 return MCInstBuilder(Opcode)
146 .addReg(Reg: SystemZMC::getRegAsGR64(Reg: MI->getOperand(i: 0).getReg()))
147 .addReg(Reg: SystemZMC::getRegAsVR128(Reg: MI->getOperand(i: 1).getReg()))
148 .addReg(Reg: 0)
149 .addImm(Val: 0);
150}
151
152// MI inserts value into the first element of the destination vector.
153static MCInst lowerVecEltInsertion(const MachineInstr *MI, unsigned Opcode) {
154 return MCInstBuilder(Opcode)
155 .addReg(Reg: SystemZMC::getRegAsVR128(Reg: MI->getOperand(i: 0).getReg()))
156 .addReg(Reg: SystemZMC::getRegAsVR128(Reg: MI->getOperand(i: 0).getReg()))
157 .addReg(Reg: MI->getOperand(i: 1).getReg())
158 .addReg(Reg: 0)
159 .addImm(Val: 0);
160}
161
162// The XPLINK ABI requires that a no-op encoding the call type is emitted after
163// each call to a subroutine. This information can be used by the called
164// function to determine its entry point, e.g. for generating a backtrace. The
165// call type is encoded as a register number in the bcr instruction. See
166// enumeration CallType for the possible values.
167void SystemZAsmPrinter::emitCallInformation(CallType CT) {
168 EmitToStreamer(S&: *OutStreamer,
169 Inst: MCInstBuilder(SystemZ::BCRAsm)
170 .addImm(Val: 0)
171 .addReg(Reg: SystemZMC::GR64Regs[static_cast<unsigned>(CT)]));
172}
173
174uint32_t SystemZAsmPrinter::AssociatedDataAreaTable::insert(const MCSymbol *Sym,
175 unsigned SlotKind) {
176 auto Key = std::make_pair(x&: Sym, y&: SlotKind);
177 auto It = Displacements.find(Key);
178
179 if (It != Displacements.end())
180 return (*It).second;
181
182 // Determine length of descriptor.
183 uint32_t Length;
184 switch (SlotKind) {
185 case SystemZII::MO_ADA_DIRECT_FUNC_DESC:
186 Length = 2 * PointerSize;
187 break;
188 default:
189 Length = PointerSize;
190 break;
191 }
192
193 uint32_t Displacement = NextDisplacement;
194 Displacements[std::make_pair(x&: Sym, y&: SlotKind)] = NextDisplacement;
195 NextDisplacement += Length;
196
197 return Displacement;
198}
199
200uint32_t
201SystemZAsmPrinter::AssociatedDataAreaTable::insert(const MachineOperand MO) {
202 MCSymbol *Sym;
203 if (MO.getType() == MachineOperand::MO_GlobalAddress) {
204 const GlobalValue *GV = MO.getGlobal();
205 Sym = MO.getParent()->getMF()->getTarget().getSymbol(GV);
206 assert(Sym && "No symbol");
207 } else if (MO.getType() == MachineOperand::MO_ExternalSymbol) {
208 const char *SymName = MO.getSymbolName();
209 Sym = MO.getParent()->getMF()->getContext().getOrCreateSymbol(Name: SymName);
210 assert(Sym && "No symbol");
211 } else
212 llvm_unreachable("Unexpected operand type");
213
214 unsigned ADAslotType = MO.getTargetFlags();
215 return insert(Sym, SlotKind: ADAslotType);
216}
217
218void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
219 SystemZ_MC::verifyInstructionPredicates(Opcode: MI->getOpcode(),
220 Features: getSubtargetInfo().getFeatureBits());
221
222 SystemZMCInstLower Lower(MF->getContext(), *this);
223 MCInst LoweredMI;
224 switch (MI->getOpcode()) {
225 case SystemZ::Return:
226 LoweredMI = MCInstBuilder(SystemZ::BR)
227 .addReg(Reg: SystemZ::R14D);
228 break;
229
230 case SystemZ::Return_XPLINK:
231 LoweredMI = MCInstBuilder(SystemZ::B)
232 .addReg(Reg: SystemZ::R7D)
233 .addImm(Val: 2)
234 .addReg(Reg: 0);
235 break;
236
237 case SystemZ::CondReturn:
238 LoweredMI = MCInstBuilder(SystemZ::BCR)
239 .addImm(Val: MI->getOperand(i: 0).getImm())
240 .addImm(Val: MI->getOperand(i: 1).getImm())
241 .addReg(Reg: SystemZ::R14D);
242 break;
243
244 case SystemZ::CondReturn_XPLINK:
245 LoweredMI = MCInstBuilder(SystemZ::BC)
246 .addImm(Val: MI->getOperand(i: 0).getImm())
247 .addImm(Val: MI->getOperand(i: 1).getImm())
248 .addReg(Reg: SystemZ::R7D)
249 .addImm(Val: 2)
250 .addReg(Reg: 0);
251 break;
252
253 case SystemZ::CRBReturn:
254 LoweredMI = MCInstBuilder(SystemZ::CRB)
255 .addReg(Reg: MI->getOperand(i: 0).getReg())
256 .addReg(Reg: MI->getOperand(i: 1).getReg())
257 .addImm(Val: MI->getOperand(i: 2).getImm())
258 .addReg(Reg: SystemZ::R14D)
259 .addImm(Val: 0);
260 break;
261
262 case SystemZ::CGRBReturn:
263 LoweredMI = MCInstBuilder(SystemZ::CGRB)
264 .addReg(Reg: MI->getOperand(i: 0).getReg())
265 .addReg(Reg: MI->getOperand(i: 1).getReg())
266 .addImm(Val: MI->getOperand(i: 2).getImm())
267 .addReg(Reg: SystemZ::R14D)
268 .addImm(Val: 0);
269 break;
270
271 case SystemZ::CIBReturn:
272 LoweredMI = MCInstBuilder(SystemZ::CIB)
273 .addReg(Reg: MI->getOperand(i: 0).getReg())
274 .addImm(Val: MI->getOperand(i: 1).getImm())
275 .addImm(Val: MI->getOperand(i: 2).getImm())
276 .addReg(Reg: SystemZ::R14D)
277 .addImm(Val: 0);
278 break;
279
280 case SystemZ::CGIBReturn:
281 LoweredMI = MCInstBuilder(SystemZ::CGIB)
282 .addReg(Reg: MI->getOperand(i: 0).getReg())
283 .addImm(Val: MI->getOperand(i: 1).getImm())
284 .addImm(Val: MI->getOperand(i: 2).getImm())
285 .addReg(Reg: SystemZ::R14D)
286 .addImm(Val: 0);
287 break;
288
289 case SystemZ::CLRBReturn:
290 LoweredMI = MCInstBuilder(SystemZ::CLRB)
291 .addReg(Reg: MI->getOperand(i: 0).getReg())
292 .addReg(Reg: MI->getOperand(i: 1).getReg())
293 .addImm(Val: MI->getOperand(i: 2).getImm())
294 .addReg(Reg: SystemZ::R14D)
295 .addImm(Val: 0);
296 break;
297
298 case SystemZ::CLGRBReturn:
299 LoweredMI = MCInstBuilder(SystemZ::CLGRB)
300 .addReg(Reg: MI->getOperand(i: 0).getReg())
301 .addReg(Reg: MI->getOperand(i: 1).getReg())
302 .addImm(Val: MI->getOperand(i: 2).getImm())
303 .addReg(Reg: SystemZ::R14D)
304 .addImm(Val: 0);
305 break;
306
307 case SystemZ::CLIBReturn:
308 LoweredMI = MCInstBuilder(SystemZ::CLIB)
309 .addReg(Reg: MI->getOperand(i: 0).getReg())
310 .addImm(Val: MI->getOperand(i: 1).getImm())
311 .addImm(Val: MI->getOperand(i: 2).getImm())
312 .addReg(Reg: SystemZ::R14D)
313 .addImm(Val: 0);
314 break;
315
316 case SystemZ::CLGIBReturn:
317 LoweredMI = MCInstBuilder(SystemZ::CLGIB)
318 .addReg(Reg: MI->getOperand(i: 0).getReg())
319 .addImm(Val: MI->getOperand(i: 1).getImm())
320 .addImm(Val: MI->getOperand(i: 2).getImm())
321 .addReg(Reg: SystemZ::R14D)
322 .addImm(Val: 0);
323 break;
324
325 case SystemZ::CallBRASL_XPLINK64:
326 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::BRASL)
327 .addReg(Reg: SystemZ::R7D)
328 .addExpr(Val: Lower.getExpr(MO: MI->getOperand(i: 0),
329 SystemZ::S_None)));
330 emitCallInformation(CT: CallType::BRASL7);
331 return;
332
333 case SystemZ::CallBASR_XPLINK64:
334 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::BASR)
335 .addReg(Reg: SystemZ::R7D)
336 .addReg(Reg: MI->getOperand(i: 0).getReg()));
337 emitCallInformation(CT: CallType::BASR76);
338 return;
339
340 case SystemZ::CallBASR_STACKEXT:
341 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::BASR)
342 .addReg(Reg: SystemZ::R3D)
343 .addReg(Reg: MI->getOperand(i: 0).getReg()));
344 emitCallInformation(CT: CallType::BASR33);
345 return;
346
347 case SystemZ::ADA_ENTRY_VALUE:
348 case SystemZ::ADA_ENTRY: {
349 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
350 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
351 uint32_t Disp = ADATable.insert(MO: MI->getOperand(i: 1));
352 Register TargetReg = MI->getOperand(i: 0).getReg();
353
354 Register ADAReg = MI->getOperand(i: 2).getReg();
355 Disp += MI->getOperand(i: 3).getImm();
356 bool LoadAddr = MI->getOpcode() == SystemZ::ADA_ENTRY;
357
358 unsigned Op0 = LoadAddr ? SystemZ::LA : SystemZ::LG;
359 unsigned Op = TII->getOpcodeForOffset(Opcode: Op0, Offset: Disp);
360
361 Register IndexReg = 0;
362 if (!Op) {
363 if (TargetReg != ADAReg) {
364 IndexReg = TargetReg;
365 // Use TargetReg to store displacement.
366 EmitToStreamer(
367 S&: *OutStreamer,
368 Inst: MCInstBuilder(SystemZ::LLILF).addReg(Reg: TargetReg).addImm(Val: Disp));
369 } else
370 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::ALGFI)
371 .addReg(Reg: TargetReg)
372 .addReg(Reg: TargetReg)
373 .addImm(Val: Disp));
374 Disp = 0;
375 Op = Op0;
376 }
377 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(Op)
378 .addReg(Reg: TargetReg)
379 .addReg(Reg: ADAReg)
380 .addImm(Val: Disp)
381 .addReg(Reg: IndexReg));
382
383 return;
384 }
385 case SystemZ::CallBRASL:
386 LoweredMI = MCInstBuilder(SystemZ::BRASL)
387 .addReg(Reg: SystemZ::R14D)
388 .addExpr(Val: Lower.getExpr(MO: MI->getOperand(i: 0), SystemZ::S_PLT));
389 break;
390
391 case SystemZ::CallBASR:
392 LoweredMI = MCInstBuilder(SystemZ::BASR)
393 .addReg(Reg: SystemZ::R14D)
394 .addReg(Reg: MI->getOperand(i: 0).getReg());
395 break;
396
397 case SystemZ::CallJG:
398 LoweredMI = MCInstBuilder(SystemZ::JG)
399 .addExpr(Val: Lower.getExpr(MO: MI->getOperand(i: 0), SystemZ::S_PLT));
400 break;
401
402 case SystemZ::CallBRCL:
403 LoweredMI = MCInstBuilder(SystemZ::BRCL)
404 .addImm(Val: MI->getOperand(i: 0).getImm())
405 .addImm(Val: MI->getOperand(i: 1).getImm())
406 .addExpr(Val: Lower.getExpr(MO: MI->getOperand(i: 2), SystemZ::S_PLT));
407 break;
408
409 case SystemZ::CallBR:
410 LoweredMI = MCInstBuilder(SystemZ::BR)
411 .addReg(Reg: MI->getOperand(i: 0).getReg());
412 break;
413
414 case SystemZ::CallBCR:
415 LoweredMI = MCInstBuilder(SystemZ::BCR)
416 .addImm(Val: MI->getOperand(i: 0).getImm())
417 .addImm(Val: MI->getOperand(i: 1).getImm())
418 .addReg(Reg: MI->getOperand(i: 2).getReg());
419 break;
420
421 case SystemZ::CRBCall:
422 LoweredMI = MCInstBuilder(SystemZ::CRB)
423 .addReg(Reg: MI->getOperand(i: 0).getReg())
424 .addReg(Reg: MI->getOperand(i: 1).getReg())
425 .addImm(Val: MI->getOperand(i: 2).getImm())
426 .addReg(Reg: MI->getOperand(i: 3).getReg())
427 .addImm(Val: 0);
428 break;
429
430 case SystemZ::CGRBCall:
431 LoweredMI = MCInstBuilder(SystemZ::CGRB)
432 .addReg(Reg: MI->getOperand(i: 0).getReg())
433 .addReg(Reg: MI->getOperand(i: 1).getReg())
434 .addImm(Val: MI->getOperand(i: 2).getImm())
435 .addReg(Reg: MI->getOperand(i: 3).getReg())
436 .addImm(Val: 0);
437 break;
438
439 case SystemZ::CIBCall:
440 LoweredMI = MCInstBuilder(SystemZ::CIB)
441 .addReg(Reg: MI->getOperand(i: 0).getReg())
442 .addImm(Val: MI->getOperand(i: 1).getImm())
443 .addImm(Val: MI->getOperand(i: 2).getImm())
444 .addReg(Reg: MI->getOperand(i: 3).getReg())
445 .addImm(Val: 0);
446 break;
447
448 case SystemZ::CGIBCall:
449 LoweredMI = MCInstBuilder(SystemZ::CGIB)
450 .addReg(Reg: MI->getOperand(i: 0).getReg())
451 .addImm(Val: MI->getOperand(i: 1).getImm())
452 .addImm(Val: MI->getOperand(i: 2).getImm())
453 .addReg(Reg: MI->getOperand(i: 3).getReg())
454 .addImm(Val: 0);
455 break;
456
457 case SystemZ::CLRBCall:
458 LoweredMI = MCInstBuilder(SystemZ::CLRB)
459 .addReg(Reg: MI->getOperand(i: 0).getReg())
460 .addReg(Reg: MI->getOperand(i: 1).getReg())
461 .addImm(Val: MI->getOperand(i: 2).getImm())
462 .addReg(Reg: MI->getOperand(i: 3).getReg())
463 .addImm(Val: 0);
464 break;
465
466 case SystemZ::CLGRBCall:
467 LoweredMI = MCInstBuilder(SystemZ::CLGRB)
468 .addReg(Reg: MI->getOperand(i: 0).getReg())
469 .addReg(Reg: MI->getOperand(i: 1).getReg())
470 .addImm(Val: MI->getOperand(i: 2).getImm())
471 .addReg(Reg: MI->getOperand(i: 3).getReg())
472 .addImm(Val: 0);
473 break;
474
475 case SystemZ::CLIBCall:
476 LoweredMI = MCInstBuilder(SystemZ::CLIB)
477 .addReg(Reg: MI->getOperand(i: 0).getReg())
478 .addImm(Val: MI->getOperand(i: 1).getImm())
479 .addImm(Val: MI->getOperand(i: 2).getImm())
480 .addReg(Reg: MI->getOperand(i: 3).getReg())
481 .addImm(Val: 0);
482 break;
483
484 case SystemZ::CLGIBCall:
485 LoweredMI = MCInstBuilder(SystemZ::CLGIB)
486 .addReg(Reg: MI->getOperand(i: 0).getReg())
487 .addImm(Val: MI->getOperand(i: 1).getImm())
488 .addImm(Val: MI->getOperand(i: 2).getImm())
489 .addReg(Reg: MI->getOperand(i: 3).getReg())
490 .addImm(Val: 0);
491 break;
492
493 case SystemZ::TLS_GDCALL:
494 LoweredMI =
495 MCInstBuilder(SystemZ::BRASL)
496 .addReg(Reg: SystemZ::R14D)
497 .addExpr(Val: getTLSGetOffset(Context&: MF->getContext()))
498 .addExpr(Val: Lower.getExpr(MO: MI->getOperand(i: 0), SystemZ::S_TLSGD));
499 break;
500
501 case SystemZ::TLS_LDCALL:
502 LoweredMI =
503 MCInstBuilder(SystemZ::BRASL)
504 .addReg(Reg: SystemZ::R14D)
505 .addExpr(Val: getTLSGetOffset(Context&: MF->getContext()))
506 .addExpr(Val: Lower.getExpr(MO: MI->getOperand(i: 0), SystemZ::S_TLSLDM));
507 break;
508
509 case SystemZ::GOT:
510 LoweredMI = MCInstBuilder(SystemZ::LARL)
511 .addReg(Reg: MI->getOperand(i: 0).getReg())
512 .addExpr(Val: getGlobalOffsetTable(Context&: MF->getContext()));
513 break;
514
515 case SystemZ::IILF64:
516 LoweredMI = MCInstBuilder(SystemZ::IILF)
517 .addReg(Reg: SystemZMC::getRegAsGR32(Reg: MI->getOperand(i: 0).getReg()))
518 .addImm(Val: MI->getOperand(i: 2).getImm());
519 break;
520
521 case SystemZ::IIHF64:
522 LoweredMI = MCInstBuilder(SystemZ::IIHF)
523 .addReg(Reg: SystemZMC::getRegAsGRH32(Reg: MI->getOperand(i: 0).getReg()))
524 .addImm(Val: MI->getOperand(i: 2).getImm());
525 break;
526
527 case SystemZ::RISBHH:
528 case SystemZ::RISBHL:
529 LoweredMI = lowerRIEfLow(MI, Opcode: SystemZ::RISBHG);
530 break;
531
532 case SystemZ::RISBLH:
533 case SystemZ::RISBLL:
534 LoweredMI = lowerRIEfLow(MI, Opcode: SystemZ::RISBLG);
535 break;
536
537 case SystemZ::VLVGP32:
538 LoweredMI = MCInstBuilder(SystemZ::VLVGP)
539 .addReg(Reg: MI->getOperand(i: 0).getReg())
540 .addReg(Reg: SystemZMC::getRegAsGR64(Reg: MI->getOperand(i: 1).getReg()))
541 .addReg(Reg: SystemZMC::getRegAsGR64(Reg: MI->getOperand(i: 2).getReg()));
542 break;
543
544 case SystemZ::VLR16:
545 case SystemZ::VLR32:
546 case SystemZ::VLR64:
547 LoweredMI = MCInstBuilder(SystemZ::VLR)
548 .addReg(Reg: SystemZMC::getRegAsVR128(Reg: MI->getOperand(i: 0).getReg()))
549 .addReg(Reg: SystemZMC::getRegAsVR128(Reg: MI->getOperand(i: 1).getReg()));
550 break;
551
552 case SystemZ::VL:
553 Lower.lower(MI, OutMI&: LoweredMI);
554 lowerAlignmentHint(MI, LoweredMI, Opcode: SystemZ::VLAlign);
555 break;
556
557 case SystemZ::VST:
558 Lower.lower(MI, OutMI&: LoweredMI);
559 lowerAlignmentHint(MI, LoweredMI, Opcode: SystemZ::VSTAlign);
560 break;
561
562 case SystemZ::VLM:
563 Lower.lower(MI, OutMI&: LoweredMI);
564 lowerAlignmentHint(MI, LoweredMI, Opcode: SystemZ::VLMAlign);
565 break;
566
567 case SystemZ::VSTM:
568 Lower.lower(MI, OutMI&: LoweredMI);
569 lowerAlignmentHint(MI, LoweredMI, Opcode: SystemZ::VSTMAlign);
570 break;
571
572 case SystemZ::VL16:
573 LoweredMI = lowerSubvectorLoad(MI, Opcode: SystemZ::VLREPH);
574 break;
575
576 case SystemZ::VL32:
577 LoweredMI = lowerSubvectorLoad(MI, Opcode: SystemZ::VLREPF);
578 break;
579
580 case SystemZ::VL64:
581 LoweredMI = lowerSubvectorLoad(MI, Opcode: SystemZ::VLREPG);
582 break;
583
584 case SystemZ::VST16:
585 LoweredMI = lowerSubvectorStore(MI, Opcode: SystemZ::VSTEH);
586 break;
587
588 case SystemZ::VST32:
589 LoweredMI = lowerSubvectorStore(MI, Opcode: SystemZ::VSTEF);
590 break;
591
592 case SystemZ::VST64:
593 LoweredMI = lowerSubvectorStore(MI, Opcode: SystemZ::VSTEG);
594 break;
595
596 case SystemZ::LFER:
597 LoweredMI = lowerVecEltExtraction(MI, Opcode: SystemZ::VLGVF);
598 break;
599
600 case SystemZ::LFER_16:
601 LoweredMI = lowerVecEltExtraction(MI, Opcode: SystemZ::VLGVH);
602 break;
603
604 case SystemZ::LEFR:
605 LoweredMI = lowerVecEltInsertion(MI, Opcode: SystemZ::VLVGF);
606 break;
607
608 case SystemZ::LEFR_16:
609 LoweredMI = lowerVecEltInsertion(MI, Opcode: SystemZ::VLVGH);
610 break;
611
612#define LOWER_LOW(NAME) \
613 case SystemZ::NAME##64: LoweredMI = lowerRILow(MI, SystemZ::NAME); break
614
615 LOWER_LOW(IILL);
616 LOWER_LOW(IILH);
617 LOWER_LOW(TMLL);
618 LOWER_LOW(TMLH);
619 LOWER_LOW(NILL);
620 LOWER_LOW(NILH);
621 LOWER_LOW(NILF);
622 LOWER_LOW(OILL);
623 LOWER_LOW(OILH);
624 LOWER_LOW(OILF);
625 LOWER_LOW(XILF);
626
627#undef LOWER_LOW
628
629#define LOWER_HIGH(NAME) \
630 case SystemZ::NAME##64: LoweredMI = lowerRIHigh(MI, SystemZ::NAME); break
631
632 LOWER_HIGH(IIHL);
633 LOWER_HIGH(IIHH);
634 LOWER_HIGH(TMHL);
635 LOWER_HIGH(TMHH);
636 LOWER_HIGH(NIHL);
637 LOWER_HIGH(NIHH);
638 LOWER_HIGH(NIHF);
639 LOWER_HIGH(OIHL);
640 LOWER_HIGH(OIHH);
641 LOWER_HIGH(OIHF);
642 LOWER_HIGH(XIHF);
643
644#undef LOWER_HIGH
645
646 case SystemZ::Serialize:
647 if (MF->getSubtarget<SystemZSubtarget>().hasFastSerialization())
648 LoweredMI = MCInstBuilder(SystemZ::BCRAsm)
649 .addImm(Val: 14).addReg(Reg: SystemZ::R0D);
650 else
651 LoweredMI = MCInstBuilder(SystemZ::BCRAsm)
652 .addImm(Val: 15).addReg(Reg: SystemZ::R0D);
653 break;
654
655 // We want to emit "j .+2" for traps, jumping to the relative immediate field
656 // of the jump instruction, which is an illegal instruction. We cannot emit a
657 // "." symbol, so create and emit a temp label before the instruction and use
658 // that instead.
659 case SystemZ::Trap: {
660 MCSymbol *DotSym = OutContext.createTempSymbol();
661 OutStreamer->emitLabel(Symbol: DotSym);
662
663 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Symbol: DotSym, Ctx&: OutContext);
664 const MCConstantExpr *ConstExpr = MCConstantExpr::create(Value: 2, Ctx&: OutContext);
665 LoweredMI = MCInstBuilder(SystemZ::J)
666 .addExpr(Val: MCBinaryExpr::createAdd(LHS: Expr, RHS: ConstExpr, Ctx&: OutContext));
667 }
668 break;
669
670 // Conditional traps will create a branch on condition instruction that jumps
671 // to the relative immediate field of the jump instruction. (eg. "jo .+2")
672 case SystemZ::CondTrap: {
673 MCSymbol *DotSym = OutContext.createTempSymbol();
674 OutStreamer->emitLabel(Symbol: DotSym);
675
676 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Symbol: DotSym, Ctx&: OutContext);
677 const MCConstantExpr *ConstExpr = MCConstantExpr::create(Value: 2, Ctx&: OutContext);
678 LoweredMI = MCInstBuilder(SystemZ::BRC)
679 .addImm(Val: MI->getOperand(i: 0).getImm())
680 .addImm(Val: MI->getOperand(i: 1).getImm())
681 .addExpr(Val: MCBinaryExpr::createAdd(LHS: Expr, RHS: ConstExpr, Ctx&: OutContext));
682 }
683 break;
684
685 case TargetOpcode::FENTRY_CALL:
686 LowerFENTRY_CALL(MI: *MI, MCIL&: Lower);
687 return;
688
689 case TargetOpcode::STACKMAP:
690 LowerSTACKMAP(MI: *MI);
691 return;
692
693 case TargetOpcode::PATCHPOINT:
694 LowerPATCHPOINT(MI: *MI, Lower);
695 return;
696
697 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
698 LowerPATCHABLE_FUNCTION_ENTER(MI: *MI, Lower);
699 return;
700
701 case TargetOpcode::PATCHABLE_RET:
702 LowerPATCHABLE_RET(MI: *MI, Lower);
703 return;
704
705 case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
706 llvm_unreachable("PATCHABLE_FUNCTION_EXIT should never be emitted");
707
708 case TargetOpcode::PATCHABLE_TAIL_CALL:
709 // TODO: Define a trampoline `__xray_FunctionTailExit` and differentiate a
710 // normal function exit from a tail exit.
711 llvm_unreachable("Tail call is handled in the normal case. See comments "
712 "around this assert.");
713
714 case SystemZ::EXRL_Pseudo: {
715 unsigned TargetInsOpc = MI->getOperand(i: 0).getImm();
716 Register LenMinus1Reg = MI->getOperand(i: 1).getReg();
717 Register DestReg = MI->getOperand(i: 2).getReg();
718 int64_t DestDisp = MI->getOperand(i: 3).getImm();
719 Register SrcReg = MI->getOperand(i: 4).getReg();
720 int64_t SrcDisp = MI->getOperand(i: 5).getImm();
721
722 SystemZTargetStreamer *TS = getTargetStreamer();
723 MCInst ET = MCInstBuilder(TargetInsOpc)
724 .addReg(Reg: DestReg)
725 .addImm(Val: DestDisp)
726 .addImm(Val: 1)
727 .addReg(Reg: SrcReg)
728 .addImm(Val: SrcDisp);
729 SystemZTargetStreamer::MCInstSTIPair ET_STI(ET, &MF->getSubtarget());
730 auto [It, Inserted] = TS->EXRLTargets2Sym.try_emplace(k: ET_STI);
731 if (Inserted)
732 It->second = OutContext.createTempSymbol();
733 MCSymbol *DotSym = It->second;
734 const MCSymbolRefExpr *Dot = MCSymbolRefExpr::create(Symbol: DotSym, Ctx&: OutContext);
735 EmitToStreamer(
736 S&: *OutStreamer,
737 Inst: MCInstBuilder(SystemZ::EXRL).addReg(Reg: LenMinus1Reg).addExpr(Val: Dot));
738 return;
739 }
740
741 // EH_SjLj_Setup is a dummy terminator instruction of size 0.
742 // It is used to handle the clobber register for builtin setjmp.
743 case SystemZ::EH_SjLj_Setup:
744 return;
745
746 default:
747 Lower.lower(MI, OutMI&: LoweredMI);
748 break;
749 }
750 EmitToStreamer(S&: *OutStreamer, Inst: LoweredMI);
751}
752
753// Emit the largest nop instruction smaller than or equal to NumBytes
754// bytes. Return the size of nop emitted.
755static unsigned EmitNop(MCContext &OutContext, MCStreamer &OutStreamer,
756 unsigned NumBytes, const MCSubtargetInfo &STI) {
757 if (NumBytes < 2) {
758 llvm_unreachable("Zero nops?");
759 return 0;
760 }
761 else if (NumBytes < 4) {
762 OutStreamer.emitInstruction(
763 Inst: MCInstBuilder(SystemZ::BCRAsm).addImm(Val: 0).addReg(Reg: SystemZ::R0D), STI);
764 return 2;
765 }
766 else if (NumBytes < 6) {
767 OutStreamer.emitInstruction(
768 Inst: MCInstBuilder(SystemZ::BCAsm).addImm(Val: 0).addReg(Reg: 0).addImm(Val: 0).addReg(Reg: 0),
769 STI);
770 return 4;
771 }
772 else {
773 MCSymbol *DotSym = OutContext.createTempSymbol();
774 const MCSymbolRefExpr *Dot = MCSymbolRefExpr::create(Symbol: DotSym, Ctx&: OutContext);
775 OutStreamer.emitLabel(Symbol: DotSym);
776 OutStreamer.emitInstruction(
777 Inst: MCInstBuilder(SystemZ::BRCLAsm).addImm(Val: 0).addExpr(Val: Dot), STI);
778 return 6;
779 }
780}
781
782void SystemZAsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI,
783 SystemZMCInstLower &Lower) {
784 MCContext &Ctx = MF->getContext();
785 if (MF->getFunction().hasFnAttribute(Kind: "mrecord-mcount")) {
786 MCSymbol *DotSym = OutContext.createTempSymbol();
787 OutStreamer->pushSection();
788 OutStreamer->switchSection(
789 Section: Ctx.getELFSection(Section: "__mcount_loc", Type: ELF::SHT_PROGBITS, Flags: ELF::SHF_ALLOC));
790 OutStreamer->emitSymbolValue(Sym: DotSym, Size: 8);
791 OutStreamer->popSection();
792 OutStreamer->emitLabel(Symbol: DotSym);
793 }
794
795 if (MF->getFunction().hasFnAttribute(Kind: "mnop-mcount")) {
796 EmitNop(OutContext&: Ctx, OutStreamer&: *OutStreamer, NumBytes: 6, STI: getSubtargetInfo());
797 return;
798 }
799
800 MCSymbol *fentry = Ctx.getOrCreateSymbol(Name: "__fentry__");
801 const MCSymbolRefExpr *Op =
802 MCSymbolRefExpr::create(Symbol: fentry, specifier: SystemZ::S_PLT, Ctx);
803 OutStreamer->emitInstruction(
804 Inst: MCInstBuilder(SystemZ::BRASL).addReg(Reg: SystemZ::R0D).addExpr(Val: Op),
805 STI: getSubtargetInfo());
806}
807
808void SystemZAsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
809 auto *TII = MF->getSubtarget<SystemZSubtarget>().getInstrInfo();
810
811 unsigned NumNOPBytes = MI.getOperand(i: 1).getImm();
812
813 auto &Ctx = OutStreamer->getContext();
814 MCSymbol *MILabel = Ctx.createTempSymbol();
815 OutStreamer->emitLabel(Symbol: MILabel);
816
817 SM.recordStackMap(L: *MILabel, MI);
818 assert(NumNOPBytes % 2 == 0 && "Invalid number of NOP bytes requested!");
819
820 // Scan ahead to trim the shadow.
821 unsigned ShadowBytes = 0;
822 const MachineBasicBlock &MBB = *MI.getParent();
823 MachineBasicBlock::const_iterator MII(MI);
824 ++MII;
825 while (ShadowBytes < NumNOPBytes) {
826 if (MII == MBB.end() ||
827 MII->getOpcode() == TargetOpcode::PATCHPOINT ||
828 MII->getOpcode() == TargetOpcode::STACKMAP)
829 break;
830 ShadowBytes += TII->getInstSizeInBytes(MI: *MII);
831 if (MII->isCall())
832 break;
833 ++MII;
834 }
835
836 // Emit nops.
837 while (ShadowBytes < NumNOPBytes)
838 ShadowBytes += EmitNop(OutContext, OutStreamer&: *OutStreamer, NumBytes: NumNOPBytes - ShadowBytes,
839 STI: getSubtargetInfo());
840}
841
842// Lower a patchpoint of the form:
843// [<def>], <id>, <numBytes>, <target>, <numArgs>
844void SystemZAsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
845 SystemZMCInstLower &Lower) {
846 auto &Ctx = OutStreamer->getContext();
847 MCSymbol *MILabel = Ctx.createTempSymbol();
848 OutStreamer->emitLabel(Symbol: MILabel);
849
850 SM.recordPatchPoint(L: *MILabel, MI);
851 PatchPointOpers Opers(&MI);
852
853 unsigned EncodedBytes = 0;
854 const MachineOperand &CalleeMO = Opers.getCallTarget();
855
856 if (CalleeMO.isImm()) {
857 uint64_t CallTarget = CalleeMO.getImm();
858 if (CallTarget) {
859 unsigned ScratchIdx = -1;
860 unsigned ScratchReg = 0;
861 do {
862 ScratchIdx = Opers.getNextScratchIdx(StartIdx: ScratchIdx + 1);
863 ScratchReg = MI.getOperand(i: ScratchIdx).getReg();
864 } while (ScratchReg == SystemZ::R0D);
865
866 // Materialize the call target address
867 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::LLILF)
868 .addReg(Reg: ScratchReg)
869 .addImm(Val: CallTarget & 0xFFFFFFFF));
870 EncodedBytes += 6;
871 if (CallTarget >> 32) {
872 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::IIHF)
873 .addReg(Reg: ScratchReg)
874 .addImm(Val: CallTarget >> 32));
875 EncodedBytes += 6;
876 }
877
878 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::BASR)
879 .addReg(Reg: SystemZ::R14D)
880 .addReg(Reg: ScratchReg));
881 EncodedBytes += 2;
882 }
883 } else if (CalleeMO.isGlobal()) {
884 const MCExpr *Expr = Lower.getExpr(MO: CalleeMO, SystemZ::S_PLT);
885 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::BRASL)
886 .addReg(Reg: SystemZ::R14D)
887 .addExpr(Val: Expr));
888 EncodedBytes += 6;
889 }
890
891 // Emit padding.
892 unsigned NumBytes = Opers.getNumPatchBytes();
893 assert(NumBytes >= EncodedBytes &&
894 "Patchpoint can't request size less than the length of a call.");
895 assert((NumBytes - EncodedBytes) % 2 == 0 &&
896 "Invalid number of NOP bytes requested!");
897 while (EncodedBytes < NumBytes)
898 EncodedBytes += EmitNop(OutContext, OutStreamer&: *OutStreamer, NumBytes: NumBytes - EncodedBytes,
899 STI: getSubtargetInfo());
900}
901
902void SystemZAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(
903 const MachineInstr &MI, SystemZMCInstLower &Lower) {
904
905 const MachineFunction &MF = *(MI.getParent()->getParent());
906 const Function &F = MF.getFunction();
907
908 // If patchable-function-entry is set, emit in-function nops here.
909 if (F.hasFnAttribute(Kind: "patchable-function-entry")) {
910 unsigned Num;
911 // get M-N from function attribute (CodeGenFunction subtracts N
912 // from M to yield the correct patchable-function-entry).
913 if (F.getFnAttribute(Kind: "patchable-function-entry")
914 .getValueAsString()
915 .getAsInteger(Radix: 10, Result&: Num))
916 return;
917 // Emit M-N 2-byte nops. Use getNop() here instead of emitNops()
918 // to keep it aligned with the common code implementation emitting
919 // the prefix nops.
920 for (unsigned I = 0; I < Num; ++I)
921 EmitToStreamer(S&: *OutStreamer, Inst: MF.getSubtarget().getInstrInfo()->getNop());
922 return;
923 }
924 // Otherwise, emit xray sled.
925 // .begin:
926 // j .end # -> stmg %r2, %r15, 16(%r15)
927 // nop
928 // llilf %2, FuncID
929 // brasl %r14, __xray_FunctionEntry@GOT
930 // .end:
931 //
932 // Update compiler-rt/lib/xray/xray_s390x.cpp accordingly when number
933 // of instructions change.
934 bool HasVectorFeature =
935 TM.getMCSubtargetInfo()->hasFeature(Feature: SystemZ::FeatureVector) &&
936 !TM.getMCSubtargetInfo()->hasFeature(Feature: SystemZ::FeatureSoftFloat);
937 MCSymbol *FuncEntry = OutContext.getOrCreateSymbol(
938 Name: HasVectorFeature ? "__xray_FunctionEntryVec" : "__xray_FunctionEntry");
939 MCSymbol *BeginOfSled = OutContext.createTempSymbol(Name: "xray_sled_", AlwaysAddSuffix: true);
940 MCSymbol *EndOfSled = OutContext.createTempSymbol();
941 OutStreamer->emitLabel(Symbol: BeginOfSled);
942 EmitToStreamer(S&: *OutStreamer,
943 Inst: MCInstBuilder(SystemZ::J)
944 .addExpr(Val: MCSymbolRefExpr::create(Symbol: EndOfSled, Ctx&: OutContext)));
945 EmitNop(OutContext, OutStreamer&: *OutStreamer, NumBytes: 2, STI: getSubtargetInfo());
946 EmitToStreamer(S&: *OutStreamer,
947 Inst: MCInstBuilder(SystemZ::LLILF).addReg(Reg: SystemZ::R2D).addImm(Val: 0));
948 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::BRASL)
949 .addReg(Reg: SystemZ::R14D)
950 .addExpr(Val: MCSymbolRefExpr::create(
951 Symbol: FuncEntry, specifier: SystemZ::S_PLT, Ctx&: OutContext)));
952 OutStreamer->emitLabel(Symbol: EndOfSled);
953 recordSled(Sled: BeginOfSled, MI, Kind: SledKind::FUNCTION_ENTER, Version: 2);
954}
955
956void SystemZAsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI,
957 SystemZMCInstLower &Lower) {
958 unsigned OpCode = MI.getOperand(i: 0).getImm();
959 MCSymbol *FallthroughLabel = nullptr;
960 if (OpCode == SystemZ::CondReturn) {
961 FallthroughLabel = OutContext.createTempSymbol();
962 int64_t Cond0 = MI.getOperand(i: 1).getImm();
963 int64_t Cond1 = MI.getOperand(i: 2).getImm();
964 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::BRC)
965 .addImm(Val: Cond0)
966 .addImm(Val: Cond1 ^ Cond0)
967 .addExpr(Val: MCSymbolRefExpr::create(
968 Symbol: FallthroughLabel, Ctx&: OutContext)));
969 }
970 // .begin:
971 // br %r14 # -> stmg %r2, %r15, 24(%r15)
972 // nop
973 // nop
974 // llilf %2,FuncID
975 // j __xray_FunctionExit@GOT
976 //
977 // Update compiler-rt/lib/xray/xray_s390x.cpp accordingly when number
978 // of instructions change.
979 bool HasVectorFeature =
980 TM.getMCSubtargetInfo()->hasFeature(Feature: SystemZ::FeatureVector) &&
981 !TM.getMCSubtargetInfo()->hasFeature(Feature: SystemZ::FeatureSoftFloat);
982 MCSymbol *FuncExit = OutContext.getOrCreateSymbol(
983 Name: HasVectorFeature ? "__xray_FunctionExitVec" : "__xray_FunctionExit");
984 MCSymbol *BeginOfSled = OutContext.createTempSymbol(Name: "xray_sled_", AlwaysAddSuffix: true);
985 OutStreamer->emitLabel(Symbol: BeginOfSled);
986 EmitToStreamer(S&: *OutStreamer,
987 Inst: MCInstBuilder(SystemZ::BR).addReg(Reg: SystemZ::R14D));
988 EmitNop(OutContext, OutStreamer&: *OutStreamer, NumBytes: 4, STI: getSubtargetInfo());
989 EmitToStreamer(S&: *OutStreamer,
990 Inst: MCInstBuilder(SystemZ::LLILF).addReg(Reg: SystemZ::R2D).addImm(Val: 0));
991 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::J)
992 .addExpr(Val: MCSymbolRefExpr::create(
993 Symbol: FuncExit, specifier: SystemZ::S_PLT, Ctx&: OutContext)));
994 if (FallthroughLabel)
995 OutStreamer->emitLabel(Symbol: FallthroughLabel);
996 recordSled(Sled: BeginOfSled, MI, Kind: SledKind::FUNCTION_EXIT, Version: 2);
997}
998
999// The *alignment* of 128-bit vector types is different between the software
1000// and hardware vector ABIs. If the there is an externally visible use of a
1001// vector type in the module it should be annotated with an attribute.
1002void SystemZAsmPrinter::emitAttributes(Module &M) {
1003 if (M.getModuleFlag(Key: "s390x-visible-vector-ABI")) {
1004 bool HasVectorFeature =
1005 TM.getMCSubtargetInfo()->hasFeature(Feature: SystemZ::FeatureVector);
1006 OutStreamer->emitGNUAttribute(Tag: 8, Value: HasVectorFeature ? 2 : 1);
1007 }
1008}
1009
1010// Convert a SystemZ-specific constant pool modifier into the associated
1011// specifier.
1012static uint8_t getSpecifierFromModifier(SystemZCP::SystemZCPModifier Modifier) {
1013 switch (Modifier) {
1014 case SystemZCP::TLSGD:
1015 return SystemZ::S_TLSGD;
1016 case SystemZCP::TLSLDM:
1017 return SystemZ::S_TLSLDM;
1018 case SystemZCP::DTPOFF:
1019 return SystemZ::S_DTPOFF;
1020 case SystemZCP::NTPOFF:
1021 return SystemZ::S_NTPOFF;
1022 }
1023 llvm_unreachable("Invalid SystemCPModifier!");
1024}
1025
1026void SystemZAsmPrinter::emitMachineConstantPoolValue(
1027 MachineConstantPoolValue *MCPV) {
1028 auto *ZCPV = static_cast<SystemZConstantPoolValue*>(MCPV);
1029
1030 const MCExpr *Expr = MCSymbolRefExpr::create(
1031 Symbol: getSymbol(GV: ZCPV->getGlobalValue()),
1032 specifier: getSpecifierFromModifier(Modifier: ZCPV->getModifier()), Ctx&: OutContext);
1033 uint64_t Size = getDataLayout().getTypeAllocSize(Ty: ZCPV->getType());
1034
1035 OutStreamer->emitValue(Value: Expr, Size);
1036}
1037
1038// Emit the ctor or dtor list taking into account the init priority.
1039void SystemZAsmPrinter::emitXXStructorList(const DataLayout &DL,
1040 const Constant *List, bool IsCtor) {
1041 if (!TM.getTargetTriple().isOSBinFormatGOFF())
1042 return AsmPrinter::emitXXStructorList(DL, List, IsCtor);
1043
1044 SmallVector<Structor, 8> Structors;
1045 preprocessXXStructorList(DL, List, Structors);
1046 if (Structors.empty())
1047 return;
1048
1049 const Align Align = llvm::Align(4);
1050 const TargetLoweringObjectFileGOFF &Obj =
1051 static_cast<const TargetLoweringObjectFileGOFF &>(getObjFileLowering());
1052 for (Structor &S : Structors) {
1053 MCSectionGOFF *Section =
1054 static_cast<MCSectionGOFF *>(Obj.getStaticXtorSection(Priority: S.Priority));
1055 OutStreamer->switchSection(Section);
1056 if (OutStreamer->getCurrentSection() != OutStreamer->getPreviousSection())
1057 emitAlignment(Alignment: Align);
1058
1059 // The priority is provided as an input to getStaticXtorSection(), and is
1060 // recalculated within that function as `Prio` going to going into the
1061 // PR section.
1062 // This priority retrieved via the `SortKey` below is the recalculated
1063 // Priority.
1064 uint32_t XtorPriority = Section->getPRAttributes().SortKey;
1065
1066 const GlobalValue *GV = dyn_cast<GlobalValue>(Val: S.Func->stripPointerCasts());
1067 assert(GV && "C++ xxtor pointer was not a GlobalValue!");
1068 MCSymbolGOFF *Symbol = static_cast<MCSymbolGOFF *>(getSymbol(GV));
1069
1070 // @@SQINIT entry: { unsigned prio; void (*ctor)(); void (*dtor)(); }
1071
1072 unsigned PointerSizeInBytes = DL.getPointerSize();
1073
1074 auto &Ctx = OutStreamer->getContext();
1075 const MCExpr *ADAFuncRefExpr;
1076 unsigned SlotKind = SystemZII::MO_ADA_DIRECT_FUNC_DESC;
1077
1078 MCSectionGOFF *ADASection =
1079 static_cast<MCSectionGOFF *>(Obj.getADASection());
1080 assert(ADASection && "ADA section must exist for GOFF targets!");
1081 const MCSymbol *ADASym = ADASection->getBeginSymbol();
1082 assert(ADASym && "ADA symbol should already be set!");
1083
1084 ADAFuncRefExpr = MCBinaryExpr::createAdd(
1085 LHS: MCSpecifierExpr::create(Expr: MCSymbolRefExpr::create(Symbol: ADASym, Ctx&: OutContext),
1086 S: SystemZ::S_QCon, Ctx&: OutContext),
1087 RHS: MCConstantExpr::create(Value: ADATable.insert(Sym: Symbol, SlotKind), Ctx), Ctx);
1088
1089 emitInt32(Value: XtorPriority);
1090 if (IsCtor) {
1091 OutStreamer->emitValue(Value: ADAFuncRefExpr, Size: PointerSizeInBytes);
1092 OutStreamer->emitIntValue(Value: 0, Size: PointerSizeInBytes);
1093 } else {
1094 OutStreamer->emitIntValue(Value: 0, Size: PointerSizeInBytes);
1095 OutStreamer->emitValue(Value: ADAFuncRefExpr, Size: PointerSizeInBytes);
1096 }
1097 }
1098}
1099
1100static void printFormattedRegName(const MCAsmInfo *MAI, unsigned RegNo,
1101 raw_ostream &OS) {
1102 const char *RegName;
1103 if (MAI->getAssemblerDialect() == AD_HLASM) {
1104 RegName = SystemZHLASMInstPrinter::getRegisterName(Reg: RegNo);
1105 // Skip register prefix so that only register number is left
1106 assert(isalpha(RegName[0]) && isdigit(RegName[1]));
1107 OS << (RegName + 1);
1108 } else {
1109 RegName = SystemZGNUInstPrinter::getRegisterName(Reg: RegNo);
1110 OS << '%' << RegName;
1111 }
1112}
1113
1114static void printReg(unsigned Reg, const MCAsmInfo *MAI, raw_ostream &OS) {
1115 if (!Reg)
1116 OS << '0';
1117 else
1118 printFormattedRegName(MAI, RegNo: Reg, OS);
1119}
1120
1121static void printOperand(const MCOperand &MCOp, const MCAsmInfo *MAI,
1122 raw_ostream &OS) {
1123 if (MCOp.isReg())
1124 printReg(Reg: MCOp.getReg(), MAI, OS);
1125 else if (MCOp.isImm())
1126 OS << MCOp.getImm();
1127 else if (MCOp.isExpr())
1128 MAI->printExpr(OS, *MCOp.getExpr());
1129 else
1130 llvm_unreachable("Invalid operand");
1131}
1132
1133static void printAddress(const MCAsmInfo *MAI, unsigned Base,
1134 const MCOperand &DispMO, unsigned Index,
1135 raw_ostream &OS) {
1136 printOperand(MCOp: DispMO, MAI, OS);
1137 if (Base || Index) {
1138 OS << '(';
1139 if (Index) {
1140 printFormattedRegName(MAI, RegNo: Index, OS);
1141 if (Base)
1142 OS << ',';
1143 }
1144 if (Base)
1145 printFormattedRegName(MAI, RegNo: Base, OS);
1146 OS << ')';
1147 }
1148}
1149
1150bool SystemZAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
1151 const char *ExtraCode,
1152 raw_ostream &OS) {
1153 const MCRegisterInfo &MRI = *TM.getMCRegisterInfo();
1154 const MachineOperand &MO = MI->getOperand(i: OpNo);
1155 MCOperand MCOp;
1156 if (ExtraCode) {
1157 if (ExtraCode[0] == 'N' && !ExtraCode[1] && MO.isReg() &&
1158 SystemZ::GR128BitRegClass.contains(Reg: MO.getReg()))
1159 MCOp =
1160 MCOperand::createReg(Reg: MRI.getSubReg(Reg: MO.getReg(), Idx: SystemZ::subreg_l64));
1161 else
1162 return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS);
1163 } else {
1164 SystemZMCInstLower Lower(MF->getContext(), *this);
1165 MCOp = Lower.lowerOperand(MO);
1166 }
1167 printOperand(MCOp, MAI, OS);
1168 return false;
1169}
1170
1171bool SystemZAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1172 unsigned OpNo,
1173 const char *ExtraCode,
1174 raw_ostream &OS) {
1175 if (ExtraCode && ExtraCode[0] && !ExtraCode[1]) {
1176 switch (ExtraCode[0]) {
1177 case 'A':
1178 // Unlike EmitMachineNode(), EmitSpecialNode(INLINEASM) does not call
1179 // setMemRefs(), so MI->memoperands() is empty and the alignment
1180 // information is not available.
1181 return false;
1182 case 'O':
1183 OS << MI->getOperand(i: OpNo + 1).getImm();
1184 return false;
1185 case 'R':
1186 ::printReg(Reg: MI->getOperand(i: OpNo).getReg(), MAI, OS);
1187 return false;
1188 }
1189 }
1190 printAddress(MAI, Base: MI->getOperand(i: OpNo).getReg(),
1191 DispMO: MCOperand::createImm(Val: MI->getOperand(i: OpNo + 1).getImm()),
1192 Index: MI->getOperand(i: OpNo + 2).getReg(), OS);
1193 return false;
1194}
1195
1196void SystemZAsmPrinter::emitEndOfAsmFile(Module &M) {
1197 auto TT = OutContext.getTargetTriple();
1198 if (TT.isOSzOS()) {
1199 emitADASection();
1200 emitIDRLSection(M);
1201 }
1202 emitAttributes(M);
1203}
1204
1205void SystemZAsmPrinter::emitADASection() {
1206 OutStreamer->pushSection();
1207
1208 const unsigned PointerSize = getDataLayout().getPointerSize();
1209 OutStreamer->switchSection(Section: getObjFileLowering().getADASection());
1210
1211 unsigned EmittedBytes = 0;
1212 for (auto &Entry : ADATable.getTable()) {
1213 const MCSymbol *Sym;
1214 unsigned SlotKind;
1215 std::tie(args&: Sym, args&: SlotKind) = Entry.first;
1216 unsigned Offset = Entry.second;
1217 assert(Offset == EmittedBytes && "Offset not as expected");
1218 (void)EmittedBytes;
1219#define EMIT_COMMENT(Str) \
1220 OutStreamer->AddComment(Twine("Offset ") \
1221 .concat(utostr(Offset)) \
1222 .concat(" " Str " ") \
1223 .concat(Sym->getName()));
1224 switch (SlotKind) {
1225 case SystemZII::MO_ADA_DIRECT_FUNC_DESC:
1226 // Language Environment DLL logic requires function descriptors, for
1227 // imported functions, that are placed in the ADA to be 8 byte aligned.
1228 EMIT_COMMENT("function descriptor of");
1229 OutStreamer->emitValue(
1230 Value: MCSpecifierExpr::create(Expr: MCSymbolRefExpr::create(Symbol: Sym, Ctx&: OutContext),
1231 S: SystemZ::S_RCon, Ctx&: OutContext),
1232 Size: PointerSize);
1233 OutStreamer->emitValue(
1234 Value: MCSpecifierExpr::create(Expr: MCSymbolRefExpr::create(Symbol: Sym, Ctx&: OutContext),
1235 S: SystemZ::S_VCon, Ctx&: OutContext),
1236 Size: PointerSize);
1237 EmittedBytes += PointerSize * 2;
1238 break;
1239 case SystemZII::MO_ADA_DATA_SYMBOL_ADDR:
1240 EMIT_COMMENT("pointer to data symbol");
1241 OutStreamer->emitValue(
1242 Value: MCSpecifierExpr::create(Expr: MCSymbolRefExpr::create(Symbol: Sym, Ctx&: OutContext),
1243 S: SystemZ::S_None, Ctx&: OutContext),
1244 Size: PointerSize);
1245 EmittedBytes += PointerSize;
1246 break;
1247 case SystemZII::MO_ADA_INDIRECT_FUNC_DESC: {
1248 MCSymbol *Alias = OutContext.createTempSymbol(
1249 Name: Twine(Sym->getName()).concat(Suffix: "@indirect"));
1250 OutStreamer->emitAssignment(Symbol: Alias,
1251 Value: MCSymbolRefExpr::create(Symbol: Sym, Ctx&: OutContext));
1252 OutStreamer->emitSymbolAttribute(Symbol: Alias, Attribute: MCSA_IndirectSymbol);
1253
1254 EMIT_COMMENT("pointer to function descriptor");
1255 OutStreamer->emitValue(
1256 Value: MCSpecifierExpr::create(Expr: MCSymbolRefExpr::create(Symbol: Alias, Ctx&: OutContext),
1257 S: SystemZ::S_VCon, Ctx&: OutContext),
1258 Size: PointerSize);
1259 EmittedBytes += PointerSize;
1260 break;
1261 }
1262 default:
1263 llvm_unreachable("Unexpected slot kind");
1264 }
1265#undef EMIT_COMMENT
1266 }
1267 OutStreamer->popSection();
1268}
1269
1270static std::string getProductID(Module &M) {
1271 std::string ProductID;
1272 if (auto *MD = M.getModuleFlag(Key: "zos_product_id"))
1273 ProductID = cast<MDString>(Val: MD)->getString().str();
1274 if (ProductID.empty())
1275 ProductID = "LLVM";
1276 return ProductID;
1277}
1278
1279static uint32_t getProductVersion(Module &M) {
1280 if (auto *VersionVal = mdconst::extract_or_null<ConstantInt>(
1281 MD: M.getModuleFlag(Key: "zos_product_major_version")))
1282 return VersionVal->getZExtValue();
1283 return LLVM_VERSION_MAJOR;
1284}
1285
1286static uint32_t getProductRelease(Module &M) {
1287 if (auto *ReleaseVal = mdconst::extract_or_null<ConstantInt>(
1288 MD: M.getModuleFlag(Key: "zos_product_minor_version")))
1289 return ReleaseVal->getZExtValue();
1290 return LLVM_VERSION_MINOR;
1291}
1292
1293static uint32_t getProductPatch(Module &M) {
1294 if (auto *PatchVal = mdconst::extract_or_null<ConstantInt>(
1295 MD: M.getModuleFlag(Key: "zos_product_patchlevel")))
1296 return PatchVal->getZExtValue();
1297 return LLVM_VERSION_PATCH;
1298}
1299
1300static time_t getTranslationTime(Module &M) {
1301 std::time_t Time = 0;
1302 if (auto *Val = mdconst::extract_or_null<ConstantInt>(
1303 MD: M.getModuleFlag(Key: "zos_translation_time"))) {
1304 long SecondsSinceEpoch = Val->getSExtValue();
1305 Time = static_cast<time_t>(SecondsSinceEpoch);
1306 }
1307 return Time;
1308}
1309
1310void SystemZAsmPrinter::emitIDRLSection(Module &M) {
1311 OutStreamer->pushSection();
1312 OutStreamer->switchSection(Section: getObjFileLowering().getIDRLSection());
1313 constexpr unsigned IDRLDataLength = 30;
1314 std::time_t Time = getTranslationTime(M);
1315
1316 uint32_t ProductVersion = getProductVersion(M);
1317 uint32_t ProductRelease = getProductRelease(M);
1318
1319 std::string ProductID = getProductID(M);
1320
1321 SmallString<IDRLDataLength + 1> TempStr;
1322 raw_svector_ostream O(TempStr);
1323 O << formatv(Fmt: "{0,-10}{1,0-2:d}{2,0-2:d}{3:%Y%m%d%H%M%S}{4,0-2}",
1324 Vals: ProductID.substr(pos: 0, n: 10).c_str(), Vals&: ProductVersion, Vals&: ProductRelease,
1325 Vals: llvm::sys::toUtcTime(T: Time), Vals: "0");
1326 SmallString<IDRLDataLength> Data;
1327 ConverterEBCDIC::convertToEBCDIC(Source: TempStr, Result&: Data);
1328
1329 OutStreamer->emitInt8(Value: 0); // Reserved.
1330 OutStreamer->emitInt8(Value: 3); // Format.
1331 OutStreamer->emitInt16(Value: IDRLDataLength); // Length.
1332 OutStreamer->emitBytes(Data: Data.str());
1333 OutStreamer->popSection();
1334}
1335
1336void SystemZAsmPrinter::emitFunctionBodyEnd() {
1337 if (TM.getTargetTriple().isOSzOS()) {
1338 // Emit symbol for the end of function if the z/OS target streamer
1339 // is used. This is needed to calculate the size of the function.
1340 MCSymbol *FnEndSym = createTempSymbol(Name: "func_end");
1341 OutStreamer->emitLabel(Symbol: FnEndSym);
1342
1343 OutStreamer->pushSection();
1344 OutStreamer->switchSection(Section: getObjFileLowering().getTextSection(),
1345 Subsec: GOFF::SK_PPA1);
1346 emitPPA1(FnEndSym);
1347 OutStreamer->popSection();
1348
1349 CurrentFnPPA1Sym = nullptr;
1350 CurrentFnEPMarkerSym = nullptr;
1351 }
1352}
1353
1354static void emitPPA1Flags(std::unique_ptr<MCStreamer> &OutStreamer, bool VarArg,
1355 bool StackProtector, bool FPRMask, bool VRMask,
1356 bool EHBlock, bool HasArgAreaLength, bool HasName) {
1357 enum class PPA1Flag1 : uint8_t {
1358 DSA64Bit = (0x80 >> 0),
1359 VarArg = (0x80 >> 7),
1360 LLVM_MARK_AS_BITMASK_ENUM(DSA64Bit)
1361 };
1362 enum class PPA1Flag2 : uint8_t {
1363 ExternalProcedure = (0x80 >> 0),
1364 STACKPROTECTOR = (0x80 >> 3),
1365 LLVM_MARK_AS_BITMASK_ENUM(ExternalProcedure)
1366 };
1367 enum class PPA1Flag3 : uint8_t {
1368 HasArgAreaLength = (0x80 >> 1),
1369 FPRMask = (0x80 >> 2),
1370 LLVM_MARK_AS_BITMASK_ENUM(HasArgAreaLength)
1371 };
1372 enum class PPA1Flag4 : uint8_t {
1373 EPMOffsetPresent = (0x80 >> 0),
1374 VRMask = (0x80 >> 2),
1375 EHBlock = (0x80 >> 3),
1376 ProcedureNamePresent = (0x80 >> 7),
1377 LLVM_MARK_AS_BITMASK_ENUM(EPMOffsetPresent)
1378 };
1379
1380 // Declare optional section flags that can be modified.
1381 auto Flags1 = PPA1Flag1(0);
1382 auto Flags2 = PPA1Flag2::ExternalProcedure;
1383 auto Flags3 = PPA1Flag3(0);
1384 auto Flags4 = PPA1Flag4::EPMOffsetPresent;
1385
1386 Flags1 |= PPA1Flag1::DSA64Bit;
1387
1388 if (VarArg)
1389 Flags1 |= PPA1Flag1::VarArg;
1390
1391 if (StackProtector)
1392 Flags2 |= PPA1Flag2::STACKPROTECTOR;
1393
1394 if (HasArgAreaLength)
1395 Flags3 |= PPA1Flag3::HasArgAreaLength; // Add emit ArgAreaLength flag.
1396
1397 // SavedGPRMask, SavedFPRMask, and SavedVRMask are precomputed in.
1398 if (FPRMask)
1399 Flags3 |= PPA1Flag3::FPRMask; // Add emit FPR mask flag.
1400
1401 if (VRMask)
1402 Flags4 |= PPA1Flag4::VRMask; // Add emit VR mask flag.
1403
1404 if (EHBlock)
1405 Flags4 |= PPA1Flag4::EHBlock; // Add optional EH block.
1406
1407 if (HasName)
1408 Flags4 |= PPA1Flag4::ProcedureNamePresent; // Add optional name block.
1409
1410 OutStreamer->AddComment(T: "PPA1 Flags 1");
1411 if ((Flags1 & PPA1Flag1::DSA64Bit) == PPA1Flag1::DSA64Bit)
1412 OutStreamer->AddComment(T: " Bit 0: 1 = 64-bit DSA");
1413 else
1414 OutStreamer->AddComment(T: " Bit 0: 0 = 32-bit DSA");
1415 if ((Flags1 & PPA1Flag1::VarArg) == PPA1Flag1::VarArg)
1416 OutStreamer->AddComment(T: " Bit 7: 1 = Vararg function");
1417 OutStreamer->emitInt8(Value: static_cast<uint8_t>(Flags1)); // Flags 1.
1418
1419 OutStreamer->AddComment(T: "PPA1 Flags 2");
1420 if ((Flags2 & PPA1Flag2::ExternalProcedure) == PPA1Flag2::ExternalProcedure)
1421 OutStreamer->AddComment(T: " Bit 0: 1 = External procedure");
1422 if ((Flags2 & PPA1Flag2::STACKPROTECTOR) == PPA1Flag2::STACKPROTECTOR)
1423 OutStreamer->AddComment(T: " Bit 3: 1 = STACKPROTECT is enabled");
1424 else
1425 OutStreamer->AddComment(T: " Bit 3: 0 = STACKPROTECT is not enabled");
1426 OutStreamer->emitInt8(Value: static_cast<uint8_t>(Flags2)); // Flags 2.
1427
1428 OutStreamer->AddComment(T: "PPA1 Flags 3");
1429 if ((Flags3 & PPA1Flag3::HasArgAreaLength) == PPA1Flag3::HasArgAreaLength)
1430 OutStreamer->AddComment(
1431 T: " Bit 1: 1 = Argument Area Length is in optional area");
1432 if ((Flags3 & PPA1Flag3::FPRMask) == PPA1Flag3::FPRMask)
1433 OutStreamer->AddComment(T: " Bit 2: 1 = FP Reg Mask is in optional area");
1434 OutStreamer->emitInt8(
1435 Value: static_cast<uint8_t>(Flags3)); // Flags 3 (optional sections).
1436
1437 OutStreamer->AddComment(T: "PPA1 Flags 4");
1438 if ((Flags4 & PPA1Flag4::VRMask) == PPA1Flag4::VRMask)
1439 OutStreamer->AddComment(T: " Bit 2: 1 = Vector Reg Mask is in optional area");
1440 if ((Flags4 & PPA1Flag4::EHBlock) == PPA1Flag4::EHBlock)
1441 OutStreamer->AddComment(T: " Bit 3: 1 = C++ EH block");
1442 if ((Flags4 & PPA1Flag4::ProcedureNamePresent) ==
1443 PPA1Flag4::ProcedureNamePresent)
1444 OutStreamer->AddComment(T: " Bit 7: 1 = Name Length and Name");
1445 OutStreamer->emitInt8(Value: static_cast<uint8_t>(
1446 Flags4)); // Flags 4 (optional sections, always emit these).
1447}
1448
1449static void emitPPA1Name(std::unique_ptr<MCStreamer> &OutStreamer,
1450 StringRef OutName) {
1451 size_t NameSize = OutName.size();
1452 uint16_t OutSize;
1453 if (NameSize < UINT16_MAX) {
1454 OutSize = static_cast<uint16_t>(NameSize);
1455 } else {
1456 OutName = OutName.substr(Start: 0, UINT16_MAX);
1457 OutSize = UINT16_MAX;
1458 }
1459 // Emit padding to ensure that the next optional field word-aligned.
1460 uint8_t ExtraZeros = 4 - ((2 + OutSize) % 4);
1461
1462 SmallString<512> OutnameConv;
1463 ConverterEBCDIC::convertToEBCDIC(Source: OutName, Result&: OutnameConv);
1464 OutName = OutnameConv.str();
1465
1466 OutStreamer->AddComment(T: "Length of Name");
1467 OutStreamer->emitInt16(Value: OutSize);
1468 OutStreamer->AddComment(T: "Name of Function");
1469 OutStreamer->emitBytes(Data: OutName);
1470 OutStreamer->emitZeros(NumBytes: ExtraZeros);
1471}
1472
1473void SystemZAsmPrinter::emitPPA1(MCSymbol *FnEndSym) {
1474 assert(PPA2Sym != nullptr && "PPA2 Symbol not defined");
1475
1476 const TargetRegisterInfo *TRI = MF->getRegInfo().getTargetRegisterInfo();
1477 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
1478 const auto TargetHasVector = Subtarget.hasVector();
1479
1480 const SystemZMachineFunctionInfo *ZFI =
1481 MF->getInfo<SystemZMachineFunctionInfo>();
1482 const auto *ZFL = static_cast<const SystemZXPLINKFrameLowering *>(
1483 Subtarget.getFrameLowering());
1484 const MachineFrameInfo &MFFrame = MF->getFrameInfo();
1485
1486 // Get saved GPR/FPR/VPR masks.
1487 const std::vector<CalleeSavedInfo> &CSI = MFFrame.getCalleeSavedInfo();
1488 uint16_t SavedGPRMask = 0;
1489 uint16_t SavedFPRMask = 0;
1490 uint8_t SavedVRMask = 0;
1491 int64_t OffsetFPR = 0;
1492 int64_t OffsetVR = 0;
1493 const int64_t TopOfStack =
1494 MFFrame.getOffsetAdjustment() + MFFrame.getStackSize();
1495
1496 // Loop over the spilled registers. The CalleeSavedInfo can't be used because
1497 // it does not contain all spilled registers.
1498 for (unsigned I = ZFI->getSpillGPRRegs().LowGPR,
1499 E = ZFI->getSpillGPRRegs().HighGPR;
1500 I && E && I <= E; ++I) {
1501 unsigned V = TRI->getEncodingValue(Reg: (Register)I);
1502 assert(V < 16 && "GPR index out of range");
1503 SavedGPRMask |= 1 << (15 - V);
1504 }
1505
1506 for (auto &CS : CSI) {
1507 unsigned Reg = CS.getReg();
1508 unsigned I = TRI->getEncodingValue(Reg);
1509
1510 if (SystemZ::FP64BitRegClass.contains(Reg)) {
1511 assert(I < 16 && "FPR index out of range");
1512 SavedFPRMask |= 1 << (15 - I);
1513 int64_t Temp = MFFrame.getObjectOffset(ObjectIdx: CS.getFrameIdx());
1514 if (Temp < OffsetFPR)
1515 OffsetFPR = Temp;
1516 } else if (SystemZ::VR128BitRegClass.contains(Reg)) {
1517 assert(I >= 16 && I <= 23 && "VPR index out of range");
1518 unsigned BitNum = I - 16;
1519 SavedVRMask |= 1 << (7 - BitNum);
1520 int64_t Temp = MFFrame.getObjectOffset(ObjectIdx: CS.getFrameIdx());
1521 if (Temp < OffsetVR)
1522 OffsetVR = Temp;
1523 }
1524 }
1525
1526 // Adjust the offset.
1527 OffsetFPR += (OffsetFPR < 0) ? TopOfStack : 0;
1528 OffsetVR += (OffsetVR < 0) ? TopOfStack : 0;
1529
1530 // Get alloca register.
1531 uint8_t FrameReg = TRI->getEncodingValue(Reg: TRI->getFrameRegister(MF: *MF));
1532 uint8_t AllocaReg = ZFL->hasFP(MF: *MF) ? FrameReg : 0;
1533 assert(AllocaReg < 16 && "Can't have alloca register larger than 15");
1534 (void)AllocaReg;
1535
1536 // Build FPR save area offset.
1537 uint32_t FrameAndFPROffset = 0;
1538 if (SavedFPRMask) {
1539 uint64_t FPRSaveAreaOffset = OffsetFPR;
1540 assert(FPRSaveAreaOffset < 0x10000000 && "Offset out of range");
1541
1542 FrameAndFPROffset = FPRSaveAreaOffset & 0x0FFFFFFF; // Lose top 4 bits.
1543 FrameAndFPROffset |= FrameReg << 28; // Put into top 4 bits.
1544 }
1545
1546 // Build VR save area offset.
1547 uint32_t FrameAndVROffset = 0;
1548 if (TargetHasVector && SavedVRMask) {
1549 uint64_t VRSaveAreaOffset = OffsetVR;
1550 assert(VRSaveAreaOffset < 0x10000000 && "Offset out of range");
1551
1552 FrameAndVROffset = VRSaveAreaOffset & 0x0FFFFFFF; // Lose top 4 bits.
1553 FrameAndVROffset |= FrameReg << 28; // Put into top 4 bits.
1554 }
1555
1556 // Emit PPA1 section.
1557 OutStreamer->AddComment(T: "PPA1");
1558 OutStreamer->emitLabel(Symbol: CurrentFnPPA1Sym);
1559 OutStreamer->AddComment(T: "Version");
1560 OutStreamer->emitInt8(Value: 0x02); // Version.
1561 OutStreamer->AddComment(T: "LE Signature X'CE'");
1562 OutStreamer->emitInt8(Value: 0xCE); // CEL signature.
1563 OutStreamer->AddComment(T: "Saved GPR Mask");
1564 OutStreamer->emitInt16(Value: SavedGPRMask);
1565 OutStreamer->AddComment(T: "Offset to PPA2");
1566 OutStreamer->emitAbsoluteSymbolDiff(Hi: PPA2Sym, Lo: CurrentFnPPA1Sym, Size: 4);
1567
1568 bool NeedEmitEHBlock = !MF->getLandingPads().empty();
1569
1570 // Optional Argument Area Length.
1571 // Note: This represents the length of the argument area that we reserve
1572 // in our stack for setting up arguments for calls to other
1573 // routines. If this optional field is not set, LE will reserve
1574 // 128 bytes for the argument area. This optional field is
1575 // created if greater than 128 bytes is required - to guarantee
1576 // the required space is reserved on stack extension in the new
1577 // extension. This optional field is also created if the
1578 // routine has alloca(). This may reduce stack space
1579 // if alloca() call causes a stack extension.
1580 bool HasArgAreaLength =
1581 (AllocaReg != 0) || (MFFrame.getMaxCallFrameSize() > 128);
1582
1583 bool HasName =
1584 MF->getFunction().hasName() && MF->getFunction().getName().size() > 0;
1585
1586 emitPPA1Flags(OutStreamer, VarArg: MF->getFunction().isVarArg(),
1587 StackProtector: MFFrame.hasStackProtectorIndex(), FPRMask: SavedFPRMask != 0,
1588 VRMask: TargetHasVector && SavedVRMask != 0, EHBlock: NeedEmitEHBlock,
1589 HasArgAreaLength, HasName);
1590
1591 OutStreamer->AddComment(T: "Length/4 of Parms");
1592 OutStreamer->emitInt16(
1593 Value: static_cast<uint16_t>(ZFI->getSizeOfFnParams() / 4)); // Parms/4.
1594 OutStreamer->AddComment(T: "Length of Code");
1595 OutStreamer->emitAbsoluteSymbolDiff(Hi: FnEndSym, Lo: CurrentFnEPMarkerSym, Size: 4);
1596
1597 if (HasArgAreaLength) {
1598 OutStreamer->AddComment(T: "Argument Area Length");
1599 OutStreamer->emitInt32(Value: MFFrame.getMaxCallFrameSize());
1600 }
1601
1602 // Emit saved FPR mask and offset to FPR save area (0x20 of flags 3).
1603 if (SavedFPRMask) {
1604 OutStreamer->AddComment(T: "FPR mask");
1605 OutStreamer->emitInt16(Value: SavedFPRMask);
1606 OutStreamer->AddComment(T: "AR mask");
1607 OutStreamer->emitInt16(Value: 0); // AR Mask, unused currently.
1608 OutStreamer->AddComment(T: "FPR Save Area Locator");
1609 OutStreamer->AddComment(T: Twine(" Bit 0-3: Register R")
1610 .concat(Suffix: utostr(X: FrameAndFPROffset >> 28))
1611 .str());
1612 OutStreamer->AddComment(T: Twine(" Bit 4-31: Offset ")
1613 .concat(Suffix: utostr(X: FrameAndFPROffset & 0x0FFFFFFF))
1614 .str());
1615 OutStreamer->emitInt32(Value: FrameAndFPROffset); // Offset to FPR save area with
1616 // register to add value to
1617 // (alloca reg).
1618 }
1619
1620 // Emit saved VR mask to VR save area.
1621 if (TargetHasVector && SavedVRMask) {
1622 OutStreamer->AddComment(T: "VR mask");
1623 OutStreamer->emitInt8(Value: SavedVRMask);
1624 OutStreamer->emitInt8(Value: 0); // Reserved.
1625 OutStreamer->emitInt16(Value: 0); // Also reserved.
1626 OutStreamer->AddComment(T: "VR Save Area Locator");
1627 OutStreamer->AddComment(T: Twine(" Bit 0-3: Register R")
1628 .concat(Suffix: utostr(X: FrameAndVROffset >> 28))
1629 .str());
1630 OutStreamer->AddComment(T: Twine(" Bit 4-31: Offset ")
1631 .concat(Suffix: utostr(X: FrameAndVROffset & 0x0FFFFFFF))
1632 .str());
1633 OutStreamer->emitInt32(Value: FrameAndVROffset);
1634 }
1635
1636 // Emit C++ EH information block
1637 const Function *Per = nullptr;
1638 if (NeedEmitEHBlock) {
1639 Per = dyn_cast<Function>(
1640 Val: MF->getFunction().getPersonalityFn()->stripPointerCasts());
1641 MCSymbol *PersonalityRoutine =
1642 Per ? MF->getTarget().getSymbol(GV: Per) : nullptr;
1643 assert(PersonalityRoutine && "Missing personality routine");
1644
1645 OutStreamer->AddComment(T: "Version");
1646 OutStreamer->emitInt32(Value: 1);
1647 OutStreamer->AddComment(T: "Flags");
1648 OutStreamer->emitInt32(Value: 0); // LSDA field is a WAS offset
1649 OutStreamer->AddComment(T: "Personality routine");
1650 OutStreamer->emitInt64(Value: ADATable.insert(
1651 Sym: PersonalityRoutine, SlotKind: SystemZII::MO_ADA_INDIRECT_FUNC_DESC));
1652 OutStreamer->AddComment(T: "LSDA location");
1653 MCSymbol *GCCEH = MF->getContext().getOrCreateSymbol(
1654 Name: Twine("GCC_except_table") + Twine(MF->getFunctionNumber()));
1655 OutStreamer->emitInt64(
1656 Value: ADATable.insert(Sym: GCCEH, SlotKind: SystemZII::MO_ADA_DATA_SYMBOL_ADDR));
1657 }
1658
1659 // Emit name length and name optional section (0x01 of flags 4)
1660 if (HasName)
1661 emitPPA1Name(OutStreamer, OutName: MF->getFunction().getName());
1662
1663 // Emit offset to entry point optional section (0x80 of flags 4).
1664 OutStreamer->emitAbsoluteSymbolDiff(Hi: CurrentFnEPMarkerSym, Lo: CurrentFnPPA1Sym,
1665 Size: 4);
1666}
1667
1668void SystemZAsmPrinter::emitStartOfAsmFile(Module &M) {
1669 if (TM.getTargetTriple().isOSzOS())
1670 emitPPA2(M);
1671 AsmPrinter::emitStartOfAsmFile(M);
1672}
1673
1674void SystemZAsmPrinter::emitPPA2(Module &M) {
1675 OutStreamer->pushSection();
1676 OutStreamer->switchSection(Section: getObjFileLowering().getTextSection(),
1677 Subsec: GOFF::SK_PPA2);
1678 MCContext &OutContext = OutStreamer->getContext();
1679 // Make CELQSTRT symbol.
1680 const char *StartSymbolName = "CELQSTRT";
1681 MCSymbol *CELQSTRT = OutContext.getOrCreateSymbol(Name: StartSymbolName);
1682 OutStreamer->emitSymbolAttribute(Symbol: CELQSTRT, Attribute: MCSA_OSLinkage);
1683 OutStreamer->emitSymbolAttribute(Symbol: CELQSTRT, Attribute: MCSA_Global);
1684
1685 // Create symbol and assign to class field for use in PPA1.
1686 PPA2Sym = OutContext.createTempSymbol(Name: "PPA2", AlwaysAddSuffix: false);
1687 MCSymbol *DateVersionSym = OutContext.createTempSymbol(Name: "DVS", AlwaysAddSuffix: false);
1688
1689 std::time_t Time = getTranslationTime(M);
1690 SmallString<14> CompilationTimeEBCDIC, CompilationTime;
1691 CompilationTime = formatv(Fmt: "{0:%Y%m%d%H%M%S}", Vals: llvm::sys::toUtcTime(T: Time));
1692
1693 uint32_t ProductVersion = getProductVersion(M),
1694 ProductRelease = getProductRelease(M),
1695 ProductPatch = getProductPatch(M);
1696
1697 SmallString<6> VersionEBCDIC, Version;
1698 Version = formatv(Fmt: "{0,0-2:d}{1,0-2:d}{2,0-2:d}", Vals&: ProductVersion,
1699 Vals&: ProductRelease, Vals&: ProductPatch);
1700
1701 ConverterEBCDIC::convertToEBCDIC(Source: CompilationTime, Result&: CompilationTimeEBCDIC);
1702 ConverterEBCDIC::convertToEBCDIC(Source: Version, Result&: VersionEBCDIC);
1703
1704 enum class PPA2MemberId : uint8_t {
1705 // See z/OS Language Environment Vendor Interfaces v2r5, p.23, for
1706 // complete list. Only the C runtime is supported by this backend.
1707 LE_C_Runtime = 3,
1708 };
1709 enum class PPA2MemberSubId : uint8_t {
1710 // List of languages using the LE C runtime implementation.
1711 C = 0x00,
1712 CXX = 0x01,
1713 Swift = 0x03,
1714 Go = 0x60,
1715 LLVMBasedLang = 0xe7,
1716 };
1717 // PPA2 Flags
1718 enum class PPA2Flags : uint8_t {
1719 CompileForBinaryFloatingPoint = 0x80,
1720 CompiledWithXPLink = 0x01,
1721 CompiledUnitASCII = 0x04,
1722 HasServiceInfo = 0x20,
1723 };
1724
1725 PPA2MemberSubId MemberSubId = PPA2MemberSubId::LLVMBasedLang;
1726 if (auto *MD = M.getModuleFlag(Key: "zos_cu_language")) {
1727 StringRef Language = cast<MDString>(Val: MD)->getString();
1728 MemberSubId = StringSwitch<PPA2MemberSubId>(Language)
1729 .Case(S: "C", Value: PPA2MemberSubId::C)
1730 .Case(S: "C++", Value: PPA2MemberSubId::CXX)
1731 .Case(S: "Swift", Value: PPA2MemberSubId::Swift)
1732 .Case(S: "Go", Value: PPA2MemberSubId::Go)
1733 .Default(Value: PPA2MemberSubId::LLVMBasedLang);
1734 }
1735
1736 // Emit PPA2 section.
1737 OutStreamer->emitLabel(Symbol: PPA2Sym);
1738 OutStreamer->emitInt8(Value: static_cast<uint8_t>(PPA2MemberId::LE_C_Runtime));
1739 OutStreamer->emitInt8(Value: static_cast<uint8_t>(MemberSubId));
1740 OutStreamer->emitInt8(Value: 0x22); // Member defined, c370_plist+c370_env
1741 OutStreamer->emitInt8(Value: 0x04); // Control level 4 (XPLink)
1742 OutStreamer->emitAbsoluteSymbolDiff(Hi: CELQSTRT, Lo: PPA2Sym, Size: 4);
1743 OutStreamer->emitInt32(Value: 0x00000000);
1744 OutStreamer->emitAbsoluteSymbolDiff(Hi: DateVersionSym, Lo: PPA2Sym, Size: 4);
1745 OutStreamer->emitInt32(
1746 Value: 0x00000000); // Offset to main entry point, always 0 (so says TR).
1747 uint8_t Flgs = static_cast<uint8_t>(PPA2Flags::CompileForBinaryFloatingPoint);
1748 Flgs |= static_cast<uint8_t>(PPA2Flags::CompiledWithXPLink);
1749
1750 bool IsASCII = true;
1751 if (auto *MD = M.getModuleFlag(Key: "zos_le_char_mode")) {
1752 const StringRef &CharMode = cast<MDString>(Val: MD)->getString();
1753 if (CharMode == "ebcdic")
1754 IsASCII = false;
1755 else if (CharMode != "ascii")
1756 OutContext.reportError(
1757 L: {}, Msg: "Only ascii or ebcdic are allowed for zos_le_char_mode");
1758 }
1759 if (IsASCII)
1760 Flgs |= static_cast<uint8_t>(
1761 PPA2Flags::CompiledUnitASCII); // Setting bit for ASCII char. mode.
1762
1763 OutStreamer->emitInt8(Value: Flgs);
1764 OutStreamer->emitInt8(Value: 0x00); // Reserved.
1765 // No MD5 signature before timestamp.
1766 // No FLOAT(AFP(VOLATILE)).
1767 // Remaining 5 flag bits reserved.
1768 OutStreamer->emitInt16(Value: 0x0000); // 16 Reserved flag bits.
1769
1770 // Emit date and version section.
1771 OutStreamer->emitLabel(Symbol: DateVersionSym);
1772 OutStreamer->emitBytes(Data: CompilationTimeEBCDIC.str());
1773 OutStreamer->emitBytes(Data: VersionEBCDIC.str());
1774
1775 OutStreamer->emitInt16(Value: 0x0000); // Service level string length.
1776
1777 // The binder requires that the offset to the PPA2 be emitted in a different,
1778 // specially-named section.
1779 OutStreamer->switchSection(Section: getObjFileLowering().getPPA2ListSection());
1780 // Emit 8 byte alignment.
1781 // Emit pointer to PPA2 label.
1782 OutStreamer->AddComment(T: "A(PPA2-CELQSTRT)");
1783 OutStreamer->emitAbsoluteSymbolDiff(Hi: PPA2Sym, Lo: CELQSTRT, Size: 8);
1784 OutStreamer->popSection();
1785}
1786
1787void SystemZAsmPrinter::emitFunctionEntryLabel() {
1788 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
1789
1790 if (Subtarget.getTargetTriple().isOSzOS()) {
1791 MCContext &OutContext = OutStreamer->getContext();
1792
1793 // Save information for later use.
1794 std::string N(MF->getFunction().hasName()
1795 ? Twine(MF->getFunction().getName()).concat(Suffix: "_").str()
1796 : "");
1797
1798 CurrentFnEPMarkerSym =
1799 OutContext.createTempSymbol(Name: Twine("EPM_").concat(Suffix: N).str(), AlwaysAddSuffix: true);
1800 CurrentFnPPA1Sym =
1801 OutContext.createTempSymbol(Name: Twine("PPA1_").concat(Suffix: N).str(), AlwaysAddSuffix: true);
1802
1803 // EntryPoint Marker
1804 const MachineFrameInfo &MFFrame = MF->getFrameInfo();
1805 bool IsUsingAlloca = MFFrame.hasVarSizedObjects();
1806 uint32_t DSASize = MFFrame.getStackSize();
1807 bool IsLeaf = DSASize == 0 && MFFrame.getCalleeSavedInfo().empty();
1808
1809 // Set Flags.
1810 uint8_t Flags = 0;
1811 if (IsLeaf)
1812 Flags |= 0x08;
1813 if (IsUsingAlloca)
1814 Flags |= 0x04;
1815
1816 // Combine into top 27 bits of DSASize and bottom 5 bits of Flags.
1817 uint32_t DSAAndFlags = DSASize & 0xFFFFFFE0; // (x/32) << 5
1818 DSAAndFlags |= Flags;
1819
1820 // Emit entry point marker section.
1821 OutStreamer->AddComment(T: "XPLINK Routine Layout Entry");
1822 OutStreamer->emitLabel(Symbol: CurrentFnEPMarkerSym);
1823 OutStreamer->AddComment(T: "Eyecatcher 0x00C300C500C500");
1824 OutStreamer->emitIntValueInHex(Value: 0x00C300C500C500, Size: 7); // Eyecatcher.
1825 OutStreamer->AddComment(T: "Mark Type C'1'");
1826 OutStreamer->emitInt8(Value: 0xF1); // Mark Type.
1827 OutStreamer->AddComment(T: "Offset to PPA1");
1828 OutStreamer->emitAbsoluteSymbolDiff(Hi: CurrentFnPPA1Sym, Lo: CurrentFnEPMarkerSym,
1829 Size: 4);
1830 if (OutStreamer->isVerboseAsm()) {
1831 OutStreamer->AddComment(T: "DSA Size 0x" + Twine::utohexstr(Val: DSASize));
1832 OutStreamer->AddComment(T: "Entry Flags");
1833 if (Flags & 0x08)
1834 OutStreamer->AddComment(T: " Bit 1: 1 = Leaf function");
1835 else
1836 OutStreamer->AddComment(T: " Bit 1: 0 = Non-leaf function");
1837 if (Flags & 0x04)
1838 OutStreamer->AddComment(T: " Bit 2: 1 = Uses alloca");
1839 else
1840 OutStreamer->AddComment(T: " Bit 2: 0 = Does not use alloca");
1841 }
1842 OutStreamer->emitInt32(Value: DSAAndFlags);
1843 }
1844
1845 AsmPrinter::emitFunctionEntryLabel();
1846}
1847
1848char SystemZAsmPrinter::ID = 0;
1849
1850INITIALIZE_PASS(SystemZAsmPrinter, "systemz-asm-printer",
1851 "SystemZ Assembly Printer", false, false)
1852
1853// Force static initialization.
1854extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
1855LLVMInitializeSystemZAsmPrinter() {
1856 RegisterAsmPrinter<SystemZAsmPrinter> X(getTheSystemZTarget());
1857}
1858