1//===-- SystemZAsmPrinter.cpp - SystemZ LLVM assembly printer -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Streams SystemZ assembly language and associated data, in the form of
10// MCInsts and MCExprs respectively.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SystemZAsmPrinter.h"
15#include "MCTargetDesc/SystemZGNUInstPrinter.h"
16#include "MCTargetDesc/SystemZHLASMInstPrinter.h"
17#include "MCTargetDesc/SystemZMCAsmInfo.h"
18#include "MCTargetDesc/SystemZMCTargetDesc.h"
19#include "SystemZConstantPoolValue.h"
20#include "SystemZMCInstLower.h"
21#include "TargetInfo/SystemZTargetInfo.h"
22#include "llvm/ADT/StringExtras.h"
23#include "llvm/BinaryFormat/ELF.h"
24#include "llvm/BinaryFormat/GOFF.h"
25#include "llvm/CodeGen/MachineModuleInfoImpls.h"
26#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
27#include "llvm/IR/Mangler.h"
28#include "llvm/IR/Module.h"
29#include "llvm/MC/MCDirectives.h"
30#include "llvm/MC/MCExpr.h"
31#include "llvm/MC/MCInstBuilder.h"
32#include "llvm/MC/MCSectionELF.h"
33#include "llvm/MC/MCStreamer.h"
34#include "llvm/MC/MCSymbolGOFF.h"
35#include "llvm/MC/TargetRegistry.h"
36#include "llvm/Support/Chrono.h"
37#include "llvm/Support/Compiler.h"
38#include "llvm/Support/ConvertEBCDIC.h"
39#include "llvm/Support/FormatVariadic.h"
40
41using namespace llvm;
42
43// Return an RI instruction like MI with opcode Opcode, but with the
44// GR64 register operands turned into GR32s.
45static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) {
46 if (MI->isCompare())
47 return MCInstBuilder(Opcode)
48 .addReg(Reg: SystemZMC::getRegAsGR32(Reg: MI->getOperand(i: 0).getReg()))
49 .addImm(Val: MI->getOperand(i: 1).getImm());
50 else
51 return MCInstBuilder(Opcode)
52 .addReg(Reg: SystemZMC::getRegAsGR32(Reg: MI->getOperand(i: 0).getReg()))
53 .addReg(Reg: SystemZMC::getRegAsGR32(Reg: MI->getOperand(i: 1).getReg()))
54 .addImm(Val: MI->getOperand(i: 2).getImm());
55}
56
57// Return an RI instruction like MI with opcode Opcode, but with the
58// GR64 register operands turned into GRH32s.
59static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode) {
60 if (MI->isCompare())
61 return MCInstBuilder(Opcode)
62 .addReg(Reg: SystemZMC::getRegAsGRH32(Reg: MI->getOperand(i: 0).getReg()))
63 .addImm(Val: MI->getOperand(i: 1).getImm());
64 else
65 return MCInstBuilder(Opcode)
66 .addReg(Reg: SystemZMC::getRegAsGRH32(Reg: MI->getOperand(i: 0).getReg()))
67 .addReg(Reg: SystemZMC::getRegAsGRH32(Reg: MI->getOperand(i: 1).getReg()))
68 .addImm(Val: MI->getOperand(i: 2).getImm());
69}
70
71// Return an RI instruction like MI with opcode Opcode, but with the
72// R2 register turned into a GR64.
73static MCInst lowerRIEfLow(const MachineInstr *MI, unsigned Opcode) {
74 return MCInstBuilder(Opcode)
75 .addReg(Reg: MI->getOperand(i: 0).getReg())
76 .addReg(Reg: MI->getOperand(i: 1).getReg())
77 .addReg(Reg: SystemZMC::getRegAsGR64(Reg: MI->getOperand(i: 2).getReg()))
78 .addImm(Val: MI->getOperand(i: 3).getImm())
79 .addImm(Val: MI->getOperand(i: 4).getImm())
80 .addImm(Val: MI->getOperand(i: 5).getImm());
81}
82
83static const MCSymbolRefExpr *getTLSGetOffset(MCContext &Context) {
84 StringRef Name = "__tls_get_offset";
85 return MCSymbolRefExpr::create(Symbol: Context.getOrCreateSymbol(Name),
86 specifier: SystemZ::S_PLT, Ctx&: Context);
87}
88
89static const MCSymbolRefExpr *getGlobalOffsetTable(MCContext &Context) {
90 StringRef Name = "_GLOBAL_OFFSET_TABLE_";
91 return MCSymbolRefExpr::create(Symbol: Context.getOrCreateSymbol(Name),
92 Ctx&: Context);
93}
94
95// MI is an instruction that accepts an optional alignment hint,
96// and which was already lowered to LoweredMI. If the alignment
97// of the original memory operand is known, update LoweredMI to
98// an instruction with the corresponding hint set.
99static void lowerAlignmentHint(const MachineInstr *MI, MCInst &LoweredMI,
100 unsigned Opcode) {
101 if (MI->memoperands_empty())
102 return;
103
104 Align Alignment = Align(16);
105 for (MachineInstr::mmo_iterator MMOI = MI->memoperands_begin(),
106 EE = MI->memoperands_end(); MMOI != EE; ++MMOI)
107 if ((*MMOI)->getAlign() < Alignment)
108 Alignment = (*MMOI)->getAlign();
109
110 unsigned AlignmentHint = 0;
111 if (Alignment >= Align(16))
112 AlignmentHint = 4;
113 else if (Alignment >= Align(8))
114 AlignmentHint = 3;
115 if (AlignmentHint == 0)
116 return;
117
118 LoweredMI.setOpcode(Opcode);
119 LoweredMI.addOperand(Op: MCOperand::createImm(Val: AlignmentHint));
120}
121
122// MI loads the high part of a vector from memory. Return an instruction
123// that uses replicating vector load Opcode to do the same thing.
124static MCInst lowerSubvectorLoad(const MachineInstr *MI, unsigned Opcode) {
125 return MCInstBuilder(Opcode)
126 .addReg(Reg: SystemZMC::getRegAsVR128(Reg: MI->getOperand(i: 0).getReg()))
127 .addReg(Reg: MI->getOperand(i: 1).getReg())
128 .addImm(Val: MI->getOperand(i: 2).getImm())
129 .addReg(Reg: MI->getOperand(i: 3).getReg());
130}
131
132// MI stores the high part of a vector to memory. Return an instruction
133// that uses elemental vector store Opcode to do the same thing.
134static MCInst lowerSubvectorStore(const MachineInstr *MI, unsigned Opcode) {
135 return MCInstBuilder(Opcode)
136 .addReg(Reg: SystemZMC::getRegAsVR128(Reg: MI->getOperand(i: 0).getReg()))
137 .addReg(Reg: MI->getOperand(i: 1).getReg())
138 .addImm(Val: MI->getOperand(i: 2).getImm())
139 .addReg(Reg: MI->getOperand(i: 3).getReg())
140 .addImm(Val: 0);
141}
142
143// MI extracts the first element of the source vector.
144static MCInst lowerVecEltExtraction(const MachineInstr *MI, unsigned Opcode) {
145 return MCInstBuilder(Opcode)
146 .addReg(Reg: SystemZMC::getRegAsGR64(Reg: MI->getOperand(i: 0).getReg()))
147 .addReg(Reg: SystemZMC::getRegAsVR128(Reg: MI->getOperand(i: 1).getReg()))
148 .addReg(Reg: 0)
149 .addImm(Val: 0);
150}
151
152// MI inserts value into the first element of the destination vector.
153static MCInst lowerVecEltInsertion(const MachineInstr *MI, unsigned Opcode) {
154 return MCInstBuilder(Opcode)
155 .addReg(Reg: SystemZMC::getRegAsVR128(Reg: MI->getOperand(i: 0).getReg()))
156 .addReg(Reg: SystemZMC::getRegAsVR128(Reg: MI->getOperand(i: 0).getReg()))
157 .addReg(Reg: MI->getOperand(i: 1).getReg())
158 .addReg(Reg: 0)
159 .addImm(Val: 0);
160}
161
162bool SystemZAsmPrinter::doInitialization(Module &M) {
163 SM.reset();
164
165 // In HLASM, the only way to represent aliases is to use the
166 // extra-label-at-definition strategy. This is similar to the AIX
167 // implementation with the additional caveat that all symbol attributes must
168 // be emitted before the label is emitted.
169 if (TM.getTargetTriple().isOSzOS()) {
170 // Construct an aliasing list for each GlobalObject.
171 for (const auto &Alias : M.aliases()) {
172 const GlobalObject *Aliasee = Alias.getAliaseeObject();
173 if (!Aliasee)
174 OutContext.reportError(
175 L: {}, Msg: "Alias without a base object is not yet supported on z/OS.");
176
177 bool IsFunc = isa<Function>(Val: Aliasee->stripPointerCasts());
178 if (IsFunc) {
179 if (Alias.hasWeakLinkage() || Alias.hasLinkOnceLinkage())
180 OutContext.reportError(L: {},
181 Msg: "Weak alias/reference not supported on z/OS");
182
183 GOAliasMap[Aliasee].push_back(Elt: &Alias);
184 } else
185 OutContext.reportError(
186 L: {}, Msg: "Only aliases to functions is supported in GOFF.");
187 }
188 }
189 return AsmPrinter::doInitialization(M);
190}
191
192// The XPLINK ABI requires that a no-op encoding the call type is emitted after
193// each call to a subroutine. This information can be used by the called
194// function to determine its entry point, e.g. for generating a backtrace. The
195// call type is encoded as a register number in the bcr instruction. See
196// enumeration CallType for the possible values.
197void SystemZAsmPrinter::emitCallInformation(CallType CT) {
198 EmitToStreamer(S&: *OutStreamer,
199 Inst: MCInstBuilder(SystemZ::BCRAsm)
200 .addImm(Val: 0)
201 .addReg(Reg: SystemZMC::GR64Regs[static_cast<unsigned>(CT)]));
202}
203
204uint32_t SystemZAsmPrinter::AssociatedDataAreaTable::insert(const MCSymbol *Sym,
205 unsigned SlotKind) {
206 auto Key = std::make_pair(x&: Sym, y&: SlotKind);
207 auto It = Displacements.find(Key);
208
209 if (It != Displacements.end())
210 return (*It).second;
211
212 // Determine length of descriptor.
213 uint32_t Length;
214 switch (SlotKind) {
215 case SystemZII::MO_ADA_DIRECT_FUNC_DESC:
216 Length = 2 * PointerSize;
217 break;
218 default:
219 Length = PointerSize;
220 break;
221 }
222
223 uint32_t Displacement = NextDisplacement;
224 Displacements[std::make_pair(x&: Sym, y&: SlotKind)] = NextDisplacement;
225 NextDisplacement += Length;
226
227 return Displacement;
228}
229
230uint32_t
231SystemZAsmPrinter::AssociatedDataAreaTable::insert(const MachineOperand MO) {
232 MCSymbol *Sym;
233 if (MO.getType() == MachineOperand::MO_GlobalAddress) {
234 const GlobalValue *GV = MO.getGlobal();
235 Sym = MO.getParent()->getMF()->getTarget().getSymbol(GV);
236 assert(Sym && "No symbol");
237 } else if (MO.getType() == MachineOperand::MO_ExternalSymbol) {
238 const char *SymName = MO.getSymbolName();
239 Sym = MO.getParent()->getMF()->getContext().getOrCreateSymbol(Name: SymName);
240 assert(Sym && "No symbol");
241 } else
242 llvm_unreachable("Unexpected operand type");
243
244 unsigned ADAslotType = MO.getTargetFlags();
245 return insert(Sym, SlotKind: ADAslotType);
246}
247
248void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
249 SystemZ_MC::verifyInstructionPredicates(Opcode: MI->getOpcode(),
250 Features: getSubtargetInfo().getFeatureBits());
251
252 SystemZMCInstLower Lower(MF->getContext(), *this);
253 MCInst LoweredMI;
254 switch (MI->getOpcode()) {
255 case SystemZ::Return:
256 LoweredMI = MCInstBuilder(SystemZ::BR)
257 .addReg(Reg: SystemZ::R14D);
258 break;
259
260 case SystemZ::Return_XPLINK:
261 LoweredMI = MCInstBuilder(SystemZ::B)
262 .addReg(Reg: SystemZ::R7D)
263 .addImm(Val: 2)
264 .addReg(Reg: 0);
265 break;
266
267 case SystemZ::CondReturn:
268 LoweredMI = MCInstBuilder(SystemZ::BCR)
269 .addImm(Val: MI->getOperand(i: 0).getImm())
270 .addImm(Val: MI->getOperand(i: 1).getImm())
271 .addReg(Reg: SystemZ::R14D);
272 break;
273
274 case SystemZ::CondReturn_XPLINK:
275 LoweredMI = MCInstBuilder(SystemZ::BC)
276 .addImm(Val: MI->getOperand(i: 0).getImm())
277 .addImm(Val: MI->getOperand(i: 1).getImm())
278 .addReg(Reg: SystemZ::R7D)
279 .addImm(Val: 2)
280 .addReg(Reg: 0);
281 break;
282
283 case SystemZ::CRBReturn:
284 LoweredMI = MCInstBuilder(SystemZ::CRB)
285 .addReg(Reg: MI->getOperand(i: 0).getReg())
286 .addReg(Reg: MI->getOperand(i: 1).getReg())
287 .addImm(Val: MI->getOperand(i: 2).getImm())
288 .addReg(Reg: SystemZ::R14D)
289 .addImm(Val: 0);
290 break;
291
292 case SystemZ::CGRBReturn:
293 LoweredMI = MCInstBuilder(SystemZ::CGRB)
294 .addReg(Reg: MI->getOperand(i: 0).getReg())
295 .addReg(Reg: MI->getOperand(i: 1).getReg())
296 .addImm(Val: MI->getOperand(i: 2).getImm())
297 .addReg(Reg: SystemZ::R14D)
298 .addImm(Val: 0);
299 break;
300
301 case SystemZ::CIBReturn:
302 LoweredMI = MCInstBuilder(SystemZ::CIB)
303 .addReg(Reg: MI->getOperand(i: 0).getReg())
304 .addImm(Val: MI->getOperand(i: 1).getImm())
305 .addImm(Val: MI->getOperand(i: 2).getImm())
306 .addReg(Reg: SystemZ::R14D)
307 .addImm(Val: 0);
308 break;
309
310 case SystemZ::CGIBReturn:
311 LoweredMI = MCInstBuilder(SystemZ::CGIB)
312 .addReg(Reg: MI->getOperand(i: 0).getReg())
313 .addImm(Val: MI->getOperand(i: 1).getImm())
314 .addImm(Val: MI->getOperand(i: 2).getImm())
315 .addReg(Reg: SystemZ::R14D)
316 .addImm(Val: 0);
317 break;
318
319 case SystemZ::CLRBReturn:
320 LoweredMI = MCInstBuilder(SystemZ::CLRB)
321 .addReg(Reg: MI->getOperand(i: 0).getReg())
322 .addReg(Reg: MI->getOperand(i: 1).getReg())
323 .addImm(Val: MI->getOperand(i: 2).getImm())
324 .addReg(Reg: SystemZ::R14D)
325 .addImm(Val: 0);
326 break;
327
328 case SystemZ::CLGRBReturn:
329 LoweredMI = MCInstBuilder(SystemZ::CLGRB)
330 .addReg(Reg: MI->getOperand(i: 0).getReg())
331 .addReg(Reg: MI->getOperand(i: 1).getReg())
332 .addImm(Val: MI->getOperand(i: 2).getImm())
333 .addReg(Reg: SystemZ::R14D)
334 .addImm(Val: 0);
335 break;
336
337 case SystemZ::CLIBReturn:
338 LoweredMI = MCInstBuilder(SystemZ::CLIB)
339 .addReg(Reg: MI->getOperand(i: 0).getReg())
340 .addImm(Val: MI->getOperand(i: 1).getImm())
341 .addImm(Val: MI->getOperand(i: 2).getImm())
342 .addReg(Reg: SystemZ::R14D)
343 .addImm(Val: 0);
344 break;
345
346 case SystemZ::CLGIBReturn:
347 LoweredMI = MCInstBuilder(SystemZ::CLGIB)
348 .addReg(Reg: MI->getOperand(i: 0).getReg())
349 .addImm(Val: MI->getOperand(i: 1).getImm())
350 .addImm(Val: MI->getOperand(i: 2).getImm())
351 .addReg(Reg: SystemZ::R14D)
352 .addImm(Val: 0);
353 break;
354
355 case SystemZ::CallBRASL_XPLINK64:
356 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::BRASL)
357 .addReg(Reg: SystemZ::R7D)
358 .addExpr(Val: Lower.getExpr(MO: MI->getOperand(i: 0),
359 SystemZ::S_None)));
360 emitCallInformation(CT: CallType::BRASL7);
361 return;
362
363 case SystemZ::CallBASR_XPLINK64:
364 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::BASR)
365 .addReg(Reg: SystemZ::R7D)
366 .addReg(Reg: MI->getOperand(i: 0).getReg()));
367 emitCallInformation(CT: CallType::BASR76);
368 return;
369
370 case SystemZ::CallBASR_STACKEXT:
371 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::BASR)
372 .addReg(Reg: SystemZ::R3D)
373 .addReg(Reg: MI->getOperand(i: 0).getReg()));
374 emitCallInformation(CT: CallType::BASR33);
375 return;
376
377 case SystemZ::ADA_ENTRY_VALUE:
378 case SystemZ::ADA_ENTRY: {
379 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
380 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
381 uint32_t Disp = ADATable.insert(MO: MI->getOperand(i: 1));
382 Register TargetReg = MI->getOperand(i: 0).getReg();
383
384 Register ADAReg = MI->getOperand(i: 2).getReg();
385 Disp += MI->getOperand(i: 3).getImm();
386 bool LoadAddr = MI->getOpcode() == SystemZ::ADA_ENTRY;
387
388 unsigned Op0 = LoadAddr ? SystemZ::LA : SystemZ::LG;
389 unsigned Op = TII->getOpcodeForOffset(Opcode: Op0, Offset: Disp);
390
391 Register IndexReg = 0;
392 if (!Op) {
393 if (TargetReg != ADAReg) {
394 IndexReg = TargetReg;
395 // Use TargetReg to store displacement.
396 EmitToStreamer(
397 S&: *OutStreamer,
398 Inst: MCInstBuilder(SystemZ::LLILF).addReg(Reg: TargetReg).addImm(Val: Disp));
399 } else
400 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::ALGFI)
401 .addReg(Reg: TargetReg)
402 .addReg(Reg: TargetReg)
403 .addImm(Val: Disp));
404 Disp = 0;
405 Op = Op0;
406 }
407 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(Op)
408 .addReg(Reg: TargetReg)
409 .addReg(Reg: ADAReg)
410 .addImm(Val: Disp)
411 .addReg(Reg: IndexReg));
412
413 return;
414 }
415 case SystemZ::CallBRASL:
416 LoweredMI = MCInstBuilder(SystemZ::BRASL)
417 .addReg(Reg: SystemZ::R14D)
418 .addExpr(Val: Lower.getExpr(MO: MI->getOperand(i: 0), SystemZ::S_PLT));
419 break;
420
421 case SystemZ::CallBASR:
422 LoweredMI = MCInstBuilder(SystemZ::BASR)
423 .addReg(Reg: SystemZ::R14D)
424 .addReg(Reg: MI->getOperand(i: 0).getReg());
425 break;
426
427 case SystemZ::CallJG:
428 LoweredMI = MCInstBuilder(SystemZ::JG)
429 .addExpr(Val: Lower.getExpr(MO: MI->getOperand(i: 0), SystemZ::S_PLT));
430 break;
431
432 case SystemZ::CallBRCL:
433 LoweredMI = MCInstBuilder(SystemZ::BRCL)
434 .addImm(Val: MI->getOperand(i: 0).getImm())
435 .addImm(Val: MI->getOperand(i: 1).getImm())
436 .addExpr(Val: Lower.getExpr(MO: MI->getOperand(i: 2), SystemZ::S_PLT));
437 break;
438
439 case SystemZ::CallBR:
440 LoweredMI = MCInstBuilder(SystemZ::BR)
441 .addReg(Reg: MI->getOperand(i: 0).getReg());
442 break;
443
444 case SystemZ::CallBCR:
445 LoweredMI = MCInstBuilder(SystemZ::BCR)
446 .addImm(Val: MI->getOperand(i: 0).getImm())
447 .addImm(Val: MI->getOperand(i: 1).getImm())
448 .addReg(Reg: MI->getOperand(i: 2).getReg());
449 break;
450
451 case SystemZ::CRBCall:
452 LoweredMI = MCInstBuilder(SystemZ::CRB)
453 .addReg(Reg: MI->getOperand(i: 0).getReg())
454 .addReg(Reg: MI->getOperand(i: 1).getReg())
455 .addImm(Val: MI->getOperand(i: 2).getImm())
456 .addReg(Reg: MI->getOperand(i: 3).getReg())
457 .addImm(Val: 0);
458 break;
459
460 case SystemZ::CGRBCall:
461 LoweredMI = MCInstBuilder(SystemZ::CGRB)
462 .addReg(Reg: MI->getOperand(i: 0).getReg())
463 .addReg(Reg: MI->getOperand(i: 1).getReg())
464 .addImm(Val: MI->getOperand(i: 2).getImm())
465 .addReg(Reg: MI->getOperand(i: 3).getReg())
466 .addImm(Val: 0);
467 break;
468
469 case SystemZ::CIBCall:
470 LoweredMI = MCInstBuilder(SystemZ::CIB)
471 .addReg(Reg: MI->getOperand(i: 0).getReg())
472 .addImm(Val: MI->getOperand(i: 1).getImm())
473 .addImm(Val: MI->getOperand(i: 2).getImm())
474 .addReg(Reg: MI->getOperand(i: 3).getReg())
475 .addImm(Val: 0);
476 break;
477
478 case SystemZ::CGIBCall:
479 LoweredMI = MCInstBuilder(SystemZ::CGIB)
480 .addReg(Reg: MI->getOperand(i: 0).getReg())
481 .addImm(Val: MI->getOperand(i: 1).getImm())
482 .addImm(Val: MI->getOperand(i: 2).getImm())
483 .addReg(Reg: MI->getOperand(i: 3).getReg())
484 .addImm(Val: 0);
485 break;
486
487 case SystemZ::CLRBCall:
488 LoweredMI = MCInstBuilder(SystemZ::CLRB)
489 .addReg(Reg: MI->getOperand(i: 0).getReg())
490 .addReg(Reg: MI->getOperand(i: 1).getReg())
491 .addImm(Val: MI->getOperand(i: 2).getImm())
492 .addReg(Reg: MI->getOperand(i: 3).getReg())
493 .addImm(Val: 0);
494 break;
495
496 case SystemZ::CLGRBCall:
497 LoweredMI = MCInstBuilder(SystemZ::CLGRB)
498 .addReg(Reg: MI->getOperand(i: 0).getReg())
499 .addReg(Reg: MI->getOperand(i: 1).getReg())
500 .addImm(Val: MI->getOperand(i: 2).getImm())
501 .addReg(Reg: MI->getOperand(i: 3).getReg())
502 .addImm(Val: 0);
503 break;
504
505 case SystemZ::CLIBCall:
506 LoweredMI = MCInstBuilder(SystemZ::CLIB)
507 .addReg(Reg: MI->getOperand(i: 0).getReg())
508 .addImm(Val: MI->getOperand(i: 1).getImm())
509 .addImm(Val: MI->getOperand(i: 2).getImm())
510 .addReg(Reg: MI->getOperand(i: 3).getReg())
511 .addImm(Val: 0);
512 break;
513
514 case SystemZ::CLGIBCall:
515 LoweredMI = MCInstBuilder(SystemZ::CLGIB)
516 .addReg(Reg: MI->getOperand(i: 0).getReg())
517 .addImm(Val: MI->getOperand(i: 1).getImm())
518 .addImm(Val: MI->getOperand(i: 2).getImm())
519 .addReg(Reg: MI->getOperand(i: 3).getReg())
520 .addImm(Val: 0);
521 break;
522
523 case SystemZ::TLS_GDCALL:
524 LoweredMI =
525 MCInstBuilder(SystemZ::BRASL)
526 .addReg(Reg: SystemZ::R14D)
527 .addExpr(Val: getTLSGetOffset(Context&: MF->getContext()))
528 .addExpr(Val: Lower.getExpr(MO: MI->getOperand(i: 0), SystemZ::S_TLSGD));
529 break;
530
531 case SystemZ::TLS_LDCALL:
532 LoweredMI =
533 MCInstBuilder(SystemZ::BRASL)
534 .addReg(Reg: SystemZ::R14D)
535 .addExpr(Val: getTLSGetOffset(Context&: MF->getContext()))
536 .addExpr(Val: Lower.getExpr(MO: MI->getOperand(i: 0), SystemZ::S_TLSLDM));
537 break;
538
539 case SystemZ::GOT:
540 LoweredMI = MCInstBuilder(SystemZ::LARL)
541 .addReg(Reg: MI->getOperand(i: 0).getReg())
542 .addExpr(Val: getGlobalOffsetTable(Context&: MF->getContext()));
543 break;
544
545 case SystemZ::IILF64:
546 LoweredMI = MCInstBuilder(SystemZ::IILF)
547 .addReg(Reg: SystemZMC::getRegAsGR32(Reg: MI->getOperand(i: 0).getReg()))
548 .addImm(Val: MI->getOperand(i: 2).getImm());
549 break;
550
551 case SystemZ::IIHF64:
552 LoweredMI = MCInstBuilder(SystemZ::IIHF)
553 .addReg(Reg: SystemZMC::getRegAsGRH32(Reg: MI->getOperand(i: 0).getReg()))
554 .addImm(Val: MI->getOperand(i: 2).getImm());
555 break;
556
557 case SystemZ::RISBHH:
558 case SystemZ::RISBHL:
559 LoweredMI = lowerRIEfLow(MI, Opcode: SystemZ::RISBHG);
560 break;
561
562 case SystemZ::RISBLH:
563 case SystemZ::RISBLL:
564 LoweredMI = lowerRIEfLow(MI, Opcode: SystemZ::RISBLG);
565 break;
566
567 case SystemZ::VLVGP32:
568 LoweredMI = MCInstBuilder(SystemZ::VLVGP)
569 .addReg(Reg: MI->getOperand(i: 0).getReg())
570 .addReg(Reg: SystemZMC::getRegAsGR64(Reg: MI->getOperand(i: 1).getReg()))
571 .addReg(Reg: SystemZMC::getRegAsGR64(Reg: MI->getOperand(i: 2).getReg()));
572 break;
573
574 case SystemZ::VLR16:
575 case SystemZ::VLR32:
576 case SystemZ::VLR64:
577 LoweredMI = MCInstBuilder(SystemZ::VLR)
578 .addReg(Reg: SystemZMC::getRegAsVR128(Reg: MI->getOperand(i: 0).getReg()))
579 .addReg(Reg: SystemZMC::getRegAsVR128(Reg: MI->getOperand(i: 1).getReg()));
580 break;
581
582 case SystemZ::VL:
583 Lower.lower(MI, OutMI&: LoweredMI);
584 lowerAlignmentHint(MI, LoweredMI, Opcode: SystemZ::VLAlign);
585 break;
586
587 case SystemZ::VST:
588 Lower.lower(MI, OutMI&: LoweredMI);
589 lowerAlignmentHint(MI, LoweredMI, Opcode: SystemZ::VSTAlign);
590 break;
591
592 case SystemZ::VLM:
593 Lower.lower(MI, OutMI&: LoweredMI);
594 lowerAlignmentHint(MI, LoweredMI, Opcode: SystemZ::VLMAlign);
595 break;
596
597 case SystemZ::VSTM:
598 Lower.lower(MI, OutMI&: LoweredMI);
599 lowerAlignmentHint(MI, LoweredMI, Opcode: SystemZ::VSTMAlign);
600 break;
601
602 case SystemZ::VL16:
603 LoweredMI = lowerSubvectorLoad(MI, Opcode: SystemZ::VLREPH);
604 break;
605
606 case SystemZ::VL32:
607 LoweredMI = lowerSubvectorLoad(MI, Opcode: SystemZ::VLREPF);
608 break;
609
610 case SystemZ::VL64:
611 LoweredMI = lowerSubvectorLoad(MI, Opcode: SystemZ::VLREPG);
612 break;
613
614 case SystemZ::VST16:
615 LoweredMI = lowerSubvectorStore(MI, Opcode: SystemZ::VSTEH);
616 break;
617
618 case SystemZ::VST32:
619 LoweredMI = lowerSubvectorStore(MI, Opcode: SystemZ::VSTEF);
620 break;
621
622 case SystemZ::VST64:
623 LoweredMI = lowerSubvectorStore(MI, Opcode: SystemZ::VSTEG);
624 break;
625
626 case SystemZ::LFER:
627 LoweredMI = lowerVecEltExtraction(MI, Opcode: SystemZ::VLGVF);
628 break;
629
630 case SystemZ::LFER_16:
631 LoweredMI = lowerVecEltExtraction(MI, Opcode: SystemZ::VLGVH);
632 break;
633
634 case SystemZ::LEFR:
635 LoweredMI = lowerVecEltInsertion(MI, Opcode: SystemZ::VLVGF);
636 break;
637
638 case SystemZ::LEFR_16:
639 LoweredMI = lowerVecEltInsertion(MI, Opcode: SystemZ::VLVGH);
640 break;
641
642#define LOWER_LOW(NAME) \
643 case SystemZ::NAME##64: LoweredMI = lowerRILow(MI, SystemZ::NAME); break
644
645 LOWER_LOW(IILL);
646 LOWER_LOW(IILH);
647 LOWER_LOW(TMLL);
648 LOWER_LOW(TMLH);
649 LOWER_LOW(NILL);
650 LOWER_LOW(NILH);
651 LOWER_LOW(NILF);
652 LOWER_LOW(OILL);
653 LOWER_LOW(OILH);
654 LOWER_LOW(OILF);
655 LOWER_LOW(XILF);
656
657#undef LOWER_LOW
658
659#define LOWER_HIGH(NAME) \
660 case SystemZ::NAME##64: LoweredMI = lowerRIHigh(MI, SystemZ::NAME); break
661
662 LOWER_HIGH(IIHL);
663 LOWER_HIGH(IIHH);
664 LOWER_HIGH(TMHL);
665 LOWER_HIGH(TMHH);
666 LOWER_HIGH(NIHL);
667 LOWER_HIGH(NIHH);
668 LOWER_HIGH(NIHF);
669 LOWER_HIGH(OIHL);
670 LOWER_HIGH(OIHH);
671 LOWER_HIGH(OIHF);
672 LOWER_HIGH(XIHF);
673
674#undef LOWER_HIGH
675
676 case SystemZ::Serialize:
677 if (MF->getSubtarget<SystemZSubtarget>().hasFastSerialization())
678 LoweredMI = MCInstBuilder(SystemZ::BCRAsm)
679 .addImm(Val: 14).addReg(Reg: SystemZ::R0D);
680 else
681 LoweredMI = MCInstBuilder(SystemZ::BCRAsm)
682 .addImm(Val: 15).addReg(Reg: SystemZ::R0D);
683 break;
684
685 // We want to emit "j .+2" for traps, jumping to the relative immediate field
686 // of the jump instruction, which is an illegal instruction. We cannot emit a
687 // "." symbol, so create and emit a temp label before the instruction and use
688 // that instead.
689 case SystemZ::Trap: {
690 MCSymbol *DotSym = OutContext.createTempSymbol();
691 OutStreamer->emitLabel(Symbol: DotSym);
692
693 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Symbol: DotSym, Ctx&: OutContext);
694 const MCConstantExpr *ConstExpr = MCConstantExpr::create(Value: 2, Ctx&: OutContext);
695 LoweredMI = MCInstBuilder(SystemZ::J)
696 .addExpr(Val: MCBinaryExpr::createAdd(LHS: Expr, RHS: ConstExpr, Ctx&: OutContext));
697 }
698 break;
699
700 // Conditional traps will create a branch on condition instruction that jumps
701 // to the relative immediate field of the jump instruction. (eg. "jo .+2")
702 case SystemZ::CondTrap: {
703 MCSymbol *DotSym = OutContext.createTempSymbol();
704 OutStreamer->emitLabel(Symbol: DotSym);
705
706 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Symbol: DotSym, Ctx&: OutContext);
707 const MCConstantExpr *ConstExpr = MCConstantExpr::create(Value: 2, Ctx&: OutContext);
708 LoweredMI = MCInstBuilder(SystemZ::BRC)
709 .addImm(Val: MI->getOperand(i: 0).getImm())
710 .addImm(Val: MI->getOperand(i: 1).getImm())
711 .addExpr(Val: MCBinaryExpr::createAdd(LHS: Expr, RHS: ConstExpr, Ctx&: OutContext));
712 }
713 break;
714
715 case TargetOpcode::FENTRY_CALL:
716 LowerFENTRY_CALL(MI: *MI, MCIL&: Lower);
717 return;
718
719 case TargetOpcode::STACKMAP:
720 LowerSTACKMAP(MI: *MI);
721 return;
722
723 case TargetOpcode::PATCHPOINT:
724 LowerPATCHPOINT(MI: *MI, Lower);
725 return;
726
727 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
728 LowerPATCHABLE_FUNCTION_ENTER(MI: *MI, Lower);
729 return;
730
731 case TargetOpcode::PATCHABLE_RET:
732 LowerPATCHABLE_RET(MI: *MI, Lower);
733 return;
734
735 case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
736 llvm_unreachable("PATCHABLE_FUNCTION_EXIT should never be emitted");
737
738 case TargetOpcode::PATCHABLE_TAIL_CALL:
739 // TODO: Define a trampoline `__xray_FunctionTailExit` and differentiate a
740 // normal function exit from a tail exit.
741 llvm_unreachable("Tail call is handled in the normal case. See comments "
742 "around this assert.");
743
744 case SystemZ::EXRL_Pseudo: {
745 unsigned TargetInsOpc = MI->getOperand(i: 0).getImm();
746 Register LenMinus1Reg = MI->getOperand(i: 1).getReg();
747 Register DestReg = MI->getOperand(i: 2).getReg();
748 int64_t DestDisp = MI->getOperand(i: 3).getImm();
749 Register SrcReg = MI->getOperand(i: 4).getReg();
750 int64_t SrcDisp = MI->getOperand(i: 5).getImm();
751
752 SystemZTargetStreamer *TS = getTargetStreamer();
753 MCInst ET = MCInstBuilder(TargetInsOpc)
754 .addReg(Reg: DestReg)
755 .addImm(Val: DestDisp)
756 .addImm(Val: 1)
757 .addReg(Reg: SrcReg)
758 .addImm(Val: SrcDisp);
759 SystemZTargetStreamer::MCInstSTIPair ET_STI(ET, &MF->getSubtarget());
760 auto [It, Inserted] = TS->EXRLTargets2Sym.try_emplace(k: ET_STI);
761 if (Inserted)
762 It->second = OutContext.createTempSymbol();
763 MCSymbol *DotSym = It->second;
764 const MCSymbolRefExpr *Dot = MCSymbolRefExpr::create(Symbol: DotSym, Ctx&: OutContext);
765 EmitToStreamer(
766 S&: *OutStreamer,
767 Inst: MCInstBuilder(SystemZ::EXRL).addReg(Reg: LenMinus1Reg).addExpr(Val: Dot));
768 return;
769 }
770
771 // EH_SjLj_Setup is a dummy terminator instruction of size 0.
772 // It is used to handle the clobber register for builtin setjmp.
773 case SystemZ::EH_SjLj_Setup:
774 return;
775
776 default:
777 Lower.lower(MI, OutMI&: LoweredMI);
778 break;
779 }
780 EmitToStreamer(S&: *OutStreamer, Inst: LoweredMI);
781}
782
783// Emit the largest nop instruction smaller than or equal to NumBytes
784// bytes. Return the size of nop emitted.
785static unsigned EmitNop(MCContext &OutContext, MCStreamer &OutStreamer,
786 unsigned NumBytes, const MCSubtargetInfo &STI) {
787 if (NumBytes < 2) {
788 llvm_unreachable("Zero nops?");
789 return 0;
790 }
791 else if (NumBytes < 4) {
792 OutStreamer.emitInstruction(
793 Inst: MCInstBuilder(SystemZ::BCRAsm).addImm(Val: 0).addReg(Reg: SystemZ::R0D), STI);
794 return 2;
795 }
796 else if (NumBytes < 6) {
797 OutStreamer.emitInstruction(
798 Inst: MCInstBuilder(SystemZ::BCAsm).addImm(Val: 0).addReg(Reg: 0).addImm(Val: 0).addReg(Reg: 0),
799 STI);
800 return 4;
801 }
802 else {
803 MCSymbol *DotSym = OutContext.createTempSymbol();
804 const MCSymbolRefExpr *Dot = MCSymbolRefExpr::create(Symbol: DotSym, Ctx&: OutContext);
805 OutStreamer.emitLabel(Symbol: DotSym);
806 OutStreamer.emitInstruction(
807 Inst: MCInstBuilder(SystemZ::BRCLAsm).addImm(Val: 0).addExpr(Val: Dot), STI);
808 return 6;
809 }
810}
811
812void SystemZAsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI,
813 SystemZMCInstLower &Lower) {
814 MCContext &Ctx = MF->getContext();
815 if (MF->getFunction().hasFnAttribute(Kind: "mrecord-mcount")) {
816 MCSymbol *DotSym = OutContext.createTempSymbol();
817 OutStreamer->pushSection();
818 OutStreamer->switchSection(
819 Section: Ctx.getELFSection(Section: "__mcount_loc", Type: ELF::SHT_PROGBITS, Flags: ELF::SHF_ALLOC));
820 OutStreamer->emitSymbolValue(Sym: DotSym, Size: 8);
821 OutStreamer->popSection();
822 OutStreamer->emitLabel(Symbol: DotSym);
823 }
824
825 if (MF->getFunction().hasFnAttribute(Kind: "mnop-mcount")) {
826 EmitNop(OutContext&: Ctx, OutStreamer&: *OutStreamer, NumBytes: 6, STI: getSubtargetInfo());
827 return;
828 }
829
830 MCSymbol *fentry = Ctx.getOrCreateSymbol(Name: "__fentry__");
831 const MCSymbolRefExpr *Op =
832 MCSymbolRefExpr::create(Symbol: fentry, specifier: SystemZ::S_PLT, Ctx);
833 OutStreamer->emitInstruction(
834 Inst: MCInstBuilder(SystemZ::BRASL).addReg(Reg: SystemZ::R0D).addExpr(Val: Op),
835 STI: getSubtargetInfo());
836}
837
838void SystemZAsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
839 auto *TII = MF->getSubtarget<SystemZSubtarget>().getInstrInfo();
840
841 unsigned NumNOPBytes = MI.getOperand(i: 1).getImm();
842
843 auto &Ctx = OutStreamer->getContext();
844 MCSymbol *MILabel = Ctx.createTempSymbol();
845 OutStreamer->emitLabel(Symbol: MILabel);
846
847 SM.recordStackMap(L: *MILabel, MI);
848 assert(NumNOPBytes % 2 == 0 && "Invalid number of NOP bytes requested!");
849
850 // Scan ahead to trim the shadow.
851 unsigned ShadowBytes = 0;
852 const MachineBasicBlock &MBB = *MI.getParent();
853 MachineBasicBlock::const_iterator MII(MI);
854 ++MII;
855 while (ShadowBytes < NumNOPBytes) {
856 if (MII == MBB.end() ||
857 MII->getOpcode() == TargetOpcode::PATCHPOINT ||
858 MII->getOpcode() == TargetOpcode::STACKMAP)
859 break;
860 ShadowBytes += TII->getInstSizeInBytes(MI: *MII);
861 if (MII->isCall())
862 break;
863 ++MII;
864 }
865
866 // Emit nops.
867 while (ShadowBytes < NumNOPBytes)
868 ShadowBytes += EmitNop(OutContext, OutStreamer&: *OutStreamer, NumBytes: NumNOPBytes - ShadowBytes,
869 STI: getSubtargetInfo());
870}
871
872// Lower a patchpoint of the form:
873// [<def>], <id>, <numBytes>, <target>, <numArgs>
874void SystemZAsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
875 SystemZMCInstLower &Lower) {
876 auto &Ctx = OutStreamer->getContext();
877 MCSymbol *MILabel = Ctx.createTempSymbol();
878 OutStreamer->emitLabel(Symbol: MILabel);
879
880 SM.recordPatchPoint(L: *MILabel, MI);
881 PatchPointOpers Opers(&MI);
882
883 unsigned EncodedBytes = 0;
884 const MachineOperand &CalleeMO = Opers.getCallTarget();
885
886 if (CalleeMO.isImm()) {
887 uint64_t CallTarget = CalleeMO.getImm();
888 if (CallTarget) {
889 unsigned ScratchIdx = -1;
890 unsigned ScratchReg = 0;
891 do {
892 ScratchIdx = Opers.getNextScratchIdx(StartIdx: ScratchIdx + 1);
893 ScratchReg = MI.getOperand(i: ScratchIdx).getReg();
894 } while (ScratchReg == SystemZ::R0D);
895
896 // Materialize the call target address
897 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::LLILF)
898 .addReg(Reg: ScratchReg)
899 .addImm(Val: CallTarget & 0xFFFFFFFF));
900 EncodedBytes += 6;
901 if (CallTarget >> 32) {
902 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::IIHF)
903 .addReg(Reg: ScratchReg)
904 .addImm(Val: CallTarget >> 32));
905 EncodedBytes += 6;
906 }
907
908 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::BASR)
909 .addReg(Reg: SystemZ::R14D)
910 .addReg(Reg: ScratchReg));
911 EncodedBytes += 2;
912 }
913 } else if (CalleeMO.isGlobal()) {
914 const MCExpr *Expr = Lower.getExpr(MO: CalleeMO, SystemZ::S_PLT);
915 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::BRASL)
916 .addReg(Reg: SystemZ::R14D)
917 .addExpr(Val: Expr));
918 EncodedBytes += 6;
919 }
920
921 // Emit padding.
922 unsigned NumBytes = Opers.getNumPatchBytes();
923 assert(NumBytes >= EncodedBytes &&
924 "Patchpoint can't request size less than the length of a call.");
925 assert((NumBytes - EncodedBytes) % 2 == 0 &&
926 "Invalid number of NOP bytes requested!");
927 while (EncodedBytes < NumBytes)
928 EncodedBytes += EmitNop(OutContext, OutStreamer&: *OutStreamer, NumBytes: NumBytes - EncodedBytes,
929 STI: getSubtargetInfo());
930}
931
932void SystemZAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(
933 const MachineInstr &MI, SystemZMCInstLower &Lower) {
934
935 const MachineFunction &MF = *(MI.getParent()->getParent());
936 const Function &F = MF.getFunction();
937
938 // If patchable-function-entry is set, emit in-function nops here.
939 if (F.hasFnAttribute(Kind: "patchable-function-entry")) {
940 unsigned Num;
941 // get M-N from function attribute (CodeGenFunction subtracts N
942 // from M to yield the correct patchable-function-entry).
943 if (F.getFnAttribute(Kind: "patchable-function-entry")
944 .getValueAsString()
945 .getAsInteger(Radix: 10, Result&: Num))
946 return;
947 // Emit M-N 2-byte nops. Use getNop() here instead of emitNops()
948 // to keep it aligned with the common code implementation emitting
949 // the prefix nops.
950 for (unsigned I = 0; I < Num; ++I)
951 EmitToStreamer(S&: *OutStreamer, Inst: MF.getSubtarget().getInstrInfo()->getNop());
952 return;
953 }
954 // Otherwise, emit xray sled.
955 // .begin:
956 // j .end # -> stmg %r2, %r15, 16(%r15)
957 // nop
958 // llilf %2, FuncID
959 // brasl %r14, __xray_FunctionEntry@GOT
960 // .end:
961 //
962 // Update compiler-rt/lib/xray/xray_s390x.cpp accordingly when number
963 // of instructions change.
964 bool HasVectorFeature =
965 TM.getMCSubtargetInfo()->hasFeature(Feature: SystemZ::FeatureVector) &&
966 !TM.getMCSubtargetInfo()->hasFeature(Feature: SystemZ::FeatureSoftFloat);
967 MCSymbol *FuncEntry = OutContext.getOrCreateSymbol(
968 Name: HasVectorFeature ? "__xray_FunctionEntryVec" : "__xray_FunctionEntry");
969 MCSymbol *BeginOfSled = OutContext.createTempSymbol(Name: "xray_sled_", AlwaysAddSuffix: true);
970 MCSymbol *EndOfSled = OutContext.createTempSymbol();
971 OutStreamer->emitLabel(Symbol: BeginOfSled);
972 EmitToStreamer(S&: *OutStreamer,
973 Inst: MCInstBuilder(SystemZ::J)
974 .addExpr(Val: MCSymbolRefExpr::create(Symbol: EndOfSled, Ctx&: OutContext)));
975 EmitNop(OutContext, OutStreamer&: *OutStreamer, NumBytes: 2, STI: getSubtargetInfo());
976 EmitToStreamer(S&: *OutStreamer,
977 Inst: MCInstBuilder(SystemZ::LLILF).addReg(Reg: SystemZ::R2D).addImm(Val: 0));
978 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::BRASL)
979 .addReg(Reg: SystemZ::R14D)
980 .addExpr(Val: MCSymbolRefExpr::create(
981 Symbol: FuncEntry, specifier: SystemZ::S_PLT, Ctx&: OutContext)));
982 OutStreamer->emitLabel(Symbol: EndOfSled);
983 recordSled(Sled: BeginOfSled, MI, Kind: SledKind::FUNCTION_ENTER, Version: 2);
984}
985
986void SystemZAsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI,
987 SystemZMCInstLower &Lower) {
988 unsigned OpCode = MI.getOperand(i: 0).getImm();
989 MCSymbol *FallthroughLabel = nullptr;
990 if (OpCode == SystemZ::CondReturn) {
991 FallthroughLabel = OutContext.createTempSymbol();
992 int64_t Cond0 = MI.getOperand(i: 1).getImm();
993 int64_t Cond1 = MI.getOperand(i: 2).getImm();
994 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::BRC)
995 .addImm(Val: Cond0)
996 .addImm(Val: Cond1 ^ Cond0)
997 .addExpr(Val: MCSymbolRefExpr::create(
998 Symbol: FallthroughLabel, Ctx&: OutContext)));
999 }
1000 // .begin:
1001 // br %r14 # -> stmg %r2, %r15, 24(%r15)
1002 // nop
1003 // nop
1004 // llilf %2,FuncID
1005 // j __xray_FunctionExit@GOT
1006 //
1007 // Update compiler-rt/lib/xray/xray_s390x.cpp accordingly when number
1008 // of instructions change.
1009 bool HasVectorFeature =
1010 TM.getMCSubtargetInfo()->hasFeature(Feature: SystemZ::FeatureVector) &&
1011 !TM.getMCSubtargetInfo()->hasFeature(Feature: SystemZ::FeatureSoftFloat);
1012 MCSymbol *FuncExit = OutContext.getOrCreateSymbol(
1013 Name: HasVectorFeature ? "__xray_FunctionExitVec" : "__xray_FunctionExit");
1014 MCSymbol *BeginOfSled = OutContext.createTempSymbol(Name: "xray_sled_", AlwaysAddSuffix: true);
1015 OutStreamer->emitLabel(Symbol: BeginOfSled);
1016 EmitToStreamer(S&: *OutStreamer,
1017 Inst: MCInstBuilder(SystemZ::BR).addReg(Reg: SystemZ::R14D));
1018 EmitNop(OutContext, OutStreamer&: *OutStreamer, NumBytes: 4, STI: getSubtargetInfo());
1019 EmitToStreamer(S&: *OutStreamer,
1020 Inst: MCInstBuilder(SystemZ::LLILF).addReg(Reg: SystemZ::R2D).addImm(Val: 0));
1021 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::J)
1022 .addExpr(Val: MCSymbolRefExpr::create(
1023 Symbol: FuncExit, specifier: SystemZ::S_PLT, Ctx&: OutContext)));
1024 if (FallthroughLabel)
1025 OutStreamer->emitLabel(Symbol: FallthroughLabel);
1026 recordSled(Sled: BeginOfSled, MI, Kind: SledKind::FUNCTION_EXIT, Version: 2);
1027}
1028
1029// The *alignment* of 128-bit vector types is different between the software
1030// and hardware vector ABIs. If the there is an externally visible use of a
1031// vector type in the module it should be annotated with an attribute.
1032void SystemZAsmPrinter::emitAttributes(Module &M) {
1033 if (M.getModuleFlag(Key: "s390x-visible-vector-ABI")) {
1034 bool HasVectorFeature =
1035 TM.getMCSubtargetInfo()->hasFeature(Feature: SystemZ::FeatureVector);
1036 OutStreamer->emitGNUAttribute(Tag: 8, Value: HasVectorFeature ? 2 : 1);
1037 }
1038}
1039
1040// Convert a SystemZ-specific constant pool modifier into the associated
1041// specifier.
1042static uint8_t getSpecifierFromModifier(SystemZCP::SystemZCPModifier Modifier) {
1043 switch (Modifier) {
1044 case SystemZCP::TLSGD:
1045 return SystemZ::S_TLSGD;
1046 case SystemZCP::TLSLDM:
1047 return SystemZ::S_TLSLDM;
1048 case SystemZCP::DTPOFF:
1049 return SystemZ::S_DTPOFF;
1050 case SystemZCP::NTPOFF:
1051 return SystemZ::S_NTPOFF;
1052 }
1053 llvm_unreachable("Invalid SystemCPModifier!");
1054}
1055
1056void SystemZAsmPrinter::emitMachineConstantPoolValue(
1057 MachineConstantPoolValue *MCPV) {
1058 auto *ZCPV = static_cast<SystemZConstantPoolValue*>(MCPV);
1059
1060 const MCExpr *Expr = MCSymbolRefExpr::create(
1061 Symbol: getSymbol(GV: ZCPV->getGlobalValue()),
1062 specifier: getSpecifierFromModifier(Modifier: ZCPV->getModifier()), Ctx&: OutContext);
1063 uint64_t Size = getDataLayout().getTypeAllocSize(Ty: ZCPV->getType());
1064
1065 OutStreamer->emitValue(Value: Expr, Size);
1066}
1067
1068// Emit the ctor or dtor list taking into account the init priority.
1069void SystemZAsmPrinter::emitXXStructorList(const DataLayout &DL,
1070 const Constant *List, bool IsCtor) {
1071 if (!TM.getTargetTriple().isOSBinFormatGOFF())
1072 return AsmPrinter::emitXXStructorList(DL, List, IsCtor);
1073
1074 SmallVector<Structor, 8> Structors;
1075 preprocessXXStructorList(DL, List, Structors);
1076 if (Structors.empty())
1077 return;
1078
1079 const Align Align = llvm::Align(4);
1080 const TargetLoweringObjectFileGOFF &Obj =
1081 static_cast<const TargetLoweringObjectFileGOFF &>(getObjFileLowering());
1082 for (Structor &S : Structors) {
1083 MCSectionGOFF *Section =
1084 static_cast<MCSectionGOFF *>(Obj.getStaticXtorSection(Priority: S.Priority));
1085 OutStreamer->switchSection(Section);
1086 if (OutStreamer->getCurrentSection() != OutStreamer->getPreviousSection())
1087 emitAlignment(Alignment: Align);
1088
1089 // The priority is provided as an input to getStaticXtorSection(), and is
1090 // recalculated within that function as `Prio` going to going into the
1091 // PR section.
1092 // This priority retrieved via the `SortKey` below is the recalculated
1093 // Priority.
1094 uint32_t XtorPriority = Section->getPRAttributes().SortKey;
1095
1096 const GlobalValue *GV = dyn_cast<GlobalValue>(Val: S.Func->stripPointerCasts());
1097 assert(GV && "C++ xxtor pointer was not a GlobalValue!");
1098 MCSymbolGOFF *Symbol = static_cast<MCSymbolGOFF *>(getSymbol(GV));
1099
1100 // @@SQINIT entry: { unsigned prio; void (*ctor)(); void (*dtor)(); }
1101
1102 unsigned PointerSizeInBytes = DL.getPointerSize();
1103
1104 auto &Ctx = OutStreamer->getContext();
1105 const MCExpr *ADAFuncRefExpr;
1106 unsigned SlotKind = SystemZII::MO_ADA_DIRECT_FUNC_DESC;
1107
1108 MCSectionGOFF *ADASection =
1109 static_cast<MCSectionGOFF *>(Obj.getADASection());
1110 assert(ADASection && "ADA section must exist for GOFF targets!");
1111 const MCSymbol *ADASym = ADASection->getBeginSymbol();
1112 assert(ADASym && "ADA symbol should already be set!");
1113
1114 ADAFuncRefExpr = MCBinaryExpr::createAdd(
1115 LHS: MCSpecifierExpr::create(Expr: MCSymbolRefExpr::create(Symbol: ADASym, Ctx&: OutContext),
1116 S: SystemZ::S_QCon, Ctx&: OutContext),
1117 RHS: MCConstantExpr::create(Value: ADATable.insert(Sym: Symbol, SlotKind), Ctx), Ctx);
1118
1119 emitInt32(Value: XtorPriority);
1120 if (IsCtor) {
1121 OutStreamer->emitValue(Value: ADAFuncRefExpr, Size: PointerSizeInBytes);
1122 OutStreamer->emitIntValue(Value: 0, Size: PointerSizeInBytes);
1123 } else {
1124 OutStreamer->emitIntValue(Value: 0, Size: PointerSizeInBytes);
1125 OutStreamer->emitValue(Value: ADAFuncRefExpr, Size: PointerSizeInBytes);
1126 }
1127 }
1128}
1129
1130static void printFormattedRegName(const MCAsmInfo *MAI, unsigned RegNo,
1131 raw_ostream &OS) {
1132 const char *RegName;
1133 if (MAI->getAssemblerDialect() == AD_HLASM) {
1134 RegName = SystemZHLASMInstPrinter::getRegisterName(Reg: RegNo);
1135 // Skip register prefix so that only register number is left
1136 assert(isalpha(RegName[0]) && isdigit(RegName[1]));
1137 OS << (RegName + 1);
1138 } else {
1139 RegName = SystemZGNUInstPrinter::getRegisterName(Reg: RegNo);
1140 OS << '%' << RegName;
1141 }
1142}
1143
1144static void printReg(unsigned Reg, const MCAsmInfo *MAI, raw_ostream &OS) {
1145 if (!Reg)
1146 OS << '0';
1147 else
1148 printFormattedRegName(MAI, RegNo: Reg, OS);
1149}
1150
1151static void printOperand(const MCOperand &MCOp, const MCAsmInfo *MAI,
1152 raw_ostream &OS) {
1153 if (MCOp.isReg())
1154 printReg(Reg: MCOp.getReg(), MAI, OS);
1155 else if (MCOp.isImm())
1156 OS << MCOp.getImm();
1157 else if (MCOp.isExpr())
1158 MAI->printExpr(OS, *MCOp.getExpr());
1159 else
1160 llvm_unreachable("Invalid operand");
1161}
1162
1163static void printAddress(const MCAsmInfo *MAI, unsigned Base,
1164 const MCOperand &DispMO, unsigned Index,
1165 raw_ostream &OS) {
1166 printOperand(MCOp: DispMO, MAI, OS);
1167 if (Base || Index) {
1168 OS << '(';
1169 if (Index) {
1170 printFormattedRegName(MAI, RegNo: Index, OS);
1171 if (Base)
1172 OS << ',';
1173 }
1174 if (Base)
1175 printFormattedRegName(MAI, RegNo: Base, OS);
1176 OS << ')';
1177 }
1178}
1179
1180bool SystemZAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
1181 const char *ExtraCode,
1182 raw_ostream &OS) {
1183 const MCRegisterInfo &MRI = *TM.getMCRegisterInfo();
1184 const MachineOperand &MO = MI->getOperand(i: OpNo);
1185 MCOperand MCOp;
1186 if (ExtraCode) {
1187 if (ExtraCode[0] == 'N' && !ExtraCode[1] && MO.isReg() &&
1188 SystemZ::GR128BitRegClass.contains(Reg: MO.getReg()))
1189 MCOp =
1190 MCOperand::createReg(Reg: MRI.getSubReg(Reg: MO.getReg(), Idx: SystemZ::subreg_l64));
1191 else
1192 return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS);
1193 } else {
1194 SystemZMCInstLower Lower(MF->getContext(), *this);
1195 MCOp = Lower.lowerOperand(MO);
1196 }
1197 printOperand(MCOp, MAI, OS);
1198 return false;
1199}
1200
1201bool SystemZAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1202 unsigned OpNo,
1203 const char *ExtraCode,
1204 raw_ostream &OS) {
1205 if (ExtraCode && ExtraCode[0] && !ExtraCode[1]) {
1206 switch (ExtraCode[0]) {
1207 case 'A':
1208 // Unlike EmitMachineNode(), EmitSpecialNode(INLINEASM) does not call
1209 // setMemRefs(), so MI->memoperands() is empty and the alignment
1210 // information is not available.
1211 return false;
1212 case 'O':
1213 OS << MI->getOperand(i: OpNo + 1).getImm();
1214 return false;
1215 case 'R':
1216 ::printReg(Reg: MI->getOperand(i: OpNo).getReg(), MAI, OS);
1217 return false;
1218 }
1219 }
1220 printAddress(MAI, Base: MI->getOperand(i: OpNo).getReg(),
1221 DispMO: MCOperand::createImm(Val: MI->getOperand(i: OpNo + 1).getImm()),
1222 Index: MI->getOperand(i: OpNo + 2).getReg(), OS);
1223 return false;
1224}
1225
1226void SystemZAsmPrinter::emitEndOfAsmFile(Module &M) {
1227 auto TT = OutContext.getTargetTriple();
1228 if (TT.isOSzOS()) {
1229 emitADASection();
1230 emitIDRLSection(M);
1231 }
1232 emitAttributes(M);
1233}
1234
1235void SystemZAsmPrinter::emitADASection() {
1236 OutStreamer->pushSection();
1237
1238 const unsigned PointerSize = getDataLayout().getPointerSize();
1239 OutStreamer->switchSection(Section: getObjFileLowering().getADASection());
1240
1241 unsigned EmittedBytes = 0;
1242 for (auto &Entry : ADATable.getTable()) {
1243 const MCSymbol *Sym;
1244 unsigned SlotKind;
1245 std::tie(args&: Sym, args&: SlotKind) = Entry.first;
1246 unsigned Offset = Entry.second;
1247 assert(Offset == EmittedBytes && "Offset not as expected");
1248 (void)EmittedBytes;
1249#define EMIT_COMMENT(Str) \
1250 OutStreamer->AddComment(Twine("Offset ") \
1251 .concat(utostr(Offset)) \
1252 .concat(" " Str " ") \
1253 .concat(Sym->getName()));
1254 switch (SlotKind) {
1255 case SystemZII::MO_ADA_DIRECT_FUNC_DESC:
1256 // Language Environment DLL logic requires function descriptors, for
1257 // imported functions, that are placed in the ADA to be 8 byte aligned.
1258 EMIT_COMMENT("function descriptor of");
1259 OutStreamer->emitValue(
1260 Value: MCSpecifierExpr::create(Expr: MCSymbolRefExpr::create(Symbol: Sym, Ctx&: OutContext),
1261 S: SystemZ::S_RCon, Ctx&: OutContext),
1262 Size: PointerSize);
1263 OutStreamer->emitValue(
1264 Value: MCSpecifierExpr::create(Expr: MCSymbolRefExpr::create(Symbol: Sym, Ctx&: OutContext),
1265 S: SystemZ::S_VCon, Ctx&: OutContext),
1266 Size: PointerSize);
1267 EmittedBytes += PointerSize * 2;
1268 break;
1269 case SystemZII::MO_ADA_DATA_SYMBOL_ADDR:
1270 EMIT_COMMENT("pointer to data symbol");
1271 OutStreamer->emitValue(
1272 Value: MCSpecifierExpr::create(Expr: MCSymbolRefExpr::create(Symbol: Sym, Ctx&: OutContext),
1273 S: SystemZ::S_None, Ctx&: OutContext),
1274 Size: PointerSize);
1275 EmittedBytes += PointerSize;
1276 break;
1277 case SystemZII::MO_ADA_INDIRECT_FUNC_DESC: {
1278 MCSymbol *Alias = OutContext.createTempSymbol(
1279 Name: Twine(Sym->getName()).concat(Suffix: "@indirect"));
1280 OutStreamer->emitAssignment(Symbol: Alias,
1281 Value: MCSymbolRefExpr::create(Symbol: Sym, Ctx&: OutContext));
1282 OutStreamer->emitSymbolAttribute(Symbol: Alias, Attribute: MCSA_IndirectSymbol);
1283
1284 EMIT_COMMENT("pointer to function descriptor");
1285 OutStreamer->emitValue(
1286 Value: MCSpecifierExpr::create(Expr: MCSymbolRefExpr::create(Symbol: Alias, Ctx&: OutContext),
1287 S: SystemZ::S_VCon, Ctx&: OutContext),
1288 Size: PointerSize);
1289 EmittedBytes += PointerSize;
1290 break;
1291 }
1292 default:
1293 llvm_unreachable("Unexpected slot kind");
1294 }
1295#undef EMIT_COMMENT
1296 }
1297 OutStreamer->popSection();
1298}
1299
1300static std::string getProductID(Module &M) {
1301 std::string ProductID;
1302 if (auto *MD = M.getModuleFlag(Key: "zos_product_id"))
1303 ProductID = cast<MDString>(Val: MD)->getString().str();
1304 if (ProductID.empty())
1305 ProductID = "LLVM";
1306 return ProductID;
1307}
1308
1309static uint32_t getProductVersion(Module &M) {
1310 if (auto *VersionVal = mdconst::extract_or_null<ConstantInt>(
1311 MD: M.getModuleFlag(Key: "zos_product_major_version")))
1312 return VersionVal->getZExtValue();
1313 return LLVM_VERSION_MAJOR;
1314}
1315
1316static uint32_t getProductRelease(Module &M) {
1317 if (auto *ReleaseVal = mdconst::extract_or_null<ConstantInt>(
1318 MD: M.getModuleFlag(Key: "zos_product_minor_version")))
1319 return ReleaseVal->getZExtValue();
1320 return LLVM_VERSION_MINOR;
1321}
1322
1323static uint32_t getProductPatch(Module &M) {
1324 if (auto *PatchVal = mdconst::extract_or_null<ConstantInt>(
1325 MD: M.getModuleFlag(Key: "zos_product_patchlevel")))
1326 return PatchVal->getZExtValue();
1327 return LLVM_VERSION_PATCH;
1328}
1329
1330static time_t getTranslationTime(Module &M) {
1331 std::time_t Time = 0;
1332 if (auto *Val = mdconst::extract_or_null<ConstantInt>(
1333 MD: M.getModuleFlag(Key: "zos_translation_time"))) {
1334 long SecondsSinceEpoch = Val->getSExtValue();
1335 Time = static_cast<time_t>(SecondsSinceEpoch);
1336 }
1337 return Time;
1338}
1339
1340void SystemZAsmPrinter::emitIDRLSection(Module &M) {
1341 OutStreamer->pushSection();
1342 OutStreamer->switchSection(Section: getObjFileLowering().getIDRLSection());
1343 constexpr unsigned IDRLDataLength = 30;
1344 std::time_t Time = getTranslationTime(M);
1345
1346 uint32_t ProductVersion = getProductVersion(M);
1347 uint32_t ProductRelease = getProductRelease(M);
1348
1349 std::string ProductID = getProductID(M);
1350
1351 SmallString<IDRLDataLength + 1> TempStr;
1352 raw_svector_ostream O(TempStr);
1353 O << formatv(Fmt: "{0,-10}{1,0-2:d}{2,0-2:d}{3:%Y%m%d%H%M%S}{4,0-2}",
1354 Vals: ProductID.substr(pos: 0, n: 10).c_str(), Vals&: ProductVersion, Vals&: ProductRelease,
1355 Vals: llvm::sys::toUtcTime(T: Time), Vals: "0");
1356 SmallString<IDRLDataLength> Data;
1357 ConverterEBCDIC::convertToEBCDIC(Source: TempStr, Result&: Data);
1358
1359 OutStreamer->emitInt8(Value: 0); // Reserved.
1360 OutStreamer->emitInt8(Value: 3); // Format.
1361 OutStreamer->emitInt16(Value: IDRLDataLength); // Length.
1362 OutStreamer->emitBytes(Data: Data.str());
1363 OutStreamer->popSection();
1364}
1365
1366void SystemZAsmPrinter::emitFunctionBodyEnd() {
1367 if (TM.getTargetTriple().isOSzOS()) {
1368 // Emit symbol for the end of function if the z/OS target streamer
1369 // is used. This is needed to calculate the size of the function.
1370 MCSymbol *FnEndSym = createTempSymbol(Name: "func_end");
1371 OutStreamer->emitLabel(Symbol: FnEndSym);
1372
1373 OutStreamer->pushSection();
1374 OutStreamer->switchSection(Section: getObjFileLowering().getTextSection(),
1375 Subsec: GOFF::SK_PPA1);
1376 emitPPA1(FnEndSym);
1377 OutStreamer->popSection();
1378
1379 CurrentFnPPA1Sym = nullptr;
1380 CurrentFnEPMarkerSym = nullptr;
1381 }
1382}
1383
1384static void emitPPA1Flags(std::unique_ptr<MCStreamer> &OutStreamer, bool VarArg,
1385 bool StackProtector, bool FPRMask, bool VRMask,
1386 bool EHBlock, bool HasArgAreaLength, bool HasName) {
1387 enum class PPA1Flag1 : uint8_t {
1388 DSA64Bit = (0x80 >> 0),
1389 VarArg = (0x80 >> 7),
1390 LLVM_MARK_AS_BITMASK_ENUM(DSA64Bit)
1391 };
1392 enum class PPA1Flag2 : uint8_t {
1393 ExternalProcedure = (0x80 >> 0),
1394 STACKPROTECTOR = (0x80 >> 3),
1395 LLVM_MARK_AS_BITMASK_ENUM(ExternalProcedure)
1396 };
1397 enum class PPA1Flag3 : uint8_t {
1398 HasArgAreaLength = (0x80 >> 1),
1399 FPRMask = (0x80 >> 2),
1400 LLVM_MARK_AS_BITMASK_ENUM(HasArgAreaLength)
1401 };
1402 enum class PPA1Flag4 : uint8_t {
1403 EPMOffsetPresent = (0x80 >> 0),
1404 VRMask = (0x80 >> 2),
1405 EHBlock = (0x80 >> 3),
1406 ProcedureNamePresent = (0x80 >> 7),
1407 LLVM_MARK_AS_BITMASK_ENUM(EPMOffsetPresent)
1408 };
1409
1410 // Declare optional section flags that can be modified.
1411 auto Flags1 = PPA1Flag1(0);
1412 auto Flags2 = PPA1Flag2::ExternalProcedure;
1413 auto Flags3 = PPA1Flag3(0);
1414 auto Flags4 = PPA1Flag4::EPMOffsetPresent;
1415
1416 Flags1 |= PPA1Flag1::DSA64Bit;
1417
1418 if (VarArg)
1419 Flags1 |= PPA1Flag1::VarArg;
1420
1421 if (StackProtector)
1422 Flags2 |= PPA1Flag2::STACKPROTECTOR;
1423
1424 if (HasArgAreaLength)
1425 Flags3 |= PPA1Flag3::HasArgAreaLength; // Add emit ArgAreaLength flag.
1426
1427 // SavedGPRMask, SavedFPRMask, and SavedVRMask are precomputed in.
1428 if (FPRMask)
1429 Flags3 |= PPA1Flag3::FPRMask; // Add emit FPR mask flag.
1430
1431 if (VRMask)
1432 Flags4 |= PPA1Flag4::VRMask; // Add emit VR mask flag.
1433
1434 if (EHBlock)
1435 Flags4 |= PPA1Flag4::EHBlock; // Add optional EH block.
1436
1437 if (HasName)
1438 Flags4 |= PPA1Flag4::ProcedureNamePresent; // Add optional name block.
1439
1440 OutStreamer->AddComment(T: "PPA1 Flags 1");
1441 if ((Flags1 & PPA1Flag1::DSA64Bit) == PPA1Flag1::DSA64Bit)
1442 OutStreamer->AddComment(T: " Bit 0: 1 = 64-bit DSA");
1443 else
1444 OutStreamer->AddComment(T: " Bit 0: 0 = 32-bit DSA");
1445 if ((Flags1 & PPA1Flag1::VarArg) == PPA1Flag1::VarArg)
1446 OutStreamer->AddComment(T: " Bit 7: 1 = Vararg function");
1447 OutStreamer->emitInt8(Value: static_cast<uint8_t>(Flags1)); // Flags 1.
1448
1449 OutStreamer->AddComment(T: "PPA1 Flags 2");
1450 if ((Flags2 & PPA1Flag2::ExternalProcedure) == PPA1Flag2::ExternalProcedure)
1451 OutStreamer->AddComment(T: " Bit 0: 1 = External procedure");
1452 if ((Flags2 & PPA1Flag2::STACKPROTECTOR) == PPA1Flag2::STACKPROTECTOR)
1453 OutStreamer->AddComment(T: " Bit 3: 1 = STACKPROTECT is enabled");
1454 else
1455 OutStreamer->AddComment(T: " Bit 3: 0 = STACKPROTECT is not enabled");
1456 OutStreamer->emitInt8(Value: static_cast<uint8_t>(Flags2)); // Flags 2.
1457
1458 OutStreamer->AddComment(T: "PPA1 Flags 3");
1459 if ((Flags3 & PPA1Flag3::HasArgAreaLength) == PPA1Flag3::HasArgAreaLength)
1460 OutStreamer->AddComment(
1461 T: " Bit 1: 1 = Argument Area Length is in optional area");
1462 if ((Flags3 & PPA1Flag3::FPRMask) == PPA1Flag3::FPRMask)
1463 OutStreamer->AddComment(T: " Bit 2: 1 = FP Reg Mask is in optional area");
1464 OutStreamer->emitInt8(
1465 Value: static_cast<uint8_t>(Flags3)); // Flags 3 (optional sections).
1466
1467 OutStreamer->AddComment(T: "PPA1 Flags 4");
1468 if ((Flags4 & PPA1Flag4::VRMask) == PPA1Flag4::VRMask)
1469 OutStreamer->AddComment(T: " Bit 2: 1 = Vector Reg Mask is in optional area");
1470 if ((Flags4 & PPA1Flag4::EHBlock) == PPA1Flag4::EHBlock)
1471 OutStreamer->AddComment(T: " Bit 3: 1 = C++ EH block");
1472 if ((Flags4 & PPA1Flag4::ProcedureNamePresent) ==
1473 PPA1Flag4::ProcedureNamePresent)
1474 OutStreamer->AddComment(T: " Bit 7: 1 = Name Length and Name");
1475 OutStreamer->emitInt8(Value: static_cast<uint8_t>(
1476 Flags4)); // Flags 4 (optional sections, always emit these).
1477}
1478
1479static void emitPPA1Name(std::unique_ptr<MCStreamer> &OutStreamer,
1480 StringRef OutName) {
1481 size_t NameSize = OutName.size();
1482 uint16_t OutSize;
1483 if (NameSize < UINT16_MAX) {
1484 OutSize = static_cast<uint16_t>(NameSize);
1485 } else {
1486 OutName = OutName.substr(Start: 0, UINT16_MAX);
1487 OutSize = UINT16_MAX;
1488 }
1489 // Emit padding to ensure that the next optional field word-aligned.
1490 uint8_t ExtraZeros = 4 - ((2 + OutSize) % 4);
1491
1492 SmallString<512> OutnameConv;
1493 ConverterEBCDIC::convertToEBCDIC(Source: OutName, Result&: OutnameConv);
1494 OutName = OutnameConv.str();
1495
1496 OutStreamer->AddComment(T: "Length of Name");
1497 OutStreamer->emitInt16(Value: OutSize);
1498 OutStreamer->AddComment(T: "Name of Function");
1499 OutStreamer->emitBytes(Data: OutName);
1500 OutStreamer->emitZeros(NumBytes: ExtraZeros);
1501}
1502
1503void SystemZAsmPrinter::emitPPA1(MCSymbol *FnEndSym) {
1504 assert(PPA2Sym != nullptr && "PPA2 Symbol not defined");
1505
1506 const TargetRegisterInfo *TRI = MF->getRegInfo().getTargetRegisterInfo();
1507 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
1508 const auto TargetHasVector = Subtarget.hasVector();
1509
1510 const SystemZMachineFunctionInfo *ZFI =
1511 MF->getInfo<SystemZMachineFunctionInfo>();
1512 const auto *ZFL = static_cast<const SystemZXPLINKFrameLowering *>(
1513 Subtarget.getFrameLowering());
1514 const MachineFrameInfo &MFFrame = MF->getFrameInfo();
1515
1516 // Get saved GPR/FPR/VPR masks.
1517 const std::vector<CalleeSavedInfo> &CSI = MFFrame.getCalleeSavedInfo();
1518 uint16_t SavedGPRMask = 0;
1519 uint16_t SavedFPRMask = 0;
1520 uint8_t SavedVRMask = 0;
1521 int64_t OffsetFPR = 0;
1522 int64_t OffsetVR = 0;
1523 const int64_t TopOfStack =
1524 MFFrame.getOffsetAdjustment() + MFFrame.getStackSize();
1525
1526 // Loop over the spilled registers. The CalleeSavedInfo can't be used because
1527 // it does not contain all spilled registers.
1528 for (unsigned I = ZFI->getSpillGPRRegs().LowGPR,
1529 E = ZFI->getSpillGPRRegs().HighGPR;
1530 I && E && I <= E; ++I) {
1531 unsigned V = TRI->getEncodingValue(Reg: (Register)I);
1532 assert(V < 16 && "GPR index out of range");
1533 SavedGPRMask |= 1 << (15 - V);
1534 }
1535
1536 for (auto &CS : CSI) {
1537 unsigned Reg = CS.getReg();
1538 unsigned I = TRI->getEncodingValue(Reg);
1539
1540 if (SystemZ::FP64BitRegClass.contains(Reg)) {
1541 assert(I < 16 && "FPR index out of range");
1542 SavedFPRMask |= 1 << (15 - I);
1543 int64_t Temp = MFFrame.getObjectOffset(ObjectIdx: CS.getFrameIdx());
1544 if (Temp < OffsetFPR)
1545 OffsetFPR = Temp;
1546 } else if (SystemZ::VR128BitRegClass.contains(Reg)) {
1547 assert(I >= 16 && I <= 23 && "VPR index out of range");
1548 unsigned BitNum = I - 16;
1549 SavedVRMask |= 1 << (7 - BitNum);
1550 int64_t Temp = MFFrame.getObjectOffset(ObjectIdx: CS.getFrameIdx());
1551 if (Temp < OffsetVR)
1552 OffsetVR = Temp;
1553 }
1554 }
1555
1556 // Adjust the offset.
1557 OffsetFPR += (OffsetFPR < 0) ? TopOfStack : 0;
1558 OffsetVR += (OffsetVR < 0) ? TopOfStack : 0;
1559
1560 // Get alloca register.
1561 uint8_t FrameReg = TRI->getEncodingValue(Reg: TRI->getFrameRegister(MF: *MF));
1562 uint8_t AllocaReg = ZFL->hasFP(MF: *MF) ? FrameReg : 0;
1563 assert(AllocaReg < 16 && "Can't have alloca register larger than 15");
1564 (void)AllocaReg;
1565
1566 // Build FPR save area offset.
1567 uint32_t FrameAndFPROffset = 0;
1568 if (SavedFPRMask) {
1569 uint64_t FPRSaveAreaOffset = OffsetFPR;
1570 assert(FPRSaveAreaOffset < 0x10000000 && "Offset out of range");
1571
1572 FrameAndFPROffset = FPRSaveAreaOffset & 0x0FFFFFFF; // Lose top 4 bits.
1573 FrameAndFPROffset |= FrameReg << 28; // Put into top 4 bits.
1574 }
1575
1576 // Build VR save area offset.
1577 uint32_t FrameAndVROffset = 0;
1578 if (TargetHasVector && SavedVRMask) {
1579 uint64_t VRSaveAreaOffset = OffsetVR;
1580 assert(VRSaveAreaOffset < 0x10000000 && "Offset out of range");
1581
1582 FrameAndVROffset = VRSaveAreaOffset & 0x0FFFFFFF; // Lose top 4 bits.
1583 FrameAndVROffset |= FrameReg << 28; // Put into top 4 bits.
1584 }
1585
1586 // Emit PPA1 section.
1587 OutStreamer->AddComment(T: "PPA1");
1588 OutStreamer->emitLabel(Symbol: CurrentFnPPA1Sym);
1589 OutStreamer->AddComment(T: "Version");
1590 OutStreamer->emitInt8(Value: 0x02); // Version.
1591 OutStreamer->AddComment(T: "LE Signature X'CE'");
1592 OutStreamer->emitInt8(Value: 0xCE); // CEL signature.
1593 OutStreamer->AddComment(T: "Saved GPR Mask");
1594 OutStreamer->emitInt16(Value: SavedGPRMask);
1595 OutStreamer->AddComment(T: "Offset to PPA2");
1596 OutStreamer->emitAbsoluteSymbolDiff(Hi: PPA2Sym, Lo: CurrentFnPPA1Sym, Size: 4);
1597
1598 bool NeedEmitEHBlock = !MF->getLandingPads().empty();
1599
1600 // Optional Argument Area Length.
1601 // Note: This represents the length of the argument area that we reserve
1602 // in our stack for setting up arguments for calls to other
1603 // routines. If this optional field is not set, LE will reserve
1604 // 128 bytes for the argument area. This optional field is
1605 // created if greater than 128 bytes is required - to guarantee
1606 // the required space is reserved on stack extension in the new
1607 // extension. This optional field is also created if the
1608 // routine has alloca(). This may reduce stack space
1609 // if alloca() call causes a stack extension.
1610 bool HasArgAreaLength =
1611 (AllocaReg != 0) || (MFFrame.getMaxCallFrameSize() > 128);
1612
1613 bool HasName =
1614 MF->getFunction().hasName() && MF->getFunction().getName().size() > 0;
1615
1616 emitPPA1Flags(OutStreamer, VarArg: MF->getFunction().isVarArg(),
1617 StackProtector: MFFrame.hasStackProtectorIndex(), FPRMask: SavedFPRMask != 0,
1618 VRMask: TargetHasVector && SavedVRMask != 0, EHBlock: NeedEmitEHBlock,
1619 HasArgAreaLength, HasName);
1620
1621 OutStreamer->AddComment(T: "Length/4 of Parms");
1622 OutStreamer->emitInt16(
1623 Value: static_cast<uint16_t>(ZFI->getSizeOfFnParams() / 4)); // Parms/4.
1624 OutStreamer->AddComment(T: "Length of Code");
1625 OutStreamer->emitAbsoluteSymbolDiff(Hi: FnEndSym, Lo: CurrentFnEPMarkerSym, Size: 4);
1626
1627 if (HasArgAreaLength) {
1628 OutStreamer->AddComment(T: "Argument Area Length");
1629 OutStreamer->emitInt32(Value: MFFrame.getMaxCallFrameSize());
1630 }
1631
1632 // Emit saved FPR mask and offset to FPR save area (0x20 of flags 3).
1633 if (SavedFPRMask) {
1634 OutStreamer->AddComment(T: "FPR mask");
1635 OutStreamer->emitInt16(Value: SavedFPRMask);
1636 OutStreamer->AddComment(T: "AR mask");
1637 OutStreamer->emitInt16(Value: 0); // AR Mask, unused currently.
1638 OutStreamer->AddComment(T: "FPR Save Area Locator");
1639 OutStreamer->AddComment(T: Twine(" Bit 0-3: Register R")
1640 .concat(Suffix: utostr(X: FrameAndFPROffset >> 28))
1641 .str());
1642 OutStreamer->AddComment(T: Twine(" Bit 4-31: Offset ")
1643 .concat(Suffix: utostr(X: FrameAndFPROffset & 0x0FFFFFFF))
1644 .str());
1645 OutStreamer->emitInt32(Value: FrameAndFPROffset); // Offset to FPR save area with
1646 // register to add value to
1647 // (alloca reg).
1648 }
1649
1650 // Emit saved VR mask to VR save area.
1651 if (TargetHasVector && SavedVRMask) {
1652 OutStreamer->AddComment(T: "VR mask");
1653 OutStreamer->emitInt8(Value: SavedVRMask);
1654 OutStreamer->emitInt8(Value: 0); // Reserved.
1655 OutStreamer->emitInt16(Value: 0); // Also reserved.
1656 OutStreamer->AddComment(T: "VR Save Area Locator");
1657 OutStreamer->AddComment(T: Twine(" Bit 0-3: Register R")
1658 .concat(Suffix: utostr(X: FrameAndVROffset >> 28))
1659 .str());
1660 OutStreamer->AddComment(T: Twine(" Bit 4-31: Offset ")
1661 .concat(Suffix: utostr(X: FrameAndVROffset & 0x0FFFFFFF))
1662 .str());
1663 OutStreamer->emitInt32(Value: FrameAndVROffset);
1664 }
1665
1666 // Emit C++ EH information block
1667 const Function *Per = nullptr;
1668 if (NeedEmitEHBlock) {
1669 Per = dyn_cast<Function>(
1670 Val: MF->getFunction().getPersonalityFn()->stripPointerCasts());
1671 MCSymbol *PersonalityRoutine =
1672 Per ? MF->getTarget().getSymbol(GV: Per) : nullptr;
1673 assert(PersonalityRoutine && "Missing personality routine");
1674
1675 OutStreamer->AddComment(T: "Version");
1676 OutStreamer->emitInt32(Value: 1);
1677 OutStreamer->AddComment(T: "Flags");
1678 OutStreamer->emitInt32(Value: 0); // LSDA field is a WAS offset
1679 OutStreamer->AddComment(T: "Personality routine");
1680 OutStreamer->emitInt64(Value: ADATable.insert(
1681 Sym: PersonalityRoutine, SlotKind: SystemZII::MO_ADA_INDIRECT_FUNC_DESC));
1682 OutStreamer->AddComment(T: "LSDA location");
1683 MCSymbol *GCCEH = MF->getContext().getOrCreateSymbol(
1684 Name: Twine("GCC_except_table") + Twine(MF->getFunctionNumber()));
1685 OutStreamer->emitInt64(
1686 Value: ADATable.insert(Sym: GCCEH, SlotKind: SystemZII::MO_ADA_DATA_SYMBOL_ADDR));
1687 }
1688
1689 // Emit name length and name optional section (0x01 of flags 4)
1690 if (HasName)
1691 emitPPA1Name(OutStreamer, OutName: MF->getFunction().getName());
1692
1693 // Emit offset to entry point optional section (0x80 of flags 4).
1694 OutStreamer->emitAbsoluteSymbolDiff(Hi: CurrentFnEPMarkerSym, Lo: CurrentFnPPA1Sym,
1695 Size: 4);
1696}
1697
1698void SystemZAsmPrinter::emitStartOfAsmFile(Module &M) {
1699 if (TM.getTargetTriple().isOSzOS())
1700 emitPPA2(M);
1701 AsmPrinter::emitStartOfAsmFile(M);
1702}
1703
1704void SystemZAsmPrinter::emitPPA2(Module &M) {
1705 OutStreamer->pushSection();
1706 OutStreamer->switchSection(Section: getObjFileLowering().getTextSection(),
1707 Subsec: GOFF::SK_PPA2);
1708 MCContext &OutContext = OutStreamer->getContext();
1709 // Make CELQSTRT symbol.
1710 const char *StartSymbolName = "CELQSTRT";
1711 MCSymbol *CELQSTRT = OutContext.getOrCreateSymbol(Name: StartSymbolName);
1712 OutStreamer->emitSymbolAttribute(Symbol: CELQSTRT, Attribute: MCSA_OSLinkage);
1713 OutStreamer->emitSymbolAttribute(Symbol: CELQSTRT, Attribute: MCSA_Global);
1714
1715 // Create symbol and assign to class field for use in PPA1.
1716 PPA2Sym = OutContext.createTempSymbol(Name: "PPA2", AlwaysAddSuffix: false);
1717 MCSymbol *DateVersionSym = OutContext.createTempSymbol(Name: "DVS", AlwaysAddSuffix: false);
1718
1719 std::time_t Time = getTranslationTime(M);
1720 SmallString<14> CompilationTimeEBCDIC, CompilationTime;
1721 CompilationTime = formatv(Fmt: "{0:%Y%m%d%H%M%S}", Vals: llvm::sys::toUtcTime(T: Time));
1722
1723 uint32_t ProductVersion = getProductVersion(M),
1724 ProductRelease = getProductRelease(M),
1725 ProductPatch = getProductPatch(M);
1726
1727 SmallString<6> VersionEBCDIC, Version;
1728 Version = formatv(Fmt: "{0,0-2:d}{1,0-2:d}{2,0-2:d}", Vals&: ProductVersion,
1729 Vals&: ProductRelease, Vals&: ProductPatch);
1730
1731 ConverterEBCDIC::convertToEBCDIC(Source: CompilationTime, Result&: CompilationTimeEBCDIC);
1732 ConverterEBCDIC::convertToEBCDIC(Source: Version, Result&: VersionEBCDIC);
1733
1734 enum class PPA2MemberId : uint8_t {
1735 // See z/OS Language Environment Vendor Interfaces v2r5, p.23, for
1736 // complete list. Only the C runtime is supported by this backend.
1737 LE_C_Runtime = 3,
1738 };
1739 enum class PPA2MemberSubId : uint8_t {
1740 // List of languages using the LE C runtime implementation.
1741 C = 0x00,
1742 CXX = 0x01,
1743 Swift = 0x03,
1744 Go = 0x60,
1745 LLVMBasedLang = 0xe7,
1746 };
1747 // PPA2 Flags
1748 enum class PPA2Flags : uint8_t {
1749 CompileForBinaryFloatingPoint = 0x80,
1750 CompiledWithXPLink = 0x01,
1751 CompiledUnitASCII = 0x04,
1752 HasServiceInfo = 0x20,
1753 };
1754
1755 PPA2MemberSubId MemberSubId = PPA2MemberSubId::LLVMBasedLang;
1756 if (auto *MD = M.getModuleFlag(Key: "zos_cu_language")) {
1757 StringRef Language = cast<MDString>(Val: MD)->getString();
1758 MemberSubId = StringSwitch<PPA2MemberSubId>(Language)
1759 .Case(S: "C", Value: PPA2MemberSubId::C)
1760 .Case(S: "C++", Value: PPA2MemberSubId::CXX)
1761 .Case(S: "Swift", Value: PPA2MemberSubId::Swift)
1762 .Case(S: "Go", Value: PPA2MemberSubId::Go)
1763 .Default(Value: PPA2MemberSubId::LLVMBasedLang);
1764 }
1765
1766 // Emit PPA2 section.
1767 OutStreamer->emitLabel(Symbol: PPA2Sym);
1768 OutStreamer->emitInt8(Value: static_cast<uint8_t>(PPA2MemberId::LE_C_Runtime));
1769 OutStreamer->emitInt8(Value: static_cast<uint8_t>(MemberSubId));
1770 OutStreamer->emitInt8(Value: 0x22); // Member defined, c370_plist+c370_env
1771 OutStreamer->emitInt8(Value: 0x04); // Control level 4 (XPLink)
1772 OutStreamer->emitAbsoluteSymbolDiff(Hi: CELQSTRT, Lo: PPA2Sym, Size: 4);
1773 OutStreamer->emitInt32(Value: 0x00000000);
1774 OutStreamer->emitAbsoluteSymbolDiff(Hi: DateVersionSym, Lo: PPA2Sym, Size: 4);
1775 OutStreamer->emitInt32(
1776 Value: 0x00000000); // Offset to main entry point, always 0 (so says TR).
1777 uint8_t Flgs = static_cast<uint8_t>(PPA2Flags::CompileForBinaryFloatingPoint);
1778 Flgs |= static_cast<uint8_t>(PPA2Flags::CompiledWithXPLink);
1779
1780 bool IsASCII = true;
1781 if (auto *MD = M.getModuleFlag(Key: "zos_le_char_mode")) {
1782 const StringRef &CharMode = cast<MDString>(Val: MD)->getString();
1783 if (CharMode == "ebcdic")
1784 IsASCII = false;
1785 else if (CharMode != "ascii")
1786 OutContext.reportError(
1787 L: {}, Msg: "Only ascii or ebcdic are allowed for zos_le_char_mode");
1788 }
1789 if (IsASCII)
1790 Flgs |= static_cast<uint8_t>(
1791 PPA2Flags::CompiledUnitASCII); // Setting bit for ASCII char. mode.
1792
1793 OutStreamer->emitInt8(Value: Flgs);
1794 OutStreamer->emitInt8(Value: 0x00); // Reserved.
1795 // No MD5 signature before timestamp.
1796 // No FLOAT(AFP(VOLATILE)).
1797 // Remaining 5 flag bits reserved.
1798 OutStreamer->emitInt16(Value: 0x0000); // 16 Reserved flag bits.
1799
1800 // Emit date and version section.
1801 OutStreamer->emitLabel(Symbol: DateVersionSym);
1802 OutStreamer->emitBytes(Data: CompilationTimeEBCDIC.str());
1803 OutStreamer->emitBytes(Data: VersionEBCDIC.str());
1804
1805 OutStreamer->emitInt16(Value: 0x0000); // Service level string length.
1806
1807 // The binder requires that the offset to the PPA2 be emitted in a different,
1808 // specially-named section.
1809 OutStreamer->switchSection(Section: getObjFileLowering().getPPA2ListSection());
1810 // Emit 8 byte alignment.
1811 // Emit pointer to PPA2 label.
1812 OutStreamer->AddComment(T: "A(PPA2-CELQSTRT)");
1813 OutStreamer->emitAbsoluteSymbolDiff(Hi: PPA2Sym, Lo: CELQSTRT, Size: 8);
1814 OutStreamer->popSection();
1815}
1816
1817void SystemZAsmPrinter::emitGlobalAlias(const Module &M,
1818 const GlobalAlias &GA) {
1819 if (!TM.getTargetTriple().isOSzOS())
1820 return AsmPrinter::emitGlobalAlias(M, GA);
1821
1822 // Aliased function labels have already been emitted for z/OS
1823}
1824
1825const MCExpr *SystemZAsmPrinter::lowerConstant(const Constant *CV,
1826 const Constant *BaseCV,
1827 uint64_t Offset) {
1828 const Triple &TargetTriple = TM.getTargetTriple();
1829
1830 if (TargetTriple.isOSzOS()) {
1831 const GlobalAlias *GA = dyn_cast<GlobalAlias>(Val: CV);
1832 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Val: CV);
1833 const Function *FV = dyn_cast<Function>(Val: CV);
1834 bool IsFunc = !GV && (FV || (GA && isa<Function>(Val: GA->getAliaseeObject())));
1835
1836 MCSymbol *Sym = NULL;
1837
1838 if (GA)
1839 Sym = getSymbol(GV: GA);
1840 else if (IsFunc)
1841 Sym = getSymbol(GV: FV);
1842 else if (GV)
1843 Sym = getSymbol(GV);
1844
1845 if (IsFunc) {
1846 OutStreamer->emitSymbolAttribute(Symbol: Sym, Attribute: MCSA_ELF_TypeFunction);
1847 if (FV->hasExternalLinkage())
1848 return MCSpecifierExpr::create(Expr: MCSymbolRefExpr::create(Symbol: Sym, Ctx&: OutContext),
1849 S: SystemZ::S_VCon, Ctx&: OutContext);
1850 // Trigger creation of function descriptor in ADA for internal
1851 // functions.
1852 unsigned Disp = ADATable.insert(Sym, SlotKind: SystemZII::MO_ADA_DIRECT_FUNC_DESC);
1853 return MCBinaryExpr::createAdd(
1854 LHS: MCSpecifierExpr::create(
1855 Expr: MCSymbolRefExpr::create(
1856 Symbol: getObjFileLowering().getADASection()->getBeginSymbol(),
1857 Ctx&: OutContext),
1858 S: SystemZ::S_None, Ctx&: OutContext),
1859 RHS: MCConstantExpr::create(Value: Disp, Ctx&: OutContext), Ctx&: OutContext);
1860 }
1861 if (Sym) {
1862 OutStreamer->emitSymbolAttribute(Symbol: Sym, Attribute: MCSA_ELF_TypeObject);
1863 return MCSymbolRefExpr::create(Symbol: Sym, Ctx&: OutContext);
1864 }
1865 }
1866 return AsmPrinter::lowerConstant(CV);
1867}
1868
1869void SystemZAsmPrinter::emitFunctionEntryLabel() {
1870 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
1871
1872 if (Subtarget.getTargetTriple().isOSzOS()) {
1873 MCContext &OutContext = OutStreamer->getContext();
1874
1875 // Save information for later use.
1876 std::string N(MF->getFunction().hasName()
1877 ? Twine(MF->getFunction().getName()).concat(Suffix: "_").str()
1878 : "");
1879
1880 CurrentFnEPMarkerSym =
1881 OutContext.createTempSymbol(Name: Twine("EPM_").concat(Suffix: N).str(), AlwaysAddSuffix: true);
1882 CurrentFnPPA1Sym =
1883 OutContext.createTempSymbol(Name: Twine("PPA1_").concat(Suffix: N).str(), AlwaysAddSuffix: true);
1884
1885 // EntryPoint Marker
1886 const MachineFrameInfo &MFFrame = MF->getFrameInfo();
1887 bool IsUsingAlloca = MFFrame.hasVarSizedObjects();
1888 uint32_t DSASize = MFFrame.getStackSize();
1889 bool IsLeaf = DSASize == 0 && MFFrame.getCalleeSavedInfo().empty();
1890
1891 // Set Flags.
1892 uint8_t Flags = 0;
1893 if (IsLeaf)
1894 Flags |= 0x08;
1895 if (IsUsingAlloca)
1896 Flags |= 0x04;
1897
1898 // Combine into top 27 bits of DSASize and bottom 5 bits of Flags.
1899 uint32_t DSAAndFlags = DSASize & 0xFFFFFFE0; // (x/32) << 5
1900 DSAAndFlags |= Flags;
1901
1902 // Emit entry point marker section.
1903 OutStreamer->AddComment(T: "XPLINK Routine Layout Entry");
1904 OutStreamer->emitLabel(Symbol: CurrentFnEPMarkerSym);
1905 OutStreamer->AddComment(T: "Eyecatcher 0x00C300C500C500");
1906 OutStreamer->emitIntValueInHex(Value: 0x00C300C500C500, Size: 7); // Eyecatcher.
1907 OutStreamer->AddComment(T: "Mark Type C'1'");
1908 OutStreamer->emitInt8(Value: 0xF1); // Mark Type.
1909 OutStreamer->AddComment(T: "Offset to PPA1");
1910 OutStreamer->emitAbsoluteSymbolDiff(Hi: CurrentFnPPA1Sym, Lo: CurrentFnEPMarkerSym,
1911 Size: 4);
1912 if (OutStreamer->isVerboseAsm()) {
1913 OutStreamer->AddComment(T: "DSA Size 0x" + Twine::utohexstr(Val: DSASize));
1914 OutStreamer->AddComment(T: "Entry Flags");
1915 if (Flags & 0x08)
1916 OutStreamer->AddComment(T: " Bit 1: 1 = Leaf function");
1917 else
1918 OutStreamer->AddComment(T: " Bit 1: 0 = Non-leaf function");
1919 if (Flags & 0x04)
1920 OutStreamer->AddComment(T: " Bit 2: 1 = Uses alloca");
1921 else
1922 OutStreamer->AddComment(T: " Bit 2: 0 = Does not use alloca");
1923 }
1924 OutStreamer->emitInt32(Value: DSAAndFlags);
1925 }
1926
1927 AsmPrinter::emitFunctionEntryLabel();
1928
1929 if (Subtarget.getTargetTriple().isOSzOS()) {
1930 const Function *F = &MF->getFunction();
1931 // Emit aliasing label for function entry point label.
1932 for (const GlobalAlias *Alias : GOAliasMap[F]) {
1933 MCSymbol *Sym = getSymbol(GV: Alias);
1934 OutStreamer->emitSymbolAttribute(Symbol: Sym, Attribute: MCSA_ELF_TypeFunction);
1935 emitVisibility(Sym, Visibility: Alias->getVisibility());
1936 emitLinkage(GV: Alias, GVSym: Sym);
1937 OutStreamer->emitLabel(Symbol: Sym);
1938 }
1939 }
1940}
1941
1942char SystemZAsmPrinter::ID = 0;
1943
1944INITIALIZE_PASS(SystemZAsmPrinter, "systemz-asm-printer",
1945 "SystemZ Assembly Printer", false, false)
1946
1947// Force static initialization.
1948extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
1949LLVMInitializeSystemZAsmPrinter() {
1950 RegisterAsmPrinter<SystemZAsmPrinter> X(getTheSystemZTarget());
1951}
1952