1//===- WebAssemblyInstructionSelector.cpp ------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements the targeting of the InstructionSelector class for
10/// WebAssembly.
11/// \todo This should be generated by TableGen.
12//===----------------------------------------------------------------------===//
13
14#include "GISel/WebAssemblyRegisterBankInfo.h"
15#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
16#include "WebAssemblyRegisterInfo.h"
17#include "WebAssemblySubtarget.h"
18#include "WebAssemblyTargetMachine.h"
19#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
20#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
21#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
22#include "llvm/CodeGen/GlobalISel/Utils.h"
23#include "llvm/CodeGen/MachineOperand.h"
24#include "llvm/CodeGen/TargetLowering.h"
25#include "llvm/IR/IntrinsicsWebAssembly.h"
26
27#define DEBUG_TYPE "wasm-isel"
28
29using namespace llvm;
30
31namespace {
32
33#define GET_GLOBALISEL_PREDICATE_BITSET
34#include "WebAssemblyGenGlobalISel.inc"
35#undef GET_GLOBALISEL_PREDICATE_BITSET
36
37class WebAssemblyInstructionSelector : public InstructionSelector {
38public:
39 WebAssemblyInstructionSelector(const WebAssemblyTargetMachine &TM,
40 const WebAssemblySubtarget &STI,
41 const WebAssemblyRegisterBankInfo &RBI);
42
43 bool select(MachineInstr &I) override;
44
45 static const char *getName() { return DEBUG_TYPE; }
46
47private:
48 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
49
50 const WebAssemblyTargetMachine &TM;
51 // const WebAssemblySubtarget &STI;
52 const WebAssemblyInstrInfo &TII;
53 const WebAssemblyRegisterInfo &TRI;
54 const WebAssemblyRegisterBankInfo &RBI;
55
56#define GET_GLOBALISEL_PREDICATES_DECL
57#include "WebAssemblyGenGlobalISel.inc"
58#undef GET_GLOBALISEL_PREDICATES_DECL
59
60#define GET_GLOBALISEL_TEMPORARIES_DECL
61#include "WebAssemblyGenGlobalISel.inc"
62#undef GET_GLOBALISEL_TEMPORARIES_DECL
63};
64
65} // end anonymous namespace
66
67#define GET_GLOBALISEL_IMPL
68#include "WebAssemblyGenGlobalISel.inc"
69#undef GET_GLOBALISEL_IMPL
70
71WebAssemblyInstructionSelector::WebAssemblyInstructionSelector(
72 const WebAssemblyTargetMachine &TM, const WebAssemblySubtarget &STI,
73 const WebAssemblyRegisterBankInfo &RBI)
74 : TM(TM), /*STI(STI),*/ TII(*STI.getInstrInfo()),
75 TRI(*STI.getRegisterInfo()), RBI(RBI),
76
77#define GET_GLOBALISEL_PREDICATES_INIT
78#include "WebAssemblyGenGlobalISel.inc"
79#undef GET_GLOBALISEL_PREDICATES_INIT
80#define GET_GLOBALISEL_TEMPORARIES_INIT
81#include "WebAssemblyGenGlobalISel.inc"
82#undef GET_GLOBALISEL_TEMPORARIES_INIT
83{
84}
85
86bool WebAssemblyInstructionSelector::select(MachineInstr &I) {
87 MachineBasicBlock &MBB = *I.getParent();
88 MachineFunction &MF = *MBB.getParent();
89 MachineRegisterInfo &MRI = MF.getRegInfo();
90
91 if (!I.isPreISelOpcode())
92 return true;
93
94 if (selectImpl(I, CoverageInfo&: *CoverageInfo))
95 return true;
96
97 using namespace TargetOpcode;
98
99 switch (I.getOpcode()) {
100 case G_IMPLICIT_DEF: {
101 const Register DefReg = I.getOperand(i: 0).getReg();
102
103 const TargetRegisterClass *DefRC =
104 TRI.getConstrainedRegClassForOperand(MO: I.getOperand(i: 0), MRI);
105
106 if (!DefRC)
107 return false;
108
109 I.setDesc(TII.get(Opcode: TargetOpcode::IMPLICIT_DEF));
110 return RBI.constrainGenericRegister(Reg: DefReg, RC: *DefRC, MRI) != nullptr;
111 }
112 default:
113 break;
114 }
115
116 return false;
117}
118
119namespace llvm {
120InstructionSelector *
121createWebAssemblyInstructionSelector(const WebAssemblyTargetMachine &TM,
122 const WebAssemblySubtarget &Subtarget,
123 const WebAssemblyRegisterBankInfo &RBI) {
124 return new WebAssemblyInstructionSelector(TM, Subtarget, RBI);
125}
126} // namespace llvm
127