1//===-- WebAssemblyInstrInfo.cpp - WebAssembly Instruction Information ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file contains the WebAssembly implementation of the
11/// TargetInstrInfo class.
12///
13//===----------------------------------------------------------------------===//
14
15#include "WebAssemblyInstrInfo.h"
16#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17#include "WebAssembly.h"
18#include "WebAssemblyMachineFunctionInfo.h"
19#include "WebAssemblySubtarget.h"
20#include "WebAssemblyUtilities.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineMemOperand.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25using namespace llvm;
26
27#define DEBUG_TYPE "wasm-instr-info"
28
29#define GET_INSTRINFO_CTOR_DTOR
30#include "WebAssemblyGenInstrInfo.inc"
31
32// defines WebAssembly::getNamedOperandIdx
33#define GET_INSTRINFO_NAMED_OPS
34#include "WebAssemblyGenInstrInfo.inc"
35
36WebAssemblyInstrInfo::WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
37 : WebAssemblyGenInstrInfo(STI, RI, WebAssembly::ADJCALLSTACKDOWN,
38 WebAssembly::ADJCALLSTACKUP,
39 WebAssembly::CATCHRET),
40 RI(STI.getTargetTriple()) {}
41
42const TargetRegisterClass *
43WebAssemblyInstrInfo::getInlineAsmMemoryOperandRegClass(
44 InlineAsm::ConstraintCode C) const {
45 return RI.getTargetTriple().getArch() == Triple::wasm64
46 ? &WebAssembly::I64RegClass
47 : &WebAssembly::I32RegClass;
48}
49
50bool WebAssemblyInstrInfo::isReMaterializableImpl(
51 const MachineInstr &MI) const {
52 switch (MI.getOpcode()) {
53 case WebAssembly::CONST_I32:
54 case WebAssembly::CONST_I64:
55 case WebAssembly::CONST_F32:
56 case WebAssembly::CONST_F64:
57 // TargetInstrInfo::isReMaterializableImpl misses these
58 // because of the ARGUMENTS implicit def, so we manually override it here.
59 return true;
60 default:
61 return TargetInstrInfo::isReMaterializableImpl(MI);
62 }
63}
64
65void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
66 MachineBasicBlock::iterator I,
67 const DebugLoc &DL, Register DestReg,
68 Register SrcReg, bool KillSrc,
69 bool RenamableDest,
70 bool RenamableSrc) const {
71 // This method is called by post-RA expansion, which expects only pregs to
72 // exist. However we need to handle both here.
73 auto &MRI = MBB.getParent()->getRegInfo();
74 const TargetRegisterClass *RC =
75 DestReg.isVirtual()
76 ? MRI.getRegClass(Reg: DestReg)
77 : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(Reg: DestReg);
78
79 unsigned CopyOpcode = WebAssembly::getCopyOpcodeForRegClass(RC);
80
81 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: CopyOpcode), DestReg)
82 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc));
83}
84
85MachineInstr *WebAssemblyInstrInfo::commuteInstructionImpl(
86 MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const {
87 // If the operands are stackified, we can't reorder them.
88 WebAssemblyFunctionInfo &MFI =
89 *MI.getParent()->getParent()->getInfo<WebAssemblyFunctionInfo>();
90 if (MFI.isVRegStackified(VReg: MI.getOperand(i: OpIdx1).getReg()) ||
91 MFI.isVRegStackified(VReg: MI.getOperand(i: OpIdx2).getReg()))
92 return nullptr;
93
94 // Otherwise use the default implementation.
95 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
96}
97
98// Branch analysis.
99bool WebAssemblyInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
100 MachineBasicBlock *&TBB,
101 MachineBasicBlock *&FBB,
102 SmallVectorImpl<MachineOperand> &Cond,
103 bool /*AllowModify*/) const {
104 const auto &MFI = *MBB.getParent()->getInfo<WebAssemblyFunctionInfo>();
105 // WebAssembly has control flow that doesn't have explicit branches or direct
106 // fallthrough (e.g. try/catch), which can't be modeled by analyzeBranch. It
107 // is created after CFGStackify.
108 if (MFI.isCFGStackified())
109 return true;
110
111 bool HaveCond = false;
112 for (MachineInstr &MI : MBB.terminators()) {
113 switch (MI.getOpcode()) {
114 default:
115 // Unhandled instruction; bail out.
116 return true;
117 case WebAssembly::BR_IF:
118 if (HaveCond)
119 return true;
120 Cond.push_back(Elt: MachineOperand::CreateImm(Val: true));
121 Cond.push_back(Elt: MI.getOperand(i: 1));
122 TBB = MI.getOperand(i: 0).getMBB();
123 HaveCond = true;
124 break;
125 case WebAssembly::BR_UNLESS:
126 if (HaveCond)
127 return true;
128 Cond.push_back(Elt: MachineOperand::CreateImm(Val: false));
129 Cond.push_back(Elt: MI.getOperand(i: 1));
130 TBB = MI.getOperand(i: 0).getMBB();
131 HaveCond = true;
132 break;
133 case WebAssembly::BR:
134 if (!HaveCond)
135 TBB = MI.getOperand(i: 0).getMBB();
136 else
137 FBB = MI.getOperand(i: 0).getMBB();
138 break;
139 }
140 if (MI.isBarrier())
141 break;
142 }
143
144 return false;
145}
146
147unsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB,
148 int *BytesRemoved) const {
149 assert(!BytesRemoved && "code size not handled");
150
151 MachineBasicBlock::instr_iterator I = MBB.instr_end();
152 unsigned Count = 0;
153
154 while (I != MBB.instr_begin()) {
155 --I;
156 if (I->isDebugInstr())
157 continue;
158 if (!I->isTerminator())
159 break;
160 // Remove the branch.
161 I->eraseFromParent();
162 I = MBB.instr_end();
163 ++Count;
164 }
165
166 return Count;
167}
168
169unsigned WebAssemblyInstrInfo::insertBranch(
170 MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
171 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
172 assert(!BytesAdded && "code size not handled");
173
174 if (Cond.empty()) {
175 if (!TBB)
176 return 0;
177
178 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: WebAssembly::BR)).addMBB(MBB: TBB);
179 return 1;
180 }
181
182 assert(Cond.size() == 2 && "Expected a flag and a successor block");
183
184 if (Cond[0].getImm())
185 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: WebAssembly::BR_IF)).addMBB(MBB: TBB).add(MO: Cond[1]);
186 else
187 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: WebAssembly::BR_UNLESS)).addMBB(MBB: TBB).add(MO: Cond[1]);
188 if (!FBB)
189 return 1;
190
191 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: WebAssembly::BR)).addMBB(MBB: FBB);
192 return 2;
193}
194
195bool WebAssemblyInstrInfo::reverseBranchCondition(
196 SmallVectorImpl<MachineOperand> &Cond) const {
197 assert(Cond.size() == 2 && "Expected a flag and a condition expression");
198 Cond.front() = MachineOperand::CreateImm(Val: !Cond.front().getImm());
199 return false;
200}
201
202ArrayRef<std::pair<int, const char *>>
203WebAssemblyInstrInfo::getSerializableTargetIndices() const {
204 static const std::pair<int, const char *> TargetIndices[] = {
205 {WebAssembly::TI_LOCAL, "wasm-local"},
206 {WebAssembly::TI_GLOBAL_FIXED, "wasm-global-fixed"},
207 {WebAssembly::TI_OPERAND_STACK, "wasm-operand-stack"},
208 {WebAssembly::TI_GLOBAL_RELOC, "wasm-global-reloc"},
209 {WebAssembly::TI_LOCAL_INDIRECT, "wasm-local-indirect"}};
210 return ArrayRef(TargetIndices);
211}
212
213const MachineOperand &
214WebAssemblyInstrInfo::getCalleeOperand(const MachineInstr &MI) const {
215 return WebAssembly::getCalleeOp(MI);
216}
217
218// This returns true when the instruction defines a value of a TargetIndex
219// operand that can be tracked by offsets. For Wasm, this returns true for only
220// local.set/local.tees. This is currently used by LiveDebugValues analysis.
221//
222// These are not included:
223// - In theory we need to add global.set here too, but we don't have global
224// indices at this point because they are relocatable and we address them by
225// names until linking, so we don't have 'offsets' (which are used to store
226// local/global indices) to deal with in LiveDebugValues. And we don't
227// associate debug info in values in globals anyway.
228// - All other value-producing instructions, i.e. instructions with defs, can
229// define values in the Wasm stack, which is represented by TI_OPERAND_STACK
230// TargetIndex. But they don't have offset info within the instruction itself,
231// and debug info analysis for them is handled separately in
232// WebAssemblyDebugFixup pass, so we don't worry about them here.
233bool WebAssemblyInstrInfo::isExplicitTargetIndexDef(const MachineInstr &MI,
234 int &Index,
235 int64_t &Offset) const {
236 unsigned Opc = MI.getOpcode();
237 if (WebAssembly::isLocalSet(Opc) || WebAssembly::isLocalTee(Opc)) {
238 Index = WebAssembly::TI_LOCAL;
239 Offset = MI.explicit_uses().begin()->getImm();
240 return true;
241 }
242 return false;
243}
244