1//===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "MCTargetDesc/X86BaseInfo.h"
10#include "MCTargetDesc/X86EncodingOptimization.h"
11#include "MCTargetDesc/X86FixupKinds.h"
12#include "MCTargetDesc/X86MCAsmInfo.h"
13#include "llvm/ADT/StringSwitch.h"
14#include "llvm/BinaryFormat/ELF.h"
15#include "llvm/BinaryFormat/MachO.h"
16#include "llvm/MC/MCAsmBackend.h"
17#include "llvm/MC/MCAssembler.h"
18#include "llvm/MC/MCCodeEmitter.h"
19#include "llvm/MC/MCContext.h"
20#include "llvm/MC/MCDwarf.h"
21#include "llvm/MC/MCELFObjectWriter.h"
22#include "llvm/MC/MCELFStreamer.h"
23#include "llvm/MC/MCExpr.h"
24#include "llvm/MC/MCInst.h"
25#include "llvm/MC/MCInstrInfo.h"
26#include "llvm/MC/MCLFIRewriter.h"
27#include "llvm/MC/MCObjectStreamer.h"
28#include "llvm/MC/MCObjectWriter.h"
29#include "llvm/MC/MCRegisterInfo.h"
30#include "llvm/MC/MCSection.h"
31#include "llvm/MC/MCSubtargetInfo.h"
32#include "llvm/MC/MCTargetOptions.h"
33#include "llvm/MC/MCValue.h"
34#include "llvm/MC/TargetRegistry.h"
35#include "llvm/Support/CommandLine.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38
39using namespace llvm;
40
41namespace {
42/// A wrapper for holding a mask of the values from X86::AlignBranchBoundaryKind
43class X86AlignBranchKind {
44private:
45 uint8_t AlignBranchKind = 0;
46
47public:
48 void operator=(const std::string &Val) {
49 if (Val.empty())
50 return;
51 SmallVector<StringRef, 6> BranchTypes;
52 StringRef(Val).split(A&: BranchTypes, Separator: '+', MaxSplit: -1, KeepEmpty: false);
53 for (auto BranchType : BranchTypes) {
54 if (BranchType == "fused")
55 addKind(Value: X86::AlignBranchFused);
56 else if (BranchType == "jcc")
57 addKind(Value: X86::AlignBranchJcc);
58 else if (BranchType == "jmp")
59 addKind(Value: X86::AlignBranchJmp);
60 else if (BranchType == "call")
61 addKind(Value: X86::AlignBranchCall);
62 else if (BranchType == "ret")
63 addKind(Value: X86::AlignBranchRet);
64 else if (BranchType == "indirect")
65 addKind(Value: X86::AlignBranchIndirect);
66 else {
67 errs() << "invalid argument " << BranchType.str()
68 << " to -x86-align-branch=; each element must be one of: fused, "
69 "jcc, jmp, call, ret, indirect.(plus separated)\n";
70 }
71 }
72 }
73
74 operator uint8_t() const { return AlignBranchKind; }
75 void addKind(X86::AlignBranchBoundaryKind Value) { AlignBranchKind |= Value; }
76};
77
78X86AlignBranchKind X86AlignBranchKindLoc;
79
80cl::opt<unsigned> X86AlignBranchBoundary(
81 "x86-align-branch-boundary", cl::init(Val: 0),
82 cl::desc(
83 "Control how the assembler should align branches with NOP. If the "
84 "boundary's size is not 0, it should be a power of 2 and no less "
85 "than 32. Branches will be aligned to prevent from being across or "
86 "against the boundary of specified size. The default value 0 does not "
87 "align branches."));
88
89cl::opt<X86AlignBranchKind, true, cl::parser<std::string>> X86AlignBranch(
90 "x86-align-branch",
91 cl::desc(
92 "Specify types of branches to align (plus separated list of types):"
93 "\njcc indicates conditional jumps"
94 "\nfused indicates fused conditional jumps"
95 "\njmp indicates direct unconditional jumps"
96 "\ncall indicates direct and indirect calls"
97 "\nret indicates rets"
98 "\nindirect indicates indirect unconditional jumps"),
99 cl::location(L&: X86AlignBranchKindLoc));
100
101cl::opt<bool> X86AlignBranchWithin32BBoundaries(
102 "x86-branches-within-32B-boundaries", cl::init(Val: false),
103 cl::desc(
104 "Align selected instructions to mitigate negative performance impact "
105 "of Intel's micro code update for errata skx102. May break "
106 "assumptions about labels corresponding to particular instructions, "
107 "and should be used with caution."));
108
109cl::opt<unsigned> X86PadMaxPrefixSize(
110 "x86-pad-max-prefix-size", cl::init(Val: 0),
111 cl::desc("Maximum number of prefixes to use for padding"));
112
113cl::opt<bool> X86PadForAlign(
114 "x86-pad-for-align", cl::init(Val: false), cl::Hidden,
115 cl::desc("Pad previous instructions to implement align directives"));
116
117cl::opt<bool> X86PadForBranchAlign(
118 "x86-pad-for-branch-align", cl::init(Val: true), cl::Hidden,
119 cl::desc("Pad previous instructions to implement branch alignment"));
120
121class X86AsmBackend : public MCAsmBackend {
122 const MCSubtargetInfo &STI;
123 std::unique_ptr<const MCInstrInfo> MCII;
124 X86AlignBranchKind AlignBranchType;
125 Align AlignBoundary;
126 unsigned TargetPrefixMax = 0;
127
128 MCInst PrevInst;
129 unsigned PrevInstOpcode = 0;
130 bool PrefixEndsBundleLock = false;
131 MCBoundaryAlignFragment *PendingBA = nullptr;
132 std::pair<MCFragment *, size_t> PrevInstPosition;
133
134 uint8_t determinePaddingPrefix(const MCInst &Inst) const;
135 bool isMacroFused(const MCInst &Cmp, const MCInst &Jcc) const;
136 bool needAlign(const MCInst &Inst) const;
137 bool canPadBranches(MCObjectStreamer &OS) const;
138 bool canPadInst(const MCInst &Inst, MCObjectStreamer &OS) const;
139 void emitInstructionBeginBundle(MCObjectStreamer &OS);
140 void emitInstructionEndBundle(MCObjectStreamer &OS);
141
142public:
143 X86AsmBackend(const Target &T, const MCSubtargetInfo &STI)
144 : MCAsmBackend(llvm::endianness::little), STI(STI),
145 MCII(T.createMCInstrInfo()) {
146 if (X86AlignBranchWithin32BBoundaries) {
147 // At the moment, this defaults to aligning fused branches, unconditional
148 // jumps, and (unfused) conditional jumps with nops. Both the
149 // instructions aligned and the alignment method (nop vs prefix) may
150 // change in the future.
151 AlignBoundary = assumeAligned(Value: 32);
152 AlignBranchType.addKind(Value: X86::AlignBranchFused);
153 AlignBranchType.addKind(Value: X86::AlignBranchJcc);
154 AlignBranchType.addKind(Value: X86::AlignBranchJmp);
155 }
156 // Allow overriding defaults set by main flag
157 if (X86AlignBranchBoundary.getNumOccurrences())
158 AlignBoundary = assumeAligned(Value: X86AlignBranchBoundary);
159 if (X86AlignBranch.getNumOccurrences())
160 AlignBranchType = X86AlignBranchKindLoc;
161 if (X86PadMaxPrefixSize.getNumOccurrences())
162 TargetPrefixMax = X86PadMaxPrefixSize;
163
164 AllowAutoPadding =
165 AlignBoundary != Align(1) && AlignBranchType != X86::AlignBranchNone;
166 AllowEnhancedRelaxation =
167 AllowAutoPadding && TargetPrefixMax != 0 && X86PadForBranchAlign;
168 AllowBundling = true;
169 }
170
171 // The streamer frees the fragments these point into.
172 void reset() override {
173 PrevInst = MCInst();
174 PrevInstOpcode = 0;
175 PrefixEndsBundleLock = false;
176 PendingBA = nullptr;
177 PrevInstPosition = {};
178 }
179
180 void emitInstructionBegin(MCObjectStreamer &OS, const MCInst &Inst,
181 const MCSubtargetInfo &STI);
182 void emitInstructionEnd(MCObjectStreamer &OS, const MCInst &Inst);
183
184
185 std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
186
187 MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override;
188
189 std::optional<bool> evaluateFixup(const MCFragment &, MCFixup &, MCValue &,
190 uint64_t &) override;
191 void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target,
192 uint8_t *Data, uint64_t Value, bool IsResolved) override;
193
194 bool mayNeedRelaxation(unsigned Opcode, ArrayRef<MCOperand> Operands,
195 const MCSubtargetInfo &STI) const override;
196
197 bool fixupNeedsRelaxationAdvanced(const MCFragment &, const MCFixup &,
198 const MCValue &, uint64_t,
199 bool) const override;
200
201 void relaxInstruction(MCInst &Inst,
202 const MCSubtargetInfo &STI) const override;
203
204 bool padInstructionViaRelaxation(MCFragment &RF, MCCodeEmitter &Emitter,
205 unsigned &RemainingSize) const;
206
207 bool padInstructionViaPrefix(MCFragment &RF, MCCodeEmitter &Emitter,
208 unsigned &RemainingSize) const;
209
210 bool padInstructionEncoding(MCFragment &RF, MCCodeEmitter &Emitter,
211 unsigned &RemainingSize) const;
212
213 bool finishLayout() const override;
214
215 bool padInstsBackward(SmallVectorImpl<MCFragment *> &Relaxable,
216 unsigned &RemainingSize) const;
217 bool foldBundlePad(const MCAssembler &Asm, MCBoundaryAlignFragment &BF,
218 SmallVectorImpl<MCFragment *> &Relaxable) const;
219 bool optimizeBundleNops(const MCAssembler &Asm) const;
220
221 unsigned getMaximumNopSize(const MCSubtargetInfo &STI) const override;
222
223 bool writeNopData(raw_ostream &OS, uint64_t Count,
224 const MCSubtargetInfo *STI) const override;
225};
226} // end anonymous namespace
227
228static bool isRelaxableBranch(unsigned Opcode) {
229 return Opcode == X86::JCC_1 || Opcode == X86::JMP_1;
230}
231
232static unsigned getRelaxedOpcodeBranch(unsigned Opcode,
233 bool Is16BitMode = false) {
234 switch (Opcode) {
235 default:
236 llvm_unreachable("invalid opcode for branch");
237 case X86::JCC_1:
238 return (Is16BitMode) ? X86::JCC_2 : X86::JCC_4;
239 case X86::JMP_1:
240 return (Is16BitMode) ? X86::JMP_2 : X86::JMP_4;
241 }
242}
243
244static unsigned getRelaxedOpcode(const MCInst &MI, bool Is16BitMode) {
245 unsigned Opcode = MI.getOpcode();
246 return isRelaxableBranch(Opcode) ? getRelaxedOpcodeBranch(Opcode, Is16BitMode)
247 : X86::getOpcodeForLongImmediateForm(Opcode);
248}
249
250static X86::CondCode getCondFromBranch(const MCInst &MI,
251 const MCInstrInfo &MCII) {
252 unsigned Opcode = MI.getOpcode();
253 switch (Opcode) {
254 default:
255 return X86::COND_INVALID;
256 case X86::JCC_1: {
257 const MCInstrDesc &Desc = MCII.get(Opcode);
258 return static_cast<X86::CondCode>(
259 MI.getOperand(i: Desc.getNumOperands() - 1).getImm());
260 }
261 }
262}
263
264static X86::SecondMacroFusionInstKind
265classifySecondInstInMacroFusion(const MCInst &MI, const MCInstrInfo &MCII) {
266 X86::CondCode CC = getCondFromBranch(MI, MCII);
267 return classifySecondCondCodeInMacroFusion(CC);
268}
269
270/// Check if the instruction uses RIP relative addressing.
271static bool isRIPRelative(const MCInst &MI, const MCInstrInfo &MCII) {
272 const MCInstrDesc &Desc = MCII.get(Opcode: MI.getOpcode());
273 int MemoryOperand = X86II::getMemoryOperandIdx(Desc);
274 if (MemoryOperand < 0)
275 return false;
276 unsigned BaseRegNum = MemoryOperand + X86::AddrBaseReg;
277 MCRegister BaseReg = MI.getOperand(i: BaseRegNum).getReg();
278 return (BaseReg == X86::RIP);
279}
280
281/// Check if the instruction is a prefix.
282static bool isPrefix(unsigned Opcode, const MCInstrInfo &MCII) {
283 return X86II::isPrefix(TSFlags: MCII.get(Opcode).TSFlags);
284}
285
286/// Check if the instruction is valid as the first instruction in macro fusion.
287static bool isFirstMacroFusibleInst(const MCInst &Inst,
288 const MCInstrInfo &MCII) {
289 // An Intel instruction with RIP relative addressing is not macro fusible.
290 if (isRIPRelative(MI: Inst, MCII))
291 return false;
292 X86::FirstMacroFusionInstKind FIK =
293 X86::classifyFirstOpcodeInMacroFusion(Opcode: Inst.getOpcode());
294 return FIK != X86::FirstMacroFusionInstKind::Invalid;
295}
296
297/// X86 can reduce the bytes of NOP by padding instructions with prefixes to
298/// get a better peformance in some cases. Here, we determine which prefix is
299/// the most suitable.
300///
301/// If the instruction has a segment override prefix, use the existing one.
302/// If the target is 64-bit, use the CS.
303/// If the target is 32-bit,
304/// - If the instruction has a ESP/EBP base register, use SS.
305/// - Otherwise use DS.
306uint8_t X86AsmBackend::determinePaddingPrefix(const MCInst &Inst) const {
307 assert((STI.hasFeature(X86::Is32Bit) || STI.hasFeature(X86::Is64Bit)) &&
308 "Prefixes can be added only in 32-bit or 64-bit mode.");
309 const MCInstrDesc &Desc = MCII->get(Opcode: Inst.getOpcode());
310 uint64_t TSFlags = Desc.TSFlags;
311
312 // Determine where the memory operand starts, if present.
313 int MemoryOperand = X86II::getMemoryOperandIdx(Desc);
314
315 MCRegister SegmentReg;
316 if (MemoryOperand >= 0) {
317 // Check for explicit segment override on memory operand.
318 SegmentReg = Inst.getOperand(i: MemoryOperand + X86::AddrSegmentReg).getReg();
319 }
320
321 switch (TSFlags & X86II::FormMask) {
322 default:
323 break;
324 case X86II::RawFrmDstSrc: {
325 // Check segment override opcode prefix as needed (not for %ds).
326 if (Inst.getOperand(i: 2).getReg() != X86::DS)
327 SegmentReg = Inst.getOperand(i: 2).getReg();
328 break;
329 }
330 case X86II::RawFrmSrc: {
331 // Check segment override opcode prefix as needed (not for %ds).
332 if (Inst.getOperand(i: 1).getReg() != X86::DS)
333 SegmentReg = Inst.getOperand(i: 1).getReg();
334 break;
335 }
336 case X86II::RawFrmMemOffs: {
337 // Check segment override opcode prefix as needed.
338 SegmentReg = Inst.getOperand(i: 1).getReg();
339 break;
340 }
341 }
342
343 if (SegmentReg)
344 return X86::getSegmentOverridePrefixForReg(Reg: SegmentReg);
345
346 if (STI.hasFeature(Feature: X86::Is64Bit))
347 return X86::CS_Encoding;
348
349 if (MemoryOperand >= 0) {
350 unsigned BaseRegNum = MemoryOperand + X86::AddrBaseReg;
351 MCRegister BaseReg = Inst.getOperand(i: BaseRegNum).getReg();
352 if (BaseReg == X86::ESP || BaseReg == X86::EBP)
353 return X86::SS_Encoding;
354 }
355 return X86::DS_Encoding;
356}
357
358/// Check if the two instructions will be macro-fused on the target cpu.
359bool X86AsmBackend::isMacroFused(const MCInst &Cmp, const MCInst &Jcc) const {
360 const MCInstrDesc &InstDesc = MCII->get(Opcode: Jcc.getOpcode());
361 if (!InstDesc.isConditionalBranch())
362 return false;
363 if (!isFirstMacroFusibleInst(Inst: Cmp, MCII: *MCII))
364 return false;
365 const X86::FirstMacroFusionInstKind CmpKind =
366 X86::classifyFirstOpcodeInMacroFusion(Opcode: Cmp.getOpcode());
367 const X86::SecondMacroFusionInstKind BranchKind =
368 classifySecondInstInMacroFusion(MI: Jcc, MCII: *MCII);
369 return X86::isMacroFused(FirstKind: CmpKind, SecondKind: BranchKind);
370}
371
372/// Check if the instruction has a variant symbol operand.
373static bool hasVariantSymbol(const MCInst &MI) {
374 for (auto &Operand : MI) {
375 if (!Operand.isExpr())
376 continue;
377 const MCExpr &Expr = *Operand.getExpr();
378 if (Expr.getKind() == MCExpr::SymbolRef &&
379 cast<MCSymbolRefExpr>(Val: &Expr)->getSpecifier())
380 return true;
381 }
382 return false;
383}
384
385/// X86 has certain instructions which enable interrupts exactly one
386/// instruction *after* the instruction which stores to SS. Return true if the
387/// given instruction may have such an interrupt delay slot.
388static bool mayHaveInterruptDelaySlot(unsigned InstOpcode) {
389 switch (InstOpcode) {
390 case X86::POPSS16:
391 case X86::POPSS32:
392 case X86::STI:
393 return true;
394
395 case X86::MOV16sr:
396 case X86::MOV32sr:
397 case X86::MOV64sr:
398 case X86::MOV16sm:
399 // In fact, this is only the case if the first operand is SS. However, as
400 // segment moves occur extremely rarely, this is just a minor pessimization.
401 return true;
402 }
403 return false;
404}
405
406/// Return true if we can insert NOP or prefixes automatically before the
407/// the instruction to be emitted.
408bool X86AsmBackend::canPadInst(const MCInst &Inst, MCObjectStreamer &OS) const {
409 if (hasVariantSymbol(MI: Inst))
410 // Linker may rewrite the instruction with variant symbol operand(e.g.
411 // TLSCALL).
412 return false;
413
414 if (mayHaveInterruptDelaySlot(InstOpcode: PrevInstOpcode))
415 // If this instruction follows an interrupt enabling instruction with a one
416 // instruction delay, inserting a nop would change behavior.
417 return false;
418
419 if (isPrefix(Opcode: PrevInstOpcode, MCII: *MCII))
420 // If this instruction follows a prefix, inserting a nop/prefix would change
421 // semantic.
422 return false;
423
424 if (isPrefix(Opcode: Inst.getOpcode(), MCII: *MCII))
425 // If this instruction is a prefix, inserting a prefix would change
426 // semantic.
427 return false;
428
429 // If this instruction follows any data, there is no clear instruction
430 // boundary, inserting a nop/prefix would change semantic.
431 auto Offset = OS.getCurFragSize();
432 if (Offset && (OS.getCurrentFragment() != PrevInstPosition.first ||
433 Offset != PrevInstPosition.second))
434 return false;
435
436 return true;
437}
438
439bool X86AsmBackend::canPadBranches(MCObjectStreamer &OS) const {
440 if (!OS.getAllowAutoPadding())
441 return false;
442 assert(allowAutoPadding() && "incorrect initialization!");
443
444 // We only pad in text section.
445 if (!OS.getCurrentSectionOnly()->isText())
446 return false;
447
448 // Branches only need to be aligned in 32-bit or 64-bit mode.
449 if (!(STI.hasFeature(Feature: X86::Is64Bit) || STI.hasFeature(Feature: X86::Is32Bit)))
450 return false;
451
452 return true;
453}
454
455/// Check if the instruction operand needs to be aligned.
456bool X86AsmBackend::needAlign(const MCInst &Inst) const {
457 const MCInstrDesc &Desc = MCII->get(Opcode: Inst.getOpcode());
458 return (Desc.isConditionalBranch() &&
459 (AlignBranchType & X86::AlignBranchJcc)) ||
460 (Desc.isUnconditionalBranch() &&
461 (AlignBranchType & X86::AlignBranchJmp)) ||
462 (Desc.isCall() && (AlignBranchType & X86::AlignBranchCall)) ||
463 (Desc.isReturn() && (AlignBranchType & X86::AlignBranchRet)) ||
464 (Desc.isIndirectBranch() &&
465 (AlignBranchType & X86::AlignBranchIndirect));
466}
467
468void X86_MC::emitInstruction(MCObjectStreamer &S, const MCInst &Inst,
469 const MCSubtargetInfo &STI) {
470 bool AutoPadding = S.getAllowAutoPadding();
471 if (LLVM_LIKELY(!AutoPadding && !X86PadForAlign)) {
472 S.MCObjectStreamer::emitInstruction(Inst, STI);
473 return;
474 }
475
476 // Run the LFI rewriter outside of emitInstructionBegin/End so that nested
477 // instructions or bundle_lock/unlock directives do not corrupt the Begin/End
478 // bookkeeping for the original instruction.
479 if (S.getLFIRewriter() && S.getLFIRewriter()->rewriteInst(Inst, Out&: S, STI))
480 return;
481
482 auto &Backend = static_cast<X86AsmBackend &>(S.getAssembler().getBackend());
483 Backend.emitInstructionBegin(OS&: S, Inst, STI);
484 S.MCObjectStreamer::emitInstruction(Inst, STI);
485 Backend.emitInstructionEnd(OS&: S, Inst);
486}
487
488/// Open a MCBoundaryAlignFragment for the upcoming instruction so that layout
489/// can pad it into the next bundle. Within .bundle_lock the group's fragment
490/// already covers it.
491void X86AsmBackend::emitInstructionBeginBundle(MCObjectStreamer &OS) {
492 assert(Asm->isBundlingEnabled());
493
494 // The prefix stays in the group while this instruction gets its own
495 // fragment, so padding may land between the two.
496 if (PrefixEndsBundleLock && OS.getCurrentFragment() != PrevInstPosition.first)
497 getContext().reportError(L: OS.getStartTokLoc(),
498 Msg: "instruction prefix cannot be the last "
499 "instruction of a .bundle_lock group");
500
501 if (OS.isBundleLocked())
502 return;
503 // A pending fragment means the previous MCInst was a prefix, which must stay
504 // with this one: extend its range. Adjacency rejects a fragment left stale by
505 // an intervening .bundle_lock group.
506 if (PendingBA &&
507 PendingBA->getLastFragment()->getNext() == OS.getCurrentFragment()) {
508 PendingBA->setLastFragment(OS.getCurrentFragment());
509 return;
510 }
511 PendingBA = OS.newSpecialFragment<MCBoundaryAlignFragment>(
512 args: Asm->getBundleAlign(), args: STI);
513 // We can set LastFragment now, before the instruction is emitted, as bundling
514 // emits one fragment per instruction. Deferring setLastFragment to
515 // post-emitInstruction would risk capturing a fragment that a subsequent
516 // emitCodeAlignment repurposes in-place to FT_Align, corrupting the BA's
517 // boundary range.
518 PendingBA->setLastFragment(OS.getCurrentFragment());
519}
520
521/// Close the fragment opened by emitInstructionBeginBundle, unless the
522/// instruction was a prefix, in which case the next one extends it.
523void X86AsmBackend::emitInstructionEndBundle(MCObjectStreamer &OS) {
524 assert(Asm->isBundlingEnabled());
525
526 if (OS.isBundleLocked()) {
527 PrefixEndsBundleLock = isPrefix(Opcode: PrevInstOpcode, MCII: *MCII);
528 return;
529 }
530 PrefixEndsBundleLock = false;
531 assert(PendingBA && "MCBoundaryAlignFragment is expected for every "
532 "instruction if it is not bundle-locked");
533
534 OS.getCurrentSectionOnly()->ensureMinAlignment(MinAlignment: Asm->getBundleAlign());
535
536 if (!isPrefix(Opcode: PrevInstOpcode, MCII: *MCII))
537 PendingBA = nullptr;
538}
539
540/// Insert BoundaryAlignFragment before instructions to align branches.
541void X86AsmBackend::emitInstructionBegin(MCObjectStreamer &OS,
542 const MCInst &Inst,
543 const MCSubtargetInfo &STI) {
544 bool CanPadInst = canPadInst(Inst, OS);
545 if (Asm->isBundlingEnabled()) {
546 emitInstructionBeginBundle(OS);
547 OS.getCurrentFragment()->setAllowAutoPadding(CanPadInst);
548 return;
549 }
550 if (CanPadInst)
551 OS.getCurrentFragment()->setAllowAutoPadding(true);
552
553 if (!canPadBranches(OS))
554 return;
555
556 // NB: PrevInst only valid if canPadBranches is true.
557 if (!isMacroFused(Cmp: PrevInst, Jcc: Inst))
558 // Macro fusion doesn't happen indeed, clear the pending.
559 PendingBA = nullptr;
560
561 // When branch padding is enabled (basically the skx102 erratum => unlikely),
562 // we call canPadInst (not cheap) twice. However, in the common case, we can
563 // avoid unnecessary calls to that, as this is otherwise only used for
564 // relaxable fragments.
565 if (!CanPadInst)
566 return;
567
568 if (PendingBA) {
569 auto *NextFragment = PendingBA->getNext();
570 assert(NextFragment && "NextFragment should not be null");
571 if (NextFragment == OS.getCurrentFragment())
572 return;
573 // We eagerly create an empty fragment when inserting a fragment
574 // with a variable-size tail.
575 if (NextFragment->getNext() == OS.getCurrentFragment())
576 return;
577
578 // Macro fusion actually happens and there is no other fragment inserted
579 // after the previous instruction.
580 //
581 // Do nothing here since we already inserted a BoudaryAlign fragment when
582 // we met the first instruction in the fused pair and we'll tie them
583 // together in emitInstructionEnd.
584 //
585 // Note: When there is at least one fragment, such as MCAlignFragment,
586 // inserted after the previous instruction, e.g.
587 //
588 // \code
589 // cmp %rax %rcx
590 // .align 16
591 // je .Label0
592 // \ endcode
593 //
594 // We will treat the JCC as a unfused branch although it may be fused
595 // with the CMP.
596 return;
597 }
598
599 if (needAlign(Inst) || ((AlignBranchType & X86::AlignBranchFused) &&
600 isFirstMacroFusibleInst(Inst, MCII: *MCII))) {
601 // If we meet a unfused branch or the first instuction in a fusiable pair,
602 // insert a BoundaryAlign fragment.
603 PendingBA =
604 OS.newSpecialFragment<MCBoundaryAlignFragment>(args&: AlignBoundary, args: STI);
605 }
606}
607
608/// Set the last fragment to be aligned for the BoundaryAlignFragment.
609void X86AsmBackend::emitInstructionEnd(MCObjectStreamer &OS,
610 const MCInst &Inst) {
611 // Update PrevInstOpcode here, canPadInst() reads that.
612 MCFragment *CF = OS.getCurrentFragment();
613 PrevInstOpcode = Inst.getOpcode();
614 PrevInstPosition = std::make_pair(x&: CF, y: OS.getCurFragSize());
615 if (Asm->isBundlingEnabled())
616 return emitInstructionEndBundle(OS);
617
618 if (!canPadBranches(OS))
619 return;
620
621 // PrevInst is only needed if canPadBranches. Copying an MCInst isn't cheap.
622 PrevInst = Inst;
623
624 if (!needAlign(Inst) || !PendingBA)
625 return;
626
627 // Tie the aligned instructions into a pending BoundaryAlign.
628 PendingBA->setLastFragment(CF);
629 PendingBA = nullptr;
630
631 // We need to ensure that further data isn't added to the current
632 // DataFragment, so that we can get the size of instructions later in
633 // MCAssembler::relaxBoundaryAlign. The easiest way is to insert a new empty
634 // DataFragment.
635 OS.newFragment();
636
637 // Update the maximum alignment on the current section if necessary.
638 CF->getParent()->ensureMinAlignment(MinAlignment: AlignBoundary);
639}
640
641std::optional<MCFixupKind> X86AsmBackend::getFixupKind(StringRef Name) const {
642 if (STI.getTargetTriple().isOSBinFormatELF()) {
643 unsigned Type;
644 if (STI.getTargetTriple().isX86_64()) {
645 Type = llvm::StringSwitch<unsigned>(Name)
646#define ELF_RELOC(X, Y) .Case(#X, Y)
647#include "llvm/BinaryFormat/ELFRelocs/x86_64.def"
648#undef ELF_RELOC
649 .Case(S: "BFD_RELOC_NONE", Value: ELF::R_X86_64_NONE)
650 .Case(S: "BFD_RELOC_8", Value: ELF::R_X86_64_8)
651 .Case(S: "BFD_RELOC_16", Value: ELF::R_X86_64_16)
652 .Case(S: "BFD_RELOC_32", Value: ELF::R_X86_64_32)
653 .Case(S: "BFD_RELOC_64", Value: ELF::R_X86_64_64)
654 .Default(Value: -1u);
655 } else {
656 Type = llvm::StringSwitch<unsigned>(Name)
657#define ELF_RELOC(X, Y) .Case(#X, Y)
658#include "llvm/BinaryFormat/ELFRelocs/i386.def"
659#undef ELF_RELOC
660 .Case(S: "BFD_RELOC_NONE", Value: ELF::R_386_NONE)
661 .Case(S: "BFD_RELOC_8", Value: ELF::R_386_8)
662 .Case(S: "BFD_RELOC_16", Value: ELF::R_386_16)
663 .Case(S: "BFD_RELOC_32", Value: ELF::R_386_32)
664 .Default(Value: -1u);
665 }
666 if (Type == -1u)
667 return std::nullopt;
668 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
669 }
670 return MCAsmBackend::getFixupKind(Name);
671}
672
673MCFixupKindInfo X86AsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
674 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
675 // clang-format off
676 {.Name: "reloc_riprel_4byte", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
677 {.Name: "reloc_riprel_4byte_movq_load", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
678 {.Name: "reloc_riprel_4byte_movq_load_rex2", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
679 {.Name: "reloc_riprel_4byte_relax", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
680 {.Name: "reloc_riprel_4byte_relax_rex", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
681 {.Name: "reloc_riprel_4byte_relax_rex2", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
682 {.Name: "reloc_riprel_4byte_relax_evex", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
683 {.Name: "reloc_signed_4byte", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
684 {.Name: "reloc_signed_4byte_relax", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
685 {.Name: "reloc_global_offset_table", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
686 {.Name: "reloc_branch_4byte_pcrel", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
687 // clang-format on
688 };
689
690 // Fixup kinds from .reloc directive are like R_386_NONE/R_X86_64_NONE. They
691 // do not require any extra processing.
692 if (mc::isRelocation(FixupKind: Kind))
693 return {};
694
695 if (Kind < FirstTargetFixupKind)
696 return MCAsmBackend::getFixupKindInfo(Kind);
697
698 assert(unsigned(Kind - FirstTargetFixupKind) < X86::NumTargetFixupKinds &&
699 "Invalid kind!");
700 assert(Infos[Kind - FirstTargetFixupKind].Name && "Empty fixup name!");
701 return Infos[Kind - FirstTargetFixupKind];
702}
703
704static unsigned getFixupKindSize(unsigned Kind) {
705 switch (Kind) {
706 default:
707 llvm_unreachable("invalid fixup kind!");
708 case FK_NONE:
709 return 0;
710 case FK_SecRel_1:
711 case FK_Data_1:
712 return 1;
713 case FK_SecRel_2:
714 case FK_Data_2:
715 return 2;
716 case X86::reloc_riprel_4byte:
717 case X86::reloc_riprel_4byte_relax:
718 case X86::reloc_riprel_4byte_relax_rex:
719 case X86::reloc_riprel_4byte_relax_rex2:
720 case X86::reloc_riprel_4byte_movq_load:
721 case X86::reloc_riprel_4byte_movq_load_rex2:
722 case X86::reloc_riprel_4byte_relax_evex:
723 case X86::reloc_signed_4byte:
724 case X86::reloc_signed_4byte_relax:
725 case X86::reloc_global_offset_table:
726 case X86::reloc_branch_4byte_pcrel:
727 case FK_SecRel_4:
728 case FK_Data_4:
729 return 4;
730 case FK_SecRel_8:
731 case FK_Data_8:
732 return 8;
733 }
734}
735
736constexpr char GotSymName[] = "_GLOBAL_OFFSET_TABLE_";
737
738// Adjust PC-relative fixup offsets, which are calculated from the start of the
739// next instruction.
740std::optional<bool> X86AsmBackend::evaluateFixup(const MCFragment &,
741 MCFixup &Fixup,
742 MCValue &Target, uint64_t &) {
743 if (Fixup.isPCRel()) {
744 switch (Fixup.getKind()) {
745 case FK_Data_1:
746 Target.setConstant(Target.getConstant() - 1);
747 break;
748 case FK_Data_2:
749 Target.setConstant(Target.getConstant() - 2);
750 break;
751 default: {
752 Target.setConstant(Target.getConstant() - 4);
753 auto *Add = Target.getAddSym();
754 // If this is a pc-relative load off _GLOBAL_OFFSET_TABLE_:
755 // leaq _GLOBAL_OFFSET_TABLE_(%rip), %r15
756 // this needs to be a GOTPC32 relocation.
757 if (Add && Add->getName() == GotSymName)
758 Fixup = MCFixup::create(Offset: Fixup.getOffset(), Value: Fixup.getValue(),
759 Kind: X86::reloc_global_offset_table);
760 } break;
761 }
762 }
763 // Use default handling for `Value` and `IsResolved`.
764 return {};
765}
766
767void X86AsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
768 const MCValue &Target, uint8_t *Data,
769 uint64_t Value, bool IsResolved) {
770 // Force relocation when there is a specifier. This might be too conservative
771 // - GAS doesn't emit a relocation for call local@plt; local:.
772 if (Target.getSpecifier())
773 IsResolved = false;
774 maybeAddReloc(F, Fixup, Target, Value, IsResolved);
775
776 auto Kind = Fixup.getKind();
777 if (mc::isRelocation(FixupKind: Kind))
778 return;
779 unsigned Size = getFixupKindSize(Kind);
780
781 assert(Fixup.getOffset() + Size <= F.getSize() && "Invalid fixup offset!");
782
783 // Check fixup value overflow similar to GAS (fixups emitted as RELA
784 // relocations have a value of 0).
785 // - Unknown signedness: the range (-2^N, 2^N) is allowed,
786 // accommodating intN_t, uintN_t, and a non-positive value type.
787 // - Signed (intN_t): the range [-2^(N-1), 2^(N-1)) is allowed.
788 //
789 // Currently only resolved PC-relative fixups are treated as signed. GAS
790 // treats more as signed (e.g. unresolved R_X86_64_32S).
791 // Unresolved fixups have unknown signedness to allow `jmp foo+0xffffffff`.
792 if (Size && Size < 8) {
793 bool Signed = IsResolved && Fixup.isPCRel();
794 uint64_t Mask = ~uint64_t(0) << (Size * 8 - (Signed ? 1 : 0));
795 if ((Value & Mask) && (Signed ? (Value & Mask) != Mask : (-Value & Mask)))
796 getContext().reportError(L: Fixup.getLoc(),
797 Msg: "value of " + Twine(int64_t(Value)) +
798 " is too large for field of " + Twine(Size) +
799 (Size == 1 ? " byte" : " bytes"));
800 }
801
802 for (unsigned i = 0; i != Size; ++i)
803 Data[i] = uint8_t(Value >> (i * 8));
804}
805
806bool X86AsmBackend::mayNeedRelaxation(unsigned Opcode,
807 ArrayRef<MCOperand> Operands,
808 const MCSubtargetInfo &STI) const {
809 unsigned SkipOperands = X86::isCCMPCC(Opcode) ? 2 : 0;
810 return isRelaxableBranch(Opcode) ||
811 (X86::getOpcodeForLongImmediateForm(Opcode) != Opcode &&
812 Operands[Operands.size() - 1 - SkipOperands].isExpr());
813}
814
815bool X86AsmBackend::fixupNeedsRelaxationAdvanced(const MCFragment &F,
816 const MCFixup &Fixup,
817 const MCValue &Target,
818 uint64_t Value,
819 bool Resolved) const {
820 // If resolved, relax if the value is too big for a (signed) i8.
821 //
822 // Currently, `jmp local@plt` relaxes JMP even if the offset is small,
823 // different from gas.
824 if (Resolved) {
825 // finishLayout folds padding into encodings after relaxation, shifting a
826 // branch and its target within their bundles. Keep a bundle of headroom.
827 // Immediates do not shift.
828 int64_t Slack = Asm->isBundlingEnabled() && TargetPrefixMax != 0 &&
829 isRelaxableBranch(Opcode: F.getOpcode())
830 ? Asm->getBundleAlign().value()
831 : 0;
832 return !isInt<8>(x: int64_t(Value) + Slack) ||
833 !isInt<8>(x: int64_t(Value) - Slack) || Target.getSpecifier();
834 }
835
836 // Otherwise, relax unless there is a @ABS8 specifier.
837 if (Fixup.getKind() == FK_Data_1 && Target.getAddSym() &&
838 Target.getSpecifier() == X86::S_ABS8)
839 return false;
840 return true;
841}
842
843// FIXME: Can tblgen help at all here to verify there aren't other instructions
844// we can relax?
845void X86AsmBackend::relaxInstruction(MCInst &Inst,
846 const MCSubtargetInfo &STI) const {
847 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
848 bool Is16BitMode = STI.hasFeature(Feature: X86::Is16Bit);
849 unsigned RelaxedOp = getRelaxedOpcode(MI: Inst, Is16BitMode);
850 assert(RelaxedOp != Inst.getOpcode());
851 Inst.setOpcode(RelaxedOp);
852}
853
854bool X86AsmBackend::padInstructionViaPrefix(MCFragment &RF,
855 MCCodeEmitter &Emitter,
856 unsigned &RemainingSize) const {
857 if (!RF.getAllowAutoPadding())
858 return false;
859 // If the instruction isn't fully relaxed, shifting it around might require a
860 // larger value for one of the fixups then can be encoded. The outer loop
861 // will also catch this before moving to the next instruction, but we need to
862 // prevent padding this single instruction as well.
863 if (mayNeedRelaxation(Opcode: RF.getOpcode(), Operands: RF.getOperands(),
864 STI: *RF.getSubtargetInfo()))
865 return false;
866
867 const unsigned OldSize = RF.getVarSize();
868 if (OldSize == 15)
869 return false;
870
871 const unsigned MaxPossiblePad = std::min(a: 15 - OldSize, b: RemainingSize);
872 const unsigned RemainingPrefixSize = [&]() -> unsigned {
873 SmallString<15> Code;
874 X86_MC::emitPrefix(MCE&: Emitter, MI: RF.getInst(), CB&: Code, STI);
875 assert(Code.size() < 15 && "The number of prefixes must be less than 15.");
876
877 // TODO: It turns out we need a decent amount of plumbing for the target
878 // specific bits to determine number of prefixes its safe to add. Various
879 // targets (older chips mostly, but also Atom family) encounter decoder
880 // stalls with too many prefixes. For testing purposes, we set the value
881 // externally for the moment.
882 unsigned ExistingPrefixSize = Code.size();
883 if (TargetPrefixMax <= ExistingPrefixSize)
884 return 0;
885 return TargetPrefixMax - ExistingPrefixSize;
886 }();
887 const unsigned PrefixBytesToAdd =
888 std::min(a: MaxPossiblePad, b: RemainingPrefixSize);
889 if (PrefixBytesToAdd == 0)
890 return false;
891
892 const uint8_t Prefix = determinePaddingPrefix(Inst: RF.getInst());
893
894 SmallString<256> Code;
895 Code.append(NumInputs: PrefixBytesToAdd, Elt: Prefix);
896 Code.append(in_start: RF.getVarContents().begin(), in_end: RF.getVarContents().end());
897 RF.setVarContents(Code);
898
899 // Adjust the fixups for the change in offsets
900 for (auto &F : RF.getVarFixups())
901 F.setOffset(PrefixBytesToAdd + F.getOffset());
902
903 RemainingSize -= PrefixBytesToAdd;
904 return true;
905}
906
907bool X86AsmBackend::padInstructionViaRelaxation(MCFragment &RF,
908 MCCodeEmitter &Emitter,
909 unsigned &RemainingSize) const {
910 if (!mayNeedRelaxation(Opcode: RF.getOpcode(), Operands: RF.getOperands(),
911 STI: *RF.getSubtargetInfo()))
912 // TODO: There are lots of other tricks we could apply for increasing
913 // encoding size without impacting performance.
914 return false;
915
916 MCInst Relaxed = RF.getInst();
917 relaxInstruction(Inst&: Relaxed, STI: *RF.getSubtargetInfo());
918
919 SmallVector<MCFixup, 4> Fixups;
920 SmallString<15> Code;
921 Emitter.encodeInstruction(Inst: Relaxed, CB&: Code, Fixups, STI: *RF.getSubtargetInfo());
922 const unsigned OldSize = RF.getVarContents().size();
923 const unsigned NewSize = Code.size();
924 assert(NewSize >= OldSize && "size decrease during relaxation?");
925 unsigned Delta = NewSize - OldSize;
926 if (Delta > RemainingSize)
927 return false;
928 RF.setInst(Relaxed);
929 RF.setVarContents(Code);
930 RF.setVarFixups(Fixups);
931 RemainingSize -= Delta;
932 return true;
933}
934
935bool X86AsmBackend::padInstructionEncoding(MCFragment &RF,
936 MCCodeEmitter &Emitter,
937 unsigned &RemainingSize) const {
938 bool Changed = false;
939 if (RemainingSize != 0)
940 Changed |= padInstructionViaRelaxation(RF, Emitter, RemainingSize);
941 if (RemainingSize != 0)
942 Changed |= padInstructionViaPrefix(RF, Emitter, RemainingSize);
943 return Changed;
944}
945
946bool X86AsmBackend::padInstsBackward(SmallVectorImpl<MCFragment *> &Relaxable,
947 unsigned &RemainingSize) const {
948 bool Changed = false;
949 while (!Relaxable.empty() && RemainingSize != 0) {
950 auto &RF = *Relaxable.pop_back_val();
951 // Give the backend a chance to play any tricks it wishes to increase
952 // the encoding size of the given instruction. Target independent code
953 // will try further relaxation, but target's may play further tricks.
954 Changed |= padInstructionEncoding(RF, Emitter&: Asm->getEmitter(), RemainingSize);
955
956 // If we have an instruction which hasn't been fully relaxed, we can't
957 // skip past it and insert bytes before it. Changing its starting
958 // offset might require a larger negative offset than it can encode.
959 // We don't need to worry about larger positive offsets as none of the
960 // possible offsets between this and our align are visible, and the
961 // ones afterwards aren't changing.
962 if (mayNeedRelaxation(Opcode: RF.getOpcode(), Operands: RF.getOperands(),
963 STI: *RF.getSubtargetInfo()))
964 break;
965 }
966 Relaxable.clear();
967 return Changed;
968}
969
970/// Trade the padding held by \p BF for ignored prefixes on the instructions
971/// around it. Padding never leaves its own bundle, so no instruction or
972/// bundle-locked group moves across a boundary. \p Relaxable holds the
973/// preceding instructions in that bundle and is consumed.
974bool X86AsmBackend::foldBundlePad(
975 const MCAssembler &Asm, MCBoundaryAlignFragment &BF,
976 SmallVectorImpl<MCFragment *> &Relaxable) const {
977 const uint64_t BundleSize = Asm.getBundleAlign().value();
978 const uint64_t PadStart = Asm.getFragmentOffset(F: BF);
979 unsigned Remaining = BF.getSize();
980
981 // Only padding in PadStart's own bundle may move backward; an align_to_end
982 // group can push the rest into the next bundle.
983 unsigned Budget =
984 std::min<uint64_t>(a: Remaining, b: BundleSize - PadStart % BundleSize);
985 unsigned Left = Budget;
986 bool Changed = padInstsBackward(Relaxable, RemainingSize&: Left);
987 Remaining -= Budget - Left;
988
989 // Absorbing padding moves the group's start earlier while its end is pinned,
990 // so it may only grow into the slack in its bundle: BundleSize - GroupSize
991 // for align_to_end, zero for a group that already starts on a boundary.
992 if (BF.isAlignToEnd() && Remaining) {
993 uint64_t GroupSize = 0;
994 for (const MCFragment *F = BF.getNext();; F = F->getNext()) {
995 GroupSize += Asm.computeFragmentSize(F: *F);
996 if (F == BF.getLastFragment())
997 break;
998 }
999 if (GroupSize < BundleSize) {
1000 Left = Budget = std::min<uint64_t>(a: Remaining, b: BundleSize - GroupSize);
1001 for (MCFragment *F = BF.getNext(); F; F = F->getNext()) {
1002 if (F->getKind() == MCFragment::FT_Relaxable)
1003 Changed |= padInstructionEncoding(RF&: *F, Emitter&: Asm.getEmitter(), RemainingSize&: Left);
1004 if (F == BF.getLastFragment() || Left == 0)
1005 break;
1006 }
1007 Remaining -= Budget - Left;
1008 }
1009 }
1010
1011 BF.setSize(Remaining);
1012 return Changed;
1013}
1014
1015bool X86AsmBackend::optimizeBundleNops(const MCAssembler &Asm) const {
1016 const uint64_t BundleSize = Asm.getBundleAlign().value();
1017 bool Changed = false;
1018 for (MCSection &Sec : Asm) {
1019 if (!Sec.isText())
1020 continue;
1021
1022 // Instructions preceding the next padding and sharing its bundle.
1023 SmallVector<MCFragment *, 8> Relaxable;
1024 // Folding leaves stale offsets until the next layout, so skip the
1025 // rewritten range.
1026 const MCFragment *ResumeAfter = nullptr;
1027 for (MCFragment &F : Sec) {
1028 if (ResumeAfter) {
1029 if (&F == ResumeAfter)
1030 ResumeAfter = nullptr;
1031 continue;
1032 }
1033 uint64_t Offset = Asm.getFragmentOffset(F);
1034 if (!Relaxable.empty() &&
1035 Asm.getFragmentOffset(F: *Relaxable.front()) / BundleSize !=
1036 Offset / BundleSize)
1037 Relaxable.clear();
1038
1039 switch (F.getKind()) {
1040 case MCFragment::FT_BoundaryAlign: {
1041 auto &BF = static_cast<MCBoundaryAlignFragment &>(F);
1042 if (!BF.getSize())
1043 break; // Nothing to fold, and not a barrier.
1044 Changed |= foldBundlePad(Asm, BF, Relaxable);
1045 ResumeAfter = BF.getLastFragment();
1046 break;
1047 }
1048 case MCFragment::FT_Relaxable:
1049 Relaxable.push_back(Elt: &F);
1050 break;
1051 case MCFragment::FT_Data:
1052 break; // Fixed bytes, safe to shift.
1053 default:
1054 // Other kinds may change size when shifted (.p2align, .org, LEBs).
1055 Relaxable.clear();
1056 break;
1057 }
1058 }
1059 }
1060
1061 return Changed;
1062}
1063
1064bool X86AsmBackend::finishLayout() const {
1065 // With bundling, padding is fully determined during layout and the only
1066 // post-layout optimization is prefix padding.
1067 if (Asm->isBundlingEnabled())
1068 return TargetPrefixMax != 0 && optimizeBundleNops(Asm: *Asm);
1069 // See if we can further relax some instructions to cut down on the number of
1070 // nop bytes required for code alignment. The actual win is in reducing
1071 // instruction count, not number of bytes. Modern X86-64 can easily end up
1072 // decode limited. It is often better to reduce the number of instructions
1073 // (i.e. eliminate nops) even at the cost of increasing the size and
1074 // complexity of others.
1075 if (!X86PadForAlign && !X86PadForBranchAlign)
1076 return false;
1077
1078 // The processed regions are delimitered by LabeledFragments. -g may have more
1079 // MCSymbols and therefore different relaxation results. X86PadForAlign is
1080 // disabled by default to eliminate the -g vs non -g difference.
1081 DenseSet<MCFragment *> LabeledFragments;
1082 for (const MCSymbol &S : Asm->symbols())
1083 LabeledFragments.insert(V: S.getFragment());
1084
1085 bool Changed = false;
1086 for (MCSection &Sec : *Asm) {
1087 if (!Sec.isText())
1088 continue;
1089
1090 SmallVector<MCFragment *, 4> Relaxable;
1091 for (MCSection::iterator I = Sec.begin(), IE = Sec.end(); I != IE; ++I) {
1092 MCFragment &F = *I;
1093
1094 if (LabeledFragments.count(V: &F))
1095 Relaxable.clear();
1096
1097 if (F.getKind() == MCFragment::FT_Data) // Skip and ignore
1098 continue;
1099
1100 if (F.getKind() == MCFragment::FT_Relaxable) {
1101 auto &RF = cast<MCFragment>(Val&: *I);
1102 Relaxable.push_back(Elt: &RF);
1103 continue;
1104 }
1105
1106 auto canHandle = [](MCFragment &F) -> bool {
1107 switch (F.getKind()) {
1108 default:
1109 return false;
1110 case MCFragment::FT_Align:
1111 return X86PadForAlign;
1112 case MCFragment::FT_BoundaryAlign:
1113 return X86PadForBranchAlign;
1114 }
1115 };
1116 // For any unhandled kind, assume we can't change layout.
1117 if (!canHandle(F)) {
1118 Relaxable.clear();
1119 continue;
1120 }
1121
1122 // To keep the effects local, prefer to relax instructions closest to
1123 // the align directive. This is purely about human understandability
1124 // of the resulting code. If we later find a reason to expand
1125 // particular instructions over others, we can adjust.
1126 unsigned RemainingSize = Asm->computeFragmentSize(F) - F.getFixedSize();
1127 Changed |= padInstsBackward(Relaxable, RemainingSize);
1128
1129 // If we're looking at a boundary align, make sure we don't try to pad
1130 // its target instructions for some following directive. Doing so would
1131 // break the alignment of the current boundary align.
1132 if (auto *BF = dyn_cast<MCBoundaryAlignFragment>(Val: &F)) {
1133 cast<MCBoundaryAlignFragment>(Val&: F).setSize(RemainingSize);
1134 Changed = true;
1135 const MCFragment *LastFragment = BF->getLastFragment();
1136 if (!LastFragment)
1137 continue;
1138 while (&*I != LastFragment)
1139 ++I;
1140 }
1141 }
1142 }
1143
1144 return Changed;
1145}
1146
1147unsigned X86AsmBackend::getMaximumNopSize(const MCSubtargetInfo &STI) const {
1148 if (STI.hasFeature(Feature: X86::Is16Bit))
1149 return 4;
1150 if (!STI.hasFeature(Feature: X86::FeatureNOPL) && !STI.hasFeature(Feature: X86::Is64Bit))
1151 return 1;
1152 if (STI.hasFeature(Feature: X86::TuningFast7ByteNOP))
1153 return 7;
1154 if (STI.hasFeature(Feature: X86::TuningFast15ByteNOP))
1155 return 15;
1156 if (STI.hasFeature(Feature: X86::TuningFast11ByteNOP))
1157 return 11;
1158 // FIXME: handle 32-bit mode
1159 // 15-bytes is the longest single NOP instruction, but 10-bytes is
1160 // commonly the longest that can be efficiently decoded.
1161 return 10;
1162}
1163
1164/// Write a sequence of optimal nops to the output, covering \p Count
1165/// bytes.
1166/// \return - true on success, false on failure
1167bool X86AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
1168 const MCSubtargetInfo *STI) const {
1169 static const char Nops32Bit[10][11] = {
1170 // nop
1171 "\x90",
1172 // xchg %ax,%ax
1173 "\x66\x90",
1174 // nopl (%[re]ax)
1175 "\x0f\x1f\x00",
1176 // nopl 0(%[re]ax)
1177 "\x0f\x1f\x40\x00",
1178 // nopl 0(%[re]ax,%[re]ax,1)
1179 "\x0f\x1f\x44\x00\x00",
1180 // nopw 0(%[re]ax,%[re]ax,1)
1181 "\x66\x0f\x1f\x44\x00\x00",
1182 // nopl 0L(%[re]ax)
1183 "\x0f\x1f\x80\x00\x00\x00\x00",
1184 // nopl 0L(%[re]ax,%[re]ax,1)
1185 "\x0f\x1f\x84\x00\x00\x00\x00\x00",
1186 // nopw 0L(%[re]ax,%[re]ax,1)
1187 "\x66\x0f\x1f\x84\x00\x00\x00\x00\x00",
1188 // nopw %cs:0L(%[re]ax,%[re]ax,1)
1189 "\x66\x2e\x0f\x1f\x84\x00\x00\x00\x00\x00",
1190 };
1191
1192 // 16-bit mode uses different nop patterns than 32-bit.
1193 static const char Nops16Bit[4][11] = {
1194 // nop
1195 "\x90",
1196 // xchg %eax,%eax
1197 "\x66\x90",
1198 // lea 0(%si),%si
1199 "\x8d\x74\x00",
1200 // lea 0w(%si),%si
1201 "\x8d\xb4\x00\x00",
1202 };
1203
1204 const char(*Nops)[11] =
1205 STI->hasFeature(Feature: X86::Is16Bit) ? Nops16Bit : Nops32Bit;
1206
1207 uint64_t MaxNopLength = (uint64_t)getMaximumNopSize(STI: *STI);
1208
1209 // Emit as many MaxNopLength NOPs as needed, then emit a NOP of the remaining
1210 // length.
1211 do {
1212 const uint8_t ThisNopLength = (uint8_t) std::min(a: Count, b: MaxNopLength);
1213 const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
1214 for (uint8_t i = 0; i < Prefixes; i++)
1215 OS << '\x66';
1216 const uint8_t Rest = ThisNopLength - Prefixes;
1217 if (Rest != 0)
1218 OS.write(Ptr: Nops[Rest - 1], Size: Rest);
1219 Count -= ThisNopLength;
1220 } while (Count != 0);
1221
1222 return true;
1223}
1224
1225/* *** */
1226
1227namespace {
1228
1229class ELFX86AsmBackend : public X86AsmBackend {
1230public:
1231 uint8_t OSABI;
1232 ELFX86AsmBackend(const Target &T, uint8_t OSABI, const MCSubtargetInfo &STI)
1233 : X86AsmBackend(T, STI), OSABI(OSABI) {}
1234};
1235
1236class ELFX86_32AsmBackend : public ELFX86AsmBackend {
1237public:
1238 ELFX86_32AsmBackend(const Target &T, uint8_t OSABI,
1239 const MCSubtargetInfo &STI)
1240 : ELFX86AsmBackend(T, OSABI, STI) {}
1241
1242 std::unique_ptr<MCObjectTargetWriter>
1243 createObjectTargetWriter() const override {
1244 return createX86ELFObjectWriter(/*IsELF64*/ false, OSABI, EMachine: ELF::EM_386);
1245 }
1246};
1247
1248class ELFX86_X32AsmBackend : public ELFX86AsmBackend {
1249public:
1250 ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI,
1251 const MCSubtargetInfo &STI)
1252 : ELFX86AsmBackend(T, OSABI, STI) {}
1253
1254 std::unique_ptr<MCObjectTargetWriter>
1255 createObjectTargetWriter() const override {
1256 return createX86ELFObjectWriter(/*IsELF64*/ false, OSABI,
1257 EMachine: ELF::EM_X86_64);
1258 }
1259};
1260
1261class ELFX86_IAMCUAsmBackend : public ELFX86AsmBackend {
1262public:
1263 ELFX86_IAMCUAsmBackend(const Target &T, uint8_t OSABI,
1264 const MCSubtargetInfo &STI)
1265 : ELFX86AsmBackend(T, OSABI, STI) {}
1266
1267 std::unique_ptr<MCObjectTargetWriter>
1268 createObjectTargetWriter() const override {
1269 return createX86ELFObjectWriter(/*IsELF64*/ false, OSABI,
1270 EMachine: ELF::EM_IAMCU);
1271 }
1272};
1273
1274class ELFX86_64AsmBackend : public ELFX86AsmBackend {
1275public:
1276 ELFX86_64AsmBackend(const Target &T, uint8_t OSABI,
1277 const MCSubtargetInfo &STI)
1278 : ELFX86AsmBackend(T, OSABI, STI) {}
1279
1280 std::unique_ptr<MCObjectTargetWriter>
1281 createObjectTargetWriter() const override {
1282 return createX86ELFObjectWriter(/*IsELF64*/ true, OSABI, EMachine: ELF::EM_X86_64);
1283 }
1284};
1285
1286class WindowsX86AsmBackend : public X86AsmBackend {
1287 bool Is64Bit;
1288
1289public:
1290 WindowsX86AsmBackend(const Target &T, bool is64Bit,
1291 const MCSubtargetInfo &STI)
1292 : X86AsmBackend(T, STI)
1293 , Is64Bit(is64Bit) {
1294 }
1295
1296 std::optional<MCFixupKind> getFixupKind(StringRef Name) const override {
1297 return StringSwitch<std::optional<MCFixupKind>>(Name)
1298 .Case(S: "dir32", Value: FK_Data_4)
1299 .Case(S: "secrel32", Value: FK_SecRel_4)
1300 .Case(S: "secidx", Value: FK_SecRel_2)
1301 .Default(Value: MCAsmBackend::getFixupKind(Name));
1302 }
1303
1304 std::unique_ptr<MCObjectTargetWriter>
1305 createObjectTargetWriter() const override {
1306 return createX86WinCOFFObjectWriter(Is64Bit);
1307 }
1308};
1309
1310namespace CU {
1311
1312 /// Compact unwind encoding values.
1313 enum CompactUnwindEncodings {
1314 /// [RE]BP based frame where [RE]BP is pused on the stack immediately after
1315 /// the return address, then [RE]SP is moved to [RE]BP.
1316 UNWIND_MODE_BP_FRAME = 0x01000000,
1317
1318 /// A frameless function with a small constant stack size.
1319 UNWIND_MODE_STACK_IMMD = 0x02000000,
1320
1321 /// A frameless function with a large constant stack size.
1322 UNWIND_MODE_STACK_IND = 0x03000000,
1323
1324 /// No compact unwind encoding is available.
1325 UNWIND_MODE_DWARF = 0x04000000,
1326
1327 /// Mask for encoding the frame registers.
1328 UNWIND_BP_FRAME_REGISTERS = 0x00007FFF,
1329
1330 /// Mask for encoding the frameless registers.
1331 UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF
1332 };
1333
1334} // namespace CU
1335
1336class DarwinX86AsmBackend : public X86AsmBackend {
1337 const MCRegisterInfo &MRI;
1338
1339 /// Number of registers that can be saved in a compact unwind encoding.
1340 enum { CU_NUM_SAVED_REGS = 6 };
1341
1342 mutable unsigned SavedRegs[CU_NUM_SAVED_REGS];
1343 Triple TT;
1344 bool Is64Bit;
1345
1346 unsigned OffsetSize; ///< Offset of a "push" instruction.
1347 unsigned MoveInstrSize; ///< Size of a "move" instruction.
1348 unsigned StackDivide; ///< Amount to adjust stack size by.
1349protected:
1350 /// Size of a "push" instruction for the given register.
1351 unsigned PushInstrSize(MCRegister Reg) const {
1352 switch (Reg.id()) {
1353 case X86::EBX:
1354 case X86::ECX:
1355 case X86::EDX:
1356 case X86::EDI:
1357 case X86::ESI:
1358 case X86::EBP:
1359 case X86::RBX:
1360 case X86::RBP:
1361 return 1;
1362 case X86::R12:
1363 case X86::R13:
1364 case X86::R14:
1365 case X86::R15:
1366 return 2;
1367 }
1368 return 1;
1369 }
1370
1371private:
1372 /// Get the compact unwind number for a given register. The number
1373 /// corresponds to the enum lists in compact_unwind_encoding.h.
1374 int getCompactUnwindRegNum(unsigned Reg) const {
1375 static const MCPhysReg CU32BitRegs[7] = {
1376 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
1377 };
1378 static const MCPhysReg CU64BitRegs[] = {
1379 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
1380 };
1381 const MCPhysReg *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
1382 for (int Idx = 1; *CURegs; ++CURegs, ++Idx)
1383 if (*CURegs == Reg)
1384 return Idx;
1385
1386 return -1;
1387 }
1388
1389 /// Return the registers encoded for a compact encoding with a frame
1390 /// pointer.
1391 uint32_t encodeCompactUnwindRegistersWithFrame() const {
1392 // Encode the registers in the order they were saved --- 3-bits per
1393 // register. The list of saved registers is assumed to be in reverse
1394 // order. The registers are numbered from 1 to CU_NUM_SAVED_REGS.
1395 uint32_t RegEnc = 0;
1396 for (int i = 0, Idx = 0; i != CU_NUM_SAVED_REGS; ++i) {
1397 unsigned Reg = SavedRegs[i];
1398 if (Reg == 0) break;
1399
1400 int CURegNum = getCompactUnwindRegNum(Reg);
1401 if (CURegNum == -1) return ~0U;
1402
1403 // Encode the 3-bit register number in order, skipping over 3-bits for
1404 // each register.
1405 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3);
1406 }
1407
1408 assert((RegEnc & 0x3FFFF) == RegEnc &&
1409 "Invalid compact register encoding!");
1410 return RegEnc;
1411 }
1412
1413 /// Create the permutation encoding used with frameless stacks. It is
1414 /// passed the number of registers to be saved and an array of the registers
1415 /// saved.
1416 uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned RegCount) const {
1417 // The saved registers are numbered from 1 to 6. In order to encode the
1418 // order in which they were saved, we re-number them according to their
1419 // place in the register order. The re-numbering is relative to the last
1420 // re-numbered register. E.g., if we have registers {6, 2, 4, 5} saved in
1421 // that order:
1422 //
1423 // Orig Re-Num
1424 // ---- ------
1425 // 6 6
1426 // 2 2
1427 // 4 3
1428 // 5 3
1429 //
1430 for (unsigned i = 0; i < RegCount; ++i) {
1431 int CUReg = getCompactUnwindRegNum(Reg: SavedRegs[i]);
1432 if (CUReg == -1) return ~0U;
1433 SavedRegs[i] = CUReg;
1434 }
1435
1436 // Reverse the list.
1437 std::reverse(first: &SavedRegs[0], last: &SavedRegs[CU_NUM_SAVED_REGS]);
1438
1439 uint32_t RenumRegs[CU_NUM_SAVED_REGS];
1440 for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){
1441 unsigned Countless = 0;
1442 for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j)
1443 if (SavedRegs[j] < SavedRegs[i])
1444 ++Countless;
1445
1446 RenumRegs[i] = SavedRegs[i] - Countless - 1;
1447 }
1448
1449 // Take the renumbered values and encode them into a 10-bit number.
1450 uint32_t permutationEncoding = 0;
1451 switch (RegCount) {
1452 case 6:
1453 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
1454 + 6 * RenumRegs[2] + 2 * RenumRegs[3]
1455 + RenumRegs[4];
1456 break;
1457 case 5:
1458 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
1459 + 6 * RenumRegs[3] + 2 * RenumRegs[4]
1460 + RenumRegs[5];
1461 break;
1462 case 4:
1463 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
1464 + 3 * RenumRegs[4] + RenumRegs[5];
1465 break;
1466 case 3:
1467 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
1468 + RenumRegs[5];
1469 break;
1470 case 2:
1471 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
1472 break;
1473 case 1:
1474 permutationEncoding |= RenumRegs[5];
1475 break;
1476 }
1477
1478 assert((permutationEncoding & 0x3FF) == permutationEncoding &&
1479 "Invalid compact register encoding!");
1480 return permutationEncoding;
1481 }
1482
1483public:
1484 DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI,
1485 const MCSubtargetInfo &STI)
1486 : X86AsmBackend(T, STI), MRI(MRI), TT(STI.getTargetTriple()),
1487 Is64Bit(TT.isX86_64()) {
1488 memset(s: SavedRegs, c: 0, n: sizeof(SavedRegs));
1489 OffsetSize = Is64Bit ? 8 : 4;
1490 MoveInstrSize = Is64Bit ? 3 : 2;
1491 StackDivide = Is64Bit ? 8 : 4;
1492 }
1493
1494 std::unique_ptr<MCObjectTargetWriter>
1495 createObjectTargetWriter() const override {
1496 uint32_t CPUType = cantFail(ValOrErr: MachO::getCPUType(T: TT));
1497 uint32_t CPUSubType = cantFail(ValOrErr: MachO::getCPUSubType(T: TT));
1498 return createX86MachObjectWriter(Is64Bit, CPUType, CPUSubtype: CPUSubType);
1499 }
1500
1501 /// Implementation of algorithm to generate the compact unwind encoding
1502 /// for the CFI instructions.
1503 uint64_t generateCompactUnwindEncoding(const MCDwarfFrameInfo *FI,
1504 const MCContext *Ctxt) const override {
1505 if (Ctxt->emitDwarfUnwindInfo() == EmitDwarfUnwindType::DwarfOnly)
1506 return CU::UNWIND_MODE_DWARF;
1507
1508 // Signal frames cannot be encoded in compact unwind.
1509 if (FI->IsSignalFrame)
1510 return CU::UNWIND_MODE_DWARF;
1511
1512 ArrayRef<MCCFIInstruction> Instrs = FI->Instructions;
1513 if (Instrs.empty()) return 0;
1514 if (!isDarwinCanonicalPersonality(Sym: FI->Personality) &&
1515 !Ctxt->emitCompactUnwindNonCanonical())
1516 return CU::UNWIND_MODE_DWARF;
1517
1518 // Reset the saved registers.
1519 unsigned SavedRegIdx = 0;
1520 memset(s: SavedRegs, c: 0, n: sizeof(SavedRegs));
1521
1522 bool HasFP = false;
1523
1524 // Encode that we are using EBP/RBP as the frame pointer.
1525 uint64_t CompactUnwindEncoding = 0;
1526
1527 unsigned SubtractInstrIdx = Is64Bit ? 3 : 2;
1528 unsigned InstrOffset = 0;
1529 unsigned StackAdjust = 0;
1530 uint64_t StackSize = 0;
1531 int64_t MinAbsOffset = std::numeric_limits<int64_t>::max();
1532
1533 for (const MCCFIInstruction &Inst : Instrs) {
1534 switch (Inst.getOperation()) {
1535 default:
1536 // Any other CFI directives indicate a frame that we aren't prepared
1537 // to represent via compact unwind, so just bail out.
1538 return CU::UNWIND_MODE_DWARF;
1539 case MCCFIInstruction::OpDefCfaRegister: {
1540 // Defines a frame pointer. E.g.
1541 //
1542 // movq %rsp, %rbp
1543 // L0:
1544 // .cfi_def_cfa_register %rbp
1545 //
1546 HasFP = true;
1547
1548 // If the frame pointer is other than esp/rsp, we do not have a way to
1549 // generate a compact unwinding representation, so bail out.
1550 if (*MRI.getLLVMRegNum(RegNum: Inst.getRegister(), isEH: true) !=
1551 (Is64Bit ? X86::RBP : X86::EBP))
1552 return CU::UNWIND_MODE_DWARF;
1553
1554 // Reset the counts.
1555 memset(s: SavedRegs, c: 0, n: sizeof(SavedRegs));
1556 StackAdjust = 0;
1557 SavedRegIdx = 0;
1558 MinAbsOffset = std::numeric_limits<int64_t>::max();
1559 InstrOffset += MoveInstrSize;
1560 break;
1561 }
1562 case MCCFIInstruction::OpDefCfaOffset: {
1563 // Defines a new offset for the CFA. E.g.
1564 //
1565 // With frame:
1566 //
1567 // pushq %rbp
1568 // L0:
1569 // .cfi_def_cfa_offset 16
1570 //
1571 // Without frame:
1572 //
1573 // subq $72, %rsp
1574 // L0:
1575 // .cfi_def_cfa_offset 80
1576 //
1577 StackSize = Inst.getOffset() / StackDivide;
1578 break;
1579 }
1580 case MCCFIInstruction::OpOffset: {
1581 // Defines a "push" of a callee-saved register. E.g.
1582 //
1583 // pushq %r15
1584 // pushq %r14
1585 // pushq %rbx
1586 // L0:
1587 // subq $120, %rsp
1588 // L1:
1589 // .cfi_offset %rbx, -40
1590 // .cfi_offset %r14, -32
1591 // .cfi_offset %r15, -24
1592 //
1593 if (SavedRegIdx == CU_NUM_SAVED_REGS)
1594 // If there are too many saved registers, we cannot use a compact
1595 // unwind encoding.
1596 return CU::UNWIND_MODE_DWARF;
1597
1598 MCRegister Reg = *MRI.getLLVMRegNum(RegNum: Inst.getRegister(), isEH: true);
1599 SavedRegs[SavedRegIdx++] = Reg.id();
1600 StackAdjust += OffsetSize;
1601 MinAbsOffset = std::min(a: MinAbsOffset, b: std::abs(i: Inst.getOffset()));
1602 InstrOffset += PushInstrSize(Reg);
1603 break;
1604 }
1605 }
1606 }
1607
1608 StackAdjust /= StackDivide;
1609
1610 if (HasFP) {
1611 if ((StackAdjust & 0xFF) != StackAdjust)
1612 // Offset was too big for a compact unwind encoding.
1613 return CU::UNWIND_MODE_DWARF;
1614
1615 // We don't attempt to track a real StackAdjust, so if the saved registers
1616 // aren't adjacent to rbp we can't cope.
1617 if (SavedRegIdx != 0 && MinAbsOffset != 3 * (int)OffsetSize)
1618 return CU::UNWIND_MODE_DWARF;
1619
1620 // Get the encoding of the saved registers when we have a frame pointer.
1621 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame();
1622 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
1623
1624 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
1625 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
1626 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
1627 } else {
1628 SubtractInstrIdx += InstrOffset;
1629 ++StackAdjust;
1630
1631 if ((StackSize & 0xFF) == StackSize) {
1632 // Frameless stack with a small stack size.
1633 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
1634
1635 // Encode the stack size.
1636 CompactUnwindEncoding |= (StackSize & 0xFF) << 16;
1637 } else {
1638 if ((StackAdjust & 0x7) != StackAdjust)
1639 // The extra stack adjustments are too big for us to handle.
1640 return CU::UNWIND_MODE_DWARF;
1641
1642 // Frameless stack with an offset too large for us to encode compactly.
1643 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
1644
1645 // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP'
1646 // instruction.
1647 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
1648
1649 // Encode any extra stack adjustments (done via push instructions).
1650 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
1651 }
1652
1653 // Encode the number of registers saved. (Reverse the list first.)
1654 std::reverse(first: &SavedRegs[0], last: &SavedRegs[SavedRegIdx]);
1655 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
1656
1657 // Get the encoding of the saved registers when we don't have a frame
1658 // pointer.
1659 uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(RegCount: SavedRegIdx);
1660 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
1661
1662 // Encode the register encoding.
1663 CompactUnwindEncoding |=
1664 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
1665 }
1666
1667 return CompactUnwindEncoding;
1668 }
1669};
1670
1671} // end anonymous namespace
1672
1673MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
1674 const MCSubtargetInfo &STI,
1675 const MCRegisterInfo &MRI,
1676 const MCTargetOptions &Options) {
1677 const Triple &TheTriple = STI.getTargetTriple();
1678 if (TheTriple.isOSBinFormatMachO())
1679 return new DarwinX86AsmBackend(T, MRI, STI);
1680
1681 if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF())
1682 return new WindowsX86AsmBackend(T, false, STI);
1683
1684 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType: TheTriple.getOS());
1685
1686 if (TheTriple.isOSIAMCU())
1687 return new ELFX86_IAMCUAsmBackend(T, OSABI, STI);
1688
1689 return new ELFX86_32AsmBackend(T, OSABI, STI);
1690}
1691
1692MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
1693 const MCSubtargetInfo &STI,
1694 const MCRegisterInfo &MRI,
1695 const MCTargetOptions &Options) {
1696 const Triple &TheTriple = STI.getTargetTriple();
1697 if (TheTriple.isOSBinFormatMachO())
1698 return new DarwinX86AsmBackend(T, MRI, STI);
1699
1700 if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF())
1701 return new WindowsX86AsmBackend(T, true, STI);
1702
1703 if (TheTriple.isUEFI()) {
1704 assert(TheTriple.isOSBinFormatCOFF() &&
1705 "Only COFF format is supported in UEFI environment.");
1706 return new WindowsX86AsmBackend(T, true, STI);
1707 }
1708
1709 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType: TheTriple.getOS());
1710
1711 if (TheTriple.isX32())
1712 return new ELFX86_X32AsmBackend(T, OSABI, STI);
1713 return new ELFX86_64AsmBackend(T, OSABI, STI);
1714}
1715
1716namespace {
1717class X86ELFStreamer : public MCELFStreamer {
1718public:
1719 X86ELFStreamer(MCContext &Context, std::unique_ptr<MCAsmBackend> TAB,
1720 std::unique_ptr<MCObjectWriter> OW,
1721 std::unique_ptr<MCCodeEmitter> Emitter)
1722 : MCELFStreamer(Context, std::move(TAB), std::move(OW),
1723 std::move(Emitter)) {}
1724
1725 void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override;
1726};
1727} // end anonymous namespace
1728
1729void X86ELFStreamer::emitInstruction(const MCInst &Inst,
1730 const MCSubtargetInfo &STI) {
1731 X86_MC::emitInstruction(S&: *this, Inst, STI);
1732}
1733
1734MCStreamer *llvm::createX86ELFStreamer(const Triple &T, MCContext &Context,
1735 std::unique_ptr<MCAsmBackend> &&MAB,
1736 std::unique_ptr<MCObjectWriter> &&MOW,
1737 std::unique_ptr<MCCodeEmitter> &&MCE) {
1738 return new X86ELFStreamer(Context, std::move(MAB), std::move(MOW),
1739 std::move(MCE));
1740}
1741