1//===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "MCTargetDesc/X86BaseInfo.h"
10#include "MCTargetDesc/X86EncodingOptimization.h"
11#include "MCTargetDesc/X86FixupKinds.h"
12#include "MCTargetDesc/X86MCAsmInfo.h"
13#include "MCTargetDesc/X86MCOptions.h"
14#include "llvm/ADT/StringSwitch.h"
15#include "llvm/BinaryFormat/ELF.h"
16#include "llvm/BinaryFormat/MachO.h"
17#include "llvm/MC/MCAsmBackend.h"
18#include "llvm/MC/MCAssembler.h"
19#include "llvm/MC/MCCodeEmitter.h"
20#include "llvm/MC/MCContext.h"
21#include "llvm/MC/MCDwarf.h"
22#include "llvm/MC/MCELFObjectWriter.h"
23#include "llvm/MC/MCELFStreamer.h"
24#include "llvm/MC/MCExpr.h"
25#include "llvm/MC/MCInst.h"
26#include "llvm/MC/MCInstrInfo.h"
27#include "llvm/MC/MCLFIRewriter.h"
28#include "llvm/MC/MCObjectStreamer.h"
29#include "llvm/MC/MCObjectWriter.h"
30#include "llvm/MC/MCRegisterInfo.h"
31#include "llvm/MC/MCSection.h"
32#include "llvm/MC/MCSubtargetInfo.h"
33#include "llvm/MC/MCTargetOptions.h"
34#include "llvm/MC/MCValue.h"
35#include "llvm/MC/TargetRegistry.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38
39using namespace llvm;
40
41namespace {
42/// A wrapper for holding a mask of the values from X86::AlignBranchBoundaryKind
43class X86AlignBranchKind {
44private:
45 uint8_t AlignBranchKind = 0;
46
47public:
48 X86AlignBranchKind() = default;
49 explicit X86AlignBranchKind(StringRef Val) {
50 SmallVector<StringRef, 6> BranchTypes;
51 Val.split(A&: BranchTypes, Separator: '+', MaxSplit: -1, KeepEmpty: false);
52 for (auto BranchType : BranchTypes) {
53 if (BranchType == "fused")
54 addKind(Value: X86::AlignBranchFused);
55 else if (BranchType == "jcc")
56 addKind(Value: X86::AlignBranchJcc);
57 else if (BranchType == "jmp")
58 addKind(Value: X86::AlignBranchJmp);
59 else if (BranchType == "call")
60 addKind(Value: X86::AlignBranchCall);
61 else if (BranchType == "ret")
62 addKind(Value: X86::AlignBranchRet);
63 else if (BranchType == "indirect")
64 addKind(Value: X86::AlignBranchIndirect);
65 else {
66 errs() << "invalid argument " << BranchType.str()
67 << " to -x86-align-branch=; each element must be one of: fused, "
68 "jcc, jmp, call, ret, indirect.(plus separated)\n";
69 }
70 }
71 }
72
73 operator uint8_t() const { return AlignBranchKind; }
74 void addKind(X86::AlignBranchBoundaryKind Value) { AlignBranchKind |= Value; }
75};
76
77class X86AsmBackend : public MCAsmBackend {
78 const X86MCOptions &CLOpts;
79 const MCSubtargetInfo &STI;
80 std::unique_ptr<const MCInstrInfo> MCII;
81 X86AlignBranchKind AlignBranchType;
82 Align AlignBoundary;
83 unsigned TargetPrefixMax = 0;
84
85 MCInst PrevInst;
86 unsigned PrevInstOpcode = 0;
87 bool PrefixEndsBundleLock = false;
88 MCBoundaryAlignFragment *PendingBA = nullptr;
89 std::pair<MCFragment *, size_t> PrevInstPosition;
90
91 uint8_t determinePaddingPrefix(const MCInst &Inst) const;
92 bool isMacroFused(const MCInst &Cmp, const MCInst &Jcc) const;
93 bool needAlign(const MCInst &Inst) const;
94 bool canPadBranches(MCObjectStreamer &OS) const;
95 bool canPadInst(const MCInst &Inst, MCObjectStreamer &OS) const;
96 void emitInstructionBeginBundle(MCObjectStreamer &OS);
97 void emitInstructionEndBundle(MCObjectStreamer &OS);
98
99public:
100 X86AsmBackend(const X86MCOptions &CLOpts, const Target &T,
101 const MCSubtargetInfo &STI)
102 : MCAsmBackend(llvm::endianness::little), CLOpts(CLOpts), STI(STI),
103 MCII(T.createMCInstrInfo()) {
104 if (CLOpts.branches_within_32B_boundaries) {
105 // At the moment, this defaults to aligning fused branches, unconditional
106 // jumps, and (unfused) conditional jumps with nops. Both the
107 // instructions aligned and the alignment method (nop vs prefix) may
108 // change in the future.
109 AlignBoundary = assumeAligned(Value: 32);
110 AlignBranchType.addKind(Value: X86::AlignBranchFused);
111 AlignBranchType.addKind(Value: X86::AlignBranchJcc);
112 AlignBranchType.addKind(Value: X86::AlignBranchJmp);
113 }
114 // Allow overriding defaults set by main flag
115 if (CLOpts.align_branch_boundary)
116 AlignBoundary = assumeAligned(Value: *CLOpts.align_branch_boundary);
117 if (CLOpts.align_branch)
118 AlignBranchType = X86AlignBranchKind(*CLOpts.align_branch);
119 if (CLOpts.pad_max_prefix_size)
120 TargetPrefixMax = *CLOpts.pad_max_prefix_size;
121
122 AllowAutoPadding =
123 AlignBoundary != Align(1) && AlignBranchType != X86::AlignBranchNone;
124 AllowEnhancedRelaxation =
125 AllowAutoPadding && TargetPrefixMax != 0 && CLOpts.pad_for_branch_align;
126 AllowBundling = true;
127 }
128
129 const X86MCOptions &getCLOpts() const { return CLOpts; }
130
131 // The streamer frees the fragments these point into.
132 void reset() override {
133 PrevInst = MCInst();
134 PrevInstOpcode = 0;
135 PrefixEndsBundleLock = false;
136 PendingBA = nullptr;
137 PrevInstPosition = {};
138 }
139
140 void emitInstructionBegin(MCObjectStreamer &OS, const MCInst &Inst,
141 const MCSubtargetInfo &STI);
142 void emitInstructionEnd(MCObjectStreamer &OS, const MCInst &Inst);
143
144
145 std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
146
147 MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override;
148
149 std::optional<bool> evaluateFixup(const MCFragment &, MCFixup &, MCValue &,
150 uint64_t &) override;
151 void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target,
152 uint8_t *Data, uint64_t Value, bool IsResolved) override;
153
154 bool mayNeedRelaxation(unsigned Opcode, ArrayRef<MCOperand> Operands,
155 const MCSubtargetInfo &STI) const override;
156
157 bool fixupNeedsRelaxationAdvanced(const MCFragment &, const MCFixup &,
158 const MCValue &, uint64_t,
159 bool) const override;
160
161 void relaxInstruction(MCInst &Inst,
162 const MCSubtargetInfo &STI) const override;
163
164 bool padInstructionViaRelaxation(MCFragment &RF, MCCodeEmitter &Emitter,
165 unsigned &RemainingSize) const;
166
167 bool padInstructionViaPrefix(MCFragment &RF, MCCodeEmitter &Emitter,
168 unsigned &RemainingSize) const;
169
170 bool padInstructionEncoding(MCFragment &RF, MCCodeEmitter &Emitter,
171 unsigned &RemainingSize) const;
172
173 bool finishLayout() const override;
174
175 bool padInstsBackward(SmallVectorImpl<MCFragment *> &Relaxable,
176 unsigned &RemainingSize) const;
177 bool foldBundlePad(const MCAssembler &Asm, MCBoundaryAlignFragment &BF,
178 SmallVectorImpl<MCFragment *> &Relaxable) const;
179 bool optimizeBundleNops(const MCAssembler &Asm) const;
180
181 unsigned getMaximumNopSize(const MCSubtargetInfo &STI) const override;
182
183 bool writeNopData(raw_ostream &OS, uint64_t Count,
184 const MCSubtargetInfo *STI) const override;
185};
186} // end anonymous namespace
187
188static bool isRelaxableBranch(unsigned Opcode) {
189 return Opcode == X86::JCC_1 || Opcode == X86::JMP_1;
190}
191
192static unsigned getRelaxedOpcodeBranch(unsigned Opcode,
193 bool Is16BitMode = false) {
194 switch (Opcode) {
195 default:
196 llvm_unreachable("invalid opcode for branch");
197 case X86::JCC_1:
198 return (Is16BitMode) ? X86::JCC_2 : X86::JCC_4;
199 case X86::JMP_1:
200 return (Is16BitMode) ? X86::JMP_2 : X86::JMP_4;
201 }
202}
203
204static unsigned getRelaxedOpcode(const MCInst &MI, bool Is16BitMode) {
205 unsigned Opcode = MI.getOpcode();
206 return isRelaxableBranch(Opcode) ? getRelaxedOpcodeBranch(Opcode, Is16BitMode)
207 : X86::getOpcodeForLongImmediateForm(Opcode);
208}
209
210static X86::CondCode getCondFromBranch(const MCInst &MI,
211 const MCInstrInfo &MCII) {
212 unsigned Opcode = MI.getOpcode();
213 switch (Opcode) {
214 default:
215 return X86::COND_INVALID;
216 case X86::JCC_1: {
217 const MCInstrDesc &Desc = MCII.get(Opcode);
218 return static_cast<X86::CondCode>(
219 MI.getOperand(i: Desc.getNumOperands() - 1).getImm());
220 }
221 }
222}
223
224static X86::SecondMacroFusionInstKind
225classifySecondInstInMacroFusion(const MCInst &MI, const MCInstrInfo &MCII) {
226 X86::CondCode CC = getCondFromBranch(MI, MCII);
227 return classifySecondCondCodeInMacroFusion(CC);
228}
229
230/// Check if the instruction uses RIP relative addressing.
231static bool isRIPRelative(const MCInst &MI, const MCInstrInfo &MCII) {
232 const MCInstrDesc &Desc = MCII.get(Opcode: MI.getOpcode());
233 int MemoryOperand = X86II::getMemoryOperandIdx(Desc);
234 if (MemoryOperand < 0)
235 return false;
236 unsigned BaseRegNum = MemoryOperand + X86::AddrBaseReg;
237 MCRegister BaseReg = MI.getOperand(i: BaseRegNum).getReg();
238 return (BaseReg == X86::RIP);
239}
240
241/// Check if the instruction is a prefix.
242static bool isPrefix(unsigned Opcode, const MCInstrInfo &MCII) {
243 return X86II::isPrefix(TSFlags: MCII.get(Opcode).TSFlags);
244}
245
246/// Check if the instruction is valid as the first instruction in macro fusion.
247static bool isFirstMacroFusibleInst(const MCInst &Inst,
248 const MCInstrInfo &MCII) {
249 // An Intel instruction with RIP relative addressing is not macro fusible.
250 if (isRIPRelative(MI: Inst, MCII))
251 return false;
252 X86::FirstMacroFusionInstKind FIK =
253 X86::classifyFirstOpcodeInMacroFusion(Opcode: Inst.getOpcode());
254 return FIK != X86::FirstMacroFusionInstKind::Invalid;
255}
256
257/// X86 can reduce the bytes of NOP by padding instructions with prefixes to
258/// get a better peformance in some cases. Here, we determine which prefix is
259/// the most suitable.
260///
261/// If the instruction has a segment override prefix, use the existing one.
262/// If the target is 64-bit, use the CS.
263/// If the target is 32-bit,
264/// - If the instruction has a ESP/EBP base register, use SS.
265/// - Otherwise use DS.
266uint8_t X86AsmBackend::determinePaddingPrefix(const MCInst &Inst) const {
267 assert((STI.hasFeature(X86::Is32Bit) || STI.hasFeature(X86::Is64Bit)) &&
268 "Prefixes can be added only in 32-bit or 64-bit mode.");
269 const MCInstrDesc &Desc = MCII->get(Opcode: Inst.getOpcode());
270 uint64_t TSFlags = Desc.TSFlags;
271
272 // Determine where the memory operand starts, if present.
273 int MemoryOperand = X86II::getMemoryOperandIdx(Desc);
274
275 MCRegister SegmentReg;
276 if (MemoryOperand >= 0) {
277 // Check for explicit segment override on memory operand.
278 SegmentReg = Inst.getOperand(i: MemoryOperand + X86::AddrSegmentReg).getReg();
279 }
280
281 switch (TSFlags & X86II::FormMask) {
282 default:
283 break;
284 case X86II::RawFrmDstSrc: {
285 // Check segment override opcode prefix as needed (not for %ds).
286 if (Inst.getOperand(i: 2).getReg() != X86::DS)
287 SegmentReg = Inst.getOperand(i: 2).getReg();
288 break;
289 }
290 case X86II::RawFrmSrc: {
291 // Check segment override opcode prefix as needed (not for %ds).
292 if (Inst.getOperand(i: 1).getReg() != X86::DS)
293 SegmentReg = Inst.getOperand(i: 1).getReg();
294 break;
295 }
296 case X86II::RawFrmMemOffs: {
297 // Check segment override opcode prefix as needed.
298 SegmentReg = Inst.getOperand(i: 1).getReg();
299 break;
300 }
301 }
302
303 if (SegmentReg)
304 return X86::getSegmentOverridePrefixForReg(Reg: SegmentReg);
305
306 if (STI.hasFeature(Feature: X86::Is64Bit))
307 return X86::CS_Encoding;
308
309 if (MemoryOperand >= 0) {
310 unsigned BaseRegNum = MemoryOperand + X86::AddrBaseReg;
311 MCRegister BaseReg = Inst.getOperand(i: BaseRegNum).getReg();
312 if (BaseReg == X86::ESP || BaseReg == X86::EBP)
313 return X86::SS_Encoding;
314 }
315 return X86::DS_Encoding;
316}
317
318/// Check if the two instructions will be macro-fused on the target cpu.
319bool X86AsmBackend::isMacroFused(const MCInst &Cmp, const MCInst &Jcc) const {
320 const MCInstrDesc &InstDesc = MCII->get(Opcode: Jcc.getOpcode());
321 if (!InstDesc.isConditionalBranch())
322 return false;
323 if (!isFirstMacroFusibleInst(Inst: Cmp, MCII: *MCII))
324 return false;
325 const X86::FirstMacroFusionInstKind CmpKind =
326 X86::classifyFirstOpcodeInMacroFusion(Opcode: Cmp.getOpcode());
327 const X86::SecondMacroFusionInstKind BranchKind =
328 classifySecondInstInMacroFusion(MI: Jcc, MCII: *MCII);
329 return X86::isMacroFused(FirstKind: CmpKind, SecondKind: BranchKind);
330}
331
332/// Check if the instruction has a variant symbol operand.
333static bool hasVariantSymbol(const MCInst &MI) {
334 for (auto &Operand : MI) {
335 if (!Operand.isExpr())
336 continue;
337 const MCExpr &Expr = *Operand.getExpr();
338 if (Expr.getKind() == MCExpr::SymbolRef &&
339 cast<MCSymbolRefExpr>(Val: &Expr)->getSpecifier())
340 return true;
341 }
342 return false;
343}
344
345/// X86 has certain instructions which enable interrupts exactly one
346/// instruction *after* the instruction which stores to SS. Return true if the
347/// given instruction may have such an interrupt delay slot.
348static bool mayHaveInterruptDelaySlot(unsigned InstOpcode) {
349 switch (InstOpcode) {
350 case X86::POPSS16:
351 case X86::POPSS32:
352 case X86::STI:
353 return true;
354
355 case X86::MOV16sr:
356 case X86::MOV32sr:
357 case X86::MOV64sr:
358 case X86::MOV16sm:
359 // In fact, this is only the case if the first operand is SS. However, as
360 // segment moves occur extremely rarely, this is just a minor pessimization.
361 return true;
362 }
363 return false;
364}
365
366/// Return true if we can insert NOP or prefixes automatically before the
367/// the instruction to be emitted.
368bool X86AsmBackend::canPadInst(const MCInst &Inst, MCObjectStreamer &OS) const {
369 if (hasVariantSymbol(MI: Inst))
370 // Linker may rewrite the instruction with variant symbol operand(e.g.
371 // TLSCALL).
372 return false;
373
374 if (mayHaveInterruptDelaySlot(InstOpcode: PrevInstOpcode))
375 // If this instruction follows an interrupt enabling instruction with a one
376 // instruction delay, inserting a nop would change behavior.
377 return false;
378
379 if (isPrefix(Opcode: PrevInstOpcode, MCII: *MCII))
380 // If this instruction follows a prefix, inserting a nop/prefix would change
381 // semantic.
382 return false;
383
384 if (isPrefix(Opcode: Inst.getOpcode(), MCII: *MCII))
385 // If this instruction is a prefix, inserting a prefix would change
386 // semantic.
387 return false;
388
389 // If this instruction follows any data, there is no clear instruction
390 // boundary, inserting a nop/prefix would change semantic.
391 auto Offset = OS.getCurFragSize();
392 if (Offset && (OS.getCurrentFragment() != PrevInstPosition.first ||
393 Offset != PrevInstPosition.second))
394 return false;
395
396 return true;
397}
398
399bool X86AsmBackend::canPadBranches(MCObjectStreamer &OS) const {
400 if (!OS.getAllowAutoPadding())
401 return false;
402 assert(allowAutoPadding() && "incorrect initialization!");
403
404 // We only pad in text section.
405 if (!OS.getCurrentSectionOnly()->isText())
406 return false;
407
408 // Branches only need to be aligned in 32-bit or 64-bit mode.
409 if (!(STI.hasFeature(Feature: X86::Is64Bit) || STI.hasFeature(Feature: X86::Is32Bit)))
410 return false;
411
412 return true;
413}
414
415/// Check if the instruction operand needs to be aligned.
416bool X86AsmBackend::needAlign(const MCInst &Inst) const {
417 const MCInstrDesc &Desc = MCII->get(Opcode: Inst.getOpcode());
418 return (Desc.isConditionalBranch() &&
419 (AlignBranchType & X86::AlignBranchJcc)) ||
420 (Desc.isUnconditionalBranch() &&
421 (AlignBranchType & X86::AlignBranchJmp)) ||
422 (Desc.isCall() && (AlignBranchType & X86::AlignBranchCall)) ||
423 (Desc.isReturn() && (AlignBranchType & X86::AlignBranchRet)) ||
424 (Desc.isIndirectBranch() &&
425 (AlignBranchType & X86::AlignBranchIndirect));
426}
427
428void X86_MC::emitInstruction(MCObjectStreamer &S, const MCInst &Inst,
429 const MCSubtargetInfo &STI) {
430 auto &Backend = static_cast<X86AsmBackend &>(S.getAssembler().getBackend());
431 bool AutoPadding = S.getAllowAutoPadding();
432 if (LLVM_LIKELY(!AutoPadding && !Backend.getCLOpts().pad_for_align)) {
433 S.MCObjectStreamer::emitInstruction(Inst, STI);
434 return;
435 }
436
437 // Run the LFI rewriter outside of emitInstructionBegin/End so that nested
438 // instructions or bundle_lock/unlock directives do not corrupt the Begin/End
439 // bookkeeping for the original instruction.
440 if (S.getLFIRewriter() && S.getLFIRewriter()->rewriteInst(Inst, Out&: S, STI))
441 return;
442
443 Backend.emitInstructionBegin(OS&: S, Inst, STI);
444 S.MCObjectStreamer::emitInstruction(Inst, STI);
445 Backend.emitInstructionEnd(OS&: S, Inst);
446}
447
448/// Open a MCBoundaryAlignFragment for the upcoming instruction so that layout
449/// can pad it into the next bundle. Within .bundle_lock the group's fragment
450/// already covers it.
451void X86AsmBackend::emitInstructionBeginBundle(MCObjectStreamer &OS) {
452 assert(Asm->isBundlingEnabled());
453
454 // The prefix stays in the group while this instruction gets its own
455 // fragment, so padding may land between the two.
456 if (PrefixEndsBundleLock && OS.getCurrentFragment() != PrevInstPosition.first)
457 getContext().reportError(L: OS.getStartTokLoc(),
458 Msg: "instruction prefix cannot be the last "
459 "instruction of a .bundle_lock group");
460
461 if (OS.isBundleLocked())
462 return;
463 // A pending fragment means the previous MCInst was a prefix, which must stay
464 // with this one: extend its range. Adjacency rejects a fragment left stale by
465 // an intervening .bundle_lock group.
466 if (PendingBA &&
467 PendingBA->getLastFragment()->getNext() == OS.getCurrentFragment()) {
468 PendingBA->setLastFragment(OS.getCurrentFragment());
469 return;
470 }
471 PendingBA = OS.newSpecialFragment<MCBoundaryAlignFragment>(
472 args: Asm->getBundleAlign(), args: STI);
473 // We can set LastFragment now, before the instruction is emitted, as bundling
474 // emits one fragment per instruction. Deferring setLastFragment to
475 // post-emitInstruction would risk capturing a fragment that a subsequent
476 // emitCodeAlignment repurposes in-place to FT_Align, corrupting the BA's
477 // boundary range.
478 PendingBA->setLastFragment(OS.getCurrentFragment());
479}
480
481/// Close the fragment opened by emitInstructionBeginBundle, unless the
482/// instruction was a prefix, in which case the next one extends it.
483void X86AsmBackend::emitInstructionEndBundle(MCObjectStreamer &OS) {
484 assert(Asm->isBundlingEnabled());
485
486 if (OS.isBundleLocked()) {
487 PrefixEndsBundleLock = isPrefix(Opcode: PrevInstOpcode, MCII: *MCII);
488 return;
489 }
490 PrefixEndsBundleLock = false;
491 assert(PendingBA && "MCBoundaryAlignFragment is expected for every "
492 "instruction if it is not bundle-locked");
493
494 OS.getCurrentSectionOnly()->ensureMinAlignment(MinAlignment: Asm->getBundleAlign());
495
496 if (!isPrefix(Opcode: PrevInstOpcode, MCII: *MCII))
497 PendingBA = nullptr;
498}
499
500/// Insert BoundaryAlignFragment before instructions to align branches.
501void X86AsmBackend::emitInstructionBegin(MCObjectStreamer &OS,
502 const MCInst &Inst,
503 const MCSubtargetInfo &STI) {
504 bool CanPadInst = canPadInst(Inst, OS);
505 if (Asm->isBundlingEnabled()) {
506 emitInstructionBeginBundle(OS);
507 OS.getCurrentFragment()->setAllowAutoPadding(CanPadInst);
508 return;
509 }
510 if (CanPadInst)
511 OS.getCurrentFragment()->setAllowAutoPadding(true);
512
513 if (!canPadBranches(OS))
514 return;
515
516 // NB: PrevInst only valid if canPadBranches is true.
517 if (!isMacroFused(Cmp: PrevInst, Jcc: Inst))
518 // Macro fusion doesn't happen indeed, clear the pending.
519 PendingBA = nullptr;
520
521 // When branch padding is enabled (basically the skx102 erratum => unlikely),
522 // we call canPadInst (not cheap) twice. However, in the common case, we can
523 // avoid unnecessary calls to that, as this is otherwise only used for
524 // relaxable fragments.
525 if (!CanPadInst)
526 return;
527
528 if (PendingBA) {
529 auto *NextFragment = PendingBA->getNext();
530 assert(NextFragment && "NextFragment should not be null");
531 if (NextFragment == OS.getCurrentFragment())
532 return;
533 // We eagerly create an empty fragment when inserting a fragment
534 // with a variable-size tail.
535 if (NextFragment->getNext() == OS.getCurrentFragment())
536 return;
537
538 // Macro fusion actually happens and there is no other fragment inserted
539 // after the previous instruction.
540 //
541 // Do nothing here since we already inserted a BoudaryAlign fragment when
542 // we met the first instruction in the fused pair and we'll tie them
543 // together in emitInstructionEnd.
544 //
545 // Note: When there is at least one fragment, such as MCAlignFragment,
546 // inserted after the previous instruction, e.g.
547 //
548 // \code
549 // cmp %rax %rcx
550 // .align 16
551 // je .Label0
552 // \ endcode
553 //
554 // We will treat the JCC as a unfused branch although it may be fused
555 // with the CMP.
556 return;
557 }
558
559 if (needAlign(Inst) || ((AlignBranchType & X86::AlignBranchFused) &&
560 isFirstMacroFusibleInst(Inst, MCII: *MCII))) {
561 // If we meet a unfused branch or the first instuction in a fusiable pair,
562 // insert a BoundaryAlign fragment.
563 PendingBA =
564 OS.newSpecialFragment<MCBoundaryAlignFragment>(args&: AlignBoundary, args: STI);
565 }
566}
567
568/// Set the last fragment to be aligned for the BoundaryAlignFragment.
569void X86AsmBackend::emitInstructionEnd(MCObjectStreamer &OS,
570 const MCInst &Inst) {
571 // Update PrevInstOpcode here, canPadInst() reads that.
572 MCFragment *CF = OS.getCurrentFragment();
573 PrevInstOpcode = Inst.getOpcode();
574 PrevInstPosition = std::make_pair(x&: CF, y: OS.getCurFragSize());
575 if (Asm->isBundlingEnabled())
576 return emitInstructionEndBundle(OS);
577
578 if (!canPadBranches(OS))
579 return;
580
581 // PrevInst is only needed if canPadBranches. Copying an MCInst isn't cheap.
582 PrevInst = Inst;
583
584 if (!needAlign(Inst) || !PendingBA)
585 return;
586
587 // Tie the aligned instructions into a pending BoundaryAlign.
588 PendingBA->setLastFragment(CF);
589 PendingBA = nullptr;
590
591 // We need to ensure that further data isn't added to the current
592 // DataFragment, so that we can get the size of instructions later in
593 // MCAssembler::relaxBoundaryAlign. The easiest way is to insert a new empty
594 // DataFragment.
595 OS.newFragment();
596
597 // Update the maximum alignment on the current section if necessary.
598 CF->getParent()->ensureMinAlignment(MinAlignment: AlignBoundary);
599}
600
601std::optional<MCFixupKind> X86AsmBackend::getFixupKind(StringRef Name) const {
602 if (STI.getTargetTriple().isOSBinFormatELF()) {
603 unsigned Type;
604 if (STI.getTargetTriple().isX86_64()) {
605 Type = llvm::StringSwitch<unsigned>(Name)
606#define ELF_RELOC(X, Y) .Case(#X, Y)
607#include "llvm/BinaryFormat/ELFRelocs/x86_64.def"
608#undef ELF_RELOC
609 .Case(S: "BFD_RELOC_NONE", Value: ELF::R_X86_64_NONE)
610 .Case(S: "BFD_RELOC_8", Value: ELF::R_X86_64_8)
611 .Case(S: "BFD_RELOC_16", Value: ELF::R_X86_64_16)
612 .Case(S: "BFD_RELOC_32", Value: ELF::R_X86_64_32)
613 .Case(S: "BFD_RELOC_64", Value: ELF::R_X86_64_64)
614 .Default(Value: -1u);
615 } else {
616 Type = llvm::StringSwitch<unsigned>(Name)
617#define ELF_RELOC(X, Y) .Case(#X, Y)
618#include "llvm/BinaryFormat/ELFRelocs/i386.def"
619#undef ELF_RELOC
620 .Case(S: "BFD_RELOC_NONE", Value: ELF::R_386_NONE)
621 .Case(S: "BFD_RELOC_8", Value: ELF::R_386_8)
622 .Case(S: "BFD_RELOC_16", Value: ELF::R_386_16)
623 .Case(S: "BFD_RELOC_32", Value: ELF::R_386_32)
624 .Default(Value: -1u);
625 }
626 if (Type == -1u)
627 return std::nullopt;
628 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
629 }
630 return MCAsmBackend::getFixupKind(Name);
631}
632
633MCFixupKindInfo X86AsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
634 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
635 // clang-format off
636 {.Name: "reloc_riprel_4byte", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
637 {.Name: "reloc_riprel_4byte_movq_load", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
638 {.Name: "reloc_riprel_4byte_movq_load_rex2", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
639 {.Name: "reloc_riprel_4byte_relax", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
640 {.Name: "reloc_riprel_4byte_relax_rex", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
641 {.Name: "reloc_riprel_4byte_relax_rex2", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
642 {.Name: "reloc_riprel_4byte_relax_evex", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
643 {.Name: "reloc_signed_4byte", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
644 {.Name: "reloc_signed_4byte_relax", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
645 {.Name: "reloc_global_offset_table", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
646 {.Name: "reloc_branch_4byte_pcrel", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
647 // clang-format on
648 };
649
650 // Fixup kinds from .reloc directive are like R_386_NONE/R_X86_64_NONE. They
651 // do not require any extra processing.
652 if (mc::isRelocation(FixupKind: Kind))
653 return {};
654
655 if (Kind < FirstTargetFixupKind)
656 return MCAsmBackend::getFixupKindInfo(Kind);
657
658 assert(unsigned(Kind - FirstTargetFixupKind) < X86::NumTargetFixupKinds &&
659 "Invalid kind!");
660 assert(Infos[Kind - FirstTargetFixupKind].Name && "Empty fixup name!");
661 return Infos[Kind - FirstTargetFixupKind];
662}
663
664static unsigned getFixupKindSize(unsigned Kind) {
665 switch (Kind) {
666 default:
667 llvm_unreachable("invalid fixup kind!");
668 case FK_NONE:
669 return 0;
670 case FK_SecRel_1:
671 case FK_Data_1:
672 return 1;
673 case FK_SecRel_2:
674 case FK_Data_2:
675 return 2;
676 case X86::reloc_riprel_4byte:
677 case X86::reloc_riprel_4byte_relax:
678 case X86::reloc_riprel_4byte_relax_rex:
679 case X86::reloc_riprel_4byte_relax_rex2:
680 case X86::reloc_riprel_4byte_movq_load:
681 case X86::reloc_riprel_4byte_movq_load_rex2:
682 case X86::reloc_riprel_4byte_relax_evex:
683 case X86::reloc_signed_4byte:
684 case X86::reloc_signed_4byte_relax:
685 case X86::reloc_global_offset_table:
686 case X86::reloc_branch_4byte_pcrel:
687 case FK_SecRel_4:
688 case FK_Data_4:
689 return 4;
690 case FK_SecRel_8:
691 case FK_Data_8:
692 return 8;
693 }
694}
695
696constexpr char GotSymName[] = "_GLOBAL_OFFSET_TABLE_";
697
698// Adjust PC-relative fixup offsets, which are calculated from the start of the
699// next instruction.
700std::optional<bool> X86AsmBackend::evaluateFixup(const MCFragment &,
701 MCFixup &Fixup,
702 MCValue &Target, uint64_t &) {
703 if (Fixup.isPCRel()) {
704 switch (Fixup.getKind()) {
705 case FK_Data_1:
706 Target.setConstant(Target.getConstant() - 1);
707 break;
708 case FK_Data_2:
709 Target.setConstant(Target.getConstant() - 2);
710 break;
711 default: {
712 Target.setConstant(Target.getConstant() - 4);
713 auto *Add = Target.getAddSym();
714 // If this is a pc-relative load off _GLOBAL_OFFSET_TABLE_:
715 // leaq _GLOBAL_OFFSET_TABLE_(%rip), %r15
716 // this needs to be a GOTPC32 relocation.
717 if (Add && Add->getName() == GotSymName)
718 Fixup = MCFixup::create(Offset: Fixup.getOffset(), Value: Fixup.getValue(),
719 Kind: X86::reloc_global_offset_table);
720 } break;
721 }
722 }
723 // Use default handling for `Value` and `IsResolved`.
724 return {};
725}
726
727void X86AsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
728 const MCValue &Target, uint8_t *Data,
729 uint64_t Value, bool IsResolved) {
730 // Force relocation when there is a specifier. This might be too conservative
731 // - GAS doesn't emit a relocation for call local@plt; local:.
732 if (Target.getSpecifier())
733 IsResolved = false;
734 maybeAddReloc(F, Fixup, Target, Value, IsResolved);
735
736 auto Kind = Fixup.getKind();
737 if (mc::isRelocation(FixupKind: Kind))
738 return;
739 unsigned Size = getFixupKindSize(Kind);
740
741 assert(Fixup.getOffset() + Size <= F.getSize() && "Invalid fixup offset!");
742
743 // Check fixup value overflow similar to GAS (fixups emitted as RELA
744 // relocations have a value of 0).
745 // - Unknown signedness: the range (-2^N, 2^N) is allowed,
746 // accommodating intN_t, uintN_t, and a non-positive value type.
747 // - Signed (intN_t): the range [-2^(N-1), 2^(N-1)) is allowed.
748 //
749 // Currently only resolved PC-relative fixups are treated as signed. GAS
750 // treats more as signed (e.g. unresolved R_X86_64_32S).
751 // Unresolved fixups have unknown signedness to allow `jmp foo+0xffffffff`.
752 if (Size && Size < 8) {
753 bool Signed = IsResolved && Fixup.isPCRel();
754 uint64_t Mask = ~uint64_t(0) << (Size * 8 - (Signed ? 1 : 0));
755 if ((Value & Mask) && (Signed ? (Value & Mask) != Mask : (-Value & Mask)))
756 getContext().reportError(L: Fixup.getLoc(),
757 Msg: "value of " + Twine(int64_t(Value)) +
758 " is too large for field of " + Twine(Size) +
759 (Size == 1 ? " byte" : " bytes"));
760 }
761
762 for (unsigned i = 0; i != Size; ++i)
763 Data[i] = uint8_t(Value >> (i * 8));
764}
765
766bool X86AsmBackend::mayNeedRelaxation(unsigned Opcode,
767 ArrayRef<MCOperand> Operands,
768 const MCSubtargetInfo &STI) const {
769 unsigned SkipOperands = X86::isCCMPCC(Opcode) ? 2 : 0;
770 return isRelaxableBranch(Opcode) ||
771 (X86::getOpcodeForLongImmediateForm(Opcode) != Opcode &&
772 Operands[Operands.size() - 1 - SkipOperands].isExpr());
773}
774
775bool X86AsmBackend::fixupNeedsRelaxationAdvanced(const MCFragment &F,
776 const MCFixup &Fixup,
777 const MCValue &Target,
778 uint64_t Value,
779 bool Resolved) const {
780 // If resolved, relax if the value is too big for a (signed) i8.
781 //
782 // Currently, `jmp local@plt` relaxes JMP even if the offset is small,
783 // different from gas.
784 if (Resolved) {
785 // finishLayout folds padding into encodings after relaxation, shifting a
786 // branch and its target within their bundles. Keep a bundle of headroom.
787 // Immediates do not shift.
788 int64_t Slack = Asm->isBundlingEnabled() && TargetPrefixMax != 0 &&
789 isRelaxableBranch(Opcode: F.getOpcode())
790 ? Asm->getBundleAlign().value()
791 : 0;
792 return !isInt<8>(x: int64_t(Value) + Slack) ||
793 !isInt<8>(x: int64_t(Value) - Slack) || Target.getSpecifier();
794 }
795
796 // Otherwise, relax unless there is a @ABS8 specifier.
797 if (Fixup.getKind() == FK_Data_1 && Target.getAddSym() &&
798 Target.getSpecifier() == X86::S_ABS8)
799 return false;
800 return true;
801}
802
803// FIXME: Can tblgen help at all here to verify there aren't other instructions
804// we can relax?
805void X86AsmBackend::relaxInstruction(MCInst &Inst,
806 const MCSubtargetInfo &STI) const {
807 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
808 bool Is16BitMode = STI.hasFeature(Feature: X86::Is16Bit);
809 unsigned RelaxedOp = getRelaxedOpcode(MI: Inst, Is16BitMode);
810 assert(RelaxedOp != Inst.getOpcode());
811 Inst.setOpcode(RelaxedOp);
812}
813
814bool X86AsmBackend::padInstructionViaPrefix(MCFragment &RF,
815 MCCodeEmitter &Emitter,
816 unsigned &RemainingSize) const {
817 if (!RF.getAllowAutoPadding())
818 return false;
819 // If the instruction isn't fully relaxed, shifting it around might require a
820 // larger value for one of the fixups then can be encoded. The outer loop
821 // will also catch this before moving to the next instruction, but we need to
822 // prevent padding this single instruction as well.
823 if (mayNeedRelaxation(Opcode: RF.getOpcode(), Operands: RF.getOperands(),
824 STI: *RF.getSubtargetInfo()))
825 return false;
826
827 const unsigned OldSize = RF.getVarSize();
828 if (OldSize == 15)
829 return false;
830
831 const unsigned MaxPossiblePad = std::min(a: 15 - OldSize, b: RemainingSize);
832 const unsigned RemainingPrefixSize = [&]() -> unsigned {
833 SmallString<15> Code;
834 X86_MC::emitPrefix(MCE&: Emitter, MI: RF.getInst(), CB&: Code, STI);
835 assert(Code.size() < 15 && "The number of prefixes must be less than 15.");
836
837 // TODO: It turns out we need a decent amount of plumbing for the target
838 // specific bits to determine number of prefixes its safe to add. Various
839 // targets (older chips mostly, but also Atom family) encounter decoder
840 // stalls with too many prefixes. For testing purposes, we set the value
841 // externally for the moment.
842 unsigned ExistingPrefixSize = Code.size();
843 if (TargetPrefixMax <= ExistingPrefixSize)
844 return 0;
845 return TargetPrefixMax - ExistingPrefixSize;
846 }();
847 const unsigned PrefixBytesToAdd =
848 std::min(a: MaxPossiblePad, b: RemainingPrefixSize);
849 if (PrefixBytesToAdd == 0)
850 return false;
851
852 const uint8_t Prefix = determinePaddingPrefix(Inst: RF.getInst());
853
854 SmallString<256> Code;
855 Code.append(NumInputs: PrefixBytesToAdd, Elt: Prefix);
856 Code.append(in_start: RF.getVarContents().begin(), in_end: RF.getVarContents().end());
857 RF.setVarContents(Code);
858
859 // Adjust the fixups for the change in offsets
860 for (auto &F : RF.getVarFixups())
861 F.setOffset(PrefixBytesToAdd + F.getOffset());
862
863 RemainingSize -= PrefixBytesToAdd;
864 return true;
865}
866
867bool X86AsmBackend::padInstructionViaRelaxation(MCFragment &RF,
868 MCCodeEmitter &Emitter,
869 unsigned &RemainingSize) const {
870 if (!mayNeedRelaxation(Opcode: RF.getOpcode(), Operands: RF.getOperands(),
871 STI: *RF.getSubtargetInfo()))
872 // TODO: There are lots of other tricks we could apply for increasing
873 // encoding size without impacting performance.
874 return false;
875
876 MCInst Relaxed = RF.getInst();
877 relaxInstruction(Inst&: Relaxed, STI: *RF.getSubtargetInfo());
878
879 SmallVector<MCFixup, 4> Fixups;
880 SmallString<15> Code;
881 Emitter.encodeInstruction(Inst: Relaxed, CB&: Code, Fixups, STI: *RF.getSubtargetInfo());
882 const unsigned OldSize = RF.getVarContents().size();
883 const unsigned NewSize = Code.size();
884 assert(NewSize >= OldSize && "size decrease during relaxation?");
885 unsigned Delta = NewSize - OldSize;
886 if (Delta > RemainingSize)
887 return false;
888 RF.setInst(Relaxed);
889 RF.setVarContents(Code);
890 RF.setVarFixups(Fixups);
891 RemainingSize -= Delta;
892 return true;
893}
894
895bool X86AsmBackend::padInstructionEncoding(MCFragment &RF,
896 MCCodeEmitter &Emitter,
897 unsigned &RemainingSize) const {
898 bool Changed = false;
899 if (RemainingSize != 0)
900 Changed |= padInstructionViaRelaxation(RF, Emitter, RemainingSize);
901 if (RemainingSize != 0)
902 Changed |= padInstructionViaPrefix(RF, Emitter, RemainingSize);
903 return Changed;
904}
905
906bool X86AsmBackend::padInstsBackward(SmallVectorImpl<MCFragment *> &Relaxable,
907 unsigned &RemainingSize) const {
908 bool Changed = false;
909 while (!Relaxable.empty() && RemainingSize != 0) {
910 auto &RF = *Relaxable.pop_back_val();
911 // Give the backend a chance to play any tricks it wishes to increase
912 // the encoding size of the given instruction. Target independent code
913 // will try further relaxation, but target's may play further tricks.
914 Changed |= padInstructionEncoding(RF, Emitter&: Asm->getEmitter(), RemainingSize);
915
916 // If we have an instruction which hasn't been fully relaxed, we can't
917 // skip past it and insert bytes before it. Changing its starting
918 // offset might require a larger negative offset than it can encode.
919 // We don't need to worry about larger positive offsets as none of the
920 // possible offsets between this and our align are visible, and the
921 // ones afterwards aren't changing.
922 if (mayNeedRelaxation(Opcode: RF.getOpcode(), Operands: RF.getOperands(),
923 STI: *RF.getSubtargetInfo()))
924 break;
925 }
926 Relaxable.clear();
927 return Changed;
928}
929
930/// Trade the padding held by \p BF for ignored prefixes on the instructions
931/// around it. Padding never leaves its own bundle, so no instruction or
932/// bundle-locked group moves across a boundary. \p Relaxable holds the
933/// preceding instructions in that bundle and is consumed.
934bool X86AsmBackend::foldBundlePad(
935 const MCAssembler &Asm, MCBoundaryAlignFragment &BF,
936 SmallVectorImpl<MCFragment *> &Relaxable) const {
937 const uint64_t BundleSize = Asm.getBundleAlign().value();
938 const uint64_t PadStart = Asm.getFragmentOffset(F: BF);
939 unsigned Remaining = BF.getSize();
940
941 // Only padding in PadStart's own bundle may move backward; an align_to_end
942 // group can push the rest into the next bundle.
943 unsigned Budget =
944 std::min<uint64_t>(a: Remaining, b: BundleSize - PadStart % BundleSize);
945 unsigned Left = Budget;
946 bool Changed = padInstsBackward(Relaxable, RemainingSize&: Left);
947 Remaining -= Budget - Left;
948
949 // Absorbing padding moves the group's start earlier while its end is pinned,
950 // so it may only grow into the slack in its bundle: BundleSize - GroupSize
951 // for align_to_end, zero for a group that already starts on a boundary.
952 if (BF.isAlignToEnd() && Remaining) {
953 uint64_t GroupSize = 0;
954 for (const MCFragment *F = BF.getNext();; F = F->getNext()) {
955 GroupSize += Asm.computeFragmentSize(F: *F);
956 if (F == BF.getLastFragment())
957 break;
958 }
959 if (GroupSize < BundleSize) {
960 Left = Budget = std::min<uint64_t>(a: Remaining, b: BundleSize - GroupSize);
961 for (MCFragment *F = BF.getNext(); F; F = F->getNext()) {
962 if (F->getKind() == MCFragment::FT_Relaxable)
963 Changed |= padInstructionEncoding(RF&: *F, Emitter&: Asm.getEmitter(), RemainingSize&: Left);
964 if (F == BF.getLastFragment() || Left == 0)
965 break;
966 }
967 Remaining -= Budget - Left;
968 }
969 }
970
971 BF.setSize(Remaining);
972 return Changed;
973}
974
975bool X86AsmBackend::optimizeBundleNops(const MCAssembler &Asm) const {
976 const uint64_t BundleSize = Asm.getBundleAlign().value();
977 bool Changed = false;
978 for (MCSection &Sec : Asm) {
979 if (!Sec.isText())
980 continue;
981
982 // Instructions preceding the next padding and sharing its bundle.
983 SmallVector<MCFragment *, 8> Relaxable;
984 // Folding leaves stale offsets until the next layout, so skip the
985 // rewritten range.
986 const MCFragment *ResumeAfter = nullptr;
987 for (MCFragment &F : Sec) {
988 if (ResumeAfter) {
989 if (&F == ResumeAfter)
990 ResumeAfter = nullptr;
991 continue;
992 }
993 uint64_t Offset = Asm.getFragmentOffset(F);
994 if (!Relaxable.empty() &&
995 Asm.getFragmentOffset(F: *Relaxable.front()) / BundleSize !=
996 Offset / BundleSize)
997 Relaxable.clear();
998
999 switch (F.getKind()) {
1000 case MCFragment::FT_BoundaryAlign: {
1001 auto &BF = static_cast<MCBoundaryAlignFragment &>(F);
1002 if (!BF.getSize())
1003 break; // Nothing to fold, and not a barrier.
1004 Changed |= foldBundlePad(Asm, BF, Relaxable);
1005 ResumeAfter = BF.getLastFragment();
1006 break;
1007 }
1008 case MCFragment::FT_Relaxable:
1009 Relaxable.push_back(Elt: &F);
1010 break;
1011 case MCFragment::FT_Data:
1012 break; // Fixed bytes, safe to shift.
1013 default:
1014 // Other kinds may change size when shifted (.p2align, .org, LEBs).
1015 Relaxable.clear();
1016 break;
1017 }
1018 }
1019 }
1020
1021 return Changed;
1022}
1023
1024bool X86AsmBackend::finishLayout() const {
1025 // With bundling, padding is fully determined during layout and the only
1026 // post-layout optimization is prefix padding.
1027 if (Asm->isBundlingEnabled())
1028 return TargetPrefixMax != 0 && optimizeBundleNops(Asm: *Asm);
1029 // See if we can further relax some instructions to cut down on the number of
1030 // nop bytes required for code alignment. The actual win is in reducing
1031 // instruction count, not number of bytes. Modern X86-64 can easily end up
1032 // decode limited. It is often better to reduce the number of instructions
1033 // (i.e. eliminate nops) even at the cost of increasing the size and
1034 // complexity of others.
1035 if (!CLOpts.pad_for_align && !CLOpts.pad_for_branch_align)
1036 return false;
1037
1038 // The processed regions are delimitered by LabeledFragments. -g may have more
1039 // MCSymbols and therefore different relaxation results. -x86-pad-for-align is
1040 // disabled by default to eliminate the -g vs non -g difference.
1041 DenseSet<MCFragment *> LabeledFragments;
1042 for (const MCSymbol &S : Asm->symbols())
1043 LabeledFragments.insert(V: S.getFragment());
1044
1045 bool Changed = false;
1046 for (MCSection &Sec : *Asm) {
1047 if (!Sec.isText())
1048 continue;
1049
1050 SmallVector<MCFragment *, 4> Relaxable;
1051 for (MCSection::iterator I = Sec.begin(), IE = Sec.end(); I != IE; ++I) {
1052 MCFragment &F = *I;
1053
1054 if (LabeledFragments.count(V: &F))
1055 Relaxable.clear();
1056
1057 if (F.getKind() == MCFragment::FT_Data) // Skip and ignore
1058 continue;
1059
1060 if (F.getKind() == MCFragment::FT_Relaxable) {
1061 auto &RF = cast<MCFragment>(Val&: *I);
1062 Relaxable.push_back(Elt: &RF);
1063 continue;
1064 }
1065
1066 auto canHandle = [&](MCFragment &F) -> bool {
1067 switch (F.getKind()) {
1068 default:
1069 return false;
1070 case MCFragment::FT_Align:
1071 return CLOpts.pad_for_align;
1072 case MCFragment::FT_BoundaryAlign:
1073 return CLOpts.pad_for_branch_align;
1074 }
1075 };
1076 // For any unhandled kind, assume we can't change layout.
1077 if (!canHandle(F)) {
1078 Relaxable.clear();
1079 continue;
1080 }
1081
1082 // To keep the effects local, prefer to relax instructions closest to
1083 // the align directive. This is purely about human understandability
1084 // of the resulting code. If we later find a reason to expand
1085 // particular instructions over others, we can adjust.
1086 unsigned RemainingSize = Asm->computeFragmentSize(F) - F.getFixedSize();
1087 Changed |= padInstsBackward(Relaxable, RemainingSize);
1088
1089 // If we're looking at a boundary align, make sure we don't try to pad
1090 // its target instructions for some following directive. Doing so would
1091 // break the alignment of the current boundary align.
1092 if (auto *BF = dyn_cast<MCBoundaryAlignFragment>(Val: &F)) {
1093 cast<MCBoundaryAlignFragment>(Val&: F).setSize(RemainingSize);
1094 Changed = true;
1095 const MCFragment *LastFragment = BF->getLastFragment();
1096 if (!LastFragment)
1097 continue;
1098 while (&*I != LastFragment)
1099 ++I;
1100 }
1101 }
1102 }
1103
1104 return Changed;
1105}
1106
1107unsigned X86AsmBackend::getMaximumNopSize(const MCSubtargetInfo &STI) const {
1108 if (STI.hasFeature(Feature: X86::Is16Bit))
1109 return 4;
1110 if (!STI.hasFeature(Feature: X86::FeatureNOPL) && !STI.hasFeature(Feature: X86::Is64Bit))
1111 return 1;
1112 if (STI.hasFeature(Feature: X86::TuningFast7ByteNOP))
1113 return 7;
1114 if (STI.hasFeature(Feature: X86::TuningFast15ByteNOP))
1115 return 15;
1116 if (STI.hasFeature(Feature: X86::TuningFast11ByteNOP))
1117 return 11;
1118 // FIXME: handle 32-bit mode
1119 // 15-bytes is the longest single NOP instruction, but 10-bytes is
1120 // commonly the longest that can be efficiently decoded.
1121 return 10;
1122}
1123
1124/// Write a sequence of optimal nops to the output, covering \p Count
1125/// bytes.
1126/// \return - true on success, false on failure
1127bool X86AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
1128 const MCSubtargetInfo *STI) const {
1129 static const char Nops32Bit[10][11] = {
1130 // nop
1131 "\x90",
1132 // xchg %ax,%ax
1133 "\x66\x90",
1134 // nopl (%[re]ax)
1135 "\x0f\x1f\x00",
1136 // nopl 0(%[re]ax)
1137 "\x0f\x1f\x40\x00",
1138 // nopl 0(%[re]ax,%[re]ax,1)
1139 "\x0f\x1f\x44\x00\x00",
1140 // nopw 0(%[re]ax,%[re]ax,1)
1141 "\x66\x0f\x1f\x44\x00\x00",
1142 // nopl 0L(%[re]ax)
1143 "\x0f\x1f\x80\x00\x00\x00\x00",
1144 // nopl 0L(%[re]ax,%[re]ax,1)
1145 "\x0f\x1f\x84\x00\x00\x00\x00\x00",
1146 // nopw 0L(%[re]ax,%[re]ax,1)
1147 "\x66\x0f\x1f\x84\x00\x00\x00\x00\x00",
1148 // nopw %cs:0L(%[re]ax,%[re]ax,1)
1149 "\x66\x2e\x0f\x1f\x84\x00\x00\x00\x00\x00",
1150 };
1151
1152 // 16-bit mode uses different nop patterns than 32-bit.
1153 static const char Nops16Bit[4][11] = {
1154 // nop
1155 "\x90",
1156 // xchg %eax,%eax
1157 "\x66\x90",
1158 // lea 0(%si),%si
1159 "\x8d\x74\x00",
1160 // lea 0w(%si),%si
1161 "\x8d\xb4\x00\x00",
1162 };
1163
1164 const char(*Nops)[11] =
1165 STI->hasFeature(Feature: X86::Is16Bit) ? Nops16Bit : Nops32Bit;
1166
1167 uint64_t MaxNopLength = (uint64_t)getMaximumNopSize(STI: *STI);
1168
1169 // Emit as many MaxNopLength NOPs as needed, then emit a NOP of the remaining
1170 // length.
1171 do {
1172 const uint8_t ThisNopLength = (uint8_t) std::min(a: Count, b: MaxNopLength);
1173 const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
1174 for (uint8_t i = 0; i < Prefixes; i++)
1175 OS << '\x66';
1176 const uint8_t Rest = ThisNopLength - Prefixes;
1177 if (Rest != 0)
1178 OS.write(Ptr: Nops[Rest - 1], Size: Rest);
1179 Count -= ThisNopLength;
1180 } while (Count != 0);
1181
1182 return true;
1183}
1184
1185/* *** */
1186
1187namespace {
1188
1189class ELFX86AsmBackend : public X86AsmBackend {
1190public:
1191 uint8_t OSABI;
1192 ELFX86AsmBackend(const X86MCOptions &CLOpts, const Target &T, uint8_t OSABI,
1193 const MCSubtargetInfo &STI)
1194 : X86AsmBackend(CLOpts, T, STI), OSABI(OSABI) {}
1195};
1196
1197class ELFX86_32AsmBackend : public ELFX86AsmBackend {
1198public:
1199 using ELFX86AsmBackend::ELFX86AsmBackend;
1200
1201 std::unique_ptr<MCObjectTargetWriter>
1202 createObjectTargetWriter() const override {
1203 return createX86ELFObjectWriter(/*IsELF64*/ false, OSABI, EMachine: ELF::EM_386);
1204 }
1205};
1206
1207class ELFX86_X32AsmBackend : public ELFX86AsmBackend {
1208public:
1209 using ELFX86AsmBackend::ELFX86AsmBackend;
1210
1211 std::unique_ptr<MCObjectTargetWriter>
1212 createObjectTargetWriter() const override {
1213 return createX86ELFObjectWriter(/*IsELF64*/ false, OSABI,
1214 EMachine: ELF::EM_X86_64);
1215 }
1216};
1217
1218class ELFX86_IAMCUAsmBackend : public ELFX86AsmBackend {
1219public:
1220 using ELFX86AsmBackend::ELFX86AsmBackend;
1221
1222 std::unique_ptr<MCObjectTargetWriter>
1223 createObjectTargetWriter() const override {
1224 return createX86ELFObjectWriter(/*IsELF64*/ false, OSABI,
1225 EMachine: ELF::EM_IAMCU);
1226 }
1227};
1228
1229class ELFX86_64AsmBackend : public ELFX86AsmBackend {
1230public:
1231 using ELFX86AsmBackend::ELFX86AsmBackend;
1232
1233 std::unique_ptr<MCObjectTargetWriter>
1234 createObjectTargetWriter() const override {
1235 return createX86ELFObjectWriter(/*IsELF64*/ true, OSABI, EMachine: ELF::EM_X86_64);
1236 }
1237};
1238
1239class WindowsX86AsmBackend : public X86AsmBackend {
1240 bool Is64Bit;
1241
1242public:
1243 WindowsX86AsmBackend(const X86MCOptions &CLOpts, const Target &T,
1244 bool is64Bit, const MCSubtargetInfo &STI)
1245 : X86AsmBackend(CLOpts, T, STI), Is64Bit(is64Bit) {}
1246
1247 std::optional<MCFixupKind> getFixupKind(StringRef Name) const override {
1248 return StringSwitch<std::optional<MCFixupKind>>(Name)
1249 .Case(S: "dir32", Value: FK_Data_4)
1250 .Case(S: "secrel32", Value: FK_SecRel_4)
1251 .Case(S: "secidx", Value: FK_SecRel_2)
1252 .Default(Value: MCAsmBackend::getFixupKind(Name));
1253 }
1254
1255 std::unique_ptr<MCObjectTargetWriter>
1256 createObjectTargetWriter() const override {
1257 return createX86WinCOFFObjectWriter(Is64Bit);
1258 }
1259};
1260
1261namespace CU {
1262
1263 /// Compact unwind encoding values.
1264 enum CompactUnwindEncodings {
1265 /// [RE]BP based frame where [RE]BP is pused on the stack immediately after
1266 /// the return address, then [RE]SP is moved to [RE]BP.
1267 UNWIND_MODE_BP_FRAME = 0x01000000,
1268
1269 /// A frameless function with a small constant stack size.
1270 UNWIND_MODE_STACK_IMMD = 0x02000000,
1271
1272 /// A frameless function with a large constant stack size.
1273 UNWIND_MODE_STACK_IND = 0x03000000,
1274
1275 /// No compact unwind encoding is available.
1276 UNWIND_MODE_DWARF = 0x04000000,
1277
1278 /// Mask for encoding the frame registers.
1279 UNWIND_BP_FRAME_REGISTERS = 0x00007FFF,
1280
1281 /// Mask for encoding the frameless registers.
1282 UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF
1283 };
1284
1285} // namespace CU
1286
1287class DarwinX86AsmBackend : public X86AsmBackend {
1288 const MCRegisterInfo &MRI;
1289
1290 /// Number of registers that can be saved in a compact unwind encoding.
1291 enum { CU_NUM_SAVED_REGS = 6 };
1292
1293 mutable unsigned SavedRegs[CU_NUM_SAVED_REGS];
1294 Triple TT;
1295 bool Is64Bit;
1296
1297 unsigned OffsetSize; ///< Offset of a "push" instruction.
1298 unsigned MoveInstrSize; ///< Size of a "move" instruction.
1299 unsigned StackDivide; ///< Amount to adjust stack size by.
1300protected:
1301 /// Size of a "push" instruction for the given register.
1302 unsigned PushInstrSize(MCRegister Reg) const {
1303 switch (Reg.id()) {
1304 case X86::EBX:
1305 case X86::ECX:
1306 case X86::EDX:
1307 case X86::EDI:
1308 case X86::ESI:
1309 case X86::EBP:
1310 case X86::RBX:
1311 case X86::RBP:
1312 return 1;
1313 case X86::R12:
1314 case X86::R13:
1315 case X86::R14:
1316 case X86::R15:
1317 return 2;
1318 }
1319 return 1;
1320 }
1321
1322private:
1323 /// Get the compact unwind number for a given register. The number
1324 /// corresponds to the enum lists in compact_unwind_encoding.h.
1325 int getCompactUnwindRegNum(unsigned Reg) const {
1326 static const MCPhysReg CU32BitRegs[7] = {
1327 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
1328 };
1329 static const MCPhysReg CU64BitRegs[] = {
1330 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
1331 };
1332 const MCPhysReg *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
1333 for (int Idx = 1; *CURegs; ++CURegs, ++Idx)
1334 if (*CURegs == Reg)
1335 return Idx;
1336
1337 return -1;
1338 }
1339
1340 /// Return the registers encoded for a compact encoding with a frame
1341 /// pointer.
1342 uint32_t encodeCompactUnwindRegistersWithFrame() const {
1343 // Encode the registers in the order they were saved --- 3-bits per
1344 // register. The list of saved registers is assumed to be in reverse
1345 // order. The registers are numbered from 1 to CU_NUM_SAVED_REGS.
1346 uint32_t RegEnc = 0;
1347 for (int i = 0, Idx = 0; i != CU_NUM_SAVED_REGS; ++i) {
1348 unsigned Reg = SavedRegs[i];
1349 if (Reg == 0) break;
1350
1351 int CURegNum = getCompactUnwindRegNum(Reg);
1352 if (CURegNum == -1) return ~0U;
1353
1354 // Encode the 3-bit register number in order, skipping over 3-bits for
1355 // each register.
1356 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3);
1357 }
1358
1359 assert((RegEnc & 0x3FFFF) == RegEnc &&
1360 "Invalid compact register encoding!");
1361 return RegEnc;
1362 }
1363
1364 /// Create the permutation encoding used with frameless stacks. It is
1365 /// passed the number of registers to be saved and an array of the registers
1366 /// saved.
1367 uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned RegCount) const {
1368 // The saved registers are numbered from 1 to 6. In order to encode the
1369 // order in which they were saved, we re-number them according to their
1370 // place in the register order. The re-numbering is relative to the last
1371 // re-numbered register. E.g., if we have registers {6, 2, 4, 5} saved in
1372 // that order:
1373 //
1374 // Orig Re-Num
1375 // ---- ------
1376 // 6 6
1377 // 2 2
1378 // 4 3
1379 // 5 3
1380 //
1381 for (unsigned i = 0; i < RegCount; ++i) {
1382 int CUReg = getCompactUnwindRegNum(Reg: SavedRegs[i]);
1383 if (CUReg == -1) return ~0U;
1384 SavedRegs[i] = CUReg;
1385 }
1386
1387 // Reverse the list.
1388 std::reverse(first: &SavedRegs[0], last: &SavedRegs[CU_NUM_SAVED_REGS]);
1389
1390 uint32_t RenumRegs[CU_NUM_SAVED_REGS];
1391 for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){
1392 unsigned Countless = 0;
1393 for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j)
1394 if (SavedRegs[j] < SavedRegs[i])
1395 ++Countless;
1396
1397 RenumRegs[i] = SavedRegs[i] - Countless - 1;
1398 }
1399
1400 // Take the renumbered values and encode them into a 10-bit number.
1401 uint32_t permutationEncoding = 0;
1402 switch (RegCount) {
1403 case 6:
1404 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
1405 + 6 * RenumRegs[2] + 2 * RenumRegs[3]
1406 + RenumRegs[4];
1407 break;
1408 case 5:
1409 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
1410 + 6 * RenumRegs[3] + 2 * RenumRegs[4]
1411 + RenumRegs[5];
1412 break;
1413 case 4:
1414 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
1415 + 3 * RenumRegs[4] + RenumRegs[5];
1416 break;
1417 case 3:
1418 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
1419 + RenumRegs[5];
1420 break;
1421 case 2:
1422 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
1423 break;
1424 case 1:
1425 permutationEncoding |= RenumRegs[5];
1426 break;
1427 }
1428
1429 assert((permutationEncoding & 0x3FF) == permutationEncoding &&
1430 "Invalid compact register encoding!");
1431 return permutationEncoding;
1432 }
1433
1434public:
1435 DarwinX86AsmBackend(const X86MCOptions &CLOpts, const Target &T,
1436 const MCRegisterInfo &MRI, const MCSubtargetInfo &STI)
1437 : X86AsmBackend(CLOpts, T, STI), MRI(MRI), TT(STI.getTargetTriple()),
1438 Is64Bit(TT.isX86_64()) {
1439 memset(s: SavedRegs, c: 0, n: sizeof(SavedRegs));
1440 OffsetSize = Is64Bit ? 8 : 4;
1441 MoveInstrSize = Is64Bit ? 3 : 2;
1442 StackDivide = Is64Bit ? 8 : 4;
1443 }
1444
1445 std::unique_ptr<MCObjectTargetWriter>
1446 createObjectTargetWriter() const override {
1447 uint32_t CPUType = cantFail(ValOrErr: MachO::getCPUType(T: TT));
1448 uint32_t CPUSubType = cantFail(ValOrErr: MachO::getCPUSubType(T: TT));
1449 return createX86MachObjectWriter(Is64Bit, CPUType, CPUSubtype: CPUSubType);
1450 }
1451
1452 /// Implementation of algorithm to generate the compact unwind encoding
1453 /// for the CFI instructions.
1454 uint64_t generateCompactUnwindEncoding(const MCDwarfFrameInfo *FI,
1455 const MCContext *Ctxt) const override {
1456 if (Ctxt->emitDwarfUnwindInfo() == EmitDwarfUnwindType::DwarfOnly)
1457 return CU::UNWIND_MODE_DWARF;
1458
1459 // Signal frames cannot be encoded in compact unwind.
1460 if (FI->IsSignalFrame)
1461 return CU::UNWIND_MODE_DWARF;
1462
1463 ArrayRef<MCCFIInstruction> Instrs = FI->Instructions;
1464 if (Instrs.empty()) return 0;
1465 if (!isDarwinCanonicalPersonality(Sym: FI->Personality) &&
1466 !Ctxt->emitCompactUnwindNonCanonical())
1467 return CU::UNWIND_MODE_DWARF;
1468
1469 // Reset the saved registers.
1470 unsigned SavedRegIdx = 0;
1471 memset(s: SavedRegs, c: 0, n: sizeof(SavedRegs));
1472
1473 bool HasFP = false;
1474
1475 // Encode that we are using EBP/RBP as the frame pointer.
1476 uint64_t CompactUnwindEncoding = 0;
1477
1478 unsigned SubtractInstrIdx = Is64Bit ? 3 : 2;
1479 unsigned InstrOffset = 0;
1480 unsigned StackAdjust = 0;
1481 uint64_t StackSize = 0;
1482 int64_t MinAbsOffset = std::numeric_limits<int64_t>::max();
1483
1484 for (const MCCFIInstruction &Inst : Instrs) {
1485 switch (Inst.getOperation()) {
1486 default:
1487 // Any other CFI directives indicate a frame that we aren't prepared
1488 // to represent via compact unwind, so just bail out.
1489 return CU::UNWIND_MODE_DWARF;
1490 case MCCFIInstruction::OpDefCfaRegister: {
1491 // Defines a frame pointer. E.g.
1492 //
1493 // movq %rsp, %rbp
1494 // L0:
1495 // .cfi_def_cfa_register %rbp
1496 //
1497 HasFP = true;
1498
1499 // If the frame pointer is other than esp/rsp, we do not have a way to
1500 // generate a compact unwinding representation, so bail out.
1501 if (*MRI.getLLVMRegNum(RegNum: Inst.getRegister(), isEH: true) !=
1502 (Is64Bit ? X86::RBP : X86::EBP))
1503 return CU::UNWIND_MODE_DWARF;
1504
1505 // Reset the counts.
1506 memset(s: SavedRegs, c: 0, n: sizeof(SavedRegs));
1507 StackAdjust = 0;
1508 SavedRegIdx = 0;
1509 MinAbsOffset = std::numeric_limits<int64_t>::max();
1510 InstrOffset += MoveInstrSize;
1511 break;
1512 }
1513 case MCCFIInstruction::OpDefCfaOffset: {
1514 // Defines a new offset for the CFA. E.g.
1515 //
1516 // With frame:
1517 //
1518 // pushq %rbp
1519 // L0:
1520 // .cfi_def_cfa_offset 16
1521 //
1522 // Without frame:
1523 //
1524 // subq $72, %rsp
1525 // L0:
1526 // .cfi_def_cfa_offset 80
1527 //
1528 StackSize = Inst.getOffset() / StackDivide;
1529 break;
1530 }
1531 case MCCFIInstruction::OpOffset: {
1532 // Defines a "push" of a callee-saved register. E.g.
1533 //
1534 // pushq %r15
1535 // pushq %r14
1536 // pushq %rbx
1537 // L0:
1538 // subq $120, %rsp
1539 // L1:
1540 // .cfi_offset %rbx, -40
1541 // .cfi_offset %r14, -32
1542 // .cfi_offset %r15, -24
1543 //
1544 if (SavedRegIdx == CU_NUM_SAVED_REGS)
1545 // If there are too many saved registers, we cannot use a compact
1546 // unwind encoding.
1547 return CU::UNWIND_MODE_DWARF;
1548
1549 MCRegister Reg = *MRI.getLLVMRegNum(RegNum: Inst.getRegister(), isEH: true);
1550 SavedRegs[SavedRegIdx++] = Reg.id();
1551 StackAdjust += OffsetSize;
1552 MinAbsOffset = std::min(a: MinAbsOffset, b: std::abs(i: Inst.getOffset()));
1553 InstrOffset += PushInstrSize(Reg);
1554 break;
1555 }
1556 }
1557 }
1558
1559 StackAdjust /= StackDivide;
1560
1561 if (HasFP) {
1562 if ((StackAdjust & 0xFF) != StackAdjust)
1563 // Offset was too big for a compact unwind encoding.
1564 return CU::UNWIND_MODE_DWARF;
1565
1566 // We don't attempt to track a real StackAdjust, so if the saved registers
1567 // aren't adjacent to rbp we can't cope.
1568 if (SavedRegIdx != 0 && MinAbsOffset != 3 * (int)OffsetSize)
1569 return CU::UNWIND_MODE_DWARF;
1570
1571 // Get the encoding of the saved registers when we have a frame pointer.
1572 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame();
1573 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
1574
1575 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
1576 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
1577 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
1578 } else {
1579 SubtractInstrIdx += InstrOffset;
1580 ++StackAdjust;
1581
1582 if ((StackSize & 0xFF) == StackSize) {
1583 // Frameless stack with a small stack size.
1584 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
1585
1586 // Encode the stack size.
1587 CompactUnwindEncoding |= (StackSize & 0xFF) << 16;
1588 } else {
1589 if ((StackAdjust & 0x7) != StackAdjust)
1590 // The extra stack adjustments are too big for us to handle.
1591 return CU::UNWIND_MODE_DWARF;
1592
1593 // Frameless stack with an offset too large for us to encode compactly.
1594 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
1595
1596 // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP'
1597 // instruction.
1598 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
1599
1600 // Encode any extra stack adjustments (done via push instructions).
1601 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
1602 }
1603
1604 // Encode the number of registers saved. (Reverse the list first.)
1605 std::reverse(first: &SavedRegs[0], last: &SavedRegs[SavedRegIdx]);
1606 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
1607
1608 // Get the encoding of the saved registers when we don't have a frame
1609 // pointer.
1610 uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(RegCount: SavedRegIdx);
1611 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
1612
1613 // Encode the register encoding.
1614 CompactUnwindEncoding |=
1615 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
1616 }
1617
1618 return CompactUnwindEncoding;
1619 }
1620};
1621
1622} // end anonymous namespace
1623
1624MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
1625 const MCSubtargetInfo &STI,
1626 const MCRegisterInfo &MRI,
1627 const MCTargetOptions &Options) {
1628 const Triple &TheTriple = STI.getTargetTriple();
1629 const X86MCOptions &CLOpts = X86_MC::getCLOpts(Options);
1630 if (TheTriple.isOSBinFormatMachO())
1631 return new DarwinX86AsmBackend(CLOpts, T, MRI, STI);
1632
1633 if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF())
1634 return new WindowsX86AsmBackend(CLOpts, T, false, STI);
1635
1636 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType: TheTriple.getOS());
1637
1638 if (TheTriple.isOSIAMCU())
1639 return new ELFX86_IAMCUAsmBackend(CLOpts, T, OSABI, STI);
1640
1641 return new ELFX86_32AsmBackend(CLOpts, T, OSABI, STI);
1642}
1643
1644MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
1645 const MCSubtargetInfo &STI,
1646 const MCRegisterInfo &MRI,
1647 const MCTargetOptions &Options) {
1648 const Triple &TheTriple = STI.getTargetTriple();
1649 const X86MCOptions &CLOpts = X86_MC::getCLOpts(Options);
1650 if (TheTriple.isOSBinFormatMachO())
1651 return new DarwinX86AsmBackend(CLOpts, T, MRI, STI);
1652
1653 if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF())
1654 return new WindowsX86AsmBackend(CLOpts, T, true, STI);
1655
1656 if (TheTriple.isUEFI()) {
1657 assert(TheTriple.isOSBinFormatCOFF() &&
1658 "Only COFF format is supported in UEFI environment.");
1659 return new WindowsX86AsmBackend(CLOpts, T, true, STI);
1660 }
1661
1662 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType: TheTriple.getOS());
1663
1664 if (TheTriple.isX32())
1665 return new ELFX86_X32AsmBackend(CLOpts, T, OSABI, STI);
1666 return new ELFX86_64AsmBackend(CLOpts, T, OSABI, STI);
1667}
1668
1669namespace {
1670class X86ELFStreamer : public MCELFStreamer {
1671public:
1672 X86ELFStreamer(MCContext &Context, std::unique_ptr<MCAsmBackend> TAB,
1673 std::unique_ptr<MCObjectWriter> OW,
1674 std::unique_ptr<MCCodeEmitter> Emitter)
1675 : MCELFStreamer(Context, std::move(TAB), std::move(OW),
1676 std::move(Emitter)) {}
1677
1678 void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override;
1679};
1680} // end anonymous namespace
1681
1682void X86ELFStreamer::emitInstruction(const MCInst &Inst,
1683 const MCSubtargetInfo &STI) {
1684 X86_MC::emitInstruction(S&: *this, Inst, STI);
1685}
1686
1687MCStreamer *llvm::createX86ELFStreamer(const Triple &T, MCContext &Context,
1688 std::unique_ptr<MCAsmBackend> &&MAB,
1689 std::unique_ptr<MCObjectWriter> &&MOW,
1690 std::unique_ptr<MCCodeEmitter> &&MCE) {
1691 return new X86ELFStreamer(Context, std::move(MAB), std::move(MOW),
1692 std::move(MCE));
1693}
1694