1//===- SPIR.cpp -----------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "ABIInfoImpl.h"
10#include "HLSLBufferLayoutBuilder.h"
11#include "TargetInfo.h"
12
13using namespace clang;
14using namespace clang::CodeGen;
15
16//===----------------------------------------------------------------------===//
17// Base ABI and target codegen info implementation common between SPIR and
18// SPIR-V.
19//===----------------------------------------------------------------------===//
20
21namespace {
22class CommonSPIRABIInfo : public DefaultABIInfo {
23public:
24 CommonSPIRABIInfo(CodeGenTypes &CGT) : DefaultABIInfo(CGT) { setCCs(); }
25
26private:
27 void setCCs();
28};
29
30class SPIRVABIInfo : public CommonSPIRABIInfo {
31public:
32 SPIRVABIInfo(CodeGenTypes &CGT) : CommonSPIRABIInfo(CGT) {}
33 void computeInfo(CGFunctionInfo &FI) const override;
34
35private:
36 ABIArgInfo classifyReturnType(QualType RetTy) const;
37 ABIArgInfo classifyKernelArgumentType(QualType Ty) const;
38 ABIArgInfo classifyArgumentType(QualType Ty) const;
39};
40} // end anonymous namespace
41namespace {
42class CommonSPIRTargetCodeGenInfo : public TargetCodeGenInfo {
43public:
44 CommonSPIRTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
45 : TargetCodeGenInfo(std::make_unique<CommonSPIRABIInfo>(args&: CGT)) {}
46 CommonSPIRTargetCodeGenInfo(std::unique_ptr<ABIInfo> ABIInfo)
47 : TargetCodeGenInfo(std::move(ABIInfo)) {}
48
49 LangAS getASTAllocaAddressSpace() const override {
50 return getLangASFromTargetAS(
51 TargetAS: getABIInfo().getDataLayout().getAllocaAddrSpace());
52 }
53
54 unsigned getDeviceKernelCallingConv() const override;
55 llvm::Type *getOpenCLType(CodeGenModule &CGM, const Type *T) const override;
56 llvm::Type *
57 getHLSLType(CodeGenModule &CGM, const Type *Ty,
58 const SmallVector<int32_t> *Packoffsets = nullptr) const override;
59 llvm::Type *getSPIRVImageTypeFromHLSLResource(
60 const HLSLAttributedResourceType::Attributes &attributes,
61 QualType SampledType, CodeGenModule &CGM) const;
62 void
63 setOCLKernelStubCallingConvention(const FunctionType *&FT) const override;
64};
65class SPIRVTargetCodeGenInfo : public CommonSPIRTargetCodeGenInfo {
66public:
67 SPIRVTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
68 : CommonSPIRTargetCodeGenInfo(std::make_unique<SPIRVABIInfo>(args&: CGT)) {}
69 void setCUDAKernelCallingConvention(const FunctionType *&FT) const override;
70 LangAS getGlobalVarAddressSpace(CodeGenModule &CGM,
71 const VarDecl *D) const override;
72 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
73 CodeGen::CodeGenModule &M) const override;
74 llvm::SyncScope::ID getLLVMSyncScopeID(const LangOptions &LangOpts,
75 SyncScope Scope,
76 llvm::AtomicOrdering Ordering,
77 llvm::LLVMContext &Ctx) const override;
78 bool supportsLibCall() const override {
79 return getABIInfo().getTarget().getTriple().getVendor() !=
80 llvm::Triple::AMD;
81 }
82};
83
84inline StringRef mapClangSyncScopeToLLVM(SyncScope Scope) {
85 switch (Scope) {
86 case SyncScope::HIPSingleThread:
87 case SyncScope::SingleScope:
88 return "singlethread";
89 case SyncScope::HIPWavefront:
90 case SyncScope::OpenCLSubGroup:
91 case SyncScope::WavefrontScope:
92 return "subgroup";
93 case SyncScope::HIPWorkgroup:
94 case SyncScope::OpenCLWorkGroup:
95 case SyncScope::WorkgroupScope:
96 return "workgroup";
97 case SyncScope::HIPAgent:
98 case SyncScope::OpenCLDevice:
99 case SyncScope::DeviceScope:
100 return "device";
101 case SyncScope::SystemScope:
102 case SyncScope::HIPSystem:
103 case SyncScope::OpenCLAllSVMDevices:
104 return "";
105 }
106 return "";
107}
108} // End anonymous namespace.
109
110void CommonSPIRABIInfo::setCCs() {
111 assert(getRuntimeCC() == llvm::CallingConv::C);
112 RuntimeCC = llvm::CallingConv::SPIR_FUNC;
113}
114
115ABIArgInfo SPIRVABIInfo::classifyReturnType(QualType RetTy) const {
116 if (getTarget().getTriple().getVendor() != llvm::Triple::AMD)
117 return DefaultABIInfo::classifyReturnType(RetTy);
118 if (!isAggregateTypeForABI(T: RetTy) || getRecordArgABI(T: RetTy, CXXABI&: getCXXABI()))
119 return DefaultABIInfo::classifyReturnType(RetTy);
120
121 if (const RecordType *RT = RetTy->getAs<RecordType>()) {
122 const RecordDecl *RD = RT->getDecl();
123 if (RD->hasFlexibleArrayMember())
124 return DefaultABIInfo::classifyReturnType(RetTy);
125 }
126
127 // TODO: The AMDGPU ABI is non-trivial to represent in SPIR-V; in order to
128 // avoid encoding various architecture specific bits here we return everything
129 // as direct to retain type info for things like aggregates, for later perusal
130 // when translating back to LLVM/lowering in the BE. This is also why we
131 // disable flattening as the outcomes can mismatch between SPIR-V and AMDGPU.
132 // This will be revisited / optimised in the future.
133 return ABIArgInfo::getDirect(T: CGT.ConvertType(T: RetTy), Offset: 0u, Padding: nullptr, CanBeFlattened: false);
134}
135
136ABIArgInfo SPIRVABIInfo::classifyKernelArgumentType(QualType Ty) const {
137 if (getContext().getLangOpts().CUDAIsDevice) {
138 // Coerce pointer arguments with default address space to CrossWorkGroup
139 // pointers for HIPSPV/CUDASPV. When the language mode is HIP/CUDA, the
140 // SPIRTargetInfo maps cuda_device to SPIR-V's CrossWorkGroup address space.
141 llvm::Type *LTy = CGT.ConvertType(T: Ty);
142 auto DefaultAS = getContext().getTargetAddressSpace(AS: LangAS::Default);
143 auto GlobalAS = getContext().getTargetAddressSpace(AS: LangAS::cuda_device);
144 auto *PtrTy = llvm::dyn_cast<llvm::PointerType>(Val: LTy);
145 if (PtrTy && PtrTy->getAddressSpace() == DefaultAS) {
146 LTy = llvm::PointerType::get(C&: PtrTy->getContext(), AddressSpace: GlobalAS);
147 return ABIArgInfo::getDirect(T: LTy, Offset: 0, Padding: nullptr, CanBeFlattened: false);
148 }
149
150 if (isAggregateTypeForABI(T: Ty)) {
151 if (getTarget().getTriple().getVendor() == llvm::Triple::AMD)
152 // TODO: The AMDGPU kernel ABI passes aggregates byref, which is not
153 // currently expressible in SPIR-V; SPIR-V passes aggregates byval,
154 // which the AMDGPU kernel ABI does not allow. Passing aggregates as
155 // direct works around this impedance mismatch, as it retains type info
156 // and can be correctly handled, post reverse-translation, by the AMDGPU
157 // BE, which has to support this CC for legacy OpenCL purposes. It can
158 // be brittle and does lead to performance degradation in certain
159 // pathological cases. This will be revisited / optimised in the future,
160 // once a way to deal with the byref/byval impedance mismatch is
161 // identified.
162 return ABIArgInfo::getDirect(T: LTy, Offset: 0, Padding: nullptr, CanBeFlattened: false);
163 // Force copying aggregate type in kernel arguments by value when
164 // compiling CUDA targeting SPIR-V. This is required for the object
165 // copied to be valid on the device.
166 // This behavior follows the CUDA spec
167 // https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#global-function-argument-processing,
168 // and matches the NVPTX implementation. TODO: hardcoding to 0 should be
169 // revisited if HIPSPV / byval starts making use of the AS of an indirect
170 // arg.
171 return getNaturalAlignIndirect(Ty, /*AddrSpace=*/0, /*byval=*/ByVal: true);
172 }
173 }
174 return classifyArgumentType(Ty);
175}
176
177ABIArgInfo SPIRVABIInfo::classifyArgumentType(QualType Ty) const {
178 if (getTarget().getTriple().getVendor() != llvm::Triple::AMD)
179 return DefaultABIInfo::classifyArgumentType(RetTy: Ty);
180 if (!isAggregateTypeForABI(T: Ty))
181 return DefaultABIInfo::classifyArgumentType(RetTy: Ty);
182
183 // Records with non-trivial destructors/copy-constructors should not be
184 // passed by value.
185 if (auto RAA = getRecordArgABI(T: Ty, CXXABI&: getCXXABI()))
186 return getNaturalAlignIndirect(Ty, AddrSpace: getDataLayout().getAllocaAddrSpace(),
187 ByVal: RAA == CGCXXABI::RAA_DirectInMemory);
188
189 if (const RecordType *RT = Ty->getAs<RecordType>()) {
190 const RecordDecl *RD = RT->getDecl();
191 if (RD->hasFlexibleArrayMember())
192 return DefaultABIInfo::classifyArgumentType(RetTy: Ty);
193 }
194
195 return ABIArgInfo::getDirect(T: CGT.ConvertType(T: Ty), Offset: 0u, Padding: nullptr, CanBeFlattened: false);
196}
197
198void SPIRVABIInfo::computeInfo(CGFunctionInfo &FI) const {
199 // The logic is same as in DefaultABIInfo with an exception on the kernel
200 // arguments handling.
201 llvm::CallingConv::ID CC = FI.getCallingConvention();
202
203 if (!getCXXABI().classifyReturnType(FI))
204 FI.getReturnInfo() = classifyReturnType(RetTy: FI.getReturnType());
205
206 for (auto &I : FI.arguments()) {
207 if (CC == llvm::CallingConv::SPIR_KERNEL) {
208 I.info = classifyKernelArgumentType(Ty: I.type);
209 } else {
210 I.info = classifyArgumentType(Ty: I.type);
211 }
212 }
213}
214
215namespace clang {
216namespace CodeGen {
217void computeSPIRKernelABIInfo(CodeGenModule &CGM, CGFunctionInfo &FI) {
218 if (CGM.getTarget().getTriple().isSPIRV())
219 SPIRVABIInfo(CGM.getTypes()).computeInfo(FI);
220 else
221 CommonSPIRABIInfo(CGM.getTypes()).computeInfo(FI);
222}
223}
224}
225
226unsigned CommonSPIRTargetCodeGenInfo::getDeviceKernelCallingConv() const {
227 return llvm::CallingConv::SPIR_KERNEL;
228}
229
230void SPIRVTargetCodeGenInfo::setCUDAKernelCallingConvention(
231 const FunctionType *&FT) const {
232 // Convert HIP kernels to SPIR-V kernels.
233 if (getABIInfo().getContext().getLangOpts().HIP) {
234 FT = getABIInfo().getContext().adjustFunctionType(
235 Fn: FT, EInfo: FT->getExtInfo().withCallingConv(cc: CC_DeviceKernel));
236 return;
237 }
238}
239
240void CommonSPIRTargetCodeGenInfo::setOCLKernelStubCallingConvention(
241 const FunctionType *&FT) const {
242 FT = getABIInfo().getContext().adjustFunctionType(
243 Fn: FT, EInfo: FT->getExtInfo().withCallingConv(cc: CC_SpirFunction));
244}
245
246LangAS
247SPIRVTargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM,
248 const VarDecl *D) const {
249 assert(!CGM.getLangOpts().OpenCL &&
250 !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&
251 "Address space agnostic languages only");
252 // If we're here it means that we're using the SPIRDefIsGen ASMap, hence for
253 // the global AS we can rely on either cuda_device or sycl_global to be
254 // correct; however, since this is not a CUDA Device context, we use
255 // sycl_global to prevent confusion with the assertion.
256 LangAS DefaultGlobalAS = getLangASFromTargetAS(
257 TargetAS: CGM.getContext().getTargetAddressSpace(AS: LangAS::sycl_global));
258 if (!D)
259 return DefaultGlobalAS;
260
261 LangAS AddrSpace = D->getType().getAddressSpace();
262 if (AddrSpace != LangAS::Default)
263 return AddrSpace;
264
265 return DefaultGlobalAS;
266}
267
268void SPIRVTargetCodeGenInfo::setTargetAttributes(
269 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
270 if (!M.getLangOpts().HIP ||
271 M.getTarget().getTriple().getVendor() != llvm::Triple::AMD)
272 return;
273 if (GV->isDeclaration())
274 return;
275
276 auto F = dyn_cast<llvm::Function>(Val: GV);
277 if (!F)
278 return;
279
280 auto FD = dyn_cast_or_null<FunctionDecl>(Val: D);
281 if (!FD)
282 return;
283 if (!FD->hasAttr<CUDAGlobalAttr>())
284 return;
285
286 unsigned N = M.getLangOpts().GPUMaxThreadsPerBlock;
287 if (auto FlatWGS = FD->getAttr<AMDGPUFlatWorkGroupSizeAttr>())
288 N = FlatWGS->getMax()->EvaluateKnownConstInt(Ctx: M.getContext()).getExtValue();
289
290 // We encode the maximum flat WG size in the first component of the 3D
291 // max_work_group_size attribute, which will get reverse translated into the
292 // original AMDGPU attribute when targeting AMDGPU.
293 auto Int32Ty = llvm::IntegerType::getInt32Ty(C&: M.getLLVMContext());
294 llvm::Metadata *AttrMDArgs[] = {
295 llvm::ConstantAsMetadata::get(C: llvm::ConstantInt::get(Ty: Int32Ty, V: N)),
296 llvm::ConstantAsMetadata::get(C: llvm::ConstantInt::get(Ty: Int32Ty, V: 1)),
297 llvm::ConstantAsMetadata::get(C: llvm::ConstantInt::get(Ty: Int32Ty, V: 1))};
298
299 F->setMetadata(Kind: "max_work_group_size",
300 Node: llvm::MDNode::get(Context&: M.getLLVMContext(), MDs: AttrMDArgs));
301}
302
303llvm::SyncScope::ID
304SPIRVTargetCodeGenInfo::getLLVMSyncScopeID(const LangOptions &, SyncScope Scope,
305 llvm::AtomicOrdering,
306 llvm::LLVMContext &Ctx) const {
307 return Ctx.getOrInsertSyncScopeID(SSN: mapClangSyncScopeToLLVM(Scope));
308}
309
310/// Construct a SPIR-V target extension type for the given OpenCL image type.
311static llvm::Type *getSPIRVImageType(llvm::LLVMContext &Ctx, StringRef BaseType,
312 StringRef OpenCLName,
313 unsigned AccessQualifier) {
314 // These parameters compare to the operands of OpTypeImage (see
315 // https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpTypeImage
316 // for more details). The first 6 integer parameters all default to 0, and
317 // will be changed to 1 only for the image type(s) that set the parameter to
318 // one. The 7th integer parameter is the access qualifier, which is tacked on
319 // at the end.
320 SmallVector<unsigned, 7> IntParams = {0, 0, 0, 0, 0, 0};
321
322 // Choose the dimension of the image--this corresponds to the Dim enum in
323 // SPIR-V (first integer parameter of OpTypeImage).
324 if (OpenCLName.starts_with(Prefix: "image2d"))
325 IntParams[0] = 1; // 1D
326 else if (OpenCLName.starts_with(Prefix: "image3d"))
327 IntParams[0] = 2; // 2D
328 else if (OpenCLName == "image1d_buffer")
329 IntParams[0] = 5; // Buffer
330 else
331 assert(OpenCLName.starts_with("image1d") && "Unknown image type");
332
333 // Set the other integer parameters of OpTypeImage if necessary. Note that the
334 // OpenCL image types don't provide any information for the Sampled or
335 // Image Format parameters.
336 if (OpenCLName.contains(Other: "_depth"))
337 IntParams[1] = 1;
338 if (OpenCLName.contains(Other: "_array"))
339 IntParams[2] = 1;
340 if (OpenCLName.contains(Other: "_msaa"))
341 IntParams[3] = 1;
342
343 // Access qualifier
344 IntParams.push_back(Elt: AccessQualifier);
345
346 return llvm::TargetExtType::get(Context&: Ctx, Name: BaseType, Types: {llvm::Type::getVoidTy(C&: Ctx)},
347 Ints: IntParams);
348}
349
350llvm::Type *CommonSPIRTargetCodeGenInfo::getOpenCLType(CodeGenModule &CGM,
351 const Type *Ty) const {
352 llvm::LLVMContext &Ctx = CGM.getLLVMContext();
353 if (auto *PipeTy = dyn_cast<PipeType>(Val: Ty))
354 return llvm::TargetExtType::get(Context&: Ctx, Name: "spirv.Pipe", Types: {},
355 Ints: {!PipeTy->isReadOnly()});
356 if (auto *BuiltinTy = dyn_cast<BuiltinType>(Val: Ty)) {
357 enum AccessQualifier : unsigned { AQ_ro = 0, AQ_wo = 1, AQ_rw = 2 };
358 switch (BuiltinTy->getKind()) {
359#define IMAGE_TYPE(ImgType, Id, SingletonId, Access, Suffix) \
360 case BuiltinType::Id: \
361 return getSPIRVImageType(Ctx, "spirv.Image", #ImgType, AQ_##Suffix);
362#include "clang/Basic/OpenCLImageTypes.def"
363 case BuiltinType::OCLSampler:
364 return llvm::TargetExtType::get(Context&: Ctx, Name: "spirv.Sampler");
365 case BuiltinType::OCLEvent:
366 return llvm::TargetExtType::get(Context&: Ctx, Name: "spirv.Event");
367 case BuiltinType::OCLClkEvent:
368 return llvm::TargetExtType::get(Context&: Ctx, Name: "spirv.DeviceEvent");
369 case BuiltinType::OCLQueue:
370 return llvm::TargetExtType::get(Context&: Ctx, Name: "spirv.Queue");
371 case BuiltinType::OCLReserveID:
372 return llvm::TargetExtType::get(Context&: Ctx, Name: "spirv.ReserveId");
373#define INTEL_SUBGROUP_AVC_TYPE(Name, Id) \
374 case BuiltinType::OCLIntelSubgroupAVC##Id: \
375 return llvm::TargetExtType::get(Ctx, "spirv.Avc" #Id "INTEL");
376#include "clang/Basic/OpenCLExtensionTypes.def"
377 default:
378 return nullptr;
379 }
380 }
381
382 return nullptr;
383}
384
385// Gets a spirv.IntegralConstant or spirv.Literal. If IntegralType is present,
386// returns an IntegralConstant, otherwise returns a Literal.
387static llvm::Type *getInlineSpirvConstant(CodeGenModule &CGM,
388 llvm::Type *IntegralType,
389 llvm::APInt Value) {
390 llvm::LLVMContext &Ctx = CGM.getLLVMContext();
391
392 // Convert the APInt value to an array of uint32_t words
393 llvm::SmallVector<uint32_t> Words;
394
395 while (Value.ugt(RHS: 0)) {
396 uint32_t Word = Value.trunc(width: 32).getZExtValue();
397 Value.lshrInPlace(ShiftAmt: 32);
398
399 Words.push_back(Elt: Word);
400 }
401 if (Words.size() == 0)
402 Words.push_back(Elt: 0);
403
404 if (IntegralType)
405 return llvm::TargetExtType::get(Context&: Ctx, Name: "spirv.IntegralConstant",
406 Types: {IntegralType}, Ints: Words);
407 return llvm::TargetExtType::get(Context&: Ctx, Name: "spirv.Literal", Types: {}, Ints: Words);
408}
409
410static llvm::Type *getInlineSpirvType(CodeGenModule &CGM,
411 const HLSLInlineSpirvType *SpirvType) {
412 llvm::LLVMContext &Ctx = CGM.getLLVMContext();
413
414 llvm::SmallVector<llvm::Type *> Operands;
415
416 for (auto &Operand : SpirvType->getOperands()) {
417 using SpirvOperandKind = SpirvOperand::SpirvOperandKind;
418
419 llvm::Type *Result = nullptr;
420 switch (Operand.getKind()) {
421 case SpirvOperandKind::ConstantId: {
422 llvm::Type *IntegralType =
423 CGM.getTypes().ConvertType(T: Operand.getResultType());
424 llvm::APInt Value = Operand.getValue();
425
426 Result = getInlineSpirvConstant(CGM, IntegralType, Value);
427 break;
428 }
429 case SpirvOperandKind::Literal: {
430 llvm::APInt Value = Operand.getValue();
431 Result = getInlineSpirvConstant(CGM, IntegralType: nullptr, Value);
432 break;
433 }
434 case SpirvOperandKind::TypeId: {
435 QualType TypeOperand = Operand.getResultType();
436 if (auto *RT = TypeOperand->getAs<RecordType>()) {
437 auto *RD = RT->getDecl();
438 assert(RD->isCompleteDefinition() &&
439 "Type completion should have been required in Sema");
440
441 const FieldDecl *HandleField = RD->findFirstNamedDataMember();
442 if (HandleField) {
443 QualType ResourceType = HandleField->getType();
444 if (ResourceType->getAs<HLSLAttributedResourceType>()) {
445 TypeOperand = ResourceType;
446 }
447 }
448 }
449 Result = CGM.getTypes().ConvertType(T: TypeOperand);
450 break;
451 }
452 default:
453 llvm_unreachable("HLSLInlineSpirvType had invalid operand!");
454 break;
455 }
456
457 assert(Result);
458 Operands.push_back(Elt: Result);
459 }
460
461 return llvm::TargetExtType::get(Context&: Ctx, Name: "spirv.Type", Types: Operands,
462 Ints: {SpirvType->getOpcode(), SpirvType->getSize(),
463 SpirvType->getAlignment()});
464}
465
466llvm::Type *CommonSPIRTargetCodeGenInfo::getHLSLType(
467 CodeGenModule &CGM, const Type *Ty,
468 const SmallVector<int32_t> *Packoffsets) const {
469 llvm::LLVMContext &Ctx = CGM.getLLVMContext();
470
471 if (auto *SpirvType = dyn_cast<HLSLInlineSpirvType>(Val: Ty))
472 return getInlineSpirvType(CGM, SpirvType);
473
474 auto *ResType = dyn_cast<HLSLAttributedResourceType>(Val: Ty);
475 if (!ResType)
476 return nullptr;
477
478 const HLSLAttributedResourceType::Attributes &ResAttrs = ResType->getAttrs();
479 switch (ResAttrs.ResourceClass) {
480 case llvm::dxil::ResourceClass::UAV:
481 case llvm::dxil::ResourceClass::SRV: {
482 // TypedBuffer and RawBuffer both need element type
483 QualType ContainedTy = ResType->getContainedType();
484 if (ContainedTy.isNull())
485 return nullptr;
486
487 assert(!ResAttrs.IsROV &&
488 "Rasterizer order views not implemented for SPIR-V yet");
489
490 if (!ResAttrs.RawBuffer) {
491 // convert element type
492 return getSPIRVImageTypeFromHLSLResource(attributes: ResAttrs, SampledType: ContainedTy, CGM);
493 }
494
495 llvm::Type *ElemType = CGM.getTypes().ConvertTypeForMem(T: ContainedTy);
496 llvm::ArrayType *RuntimeArrayType = llvm::ArrayType::get(ElementType: ElemType, NumElements: 0);
497 uint32_t StorageClass = /* StorageBuffer storage class */ 12;
498 bool IsWritable = ResAttrs.ResourceClass == llvm::dxil::ResourceClass::UAV;
499 return llvm::TargetExtType::get(Context&: Ctx, Name: "spirv.VulkanBuffer",
500 Types: {RuntimeArrayType},
501 Ints: {StorageClass, IsWritable});
502 }
503 case llvm::dxil::ResourceClass::CBuffer: {
504 QualType ContainedTy = ResType->getContainedType();
505 if (ContainedTy.isNull() || !ContainedTy->isStructureType())
506 return nullptr;
507
508 llvm::Type *BufferLayoutTy =
509 HLSLBufferLayoutBuilder(CGM, "spirv.Layout")
510 .createLayoutType(StructType: ContainedTy->getAsStructureType(), Packoffsets);
511 uint32_t StorageClass = /* Uniform storage class */ 2;
512 return llvm::TargetExtType::get(Context&: Ctx, Name: "spirv.VulkanBuffer", Types: {BufferLayoutTy},
513 Ints: {StorageClass, false});
514 break;
515 }
516 case llvm::dxil::ResourceClass::Sampler:
517 return llvm::TargetExtType::get(Context&: Ctx, Name: "spirv.Sampler");
518 }
519 return nullptr;
520}
521
522llvm::Type *CommonSPIRTargetCodeGenInfo::getSPIRVImageTypeFromHLSLResource(
523 const HLSLAttributedResourceType::Attributes &attributes, QualType Ty,
524 CodeGenModule &CGM) const {
525 llvm::LLVMContext &Ctx = CGM.getLLVMContext();
526
527 Ty = Ty->getCanonicalTypeUnqualified();
528 if (const VectorType *V = dyn_cast<VectorType>(Val&: Ty))
529 Ty = V->getElementType();
530 assert(!Ty->isVectorType() && "We still have a vector type.");
531
532 llvm::Type *SampledType = CGM.getTypes().ConvertTypeForMem(T: Ty);
533
534 assert((SampledType->isIntegerTy() || SampledType->isFloatingPointTy()) &&
535 "The element type for a SPIR-V resource must be a scalar integer or "
536 "floating point type.");
537
538 // These parameters correspond to the operands to the OpTypeImage SPIR-V
539 // instruction. See
540 // https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpTypeImage.
541 SmallVector<unsigned, 6> IntParams(6, 0);
542
543 const char *Name =
544 Ty->isSignedIntegerType() ? "spirv.SignedImage" : "spirv.Image";
545
546 // Dim
547 // For now we assume everything is a buffer.
548 IntParams[0] = 5;
549
550 // Depth
551 // HLSL does not indicate if it is a depth texture or not, so we use unknown.
552 IntParams[1] = 2;
553
554 // Arrayed
555 IntParams[2] = 0;
556
557 // MS
558 IntParams[3] = 0;
559
560 // Sampled
561 IntParams[4] =
562 attributes.ResourceClass == llvm::dxil::ResourceClass::UAV ? 2 : 1;
563
564 // Image format.
565 // Setting to unknown for now.
566 IntParams[5] = 0;
567
568 llvm::TargetExtType *ImageType =
569 llvm::TargetExtType::get(Context&: Ctx, Name, Types: {SampledType}, Ints: IntParams);
570 return ImageType;
571}
572
573std::unique_ptr<TargetCodeGenInfo>
574CodeGen::createCommonSPIRTargetCodeGenInfo(CodeGenModule &CGM) {
575 return std::make_unique<CommonSPIRTargetCodeGenInfo>(args&: CGM.getTypes());
576}
577
578std::unique_ptr<TargetCodeGenInfo>
579CodeGen::createSPIRVTargetCodeGenInfo(CodeGenModule &CGM) {
580 return std::make_unique<SPIRVTargetCodeGenInfo>(args&: CGM.getTypes());
581}
582