1//===- FunctionLoweringInfo.h - Lower functions from LLVM IR ---*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements routines for translating functions from LLVM IR into
10// Machine IR.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
15#define LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
16
17#include "llvm/ADT/BitVector.h"
18#include "llvm/ADT/DenseMap.h"
19#include "llvm/ADT/IndexedMap.h"
20#include "llvm/ADT/SmallPtrSet.h"
21#include "llvm/ADT/SmallVector.h"
22#include "llvm/CodeGen/ISDOpcodes.h"
23#include "llvm/CodeGen/MachineBasicBlock.h"
24#include "llvm/CodeGen/TargetRegisterInfo.h"
25#include "llvm/IR/Instructions.h"
26#include "llvm/IR/Type.h"
27#include "llvm/IR/Value.h"
28#include "llvm/Support/KnownBits.h"
29#include <cassert>
30#include <utility>
31#include <vector>
32
33namespace llvm {
34
35class Argument;
36class BasicBlock;
37class BranchProbabilityInfo;
38class Function;
39class Instruction;
40class MachineFunction;
41class MachineInstr;
42class MachineRegisterInfo;
43class MVT;
44class SelectionDAG;
45class TargetLowering;
46
47template <typename T> class GenericSSAContext;
48using SSAContext = GenericSSAContext<Function>;
49template <typename T> class GenericUniformityInfo;
50using UniformityInfo = GenericUniformityInfo<SSAContext>;
51
52//===--------------------------------------------------------------------===//
53/// FunctionLoweringInfo - This contains information that is global to a
54/// function that is used when lowering a region of the function.
55///
56class FunctionLoweringInfo {
57public:
58 const Function *Fn;
59 MachineFunction *MF;
60 const TargetLowering *TLI;
61 MachineRegisterInfo *RegInfo;
62 BranchProbabilityInfo *BPI;
63 const UniformityInfo *UA;
64 /// CanLowerReturn - true iff the function's return value can be lowered to
65 /// registers.
66 bool CanLowerReturn;
67
68 /// True if part of the CSRs will be handled via explicit copies.
69 bool SplitCSR;
70
71 /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
72 /// allocated to hold a pointer to the hidden sret parameter.
73 Register DemoteRegister;
74
75 /// A mapping from LLVM basic block number to their machine block.
76 SmallVector<MachineBasicBlock *> MBBMap;
77
78 /// ValueMap - Since we emit code for the function a basic block at a time,
79 /// we must remember which virtual registers hold the values for
80 /// cross-basic-block values.
81 DenseMap<const Value *, Register> ValueMap;
82
83 /// VirtReg2Value map is needed by the Divergence Analysis driven
84 /// instruction selection. It is reverted ValueMap. It is computed
85 /// in lazy style - on demand. It is used to get the Value corresponding
86 /// to the live in virtual register and is called from the
87 /// TargetLowerinInfo::isSDNodeSourceOfDivergence.
88 DenseMap<Register, const Value*> VirtReg2Value;
89
90 /// This method is called from TargetLowerinInfo::isSDNodeSourceOfDivergence
91 /// to get the Value corresponding to the live-in virtual register.
92 const Value *getValueFromVirtualReg(Register Vreg);
93
94 /// Track virtual registers created for exception pointers.
95 DenseMap<const Value *, Register> CatchPadExceptionPointers;
96
97 /// Helper object to track which of three possible relocation mechanisms are
98 /// used for a particular value being relocated over a statepoint.
99 struct StatepointRelocationRecord {
100 enum RelocType {
101 // Value did not need to be relocated and can be used directly.
102 NoRelocate,
103 // Value was spilled to stack and needs filled at the gc.relocate.
104 Spill,
105 // Value was lowered to tied def and gc.relocate should be replaced with
106 // copy from vreg.
107 VReg,
108 // Value was lowered to tied def and gc.relocate should be replaced with
109 // SDValue kept in StatepointLoweringInfo structure. This valid for local
110 // relocates only.
111 SDValueNode,
112 } type = NoRelocate;
113 // Payload contains either frame index of the stack slot in which the value
114 // was spilled, or virtual register which contains the re-definition.
115 union payload_t {
116 payload_t() : FI(-1) {}
117 int FI;
118 Register Reg;
119 } payload;
120 };
121
122 /// Keep track of each value which was relocated and the strategy used to
123 /// relocate that value. This information is required when visiting
124 /// gc.relocates which may appear in following blocks.
125 using StatepointSpillMapTy =
126 DenseMap<const Value *, StatepointRelocationRecord>;
127 DenseMap<const Instruction *, StatepointSpillMapTy> StatepointRelocationMaps;
128
129 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
130 /// the entry block. This allows the allocas to be efficiently referenced
131 /// anywhere in the function.
132 DenseMap<const AllocaInst*, int> StaticAllocaMap;
133
134 /// ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
135 DenseMap<const Argument*, int> ByValArgFrameIndexMap;
136
137 /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for
138 /// function arguments that are inserted after scheduling is completed.
139 SmallVector<MachineInstr*, 8> ArgDbgValues;
140
141 /// Bitvector with a bit set if corresponding argument is described in
142 /// ArgDbgValues. Using arg numbers according to Argument numbering.
143 BitVector DescribedArgs;
144
145 /// RegFixups - Registers which need to be replaced after isel is done.
146 DenseMap<Register, Register> RegFixups;
147
148 DenseSet<Register> RegsWithFixups;
149
150 /// StatepointStackSlots - A list of temporary stack slots (frame indices)
151 /// used to spill values at a statepoint. We store them here to enable
152 /// reuse of the same stack slots across different statepoints in different
153 /// basic blocks.
154 SmallVector<unsigned, 50> StatepointStackSlots;
155
156 /// MBB - The current block.
157 MachineBasicBlock *MBB;
158
159 /// MBB - The current insert position inside the current block.
160 MachineBasicBlock::iterator InsertPt;
161
162 struct LiveOutInfo {
163 unsigned NumSignBits : 31;
164 unsigned IsValid : 1;
165 KnownBits Known = 1;
166
167 LiveOutInfo() : NumSignBits(0), IsValid(true) {}
168 };
169
170 /// Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND)
171 /// for a value.
172 DenseMap<const Value *, ISD::NodeType> PreferredExtendType;
173
174 /// The set of basic blocks visited thus far by instruction selection. Indexed
175 /// by basic block number.
176 SmallVector<bool> VisitedBBs;
177
178 /// PHINodesToUpdate - A list of phi instructions whose operand list will
179 /// be updated after processing the current basic block.
180 /// TODO: This isn't per-function state, it's per-basic-block state. But
181 /// there's no other convenient place for it to live right now.
182 std::vector<std::pair<MachineInstr*, Register>> PHINodesToUpdate;
183 unsigned OrigNumPHINodesToUpdate;
184
185 /// If the current MBB is a landing pad, the exception pointer and exception
186 /// selector registers are copied into these virtual registers by
187 /// SelectionDAGISel::PrepareEHLandingPad().
188 Register ExceptionPointerVirtReg, ExceptionSelectorVirtReg;
189
190 /// The current call site index being processed, if any. 0 if none.
191 unsigned CurCallSite = 0;
192
193 /// Collection of dbg_declare instructions handled after argument
194 /// lowering and before ISel proper.
195 SmallPtrSet<const DbgVariableRecord *, 8> PreprocessedDVRDeclares;
196
197 /// set - Initialize this FunctionLoweringInfo with the given Function
198 /// and its associated MachineFunction.
199 ///
200 void set(const Function &Fn, MachineFunction &MF, SelectionDAG *DAG);
201
202 /// clear - Clear out all the function-specific state. This returns this
203 /// FunctionLoweringInfo to an empty state, ready to be used for a
204 /// different function.
205 void clear();
206
207 /// isExportedInst - Return true if the specified value is an instruction
208 /// exported from its block.
209 bool isExportedInst(const Value *V) const {
210 return ValueMap.count(Val: V);
211 }
212
213 MachineBasicBlock *getMBB(const BasicBlock *BB) const {
214 assert(BB->getNumber() < MBBMap.size() && "uninitialized MBBMap?");
215 return MBBMap[BB->getNumber()];
216 }
217
218 Register CreateReg(MVT VT, bool isDivergent = false);
219
220 Register CreateRegs(const Value *V);
221
222 Register CreateRegs(Type *Ty, bool isDivergent = false);
223
224 Register InitializeRegForValue(const Value *V);
225
226 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
227 /// register is a PHI destination and the PHI's LiveOutInfo is not valid.
228 const LiveOutInfo *GetLiveOutRegInfo(Register Reg) {
229 if (!LiveOutRegInfo.inBounds(n: Reg))
230 return nullptr;
231
232 const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
233 if (!LOI->IsValid)
234 return nullptr;
235
236 return LOI;
237 }
238
239 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
240 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
241 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
242 /// the larger bit width by zero extension. The bit width must be no smaller
243 /// than the LiveOutInfo's existing bit width.
244 const LiveOutInfo *GetLiveOutRegInfo(Register Reg, unsigned BitWidth);
245
246 /// AddLiveOutRegInfo - Adds LiveOutInfo for a register.
247 void AddLiveOutRegInfo(Register Reg, unsigned NumSignBits,
248 const KnownBits &Known) {
249 // Only install this information if it tells us something.
250 if (NumSignBits == 1 && Known.isUnknown())
251 return;
252
253 LiveOutRegInfo.grow(n: Reg);
254 LiveOutInfo &LOI = LiveOutRegInfo[Reg];
255 LOI.NumSignBits = NumSignBits;
256 LOI.Known.One = Known.One;
257 LOI.Known.Zero = Known.Zero;
258 }
259
260 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
261 /// register based on the LiveOutInfo of its operands.
262 void ComputePHILiveOutRegInfo(const PHINode*);
263
264 /// InvalidatePHILiveOutRegInfo - Invalidates a PHI's LiveOutInfo, to be
265 /// called when a block is visited before all of its predecessors.
266 void InvalidatePHILiveOutRegInfo(const PHINode *PN) {
267 // PHIs with no uses have no ValueMap entry.
268 DenseMap<const Value*, Register>::const_iterator It = ValueMap.find(Val: PN);
269 if (It == ValueMap.end())
270 return;
271
272 Register Reg = It->second;
273 if (Reg == 0)
274 return;
275
276 LiveOutRegInfo.grow(n: Reg);
277 LiveOutRegInfo[Reg].IsValid = false;
278 }
279
280 /// setArgumentFrameIndex - Record frame index for the byval
281 /// argument.
282 void setArgumentFrameIndex(const Argument *A, int FI);
283
284 /// getArgumentFrameIndex - Get frame index for the byval argument.
285 int getArgumentFrameIndex(const Argument *A);
286
287 Register getCatchPadExceptionPointerVReg(const Value *CPI,
288 const TargetRegisterClass *RC);
289
290 /// Set the call site currently being processed.
291 void setCurrentCallSite(unsigned Site) { CurCallSite = Site; }
292
293 /// Get the call site currently being processed, if any. Return zero if none.
294 unsigned getCurrentCallSite() { return CurCallSite; }
295
296private:
297 /// LiveOutRegInfo - Information about live out vregs.
298 IndexedMap<LiveOutInfo, VirtReg2IndexFunctor> LiveOutRegInfo;
299};
300
301} // end namespace llvm
302
303#endif // LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
304