1//===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements the ScheduleDAG class, which is a base class used by
10// scheduling implementation classes.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ScheduleDAGSDNodes.h"
15#include "InstrEmitter.h"
16#include "SDNodeDbgValue.h"
17#include "llvm/ADT/DenseMap.h"
18#include "llvm/ADT/SmallPtrSet.h"
19#include "llvm/ADT/SmallSet.h"
20#include "llvm/ADT/SmallVector.h"
21#include "llvm/ADT/Statistic.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/SelectionDAG.h"
25#include "llvm/CodeGen/TargetInstrInfo.h"
26#include "llvm/CodeGen/TargetLowering.h"
27#include "llvm/CodeGen/TargetRegisterInfo.h"
28#include "llvm/CodeGen/TargetSubtargetInfo.h"
29#include "llvm/Config/llvm-config.h"
30#include "llvm/IR/MemoryModelRelaxationAnnotations.h"
31#include "llvm/MC/MCInstrItineraries.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/Debug.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetMachine.h"
36using namespace llvm;
37
38#define DEBUG_TYPE "pre-RA-sched"
39
40STATISTIC(LoadsClustered, "Number of loads clustered together");
41
42// This allows the latency-based scheduler to notice high latency instructions
43// without a target itinerary. The choice of number here has more to do with
44// balancing scheduler heuristics than with the actual machine latency.
45static cl::opt<int> HighLatencyCycles(
46 "sched-high-latency-cycles", cl::Hidden, cl::init(Val: 10),
47 cl::desc("Roughly estimate the number of cycles that 'long latency' "
48 "instructions take for targets with no itinerary"));
49
50ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf)
51 : ScheduleDAG(mf), InstrItins(mf.getSubtarget().getInstrItineraryData()) {}
52
53/// Run - perform scheduling.
54///
55void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb) {
56 BB = bb;
57 DAG = dag;
58
59 // Clear the scheduler's SUnit DAG.
60 ScheduleDAG::clearDAG();
61 Sequence.clear();
62
63 // Invoke the target's selection of scheduler.
64 Schedule();
65}
66
67/// NewSUnit - Creates a new SUnit and return a ptr to it.
68///
69SUnit *ScheduleDAGSDNodes::newSUnit(SDNode *N) {
70#ifndef NDEBUG
71 const SUnit *Addr = nullptr;
72 if (!SUnits.empty())
73 Addr = &SUnits[0];
74#endif
75 SUnits.emplace_back(args&: N, args: (unsigned)SUnits.size());
76 assert((Addr == nullptr || Addr == &SUnits[0]) &&
77 "SUnits std::vector reallocated on the fly!");
78 SUnits.back().OrigNode = &SUnits.back();
79 SUnit *SU = &SUnits.back();
80 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
81 if (!N ||
82 (N->isMachineOpcode() &&
83 N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF))
84 SU->SchedulingPref = Sched::None;
85 else
86 SU->SchedulingPref = TLI.getSchedulingPreference(N);
87 return SU;
88}
89
90SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
91 SUnit *SU = newSUnit(N: Old->getNode());
92 SU->OrigNode = Old->OrigNode;
93 SU->Latency = Old->Latency;
94 SU->isVRegCycle = Old->isVRegCycle;
95 SU->isCall = Old->isCall;
96 SU->isCallOp = Old->isCallOp;
97 SU->isTwoAddress = Old->isTwoAddress;
98 SU->isCommutable = Old->isCommutable;
99 SU->hasPhysRegDefs = Old->hasPhysRegDefs;
100 SU->hasPhysRegClobbers = Old->hasPhysRegClobbers;
101 SU->isScheduleHigh = Old->isScheduleHigh;
102 SU->isScheduleLow = Old->isScheduleLow;
103 SU->SchedulingPref = Old->SchedulingPref;
104 Old->isCloned = true;
105 return SU;
106}
107
108/// CheckForPhysRegDependency - Check if the dependency between def and use of
109/// a specified operand is a physical register dependency. If so, returns the
110/// register and the cost of copying the register.
111static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
112 const TargetRegisterInfo *TRI,
113 const TargetInstrInfo *TII,
114 const TargetLowering &TLI,
115 MCRegister &PhysReg, int &Cost) {
116 if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
117 return;
118
119 Register Reg = cast<RegisterSDNode>(Val: User->getOperand(Num: 1))->getReg();
120 if (TLI.checkForPhysRegDependency(Def, User, Op, TRI, TII, PhysReg, Cost))
121 return;
122
123 if (Reg.isVirtual())
124 return;
125
126 unsigned ResNo = User->getOperand(Num: 2).getResNo();
127 if (Def->getOpcode() == ISD::CopyFromReg &&
128 cast<RegisterSDNode>(Val: Def->getOperand(Num: 1))->getReg() == Reg) {
129 PhysReg = Reg;
130 } else if (Def->isMachineOpcode()) {
131 const MCInstrDesc &II = TII->get(Opcode: Def->getMachineOpcode());
132 if (ResNo >= II.getNumDefs() && II.hasImplicitDefOfPhysReg(Reg))
133 PhysReg = Reg;
134 }
135
136 if (PhysReg) {
137 const TargetRegisterClass *RC =
138 TRI->getMinimalPhysRegClass(Reg, VT: Def->getSimpleValueType(ResNo));
139 Cost = RC->getCopyCost();
140 }
141}
142
143// Helper for AddGlue to clone node operands.
144static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, ArrayRef<EVT> VTs,
145 SDValue ExtraOper = SDValue()) {
146 SmallVector<SDValue, 8> Ops(N->ops());
147 if (ExtraOper.getNode())
148 Ops.push_back(Elt: ExtraOper);
149
150 SDVTList VTList = DAG->getVTList(VTs);
151 MachineSDNode *MN = dyn_cast<MachineSDNode>(Val: N);
152
153 // Store memory references.
154 SmallVector<MachineMemOperand *, 2> MMOs;
155 if (MN)
156 MMOs.assign(in_start: MN->memoperands_begin(), in_end: MN->memoperands_end());
157
158 DAG->MorphNodeTo(N, Opc: N->getOpcode(), VTs: VTList, Ops);
159
160 // Reset the memory references
161 if (MN)
162 DAG->setNodeMemRefs(N: MN, NewMemRefs: MMOs);
163}
164
165static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) {
166 SDNode *GlueDestNode = Glue.getNode();
167
168 // Don't add glue from a node to itself.
169 if (GlueDestNode == N) return false;
170
171 // Don't add a glue operand to something that already uses glue.
172 if (GlueDestNode &&
173 N->getOperand(Num: N->getNumOperands()-1).getValueType() == MVT::Glue) {
174 return false;
175 }
176 // Don't add glue to something that already has a glue value.
177 if (N->getValueType(ResNo: N->getNumValues() - 1) == MVT::Glue) return false;
178
179 SmallVector<EVT, 4> VTs(N->values());
180 if (AddGlue)
181 VTs.push_back(Elt: MVT::Glue);
182
183 CloneNodeWithValues(N, DAG, VTs, ExtraOper: Glue);
184
185 return true;
186}
187
188// Cleanup after unsuccessful AddGlue. Use the standard method of morphing the
189// node even though simply shrinking the value list is sufficient.
190static void RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG) {
191 assert((N->getValueType(N->getNumValues() - 1) == MVT::Glue &&
192 !N->hasAnyUseOfValue(N->getNumValues() - 1)) &&
193 "expected an unused glue value");
194
195 CloneNodeWithValues(N, DAG,
196 VTs: ArrayRef(N->value_begin(), N->getNumValues() - 1));
197}
198
199/// ClusterNeighboringLoads - Force nearby loads together by "gluing" them.
200/// This function finds loads of the same base and different offsets. If the
201/// offsets are not far apart (target specific), it add MVT::Glue inputs and
202/// outputs to ensure they are scheduled together and in order. This
203/// optimization may benefit some targets by improving cache locality.
204void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) {
205 SDValue Chain;
206 unsigned NumOps = Node->getNumOperands();
207 if (Node->getOperand(Num: NumOps-1).getValueType() == MVT::Other)
208 Chain = Node->getOperand(Num: NumOps-1);
209 if (!Chain)
210 return;
211
212 // Skip any load instruction that has a tied input. There may be an additional
213 // dependency requiring a different order than by increasing offsets, and the
214 // added glue may introduce a cycle.
215 auto hasTiedInput = [this](const SDNode *N) {
216 const MCInstrDesc &MCID = TII->get(Opcode: N->getMachineOpcode());
217 for (unsigned I = 0; I != MCID.getNumOperands(); ++I) {
218 if (MCID.getOperandConstraint(OpNum: I, Constraint: MCOI::TIED_TO) != -1)
219 return true;
220 }
221
222 return false;
223 };
224
225 // Look for other loads of the same chain. Find loads that are loading from
226 // the same base pointer and different offsets.
227 SmallPtrSet<SDNode*, 16> Visited;
228 SmallVector<int64_t, 4> Offsets;
229 DenseMap<long long, SDNode*> O2SMap; // Map from offset to SDNode.
230 bool Cluster = false;
231 SDNode *Base = Node;
232
233 if (hasTiedInput(Base))
234 return;
235
236 // This algorithm requires a reasonably low use count before finding a match
237 // to avoid uselessly blowing up compile time in large blocks.
238 unsigned UseCount = 0;
239 for (SDNode::user_iterator I = Chain->user_begin(), E = Chain->user_end();
240 I != E && UseCount < 100; ++I, ++UseCount) {
241 if (I.getUse().getResNo() != Chain.getResNo())
242 continue;
243
244 SDNode *User = *I;
245 if (User == Node || !Visited.insert(Ptr: User).second)
246 continue;
247 int64_t Offset1, Offset2;
248 if (!TII->areLoadsFromSameBasePtr(Load1: Base, Load2: User, Offset1, Offset2) ||
249 Offset1 == Offset2 ||
250 hasTiedInput(User)) {
251 // FIXME: Should be ok if they addresses are identical. But earlier
252 // optimizations really should have eliminated one of the loads.
253 continue;
254 }
255 if (O2SMap.insert(KV: std::make_pair(x&: Offset1, y&: Base)).second)
256 Offsets.push_back(Elt: Offset1);
257 O2SMap.insert(KV: std::make_pair(x&: Offset2, y&: User));
258 Offsets.push_back(Elt: Offset2);
259 if (Offset2 < Offset1)
260 Base = User;
261 Cluster = true;
262 // Reset UseCount to allow more matches.
263 UseCount = 0;
264 }
265
266 if (!Cluster)
267 return;
268
269 // Sort them in increasing order.
270 llvm::sort(C&: Offsets);
271
272 // Check if the loads are close enough.
273 SmallVector<SDNode*, 4> Loads;
274 unsigned NumLoads = 0;
275 int64_t BaseOff = Offsets[0];
276 SDNode *BaseLoad = O2SMap[BaseOff];
277 Loads.push_back(Elt: BaseLoad);
278 for (unsigned i = 1, e = Offsets.size(); i != e; ++i) {
279 int64_t Offset = Offsets[i];
280 SDNode *Load = O2SMap[Offset];
281 if (!TII->shouldScheduleLoadsNear(Load1: BaseLoad, Load2: Load, Offset1: BaseOff, Offset2: Offset,NumLoads))
282 break; // Stop right here. Ignore loads that are further away.
283 Loads.push_back(Elt: Load);
284 ++NumLoads;
285 }
286
287 if (NumLoads == 0)
288 return;
289
290 // Cluster loads by adding MVT::Glue outputs and inputs. This also
291 // ensure they are scheduled in order of increasing addresses.
292 SDNode *Lead = Loads[0];
293 SDValue InGlue;
294 if (AddGlue(N: Lead, Glue: InGlue, AddGlue: true, DAG))
295 InGlue = SDValue(Lead, Lead->getNumValues() - 1);
296 for (unsigned I = 1, E = Loads.size(); I != E; ++I) {
297 bool OutGlue = I < E - 1;
298 SDNode *Load = Loads[I];
299
300 // If AddGlue fails, we could leave an unsused glue value. This should not
301 // cause any
302 if (AddGlue(N: Load, Glue: InGlue, AddGlue: OutGlue, DAG)) {
303 if (OutGlue)
304 InGlue = SDValue(Load, Load->getNumValues() - 1);
305
306 ++LoadsClustered;
307 }
308 else if (!OutGlue && InGlue.getNode())
309 RemoveUnusedGlue(N: InGlue.getNode(), DAG);
310 }
311}
312
313/// ClusterNodes - Cluster certain nodes which should be scheduled together.
314///
315void ScheduleDAGSDNodes::ClusterNodes() {
316 for (SDNode &NI : DAG->allnodes()) {
317 SDNode *Node = &NI;
318 if (!Node || !Node->isMachineOpcode())
319 continue;
320
321 unsigned Opc = Node->getMachineOpcode();
322 const MCInstrDesc &MCID = TII->get(Opcode: Opc);
323 if (MCID.mayLoad())
324 // Cluster loads from "near" addresses into combined SUnits.
325 ClusterNeighboringLoads(Node);
326 }
327}
328
329void ScheduleDAGSDNodes::BuildSchedUnits() {
330 // During scheduling, the NodeId field of SDNode is used to map SDNodes
331 // to their associated SUnits by holding SUnits table indices. A value
332 // of -1 means the SDNode does not yet have an associated SUnit.
333 unsigned NumNodes = 0;
334 for (SDNode &NI : DAG->allnodes()) {
335 NI.setNodeId(-1);
336 ++NumNodes;
337 }
338
339 // Reserve entries in the vector for each of the SUnits we are creating. This
340 // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
341 // invalidated.
342 // FIXME: Multiply by 2 because we may clone nodes during scheduling.
343 // This is a temporary workaround.
344 SUnits.reserve(n: NumNodes * 2);
345
346 // Add all nodes in depth first order.
347 SmallVector<SDNode*, 64> Worklist;
348 SmallPtrSet<SDNode*, 32> Visited;
349 Worklist.push_back(Elt: DAG->getRoot().getNode());
350 Visited.insert(Ptr: DAG->getRoot().getNode());
351
352 SmallVector<SUnit*, 8> CallSUnits;
353 while (!Worklist.empty()) {
354 SDNode *NI = Worklist.pop_back_val();
355
356 // Add all operands to the worklist unless they've already been added.
357 for (const SDValue &Op : NI->op_values())
358 if (Visited.insert(Ptr: Op.getNode()).second)
359 Worklist.push_back(Elt: Op.getNode());
360
361 if (isPassiveNode(Node: NI)) // Leaf node, e.g. a TargetImmediate.
362 continue;
363
364 // If this node has already been processed, stop now.
365 if (NI->getNodeId() != -1) continue;
366
367 SUnit *NodeSUnit = newSUnit(N: NI);
368
369 // See if anything is glued to this node, if so, add them to glued
370 // nodes. Nodes can have at most one glue input and one glue output. Glue
371 // is required to be the last operand and result of a node.
372
373 // Scan up to find glued preds.
374 SDNode *N = NI;
375 while (N->getNumOperands() &&
376 N->getOperand(Num: N->getNumOperands()-1).getValueType() == MVT::Glue) {
377 N = N->getOperand(Num: N->getNumOperands()-1).getNode();
378 assert(N->getNodeId() == -1 && "Node already inserted!");
379 N->setNodeId(NodeSUnit->NodeNum);
380 if (N->isMachineOpcode() && TII->get(Opcode: N->getMachineOpcode()).isCall())
381 NodeSUnit->isCall = true;
382 }
383
384 // Scan down to find any glued succs.
385 N = NI;
386 while (N->getValueType(ResNo: N->getNumValues()-1) == MVT::Glue) {
387 SDValue GlueVal(N, N->getNumValues()-1);
388
389 // There are either zero or one users of the Glue result.
390 bool HasGlueUse = false;
391 for (SDNode *U : N->users())
392 if (GlueVal.isOperandOf(N: U)) {
393 HasGlueUse = true;
394 assert(N->getNodeId() == -1 && "Node already inserted!");
395 N->setNodeId(NodeSUnit->NodeNum);
396 N = U;
397 if (N->isMachineOpcode() && TII->get(Opcode: N->getMachineOpcode()).isCall())
398 NodeSUnit->isCall = true;
399 break;
400 }
401 if (!HasGlueUse) break;
402 }
403
404 if (NodeSUnit->isCall)
405 CallSUnits.push_back(Elt: NodeSUnit);
406
407 // Schedule zero-latency TokenFactor below any nodes that may increase the
408 // schedule height. Otherwise, ancestors of the TokenFactor may appear to
409 // have false stalls.
410 if (NI->getOpcode() == ISD::TokenFactor)
411 NodeSUnit->isScheduleLow = true;
412
413 // If there are glue operands involved, N is now the bottom-most node
414 // of the sequence of nodes that are glued together.
415 // Update the SUnit.
416 NodeSUnit->setNode(N);
417 assert(N->getNodeId() == -1 && "Node already inserted!");
418 N->setNodeId(NodeSUnit->NodeNum);
419
420 // Compute NumRegDefsLeft. This must be done before AddSchedEdges.
421 InitNumRegDefsLeft(SU: NodeSUnit);
422
423 // Assign the Latency field of NodeSUnit using target-provided information.
424 computeLatency(SU: NodeSUnit);
425 }
426
427 // Find all call operands.
428 while (!CallSUnits.empty()) {
429 SUnit *SU = CallSUnits.pop_back_val();
430 for (const SDNode *SUNode = SU->getNode(); SUNode;
431 SUNode = SUNode->getGluedNode()) {
432 if (SUNode->getOpcode() != ISD::CopyToReg)
433 continue;
434 SDNode *SrcN = SUNode->getOperand(Num: 2).getNode();
435 if (isPassiveNode(Node: SrcN)) continue; // Not scheduled.
436 SUnit *SrcSU = &SUnits[SrcN->getNodeId()];
437 SrcSU->isCallOp = true;
438 }
439 }
440}
441
442void ScheduleDAGSDNodes::AddSchedEdges() {
443 const TargetSubtargetInfo &ST = MF.getSubtarget();
444
445 // Check to see if the scheduler cares about latencies.
446 bool UnitLatencies = forceUnitLatencies();
447
448 // Pass 2: add the preds, succs, etc.
449 for (SUnit &SU : SUnits) {
450 SDNode *MainNode = SU.getNode();
451
452 if (MainNode->isMachineOpcode()) {
453 unsigned Opc = MainNode->getMachineOpcode();
454 const MCInstrDesc &MCID = TII->get(Opcode: Opc);
455 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
456 if (MCID.getOperandConstraint(OpNum: i, Constraint: MCOI::TIED_TO) != -1) {
457 SU.isTwoAddress = true;
458 break;
459 }
460 }
461 if (MCID.isCommutable())
462 SU.isCommutable = true;
463 }
464
465 // Find all predecessors and successors of the group.
466 for (SDNode *N = SU.getNode(); N; N = N->getGluedNode()) {
467 if (N->isMachineOpcode() &&
468 !TII->get(Opcode: N->getMachineOpcode()).implicit_defs().empty()) {
469 SU.hasPhysRegClobbers = true;
470 unsigned NumUsed = InstrEmitter::CountResults(Node: N);
471 while (NumUsed != 0 && !N->hasAnyUseOfValue(Value: NumUsed - 1))
472 --NumUsed; // Skip over unused values at the end.
473 if (NumUsed > TII->get(Opcode: N->getMachineOpcode()).getNumDefs())
474 SU.hasPhysRegDefs = true;
475 }
476
477 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
478 SDNode *OpN = N->getOperand(Num: i).getNode();
479 unsigned DefIdx = N->getOperand(Num: i).getResNo();
480 if (isPassiveNode(Node: OpN)) continue; // Not scheduled.
481 SUnit *OpSU = &SUnits[OpN->getNodeId()];
482 assert(OpSU && "Node has no SUnit!");
483 if (OpSU == &SU)
484 continue; // In the same group.
485
486 EVT OpVT = N->getOperand(Num: i).getValueType();
487 assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!");
488 bool isChain = OpVT == MVT::Other;
489
490 MCRegister PhysReg;
491 int Cost = 1;
492 // Determine if this is a physical register dependency.
493 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
494 CheckForPhysRegDependency(Def: OpN, User: N, Op: i, TRI, TII, TLI, PhysReg, Cost);
495 assert((!PhysReg || !isChain) && "Chain dependence via physreg data?");
496 // FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler
497 // emits a copy from the physical register to a virtual register unless
498 // it requires a cross class copy (cost < 0). That means we are only
499 // treating "expensive to copy" register dependency as physical register
500 // dependency. This may change in the future though.
501 if (Cost >= 0 && !StressSched)
502 PhysReg = MCRegister();
503
504 // If this is a ctrl dep, latency is 1.
505 unsigned OpLatency = isChain ? 1 : OpSU->Latency;
506 // Special-case TokenFactor chains as zero-latency.
507 if(isChain && OpN->getOpcode() == ISD::TokenFactor)
508 OpLatency = 0;
509
510 SDep Dep = isChain ? SDep(OpSU, SDep::Barrier)
511 : SDep(OpSU, SDep::Data, PhysReg);
512 Dep.setLatency(OpLatency);
513 if (!isChain && !UnitLatencies) {
514 computeOperandLatency(Def: OpN, Use: N, OpIdx: i, dep&: Dep);
515 ST.adjustSchedDependency(Def: OpSU, DefOpIdx: DefIdx, Use: &SU, UseOpIdx: i, Dep, SchedModel: nullptr);
516 }
517
518 if (!SU.addPred(D: Dep) && !Dep.isCtrl() && OpSU->NumRegDefsLeft > 1) {
519 // Multiple register uses are combined in the same SUnit. For example,
520 // we could have a set of glued nodes with all their defs consumed by
521 // another set of glued nodes. Register pressure tracking sees this as
522 // a single use, so to keep pressure balanced we reduce the defs.
523 //
524 // We can't tell (without more book-keeping) if this results from
525 // glued nodes or duplicate operands. As long as we don't reduce
526 // NumRegDefsLeft to zero, we handle the common cases well.
527 --OpSU->NumRegDefsLeft;
528 }
529 }
530 }
531 }
532}
533
534/// BuildSchedGraph - Build the SUnit graph from the selection dag that we
535/// are input. This SUnit graph is similar to the SelectionDAG, but
536/// excludes nodes that aren't interesting to scheduling, and represents
537/// glued together nodes with a single SUnit.
538void ScheduleDAGSDNodes::BuildSchedGraph() {
539 // Cluster certain nodes which should be scheduled together.
540 ClusterNodes();
541 // Populate the SUnits array.
542 BuildSchedUnits();
543 // Compute all the scheduling dependencies between nodes.
544 AddSchedEdges();
545}
546
547// Initialize NumNodeDefs for the current Node's opcode.
548void ScheduleDAGSDNodes::RegDefIter::InitNodeNumDefs() {
549 // Check for phys reg copy.
550 if (!Node)
551 return;
552
553 if (!Node->isMachineOpcode()) {
554 if (Node->getOpcode() == ISD::CopyFromReg)
555 NodeNumDefs = 1;
556 else
557 NodeNumDefs = 0;
558 return;
559 }
560 unsigned POpc = Node->getMachineOpcode();
561 if (POpc == TargetOpcode::IMPLICIT_DEF) {
562 // No register need be allocated for this.
563 NodeNumDefs = 0;
564 return;
565 }
566 if (POpc == TargetOpcode::PATCHPOINT &&
567 Node->getValueType(ResNo: 0) == MVT::Other) {
568 // PATCHPOINT is defined to have one result, but it might really have none
569 // if we're not using CallingConv::AnyReg. Don't mistake the chain for a
570 // real definition.
571 NodeNumDefs = 0;
572 return;
573 }
574 unsigned NRegDefs = SchedDAG->TII->get(Opcode: Node->getMachineOpcode()).getNumDefs();
575 // Some instructions define regs that are not represented in the selection DAG
576 // (e.g. unused flags). See tMOVi8. Make sure we don't access past NumValues.
577 NodeNumDefs = std::min(a: Node->getNumValues(), b: NRegDefs);
578 DefIdx = 0;
579}
580
581// Construct a RegDefIter for this SUnit and find the first valid value.
582ScheduleDAGSDNodes::RegDefIter::RegDefIter(const SUnit *SU,
583 const ScheduleDAGSDNodes *SD)
584 : SchedDAG(SD), Node(SU->getNode()) {
585 InitNodeNumDefs();
586 Advance();
587}
588
589// Advance to the next valid value defined by the SUnit.
590void ScheduleDAGSDNodes::RegDefIter::Advance() {
591 for (;Node;) { // Visit all glued nodes.
592 for (;DefIdx < NodeNumDefs; ++DefIdx) {
593 if (!Node->hasAnyUseOfValue(Value: DefIdx))
594 continue;
595 ValueType = Node->getSimpleValueType(ResNo: DefIdx);
596 ++DefIdx;
597 return; // Found a normal regdef.
598 }
599 Node = Node->getGluedNode();
600 if (!Node) {
601 return; // No values left to visit.
602 }
603 InitNodeNumDefs();
604 }
605}
606
607void ScheduleDAGSDNodes::InitNumRegDefsLeft(SUnit *SU) {
608 assert(SU->NumRegDefsLeft == 0 && "expect a new node");
609 for (RegDefIter I(SU, this); I.IsValid(); I.Advance()) {
610 assert(SU->NumRegDefsLeft < USHRT_MAX && "overflow is ok but unexpected");
611 ++SU->NumRegDefsLeft;
612 }
613}
614
615void ScheduleDAGSDNodes::computeLatency(SUnit *SU) {
616 SDNode *N = SU->getNode();
617
618 // TokenFactor operands are considered zero latency, and some schedulers
619 // (e.g. Top-Down list) may rely on the fact that operand latency is nonzero
620 // whenever node latency is nonzero.
621 if (N && N->getOpcode() == ISD::TokenFactor) {
622 SU->Latency = 0;
623 return;
624 }
625
626 // Check to see if the scheduler cares about latencies.
627 if (forceUnitLatencies()) {
628 SU->Latency = 1;
629 return;
630 }
631
632 if (!InstrItins || InstrItins->isEmpty()) {
633 if (N && N->isMachineOpcode() &&
634 TII->isHighLatencyDef(opc: N->getMachineOpcode()))
635 SU->Latency = HighLatencyCycles;
636 else
637 SU->Latency = 1;
638 return;
639 }
640
641 // Compute the latency for the node. We use the sum of the latencies for
642 // all nodes glued together into this SUnit.
643 SU->Latency = 0;
644 for (SDNode *N = SU->getNode(); N; N = N->getGluedNode())
645 if (N->isMachineOpcode())
646 SU->Latency += TII->getInstrLatency(ItinData: InstrItins, Node: N);
647}
648
649void ScheduleDAGSDNodes::computeOperandLatency(SDNode *Def, SDNode *Use,
650 unsigned OpIdx, SDep& dep) const{
651 // Check to see if the scheduler cares about latencies.
652 if (forceUnitLatencies())
653 return;
654
655 if (dep.getKind() != SDep::Data)
656 return;
657
658 unsigned DefIdx = Use->getOperand(Num: OpIdx).getResNo();
659 if (Use->isMachineOpcode())
660 // Adjust the use operand index by num of defs.
661 OpIdx += TII->get(Opcode: Use->getMachineOpcode()).getNumDefs();
662 std::optional<unsigned> Latency =
663 TII->getOperandLatency(ItinData: InstrItins, DefNode: Def, DefIdx, UseNode: Use, UseIdx: OpIdx);
664 if (Latency > 1U && Use->getOpcode() == ISD::CopyToReg &&
665 !BB->succ_empty()) {
666 Register Reg = cast<RegisterSDNode>(Val: Use->getOperand(Num: 1))->getReg();
667 if (Reg.isVirtual())
668 // This copy is a liveout value. It is likely coalesced, so reduce the
669 // latency so not to penalize the def.
670 // FIXME: need target specific adjustment here?
671 Latency = *Latency - 1;
672 }
673 if (Latency)
674 dep.setLatency(*Latency);
675}
676
677void ScheduleDAGSDNodes::dumpNode(const SUnit &SU) const {
678#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
679 dumpNodeName(SU);
680 dbgs() << ": ";
681
682 if (!SU.getNode()) {
683 dbgs() << "PHYS REG COPY\n";
684 return;
685 }
686
687 SU.getNode()->dump(DAG);
688 dbgs() << "\n";
689 SmallVector<SDNode *, 4> GluedNodes;
690 for (SDNode *N = SU.getNode()->getGluedNode(); N; N = N->getGluedNode())
691 GluedNodes.push_back(N);
692 while (!GluedNodes.empty()) {
693 dbgs() << " ";
694 GluedNodes.back()->dump(DAG);
695 dbgs() << "\n";
696 GluedNodes.pop_back();
697 }
698#endif
699}
700
701void ScheduleDAGSDNodes::dump() const {
702#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
703 if (EntrySU.getNode() != nullptr)
704 dumpNodeAll(EntrySU);
705 for (const SUnit &SU : SUnits)
706 dumpNodeAll(SU);
707 if (ExitSU.getNode() != nullptr)
708 dumpNodeAll(ExitSU);
709#endif
710}
711
712#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
713void ScheduleDAGSDNodes::dumpSchedule() const {
714 for (const SUnit *SU : Sequence) {
715 if (SU)
716 dumpNode(*SU);
717 else
718 dbgs() << "**** NOOP ****\n";
719 }
720}
721#endif
722
723#ifndef NDEBUG
724/// VerifyScheduledSequence - Verify that all SUnits were scheduled and that
725/// their state is consistent with the nodes listed in Sequence.
726///
727void ScheduleDAGSDNodes::VerifyScheduledSequence(bool isBottomUp) {
728 unsigned ScheduledNodes = ScheduleDAG::VerifyScheduledDAG(isBottomUp);
729 unsigned Noops = llvm::count(Sequence, nullptr);
730 assert(Sequence.size() - Noops == ScheduledNodes &&
731 "The number of nodes scheduled doesn't match the expected number!");
732}
733#endif // NDEBUG
734
735/// ProcessSDDbgValues - Process SDDbgValues associated with this node.
736static void
737ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
738 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,
739 InstrEmitter::VRBaseMapType &VRBaseMap, unsigned Order) {
740 if (!N->getHasDebugValue())
741 return;
742
743 /// Returns true if \p DV has any VReg operand locations which don't exist in
744 /// VRBaseMap.
745 auto HasUnknownVReg = [&VRBaseMap](SDDbgValue *DV) {
746 for (const SDDbgOperand &L : DV->getLocationOps()) {
747 if (L.getKind() == SDDbgOperand::SDNODE &&
748 VRBaseMap.count(Val: {L.getSDNode(), L.getResNo()}) == 0)
749 return true;
750 }
751 return false;
752 };
753
754 // Opportunistically insert immediate dbg_value uses, i.e. those with the same
755 // source order number as N.
756 MachineBasicBlock *BB = Emitter.getBlock();
757 MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos();
758 for (auto *DV : DAG->GetDbgValues(SD: N)) {
759 if (DV->isEmitted())
760 continue;
761 unsigned DVOrder = DV->getOrder();
762 if (Order != 0 && DVOrder != Order)
763 continue;
764 // If DV has any VReg location operands which haven't been mapped then
765 // either that node is no longer available or we just haven't visited the
766 // node yet. In the former case we should emit an undef dbg_value, but we
767 // can do it later. And for the latter we'll want to wait until all
768 // dependent nodes have been visited.
769 if (!DV->isInvalidated() && HasUnknownVReg(DV))
770 continue;
771 MachineInstr *DbgMI = Emitter.EmitDbgValue(SD: DV, VRBaseMap);
772 if (!DbgMI)
773 continue;
774 Orders.push_back(Elt: {DVOrder, DbgMI});
775 BB->insert(I: InsertPos, MI: DbgMI);
776 }
777}
778
779// ProcessSourceNode - Process nodes with source order numbers. These are added
780// to a vector which EmitSchedule uses to determine how to insert dbg_value
781// instructions in the right order.
782static void
783ProcessSourceNode(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
784 InstrEmitter::VRBaseMapType &VRBaseMap,
785 SmallVectorImpl<std::pair<unsigned, MachineInstr *>> &Orders,
786 SmallSet<Register, 8> &Seen, MachineInstr *NewInsn) {
787 unsigned Order = N->getIROrder();
788 if (!Order || Seen.count(V: Order)) {
789 // Process any valid SDDbgValues even if node does not have any order
790 // assigned.
791 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order: 0);
792 return;
793 }
794
795 // If a new instruction was generated for this Order number, record it.
796 // Otherwise, leave this order number unseen: we will either find later
797 // instructions for it, or leave it unseen if there were no instructions at
798 // all.
799 if (NewInsn) {
800 Seen.insert(V: Order);
801 Orders.push_back(Elt: {Order, NewInsn});
802 }
803
804 // Even if no instruction was generated, a Value may have become defined via
805 // earlier nodes. Try to process them now.
806 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
807}
808
809void ScheduleDAGSDNodes::
810EmitPhysRegCopy(SUnit *SU, SmallDenseMap<SUnit *, Register, 16> &VRBaseMap,
811 MachineBasicBlock::iterator InsertPos) {
812 for (const SDep &Pred : SU->Preds) {
813 if (Pred.isCtrl())
814 continue; // ignore chain preds
815 if (Pred.getSUnit()->CopyDstRC) {
816 // Copy to physical register.
817 DenseMap<SUnit *, Register>::iterator VRI =
818 VRBaseMap.find(Val: Pred.getSUnit());
819 assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
820 // Find the destination physical register.
821 Register Reg;
822 for (const SDep &Succ : SU->Succs) {
823 if (Succ.isCtrl())
824 continue; // ignore chain preds
825 if (Succ.getReg()) {
826 Reg = Succ.getReg();
827 break;
828 }
829 }
830 BuildMI(BB&: *BB, I: InsertPos, MIMD: DebugLoc(), MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: Reg)
831 .addReg(RegNo: VRI->second);
832 } else {
833 // Copy from physical register.
834 assert(Pred.getReg() && "Unknown physical register!");
835 Register VRBase = MRI.createVirtualRegister(RegClass: SU->CopyDstRC);
836 bool isNew = VRBaseMap.insert(KV: std::make_pair(x&: SU, y&: VRBase)).second;
837 (void)isNew; // Silence compiler warning.
838 assert(isNew && "Node emitted out of order - early");
839 BuildMI(BB&: *BB, I: InsertPos, MIMD: DebugLoc(), MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: VRBase)
840 .addReg(RegNo: Pred.getReg());
841 }
842 break;
843 }
844}
845
846/// EmitSchedule - Emit the machine code in scheduled order. Return the new
847/// InsertPos and MachineBasicBlock that contains this insertion
848/// point. ScheduleDAGSDNodes holds a BB pointer for convenience, but this does
849/// not necessarily refer to returned BB. The emitter may split blocks.
850MachineBasicBlock *ScheduleDAGSDNodes::
851EmitSchedule(MachineBasicBlock::iterator &InsertPos) {
852 InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos);
853 InstrEmitter::VRBaseMapType VRBaseMap;
854 SmallDenseMap<SUnit *, Register, 16> CopyVRBaseMap;
855 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
856 SmallSet<Register, 8> Seen;
857 bool HasDbg = DAG->hasDebugValues();
858
859 // Emit a node, and determine where its first instruction is for debuginfo.
860 // Zero, one, or multiple instructions can be created when emitting a node.
861 auto EmitNode =
862 [&](SDNode *Node, bool IsClone, bool IsCloned,
863 InstrEmitter::VRBaseMapType &VRBaseMap) -> MachineInstr * {
864 // Fetch instruction prior to this, or end() if nonexistant.
865 auto GetPrevInsn = [&](MachineBasicBlock::iterator I) {
866 if (I == BB->begin())
867 return BB->end();
868 else
869 return std::prev(x: Emitter.getInsertPos());
870 };
871
872 MachineBasicBlock::iterator Before = GetPrevInsn(Emitter.getInsertPos());
873 Emitter.EmitNode(Node, IsClone, IsCloned, VRBaseMap);
874 MachineBasicBlock::iterator After = GetPrevInsn(Emitter.getInsertPos());
875
876 // If the iterator did not change, no instructions were inserted.
877 if (Before == After)
878 return nullptr;
879
880 MachineInstr *MI;
881 if (Before == BB->end()) {
882 // There were no prior instructions; the new ones must start at the
883 // beginning of the block.
884 MI = &Emitter.getBlock()->instr_front();
885 } else {
886 // Return first instruction after the pre-existing instructions.
887 MI = &*std::next(x: Before);
888 }
889
890 if (MI->isCandidateForAdditionalCallInfo()) {
891 if (DAG->getTarget().Options.EmitCallSiteInfo)
892 MF.addCallSiteInfo(CallI: MI, CallInfo: DAG->getCallSiteInfo(Node));
893
894 if (auto CalledGlobal = DAG->getCalledGlobal(Node))
895 if (CalledGlobal->Callee)
896 MF.addCalledGlobal(MI, Details: *CalledGlobal);
897 }
898
899 if (DAG->getNoMergeSiteInfo(Node)) {
900 MI->setFlag(MachineInstr::MIFlag::NoMerge);
901 }
902
903 if (MDNode *MD = DAG->getPCSections(Node))
904 MI->setPCSections(MF, MD);
905
906 // Set MMRAs on _all_ added instructions.
907 if (MDNode *MMRA = DAG->getMMRAMetadata(Node)) {
908 for (MachineBasicBlock::iterator It = MI->getIterator(),
909 End = std::next(x: After);
910 It != End; ++It)
911 It->setMMRAMetadata(MF, MMRAs: MMRA);
912 }
913
914 return MI;
915 };
916
917 // If this is the first BB, emit byval parameter dbg_value's.
918 if (HasDbg && BB->getParent()->begin() == MachineFunction::iterator(BB)) {
919 SDDbgInfo::DbgIterator PDI = DAG->ByvalParmDbgBegin();
920 SDDbgInfo::DbgIterator PDE = DAG->ByvalParmDbgEnd();
921 for (; PDI != PDE; ++PDI) {
922 MachineInstr *DbgMI= Emitter.EmitDbgValue(SD: *PDI, VRBaseMap);
923 if (DbgMI) {
924 BB->insert(I: InsertPos, MI: DbgMI);
925 // We re-emit the dbg_value closer to its use, too, after instructions
926 // are emitted to the BB.
927 (*PDI)->clearIsEmitted();
928 }
929 }
930 }
931
932 for (SUnit *SU : Sequence) {
933 if (!SU) {
934 // Null SUnit* is a noop.
935 TII->insertNoop(MBB&: *Emitter.getBlock(), MI: InsertPos);
936 continue;
937 }
938
939 // For pre-regalloc scheduling, create instructions corresponding to the
940 // SDNode and any glued SDNodes and append them to the block.
941 if (!SU->getNode()) {
942 // Emit a copy.
943 EmitPhysRegCopy(SU, VRBaseMap&: CopyVRBaseMap, InsertPos);
944 continue;
945 }
946
947 SmallVector<SDNode *, 4> GluedNodes;
948 for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode())
949 GluedNodes.push_back(Elt: N);
950 while (!GluedNodes.empty()) {
951 SDNode *N = GluedNodes.back();
952 auto NewInsn = EmitNode(N, SU->OrigNode != SU, SU->isCloned, VRBaseMap);
953 // Remember the source order of the inserted instruction.
954 if (HasDbg)
955 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen, NewInsn);
956
957 if (MDNode *MD = DAG->getHeapAllocSite(Node: N))
958 if (NewInsn && NewInsn->isCall())
959 NewInsn->setHeapAllocMarker(MF, MD);
960
961 GluedNodes.pop_back();
962 }
963 auto NewInsn =
964 EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned, VRBaseMap);
965 // Remember the source order of the inserted instruction.
966 if (HasDbg)
967 ProcessSourceNode(N: SU->getNode(), DAG, Emitter, VRBaseMap, Orders, Seen,
968 NewInsn);
969
970 if (MDNode *MD = DAG->getHeapAllocSite(Node: SU->getNode())) {
971 if (NewInsn && NewInsn->isCall())
972 NewInsn->setHeapAllocMarker(MF, MD);
973 }
974 }
975
976 // Insert all the dbg_values which have not already been inserted in source
977 // order sequence.
978 if (HasDbg) {
979 MachineBasicBlock::iterator BBBegin = BB->getFirstNonPHI();
980
981 // Sort the source order instructions and use the order to insert debug
982 // values. Use stable_sort so that DBG_VALUEs are inserted in the same order
983 // regardless of the host's implementation fo std::sort.
984 llvm::stable_sort(Range&: Orders, C: less_first());
985 std::stable_sort(first: DAG->DbgBegin(), last: DAG->DbgEnd(),
986 comp: [](const SDDbgValue *LHS, const SDDbgValue *RHS) {
987 return LHS->getOrder() < RHS->getOrder();
988 });
989
990 SDDbgInfo::DbgIterator DI = DAG->DbgBegin();
991 SDDbgInfo::DbgIterator DE = DAG->DbgEnd();
992 // Now emit the rest according to source order.
993 unsigned LastOrder = 0;
994 for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) {
995 unsigned Order = Orders[i].first;
996 MachineInstr *MI = Orders[i].second;
997 // Insert all SDDbgValue's whose order(s) are before "Order".
998 assert(MI);
999 for (; DI != DE; ++DI) {
1000 if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order)
1001 break;
1002 if ((*DI)->isEmitted())
1003 continue;
1004
1005 MachineInstr *DbgMI = Emitter.EmitDbgValue(SD: *DI, VRBaseMap);
1006 if (DbgMI) {
1007 if (!LastOrder)
1008 // Insert to start of the BB (after PHIs).
1009 BB->insert(I: BBBegin, MI: DbgMI);
1010 else {
1011 // Insert at the instruction, which may be in a different
1012 // block, if the block was split by a custom inserter.
1013 MachineBasicBlock::iterator Pos = MI;
1014 MI->getParent()->insert(I: Pos, MI: DbgMI);
1015 }
1016 }
1017 }
1018 LastOrder = Order;
1019 }
1020 // Add trailing DbgValue's before the terminator. FIXME: May want to add
1021 // some of them before one or more conditional branches?
1022 SmallVector<MachineInstr*, 8> DbgMIs;
1023 for (; DI != DE; ++DI) {
1024 if ((*DI)->isEmitted())
1025 continue;
1026 assert((*DI)->getOrder() >= LastOrder &&
1027 "emitting DBG_VALUE out of order");
1028 if (MachineInstr *DbgMI = Emitter.EmitDbgValue(SD: *DI, VRBaseMap))
1029 DbgMIs.push_back(Elt: DbgMI);
1030 }
1031
1032 MachineBasicBlock *InsertBB = Emitter.getBlock();
1033 MachineBasicBlock::iterator Pos = InsertBB->getFirstTerminator();
1034 InsertBB->insert(I: Pos, S: DbgMIs.begin(), E: DbgMIs.end());
1035
1036 SDDbgInfo::DbgLabelIterator DLI = DAG->DbgLabelBegin();
1037 SDDbgInfo::DbgLabelIterator DLE = DAG->DbgLabelEnd();
1038 // Now emit the rest according to source order.
1039 LastOrder = 0;
1040 for (const auto &InstrOrder : Orders) {
1041 unsigned Order = InstrOrder.first;
1042 MachineInstr *MI = InstrOrder.second;
1043 if (!MI)
1044 continue;
1045
1046 // Insert all SDDbgLabel's whose order(s) are before "Order".
1047 for (; DLI != DLE &&
1048 (*DLI)->getOrder() >= LastOrder && (*DLI)->getOrder() < Order;
1049 ++DLI) {
1050 MachineInstr *DbgMI = Emitter.EmitDbgLabel(SD: *DLI);
1051 if (DbgMI) {
1052 if (!LastOrder)
1053 // Insert to start of the BB (after PHIs).
1054 BB->insert(I: BBBegin, MI: DbgMI);
1055 else {
1056 // Insert at the instruction, which may be in a different
1057 // block, if the block was split by a custom inserter.
1058 MachineBasicBlock::iterator Pos = MI;
1059 MI->getParent()->insert(I: Pos, MI: DbgMI);
1060 }
1061 }
1062 }
1063 if (DLI == DLE)
1064 break;
1065
1066 LastOrder = Order;
1067 }
1068 }
1069
1070 InsertPos = Emitter.getInsertPos();
1071 // In some cases, DBG_VALUEs might be inserted after the first terminator,
1072 // which results in an invalid MBB. If that happens, move the DBG_VALUEs
1073 // before the first terminator.
1074 MachineBasicBlock *InsertBB = Emitter.getBlock();
1075 auto FirstTerm = InsertBB->getFirstTerminator();
1076 if (FirstTerm != InsertBB->end()) {
1077 assert(!FirstTerm->isDebugValue() &&
1078 "first terminator cannot be a debug value");
1079 for (MachineInstr &MI : make_early_inc_range(
1080 Range: make_range(x: std::next(x: FirstTerm), y: InsertBB->end()))) {
1081 // Only scan up to insertion point.
1082 if (&MI == InsertPos)
1083 break;
1084
1085 if (!MI.isDebugValue())
1086 continue;
1087
1088 // The DBG_VALUE was referencing a value produced by a terminator. By
1089 // moving the DBG_VALUE, the referenced value also needs invalidating.
1090 MI.getOperand(i: 0).ChangeToRegister(Reg: 0, isDef: false);
1091 MI.moveBefore(MovePos: &*FirstTerm);
1092 }
1093 }
1094 return InsertBB;
1095}
1096
1097/// Return the basic block label.
1098std::string ScheduleDAGSDNodes::getDAGName() const {
1099 return "sunit-dag." + BB->getFullName();
1100}
1101