1//===- SplitKit.cpp - Toolkit for splitting live ranges -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the SplitAnalysis class as well as mutator functions for
10// live range splitting.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SplitKit.h"
15#include "llvm/ADT/STLExtras.h"
16#include "llvm/ADT/Statistic.h"
17#include "llvm/CodeGen/LiveRangeEdit.h"
18#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
19#include "llvm/CodeGen/MachineDominators.h"
20#include "llvm/CodeGen/MachineInstr.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineLoopInfo.h"
23#include "llvm/CodeGen/MachineOperand.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/TargetInstrInfo.h"
26#include "llvm/CodeGen/TargetOpcodes.h"
27#include "llvm/CodeGen/TargetRegisterInfo.h"
28#include "llvm/CodeGen/TargetSubtargetInfo.h"
29#include "llvm/CodeGen/VirtRegMap.h"
30#include "llvm/Config/llvm-config.h"
31#include "llvm/IR/DebugLoc.h"
32#include "llvm/Support/Allocator.h"
33#include "llvm/Support/BlockFrequency.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/raw_ostream.h"
37#include <algorithm>
38#include <cassert>
39#include <iterator>
40#include <limits>
41#include <tuple>
42
43using namespace llvm;
44
45#define DEBUG_TYPE "regalloc"
46
47static cl::opt<bool>
48 EnableLoopIVHeuristic("enable-split-loopiv-heuristic",
49 cl::desc("Enable loop iv regalloc heuristic"),
50 cl::init(Val: true));
51
52STATISTIC(NumFinished, "Number of splits finished");
53STATISTIC(NumSimple, "Number of splits that were simple");
54STATISTIC(NumCopies, "Number of copies inserted for splitting");
55STATISTIC(NumRemats, "Number of rematerialized defs for splitting");
56
57//===----------------------------------------------------------------------===//
58// Last Insert Point Analysis
59//===----------------------------------------------------------------------===//
60
61InsertPointAnalysis::InsertPointAnalysis(const LiveIntervals &lis,
62 unsigned BBNum)
63 : LIS(lis), LastInsertPoint(BBNum) {}
64
65SlotIndex
66InsertPointAnalysis::computeLastInsertPoint(const LiveInterval &CurLI,
67 const MachineBasicBlock &MBB) {
68 unsigned Num = MBB.getNumber();
69 std::pair<SlotIndex, SlotIndex> &LIP = LastInsertPoint[Num];
70 SlotIndex MBBEnd = LIS.getMBBEndIdx(mbb: &MBB);
71
72 SmallVector<const MachineBasicBlock *, 1> ExceptionalSuccessors;
73 bool EHPadSuccessor = false;
74 for (const MachineBasicBlock *SMBB : MBB.successors()) {
75 if (SMBB->isEHPad()) {
76 ExceptionalSuccessors.push_back(Elt: SMBB);
77 EHPadSuccessor = true;
78 } else if (SMBB->isInlineAsmBrIndirectTarget())
79 ExceptionalSuccessors.push_back(Elt: SMBB);
80 }
81
82 // Compute insert points on the first call. The pair is independent of the
83 // current live interval.
84 if (!LIP.first.isValid()) {
85 MachineBasicBlock::const_iterator FirstTerm = MBB.getFirstTerminator();
86 if (FirstTerm == MBB.end())
87 LIP.first = MBBEnd;
88 else
89 LIP.first = LIS.getInstructionIndex(Instr: *FirstTerm);
90
91 // If there is a landing pad or inlineasm_br successor, also find the
92 // instruction. If there is no such instruction, we don't need to do
93 // anything special. We assume there cannot be multiple instructions that
94 // are Calls with EHPad successors or INLINEASM_BR in a block. Further, we
95 // assume that if there are any, they will be after any other call
96 // instructions in the block.
97 if (ExceptionalSuccessors.empty())
98 return LIP.first;
99 for (const MachineInstr &MI : llvm::reverse(C: MBB)) {
100 if ((EHPadSuccessor && MI.isCall()) ||
101 MI.getOpcode() == TargetOpcode::INLINEASM_BR) {
102 LIP.second = LIS.getInstructionIndex(Instr: MI);
103 break;
104 }
105 }
106 }
107
108 // If CurLI is live into a landing pad successor, move the last insert point
109 // back to the call that may throw.
110 if (!LIP.second)
111 return LIP.first;
112
113 if (none_of(Range&: ExceptionalSuccessors, P: [&](const MachineBasicBlock *EHPad) {
114 return LIS.isLiveInToMBB(LR: CurLI, mbb: EHPad);
115 }))
116 return LIP.first;
117
118 // Find the value leaving MBB.
119 const VNInfo *VNI = CurLI.getVNInfoBefore(Idx: MBBEnd);
120 if (!VNI)
121 return LIP.first;
122
123 // The def of statepoint instruction is a gc relocation and it should be alive
124 // in landing pad. So we cannot split interval after statepoint instruction.
125 if (SlotIndex::isSameInstr(A: VNI->def, B: LIP.second))
126 if (auto *I = LIS.getInstructionFromIndex(index: LIP.second))
127 if (I->getOpcode() == TargetOpcode::STATEPOINT)
128 return LIP.second;
129
130 // If the value leaving MBB was defined after the call in MBB, it can't
131 // really be live-in to the landing pad. This can happen if the landing pad
132 // has a PHI, and this register is undef on the exceptional edge.
133 if (!SlotIndex::isEarlierInstr(A: VNI->def, B: LIP.second) && VNI->def < MBBEnd)
134 return LIP.first;
135
136 // Value is properly live-in to the landing pad.
137 // Only allow inserts before the call.
138 return LIP.second;
139}
140
141MachineBasicBlock::iterator
142InsertPointAnalysis::getLastInsertPointIter(const LiveInterval &CurLI,
143 MachineBasicBlock &MBB) {
144 SlotIndex LIP = getLastInsertPoint(CurLI, MBB);
145 if (LIP == LIS.getMBBEndIdx(mbb: &MBB))
146 return MBB.end();
147 return LIS.getInstructionFromIndex(index: LIP);
148}
149
150//===----------------------------------------------------------------------===//
151// Split Analysis
152//===----------------------------------------------------------------------===//
153
154SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis,
155 const MachineLoopInfo &mli)
156 : MF(vrm.getMachineFunction()), VRM(vrm), LIS(lis), Loops(mli),
157 TII(*MF.getSubtarget().getInstrInfo()), IPA(lis, MF.getNumBlockIDs()) {}
158
159void SplitAnalysis::clear() {
160 UseSlots.clear();
161 UseBlocks.clear();
162 ThroughBlocks.clear();
163 CurLI = nullptr;
164}
165
166/// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
167void SplitAnalysis::analyzeUses() {
168 assert(UseSlots.empty() && "Call clear first");
169
170 // First get all the defs from the interval values. This provides the correct
171 // slots for early clobbers.
172 for (const VNInfo *VNI : CurLI->valnos)
173 if (!VNI->isPHIDef() && !VNI->isUnused())
174 UseSlots.push_back(Elt: VNI->def);
175
176 // Get use slots form the use-def chain.
177 const MachineRegisterInfo &MRI = MF.getRegInfo();
178 for (MachineOperand &MO : MRI.use_nodbg_operands(Reg: CurLI->reg()))
179 if (!MO.isUndef())
180 UseSlots.push_back(Elt: LIS.getInstructionIndex(Instr: *MO.getParent()).getRegSlot());
181
182 array_pod_sort(Start: UseSlots.begin(), End: UseSlots.end());
183
184 // Remove duplicates, keeping the smaller slot for each instruction.
185 // That is what we want for early clobbers.
186 UseSlots.erase(CS: llvm::unique(R&: UseSlots, P: SlotIndex::isSameInstr),
187 CE: UseSlots.end());
188
189 // Compute per-live block info.
190 calcLiveBlockInfo();
191
192 LLVM_DEBUG(dbgs() << "Analyze counted " << UseSlots.size() << " instrs in "
193 << UseBlocks.size() << " blocks, through "
194 << NumThroughBlocks << " blocks.\n");
195}
196
197/// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
198/// where CurLI is live.
199void SplitAnalysis::calcLiveBlockInfo() {
200 ThroughBlocks.resize(N: MF.getNumBlockIDs());
201 NumThroughBlocks = NumGapBlocks = 0;
202 if (CurLI->empty())
203 return;
204
205 LiveInterval::const_iterator LVI = CurLI->begin();
206 LiveInterval::const_iterator LVE = CurLI->end();
207
208 SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
209 UseI = UseSlots.begin();
210 UseE = UseSlots.end();
211
212 // Loop over basic blocks where CurLI is live.
213 MachineFunction::iterator MFI =
214 LIS.getMBBFromIndex(index: LVI->start)->getIterator();
215 while (true) {
216 BlockInfo BI;
217 BI.MBB = &*MFI;
218 SlotIndex Start, Stop;
219 std::tie(args&: Start, args&: Stop) = LIS.getSlotIndexes()->getMBBRange(MBB: BI.MBB);
220
221 // If the block contains no uses, the range must be live through. At one
222 // point, RegisterCoalescer could create dangling ranges that ended
223 // mid-block.
224 if (UseI == UseE || *UseI >= Stop) {
225 ++NumThroughBlocks;
226 ThroughBlocks.set(BI.MBB->getNumber());
227 // The range shouldn't end mid-block if there are no uses. This shouldn't
228 // happen.
229 assert(LVI->end >= Stop && "range ends mid block with no uses");
230 } else {
231 // This block has uses. Find the first and last uses in the block.
232 BI.FirstInstr = *UseI;
233 assert(BI.FirstInstr >= Start);
234 do ++UseI;
235 while (UseI != UseE && *UseI < Stop);
236 BI.LastInstr = UseI[-1];
237 assert(BI.LastInstr < Stop);
238
239 // LVI is the first live segment overlapping MBB.
240 BI.LiveIn = LVI->start <= Start;
241
242 // When not live in, the first use should be a def.
243 if (!BI.LiveIn) {
244 assert(LVI->start == LVI->valno->def && "Dangling Segment start");
245 assert(LVI->start == BI.FirstInstr && "First instr should be a def");
246 BI.FirstDef = BI.FirstInstr;
247 }
248
249 // Look for gaps in the live range.
250 BI.LiveOut = true;
251 while (LVI->end < Stop) {
252 SlotIndex LastStop = LVI->end;
253 if (++LVI == LVE || LVI->start >= Stop) {
254 BI.LiveOut = false;
255 BI.LastInstr = LastStop;
256 break;
257 }
258
259 if (LastStop < LVI->start) {
260 // There is a gap in the live range. Create duplicate entries for the
261 // live-in snippet and the live-out snippet.
262 ++NumGapBlocks;
263
264 // Push the Live-in part.
265 BI.LiveOut = false;
266 UseBlocks.push_back(Elt: BI);
267 UseBlocks.back().LastInstr = LastStop;
268
269 // Set up BI for the live-out part.
270 BI.LiveIn = false;
271 BI.LiveOut = true;
272 BI.FirstInstr = BI.FirstDef = LVI->start;
273 }
274
275 // A Segment that starts in the middle of the block must be a def.
276 assert(LVI->start == LVI->valno->def && "Dangling Segment start");
277 if (!BI.FirstDef)
278 BI.FirstDef = LVI->start;
279 }
280
281 UseBlocks.push_back(Elt: BI);
282
283 // LVI is now at LVE or LVI->end >= Stop.
284 if (LVI == LVE)
285 break;
286 }
287
288 // Live segment ends exactly at Stop. Move to the next segment.
289 if (LVI->end == Stop && ++LVI == LVE)
290 break;
291
292 // Pick the next basic block.
293 if (LVI->start < Stop)
294 ++MFI;
295 else
296 MFI = LIS.getMBBFromIndex(index: LVI->start)->getIterator();
297 }
298
299 LooksLikeLoopIV = EnableLoopIVHeuristic && UseBlocks.size() == 2 &&
300 any_of(Range&: UseBlocks, P: [this](BlockInfo &BI) {
301 MachineLoop *L = Loops.getLoopFor(BB: BI.MBB);
302 return BI.LiveIn && BI.LiveOut && BI.FirstDef && L &&
303 L->isLoopLatch(BB: BI.MBB);
304 });
305
306 assert(getNumLiveBlocks() == countLiveBlocks(CurLI) && "Bad block count");
307}
308
309unsigned SplitAnalysis::countLiveBlocks(const LiveInterval *cli) const {
310 if (cli->empty())
311 return 0;
312 LiveInterval *li = const_cast<LiveInterval*>(cli);
313 LiveInterval::iterator LVI = li->begin();
314 LiveInterval::iterator LVE = li->end();
315 unsigned Count = 0;
316
317 // Loop over basic blocks where li is live.
318 MachineFunction::const_iterator MFI =
319 LIS.getMBBFromIndex(index: LVI->start)->getIterator();
320 SlotIndex Stop = LIS.getMBBEndIdx(mbb: &*MFI);
321 while (true) {
322 ++Count;
323 LVI = li->advanceTo(I: LVI, Pos: Stop);
324 if (LVI == LVE)
325 return Count;
326 do {
327 ++MFI;
328 Stop = LIS.getMBBEndIdx(mbb: &*MFI);
329 } while (Stop <= LVI->start);
330 }
331}
332
333bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
334 Register OrigReg = VRM.getOriginal(VirtReg: CurLI->reg());
335 const LiveInterval &Orig = LIS.getInterval(Reg: OrigReg);
336 assert(!Orig.empty() && "Splitting empty interval?");
337 LiveInterval::const_iterator I = Orig.find(Pos: Idx);
338
339 // Range containing Idx should begin at Idx.
340 if (I != Orig.end() && I->start <= Idx)
341 return I->start == Idx;
342
343 // Range does not contain Idx, previous must end at Idx.
344 return I != Orig.begin() && (--I)->end == Idx;
345}
346
347void SplitAnalysis::analyze(const LiveInterval *li) {
348 clear();
349 CurLI = li;
350 analyzeUses();
351}
352
353//===----------------------------------------------------------------------===//
354// Split Editor
355//===----------------------------------------------------------------------===//
356
357/// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
358SplitEditor::SplitEditor(SplitAnalysis &SA, LiveIntervals &LIS, VirtRegMap &VRM,
359 MachineDominatorTree &MDT,
360 MachineBlockFrequencyInfo &MBFI, VirtRegAuxInfo &VRAI)
361 : SA(SA), LIS(LIS), VRM(VRM), MRI(VRM.getMachineFunction().getRegInfo()),
362 MDT(MDT), TII(*VRM.getMachineFunction().getSubtarget().getInstrInfo()),
363 TRI(*VRM.getMachineFunction().getSubtarget().getRegisterInfo()),
364 MBFI(MBFI), VRAI(VRAI), RegAssign(Allocator) {}
365
366void SplitEditor::reset(LiveRangeEdit &LRE, ComplementSpillMode SM) {
367 Edit = &LRE;
368 SpillMode = SM;
369 OpenIdx = 0;
370 RegAssign.clear();
371 Values.clear();
372
373 // Reset the LiveIntervalCalc instances needed for this spill mode.
374 LICalc[0].reset(mf: &VRM.getMachineFunction(), SI: LIS.getSlotIndexes(), MDT: &MDT,
375 VNIA: &LIS.getVNInfoAllocator());
376 if (SpillMode)
377 LICalc[1].reset(mf: &VRM.getMachineFunction(), SI: LIS.getSlotIndexes(), MDT: &MDT,
378 VNIA: &LIS.getVNInfoAllocator());
379
380 Edit->anyRematerializable();
381}
382
383#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
384LLVM_DUMP_METHOD void SplitEditor::dump() const {
385 if (RegAssign.empty()) {
386 dbgs() << " empty\n";
387 return;
388 }
389
390 for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
391 dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
392 dbgs() << '\n';
393}
394#endif
395
396/// Find a subrange corresponding to the exact lane mask @p LM in the live
397/// interval @p LI. The interval @p LI is assumed to contain such a subrange.
398/// This function is used to find corresponding subranges between the
399/// original interval and the new intervals.
400template <typename T> auto &getSubrangeImpl(LaneBitmask LM, T &LI) {
401 for (auto &S : LI.subranges())
402 if (S.LaneMask == LM)
403 return S;
404 llvm_unreachable("SubRange for this mask not found");
405}
406
407LiveInterval::SubRange &getSubRangeForMaskExact(LaneBitmask LM,
408 LiveInterval &LI) {
409 return getSubrangeImpl(LM, LI);
410}
411
412const LiveInterval::SubRange &getSubRangeForMaskExact(LaneBitmask LM,
413 const LiveInterval &LI) {
414 return getSubrangeImpl(LM, LI);
415}
416
417/// Find a subrange corresponding to the lane mask @p LM, or a superset of it,
418/// in the live interval @p LI. The interval @p LI is assumed to contain such
419/// a subrange. This function is used to find corresponding subranges between
420/// the original interval and the new intervals.
421const LiveInterval::SubRange &getSubRangeForMask(LaneBitmask LM,
422 const LiveInterval &LI) {
423 for (const LiveInterval::SubRange &S : LI.subranges())
424 if ((S.LaneMask & LM) == LM)
425 return S;
426 llvm_unreachable("SubRange for this mask not found");
427}
428
429void SplitEditor::addDeadDef(LiveInterval &LI, VNInfo *VNI, bool Original) {
430 if (!LI.hasSubRanges()) {
431 LI.createDeadDef(VNI);
432 return;
433 }
434
435 SlotIndex Def = VNI->def;
436 if (Original) {
437 // If we are transferring a def from the original interval, make sure
438 // to only update the subranges for which the original subranges had
439 // a def at this location.
440 for (LiveInterval::SubRange &S : LI.subranges()) {
441 auto &PS = getSubRangeForMask(LM: S.LaneMask, LI: Edit->getParent());
442 VNInfo *PV = PS.getVNInfoAt(Idx: Def);
443 if (PV != nullptr && PV->def == Def)
444 S.createDeadDef(Def, VNIAlloc&: LIS.getVNInfoAllocator());
445 }
446 } else {
447 // This is a new def: either from rematerialization, or from an inserted
448 // copy. Since rematerialization can regenerate a definition of a sub-
449 // register, we need to check which subranges need to be updated.
450 const MachineInstr *DefMI = LIS.getInstructionFromIndex(index: Def);
451 assert(DefMI != nullptr);
452 LaneBitmask LM;
453 for (const MachineOperand &DefOp : DefMI->defs()) {
454 Register R = DefOp.getReg();
455 if (R != LI.reg())
456 continue;
457 if (unsigned SR = DefOp.getSubReg())
458 LM |= TRI.getSubRegIndexLaneMask(SubIdx: SR);
459 else {
460 LM = MRI.getMaxLaneMaskForVReg(Reg: R);
461 break;
462 }
463 }
464 for (LiveInterval::SubRange &S : LI.subranges())
465 if ((S.LaneMask & LM).any())
466 S.createDeadDef(Def, VNIAlloc&: LIS.getVNInfoAllocator());
467 }
468}
469
470VNInfo *SplitEditor::defValue(unsigned RegIdx,
471 const VNInfo *ParentVNI,
472 SlotIndex Idx,
473 bool Original) {
474 assert(ParentVNI && "Mapping NULL value");
475 assert(Idx.isValid() && "Invalid SlotIndex");
476 assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
477 LiveInterval *LI = &LIS.getInterval(Reg: Edit->get(idx: RegIdx));
478
479 // Create a new value.
480 VNInfo *VNI = LI->getNextValue(Def: Idx, VNInfoAllocator&: LIS.getVNInfoAllocator());
481
482 bool Force = LI->hasSubRanges();
483 ValueForcePair FP(Force ? nullptr : VNI, Force);
484 // Use insert for lookup, so we can add missing values with a second lookup.
485 std::pair<ValueMap::iterator, bool> InsP =
486 Values.insert(KV: std::make_pair(x: std::make_pair(x&: RegIdx, y: ParentVNI->id), y&: FP));
487
488 // This was the first time (RegIdx, ParentVNI) was mapped, and it is not
489 // forced. Keep it as a simple def without any liveness.
490 if (!Force && InsP.second)
491 return VNI;
492
493 // If the previous value was a simple mapping, add liveness for it now.
494 if (VNInfo *OldVNI = InsP.first->second.getPointer()) {
495 addDeadDef(LI&: *LI, VNI: OldVNI, Original);
496
497 // No longer a simple mapping. Switch to a complex mapping. If the
498 // interval has subranges, make it a forced mapping.
499 InsP.first->second = ValueForcePair(nullptr, Force);
500 }
501
502 // This is a complex mapping, add liveness for VNI
503 addDeadDef(LI&: *LI, VNI, Original);
504 return VNI;
505}
506
507void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo &ParentVNI) {
508 ValueForcePair &VFP = Values[std::make_pair(x&: RegIdx, y: ParentVNI.id)];
509 VNInfo *VNI = VFP.getPointer();
510
511 // ParentVNI was either unmapped or already complex mapped. Either way, just
512 // set the force bit.
513 if (!VNI) {
514 VFP.setInt(true);
515 return;
516 }
517
518 // This was previously a single mapping. Make sure the old def is represented
519 // by a trivial live range.
520 addDeadDef(LI&: LIS.getInterval(Reg: Edit->get(idx: RegIdx)), VNI, Original: false);
521
522 // Mark as complex mapped, forced.
523 VFP = ValueForcePair(nullptr, true);
524}
525
526SlotIndex SplitEditor::buildSingleSubRegCopy(
527 Register FromReg, Register ToReg, MachineBasicBlock &MBB,
528 MachineBasicBlock::iterator InsertBefore, unsigned SubIdx,
529 LiveInterval &DestLI, bool Late, SlotIndex Def, const MCInstrDesc &Desc) {
530 bool FirstCopy = !Def.isValid();
531 MachineInstr *CopyMI = BuildMI(BB&: MBB, I: InsertBefore, MIMD: DebugLoc(), MCID: Desc)
532 .addReg(RegNo: ToReg, flags: RegState::Define | getUndefRegState(B: FirstCopy)
533 | getInternalReadRegState(B: !FirstCopy), SubReg: SubIdx)
534 .addReg(RegNo: FromReg, flags: 0, SubReg: SubIdx);
535
536 SlotIndexes &Indexes = *LIS.getSlotIndexes();
537 if (FirstCopy) {
538 Def = Indexes.insertMachineInstrInMaps(MI&: *CopyMI, Late).getRegSlot();
539 } else {
540 CopyMI->bundleWithPred();
541 }
542 return Def;
543}
544
545SlotIndex SplitEditor::buildCopy(Register FromReg, Register ToReg,
546 LaneBitmask LaneMask, MachineBasicBlock &MBB,
547 MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) {
548 const MCInstrDesc &Desc =
549 TII.get(Opcode: TII.getLiveRangeSplitOpcode(Reg: FromReg, MF: *MBB.getParent()));
550 SlotIndexes &Indexes = *LIS.getSlotIndexes();
551 if (LaneMask.all() || LaneMask == MRI.getMaxLaneMaskForVReg(Reg: FromReg)) {
552 // The full vreg is copied.
553 MachineInstr *CopyMI =
554 BuildMI(BB&: MBB, I: InsertBefore, MIMD: DebugLoc(), MCID: Desc, DestReg: ToReg).addReg(RegNo: FromReg);
555 return Indexes.insertMachineInstrInMaps(MI&: *CopyMI, Late).getRegSlot();
556 }
557
558 // Only a subset of lanes needs to be copied. The following is a simple
559 // heuristic to construct a sequence of COPYs. We could add a target
560 // specific callback if this turns out to be suboptimal.
561 LiveInterval &DestLI = LIS.getInterval(Reg: Edit->get(idx: RegIdx));
562
563 // First pass: Try to find a perfectly matching subregister index. If none
564 // exists find the one covering the most lanemask bits.
565 const TargetRegisterClass *RC = MRI.getRegClass(Reg: FromReg);
566 assert(RC == MRI.getRegClass(ToReg) && "Should have same reg class");
567
568 SmallVector<unsigned, 8> SubIndexes;
569
570 // Abort if we cannot possibly implement the COPY with the given indexes.
571 if (!TRI.getCoveringSubRegIndexes(RC, LaneMask, Indexes&: SubIndexes))
572 report_fatal_error(reason: "Impossible to implement partial COPY");
573
574 SlotIndex Def;
575 for (unsigned BestIdx : SubIndexes) {
576 Def = buildSingleSubRegCopy(FromReg, ToReg, MBB, InsertBefore, SubIdx: BestIdx,
577 DestLI, Late, Def, Desc);
578 }
579
580 BumpPtrAllocator &Allocator = LIS.getVNInfoAllocator();
581 DestLI.refineSubRanges(
582 Allocator, LaneMask,
583 Apply: [Def, &Allocator](LiveInterval::SubRange &SR) {
584 SR.createDeadDef(Def, VNIAlloc&: Allocator);
585 },
586 Indexes, TRI);
587
588 return Def;
589}
590
591bool SplitEditor::rematWillIncreaseRestriction(const MachineInstr *DefMI,
592 MachineBasicBlock &MBB,
593 SlotIndex UseIdx) const {
594 const MachineInstr *UseMI = LIS.getInstructionFromIndex(index: UseIdx);
595 if (!UseMI)
596 return false;
597
598 // Currently code assumes rematerialization only happens for a def at 0.
599 const unsigned DefOperandIdx = 0;
600 // We want to compute the static register class constraint for the instruction
601 // def. If it is a smaller subclass than getLargestLegalSuperClass at the use
602 // site, then rematerializing it will increase the constraints.
603 const TargetRegisterClass *DefConstrainRC =
604 DefMI->getRegClassConstraint(OpIdx: DefOperandIdx, TII: &TII, TRI: &TRI);
605 if (!DefConstrainRC)
606 return false;
607
608 const TargetRegisterClass *RC = MRI.getRegClass(Reg: Edit->getReg());
609
610 // We want to find the register class that can be inflated to after the split
611 // occurs in recomputeRegClass
612 const TargetRegisterClass *SuperRC =
613 TRI.getLargestLegalSuperClass(RC, *MBB.getParent());
614
615 Register DefReg = DefMI->getOperand(i: DefOperandIdx).getReg();
616 const TargetRegisterClass *UseConstrainRC =
617 UseMI->getRegClassConstraintEffectForVReg(Reg: DefReg, CurRC: SuperRC, TII: &TII, TRI: &TRI,
618 /*ExploreBundle=*/true);
619 return UseConstrainRC->hasSubClass(RC: DefConstrainRC);
620}
621
622VNInfo *SplitEditor::defFromParent(unsigned RegIdx, const VNInfo *ParentVNI,
623 SlotIndex UseIdx, MachineBasicBlock &MBB,
624 MachineBasicBlock::iterator I) {
625 LiveInterval *LI = &LIS.getInterval(Reg: Edit->get(idx: RegIdx));
626
627 // We may be trying to avoid interference that ends at a deleted instruction,
628 // so always begin RegIdx 0 early and all others late.
629 bool Late = RegIdx != 0;
630
631 // Attempt cheap-as-a-copy rematerialization.
632 Register Original = VRM.getOriginal(VirtReg: Edit->get(idx: RegIdx));
633 LiveInterval &OrigLI = LIS.getInterval(Reg: Original);
634 VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx: UseIdx);
635
636 Register Reg = LI->reg();
637 if (OrigVNI) {
638 LiveRangeEdit::Remat RM(ParentVNI);
639 RM.OrigMI = LIS.getInstructionFromIndex(index: OrigVNI->def);
640 if (RM.OrigMI && TII.isAsCheapAsAMove(MI: *RM.OrigMI) &&
641 Edit->canRematerializeAt(RM, OrigVNI, UseIdx)) {
642 if (!rematWillIncreaseRestriction(DefMI: RM.OrigMI, MBB, UseIdx)) {
643 SlotIndex Def = Edit->rematerializeAt(MBB, MI: I, DestReg: Reg, RM, TRI, Late);
644 ++NumRemats;
645 // Define the value in Reg.
646 return defValue(RegIdx, ParentVNI, Idx: Def, Original: false);
647 }
648 LLVM_DEBUG(
649 dbgs() << "skipping rematerialize of " << printReg(Reg) << " at "
650 << UseIdx
651 << " since it will increase register class restrictions\n");
652 }
653 }
654
655 LaneBitmask LaneMask;
656 if (OrigLI.hasSubRanges()) {
657 LaneMask = LaneBitmask::getNone();
658 for (LiveInterval::SubRange &S : OrigLI.subranges()) {
659 if (S.liveAt(index: UseIdx))
660 LaneMask |= S.LaneMask;
661 }
662 } else {
663 LaneMask = LaneBitmask::getAll();
664 }
665
666 SlotIndex Def;
667 if (LaneMask.none()) {
668 const MCInstrDesc &Desc = TII.get(Opcode: TargetOpcode::IMPLICIT_DEF);
669 MachineInstr *ImplicitDef = BuildMI(BB&: MBB, I, MIMD: DebugLoc(), MCID: Desc, DestReg: Reg);
670 SlotIndexes &Indexes = *LIS.getSlotIndexes();
671 Def = Indexes.insertMachineInstrInMaps(MI&: *ImplicitDef, Late).getRegSlot();
672 } else {
673 ++NumCopies;
674 Def = buildCopy(FromReg: Edit->getReg(), ToReg: Reg, LaneMask, MBB, InsertBefore: I, Late, RegIdx);
675 }
676
677 // Define the value in Reg.
678 return defValue(RegIdx, ParentVNI, Idx: Def, Original: false);
679}
680
681/// Create a new virtual register and live interval.
682unsigned SplitEditor::openIntv() {
683 // Create the complement as index 0.
684 if (Edit->empty())
685 Edit->createEmptyInterval();
686
687 // Create the open interval.
688 OpenIdx = Edit->size();
689 Edit->createEmptyInterval();
690 return OpenIdx;
691}
692
693void SplitEditor::selectIntv(unsigned Idx) {
694 assert(Idx != 0 && "Cannot select the complement interval");
695 assert(Idx < Edit->size() && "Can only select previously opened interval");
696 LLVM_DEBUG(dbgs() << " selectIntv " << OpenIdx << " -> " << Idx << '\n');
697 OpenIdx = Idx;
698}
699
700SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
701 assert(OpenIdx && "openIntv not called before enterIntvBefore");
702 LLVM_DEBUG(dbgs() << " enterIntvBefore " << Idx);
703 Idx = Idx.getBaseIndex();
704 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
705 if (!ParentVNI) {
706 LLVM_DEBUG(dbgs() << ": not live\n");
707 return Idx;
708 }
709 LLVM_DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
710 MachineInstr *MI = LIS.getInstructionFromIndex(index: Idx);
711 assert(MI && "enterIntvBefore called with invalid index");
712
713 VNInfo *VNI = defFromParent(RegIdx: OpenIdx, ParentVNI, UseIdx: Idx, MBB&: *MI->getParent(), I: MI);
714 return VNI->def;
715}
716
717SlotIndex SplitEditor::enterIntvAfter(SlotIndex Idx) {
718 assert(OpenIdx && "openIntv not called before enterIntvAfter");
719 LLVM_DEBUG(dbgs() << " enterIntvAfter " << Idx);
720 Idx = Idx.getBoundaryIndex();
721 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
722 if (!ParentVNI) {
723 LLVM_DEBUG(dbgs() << ": not live\n");
724 return Idx;
725 }
726 LLVM_DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
727 MachineInstr *MI = LIS.getInstructionFromIndex(index: Idx);
728 assert(MI && "enterIntvAfter called with invalid index");
729
730 VNInfo *VNI = defFromParent(RegIdx: OpenIdx, ParentVNI, UseIdx: Idx, MBB&: *MI->getParent(),
731 I: std::next(x: MachineBasicBlock::iterator(MI)));
732 return VNI->def;
733}
734
735SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
736 assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
737 SlotIndex End = LIS.getMBBEndIdx(mbb: &MBB);
738 SlotIndex Last = End.getPrevSlot();
739 LLVM_DEBUG(dbgs() << " enterIntvAtEnd " << printMBBReference(MBB) << ", "
740 << Last);
741 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx: Last);
742 if (!ParentVNI) {
743 LLVM_DEBUG(dbgs() << ": not live\n");
744 return End;
745 }
746 SlotIndex LSP = SA.getLastSplitPoint(BB: &MBB);
747 if (LSP < Last) {
748 // It could be that the use after LSP is a def, and thus the ParentVNI
749 // just selected starts at that def. For this case to exist, the def
750 // must be part of a tied def/use pair (as otherwise we'd have split
751 // distinct live ranges into individual live intervals), and thus we
752 // can insert the def into the VNI of the use and the tied def/use
753 // pair can live in the resulting interval.
754 Last = LSP;
755 ParentVNI = Edit->getParent().getVNInfoAt(Idx: Last);
756 if (!ParentVNI) {
757 // undef use --> undef tied def
758 LLVM_DEBUG(dbgs() << ": tied use not live\n");
759 return End;
760 }
761 }
762
763 LLVM_DEBUG(dbgs() << ": valno " << ParentVNI->id);
764 VNInfo *VNI = defFromParent(RegIdx: OpenIdx, ParentVNI, UseIdx: Last, MBB,
765 I: SA.getLastSplitPointIter(BB: &MBB));
766 RegAssign.insert(a: VNI->def, b: End, y: OpenIdx);
767 LLVM_DEBUG(dump());
768 return VNI->def;
769}
770
771/// useIntv - indicate that all instructions in MBB should use OpenLI.
772void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
773 useIntv(Start: LIS.getMBBStartIdx(mbb: &MBB), End: LIS.getMBBEndIdx(mbb: &MBB));
774}
775
776void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
777 assert(OpenIdx && "openIntv not called before useIntv");
778 LLVM_DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):");
779 RegAssign.insert(a: Start, b: End, y: OpenIdx);
780 LLVM_DEBUG(dump());
781}
782
783SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
784 assert(OpenIdx && "openIntv not called before leaveIntvAfter");
785 LLVM_DEBUG(dbgs() << " leaveIntvAfter " << Idx);
786
787 // The interval must be live beyond the instruction at Idx.
788 SlotIndex Boundary = Idx.getBoundaryIndex();
789 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx: Boundary);
790 if (!ParentVNI) {
791 LLVM_DEBUG(dbgs() << ": not live\n");
792 return Boundary.getNextSlot();
793 }
794 LLVM_DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
795 MachineInstr *MI = LIS.getInstructionFromIndex(index: Boundary);
796 assert(MI && "No instruction at index");
797
798 // In spill mode, make live ranges as short as possible by inserting the copy
799 // before MI. This is only possible if that instruction doesn't redefine the
800 // value. The inserted COPY is not a kill, and we don't need to recompute
801 // the source live range. The spiller also won't try to hoist this copy.
802 if (SpillMode && !SlotIndex::isSameInstr(A: ParentVNI->def, B: Idx) &&
803 MI->readsVirtualRegister(Reg: Edit->getReg())) {
804 forceRecompute(RegIdx: 0, ParentVNI: *ParentVNI);
805 defFromParent(RegIdx: 0, ParentVNI, UseIdx: Idx, MBB&: *MI->getParent(), I: MI);
806 return Idx;
807 }
808
809 VNInfo *VNI = defFromParent(RegIdx: 0, ParentVNI, UseIdx: Boundary, MBB&: *MI->getParent(),
810 I: std::next(x: MachineBasicBlock::iterator(MI)));
811 return VNI->def;
812}
813
814SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
815 assert(OpenIdx && "openIntv not called before leaveIntvBefore");
816 LLVM_DEBUG(dbgs() << " leaveIntvBefore " << Idx);
817
818 // The interval must be live into the instruction at Idx.
819 Idx = Idx.getBaseIndex();
820 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
821 if (!ParentVNI) {
822 LLVM_DEBUG(dbgs() << ": not live\n");
823 return Idx.getNextSlot();
824 }
825 LLVM_DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
826
827 MachineInstr *MI = LIS.getInstructionFromIndex(index: Idx);
828 assert(MI && "No instruction at index");
829 VNInfo *VNI = defFromParent(RegIdx: 0, ParentVNI, UseIdx: Idx, MBB&: *MI->getParent(), I: MI);
830 return VNI->def;
831}
832
833SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
834 assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
835 SlotIndex Start = LIS.getMBBStartIdx(mbb: &MBB);
836 LLVM_DEBUG(dbgs() << " leaveIntvAtTop " << printMBBReference(MBB) << ", "
837 << Start);
838
839 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx: Start);
840 if (!ParentVNI) {
841 LLVM_DEBUG(dbgs() << ": not live\n");
842 return Start;
843 }
844
845 unsigned RegIdx = 0;
846 Register Reg = LIS.getInterval(Reg: Edit->get(idx: RegIdx)).reg();
847 VNInfo *VNI = defFromParent(RegIdx, ParentVNI, UseIdx: Start, MBB,
848 I: MBB.SkipPHIsLabelsAndDebug(I: MBB.begin(), Reg));
849 RegAssign.insert(a: Start, b: VNI->def, y: OpenIdx);
850 LLVM_DEBUG(dump());
851 return VNI->def;
852}
853
854static bool hasTiedUseOf(MachineInstr &MI, Register Reg) {
855 return any_of(Range: MI.defs(), P: [Reg](const MachineOperand &MO) {
856 return MO.isReg() && MO.isTied() && MO.getReg() == Reg;
857 });
858}
859
860void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
861 assert(OpenIdx && "openIntv not called before overlapIntv");
862 const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx: Start);
863 assert(ParentVNI == Edit->getParent().getVNInfoBefore(End) &&
864 "Parent changes value in extended range");
865 assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
866 "Range cannot span basic blocks");
867
868 // The complement interval will be extended as needed by LICalc.extend().
869 if (ParentVNI)
870 forceRecompute(RegIdx: 0, ParentVNI: *ParentVNI);
871
872 // If the last use is tied to a def, we can't mark it as live for the
873 // interval which includes only the use. That would cause the tied pair
874 // to end up in two different intervals.
875 if (auto *MI = LIS.getInstructionFromIndex(index: End))
876 if (hasTiedUseOf(MI&: *MI, Reg: Edit->getReg())) {
877 LLVM_DEBUG(dbgs() << "skip overlap due to tied def at end\n");
878 return;
879 }
880
881 LLVM_DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):");
882 RegAssign.insert(a: Start, b: End, y: OpenIdx);
883 LLVM_DEBUG(dump());
884}
885
886//===----------------------------------------------------------------------===//
887// Spill modes
888//===----------------------------------------------------------------------===//
889
890void SplitEditor::removeBackCopies(SmallVectorImpl<VNInfo*> &Copies) {
891 LiveInterval *LI = &LIS.getInterval(Reg: Edit->get(idx: 0));
892 LLVM_DEBUG(dbgs() << "Removing " << Copies.size() << " back-copies.\n");
893 RegAssignMap::iterator AssignI;
894 AssignI.setMap(RegAssign);
895
896 for (const VNInfo *C : Copies) {
897 SlotIndex Def = C->def;
898 MachineInstr *MI = LIS.getInstructionFromIndex(index: Def);
899 assert(MI && "No instruction for back-copy");
900
901 MachineBasicBlock *MBB = MI->getParent();
902 MachineBasicBlock::iterator MBBI(MI);
903 bool AtBegin;
904 do AtBegin = MBBI == MBB->begin();
905 while (!AtBegin && (--MBBI)->isDebugOrPseudoInstr());
906
907 LLVM_DEBUG(dbgs() << "Removing " << Def << '\t' << *MI);
908 LIS.removeVRegDefAt(LI&: *LI, Pos: Def);
909 LIS.RemoveMachineInstrFromMaps(MI&: *MI);
910 MI->eraseFromParent();
911
912 // Adjust RegAssign if a register assignment is killed at Def. We want to
913 // avoid calculating the live range of the source register if possible.
914 AssignI.find(x: Def.getPrevSlot());
915 if (!AssignI.valid() || AssignI.start() >= Def)
916 continue;
917 // If MI doesn't kill the assigned register, just leave it.
918 if (AssignI.stop() != Def)
919 continue;
920 unsigned RegIdx = AssignI.value();
921 // We could hoist back-copy right after another back-copy. As a result
922 // MMBI points to copy instruction which is actually dead now.
923 // We cannot set its stop to MBBI which will be the same as start and
924 // interval does not support that.
925 SlotIndex Kill =
926 AtBegin ? SlotIndex() : LIS.getInstructionIndex(Instr: *MBBI).getRegSlot();
927 if (AtBegin || !MBBI->readsVirtualRegister(Reg: Edit->getReg()) ||
928 Kill <= AssignI.start()) {
929 LLVM_DEBUG(dbgs() << " cannot find simple kill of RegIdx " << RegIdx
930 << '\n');
931 forceRecompute(RegIdx, ParentVNI: *Edit->getParent().getVNInfoAt(Idx: Def));
932 } else {
933 LLVM_DEBUG(dbgs() << " move kill to " << Kill << '\t' << *MBBI);
934 AssignI.setStop(Kill);
935 }
936 }
937}
938
939MachineBasicBlock*
940SplitEditor::findShallowDominator(MachineBasicBlock *MBB,
941 MachineBasicBlock *DefMBB) {
942 if (MBB == DefMBB)
943 return MBB;
944 assert(MDT.dominates(DefMBB, MBB) && "MBB must be dominated by the def.");
945
946 const MachineLoopInfo &Loops = SA.Loops;
947 const MachineLoop *DefLoop = Loops.getLoopFor(BB: DefMBB);
948 MachineDomTreeNode *DefDomNode = MDT[DefMBB];
949
950 // Best candidate so far.
951 MachineBasicBlock *BestMBB = MBB;
952 unsigned BestDepth = std::numeric_limits<unsigned>::max();
953
954 while (true) {
955 const MachineLoop *Loop = Loops.getLoopFor(BB: MBB);
956
957 // MBB isn't in a loop, it doesn't get any better. All dominators have a
958 // higher frequency by definition.
959 if (!Loop) {
960 LLVM_DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB)
961 << " dominates " << printMBBReference(*MBB)
962 << " at depth 0\n");
963 return MBB;
964 }
965
966 // We'll never be able to exit the DefLoop.
967 if (Loop == DefLoop) {
968 LLVM_DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB)
969 << " dominates " << printMBBReference(*MBB)
970 << " in the same loop\n");
971 return MBB;
972 }
973
974 // Least busy dominator seen so far.
975 unsigned Depth = Loop->getLoopDepth();
976 if (Depth < BestDepth) {
977 BestMBB = MBB;
978 BestDepth = Depth;
979 LLVM_DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB)
980 << " dominates " << printMBBReference(*MBB)
981 << " at depth " << Depth << '\n');
982 }
983
984 // Leave loop by going to the immediate dominator of the loop header.
985 // This is a bigger stride than simply walking up the dominator tree.
986 MachineDomTreeNode *IDom = MDT[Loop->getHeader()]->getIDom();
987
988 // Too far up the dominator tree?
989 if (!IDom || !MDT.dominates(A: DefDomNode, B: IDom))
990 return BestMBB;
991
992 MBB = IDom->getBlock();
993 }
994}
995
996void SplitEditor::computeRedundantBackCopies(
997 DenseSet<unsigned> &NotToHoistSet, SmallVectorImpl<VNInfo *> &BackCopies) {
998 LiveInterval *LI = &LIS.getInterval(Reg: Edit->get(idx: 0));
999 const LiveInterval *Parent = &Edit->getParent();
1000 SmallVector<SmallPtrSet<VNInfo *, 8>, 8> EqualVNs(Parent->getNumValNums());
1001 SmallPtrSet<VNInfo *, 8> DominatedVNIs;
1002
1003 // Aggregate VNIs having the same value as ParentVNI.
1004 for (VNInfo *VNI : LI->valnos) {
1005 if (VNI->isUnused())
1006 continue;
1007 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx: VNI->def);
1008 EqualVNs[ParentVNI->id].insert(Ptr: VNI);
1009 }
1010
1011 // For VNI aggregation of each ParentVNI, collect dominated, i.e.,
1012 // redundant VNIs to BackCopies.
1013 for (unsigned i = 0, e = Parent->getNumValNums(); i != e; ++i) {
1014 const VNInfo *ParentVNI = Parent->getValNumInfo(ValNo: i);
1015 if (!NotToHoistSet.count(V: ParentVNI->id))
1016 continue;
1017 SmallPtrSetIterator<VNInfo *> It1 = EqualVNs[ParentVNI->id].begin();
1018 SmallPtrSetIterator<VNInfo *> It2 = It1;
1019 for (; It1 != EqualVNs[ParentVNI->id].end(); ++It1) {
1020 It2 = It1;
1021 for (++It2; It2 != EqualVNs[ParentVNI->id].end(); ++It2) {
1022 if (DominatedVNIs.count(Ptr: *It1) || DominatedVNIs.count(Ptr: *It2))
1023 continue;
1024
1025 MachineBasicBlock *MBB1 = LIS.getMBBFromIndex(index: (*It1)->def);
1026 MachineBasicBlock *MBB2 = LIS.getMBBFromIndex(index: (*It2)->def);
1027 if (MBB1 == MBB2) {
1028 DominatedVNIs.insert(Ptr: (*It1)->def < (*It2)->def ? (*It2) : (*It1));
1029 } else if (MDT.dominates(A: MBB1, B: MBB2)) {
1030 DominatedVNIs.insert(Ptr: *It2);
1031 } else if (MDT.dominates(A: MBB2, B: MBB1)) {
1032 DominatedVNIs.insert(Ptr: *It1);
1033 }
1034 }
1035 }
1036 if (!DominatedVNIs.empty()) {
1037 forceRecompute(RegIdx: 0, ParentVNI: *ParentVNI);
1038 append_range(C&: BackCopies, R&: DominatedVNIs);
1039 DominatedVNIs.clear();
1040 }
1041 }
1042}
1043
1044/// For SM_Size mode, find a common dominator for all the back-copies for
1045/// the same ParentVNI and hoist the backcopies to the dominator BB.
1046/// For SM_Speed mode, if the common dominator is hot and it is not beneficial
1047/// to do the hoisting, simply remove the dominated backcopies for the same
1048/// ParentVNI.
1049void SplitEditor::hoistCopies() {
1050 // Get the complement interval, always RegIdx 0.
1051 LiveInterval *LI = &LIS.getInterval(Reg: Edit->get(idx: 0));
1052 const LiveInterval *Parent = &Edit->getParent();
1053
1054 // Track the nearest common dominator for all back-copies for each ParentVNI,
1055 // indexed by ParentVNI->id.
1056 using DomPair = std::pair<MachineBasicBlock *, SlotIndex>;
1057 SmallVector<DomPair, 8> NearestDom(Parent->getNumValNums());
1058 // The total cost of all the back-copies for each ParentVNI.
1059 SmallVector<BlockFrequency, 8> Costs(Parent->getNumValNums());
1060 // The ParentVNI->id set for which hoisting back-copies are not beneficial
1061 // for Speed.
1062 DenseSet<unsigned> NotToHoistSet;
1063
1064 // Find the nearest common dominator for parent values with multiple
1065 // back-copies. If a single back-copy dominates, put it in DomPair.second.
1066 for (VNInfo *VNI : LI->valnos) {
1067 if (VNI->isUnused())
1068 continue;
1069 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx: VNI->def);
1070 assert(ParentVNI && "Parent not live at complement def");
1071
1072 // Don't hoist remats. The complement is probably going to disappear
1073 // completely anyway.
1074 if (Edit->didRematerialize(ParentVNI))
1075 continue;
1076
1077 MachineBasicBlock *ValMBB = LIS.getMBBFromIndex(index: VNI->def);
1078
1079 DomPair &Dom = NearestDom[ParentVNI->id];
1080
1081 // Keep directly defined parent values. This is either a PHI or an
1082 // instruction in the complement range. All other copies of ParentVNI
1083 // should be eliminated.
1084 if (VNI->def == ParentVNI->def) {
1085 LLVM_DEBUG(dbgs() << "Direct complement def at " << VNI->def << '\n');
1086 Dom = DomPair(ValMBB, VNI->def);
1087 continue;
1088 }
1089 // Skip the singly mapped values. There is nothing to gain from hoisting a
1090 // single back-copy.
1091 if (Values.lookup(Val: std::make_pair(x: 0, y&: ParentVNI->id)).getPointer()) {
1092 LLVM_DEBUG(dbgs() << "Single complement def at " << VNI->def << '\n');
1093 continue;
1094 }
1095
1096 if (!Dom.first) {
1097 // First time we see ParentVNI. VNI dominates itself.
1098 Dom = DomPair(ValMBB, VNI->def);
1099 } else if (Dom.first == ValMBB) {
1100 // Two defs in the same block. Pick the earlier def.
1101 if (!Dom.second.isValid() || VNI->def < Dom.second)
1102 Dom.second = VNI->def;
1103 } else {
1104 // Different basic blocks. Check if one dominates.
1105 MachineBasicBlock *Near =
1106 MDT.findNearestCommonDominator(A: Dom.first, B: ValMBB);
1107 if (Near == ValMBB)
1108 // Def ValMBB dominates.
1109 Dom = DomPair(ValMBB, VNI->def);
1110 else if (Near != Dom.first)
1111 // None dominate. Hoist to common dominator, need new def.
1112 Dom = DomPair(Near, SlotIndex());
1113 Costs[ParentVNI->id] += MBFI.getBlockFreq(MBB: ValMBB);
1114 }
1115
1116 LLVM_DEBUG(dbgs() << "Multi-mapped complement " << VNI->id << '@'
1117 << VNI->def << " for parent " << ParentVNI->id << '@'
1118 << ParentVNI->def << " hoist to "
1119 << printMBBReference(*Dom.first) << ' ' << Dom.second
1120 << '\n');
1121 }
1122
1123 // Insert the hoisted copies.
1124 for (unsigned i = 0, e = Parent->getNumValNums(); i != e; ++i) {
1125 DomPair &Dom = NearestDom[i];
1126 if (!Dom.first || Dom.second.isValid())
1127 continue;
1128 // This value needs a hoisted copy inserted at the end of Dom.first.
1129 const VNInfo *ParentVNI = Parent->getValNumInfo(ValNo: i);
1130 MachineBasicBlock *DefMBB = LIS.getMBBFromIndex(index: ParentVNI->def);
1131 // Get a less loopy dominator than Dom.first.
1132 Dom.first = findShallowDominator(MBB: Dom.first, DefMBB);
1133 if (SpillMode == SM_Speed &&
1134 MBFI.getBlockFreq(MBB: Dom.first) > Costs[ParentVNI->id]) {
1135 NotToHoistSet.insert(V: ParentVNI->id);
1136 continue;
1137 }
1138 SlotIndex LSP = SA.getLastSplitPoint(BB: Dom.first);
1139 if (LSP <= ParentVNI->def) {
1140 NotToHoistSet.insert(V: ParentVNI->id);
1141 continue;
1142 }
1143 Dom.second = defFromParent(RegIdx: 0, ParentVNI, UseIdx: LSP, MBB&: *Dom.first,
1144 I: SA.getLastSplitPointIter(BB: Dom.first))->def;
1145 }
1146
1147 // Remove redundant back-copies that are now known to be dominated by another
1148 // def with the same value.
1149 SmallVector<VNInfo*, 8> BackCopies;
1150 for (VNInfo *VNI : LI->valnos) {
1151 if (VNI->isUnused())
1152 continue;
1153 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx: VNI->def);
1154 const DomPair &Dom = NearestDom[ParentVNI->id];
1155 if (!Dom.first || Dom.second == VNI->def ||
1156 NotToHoistSet.count(V: ParentVNI->id))
1157 continue;
1158 BackCopies.push_back(Elt: VNI);
1159 forceRecompute(RegIdx: 0, ParentVNI: *ParentVNI);
1160 }
1161
1162 // If it is not beneficial to hoist all the BackCopies, simply remove
1163 // redundant BackCopies in speed mode.
1164 if (SpillMode == SM_Speed && !NotToHoistSet.empty())
1165 computeRedundantBackCopies(NotToHoistSet, BackCopies);
1166
1167 removeBackCopies(Copies&: BackCopies);
1168}
1169
1170/// transferValues - Transfer all possible values to the new live ranges.
1171/// Values that were rematerialized are left alone, they need LICalc.extend().
1172bool SplitEditor::transferValues() {
1173 bool Skipped = false;
1174 RegAssignMap::const_iterator AssignI = RegAssign.begin();
1175 for (const LiveRange::Segment &S : Edit->getParent()) {
1176 LLVM_DEBUG(dbgs() << " blit " << S << ':');
1177 VNInfo *ParentVNI = S.valno;
1178 // RegAssign has holes where RegIdx 0 should be used.
1179 SlotIndex Start = S.start;
1180 AssignI.advanceTo(x: Start);
1181 do {
1182 unsigned RegIdx;
1183 SlotIndex End = S.end;
1184 if (!AssignI.valid()) {
1185 RegIdx = 0;
1186 } else if (AssignI.start() <= Start) {
1187 RegIdx = AssignI.value();
1188 if (AssignI.stop() < End) {
1189 End = AssignI.stop();
1190 ++AssignI;
1191 }
1192 } else {
1193 RegIdx = 0;
1194 End = std::min(a: End, b: AssignI.start());
1195 }
1196
1197 // The interval [Start;End) is continuously mapped to RegIdx, ParentVNI.
1198 LLVM_DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx << '('
1199 << printReg(Edit->get(RegIdx)) << ')');
1200 LiveInterval &LI = LIS.getInterval(Reg: Edit->get(idx: RegIdx));
1201
1202 // Check for a simply defined value that can be blitted directly.
1203 ValueForcePair VFP = Values.lookup(Val: std::make_pair(x&: RegIdx, y&: ParentVNI->id));
1204 if (VNInfo *VNI = VFP.getPointer()) {
1205 LLVM_DEBUG(dbgs() << ':' << VNI->id);
1206 LI.addSegment(S: LiveInterval::Segment(Start, End, VNI));
1207 Start = End;
1208 continue;
1209 }
1210
1211 // Skip values with forced recomputation.
1212 if (VFP.getInt()) {
1213 LLVM_DEBUG(dbgs() << "(recalc)");
1214 Skipped = true;
1215 Start = End;
1216 continue;
1217 }
1218
1219 LiveIntervalCalc &LIC = getLICalc(RegIdx);
1220
1221 // This value has multiple defs in RegIdx, but it wasn't rematerialized,
1222 // so the live range is accurate. Add live-in blocks in [Start;End) to the
1223 // LiveInBlocks.
1224 MachineFunction::iterator MBB = LIS.getMBBFromIndex(index: Start)->getIterator();
1225 SlotIndex BlockStart, BlockEnd;
1226 std::tie(args&: BlockStart, args&: BlockEnd) = LIS.getSlotIndexes()->getMBBRange(MBB: &*MBB);
1227
1228 // The first block may be live-in, or it may have its own def.
1229 if (Start != BlockStart) {
1230 VNInfo *VNI = LI.extendInBlock(StartIdx: BlockStart, Kill: std::min(a: BlockEnd, b: End));
1231 assert(VNI && "Missing def for complex mapped value");
1232 LLVM_DEBUG(dbgs() << ':' << VNI->id << "*" << printMBBReference(*MBB));
1233 // MBB has its own def. Is it also live-out?
1234 if (BlockEnd <= End)
1235 LIC.setLiveOutValue(MBB: &*MBB, VNI);
1236
1237 // Skip to the next block for live-in.
1238 ++MBB;
1239 BlockStart = BlockEnd;
1240 }
1241
1242 // Handle the live-in blocks covered by [Start;End).
1243 assert(Start <= BlockStart && "Expected live-in block");
1244 while (BlockStart < End) {
1245 LLVM_DEBUG(dbgs() << ">" << printMBBReference(*MBB));
1246 BlockEnd = LIS.getMBBEndIdx(mbb: &*MBB);
1247 if (BlockStart == ParentVNI->def) {
1248 // This block has the def of a parent PHI, so it isn't live-in.
1249 assert(ParentVNI->isPHIDef() && "Non-phi defined at block start?");
1250 VNInfo *VNI = LI.extendInBlock(StartIdx: BlockStart, Kill: std::min(a: BlockEnd, b: End));
1251 assert(VNI && "Missing def for complex mapped parent PHI");
1252 if (End >= BlockEnd)
1253 LIC.setLiveOutValue(MBB: &*MBB, VNI); // Live-out as well.
1254 } else {
1255 // This block needs a live-in value. The last block covered may not
1256 // be live-out.
1257 if (End < BlockEnd)
1258 LIC.addLiveInBlock(LR&: LI, DomNode: MDT[&*MBB], Kill: End);
1259 else {
1260 // Live-through, and we don't know the value.
1261 LIC.addLiveInBlock(LR&: LI, DomNode: MDT[&*MBB]);
1262 LIC.setLiveOutValue(MBB: &*MBB, VNI: nullptr);
1263 }
1264 }
1265 BlockStart = BlockEnd;
1266 ++MBB;
1267 }
1268 Start = End;
1269 } while (Start != S.end);
1270 LLVM_DEBUG(dbgs() << '\n');
1271 }
1272
1273 LICalc[0].calculateValues();
1274 if (SpillMode)
1275 LICalc[1].calculateValues();
1276
1277 return Skipped;
1278}
1279
1280static bool removeDeadSegment(SlotIndex Def, LiveRange &LR) {
1281 const LiveRange::Segment *Seg = LR.getSegmentContaining(Idx: Def);
1282 if (Seg == nullptr)
1283 return true;
1284 if (Seg->end != Def.getDeadSlot())
1285 return false;
1286 // This is a dead PHI. Remove it.
1287 LR.removeSegment(S: *Seg, RemoveDeadValNo: true);
1288 return true;
1289}
1290
1291void SplitEditor::extendPHIRange(MachineBasicBlock &B, LiveIntervalCalc &LIC,
1292 LiveRange &LR, LaneBitmask LM,
1293 ArrayRef<SlotIndex> Undefs) {
1294 for (MachineBasicBlock *P : B.predecessors()) {
1295 SlotIndex End = LIS.getMBBEndIdx(mbb: P);
1296 SlotIndex LastUse = End.getPrevSlot();
1297 // The predecessor may not have a live-out value. That is OK, like an
1298 // undef PHI operand.
1299 const LiveInterval &PLI = Edit->getParent();
1300 // Need the cast because the inputs to ?: would otherwise be deemed
1301 // "incompatible": SubRange vs LiveInterval.
1302 const LiveRange &PSR = !LM.all() ? getSubRangeForMaskExact(LM, LI: PLI)
1303 : static_cast<const LiveRange &>(PLI);
1304 if (PSR.liveAt(index: LastUse))
1305 LIC.extend(LR, Use: End, /*PhysReg=*/0, Undefs);
1306 }
1307}
1308
1309void SplitEditor::extendPHIKillRanges() {
1310 // Extend live ranges to be live-out for successor PHI values.
1311
1312 // Visit each PHI def slot in the parent live interval. If the def is dead,
1313 // remove it. Otherwise, extend the live interval to reach the end indexes
1314 // of all predecessor blocks.
1315
1316 const LiveInterval &ParentLI = Edit->getParent();
1317 for (const VNInfo *V : ParentLI.valnos) {
1318 if (V->isUnused() || !V->isPHIDef())
1319 continue;
1320
1321 unsigned RegIdx = RegAssign.lookup(x: V->def);
1322 LiveInterval &LI = LIS.getInterval(Reg: Edit->get(idx: RegIdx));
1323 LiveIntervalCalc &LIC = getLICalc(RegIdx);
1324 MachineBasicBlock &B = *LIS.getMBBFromIndex(index: V->def);
1325 if (!removeDeadSegment(Def: V->def, LR&: LI))
1326 extendPHIRange(B, LIC, LR&: LI, LM: LaneBitmask::getAll(), /*Undefs=*/{});
1327 }
1328
1329 SmallVector<SlotIndex, 4> Undefs;
1330 LiveIntervalCalc SubLIC;
1331
1332 for (const LiveInterval::SubRange &PS : ParentLI.subranges()) {
1333 for (const VNInfo *V : PS.valnos) {
1334 if (V->isUnused() || !V->isPHIDef())
1335 continue;
1336 unsigned RegIdx = RegAssign.lookup(x: V->def);
1337 LiveInterval &LI = LIS.getInterval(Reg: Edit->get(idx: RegIdx));
1338 LiveInterval::SubRange &S = getSubRangeForMaskExact(LM: PS.LaneMask, LI);
1339 if (removeDeadSegment(Def: V->def, LR&: S))
1340 continue;
1341
1342 MachineBasicBlock &B = *LIS.getMBBFromIndex(index: V->def);
1343 SubLIC.reset(mf: &VRM.getMachineFunction(), SI: LIS.getSlotIndexes(), MDT: &MDT,
1344 VNIA: &LIS.getVNInfoAllocator());
1345 Undefs.clear();
1346 LI.computeSubRangeUndefs(Undefs, LaneMask: PS.LaneMask, MRI, Indexes: *LIS.getSlotIndexes());
1347 extendPHIRange(B, LIC&: SubLIC, LR&: S, LM: PS.LaneMask, Undefs);
1348 }
1349 }
1350}
1351
1352/// rewriteAssigned - Rewrite all uses of Edit->getReg().
1353void SplitEditor::rewriteAssigned(bool ExtendRanges) {
1354 struct ExtPoint {
1355 ExtPoint(const MachineOperand &O, unsigned R, SlotIndex N)
1356 : MO(O), RegIdx(R), Next(N) {}
1357
1358 MachineOperand MO;
1359 unsigned RegIdx;
1360 SlotIndex Next;
1361 };
1362
1363 SmallVector<ExtPoint,4> ExtPoints;
1364
1365 for (MachineOperand &MO :
1366 llvm::make_early_inc_range(Range: MRI.reg_operands(Reg: Edit->getReg()))) {
1367 MachineInstr *MI = MO.getParent();
1368 // LiveDebugVariables should have handled all DBG_VALUE instructions.
1369 if (MI->isDebugValue()) {
1370 LLVM_DEBUG(dbgs() << "Zapping " << *MI);
1371 MO.setReg(0);
1372 continue;
1373 }
1374
1375 // <undef> operands don't really read the register, so it doesn't matter
1376 // which register we choose. When the use operand is tied to a def, we must
1377 // use the same register as the def, so just do that always.
1378 SlotIndex Idx = LIS.getInstructionIndex(Instr: *MI);
1379 if (MO.isDef() || MO.isUndef())
1380 Idx = Idx.getRegSlot(EC: MO.isEarlyClobber());
1381
1382 // Rewrite to the mapped register at Idx.
1383 unsigned RegIdx = RegAssign.lookup(x: Idx);
1384 LiveInterval &LI = LIS.getInterval(Reg: Edit->get(idx: RegIdx));
1385 MO.setReg(LI.reg());
1386 LLVM_DEBUG(dbgs() << " rewr " << printMBBReference(*MI->getParent())
1387 << '\t' << Idx << ':' << RegIdx << '\t' << *MI);
1388
1389 // Extend liveness to Idx if the instruction reads reg.
1390 if (!ExtendRanges || MO.isUndef())
1391 continue;
1392
1393 // Skip instructions that don't read Reg.
1394 if (MO.isDef()) {
1395 if (!MO.getSubReg() && !MO.isEarlyClobber())
1396 continue;
1397 // We may want to extend a live range for a partial redef, or for a use
1398 // tied to an early clobber.
1399 if (!Edit->getParent().liveAt(index: Idx.getPrevSlot()))
1400 continue;
1401 } else {
1402 assert(MO.isUse());
1403 bool IsEarlyClobber = false;
1404 if (MO.isTied()) {
1405 // We want to extend a live range into `e` slot rather than `r` slot if
1406 // tied-def is early clobber, because the `e` slot already contained
1407 // in the live range of early-clobber tied-def operand, give an example
1408 // here:
1409 // 0 %0 = ...
1410 // 16 early-clobber %0 = Op %0 (tied-def 0), ...
1411 // 32 ... = Op %0
1412 // Before extend:
1413 // %0 = [0r, 0d) [16e, 32d)
1414 // The point we want to extend is 0d to 16e not 16r in this case, but if
1415 // we use 16r here we will extend nothing because that already contained
1416 // in [16e, 32d).
1417 unsigned OpIdx = MO.getOperandNo();
1418 unsigned DefOpIdx = MI->findTiedOperandIdx(OpIdx);
1419 const MachineOperand &DefOp = MI->getOperand(i: DefOpIdx);
1420 IsEarlyClobber = DefOp.isEarlyClobber();
1421 }
1422
1423 Idx = Idx.getRegSlot(EC: IsEarlyClobber);
1424 }
1425
1426 SlotIndex Next = Idx;
1427 if (LI.hasSubRanges()) {
1428 // We have to delay extending subranges until we have seen all operands
1429 // defining the register. This is because a <def,read-undef> operand
1430 // will create an "undef" point, and we cannot extend any subranges
1431 // until all of them have been accounted for.
1432 if (MO.isUse())
1433 ExtPoints.push_back(Elt: ExtPoint(MO, RegIdx, Next));
1434 } else {
1435 LiveIntervalCalc &LIC = getLICalc(RegIdx);
1436 LIC.extend(LR&: LI, Use: Next, PhysReg: 0, Undefs: ArrayRef<SlotIndex>());
1437 }
1438 }
1439
1440 for (ExtPoint &EP : ExtPoints) {
1441 LiveInterval &LI = LIS.getInterval(Reg: Edit->get(idx: EP.RegIdx));
1442 assert(LI.hasSubRanges());
1443
1444 LiveIntervalCalc SubLIC;
1445 Register Reg = EP.MO.getReg();
1446 unsigned Sub = EP.MO.getSubReg();
1447 LaneBitmask LM = Sub != 0 ? TRI.getSubRegIndexLaneMask(SubIdx: Sub)
1448 : MRI.getMaxLaneMaskForVReg(Reg);
1449 for (LiveInterval::SubRange &S : LI.subranges()) {
1450 if ((S.LaneMask & LM).none())
1451 continue;
1452 // The problem here can be that the new register may have been created
1453 // for a partially defined original register. For example:
1454 // %0:subreg_hireg<def,read-undef> = ...
1455 // ...
1456 // %1 = COPY %0
1457 if (S.empty())
1458 continue;
1459 SubLIC.reset(mf: &VRM.getMachineFunction(), SI: LIS.getSlotIndexes(), MDT: &MDT,
1460 VNIA: &LIS.getVNInfoAllocator());
1461 SmallVector<SlotIndex, 4> Undefs;
1462 LI.computeSubRangeUndefs(Undefs, LaneMask: S.LaneMask, MRI, Indexes: *LIS.getSlotIndexes());
1463 SubLIC.extend(LR&: S, Use: EP.Next, PhysReg: 0, Undefs);
1464 }
1465 }
1466
1467 for (Register R : *Edit) {
1468 LiveInterval &LI = LIS.getInterval(Reg: R);
1469 if (!LI.hasSubRanges())
1470 continue;
1471 LI.clear();
1472 LI.removeEmptySubRanges();
1473 LIS.constructMainRangeFromSubranges(LI);
1474 }
1475}
1476
1477void SplitEditor::deleteRematVictims() {
1478 SmallVector<MachineInstr*, 8> Dead;
1479 for (const Register &R : *Edit) {
1480 LiveInterval *LI = &LIS.getInterval(Reg: R);
1481 for (const LiveRange::Segment &S : LI->segments) {
1482 // Dead defs end at the dead slot.
1483 if (S.end != S.valno->def.getDeadSlot())
1484 continue;
1485 if (S.valno->isPHIDef())
1486 continue;
1487 MachineInstr *MI = LIS.getInstructionFromIndex(index: S.valno->def);
1488 assert(MI && "Missing instruction for dead def");
1489 MI->addRegisterDead(Reg: LI->reg(), RegInfo: &TRI);
1490
1491 if (!MI->allDefsAreDead())
1492 continue;
1493
1494 LLVM_DEBUG(dbgs() << "All defs dead: " << *MI);
1495 Dead.push_back(Elt: MI);
1496 }
1497 }
1498
1499 if (Dead.empty())
1500 return;
1501
1502 Edit->eliminateDeadDefs(Dead, RegsBeingSpilled: {});
1503}
1504
1505void SplitEditor::forceRecomputeVNI(const VNInfo &ParentVNI) {
1506 // Fast-path for common case.
1507 if (!ParentVNI.isPHIDef()) {
1508 for (unsigned I = 0, E = Edit->size(); I != E; ++I)
1509 forceRecompute(RegIdx: I, ParentVNI);
1510 return;
1511 }
1512
1513 // Trace value through phis.
1514 SmallPtrSet<const VNInfo *, 8> Visited; ///< whether VNI was/is in worklist.
1515 SmallVector<const VNInfo *, 4> WorkList;
1516 Visited.insert(Ptr: &ParentVNI);
1517 WorkList.push_back(Elt: &ParentVNI);
1518
1519 const LiveInterval &ParentLI = Edit->getParent();
1520 const SlotIndexes &Indexes = *LIS.getSlotIndexes();
1521 do {
1522 const VNInfo &VNI = *WorkList.pop_back_val();
1523 for (unsigned I = 0, E = Edit->size(); I != E; ++I)
1524 forceRecompute(RegIdx: I, ParentVNI: VNI);
1525 if (!VNI.isPHIDef())
1526 continue;
1527
1528 MachineBasicBlock &MBB = *Indexes.getMBBFromIndex(index: VNI.def);
1529 for (const MachineBasicBlock *Pred : MBB.predecessors()) {
1530 SlotIndex PredEnd = Indexes.getMBBEndIdx(mbb: Pred);
1531 VNInfo *PredVNI = ParentLI.getVNInfoBefore(Idx: PredEnd);
1532 assert(PredVNI && "Value available in PhiVNI predecessor");
1533 if (Visited.insert(Ptr: PredVNI).second)
1534 WorkList.push_back(Elt: PredVNI);
1535 }
1536 } while(!WorkList.empty());
1537}
1538
1539void SplitEditor::finish(SmallVectorImpl<unsigned> *LRMap) {
1540 ++NumFinished;
1541
1542 // At this point, the live intervals in Edit contain VNInfos corresponding to
1543 // the inserted copies.
1544
1545 // Add the original defs from the parent interval.
1546 for (const VNInfo *ParentVNI : Edit->getParent().valnos) {
1547 if (ParentVNI->isUnused())
1548 continue;
1549 unsigned RegIdx = RegAssign.lookup(x: ParentVNI->def);
1550 defValue(RegIdx, ParentVNI, Idx: ParentVNI->def, Original: true);
1551
1552 // Force rematted values to be recomputed everywhere.
1553 // The new live ranges may be truncated.
1554 if (Edit->didRematerialize(ParentVNI))
1555 forceRecomputeVNI(ParentVNI: *ParentVNI);
1556 }
1557
1558 // Hoist back-copies to the complement interval when in spill mode.
1559 switch (SpillMode) {
1560 case SM_Partition:
1561 // Leave all back-copies as is.
1562 break;
1563 case SM_Size:
1564 case SM_Speed:
1565 // hoistCopies will behave differently between size and speed.
1566 hoistCopies();
1567 }
1568
1569 // Transfer the simply mapped values, check if any are skipped.
1570 bool Skipped = transferValues();
1571
1572 // Rewrite virtual registers, possibly extending ranges.
1573 rewriteAssigned(ExtendRanges: Skipped);
1574
1575 if (Skipped)
1576 extendPHIKillRanges();
1577 else
1578 ++NumSimple;
1579
1580 // Delete defs that were rematted everywhere.
1581 if (Skipped)
1582 deleteRematVictims();
1583
1584 // Get rid of unused values and set phi-kill flags.
1585 for (Register Reg : *Edit) {
1586 LiveInterval &LI = LIS.getInterval(Reg);
1587 LI.removeEmptySubRanges();
1588 LI.RenumberValues();
1589 }
1590
1591 // Provide a reverse mapping from original indices to Edit ranges.
1592 if (LRMap) {
1593 auto Seq = llvm::seq<unsigned>(Begin: 0, End: Edit->size());
1594 LRMap->assign(in_start: Seq.begin(), in_end: Seq.end());
1595 }
1596
1597 // Now check if any registers were separated into multiple components.
1598 ConnectedVNInfoEqClasses ConEQ(LIS);
1599 for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
1600 // Don't use iterators, they are invalidated by create() below.
1601 Register VReg = Edit->get(idx: i);
1602 LiveInterval &LI = LIS.getInterval(Reg: VReg);
1603 SmallVector<LiveInterval*, 8> SplitLIs;
1604 LIS.splitSeparateComponents(LI, SplitLIs);
1605 Register Original = VRM.getOriginal(VirtReg: VReg);
1606 for (LiveInterval *SplitLI : SplitLIs)
1607 VRM.setIsSplitFromReg(virtReg: SplitLI->reg(), SReg: Original);
1608
1609 // The new intervals all map back to i.
1610 if (LRMap)
1611 LRMap->resize(N: Edit->size(), NV: i);
1612 }
1613
1614 // Calculate spill weight and allocation hints for new intervals.
1615 Edit->calculateRegClassAndHint(VRM.getMachineFunction(), VRAI);
1616
1617 assert(!LRMap || LRMap->size() == Edit->size());
1618}
1619
1620//===----------------------------------------------------------------------===//
1621// Single Block Splitting
1622//===----------------------------------------------------------------------===//
1623
1624bool SplitAnalysis::shouldSplitSingleBlock(const BlockInfo &BI,
1625 bool SingleInstrs) const {
1626 // Always split for multiple instructions.
1627 if (!BI.isOneInstr())
1628 return true;
1629 // Don't split for single instructions unless explicitly requested.
1630 if (!SingleInstrs)
1631 return false;
1632 // Splitting a live-through range always makes progress.
1633 if (BI.LiveIn && BI.LiveOut)
1634 return true;
1635 // No point in isolating a copy. It has no register class constraints.
1636 MachineInstr *MI = LIS.getInstructionFromIndex(index: BI.FirstInstr);
1637 bool copyLike = TII.isCopyInstr(MI: *MI) || MI->isSubregToReg();
1638 if (copyLike)
1639 return false;
1640 // Finally, don't isolate an end point that was created by earlier splits.
1641 return isOriginalEndpoint(Idx: BI.FirstInstr);
1642}
1643
1644void SplitEditor::splitSingleBlock(const SplitAnalysis::BlockInfo &BI) {
1645 openIntv();
1646 SlotIndex LastSplitPoint = SA.getLastSplitPoint(BB: BI.MBB);
1647 SlotIndex SegStart = enterIntvBefore(Idx: std::min(a: BI.FirstInstr,
1648 b: LastSplitPoint));
1649 if (!BI.LiveOut || BI.LastInstr < LastSplitPoint) {
1650 useIntv(Start: SegStart, End: leaveIntvAfter(Idx: BI.LastInstr));
1651 } else {
1652 // The last use is after the last valid split point.
1653 SlotIndex SegStop = leaveIntvBefore(Idx: LastSplitPoint);
1654 useIntv(Start: SegStart, End: SegStop);
1655 overlapIntv(Start: SegStop, End: BI.LastInstr);
1656 }
1657}
1658
1659//===----------------------------------------------------------------------===//
1660// Global Live Range Splitting Support
1661//===----------------------------------------------------------------------===//
1662
1663// These methods support a method of global live range splitting that uses a
1664// global algorithm to decide intervals for CFG edges. They will insert split
1665// points and color intervals in basic blocks while avoiding interference.
1666//
1667// Note that splitSingleBlock is also useful for blocks where both CFG edges
1668// are on the stack.
1669
1670void SplitEditor::splitLiveThroughBlock(unsigned MBBNum,
1671 unsigned IntvIn, SlotIndex LeaveBefore,
1672 unsigned IntvOut, SlotIndex EnterAfter){
1673 SlotIndex Start, Stop;
1674 std::tie(args&: Start, args&: Stop) = LIS.getSlotIndexes()->getMBBRange(Num: MBBNum);
1675
1676 LLVM_DEBUG(dbgs() << "%bb." << MBBNum << " [" << Start << ';' << Stop
1677 << ") intf " << LeaveBefore << '-' << EnterAfter
1678 << ", live-through " << IntvIn << " -> " << IntvOut);
1679
1680 assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks");
1681
1682 assert((!LeaveBefore || LeaveBefore < Stop) && "Interference after block");
1683 assert((!IntvIn || !LeaveBefore || LeaveBefore > Start) && "Impossible intf");
1684 assert((!EnterAfter || EnterAfter >= Start) && "Interference before block");
1685
1686 MachineBasicBlock *MBB = VRM.getMachineFunction().getBlockNumbered(N: MBBNum);
1687
1688 if (!IntvOut) {
1689 LLVM_DEBUG(dbgs() << ", spill on entry.\n");
1690 //
1691 // <<<<<<<<< Possible LeaveBefore interference.
1692 // |-----------| Live through.
1693 // -____________ Spill on entry.
1694 //
1695 selectIntv(Idx: IntvIn);
1696 SlotIndex Idx = leaveIntvAtTop(MBB&: *MBB);
1697 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1698 (void)Idx;
1699 return;
1700 }
1701
1702 if (!IntvIn) {
1703 LLVM_DEBUG(dbgs() << ", reload on exit.\n");
1704 //
1705 // >>>>>>> Possible EnterAfter interference.
1706 // |-----------| Live through.
1707 // ___________-- Reload on exit.
1708 //
1709 selectIntv(Idx: IntvOut);
1710 SlotIndex Idx = enterIntvAtEnd(MBB&: *MBB);
1711 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1712 (void)Idx;
1713 return;
1714 }
1715
1716 if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) {
1717 LLVM_DEBUG(dbgs() << ", straight through.\n");
1718 //
1719 // |-----------| Live through.
1720 // ------------- Straight through, same intv, no interference.
1721 //
1722 selectIntv(Idx: IntvOut);
1723 useIntv(Start, End: Stop);
1724 return;
1725 }
1726
1727 // We cannot legally insert splits after LSP.
1728 SlotIndex LSP = SA.getLastSplitPoint(Num: MBBNum);
1729 assert((!IntvOut || !EnterAfter || EnterAfter < LSP) && "Impossible intf");
1730
1731 if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter ||
1732 LeaveBefore.getBaseIndex() > EnterAfter.getBoundaryIndex())) {
1733 LLVM_DEBUG(dbgs() << ", switch avoiding interference.\n");
1734 //
1735 // >>>> <<<< Non-overlapping EnterAfter/LeaveBefore interference.
1736 // |-----------| Live through.
1737 // ------======= Switch intervals between interference.
1738 //
1739 selectIntv(Idx: IntvOut);
1740 SlotIndex Idx;
1741 if (LeaveBefore && LeaveBefore < LSP) {
1742 Idx = enterIntvBefore(Idx: LeaveBefore);
1743 useIntv(Start: Idx, End: Stop);
1744 } else {
1745 Idx = enterIntvAtEnd(MBB&: *MBB);
1746 }
1747 selectIntv(Idx: IntvIn);
1748 useIntv(Start, End: Idx);
1749 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1750 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1751 return;
1752 }
1753
1754 LLVM_DEBUG(dbgs() << ", create local intv for interference.\n");
1755 //
1756 // >>><><><><<<< Overlapping EnterAfter/LeaveBefore interference.
1757 // |-----------| Live through.
1758 // ==---------== Switch intervals before/after interference.
1759 //
1760 assert(LeaveBefore <= EnterAfter && "Missed case");
1761
1762 selectIntv(Idx: IntvOut);
1763 SlotIndex Idx = enterIntvAfter(Idx: EnterAfter);
1764 useIntv(Start: Idx, End: Stop);
1765 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1766
1767 selectIntv(Idx: IntvIn);
1768 Idx = leaveIntvBefore(Idx: LeaveBefore);
1769 useIntv(Start, End: Idx);
1770 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1771}
1772
1773void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI,
1774 unsigned IntvIn, SlotIndex LeaveBefore) {
1775 SlotIndex Start, Stop;
1776 std::tie(args&: Start, args&: Stop) = LIS.getSlotIndexes()->getMBBRange(MBB: BI.MBB);
1777
1778 LLVM_DEBUG(dbgs() << printMBBReference(*BI.MBB) << " [" << Start << ';'
1779 << Stop << "), uses " << BI.FirstInstr << '-'
1780 << BI.LastInstr << ", reg-in " << IntvIn
1781 << ", leave before " << LeaveBefore
1782 << (BI.LiveOut ? ", stack-out" : ", killed in block"));
1783
1784 assert(IntvIn && "Must have register in");
1785 assert(BI.LiveIn && "Must be live-in");
1786 assert((!LeaveBefore || LeaveBefore > Start) && "Bad interference");
1787
1788 if (!BI.LiveOut && (!LeaveBefore || LeaveBefore >= BI.LastInstr)) {
1789 LLVM_DEBUG(dbgs() << " before interference.\n");
1790 //
1791 // <<< Interference after kill.
1792 // |---o---x | Killed in block.
1793 // ========= Use IntvIn everywhere.
1794 //
1795 selectIntv(Idx: IntvIn);
1796 useIntv(Start, End: BI.LastInstr);
1797 return;
1798 }
1799
1800 SlotIndex LSP = SA.getLastSplitPoint(BB: BI.MBB);
1801
1802 if (!LeaveBefore || LeaveBefore > BI.LastInstr.getBoundaryIndex()) {
1803 //
1804 // <<< Possible interference after last use.
1805 // |---o---o---| Live-out on stack.
1806 // =========____ Leave IntvIn after last use.
1807 //
1808 // < Interference after last use.
1809 // |---o---o--o| Live-out on stack, late last use.
1810 // ============ Copy to stack after LSP, overlap IntvIn.
1811 // \_____ Stack interval is live-out.
1812 //
1813 if (BI.LastInstr < LSP) {
1814 LLVM_DEBUG(dbgs() << ", spill after last use before interference.\n");
1815 selectIntv(Idx: IntvIn);
1816 SlotIndex Idx = leaveIntvAfter(Idx: BI.LastInstr);
1817 useIntv(Start, End: Idx);
1818 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1819 } else {
1820 LLVM_DEBUG(dbgs() << ", spill before last split point.\n");
1821 selectIntv(Idx: IntvIn);
1822 SlotIndex Idx = leaveIntvBefore(Idx: LSP);
1823 overlapIntv(Start: Idx, End: BI.LastInstr);
1824 useIntv(Start, End: Idx);
1825 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1826 }
1827 return;
1828 }
1829
1830 // The interference is overlapping somewhere we wanted to use IntvIn. That
1831 // means we need to create a local interval that can be allocated a
1832 // different register.
1833 unsigned LocalIntv = openIntv();
1834 (void)LocalIntv;
1835 LLVM_DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n");
1836
1837 if (!BI.LiveOut || BI.LastInstr < LSP) {
1838 //
1839 // <<<<<<< Interference overlapping uses.
1840 // |---o---o---| Live-out on stack.
1841 // =====----____ Leave IntvIn before interference, then spill.
1842 //
1843 SlotIndex To = leaveIntvAfter(Idx: BI.LastInstr);
1844 SlotIndex From = enterIntvBefore(Idx: LeaveBefore);
1845 useIntv(Start: From, End: To);
1846 selectIntv(Idx: IntvIn);
1847 useIntv(Start, End: From);
1848 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1849 return;
1850 }
1851
1852 // <<<<<<< Interference overlapping uses.
1853 // |---o---o--o| Live-out on stack, late last use.
1854 // =====------- Copy to stack before LSP, overlap LocalIntv.
1855 // \_____ Stack interval is live-out.
1856 //
1857 SlotIndex To = leaveIntvBefore(Idx: LSP);
1858 overlapIntv(Start: To, End: BI.LastInstr);
1859 SlotIndex From = enterIntvBefore(Idx: std::min(a: To, b: LeaveBefore));
1860 useIntv(Start: From, End: To);
1861 selectIntv(Idx: IntvIn);
1862 useIntv(Start, End: From);
1863 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1864}
1865
1866void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI,
1867 unsigned IntvOut, SlotIndex EnterAfter) {
1868 SlotIndex Start, Stop;
1869 std::tie(args&: Start, args&: Stop) = LIS.getSlotIndexes()->getMBBRange(MBB: BI.MBB);
1870
1871 LLVM_DEBUG(dbgs() << printMBBReference(*BI.MBB) << " [" << Start << ';'
1872 << Stop << "), uses " << BI.FirstInstr << '-'
1873 << BI.LastInstr << ", reg-out " << IntvOut
1874 << ", enter after " << EnterAfter
1875 << (BI.LiveIn ? ", stack-in" : ", defined in block"));
1876
1877 SlotIndex LSP = SA.getLastSplitPoint(BB: BI.MBB);
1878
1879 assert(IntvOut && "Must have register out");
1880 assert(BI.LiveOut && "Must be live-out");
1881 assert((!EnterAfter || EnterAfter < LSP) && "Bad interference");
1882
1883 if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstInstr)) {
1884 LLVM_DEBUG(dbgs() << " after interference.\n");
1885 //
1886 // >>>> Interference before def.
1887 // | o---o---| Defined in block.
1888 // ========= Use IntvOut everywhere.
1889 //
1890 selectIntv(Idx: IntvOut);
1891 useIntv(Start: BI.FirstInstr, End: Stop);
1892 return;
1893 }
1894
1895 if (!EnterAfter || EnterAfter < BI.FirstInstr.getBaseIndex()) {
1896 LLVM_DEBUG(dbgs() << ", reload after interference.\n");
1897 //
1898 // >>>> Interference before def.
1899 // |---o---o---| Live-through, stack-in.
1900 // ____========= Enter IntvOut before first use.
1901 //
1902 selectIntv(Idx: IntvOut);
1903 SlotIndex Idx = enterIntvBefore(Idx: std::min(a: LSP, b: BI.FirstInstr));
1904 useIntv(Start: Idx, End: Stop);
1905 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1906 return;
1907 }
1908
1909 // The interference is overlapping somewhere we wanted to use IntvOut. That
1910 // means we need to create a local interval that can be allocated a
1911 // different register.
1912 LLVM_DEBUG(dbgs() << ", interference overlaps uses.\n");
1913 //
1914 // >>>>>>> Interference overlapping uses.
1915 // |---o---o---| Live-through, stack-in.
1916 // ____---====== Create local interval for interference range.
1917 //
1918 selectIntv(Idx: IntvOut);
1919 SlotIndex Idx = enterIntvAfter(Idx: EnterAfter);
1920 useIntv(Start: Idx, End: Stop);
1921 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1922
1923 openIntv();
1924 SlotIndex From = enterIntvBefore(Idx: std::min(a: Idx, b: BI.FirstInstr));
1925 useIntv(Start: From, End: Idx);
1926}
1927
1928void SplitAnalysis::BlockInfo::print(raw_ostream &OS) const {
1929 OS << "{" << printMBBReference(MBB: *MBB) << ", "
1930 << "uses " << FirstInstr << " to " << LastInstr << ", "
1931 << "1st def " << FirstDef << ", "
1932 << (LiveIn ? "live in" : "dead in") << ", "
1933 << (LiveOut ? "live out" : "dead out") << "}";
1934}
1935
1936void SplitAnalysis::BlockInfo::dump() const {
1937 print(OS&: dbgs());
1938 dbgs() << "\n";
1939}
1940