1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "ARMBaseInstrInfo.h"
10#include "MCTargetDesc/ARMAddressingModes.h"
11#include "MCTargetDesc/ARMBaseInfo.h"
12#include "MCTargetDesc/ARMMCTargetDesc.h"
13#include "TargetInfo/ARMTargetInfo.h"
14#include "Utils/ARMBaseInfo.h"
15#include "llvm/MC/MCContext.h"
16#include "llvm/MC/MCDecoderOps.h"
17#include "llvm/MC/MCDisassembler/MCDisassembler.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCInstrDesc.h"
20#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/MC/MCSubtargetInfo.h"
22#include "llvm/MC/TargetRegistry.h"
23#include "llvm/Support/Compiler.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/raw_ostream.h"
27#include "llvm/TargetParser/SubtargetFeature.h"
28#include <algorithm>
29#include <cassert>
30#include <cstdint>
31#include <vector>
32
33using namespace llvm;
34
35#define DEBUG_TYPE "arm-disassembler"
36
37using DecodeStatus = MCDisassembler::DecodeStatus;
38
39namespace {
40
41 // Handles the condition code status of instructions in IT blocks
42 class ITStatus
43 {
44 public:
45 // Returns the condition code for instruction in IT block
46 unsigned getITCC() {
47 unsigned CC = ARMCC::AL;
48 if (instrInITBlock())
49 CC = ITStates.back();
50 return CC;
51 }
52
53 // Advances the IT block state to the next T or E
54 void advanceITState() {
55 ITStates.pop_back();
56 }
57
58 // Returns true if the current instruction is in an IT block
59 bool instrInITBlock() {
60 return !ITStates.empty();
61 }
62
63 // Returns true if current instruction is the last instruction in an IT block
64 bool instrLastInITBlock() {
65 return ITStates.size() == 1;
66 }
67
68 // Called when decoding an IT instruction. Sets the IT state for
69 // the following instructions that for the IT block. Firstcond
70 // corresponds to the field in the IT instruction encoding; Mask
71 // is in the MCOperand format in which 1 means 'else' and 0 'then'.
72 void setITState(char Firstcond, char Mask) {
73 // (3 - the number of trailing zeros) is the number of then / else.
74 unsigned NumTZ = llvm::countr_zero<uint8_t>(Val: Mask);
75 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
76 assert(NumTZ <= 3 && "Invalid IT mask!");
77 // push condition codes onto the stack the correct order for the pops
78 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
79 unsigned Else = (Mask >> Pos) & 1;
80 ITStates.push_back(x: CCBits ^ Else);
81 }
82 ITStates.push_back(x: CCBits);
83 }
84
85 private:
86 std::vector<unsigned char> ITStates;
87 };
88
89 class VPTStatus
90 {
91 public:
92 unsigned getVPTPred() {
93 unsigned Pred = ARMVCC::None;
94 if (instrInVPTBlock())
95 Pred = VPTStates.back();
96 return Pred;
97 }
98
99 void advanceVPTState() {
100 VPTStates.pop_back();
101 }
102
103 bool instrInVPTBlock() {
104 return !VPTStates.empty();
105 }
106
107 bool instrLastInVPTBlock() {
108 return VPTStates.size() == 1;
109 }
110
111 void setVPTState(char Mask) {
112 // (3 - the number of trailing zeros) is the number of then / else.
113 unsigned NumTZ = llvm::countr_zero<uint8_t>(Val: Mask);
114 assert(NumTZ <= 3 && "Invalid VPT mask!");
115 // push predicates onto the stack the correct order for the pops
116 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
117 bool T = ((Mask >> Pos) & 1) == 0;
118 if (T)
119 VPTStates.push_back(Elt: ARMVCC::Then);
120 else
121 VPTStates.push_back(Elt: ARMVCC::Else);
122 }
123 VPTStates.push_back(Elt: ARMVCC::Then);
124 }
125
126 private:
127 SmallVector<unsigned char, 4> VPTStates;
128 };
129
130/// ARM disassembler for all ARM platforms.
131class ARMDisassembler : public MCDisassembler {
132public:
133 std::unique_ptr<const MCInstrInfo> MCII;
134
135 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
136 const MCInstrInfo *MCII)
137 : MCDisassembler(STI, Ctx), MCII(MCII) {
138 InstructionEndianness = STI.hasFeature(Feature: ARM::ModeBigEndianInstructions)
139 ? llvm::endianness::big
140 : llvm::endianness::little;
141 }
142
143 ~ARMDisassembler() override = default;
144
145 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
146 ArrayRef<uint8_t> Bytes, uint64_t Address,
147 raw_ostream &CStream) const override;
148
149 uint64_t suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
150 uint64_t Address) const override;
151
152private:
153 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size,
154 ArrayRef<uint8_t> Bytes, uint64_t Address,
155 raw_ostream &CStream) const;
156
157 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size,
158 ArrayRef<uint8_t> Bytes, uint64_t Address,
159 raw_ostream &CStream) const;
160
161 mutable ITStatus ITBlock;
162 mutable VPTStatus VPTBlock;
163
164 void AddThumb1SBit(MCInst &MI, bool InITBlock) const;
165 bool isVectorPredicable(const MCInst &MI) const;
166 DecodeStatus AddThumbPredicate(MCInst&) const;
167 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const;
168
169 llvm::endianness InstructionEndianness;
170};
171
172} // end anonymous namespace
173
174// Forward declare these because the autogenerated code will reference them.
175// Definitions are further down.
176static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
177 uint64_t Address,
178 const MCDisassembler *Decoder);
179static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
180 uint64_t Address,
181 const MCDisassembler *Decoder);
182static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
183 uint64_t Address,
184 const MCDisassembler *Decoder);
185static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
186 uint64_t Address,
187 const MCDisassembler *Decoder);
188static DecodeStatus
189DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
190 uint64_t Address,
191 const MCDisassembler *Decoder);
192static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
193 uint64_t Address,
194 const MCDisassembler *Decoder);
195static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
196 uint64_t Address,
197 const MCDisassembler *Decoder);
198static DecodeStatus
199DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
200 const MCDisassembler *Decoder);
201static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo,
202 uint64_t Address,
203 const MCDisassembler *Decoder);
204static DecodeStatus
205DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
206 const MCDisassembler *Decoder);
207static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
208 uint64_t Address,
209 const MCDisassembler *Decoder);
210static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
211 uint64_t Address,
212 const MCDisassembler *Decoder);
213static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
214 uint64_t Address,
215 const MCDisassembler *Decoder);
216static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
217 uint64_t Address,
218 const MCDisassembler *Decoder);
219static DecodeStatus
220DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
221 const MCDisassembler *Decoder);
222static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
223 uint64_t Address,
224 const MCDisassembler *Decoder);
225static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
226 uint64_t Address,
227 const MCDisassembler *Decoder);
228static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
229 uint64_t Address,
230 const MCDisassembler *Decoder);
231static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
232 uint64_t Address,
233 const MCDisassembler *Decoder);
234static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
235 uint64_t Address,
236 const MCDisassembler *Decoder);
237static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
238 uint64_t Address,
239 const MCDisassembler *Decoder);
240static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
241 uint64_t Address,
242 const MCDisassembler *Decoder);
243static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
244 uint64_t Address,
245 const MCDisassembler *Decoder);
246static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
247 uint64_t Address,
248 const MCDisassembler *Decoder);
249static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
250 uint64_t Address,
251 const MCDisassembler *Decoder);
252static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
253 uint64_t Address,
254 const MCDisassembler *Decoder);
255static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
256 uint64_t Address,
257 const MCDisassembler *Decoder);
258static DecodeStatus
259DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
260 const MCDisassembler *Decoder);
261
262static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
263 uint64_t Address,
264 const MCDisassembler *Decoder);
265static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
266 uint64_t Address,
267 const MCDisassembler *Decoder);
268static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
269 uint64_t Address,
270 const MCDisassembler *Decoder);
271static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
272 uint64_t Address,
273 const MCDisassembler *Decoder);
274static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
275 uint64_t Address,
276 const MCDisassembler *Decoder);
277
278static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
279 uint64_t Address,
280 const MCDisassembler *Decoder);
281static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
282 uint64_t Address,
283 const MCDisassembler *Decoder);
284static DecodeStatus
285DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
286 const MCDisassembler *Decoder);
287static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
288 uint64_t Address,
289 const MCDisassembler *Decoder);
290static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
291 uint64_t Address,
292 const MCDisassembler *Decoder);
293static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn,
294 uint64_t Address,
295 const MCDisassembler *Decoder);
296static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
297 uint64_t Address,
298 const MCDisassembler *Decoder);
299static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
300 uint64_t Address,
301 const MCDisassembler *Decoder);
302
303static DecodeStatus
304DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn,
305 uint64_t Adddress,
306 const MCDisassembler *Decoder);
307static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
308 uint64_t Address,
309 const MCDisassembler *Decoder);
310static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
311 uint64_t Address,
312 const MCDisassembler *Decoder);
313static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
314 uint64_t Address,
315 const MCDisassembler *Decoder);
316static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
317 uint64_t Address,
318 const MCDisassembler *Decoder);
319static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
320 uint64_t Address,
321 const MCDisassembler *Decoder);
322static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
323 uint64_t Address,
324 const MCDisassembler *Decoder);
325static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
326 uint64_t Address,
327 const MCDisassembler *Decoder);
328static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
329 uint64_t Address,
330 const MCDisassembler *Decoder);
331static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn,
332 uint64_t Address,
333 const MCDisassembler *Decoder);
334static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
335 uint64_t Address,
336 const MCDisassembler *Decoder);
337static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
338 uint64_t Address,
339 const MCDisassembler *Decoder);
340static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
341 uint64_t Address,
342 const MCDisassembler *Decoder);
343static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
344 uint64_t Address,
345 const MCDisassembler *Decoder);
346static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
347 uint64_t Address,
348 const MCDisassembler *Decoder);
349static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
350 uint64_t Address,
351 const MCDisassembler *Decoder);
352static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
353 uint64_t Address,
354 const MCDisassembler *Decoder);
355static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
356 uint64_t Address,
357 const MCDisassembler *Decoder);
358static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
359 uint64_t Address,
360 const MCDisassembler *Decoder);
361static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
362 uint64_t Address,
363 const MCDisassembler *Decoder);
364static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
365 uint64_t Address,
366 const MCDisassembler *Decoder);
367static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
368 uint64_t Address,
369 const MCDisassembler *Decoder);
370static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
371 uint64_t Address,
372 const MCDisassembler *Decoder);
373static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
374 uint64_t Address,
375 const MCDisassembler *Decoder);
376static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
377 uint64_t Address,
378 const MCDisassembler *Decoder);
379static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
380 uint64_t Address,
381 const MCDisassembler *Decoder);
382static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
383 uint64_t Address,
384 const MCDisassembler *Decoder);
385static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Val,
386 uint64_t Address,
387 const MCDisassembler *Decoder);
388static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Val,
389 uint64_t Address,
390 const MCDisassembler *Decoder);
391static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
392 uint64_t Address,
393 const MCDisassembler *Decoder);
394static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
395 uint64_t Address,
396 const MCDisassembler *Decoder);
397static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
398 uint64_t Address,
399 const MCDisassembler *Decoder);
400static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
401 uint64_t Address,
402 const MCDisassembler *Decoder);
403static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
404 uint64_t Address,
405 const MCDisassembler *Decoder);
406static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
407 uint64_t Address,
408 const MCDisassembler *Decoder);
409static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
410 uint64_t Address,
411 const MCDisassembler *Decoder);
412static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
413 uint64_t Address,
414 const MCDisassembler *Decoder);
415static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
416 uint64_t Address,
417 const MCDisassembler *Decoder);
418template <int shift>
419static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
420 uint64_t Address,
421 const MCDisassembler *Decoder);
422static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
423 uint64_t Address,
424 const MCDisassembler *Decoder);
425static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
426 uint64_t Address,
427 const MCDisassembler *Decoder);
428static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
429 uint64_t Address,
430 const MCDisassembler *Decoder);
431static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, uint64_t Address,
432 const MCDisassembler *Decoder);
433static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
434 uint64_t Address,
435 const MCDisassembler *Decoder);
436static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
437 uint64_t Address,
438 const MCDisassembler *Decoder);
439static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
440 uint64_t Address,
441 const MCDisassembler *Decoder);
442static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
443 uint64_t Address,
444 const MCDisassembler *Decoder);
445static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
446 uint64_t Address,
447 const MCDisassembler *Decoder);
448static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
449 uint64_t Address,
450 const MCDisassembler *Decoder);
451static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
452 uint64_t Address,
453 const MCDisassembler *Decoder);
454static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
455 const MCDisassembler *Decoder);
456static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
457 const MCDisassembler *Decoder);
458static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
459 const MCDisassembler *Decoder);
460static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
461 const MCDisassembler *Decoder);
462static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
463 const MCDisassembler *Decoder);
464static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
465 const MCDisassembler *Decoder);
466static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
467 const MCDisassembler *Decoder);
468static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
469 const MCDisassembler *Decoder);
470static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address,
471 const MCDisassembler *Decoder);
472static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address,
473 const MCDisassembler *Decoder);
474static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address,
475 const MCDisassembler *Decoder);
476static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address,
477 const MCDisassembler *Decoder);
478static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address,
479 const MCDisassembler *Decoder);
480static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn,
481 uint64_t Address,
482 const MCDisassembler *Decoder);
483static DecodeStatus
484DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Val, uint64_t Address,
485 const MCDisassembler *Decoder);
486
487static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
488 uint64_t Address,
489 const MCDisassembler *Decoder);
490static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
491 uint64_t Address,
492 const MCDisassembler *Decoder);
493static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
494 uint64_t Address,
495 const MCDisassembler *Decoder);
496static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
497 uint64_t Address,
498 const MCDisassembler *Decoder);
499static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
500 uint64_t Address,
501 const MCDisassembler *Decoder);
502static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
503 uint64_t Address,
504 const MCDisassembler *Decoder);
505static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
506 uint64_t Address,
507 const MCDisassembler *Decoder);
508static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
509 uint64_t Address,
510 const MCDisassembler *Decoder);
511static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
512 uint64_t Address,
513 const MCDisassembler *Decoder);
514static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
515 uint64_t Address,
516 const MCDisassembler *Decoder);
517static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
518 uint64_t Address,
519 const MCDisassembler *Decoder);
520static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
521 uint64_t Address,
522 const MCDisassembler *Decoder);
523static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address,
524 const MCDisassembler *Decoder);
525static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
526 uint64_t Address,
527 const MCDisassembler *Decoder);
528static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address,
529 const MCDisassembler *Decoder);
530static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
531 const MCDisassembler *Decoder);
532static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
533 uint64_t Address,
534 const MCDisassembler *Decoder);
535static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
536 uint64_t Address,
537 const MCDisassembler *Decoder);
538static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val,
539 uint64_t Address,
540 const MCDisassembler *Decoder);
541static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address,
542 const MCDisassembler *Decoder);
543template <int shift>
544static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address,
545 const MCDisassembler *Decoder);
546static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
547 uint64_t Address,
548 const MCDisassembler *Decoder);
549template <int shift>
550static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
551 uint64_t Address,
552 const MCDisassembler *Decoder);
553template <int shift, int WriteBack>
554static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
555 uint64_t Address,
556 const MCDisassembler *Decoder);
557static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
558 uint64_t Address,
559 const MCDisassembler *Decoder);
560static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
561 uint64_t Address,
562 const MCDisassembler *Decoder);
563static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
564 uint64_t Address,
565 const MCDisassembler *Decoder);
566static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
567 uint64_t Address,
568 const MCDisassembler *Decoder);
569static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
570 uint64_t Address,
571 const MCDisassembler *Decoder);
572static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
573 uint64_t Address,
574 const MCDisassembler *Decoder);
575static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
576 uint64_t Address,
577 const MCDisassembler *Decoder);
578static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
579 uint64_t Address,
580 const MCDisassembler *Decoder);
581static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address,
582 const MCDisassembler *Decoder);
583static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
584 uint64_t Address,
585 const MCDisassembler *Decoder);
586static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
587 uint64_t Address,
588 const MCDisassembler *Decoder);
589static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, uint64_t Address,
590 const MCDisassembler *Decoder);
591static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
592 uint64_t Address,
593 const MCDisassembler *Decoder);
594static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
595 uint64_t Address,
596 const MCDisassembler *Decoder);
597static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, uint64_t Address,
598 const MCDisassembler *Decoder);
599static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
600 uint64_t Address,
601 const MCDisassembler *Decoder);
602static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
603 uint64_t Address,
604 const MCDisassembler *Decoder);
605
606static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address,
607 const MCDisassembler *Decoder);
608static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
609 uint64_t Address,
610 const MCDisassembler *Decoder);
611static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
612 uint64_t Address,
613 const MCDisassembler *Decoder);
614
615template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
616static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val,
617 uint64_t Address,
618 const MCDisassembler *Decoder);
619static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val,
620 uint64_t Address,
621 const MCDisassembler *Decoder);
622static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
623 uint64_t Address,
624 const MCDisassembler *Decoder);
625static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
626 const MCDisassembler *Decoder);
627static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
628 uint64_t Address,
629 const MCDisassembler *Decoder);
630static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
631 const MCDisassembler *Decoder);
632static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
633 uint64_t Address,
634 const MCDisassembler *Decoder);
635static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val,
636 uint64_t Address,
637 const MCDisassembler *Decoder);
638static DecodeStatus DecodeVpredNOperand(MCInst &Inst, unsigned Val,
639 uint64_t Address,
640 const MCDisassembler *Decoder);
641static DecodeStatus
642DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
643 const MCDisassembler *Decoder);
644static DecodeStatus
645DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
646 const MCDisassembler *Decoder);
647static DecodeStatus
648DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
649 const MCDisassembler *Decoder);
650static DecodeStatus
651DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
652 const MCDisassembler *Decoder);
653template <bool Writeback>
654static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn,
655 uint64_t Address,
656 const MCDisassembler *Decoder);
657template <int shift>
658static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
659 uint64_t Address,
660 const MCDisassembler *Decoder);
661template <int shift>
662static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
663 uint64_t Address,
664 const MCDisassembler *Decoder);
665template <int shift>
666static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
667 uint64_t Address,
668 const MCDisassembler *Decoder);
669template <unsigned MinLog, unsigned MaxLog>
670static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
671 uint64_t Address,
672 const MCDisassembler *Decoder);
673template <unsigned start>
674static DecodeStatus
675DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address,
676 const MCDisassembler *Decoder);
677static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
678 uint64_t Address,
679 const MCDisassembler *Decoder);
680static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
681 uint64_t Address,
682 const MCDisassembler *Decoder);
683static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
684 uint64_t Address,
685 const MCDisassembler *Decoder);
686typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val,
687 uint64_t Address,
688 const MCDisassembler *Decoder);
689template <bool scalar, OperandDecoder predicate_decoder>
690static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
691 const MCDisassembler *Decoder);
692static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
693 const MCDisassembler *Decoder);
694static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
695 uint64_t Address,
696 const MCDisassembler *Decoder);
697static DecodeStatus
698DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address,
699 const MCDisassembler *Decoder);
700static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
701 uint64_t Address,
702 const MCDisassembler *Decoder);
703static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn,
704 uint64_t Address,
705 const MCDisassembler *Decoder);
706
707#include "ARMGenDisassemblerTables.inc"
708
709static MCDisassembler *createARMDisassembler(const Target &T,
710 const MCSubtargetInfo &STI,
711 MCContext &Ctx) {
712 return new ARMDisassembler(STI, Ctx, T.createMCInstrInfo());
713}
714
715// Post-decoding checks
716static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
717 uint64_t Address, raw_ostream &CS,
718 uint32_t Insn,
719 DecodeStatus Result) {
720 switch (MI.getOpcode()) {
721 case ARM::HVC: {
722 // HVC is undefined if condition = 0xf otherwise upredictable
723 // if condition != 0xe
724 uint32_t Cond = (Insn >> 28) & 0xF;
725 if (Cond == 0xF)
726 return MCDisassembler::Fail;
727 if (Cond != 0xE)
728 return MCDisassembler::SoftFail;
729 return Result;
730 }
731 case ARM::t2ADDri:
732 case ARM::t2ADDri12:
733 case ARM::t2ADDrr:
734 case ARM::t2ADDrs:
735 case ARM::t2SUBri:
736 case ARM::t2SUBri12:
737 case ARM::t2SUBrr:
738 case ARM::t2SUBrs:
739 if (MI.getOperand(i: 0).getReg() == ARM::SP &&
740 MI.getOperand(i: 1).getReg() != ARM::SP)
741 return MCDisassembler::SoftFail;
742 return Result;
743 default: return Result;
744 }
745}
746
747uint64_t ARMDisassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
748 uint64_t Address) const {
749 // In Arm state, instructions are always 4 bytes wide, so there's no
750 // point in skipping any smaller number of bytes if an instruction
751 // can't be decoded.
752 if (!STI.hasFeature(Feature: ARM::ModeThumb))
753 return 4;
754
755 // In a Thumb instruction stream, a halfword is a standalone 2-byte
756 // instruction if and only if its value is less than 0xE800.
757 // Otherwise, it's the first halfword of a 4-byte instruction.
758 //
759 // So, if we can see the upcoming halfword, we can judge on that
760 // basis, and maybe skip a whole 4-byte instruction that we don't
761 // know how to decode, without accidentally trying to interpret its
762 // second half as something else.
763 //
764 // If we don't have the instruction data available, we just have to
765 // recommend skipping the minimum sensible distance, which is 2
766 // bytes.
767 if (Bytes.size() < 2)
768 return 2;
769
770 uint16_t Insn16 = llvm::support::endian::read<uint16_t>(
771 memory: Bytes.data(), endian: InstructionEndianness);
772 return Insn16 < 0xE800 ? 2 : 4;
773}
774
775DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
776 ArrayRef<uint8_t> Bytes,
777 uint64_t Address,
778 raw_ostream &CS) const {
779 if (STI.hasFeature(Feature: ARM::ModeThumb))
780 return getThumbInstruction(Instr&: MI, Size, Bytes, Address, CStream&: CS);
781 return getARMInstruction(Instr&: MI, Size, Bytes, Address, CStream&: CS);
782}
783
784DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size,
785 ArrayRef<uint8_t> Bytes,
786 uint64_t Address,
787 raw_ostream &CS) const {
788 CommentStream = &CS;
789
790 assert(!STI.hasFeature(ARM::ModeThumb) &&
791 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
792 "mode!");
793
794 // We want to read exactly 4 bytes of data.
795 if (Bytes.size() < 4) {
796 Size = 0;
797 return MCDisassembler::Fail;
798 }
799
800 // Encoded as a 32-bit word in the stream.
801 uint32_t Insn = llvm::support::endian::read<uint32_t>(memory: Bytes.data(),
802 endian: InstructionEndianness);
803
804 // Calling the auto-generated decoder function.
805 DecodeStatus Result =
806 decodeInstruction(DecodeTable: DecoderTableARM32, MI, insn: Insn, Address, DisAsm: this, STI);
807 if (Result != MCDisassembler::Fail) {
808 Size = 4;
809 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
810 }
811
812 struct DecodeTable {
813 const uint8_t *P;
814 bool DecodePred;
815 };
816
817 const DecodeTable Tables[] = {
818 {.P: DecoderTableVFP32, .DecodePred: false}, {.P: DecoderTableVFPV832, .DecodePred: false},
819 {.P: DecoderTableNEONData32, .DecodePred: true}, {.P: DecoderTableNEONLoadStore32, .DecodePred: true},
820 {.P: DecoderTableNEONDup32, .DecodePred: true}, {.P: DecoderTablev8NEON32, .DecodePred: false},
821 {.P: DecoderTablev8Crypto32, .DecodePred: false},
822 };
823
824 for (auto Table : Tables) {
825 Result = decodeInstruction(DecodeTable: Table.P, MI, insn: Insn, Address, DisAsm: this, STI);
826 if (Result != MCDisassembler::Fail) {
827 Size = 4;
828 // Add a fake predicate operand, because we share these instruction
829 // definitions with Thumb2 where these instructions are predicable.
830 if (Table.DecodePred && !DecodePredicateOperand(Inst&: MI, Val: 0xE, Address, Decoder: this))
831 return MCDisassembler::Fail;
832 return Result;
833 }
834 }
835
836 Result =
837 decodeInstruction(DecodeTable: DecoderTableCoProc32, MI, insn: Insn, Address, DisAsm: this, STI);
838 if (Result != MCDisassembler::Fail) {
839 Size = 4;
840 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
841 }
842
843 Size = 4;
844 return MCDisassembler::Fail;
845}
846
847/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
848/// immediate Value in the MCInst. The immediate Value has had any PC
849/// adjustment made by the caller. If the instruction is a branch instruction
850/// then isBranch is true, else false. If the getOpInfo() function was set as
851/// part of the setupForSymbolicDisassembly() call then that function is called
852/// to get any symbolic information at the Address for this instruction. If
853/// that returns non-zero then the symbolic information it returns is used to
854/// create an MCExpr and that is added as an operand to the MCInst. If
855/// getOpInfo() returns zero and isBranch is true then a symbol look up for
856/// Value is done and if a symbol is found an MCExpr is created with that, else
857/// an MCExpr with Value is created. This function returns true if it adds an
858/// operand to the MCInst and false otherwise.
859static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
860 bool isBranch, uint64_t InstSize,
861 MCInst &MI,
862 const MCDisassembler *Decoder) {
863 // FIXME: Does it make sense for value to be negative?
864 return Decoder->tryAddingSymbolicOperand(Inst&: MI, Value: (uint32_t)Value, Address,
865 IsBranch: isBranch, /*Offset=*/0, /*OpSize=*/0,
866 InstSize);
867}
868
869/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
870/// referenced by a load instruction with the base register that is the Pc.
871/// These can often be values in a literal pool near the Address of the
872/// instruction. The Address of the instruction and its immediate Value are
873/// used as a possible literal pool entry. The SymbolLookUp call back will
874/// return the name of a symbol referenced by the literal pool's entry if
875/// the referenced address is that of a symbol. Or it will return a pointer to
876/// a literal 'C' string if the referenced address of the literal pool's entry
877/// is an address into a section with 'C' string literals.
878static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
879 const MCDisassembler *Decoder) {
880 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
881 Dis->tryAddingPcLoadReferenceComment(Value, Address);
882}
883
884// Thumb1 instructions don't have explicit S bits. Rather, they
885// implicitly set CPSR. Since it's not represented in the encoding, the
886// auto-generated decoder won't inject the CPSR operand. We need to fix
887// that as a post-pass.
888void ARMDisassembler::AddThumb1SBit(MCInst &MI, bool InITBlock) const {
889 const MCInstrDesc &MCID = MCII->get(Opcode: MI.getOpcode());
890 MCInst::iterator I = MI.begin();
891 for (unsigned i = 0; i < MCID.NumOperands; ++i, ++I) {
892 if (I == MI.end()) break;
893 if (MCID.operands()[i].isOptionalDef() &&
894 MCID.operands()[i].RegClass == ARM::CCRRegClassID) {
895 if (i > 0 && MCID.operands()[i - 1].isPredicate())
896 continue;
897 MI.insert(I,
898 Op: MCOperand::createReg(Reg: InITBlock ? ARM::NoRegister : ARM::CPSR));
899 return;
900 }
901 }
902
903 MI.insert(I, Op: MCOperand::createReg(Reg: InITBlock ? ARM::NoRegister : ARM::CPSR));
904}
905
906bool ARMDisassembler::isVectorPredicable(const MCInst &MI) const {
907 const MCInstrDesc &MCID = MCII->get(Opcode: MI.getOpcode());
908 for (unsigned i = 0; i < MCID.NumOperands; ++i) {
909 if (ARM::isVpred(op: MCID.operands()[i].OperandType))
910 return true;
911 }
912 return false;
913}
914
915// Most Thumb instructions don't have explicit predicates in the
916// encoding, but rather get their predicates from IT context. We need
917// to fix up the predicate operands using this context information as a
918// post-pass.
919MCDisassembler::DecodeStatus
920ARMDisassembler::AddThumbPredicate(MCInst &MI) const {
921 MCDisassembler::DecodeStatus S = Success;
922
923 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
924
925 // A few instructions actually have predicates encoded in them. Don't
926 // try to overwrite it if we're seeing one of those.
927 switch (MI.getOpcode()) {
928 case ARM::tBcc:
929 case ARM::t2Bcc:
930 case ARM::tCBZ:
931 case ARM::tCBNZ:
932 case ARM::tCPS:
933 case ARM::t2CPS3p:
934 case ARM::t2CPS2p:
935 case ARM::t2CPS1p:
936 case ARM::t2CSEL:
937 case ARM::t2CSINC:
938 case ARM::t2CSINV:
939 case ARM::t2CSNEG:
940 case ARM::tMOVSr:
941 case ARM::tSETEND:
942 // Some instructions (mostly conditional branches) are not
943 // allowed in IT blocks.
944 if (ITBlock.instrInITBlock())
945 S = SoftFail;
946 else
947 return Success;
948 break;
949 case ARM::t2HINT:
950 if (MI.getOperand(i: 0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
951 S = SoftFail;
952 break;
953 case ARM::tB:
954 case ARM::t2B:
955 case ARM::t2TBB:
956 case ARM::t2TBH:
957 // Some instructions (mostly unconditional branches) can
958 // only appears at the end of, or outside of, an IT.
959 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
960 S = SoftFail;
961 break;
962 default:
963 break;
964 }
965
966 // Warn on non-VPT predicable instruction in a VPT block and a VPT
967 // predicable instruction in an IT block
968 if ((!isVectorPredicable(MI) && VPTBlock.instrInVPTBlock()) ||
969 (isVectorPredicable(MI) && ITBlock.instrInITBlock()))
970 S = SoftFail;
971
972 // If we're in an IT/VPT block, base the predicate on that. Otherwise,
973 // assume a predicate of AL.
974 unsigned CC = ARMCC::AL;
975 unsigned VCC = ARMVCC::None;
976 if (ITBlock.instrInITBlock()) {
977 CC = ITBlock.getITCC();
978 ITBlock.advanceITState();
979 } else if (VPTBlock.instrInVPTBlock()) {
980 VCC = VPTBlock.getVPTPred();
981 VPTBlock.advanceVPTState();
982 }
983
984 const MCInstrDesc &MCID = MCII->get(Opcode: MI.getOpcode());
985
986 MCInst::iterator CCI = MI.begin();
987 for (unsigned i = 0; i < MCID.NumOperands; ++i, ++CCI) {
988 if (MCID.operands()[i].isPredicate() || CCI == MI.end())
989 break;
990 }
991
992 if (MCID.isPredicable()) {
993 CCI = MI.insert(I: CCI, Op: MCOperand::createImm(Val: CC));
994 ++CCI;
995 if (CC == ARMCC::AL)
996 MI.insert(I: CCI, Op: MCOperand::createReg(Reg: ARM::NoRegister));
997 else
998 MI.insert(I: CCI, Op: MCOperand::createReg(Reg: ARM::CPSR));
999 } else if (CC != ARMCC::AL) {
1000 Check(Out&: S, In: SoftFail);
1001 }
1002
1003 MCInst::iterator VCCI = MI.begin();
1004 unsigned VCCPos;
1005 for (VCCPos = 0; VCCPos < MCID.NumOperands; ++VCCPos, ++VCCI) {
1006 if (ARM::isVpred(op: MCID.operands()[VCCPos].OperandType) || VCCI == MI.end())
1007 break;
1008 }
1009
1010 if (isVectorPredicable(MI)) {
1011 VCCI = MI.insert(I: VCCI, Op: MCOperand::createImm(Val: VCC));
1012 ++VCCI;
1013 if (VCC == ARMVCC::None)
1014 VCCI = MI.insert(I: VCCI, Op: MCOperand::createReg(Reg: 0));
1015 else
1016 VCCI = MI.insert(I: VCCI, Op: MCOperand::createReg(Reg: ARM::P0));
1017 ++VCCI;
1018 VCCI = MI.insert(I: VCCI, Op: MCOperand::createReg(Reg: 0));
1019 ++VCCI;
1020 if (MCID.operands()[VCCPos].OperandType == ARM::OPERAND_VPRED_R) {
1021 int TiedOp = MCID.getOperandConstraint(OpNum: VCCPos + 3, Constraint: MCOI::TIED_TO);
1022 assert(TiedOp >= 0 &&
1023 "Inactive register in vpred_r is not tied to an output!");
1024 // Copy the operand to ensure it's not invalidated when MI grows.
1025 MI.insert(I: VCCI, Op: MCOperand(MI.getOperand(i: TiedOp)));
1026 }
1027 } else if (VCC != ARMVCC::None) {
1028 Check(Out&: S, In: SoftFail);
1029 }
1030
1031 return S;
1032}
1033
1034// Thumb VFP instructions are a special case. Because we share their
1035// encodings between ARM and Thumb modes, and they are predicable in ARM
1036// mode, the auto-generated decoder will give them an (incorrect)
1037// predicate operand. We need to rewrite these operands based on the IT
1038// context as a post-pass.
1039void ARMDisassembler::UpdateThumbVFPPredicate(
1040 DecodeStatus &S, MCInst &MI) const {
1041 unsigned CC;
1042 CC = ITBlock.getITCC();
1043 if (CC == 0xF)
1044 CC = ARMCC::AL;
1045 if (ITBlock.instrInITBlock())
1046 ITBlock.advanceITState();
1047 else if (VPTBlock.instrInVPTBlock()) {
1048 CC = VPTBlock.getVPTPred();
1049 VPTBlock.advanceVPTState();
1050 }
1051
1052 const MCInstrDesc &MCID = MCII->get(Opcode: MI.getOpcode());
1053 ArrayRef<MCOperandInfo> OpInfo = MCID.operands();
1054 MCInst::iterator I = MI.begin();
1055 unsigned short NumOps = MCID.NumOperands;
1056 for (unsigned i = 0; i < NumOps; ++i, ++I) {
1057 if (OpInfo[i].isPredicate() ) {
1058 if (CC != ARMCC::AL && !MCID.isPredicable())
1059 Check(Out&: S, In: SoftFail);
1060 I->setImm(CC);
1061 ++I;
1062 if (CC == ARMCC::AL)
1063 I->setReg(ARM::NoRegister);
1064 else
1065 I->setReg(ARM::CPSR);
1066 return;
1067 }
1068 }
1069}
1070
1071DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size,
1072 ArrayRef<uint8_t> Bytes,
1073 uint64_t Address,
1074 raw_ostream &CS) const {
1075 CommentStream = &CS;
1076
1077 assert(STI.hasFeature(ARM::ModeThumb) &&
1078 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
1079
1080 // We want to read exactly 2 bytes of data.
1081 if (Bytes.size() < 2) {
1082 Size = 0;
1083 return MCDisassembler::Fail;
1084 }
1085
1086 uint16_t Insn16 = llvm::support::endian::read<uint16_t>(
1087 memory: Bytes.data(), endian: InstructionEndianness);
1088 DecodeStatus Result =
1089 decodeInstruction(DecodeTable: DecoderTableThumb16, MI, insn: Insn16, Address, DisAsm: this, STI);
1090 if (Result != MCDisassembler::Fail) {
1091 Size = 2;
1092 Check(Out&: Result, In: AddThumbPredicate(MI));
1093 return Result;
1094 }
1095
1096 Result = decodeInstruction(DecodeTable: DecoderTableThumbSBit16, MI, insn: Insn16, Address, DisAsm: this,
1097 STI);
1098 if (Result) {
1099 Size = 2;
1100 bool InITBlock = ITBlock.instrInITBlock();
1101 Check(Out&: Result, In: AddThumbPredicate(MI));
1102 AddThumb1SBit(MI, InITBlock);
1103 return Result;
1104 }
1105
1106 Result =
1107 decodeInstruction(DecodeTable: DecoderTableThumb216, MI, insn: Insn16, Address, DisAsm: this, STI);
1108 if (Result != MCDisassembler::Fail) {
1109 Size = 2;
1110
1111 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
1112 // the Thumb predicate.
1113 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
1114 Result = MCDisassembler::SoftFail;
1115
1116 Check(Out&: Result, In: AddThumbPredicate(MI));
1117
1118 // If we find an IT instruction, we need to parse its condition
1119 // code and mask operands so that we can apply them correctly
1120 // to the subsequent instructions.
1121 if (MI.getOpcode() == ARM::t2IT) {
1122 unsigned Firstcond = MI.getOperand(i: 0).getImm();
1123 unsigned Mask = MI.getOperand(i: 1).getImm();
1124 ITBlock.setITState(Firstcond, Mask);
1125
1126 // An IT instruction that would give a 'NV' predicate is unpredictable.
1127 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Value: Mask))
1128 CS << "unpredictable IT predicate sequence";
1129 }
1130
1131 return Result;
1132 }
1133
1134 // We want to read exactly 4 bytes of data.
1135 if (Bytes.size() < 4) {
1136 Size = 0;
1137 return MCDisassembler::Fail;
1138 }
1139
1140 uint32_t Insn32 =
1141 (uint32_t(Insn16) << 16) | llvm::support::endian::read<uint16_t>(
1142 memory: Bytes.data() + 2, endian: InstructionEndianness);
1143
1144 Result =
1145 decodeInstruction(DecodeTable: DecoderTableMVE32, MI, insn: Insn32, Address, DisAsm: this, STI);
1146 if (Result != MCDisassembler::Fail) {
1147 Size = 4;
1148
1149 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add
1150 // the VPT predicate.
1151 if (isVPTOpcode(Opc: MI.getOpcode()) && VPTBlock.instrInVPTBlock())
1152 Result = MCDisassembler::SoftFail;
1153
1154 Check(Out&: Result, In: AddThumbPredicate(MI));
1155
1156 if (isVPTOpcode(Opc: MI.getOpcode())) {
1157 unsigned Mask = MI.getOperand(i: 0).getImm();
1158 VPTBlock.setVPTState(Mask);
1159 }
1160
1161 return Result;
1162 }
1163
1164 Result =
1165 decodeInstruction(DecodeTable: DecoderTableThumb32, MI, insn: Insn32, Address, DisAsm: this, STI);
1166 if (Result != MCDisassembler::Fail) {
1167 Size = 4;
1168 bool InITBlock = ITBlock.instrInITBlock();
1169 Check(Out&: Result, In: AddThumbPredicate(MI));
1170 AddThumb1SBit(MI, InITBlock);
1171 return Result;
1172 }
1173
1174 Result =
1175 decodeInstruction(DecodeTable: DecoderTableThumb232, MI, insn: Insn32, Address, DisAsm: this, STI);
1176 if (Result != MCDisassembler::Fail) {
1177 Size = 4;
1178 Check(Out&: Result, In: AddThumbPredicate(MI));
1179 return checkDecodedInstruction(MI, Size, Address, CS, Insn: Insn32, Result);
1180 }
1181
1182 if (fieldFromInstruction(insn: Insn32, startBit: 28, numBits: 4) == 0xE) {
1183 Result =
1184 decodeInstruction(DecodeTable: DecoderTableVFP32, MI, insn: Insn32, Address, DisAsm: this, STI);
1185 if (Result != MCDisassembler::Fail) {
1186 Size = 4;
1187 UpdateThumbVFPPredicate(S&: Result, MI);
1188 return Result;
1189 }
1190 }
1191
1192 Result =
1193 decodeInstruction(DecodeTable: DecoderTableVFPV832, MI, insn: Insn32, Address, DisAsm: this, STI);
1194 if (Result != MCDisassembler::Fail) {
1195 Size = 4;
1196 return Result;
1197 }
1198
1199 if (fieldFromInstruction(insn: Insn32, startBit: 28, numBits: 4) == 0xE) {
1200 Result = decodeInstruction(DecodeTable: DecoderTableNEONDup32, MI, insn: Insn32, Address, DisAsm: this,
1201 STI);
1202 if (Result != MCDisassembler::Fail) {
1203 Size = 4;
1204 Check(Out&: Result, In: AddThumbPredicate(MI));
1205 return Result;
1206 }
1207 }
1208
1209 if (fieldFromInstruction(insn: Insn32, startBit: 24, numBits: 8) == 0xF9) {
1210 uint32_t NEONLdStInsn = Insn32;
1211 NEONLdStInsn &= 0xF0FFFFFF;
1212 NEONLdStInsn |= 0x04000000;
1213 Result = decodeInstruction(DecodeTable: DecoderTableNEONLoadStore32, MI, insn: NEONLdStInsn,
1214 Address, DisAsm: this, STI);
1215 if (Result != MCDisassembler::Fail) {
1216 Size = 4;
1217 Check(Out&: Result, In: AddThumbPredicate(MI));
1218 return Result;
1219 }
1220 }
1221
1222 if (fieldFromInstruction(insn: Insn32, startBit: 24, numBits: 4) == 0xF) {
1223 uint32_t NEONDataInsn = Insn32;
1224 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
1225 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
1226 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
1227 Result = decodeInstruction(DecodeTable: DecoderTableNEONData32, MI, insn: NEONDataInsn,
1228 Address, DisAsm: this, STI);
1229 if (Result != MCDisassembler::Fail) {
1230 Size = 4;
1231 Check(Out&: Result, In: AddThumbPredicate(MI));
1232 return Result;
1233 }
1234
1235 uint32_t NEONCryptoInsn = Insn32;
1236 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
1237 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
1238 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
1239 Result = decodeInstruction(DecodeTable: DecoderTablev8Crypto32, MI, insn: NEONCryptoInsn,
1240 Address, DisAsm: this, STI);
1241 if (Result != MCDisassembler::Fail) {
1242 Size = 4;
1243 return Result;
1244 }
1245
1246 uint32_t NEONv8Insn = Insn32;
1247 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
1248 Result = decodeInstruction(DecodeTable: DecoderTablev8NEON32, MI, insn: NEONv8Insn, Address,
1249 DisAsm: this, STI);
1250 if (Result != MCDisassembler::Fail) {
1251 Size = 4;
1252 return Result;
1253 }
1254 }
1255
1256 uint32_t Coproc = fieldFromInstruction(insn: Insn32, startBit: 8, numBits: 4);
1257 const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI)
1258 ? DecoderTableThumb2CDE32
1259 : DecoderTableThumb2CoProc32;
1260 Result =
1261 decodeInstruction(DecodeTable: DecoderTable, MI, insn: Insn32, Address, DisAsm: this, STI);
1262 if (Result != MCDisassembler::Fail) {
1263 Size = 4;
1264 Check(Out&: Result, In: AddThumbPredicate(MI));
1265 return Result;
1266 }
1267
1268 Size = 0;
1269 return MCDisassembler::Fail;
1270}
1271
1272extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
1273LLVMInitializeARMDisassembler() {
1274 TargetRegistry::RegisterMCDisassembler(T&: getTheARMLETarget(),
1275 Fn: createARMDisassembler);
1276 TargetRegistry::RegisterMCDisassembler(T&: getTheARMBETarget(),
1277 Fn: createARMDisassembler);
1278 TargetRegistry::RegisterMCDisassembler(T&: getTheThumbLETarget(),
1279 Fn: createARMDisassembler);
1280 TargetRegistry::RegisterMCDisassembler(T&: getTheThumbBETarget(),
1281 Fn: createARMDisassembler);
1282}
1283
1284static const uint16_t GPRDecoderTable[] = {
1285 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1286 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1287 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1288 ARM::R12, ARM::SP, ARM::LR, ARM::PC
1289};
1290
1291static const uint16_t CLRMGPRDecoderTable[] = {
1292 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1293 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1294 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1295 ARM::R12, 0, ARM::LR, ARM::APSR
1296};
1297
1298static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1299 uint64_t Address,
1300 const MCDisassembler *Decoder) {
1301 if (RegNo > 15)
1302 return MCDisassembler::Fail;
1303
1304 unsigned Register = GPRDecoderTable[RegNo];
1305 Inst.addOperand(Op: MCOperand::createReg(Reg: Register));
1306 return MCDisassembler::Success;
1307}
1308
1309static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1310 uint64_t Address,
1311 const MCDisassembler *Decoder) {
1312 if (RegNo > 15)
1313 return MCDisassembler::Fail;
1314
1315 unsigned Register = CLRMGPRDecoderTable[RegNo];
1316 if (Register == 0)
1317 return MCDisassembler::Fail;
1318
1319 Inst.addOperand(Op: MCOperand::createReg(Reg: Register));
1320 return MCDisassembler::Success;
1321}
1322
1323static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
1324 uint64_t Address,
1325 const MCDisassembler *Decoder) {
1326 DecodeStatus S = MCDisassembler::Success;
1327
1328 if (RegNo == 15)
1329 S = MCDisassembler::SoftFail;
1330
1331 Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1332
1333 return S;
1334}
1335
1336static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
1337 uint64_t Address,
1338 const MCDisassembler *Decoder) {
1339 DecodeStatus S = MCDisassembler::Success;
1340
1341 if (RegNo == 13)
1342 S = MCDisassembler::SoftFail;
1343
1344 Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1345
1346 return S;
1347}
1348
1349static DecodeStatus
1350DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1351 const MCDisassembler *Decoder) {
1352 DecodeStatus S = MCDisassembler::Success;
1353
1354 if (RegNo == 15)
1355 {
1356 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::APSR_NZCV));
1357 return MCDisassembler::Success;
1358 }
1359
1360 Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1361 return S;
1362}
1363
1364static DecodeStatus
1365DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1366 const MCDisassembler *Decoder) {
1367 DecodeStatus S = MCDisassembler::Success;
1368
1369 if (RegNo == 15)
1370 {
1371 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::ZR));
1372 return MCDisassembler::Success;
1373 }
1374
1375 if (RegNo == 13)
1376 Check(Out&: S, In: MCDisassembler::SoftFail);
1377
1378 Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1379 return S;
1380}
1381
1382static DecodeStatus
1383DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1384 const MCDisassembler *Decoder) {
1385 DecodeStatus S = MCDisassembler::Success;
1386 if (RegNo == 13)
1387 return MCDisassembler::Fail;
1388 Check(Out&: S, In: DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder));
1389 return S;
1390}
1391
1392static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1393 uint64_t Address,
1394 const MCDisassembler *Decoder) {
1395 if (RegNo > 7)
1396 return MCDisassembler::Fail;
1397 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
1398}
1399
1400static const uint16_t GPRPairDecoderTable[] = {
1401 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
1402 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
1403};
1404
1405static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
1406 uint64_t Address,
1407 const MCDisassembler *Decoder) {
1408 DecodeStatus S = MCDisassembler::Success;
1409
1410 // According to the Arm ARM RegNo = 14 is undefined, but we return fail
1411 // rather than SoftFail as there is no GPRPair table entry for index 7.
1412 if (RegNo > 13)
1413 return MCDisassembler::Fail;
1414
1415 if (RegNo & 1)
1416 S = MCDisassembler::SoftFail;
1417
1418 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
1419 Inst.addOperand(Op: MCOperand::createReg(Reg: RegisterPair));
1420 return S;
1421}
1422
1423static DecodeStatus
1424DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1425 const MCDisassembler *Decoder) {
1426 if (RegNo > 13)
1427 return MCDisassembler::Fail;
1428
1429 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
1430 Inst.addOperand(Op: MCOperand::createReg(Reg: RegisterPair));
1431
1432 if ((RegNo & 1) || RegNo > 10)
1433 return MCDisassembler::SoftFail;
1434 return MCDisassembler::Success;
1435}
1436
1437static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
1438 uint64_t Address,
1439 const MCDisassembler *Decoder) {
1440 if (RegNo != 13)
1441 return MCDisassembler::Fail;
1442
1443 unsigned Register = GPRDecoderTable[RegNo];
1444 Inst.addOperand(Op: MCOperand::createReg(Reg: Register));
1445 return MCDisassembler::Success;
1446}
1447
1448static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1449 uint64_t Address,
1450 const MCDisassembler *Decoder) {
1451 unsigned Register = 0;
1452 switch (RegNo) {
1453 case 0:
1454 Register = ARM::R0;
1455 break;
1456 case 1:
1457 Register = ARM::R1;
1458 break;
1459 case 2:
1460 Register = ARM::R2;
1461 break;
1462 case 3:
1463 Register = ARM::R3;
1464 break;
1465 case 9:
1466 Register = ARM::R9;
1467 break;
1468 case 12:
1469 Register = ARM::R12;
1470 break;
1471 default:
1472 return MCDisassembler::Fail;
1473 }
1474
1475 Inst.addOperand(Op: MCOperand::createReg(Reg: Register));
1476 return MCDisassembler::Success;
1477}
1478
1479static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1480 uint64_t Address,
1481 const MCDisassembler *Decoder) {
1482 DecodeStatus S = MCDisassembler::Success;
1483
1484 const FeatureBitset &featureBits =
1485 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1486
1487 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
1488 S = MCDisassembler::SoftFail;
1489
1490 Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1491 return S;
1492}
1493
1494static const MCPhysReg SPRDecoderTable[] = {
1495 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1496 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1497 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1498 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1499 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1500 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1501 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1502 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1503};
1504
1505static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
1506 uint64_t Address,
1507 const MCDisassembler *Decoder) {
1508 if (RegNo > 31)
1509 return MCDisassembler::Fail;
1510
1511 unsigned Register = SPRDecoderTable[RegNo];
1512 Inst.addOperand(Op: MCOperand::createReg(Reg: Register));
1513 return MCDisassembler::Success;
1514}
1515
1516static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
1517 uint64_t Address,
1518 const MCDisassembler *Decoder) {
1519 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1520}
1521
1522static const MCPhysReg DPRDecoderTable[] = {
1523 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1524 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1525 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1526 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1527 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1528 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1529 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1530 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1531};
1532
1533// Does this instruction/subtarget permit use of registers d16-d31?
1534static bool PermitsD32(const MCInst &Inst, const MCDisassembler *Decoder) {
1535 if (Inst.getOpcode() == ARM::VSCCLRMD || Inst.getOpcode() == ARM::VSCCLRMS)
1536 return true;
1537 const FeatureBitset &featureBits =
1538 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1539 return featureBits[ARM::FeatureD32];
1540}
1541
1542static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1543 uint64_t Address,
1544 const MCDisassembler *Decoder) {
1545 if (RegNo > (PermitsD32(Inst, Decoder) ? 31u : 15u))
1546 return MCDisassembler::Fail;
1547
1548 unsigned Register = DPRDecoderTable[RegNo];
1549 Inst.addOperand(Op: MCOperand::createReg(Reg: Register));
1550 return MCDisassembler::Success;
1551}
1552
1553static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1554 uint64_t Address,
1555 const MCDisassembler *Decoder) {
1556 if (RegNo > 7)
1557 return MCDisassembler::Fail;
1558 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1559}
1560
1561static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1562 uint64_t Address,
1563 const MCDisassembler *Decoder) {
1564 if (RegNo > 15)
1565 return MCDisassembler::Fail;
1566 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1567}
1568
1569static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1570 uint64_t Address,
1571 const MCDisassembler *Decoder) {
1572 if (RegNo > 15)
1573 return MCDisassembler::Fail;
1574 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1575}
1576
1577static const MCPhysReg QPRDecoderTable[] = {
1578 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1579 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1580 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1581 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1582};
1583
1584static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1585 uint64_t Address,
1586 const MCDisassembler *Decoder) {
1587 if (RegNo > 31 || (RegNo & 1) != 0)
1588 return MCDisassembler::Fail;
1589 RegNo >>= 1;
1590
1591 unsigned Register = QPRDecoderTable[RegNo];
1592 Inst.addOperand(Op: MCOperand::createReg(Reg: Register));
1593 return MCDisassembler::Success;
1594}
1595
1596static const MCPhysReg DPairDecoderTable[] = {
1597 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1598 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1599 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1600 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1601 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1602 ARM::Q15
1603};
1604
1605static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1606 uint64_t Address,
1607 const MCDisassembler *Decoder) {
1608 if (RegNo > 30)
1609 return MCDisassembler::Fail;
1610
1611 unsigned Register = DPairDecoderTable[RegNo];
1612 Inst.addOperand(Op: MCOperand::createReg(Reg: Register));
1613 return MCDisassembler::Success;
1614}
1615
1616static const MCPhysReg DPairSpacedDecoderTable[] = {
1617 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1618 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1619 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1620 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1621 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1622 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1623 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1624 ARM::D28_D30, ARM::D29_D31
1625};
1626
1627static DecodeStatus
1628DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1629 const MCDisassembler *Decoder) {
1630 if (RegNo > 29)
1631 return MCDisassembler::Fail;
1632
1633 unsigned Register = DPairSpacedDecoderTable[RegNo];
1634 Inst.addOperand(Op: MCOperand::createReg(Reg: Register));
1635 return MCDisassembler::Success;
1636}
1637
1638static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1639 uint64_t Address,
1640 const MCDisassembler *Decoder) {
1641 DecodeStatus S = MCDisassembler::Success;
1642 if (Val == 0xF) return MCDisassembler::Fail;
1643 // AL predicate is not allowed on Thumb1 branches.
1644 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1645 return MCDisassembler::Fail;
1646 const MCInstrInfo *MCII =
1647 static_cast<const ARMDisassembler *>(Decoder)->MCII.get();
1648 if (Val != ARMCC::AL && !MCII->get(Opcode: Inst.getOpcode()).isPredicable())
1649 Check(Out&: S, In: MCDisassembler::SoftFail);
1650 Inst.addOperand(Op: MCOperand::createImm(Val));
1651 if (Val == ARMCC::AL) {
1652 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::NoRegister));
1653 } else
1654 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::CPSR));
1655 return S;
1656}
1657
1658static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1659 uint64_t Address,
1660 const MCDisassembler *Decoder) {
1661 if (Val)
1662 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::CPSR));
1663 else
1664 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::NoRegister));
1665 return MCDisassembler::Success;
1666}
1667
1668static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1669 uint64_t Address,
1670 const MCDisassembler *Decoder) {
1671 DecodeStatus S = MCDisassembler::Success;
1672
1673 unsigned Rm = fieldFromInstruction(insn: Val, startBit: 0, numBits: 4);
1674 unsigned type = fieldFromInstruction(insn: Val, startBit: 5, numBits: 2);
1675 unsigned imm = fieldFromInstruction(insn: Val, startBit: 7, numBits: 5);
1676
1677 // Register-immediate
1678 if (!Check(Out&: S, In: DecoderGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
1679 return MCDisassembler::Fail;
1680
1681 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1682 switch (type) {
1683 case 0:
1684 Shift = ARM_AM::lsl;
1685 break;
1686 case 1:
1687 Shift = ARM_AM::lsr;
1688 break;
1689 case 2:
1690 Shift = ARM_AM::asr;
1691 break;
1692 case 3:
1693 Shift = ARM_AM::ror;
1694 break;
1695 }
1696
1697 if (Shift == ARM_AM::ror && imm == 0)
1698 Shift = ARM_AM::rrx;
1699
1700 unsigned Op = Shift | (imm << 3);
1701 Inst.addOperand(Op: MCOperand::createImm(Val: Op));
1702
1703 return S;
1704}
1705
1706static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1707 uint64_t Address,
1708 const MCDisassembler *Decoder) {
1709 DecodeStatus S = MCDisassembler::Success;
1710
1711 unsigned Rm = fieldFromInstruction(insn: Val, startBit: 0, numBits: 4);
1712 unsigned type = fieldFromInstruction(insn: Val, startBit: 5, numBits: 2);
1713 unsigned Rs = fieldFromInstruction(insn: Val, startBit: 8, numBits: 4);
1714
1715 // Register-register
1716 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
1717 return MCDisassembler::Fail;
1718 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rs, Address, Decoder)))
1719 return MCDisassembler::Fail;
1720
1721 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1722 switch (type) {
1723 case 0:
1724 Shift = ARM_AM::lsl;
1725 break;
1726 case 1:
1727 Shift = ARM_AM::lsr;
1728 break;
1729 case 2:
1730 Shift = ARM_AM::asr;
1731 break;
1732 case 3:
1733 Shift = ARM_AM::ror;
1734 break;
1735 }
1736
1737 Inst.addOperand(Op: MCOperand::createImm(Val: Shift));
1738
1739 return S;
1740}
1741
1742static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1743 uint64_t Address,
1744 const MCDisassembler *Decoder) {
1745 DecodeStatus S = MCDisassembler::Success;
1746
1747 bool NeedDisjointWriteback = false;
1748 MCRegister WritebackReg;
1749 bool CLRM = false;
1750 switch (Inst.getOpcode()) {
1751 default:
1752 break;
1753 case ARM::LDMIA_UPD:
1754 case ARM::LDMDB_UPD:
1755 case ARM::LDMIB_UPD:
1756 case ARM::LDMDA_UPD:
1757 case ARM::t2LDMIA_UPD:
1758 case ARM::t2LDMDB_UPD:
1759 case ARM::t2STMIA_UPD:
1760 case ARM::t2STMDB_UPD:
1761 NeedDisjointWriteback = true;
1762 WritebackReg = Inst.getOperand(i: 0).getReg();
1763 break;
1764 case ARM::t2CLRM:
1765 CLRM = true;
1766 break;
1767 }
1768
1769 // Empty register lists are not allowed.
1770 if (Val == 0) return MCDisassembler::Fail;
1771 for (unsigned i = 0; i < 16; ++i) {
1772 if (Val & (1 << i)) {
1773 if (CLRM) {
1774 if (!Check(Out&: S, In: DecodeCLRMGPRRegisterClass(Inst, RegNo: i, Address, Decoder))) {
1775 return MCDisassembler::Fail;
1776 }
1777 } else {
1778 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: i, Address, Decoder)))
1779 return MCDisassembler::Fail;
1780 // Writeback not allowed if Rn is in the target list.
1781 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1782 Check(Out&: S, In: MCDisassembler::SoftFail);
1783 }
1784 }
1785 }
1786
1787 return S;
1788}
1789
1790static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1791 uint64_t Address,
1792 const MCDisassembler *Decoder) {
1793 DecodeStatus S = MCDisassembler::Success;
1794
1795 unsigned Vd = fieldFromInstruction(insn: Val, startBit: 8, numBits: 5);
1796 unsigned regs = fieldFromInstruction(insn: Val, startBit: 0, numBits: 8);
1797
1798 // In case of unpredictable encoding, tweak the operands.
1799 if (regs == 0 || (Vd + regs) > 32) {
1800 regs = Vd + regs > 32 ? 32 - Vd : regs;
1801 regs = std::max( a: 1u, b: regs);
1802 S = MCDisassembler::SoftFail;
1803 }
1804
1805 if (!Check(Out&: S, In: DecodeSPRRegisterClass(Inst, RegNo: Vd, Address, Decoder)))
1806 return MCDisassembler::Fail;
1807 for (unsigned i = 0; i < (regs - 1); ++i) {
1808 if (!Check(Out&: S, In: DecodeSPRRegisterClass(Inst, RegNo: ++Vd, Address, Decoder)))
1809 return MCDisassembler::Fail;
1810 }
1811
1812 return S;
1813}
1814
1815static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1816 uint64_t Address,
1817 const MCDisassembler *Decoder) {
1818 DecodeStatus S = MCDisassembler::Success;
1819
1820 unsigned Vd = fieldFromInstruction(insn: Val, startBit: 8, numBits: 5);
1821 unsigned regs = fieldFromInstruction(insn: Val, startBit: 1, numBits: 7);
1822
1823 // In case of unpredictable encoding, tweak the operands.
1824 unsigned MaxReg = PermitsD32(Inst, Decoder) ? 32 : 16;
1825 if (regs == 0 || (Vd + regs) > MaxReg) {
1826 regs = Vd + regs > MaxReg ? MaxReg - Vd : regs;
1827 regs = std::max( a: 1u, b: regs);
1828 regs = std::min(a: MaxReg, b: regs);
1829 S = MCDisassembler::SoftFail;
1830 }
1831
1832 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Vd, Address, Decoder)))
1833 return MCDisassembler::Fail;
1834 for (unsigned i = 0; i < (regs - 1); ++i) {
1835 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: ++Vd, Address, Decoder)))
1836 return MCDisassembler::Fail;
1837 }
1838
1839 return S;
1840}
1841
1842static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1843 uint64_t Address,
1844 const MCDisassembler *Decoder) {
1845 // This operand encodes a mask of contiguous zeros between a specified MSB
1846 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1847 // the mask of all bits LSB-and-lower, and then xor them to create
1848 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1849 // create the final mask.
1850 unsigned msb = fieldFromInstruction(insn: Val, startBit: 5, numBits: 5);
1851 unsigned lsb = fieldFromInstruction(insn: Val, startBit: 0, numBits: 5);
1852
1853 DecodeStatus S = MCDisassembler::Success;
1854 if (lsb > msb) {
1855 Check(Out&: S, In: MCDisassembler::SoftFail);
1856 // The check above will cause the warning for the "potentially undefined
1857 // instruction encoding" but we can't build a bad MCOperand value here
1858 // with a lsb > msb or else printing the MCInst will cause a crash.
1859 lsb = msb;
1860 }
1861
1862 uint32_t msb_mask = 0xFFFFFFFF;
1863 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1864 uint32_t lsb_mask = (1U << lsb) - 1;
1865
1866 Inst.addOperand(Op: MCOperand::createImm(Val: ~(msb_mask ^ lsb_mask)));
1867 return S;
1868}
1869
1870static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1871 uint64_t Address,
1872 const MCDisassembler *Decoder) {
1873 DecodeStatus S = MCDisassembler::Success;
1874
1875 unsigned pred = fieldFromInstruction(insn: Insn, startBit: 28, numBits: 4);
1876 unsigned CRd = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
1877 unsigned coproc = fieldFromInstruction(insn: Insn, startBit: 8, numBits: 4);
1878 unsigned imm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 8);
1879 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
1880 unsigned U = fieldFromInstruction(insn: Insn, startBit: 23, numBits: 1);
1881 const FeatureBitset &featureBits =
1882 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1883
1884 switch (Inst.getOpcode()) {
1885 case ARM::LDC_OFFSET:
1886 case ARM::LDC_PRE:
1887 case ARM::LDC_POST:
1888 case ARM::LDC_OPTION:
1889 case ARM::LDCL_OFFSET:
1890 case ARM::LDCL_PRE:
1891 case ARM::LDCL_POST:
1892 case ARM::LDCL_OPTION:
1893 case ARM::STC_OFFSET:
1894 case ARM::STC_PRE:
1895 case ARM::STC_POST:
1896 case ARM::STC_OPTION:
1897 case ARM::STCL_OFFSET:
1898 case ARM::STCL_PRE:
1899 case ARM::STCL_POST:
1900 case ARM::STCL_OPTION:
1901 case ARM::t2LDC_OFFSET:
1902 case ARM::t2LDC_PRE:
1903 case ARM::t2LDC_POST:
1904 case ARM::t2LDC_OPTION:
1905 case ARM::t2LDCL_OFFSET:
1906 case ARM::t2LDCL_PRE:
1907 case ARM::t2LDCL_POST:
1908 case ARM::t2LDCL_OPTION:
1909 case ARM::t2STC_OFFSET:
1910 case ARM::t2STC_PRE:
1911 case ARM::t2STC_POST:
1912 case ARM::t2STC_OPTION:
1913 case ARM::t2STCL_OFFSET:
1914 case ARM::t2STCL_PRE:
1915 case ARM::t2STCL_POST:
1916 case ARM::t2STCL_OPTION:
1917 case ARM::t2LDC2_OFFSET:
1918 case ARM::t2LDC2L_OFFSET:
1919 case ARM::t2LDC2_PRE:
1920 case ARM::t2LDC2L_PRE:
1921 case ARM::t2STC2_OFFSET:
1922 case ARM::t2STC2L_OFFSET:
1923 case ARM::t2STC2_PRE:
1924 case ARM::t2STC2L_PRE:
1925 case ARM::LDC2_OFFSET:
1926 case ARM::LDC2L_OFFSET:
1927 case ARM::LDC2_PRE:
1928 case ARM::LDC2L_PRE:
1929 case ARM::STC2_OFFSET:
1930 case ARM::STC2L_OFFSET:
1931 case ARM::STC2_PRE:
1932 case ARM::STC2L_PRE:
1933 case ARM::t2LDC2_OPTION:
1934 case ARM::t2STC2_OPTION:
1935 case ARM::t2LDC2_POST:
1936 case ARM::t2LDC2L_POST:
1937 case ARM::t2STC2_POST:
1938 case ARM::t2STC2L_POST:
1939 case ARM::LDC2_POST:
1940 case ARM::LDC2L_POST:
1941 case ARM::STC2_POST:
1942 case ARM::STC2L_POST:
1943 if (coproc == 0xA || coproc == 0xB ||
1944 (featureBits[ARM::HasV8_1MMainlineOps] &&
1945 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||
1946 coproc == 0xE || coproc == 0xF)))
1947 return MCDisassembler::Fail;
1948 break;
1949 default:
1950 break;
1951 }
1952
1953 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1954 return MCDisassembler::Fail;
1955
1956 Inst.addOperand(Op: MCOperand::createImm(Val: coproc));
1957 Inst.addOperand(Op: MCOperand::createImm(Val: CRd));
1958 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
1959 return MCDisassembler::Fail;
1960
1961 switch (Inst.getOpcode()) {
1962 case ARM::t2LDC2_OFFSET:
1963 case ARM::t2LDC2L_OFFSET:
1964 case ARM::t2LDC2_PRE:
1965 case ARM::t2LDC2L_PRE:
1966 case ARM::t2STC2_OFFSET:
1967 case ARM::t2STC2L_OFFSET:
1968 case ARM::t2STC2_PRE:
1969 case ARM::t2STC2L_PRE:
1970 case ARM::LDC2_OFFSET:
1971 case ARM::LDC2L_OFFSET:
1972 case ARM::LDC2_PRE:
1973 case ARM::LDC2L_PRE:
1974 case ARM::STC2_OFFSET:
1975 case ARM::STC2L_OFFSET:
1976 case ARM::STC2_PRE:
1977 case ARM::STC2L_PRE:
1978 case ARM::t2LDC_OFFSET:
1979 case ARM::t2LDCL_OFFSET:
1980 case ARM::t2LDC_PRE:
1981 case ARM::t2LDCL_PRE:
1982 case ARM::t2STC_OFFSET:
1983 case ARM::t2STCL_OFFSET:
1984 case ARM::t2STC_PRE:
1985 case ARM::t2STCL_PRE:
1986 case ARM::LDC_OFFSET:
1987 case ARM::LDCL_OFFSET:
1988 case ARM::LDC_PRE:
1989 case ARM::LDCL_PRE:
1990 case ARM::STC_OFFSET:
1991 case ARM::STCL_OFFSET:
1992 case ARM::STC_PRE:
1993 case ARM::STCL_PRE:
1994 imm = ARM_AM::getAM5Opc(Opc: U ? ARM_AM::add : ARM_AM::sub, Offset: imm);
1995 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
1996 break;
1997 case ARM::t2LDC2_POST:
1998 case ARM::t2LDC2L_POST:
1999 case ARM::t2STC2_POST:
2000 case ARM::t2STC2L_POST:
2001 case ARM::LDC2_POST:
2002 case ARM::LDC2L_POST:
2003 case ARM::STC2_POST:
2004 case ARM::STC2L_POST:
2005 case ARM::t2LDC_POST:
2006 case ARM::t2LDCL_POST:
2007 case ARM::t2STC_POST:
2008 case ARM::t2STCL_POST:
2009 case ARM::LDC_POST:
2010 case ARM::LDCL_POST:
2011 case ARM::STC_POST:
2012 case ARM::STCL_POST:
2013 imm |= U << 8;
2014 [[fallthrough]];
2015 default:
2016 // The 'option' variant doesn't encode 'U' in the immediate since
2017 // the immediate is unsigned [0,255].
2018 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
2019 break;
2020 }
2021
2022 switch (Inst.getOpcode()) {
2023 case ARM::LDC_OFFSET:
2024 case ARM::LDC_PRE:
2025 case ARM::LDC_POST:
2026 case ARM::LDC_OPTION:
2027 case ARM::LDCL_OFFSET:
2028 case ARM::LDCL_PRE:
2029 case ARM::LDCL_POST:
2030 case ARM::LDCL_OPTION:
2031 case ARM::STC_OFFSET:
2032 case ARM::STC_PRE:
2033 case ARM::STC_POST:
2034 case ARM::STC_OPTION:
2035 case ARM::STCL_OFFSET:
2036 case ARM::STCL_PRE:
2037 case ARM::STCL_POST:
2038 case ARM::STCL_OPTION:
2039 if (!Check(Out&: S, In: DecodePredicateOperand(Inst, Val: pred, Address, Decoder)))
2040 return MCDisassembler::Fail;
2041 break;
2042 default:
2043 break;
2044 }
2045
2046 return S;
2047}
2048
2049static DecodeStatus
2050DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
2051 const MCDisassembler *Decoder) {
2052 DecodeStatus S = MCDisassembler::Success;
2053
2054 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
2055 unsigned Rt = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
2056 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
2057 unsigned imm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 12);
2058 unsigned pred = fieldFromInstruction(insn: Insn, startBit: 28, numBits: 4);
2059 unsigned reg = fieldFromInstruction(insn: Insn, startBit: 25, numBits: 1);
2060 unsigned P = fieldFromInstruction(insn: Insn, startBit: 24, numBits: 1);
2061 unsigned W = fieldFromInstruction(insn: Insn, startBit: 21, numBits: 1);
2062
2063 // On stores, the writeback operand precedes Rt.
2064 switch (Inst.getOpcode()) {
2065 case ARM::STR_POST_IMM:
2066 case ARM::STR_POST_REG:
2067 case ARM::STRB_POST_IMM:
2068 case ARM::STRB_POST_REG:
2069 case ARM::STRT_POST_REG:
2070 case ARM::STRT_POST_IMM:
2071 case ARM::STRBT_POST_REG:
2072 case ARM::STRBT_POST_IMM:
2073 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
2074 return MCDisassembler::Fail;
2075 break;
2076 default:
2077 break;
2078 }
2079
2080 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rt, Address, Decoder)))
2081 return MCDisassembler::Fail;
2082
2083 // On loads, the writeback operand comes after Rt.
2084 switch (Inst.getOpcode()) {
2085 case ARM::LDR_POST_IMM:
2086 case ARM::LDR_POST_REG:
2087 case ARM::LDRB_POST_IMM:
2088 case ARM::LDRB_POST_REG:
2089 case ARM::LDRBT_POST_REG:
2090 case ARM::LDRBT_POST_IMM:
2091 case ARM::LDRT_POST_REG:
2092 case ARM::LDRT_POST_IMM:
2093 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
2094 return MCDisassembler::Fail;
2095 break;
2096 default:
2097 break;
2098 }
2099
2100 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
2101 return MCDisassembler::Fail;
2102
2103 ARM_AM::AddrOpc Op = ARM_AM::add;
2104 if (!fieldFromInstruction(insn: Insn, startBit: 23, numBits: 1))
2105 Op = ARM_AM::sub;
2106
2107 bool writeback = (P == 0) || (W == 1);
2108 unsigned idx_mode = 0;
2109 if (P && writeback)
2110 idx_mode = ARMII::IndexModePre;
2111 else if (!P && writeback)
2112 idx_mode = ARMII::IndexModePost;
2113
2114 if (writeback && (Rn == 15 || Rn == Rt))
2115 S = MCDisassembler::SoftFail; // UNPREDICTABLE
2116
2117 if (reg) {
2118 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
2119 return MCDisassembler::Fail;
2120 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
2121 switch( fieldFromInstruction(insn: Insn, startBit: 5, numBits: 2)) {
2122 case 0:
2123 Opc = ARM_AM::lsl;
2124 break;
2125 case 1:
2126 Opc = ARM_AM::lsr;
2127 break;
2128 case 2:
2129 Opc = ARM_AM::asr;
2130 break;
2131 case 3:
2132 Opc = ARM_AM::ror;
2133 break;
2134 default:
2135 return MCDisassembler::Fail;
2136 }
2137 unsigned amt = fieldFromInstruction(insn: Insn, startBit: 7, numBits: 5);
2138 if (Opc == ARM_AM::ror && amt == 0)
2139 Opc = ARM_AM::rrx;
2140 unsigned imm = ARM_AM::getAM2Opc(Opc: Op, Imm12: amt, SO: Opc, IdxMode: idx_mode);
2141
2142 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
2143 } else {
2144 Inst.addOperand(Op: MCOperand::createReg(Reg: 0));
2145 unsigned tmp = ARM_AM::getAM2Opc(Opc: Op, Imm12: imm, SO: ARM_AM::lsl, IdxMode: idx_mode);
2146 Inst.addOperand(Op: MCOperand::createImm(Val: tmp));
2147 }
2148
2149 if (!Check(Out&: S, In: DecodePredicateOperand(Inst, Val: pred, Address, Decoder)))
2150 return MCDisassembler::Fail;
2151
2152 return S;
2153}
2154
2155static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
2156 uint64_t Address,
2157 const MCDisassembler *Decoder) {
2158 DecodeStatus S = MCDisassembler::Success;
2159
2160 unsigned Rn = fieldFromInstruction(insn: Val, startBit: 13, numBits: 4);
2161 unsigned Rm = fieldFromInstruction(insn: Val, startBit: 0, numBits: 4);
2162 unsigned type = fieldFromInstruction(insn: Val, startBit: 5, numBits: 2);
2163 unsigned imm = fieldFromInstruction(insn: Val, startBit: 7, numBits: 5);
2164 unsigned U = fieldFromInstruction(insn: Val, startBit: 12, numBits: 1);
2165
2166 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
2167 switch (type) {
2168 case 0:
2169 ShOp = ARM_AM::lsl;
2170 break;
2171 case 1:
2172 ShOp = ARM_AM::lsr;
2173 break;
2174 case 2:
2175 ShOp = ARM_AM::asr;
2176 break;
2177 case 3:
2178 ShOp = ARM_AM::ror;
2179 break;
2180 }
2181
2182 if (ShOp == ARM_AM::ror && imm == 0)
2183 ShOp = ARM_AM::rrx;
2184
2185 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
2186 return MCDisassembler::Fail;
2187 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
2188 return MCDisassembler::Fail;
2189 unsigned shift;
2190 if (U)
2191 shift = ARM_AM::getAM2Opc(Opc: ARM_AM::add, Imm12: imm, SO: ShOp);
2192 else
2193 shift = ARM_AM::getAM2Opc(Opc: ARM_AM::sub, Imm12: imm, SO: ShOp);
2194 Inst.addOperand(Op: MCOperand::createImm(Val: shift));
2195
2196 return S;
2197}
2198
2199static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn,
2200 uint64_t Address,
2201 const MCDisassembler *Decoder) {
2202 if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB)
2203 return MCDisassembler::Fail;
2204
2205 // The "csync" operand is not encoded into the "tsb" instruction (as this is
2206 // the only available operand), but LLVM expects the instruction to have one
2207 // operand, so we need to add the csync when decoding.
2208 Inst.addOperand(Op: MCOperand::createImm(Val: ARM_TSB::CSYNC));
2209 return MCDisassembler::Success;
2210}
2211
2212static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
2213 uint64_t Address,
2214 const MCDisassembler *Decoder) {
2215 DecodeStatus S = MCDisassembler::Success;
2216
2217 unsigned Rt = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
2218 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
2219 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
2220 unsigned type = fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1);
2221 unsigned imm = fieldFromInstruction(insn: Insn, startBit: 8, numBits: 4);
2222 unsigned U = ((~fieldFromInstruction(insn: Insn, startBit: 23, numBits: 1)) & 1) << 8;
2223 unsigned pred = fieldFromInstruction(insn: Insn, startBit: 28, numBits: 4);
2224 unsigned W = fieldFromInstruction(insn: Insn, startBit: 21, numBits: 1);
2225 unsigned P = fieldFromInstruction(insn: Insn, startBit: 24, numBits: 1);
2226 unsigned Rt2 = Rt + 1;
2227
2228 bool writeback = (W == 1) | (P == 0);
2229
2230 // For {LD,ST}RD, Rt must be even, else undefined.
2231 switch (Inst.getOpcode()) {
2232 case ARM::STRD:
2233 case ARM::STRD_PRE:
2234 case ARM::STRD_POST:
2235 case ARM::LDRD:
2236 case ARM::LDRD_PRE:
2237 case ARM::LDRD_POST:
2238 if (Rt & 0x1) S = MCDisassembler::SoftFail;
2239 break;
2240 default:
2241 break;
2242 }
2243 switch (Inst.getOpcode()) {
2244 case ARM::STRD:
2245 case ARM::STRD_PRE:
2246 case ARM::STRD_POST:
2247 if (P == 0 && W == 1)
2248 S = MCDisassembler::SoftFail;
2249
2250 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
2251 S = MCDisassembler::SoftFail;
2252 if (type && Rm == 15)
2253 S = MCDisassembler::SoftFail;
2254 if (Rt2 == 15)
2255 S = MCDisassembler::SoftFail;
2256 if (!type && fieldFromInstruction(insn: Insn, startBit: 8, numBits: 4))
2257 S = MCDisassembler::SoftFail;
2258 break;
2259 case ARM::STRH:
2260 case ARM::STRH_PRE:
2261 case ARM::STRH_POST:
2262 if (Rt == 15)
2263 S = MCDisassembler::SoftFail;
2264 if (writeback && (Rn == 15 || Rn == Rt))
2265 S = MCDisassembler::SoftFail;
2266 if (!type && Rm == 15)
2267 S = MCDisassembler::SoftFail;
2268 break;
2269 case ARM::LDRD:
2270 case ARM::LDRD_PRE:
2271 case ARM::LDRD_POST:
2272 if (type && Rn == 15) {
2273 if (Rt2 == 15)
2274 S = MCDisassembler::SoftFail;
2275 break;
2276 }
2277 if (P == 0 && W == 1)
2278 S = MCDisassembler::SoftFail;
2279 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2280 S = MCDisassembler::SoftFail;
2281 if (!type && writeback && Rn == 15)
2282 S = MCDisassembler::SoftFail;
2283 if (writeback && (Rn == Rt || Rn == Rt2))
2284 S = MCDisassembler::SoftFail;
2285 break;
2286 case ARM::LDRH:
2287 case ARM::LDRH_PRE:
2288 case ARM::LDRH_POST:
2289 if (type && Rn == 15) {
2290 if (Rt == 15)
2291 S = MCDisassembler::SoftFail;
2292 break;
2293 }
2294 if (Rt == 15)
2295 S = MCDisassembler::SoftFail;
2296 if (!type && Rm == 15)
2297 S = MCDisassembler::SoftFail;
2298 if (!type && writeback && (Rn == 15 || Rn == Rt))
2299 S = MCDisassembler::SoftFail;
2300 break;
2301 case ARM::LDRSH:
2302 case ARM::LDRSH_PRE:
2303 case ARM::LDRSH_POST:
2304 case ARM::LDRSB:
2305 case ARM::LDRSB_PRE:
2306 case ARM::LDRSB_POST:
2307 if (type && Rn == 15) {
2308 if (Rt == 15)
2309 S = MCDisassembler::SoftFail;
2310 break;
2311 }
2312 if (type && (Rt == 15 || (writeback && Rn == Rt)))
2313 S = MCDisassembler::SoftFail;
2314 if (!type && (Rt == 15 || Rm == 15))
2315 S = MCDisassembler::SoftFail;
2316 if (!type && writeback && (Rn == 15 || Rn == Rt))
2317 S = MCDisassembler::SoftFail;
2318 break;
2319 default:
2320 break;
2321 }
2322
2323 if (writeback) { // Writeback
2324 if (P)
2325 U |= ARMII::IndexModePre << 9;
2326 else
2327 U |= ARMII::IndexModePost << 9;
2328
2329 // On stores, the writeback operand precedes Rt.
2330 switch (Inst.getOpcode()) {
2331 case ARM::STRD:
2332 case ARM::STRD_PRE:
2333 case ARM::STRD_POST:
2334 case ARM::STRH:
2335 case ARM::STRH_PRE:
2336 case ARM::STRH_POST:
2337 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
2338 return MCDisassembler::Fail;
2339 break;
2340 default:
2341 break;
2342 }
2343 }
2344
2345 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rt, Address, Decoder)))
2346 return MCDisassembler::Fail;
2347 switch (Inst.getOpcode()) {
2348 case ARM::STRD:
2349 case ARM::STRD_PRE:
2350 case ARM::STRD_POST:
2351 case ARM::LDRD:
2352 case ARM::LDRD_PRE:
2353 case ARM::LDRD_POST:
2354 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rt+1, Address, Decoder)))
2355 return MCDisassembler::Fail;
2356 break;
2357 default:
2358 break;
2359 }
2360
2361 if (writeback) {
2362 // On loads, the writeback operand comes after Rt.
2363 switch (Inst.getOpcode()) {
2364 case ARM::LDRD:
2365 case ARM::LDRD_PRE:
2366 case ARM::LDRD_POST:
2367 case ARM::LDRH:
2368 case ARM::LDRH_PRE:
2369 case ARM::LDRH_POST:
2370 case ARM::LDRSH:
2371 case ARM::LDRSH_PRE:
2372 case ARM::LDRSH_POST:
2373 case ARM::LDRSB:
2374 case ARM::LDRSB_PRE:
2375 case ARM::LDRSB_POST:
2376 case ARM::LDRHTr:
2377 case ARM::LDRSBTr:
2378 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
2379 return MCDisassembler::Fail;
2380 break;
2381 default:
2382 break;
2383 }
2384 }
2385
2386 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
2387 return MCDisassembler::Fail;
2388
2389 if (type) {
2390 Inst.addOperand(Op: MCOperand::createReg(Reg: 0));
2391 Inst.addOperand(Op: MCOperand::createImm(Val: U | (imm << 4) | Rm));
2392 } else {
2393 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
2394 return MCDisassembler::Fail;
2395 Inst.addOperand(Op: MCOperand::createImm(Val: U));
2396 }
2397
2398 if (!Check(Out&: S, In: DecodePredicateOperand(Inst, Val: pred, Address, Decoder)))
2399 return MCDisassembler::Fail;
2400
2401 return S;
2402}
2403
2404static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
2405 uint64_t Address,
2406 const MCDisassembler *Decoder) {
2407 DecodeStatus S = MCDisassembler::Success;
2408
2409 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
2410 unsigned mode = fieldFromInstruction(insn: Insn, startBit: 23, numBits: 2);
2411
2412 switch (mode) {
2413 case 0:
2414 mode = ARM_AM::da;
2415 break;
2416 case 1:
2417 mode = ARM_AM::ia;
2418 break;
2419 case 2:
2420 mode = ARM_AM::db;
2421 break;
2422 case 3:
2423 mode = ARM_AM::ib;
2424 break;
2425 }
2426
2427 Inst.addOperand(Op: MCOperand::createImm(Val: mode));
2428 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
2429 return MCDisassembler::Fail;
2430
2431 return S;
2432}
2433
2434static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
2435 uint64_t Address,
2436 const MCDisassembler *Decoder) {
2437 DecodeStatus S = MCDisassembler::Success;
2438
2439 unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
2440 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
2441 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
2442 unsigned pred = fieldFromInstruction(insn: Insn, startBit: 28, numBits: 4);
2443
2444 if (pred == 0xF)
2445 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2446
2447 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
2448 return MCDisassembler::Fail;
2449 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
2450 return MCDisassembler::Fail;
2451 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
2452 return MCDisassembler::Fail;
2453 if (!Check(Out&: S, In: DecodePredicateOperand(Inst, Val: pred, Address, Decoder)))
2454 return MCDisassembler::Fail;
2455 return S;
2456}
2457
2458static DecodeStatus
2459DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn,
2460 uint64_t Address,
2461 const MCDisassembler *Decoder) {
2462 DecodeStatus S = MCDisassembler::Success;
2463
2464 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
2465 unsigned pred = fieldFromInstruction(insn: Insn, startBit: 28, numBits: 4);
2466 unsigned reglist = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 16);
2467
2468 if (pred == 0xF) {
2469 // Ambiguous with RFE and SRS
2470 switch (Inst.getOpcode()) {
2471 case ARM::LDMDA:
2472 Inst.setOpcode(ARM::RFEDA);
2473 break;
2474 case ARM::LDMDA_UPD:
2475 Inst.setOpcode(ARM::RFEDA_UPD);
2476 break;
2477 case ARM::LDMDB:
2478 Inst.setOpcode(ARM::RFEDB);
2479 break;
2480 case ARM::LDMDB_UPD:
2481 Inst.setOpcode(ARM::RFEDB_UPD);
2482 break;
2483 case ARM::LDMIA:
2484 Inst.setOpcode(ARM::RFEIA);
2485 break;
2486 case ARM::LDMIA_UPD:
2487 Inst.setOpcode(ARM::RFEIA_UPD);
2488 break;
2489 case ARM::LDMIB:
2490 Inst.setOpcode(ARM::RFEIB);
2491 break;
2492 case ARM::LDMIB_UPD:
2493 Inst.setOpcode(ARM::RFEIB_UPD);
2494 break;
2495 case ARM::STMDA:
2496 Inst.setOpcode(ARM::SRSDA);
2497 break;
2498 case ARM::STMDA_UPD:
2499 Inst.setOpcode(ARM::SRSDA_UPD);
2500 break;
2501 case ARM::STMDB:
2502 Inst.setOpcode(ARM::SRSDB);
2503 break;
2504 case ARM::STMDB_UPD:
2505 Inst.setOpcode(ARM::SRSDB_UPD);
2506 break;
2507 case ARM::STMIA:
2508 Inst.setOpcode(ARM::SRSIA);
2509 break;
2510 case ARM::STMIA_UPD:
2511 Inst.setOpcode(ARM::SRSIA_UPD);
2512 break;
2513 case ARM::STMIB:
2514 Inst.setOpcode(ARM::SRSIB);
2515 break;
2516 case ARM::STMIB_UPD:
2517 Inst.setOpcode(ARM::SRSIB_UPD);
2518 break;
2519 default:
2520 return MCDisassembler::Fail;
2521 }
2522
2523 // For stores (which become SRS's, the only operand is the mode.
2524 if (fieldFromInstruction(insn: Insn, startBit: 20, numBits: 1) == 0) {
2525 // Check SRS encoding constraints
2526 if (!(fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) == 1 &&
2527 fieldFromInstruction(insn: Insn, startBit: 20, numBits: 1) == 0))
2528 return MCDisassembler::Fail;
2529
2530 Inst.addOperand(
2531 Op: MCOperand::createImm(Val: fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4)));
2532 return S;
2533 }
2534
2535 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
2536 }
2537
2538 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
2539 return MCDisassembler::Fail;
2540 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
2541 return MCDisassembler::Fail; // Tied
2542 if (!Check(Out&: S, In: DecodePredicateOperand(Inst, Val: pred, Address, Decoder)))
2543 return MCDisassembler::Fail;
2544 if (!Check(Out&: S, In: DecodeRegListOperand(Inst, Val: reglist, Address, Decoder)))
2545 return MCDisassembler::Fail;
2546
2547 return S;
2548}
2549
2550// Check for UNPREDICTABLE predicated ESB instruction
2551static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
2552 uint64_t Address,
2553 const MCDisassembler *Decoder) {
2554 unsigned pred = fieldFromInstruction(insn: Insn, startBit: 28, numBits: 4);
2555 unsigned imm8 = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 8);
2556 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2557 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2558
2559 DecodeStatus S = MCDisassembler::Success;
2560
2561 Inst.addOperand(Op: MCOperand::createImm(Val: imm8));
2562
2563 if (!Check(Out&: S, In: DecodePredicateOperand(Inst, Val: pred, Address, Decoder)))
2564 return MCDisassembler::Fail;
2565
2566 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
2567 // so all predicates should be allowed.
2568 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
2569 S = MCDisassembler::SoftFail;
2570
2571 return S;
2572}
2573
2574static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
2575 uint64_t Address,
2576 const MCDisassembler *Decoder) {
2577 unsigned imod = fieldFromInstruction(insn: Insn, startBit: 18, numBits: 2);
2578 unsigned M = fieldFromInstruction(insn: Insn, startBit: 17, numBits: 1);
2579 unsigned iflags = fieldFromInstruction(insn: Insn, startBit: 6, numBits: 3);
2580 unsigned mode = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 5);
2581
2582 DecodeStatus S = MCDisassembler::Success;
2583
2584 // This decoder is called from multiple location that do not check
2585 // the full encoding is valid before they do.
2586 if (fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1) != 0 ||
2587 fieldFromInstruction(insn: Insn, startBit: 16, numBits: 1) != 0 ||
2588 fieldFromInstruction(insn: Insn, startBit: 20, numBits: 8) != 0x10)
2589 return MCDisassembler::Fail;
2590
2591 // imod == '01' --> UNPREDICTABLE
2592 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2593 // return failure here. The '01' imod value is unprintable, so there's
2594 // nothing useful we could do even if we returned UNPREDICTABLE.
2595
2596 if (imod == 1) return MCDisassembler::Fail;
2597
2598 if (imod && M) {
2599 Inst.setOpcode(ARM::CPS3p);
2600 Inst.addOperand(Op: MCOperand::createImm(Val: imod));
2601 Inst.addOperand(Op: MCOperand::createImm(Val: iflags));
2602 Inst.addOperand(Op: MCOperand::createImm(Val: mode));
2603 } else if (imod && !M) {
2604 Inst.setOpcode(ARM::CPS2p);
2605 Inst.addOperand(Op: MCOperand::createImm(Val: imod));
2606 Inst.addOperand(Op: MCOperand::createImm(Val: iflags));
2607 if (mode) S = MCDisassembler::SoftFail;
2608 } else if (!imod && M) {
2609 Inst.setOpcode(ARM::CPS1p);
2610 Inst.addOperand(Op: MCOperand::createImm(Val: mode));
2611 if (iflags) S = MCDisassembler::SoftFail;
2612 } else {
2613 // imod == '00' && M == '0' --> UNPREDICTABLE
2614 Inst.setOpcode(ARM::CPS1p);
2615 Inst.addOperand(Op: MCOperand::createImm(Val: mode));
2616 S = MCDisassembler::SoftFail;
2617 }
2618
2619 return S;
2620}
2621
2622static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
2623 uint64_t Address,
2624 const MCDisassembler *Decoder) {
2625 unsigned imod = fieldFromInstruction(insn: Insn, startBit: 9, numBits: 2);
2626 unsigned M = fieldFromInstruction(insn: Insn, startBit: 8, numBits: 1);
2627 unsigned iflags = fieldFromInstruction(insn: Insn, startBit: 5, numBits: 3);
2628 unsigned mode = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 5);
2629
2630 DecodeStatus S = MCDisassembler::Success;
2631
2632 // imod == '01' --> UNPREDICTABLE
2633 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2634 // return failure here. The '01' imod value is unprintable, so there's
2635 // nothing useful we could do even if we returned UNPREDICTABLE.
2636
2637 if (imod == 1) return MCDisassembler::Fail;
2638
2639 if (imod && M) {
2640 Inst.setOpcode(ARM::t2CPS3p);
2641 Inst.addOperand(Op: MCOperand::createImm(Val: imod));
2642 Inst.addOperand(Op: MCOperand::createImm(Val: iflags));
2643 Inst.addOperand(Op: MCOperand::createImm(Val: mode));
2644 } else if (imod && !M) {
2645 Inst.setOpcode(ARM::t2CPS2p);
2646 Inst.addOperand(Op: MCOperand::createImm(Val: imod));
2647 Inst.addOperand(Op: MCOperand::createImm(Val: iflags));
2648 if (mode) S = MCDisassembler::SoftFail;
2649 } else if (!imod && M) {
2650 Inst.setOpcode(ARM::t2CPS1p);
2651 Inst.addOperand(Op: MCOperand::createImm(Val: mode));
2652 if (iflags) S = MCDisassembler::SoftFail;
2653 } else {
2654 // imod == '00' && M == '0' --> this is a HINT instruction
2655 int imm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 8);
2656 // HINT are defined only for immediate in [0..4]
2657 if(imm > 4) return MCDisassembler::Fail;
2658 Inst.setOpcode(ARM::t2HINT);
2659 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
2660 }
2661
2662 return S;
2663}
2664
2665static DecodeStatus
2666DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
2667 const MCDisassembler *Decoder) {
2668 unsigned imm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 8);
2669
2670 unsigned Opcode = ARM::t2HINT;
2671
2672 if (imm == 0x0D) {
2673 Opcode = ARM::t2PACBTI;
2674 } else if (imm == 0x1D) {
2675 Opcode = ARM::t2PAC;
2676 } else if (imm == 0x2D) {
2677 Opcode = ARM::t2AUT;
2678 } else if (imm == 0x0F) {
2679 Opcode = ARM::t2BTI;
2680 }
2681
2682 Inst.setOpcode(Opcode);
2683 if (Opcode == ARM::t2HINT) {
2684 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
2685 }
2686
2687 return MCDisassembler::Success;
2688}
2689
2690static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2691 uint64_t Address,
2692 const MCDisassembler *Decoder) {
2693 DecodeStatus S = MCDisassembler::Success;
2694
2695 unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 8, numBits: 4);
2696 unsigned imm = 0;
2697
2698 imm |= (fieldFromInstruction(insn: Insn, startBit: 0, numBits: 8) << 0);
2699 imm |= (fieldFromInstruction(insn: Insn, startBit: 12, numBits: 3) << 8);
2700 imm |= (fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4) << 12);
2701 imm |= (fieldFromInstruction(insn: Insn, startBit: 26, numBits: 1) << 11);
2702
2703 if (Inst.getOpcode() == ARM::t2MOVTi16)
2704 if (!Check(Out&: S, In: DecoderGPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
2705 return MCDisassembler::Fail;
2706 if (!Check(Out&: S, In: DecoderGPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
2707 return MCDisassembler::Fail;
2708
2709 if (!tryAddingSymbolicOperand(Address, Value: imm, isBranch: false, InstSize: 4, MI&: Inst, Decoder))
2710 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
2711
2712 return S;
2713}
2714
2715static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2716 uint64_t Address,
2717 const MCDisassembler *Decoder) {
2718 DecodeStatus S = MCDisassembler::Success;
2719
2720 unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
2721 unsigned pred = fieldFromInstruction(insn: Insn, startBit: 28, numBits: 4);
2722 unsigned imm = 0;
2723
2724 imm |= (fieldFromInstruction(insn: Insn, startBit: 0, numBits: 12) << 0);
2725 imm |= (fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4) << 12);
2726
2727 if (Inst.getOpcode() == ARM::MOVTi16)
2728 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
2729 return MCDisassembler::Fail;
2730
2731 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
2732 return MCDisassembler::Fail;
2733
2734 if (!tryAddingSymbolicOperand(Address, Value: imm, isBranch: false, InstSize: 4, MI&: Inst, Decoder))
2735 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
2736
2737 if (!Check(Out&: S, In: DecodePredicateOperand(Inst, Val: pred, Address, Decoder)))
2738 return MCDisassembler::Fail;
2739
2740 return S;
2741}
2742
2743static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2744 uint64_t Address,
2745 const MCDisassembler *Decoder) {
2746 DecodeStatus S = MCDisassembler::Success;
2747
2748 unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
2749 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
2750 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 8, numBits: 4);
2751 unsigned Ra = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
2752 unsigned pred = fieldFromInstruction(insn: Insn, startBit: 28, numBits: 4);
2753
2754 if (pred == 0xF)
2755 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2756
2757 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
2758 return MCDisassembler::Fail;
2759 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
2760 return MCDisassembler::Fail;
2761 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
2762 return MCDisassembler::Fail;
2763 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Ra, Address, Decoder)))
2764 return MCDisassembler::Fail;
2765
2766 if (!Check(Out&: S, In: DecodePredicateOperand(Inst, Val: pred, Address, Decoder)))
2767 return MCDisassembler::Fail;
2768
2769 return S;
2770}
2771
2772static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
2773 uint64_t Address,
2774 const MCDisassembler *Decoder) {
2775 DecodeStatus S = MCDisassembler::Success;
2776
2777 unsigned Pred = fieldFromInstruction(insn: Insn, startBit: 28, numBits: 4);
2778 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
2779 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
2780
2781 if (Pred == 0xF)
2782 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2783
2784 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
2785 return MCDisassembler::Fail;
2786 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
2787 return MCDisassembler::Fail;
2788 if (!Check(Out&: S, In: DecodePredicateOperand(Inst, Val: Pred, Address, Decoder)))
2789 return MCDisassembler::Fail;
2790
2791 return S;
2792}
2793
2794static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
2795 uint64_t Address,
2796 const MCDisassembler *Decoder) {
2797 DecodeStatus S = MCDisassembler::Success;
2798
2799 unsigned Imm = fieldFromInstruction(insn: Insn, startBit: 9, numBits: 1);
2800
2801 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2802 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2803
2804 if (!FeatureBits[ARM::HasV8_1aOps] ||
2805 !FeatureBits[ARM::HasV8Ops])
2806 return MCDisassembler::Fail;
2807
2808 // Decoder can be called from DecodeTST, which does not check the full
2809 // encoding is valid.
2810 if (fieldFromInstruction(insn: Insn, startBit: 20,numBits: 12) != 0xf11 ||
2811 fieldFromInstruction(insn: Insn, startBit: 4,numBits: 4) != 0)
2812 return MCDisassembler::Fail;
2813 if (fieldFromInstruction(insn: Insn, startBit: 10,numBits: 10) != 0 ||
2814 fieldFromInstruction(insn: Insn, startBit: 0,numBits: 4) != 0)
2815 S = MCDisassembler::SoftFail;
2816
2817 Inst.setOpcode(ARM::SETPAN);
2818 Inst.addOperand(Op: MCOperand::createImm(Val: Imm));
2819
2820 return S;
2821}
2822
2823static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2824 uint64_t Address,
2825 const MCDisassembler *Decoder) {
2826 DecodeStatus S = MCDisassembler::Success;
2827
2828 unsigned add = fieldFromInstruction(insn: Val, startBit: 12, numBits: 1);
2829 unsigned imm = fieldFromInstruction(insn: Val, startBit: 0, numBits: 12);
2830 unsigned Rn = fieldFromInstruction(insn: Val, startBit: 13, numBits: 4);
2831
2832 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
2833 return MCDisassembler::Fail;
2834
2835 if (!add) imm *= -1;
2836 if (imm == 0 && !add) imm = INT32_MIN;
2837 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
2838 if (Rn == 15)
2839 tryAddingPcLoadReferenceComment(Address, Value: Address + imm + 8, Decoder);
2840
2841 return S;
2842}
2843
2844static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2845 uint64_t Address,
2846 const MCDisassembler *Decoder) {
2847 DecodeStatus S = MCDisassembler::Success;
2848
2849 unsigned Rn = fieldFromInstruction(insn: Val, startBit: 9, numBits: 4);
2850 // U == 1 to add imm, 0 to subtract it.
2851 unsigned U = fieldFromInstruction(insn: Val, startBit: 8, numBits: 1);
2852 unsigned imm = fieldFromInstruction(insn: Val, startBit: 0, numBits: 8);
2853
2854 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
2855 return MCDisassembler::Fail;
2856
2857 if (U)
2858 Inst.addOperand(Op: MCOperand::createImm(Val: ARM_AM::getAM5Opc(Opc: ARM_AM::add, Offset: imm)));
2859 else
2860 Inst.addOperand(Op: MCOperand::createImm(Val: ARM_AM::getAM5Opc(Opc: ARM_AM::sub, Offset: imm)));
2861
2862 return S;
2863}
2864
2865static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
2866 uint64_t Address,
2867 const MCDisassembler *Decoder) {
2868 DecodeStatus S = MCDisassembler::Success;
2869
2870 unsigned Rn = fieldFromInstruction(insn: Val, startBit: 9, numBits: 4);
2871 // U == 1 to add imm, 0 to subtract it.
2872 unsigned U = fieldFromInstruction(insn: Val, startBit: 8, numBits: 1);
2873 unsigned imm = fieldFromInstruction(insn: Val, startBit: 0, numBits: 8);
2874
2875 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
2876 return MCDisassembler::Fail;
2877
2878 if (U)
2879 Inst.addOperand(Op: MCOperand::createImm(Val: ARM_AM::getAM5FP16Opc(Opc: ARM_AM::add, Offset: imm)));
2880 else
2881 Inst.addOperand(Op: MCOperand::createImm(Val: ARM_AM::getAM5FP16Opc(Opc: ARM_AM::sub, Offset: imm)));
2882
2883 return S;
2884}
2885
2886static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2887 uint64_t Address,
2888 const MCDisassembler *Decoder) {
2889 return DecodeGPRRegisterClass(Inst, RegNo: Val, Address, Decoder);
2890}
2891
2892static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2893 uint64_t Address,
2894 const MCDisassembler *Decoder) {
2895 DecodeStatus Status = MCDisassembler::Success;
2896
2897 // Note the J1 and J2 values are from the encoded instruction. So here
2898 // change them to I1 and I2 values via as documented:
2899 // I1 = NOT(J1 EOR S);
2900 // I2 = NOT(J2 EOR S);
2901 // and build the imm32 with one trailing zero as documented:
2902 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2903 unsigned S = fieldFromInstruction(insn: Insn, startBit: 26, numBits: 1);
2904 unsigned J1 = fieldFromInstruction(insn: Insn, startBit: 13, numBits: 1);
2905 unsigned J2 = fieldFromInstruction(insn: Insn, startBit: 11, numBits: 1);
2906 unsigned I1 = !(J1 ^ S);
2907 unsigned I2 = !(J2 ^ S);
2908 unsigned imm10 = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 10);
2909 unsigned imm11 = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 11);
2910 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2911 int imm32 = SignExtend32<25>(X: tmp << 1);
2912 if (!tryAddingSymbolicOperand(Address, Value: Address + imm32 + 4,
2913 isBranch: true, InstSize: 4, MI&: Inst, Decoder))
2914 Inst.addOperand(Op: MCOperand::createImm(Val: imm32));
2915
2916 return Status;
2917}
2918
2919static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2920 uint64_t Address,
2921 const MCDisassembler *Decoder) {
2922 DecodeStatus S = MCDisassembler::Success;
2923
2924 unsigned pred = fieldFromInstruction(insn: Insn, startBit: 28, numBits: 4);
2925 unsigned imm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 24) << 2;
2926
2927 if (pred == 0xF) {
2928 Inst.setOpcode(ARM::BLXi);
2929 imm |= fieldFromInstruction(insn: Insn, startBit: 24, numBits: 1) << 1;
2930 if (!tryAddingSymbolicOperand(Address, Value: Address + SignExtend32<26>(X: imm) + 8,
2931 isBranch: true, InstSize: 4, MI&: Inst, Decoder))
2932 Inst.addOperand(Op: MCOperand::createImm(Val: SignExtend32<26>(X: imm)));
2933 return S;
2934 }
2935
2936 if (!tryAddingSymbolicOperand(Address, Value: Address + SignExtend32<26>(X: imm) + 8,
2937 isBranch: true, InstSize: 4, MI&: Inst, Decoder))
2938 Inst.addOperand(Op: MCOperand::createImm(Val: SignExtend32<26>(X: imm)));
2939
2940 // We already have BL_pred for BL w/ predicate, no need to add addition
2941 // predicate opreands for BL
2942 if (Inst.getOpcode() != ARM::BL)
2943 if (!Check(Out&: S, In: DecodePredicateOperand(Inst, Val: pred, Address, Decoder)))
2944 return MCDisassembler::Fail;
2945
2946 return S;
2947}
2948
2949static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2950 uint64_t Address,
2951 const MCDisassembler *Decoder) {
2952 DecodeStatus S = MCDisassembler::Success;
2953
2954 unsigned Rm = fieldFromInstruction(insn: Val, startBit: 0, numBits: 4);
2955 unsigned align = fieldFromInstruction(insn: Val, startBit: 4, numBits: 2);
2956
2957 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
2958 return MCDisassembler::Fail;
2959 if (!align)
2960 Inst.addOperand(Op: MCOperand::createImm(Val: 0));
2961 else
2962 Inst.addOperand(Op: MCOperand::createImm(Val: 4 << align));
2963
2964 return S;
2965}
2966
2967static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2968 uint64_t Address,
2969 const MCDisassembler *Decoder) {
2970 DecodeStatus S = MCDisassembler::Success;
2971
2972 unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
2973 Rd |= fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 4;
2974 unsigned wb = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
2975 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
2976 Rn |= fieldFromInstruction(insn: Insn, startBit: 4, numBits: 2) << 4;
2977 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
2978
2979 // First output register
2980 switch (Inst.getOpcode()) {
2981 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2982 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2983 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2984 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2985 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2986 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2987 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2988 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2989 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2990 if (!Check(Out&: S, In: DecodeDPairRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
2991 return MCDisassembler::Fail;
2992 break;
2993 case ARM::VLD2b16:
2994 case ARM::VLD2b32:
2995 case ARM::VLD2b8:
2996 case ARM::VLD2b16wb_fixed:
2997 case ARM::VLD2b16wb_register:
2998 case ARM::VLD2b32wb_fixed:
2999 case ARM::VLD2b32wb_register:
3000 case ARM::VLD2b8wb_fixed:
3001 case ARM::VLD2b8wb_register:
3002 if (!Check(Out&: S, In: DecodeDPairSpacedRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
3003 return MCDisassembler::Fail;
3004 break;
3005 default:
3006 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
3007 return MCDisassembler::Fail;
3008 }
3009
3010 // Second output register
3011 switch (Inst.getOpcode()) {
3012 case ARM::VLD3d8:
3013 case ARM::VLD3d16:
3014 case ARM::VLD3d32:
3015 case ARM::VLD3d8_UPD:
3016 case ARM::VLD3d16_UPD:
3017 case ARM::VLD3d32_UPD:
3018 case ARM::VLD4d8:
3019 case ARM::VLD4d16:
3020 case ARM::VLD4d32:
3021 case ARM::VLD4d8_UPD:
3022 case ARM::VLD4d16_UPD:
3023 case ARM::VLD4d32_UPD:
3024 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: (Rd+1)%32, Address, Decoder)))
3025 return MCDisassembler::Fail;
3026 break;
3027 case ARM::VLD3q8:
3028 case ARM::VLD3q16:
3029 case ARM::VLD3q32:
3030 case ARM::VLD3q8_UPD:
3031 case ARM::VLD3q16_UPD:
3032 case ARM::VLD3q32_UPD:
3033 case ARM::VLD4q8:
3034 case ARM::VLD4q16:
3035 case ARM::VLD4q32:
3036 case ARM::VLD4q8_UPD:
3037 case ARM::VLD4q16_UPD:
3038 case ARM::VLD4q32_UPD:
3039 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: (Rd+2)%32, Address, Decoder)))
3040 return MCDisassembler::Fail;
3041 break;
3042 default:
3043 break;
3044 }
3045
3046 // Third output register
3047 switch(Inst.getOpcode()) {
3048 case ARM::VLD3d8:
3049 case ARM::VLD3d16:
3050 case ARM::VLD3d32:
3051 case ARM::VLD3d8_UPD:
3052 case ARM::VLD3d16_UPD:
3053 case ARM::VLD3d32_UPD:
3054 case ARM::VLD4d8:
3055 case ARM::VLD4d16:
3056 case ARM::VLD4d32:
3057 case ARM::VLD4d8_UPD:
3058 case ARM::VLD4d16_UPD:
3059 case ARM::VLD4d32_UPD:
3060 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: (Rd+2)%32, Address, Decoder)))
3061 return MCDisassembler::Fail;
3062 break;
3063 case ARM::VLD3q8:
3064 case ARM::VLD3q16:
3065 case ARM::VLD3q32:
3066 case ARM::VLD3q8_UPD:
3067 case ARM::VLD3q16_UPD:
3068 case ARM::VLD3q32_UPD:
3069 case ARM::VLD4q8:
3070 case ARM::VLD4q16:
3071 case ARM::VLD4q32:
3072 case ARM::VLD4q8_UPD:
3073 case ARM::VLD4q16_UPD:
3074 case ARM::VLD4q32_UPD:
3075 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: (Rd+4)%32, Address, Decoder)))
3076 return MCDisassembler::Fail;
3077 break;
3078 default:
3079 break;
3080 }
3081
3082 // Fourth output register
3083 switch (Inst.getOpcode()) {
3084 case ARM::VLD4d8:
3085 case ARM::VLD4d16:
3086 case ARM::VLD4d32:
3087 case ARM::VLD4d8_UPD:
3088 case ARM::VLD4d16_UPD:
3089 case ARM::VLD4d32_UPD:
3090 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: (Rd+3)%32, Address, Decoder)))
3091 return MCDisassembler::Fail;
3092 break;
3093 case ARM::VLD4q8:
3094 case ARM::VLD4q16:
3095 case ARM::VLD4q32:
3096 case ARM::VLD4q8_UPD:
3097 case ARM::VLD4q16_UPD:
3098 case ARM::VLD4q32_UPD:
3099 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: (Rd+6)%32, Address, Decoder)))
3100 return MCDisassembler::Fail;
3101 break;
3102 default:
3103 break;
3104 }
3105
3106 // Writeback operand
3107 switch (Inst.getOpcode()) {
3108 case ARM::VLD1d8wb_fixed:
3109 case ARM::VLD1d16wb_fixed:
3110 case ARM::VLD1d32wb_fixed:
3111 case ARM::VLD1d64wb_fixed:
3112 case ARM::VLD1d8wb_register:
3113 case ARM::VLD1d16wb_register:
3114 case ARM::VLD1d32wb_register:
3115 case ARM::VLD1d64wb_register:
3116 case ARM::VLD1q8wb_fixed:
3117 case ARM::VLD1q16wb_fixed:
3118 case ARM::VLD1q32wb_fixed:
3119 case ARM::VLD1q64wb_fixed:
3120 case ARM::VLD1q8wb_register:
3121 case ARM::VLD1q16wb_register:
3122 case ARM::VLD1q32wb_register:
3123 case ARM::VLD1q64wb_register:
3124 case ARM::VLD1d8Twb_fixed:
3125 case ARM::VLD1d8Twb_register:
3126 case ARM::VLD1d16Twb_fixed:
3127 case ARM::VLD1d16Twb_register:
3128 case ARM::VLD1d32Twb_fixed:
3129 case ARM::VLD1d32Twb_register:
3130 case ARM::VLD1d64Twb_fixed:
3131 case ARM::VLD1d64Twb_register:
3132 case ARM::VLD1d8Qwb_fixed:
3133 case ARM::VLD1d8Qwb_register:
3134 case ARM::VLD1d16Qwb_fixed:
3135 case ARM::VLD1d16Qwb_register:
3136 case ARM::VLD1d32Qwb_fixed:
3137 case ARM::VLD1d32Qwb_register:
3138 case ARM::VLD1d64Qwb_fixed:
3139 case ARM::VLD1d64Qwb_register:
3140 case ARM::VLD2d8wb_fixed:
3141 case ARM::VLD2d16wb_fixed:
3142 case ARM::VLD2d32wb_fixed:
3143 case ARM::VLD2q8wb_fixed:
3144 case ARM::VLD2q16wb_fixed:
3145 case ARM::VLD2q32wb_fixed:
3146 case ARM::VLD2d8wb_register:
3147 case ARM::VLD2d16wb_register:
3148 case ARM::VLD2d32wb_register:
3149 case ARM::VLD2q8wb_register:
3150 case ARM::VLD2q16wb_register:
3151 case ARM::VLD2q32wb_register:
3152 case ARM::VLD2b8wb_fixed:
3153 case ARM::VLD2b16wb_fixed:
3154 case ARM::VLD2b32wb_fixed:
3155 case ARM::VLD2b8wb_register:
3156 case ARM::VLD2b16wb_register:
3157 case ARM::VLD2b32wb_register:
3158 Inst.addOperand(Op: MCOperand::createImm(Val: 0));
3159 break;
3160 case ARM::VLD3d8_UPD:
3161 case ARM::VLD3d16_UPD:
3162 case ARM::VLD3d32_UPD:
3163 case ARM::VLD3q8_UPD:
3164 case ARM::VLD3q16_UPD:
3165 case ARM::VLD3q32_UPD:
3166 case ARM::VLD4d8_UPD:
3167 case ARM::VLD4d16_UPD:
3168 case ARM::VLD4d32_UPD:
3169 case ARM::VLD4q8_UPD:
3170 case ARM::VLD4q16_UPD:
3171 case ARM::VLD4q32_UPD:
3172 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: wb, Address, Decoder)))
3173 return MCDisassembler::Fail;
3174 break;
3175 default:
3176 break;
3177 }
3178
3179 // AddrMode6 Base (register+alignment)
3180 if (!Check(Out&: S, In: DecodeAddrMode6Operand(Inst, Val: Rn, Address, Decoder)))
3181 return MCDisassembler::Fail;
3182
3183 // AddrMode6 Offset (register)
3184 switch (Inst.getOpcode()) {
3185 default:
3186 // The below have been updated to have explicit am6offset split
3187 // between fixed and register offset. For those instructions not
3188 // yet updated, we need to add an additional reg0 operand for the
3189 // fixed variant.
3190 //
3191 // The fixed offset encodes as Rm == 0xd, so we check for that.
3192 if (Rm == 0xd) {
3193 Inst.addOperand(Op: MCOperand::createReg(Reg: 0));
3194 break;
3195 }
3196 // Fall through to handle the register offset variant.
3197 [[fallthrough]];
3198 case ARM::VLD1d8wb_fixed:
3199 case ARM::VLD1d16wb_fixed:
3200 case ARM::VLD1d32wb_fixed:
3201 case ARM::VLD1d64wb_fixed:
3202 case ARM::VLD1d8Twb_fixed:
3203 case ARM::VLD1d16Twb_fixed:
3204 case ARM::VLD1d32Twb_fixed:
3205 case ARM::VLD1d64Twb_fixed:
3206 case ARM::VLD1d8Qwb_fixed:
3207 case ARM::VLD1d16Qwb_fixed:
3208 case ARM::VLD1d32Qwb_fixed:
3209 case ARM::VLD1d64Qwb_fixed:
3210 case ARM::VLD1d8wb_register:
3211 case ARM::VLD1d16wb_register:
3212 case ARM::VLD1d32wb_register:
3213 case ARM::VLD1d64wb_register:
3214 case ARM::VLD1q8wb_fixed:
3215 case ARM::VLD1q16wb_fixed:
3216 case ARM::VLD1q32wb_fixed:
3217 case ARM::VLD1q64wb_fixed:
3218 case ARM::VLD1q8wb_register:
3219 case ARM::VLD1q16wb_register:
3220 case ARM::VLD1q32wb_register:
3221 case ARM::VLD1q64wb_register:
3222 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
3223 // variant encodes Rm == 0xf. Anything else is a register offset post-
3224 // increment and we need to add the register operand to the instruction.
3225 if (Rm != 0xD && Rm != 0xF &&
3226 !Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
3227 return MCDisassembler::Fail;
3228 break;
3229 case ARM::VLD2d8wb_fixed:
3230 case ARM::VLD2d16wb_fixed:
3231 case ARM::VLD2d32wb_fixed:
3232 case ARM::VLD2b8wb_fixed:
3233 case ARM::VLD2b16wb_fixed:
3234 case ARM::VLD2b32wb_fixed:
3235 case ARM::VLD2q8wb_fixed:
3236 case ARM::VLD2q16wb_fixed:
3237 case ARM::VLD2q32wb_fixed:
3238 break;
3239 }
3240
3241 return S;
3242}
3243
3244static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
3245 uint64_t Address,
3246 const MCDisassembler *Decoder) {
3247 unsigned type = fieldFromInstruction(insn: Insn, startBit: 8, numBits: 4);
3248 unsigned align = fieldFromInstruction(insn: Insn, startBit: 4, numBits: 2);
3249 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
3250 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
3251 if (type == 10 && align == 3) return MCDisassembler::Fail;
3252
3253 unsigned load = fieldFromInstruction(insn: Insn, startBit: 21, numBits: 1);
3254 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3255 : DecodeVSTInstruction(Inst, Val: Insn, Address, Decoder);
3256}
3257
3258static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
3259 uint64_t Address,
3260 const MCDisassembler *Decoder) {
3261 unsigned size = fieldFromInstruction(insn: Insn, startBit: 6, numBits: 2);
3262 if (size == 3) return MCDisassembler::Fail;
3263
3264 unsigned type = fieldFromInstruction(insn: Insn, startBit: 8, numBits: 4);
3265 unsigned align = fieldFromInstruction(insn: Insn, startBit: 4, numBits: 2);
3266 if (type == 8 && align == 3) return MCDisassembler::Fail;
3267 if (type == 9 && align == 3) return MCDisassembler::Fail;
3268
3269 unsigned load = fieldFromInstruction(insn: Insn, startBit: 21, numBits: 1);
3270 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3271 : DecodeVSTInstruction(Inst, Val: Insn, Address, Decoder);
3272}
3273
3274static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
3275 uint64_t Address,
3276 const MCDisassembler *Decoder) {
3277 unsigned size = fieldFromInstruction(insn: Insn, startBit: 6, numBits: 2);
3278 if (size == 3) return MCDisassembler::Fail;
3279
3280 unsigned align = fieldFromInstruction(insn: Insn, startBit: 4, numBits: 2);
3281 if (align & 2) return MCDisassembler::Fail;
3282
3283 unsigned load = fieldFromInstruction(insn: Insn, startBit: 21, numBits: 1);
3284 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3285 : DecodeVSTInstruction(Inst, Val: Insn, Address, Decoder);
3286}
3287
3288static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
3289 uint64_t Address,
3290 const MCDisassembler *Decoder) {
3291 unsigned size = fieldFromInstruction(insn: Insn, startBit: 6, numBits: 2);
3292 if (size == 3) return MCDisassembler::Fail;
3293
3294 unsigned load = fieldFromInstruction(insn: Insn, startBit: 21, numBits: 1);
3295 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3296 : DecodeVSTInstruction(Inst, Val: Insn, Address, Decoder);
3297}
3298
3299static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
3300 uint64_t Address,
3301 const MCDisassembler *Decoder) {
3302 DecodeStatus S = MCDisassembler::Success;
3303
3304 unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
3305 Rd |= fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 4;
3306 unsigned wb = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
3307 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
3308 Rn |= fieldFromInstruction(insn: Insn, startBit: 4, numBits: 2) << 4;
3309 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
3310
3311 // Writeback Operand
3312 switch (Inst.getOpcode()) {
3313 case ARM::VST1d8wb_fixed:
3314 case ARM::VST1d16wb_fixed:
3315 case ARM::VST1d32wb_fixed:
3316 case ARM::VST1d64wb_fixed:
3317 case ARM::VST1d8wb_register:
3318 case ARM::VST1d16wb_register:
3319 case ARM::VST1d32wb_register:
3320 case ARM::VST1d64wb_register:
3321 case ARM::VST1q8wb_fixed:
3322 case ARM::VST1q16wb_fixed:
3323 case ARM::VST1q32wb_fixed:
3324 case ARM::VST1q64wb_fixed:
3325 case ARM::VST1q8wb_register:
3326 case ARM::VST1q16wb_register:
3327 case ARM::VST1q32wb_register:
3328 case ARM::VST1q64wb_register:
3329 case ARM::VST1d8Twb_fixed:
3330 case ARM::VST1d16Twb_fixed:
3331 case ARM::VST1d32Twb_fixed:
3332 case ARM::VST1d64Twb_fixed:
3333 case ARM::VST1d8Twb_register:
3334 case ARM::VST1d16Twb_register:
3335 case ARM::VST1d32Twb_register:
3336 case ARM::VST1d64Twb_register:
3337 case ARM::VST1d8Qwb_fixed:
3338 case ARM::VST1d16Qwb_fixed:
3339 case ARM::VST1d32Qwb_fixed:
3340 case ARM::VST1d64Qwb_fixed:
3341 case ARM::VST1d8Qwb_register:
3342 case ARM::VST1d16Qwb_register:
3343 case ARM::VST1d32Qwb_register:
3344 case ARM::VST1d64Qwb_register:
3345 case ARM::VST2d8wb_fixed:
3346 case ARM::VST2d16wb_fixed:
3347 case ARM::VST2d32wb_fixed:
3348 case ARM::VST2d8wb_register:
3349 case ARM::VST2d16wb_register:
3350 case ARM::VST2d32wb_register:
3351 case ARM::VST2q8wb_fixed:
3352 case ARM::VST2q16wb_fixed:
3353 case ARM::VST2q32wb_fixed:
3354 case ARM::VST2q8wb_register:
3355 case ARM::VST2q16wb_register:
3356 case ARM::VST2q32wb_register:
3357 case ARM::VST2b8wb_fixed:
3358 case ARM::VST2b16wb_fixed:
3359 case ARM::VST2b32wb_fixed:
3360 case ARM::VST2b8wb_register:
3361 case ARM::VST2b16wb_register:
3362 case ARM::VST2b32wb_register:
3363 if (Rm == 0xF)
3364 return MCDisassembler::Fail;
3365 Inst.addOperand(Op: MCOperand::createImm(Val: 0));
3366 break;
3367 case ARM::VST3d8_UPD:
3368 case ARM::VST3d16_UPD:
3369 case ARM::VST3d32_UPD:
3370 case ARM::VST3q8_UPD:
3371 case ARM::VST3q16_UPD:
3372 case ARM::VST3q32_UPD:
3373 case ARM::VST4d8_UPD:
3374 case ARM::VST4d16_UPD:
3375 case ARM::VST4d32_UPD:
3376 case ARM::VST4q8_UPD:
3377 case ARM::VST4q16_UPD:
3378 case ARM::VST4q32_UPD:
3379 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: wb, Address, Decoder)))
3380 return MCDisassembler::Fail;
3381 break;
3382 default:
3383 break;
3384 }
3385
3386 // AddrMode6 Base (register+alignment)
3387 if (!Check(Out&: S, In: DecodeAddrMode6Operand(Inst, Val: Rn, Address, Decoder)))
3388 return MCDisassembler::Fail;
3389
3390 // AddrMode6 Offset (register)
3391 switch (Inst.getOpcode()) {
3392 default:
3393 if (Rm == 0xD)
3394 Inst.addOperand(Op: MCOperand::createReg(Reg: 0));
3395 else if (Rm != 0xF) {
3396 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
3397 return MCDisassembler::Fail;
3398 }
3399 break;
3400 case ARM::VST1d8wb_fixed:
3401 case ARM::VST1d16wb_fixed:
3402 case ARM::VST1d32wb_fixed:
3403 case ARM::VST1d64wb_fixed:
3404 case ARM::VST1q8wb_fixed:
3405 case ARM::VST1q16wb_fixed:
3406 case ARM::VST1q32wb_fixed:
3407 case ARM::VST1q64wb_fixed:
3408 case ARM::VST1d8Twb_fixed:
3409 case ARM::VST1d16Twb_fixed:
3410 case ARM::VST1d32Twb_fixed:
3411 case ARM::VST1d64Twb_fixed:
3412 case ARM::VST1d8Qwb_fixed:
3413 case ARM::VST1d16Qwb_fixed:
3414 case ARM::VST1d32Qwb_fixed:
3415 case ARM::VST1d64Qwb_fixed:
3416 case ARM::VST2d8wb_fixed:
3417 case ARM::VST2d16wb_fixed:
3418 case ARM::VST2d32wb_fixed:
3419 case ARM::VST2q8wb_fixed:
3420 case ARM::VST2q16wb_fixed:
3421 case ARM::VST2q32wb_fixed:
3422 case ARM::VST2b8wb_fixed:
3423 case ARM::VST2b16wb_fixed:
3424 case ARM::VST2b32wb_fixed:
3425 break;
3426 }
3427
3428 // First input register
3429 switch (Inst.getOpcode()) {
3430 case ARM::VST1q16:
3431 case ARM::VST1q32:
3432 case ARM::VST1q64:
3433 case ARM::VST1q8:
3434 case ARM::VST1q16wb_fixed:
3435 case ARM::VST1q16wb_register:
3436 case ARM::VST1q32wb_fixed:
3437 case ARM::VST1q32wb_register:
3438 case ARM::VST1q64wb_fixed:
3439 case ARM::VST1q64wb_register:
3440 case ARM::VST1q8wb_fixed:
3441 case ARM::VST1q8wb_register:
3442 case ARM::VST2d16:
3443 case ARM::VST2d32:
3444 case ARM::VST2d8:
3445 case ARM::VST2d16wb_fixed:
3446 case ARM::VST2d16wb_register:
3447 case ARM::VST2d32wb_fixed:
3448 case ARM::VST2d32wb_register:
3449 case ARM::VST2d8wb_fixed:
3450 case ARM::VST2d8wb_register:
3451 if (!Check(Out&: S, In: DecodeDPairRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
3452 return MCDisassembler::Fail;
3453 break;
3454 case ARM::VST2b16:
3455 case ARM::VST2b32:
3456 case ARM::VST2b8:
3457 case ARM::VST2b16wb_fixed:
3458 case ARM::VST2b16wb_register:
3459 case ARM::VST2b32wb_fixed:
3460 case ARM::VST2b32wb_register:
3461 case ARM::VST2b8wb_fixed:
3462 case ARM::VST2b8wb_register:
3463 if (!Check(Out&: S, In: DecodeDPairSpacedRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
3464 return MCDisassembler::Fail;
3465 break;
3466 default:
3467 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
3468 return MCDisassembler::Fail;
3469 }
3470
3471 // Second input register
3472 switch (Inst.getOpcode()) {
3473 case ARM::VST3d8:
3474 case ARM::VST3d16:
3475 case ARM::VST3d32:
3476 case ARM::VST3d8_UPD:
3477 case ARM::VST3d16_UPD:
3478 case ARM::VST3d32_UPD:
3479 case ARM::VST4d8:
3480 case ARM::VST4d16:
3481 case ARM::VST4d32:
3482 case ARM::VST4d8_UPD:
3483 case ARM::VST4d16_UPD:
3484 case ARM::VST4d32_UPD:
3485 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: (Rd+1)%32, Address, Decoder)))
3486 return MCDisassembler::Fail;
3487 break;
3488 case ARM::VST3q8:
3489 case ARM::VST3q16:
3490 case ARM::VST3q32:
3491 case ARM::VST3q8_UPD:
3492 case ARM::VST3q16_UPD:
3493 case ARM::VST3q32_UPD:
3494 case ARM::VST4q8:
3495 case ARM::VST4q16:
3496 case ARM::VST4q32:
3497 case ARM::VST4q8_UPD:
3498 case ARM::VST4q16_UPD:
3499 case ARM::VST4q32_UPD:
3500 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: (Rd+2)%32, Address, Decoder)))
3501 return MCDisassembler::Fail;
3502 break;
3503 default:
3504 break;
3505 }
3506
3507 // Third input register
3508 switch (Inst.getOpcode()) {
3509 case ARM::VST3d8:
3510 case ARM::VST3d16:
3511 case ARM::VST3d32:
3512 case ARM::VST3d8_UPD:
3513 case ARM::VST3d16_UPD:
3514 case ARM::VST3d32_UPD:
3515 case ARM::VST4d8:
3516 case ARM::VST4d16:
3517 case ARM::VST4d32:
3518 case ARM::VST4d8_UPD:
3519 case ARM::VST4d16_UPD:
3520 case ARM::VST4d32_UPD:
3521 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: (Rd+2)%32, Address, Decoder)))
3522 return MCDisassembler::Fail;
3523 break;
3524 case ARM::VST3q8:
3525 case ARM::VST3q16:
3526 case ARM::VST3q32:
3527 case ARM::VST3q8_UPD:
3528 case ARM::VST3q16_UPD:
3529 case ARM::VST3q32_UPD:
3530 case ARM::VST4q8:
3531 case ARM::VST4q16:
3532 case ARM::VST4q32:
3533 case ARM::VST4q8_UPD:
3534 case ARM::VST4q16_UPD:
3535 case ARM::VST4q32_UPD:
3536 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: (Rd+4)%32, Address, Decoder)))
3537 return MCDisassembler::Fail;
3538 break;
3539 default:
3540 break;
3541 }
3542
3543 // Fourth input register
3544 switch (Inst.getOpcode()) {
3545 case ARM::VST4d8:
3546 case ARM::VST4d16:
3547 case ARM::VST4d32:
3548 case ARM::VST4d8_UPD:
3549 case ARM::VST4d16_UPD:
3550 case ARM::VST4d32_UPD:
3551 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: (Rd+3)%32, Address, Decoder)))
3552 return MCDisassembler::Fail;
3553 break;
3554 case ARM::VST4q8:
3555 case ARM::VST4q16:
3556 case ARM::VST4q32:
3557 case ARM::VST4q8_UPD:
3558 case ARM::VST4q16_UPD:
3559 case ARM::VST4q32_UPD:
3560 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: (Rd+6)%32, Address, Decoder)))
3561 return MCDisassembler::Fail;
3562 break;
3563 default:
3564 break;
3565 }
3566
3567 return S;
3568}
3569
3570static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
3571 uint64_t Address,
3572 const MCDisassembler *Decoder) {
3573 DecodeStatus S = MCDisassembler::Success;
3574
3575 unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
3576 Rd |= fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 4;
3577 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
3578 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
3579 unsigned align = fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1);
3580 unsigned size = fieldFromInstruction(insn: Insn, startBit: 6, numBits: 2);
3581
3582 if (size == 0 && align == 1)
3583 return MCDisassembler::Fail;
3584 align *= (1 << size);
3585
3586 switch (Inst.getOpcode()) {
3587 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
3588 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
3589 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
3590 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
3591 if (!Check(Out&: S, In: DecodeDPairRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
3592 return MCDisassembler::Fail;
3593 break;
3594 default:
3595 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
3596 return MCDisassembler::Fail;
3597 break;
3598 }
3599 if (Rm != 0xF) {
3600 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
3601 return MCDisassembler::Fail;
3602 }
3603
3604 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
3605 return MCDisassembler::Fail;
3606 Inst.addOperand(Op: MCOperand::createImm(Val: align));
3607
3608 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
3609 // variant encodes Rm == 0xf. Anything else is a register offset post-
3610 // increment and we need to add the register operand to the instruction.
3611 if (Rm != 0xD && Rm != 0xF &&
3612 !Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
3613 return MCDisassembler::Fail;
3614
3615 return S;
3616}
3617
3618static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
3619 uint64_t Address,
3620 const MCDisassembler *Decoder) {
3621 DecodeStatus S = MCDisassembler::Success;
3622
3623 unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
3624 Rd |= fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 4;
3625 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
3626 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
3627 unsigned align = fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1);
3628 unsigned size = 1 << fieldFromInstruction(insn: Insn, startBit: 6, numBits: 2);
3629 align *= 2*size;
3630
3631 switch (Inst.getOpcode()) {
3632 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
3633 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
3634 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
3635 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
3636 if (!Check(Out&: S, In: DecodeDPairRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
3637 return MCDisassembler::Fail;
3638 break;
3639 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
3640 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
3641 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
3642 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
3643 if (!Check(Out&: S, In: DecodeDPairSpacedRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
3644 return MCDisassembler::Fail;
3645 break;
3646 default:
3647 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
3648 return MCDisassembler::Fail;
3649 break;
3650 }
3651
3652 if (Rm != 0xF)
3653 Inst.addOperand(Op: MCOperand::createImm(Val: 0));
3654
3655 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
3656 return MCDisassembler::Fail;
3657 Inst.addOperand(Op: MCOperand::createImm(Val: align));
3658
3659 if (Rm != 0xD && Rm != 0xF) {
3660 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
3661 return MCDisassembler::Fail;
3662 }
3663
3664 return S;
3665}
3666
3667static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
3668 uint64_t Address,
3669 const MCDisassembler *Decoder) {
3670 DecodeStatus S = MCDisassembler::Success;
3671
3672 unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
3673 Rd |= fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 4;
3674 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
3675 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
3676 unsigned inc = fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1) + 1;
3677
3678 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
3679 return MCDisassembler::Fail;
3680 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: (Rd+inc)%32, Address, Decoder)))
3681 return MCDisassembler::Fail;
3682 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: (Rd+2*inc)%32, Address, Decoder)))
3683 return MCDisassembler::Fail;
3684 if (Rm != 0xF) {
3685 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
3686 return MCDisassembler::Fail;
3687 }
3688
3689 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
3690 return MCDisassembler::Fail;
3691 Inst.addOperand(Op: MCOperand::createImm(Val: 0));
3692
3693 if (Rm == 0xD)
3694 Inst.addOperand(Op: MCOperand::createReg(Reg: 0));
3695 else if (Rm != 0xF) {
3696 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
3697 return MCDisassembler::Fail;
3698 }
3699
3700 return S;
3701}
3702
3703static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
3704 uint64_t Address,
3705 const MCDisassembler *Decoder) {
3706 DecodeStatus S = MCDisassembler::Success;
3707
3708 unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
3709 Rd |= fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 4;
3710 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
3711 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
3712 unsigned size = fieldFromInstruction(insn: Insn, startBit: 6, numBits: 2);
3713 unsigned inc = fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1) + 1;
3714 unsigned align = fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1);
3715
3716 if (size == 0x3) {
3717 if (align == 0)
3718 return MCDisassembler::Fail;
3719 align = 16;
3720 } else {
3721 if (size == 2) {
3722 align *= 8;
3723 } else {
3724 size = 1 << size;
3725 align *= 4*size;
3726 }
3727 }
3728
3729 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
3730 return MCDisassembler::Fail;
3731 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: (Rd+inc)%32, Address, Decoder)))
3732 return MCDisassembler::Fail;
3733 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: (Rd+2*inc)%32, Address, Decoder)))
3734 return MCDisassembler::Fail;
3735 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: (Rd+3*inc)%32, Address, Decoder)))
3736 return MCDisassembler::Fail;
3737 if (Rm != 0xF) {
3738 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
3739 return MCDisassembler::Fail;
3740 }
3741
3742 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
3743 return MCDisassembler::Fail;
3744 Inst.addOperand(Op: MCOperand::createImm(Val: align));
3745
3746 if (Rm == 0xD)
3747 Inst.addOperand(Op: MCOperand::createReg(Reg: 0));
3748 else if (Rm != 0xF) {
3749 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
3750 return MCDisassembler::Fail;
3751 }
3752
3753 return S;
3754}
3755
3756static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn,
3757 uint64_t Address,
3758 const MCDisassembler *Decoder) {
3759 DecodeStatus S = MCDisassembler::Success;
3760
3761 unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
3762 Rd |= fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 4;
3763 unsigned imm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
3764 imm |= fieldFromInstruction(insn: Insn, startBit: 16, numBits: 3) << 4;
3765 imm |= fieldFromInstruction(insn: Insn, startBit: 24, numBits: 1) << 7;
3766 imm |= fieldFromInstruction(insn: Insn, startBit: 8, numBits: 4) << 8;
3767 imm |= fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1) << 12;
3768 unsigned Q = fieldFromInstruction(insn: Insn, startBit: 6, numBits: 1);
3769
3770 if (Q) {
3771 if (!Check(Out&: S, In: DecodeQPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
3772 return MCDisassembler::Fail;
3773 } else {
3774 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
3775 return MCDisassembler::Fail;
3776 }
3777
3778 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
3779
3780 switch (Inst.getOpcode()) {
3781 case ARM::VORRiv4i16:
3782 case ARM::VORRiv2i32:
3783 case ARM::VBICiv4i16:
3784 case ARM::VBICiv2i32:
3785 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
3786 return MCDisassembler::Fail;
3787 break;
3788 case ARM::VORRiv8i16:
3789 case ARM::VORRiv4i32:
3790 case ARM::VBICiv8i16:
3791 case ARM::VBICiv4i32:
3792 if (!Check(Out&: S, In: DecodeQPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
3793 return MCDisassembler::Fail;
3794 break;
3795 default:
3796 break;
3797 }
3798
3799 return S;
3800}
3801
3802static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn,
3803 uint64_t Address,
3804 const MCDisassembler *Decoder) {
3805 DecodeStatus S = MCDisassembler::Success;
3806
3807 unsigned Qd = ((fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 3) |
3808 fieldFromInstruction(insn: Insn, startBit: 13, numBits: 3));
3809 unsigned cmode = fieldFromInstruction(insn: Insn, startBit: 8, numBits: 4);
3810 unsigned imm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
3811 imm |= fieldFromInstruction(insn: Insn, startBit: 16, numBits: 3) << 4;
3812 imm |= fieldFromInstruction(insn: Insn, startBit: 28, numBits: 1) << 7;
3813 imm |= cmode << 8;
3814 imm |= fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1) << 12;
3815
3816 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32)
3817 return MCDisassembler::Fail;
3818
3819 if (!Check(Out&: S, In: DecodeMQPRRegisterClass(Inst, RegNo: Qd, Address, Decoder)))
3820 return MCDisassembler::Fail;
3821
3822 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
3823
3824 Inst.addOperand(Op: MCOperand::createImm(Val: ARMVCC::None));
3825 Inst.addOperand(Op: MCOperand::createReg(Reg: 0));
3826 Inst.addOperand(Op: MCOperand::createImm(Val: 0));
3827
3828 return S;
3829}
3830
3831static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
3832 uint64_t Address,
3833 const MCDisassembler *Decoder) {
3834 DecodeStatus S = MCDisassembler::Success;
3835
3836 unsigned Qd = fieldFromInstruction(insn: Insn, startBit: 13, numBits: 3);
3837 Qd |= fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 3;
3838 if (!Check(Out&: S, In: DecodeMQPRRegisterClass(Inst, RegNo: Qd, Address, Decoder)))
3839 return MCDisassembler::Fail;
3840 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::FPSCR_NZCV));
3841
3842 unsigned Qn = fieldFromInstruction(insn: Insn, startBit: 17, numBits: 3);
3843 Qn |= fieldFromInstruction(insn: Insn, startBit: 7, numBits: 1) << 3;
3844 if (!Check(Out&: S, In: DecodeMQPRRegisterClass(Inst, RegNo: Qn, Address, Decoder)))
3845 return MCDisassembler::Fail;
3846 unsigned Qm = fieldFromInstruction(insn: Insn, startBit: 1, numBits: 3);
3847 Qm |= fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1) << 3;
3848 if (!Check(Out&: S, In: DecodeMQPRRegisterClass(Inst, RegNo: Qm, Address, Decoder)))
3849 return MCDisassembler::Fail;
3850 if (!fieldFromInstruction(insn: Insn, startBit: 12, numBits: 1)) // I bit clear => need input FPSCR
3851 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::FPSCR_NZCV));
3852 Inst.addOperand(Op: MCOperand::createImm(Val: Qd));
3853
3854 return S;
3855}
3856
3857static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3858 uint64_t Address,
3859 const MCDisassembler *Decoder) {
3860 DecodeStatus S = MCDisassembler::Success;
3861
3862 unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
3863 Rd |= fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 4;
3864 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
3865 Rm |= fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1) << 4;
3866 unsigned size = fieldFromInstruction(insn: Insn, startBit: 18, numBits: 2);
3867
3868 if (!Check(Out&: S, In: DecodeQPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
3869 return MCDisassembler::Fail;
3870 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
3871 return MCDisassembler::Fail;
3872 Inst.addOperand(Op: MCOperand::createImm(Val: 8 << size));
3873
3874 return S;
3875}
3876
3877static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3878 uint64_t Address,
3879 const MCDisassembler *Decoder) {
3880 Inst.addOperand(Op: MCOperand::createImm(Val: 8 - Val));
3881 return MCDisassembler::Success;
3882}
3883
3884static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3885 uint64_t Address,
3886 const MCDisassembler *Decoder) {
3887 Inst.addOperand(Op: MCOperand::createImm(Val: 16 - Val));
3888 return MCDisassembler::Success;
3889}
3890
3891static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3892 uint64_t Address,
3893 const MCDisassembler *Decoder) {
3894 Inst.addOperand(Op: MCOperand::createImm(Val: 32 - Val));
3895 return MCDisassembler::Success;
3896}
3897
3898static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3899 uint64_t Address,
3900 const MCDisassembler *Decoder) {
3901 Inst.addOperand(Op: MCOperand::createImm(Val: 64 - Val));
3902 return MCDisassembler::Success;
3903}
3904
3905static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3906 uint64_t Address,
3907 const MCDisassembler *Decoder) {
3908 DecodeStatus S = MCDisassembler::Success;
3909
3910 unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
3911 Rd |= fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 4;
3912 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
3913 Rn |= fieldFromInstruction(insn: Insn, startBit: 7, numBits: 1) << 4;
3914 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
3915 Rm |= fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1) << 4;
3916 unsigned op = fieldFromInstruction(insn: Insn, startBit: 6, numBits: 1);
3917
3918 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
3919 return MCDisassembler::Fail;
3920 if (op) {
3921 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
3922 return MCDisassembler::Fail; // Writeback
3923 }
3924
3925 switch (Inst.getOpcode()) {
3926 case ARM::VTBL2:
3927 case ARM::VTBX2:
3928 if (!Check(Out&: S, In: DecodeDPairRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
3929 return MCDisassembler::Fail;
3930 break;
3931 default:
3932 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
3933 return MCDisassembler::Fail;
3934 }
3935
3936 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
3937 return MCDisassembler::Fail;
3938
3939 return S;
3940}
3941
3942static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3943 uint64_t Address,
3944 const MCDisassembler *Decoder) {
3945 DecodeStatus S = MCDisassembler::Success;
3946
3947 unsigned dst = fieldFromInstruction(insn: Insn, startBit: 8, numBits: 3);
3948 unsigned imm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 8);
3949
3950 if (!Check(Out&: S, In: DecodetGPRRegisterClass(Inst, RegNo: dst, Address, Decoder)))
3951 return MCDisassembler::Fail;
3952
3953 switch(Inst.getOpcode()) {
3954 default:
3955 return MCDisassembler::Fail;
3956 case ARM::tADR:
3957 break; // tADR does not explicitly represent the PC as an operand.
3958 case ARM::tADDrSPi:
3959 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::SP));
3960 break;
3961 }
3962
3963 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
3964 return S;
3965}
3966
3967static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3968 uint64_t Address,
3969 const MCDisassembler *Decoder) {
3970 if (!tryAddingSymbolicOperand(Address, Value: Address + SignExtend32<12>(X: Val<<1) + 4,
3971 isBranch: true, InstSize: 2, MI&: Inst, Decoder))
3972 Inst.addOperand(Op: MCOperand::createImm(Val: SignExtend32<12>(X: Val << 1)));
3973 return MCDisassembler::Success;
3974}
3975
3976static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3977 uint64_t Address,
3978 const MCDisassembler *Decoder) {
3979 if (!tryAddingSymbolicOperand(Address, Value: Address + SignExtend32<21>(X: Val) + 4,
3980 isBranch: true, InstSize: 4, MI&: Inst, Decoder))
3981 Inst.addOperand(Op: MCOperand::createImm(Val: SignExtend32<21>(X: Val)));
3982 return MCDisassembler::Success;
3983}
3984
3985static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3986 uint64_t Address,
3987 const MCDisassembler *Decoder) {
3988 if (!tryAddingSymbolicOperand(Address, Value: Address + (Val<<1) + 4,
3989 isBranch: true, InstSize: 2, MI&: Inst, Decoder))
3990 Inst.addOperand(Op: MCOperand::createImm(Val: Val << 1));
3991 return MCDisassembler::Success;
3992}
3993
3994static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3995 uint64_t Address,
3996 const MCDisassembler *Decoder) {
3997 DecodeStatus S = MCDisassembler::Success;
3998
3999 unsigned Rn = fieldFromInstruction(insn: Val, startBit: 0, numBits: 3);
4000 unsigned Rm = fieldFromInstruction(insn: Val, startBit: 3, numBits: 3);
4001
4002 if (!Check(Out&: S, In: DecodetGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
4003 return MCDisassembler::Fail;
4004 if (!Check(Out&: S, In: DecodetGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
4005 return MCDisassembler::Fail;
4006
4007 return S;
4008}
4009
4010static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
4011 uint64_t Address,
4012 const MCDisassembler *Decoder) {
4013 DecodeStatus S = MCDisassembler::Success;
4014
4015 unsigned Rn = fieldFromInstruction(insn: Val, startBit: 0, numBits: 3);
4016 unsigned imm = fieldFromInstruction(insn: Val, startBit: 3, numBits: 5);
4017
4018 if (!Check(Out&: S, In: DecodetGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
4019 return MCDisassembler::Fail;
4020 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
4021
4022 return S;
4023}
4024
4025static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
4026 uint64_t Address,
4027 const MCDisassembler *Decoder) {
4028 unsigned imm = Val << 2;
4029
4030 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
4031 tryAddingPcLoadReferenceComment(Address, Value: (Address & ~2u) + imm + 4, Decoder);
4032
4033 return MCDisassembler::Success;
4034}
4035
4036static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
4037 uint64_t Address,
4038 const MCDisassembler *Decoder) {
4039 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::SP));
4040 Inst.addOperand(Op: MCOperand::createImm(Val));
4041
4042 return MCDisassembler::Success;
4043}
4044
4045static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
4046 uint64_t Address,
4047 const MCDisassembler *Decoder) {
4048 DecodeStatus S = MCDisassembler::Success;
4049
4050 unsigned Rn = fieldFromInstruction(insn: Val, startBit: 6, numBits: 4);
4051 unsigned Rm = fieldFromInstruction(insn: Val, startBit: 2, numBits: 4);
4052 unsigned imm = fieldFromInstruction(insn: Val, startBit: 0, numBits: 2);
4053
4054 // Thumb stores cannot use PC as dest register.
4055 switch (Inst.getOpcode()) {
4056 case ARM::t2STRHs:
4057 case ARM::t2STRBs:
4058 case ARM::t2STRs:
4059 if (Rn == 15)
4060 return MCDisassembler::Fail;
4061 break;
4062 default:
4063 break;
4064 }
4065
4066 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
4067 return MCDisassembler::Fail;
4068 if (!Check(Out&: S, In: DecoderGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
4069 return MCDisassembler::Fail;
4070 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
4071
4072 return S;
4073}
4074
4075static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
4076 uint64_t Address,
4077 const MCDisassembler *Decoder) {
4078 DecodeStatus S = MCDisassembler::Success;
4079
4080 unsigned Rt = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
4081 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
4082
4083 const FeatureBitset &featureBits =
4084 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4085
4086 bool hasMP = featureBits[ARM::FeatureMP];
4087 bool hasV7Ops = featureBits[ARM::HasV7Ops];
4088
4089 if (Rn == 15) {
4090 switch (Inst.getOpcode()) {
4091 case ARM::t2LDRBs:
4092 Inst.setOpcode(ARM::t2LDRBpci);
4093 break;
4094 case ARM::t2LDRHs:
4095 Inst.setOpcode(ARM::t2LDRHpci);
4096 break;
4097 case ARM::t2LDRSHs:
4098 Inst.setOpcode(ARM::t2LDRSHpci);
4099 break;
4100 case ARM::t2LDRSBs:
4101 Inst.setOpcode(ARM::t2LDRSBpci);
4102 break;
4103 case ARM::t2LDRs:
4104 Inst.setOpcode(ARM::t2LDRpci);
4105 break;
4106 case ARM::t2PLDs:
4107 Inst.setOpcode(ARM::t2PLDpci);
4108 break;
4109 case ARM::t2PLIs:
4110 Inst.setOpcode(ARM::t2PLIpci);
4111 break;
4112 default:
4113 return MCDisassembler::Fail;
4114 }
4115
4116 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4117 }
4118
4119 if (Rt == 15) {
4120 switch (Inst.getOpcode()) {
4121 case ARM::t2LDRSHs:
4122 return MCDisassembler::Fail;
4123 case ARM::t2LDRHs:
4124 Inst.setOpcode(ARM::t2PLDWs);
4125 break;
4126 case ARM::t2LDRSBs:
4127 Inst.setOpcode(ARM::t2PLIs);
4128 break;
4129 default:
4130 break;
4131 }
4132 }
4133
4134 switch (Inst.getOpcode()) {
4135 case ARM::t2PLDs:
4136 break;
4137 case ARM::t2PLIs:
4138 if (!hasV7Ops)
4139 return MCDisassembler::Fail;
4140 break;
4141 case ARM::t2PLDWs:
4142 if (!hasV7Ops || !hasMP)
4143 return MCDisassembler::Fail;
4144 break;
4145 default:
4146 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rt, Address, Decoder)))
4147 return MCDisassembler::Fail;
4148 }
4149
4150 unsigned addrmode = fieldFromInstruction(insn: Insn, startBit: 4, numBits: 2);
4151 addrmode |= fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4) << 2;
4152 addrmode |= fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4) << 6;
4153 if (!Check(Out&: S, In: DecodeT2AddrModeSOReg(Inst, Val: addrmode, Address, Decoder)))
4154 return MCDisassembler::Fail;
4155
4156 return S;
4157}
4158
4159static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
4160 uint64_t Address,
4161 const MCDisassembler *Decoder) {
4162 DecodeStatus S = MCDisassembler::Success;
4163
4164 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
4165 unsigned Rt = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
4166 unsigned U = fieldFromInstruction(insn: Insn, startBit: 9, numBits: 1);
4167 unsigned imm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 8);
4168 imm |= (U << 8);
4169 imm |= (Rn << 9);
4170 unsigned add = fieldFromInstruction(insn: Insn, startBit: 9, numBits: 1);
4171
4172 const FeatureBitset &featureBits =
4173 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4174
4175 bool hasMP = featureBits[ARM::FeatureMP];
4176 bool hasV7Ops = featureBits[ARM::HasV7Ops];
4177
4178 if (Rn == 15) {
4179 switch (Inst.getOpcode()) {
4180 case ARM::t2LDRi8:
4181 Inst.setOpcode(ARM::t2LDRpci);
4182 break;
4183 case ARM::t2LDRBi8:
4184 Inst.setOpcode(ARM::t2LDRBpci);
4185 break;
4186 case ARM::t2LDRSBi8:
4187 Inst.setOpcode(ARM::t2LDRSBpci);
4188 break;
4189 case ARM::t2LDRHi8:
4190 Inst.setOpcode(ARM::t2LDRHpci);
4191 break;
4192 case ARM::t2LDRSHi8:
4193 Inst.setOpcode(ARM::t2LDRSHpci);
4194 break;
4195 case ARM::t2PLDi8:
4196 Inst.setOpcode(ARM::t2PLDpci);
4197 break;
4198 case ARM::t2PLIi8:
4199 Inst.setOpcode(ARM::t2PLIpci);
4200 break;
4201 default:
4202 return MCDisassembler::Fail;
4203 }
4204 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4205 }
4206
4207 if (Rt == 15) {
4208 switch (Inst.getOpcode()) {
4209 case ARM::t2LDRSHi8:
4210 return MCDisassembler::Fail;
4211 case ARM::t2LDRHi8:
4212 if (!add)
4213 Inst.setOpcode(ARM::t2PLDWi8);
4214 break;
4215 case ARM::t2LDRSBi8:
4216 Inst.setOpcode(ARM::t2PLIi8);
4217 break;
4218 default:
4219 break;
4220 }
4221 }
4222
4223 switch (Inst.getOpcode()) {
4224 case ARM::t2PLDi8:
4225 break;
4226 case ARM::t2PLIi8:
4227 if (!hasV7Ops)
4228 return MCDisassembler::Fail;
4229 break;
4230 case ARM::t2PLDWi8:
4231 if (!hasV7Ops || !hasMP)
4232 return MCDisassembler::Fail;
4233 break;
4234 default:
4235 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rt, Address, Decoder)))
4236 return MCDisassembler::Fail;
4237 }
4238
4239 if (!Check(Out&: S, In: DecodeT2AddrModeImm8(Inst, Val: imm, Address, Decoder)))
4240 return MCDisassembler::Fail;
4241 return S;
4242}
4243
4244static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
4245 uint64_t Address,
4246 const MCDisassembler *Decoder) {
4247 DecodeStatus S = MCDisassembler::Success;
4248
4249 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
4250 unsigned Rt = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
4251 unsigned imm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 12);
4252 imm |= (Rn << 13);
4253
4254 const FeatureBitset &featureBits =
4255 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4256
4257 bool hasMP = featureBits[ARM::FeatureMP];
4258 bool hasV7Ops = featureBits[ARM::HasV7Ops];
4259
4260 if (Rn == 15) {
4261 switch (Inst.getOpcode()) {
4262 case ARM::t2LDRi12:
4263 Inst.setOpcode(ARM::t2LDRpci);
4264 break;
4265 case ARM::t2LDRHi12:
4266 Inst.setOpcode(ARM::t2LDRHpci);
4267 break;
4268 case ARM::t2LDRSHi12:
4269 Inst.setOpcode(ARM::t2LDRSHpci);
4270 break;
4271 case ARM::t2LDRBi12:
4272 Inst.setOpcode(ARM::t2LDRBpci);
4273 break;
4274 case ARM::t2LDRSBi12:
4275 Inst.setOpcode(ARM::t2LDRSBpci);
4276 break;
4277 case ARM::t2PLDi12:
4278 Inst.setOpcode(ARM::t2PLDpci);
4279 break;
4280 case ARM::t2PLIi12:
4281 Inst.setOpcode(ARM::t2PLIpci);
4282 break;
4283 default:
4284 return MCDisassembler::Fail;
4285 }
4286 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4287 }
4288
4289 if (Rt == 15) {
4290 switch (Inst.getOpcode()) {
4291 case ARM::t2LDRSHi12:
4292 return MCDisassembler::Fail;
4293 case ARM::t2LDRHi12:
4294 Inst.setOpcode(ARM::t2PLDWi12);
4295 break;
4296 case ARM::t2LDRSBi12:
4297 Inst.setOpcode(ARM::t2PLIi12);
4298 break;
4299 default:
4300 break;
4301 }
4302 }
4303
4304 switch (Inst.getOpcode()) {
4305 case ARM::t2PLDi12:
4306 break;
4307 case ARM::t2PLIi12:
4308 if (!hasV7Ops)
4309 return MCDisassembler::Fail;
4310 break;
4311 case ARM::t2PLDWi12:
4312 if (!hasV7Ops || !hasMP)
4313 return MCDisassembler::Fail;
4314 break;
4315 default:
4316 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rt, Address, Decoder)))
4317 return MCDisassembler::Fail;
4318 }
4319
4320 if (!Check(Out&: S, In: DecodeT2AddrModeImm12(Inst, Val: imm, Address, Decoder)))
4321 return MCDisassembler::Fail;
4322 return S;
4323}
4324
4325static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address,
4326 const MCDisassembler *Decoder) {
4327 DecodeStatus S = MCDisassembler::Success;
4328
4329 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
4330 unsigned Rt = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
4331 unsigned imm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 8);
4332 imm |= (Rn << 9);
4333
4334 if (Rn == 15) {
4335 switch (Inst.getOpcode()) {
4336 case ARM::t2LDRT:
4337 Inst.setOpcode(ARM::t2LDRpci);
4338 break;
4339 case ARM::t2LDRBT:
4340 Inst.setOpcode(ARM::t2LDRBpci);
4341 break;
4342 case ARM::t2LDRHT:
4343 Inst.setOpcode(ARM::t2LDRHpci);
4344 break;
4345 case ARM::t2LDRSBT:
4346 Inst.setOpcode(ARM::t2LDRSBpci);
4347 break;
4348 case ARM::t2LDRSHT:
4349 Inst.setOpcode(ARM::t2LDRSHpci);
4350 break;
4351 default:
4352 return MCDisassembler::Fail;
4353 }
4354 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4355 }
4356
4357 if (!Check(Out&: S, In: DecoderGPRRegisterClass(Inst, RegNo: Rt, Address, Decoder)))
4358 return MCDisassembler::Fail;
4359 if (!Check(Out&: S, In: DecodeT2AddrModeImm8(Inst, Val: imm, Address, Decoder)))
4360 return MCDisassembler::Fail;
4361 return S;
4362}
4363
4364static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
4365 uint64_t Address,
4366 const MCDisassembler *Decoder) {
4367 DecodeStatus S = MCDisassembler::Success;
4368
4369 unsigned Rt = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
4370 unsigned U = fieldFromInstruction(insn: Insn, startBit: 23, numBits: 1);
4371 int imm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 12);
4372
4373 const FeatureBitset &featureBits =
4374 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4375
4376 bool hasV7Ops = featureBits[ARM::HasV7Ops];
4377
4378 if (Rt == 15) {
4379 switch (Inst.getOpcode()) {
4380 case ARM::t2LDRBpci:
4381 case ARM::t2LDRHpci:
4382 Inst.setOpcode(ARM::t2PLDpci);
4383 break;
4384 case ARM::t2LDRSBpci:
4385 Inst.setOpcode(ARM::t2PLIpci);
4386 break;
4387 case ARM::t2LDRSHpci:
4388 return MCDisassembler::Fail;
4389 default:
4390 break;
4391 }
4392 }
4393
4394 switch(Inst.getOpcode()) {
4395 case ARM::t2PLDpci:
4396 break;
4397 case ARM::t2PLIpci:
4398 if (!hasV7Ops)
4399 return MCDisassembler::Fail;
4400 break;
4401 default:
4402 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rt, Address, Decoder)))
4403 return MCDisassembler::Fail;
4404 }
4405
4406 if (!U) {
4407 // Special case for #-0.
4408 if (imm == 0)
4409 imm = INT32_MIN;
4410 else
4411 imm = -imm;
4412 }
4413 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
4414
4415 return S;
4416}
4417
4418static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address,
4419 const MCDisassembler *Decoder) {
4420 if (Val == 0)
4421 Inst.addOperand(Op: MCOperand::createImm(INT32_MIN));
4422 else {
4423 int imm = Val & 0xFF;
4424
4425 if (!(Val & 0x100)) imm *= -1;
4426 Inst.addOperand(Op: MCOperand::createImm(Val: imm * 4));
4427 }
4428
4429 return MCDisassembler::Success;
4430}
4431
4432static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
4433 const MCDisassembler *Decoder) {
4434 if (Val == 0)
4435 Inst.addOperand(Op: MCOperand::createImm(INT32_MIN));
4436 else {
4437 int imm = Val & 0x7F;
4438
4439 if (!(Val & 0x80))
4440 imm *= -1;
4441 Inst.addOperand(Op: MCOperand::createImm(Val: imm * 4));
4442 }
4443
4444 return MCDisassembler::Success;
4445}
4446
4447static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
4448 uint64_t Address,
4449 const MCDisassembler *Decoder) {
4450 DecodeStatus S = MCDisassembler::Success;
4451
4452 unsigned Rn = fieldFromInstruction(insn: Val, startBit: 9, numBits: 4);
4453 unsigned imm = fieldFromInstruction(insn: Val, startBit: 0, numBits: 9);
4454
4455 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
4456 return MCDisassembler::Fail;
4457 if (!Check(Out&: S, In: DecodeT2Imm8S4(Inst, Val: imm, Address, Decoder)))
4458 return MCDisassembler::Fail;
4459
4460 return S;
4461}
4462
4463static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
4464 uint64_t Address,
4465 const MCDisassembler *Decoder) {
4466 DecodeStatus S = MCDisassembler::Success;
4467
4468 unsigned Rn = fieldFromInstruction(insn: Val, startBit: 8, numBits: 4);
4469 unsigned imm = fieldFromInstruction(insn: Val, startBit: 0, numBits: 8);
4470
4471 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
4472 return MCDisassembler::Fail;
4473 if (!Check(Out&: S, In: DecodeT2Imm7S4(Inst, Val: imm, Address, Decoder)))
4474 return MCDisassembler::Fail;
4475
4476 return S;
4477}
4478
4479static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val,
4480 uint64_t Address,
4481 const MCDisassembler *Decoder) {
4482 DecodeStatus S = MCDisassembler::Success;
4483
4484 unsigned Rn = fieldFromInstruction(insn: Val, startBit: 8, numBits: 4);
4485 unsigned imm = fieldFromInstruction(insn: Val, startBit: 0, numBits: 8);
4486
4487 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
4488 return MCDisassembler::Fail;
4489
4490 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
4491
4492 return S;
4493}
4494
4495static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address,
4496 const MCDisassembler *Decoder) {
4497 int imm = Val & 0xFF;
4498 if (Val == 0)
4499 imm = INT32_MIN;
4500 else if (!(Val & 0x100))
4501 imm *= -1;
4502 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
4503
4504 return MCDisassembler::Success;
4505}
4506
4507template <int shift>
4508static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address,
4509 const MCDisassembler *Decoder) {
4510 int imm = Val & 0x7F;
4511 if (Val == 0)
4512 imm = INT32_MIN;
4513 else if (!(Val & 0x80))
4514 imm *= -1;
4515 if (imm != INT32_MIN)
4516 imm *= (1U << shift);
4517 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
4518
4519 return MCDisassembler::Success;
4520}
4521
4522static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
4523 uint64_t Address,
4524 const MCDisassembler *Decoder) {
4525 DecodeStatus S = MCDisassembler::Success;
4526
4527 unsigned Rn = fieldFromInstruction(insn: Val, startBit: 9, numBits: 4);
4528 unsigned imm = fieldFromInstruction(insn: Val, startBit: 0, numBits: 9);
4529
4530 // Thumb stores cannot use PC as dest register.
4531 switch (Inst.getOpcode()) {
4532 case ARM::t2STRT:
4533 case ARM::t2STRBT:
4534 case ARM::t2STRHT:
4535 case ARM::t2STRi8:
4536 case ARM::t2STRHi8:
4537 case ARM::t2STRBi8:
4538 if (Rn == 15)
4539 return MCDisassembler::Fail;
4540 break;
4541 default:
4542 break;
4543 }
4544
4545 // Some instructions always use an additive offset.
4546 switch (Inst.getOpcode()) {
4547 case ARM::t2LDRT:
4548 case ARM::t2LDRBT:
4549 case ARM::t2LDRHT:
4550 case ARM::t2LDRSBT:
4551 case ARM::t2LDRSHT:
4552 case ARM::t2STRT:
4553 case ARM::t2STRBT:
4554 case ARM::t2STRHT:
4555 imm |= 0x100;
4556 break;
4557 default:
4558 break;
4559 }
4560
4561 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
4562 return MCDisassembler::Fail;
4563 if (!Check(Out&: S, In: DecodeT2Imm8(Inst, Val: imm, Address, Decoder)))
4564 return MCDisassembler::Fail;
4565
4566 return S;
4567}
4568
4569template <int shift>
4570static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
4571 uint64_t Address,
4572 const MCDisassembler *Decoder) {
4573 DecodeStatus S = MCDisassembler::Success;
4574
4575 unsigned Rn = fieldFromInstruction(insn: Val, startBit: 8, numBits: 3);
4576 unsigned imm = fieldFromInstruction(insn: Val, startBit: 0, numBits: 8);
4577
4578 if (!Check(Out&: S, In: DecodetGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
4579 return MCDisassembler::Fail;
4580 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4581 return MCDisassembler::Fail;
4582
4583 return S;
4584}
4585
4586template <int shift, int WriteBack>
4587static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
4588 uint64_t Address,
4589 const MCDisassembler *Decoder) {
4590 DecodeStatus S = MCDisassembler::Success;
4591
4592 unsigned Rn = fieldFromInstruction(insn: Val, startBit: 8, numBits: 4);
4593 unsigned imm = fieldFromInstruction(insn: Val, startBit: 0, numBits: 8);
4594 if (WriteBack) {
4595 if (!Check(Out&: S, In: DecoderGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
4596 return MCDisassembler::Fail;
4597 } else if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
4598 return MCDisassembler::Fail;
4599 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4600 return MCDisassembler::Fail;
4601
4602 return S;
4603}
4604
4605static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
4606 uint64_t Address,
4607 const MCDisassembler *Decoder) {
4608 DecodeStatus S = MCDisassembler::Success;
4609
4610 unsigned Rt = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
4611 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
4612 unsigned addr = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 8);
4613 addr |= fieldFromInstruction(insn: Insn, startBit: 9, numBits: 1) << 8;
4614 addr |= Rn << 9;
4615 unsigned load = fieldFromInstruction(insn: Insn, startBit: 20, numBits: 1);
4616
4617 if (Rn == 15) {
4618 switch (Inst.getOpcode()) {
4619 case ARM::t2LDR_PRE:
4620 case ARM::t2LDR_POST:
4621 Inst.setOpcode(ARM::t2LDRpci);
4622 break;
4623 case ARM::t2LDRB_PRE:
4624 case ARM::t2LDRB_POST:
4625 Inst.setOpcode(ARM::t2LDRBpci);
4626 break;
4627 case ARM::t2LDRH_PRE:
4628 case ARM::t2LDRH_POST:
4629 Inst.setOpcode(ARM::t2LDRHpci);
4630 break;
4631 case ARM::t2LDRSB_PRE:
4632 case ARM::t2LDRSB_POST:
4633 if (Rt == 15)
4634 Inst.setOpcode(ARM::t2PLIpci);
4635 else
4636 Inst.setOpcode(ARM::t2LDRSBpci);
4637 break;
4638 case ARM::t2LDRSH_PRE:
4639 case ARM::t2LDRSH_POST:
4640 Inst.setOpcode(ARM::t2LDRSHpci);
4641 break;
4642 default:
4643 return MCDisassembler::Fail;
4644 }
4645 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4646 }
4647
4648 if (!load) {
4649 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
4650 return MCDisassembler::Fail;
4651 }
4652
4653 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rt, Address, Decoder)))
4654 return MCDisassembler::Fail;
4655
4656 if (load) {
4657 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
4658 return MCDisassembler::Fail;
4659 }
4660
4661 if (!Check(Out&: S, In: DecodeT2AddrModeImm8(Inst, Val: addr, Address, Decoder)))
4662 return MCDisassembler::Fail;
4663
4664 return S;
4665}
4666
4667static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
4668 uint64_t Address,
4669 const MCDisassembler *Decoder) {
4670 DecodeStatus S = MCDisassembler::Success;
4671
4672 unsigned Rn = fieldFromInstruction(insn: Val, startBit: 13, numBits: 4);
4673 unsigned imm = fieldFromInstruction(insn: Val, startBit: 0, numBits: 12);
4674
4675 // Thumb stores cannot use PC as dest register.
4676 switch (Inst.getOpcode()) {
4677 case ARM::t2STRi12:
4678 case ARM::t2STRBi12:
4679 case ARM::t2STRHi12:
4680 if (Rn == 15)
4681 return MCDisassembler::Fail;
4682 break;
4683 default:
4684 break;
4685 }
4686
4687 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
4688 return MCDisassembler::Fail;
4689 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
4690
4691 return S;
4692}
4693
4694static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
4695 uint64_t Address,
4696 const MCDisassembler *Decoder) {
4697 unsigned imm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 7);
4698
4699 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::SP));
4700 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::SP));
4701 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
4702
4703 return MCDisassembler::Success;
4704}
4705
4706static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
4707 uint64_t Address,
4708 const MCDisassembler *Decoder) {
4709 DecodeStatus S = MCDisassembler::Success;
4710
4711 if (Inst.getOpcode() == ARM::tADDrSP) {
4712 unsigned Rdm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 3);
4713 Rdm |= fieldFromInstruction(insn: Insn, startBit: 7, numBits: 1) << 3;
4714
4715 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rdm, Address, Decoder)))
4716 return MCDisassembler::Fail;
4717 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::SP));
4718 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rdm, Address, Decoder)))
4719 return MCDisassembler::Fail;
4720 } else if (Inst.getOpcode() == ARM::tADDspr) {
4721 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 3, numBits: 4);
4722
4723 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::SP));
4724 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::SP));
4725 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
4726 return MCDisassembler::Fail;
4727 }
4728
4729 return S;
4730}
4731
4732static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
4733 uint64_t Address,
4734 const MCDisassembler *Decoder) {
4735 unsigned imod = fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1) | 0x2;
4736 unsigned flags = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 3);
4737
4738 Inst.addOperand(Op: MCOperand::createImm(Val: imod));
4739 Inst.addOperand(Op: MCOperand::createImm(Val: flags));
4740
4741 return MCDisassembler::Success;
4742}
4743
4744static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
4745 uint64_t Address,
4746 const MCDisassembler *Decoder) {
4747 DecodeStatus S = MCDisassembler::Success;
4748 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
4749 unsigned add = fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1);
4750
4751 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
4752 return MCDisassembler::Fail;
4753 Inst.addOperand(Op: MCOperand::createImm(Val: add));
4754
4755 return S;
4756}
4757
4758static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
4759 uint64_t Address,
4760 const MCDisassembler *Decoder) {
4761 DecodeStatus S = MCDisassembler::Success;
4762 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 3, numBits: 4);
4763 unsigned Qm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 3);
4764
4765 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
4766 return MCDisassembler::Fail;
4767 if (!Check(Out&: S, In: DecodeMQPRRegisterClass(Inst, RegNo: Qm, Address, Decoder)))
4768 return MCDisassembler::Fail;
4769
4770 return S;
4771}
4772
4773template <int shift>
4774static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
4775 uint64_t Address,
4776 const MCDisassembler *Decoder) {
4777 DecodeStatus S = MCDisassembler::Success;
4778 unsigned Qm = fieldFromInstruction(insn: Insn, startBit: 8, numBits: 3);
4779 int imm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 7);
4780
4781 if (!Check(Out&: S, In: DecodeMQPRRegisterClass(Inst, RegNo: Qm, Address, Decoder)))
4782 return MCDisassembler::Fail;
4783
4784 if(!fieldFromInstruction(insn: Insn, startBit: 7, numBits: 1)) {
4785 if (imm == 0)
4786 imm = INT32_MIN; // indicate -0
4787 else
4788 imm *= -1;
4789 }
4790 if (imm != INT32_MIN)
4791 imm *= (1U << shift);
4792 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
4793
4794 return S;
4795}
4796
4797static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
4798 uint64_t Address,
4799 const MCDisassembler *Decoder) {
4800 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
4801 // Note only one trailing zero not two. Also the J1 and J2 values are from
4802 // the encoded instruction. So here change to I1 and I2 values via:
4803 // I1 = NOT(J1 EOR S);
4804 // I2 = NOT(J2 EOR S);
4805 // and build the imm32 with two trailing zeros as documented:
4806 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
4807 unsigned S = (Val >> 23) & 1;
4808 unsigned J1 = (Val >> 22) & 1;
4809 unsigned J2 = (Val >> 21) & 1;
4810 unsigned I1 = !(J1 ^ S);
4811 unsigned I2 = !(J2 ^ S);
4812 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4813 int imm32 = SignExtend32<25>(X: tmp << 1);
4814
4815 if (!tryAddingSymbolicOperand(Address,
4816 Value: (Address & ~2u) + imm32 + 4,
4817 isBranch: true, InstSize: 4, MI&: Inst, Decoder))
4818 Inst.addOperand(Op: MCOperand::createImm(Val: imm32));
4819 return MCDisassembler::Success;
4820}
4821
4822static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
4823 uint64_t Address,
4824 const MCDisassembler *Decoder) {
4825 if (Val == 0xA || Val == 0xB)
4826 return MCDisassembler::Fail;
4827
4828 const FeatureBitset &featureBits =
4829 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4830
4831 if (!isValidCoprocessorNumber(Num: Val, featureBits))
4832 return MCDisassembler::Fail;
4833
4834 Inst.addOperand(Op: MCOperand::createImm(Val));
4835 return MCDisassembler::Success;
4836}
4837
4838static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
4839 uint64_t Address,
4840 const MCDisassembler *Decoder) {
4841 const FeatureBitset &FeatureBits =
4842 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4843 DecodeStatus S = MCDisassembler::Success;
4844
4845 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
4846 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
4847
4848 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail;
4849 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
4850 return MCDisassembler::Fail;
4851 if (!Check(Out&: S, In: DecoderGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
4852 return MCDisassembler::Fail;
4853 return S;
4854}
4855
4856static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
4857 uint64_t Address,
4858 const MCDisassembler *Decoder) {
4859 DecodeStatus S = MCDisassembler::Success;
4860
4861 unsigned pred = fieldFromInstruction(insn: Insn, startBit: 22, numBits: 4);
4862 if (pred == 0xE || pred == 0xF) {
4863 unsigned opc = fieldFromInstruction(insn: Insn, startBit: 4, numBits: 28);
4864 switch (opc) {
4865 default:
4866 return MCDisassembler::Fail;
4867 case 0xf3bf8f4:
4868 Inst.setOpcode(ARM::t2DSB);
4869 break;
4870 case 0xf3bf8f5:
4871 Inst.setOpcode(ARM::t2DMB);
4872 break;
4873 case 0xf3bf8f6:
4874 Inst.setOpcode(ARM::t2ISB);
4875 break;
4876 }
4877
4878 unsigned imm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
4879 return DecodeMemBarrierOption(Inst, Insn: imm, Address, Decoder);
4880 }
4881
4882 unsigned brtarget = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 11) << 1;
4883 brtarget |= fieldFromInstruction(insn: Insn, startBit: 11, numBits: 1) << 19;
4884 brtarget |= fieldFromInstruction(insn: Insn, startBit: 13, numBits: 1) << 18;
4885 brtarget |= fieldFromInstruction(insn: Insn, startBit: 16, numBits: 6) << 12;
4886 brtarget |= fieldFromInstruction(insn: Insn, startBit: 26, numBits: 1) << 20;
4887
4888 if (!Check(Out&: S, In: DecodeT2BROperand(Inst, Val: brtarget, Address, Decoder)))
4889 return MCDisassembler::Fail;
4890 if (!Check(Out&: S, In: DecodePredicateOperand(Inst, Val: pred, Address, Decoder)))
4891 return MCDisassembler::Fail;
4892
4893 return S;
4894}
4895
4896// Decode a shifted immediate operand. These basically consist
4897// of an 8-bit value, and a 4-bit directive that specifies either
4898// a splat operation or a rotation.
4899static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address,
4900 const MCDisassembler *Decoder) {
4901 unsigned ctrl = fieldFromInstruction(insn: Val, startBit: 10, numBits: 2);
4902 if (ctrl == 0) {
4903 unsigned byte = fieldFromInstruction(insn: Val, startBit: 8, numBits: 2);
4904 unsigned imm = fieldFromInstruction(insn: Val, startBit: 0, numBits: 8);
4905 switch (byte) {
4906 case 0:
4907 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
4908 break;
4909 case 1:
4910 Inst.addOperand(Op: MCOperand::createImm(Val: (imm << 16) | imm));
4911 break;
4912 case 2:
4913 Inst.addOperand(Op: MCOperand::createImm(Val: (imm << 24) | (imm << 8)));
4914 break;
4915 case 3:
4916 Inst.addOperand(Op: MCOperand::createImm(Val: (imm << 24) | (imm << 16) |
4917 (imm << 8) | imm));
4918 break;
4919 }
4920 } else {
4921 unsigned unrot = fieldFromInstruction(insn: Val, startBit: 0, numBits: 7) | 0x80;
4922 unsigned rot = fieldFromInstruction(insn: Val, startBit: 7, numBits: 5);
4923 unsigned imm = llvm::rotr<uint32_t>(V: unrot, R: rot);
4924 Inst.addOperand(Op: MCOperand::createImm(Val: imm));
4925 }
4926
4927 return MCDisassembler::Success;
4928}
4929
4930static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
4931 uint64_t Address,
4932 const MCDisassembler *Decoder) {
4933 if (!tryAddingSymbolicOperand(Address, Value: Address + SignExtend32<9>(X: Val<<1) + 4,
4934 isBranch: true, InstSize: 2, MI&: Inst, Decoder))
4935 Inst.addOperand(Op: MCOperand::createImm(Val: SignExtend32<9>(X: Val << 1)));
4936 return MCDisassembler::Success;
4937}
4938
4939static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
4940 uint64_t Address,
4941 const MCDisassembler *Decoder) {
4942 // Val is passed in as S:J1:J2:imm10:imm11
4943 // Note no trailing zero after imm11. Also the J1 and J2 values are from
4944 // the encoded instruction. So here change to I1 and I2 values via:
4945 // I1 = NOT(J1 EOR S);
4946 // I2 = NOT(J2 EOR S);
4947 // and build the imm32 with one trailing zero as documented:
4948 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
4949 unsigned S = (Val >> 23) & 1;
4950 unsigned J1 = (Val >> 22) & 1;
4951 unsigned J2 = (Val >> 21) & 1;
4952 unsigned I1 = !(J1 ^ S);
4953 unsigned I2 = !(J2 ^ S);
4954 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4955 int imm32 = SignExtend32<25>(X: tmp << 1);
4956
4957 if (!tryAddingSymbolicOperand(Address, Value: Address + imm32 + 4,
4958 isBranch: true, InstSize: 4, MI&: Inst, Decoder))
4959 Inst.addOperand(Op: MCOperand::createImm(Val: imm32));
4960 return MCDisassembler::Success;
4961}
4962
4963static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4964 uint64_t Address,
4965 const MCDisassembler *Decoder) {
4966 if (Val & ~0xf)
4967 return MCDisassembler::Fail;
4968
4969 Inst.addOperand(Op: MCOperand::createImm(Val));
4970 return MCDisassembler::Success;
4971}
4972
4973static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
4974 uint64_t Address,
4975 const MCDisassembler *Decoder) {
4976 if (Val & ~0xf)
4977 return MCDisassembler::Fail;
4978
4979 Inst.addOperand(Op: MCOperand::createImm(Val));
4980 return MCDisassembler::Success;
4981}
4982
4983static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address,
4984 const MCDisassembler *Decoder) {
4985 DecodeStatus S = MCDisassembler::Success;
4986 const FeatureBitset &FeatureBits =
4987 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4988
4989 if (FeatureBits[ARM::FeatureMClass]) {
4990 unsigned ValLow = Val & 0xff;
4991
4992 // Validate the SYSm value first.
4993 switch (ValLow) {
4994 case 0: // apsr
4995 case 1: // iapsr
4996 case 2: // eapsr
4997 case 3: // xpsr
4998 case 5: // ipsr
4999 case 6: // epsr
5000 case 7: // iepsr
5001 case 8: // msp
5002 case 9: // psp
5003 case 16: // primask
5004 case 20: // control
5005 break;
5006 case 17: // basepri
5007 case 18: // basepri_max
5008 case 19: // faultmask
5009 if (!(FeatureBits[ARM::HasV7Ops]))
5010 // Values basepri, basepri_max and faultmask are only valid for v7m.
5011 return MCDisassembler::Fail;
5012 break;
5013 case 0x8a: // msplim_ns
5014 case 0x8b: // psplim_ns
5015 case 0x91: // basepri_ns
5016 case 0x93: // faultmask_ns
5017 if (!(FeatureBits[ARM::HasV8MMainlineOps]))
5018 return MCDisassembler::Fail;
5019 [[fallthrough]];
5020 case 10: // msplim
5021 case 11: // psplim
5022 case 0x88: // msp_ns
5023 case 0x89: // psp_ns
5024 case 0x90: // primask_ns
5025 case 0x94: // control_ns
5026 case 0x98: // sp_ns
5027 if (!(FeatureBits[ARM::Feature8MSecExt]))
5028 return MCDisassembler::Fail;
5029 break;
5030 case 0x20: // pac_key_p_0
5031 case 0x21: // pac_key_p_1
5032 case 0x22: // pac_key_p_2
5033 case 0x23: // pac_key_p_3
5034 case 0x24: // pac_key_u_0
5035 case 0x25: // pac_key_u_1
5036 case 0x26: // pac_key_u_2
5037 case 0x27: // pac_key_u_3
5038 case 0xa0: // pac_key_p_0_ns
5039 case 0xa1: // pac_key_p_1_ns
5040 case 0xa2: // pac_key_p_2_ns
5041 case 0xa3: // pac_key_p_3_ns
5042 case 0xa4: // pac_key_u_0_ns
5043 case 0xa5: // pac_key_u_1_ns
5044 case 0xa6: // pac_key_u_2_ns
5045 case 0xa7: // pac_key_u_3_ns
5046 if (!(FeatureBits[ARM::FeaturePACBTI]))
5047 return MCDisassembler::Fail;
5048 break;
5049 default:
5050 // Architecturally defined as unpredictable
5051 S = MCDisassembler::SoftFail;
5052 break;
5053 }
5054
5055 if (Inst.getOpcode() == ARM::t2MSR_M) {
5056 unsigned Mask = fieldFromInstruction(insn: Val, startBit: 10, numBits: 2);
5057 if (!(FeatureBits[ARM::HasV7Ops])) {
5058 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
5059 // unpredictable.
5060 if (Mask != 2)
5061 S = MCDisassembler::SoftFail;
5062 }
5063 else {
5064 // The ARMv7-M architecture stores an additional 2-bit mask value in
5065 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
5066 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
5067 // the NZCVQ bits should be moved by the instruction. Bit mask{0}
5068 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
5069 // only if the processor includes the DSP extension.
5070 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
5071 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
5072 S = MCDisassembler::SoftFail;
5073 }
5074 }
5075 } else {
5076 // A/R class
5077 if (Val == 0)
5078 return MCDisassembler::Fail;
5079 }
5080 Inst.addOperand(Op: MCOperand::createImm(Val));
5081 return S;
5082}
5083
5084static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
5085 uint64_t Address,
5086 const MCDisassembler *Decoder) {
5087 unsigned R = fieldFromInstruction(insn: Val, startBit: 5, numBits: 1);
5088 unsigned SysM = fieldFromInstruction(insn: Val, startBit: 0, numBits: 5);
5089
5090 // The table of encodings for these banked registers comes from B9.2.3 of the
5091 // ARM ARM. There are patterns, but nothing regular enough to make this logic
5092 // neater. So by fiat, these values are UNPREDICTABLE:
5093 if (!ARMBankedReg::lookupBankedRegByEncoding(Encoding: (R << 5) | SysM))
5094 return MCDisassembler::Fail;
5095
5096 Inst.addOperand(Op: MCOperand::createImm(Val));
5097 return MCDisassembler::Success;
5098}
5099
5100static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
5101 uint64_t Address,
5102 const MCDisassembler *Decoder) {
5103 DecodeStatus S = MCDisassembler::Success;
5104
5105 unsigned Rt = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
5106 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
5107 unsigned pred = fieldFromInstruction(insn: Insn, startBit: 28, numBits: 4);
5108
5109 if (Rn == 0xF)
5110 S = MCDisassembler::SoftFail;
5111
5112 if (!Check(Out&: S, In: DecodeGPRPairRegisterClass(Inst, RegNo: Rt, Address, Decoder)))
5113 return MCDisassembler::Fail;
5114 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5115 return MCDisassembler::Fail;
5116 if (!Check(Out&: S, In: DecodePredicateOperand(Inst, Val: pred, Address, Decoder)))
5117 return MCDisassembler::Fail;
5118
5119 return S;
5120}
5121
5122static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
5123 uint64_t Address,
5124 const MCDisassembler *Decoder) {
5125 DecodeStatus S = MCDisassembler::Success;
5126
5127 unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
5128 unsigned Rt = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
5129 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
5130 unsigned pred = fieldFromInstruction(insn: Insn, startBit: 28, numBits: 4);
5131
5132 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
5133 return MCDisassembler::Fail;
5134
5135 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
5136 S = MCDisassembler::SoftFail;
5137
5138 if (!Check(Out&: S, In: DecodeGPRPairRegisterClass(Inst, RegNo: Rt, Address, Decoder)))
5139 return MCDisassembler::Fail;
5140 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5141 return MCDisassembler::Fail;
5142 if (!Check(Out&: S, In: DecodePredicateOperand(Inst, Val: pred, Address, Decoder)))
5143 return MCDisassembler::Fail;
5144
5145 return S;
5146}
5147
5148static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
5149 uint64_t Address,
5150 const MCDisassembler *Decoder) {
5151 DecodeStatus S = MCDisassembler::Success;
5152
5153 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
5154 unsigned Rt = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
5155 unsigned imm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 12);
5156 imm |= fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4) << 13;
5157 imm |= fieldFromInstruction(insn: Insn, startBit: 23, numBits: 1) << 12;
5158 unsigned pred = fieldFromInstruction(insn: Insn, startBit: 28, numBits: 4);
5159
5160 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
5161
5162 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rt, Address, Decoder)))
5163 return MCDisassembler::Fail;
5164 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5165 return MCDisassembler::Fail;
5166 if (!Check(Out&: S, In: DecodeAddrModeImm12Operand(Inst, Val: imm, Address, Decoder)))
5167 return MCDisassembler::Fail;
5168 if (!Check(Out&: S, In: DecodePredicateOperand(Inst, Val: pred, Address, Decoder)))
5169 return MCDisassembler::Fail;
5170
5171 return S;
5172}
5173
5174static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
5175 uint64_t Address,
5176 const MCDisassembler *Decoder) {
5177 DecodeStatus S = MCDisassembler::Success;
5178
5179 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
5180 unsigned Rt = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
5181 unsigned imm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 12);
5182 imm |= fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4) << 13;
5183 imm |= fieldFromInstruction(insn: Insn, startBit: 23, numBits: 1) << 12;
5184 unsigned pred = fieldFromInstruction(insn: Insn, startBit: 28, numBits: 4);
5185 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
5186
5187 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
5188 if (Rm == 0xF) S = MCDisassembler::SoftFail;
5189
5190 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rt, Address, Decoder)))
5191 return MCDisassembler::Fail;
5192 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5193 return MCDisassembler::Fail;
5194 if (!Check(Out&: S, In: DecodeSORegMemOperand(Inst, Val: imm, Address, Decoder)))
5195 return MCDisassembler::Fail;
5196 if (!Check(Out&: S, In: DecodePredicateOperand(Inst, Val: pred, Address, Decoder)))
5197 return MCDisassembler::Fail;
5198
5199 return S;
5200}
5201
5202static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
5203 uint64_t Address,
5204 const MCDisassembler *Decoder) {
5205 DecodeStatus S = MCDisassembler::Success;
5206
5207 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
5208 unsigned Rt = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
5209 unsigned imm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 12);
5210 imm |= fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4) << 13;
5211 imm |= fieldFromInstruction(insn: Insn, startBit: 23, numBits: 1) << 12;
5212 unsigned pred = fieldFromInstruction(insn: Insn, startBit: 28, numBits: 4);
5213
5214 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
5215
5216 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5217 return MCDisassembler::Fail;
5218 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rt, Address, Decoder)))
5219 return MCDisassembler::Fail;
5220 if (!Check(Out&: S, In: DecodeAddrModeImm12Operand(Inst, Val: imm, Address, Decoder)))
5221 return MCDisassembler::Fail;
5222 if (!Check(Out&: S, In: DecodePredicateOperand(Inst, Val: pred, Address, Decoder)))
5223 return MCDisassembler::Fail;
5224
5225 return S;
5226}
5227
5228static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
5229 uint64_t Address,
5230 const MCDisassembler *Decoder) {
5231 DecodeStatus S = MCDisassembler::Success;
5232
5233 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
5234 unsigned Rt = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
5235 unsigned imm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 12);
5236 imm |= fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4) << 13;
5237 imm |= fieldFromInstruction(insn: Insn, startBit: 23, numBits: 1) << 12;
5238 unsigned pred = fieldFromInstruction(insn: Insn, startBit: 28, numBits: 4);
5239
5240 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
5241
5242 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5243 return MCDisassembler::Fail;
5244 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rt, Address, Decoder)))
5245 return MCDisassembler::Fail;
5246 if (!Check(Out&: S, In: DecodeSORegMemOperand(Inst, Val: imm, Address, Decoder)))
5247 return MCDisassembler::Fail;
5248 if (!Check(Out&: S, In: DecodePredicateOperand(Inst, Val: pred, Address, Decoder)))
5249 return MCDisassembler::Fail;
5250
5251 return S;
5252}
5253
5254static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5255 const MCDisassembler *Decoder) {
5256 DecodeStatus S = MCDisassembler::Success;
5257
5258 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
5259 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
5260 unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
5261 Rd |= fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 4;
5262 unsigned size = fieldFromInstruction(insn: Insn, startBit: 10, numBits: 2);
5263
5264 unsigned align = 0;
5265 unsigned index = 0;
5266 switch (size) {
5267 default:
5268 return MCDisassembler::Fail;
5269 case 0:
5270 if (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1))
5271 return MCDisassembler::Fail; // UNDEFINED
5272 index = fieldFromInstruction(insn: Insn, startBit: 5, numBits: 3);
5273 break;
5274 case 1:
5275 if (fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1))
5276 return MCDisassembler::Fail; // UNDEFINED
5277 index = fieldFromInstruction(insn: Insn, startBit: 6, numBits: 2);
5278 if (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1))
5279 align = 2;
5280 break;
5281 case 2:
5282 if (fieldFromInstruction(insn: Insn, startBit: 6, numBits: 1))
5283 return MCDisassembler::Fail; // UNDEFINED
5284 index = fieldFromInstruction(insn: Insn, startBit: 7, numBits: 1);
5285
5286 switch (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 2)) {
5287 case 0 :
5288 align = 0; break;
5289 case 3:
5290 align = 4; break;
5291 default:
5292 return MCDisassembler::Fail;
5293 }
5294 break;
5295 }
5296
5297 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
5298 return MCDisassembler::Fail;
5299 if (Rm != 0xF) { // Writeback
5300 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5301 return MCDisassembler::Fail;
5302 }
5303 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5304 return MCDisassembler::Fail;
5305 Inst.addOperand(Op: MCOperand::createImm(Val: align));
5306 if (Rm != 0xF) {
5307 if (Rm != 0xD) {
5308 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
5309 return MCDisassembler::Fail;
5310 } else
5311 Inst.addOperand(Op: MCOperand::createReg(Reg: 0));
5312 }
5313
5314 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
5315 return MCDisassembler::Fail;
5316 Inst.addOperand(Op: MCOperand::createImm(Val: index));
5317
5318 return S;
5319}
5320
5321static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5322 const MCDisassembler *Decoder) {
5323 DecodeStatus S = MCDisassembler::Success;
5324
5325 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
5326 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
5327 unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
5328 Rd |= fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 4;
5329 unsigned size = fieldFromInstruction(insn: Insn, startBit: 10, numBits: 2);
5330
5331 unsigned align = 0;
5332 unsigned index = 0;
5333 switch (size) {
5334 default:
5335 return MCDisassembler::Fail;
5336 case 0:
5337 if (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1))
5338 return MCDisassembler::Fail; // UNDEFINED
5339 index = fieldFromInstruction(insn: Insn, startBit: 5, numBits: 3);
5340 break;
5341 case 1:
5342 if (fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1))
5343 return MCDisassembler::Fail; // UNDEFINED
5344 index = fieldFromInstruction(insn: Insn, startBit: 6, numBits: 2);
5345 if (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1))
5346 align = 2;
5347 break;
5348 case 2:
5349 if (fieldFromInstruction(insn: Insn, startBit: 6, numBits: 1))
5350 return MCDisassembler::Fail; // UNDEFINED
5351 index = fieldFromInstruction(insn: Insn, startBit: 7, numBits: 1);
5352
5353 switch (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 2)) {
5354 case 0:
5355 align = 0; break;
5356 case 3:
5357 align = 4; break;
5358 default:
5359 return MCDisassembler::Fail;
5360 }
5361 break;
5362 }
5363
5364 if (Rm != 0xF) { // Writeback
5365 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5366 return MCDisassembler::Fail;
5367 }
5368 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5369 return MCDisassembler::Fail;
5370 Inst.addOperand(Op: MCOperand::createImm(Val: align));
5371 if (Rm != 0xF) {
5372 if (Rm != 0xD) {
5373 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
5374 return MCDisassembler::Fail;
5375 } else
5376 Inst.addOperand(Op: MCOperand::createReg(Reg: 0));
5377 }
5378
5379 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
5380 return MCDisassembler::Fail;
5381 Inst.addOperand(Op: MCOperand::createImm(Val: index));
5382
5383 return S;
5384}
5385
5386static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5387 const MCDisassembler *Decoder) {
5388 DecodeStatus S = MCDisassembler::Success;
5389
5390 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
5391 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
5392 unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
5393 Rd |= fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 4;
5394 unsigned size = fieldFromInstruction(insn: Insn, startBit: 10, numBits: 2);
5395
5396 unsigned align = 0;
5397 unsigned index = 0;
5398 unsigned inc = 1;
5399 switch (size) {
5400 default:
5401 return MCDisassembler::Fail;
5402 case 0:
5403 index = fieldFromInstruction(insn: Insn, startBit: 5, numBits: 3);
5404 if (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1))
5405 align = 2;
5406 break;
5407 case 1:
5408 index = fieldFromInstruction(insn: Insn, startBit: 6, numBits: 2);
5409 if (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1))
5410 align = 4;
5411 if (fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1))
5412 inc = 2;
5413 break;
5414 case 2:
5415 if (fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1))
5416 return MCDisassembler::Fail; // UNDEFINED
5417 index = fieldFromInstruction(insn: Insn, startBit: 7, numBits: 1);
5418 if (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1) != 0)
5419 align = 8;
5420 if (fieldFromInstruction(insn: Insn, startBit: 6, numBits: 1))
5421 inc = 2;
5422 break;
5423 }
5424
5425 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
5426 return MCDisassembler::Fail;
5427 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd+inc, Address, Decoder)))
5428 return MCDisassembler::Fail;
5429 if (Rm != 0xF) { // Writeback
5430 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5431 return MCDisassembler::Fail;
5432 }
5433 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5434 return MCDisassembler::Fail;
5435 Inst.addOperand(Op: MCOperand::createImm(Val: align));
5436 if (Rm != 0xF) {
5437 if (Rm != 0xD) {
5438 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
5439 return MCDisassembler::Fail;
5440 } else
5441 Inst.addOperand(Op: MCOperand::createReg(Reg: 0));
5442 }
5443
5444 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
5445 return MCDisassembler::Fail;
5446 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd+inc, Address, Decoder)))
5447 return MCDisassembler::Fail;
5448 Inst.addOperand(Op: MCOperand::createImm(Val: index));
5449
5450 return S;
5451}
5452
5453static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5454 const MCDisassembler *Decoder) {
5455 DecodeStatus S = MCDisassembler::Success;
5456
5457 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
5458 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
5459 unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
5460 Rd |= fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 4;
5461 unsigned size = fieldFromInstruction(insn: Insn, startBit: 10, numBits: 2);
5462
5463 unsigned align = 0;
5464 unsigned index = 0;
5465 unsigned inc = 1;
5466 switch (size) {
5467 default:
5468 return MCDisassembler::Fail;
5469 case 0:
5470 index = fieldFromInstruction(insn: Insn, startBit: 5, numBits: 3);
5471 if (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1))
5472 align = 2;
5473 break;
5474 case 1:
5475 index = fieldFromInstruction(insn: Insn, startBit: 6, numBits: 2);
5476 if (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1))
5477 align = 4;
5478 if (fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1))
5479 inc = 2;
5480 break;
5481 case 2:
5482 if (fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1))
5483 return MCDisassembler::Fail; // UNDEFINED
5484 index = fieldFromInstruction(insn: Insn, startBit: 7, numBits: 1);
5485 if (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1) != 0)
5486 align = 8;
5487 if (fieldFromInstruction(insn: Insn, startBit: 6, numBits: 1))
5488 inc = 2;
5489 break;
5490 }
5491
5492 if (Rm != 0xF) { // Writeback
5493 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5494 return MCDisassembler::Fail;
5495 }
5496 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5497 return MCDisassembler::Fail;
5498 Inst.addOperand(Op: MCOperand::createImm(Val: align));
5499 if (Rm != 0xF) {
5500 if (Rm != 0xD) {
5501 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
5502 return MCDisassembler::Fail;
5503 } else
5504 Inst.addOperand(Op: MCOperand::createReg(Reg: 0));
5505 }
5506
5507 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
5508 return MCDisassembler::Fail;
5509 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd+inc, Address, Decoder)))
5510 return MCDisassembler::Fail;
5511 Inst.addOperand(Op: MCOperand::createImm(Val: index));
5512
5513 return S;
5514}
5515
5516static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5517 const MCDisassembler *Decoder) {
5518 DecodeStatus S = MCDisassembler::Success;
5519
5520 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
5521 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
5522 unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
5523 Rd |= fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 4;
5524 unsigned size = fieldFromInstruction(insn: Insn, startBit: 10, numBits: 2);
5525
5526 unsigned align = 0;
5527 unsigned index = 0;
5528 unsigned inc = 1;
5529 switch (size) {
5530 default:
5531 return MCDisassembler::Fail;
5532 case 0:
5533 if (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1))
5534 return MCDisassembler::Fail; // UNDEFINED
5535 index = fieldFromInstruction(insn: Insn, startBit: 5, numBits: 3);
5536 break;
5537 case 1:
5538 if (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1))
5539 return MCDisassembler::Fail; // UNDEFINED
5540 index = fieldFromInstruction(insn: Insn, startBit: 6, numBits: 2);
5541 if (fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1))
5542 inc = 2;
5543 break;
5544 case 2:
5545 if (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 2))
5546 return MCDisassembler::Fail; // UNDEFINED
5547 index = fieldFromInstruction(insn: Insn, startBit: 7, numBits: 1);
5548 if (fieldFromInstruction(insn: Insn, startBit: 6, numBits: 1))
5549 inc = 2;
5550 break;
5551 }
5552
5553 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
5554 return MCDisassembler::Fail;
5555 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd+inc, Address, Decoder)))
5556 return MCDisassembler::Fail;
5557 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd+2*inc, Address, Decoder)))
5558 return MCDisassembler::Fail;
5559
5560 if (Rm != 0xF) { // Writeback
5561 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5562 return MCDisassembler::Fail;
5563 }
5564 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5565 return MCDisassembler::Fail;
5566 Inst.addOperand(Op: MCOperand::createImm(Val: align));
5567 if (Rm != 0xF) {
5568 if (Rm != 0xD) {
5569 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
5570 return MCDisassembler::Fail;
5571 } else
5572 Inst.addOperand(Op: MCOperand::createReg(Reg: 0));
5573 }
5574
5575 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
5576 return MCDisassembler::Fail;
5577 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd+inc, Address, Decoder)))
5578 return MCDisassembler::Fail;
5579 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd+2*inc, Address, Decoder)))
5580 return MCDisassembler::Fail;
5581 Inst.addOperand(Op: MCOperand::createImm(Val: index));
5582
5583 return S;
5584}
5585
5586static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5587 const MCDisassembler *Decoder) {
5588 DecodeStatus S = MCDisassembler::Success;
5589
5590 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
5591 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
5592 unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
5593 Rd |= fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 4;
5594 unsigned size = fieldFromInstruction(insn: Insn, startBit: 10, numBits: 2);
5595
5596 unsigned align = 0;
5597 unsigned index = 0;
5598 unsigned inc = 1;
5599 switch (size) {
5600 default:
5601 return MCDisassembler::Fail;
5602 case 0:
5603 if (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1))
5604 return MCDisassembler::Fail; // UNDEFINED
5605 index = fieldFromInstruction(insn: Insn, startBit: 5, numBits: 3);
5606 break;
5607 case 1:
5608 if (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1))
5609 return MCDisassembler::Fail; // UNDEFINED
5610 index = fieldFromInstruction(insn: Insn, startBit: 6, numBits: 2);
5611 if (fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1))
5612 inc = 2;
5613 break;
5614 case 2:
5615 if (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 2))
5616 return MCDisassembler::Fail; // UNDEFINED
5617 index = fieldFromInstruction(insn: Insn, startBit: 7, numBits: 1);
5618 if (fieldFromInstruction(insn: Insn, startBit: 6, numBits: 1))
5619 inc = 2;
5620 break;
5621 }
5622
5623 if (Rm != 0xF) { // Writeback
5624 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5625 return MCDisassembler::Fail;
5626 }
5627 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5628 return MCDisassembler::Fail;
5629 Inst.addOperand(Op: MCOperand::createImm(Val: align));
5630 if (Rm != 0xF) {
5631 if (Rm != 0xD) {
5632 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
5633 return MCDisassembler::Fail;
5634 } else
5635 Inst.addOperand(Op: MCOperand::createReg(Reg: 0));
5636 }
5637
5638 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
5639 return MCDisassembler::Fail;
5640 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd+inc, Address, Decoder)))
5641 return MCDisassembler::Fail;
5642 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd+2*inc, Address, Decoder)))
5643 return MCDisassembler::Fail;
5644 Inst.addOperand(Op: MCOperand::createImm(Val: index));
5645
5646 return S;
5647}
5648
5649static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5650 const MCDisassembler *Decoder) {
5651 DecodeStatus S = MCDisassembler::Success;
5652
5653 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
5654 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
5655 unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
5656 Rd |= fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 4;
5657 unsigned size = fieldFromInstruction(insn: Insn, startBit: 10, numBits: 2);
5658
5659 unsigned align = 0;
5660 unsigned index = 0;
5661 unsigned inc = 1;
5662 switch (size) {
5663 default:
5664 return MCDisassembler::Fail;
5665 case 0:
5666 if (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1))
5667 align = 4;
5668 index = fieldFromInstruction(insn: Insn, startBit: 5, numBits: 3);
5669 break;
5670 case 1:
5671 if (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1))
5672 align = 8;
5673 index = fieldFromInstruction(insn: Insn, startBit: 6, numBits: 2);
5674 if (fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1))
5675 inc = 2;
5676 break;
5677 case 2:
5678 switch (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 2)) {
5679 case 0:
5680 align = 0; break;
5681 case 3:
5682 return MCDisassembler::Fail;
5683 default:
5684 align = 4 << fieldFromInstruction(insn: Insn, startBit: 4, numBits: 2); break;
5685 }
5686
5687 index = fieldFromInstruction(insn: Insn, startBit: 7, numBits: 1);
5688 if (fieldFromInstruction(insn: Insn, startBit: 6, numBits: 1))
5689 inc = 2;
5690 break;
5691 }
5692
5693 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
5694 return MCDisassembler::Fail;
5695 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd+inc, Address, Decoder)))
5696 return MCDisassembler::Fail;
5697 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd+2*inc, Address, Decoder)))
5698 return MCDisassembler::Fail;
5699 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd+3*inc, Address, Decoder)))
5700 return MCDisassembler::Fail;
5701
5702 if (Rm != 0xF) { // Writeback
5703 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5704 return MCDisassembler::Fail;
5705 }
5706 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5707 return MCDisassembler::Fail;
5708 Inst.addOperand(Op: MCOperand::createImm(Val: align));
5709 if (Rm != 0xF) {
5710 if (Rm != 0xD) {
5711 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
5712 return MCDisassembler::Fail;
5713 } else
5714 Inst.addOperand(Op: MCOperand::createReg(Reg: 0));
5715 }
5716
5717 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
5718 return MCDisassembler::Fail;
5719 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd+inc, Address, Decoder)))
5720 return MCDisassembler::Fail;
5721 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd+2*inc, Address, Decoder)))
5722 return MCDisassembler::Fail;
5723 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd+3*inc, Address, Decoder)))
5724 return MCDisassembler::Fail;
5725 Inst.addOperand(Op: MCOperand::createImm(Val: index));
5726
5727 return S;
5728}
5729
5730static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5731 const MCDisassembler *Decoder) {
5732 DecodeStatus S = MCDisassembler::Success;
5733
5734 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
5735 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
5736 unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
5737 Rd |= fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 4;
5738 unsigned size = fieldFromInstruction(insn: Insn, startBit: 10, numBits: 2);
5739
5740 unsigned align = 0;
5741 unsigned index = 0;
5742 unsigned inc = 1;
5743 switch (size) {
5744 default:
5745 return MCDisassembler::Fail;
5746 case 0:
5747 if (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1))
5748 align = 4;
5749 index = fieldFromInstruction(insn: Insn, startBit: 5, numBits: 3);
5750 break;
5751 case 1:
5752 if (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1))
5753 align = 8;
5754 index = fieldFromInstruction(insn: Insn, startBit: 6, numBits: 2);
5755 if (fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1))
5756 inc = 2;
5757 break;
5758 case 2:
5759 switch (fieldFromInstruction(insn: Insn, startBit: 4, numBits: 2)) {
5760 case 0:
5761 align = 0; break;
5762 case 3:
5763 return MCDisassembler::Fail;
5764 default:
5765 align = 4 << fieldFromInstruction(insn: Insn, startBit: 4, numBits: 2); break;
5766 }
5767
5768 index = fieldFromInstruction(insn: Insn, startBit: 7, numBits: 1);
5769 if (fieldFromInstruction(insn: Insn, startBit: 6, numBits: 1))
5770 inc = 2;
5771 break;
5772 }
5773
5774 if (Rm != 0xF) { // Writeback
5775 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5776 return MCDisassembler::Fail;
5777 }
5778 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5779 return MCDisassembler::Fail;
5780 Inst.addOperand(Op: MCOperand::createImm(Val: align));
5781 if (Rm != 0xF) {
5782 if (Rm != 0xD) {
5783 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
5784 return MCDisassembler::Fail;
5785 } else
5786 Inst.addOperand(Op: MCOperand::createReg(Reg: 0));
5787 }
5788
5789 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd, Address, Decoder)))
5790 return MCDisassembler::Fail;
5791 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd+inc, Address, Decoder)))
5792 return MCDisassembler::Fail;
5793 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd+2*inc, Address, Decoder)))
5794 return MCDisassembler::Fail;
5795 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Rd+3*inc, Address, Decoder)))
5796 return MCDisassembler::Fail;
5797 Inst.addOperand(Op: MCOperand::createImm(Val: index));
5798
5799 return S;
5800}
5801
5802static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address,
5803 const MCDisassembler *Decoder) {
5804 DecodeStatus S = MCDisassembler::Success;
5805 unsigned Rt = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
5806 unsigned Rt2 = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
5807 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1);
5808 unsigned pred = fieldFromInstruction(insn: Insn, startBit: 28, numBits: 4);
5809 Rm |= fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4) << 1;
5810
5811 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5812 S = MCDisassembler::SoftFail;
5813
5814 if (!Check(Out&: S, In: DecodeSPRRegisterClass(Inst, RegNo: Rm , Address, Decoder)))
5815 return MCDisassembler::Fail;
5816 if (!Check(Out&: S, In: DecodeSPRRegisterClass(Inst, RegNo: Rm+1, Address, Decoder)))
5817 return MCDisassembler::Fail;
5818 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rt , Address, Decoder)))
5819 return MCDisassembler::Fail;
5820 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rt2 , Address, Decoder)))
5821 return MCDisassembler::Fail;
5822 if (!Check(Out&: S, In: DecodePredicateOperand(Inst, Val: pred, Address, Decoder)))
5823 return MCDisassembler::Fail;
5824
5825 return S;
5826}
5827
5828static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address,
5829 const MCDisassembler *Decoder) {
5830 DecodeStatus S = MCDisassembler::Success;
5831 unsigned Rt = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
5832 unsigned Rt2 = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
5833 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1);
5834 unsigned pred = fieldFromInstruction(insn: Insn, startBit: 28, numBits: 4);
5835 Rm |= fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4) << 1;
5836
5837 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5838 S = MCDisassembler::SoftFail;
5839
5840 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rt , Address, Decoder)))
5841 return MCDisassembler::Fail;
5842 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rt2 , Address, Decoder)))
5843 return MCDisassembler::Fail;
5844 if (!Check(Out&: S, In: DecodeSPRRegisterClass(Inst, RegNo: Rm , Address, Decoder)))
5845 return MCDisassembler::Fail;
5846 if (!Check(Out&: S, In: DecodeSPRRegisterClass(Inst, RegNo: Rm+1, Address, Decoder)))
5847 return MCDisassembler::Fail;
5848 if (!Check(Out&: S, In: DecodePredicateOperand(Inst, Val: pred, Address, Decoder)))
5849 return MCDisassembler::Fail;
5850
5851 return S;
5852}
5853
5854static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address,
5855 const MCDisassembler *Decoder) {
5856 DecodeStatus S = MCDisassembler::Success;
5857 unsigned pred = fieldFromInstruction(insn: Insn, startBit: 4, numBits: 4);
5858 unsigned mask = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
5859
5860 if (pred == 0xF) {
5861 pred = 0xE;
5862 S = MCDisassembler::SoftFail;
5863 }
5864
5865 if (mask == 0x0)
5866 return MCDisassembler::Fail;
5867
5868 // IT masks are encoded as a sequence of replacement low-order bits
5869 // for the condition code. So if the low bit of the starting
5870 // condition code is 1, then we have to flip all the bits above the
5871 // terminating bit (which is the lowest 1 bit).
5872 if (pred & 1) {
5873 unsigned LowBit = mask & -mask;
5874 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
5875 mask ^= BitsAboveLowBit;
5876 }
5877
5878 Inst.addOperand(Op: MCOperand::createImm(Val: pred));
5879 Inst.addOperand(Op: MCOperand::createImm(Val: mask));
5880 return S;
5881}
5882
5883static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
5884 uint64_t Address,
5885 const MCDisassembler *Decoder) {
5886 DecodeStatus S = MCDisassembler::Success;
5887
5888 unsigned Rt = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
5889 unsigned Rt2 = fieldFromInstruction(insn: Insn, startBit: 8, numBits: 4);
5890 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
5891 unsigned addr = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 8);
5892 unsigned W = fieldFromInstruction(insn: Insn, startBit: 21, numBits: 1);
5893 unsigned U = fieldFromInstruction(insn: Insn, startBit: 23, numBits: 1);
5894 unsigned P = fieldFromInstruction(insn: Insn, startBit: 24, numBits: 1);
5895 bool writeback = (W == 1) | (P == 0);
5896
5897 addr |= (U << 8) | (Rn << 9);
5898
5899 if (writeback && (Rn == Rt || Rn == Rt2))
5900 Check(Out&: S, In: MCDisassembler::SoftFail);
5901 if (Rt == Rt2)
5902 Check(Out&: S, In: MCDisassembler::SoftFail);
5903
5904 // Rt
5905 if (!Check(Out&: S, In: DecoderGPRRegisterClass(Inst, RegNo: Rt, Address, Decoder)))
5906 return MCDisassembler::Fail;
5907 // Rt2
5908 if (!Check(Out&: S, In: DecoderGPRRegisterClass(Inst, RegNo: Rt2, Address, Decoder)))
5909 return MCDisassembler::Fail;
5910 // Writeback operand
5911 if (!Check(Out&: S, In: DecoderGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5912 return MCDisassembler::Fail;
5913 // addr
5914 if (!Check(Out&: S, In: DecodeT2AddrModeImm8s4(Inst, Val: addr, Address, Decoder)))
5915 return MCDisassembler::Fail;
5916
5917 return S;
5918}
5919
5920static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
5921 uint64_t Address,
5922 const MCDisassembler *Decoder) {
5923 DecodeStatus S = MCDisassembler::Success;
5924
5925 unsigned Rt = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
5926 unsigned Rt2 = fieldFromInstruction(insn: Insn, startBit: 8, numBits: 4);
5927 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
5928 unsigned addr = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 8);
5929 unsigned W = fieldFromInstruction(insn: Insn, startBit: 21, numBits: 1);
5930 unsigned U = fieldFromInstruction(insn: Insn, startBit: 23, numBits: 1);
5931 unsigned P = fieldFromInstruction(insn: Insn, startBit: 24, numBits: 1);
5932 bool writeback = (W == 1) | (P == 0);
5933
5934 addr |= (U << 8) | (Rn << 9);
5935
5936 if (writeback && (Rn == Rt || Rn == Rt2))
5937 Check(Out&: S, In: MCDisassembler::SoftFail);
5938
5939 // Writeback operand
5940 if (!Check(Out&: S, In: DecoderGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
5941 return MCDisassembler::Fail;
5942 // Rt
5943 if (!Check(Out&: S, In: DecoderGPRRegisterClass(Inst, RegNo: Rt, Address, Decoder)))
5944 return MCDisassembler::Fail;
5945 // Rt2
5946 if (!Check(Out&: S, In: DecoderGPRRegisterClass(Inst, RegNo: Rt2, Address, Decoder)))
5947 return MCDisassembler::Fail;
5948 // addr
5949 if (!Check(Out&: S, In: DecodeT2AddrModeImm8s4(Inst, Val: addr, Address, Decoder)))
5950 return MCDisassembler::Fail;
5951
5952 return S;
5953}
5954
5955static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address,
5956 const MCDisassembler *Decoder) {
5957 unsigned sign1 = fieldFromInstruction(insn: Insn, startBit: 21, numBits: 1);
5958 unsigned sign2 = fieldFromInstruction(insn: Insn, startBit: 23, numBits: 1);
5959 if (sign1 != sign2) return MCDisassembler::Fail;
5960 const unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 8, numBits: 4);
5961 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst");
5962 DecodeStatus S = DecoderGPRRegisterClass(Inst, RegNo: Rd, Address, Decoder);
5963
5964 unsigned Val = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 8);
5965 Val |= fieldFromInstruction(insn: Insn, startBit: 12, numBits: 3) << 8;
5966 Val |= fieldFromInstruction(insn: Insn, startBit: 26, numBits: 1) << 11;
5967 // If sign, then it is decreasing the address.
5968 if (sign1) {
5969 // Following ARMv7 Architecture Manual, when the offset
5970 // is zero, it is decoded as a subw, not as a adr.w
5971 if (!Val) {
5972 Inst.setOpcode(ARM::t2SUBri12);
5973 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::PC));
5974 } else
5975 Val = -Val;
5976 }
5977 Inst.addOperand(Op: MCOperand::createImm(Val));
5978 return S;
5979}
5980
5981static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
5982 uint64_t Address,
5983 const MCDisassembler *Decoder) {
5984 DecodeStatus S = MCDisassembler::Success;
5985
5986 // Shift of "asr #32" is not allowed in Thumb2 mode.
5987 if (Val == 0x20) S = MCDisassembler::Fail;
5988 Inst.addOperand(Op: MCOperand::createImm(Val));
5989 return S;
5990}
5991
5992static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address,
5993 const MCDisassembler *Decoder) {
5994 unsigned Rt = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
5995 unsigned Rt2 = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
5996 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
5997 unsigned pred = fieldFromInstruction(insn: Insn, startBit: 28, numBits: 4);
5998
5999 if (pred == 0xF)
6000 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
6001
6002 DecodeStatus S = MCDisassembler::Success;
6003
6004 if (Rt == Rn || Rn == Rt2)
6005 S = MCDisassembler::SoftFail;
6006
6007 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rt, Address, Decoder)))
6008 return MCDisassembler::Fail;
6009 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rt2, Address, Decoder)))
6010 return MCDisassembler::Fail;
6011 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
6012 return MCDisassembler::Fail;
6013 if (!Check(Out&: S, In: DecodePredicateOperand(Inst, Val: pred, Address, Decoder)))
6014 return MCDisassembler::Fail;
6015
6016 return S;
6017}
6018
6019static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address,
6020 const MCDisassembler *Decoder) {
6021 const FeatureBitset &featureBits =
6022 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
6023 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
6024
6025 unsigned Vd = (fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4) << 0);
6026 Vd |= (fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 4);
6027 unsigned Vm = (fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4) << 0);
6028 Vm |= (fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1) << 4);
6029 unsigned imm = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 6);
6030 unsigned cmode = fieldFromInstruction(insn: Insn, startBit: 8, numBits: 4);
6031 unsigned op = fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1);
6032
6033 DecodeStatus S = MCDisassembler::Success;
6034
6035 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
6036 if (!(imm & 0x38)) {
6037 if (cmode == 0xF) {
6038 if (op == 1) return MCDisassembler::Fail;
6039 Inst.setOpcode(ARM::VMOVv2f32);
6040 }
6041 if (hasFullFP16) {
6042 if (cmode == 0xE) {
6043 if (op == 1) {
6044 Inst.setOpcode(ARM::VMOVv1i64);
6045 } else {
6046 Inst.setOpcode(ARM::VMOVv8i8);
6047 }
6048 }
6049 if (cmode == 0xD) {
6050 if (op == 1) {
6051 Inst.setOpcode(ARM::VMVNv2i32);
6052 } else {
6053 Inst.setOpcode(ARM::VMOVv2i32);
6054 }
6055 }
6056 if (cmode == 0xC) {
6057 if (op == 1) {
6058 Inst.setOpcode(ARM::VMVNv2i32);
6059 } else {
6060 Inst.setOpcode(ARM::VMOVv2i32);
6061 }
6062 }
6063 }
6064 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
6065 }
6066
6067 if (!(imm & 0x20)) return MCDisassembler::Fail;
6068
6069 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Vd, Address, Decoder)))
6070 return MCDisassembler::Fail;
6071 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Vm, Address, Decoder)))
6072 return MCDisassembler::Fail;
6073 Inst.addOperand(Op: MCOperand::createImm(Val: 64 - imm));
6074
6075 return S;
6076}
6077
6078static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address,
6079 const MCDisassembler *Decoder) {
6080 const FeatureBitset &featureBits =
6081 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
6082 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
6083
6084 unsigned Vd = (fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4) << 0);
6085 Vd |= (fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 4);
6086 unsigned Vm = (fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4) << 0);
6087 Vm |= (fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1) << 4);
6088 unsigned imm = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 6);
6089 unsigned cmode = fieldFromInstruction(insn: Insn, startBit: 8, numBits: 4);
6090 unsigned op = fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1);
6091
6092 DecodeStatus S = MCDisassembler::Success;
6093
6094 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
6095 if (!(imm & 0x38)) {
6096 if (cmode == 0xF) {
6097 if (op == 1) return MCDisassembler::Fail;
6098 Inst.setOpcode(ARM::VMOVv4f32);
6099 }
6100 if (hasFullFP16) {
6101 if (cmode == 0xE) {
6102 if (op == 1) {
6103 Inst.setOpcode(ARM::VMOVv2i64);
6104 } else {
6105 Inst.setOpcode(ARM::VMOVv16i8);
6106 }
6107 }
6108 if (cmode == 0xD) {
6109 if (op == 1) {
6110 Inst.setOpcode(ARM::VMVNv4i32);
6111 } else {
6112 Inst.setOpcode(ARM::VMOVv4i32);
6113 }
6114 }
6115 if (cmode == 0xC) {
6116 if (op == 1) {
6117 Inst.setOpcode(ARM::VMVNv4i32);
6118 } else {
6119 Inst.setOpcode(ARM::VMOVv4i32);
6120 }
6121 }
6122 }
6123 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
6124 }
6125
6126 if (!(imm & 0x20)) return MCDisassembler::Fail;
6127
6128 if (!Check(Out&: S, In: DecodeQPRRegisterClass(Inst, RegNo: Vd, Address, Decoder)))
6129 return MCDisassembler::Fail;
6130 if (!Check(Out&: S, In: DecodeQPRRegisterClass(Inst, RegNo: Vm, Address, Decoder)))
6131 return MCDisassembler::Fail;
6132 Inst.addOperand(Op: MCOperand::createImm(Val: 64 - imm));
6133
6134 return S;
6135}
6136
6137static DecodeStatus
6138DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Insn,
6139 uint64_t Address,
6140 const MCDisassembler *Decoder) {
6141 unsigned Vd = (fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4) << 0);
6142 Vd |= (fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 4);
6143 unsigned Vn = (fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4) << 0);
6144 Vn |= (fieldFromInstruction(insn: Insn, startBit: 7, numBits: 1) << 4);
6145 unsigned Vm = (fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4) << 0);
6146 Vm |= (fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1) << 4);
6147 unsigned q = (fieldFromInstruction(insn: Insn, startBit: 6, numBits: 1) << 0);
6148 unsigned rotate = (fieldFromInstruction(insn: Insn, startBit: 20, numBits: 2) << 0);
6149
6150 DecodeStatus S = MCDisassembler::Success;
6151
6152 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass;
6153
6154 if (!Check(Out&: S, In: DestRegDecoder(Inst, Vd, Address, Decoder)))
6155 return MCDisassembler::Fail;
6156 if (!Check(Out&: S, In: DestRegDecoder(Inst, Vd, Address, Decoder)))
6157 return MCDisassembler::Fail;
6158 if (!Check(Out&: S, In: DestRegDecoder(Inst, Vn, Address, Decoder)))
6159 return MCDisassembler::Fail;
6160 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: Vm, Address, Decoder)))
6161 return MCDisassembler::Fail;
6162 // The lane index does not have any bits in the encoding, because it can only
6163 // be 0.
6164 Inst.addOperand(Op: MCOperand::createImm(Val: 0));
6165 Inst.addOperand(Op: MCOperand::createImm(Val: rotate));
6166
6167 return S;
6168}
6169
6170static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address,
6171 const MCDisassembler *Decoder) {
6172 DecodeStatus S = MCDisassembler::Success;
6173
6174 unsigned Rn = fieldFromInstruction(insn: Val, startBit: 16, numBits: 4);
6175 unsigned Rt = fieldFromInstruction(insn: Val, startBit: 12, numBits: 4);
6176 unsigned Rm = fieldFromInstruction(insn: Val, startBit: 0, numBits: 4);
6177 Rm |= (fieldFromInstruction(insn: Val, startBit: 23, numBits: 1) << 4);
6178 unsigned Cond = fieldFromInstruction(insn: Val, startBit: 28, numBits: 4);
6179
6180 if (fieldFromInstruction(insn: Val, startBit: 8, numBits: 4) != 0 || Rn == Rt)
6181 S = MCDisassembler::SoftFail;
6182
6183 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rt, Address, Decoder)))
6184 return MCDisassembler::Fail;
6185 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
6186 return MCDisassembler::Fail;
6187 if (!Check(Out&: S, In: DecodeAddrMode7Operand(Inst, Val: Rn, Address, Decoder)))
6188 return MCDisassembler::Fail;
6189 if (!Check(Out&: S, In: DecodePostIdxReg(Inst, Insn: Rm, Address, Decoder)))
6190 return MCDisassembler::Fail;
6191 if (!Check(Out&: S, In: DecodePredicateOperand(Inst, Val: Cond, Address, Decoder)))
6192 return MCDisassembler::Fail;
6193
6194 return S;
6195}
6196
6197static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
6198 uint64_t Address,
6199 const MCDisassembler *Decoder) {
6200 DecodeStatus S = MCDisassembler::Success;
6201
6202 unsigned CRm = fieldFromInstruction(insn: Val, startBit: 0, numBits: 4);
6203 unsigned opc1 = fieldFromInstruction(insn: Val, startBit: 4, numBits: 4);
6204 unsigned cop = fieldFromInstruction(insn: Val, startBit: 8, numBits: 4);
6205 unsigned Rt = fieldFromInstruction(insn: Val, startBit: 12, numBits: 4);
6206 unsigned Rt2 = fieldFromInstruction(insn: Val, startBit: 16, numBits: 4);
6207
6208 if ((cop & ~0x1) == 0xa)
6209 return MCDisassembler::Fail;
6210
6211 if (Rt == Rt2)
6212 S = MCDisassembler::SoftFail;
6213
6214 // We have to check if the instruction is MRRC2
6215 // or MCRR2 when constructing the operands for
6216 // Inst. Reason is because MRRC2 stores to two
6217 // registers so it's tablegen desc has two
6218 // outputs whereas MCRR doesn't store to any
6219 // registers so all of it's operands are listed
6220 // as inputs, therefore the operand order for
6221 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
6222 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
6223
6224 if (Inst.getOpcode() == ARM::MRRC2) {
6225 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rt, Address, Decoder)))
6226 return MCDisassembler::Fail;
6227 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rt2, Address, Decoder)))
6228 return MCDisassembler::Fail;
6229 }
6230 Inst.addOperand(Op: MCOperand::createImm(Val: cop));
6231 Inst.addOperand(Op: MCOperand::createImm(Val: opc1));
6232 if (Inst.getOpcode() == ARM::MCRR2) {
6233 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rt, Address, Decoder)))
6234 return MCDisassembler::Fail;
6235 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rt2, Address, Decoder)))
6236 return MCDisassembler::Fail;
6237 }
6238 Inst.addOperand(Op: MCOperand::createImm(Val: CRm));
6239
6240 return S;
6241}
6242
6243static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
6244 uint64_t Address,
6245 const MCDisassembler *Decoder) {
6246 const FeatureBitset &featureBits =
6247 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
6248 DecodeStatus S = MCDisassembler::Success;
6249
6250 // Add explicit operand for the destination sysreg, for cases where
6251 // we have to model it for code generation purposes.
6252 switch (Inst.getOpcode()) {
6253 case ARM::VMSR_FPSCR_NZCVQC:
6254 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::FPSCR_NZCV));
6255 break;
6256 case ARM::VMSR_P0:
6257 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::VPR));
6258 break;
6259 }
6260
6261 if (Inst.getOpcode() != ARM::FMSTAT) {
6262 unsigned Rt = fieldFromInstruction(insn: Val, startBit: 12, numBits: 4);
6263
6264 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
6265 if (Rt == 13 || Rt == 15)
6266 S = MCDisassembler::SoftFail;
6267 Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rt, Address, Decoder));
6268 } else
6269 Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rt, Address, Decoder));
6270 }
6271
6272 // Add explicit operand for the source sysreg, similarly to above.
6273 switch (Inst.getOpcode()) {
6274 case ARM::VMRS_FPSCR_NZCVQC:
6275 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::FPSCR_NZCV));
6276 break;
6277 case ARM::VMRS_P0:
6278 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::VPR));
6279 break;
6280 }
6281
6282 if (featureBits[ARM::ModeThumb]) {
6283 Inst.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
6284 Inst.addOperand(Op: MCOperand::createReg(Reg: 0));
6285 } else {
6286 unsigned pred = fieldFromInstruction(insn: Val, startBit: 28, numBits: 4);
6287 if (!Check(Out&: S, In: DecodePredicateOperand(Inst, Val: pred, Address, Decoder)))
6288 return MCDisassembler::Fail;
6289 }
6290
6291 return S;
6292}
6293
6294template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
6295static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val,
6296 uint64_t Address,
6297 const MCDisassembler *Decoder) {
6298 DecodeStatus S = MCDisassembler::Success;
6299 if (Val == 0 && !zeroPermitted)
6300 S = MCDisassembler::Fail;
6301
6302 uint64_t DecVal;
6303 if (isSigned)
6304 DecVal = SignExtend32<size + 1>(Val << 1);
6305 else
6306 DecVal = (Val << 1);
6307
6308 if (!tryAddingSymbolicOperand(Address, Value: Address + DecVal + 4, isBranch: true, InstSize: 4, MI&: Inst,
6309 Decoder))
6310 Inst.addOperand(Op: MCOperand::createImm(Val: isNeg ? -DecVal : DecVal));
6311 return S;
6312}
6313
6314static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val,
6315 uint64_t Address,
6316 const MCDisassembler *Decoder) {
6317
6318 uint64_t LocImm = Inst.getOperand(i: 0).getImm();
6319 Val = LocImm + (2 << Val);
6320 if (!tryAddingSymbolicOperand(Address, Value: Address + Val + 4, isBranch: true, InstSize: 4, MI&: Inst,
6321 Decoder))
6322 Inst.addOperand(Op: MCOperand::createImm(Val));
6323 return MCDisassembler::Success;
6324}
6325
6326static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
6327 uint64_t Address,
6328 const MCDisassembler *Decoder) {
6329 if (Val >= ARMCC::AL) // also exclude the non-condition NV
6330 return MCDisassembler::Fail;
6331 Inst.addOperand(Op: MCOperand::createImm(Val));
6332 return MCDisassembler::Success;
6333}
6334
6335static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
6336 const MCDisassembler *Decoder) {
6337 DecodeStatus S = MCDisassembler::Success;
6338
6339 if (Inst.getOpcode() == ARM::MVE_LCTP)
6340 return S;
6341
6342 unsigned Imm = fieldFromInstruction(insn: Insn, startBit: 11, numBits: 1) |
6343 fieldFromInstruction(insn: Insn, startBit: 1, numBits: 10) << 1;
6344 switch (Inst.getOpcode()) {
6345 case ARM::t2LEUpdate:
6346 case ARM::MVE_LETP:
6347 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::LR));
6348 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::LR));
6349 [[fallthrough]];
6350 case ARM::t2LE:
6351 if (!Check(Out&: S, In: DecodeBFLabelOperand<false, true, true, 11>(
6352 Inst, Val: Imm, Address, Decoder)))
6353 return MCDisassembler::Fail;
6354 break;
6355 case ARM::t2WLS:
6356 case ARM::MVE_WLSTP_8:
6357 case ARM::MVE_WLSTP_16:
6358 case ARM::MVE_WLSTP_32:
6359 case ARM::MVE_WLSTP_64:
6360 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::LR));
6361 if (!Check(Out&: S,
6362 In: DecoderGPRRegisterClass(Inst, RegNo: fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4),
6363 Address, Decoder)) ||
6364 !Check(Out&: S, In: DecodeBFLabelOperand<false, false, true, 11>(
6365 Inst, Val: Imm, Address, Decoder)))
6366 return MCDisassembler::Fail;
6367 break;
6368 case ARM::t2DLS:
6369 case ARM::MVE_DLSTP_8:
6370 case ARM::MVE_DLSTP_16:
6371 case ARM::MVE_DLSTP_32:
6372 case ARM::MVE_DLSTP_64:
6373 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
6374 if (Rn == 0xF) {
6375 // Enforce all the rest of the instruction bits in LCTP, which
6376 // won't have been reliably checked based on LCTP's own tablegen
6377 // record, because we came to this decode by a roundabout route.
6378 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE;
6379 if ((Insn & ~SBZMask) != CanonicalLCTP)
6380 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail
6381 if (Insn != CanonicalLCTP)
6382 Check(Out&: S, In: MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail
6383
6384 Inst.setOpcode(ARM::MVE_LCTP);
6385 } else {
6386 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::LR));
6387 if (!Check(Out&: S, In: DecoderGPRRegisterClass(Inst,
6388 RegNo: fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4),
6389 Address, Decoder)))
6390 return MCDisassembler::Fail;
6391 }
6392 break;
6393 }
6394 return S;
6395}
6396
6397static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
6398 uint64_t Address,
6399 const MCDisassembler *Decoder) {
6400 DecodeStatus S = MCDisassembler::Success;
6401
6402 if (Val == 0)
6403 Val = 32;
6404
6405 Inst.addOperand(Op: MCOperand::createImm(Val));
6406
6407 return S;
6408}
6409
6410static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
6411 uint64_t Address,
6412 const MCDisassembler *Decoder) {
6413 if ((RegNo) + 1 > 11)
6414 return MCDisassembler::Fail;
6415
6416 unsigned Register = GPRDecoderTable[(RegNo) + 1];
6417 Inst.addOperand(Op: MCOperand::createReg(Reg: Register));
6418 return MCDisassembler::Success;
6419}
6420
6421static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
6422 uint64_t Address,
6423 const MCDisassembler *Decoder) {
6424 if ((RegNo) > 14)
6425 return MCDisassembler::Fail;
6426
6427 unsigned Register = GPRDecoderTable[(RegNo)];
6428 Inst.addOperand(Op: MCOperand::createReg(Reg: Register));
6429 return MCDisassembler::Success;
6430}
6431
6432static DecodeStatus
6433DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
6434 uint64_t Address,
6435 const MCDisassembler *Decoder) {
6436 if (RegNo == 15) {
6437 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::APSR_NZCV));
6438 return MCDisassembler::Success;
6439 }
6440
6441 unsigned Register = GPRDecoderTable[RegNo];
6442 Inst.addOperand(Op: MCOperand::createReg(Reg: Register));
6443
6444 if (RegNo == 13)
6445 return MCDisassembler::SoftFail;
6446
6447 return MCDisassembler::Success;
6448}
6449
6450static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
6451 const MCDisassembler *Decoder) {
6452 DecodeStatus S = MCDisassembler::Success;
6453
6454 Inst.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
6455 Inst.addOperand(Op: MCOperand::createReg(Reg: 0));
6456 unsigned regs = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 8);
6457 if (regs == 0) {
6458 // Register list contains only VPR
6459 } else if (Inst.getOpcode() == ARM::VSCCLRMD) {
6460 unsigned reglist = regs | (fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4) << 8) |
6461 (fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 12);
6462 if (!Check(Out&: S, In: DecodeDPRRegListOperand(Inst, Val: reglist, Address, Decoder))) {
6463 return MCDisassembler::Fail;
6464 }
6465 } else {
6466 unsigned Vd = (fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4) << 1) |
6467 fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1);
6468 // Registers past s31 are permitted and treated as being half of a d
6469 // register, though both halves of each d register must be present.
6470 unsigned max_reg = Vd + regs;
6471 if (max_reg > 64 || (max_reg > 32 && (max_reg & 1)))
6472 S = MCDisassembler::SoftFail;
6473 unsigned max_sreg = std::min(a: 32u, b: max_reg);
6474 unsigned max_dreg = std::min(a: 32u, b: max_reg / 2);
6475 for (unsigned i = Vd; i < max_sreg; ++i)
6476 if (!Check(Out&: S, In: DecodeSPRRegisterClass(Inst, RegNo: i, Address, Decoder)))
6477 return MCDisassembler::Fail;
6478 for (unsigned i = 16; i < max_dreg; ++i)
6479 if (!Check(Out&: S, In: DecodeDPRRegisterClass(Inst, RegNo: i, Address, Decoder)))
6480 return MCDisassembler::Fail;
6481 }
6482 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::VPR));
6483
6484 return S;
6485}
6486
6487static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
6488 uint64_t Address,
6489 const MCDisassembler *Decoder) {
6490 if (RegNo > 7)
6491 return MCDisassembler::Fail;
6492
6493 unsigned Register = QPRDecoderTable[RegNo];
6494 Inst.addOperand(Op: MCOperand::createReg(Reg: Register));
6495 return MCDisassembler::Success;
6496}
6497
6498static const MCPhysReg QQPRDecoderTable[] = {
6499 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4,
6500 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7
6501};
6502
6503static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
6504 uint64_t Address,
6505 const MCDisassembler *Decoder) {
6506 if (RegNo > 6)
6507 return MCDisassembler::Fail;
6508
6509 unsigned Register = QQPRDecoderTable[RegNo];
6510 Inst.addOperand(Op: MCOperand::createReg(Reg: Register));
6511 return MCDisassembler::Success;
6512}
6513
6514static const MCPhysReg QQQQPRDecoderTable[] = {
6515 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5,
6516 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7
6517};
6518
6519static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
6520 uint64_t Address,
6521 const MCDisassembler *Decoder) {
6522 if (RegNo > 4)
6523 return MCDisassembler::Fail;
6524
6525 unsigned Register = QQQQPRDecoderTable[RegNo];
6526 Inst.addOperand(Op: MCOperand::createReg(Reg: Register));
6527 return MCDisassembler::Success;
6528}
6529
6530static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
6531 uint64_t Address,
6532 const MCDisassembler *Decoder) {
6533 DecodeStatus S = MCDisassembler::Success;
6534
6535 // Parse VPT mask and encode it in the MCInst as an immediate with the same
6536 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and
6537 // 't' as 0 and finish with a 1.
6538 unsigned Imm = 0;
6539 // We always start with a 't'.
6540 unsigned CurBit = 0;
6541 for (int i = 3; i >= 0; --i) {
6542 // If the bit we are looking at is not the same as last one, invert the
6543 // CurBit, if it is the same leave it as is.
6544 CurBit ^= (Val >> i) & 1U;
6545
6546 // Encode the CurBit at the right place in the immediate.
6547 Imm |= (CurBit << i);
6548
6549 // If we are done, finish the encoding with a 1.
6550 if ((Val & ~(~0U << i)) == 0) {
6551 Imm |= 1U << i;
6552 break;
6553 }
6554 }
6555
6556 Inst.addOperand(Op: MCOperand::createImm(Val: Imm));
6557
6558 return S;
6559}
6560
6561static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo,
6562 uint64_t Address,
6563 const MCDisassembler *Decoder) {
6564 // The vpred_r operand type includes an MQPR register field derived
6565 // from the encoding. But we don't actually want to add an operand
6566 // to the MCInst at this stage, because AddThumbPredicate will do it
6567 // later, and will infer the register number from the TIED_TO
6568 // constraint. So this is a deliberately empty decoder method that
6569 // will inhibit the auto-generated disassembly code from adding an
6570 // operand at all.
6571 return MCDisassembler::Success;
6572}
6573
6574[[maybe_unused]] static DecodeStatus
6575DecodeVpredNOperand(MCInst &Inst, unsigned RegNo, uint64_t Address,
6576 const MCDisassembler *Decoder) {
6577 // Similar to above, we want to ensure that no operands are added for the
6578 // vpred operands. (This is marked "maybe_unused" for the moment; because
6579 // DecoderEmitter currently (wrongly) omits operands with no instruction bits,
6580 // the decoder doesn't actually call it yet. That will be addressed in a
6581 // future change.)
6582 return MCDisassembler::Success;
6583}
6584
6585static DecodeStatus
6586DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
6587 const MCDisassembler *Decoder) {
6588 Inst.addOperand(Op: MCOperand::createImm(Val: (Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE));
6589 return MCDisassembler::Success;
6590}
6591
6592static DecodeStatus
6593DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
6594 const MCDisassembler *Decoder) {
6595 unsigned Code;
6596 switch (Val & 0x3) {
6597 case 0:
6598 Code = ARMCC::GE;
6599 break;
6600 case 1:
6601 Code = ARMCC::LT;
6602 break;
6603 case 2:
6604 Code = ARMCC::GT;
6605 break;
6606 case 3:
6607 Code = ARMCC::LE;
6608 break;
6609 }
6610 Inst.addOperand(Op: MCOperand::createImm(Val: Code));
6611 return MCDisassembler::Success;
6612}
6613
6614static DecodeStatus
6615DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
6616 const MCDisassembler *Decoder) {
6617 Inst.addOperand(Op: MCOperand::createImm(Val: (Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI));
6618 return MCDisassembler::Success;
6619}
6620
6621static DecodeStatus
6622DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
6623 const MCDisassembler *Decoder) {
6624 unsigned Code;
6625 switch (Val) {
6626 default:
6627 return MCDisassembler::Fail;
6628 case 0:
6629 Code = ARMCC::EQ;
6630 break;
6631 case 1:
6632 Code = ARMCC::NE;
6633 break;
6634 case 4:
6635 Code = ARMCC::GE;
6636 break;
6637 case 5:
6638 Code = ARMCC::LT;
6639 break;
6640 case 6:
6641 Code = ARMCC::GT;
6642 break;
6643 case 7:
6644 Code = ARMCC::LE;
6645 break;
6646 }
6647
6648 Inst.addOperand(Op: MCOperand::createImm(Val: Code));
6649 return MCDisassembler::Success;
6650}
6651
6652static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val,
6653 uint64_t Address,
6654 const MCDisassembler *Decoder) {
6655 DecodeStatus S = MCDisassembler::Success;
6656
6657 unsigned DecodedVal = 64 - Val;
6658
6659 switch (Inst.getOpcode()) {
6660 case ARM::MVE_VCVTf16s16_fix:
6661 case ARM::MVE_VCVTs16f16_fix:
6662 case ARM::MVE_VCVTf16u16_fix:
6663 case ARM::MVE_VCVTu16f16_fix:
6664 if (DecodedVal > 16)
6665 return MCDisassembler::Fail;
6666 break;
6667 case ARM::MVE_VCVTf32s32_fix:
6668 case ARM::MVE_VCVTs32f32_fix:
6669 case ARM::MVE_VCVTf32u32_fix:
6670 case ARM::MVE_VCVTu32f32_fix:
6671 if (DecodedVal > 32)
6672 return MCDisassembler::Fail;
6673 break;
6674 }
6675
6676 Inst.addOperand(Op: MCOperand::createImm(Val: 64 - Val));
6677
6678 return S;
6679}
6680
6681static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) {
6682 switch (Opcode) {
6683 case ARM::VSTR_P0_off:
6684 case ARM::VSTR_P0_pre:
6685 case ARM::VSTR_P0_post:
6686 case ARM::VLDR_P0_off:
6687 case ARM::VLDR_P0_pre:
6688 case ARM::VLDR_P0_post:
6689 return ARM::P0;
6690 case ARM::VSTR_FPSCR_NZCVQC_off:
6691 case ARM::VSTR_FPSCR_NZCVQC_pre:
6692 case ARM::VSTR_FPSCR_NZCVQC_post:
6693 case ARM::VLDR_FPSCR_NZCVQC_off:
6694 case ARM::VLDR_FPSCR_NZCVQC_pre:
6695 case ARM::VLDR_FPSCR_NZCVQC_post:
6696 return ARM::FPSCR;
6697 default:
6698 return 0;
6699 }
6700}
6701
6702template <bool Writeback>
6703static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val,
6704 uint64_t Address,
6705 const MCDisassembler *Decoder) {
6706 switch (Inst.getOpcode()) {
6707 case ARM::VSTR_FPSCR_pre:
6708 case ARM::VSTR_FPSCR_NZCVQC_pre:
6709 case ARM::VLDR_FPSCR_pre:
6710 case ARM::VLDR_FPSCR_NZCVQC_pre:
6711 case ARM::VSTR_FPSCR_off:
6712 case ARM::VSTR_FPSCR_NZCVQC_off:
6713 case ARM::VLDR_FPSCR_off:
6714 case ARM::VLDR_FPSCR_NZCVQC_off:
6715 case ARM::VSTR_FPSCR_post:
6716 case ARM::VSTR_FPSCR_NZCVQC_post:
6717 case ARM::VLDR_FPSCR_post:
6718 case ARM::VLDR_FPSCR_NZCVQC_post:
6719 const FeatureBitset &featureBits =
6720 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
6721
6722 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2])
6723 return MCDisassembler::Fail;
6724 }
6725
6726 DecodeStatus S = MCDisassembler::Success;
6727 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Opcode: Inst.getOpcode()))
6728 Inst.addOperand(Op: MCOperand::createReg(Reg: Sysreg));
6729 unsigned Rn = fieldFromInstruction(insn: Val, startBit: 16, numBits: 4);
6730 unsigned addr = fieldFromInstruction(insn: Val, startBit: 0, numBits: 7) |
6731 (fieldFromInstruction(insn: Val, startBit: 23, numBits: 1) << 7) | (Rn << 8);
6732
6733 if (Writeback) {
6734 if (!Check(Out&: S, In: DecodeGPRnopcRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
6735 return MCDisassembler::Fail;
6736 }
6737 if (!Check(Out&: S, In: DecodeT2AddrModeImm7s4(Inst, Val: addr, Address, Decoder)))
6738 return MCDisassembler::Fail;
6739
6740 Inst.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
6741 Inst.addOperand(Op: MCOperand::createReg(Reg: 0));
6742
6743 return S;
6744}
6745
6746static inline DecodeStatus
6747DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address,
6748 const MCDisassembler *Decoder, unsigned Rn,
6749 OperandDecoder RnDecoder, OperandDecoder AddrDecoder) {
6750 DecodeStatus S = MCDisassembler::Success;
6751
6752 unsigned Qd = fieldFromInstruction(insn: Val, startBit: 13, numBits: 3);
6753 unsigned addr = fieldFromInstruction(insn: Val, startBit: 0, numBits: 7) |
6754 (fieldFromInstruction(insn: Val, startBit: 23, numBits: 1) << 7) | (Rn << 8);
6755
6756 if (!Check(Out&: S, In: RnDecoder(Inst, Rn, Address, Decoder)))
6757 return MCDisassembler::Fail;
6758 if (!Check(Out&: S, In: DecodeMQPRRegisterClass(Inst, RegNo: Qd, Address, Decoder)))
6759 return MCDisassembler::Fail;
6760 if (!Check(Out&: S, In: AddrDecoder(Inst, addr, Address, Decoder)))
6761 return MCDisassembler::Fail;
6762
6763 return S;
6764}
6765
6766template <int shift>
6767static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
6768 uint64_t Address,
6769 const MCDisassembler *Decoder) {
6770 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
6771 fieldFromInstruction(insn: Val, startBit: 16, numBits: 3),
6772 DecodetGPRRegisterClass,
6773 DecodeTAddrModeImm7<shift>);
6774}
6775
6776template <int shift>
6777static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
6778 uint64_t Address,
6779 const MCDisassembler *Decoder) {
6780 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
6781 fieldFromInstruction(insn: Val, startBit: 16, numBits: 4),
6782 DecoderGPRRegisterClass,
6783 DecodeT2AddrModeImm7<shift,1>);
6784}
6785
6786template <int shift>
6787static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
6788 uint64_t Address,
6789 const MCDisassembler *Decoder) {
6790 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
6791 fieldFromInstruction(insn: Val, startBit: 17, numBits: 3),
6792 DecodeMQPRRegisterClass,
6793 DecodeMveAddrModeQ<shift>);
6794}
6795
6796template <unsigned MinLog, unsigned MaxLog>
6797static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
6798 uint64_t Address,
6799 const MCDisassembler *Decoder) {
6800 DecodeStatus S = MCDisassembler::Success;
6801
6802 if (Val < MinLog || Val > MaxLog)
6803 return MCDisassembler::Fail;
6804
6805 Inst.addOperand(Op: MCOperand::createImm(Val: 1LL << Val));
6806 return S;
6807}
6808
6809template <unsigned start>
6810static DecodeStatus
6811DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address,
6812 const MCDisassembler *Decoder) {
6813 DecodeStatus S = MCDisassembler::Success;
6814
6815 Inst.addOperand(Op: MCOperand::createImm(Val: start + Val));
6816
6817 return S;
6818}
6819
6820static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
6821 uint64_t Address,
6822 const MCDisassembler *Decoder) {
6823 DecodeStatus S = MCDisassembler::Success;
6824 unsigned Rt = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
6825 unsigned Rt2 = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
6826 unsigned Qd = ((fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 3) |
6827 fieldFromInstruction(insn: Insn, startBit: 13, numBits: 3));
6828 unsigned index = fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1);
6829
6830 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rt, Address, Decoder)))
6831 return MCDisassembler::Fail;
6832 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rt2, Address, Decoder)))
6833 return MCDisassembler::Fail;
6834 if (!Check(Out&: S, In: DecodeMQPRRegisterClass(Inst, RegNo: Qd, Address, Decoder)))
6835 return MCDisassembler::Fail;
6836 if (!Check(Out&: S, In: DecodeMVEPairVectorIndexOperand<2>(Inst, Val: index, Address, Decoder)))
6837 return MCDisassembler::Fail;
6838 if (!Check(Out&: S, In: DecodeMVEPairVectorIndexOperand<0>(Inst, Val: index, Address, Decoder)))
6839 return MCDisassembler::Fail;
6840
6841 return S;
6842}
6843
6844static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
6845 uint64_t Address,
6846 const MCDisassembler *Decoder) {
6847 DecodeStatus S = MCDisassembler::Success;
6848 unsigned Rt = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
6849 unsigned Rt2 = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
6850 unsigned Qd = ((fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 3) |
6851 fieldFromInstruction(insn: Insn, startBit: 13, numBits: 3));
6852 unsigned index = fieldFromInstruction(insn: Insn, startBit: 4, numBits: 1);
6853
6854 if (!Check(Out&: S, In: DecodeMQPRRegisterClass(Inst, RegNo: Qd, Address, Decoder)))
6855 return MCDisassembler::Fail;
6856 if (!Check(Out&: S, In: DecodeMQPRRegisterClass(Inst, RegNo: Qd, Address, Decoder)))
6857 return MCDisassembler::Fail;
6858 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rt, Address, Decoder)))
6859 return MCDisassembler::Fail;
6860 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rt2, Address, Decoder)))
6861 return MCDisassembler::Fail;
6862 if (!Check(Out&: S, In: DecodeMVEPairVectorIndexOperand<2>(Inst, Val: index, Address, Decoder)))
6863 return MCDisassembler::Fail;
6864 if (!Check(Out&: S, In: DecodeMVEPairVectorIndexOperand<0>(Inst, Val: index, Address, Decoder)))
6865 return MCDisassembler::Fail;
6866
6867 return S;
6868}
6869
6870static DecodeStatus
6871DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address,
6872 const MCDisassembler *Decoder) {
6873 DecodeStatus S = MCDisassembler::Success;
6874
6875 unsigned RdaLo = fieldFromInstruction(insn: Insn, startBit: 17, numBits: 3) << 1;
6876 unsigned RdaHi = fieldFromInstruction(insn: Insn, startBit: 9, numBits: 3) << 1;
6877 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 4);
6878
6879 if (RdaHi == 14) {
6880 // This value of RdaHi (really indicating pc, because RdaHi has to
6881 // be an odd-numbered register, so the low bit will be set by the
6882 // decode function below) indicates that we must decode as SQRSHR
6883 // or UQRSHL, which both have a single Rda register field with all
6884 // four bits.
6885 unsigned Rda = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
6886
6887 switch (Inst.getOpcode()) {
6888 case ARM::MVE_ASRLr:
6889 case ARM::MVE_SQRSHRL:
6890 Inst.setOpcode(ARM::MVE_SQRSHR);
6891 break;
6892 case ARM::MVE_LSLLr:
6893 case ARM::MVE_UQRSHLL:
6894 Inst.setOpcode(ARM::MVE_UQRSHL);
6895 break;
6896 default:
6897 llvm_unreachable("Unexpected starting opcode!");
6898 }
6899
6900 // Rda as output parameter
6901 if (!Check(Out&: S, In: DecoderGPRRegisterClass(Inst, RegNo: Rda, Address, Decoder)))
6902 return MCDisassembler::Fail;
6903
6904 // Rda again as input parameter
6905 if (!Check(Out&: S, In: DecoderGPRRegisterClass(Inst, RegNo: Rda, Address, Decoder)))
6906 return MCDisassembler::Fail;
6907
6908 // Rm, the amount to shift by
6909 if (!Check(Out&: S, In: DecoderGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
6910 return MCDisassembler::Fail;
6911
6912 if (fieldFromInstruction (insn: Insn, startBit: 6, numBits: 3) != 4)
6913 return MCDisassembler::SoftFail;
6914
6915 if (Rda == Rm)
6916 return MCDisassembler::SoftFail;
6917
6918 return S;
6919 }
6920
6921 // Otherwise, we decode as whichever opcode our caller has already
6922 // put into Inst. Those all look the same:
6923
6924 // RdaLo,RdaHi as output parameters
6925 if (!Check(Out&: S, In: DecodetGPREvenRegisterClass(Inst, RegNo: RdaLo, Address, Decoder)))
6926 return MCDisassembler::Fail;
6927 if (!Check(Out&: S, In: DecodetGPROddRegisterClass(Inst, RegNo: RdaHi, Address, Decoder)))
6928 return MCDisassembler::Fail;
6929
6930 // RdaLo,RdaHi again as input parameters
6931 if (!Check(Out&: S, In: DecodetGPREvenRegisterClass(Inst, RegNo: RdaLo, Address, Decoder)))
6932 return MCDisassembler::Fail;
6933 if (!Check(Out&: S, In: DecodetGPROddRegisterClass(Inst, RegNo: RdaHi, Address, Decoder)))
6934 return MCDisassembler::Fail;
6935
6936 // Rm, the amount to shift by
6937 if (!Check(Out&: S, In: DecoderGPRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
6938 return MCDisassembler::Fail;
6939
6940 if (Inst.getOpcode() == ARM::MVE_SQRSHRL ||
6941 Inst.getOpcode() == ARM::MVE_UQRSHLL) {
6942 unsigned Saturate = fieldFromInstruction(insn: Insn, startBit: 7, numBits: 1);
6943 // Saturate, the bit position for saturation
6944 Inst.addOperand(Op: MCOperand::createImm(Val: Saturate));
6945 }
6946
6947 return S;
6948}
6949
6950static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
6951 uint64_t Address,
6952 const MCDisassembler *Decoder) {
6953 DecodeStatus S = MCDisassembler::Success;
6954 unsigned Qd = ((fieldFromInstruction(insn: Insn, startBit: 22, numBits: 1) << 3) |
6955 fieldFromInstruction(insn: Insn, startBit: 13, numBits: 3));
6956 unsigned Qm = ((fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1) << 3) |
6957 fieldFromInstruction(insn: Insn, startBit: 1, numBits: 3));
6958 unsigned imm6 = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 6);
6959
6960 if (!Check(Out&: S, In: DecodeMQPRRegisterClass(Inst, RegNo: Qd, Address, Decoder)))
6961 return MCDisassembler::Fail;
6962 if (!Check(Out&: S, In: DecodeMQPRRegisterClass(Inst, RegNo: Qm, Address, Decoder)))
6963 return MCDisassembler::Fail;
6964 if (!Check(Out&: S, In: DecodeVCVTImmOperand(Inst, Val: imm6, Address, Decoder)))
6965 return MCDisassembler::Fail;
6966
6967 return S;
6968}
6969
6970template <bool scalar, OperandDecoder predicate_decoder>
6971static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
6972 const MCDisassembler *Decoder) {
6973 DecodeStatus S = MCDisassembler::Success;
6974 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::VPR));
6975 unsigned Qn = fieldFromInstruction(insn: Insn, startBit: 17, numBits: 3);
6976 if (!Check(Out&: S, In: DecodeMQPRRegisterClass(Inst, RegNo: Qn, Address, Decoder)))
6977 return MCDisassembler::Fail;
6978
6979 unsigned fc;
6980
6981 if (scalar) {
6982 fc = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 1) << 2 |
6983 fieldFromInstruction(insn: Insn, startBit: 7, numBits: 1) |
6984 fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1) << 1;
6985 unsigned Rm = fieldFromInstruction(insn: Insn, startBit: 0, numBits: 4);
6986 if (!Check(Out&: S, In: DecodeGPRwithZRRegisterClass(Inst, RegNo: Rm, Address, Decoder)))
6987 return MCDisassembler::Fail;
6988 } else {
6989 fc = fieldFromInstruction(insn: Insn, startBit: 12, numBits: 1) << 2 |
6990 fieldFromInstruction(insn: Insn, startBit: 7, numBits: 1) |
6991 fieldFromInstruction(insn: Insn, startBit: 0, numBits: 1) << 1;
6992 unsigned Qm = fieldFromInstruction(insn: Insn, startBit: 5, numBits: 1) << 4 |
6993 fieldFromInstruction(insn: Insn, startBit: 1, numBits: 3);
6994 if (!Check(Out&: S, In: DecodeMQPRRegisterClass(Inst, RegNo: Qm, Address, Decoder)))
6995 return MCDisassembler::Fail;
6996 }
6997
6998 if (!Check(Out&: S, In: predicate_decoder(Inst, fc, Address, Decoder)))
6999 return MCDisassembler::Fail;
7000
7001 Inst.addOperand(Op: MCOperand::createImm(Val: ARMVCC::None));
7002 Inst.addOperand(Op: MCOperand::createReg(Reg: 0));
7003 Inst.addOperand(Op: MCOperand::createImm(Val: 0));
7004
7005 return S;
7006}
7007
7008static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
7009 const MCDisassembler *Decoder) {
7010 DecodeStatus S = MCDisassembler::Success;
7011 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::VPR));
7012 unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
7013 if (!Check(Out&: S, In: DecoderGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
7014 return MCDisassembler::Fail;
7015 return S;
7016}
7017
7018static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
7019 uint64_t Address,
7020 const MCDisassembler *Decoder) {
7021 DecodeStatus S = MCDisassembler::Success;
7022 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::VPR));
7023 Inst.addOperand(Op: MCOperand::createReg(Reg: ARM::VPR));
7024 return S;
7025}
7026
7027static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
7028 uint64_t Address,
7029 const MCDisassembler *Decoder) {
7030 const unsigned Rd = fieldFromInstruction(insn: Insn, startBit: 8, numBits: 4);
7031 const unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
7032 const unsigned Imm12 = fieldFromInstruction(insn: Insn, startBit: 26, numBits: 1) << 11 |
7033 fieldFromInstruction(insn: Insn, startBit: 12, numBits: 3) << 8 |
7034 fieldFromInstruction(insn: Insn, startBit: 0, numBits: 8);
7035 const unsigned TypeT3 = fieldFromInstruction(insn: Insn, startBit: 25, numBits: 1);
7036 unsigned sign1 = fieldFromInstruction(insn: Insn, startBit: 21, numBits: 1);
7037 unsigned sign2 = fieldFromInstruction(insn: Insn, startBit: 23, numBits: 1);
7038 unsigned S = fieldFromInstruction(insn: Insn, startBit: 20, numBits: 1);
7039 if (sign1 != sign2)
7040 return MCDisassembler::Fail;
7041
7042 // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm)
7043 DecodeStatus DS = MCDisassembler::Success;
7044 if ((!Check(Out&: DS,
7045 In: DecodeGPRspRegisterClass(Inst, RegNo: Rd, Address, Decoder))) || // dst
7046 (!Check(Out&: DS, In: DecodeGPRspRegisterClass(Inst, RegNo: Rn, Address, Decoder))))
7047 return MCDisassembler::Fail;
7048 if (TypeT3) {
7049 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12);
7050 Inst.addOperand(Op: MCOperand::createImm(Val: Imm12)); // zext imm12
7051 } else {
7052 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm);
7053 if (!Check(Out&: DS, In: DecodeT2SOImm(Inst, Val: Imm12, Address, Decoder))) // imm12
7054 return MCDisassembler::Fail;
7055 if (!Check(Out&: DS, In: DecodeCCOutOperand(Inst, Val: S, Address, Decoder))) // cc_out
7056 return MCDisassembler::Fail;
7057 }
7058
7059 return DS;
7060}
7061
7062static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn,
7063 uint64_t Address,
7064 const MCDisassembler *Decoder) {
7065 DecodeStatus S = MCDisassembler::Success;
7066
7067 const unsigned Rn = fieldFromInstruction(insn: Insn, startBit: 16, numBits: 4);
7068 // Adding Rn, holding memory location to save/load to/from, the only argument
7069 // that is being encoded.
7070 // '$Rn' in the assembly.
7071 if (!Check(Out&: S, In: DecodeGPRRegisterClass(Inst, RegNo: Rn, Address, Decoder)))
7072 return MCDisassembler::Fail;
7073 // An optional predicate, '$p' in the assembly.
7074 DecodePredicateOperand(Inst, Val: ARMCC::AL, Address, Decoder);
7075 // An immediate that represents a floating point registers list. '$regs' in
7076 // the assembly.
7077 Inst.addOperand(Op: MCOperand::createImm(Val: 0)); // Arbitrary value, has no effect.
7078
7079 return S;
7080}
7081