1//===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "MCTargetDesc/ARMAsmBackend.h"
10#include "MCTargetDesc/ARMAddressingModes.h"
11#include "MCTargetDesc/ARMAsmBackendDarwin.h"
12#include "MCTargetDesc/ARMAsmBackendELF.h"
13#include "MCTargetDesc/ARMAsmBackendWinCOFF.h"
14#include "MCTargetDesc/ARMFixupKinds.h"
15#include "MCTargetDesc/ARMMCAsmInfo.h"
16#include "MCTargetDesc/ARMMCTargetDesc.h"
17#include "llvm/ADT/StringSwitch.h"
18#include "llvm/BinaryFormat/ELF.h"
19#include "llvm/BinaryFormat/MachO.h"
20#include "llvm/MC/MCAsmBackend.h"
21#include "llvm/MC/MCAssembler.h"
22#include "llvm/MC/MCContext.h"
23#include "llvm/MC/MCELFObjectWriter.h"
24#include "llvm/MC/MCExpr.h"
25#include "llvm/MC/MCFixupKindInfo.h"
26#include "llvm/MC/MCObjectWriter.h"
27#include "llvm/MC/MCRegisterInfo.h"
28#include "llvm/MC/MCSubtargetInfo.h"
29#include "llvm/MC/MCTargetOptions.h"
30#include "llvm/MC/MCValue.h"
31#include "llvm/Support/Debug.h"
32#include "llvm/Support/EndianStream.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/MathExtras.h"
35#include "llvm/Support/raw_ostream.h"
36using namespace llvm;
37
38namespace {
39class ARMELFObjectWriter : public MCELFObjectTargetWriter {
40public:
41 ARMELFObjectWriter(uint8_t OSABI)
42 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
43 /*HasRelocationAddend*/ false) {}
44};
45} // end anonymous namespace
46
47std::optional<MCFixupKind> ARMAsmBackend::getFixupKind(StringRef Name) const {
48 return std::nullopt;
49}
50
51std::optional<MCFixupKind>
52ARMAsmBackendELF::getFixupKind(StringRef Name) const {
53 unsigned Type = llvm::StringSwitch<unsigned>(Name)
54#define ELF_RELOC(X, Y) .Case(#X, Y)
55#include "llvm/BinaryFormat/ELFRelocs/ARM.def"
56#undef ELF_RELOC
57 .Case(S: "BFD_RELOC_NONE", Value: ELF::R_ARM_NONE)
58 .Case(S: "BFD_RELOC_8", Value: ELF::R_ARM_ABS8)
59 .Case(S: "BFD_RELOC_16", Value: ELF::R_ARM_ABS16)
60 .Case(S: "BFD_RELOC_32", Value: ELF::R_ARM_ABS32)
61 .Default(Value: -1u);
62 if (Type == -1u)
63 return std::nullopt;
64 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
65}
66
67MCFixupKindInfo ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
68 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
69 // This table *must* be in the order that the fixup_* kinds are defined in
70 // ARMFixupKinds.h.
71 //
72 // Name Offset (bits) Size (bits) Flags
73 {.Name: "fixup_arm_ldst_pcrel_12", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
74 {.Name: "fixup_t2_ldst_pcrel_12", .TargetOffset: 0, .TargetSize: 32,
75 .Flags: MCFixupKindInfo::FKF_IsPCRel |
76 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
77 {.Name: "fixup_arm_pcrel_10_unscaled", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
78 {.Name: "fixup_arm_pcrel_10", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
79 {.Name: "fixup_t2_pcrel_10", .TargetOffset: 0, .TargetSize: 32,
80 .Flags: MCFixupKindInfo::FKF_IsPCRel |
81 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
82 {.Name: "fixup_arm_pcrel_9", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
83 {.Name: "fixup_t2_pcrel_9", .TargetOffset: 0, .TargetSize: 32,
84 .Flags: MCFixupKindInfo::FKF_IsPCRel |
85 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
86 {.Name: "fixup_arm_ldst_abs_12", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
87 {.Name: "fixup_thumb_adr_pcrel_10", .TargetOffset: 0, .TargetSize: 8,
88 .Flags: MCFixupKindInfo::FKF_IsPCRel |
89 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
90 {.Name: "fixup_arm_adr_pcrel_12", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
91 {.Name: "fixup_t2_adr_pcrel_12", .TargetOffset: 0, .TargetSize: 32,
92 .Flags: MCFixupKindInfo::FKF_IsPCRel |
93 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
94 {.Name: "fixup_arm_condbranch", .TargetOffset: 0, .TargetSize: 24, .Flags: MCFixupKindInfo::FKF_IsPCRel},
95 {.Name: "fixup_arm_uncondbranch", .TargetOffset: 0, .TargetSize: 24, .Flags: MCFixupKindInfo::FKF_IsPCRel},
96 {.Name: "fixup_t2_condbranch", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
97 {.Name: "fixup_t2_uncondbranch", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
98 {.Name: "fixup_arm_thumb_br", .TargetOffset: 0, .TargetSize: 16, .Flags: MCFixupKindInfo::FKF_IsPCRel},
99 {.Name: "fixup_arm_uncondbl", .TargetOffset: 0, .TargetSize: 24, .Flags: MCFixupKindInfo::FKF_IsPCRel},
100 {.Name: "fixup_arm_condbl", .TargetOffset: 0, .TargetSize: 24, .Flags: MCFixupKindInfo::FKF_IsPCRel},
101 {.Name: "fixup_arm_blx", .TargetOffset: 0, .TargetSize: 24, .Flags: MCFixupKindInfo::FKF_IsPCRel},
102 {.Name: "fixup_arm_thumb_bl", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
103 {.Name: "fixup_arm_thumb_blx", .TargetOffset: 0, .TargetSize: 32,
104 .Flags: MCFixupKindInfo::FKF_IsPCRel |
105 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
106 {.Name: "fixup_arm_thumb_cb", .TargetOffset: 0, .TargetSize: 16, .Flags: MCFixupKindInfo::FKF_IsPCRel},
107 {.Name: "fixup_arm_thumb_cp", .TargetOffset: 0, .TargetSize: 8,
108 .Flags: MCFixupKindInfo::FKF_IsPCRel |
109 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
110 {.Name: "fixup_arm_thumb_bcc", .TargetOffset: 0, .TargetSize: 8, .Flags: MCFixupKindInfo::FKF_IsPCRel},
111 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
112 // - 19.
113 {.Name: "fixup_arm_movt_hi16", .TargetOffset: 0, .TargetSize: 20, .Flags: 0},
114 {.Name: "fixup_arm_movw_lo16", .TargetOffset: 0, .TargetSize: 20, .Flags: 0},
115 {.Name: "fixup_t2_movt_hi16", .TargetOffset: 0, .TargetSize: 20, .Flags: 0},
116 {.Name: "fixup_t2_movw_lo16", .TargetOffset: 0, .TargetSize: 20, .Flags: 0},
117 {.Name: "fixup_arm_thumb_upper_8_15", .TargetOffset: 0, .TargetSize: 8, .Flags: 0},
118 {.Name: "fixup_arm_thumb_upper_0_7", .TargetOffset: 0, .TargetSize: 8, .Flags: 0},
119 {.Name: "fixup_arm_thumb_lower_8_15", .TargetOffset: 0, .TargetSize: 8, .Flags: 0},
120 {.Name: "fixup_arm_thumb_lower_0_7", .TargetOffset: 0, .TargetSize: 8, .Flags: 0},
121 {.Name: "fixup_arm_mod_imm", .TargetOffset: 0, .TargetSize: 12, .Flags: 0},
122 {.Name: "fixup_t2_so_imm", .TargetOffset: 0, .TargetSize: 26, .Flags: 0},
123 {.Name: "fixup_bf_branch", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
124 {.Name: "fixup_bf_target", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
125 {.Name: "fixup_bfl_target", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
126 {.Name: "fixup_bfc_target", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
127 {.Name: "fixup_bfcsel_else_target", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
128 {.Name: "fixup_wls", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
129 {.Name: "fixup_le", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel}};
130 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
131 // This table *must* be in the order that the fixup_* kinds are defined in
132 // ARMFixupKinds.h.
133 //
134 // Name Offset (bits) Size (bits) Flags
135 {.Name: "fixup_arm_ldst_pcrel_12", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
136 {.Name: "fixup_t2_ldst_pcrel_12", .TargetOffset: 0, .TargetSize: 32,
137 .Flags: MCFixupKindInfo::FKF_IsPCRel |
138 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
139 {.Name: "fixup_arm_pcrel_10_unscaled", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
140 {.Name: "fixup_arm_pcrel_10", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
141 {.Name: "fixup_t2_pcrel_10", .TargetOffset: 0, .TargetSize: 32,
142 .Flags: MCFixupKindInfo::FKF_IsPCRel |
143 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
144 {.Name: "fixup_arm_pcrel_9", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
145 {.Name: "fixup_t2_pcrel_9", .TargetOffset: 0, .TargetSize: 32,
146 .Flags: MCFixupKindInfo::FKF_IsPCRel |
147 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
148 {.Name: "fixup_arm_ldst_abs_12", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
149 {.Name: "fixup_thumb_adr_pcrel_10", .TargetOffset: 8, .TargetSize: 8,
150 .Flags: MCFixupKindInfo::FKF_IsPCRel |
151 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
152 {.Name: "fixup_arm_adr_pcrel_12", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
153 {.Name: "fixup_t2_adr_pcrel_12", .TargetOffset: 0, .TargetSize: 32,
154 .Flags: MCFixupKindInfo::FKF_IsPCRel |
155 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
156 {.Name: "fixup_arm_condbranch", .TargetOffset: 8, .TargetSize: 24, .Flags: MCFixupKindInfo::FKF_IsPCRel},
157 {.Name: "fixup_arm_uncondbranch", .TargetOffset: 8, .TargetSize: 24, .Flags: MCFixupKindInfo::FKF_IsPCRel},
158 {.Name: "fixup_t2_condbranch", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
159 {.Name: "fixup_t2_uncondbranch", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
160 {.Name: "fixup_arm_thumb_br", .TargetOffset: 0, .TargetSize: 16, .Flags: MCFixupKindInfo::FKF_IsPCRel},
161 {.Name: "fixup_arm_uncondbl", .TargetOffset: 8, .TargetSize: 24, .Flags: MCFixupKindInfo::FKF_IsPCRel},
162 {.Name: "fixup_arm_condbl", .TargetOffset: 8, .TargetSize: 24, .Flags: MCFixupKindInfo::FKF_IsPCRel},
163 {.Name: "fixup_arm_blx", .TargetOffset: 8, .TargetSize: 24, .Flags: MCFixupKindInfo::FKF_IsPCRel},
164 {.Name: "fixup_arm_thumb_bl", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
165 {.Name: "fixup_arm_thumb_blx", .TargetOffset: 0, .TargetSize: 32,
166 .Flags: MCFixupKindInfo::FKF_IsPCRel |
167 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
168 {.Name: "fixup_arm_thumb_cb", .TargetOffset: 0, .TargetSize: 16, .Flags: MCFixupKindInfo::FKF_IsPCRel},
169 {.Name: "fixup_arm_thumb_cp", .TargetOffset: 8, .TargetSize: 8,
170 .Flags: MCFixupKindInfo::FKF_IsPCRel |
171 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
172 {.Name: "fixup_arm_thumb_bcc", .TargetOffset: 8, .TargetSize: 8, .Flags: MCFixupKindInfo::FKF_IsPCRel},
173 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
174 // - 19.
175 {.Name: "fixup_arm_movt_hi16", .TargetOffset: 12, .TargetSize: 20, .Flags: 0},
176 {.Name: "fixup_arm_movw_lo16", .TargetOffset: 12, .TargetSize: 20, .Flags: 0},
177 {.Name: "fixup_t2_movt_hi16", .TargetOffset: 12, .TargetSize: 20, .Flags: 0},
178 {.Name: "fixup_t2_movw_lo16", .TargetOffset: 12, .TargetSize: 20, .Flags: 0},
179 {.Name: "fixup_arm_thumb_upper_8_15", .TargetOffset: 24, .TargetSize: 8, .Flags: 0},
180 {.Name: "fixup_arm_thumb_upper_0_7", .TargetOffset: 24, .TargetSize: 8, .Flags: 0},
181 {.Name: "fixup_arm_thumb_lower_8_15", .TargetOffset: 24, .TargetSize: 8, .Flags: 0},
182 {.Name: "fixup_arm_thumb_lower_0_7", .TargetOffset: 24, .TargetSize: 8, .Flags: 0},
183 {.Name: "fixup_arm_mod_imm", .TargetOffset: 20, .TargetSize: 12, .Flags: 0},
184 {.Name: "fixup_t2_so_imm", .TargetOffset: 26, .TargetSize: 6, .Flags: 0},
185 {.Name: "fixup_bf_branch", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
186 {.Name: "fixup_bf_target", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
187 {.Name: "fixup_bfl_target", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
188 {.Name: "fixup_bfc_target", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
189 {.Name: "fixup_bfcsel_else_target", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
190 {.Name: "fixup_wls", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel},
191 {.Name: "fixup_le", .TargetOffset: 0, .TargetSize: 32, .Flags: MCFixupKindInfo::FKF_IsPCRel}};
192
193 // Fixup kinds from .reloc directive are like R_ARM_NONE. They do not require
194 // any extra processing.
195 if (mc::isRelocation(FixupKind: Kind))
196 return MCAsmBackend::getFixupKindInfo(Kind: FK_NONE);
197
198 if (Kind < FirstTargetFixupKind)
199 return MCAsmBackend::getFixupKindInfo(Kind);
200
201 assert(unsigned(Kind - FirstTargetFixupKind) < ARM::NumTargetFixupKinds &&
202 "Invalid kind!");
203 return (Endian == llvm::endianness::little
204 ? InfosLE
205 : InfosBE)[Kind - FirstTargetFixupKind];
206}
207
208unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op,
209 const MCSubtargetInfo &STI) const {
210 bool HasThumb2 = STI.hasFeature(Feature: ARM::FeatureThumb2);
211 bool HasV8MBaselineOps = STI.hasFeature(Feature: ARM::HasV8MBaselineOps);
212
213 switch (Op) {
214 default:
215 return Op;
216 case ARM::tBcc:
217 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op;
218 case ARM::tLDRpci:
219 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op;
220 case ARM::tADR:
221 return HasThumb2 ? (unsigned)ARM::t2ADR : Op;
222 case ARM::tB:
223 return HasV8MBaselineOps ? (unsigned)ARM::t2B : Op;
224 case ARM::tCBZ:
225 return ARM::tHINT;
226 case ARM::tCBNZ:
227 return ARM::tHINT;
228 }
229}
230
231bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst,
232 const MCSubtargetInfo &STI) const {
233 if (getRelaxedOpcode(Op: Inst.getOpcode(), STI) != Inst.getOpcode())
234 return true;
235 return false;
236}
237
238static const char *checkPCRelOffset(uint64_t Value, int64_t Min, int64_t Max) {
239 int64_t Offset = int64_t(Value) - 4;
240 if (Offset < Min || Offset > Max)
241 return "out of range pc-relative fixup value";
242 return nullptr;
243}
244
245const char *ARMAsmBackend::reasonForFixupRelaxation(const MCFixup &Fixup,
246 uint64_t Value) const {
247 switch (Fixup.getTargetKind()) {
248 case ARM::fixup_arm_thumb_br: {
249 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
250 // low bit being an implied zero. There's an implied +4 offset for the
251 // branch, so we adjust the other way here to determine what's
252 // encodable.
253 //
254 // Relax if the value is too big for a (signed) i8.
255 int64_t Offset = int64_t(Value) - 4;
256 if (Offset > 2046 || Offset < -2048)
257 return "out of range pc-relative fixup value";
258 break;
259 }
260 case ARM::fixup_arm_thumb_bcc: {
261 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
262 // low bit being an implied zero. There's an implied +4 offset for the
263 // branch, so we adjust the other way here to determine what's
264 // encodable.
265 //
266 // Relax if the value is too big for a (signed) i8.
267 int64_t Offset = int64_t(Value) - 4;
268 if (Offset > 254 || Offset < -256)
269 return "out of range pc-relative fixup value";
270 break;
271 }
272 case ARM::fixup_thumb_adr_pcrel_10:
273 case ARM::fixup_arm_thumb_cp: {
274 // If the immediate is negative, greater than 1020, or not a multiple
275 // of four, the wide version of the instruction must be used.
276 int64_t Offset = int64_t(Value) - 4;
277 if (Offset & 3)
278 return "misaligned pc-relative fixup value";
279 else if (Offset > 1020 || Offset < 0)
280 return "out of range pc-relative fixup value";
281 break;
282 }
283 case ARM::fixup_arm_thumb_cb: {
284 // If we have a Thumb CBZ or CBNZ instruction and its target is the next
285 // instruction it is actually out of range for the instruction.
286 // It will be changed to a NOP.
287 int64_t Offset = (Value & ~1);
288 if (Offset == 2)
289 return "will be converted to nop";
290 break;
291 }
292 case ARM::fixup_bf_branch:
293 return checkPCRelOffset(Value, Min: 0, Max: 30);
294 case ARM::fixup_bf_target:
295 return checkPCRelOffset(Value, Min: -0x10000, Max: +0xfffe);
296 case ARM::fixup_bfl_target:
297 return checkPCRelOffset(Value, Min: -0x40000, Max: +0x3fffe);
298 case ARM::fixup_bfc_target:
299 return checkPCRelOffset(Value, Min: -0x1000, Max: +0xffe);
300 case ARM::fixup_wls:
301 return checkPCRelOffset(Value, Min: 0, Max: +0xffe);
302 case ARM::fixup_le:
303 // The offset field in the LE and LETP instructions is an 11-bit
304 // value shifted left by 2 (i.e. 0,2,4,...,4094), and it is
305 // interpreted as a negative offset from the value read from pc,
306 // i.e. from instruction_address+4.
307 //
308 // So an LE instruction can in principle address the instruction
309 // immediately after itself, or (not very usefully) the address
310 // half way through the 4-byte LE.
311 return checkPCRelOffset(Value, Min: -0xffe, Max: 0);
312 case ARM::fixup_bfcsel_else_target: {
313 if (Value != 2 && Value != 4)
314 return "out of range label-relative fixup value";
315 break;
316 }
317
318 default:
319 llvm_unreachable("Unexpected fixup kind in reasonForFixupRelaxation()!");
320 }
321 return nullptr;
322}
323
324static bool needsInterworking(const MCAssembler &Asm, const MCSymbol *Sym,
325 unsigned FixupKind) {
326 // Create relocations for unconditional branches to function symbols with
327 // different execution mode in ELF binaries.
328 if (!Sym || !Sym->isELF())
329 return false;
330 unsigned Type = cast<MCSymbolELF>(Val: Sym)->getType();
331 if ((Type == ELF::STT_FUNC || Type == ELF::STT_GNU_IFUNC)) {
332 if (Asm.isThumbFunc(Func: Sym) && (FixupKind == ARM::fixup_arm_uncondbranch))
333 return true;
334 if (!Asm.isThumbFunc(Func: Sym) && (FixupKind == ARM::fixup_arm_thumb_br ||
335 FixupKind == ARM::fixup_arm_thumb_bl ||
336 FixupKind == ARM::fixup_t2_condbranch ||
337 FixupKind == ARM::fixup_t2_uncondbranch))
338 return true;
339 }
340 return false;
341}
342
343bool ARMAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup,
344 const MCValue &Target,
345 uint64_t Value,
346 bool Resolved) const {
347 const MCSymbol *Sym = Target.getAddSym();
348 if (needsInterworking(Asm: *Asm, Sym, FixupKind: Fixup.getTargetKind()))
349 return true;
350
351 if (!Resolved)
352 return true;
353 return reasonForFixupRelaxation(Fixup, Value);
354}
355
356void ARMAsmBackend::relaxInstruction(MCInst &Inst,
357 const MCSubtargetInfo &STI) const {
358 unsigned RelaxedOp = getRelaxedOpcode(Op: Inst.getOpcode(), STI);
359
360 // Return a diagnostic if we get here w/ a bogus instruction.
361 if (RelaxedOp == Inst.getOpcode()) {
362 SmallString<256> Tmp;
363 raw_svector_ostream OS(Tmp);
364 Inst.dump_pretty(OS);
365 OS << "\n";
366 report_fatal_error(reason: "unexpected instruction to relax: " + OS.str());
367 }
368
369 // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we
370 // have to change the operands too.
371 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) &&
372 RelaxedOp == ARM::tHINT) {
373 MCInst Res;
374 Res.setOpcode(RelaxedOp);
375 Res.addOperand(Op: MCOperand::createImm(Val: 0));
376 Res.addOperand(Op: MCOperand::createImm(Val: 14));
377 Res.addOperand(Op: MCOperand::createReg(Reg: 0));
378 Inst = std::move(Res);
379 return;
380 }
381
382 // The rest of instructions we're relaxing have the same operands.
383 // We just need to update to the proper opcode.
384 Inst.setOpcode(RelaxedOp);
385}
386
387bool ARMAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
388 const MCSubtargetInfo *STI) const {
389 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
390 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
391 const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0
392 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
393 if (STI->hasFeature(Feature: ARM::ModeThumb)) {
394 const uint16_t nopEncoding =
395 hasNOP(STI) ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding;
396 uint64_t NumNops = Count / 2;
397 for (uint64_t i = 0; i != NumNops; ++i)
398 support::endian::write(os&: OS, value: nopEncoding, endian: Endian);
399 if (Count & 1)
400 OS << '\0';
401 return true;
402 }
403 // ARM mode
404 const uint32_t nopEncoding =
405 hasNOP(STI) ? ARMv6T2_NopEncoding : ARMv4_NopEncoding;
406 uint64_t NumNops = Count / 4;
407 for (uint64_t i = 0; i != NumNops; ++i)
408 support::endian::write(os&: OS, value: nopEncoding, endian: Endian);
409 // FIXME: should this function return false when unable to write exactly
410 // 'Count' bytes with NOP encodings?
411 switch (Count % 4) {
412 default:
413 break; // No leftover bytes to write
414 case 1:
415 OS << '\0';
416 break;
417 case 2:
418 OS.write(Ptr: "\0\0", Size: 2);
419 break;
420 case 3:
421 OS.write(Ptr: "\0\0\xa0", Size: 3);
422 break;
423 }
424
425 return true;
426}
427
428static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian) {
429 if (IsLittleEndian) {
430 // Note that the halfwords are stored high first and low second in thumb;
431 // so we need to swap the fixup value here to map properly.
432 uint32_t Swapped = (Value & 0xFFFF0000) >> 16;
433 Swapped |= (Value & 0x0000FFFF) << 16;
434 return Swapped;
435 } else
436 return Value;
437}
438
439static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf,
440 bool IsLittleEndian) {
441 uint32_t Value;
442
443 if (IsLittleEndian) {
444 Value = (SecondHalf & 0xFFFF) << 16;
445 Value |= (FirstHalf & 0xFFFF);
446 } else {
447 Value = (SecondHalf & 0xFFFF);
448 Value |= (FirstHalf & 0xFFFF) << 16;
449 }
450
451 return Value;
452}
453
454unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm,
455 const MCFixup &Fixup,
456 const MCValue &Target, uint64_t Value,
457 bool IsResolved, MCContext &Ctx,
458 const MCSubtargetInfo* STI) const {
459 unsigned Kind = Fixup.getKind();
460 int64_t Addend = Target.getConstant();
461
462 // For MOVW/MOVT Instructions, the fixup value must already be within a
463 // signed 16bit range.
464 if ((Kind == ARM::fixup_arm_movw_lo16 || Kind == ARM::fixup_arm_movt_hi16 ||
465 Kind == ARM::fixup_t2_movw_lo16 || Kind == ARM::fixup_t2_movt_hi16) &&
466 (Addend < minIntN(N: 16) || Addend > maxIntN(N: 16))) {
467 Ctx.reportError(L: Fixup.getLoc(), Msg: "Relocation Not In Range");
468 return 0;
469 }
470
471 // MachO tries to make .o files that look vaguely pre-linked, so for MOVW/MOVT
472 // and .word relocations they put the Thumb bit into the addend if possible.
473 // Other relocation types don't want this bit though (branches couldn't encode
474 // it if it *was* present, and no other relocations exist) and it can
475 // interfere with checking valid expressions.
476 bool IsMachO = getContext().getObjectFileType() == MCContext::IsMachO;
477 if (const auto *SA = Target.getAddSym()) {
478 if (IsMachO && Asm.isThumbFunc(Func: SA) && SA->isExternal() &&
479 (Kind == FK_Data_4 || Kind == ARM::fixup_arm_movw_lo16 ||
480 Kind == ARM::fixup_arm_movt_hi16 || Kind == ARM::fixup_t2_movw_lo16 ||
481 Kind == ARM::fixup_t2_movt_hi16))
482 Value |= 1;
483 }
484
485 switch (Kind) {
486 default:
487 return 0;
488 case FK_Data_1:
489 case FK_Data_2:
490 case FK_Data_4:
491 return Value;
492 case FK_SecRel_2:
493 return Value;
494 case FK_SecRel_4:
495 return Value;
496 case ARM::fixup_arm_movt_hi16:
497 assert(STI != nullptr);
498 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
499 Value >>= 16;
500 [[fallthrough]];
501 case ARM::fixup_arm_movw_lo16: {
502 unsigned Hi4 = (Value & 0xF000) >> 12;
503 unsigned Lo12 = Value & 0x0FFF;
504 // inst{19-16} = Hi4;
505 // inst{11-0} = Lo12;
506 Value = (Hi4 << 16) | (Lo12);
507 return Value;
508 }
509 case ARM::fixup_t2_movt_hi16:
510 assert(STI != nullptr);
511 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
512 Value >>= 16;
513 [[fallthrough]];
514 case ARM::fixup_t2_movw_lo16: {
515 unsigned Hi4 = (Value & 0xF000) >> 12;
516 unsigned i = (Value & 0x800) >> 11;
517 unsigned Mid3 = (Value & 0x700) >> 8;
518 unsigned Lo8 = Value & 0x0FF;
519 // inst{19-16} = Hi4;
520 // inst{26} = i;
521 // inst{14-12} = Mid3;
522 // inst{7-0} = Lo8;
523 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
524 return swapHalfWords(Value, IsLittleEndian: Endian == llvm::endianness::little);
525 }
526 case ARM::fixup_arm_thumb_upper_8_15:
527 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
528 return (Value & 0xff000000) >> 24;
529 return Value & 0xff;
530 case ARM::fixup_arm_thumb_upper_0_7:
531 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
532 return (Value & 0x00ff0000) >> 16;
533 return Value & 0xff;
534 case ARM::fixup_arm_thumb_lower_8_15:
535 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
536 return (Value & 0x0000ff00) >> 8;
537 return Value & 0xff;
538 case ARM::fixup_arm_thumb_lower_0_7:
539 return Value & 0x000000ff;
540 case ARM::fixup_arm_ldst_pcrel_12:
541 // ARM PC-relative values are offset by 8.
542 Value -= 4;
543 [[fallthrough]];
544 case ARM::fixup_t2_ldst_pcrel_12:
545 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
546 Value -= 4;
547 [[fallthrough]];
548 case ARM::fixup_arm_ldst_abs_12: {
549 bool isAdd = true;
550 if ((int64_t)Value < 0) {
551 Value = -Value;
552 isAdd = false;
553 }
554 if (Value >= 4096) {
555 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range pc-relative fixup value");
556 return 0;
557 }
558 Value |= isAdd << 23;
559
560 // Same addressing mode as fixup_arm_pcrel_10,
561 // but with 16-bit halfwords swapped.
562 if (Kind == ARM::fixup_t2_ldst_pcrel_12)
563 return swapHalfWords(Value, IsLittleEndian: Endian == llvm::endianness::little);
564
565 return Value;
566 }
567 case ARM::fixup_arm_adr_pcrel_12: {
568 // ARM PC-relative values are offset by 8.
569 Value -= 8;
570 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
571 if ((int64_t)Value < 0) {
572 Value = -Value;
573 opc = 2; // 0b0010
574 }
575 if (ARM_AM::getSOImmVal(Arg: Value) == -1) {
576 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range pc-relative fixup value");
577 return 0;
578 }
579 // Encode the immediate and shift the opcode into place.
580 return ARM_AM::getSOImmVal(Arg: Value) | (opc << 21);
581 }
582
583 case ARM::fixup_t2_adr_pcrel_12: {
584 Value -= 4;
585 unsigned opc = 0;
586 if ((int64_t)Value < 0) {
587 Value = -Value;
588 opc = 5;
589 }
590
591 uint32_t out = (opc << 21);
592 out |= (Value & 0x800) << 15;
593 out |= (Value & 0x700) << 4;
594 out |= (Value & 0x0FF);
595
596 return swapHalfWords(Value: out, IsLittleEndian: Endian == llvm::endianness::little);
597 }
598
599 case ARM::fixup_arm_condbranch:
600 case ARM::fixup_arm_uncondbranch:
601 case ARM::fixup_arm_uncondbl:
602 case ARM::fixup_arm_condbl:
603 case ARM::fixup_arm_blx:
604 // Check that the relocation value is legal.
605 Value -= 8;
606 if (!isInt<26>(x: Value)) {
607 Ctx.reportError(L: Fixup.getLoc(), Msg: "Relocation out of range");
608 return 0;
609 }
610 // Alignment differs for blx. Because we are switching to thumb ISA, we use
611 // 16-bit alignment. Otherwise, use 32-bit.
612 if ((Kind == ARM::fixup_arm_blx && Value % 2 != 0) ||
613 (Kind != ARM::fixup_arm_blx && Value % 4 != 0)) {
614 Ctx.reportError(L: Fixup.getLoc(), Msg: "Relocation not aligned");
615 return 0;
616 }
617
618 // These values don't encode the low two bits since they're always zero.
619 // Offset by 8 just as above.
620 if (const MCSymbolRefExpr *SRE =
621 dyn_cast<MCSymbolRefExpr>(Val: Fixup.getValue()))
622 if (SRE->getSpecifier() == ARM::S_TLSCALL)
623 return 0;
624 return 0xffffff & (Value >> 2);
625 case ARM::fixup_t2_uncondbranch: {
626 if (STI->getTargetTriple().isOSBinFormatCOFF() && !IsResolved &&
627 Value != 4) {
628 // MSVC link.exe and lld do not support this relocation type
629 // with a non-zero offset. ("Value" is offset by 4 at this point.)
630 Ctx.reportError(L: Fixup.getLoc(),
631 Msg: "cannot perform a PC-relative fixup with a non-zero "
632 "symbol offset");
633 }
634 Value = Value - 4;
635 if (!isInt<25>(x: Value)) {
636 Ctx.reportError(L: Fixup.getLoc(), Msg: "Relocation out of range");
637 return 0;
638 }
639
640 Value >>= 1; // Low bit is not encoded.
641
642 uint32_t out = 0;
643 bool I = Value & 0x800000;
644 bool J1 = Value & 0x400000;
645 bool J2 = Value & 0x200000;
646 J1 ^= I;
647 J2 ^= I;
648
649 out |= I << 26; // S bit
650 out |= !J1 << 13; // J1 bit
651 out |= !J2 << 11; // J2 bit
652 out |= (Value & 0x1FF800) << 5; // imm6 field
653 out |= (Value & 0x0007FF); // imm11 field
654
655 return swapHalfWords(Value: out, IsLittleEndian: Endian == llvm::endianness::little);
656 }
657 case ARM::fixup_t2_condbranch: {
658 Value = Value - 4;
659 if (!isInt<21>(x: Value)) {
660 Ctx.reportError(L: Fixup.getLoc(), Msg: "Relocation out of range");
661 return 0;
662 }
663
664 Value >>= 1; // Low bit is not encoded.
665
666 uint64_t out = 0;
667 out |= (Value & 0x80000) << 7; // S bit
668 out |= (Value & 0x40000) >> 7; // J2 bit
669 out |= (Value & 0x20000) >> 4; // J1 bit
670 out |= (Value & 0x1F800) << 5; // imm6 field
671 out |= (Value & 0x007FF); // imm11 field
672
673 return swapHalfWords(Value: out, IsLittleEndian: Endian == llvm::endianness::little);
674 }
675 case ARM::fixup_arm_thumb_bl: {
676 if (!isInt<25>(x: Value - 4) ||
677 (!STI->hasFeature(Feature: ARM::FeatureThumb2) &&
678 !STI->hasFeature(Feature: ARM::HasV8MBaselineOps) &&
679 !STI->hasFeature(Feature: ARM::HasV6MOps) &&
680 !isInt<23>(x: Value - 4))) {
681 Ctx.reportError(L: Fixup.getLoc(), Msg: "Relocation out of range");
682 return 0;
683 }
684 if (STI->getTargetTriple().isOSBinFormatCOFF() && !IsResolved &&
685 Value != 4) {
686 // MSVC link.exe and lld do not support this relocation type
687 // with a non-zero offset. ("Value" is offset by 4 at this point.)
688 Ctx.reportError(L: Fixup.getLoc(),
689 Msg: "cannot perform a PC-relative fixup with a non-zero "
690 "symbol offset");
691 }
692
693 // The value doesn't encode the low bit (always zero) and is offset by
694 // four. The 32-bit immediate value is encoded as
695 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0)
696 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
697 // The value is encoded into disjoint bit positions in the destination
698 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
699 // J = either J1 or J2 bit
700 //
701 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII
702 //
703 // Note that the halfwords are stored high first, low second; so we need
704 // to transpose the fixup value here to map properly.
705 uint32_t offset = (Value - 4) >> 1;
706 uint32_t signBit = (offset & 0x800000) >> 23;
707 uint32_t I1Bit = (offset & 0x400000) >> 22;
708 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
709 uint32_t I2Bit = (offset & 0x200000) >> 21;
710 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
711 uint32_t imm10Bits = (offset & 0x1FF800) >> 11;
712 uint32_t imm11Bits = (offset & 0x000007FF);
713
714 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits);
715 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
716 (uint16_t)imm11Bits);
717 return joinHalfWords(FirstHalf, SecondHalf,
718 IsLittleEndian: Endian == llvm::endianness::little);
719 }
720 case ARM::fixup_arm_thumb_blx: {
721 if (STI->getTargetTriple().isOSBinFormatCOFF() && !IsResolved &&
722 Value != 4) {
723 // MSVC link.exe and lld do not support this relocation type
724 // with a non-zero offset. ("Value" is offset by 4 at this point.)
725 Ctx.reportError(L: Fixup.getLoc(),
726 Msg: "cannot perform a PC-relative fixup with a non-zero "
727 "symbol offset");
728 }
729 // The value doesn't encode the low two bits (always zero) and is offset by
730 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as
731 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00)
732 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
733 // The value is encoded into disjoint bit positions in the destination
734 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
735 // J = either J1 or J2 bit, 0 = zero.
736 //
737 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0
738 //
739 // Note that the halfwords are stored high first, low second; so we need
740 // to transpose the fixup value here to map properly.
741 if (Value % 4 != 0) {
742 Ctx.reportError(L: Fixup.getLoc(), Msg: "misaligned ARM call destination");
743 return 0;
744 }
745
746 uint32_t offset = (Value - 4) >> 2;
747 if (const MCSymbolRefExpr *SRE =
748 dyn_cast<MCSymbolRefExpr>(Val: Fixup.getValue()))
749 if (SRE->getSpecifier() == ARM::S_TLSCALL)
750 offset = 0;
751 uint32_t signBit = (offset & 0x400000) >> 22;
752 uint32_t I1Bit = (offset & 0x200000) >> 21;
753 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
754 uint32_t I2Bit = (offset & 0x100000) >> 20;
755 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
756 uint32_t imm10HBits = (offset & 0xFFC00) >> 10;
757 uint32_t imm10LBits = (offset & 0x3FF);
758
759 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits);
760 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
761 ((uint16_t)imm10LBits) << 1);
762 return joinHalfWords(FirstHalf, SecondHalf,
763 IsLittleEndian: Endian == llvm::endianness::little);
764 }
765 case ARM::fixup_thumb_adr_pcrel_10:
766 case ARM::fixup_arm_thumb_cp:
767 // On CPUs supporting Thumb2, this will be relaxed to an ldr.w, otherwise we
768 // could have an error on our hands.
769 assert(STI != nullptr);
770 if (!STI->hasFeature(Feature: ARM::FeatureThumb2) && IsResolved) {
771 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
772 if (FixupDiagnostic) {
773 Ctx.reportError(L: Fixup.getLoc(), Msg: FixupDiagnostic);
774 return 0;
775 }
776 }
777 // Offset by 4, and don't encode the low two bits.
778 return ((Value - 4) >> 2) & 0xff;
779 case ARM::fixup_arm_thumb_cb: {
780 // CB instructions can only branch to offsets in [4, 126] in multiples of 2
781 // so ensure that the raw value LSB is zero and it lies in [2, 130].
782 // An offset of 2 will be relaxed to a NOP.
783 if ((int64_t)Value < 2 || Value > 0x82 || Value & 1) {
784 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range pc-relative fixup value");
785 return 0;
786 }
787 // Offset by 4 and don't encode the lower bit, which is always 0.
788 // FIXME: diagnose if no Thumb2
789 uint32_t Binary = (Value - 4) >> 1;
790 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
791 }
792 case ARM::fixup_arm_thumb_br:
793 // Offset by 4 and don't encode the lower bit, which is always 0.
794 assert(STI != nullptr);
795 if (!STI->hasFeature(Feature: ARM::FeatureThumb2) &&
796 !STI->hasFeature(Feature: ARM::HasV8MBaselineOps)) {
797 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
798 if (FixupDiagnostic) {
799 Ctx.reportError(L: Fixup.getLoc(), Msg: FixupDiagnostic);
800 return 0;
801 }
802 }
803 return ((Value - 4) >> 1) & 0x7ff;
804 case ARM::fixup_arm_thumb_bcc:
805 // Offset by 4 and don't encode the lower bit, which is always 0.
806 assert(STI != nullptr);
807 if (!STI->hasFeature(Feature: ARM::FeatureThumb2)) {
808 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
809 if (FixupDiagnostic) {
810 Ctx.reportError(L: Fixup.getLoc(), Msg: FixupDiagnostic);
811 return 0;
812 }
813 }
814 return ((Value - 4) >> 1) & 0xff;
815 case ARM::fixup_arm_pcrel_10_unscaled: {
816 Value = Value - 8; // ARM fixups offset by an additional word and don't
817 // need to adjust for the half-word ordering.
818 bool isAdd = true;
819 if ((int64_t)Value < 0) {
820 Value = -Value;
821 isAdd = false;
822 }
823 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].
824 if (Value >= 256) {
825 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range pc-relative fixup value");
826 return 0;
827 }
828 Value = (Value & 0xf) | ((Value & 0xf0) << 4);
829 return Value | (isAdd << 23);
830 }
831 case ARM::fixup_arm_pcrel_10:
832 Value = Value - 4; // ARM fixups offset by an additional word and don't
833 // need to adjust for the half-word ordering.
834 [[fallthrough]];
835 case ARM::fixup_t2_pcrel_10: {
836 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
837 Value = Value - 4;
838 bool isAdd = true;
839 if ((int64_t)Value < 0) {
840 Value = -Value;
841 isAdd = false;
842 }
843 // These values don't encode the low two bits since they're always zero.
844 Value >>= 2;
845 if (Value >= 256) {
846 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range pc-relative fixup value");
847 return 0;
848 }
849 Value |= isAdd << 23;
850
851 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
852 // swapped.
853 if (Kind == ARM::fixup_t2_pcrel_10)
854 return swapHalfWords(Value, IsLittleEndian: Endian == llvm::endianness::little);
855
856 return Value;
857 }
858 case ARM::fixup_arm_pcrel_9:
859 Value = Value - 4; // ARM fixups offset by an additional word and don't
860 // need to adjust for the half-word ordering.
861 [[fallthrough]];
862 case ARM::fixup_t2_pcrel_9: {
863 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
864 Value = Value - 4;
865 bool isAdd = true;
866 if ((int64_t)Value < 0) {
867 Value = -Value;
868 isAdd = false;
869 }
870 // These values don't encode the low bit since it's always zero.
871 if (Value & 1) {
872 Ctx.reportError(L: Fixup.getLoc(), Msg: "invalid value for this fixup");
873 return 0;
874 }
875 Value >>= 1;
876 if (Value >= 256) {
877 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range pc-relative fixup value");
878 return 0;
879 }
880 Value |= isAdd << 23;
881
882 // Same addressing mode as fixup_arm_pcrel_9, but with 16-bit halfwords
883 // swapped.
884 if (Kind == ARM::fixup_t2_pcrel_9)
885 return swapHalfWords(Value, IsLittleEndian: Endian == llvm::endianness::little);
886
887 return Value;
888 }
889 case ARM::fixup_arm_mod_imm:
890 Value = ARM_AM::getSOImmVal(Arg: Value);
891 if (Value >> 12) {
892 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range immediate fixup value");
893 return 0;
894 }
895 return Value;
896 case ARM::fixup_t2_so_imm: {
897 Value = ARM_AM::getT2SOImmVal(Arg: Value);
898 if ((int64_t)Value < 0) {
899 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range immediate fixup value");
900 return 0;
901 }
902 // Value will contain a 12-bit value broken up into a 4-bit shift in bits
903 // 11:8 and the 8-bit immediate in 0:7. The instruction has the immediate
904 // in 0:7. The 4-bit shift is split up into i:imm3 where i is placed at bit
905 // 10 of the upper half-word and imm3 is placed at 14:12 of the lower
906 // half-word.
907 uint64_t EncValue = 0;
908 EncValue |= (Value & 0x800) << 15;
909 EncValue |= (Value & 0x700) << 4;
910 EncValue |= (Value & 0xff);
911 return swapHalfWords(Value: EncValue, IsLittleEndian: Endian == llvm::endianness::little);
912 }
913 case ARM::fixup_bf_branch: {
914 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
915 if (FixupDiagnostic) {
916 Ctx.reportError(L: Fixup.getLoc(), Msg: FixupDiagnostic);
917 return 0;
918 }
919 uint32_t out = (((Value - 4) >> 1) & 0xf) << 23;
920 return swapHalfWords(Value: out, IsLittleEndian: Endian == llvm::endianness::little);
921 }
922 case ARM::fixup_bf_target:
923 case ARM::fixup_bfl_target:
924 case ARM::fixup_bfc_target: {
925 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
926 if (FixupDiagnostic) {
927 Ctx.reportError(L: Fixup.getLoc(), Msg: FixupDiagnostic);
928 return 0;
929 }
930 uint32_t out = 0;
931 uint32_t HighBitMask = (Kind == ARM::fixup_bf_target ? 0xf800 :
932 Kind == ARM::fixup_bfl_target ? 0x3f800 : 0x800);
933 out |= (((Value - 4) >> 1) & 0x1) << 11;
934 out |= (((Value - 4) >> 1) & 0x7fe);
935 out |= (((Value - 4) >> 1) & HighBitMask) << 5;
936 return swapHalfWords(Value: out, IsLittleEndian: Endian == llvm::endianness::little);
937 }
938 case ARM::fixup_bfcsel_else_target: {
939 // If this is a fixup of a branch future's else target then it should be a
940 // constant MCExpr representing the distance between the branch targetted
941 // and the instruction after that same branch.
942 Value = Target.getConstant();
943
944 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
945 if (FixupDiagnostic) {
946 Ctx.reportError(L: Fixup.getLoc(), Msg: FixupDiagnostic);
947 return 0;
948 }
949 uint32_t out = ((Value >> 2) & 1) << 17;
950 return swapHalfWords(Value: out, IsLittleEndian: Endian == llvm::endianness::little);
951 }
952 case ARM::fixup_wls:
953 case ARM::fixup_le: {
954 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
955 if (FixupDiagnostic) {
956 Ctx.reportError(L: Fixup.getLoc(), Msg: FixupDiagnostic);
957 return 0;
958 }
959 uint64_t real_value = Value - 4;
960 uint32_t out = 0;
961 if (Kind == ARM::fixup_le)
962 real_value = -real_value;
963 out |= ((real_value >> 1) & 0x1) << 11;
964 out |= ((real_value >> 1) & 0x7fe);
965 return swapHalfWords(Value: out, IsLittleEndian: Endian == llvm::endianness::little);
966 }
967 }
968}
969
970bool ARMAsmBackend::shouldForceRelocation(const MCFixup &Fixup,
971 const MCValue &Target) {
972 const MCSymbol *Sym = Target.getAddSym();
973 const unsigned FixupKind = Fixup.getKind();
974 if (FixupKind == ARM::fixup_arm_thumb_bl) {
975 assert(Sym && "How did we resolve this?");
976
977 // If the symbol is external the linker will handle it.
978 // FIXME: Should we handle it as an optimization?
979
980 // If the symbol is out of range, produce a relocation and hope the
981 // linker can handle it. GNU AS produces an error in this case.
982 if (Sym->isExternal())
983 return true;
984 }
985 // Create relocations for unconditional branches to function symbols with
986 // different execution mode in ELF binaries.
987 if (needsInterworking(Asm: *Asm, Sym, FixupKind: Fixup.getTargetKind()))
988 return true;
989 // We must always generate a relocation for BL/BLX instructions if we have
990 // a symbol to reference, as the linker relies on knowing the destination
991 // symbol's thumb-ness to get interworking right.
992 if (Sym && (FixupKind == ARM::fixup_arm_thumb_blx ||
993 FixupKind == ARM::fixup_arm_blx ||
994 FixupKind == ARM::fixup_arm_uncondbl ||
995 FixupKind == ARM::fixup_arm_condbl))
996 return true;
997 return Target.getSpecifier();
998}
999
1000/// getFixupKindNumBytes - The number of bytes the fixup may change.
1001static unsigned getFixupKindNumBytes(unsigned Kind) {
1002 switch (Kind) {
1003 default:
1004 llvm_unreachable("Unknown fixup kind!");
1005
1006 case FK_Data_1:
1007 case ARM::fixup_arm_thumb_bcc:
1008 case ARM::fixup_arm_thumb_cp:
1009 case ARM::fixup_thumb_adr_pcrel_10:
1010 case ARM::fixup_arm_thumb_upper_8_15:
1011 case ARM::fixup_arm_thumb_upper_0_7:
1012 case ARM::fixup_arm_thumb_lower_8_15:
1013 case ARM::fixup_arm_thumb_lower_0_7:
1014 return 1;
1015
1016 case FK_Data_2:
1017 case ARM::fixup_arm_thumb_br:
1018 case ARM::fixup_arm_thumb_cb:
1019 case ARM::fixup_arm_mod_imm:
1020 return 2;
1021
1022 case ARM::fixup_arm_pcrel_10_unscaled:
1023 case ARM::fixup_arm_ldst_pcrel_12:
1024 case ARM::fixup_arm_pcrel_10:
1025 case ARM::fixup_arm_pcrel_9:
1026 case ARM::fixup_arm_ldst_abs_12:
1027 case ARM::fixup_arm_adr_pcrel_12:
1028 case ARM::fixup_arm_uncondbl:
1029 case ARM::fixup_arm_condbl:
1030 case ARM::fixup_arm_blx:
1031 case ARM::fixup_arm_condbranch:
1032 case ARM::fixup_arm_uncondbranch:
1033 return 3;
1034
1035 case FK_Data_4:
1036 case ARM::fixup_t2_ldst_pcrel_12:
1037 case ARM::fixup_t2_condbranch:
1038 case ARM::fixup_t2_uncondbranch:
1039 case ARM::fixup_t2_pcrel_10:
1040 case ARM::fixup_t2_pcrel_9:
1041 case ARM::fixup_t2_adr_pcrel_12:
1042 case ARM::fixup_arm_thumb_bl:
1043 case ARM::fixup_arm_thumb_blx:
1044 case ARM::fixup_arm_movt_hi16:
1045 case ARM::fixup_arm_movw_lo16:
1046 case ARM::fixup_t2_movt_hi16:
1047 case ARM::fixup_t2_movw_lo16:
1048 case ARM::fixup_t2_so_imm:
1049 case ARM::fixup_bf_branch:
1050 case ARM::fixup_bf_target:
1051 case ARM::fixup_bfl_target:
1052 case ARM::fixup_bfc_target:
1053 case ARM::fixup_bfcsel_else_target:
1054 case ARM::fixup_wls:
1055 case ARM::fixup_le:
1056 return 4;
1057
1058 case FK_SecRel_2:
1059 return 2;
1060 case FK_SecRel_4:
1061 return 4;
1062 }
1063}
1064
1065/// getFixupKindContainerSizeBytes - The number of bytes of the
1066/// container involved in big endian.
1067static unsigned getFixupKindContainerSizeBytes(unsigned Kind) {
1068 switch (Kind) {
1069 default:
1070 llvm_unreachable("Unknown fixup kind!");
1071
1072 case FK_Data_1:
1073 return 1;
1074 case FK_Data_2:
1075 return 2;
1076 case FK_Data_4:
1077 return 4;
1078
1079 case ARM::fixup_arm_thumb_bcc:
1080 case ARM::fixup_arm_thumb_cp:
1081 case ARM::fixup_thumb_adr_pcrel_10:
1082 case ARM::fixup_arm_thumb_br:
1083 case ARM::fixup_arm_thumb_cb:
1084 case ARM::fixup_arm_thumb_upper_8_15:
1085 case ARM::fixup_arm_thumb_upper_0_7:
1086 case ARM::fixup_arm_thumb_lower_8_15:
1087 case ARM::fixup_arm_thumb_lower_0_7:
1088 // Instruction size is 2 bytes.
1089 return 2;
1090
1091 case ARM::fixup_arm_pcrel_10_unscaled:
1092 case ARM::fixup_arm_ldst_pcrel_12:
1093 case ARM::fixup_arm_pcrel_10:
1094 case ARM::fixup_arm_pcrel_9:
1095 case ARM::fixup_arm_adr_pcrel_12:
1096 case ARM::fixup_arm_uncondbl:
1097 case ARM::fixup_arm_condbl:
1098 case ARM::fixup_arm_blx:
1099 case ARM::fixup_arm_condbranch:
1100 case ARM::fixup_arm_uncondbranch:
1101 case ARM::fixup_t2_ldst_pcrel_12:
1102 case ARM::fixup_t2_condbranch:
1103 case ARM::fixup_t2_uncondbranch:
1104 case ARM::fixup_t2_pcrel_10:
1105 case ARM::fixup_t2_pcrel_9:
1106 case ARM::fixup_t2_adr_pcrel_12:
1107 case ARM::fixup_arm_thumb_bl:
1108 case ARM::fixup_arm_thumb_blx:
1109 case ARM::fixup_arm_movt_hi16:
1110 case ARM::fixup_arm_movw_lo16:
1111 case ARM::fixup_t2_movt_hi16:
1112 case ARM::fixup_t2_movw_lo16:
1113 case ARM::fixup_arm_mod_imm:
1114 case ARM::fixup_t2_so_imm:
1115 case ARM::fixup_bf_branch:
1116 case ARM::fixup_bf_target:
1117 case ARM::fixup_bfl_target:
1118 case ARM::fixup_bfc_target:
1119 case ARM::fixup_bfcsel_else_target:
1120 case ARM::fixup_wls:
1121 case ARM::fixup_le:
1122 // Instruction size is 4 bytes.
1123 return 4;
1124 }
1125}
1126
1127void ARMAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
1128 const MCValue &Target,
1129 MutableArrayRef<char> Data, uint64_t Value,
1130 bool IsResolved) {
1131 if (IsResolved && shouldForceRelocation(Fixup, Target))
1132 IsResolved = false;
1133 maybeAddReloc(F, Fixup, Target, Value, IsResolved);
1134 auto Kind = Fixup.getKind();
1135 if (mc::isRelocation(FixupKind: Kind))
1136 return;
1137 MCContext &Ctx = getContext();
1138 Value = adjustFixupValue(Asm: *Asm, Fixup, Target, Value, IsResolved, Ctx,
1139 STI: getSubtargetInfo(F));
1140 if (!Value)
1141 return; // Doesn't change encoding.
1142 const unsigned NumBytes = getFixupKindNumBytes(Kind);
1143
1144 unsigned Offset = Fixup.getOffset();
1145 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
1146
1147 // Used to point to big endian bytes.
1148 unsigned FullSizeBytes;
1149 if (Endian == llvm::endianness::big) {
1150 FullSizeBytes = getFixupKindContainerSizeBytes(Kind);
1151 assert((Offset + FullSizeBytes) <= Data.size() && "Invalid fixup size!");
1152 assert(NumBytes <= FullSizeBytes && "Invalid fixup size!");
1153 }
1154
1155 // For each byte of the fragment that the fixup touches, mask in the bits from
1156 // the fixup value. The Value has been "split up" into the appropriate
1157 // bitfields above.
1158 for (unsigned i = 0; i != NumBytes; ++i) {
1159 unsigned Idx =
1160 Endian == llvm::endianness::little ? i : (FullSizeBytes - 1 - i);
1161 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
1162 }
1163}
1164
1165namespace CU {
1166
1167/// Compact unwind encoding values.
1168enum CompactUnwindEncodings {
1169 UNWIND_ARM_MODE_MASK = 0x0F000000,
1170 UNWIND_ARM_MODE_FRAME = 0x01000000,
1171 UNWIND_ARM_MODE_FRAME_D = 0x02000000,
1172 UNWIND_ARM_MODE_DWARF = 0x04000000,
1173
1174 UNWIND_ARM_FRAME_STACK_ADJUST_MASK = 0x00C00000,
1175
1176 UNWIND_ARM_FRAME_FIRST_PUSH_R4 = 0x00000001,
1177 UNWIND_ARM_FRAME_FIRST_PUSH_R5 = 0x00000002,
1178 UNWIND_ARM_FRAME_FIRST_PUSH_R6 = 0x00000004,
1179
1180 UNWIND_ARM_FRAME_SECOND_PUSH_R8 = 0x00000008,
1181 UNWIND_ARM_FRAME_SECOND_PUSH_R9 = 0x00000010,
1182 UNWIND_ARM_FRAME_SECOND_PUSH_R10 = 0x00000020,
1183 UNWIND_ARM_FRAME_SECOND_PUSH_R11 = 0x00000040,
1184 UNWIND_ARM_FRAME_SECOND_PUSH_R12 = 0x00000080,
1185
1186 UNWIND_ARM_FRAME_D_REG_COUNT_MASK = 0x00000F00,
1187
1188 UNWIND_ARM_DWARF_SECTION_OFFSET = 0x00FFFFFF
1189};
1190
1191} // end CU namespace
1192
1193/// Generate compact unwind encoding for the function based on the CFI
1194/// instructions. If the CFI instructions describe a frame that cannot be
1195/// encoded in compact unwind, the method returns UNWIND_ARM_MODE_DWARF which
1196/// tells the runtime to fallback and unwind using dwarf.
1197uint64_t ARMAsmBackendDarwin::generateCompactUnwindEncoding(
1198 const MCDwarfFrameInfo *FI, const MCContext *Ctxt) const {
1199 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "generateCU()\n");
1200 // Only armv7k uses CFI based unwinding.
1201 if (Subtype != MachO::CPU_SUBTYPE_ARM_V7K)
1202 return 0;
1203 // No .cfi directives means no frame.
1204 ArrayRef<MCCFIInstruction> Instrs = FI->Instructions;
1205 if (Instrs.empty())
1206 return 0;
1207 if (!isDarwinCanonicalPersonality(Sym: FI->Personality) &&
1208 !Ctxt->emitCompactUnwindNonCanonical())
1209 return CU::UNWIND_ARM_MODE_DWARF;
1210
1211 // Start off assuming CFA is at SP+0.
1212 MCRegister CFARegister = ARM::SP;
1213 int CFARegisterOffset = 0;
1214 // Mark savable registers as initially unsaved
1215 DenseMap<MCRegister, int> RegOffsets;
1216 int FloatRegCount = 0;
1217 // Process each .cfi directive and build up compact unwind info.
1218 for (const MCCFIInstruction &Inst : Instrs) {
1219 MCRegister Reg;
1220 switch (Inst.getOperation()) {
1221 case MCCFIInstruction::OpDefCfa: // DW_CFA_def_cfa
1222 CFARegisterOffset = Inst.getOffset();
1223 CFARegister = *MRI.getLLVMRegNum(RegNum: Inst.getRegister(), isEH: true);
1224 break;
1225 case MCCFIInstruction::OpDefCfaOffset: // DW_CFA_def_cfa_offset
1226 CFARegisterOffset = Inst.getOffset();
1227 break;
1228 case MCCFIInstruction::OpDefCfaRegister: // DW_CFA_def_cfa_register
1229 CFARegister = *MRI.getLLVMRegNum(RegNum: Inst.getRegister(), isEH: true);
1230 break;
1231 case MCCFIInstruction::OpOffset: // DW_CFA_offset
1232 Reg = *MRI.getLLVMRegNum(RegNum: Inst.getRegister(), isEH: true);
1233 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
1234 RegOffsets[Reg] = Inst.getOffset();
1235 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
1236 RegOffsets[Reg] = Inst.getOffset();
1237 ++FloatRegCount;
1238 } else {
1239 DEBUG_WITH_TYPE("compact-unwind",
1240 llvm::dbgs() << ".cfi_offset on unknown register="
1241 << Inst.getRegister() << "\n");
1242 return CU::UNWIND_ARM_MODE_DWARF;
1243 }
1244 break;
1245 case MCCFIInstruction::OpRelOffset: // DW_CFA_advance_loc
1246 // Ignore
1247 break;
1248 default:
1249 // Directive not convertable to compact unwind, bail out.
1250 DEBUG_WITH_TYPE("compact-unwind",
1251 llvm::dbgs()
1252 << "CFI directive not compatible with compact "
1253 "unwind encoding, opcode="
1254 << uint8_t(Inst.getOperation()) << "\n");
1255 return CU::UNWIND_ARM_MODE_DWARF;
1256 break;
1257 }
1258 }
1259
1260 // If no frame set up, return no unwind info.
1261 if ((CFARegister == ARM::SP) && (CFARegisterOffset == 0))
1262 return 0;
1263
1264 // Verify standard frame (lr/r7) was used.
1265 if (CFARegister != ARM::R7) {
1266 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "frame register is "
1267 << CFARegister
1268 << " instead of r7\n");
1269 return CU::UNWIND_ARM_MODE_DWARF;
1270 }
1271 int StackAdjust = CFARegisterOffset - 8;
1272 if (RegOffsets.lookup(Val: ARM::LR) != (-4 - StackAdjust)) {
1273 DEBUG_WITH_TYPE(
1274 "compact-unwind",
1275 llvm::dbgs() << "LR not saved as standard frame, StackAdjust="
1276 << StackAdjust
1277 << ", CFARegisterOffset=" << CFARegisterOffset
1278 << ", lr save at offset=" << RegOffsets[ARM::LR] << "\n");
1279 return CU::UNWIND_ARM_MODE_DWARF;
1280 }
1281 if (RegOffsets.lookup(Val: ARM::R7) != (-8 - StackAdjust)) {
1282 DEBUG_WITH_TYPE("compact-unwind",
1283 llvm::dbgs() << "r7 not saved as standard frame\n");
1284 return CU::UNWIND_ARM_MODE_DWARF;
1285 }
1286 uint32_t CompactUnwindEncoding = CU::UNWIND_ARM_MODE_FRAME;
1287
1288 // If var-args are used, there may be a stack adjust required.
1289 switch (StackAdjust) {
1290 case 0:
1291 break;
1292 case 4:
1293 CompactUnwindEncoding |= 0x00400000;
1294 break;
1295 case 8:
1296 CompactUnwindEncoding |= 0x00800000;
1297 break;
1298 case 12:
1299 CompactUnwindEncoding |= 0x00C00000;
1300 break;
1301 default:
1302 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs()
1303 << ".cfi_def_cfa stack adjust ("
1304 << StackAdjust << ") out of range\n");
1305 return CU::UNWIND_ARM_MODE_DWARF;
1306 }
1307
1308 // If r6 is saved, it must be right below r7.
1309 static struct {
1310 unsigned Reg;
1311 unsigned Encoding;
1312 } GPRCSRegs[] = {{.Reg: ARM::R6, .Encoding: CU::UNWIND_ARM_FRAME_FIRST_PUSH_R6},
1313 {.Reg: ARM::R5, .Encoding: CU::UNWIND_ARM_FRAME_FIRST_PUSH_R5},
1314 {.Reg: ARM::R4, .Encoding: CU::UNWIND_ARM_FRAME_FIRST_PUSH_R4},
1315 {.Reg: ARM::R12, .Encoding: CU::UNWIND_ARM_FRAME_SECOND_PUSH_R12},
1316 {.Reg: ARM::R11, .Encoding: CU::UNWIND_ARM_FRAME_SECOND_PUSH_R11},
1317 {.Reg: ARM::R10, .Encoding: CU::UNWIND_ARM_FRAME_SECOND_PUSH_R10},
1318 {.Reg: ARM::R9, .Encoding: CU::UNWIND_ARM_FRAME_SECOND_PUSH_R9},
1319 {.Reg: ARM::R8, .Encoding: CU::UNWIND_ARM_FRAME_SECOND_PUSH_R8}};
1320
1321 int CurOffset = -8 - StackAdjust;
1322 for (auto CSReg : GPRCSRegs) {
1323 auto Offset = RegOffsets.find(Val: CSReg.Reg);
1324 if (Offset == RegOffsets.end())
1325 continue;
1326
1327 int RegOffset = Offset->second;
1328 if (RegOffset != CurOffset - 4) {
1329 DEBUG_WITH_TYPE("compact-unwind",
1330 llvm::dbgs() << MRI.getName(CSReg.Reg) << " saved at "
1331 << RegOffset << " but only supported at "
1332 << CurOffset << "\n");
1333 return CU::UNWIND_ARM_MODE_DWARF;
1334 }
1335 CompactUnwindEncoding |= CSReg.Encoding;
1336 CurOffset -= 4;
1337 }
1338
1339 // If no floats saved, we are done.
1340 if (FloatRegCount == 0)
1341 return CompactUnwindEncoding;
1342
1343 // Switch mode to include D register saving.
1344 CompactUnwindEncoding &= ~CU::UNWIND_ARM_MODE_MASK;
1345 CompactUnwindEncoding |= CU::UNWIND_ARM_MODE_FRAME_D;
1346
1347 // FIXME: supporting more than 4 saved D-registers compactly would be trivial,
1348 // but needs coordination with the linker and libunwind.
1349 if (FloatRegCount > 4) {
1350 DEBUG_WITH_TYPE("compact-unwind",
1351 llvm::dbgs() << "unsupported number of D registers saved ("
1352 << FloatRegCount << ")\n");
1353 return CU::UNWIND_ARM_MODE_DWARF;
1354 }
1355
1356 // Floating point registers must either be saved sequentially, or we defer to
1357 // DWARF. No gaps allowed here so check that each saved d-register is
1358 // precisely where it should be.
1359 static MCPhysReg FPRCSRegs[] = {ARM::D8, ARM::D10, ARM::D12, ARM::D14};
1360 for (int Idx = FloatRegCount - 1; Idx >= 0; --Idx) {
1361 auto Offset = RegOffsets.find(Val: FPRCSRegs[Idx]);
1362 if (Offset == RegOffsets.end()) {
1363 DEBUG_WITH_TYPE("compact-unwind",
1364 llvm::dbgs() << FloatRegCount << " D-regs saved, but "
1365 << MRI.getName(FPRCSRegs[Idx])
1366 << " not saved\n");
1367 return CU::UNWIND_ARM_MODE_DWARF;
1368 } else if (Offset->second != CurOffset - 8) {
1369 DEBUG_WITH_TYPE("compact-unwind",
1370 llvm::dbgs() << FloatRegCount << " D-regs saved, but "
1371 << MRI.getName(FPRCSRegs[Idx])
1372 << " saved at " << Offset->second
1373 << ", expected at " << CurOffset - 8
1374 << "\n");
1375 return CU::UNWIND_ARM_MODE_DWARF;
1376 }
1377 CurOffset -= 8;
1378 }
1379
1380 return CompactUnwindEncoding | ((FloatRegCount - 1) << 8);
1381}
1382
1383static MCAsmBackend *createARMAsmBackend(const Target &T,
1384 const MCSubtargetInfo &STI,
1385 const MCRegisterInfo &MRI,
1386 const MCTargetOptions &Options,
1387 llvm::endianness Endian) {
1388 const Triple &TheTriple = STI.getTargetTriple();
1389 switch (TheTriple.getObjectFormat()) {
1390 default:
1391 llvm_unreachable("unsupported object format");
1392 case Triple::MachO:
1393 return new ARMAsmBackendDarwin(T, STI, MRI);
1394 case Triple::COFF:
1395 assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
1396 return new ARMAsmBackendWinCOFF(T);
1397 case Triple::ELF:
1398 assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target");
1399 uint8_t OSABI = Options.FDPIC
1400 ? static_cast<uint8_t>(ELF::ELFOSABI_ARM_FDPIC)
1401 : MCELFObjectTargetWriter::getOSABI(OSType: TheTriple.getOS());
1402 return new ARMAsmBackendELF(T, OSABI, Endian);
1403 }
1404}
1405
1406MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
1407 const MCSubtargetInfo &STI,
1408 const MCRegisterInfo &MRI,
1409 const MCTargetOptions &Options) {
1410 return createARMAsmBackend(T, STI, MRI, Options, Endian: llvm::endianness::little);
1411}
1412
1413MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
1414 const MCSubtargetInfo &STI,
1415 const MCRegisterInfo &MRI,
1416 const MCTargetOptions &Options) {
1417 return createARMAsmBackend(T, STI, MRI, Options, Endian: llvm::endianness::big);
1418}
1419