1//===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "MCTargetDesc/HexagonBaseInfo.h"
10#include "MCTargetDesc/HexagonMCChecker.h"
11#include "MCTargetDesc/HexagonMCInstrInfo.h"
12#include "MCTargetDesc/HexagonMCTargetDesc.h"
13#include "TargetInfo/HexagonTargetInfo.h"
14#include "llvm/ADT/ArrayRef.h"
15#include "llvm/MC/MCContext.h"
16#include "llvm/MC/MCDecoderOps.h"
17#include "llvm/MC/MCDisassembler/MCDisassembler.h"
18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/MC/TargetRegistry.h"
24#include "llvm/Support/Compiler.h"
25#include "llvm/Support/Endian.h"
26#include "llvm/Support/MathExtras.h"
27#include "llvm/Support/raw_ostream.h"
28#include <cassert>
29#include <cstddef>
30#include <cstdint>
31#include <memory>
32
33#define DEBUG_TYPE "hexagon-disassembler"
34
35using namespace llvm;
36using namespace Hexagon;
37
38using DecodeStatus = MCDisassembler::DecodeStatus;
39
40namespace {
41
42/// Hexagon disassembler for all Hexagon platforms.
43class HexagonDisassembler : public MCDisassembler {
44public:
45 std::unique_ptr<MCInstrInfo const> const MCII;
46 std::unique_ptr<MCInst *> CurrentBundle;
47 mutable MCInst const *CurrentExtender;
48
49 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
50 MCInstrInfo const *MCII)
51 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *),
52 CurrentExtender(nullptr) {}
53
54 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
55 ArrayRef<uint8_t> Bytes, uint64_t Address,
56 raw_ostream &CStream, bool &Complete) const;
57 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
58 ArrayRef<uint8_t> Bytes, uint64_t Address,
59 raw_ostream &CStream) const override;
60 void remapInstruction(MCInst &Instr) const;
61};
62
63static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI,
64 int64_t Value) {
65 MCInstrInfo MCII = *Disassembler.MCII;
66 if (!Disassembler.CurrentExtender ||
67 MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MCI: MI))
68 return Value;
69 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MCI: MI);
70 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f;
71 int64_t Bits;
72 bool Success =
73 Disassembler.CurrentExtender->getOperand(i: 0).getExpr()->evaluateAsAbsolute(
74 Res&: Bits);
75 assert(Success);
76 (void)Success;
77 uint64_t Upper26 = static_cast<uint64_t>(Bits);
78 uint64_t Operand = Upper26 | Lower6;
79 return Operand;
80}
81static HexagonDisassembler const &disassembler(const MCDisassembler *Decoder) {
82 return *static_cast<HexagonDisassembler const *>(Decoder);
83}
84template <size_t T>
85static void signedDecoder(MCInst &MI, unsigned tmp,
86 const MCDisassembler *Decoder) {
87 HexagonDisassembler const &Disassembler = disassembler(Decoder);
88 int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp));
89 int64_t Extended = SignExtend64<32>(x: FullValue);
90 HexagonMCInstrInfo::addConstant(MI, Value: Extended, Context&: Disassembler.getContext());
91}
92}
93
94// Forward declare these because the auto-generated code will reference them.
95// Definitions are further down.
96
97static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
98 uint64_t Address,
99 const MCDisassembler *Decoder);
100static DecodeStatus
101DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo,
102 uint64_t Address,
103 const MCDisassembler *Decoder);
104static DecodeStatus
105DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
106 const MCDisassembler *Decoder);
107static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
108 uint64_t Address,
109 const MCDisassembler *Decoder);
110static DecodeStatus
111DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
112 const MCDisassembler *Decoder);
113static DecodeStatus
114DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
115 uint64_t Address,
116 const MCDisassembler *Decoder);
117static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
118 uint64_t Address,
119 const MCDisassembler *Decoder);
120static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo,
121 uint64_t Address,
122 const MCDisassembler *Decoder);
123static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
124 uint64_t Address,
125 const MCDisassembler *Decoder);
126static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
127 uint64_t Address,
128 const MCDisassembler *Decoder);
129static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
130 uint64_t Address,
131 const MCDisassembler *Decoder);
132static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
133 uint64_t Address,
134 const MCDisassembler *Decoder);
135static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
136 uint64_t Address,
137 const MCDisassembler *Decoder);
138static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
139 uint64_t Address,
140 const MCDisassembler *Decoder);
141static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
142 uint64_t Address,
143 const MCDisassembler *Decoder);
144static DecodeStatus
145DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
146 const MCDisassembler *Decoder);
147static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
148 uint64_t Address,
149 const MCDisassembler *Decoder);
150
151static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
152 uint64_t Address,
153 const MCDisassembler *Decoder);
154static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
155 uint64_t /*Address*/,
156 const MCDisassembler *Decoder);
157static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
158 const MCDisassembler *Decoder);
159#include "HexagonDepDecoders.inc"
160#include "HexagonGenDisassemblerTables.inc"
161
162static MCDisassembler *createHexagonDisassembler(const Target &T,
163 const MCSubtargetInfo &STI,
164 MCContext &Ctx) {
165 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo());
166}
167
168extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
169LLVMInitializeHexagonDisassembler() {
170 TargetRegistry::RegisterMCDisassembler(T&: getTheHexagonTarget(),
171 Fn: createHexagonDisassembler);
172}
173
174DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
175 ArrayRef<uint8_t> Bytes,
176 uint64_t Address,
177 raw_ostream &CS) const {
178 CommentStream = &CS;
179
180 DecodeStatus Result = DecodeStatus::Success;
181 bool Complete = false;
182 Size = 0;
183
184 *CurrentBundle = &MI;
185 MI.setOpcode(Hexagon::BUNDLE);
186 MI.addOperand(Op: MCOperand::createImm(Val: 0));
187 while (Result == Success && !Complete) {
188 if (Bytes.size() < HEXAGON_INSTR_SIZE)
189 return MCDisassembler::Fail;
190 MCInst *Inst = getContext().createMCInst();
191 Result = getSingleInstruction(Instr&: *Inst, MCB&: MI, Bytes, Address, CStream&: CS, Complete);
192 MI.addOperand(Op: MCOperand::createInst(Val: Inst));
193 Size += HEXAGON_INSTR_SIZE;
194 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE);
195 }
196 if (Result == MCDisassembler::Fail)
197 return Result;
198 if (Size > HEXAGON_MAX_PACKET_SIZE)
199 return MCDisassembler::Fail;
200
201 const auto ArchSTI = Hexagon_MC::getArchSubtarget(STI: &STI);
202 const auto STI_ = (ArchSTI != nullptr) ? *ArchSTI : STI;
203 HexagonMCChecker Checker(getContext(), *MCII, STI_, MI,
204 *getContext().getRegisterInfo(), false);
205 if (!Checker.check())
206 return MCDisassembler::Fail;
207 remapInstruction(Instr&: MI);
208 return MCDisassembler::Success;
209}
210
211void HexagonDisassembler::remapInstruction(MCInst &Instr) const {
212 for (auto I: HexagonMCInstrInfo::bundleInstructions(MCI: Instr)) {
213 auto &MI = const_cast<MCInst &>(*I.getInst());
214 switch (MI.getOpcode()) {
215 case Hexagon::S2_allocframe:
216 if (MI.getOperand(i: 0).getReg() == Hexagon::R29) {
217 MI.setOpcode(Hexagon::S6_allocframe_to_raw);
218 MI.erase(I: MI.begin () + 1);
219 MI.erase(I: MI.begin ());
220 }
221 break;
222 case Hexagon::L2_deallocframe:
223 if (MI.getOperand(i: 0).getReg() == Hexagon::D15 &&
224 MI.getOperand(i: 1).getReg() == Hexagon::R30) {
225 MI.setOpcode(L6_deallocframe_map_to_raw);
226 MI.erase(I: MI.begin () + 1);
227 MI.erase(I: MI.begin ());
228 }
229 break;
230 case Hexagon::L4_return:
231 if (MI.getOperand(i: 0).getReg() == Hexagon::D15 &&
232 MI.getOperand(i: 1).getReg() == Hexagon::R30) {
233 MI.setOpcode(L6_return_map_to_raw);
234 MI.erase(I: MI.begin () + 1);
235 MI.erase(I: MI.begin ());
236 }
237 break;
238 case Hexagon::L4_return_t:
239 if (MI.getOperand(i: 0).getReg() == Hexagon::D15 &&
240 MI.getOperand(i: 2).getReg() == Hexagon::R30) {
241 MI.setOpcode(L4_return_map_to_raw_t);
242 MI.erase(I: MI.begin () + 2);
243 MI.erase(I: MI.begin ());
244 }
245 break;
246 case Hexagon::L4_return_f:
247 if (MI.getOperand(i: 0).getReg() == Hexagon::D15 &&
248 MI.getOperand(i: 2).getReg() == Hexagon::R30) {
249 MI.setOpcode(L4_return_map_to_raw_f);
250 MI.erase(I: MI.begin () + 2);
251 MI.erase(I: MI.begin ());
252 }
253 break;
254 case Hexagon::L4_return_tnew_pt:
255 if (MI.getOperand(i: 0).getReg() == Hexagon::D15 &&
256 MI.getOperand(i: 2).getReg() == Hexagon::R30) {
257 MI.setOpcode(L4_return_map_to_raw_tnew_pt);
258 MI.erase(I: MI.begin () + 2);
259 MI.erase(I: MI.begin ());
260 }
261 break;
262 case Hexagon::L4_return_fnew_pt:
263 if (MI.getOperand(i: 0).getReg() == Hexagon::D15 &&
264 MI.getOperand(i: 2).getReg() == Hexagon::R30) {
265 MI.setOpcode(L4_return_map_to_raw_fnew_pt);
266 MI.erase(I: MI.begin () + 2);
267 MI.erase(I: MI.begin ());
268 }
269 break;
270 case Hexagon::L4_return_tnew_pnt:
271 if (MI.getOperand(i: 0).getReg() == Hexagon::D15 &&
272 MI.getOperand(i: 2).getReg() == Hexagon::R30) {
273 MI.setOpcode(L4_return_map_to_raw_tnew_pnt);
274 MI.erase(I: MI.begin () + 2);
275 MI.erase(I: MI.begin ());
276 }
277 break;
278 case Hexagon::L4_return_fnew_pnt:
279 if (MI.getOperand(i: 0).getReg() == Hexagon::D15 &&
280 MI.getOperand(i: 2).getReg() == Hexagon::R30) {
281 MI.setOpcode(L4_return_map_to_raw_fnew_pnt);
282 MI.erase(I: MI.begin () + 2);
283 MI.erase(I: MI.begin ());
284 }
285 break;
286 }
287 }
288}
289
290static void adjustDuplex(MCInst &MI, MCContext &Context) {
291 switch (MI.getOpcode()) {
292 case Hexagon::SA1_setin1:
293 MI.insert(I: MI.begin() + 1,
294 Op: MCOperand::createExpr(Val: MCConstantExpr::create(Value: -1, Ctx&: Context)));
295 break;
296 case Hexagon::SA1_dec:
297 MI.insert(I: MI.begin() + 2,
298 Op: MCOperand::createExpr(Val: MCConstantExpr::create(Value: -1, Ctx&: Context)));
299 break;
300 default:
301 break;
302 }
303}
304
305DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
306 ArrayRef<uint8_t> Bytes,
307 uint64_t Address,
308 raw_ostream &cs,
309 bool &Complete) const {
310 assert(Bytes.size() >= HEXAGON_INSTR_SIZE);
311
312 uint32_t Instruction = support::endian::read32le(P: Bytes.data());
313
314 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCI: MCB);
315 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
316 HexagonII::INST_PARSE_LOOP_END) {
317 if (BundleSize == 0)
318 HexagonMCInstrInfo::setInnerLoop(MCB);
319 else if (BundleSize == 1)
320 HexagonMCInstrInfo::setOuterLoop(MCB);
321 else
322 return DecodeStatus::Fail;
323 }
324
325 CurrentExtender = HexagonMCInstrInfo::extenderForIndex(
326 MCB, Index: HexagonMCInstrInfo::bundleSize(MCI: MCB));
327
328 DecodeStatus Result = DecodeStatus::Fail;
329 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
330 HexagonII::INST_PARSE_DUPLEX) {
331 unsigned duplexIClass;
332 uint8_t const *DecodeLow, *DecodeHigh;
333 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);
334 switch (duplexIClass) {
335 default:
336 return MCDisassembler::Fail;
337 case 0:
338 DecodeLow = DecoderTableSUBINSN_L132;
339 DecodeHigh = DecoderTableSUBINSN_L132;
340 break;
341 case 1:
342 DecodeLow = DecoderTableSUBINSN_L232;
343 DecodeHigh = DecoderTableSUBINSN_L132;
344 break;
345 case 2:
346 DecodeLow = DecoderTableSUBINSN_L232;
347 DecodeHigh = DecoderTableSUBINSN_L232;
348 break;
349 case 3:
350 DecodeLow = DecoderTableSUBINSN_A32;
351 DecodeHigh = DecoderTableSUBINSN_A32;
352 break;
353 case 4:
354 DecodeLow = DecoderTableSUBINSN_L132;
355 DecodeHigh = DecoderTableSUBINSN_A32;
356 break;
357 case 5:
358 DecodeLow = DecoderTableSUBINSN_L232;
359 DecodeHigh = DecoderTableSUBINSN_A32;
360 break;
361 case 6:
362 DecodeLow = DecoderTableSUBINSN_S132;
363 DecodeHigh = DecoderTableSUBINSN_A32;
364 break;
365 case 7:
366 DecodeLow = DecoderTableSUBINSN_S232;
367 DecodeHigh = DecoderTableSUBINSN_A32;
368 break;
369 case 8:
370 DecodeLow = DecoderTableSUBINSN_S132;
371 DecodeHigh = DecoderTableSUBINSN_L132;
372 break;
373 case 9:
374 DecodeLow = DecoderTableSUBINSN_S132;
375 DecodeHigh = DecoderTableSUBINSN_L232;
376 break;
377 case 10:
378 DecodeLow = DecoderTableSUBINSN_S132;
379 DecodeHigh = DecoderTableSUBINSN_S132;
380 break;
381 case 11:
382 DecodeLow = DecoderTableSUBINSN_S232;
383 DecodeHigh = DecoderTableSUBINSN_S132;
384 break;
385 case 12:
386 DecodeLow = DecoderTableSUBINSN_S232;
387 DecodeHigh = DecoderTableSUBINSN_L132;
388 break;
389 case 13:
390 DecodeLow = DecoderTableSUBINSN_S232;
391 DecodeHigh = DecoderTableSUBINSN_L232;
392 break;
393 case 14:
394 DecodeLow = DecoderTableSUBINSN_S232;
395 DecodeHigh = DecoderTableSUBINSN_S232;
396 break;
397 }
398 MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass);
399 MCInst *MILow = getContext().createMCInst();
400 MCInst *MIHigh = getContext().createMCInst();
401 auto TmpExtender = CurrentExtender;
402 CurrentExtender =
403 nullptr; // constant extenders in duplex must always be in slot 1
404 Result = decodeInstruction(DecodeTable: DecodeLow, MI&: *MILow, insn: Instruction & 0x1fff, Address,
405 DisAsm: this, STI);
406 CurrentExtender = TmpExtender;
407 if (Result != DecodeStatus::Success)
408 return DecodeStatus::Fail;
409 adjustDuplex(MI&: *MILow, Context&: getContext());
410 Result = decodeInstruction(
411 DecodeTable: DecodeHigh, MI&: *MIHigh, insn: (Instruction >> 16) & 0x1fff, Address, DisAsm: this, STI);
412 if (Result != DecodeStatus::Success)
413 return DecodeStatus::Fail;
414 adjustDuplex(MI&: *MIHigh, Context&: getContext());
415 MCOperand OPLow = MCOperand::createInst(Val: MILow);
416 MCOperand OPHigh = MCOperand::createInst(Val: MIHigh);
417 MI.addOperand(Op: OPLow);
418 MI.addOperand(Op: OPHigh);
419 Complete = true;
420 } else {
421 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
422 HexagonII::INST_PARSE_PACKET_END)
423 Complete = true;
424
425 if (CurrentExtender != nullptr)
426 Result = decodeInstruction(DecodeTable: DecoderTableMustExtend32, MI, insn: Instruction,
427 Address, DisAsm: this, STI);
428
429 if (Result != MCDisassembler::Success)
430 Result = decodeInstruction(DecodeTable: DecoderTable32, MI, insn: Instruction, Address, DisAsm: this,
431 STI);
432
433 if (Result != MCDisassembler::Success &&
434 STI.hasFeature(Feature: Hexagon::ExtensionHVX))
435 Result = decodeInstruction(DecodeTable: DecoderTableEXT_mmvec32, MI, insn: Instruction,
436 Address, DisAsm: this, STI);
437
438 }
439
440 switch (MI.getOpcode()) {
441 case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
442 case Hexagon::J4_cmpeqn1_f_jumpnv_t:
443 case Hexagon::J4_cmpeqn1_fp0_jump_nt:
444 case Hexagon::J4_cmpeqn1_fp0_jump_t:
445 case Hexagon::J4_cmpeqn1_fp1_jump_nt:
446 case Hexagon::J4_cmpeqn1_fp1_jump_t:
447 case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
448 case Hexagon::J4_cmpeqn1_t_jumpnv_t:
449 case Hexagon::J4_cmpeqn1_tp0_jump_nt:
450 case Hexagon::J4_cmpeqn1_tp0_jump_t:
451 case Hexagon::J4_cmpeqn1_tp1_jump_nt:
452 case Hexagon::J4_cmpeqn1_tp1_jump_t:
453 case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
454 case Hexagon::J4_cmpgtn1_f_jumpnv_t:
455 case Hexagon::J4_cmpgtn1_fp0_jump_nt:
456 case Hexagon::J4_cmpgtn1_fp0_jump_t:
457 case Hexagon::J4_cmpgtn1_fp1_jump_nt:
458 case Hexagon::J4_cmpgtn1_fp1_jump_t:
459 case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
460 case Hexagon::J4_cmpgtn1_t_jumpnv_t:
461 case Hexagon::J4_cmpgtn1_tp0_jump_nt:
462 case Hexagon::J4_cmpgtn1_tp0_jump_t:
463 case Hexagon::J4_cmpgtn1_tp1_jump_nt:
464 case Hexagon::J4_cmpgtn1_tp1_jump_t:
465 MI.insert(I: MI.begin() + 1,
466 Op: MCOperand::createExpr(Val: MCConstantExpr::create(Value: -1, Ctx&: getContext())));
467 break;
468 default:
469 break;
470 }
471
472 if (HexagonMCInstrInfo::isNewValue(MCII: *MCII, MCI: MI)) {
473 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(MCII: *MCII, MCI: MI);
474 MCOperand &MCO = MI.getOperand(i: OpIndex);
475 assert(MCO.isReg() && "New value consumers must be registers");
476 unsigned Register =
477 getContext().getRegisterInfo()->getEncodingValue(Reg: MCO.getReg());
478 if ((Register & 0x6) == 0)
479 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved
480 return MCDisassembler::Fail;
481 unsigned Lookback = (Register & 0x6) >> 1;
482 unsigned Offset = 1;
483 bool Vector = HexagonMCInstrInfo::isVector(MCII: *MCII, MCI: MI);
484 bool PrevVector = false;
485 auto Instructions = HexagonMCInstrInfo::bundleInstructions(MCI: **CurrentBundle);
486 auto i = Instructions.end() - 1;
487 for (auto n = Instructions.begin() - 1;; --i, ++Offset) {
488 if (i == n)
489 // Couldn't find producer
490 return MCDisassembler::Fail;
491 bool CurrentVector = HexagonMCInstrInfo::isVector(MCII: *MCII, MCI: *i->getInst());
492 if (Vector && !CurrentVector)
493 // Skip scalars when calculating distances for vectors
494 ++Lookback;
495 if (HexagonMCInstrInfo::isImmext(MCI: *i->getInst()) && (Vector == PrevVector))
496 ++Lookback;
497 PrevVector = CurrentVector;
498 if (Offset == Lookback)
499 break;
500 }
501 auto const &Inst = *i->getInst();
502 bool SubregBit = (Register & 0x1) != 0;
503 if (HexagonMCInstrInfo::hasNewValue2(MCII: *MCII, MCI: Inst)) {
504 // If subreg bit is set we're selecting the second produced newvalue
505 MCRegister Producer =
506 SubregBit
507 ? HexagonMCInstrInfo::getNewValueOperand(MCII: *MCII, MCI: Inst).getReg()
508 : HexagonMCInstrInfo::getNewValueOperand2(MCII: *MCII, MCI: Inst).getReg();
509 assert(Producer != Hexagon::NoRegister);
510 MCO.setReg(Producer);
511 } else if (HexagonMCInstrInfo::hasNewValue(MCII: *MCII, MCI: Inst)) {
512 MCRegister Producer =
513 HexagonMCInstrInfo::getNewValueOperand(MCII: *MCII, MCI: Inst).getReg();
514
515 if (HexagonMCInstrInfo::IsVecRegPair(VecReg: Producer)) {
516 const bool Rev = HexagonMCInstrInfo::IsReverseVecRegPair(VecReg: Producer);
517 const unsigned ProdPairIndex =
518 Rev ? Producer - Hexagon::WR0 : Producer - Hexagon::W0;
519 if (Rev)
520 SubregBit = !SubregBit;
521 Producer = (ProdPairIndex << 1) + SubregBit + Hexagon::V0;
522 } else if (SubregBit)
523 // Hexagon PRM 10.11 New-value operands
524 // Nt[0] is reserved and should always be encoded as zero.
525 return MCDisassembler::Fail;
526 assert(Producer != Hexagon::NoRegister);
527 MCO.setReg(Producer);
528 } else
529 return MCDisassembler::Fail;
530 }
531
532 if (CurrentExtender != nullptr) {
533 MCInst const &Inst = HexagonMCInstrInfo::isDuplex(MCII: *MCII, MCI: MI)
534 ? *MI.getOperand(i: 1).getInst()
535 : MI;
536 if (!HexagonMCInstrInfo::isExtendable(MCII: *MCII, MCI: Inst) &&
537 !HexagonMCInstrInfo::isExtended(MCII: *MCII, MCI: Inst))
538 return MCDisassembler::Fail;
539 }
540 return Result;
541}
542
543static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
544 ArrayRef<MCPhysReg> Table) {
545 if (RegNo < Table.size()) {
546 Inst.addOperand(Op: MCOperand::createReg(Reg: Table[RegNo]));
547 return MCDisassembler::Success;
548 }
549
550 return MCDisassembler::Fail;
551}
552
553static DecodeStatus
554DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
555 const MCDisassembler *Decoder) {
556 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
557}
558
559static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
560 uint64_t Address,
561 const MCDisassembler *Decoder) {
562 static const MCPhysReg IntRegDecoderTable[] = {
563 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
564 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
565 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
566 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
567 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
568 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
569 Hexagon::R30, Hexagon::R31};
570
571 return DecodeRegisterClass(Inst, RegNo, Table: IntRegDecoderTable);
572}
573
574static DecodeStatus
575DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo,
576 uint64_t Address,
577 const MCDisassembler *Decoder) {
578 static const MCPhysReg GeneralSubRegDecoderTable[] = {
579 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,
580 Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7,
581 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
582 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
583 };
584
585 return DecodeRegisterClass(Inst, RegNo, Table: GeneralSubRegDecoderTable);
586}
587
588static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
589 uint64_t /*Address*/,
590 const MCDisassembler *Decoder) {
591 static const MCPhysReg HvxVRDecoderTable[] = {
592 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
593 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
594 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
595 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19,
596 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24,
597 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
598 Hexagon::V30, Hexagon::V31};
599
600 return DecodeRegisterClass(Inst, RegNo, Table: HvxVRDecoderTable);
601}
602
603static DecodeStatus
604DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
605 uint64_t /*Address*/,
606 const MCDisassembler *Decoder) {
607 static const MCPhysReg DoubleRegDecoderTable[] = {
608 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
609 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
610 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
611 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
612
613 return DecodeRegisterClass(Inst, RegNo: RegNo >> 1, Table: DoubleRegDecoderTable);
614}
615
616static DecodeStatus
617DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
618 uint64_t /*Address*/,
619 const MCDisassembler *Decoder) {
620 static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = {
621 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
622 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11};
623
624 return DecodeRegisterClass(Inst, RegNo, Table: GeneralDoubleLow8RegDecoderTable);
625}
626
627static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
628 uint64_t /*Address*/,
629 const MCDisassembler *Decoder) {
630 static const MCPhysReg HvxWRDecoderTable[] = {
631 Hexagon::W0, Hexagon::WR0, Hexagon::W1, Hexagon::WR1, Hexagon::W2,
632 Hexagon::WR2, Hexagon::W3, Hexagon::WR3, Hexagon::W4, Hexagon::WR4,
633 Hexagon::W5, Hexagon::WR5, Hexagon::W6, Hexagon::WR6, Hexagon::W7,
634 Hexagon::WR7, Hexagon::W8, Hexagon::WR8, Hexagon::W9, Hexagon::WR9,
635 Hexagon::W10, Hexagon::WR10, Hexagon::W11, Hexagon::WR11, Hexagon::W12,
636 Hexagon::WR12, Hexagon::W13, Hexagon::WR13, Hexagon::W14, Hexagon::WR14,
637 Hexagon::W15, Hexagon::WR15,
638 };
639
640 return DecodeRegisterClass(Inst, RegNo, Table: HvxWRDecoderTable);
641}
642
643LLVM_ATTRIBUTE_UNUSED // Suppress warning temporarily.
644 static DecodeStatus
645 DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo,
646 uint64_t /*Address*/,
647 const MCDisassembler *Decoder) {
648 static const MCPhysReg HvxVQRDecoderTable[] = {
649 Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3,
650 Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7};
651
652 return DecodeRegisterClass(Inst, RegNo: RegNo >> 2, Table: HvxVQRDecoderTable);
653}
654
655static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
656 uint64_t /*Address*/,
657 const MCDisassembler *Decoder) {
658 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
659 Hexagon::P2, Hexagon::P3};
660
661 return DecodeRegisterClass(Inst, RegNo, Table: PredRegDecoderTable);
662}
663
664static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
665 uint64_t /*Address*/,
666 const MCDisassembler *Decoder) {
667 static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
668 Hexagon::Q2, Hexagon::Q3};
669
670 return DecodeRegisterClass(Inst, RegNo, Table: HvxQRDecoderTable);
671}
672
673static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
674 uint64_t /*Address*/,
675 const MCDisassembler *Decoder) {
676 using namespace Hexagon;
677
678 static const MCPhysReg CtrlRegDecoderTable[] = {
679 /* 0 */ SA0, LC0, SA1, LC1,
680 /* 4 */ P3_0, C5, M0, M1,
681 /* 8 */ USR, PC, UGP, GP,
682 /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI,
683 /* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI,
684 /* 20 */ 0, 0, 0, 0,
685 /* 24 */ 0, 0, 0, 0,
686 /* 28 */ 0, 0, UTIMERLO, UTIMERHI
687 };
688
689 if (RegNo >= std::size(CtrlRegDecoderTable))
690 return MCDisassembler::Fail;
691
692 static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
693 if (CtrlRegDecoderTable[RegNo] == NoRegister)
694 return MCDisassembler::Fail;
695
696 unsigned Register = CtrlRegDecoderTable[RegNo];
697 Inst.addOperand(Op: MCOperand::createReg(Reg: Register));
698 return MCDisassembler::Success;
699}
700
701static DecodeStatus
702DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
703 const MCDisassembler *Decoder) {
704 using namespace Hexagon;
705
706 static const MCPhysReg CtrlReg64DecoderTable[] = {
707 /* 0 */ C1_0, 0, C3_2, 0,
708 /* 4 */ C5_4, 0, C7_6, 0,
709 /* 8 */ C9_8, 0, C11_10, 0,
710 /* 12 */ CS, 0, UPCYCLE, 0,
711 /* 16 */ C17_16, 0, PKTCOUNT, 0,
712 /* 20 */ 0, 0, 0, 0,
713 /* 24 */ 0, 0, 0, 0,
714 /* 28 */ 0, 0, UTIMER, 0
715 };
716
717 if (RegNo >= std::size(CtrlReg64DecoderTable))
718 return MCDisassembler::Fail;
719
720 static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
721 if (CtrlReg64DecoderTable[RegNo] == NoRegister)
722 return MCDisassembler::Fail;
723
724 unsigned Register = CtrlReg64DecoderTable[RegNo];
725 Inst.addOperand(Op: MCOperand::createReg(Reg: Register));
726 return MCDisassembler::Success;
727}
728
729static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
730 uint64_t /*Address*/,
731 const MCDisassembler *Decoder) {
732 unsigned Register = 0;
733 switch (RegNo) {
734 case 0:
735 Register = Hexagon::M0;
736 break;
737 case 1:
738 Register = Hexagon::M1;
739 break;
740 default:
741 return MCDisassembler::Fail;
742 }
743 Inst.addOperand(Op: MCOperand::createReg(Reg: Register));
744 return MCDisassembler::Success;
745}
746
747static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
748 uint64_t /*Address*/,
749 const MCDisassembler *Decoder) {
750 HexagonDisassembler const &Disassembler = disassembler(Decoder);
751 int64_t FullValue = fullValue(Disassembler, MI, Value: tmp);
752 assert(FullValue >= 0 && "Negative in unsigned decoder");
753 HexagonMCInstrInfo::addConstant(MI, Value: FullValue, Context&: Disassembler.getContext());
754 return MCDisassembler::Success;
755}
756
757static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
758 uint64_t /*Address*/,
759 const MCDisassembler *Decoder) {
760 HexagonDisassembler const &Disassembler = disassembler(Decoder);
761 unsigned Bits = HexagonMCInstrInfo::getExtentBits(MCII: *Disassembler.MCII, MCI: MI);
762 tmp = SignExtend64(X: tmp, B: Bits);
763 signedDecoder<32>(MI, tmp, Decoder);
764 return MCDisassembler::Success;
765}
766
767// custom decoder for various jump/call immediates
768static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
769 const MCDisassembler *Decoder) {
770 HexagonDisassembler const &Disassembler = disassembler(Decoder);
771 unsigned Bits = HexagonMCInstrInfo::getExtentBits(MCII: *Disassembler.MCII, MCI: MI);
772 // r13_2 is not extendable, so if there are no extent bits, it's r13_2
773 if (Bits == 0)
774 Bits = 15;
775 uint64_t FullValue = fullValue(Disassembler, MI, Value: SignExtend64(X: tmp, B: Bits));
776 uint32_t Extended = FullValue + Address;
777 if (!Disassembler.tryAddingSymbolicOperand(Inst&: MI, Value: Extended, Address, IsBranch: true, Offset: 0, OpSize: 0,
778 InstSize: 4))
779 HexagonMCInstrInfo::addConstant(MI, Value: Extended, Context&: Disassembler.getContext());
780 return MCDisassembler::Success;
781}
782
783static const uint16_t SysRegDecoderTable[] = {
784 Hexagon::SGP0, Hexagon::SGP1, Hexagon::STID,
785 Hexagon::ELR, Hexagon::BADVA0, Hexagon::BADVA1,
786 Hexagon::SSR, Hexagon::CCR, Hexagon::HTID,
787 Hexagon::BADVA, Hexagon::IMASK, Hexagon::S11,
788 Hexagon::S12, Hexagon::S13, Hexagon::S14,
789 Hexagon::S15, Hexagon::EVB, Hexagon::MODECTL,
790 Hexagon::SYSCFG, Hexagon::S19, Hexagon::S20,
791 Hexagon::VID, Hexagon::S22, Hexagon::S23,
792 Hexagon::S24, Hexagon::S25, Hexagon::S26,
793 Hexagon::CFGBASE, Hexagon::DIAG, Hexagon::REV,
794 Hexagon::PCYCLELO, Hexagon::PCYCLEHI, Hexagon::ISDBST,
795 Hexagon::ISDBCFG0, Hexagon::ISDBCFG1, Hexagon::S35,
796 Hexagon::BRKPTPC0, Hexagon::BRKPTCFG0, Hexagon::BRKPTPC1,
797 Hexagon::BRKPTCFG1, Hexagon::ISDBMBXIN, Hexagon::ISDBMBXOUT,
798 Hexagon::ISDBEN, Hexagon::ISDBGPR, Hexagon::S44,
799 Hexagon::S45, Hexagon::S46, Hexagon::S47,
800 Hexagon::PMUCNT0, Hexagon::PMUCNT1, Hexagon::PMUCNT2,
801 Hexagon::PMUCNT3, Hexagon::PMUEVTCFG, Hexagon::PMUCFG,
802 Hexagon::S54, Hexagon::S55, Hexagon::S56,
803 Hexagon::S57, Hexagon::S58, Hexagon::S59,
804 Hexagon::S60, Hexagon::S61, Hexagon::S62,
805 Hexagon::S63, Hexagon::S64, Hexagon::S65,
806 Hexagon::S66, Hexagon::S67, Hexagon::S68,
807 Hexagon::S69, Hexagon::S70, Hexagon::S71,
808 Hexagon::S72, Hexagon::S73, Hexagon::S74,
809 Hexagon::S75, Hexagon::S76, Hexagon::S77,
810 Hexagon::S78, Hexagon::S79, Hexagon::S80,
811};
812
813static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
814 uint64_t /*Address*/,
815 const MCDisassembler *Decoder) {
816 if (RegNo >= std::size(SysRegDecoderTable))
817 return MCDisassembler::Fail;
818
819 if (SysRegDecoderTable[RegNo] == Hexagon::NoRegister)
820 return MCDisassembler::Fail;
821
822 unsigned Register = SysRegDecoderTable[RegNo];
823 Inst.addOperand(Op: MCOperand::createReg(Reg: Register));
824 return MCDisassembler::Success;
825}
826
827static const uint16_t SysReg64DecoderTable[] = {
828 Hexagon::SGP1_0, Hexagon::S3_2, Hexagon::S5_4, Hexagon::S7_6,
829 Hexagon::S9_8, Hexagon::S11_10, Hexagon::S13_12, Hexagon::S15_14,
830 Hexagon::S17_16, Hexagon::S19_18, Hexagon::S21_20, Hexagon::S23_22,
831 Hexagon::S25_24, Hexagon::S27_26, Hexagon::S29_28, Hexagon::S31_30,
832 Hexagon::S33_32, Hexagon::S35_34, Hexagon::S37_36, Hexagon::S39_38,
833 Hexagon::S41_40, Hexagon::S43_42, Hexagon::S45_44, Hexagon::S47_46,
834 Hexagon::S49_48, Hexagon::S51_50, Hexagon::S53_52, Hexagon::S55_54,
835 Hexagon::S57_56, Hexagon::S59_58, Hexagon::S61_60, Hexagon::S63_62,
836 Hexagon::S65_64, Hexagon::S67_66, Hexagon::S69_68, Hexagon::S71_70,
837 Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78,
838};
839
840static DecodeStatus
841DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
842 const MCDisassembler *Decoder) {
843 RegNo = RegNo >> 1;
844 if (RegNo >= std::size(SysReg64DecoderTable))
845 return MCDisassembler::Fail;
846
847 if (SysReg64DecoderTable[RegNo] == Hexagon::NoRegister)
848 return MCDisassembler::Fail;
849
850 unsigned Register = SysReg64DecoderTable[RegNo];
851 Inst.addOperand(Op: MCOperand::createReg(Reg: Register));
852 return MCDisassembler::Success;
853}
854
855static DecodeStatus
856DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
857 const MCDisassembler *Decoder) {
858 using namespace Hexagon;
859
860 static const MCPhysReg GuestRegDecoderTable[] = {
861 /* 0 */ GELR, GSR, GOSP, G3,
862 /* 4 */ G4, G5, G6, G7,
863 /* 8 */ G8, G9, G10, G11,
864 /* 12 */ G12, G13, G14, G15,
865 /* 16 */ GPMUCNT4, GPMUCNT5, GPMUCNT6, GPMUCNT7,
866 /* 20 */ G20, G21, G22, G23,
867 /* 24 */ GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1,
868 /* 28 */ GPMUCNT2, GPMUCNT3, G30, G31
869 };
870
871 if (RegNo >= std::size(GuestRegDecoderTable))
872 return MCDisassembler::Fail;
873 if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister)
874 return MCDisassembler::Fail;
875
876 unsigned Register = GuestRegDecoderTable[RegNo];
877 Inst.addOperand(Op: MCOperand::createReg(Reg: Register));
878 return MCDisassembler::Success;
879}
880
881static DecodeStatus
882DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
883 uint64_t /*Address*/,
884 const MCDisassembler *Decoder) {
885 using namespace Hexagon;
886
887 static const MCPhysReg GuestReg64DecoderTable[] = {
888 /* 0 */ G1_0, 0, G3_2, 0,
889 /* 4 */ G5_4, 0, G7_6, 0,
890 /* 8 */ G9_8, 0, G11_10, 0,
891 /* 12 */ G13_12, 0, G15_14, 0,
892 /* 16 */ G17_16, 0, G19_18, 0,
893 /* 20 */ G21_20, 0, G23_22, 0,
894 /* 24 */ G25_24, 0, G27_26, 0,
895 /* 28 */ G29_28, 0, G31_30, 0
896 };
897
898 if (RegNo >= std::size(GuestReg64DecoderTable))
899 return MCDisassembler::Fail;
900 if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister)
901 return MCDisassembler::Fail;
902
903 unsigned Register = GuestReg64DecoderTable[RegNo];
904 Inst.addOperand(Op: MCOperand::createReg(Reg: Register));
905 return MCDisassembler::Success;
906}
907