| 1 | //===-- MipsSEISelDAGToDAG.h - A Dag to Dag Inst Selector for MipsSE -----===// |
| 2 | // |
| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | // |
| 7 | //===----------------------------------------------------------------------===// |
| 8 | // |
| 9 | // Subclass of MipsDAGToDAGISel specialized for mips32/64. |
| 10 | // |
| 11 | //===----------------------------------------------------------------------===// |
| 12 | |
| 13 | #ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELDAGTODAG_H |
| 14 | #define LLVM_LIB_TARGET_MIPS_MIPSSEISELDAGTODAG_H |
| 15 | |
| 16 | #include "MipsISelDAGToDAG.h" |
| 17 | |
| 18 | namespace llvm { |
| 19 | |
| 20 | class MipsSEDAGToDAGISel : public MipsDAGToDAGISel { |
| 21 | |
| 22 | public: |
| 23 | explicit MipsSEDAGToDAGISel(MipsTargetMachine &TM, CodeGenOptLevel OL) |
| 24 | : MipsDAGToDAGISel(TM, OL) {} |
| 25 | |
| 26 | private: |
| 27 | |
| 28 | bool runOnMachineFunction(MachineFunction &MF) override; |
| 29 | |
| 30 | void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI, |
| 31 | MachineFunction &MF); |
| 32 | |
| 33 | MCRegister getMSACtrlReg(const SDValue RegIdx) const; |
| 34 | |
| 35 | bool replaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&); |
| 36 | |
| 37 | std::pair<SDNode *, SDNode *> selectMULT(SDNode *N, unsigned Opc, |
| 38 | const SDLoc &dl, EVT Ty, bool HasLo, |
| 39 | bool HasHi); |
| 40 | |
| 41 | void selectAddE(SDNode *Node, const SDLoc &DL) const; |
| 42 | |
| 43 | bool selectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset) const; |
| 44 | bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset, |
| 45 | unsigned OffsetBits, |
| 46 | unsigned ShiftAmount) const; |
| 47 | |
| 48 | bool selectAddrRegImm(SDValue Addr, SDValue &Base, |
| 49 | SDValue &Offset) const override; |
| 50 | |
| 51 | bool selectAddrDefault(SDValue Addr, SDValue &Base, |
| 52 | SDValue &Offset) const override; |
| 53 | |
| 54 | bool selectIntAddr(SDValue Addr, SDValue &Base, |
| 55 | SDValue &Offset) const override; |
| 56 | |
| 57 | bool selectAddrRegImm9(SDValue Addr, SDValue &Base, |
| 58 | SDValue &Offset) const; |
| 59 | |
| 60 | bool selectAddrRegImm11(SDValue Addr, SDValue &Base, |
| 61 | SDValue &Offset) const; |
| 62 | |
| 63 | bool selectAddrRegImm12(SDValue Addr, SDValue &Base, |
| 64 | SDValue &Offset) const; |
| 65 | |
| 66 | bool selectAddrRegImm16(SDValue Addr, SDValue &Base, |
| 67 | SDValue &Offset) const; |
| 68 | |
| 69 | bool selectIntAddr11MM(SDValue Addr, SDValue &Base, |
| 70 | SDValue &Offset) const override; |
| 71 | |
| 72 | bool selectIntAddr12MM(SDValue Addr, SDValue &Base, |
| 73 | SDValue &Offset) const override; |
| 74 | |
| 75 | bool selectIntAddr16MM(SDValue Addr, SDValue &Base, |
| 76 | SDValue &Offset) const override; |
| 77 | |
| 78 | bool selectIntAddrLSL2MM(SDValue Addr, SDValue &Base, |
| 79 | SDValue &Offset) const override; |
| 80 | |
| 81 | bool selectIntAddrSImm10(SDValue Addr, SDValue &Base, |
| 82 | SDValue &Offset) const override; |
| 83 | |
| 84 | bool selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base, |
| 85 | SDValue &Offset) const override; |
| 86 | |
| 87 | bool selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base, |
| 88 | SDValue &Offset) const override; |
| 89 | |
| 90 | bool selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base, |
| 91 | SDValue &Offset) const override; |
| 92 | |
| 93 | /// Select constant vector splats. |
| 94 | bool selectVSplat(SDNode *N, APInt &Imm, |
| 95 | unsigned MinSizeInBits) const override; |
| 96 | /// Select constant vector splats whose value fits in a given integer. |
| 97 | bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed, |
| 98 | unsigned ImmBitSize) const override; |
| 99 | /// Select constant vector splats whose value is a power of 2. |
| 100 | bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) const override; |
| 101 | /// Select constant vector splats whose value is the inverse of a |
| 102 | /// power of 2. |
| 103 | bool selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const override; |
| 104 | /// Select constant vector splats whose value is a run of set bits |
| 105 | /// ending at the most significant bit. |
| 106 | bool selectVSplatMaskL(SDValue N, SDValue &Imm) const override; |
| 107 | /// Select constant vector splats whose value is a run of set bits |
| 108 | /// starting at bit zero. |
| 109 | bool selectVSplatMaskR(SDValue N, SDValue &Imm) const override; |
| 110 | |
| 111 | /// Select constant vector splats whose value is 1. |
| 112 | bool selectVSplatImmEq1(SDValue N) const override; |
| 113 | |
| 114 | bool trySelect(SDNode *Node) override; |
| 115 | |
| 116 | // Emits proper ABI for _mcount profiling calls. |
| 117 | void emitMCountABI(MachineInstr &MI, MachineBasicBlock &MBB, |
| 118 | MachineFunction &MF); |
| 119 | |
| 120 | void processFunctionAfterISel(MachineFunction &MF) override; |
| 121 | |
| 122 | bool SelectInlineAsmMemoryOperand(const SDValue &Op, |
| 123 | InlineAsm::ConstraintCode ConstraintID, |
| 124 | std::vector<SDValue> &OutOps) override; |
| 125 | }; |
| 126 | |
| 127 | class MipsSEDAGToDAGISelLegacy : public MipsDAGToDAGISelLegacy { |
| 128 | public: |
| 129 | explicit MipsSEDAGToDAGISelLegacy(MipsTargetMachine &TM, CodeGenOptLevel OL); |
| 130 | void getAnalysisUsage(AnalysisUsage &AU) const override; |
| 131 | }; |
| 132 | |
| 133 | FunctionPass *createMipsSEISelDag(MipsTargetMachine &TM, |
| 134 | CodeGenOptLevel OptLevel); |
| 135 | } |
| 136 | |
| 137 | #endif |
| 138 | |