1//===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This tablegen backend emits an assembly printer for the current target.
10// Note that this is currently fairly skeletal, but will grow over time.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Basic/SequenceToOffsetTable.h"
15#include "Common/AsmWriterInst.h"
16#include "Common/CodeGenInstAlias.h"
17#include "Common/CodeGenInstruction.h"
18#include "Common/CodeGenRegisters.h"
19#include "Common/CodeGenTarget.h"
20#include "Common/Types.h"
21#include "llvm/ADT/ArrayRef.h"
22#include "llvm/ADT/DenseMap.h"
23#include "llvm/ADT/STLExtras.h"
24#include "llvm/ADT/SmallString.h"
25#include "llvm/ADT/SmallVector.h"
26#include "llvm/ADT/StringExtras.h"
27#include "llvm/ADT/StringRef.h"
28#include "llvm/ADT/Twine.h"
29#include "llvm/Support/Casting.h"
30#include "llvm/Support/Debug.h"
31#include "llvm/Support/Format.h"
32#include "llvm/Support/FormatVariadic.h"
33#include "llvm/Support/MathExtras.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/TableGen/Error.h"
36#include "llvm/TableGen/Record.h"
37#include "llvm/TableGen/TableGenBackend.h"
38#include <algorithm>
39#include <cassert>
40#include <cstddef>
41#include <cstdint>
42#include <deque>
43#include <iterator>
44#include <map>
45#include <set>
46#include <string>
47#include <tuple>
48#include <utility>
49#include <vector>
50
51using namespace llvm;
52
53#define DEBUG_TYPE "asm-writer-emitter"
54
55namespace {
56
57class AsmWriterEmitter {
58 const RecordKeeper &Records;
59 CodeGenTarget Target;
60 ArrayRef<const CodeGenInstruction *> NumberedInstructions;
61 std::vector<AsmWriterInst> Instructions;
62
63public:
64 AsmWriterEmitter(const RecordKeeper &R);
65
66 void run(raw_ostream &o);
67
68private:
69 void EmitGetMnemonic(
70 raw_ostream &o,
71 std::vector<std::vector<std::string>> &TableDrivenOperandPrinters,
72 unsigned &BitsLeft, unsigned &AsmStrBits);
73 void EmitPrintInstruction(
74 raw_ostream &o,
75 std::vector<std::vector<std::string>> &TableDrivenOperandPrinters,
76 unsigned &BitsLeft, unsigned &AsmStrBits);
77 void EmitGetRegisterName(raw_ostream &o);
78 void EmitPrintAliasInstruction(raw_ostream &O);
79
80 void FindUniqueOperandCommands(std::vector<std::string> &UOC,
81 std::vector<std::vector<unsigned>> &InstIdxs,
82 std::vector<unsigned> &InstOpsUsed,
83 bool PassSubtarget) const;
84};
85
86} // end anonymous namespace
87
88static void
89PrintCases(std::vector<std::pair<std::string, AsmWriterOperand>> &OpsToPrint,
90 raw_ostream &O, bool PassSubtarget) {
91 O << " case " << OpsToPrint.back().first << ":";
92 AsmWriterOperand TheOp = OpsToPrint.back().second;
93 OpsToPrint.pop_back();
94
95 // Check to see if any other operands are identical in this list, and if so,
96 // emit a case label for them.
97 for (unsigned i = OpsToPrint.size(); i != 0; --i)
98 if (OpsToPrint[i - 1].second == TheOp) {
99 O << "\n case " << OpsToPrint[i - 1].first << ":";
100 OpsToPrint.erase(position: OpsToPrint.begin() + i - 1);
101 }
102
103 // Finally, emit the code.
104 O << "\n " << TheOp.getCode(PassSubtarget);
105 O << "\n break;\n";
106}
107
108/// EmitInstructions - Emit the last instruction in the vector and any other
109/// instructions that are suitably similar to it.
110static void EmitInstructions(std::vector<AsmWriterInst> &Insts, raw_ostream &O,
111 bool PassSubtarget) {
112 AsmWriterInst FirstInst = Insts.back();
113 Insts.pop_back();
114
115 std::vector<AsmWriterInst> SimilarInsts;
116 unsigned DifferingOperand = ~0;
117 for (unsigned i = Insts.size(); i != 0; --i) {
118 unsigned DiffOp = Insts[i - 1].MatchesAllButOneOp(Other: FirstInst);
119 if (DiffOp != ~1U) {
120 if (DifferingOperand == ~0U) // First match!
121 DifferingOperand = DiffOp;
122
123 // If this differs in the same operand as the rest of the instructions in
124 // this class, move it to the SimilarInsts list.
125 if (DifferingOperand == DiffOp || DiffOp == ~0U) {
126 SimilarInsts.push_back(x: Insts[i - 1]);
127 Insts.erase(position: Insts.begin() + i - 1);
128 }
129 }
130 }
131
132 O << " case " << FirstInst.CGI->Namespace
133 << "::" << FirstInst.CGI->TheDef->getName() << ":\n";
134 for (const AsmWriterInst &AWI : SimilarInsts)
135 O << " case " << AWI.CGI->Namespace << "::" << AWI.CGI->TheDef->getName()
136 << ":\n";
137 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
138 if (i != DifferingOperand) {
139 // If the operand is the same for all instructions, just print it.
140 O << " " << FirstInst.Operands[i].getCode(PassSubtarget);
141 } else {
142 // If this is the operand that varies between all of the instructions,
143 // emit a switch for just this operand now.
144 O << " switch (MI->getOpcode()) {\n";
145 O << " default: llvm_unreachable(\"Unexpected opcode.\");\n";
146 std::vector<std::pair<std::string, AsmWriterOperand>> OpsToPrint;
147 OpsToPrint.emplace_back(args: FirstInst.CGI->Namespace.str() +
148 "::" + FirstInst.CGI->TheDef->getName().str(),
149 args&: FirstInst.Operands[i]);
150
151 for (const AsmWriterInst &AWI : SimilarInsts) {
152 OpsToPrint.emplace_back(args: AWI.CGI->Namespace.str() +
153 "::" + AWI.CGI->TheDef->getName().str(),
154 args: AWI.Operands[i]);
155 }
156 std::reverse(first: OpsToPrint.begin(), last: OpsToPrint.end());
157 while (!OpsToPrint.empty())
158 PrintCases(OpsToPrint, O, PassSubtarget);
159 O << " }";
160 }
161 O << "\n";
162 }
163 O << " break;\n";
164}
165
166void AsmWriterEmitter::FindUniqueOperandCommands(
167 std::vector<std::string> &UniqueOperandCommands,
168 std::vector<std::vector<unsigned>> &InstIdxs,
169 std::vector<unsigned> &InstOpsUsed, bool PassSubtarget) const {
170 // This vector parallels UniqueOperandCommands, keeping track of which
171 // instructions each case are used for. It is a comma separated string of
172 // enums.
173 std::vector<std::string> InstrsForCase;
174 InstrsForCase.resize(new_size: UniqueOperandCommands.size());
175 InstOpsUsed.assign(n: UniqueOperandCommands.size(), val: 0);
176
177 for (size_t i = 0, e = Instructions.size(); i != e; ++i) {
178 const AsmWriterInst &Inst = Instructions[i];
179 if (Inst.Operands.empty())
180 continue; // Instruction already done.
181
182 std::string Command =
183 " " + Inst.Operands[0].getCode(PassSubtarget) + "\n";
184
185 // Check to see if we already have 'Command' in UniqueOperandCommands.
186 // If not, add it.
187 auto I = llvm::find(Range&: UniqueOperandCommands, Val: Command);
188 if (I != UniqueOperandCommands.end()) {
189 size_t idx = I - UniqueOperandCommands.begin();
190 InstrsForCase[idx] += ", ";
191 InstrsForCase[idx] += Inst.CGI->TheDef->getName();
192 InstIdxs[idx].push_back(x: i);
193 } else {
194 UniqueOperandCommands.push_back(x: std::move(Command));
195 InstrsForCase.push_back(x: Inst.CGI->TheDef->getName().str());
196 InstIdxs.emplace_back();
197 InstIdxs.back().push_back(x: i);
198
199 // This command matches one operand so far.
200 InstOpsUsed.push_back(x: 1);
201 }
202 }
203
204 // For each entry of UniqueOperandCommands, there is a set of instructions
205 // that uses it. If the next command of all instructions in the set are
206 // identical, fold it into the command.
207 for (size_t CommandIdx = 0, e = UniqueOperandCommands.size(); CommandIdx != e;
208 ++CommandIdx) {
209
210 const auto &Idxs = InstIdxs[CommandIdx];
211
212 for (unsigned Op = 1;; ++Op) {
213 // Find the first instruction in the set.
214 const AsmWriterInst &FirstInst = Instructions[Idxs.front()];
215 // If this instruction has no more operands, we isn't anything to merge
216 // into this command.
217 if (FirstInst.Operands.size() == Op)
218 break;
219
220 // Otherwise, scan to see if all of the other instructions in this command
221 // set share the operand.
222 if (any_of(Range: drop_begin(RangeOrContainer: Idxs), P: [&](unsigned Idx) {
223 const AsmWriterInst &OtherInst = Instructions[Idx];
224 return OtherInst.Operands.size() == Op ||
225 OtherInst.Operands[Op] != FirstInst.Operands[Op];
226 }))
227 break;
228
229 // Okay, everything in this command set has the same next operand. Add it
230 // to UniqueOperandCommands and remember that it was consumed.
231 std::string Command =
232 " " + FirstInst.Operands[Op].getCode(PassSubtarget) + "\n";
233
234 UniqueOperandCommands[CommandIdx] += Command;
235 InstOpsUsed[CommandIdx]++;
236 }
237 }
238
239 // Prepend some of the instructions each case is used for onto the case val.
240 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
241 std::string Instrs = InstrsForCase[i];
242 if (Instrs.size() > 70) {
243 Instrs.erase(first: Instrs.begin() + 70, last: Instrs.end());
244 Instrs += "...";
245 }
246
247 if (!Instrs.empty())
248 UniqueOperandCommands[i] =
249 " // " + Instrs + "\n" + UniqueOperandCommands[i];
250 }
251}
252
253static void UnescapeString(std::string &Str) {
254 for (unsigned i = 0; i != Str.size(); ++i) {
255 if (Str[i] == '\\' && i != Str.size() - 1) {
256 switch (Str[i + 1]) {
257 default:
258 continue; // Don't execute the code after the switch.
259 case 'a':
260 Str[i] = '\a';
261 break;
262 case 'b':
263 Str[i] = '\b';
264 break;
265 case 'e':
266 Str[i] = 27;
267 break;
268 case 'f':
269 Str[i] = '\f';
270 break;
271 case 'n':
272 Str[i] = '\n';
273 break;
274 case 'r':
275 Str[i] = '\r';
276 break;
277 case 't':
278 Str[i] = '\t';
279 break;
280 case 'v':
281 Str[i] = '\v';
282 break;
283 case '"':
284 Str[i] = '\"';
285 break;
286 case '\'':
287 Str[i] = '\'';
288 break;
289 case '\\':
290 Str[i] = '\\';
291 break;
292 }
293 // Nuke the second character.
294 Str.erase(position: Str.begin() + i + 1);
295 }
296 }
297}
298
299/// UnescapeAliasString - Supports literal braces in InstAlias asm string which
300/// are escaped with '\\' to avoid being interpreted as variants. Braces must
301/// be unescaped before c++ code is generated as (e.g.):
302///
303/// AsmString = "foo \{$\x01\}";
304///
305/// causes non-standard escape character warnings.
306static void UnescapeAliasString(std::string &Str) {
307 for (unsigned i = 0; i != Str.size(); ++i) {
308 if (Str[i] == '\\' && i != Str.size() - 1) {
309 switch (Str[i + 1]) {
310 default:
311 continue; // Don't execute the code after the switch.
312 case '{':
313 Str[i] = '{';
314 break;
315 case '}':
316 Str[i] = '}';
317 break;
318 }
319 // Nuke the second character.
320 Str.erase(position: Str.begin() + i + 1);
321 }
322 }
323}
324
325void AsmWriterEmitter::EmitGetMnemonic(
326 raw_ostream &O,
327 std::vector<std::vector<std::string>> &TableDrivenOperandPrinters,
328 unsigned &BitsLeft, unsigned &AsmStrBits) {
329 const Record *AsmWriter = Target.getAsmWriter();
330 StringRef ClassName = AsmWriter->getValueAsString(FieldName: "AsmWriterClassName");
331 bool PassSubtarget = AsmWriter->getValueAsInt(FieldName: "PassSubtarget");
332
333 O << "/// getMnemonic - This method is automatically generated by "
334 "tablegen\n"
335 "/// from the instruction set description.\n"
336 "std::pair<const char *, uint64_t>\n"
337 << Target.getName() << ClassName
338 << "::getMnemonic(const MCInst &MI) const {\n";
339
340 // Build an aggregate string, and build a table of offsets into it.
341 SequenceToOffsetTable<std::string> StringTable;
342
343 /// OpcodeInfo - This encodes the index of the string to use for the first
344 /// chunk of the output as well as indices used for operand printing.
345 std::vector<uint64_t> OpcodeInfo(NumberedInstructions.size());
346 const unsigned OpcodeInfoBits = 64;
347
348 // Add all strings to the string table upfront so it can generate an optimized
349 // representation.
350 for (AsmWriterInst &AWI : Instructions) {
351 if (AWI.Operands[0].OperandType == AsmWriterOperand::isLiteralTextOperand &&
352 !AWI.Operands[0].Str.empty()) {
353 std::string Str = AWI.Operands[0].Str;
354 UnescapeString(Str);
355 StringTable.add(Seq: Str);
356 }
357 }
358
359 StringTable.layout();
360
361 unsigned MaxStringIdx = 0;
362 for (AsmWriterInst &AWI : Instructions) {
363 unsigned Idx;
364 if (AWI.Operands[0].OperandType != AsmWriterOperand::isLiteralTextOperand ||
365 AWI.Operands[0].Str.empty()) {
366 // Something handled by the asmwriter printer, but with no leading string.
367 Idx = StringTable.get(Seq: "");
368 } else {
369 std::string Str = AWI.Operands[0].Str;
370 UnescapeString(Str);
371 Idx = StringTable.get(Seq: Str);
372 MaxStringIdx = std::max(a: MaxStringIdx, b: Idx);
373
374 // Nuke the string from the operand list. It is now handled!
375 AWI.Operands.erase(position: AWI.Operands.begin());
376 }
377
378 // Bias offset by one since we want 0 as a sentinel.
379 OpcodeInfo[AWI.CGIIndex] = Idx + 1;
380 }
381
382 // Figure out how many bits we used for the string index.
383 AsmStrBits = Log2_32_Ceil(Value: MaxStringIdx + 2);
384
385 // To reduce code size, we compactify common instructions into a few bits
386 // in the opcode-indexed table.
387 BitsLeft = OpcodeInfoBits - AsmStrBits;
388
389 while (true) {
390 std::vector<std::string> UniqueOperandCommands;
391 std::vector<std::vector<unsigned>> InstIdxs;
392 std::vector<unsigned> NumInstOpsHandled;
393 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
394 InstOpsUsed&: NumInstOpsHandled, PassSubtarget);
395
396 // If we ran out of operands to print, we're done.
397 if (UniqueOperandCommands.empty())
398 break;
399
400 // Compute the number of bits we need to represent these cases, this is
401 // ceil(log2(numentries)).
402 unsigned NumBits = Log2_32_Ceil(Value: UniqueOperandCommands.size());
403
404 // If we don't have enough bits for this operand, don't include it.
405 if (NumBits > BitsLeft) {
406 LLVM_DEBUG(errs() << "Not enough bits to densely encode " << NumBits
407 << " more bits\n");
408 break;
409 }
410
411 // Otherwise, we can include this in the initial lookup table. Add it in.
412 for (size_t i = 0, e = InstIdxs.size(); i != e; ++i) {
413 unsigned NumOps = NumInstOpsHandled[i];
414 for (unsigned Idx : InstIdxs[i]) {
415 OpcodeInfo[Instructions[Idx].CGIIndex] |=
416 (uint64_t)i << (OpcodeInfoBits - BitsLeft);
417 // Remove the info about this operand from the instruction.
418 AsmWriterInst &Inst = Instructions[Idx];
419 if (!Inst.Operands.empty()) {
420 assert(NumOps <= Inst.Operands.size() &&
421 "Can't remove this many ops!");
422 Inst.Operands.erase(first: Inst.Operands.begin(),
423 last: Inst.Operands.begin() + NumOps);
424 }
425 }
426 }
427 BitsLeft -= NumBits;
428
429 // Remember the handlers for this set of operands.
430 TableDrivenOperandPrinters.push_back(x: std::move(UniqueOperandCommands));
431 }
432
433 // Emit the string table itself.
434 StringTable.emitStringLiteralDef(OS&: O, Decl: " static const char AsmStrs[]");
435
436 // Emit the lookup tables in pieces to minimize wasted bytes.
437 unsigned BytesNeeded = ((OpcodeInfoBits - BitsLeft) + 7) / 8;
438 unsigned Table = 0, Shift = 0;
439 SmallString<128> BitsString;
440 raw_svector_ostream BitsOS(BitsString);
441 // If the total bits is more than 32-bits we need to use a 64-bit type.
442 BitsOS << " uint" << ((BitsLeft < (OpcodeInfoBits - 32)) ? 64 : 32)
443 << "_t Bits = 0;\n";
444 while (BytesNeeded != 0) {
445 // Figure out how big this table section needs to be, but no bigger than 4.
446 unsigned TableSize = std::min(a: llvm::bit_floor(Value: BytesNeeded), b: 4u);
447 BytesNeeded -= TableSize;
448 TableSize *= 8; // Convert to bits;
449 uint64_t Mask = (1ULL << TableSize) - 1;
450 O << " static const uint" << TableSize << "_t OpInfo" << Table
451 << "[] = {\n";
452 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
453 O << " " << ((OpcodeInfo[i] >> Shift) & Mask) << "U,\t// "
454 << NumberedInstructions[i]->TheDef->getName() << "\n";
455 }
456 O << " };\n\n";
457 // Emit string to combine the individual table lookups.
458 BitsOS << " Bits |= ";
459 // If the total bits is more than 32-bits we need to use a 64-bit type.
460 if (BitsLeft < (OpcodeInfoBits - 32))
461 BitsOS << "(uint64_t)";
462 BitsOS << "OpInfo" << Table << "[MI.getOpcode()] << " << Shift << ";\n";
463 // Prepare the shift for the next iteration and increment the table count.
464 Shift += TableSize;
465 ++Table;
466 }
467
468 O << " // Emit the opcode for the instruction.\n";
469 O << BitsString;
470
471 // Make sure we don't return an invalid pointer if bits is 0
472 O << " if (Bits == 0)\n"
473 " return {nullptr, Bits};\n";
474
475 // Return mnemonic string and bits.
476 O << " return {AsmStrs+(Bits & " << (1 << AsmStrBits) - 1
477 << ")-1, Bits};\n\n";
478
479 O << "}\n";
480}
481
482/// EmitPrintInstruction - Generate the code for the "printInstruction" method
483/// implementation. Destroys all instances of AsmWriterInst information, by
484/// clearing the Instructions vector.
485void AsmWriterEmitter::EmitPrintInstruction(
486 raw_ostream &O,
487 std::vector<std::vector<std::string>> &TableDrivenOperandPrinters,
488 unsigned &BitsLeft, unsigned &AsmStrBits) {
489 const unsigned OpcodeInfoBits = 64;
490 const Record *AsmWriter = Target.getAsmWriter();
491 StringRef ClassName = AsmWriter->getValueAsString(FieldName: "AsmWriterClassName");
492 bool PassSubtarget = AsmWriter->getValueAsInt(FieldName: "PassSubtarget");
493
494 // This function has some huge switch statements that causing excessive
495 // compile time in LLVM profile instrumenation build. This print function
496 // usually is not frequently called in compilation. Here we disable the
497 // profile instrumenation for this function.
498 O << "/// printInstruction - This method is automatically generated by "
499 "tablegen\n"
500 "/// from the instruction set description.\n"
501 "LLVM_NO_PROFILE_INSTRUMENT_FUNCTION\n"
502 "void "
503 << Target.getName() << ClassName
504 << "::printInstruction(const MCInst *MI, uint64_t Address, "
505 << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "")
506 << "raw_ostream &O) {\n";
507
508 // Emit the initial tab character.
509 O << " O << \"\\t\";\n\n";
510
511 // Emit the starting string.
512 O << " auto MnemonicInfo = getMnemonic(*MI);\n\n";
513 O << " O << MnemonicInfo.first;\n\n";
514
515 O << " uint" << ((BitsLeft < (OpcodeInfoBits - 32)) ? 64 : 32)
516 << "_t Bits = MnemonicInfo.second;\n"
517 << " assert(Bits != 0 && \"Cannot print this instruction.\");\n";
518
519 // Output the table driven operand information.
520 BitsLeft = OpcodeInfoBits - AsmStrBits;
521 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
522 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
523
524 // Compute the number of bits we need to represent these cases, this is
525 // ceil(log2(numentries)).
526 unsigned NumBits = Log2_32_Ceil(Value: Commands.size());
527 assert(NumBits <= BitsLeft && "consistency error");
528
529 // Emit code to extract this field from Bits.
530 O << "\n // Fragment " << i << " encoded into " << NumBits << " bits for "
531 << Commands.size() << " unique commands.\n";
532
533 if (Commands.size() == 2) {
534 // Emit two possibilitys with if/else.
535 O << " if ((Bits >> " << (OpcodeInfoBits - BitsLeft) << ") & "
536 << ((1 << NumBits) - 1) << ") {\n"
537 << Commands[1] << " } else {\n"
538 << Commands[0] << " }\n\n";
539 } else if (Commands.size() == 1) {
540 // Emit a single possibility.
541 O << Commands[0] << "\n\n";
542 } else {
543 O << " switch ((Bits >> " << (OpcodeInfoBits - BitsLeft) << ") & "
544 << ((1 << NumBits) - 1) << ") {\n"
545 << " default: llvm_unreachable(\"Invalid command number.\");\n";
546
547 // Print out all the cases.
548 for (unsigned j = 0, e = Commands.size(); j != e; ++j) {
549 O << " case " << j << ":\n";
550 O << Commands[j];
551 O << " break;\n";
552 }
553 O << " }\n\n";
554 }
555 BitsLeft -= NumBits;
556 }
557
558 // Okay, delete instructions with no operand info left.
559 llvm::erase_if(C&: Instructions,
560 P: [](AsmWriterInst &Inst) { return Inst.Operands.empty(); });
561
562 // Because this is a vector, we want to emit from the end. Reverse all of the
563 // elements in the vector.
564 std::reverse(first: Instructions.begin(), last: Instructions.end());
565
566 // Now that we've emitted all of the operand info that fit into 64 bits, emit
567 // information for those instructions that are left. This is a less dense
568 // encoding, but we expect the main 64-bit table to handle the majority of
569 // instructions.
570 if (!Instructions.empty()) {
571 // Find the opcode # of inline asm.
572 O << " switch (MI->getOpcode()) {\n";
573 O << " default: llvm_unreachable(\"Unexpected opcode.\");\n";
574 while (!Instructions.empty())
575 EmitInstructions(Insts&: Instructions, O, PassSubtarget);
576
577 O << " }\n";
578 }
579
580 O << "}\n";
581}
582
583static void
584emitRegisterNameString(raw_ostream &O, StringRef AltName,
585 const std::deque<CodeGenRegister> &Registers) {
586 SequenceToOffsetTable<std::string> StringTable;
587 SmallVector<std::string, 4> AsmNames(Registers.size());
588 unsigned i = 0;
589 for (const auto &Reg : Registers) {
590 std::string &AsmName = AsmNames[i++];
591
592 // "NoRegAltName" is special. We don't need to do a lookup for that,
593 // as it's just a reference to the default register name.
594 if (AltName == "" || AltName == "NoRegAltName") {
595 AsmName = Reg.TheDef->getValueAsString(FieldName: "AsmName").str();
596 if (AsmName.empty())
597 AsmName = Reg.getName().str();
598 } else {
599 // Make sure the register has an alternate name for this index.
600 std::vector<const Record *> AltNameList =
601 Reg.TheDef->getValueAsListOfDefs(FieldName: "RegAltNameIndices");
602 unsigned Idx = 0, e;
603 for (e = AltNameList.size();
604 Idx < e && (AltNameList[Idx]->getName() != AltName); ++Idx)
605 ;
606 // If the register has an alternate name for this index, use it.
607 // Otherwise, leave it empty as an error flag.
608 if (Idx < e) {
609 std::vector<StringRef> AltNames =
610 Reg.TheDef->getValueAsListOfStrings(FieldName: "AltNames");
611 if (AltNames.size() <= Idx)
612 PrintFatalError(ErrorLoc: Reg.TheDef->getLoc(),
613 Msg: "Register definition missing alt name for '" +
614 AltName + "'.");
615 AsmName = AltNames[Idx].str();
616 }
617 }
618 StringTable.add(Seq: AsmName);
619 }
620
621 StringTable.layout();
622 StringTable.emitStringLiteralDef(OS&: O, Decl: Twine(" static const char AsmStrs") +
623 AltName + "[]");
624
625 O << " static const " << getMinimalTypeForRange(Range: StringTable.size() - 1, MaxSize: 32)
626 << " RegAsmOffset" << AltName << "[] = {";
627 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
628 if ((i % 14) == 0)
629 O << "\n ";
630 O << StringTable.get(Seq: AsmNames[i]) << ", ";
631 }
632 O << "\n };\n"
633 << "\n";
634}
635
636void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
637 const Record *AsmWriter = Target.getAsmWriter();
638 StringRef ClassName = AsmWriter->getValueAsString(FieldName: "AsmWriterClassName");
639 const auto &Registers = Target.getRegBank().getRegisters();
640 ArrayRef<const Record *> AltNameIndices = Target.getRegAltNameIndices();
641 bool hasAltNames = AltNameIndices.size() > 1;
642 StringRef Namespace = Registers.front().TheDef->getValueAsString(FieldName: "Namespace");
643
644 O << "\n\n/// getRegisterName - This method is automatically generated by "
645 "tblgen\n"
646 "/// from the register set description. This returns the assembler "
647 "name\n"
648 "/// for the specified register.\n"
649 "const char *"
650 << Target.getName() << ClassName << "::";
651 if (hasAltNames)
652 O << "\ngetRegisterName(MCRegister Reg, unsigned AltIdx) {\n";
653 else
654 O << "getRegisterName(MCRegister Reg) {\n";
655 O << " unsigned RegNo = Reg.id();\n"
656 << " assert(RegNo && RegNo < " << (Registers.size() + 1)
657 << " && \"Invalid register number!\");\n"
658 << "\n";
659
660 if (hasAltNames) {
661 for (const Record *R : AltNameIndices)
662 emitRegisterNameString(O, AltName: R->getName(), Registers);
663 } else {
664 emitRegisterNameString(O, AltName: "", Registers);
665 }
666
667 if (hasAltNames) {
668 O << " switch(AltIdx) {\n"
669 << " default: llvm_unreachable(\"Invalid register alt name index!\");\n";
670 for (const Record *R : AltNameIndices) {
671 StringRef AltName = R->getName();
672 O << " case ";
673 if (!Namespace.empty())
674 O << Namespace << "::";
675 O << AltName << ":\n";
676 if (R->isValueUnset(FieldName: "FallbackRegAltNameIndex"))
677 O << " assert(*(AsmStrs" << AltName << "+RegAsmOffset" << AltName
678 << "[RegNo-1]) &&\n"
679 << " \"Invalid alt name index for register!\");\n";
680 else {
681 O << " if (!*(AsmStrs" << AltName << "+RegAsmOffset" << AltName
682 << "[RegNo-1]))\n"
683 << " return getRegisterName(RegNo, ";
684 if (!Namespace.empty())
685 O << Namespace << "::";
686 O << R->getValueAsDef(FieldName: "FallbackRegAltNameIndex")->getName() << ");\n";
687 }
688 O << " return AsmStrs" << AltName << "+RegAsmOffset" << AltName
689 << "[RegNo-1];\n";
690 }
691 O << " }\n";
692 } else {
693 O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n"
694 << " \"Invalid alt name index for register!\");\n"
695 << " return AsmStrs+RegAsmOffset[RegNo-1];\n";
696 }
697 O << "}\n";
698}
699
700namespace {
701
702// IAPrinter - Holds information about an InstAlias. Two InstAliases match if
703// they both have the same conditionals. In which case, we cannot print out the
704// alias for that pattern.
705class IAPrinter {
706 std::map<StringRef, std::pair<int, int>> OpMap;
707
708 std::vector<std::string> Conds;
709
710 std::string Result;
711 std::string AsmString;
712
713 unsigned NumMIOps;
714
715public:
716 IAPrinter(std::string R, std::string AS, unsigned NumMIOps)
717 : Result(std::move(R)), AsmString(std::move(AS)), NumMIOps(NumMIOps) {}
718
719 void addCond(std::string C) { Conds.push_back(x: std::move(C)); }
720 ArrayRef<std::string> getConds() const { return Conds; }
721 size_t getCondCount() const { return Conds.size(); }
722
723 void addOperand(StringRef Op, int OpIdx, int PrintMethodIdx = -1) {
724 assert(OpIdx >= 0 && OpIdx < 0xFE && "Idx out of range");
725 assert(PrintMethodIdx >= -1 && PrintMethodIdx < 0xFF && "Idx out of range");
726 OpMap[Op] = {OpIdx, PrintMethodIdx};
727 }
728
729 unsigned getNumMIOps() { return NumMIOps; }
730
731 StringRef getResult() { return Result; }
732
733 bool isOpMapped(StringRef Op) { return OpMap.find(x: Op) != OpMap.end(); }
734 int getOpIndex(StringRef Op) { return OpMap[Op].first; }
735 std::pair<int, int> &getOpData(StringRef Op) { return OpMap[Op]; }
736
737 std::pair<StringRef, StringRef::iterator> parseName(StringRef::iterator Start,
738 StringRef::iterator End) {
739 StringRef::iterator I = Start;
740 StringRef::iterator Next;
741 if (*I == '{') {
742 // ${some_name}
743 Start = ++I;
744 while (I != End && *I != '}')
745 ++I;
746 Next = I;
747 // eat the final '}'
748 if (Next != End)
749 ++Next;
750 } else {
751 // $name, just eat the usual suspects.
752 while (I != End && (isAlnum(C: *I) || *I == '_'))
753 ++I;
754 Next = I;
755 }
756
757 return {StringRef(Start, I - Start), Next};
758 }
759
760 std::string formatAliasString(uint32_t &UnescapedSize) {
761 // Directly mangle mapped operands into the string. Each operand is
762 // identified by a '$' sign followed by a byte identifying the number of the
763 // operand. We add one to the index to avoid zero bytes.
764 StringRef ASM(AsmString);
765 std::string OutString;
766 raw_string_ostream OS(OutString);
767 for (StringRef::iterator I = ASM.begin(), E = ASM.end(); I != E;) {
768 OS << *I;
769 ++UnescapedSize;
770 if (*I == '$') {
771 StringRef Name;
772 std::tie(args&: Name, args&: I) = parseName(Start: ++I, End: E);
773 assert(isOpMapped(Name) && "Unmapped operand!");
774
775 int OpIndex, PrintIndex;
776 std::tie(args&: OpIndex, args&: PrintIndex) = getOpData(Op: Name);
777 if (PrintIndex == -1) {
778 // Can use the default printOperand route.
779 OS << format(Fmt: "\\x%02X", Vals: (unsigned char)OpIndex + 1);
780 ++UnescapedSize;
781 } else {
782 // 3 bytes if a PrintMethod is needed: 0xFF, the MCInst operand
783 // number, and which of our pre-detected Methods to call.
784 OS << format(Fmt: "\\xFF\\x%02X\\x%02X", Vals: OpIndex + 1, Vals: PrintIndex + 1);
785 UnescapedSize += 3;
786 }
787 } else {
788 ++I;
789 }
790 }
791 return OutString;
792 }
793
794 bool operator==(const IAPrinter &RHS) const {
795 if (NumMIOps != RHS.NumMIOps)
796 return false;
797 if (Conds.size() != RHS.Conds.size())
798 return false;
799
800 unsigned Idx = 0;
801 for (const auto &str : Conds)
802 if (str != RHS.Conds[Idx++])
803 return false;
804
805 return true;
806 }
807};
808
809} // end anonymous namespace
810
811static unsigned CountNumOperands(StringRef AsmString, unsigned Variant) {
812 return AsmString.count(C: ' ') + AsmString.count(C: '\t');
813}
814
815namespace {
816
817struct AliasPriorityComparator {
818 typedef std::pair<CodeGenInstAlias, int> ValueType;
819 bool operator()(const ValueType &LHS, const ValueType &RHS) const {
820 if (LHS.second == RHS.second) {
821 // We don't actually care about the order, but for consistency it
822 // shouldn't depend on pointer comparisons.
823 return LessRecordByID()(LHS.first.TheDef, RHS.first.TheDef);
824 }
825
826 // Aliases with larger priorities should be considered first.
827 return LHS.second > RHS.second;
828 }
829};
830
831} // end anonymous namespace
832
833void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
834 const Record *AsmWriter = Target.getAsmWriter();
835
836 O << "\n#ifdef PRINT_ALIAS_INSTR\n";
837 O << "#undef PRINT_ALIAS_INSTR\n\n";
838
839 //////////////////////////////
840 // Gather information about aliases we need to print
841 //////////////////////////////
842
843 // Emit the method that prints the alias instruction.
844 StringRef ClassName = AsmWriter->getValueAsString(FieldName: "AsmWriterClassName");
845 unsigned Variant = AsmWriter->getValueAsInt(FieldName: "Variant");
846 bool PassSubtarget = AsmWriter->getValueAsInt(FieldName: "PassSubtarget");
847
848 // Create a map from the qualified name to a list of potential matches.
849 typedef std::set<std::pair<CodeGenInstAlias, int>, AliasPriorityComparator>
850 AliasWithPriority;
851 std::map<std::string, AliasWithPriority> AliasMap;
852 for (const Record *R : Records.getAllDerivedDefinitions(ClassName: "InstAlias")) {
853 int Priority = R->getValueAsInt(FieldName: "EmitPriority");
854 if (Priority < 1)
855 continue; // Aliases with priority 0 are never emitted.
856
857 const DagInit *DI = R->getValueAsDag(FieldName: "ResultInst");
858 AliasMap[getQualifiedName(R: DI->getOperatorAsDef(Loc: R->getLoc()))].emplace(
859 args: CodeGenInstAlias(R, Target), args&: Priority);
860 }
861
862 // A map of which conditions need to be met for each instruction operand
863 // before it can be matched to the mnemonic.
864 std::map<std::string, std::vector<IAPrinter>> IAPrinterMap;
865
866 std::vector<std::pair<std::string, bool>> PrintMethods;
867
868 // A list of MCOperandPredicates for all operands in use, and the reverse map
869 std::vector<const Record *> MCOpPredicates;
870 DenseMap<const Record *, unsigned> MCOpPredicateMap;
871
872 for (auto &Aliases : AliasMap) {
873 for (auto &Alias : Aliases.second) {
874 const CodeGenInstAlias &CGA = Alias.first;
875 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
876 std::string FlatInstAsmString =
877 CodeGenInstruction::FlattenAsmStringVariants(
878 AsmString: CGA.ResultInst->AsmString, Variant);
879 unsigned NumResultOps = CountNumOperands(AsmString: FlatInstAsmString, Variant);
880
881 std::string FlatAliasAsmString =
882 CodeGenInstruction::FlattenAsmStringVariants(AsmString: CGA.AsmString, Variant);
883 UnescapeAliasString(Str&: FlatAliasAsmString);
884
885 // Don't emit the alias if it has more operands than what it's aliasing.
886 if (NumResultOps < CountNumOperands(AsmString: FlatAliasAsmString, Variant))
887 continue;
888
889 StringRef Namespace = Target.getName();
890 unsigned NumMIOps = 0;
891 for (auto &ResultInstOpnd : CGA.ResultInst->Operands)
892 NumMIOps += ResultInstOpnd.MINumOperands;
893
894 IAPrinter IAP(CGA.Result->getAsString(), FlatAliasAsmString, NumMIOps);
895
896 unsigned MIOpNum = 0;
897 for (unsigned i = 0, e = LastOpNo; i != e; ++i) {
898 // Skip over tied operands as they're not part of an alias declaration.
899 auto &Operands = CGA.ResultInst->Operands;
900 while (true) {
901 unsigned OpNum = Operands.getSubOperandNumber(Op: MIOpNum).first;
902 if (Operands[OpNum].MINumOperands == 1 &&
903 Operands[OpNum].getTiedRegister() != -1) {
904 // Tied operands of different RegisterClass should be explicit
905 // within an instruction's syntax and so cannot be skipped.
906 int TiedOpNum = Operands[OpNum].getTiedRegister();
907 if (Operands[OpNum].Rec->getName() ==
908 Operands[TiedOpNum].Rec->getName()) {
909 ++MIOpNum;
910 continue;
911 }
912 }
913 break;
914 }
915
916 // Ignore unchecked result operands.
917 while (IAP.getCondCount() < MIOpNum)
918 IAP.addCond(C: "AliasPatternCond::K_Ignore, 0");
919
920 const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i];
921
922 switch (RO.Kind) {
923 case CodeGenInstAlias::ResultOperand::K_Record: {
924 const Record *Rec = RO.getRecord();
925 StringRef ROName = RO.getName();
926 int PrintMethodIdx = -1;
927
928 // These two may have a PrintMethod, which we want to record (if it's
929 // the first time we've seen it) and provide an index for the aliasing
930 // code to use.
931 if (Rec->isSubClassOf(Name: "RegisterOperand") ||
932 Rec->isSubClassOf(Name: "Operand")) {
933 StringRef PrintMethod = Rec->getValueAsString(FieldName: "PrintMethod");
934 bool IsPCRel =
935 Rec->getValueAsString(FieldName: "OperandType") == "OPERAND_PCREL";
936 if (PrintMethod != "" && PrintMethod != "printOperand") {
937 PrintMethodIdx = llvm::find_if(Range&: PrintMethods,
938 P: [&](auto &X) {
939 return X.first == PrintMethod;
940 }) -
941 PrintMethods.begin();
942 if (static_cast<unsigned>(PrintMethodIdx) == PrintMethods.size())
943 PrintMethods.emplace_back(args: PrintMethod.str(), args&: IsPCRel);
944 }
945 }
946
947 if (Rec->isSubClassOf(Name: "RegisterOperand"))
948 Rec = Rec->getValueAsDef(FieldName: "RegClass");
949 if (Rec->isSubClassOf(Name: "RegisterClass")) {
950 if (!IAP.isOpMapped(Op: ROName)) {
951 IAP.addOperand(Op: ROName, OpIdx: MIOpNum, PrintMethodIdx);
952 const Record *R = CGA.ResultOperands[i].getRecord();
953 if (R->isSubClassOf(Name: "RegisterOperand"))
954 R = R->getValueAsDef(FieldName: "RegClass");
955 IAP.addCond(C: std::string(
956 formatv(Fmt: "AliasPatternCond::K_RegClass, {}::{}RegClassID",
957 Vals&: Namespace, Vals: R->getName())));
958 } else {
959 IAP.addCond(C: std::string(formatv(Fmt: "AliasPatternCond::K_TiedReg, {}",
960 Vals: IAP.getOpIndex(Op: ROName))));
961 }
962 } else {
963 // Assume all printable operands are desired for now. This can be
964 // overridden in the InstAlias instantiation if necessary.
965 IAP.addOperand(Op: ROName, OpIdx: MIOpNum, PrintMethodIdx);
966
967 // There might be an additional predicate on the MCOperand
968 unsigned &Entry = MCOpPredicateMap[Rec];
969 if (!Entry) {
970 if (!Rec->isValueUnset(FieldName: "MCOperandPredicate")) {
971 MCOpPredicates.push_back(x: Rec);
972 Entry = MCOpPredicates.size();
973 } else {
974 break; // No conditions on this operand at all
975 }
976 }
977 IAP.addCond(
978 C: std::string(formatv(Fmt: "AliasPatternCond::K_Custom, {}", Vals&: Entry)));
979 }
980 break;
981 }
982 case CodeGenInstAlias::ResultOperand::K_Imm: {
983 // Just because the alias has an immediate result, doesn't mean the
984 // MCInst will. An MCExpr could be present, for example.
985 auto Imm = CGA.ResultOperands[i].getImm();
986 int32_t Imm32 = int32_t(Imm);
987 if (Imm != Imm32)
988 PrintFatalError(Msg: "Matching an alias with an immediate out of the "
989 "range of int32_t is not supported");
990 IAP.addCond(C: std::string(
991 formatv(Fmt: "AliasPatternCond::K_Imm, uint32_t({})", Vals&: Imm32)));
992 break;
993 }
994 case CodeGenInstAlias::ResultOperand::K_Reg:
995 if (!CGA.ResultOperands[i].getRegister()) {
996 IAP.addCond(C: std::string(
997 formatv(Fmt: "AliasPatternCond::K_Reg, {}::NoRegister", Vals&: Namespace)));
998 break;
999 }
1000
1001 StringRef Reg = CGA.ResultOperands[i].getRegister()->getName();
1002 IAP.addCond(C: std::string(
1003 formatv(Fmt: "AliasPatternCond::K_Reg, {}::{}", Vals&: Namespace, Vals&: Reg)));
1004 break;
1005 }
1006
1007 MIOpNum += RO.getMINumOperands();
1008 }
1009
1010 std::vector<const Record *> ReqFeatures;
1011 if (PassSubtarget) {
1012 // We only consider ReqFeatures predicates if PassSubtarget
1013 std::vector<const Record *> RF =
1014 CGA.TheDef->getValueAsListOfDefs(FieldName: "Predicates");
1015 copy_if(Range&: RF, Out: std::back_inserter(x&: ReqFeatures), P: [](const Record *R) {
1016 return R->getValueAsBit(FieldName: "AssemblerMatcherPredicate");
1017 });
1018 }
1019
1020 for (const Record *R : ReqFeatures) {
1021 const DagInit *D = R->getValueAsDag(FieldName: "AssemblerCondDag");
1022 auto *Op = dyn_cast<DefInit>(Val: D->getOperator());
1023 if (!Op)
1024 PrintFatalError(ErrorLoc: R->getLoc(), Msg: "Invalid AssemblerCondDag!");
1025 StringRef CombineType = Op->getDef()->getName();
1026 if (CombineType != "any_of" && CombineType != "all_of")
1027 PrintFatalError(ErrorLoc: R->getLoc(), Msg: "Invalid AssemblerCondDag!");
1028 if (D->getNumArgs() == 0)
1029 PrintFatalError(ErrorLoc: R->getLoc(), Msg: "Invalid AssemblerCondDag!");
1030 bool IsOr = CombineType == "any_of";
1031 // Change (any_of FeatureAll, (any_of ...)) to (any_of FeatureAll, ...).
1032 if (IsOr && D->getNumArgs() == 2 && isa<DagInit>(Val: D->getArg(Num: 1))) {
1033 const DagInit *RHS = cast<DagInit>(Val: D->getArg(Num: 1));
1034 SmallVector<std::pair<const Init *, const StringInit *>> Args{
1035 *D->getArgAndNames().begin()};
1036 llvm::append_range(C&: Args, R: RHS->getArgAndNames());
1037 D = DagInit::get(V: D->getOperator(), ArgAndNames: Args);
1038 }
1039
1040 for (auto *Arg : D->getArgs()) {
1041 bool IsNeg = false;
1042 if (auto *NotArg = dyn_cast<DagInit>(Val: Arg)) {
1043 if (NotArg->getOperator()->getAsString() != "not" ||
1044 NotArg->getNumArgs() != 1)
1045 PrintFatalError(ErrorLoc: R->getLoc(), Msg: "Invalid AssemblerCondDag!");
1046 Arg = NotArg->getArg(Num: 0);
1047 IsNeg = true;
1048 }
1049 if (!isa<DefInit>(Val: Arg) ||
1050 !cast<DefInit>(Val: Arg)->getDef()->isSubClassOf(Name: "SubtargetFeature"))
1051 PrintFatalError(ErrorLoc: R->getLoc(), Msg: "Invalid AssemblerCondDag!");
1052
1053 IAP.addCond(C: std::string(formatv(
1054 Fmt: "AliasPatternCond::K_{}{}Feature, {}::{}", Vals: IsOr ? "Or" : "",
1055 Vals: IsNeg ? "Neg" : "", Vals&: Namespace, Vals: Arg->getAsString())));
1056 }
1057 // If an AssemblerPredicate with ors is used, note end of list should
1058 // these be combined.
1059 if (IsOr)
1060 IAP.addCond(C: "AliasPatternCond::K_EndOrFeatures, 0");
1061 }
1062
1063 IAPrinterMap[Aliases.first].push_back(x: std::move(IAP));
1064 }
1065 }
1066
1067 //////////////////////////////
1068 // Write out the printAliasInstr function
1069 //////////////////////////////
1070
1071 std::string Header;
1072 raw_string_ostream HeaderO(Header);
1073
1074 HeaderO << "bool " << Target.getName() << ClassName
1075 << "::printAliasInstr(const MCInst"
1076 << " *MI, uint64_t Address, "
1077 << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "")
1078 << "raw_ostream &OS) {\n";
1079
1080 std::string PatternsForOpcode;
1081 raw_string_ostream OpcodeO(PatternsForOpcode);
1082
1083 unsigned PatternCount = 0;
1084 std::string Patterns;
1085 raw_string_ostream PatternO(Patterns);
1086
1087 unsigned CondCount = 0;
1088 std::string Conds;
1089 raw_string_ostream CondO(Conds);
1090
1091 // All flattened alias strings.
1092 std::map<std::string, uint32_t> AsmStringOffsets;
1093 std::vector<std::pair<uint32_t, std::string>> AsmStrings;
1094 size_t AsmStringsSize = 0;
1095
1096 // Iterate over the opcodes in enum order so they are sorted by opcode for
1097 // binary search.
1098 for (const CodeGenInstruction *Inst : NumberedInstructions) {
1099 auto It = IAPrinterMap.find(x: getQualifiedName(R: Inst->TheDef));
1100 if (It == IAPrinterMap.end())
1101 continue;
1102 std::vector<IAPrinter> &IAPs = It->second;
1103 std::vector<IAPrinter *> UniqueIAPs;
1104
1105 // Remove any ambiguous alias rules.
1106 for (auto &LHS : IAPs) {
1107 bool IsDup = false;
1108 for (const auto &RHS : IAPs) {
1109 if (&LHS != &RHS && LHS == RHS) {
1110 IsDup = true;
1111 break;
1112 }
1113 }
1114
1115 if (!IsDup)
1116 UniqueIAPs.push_back(x: &LHS);
1117 }
1118
1119 if (UniqueIAPs.empty())
1120 continue;
1121
1122 unsigned PatternStart = PatternCount;
1123
1124 // Insert the pattern start and opcode in the pattern list for debugging.
1125 PatternO << formatv(Fmt: " // {} - {}\n", Vals: It->first, Vals&: PatternStart);
1126
1127 for (IAPrinter *IAP : UniqueIAPs) {
1128 // Start each condition list with a comment of the resulting pattern that
1129 // we're trying to match.
1130 unsigned CondStart = CondCount;
1131 CondO << formatv(Fmt: " // {} - {}\n", Vals: IAP->getResult(), Vals&: CondStart);
1132 for (const auto &Cond : IAP->getConds())
1133 CondO << " {" << Cond << "},\n";
1134 CondCount += IAP->getCondCount();
1135
1136 // After operands have been examined, re-encode the alias string with
1137 // escapes indicating how operands should be printed.
1138 uint32_t UnescapedSize = 0;
1139 std::string EncodedAsmString = IAP->formatAliasString(UnescapedSize);
1140 auto Insertion =
1141 AsmStringOffsets.try_emplace(k: EncodedAsmString, args&: AsmStringsSize);
1142 if (Insertion.second) {
1143 // If the string is new, add it to the vector.
1144 AsmStrings.emplace_back(args&: AsmStringsSize, args&: EncodedAsmString);
1145 AsmStringsSize += UnescapedSize + 1;
1146 }
1147 unsigned AsmStrOffset = Insertion.first->second;
1148
1149 PatternO << formatv(Fmt: " {{{}, {}, {}, {} },\n", Vals&: AsmStrOffset, Vals&: CondStart,
1150 Vals: IAP->getNumMIOps(), Vals: IAP->getCondCount());
1151 ++PatternCount;
1152 }
1153
1154 OpcodeO << formatv(Fmt: " {{{}, {}, {} },\n", Vals: It->first, Vals&: PatternStart,
1155 Vals: PatternCount - PatternStart);
1156 }
1157
1158 if (PatternsForOpcode.empty()) {
1159 O << Header;
1160 O << " return false;\n";
1161 O << "}\n\n";
1162 O << "#endif // PRINT_ALIAS_INSTR\n";
1163 return;
1164 }
1165
1166 // Forward declare the validation method if needed.
1167 if (!MCOpPredicates.empty())
1168 O << "static bool " << Target.getName() << ClassName
1169 << "ValidateMCOperand(const MCOperand &MCOp,\n"
1170 << " const MCSubtargetInfo &STI,\n"
1171 << " unsigned PredicateIndex);\n";
1172
1173 O << Header;
1174 O.indent(NumSpaces: 2) << "static const PatternsForOpcode OpToPatterns[] = {\n";
1175 O << PatternsForOpcode;
1176 O.indent(NumSpaces: 2) << "};\n\n";
1177 O.indent(NumSpaces: 2) << "static const AliasPattern Patterns[] = {\n";
1178 O << Patterns;
1179 O.indent(NumSpaces: 2) << "};\n\n";
1180 O.indent(NumSpaces: 2) << "static const AliasPatternCond Conds[] = {\n";
1181 O << Conds;
1182 O.indent(NumSpaces: 2) << "};\n\n";
1183 O.indent(NumSpaces: 2) << "static const char AsmStrings[] =\n";
1184 for (const auto &P : AsmStrings) {
1185 O.indent(NumSpaces: 4) << "/* " << P.first << " */ \"" << P.second << "\\0\"\n";
1186 }
1187
1188 O.indent(NumSpaces: 2) << ";\n\n";
1189
1190 // Assert that the opcode table is sorted. Use a static local constructor to
1191 // ensure that the check only happens once on first run.
1192 O << "#ifndef NDEBUG\n";
1193 O.indent(NumSpaces: 2) << "static struct SortCheck {\n";
1194 O.indent(NumSpaces: 2) << " SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {\n";
1195 O.indent(NumSpaces: 2) << " assert(std::is_sorted(\n";
1196 O.indent(NumSpaces: 2) << " OpToPatterns.begin(), OpToPatterns.end(),\n";
1197 O.indent(NumSpaces: 2) << " [](const PatternsForOpcode &L, const "
1198 "PatternsForOpcode &R) {\n";
1199 O.indent(NumSpaces: 2) << " return L.Opcode < R.Opcode;\n";
1200 O.indent(NumSpaces: 2) << " }) &&\n";
1201 O.indent(NumSpaces: 2) << " \"tablegen failed to sort opcode patterns\");\n";
1202 O.indent(NumSpaces: 2) << " }\n";
1203 O.indent(NumSpaces: 2) << "} sortCheckVar(OpToPatterns);\n";
1204 O << "#endif\n\n";
1205
1206 O.indent(NumSpaces: 2) << "AliasMatchingData M {\n";
1207 O.indent(NumSpaces: 2) << " ArrayRef(OpToPatterns),\n";
1208 O.indent(NumSpaces: 2) << " ArrayRef(Patterns),\n";
1209 O.indent(NumSpaces: 2) << " ArrayRef(Conds),\n";
1210 O.indent(NumSpaces: 2) << " StringRef(AsmStrings, std::size(AsmStrings)),\n";
1211 if (MCOpPredicates.empty())
1212 O.indent(NumSpaces: 2) << " nullptr,\n";
1213 else
1214 O.indent(NumSpaces: 2) << " &" << Target.getName() << ClassName
1215 << "ValidateMCOperand,\n";
1216 O.indent(NumSpaces: 2) << "};\n";
1217
1218 O.indent(NumSpaces: 2) << "const char *AsmString = matchAliasPatterns(MI, "
1219 << (PassSubtarget ? "&STI" : "nullptr") << ", M);\n";
1220 O.indent(NumSpaces: 2) << "if (!AsmString) return false;\n\n";
1221
1222 // Code that prints the alias, replacing the operands with the ones from the
1223 // MCInst.
1224 O << " unsigned I = 0;\n";
1225 O << " while (AsmString[I] != ' ' && AsmString[I] != '\\t' &&\n";
1226 O << " AsmString[I] != '$' && AsmString[I] != '\\0')\n";
1227 O << " ++I;\n";
1228 O << " OS << '\\t' << StringRef(AsmString, I);\n";
1229
1230 O << " if (AsmString[I] != '\\0') {\n";
1231 O << " if (AsmString[I] == ' ' || AsmString[I] == '\\t') {\n";
1232 O << " OS << '\\t';\n";
1233 O << " ++I;\n";
1234 O << " }\n";
1235 O << " do {\n";
1236 O << " if (AsmString[I] == '$') {\n";
1237 O << " ++I;\n";
1238 O << " if (AsmString[I] == (char)0xff) {\n";
1239 O << " ++I;\n";
1240 O << " int OpIdx = AsmString[I++] - 1;\n";
1241 O << " int PrintMethodIdx = AsmString[I++] - 1;\n";
1242 O << " printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, ";
1243 O << (PassSubtarget ? "STI, " : "");
1244 O << "OS);\n";
1245 O << " } else\n";
1246 O << " printOperand(MI, unsigned(AsmString[I++]) - 1, ";
1247 O << (PassSubtarget ? "STI, " : "");
1248 O << "OS);\n";
1249 O << " } else {\n";
1250 O << " OS << AsmString[I++];\n";
1251 O << " }\n";
1252 O << " } while (AsmString[I] != '\\0');\n";
1253 O << " }\n\n";
1254
1255 O << " return true;\n";
1256 O << "}\n\n";
1257
1258 //////////////////////////////
1259 // Write out the printCustomAliasOperand function
1260 //////////////////////////////
1261
1262 O << "void " << Target.getName() << ClassName << "::"
1263 << "printCustomAliasOperand(\n"
1264 << " const MCInst *MI, uint64_t Address, unsigned OpIdx,\n"
1265 << " unsigned PrintMethodIdx,\n"
1266 << (PassSubtarget ? " const MCSubtargetInfo &STI,\n" : "")
1267 << " raw_ostream &OS) {\n";
1268 if (PrintMethods.empty())
1269 O << " llvm_unreachable(\"Unknown PrintMethod kind\");\n";
1270 else {
1271 O << " switch (PrintMethodIdx) {\n"
1272 << " default:\n"
1273 << " llvm_unreachable(\"Unknown PrintMethod kind\");\n"
1274 << " break;\n";
1275
1276 for (unsigned i = 0; i < PrintMethods.size(); ++i) {
1277 O << " case " << i << ":\n"
1278 << " " << PrintMethods[i].first << "(MI, "
1279 << (PrintMethods[i].second ? "Address, " : "") << "OpIdx, "
1280 << (PassSubtarget ? "STI, " : "") << "OS);\n"
1281 << " break;\n";
1282 }
1283 O << " }\n";
1284 }
1285 O << "}\n\n";
1286
1287 if (!MCOpPredicates.empty()) {
1288 O << "static bool " << Target.getName() << ClassName
1289 << "ValidateMCOperand(const MCOperand &MCOp,\n"
1290 << " const MCSubtargetInfo &STI,\n"
1291 << " unsigned PredicateIndex) {\n"
1292 << " switch (PredicateIndex) {\n"
1293 << " default:\n"
1294 << " llvm_unreachable(\"Unknown MCOperandPredicate kind\");\n"
1295 << " break;\n";
1296
1297 for (unsigned i = 0; i < MCOpPredicates.size(); ++i) {
1298 StringRef MCOpPred =
1299 MCOpPredicates[i]->getValueAsString(FieldName: "MCOperandPredicate");
1300 O << " case " << i + 1 << ": {\n"
1301 << MCOpPred.data() << "\n"
1302 << " }\n";
1303 }
1304 O << " }\n"
1305 << "}\n\n";
1306 }
1307
1308 O << "#endif // PRINT_ALIAS_INSTR\n";
1309}
1310
1311AsmWriterEmitter::AsmWriterEmitter(const RecordKeeper &R)
1312 : Records(R), Target(R) {
1313 const Record *AsmWriter = Target.getAsmWriter();
1314 unsigned Variant = AsmWriter->getValueAsInt(FieldName: "Variant");
1315
1316 // Get the instruction numbering.
1317 NumberedInstructions = Target.getInstructionsByEnumValue();
1318
1319 for (const auto &[Idx, I] : enumerate(First&: NumberedInstructions)) {
1320 if (!I->AsmString.empty() && I->TheDef->getName() != "PHI")
1321 Instructions.emplace_back(args: *I, args&: Idx, args&: Variant);
1322 }
1323}
1324
1325void AsmWriterEmitter::run(raw_ostream &O) {
1326 std::vector<std::vector<std::string>> TableDrivenOperandPrinters;
1327 unsigned BitsLeft = 0;
1328 unsigned AsmStrBits = 0;
1329 emitSourceFileHeader(Desc: "Assembly Writer Source Fragment", OS&: O, Record: Records);
1330 EmitGetMnemonic(O, TableDrivenOperandPrinters, BitsLeft, AsmStrBits);
1331 EmitPrintInstruction(O, TableDrivenOperandPrinters, BitsLeft, AsmStrBits);
1332 EmitGetRegisterName(O);
1333 EmitPrintAliasInstruction(O);
1334}
1335
1336static TableGen::Emitter::OptClass<AsmWriterEmitter>
1337 X("gen-asm-writer", "Generate assembly writer");
1338