1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass MipsMCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::v4i8, MVT::v2i16, MVT::i32, MVT::Other,
15 /* 4 */ MVT::i64, MVT::Other,
16 /* 6 */ MVT::f16, MVT::Other,
17 /* 8 */ MVT::f32, MVT::Other,
18 /* 10 */ MVT::i32, MVT::f32, MVT::f64, MVT::Other,
19 /* 14 */ MVT::v16i8, MVT::Other,
20 /* 16 */ MVT::v4i8, MVT::v2i16, MVT::Other,
21 /* 19 */ MVT::v8i16, MVT::v8f16, MVT::Other,
22 /* 22 */ MVT::v4i32, MVT::v4f32, MVT::Other,
23 /* 25 */ MVT::v2i64, MVT::v2f64, MVT::Other,
24 /* 28 */ MVT::Untyped, MVT::Other,
25};
26
27static const char *SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_dsp16_19", "sub_dsp20", "sub_dsp21", "sub_dsp22", "sub_dsp23", "sub_hi", "sub_lo", "sub_hi_then_sub_32", "sub_32_sub_hi_then_sub_32", "" };
28
29static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
30 { .Offset: 65535, .Size: 65535 },
31 { .Offset: 0, .Size: 32 }, // sub_32
32 { .Offset: 0, .Size: 64 }, // sub_64
33 { .Offset: 16, .Size: 4 }, // sub_dsp16_19
34 { .Offset: 20, .Size: 1 }, // sub_dsp20
35 { .Offset: 21, .Size: 1 }, // sub_dsp21
36 { .Offset: 22, .Size: 1 }, // sub_dsp22
37 { .Offset: 23, .Size: 1 }, // sub_dsp23
38 { .Offset: 32, .Size: 32 }, // sub_hi
39 { .Offset: 0, .Size: 32 }, // sub_lo
40 { .Offset: 32, .Size: 32 }, // sub_hi_then_sub_32
41 { .Offset: 0, .Size: 64 }, // sub_32_sub_hi_then_sub_32
42 { .Offset: 65535, .Size: 65535 },
43 { .Offset: 0, .Size: 32 }, // sub_32
44 { .Offset: 0, .Size: 64 }, // sub_64
45 { .Offset: 16, .Size: 4 }, // sub_dsp16_19
46 { .Offset: 20, .Size: 1 }, // sub_dsp20
47 { .Offset: 21, .Size: 1 }, // sub_dsp21
48 { .Offset: 22, .Size: 1 }, // sub_dsp22
49 { .Offset: 23, .Size: 1 }, // sub_dsp23
50 { .Offset: 32, .Size: 32 }, // sub_hi
51 { .Offset: 0, .Size: 32 }, // sub_lo
52 { .Offset: 32, .Size: 32 }, // sub_hi_then_sub_32
53 { .Offset: 0, .Size: 64 }, // sub_32_sub_hi_then_sub_32
54};
55
56
57static const LaneBitmask SubRegIndexLaneMaskTable[] = {
58 LaneBitmask::getAll(),
59 LaneBitmask(0x0000000000000001), // sub_32
60 LaneBitmask(0x0000000000000041), // sub_64
61 LaneBitmask(0x0000000000000002), // sub_dsp16_19
62 LaneBitmask(0x0000000000000004), // sub_dsp20
63 LaneBitmask(0x0000000000000008), // sub_dsp21
64 LaneBitmask(0x0000000000000010), // sub_dsp22
65 LaneBitmask(0x0000000000000020), // sub_dsp23
66 LaneBitmask(0x0000000000000040), // sub_hi
67 LaneBitmask(0x0000000000000001), // sub_lo
68 LaneBitmask(0x0000000000000040), // sub_hi_then_sub_32
69 LaneBitmask(0x0000000000000041), // sub_32_sub_hi_then_sub_32
70 };
71
72
73
74static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
75 // Mode = 0 (Default)
76 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 6 }, // MSA128F16
77 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // CCR
78 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // COP0
79 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // COP2
80 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // COP3
81 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // DSPR
82 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // FGR32
83 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // FGR32CC
84 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPR32
85 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // HWRegs
86 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // MSACtrl
87 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPR32NONZERO
88 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // CPU16RegsPlusSP
89 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // CPU16Regs
90 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // FCC
91 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPRMM16
92 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPRMM16MoveP
93 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPRMM16Zero
94 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // CPU16Regs_and_GPRMM16Zero
95 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPR32NONZERO_and_GPRMM16MoveP
96 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPRMM16MovePPairSecond
97 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // CPU16Regs_and_GPRMM16MoveP
98 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPRMM16MoveP_and_GPRMM16Zero
99 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // HI32DSP
100 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // LO32DSP
101 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // CPU16Regs_and_GPRMM16MovePPairSecond
102 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPRMM16MovePPairFirst
103 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
104 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
105 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // CPURAReg
106 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // CPUSPReg
107 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 16 }, // DSPCC
108 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GP32
109 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPR32ZERO
110 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // HI32
111 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // LO32
112 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // SP32
113 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // FGR64CC
114 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 12 }, // FGR64
115 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64
116 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPR32NONZERO
117 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 12 }, // AFGR64
118 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16RegsPlusSP
119 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs
120 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MoveP
121 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16Zero
122 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
123 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
124 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
125 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 28 }, // ACC64DSP
126 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
127 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
128 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
129 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
130 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
131 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // OCTEON_MPL
132 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // OCTEON_P
133 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
134 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 28 }, // ACC64
135 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GP64
136 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPURAReg
137 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPR32ZERO
138 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // HI64
139 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // LO64
140 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // SP64
141 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 14 }, // MSA128B
142 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 25 }, // MSA128D
143 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 19 }, // MSA128H
144 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 22 }, // MSA128W
145 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 22 }, // MSA128WEvens
146 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 28 }, // ACC128
147 // Mode = 1 (MIPS64)
148 { .RegSize: 16, .SpillSize: 16, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 6 }, // MSA128F16
149 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // CCR
150 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // COP0
151 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // COP2
152 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // COP3
153 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // DSPR
154 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // FGR32
155 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // FGR32CC
156 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPR32
157 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // HWRegs
158 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // MSACtrl
159 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPR32NONZERO
160 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // CPU16RegsPlusSP
161 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // CPU16Regs
162 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // FCC
163 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPRMM16
164 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPRMM16MoveP
165 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPRMM16Zero
166 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // CPU16Regs_and_GPRMM16Zero
167 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPR32NONZERO_and_GPRMM16MoveP
168 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPRMM16MovePPairSecond
169 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // CPU16Regs_and_GPRMM16MoveP
170 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPRMM16MoveP_and_GPRMM16Zero
171 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // HI32DSP
172 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // LO32DSP
173 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // CPU16Regs_and_GPRMM16MovePPairSecond
174 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPRMM16MovePPairFirst
175 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
176 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
177 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // CPURAReg
178 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // CPUSPReg
179 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 16 }, // DSPCC
180 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GP32
181 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // GPR32ZERO
182 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // HI32
183 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // LO32
184 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // SP32
185 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // FGR64CC
186 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 12 }, // FGR64
187 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64
188 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPR32NONZERO
189 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 12 }, // AFGR64
190 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16RegsPlusSP
191 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs
192 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MoveP
193 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16Zero
194 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
195 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
196 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
197 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 28 }, // ACC64DSP
198 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
199 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
200 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
201 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
202 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
203 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // OCTEON_MPL
204 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // OCTEON_P
205 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
206 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 28 }, // ACC64
207 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GP64
208 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPURAReg
209 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPR32ZERO
210 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // HI64
211 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // LO64
212 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 4 }, // SP64
213 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 14 }, // MSA128B
214 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 25 }, // MSA128D
215 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 19 }, // MSA128H
216 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 22 }, // MSA128W
217 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 22 }, // MSA128WEvens
218 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 28 }, // ACC128
219};
220static const uint32_t MSA128F16SubClassMask[] = {
221 0x00000001, 0x00000000, 0x0000003e,
222};
223
224static const uint32_t CCRSubClassMask[] = {
225 0x00000002, 0x00000000, 0x00000000,
226};
227
228static const uint32_t COP0SubClassMask[] = {
229 0x00000004, 0x00000000, 0x00000000,
230};
231
232static const uint32_t COP2SubClassMask[] = {
233 0x00000008, 0x00000000, 0x00000000,
234};
235
236static const uint32_t COP3SubClassMask[] = {
237 0x00000010, 0x00000000, 0x00000000,
238};
239
240static const uint32_t DSPRSubClassMask[] = {
241 0x7e7fb920, 0x00000013, 0x00000000,
242 0x00000000, 0x3a7dfd80, 0x00000001, // sub_32
243};
244
245static const uint32_t FGR32SubClassMask[] = {
246 0x000000c0, 0x00000000, 0x00000000,
247 0x00000000, 0x00000200, 0x00000000, // sub_hi
248 0x00000001, 0x00000260, 0x0000003e, // sub_lo
249};
250
251static const uint32_t FGR32CCSubClassMask[] = {
252 0x000000c0, 0x00000000, 0x00000000,
253 0x00000000, 0x00000200, 0x00000000, // sub_hi
254 0x00000001, 0x00000260, 0x0000003e, // sub_lo
255};
256
257static const uint32_t GPR32SubClassMask[] = {
258 0x7e7fb900, 0x00000013, 0x00000000,
259 0x00000000, 0x3a7dfd80, 0x00000001, // sub_32
260};
261
262static const uint32_t HWRegsSubClassMask[] = {
263 0x00000200, 0x00000000, 0x00000000,
264};
265
266static const uint32_t MSACtrlSubClassMask[] = {
267 0x00000400, 0x00000000, 0x00000000,
268};
269
270static const uint32_t GPR32NONZEROSubClassMask[] = {
271 0x7e3cb800, 0x00000011, 0x00000000,
272 0x00000000, 0x1a75cd00, 0x00000001, // sub_32
273};
274
275static const uint32_t CPU16RegsPlusSPSubClassMask[] = {
276 0x5e24b000, 0x00000010, 0x00000000,
277 0x00000000, 0x02744c00, 0x00000001, // sub_32
278};
279
280static const uint32_t CPU16RegsSubClassMask[] = {
281 0x1e24a000, 0x00000000, 0x00000000,
282 0x00000000, 0x02744800, 0x00000000, // sub_32
283};
284
285static const uint32_t FCCSubClassMask[] = {
286 0x00004000, 0x00000000, 0x00000000,
287};
288
289static const uint32_t GPRMM16SubClassMask[] = {
290 0x1e248000, 0x00000000, 0x00000000,
291 0x00000000, 0x02744800, 0x00000000, // sub_32
292};
293
294static const uint32_t GPRMM16MovePSubClassMask[] = {
295 0x08690000, 0x00000002, 0x00000000,
296 0x00000000, 0x204c9000, 0x00000000, // sub_32
297};
298
299static const uint32_t GPRMM16ZeroSubClassMask[] = {
300 0x1e460000, 0x00000002, 0x00000000,
301 0x00000000, 0x22786000, 0x00000000, // sub_32
302};
303
304static const uint32_t CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
305 0x1e040000, 0x00000000, 0x00000000,
306 0x00000000, 0x02704000, 0x00000000, // sub_32
307};
308
309static const uint32_t GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
310 0x08280000, 0x00000000, 0x00000000,
311 0x00000000, 0x00448000, 0x00000000, // sub_32
312};
313
314static const uint32_t GPRMM16MovePPairSecondSubClassMask[] = {
315 0x12100000, 0x00000000, 0x00000000,
316 0x00000000, 0x02110000, 0x00000000, // sub_32
317};
318
319static const uint32_t CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
320 0x08200000, 0x00000000, 0x00000000,
321 0x00000000, 0x00440000, 0x00000000, // sub_32
322};
323
324static const uint32_t GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
325 0x08400000, 0x00000002, 0x00000000,
326 0x00000000, 0x20480000, 0x00000000, // sub_32
327};
328
329static const uint32_t HI32DSPSubClassMask[] = {
330 0x00800000, 0x00000004, 0x00000000,
331 0x00000000, 0x40000000, 0x00000000, // sub_32
332 0x00000000, 0x04020000, 0x00000000, // sub_hi
333 0x00000000, 0x00000000, 0x00000040, // sub_hi_then_sub_32
334};
335
336static const uint32_t LO32DSPSubClassMask[] = {
337 0x01000000, 0x00000008, 0x00000000,
338 0x00000000, 0x80000000, 0x00000040, // sub_32
339 0x00000000, 0x04020000, 0x00000000, // sub_lo
340};
341
342static const uint32_t CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {
343 0x12000000, 0x00000000, 0x00000000,
344 0x00000000, 0x02100000, 0x00000000, // sub_32
345};
346
347static const uint32_t GPRMM16MovePPairFirstSubClassMask[] = {
348 0x14000000, 0x00000000, 0x00000000,
349 0x00000000, 0x02200000, 0x00000000, // sub_32
350};
351
352static const uint32_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
353 0x08000000, 0x00000000, 0x00000000,
354 0x00000000, 0x00400000, 0x00000000, // sub_32
355};
356
357static const uint32_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {
358 0x10000000, 0x00000000, 0x00000000,
359 0x00000000, 0x02000000, 0x00000000, // sub_32
360};
361
362static const uint32_t CPURARegSubClassMask[] = {
363 0x20000000, 0x00000000, 0x00000000,
364 0x00000000, 0x10000000, 0x00000000, // sub_32
365};
366
367static const uint32_t CPUSPRegSubClassMask[] = {
368 0x40000000, 0x00000010, 0x00000000,
369 0x00000000, 0x00000000, 0x00000001, // sub_32
370};
371
372static const uint32_t DSPCCSubClassMask[] = {
373 0x80000000, 0x00000000, 0x00000000,
374};
375
376static const uint32_t GP32SubClassMask[] = {
377 0x00000000, 0x00000001, 0x00000000,
378 0x00000000, 0x08000000, 0x00000000, // sub_32
379};
380
381static const uint32_t GPR32ZEROSubClassMask[] = {
382 0x00000000, 0x00000002, 0x00000000,
383 0x00000000, 0x20000000, 0x00000000, // sub_32
384};
385
386static const uint32_t HI32SubClassMask[] = {
387 0x00000000, 0x00000004, 0x00000000,
388 0x00000000, 0x40000000, 0x00000000, // sub_32
389 0x00000000, 0x04000000, 0x00000000, // sub_hi
390 0x00000000, 0x00000000, 0x00000040, // sub_hi_then_sub_32
391};
392
393static const uint32_t LO32SubClassMask[] = {
394 0x00000000, 0x00000008, 0x00000000,
395 0x00000000, 0x80000000, 0x00000040, // sub_32
396 0x00000000, 0x04000000, 0x00000000, // sub_lo
397};
398
399static const uint32_t SP32SubClassMask[] = {
400 0x00000000, 0x00000010, 0x00000000,
401 0x00000000, 0x00000000, 0x00000001, // sub_32
402};
403
404static const uint32_t FGR64CCSubClassMask[] = {
405 0x00000000, 0x00000060, 0x00000000,
406 0x00000001, 0x00000000, 0x0000003e, // sub_64
407};
408
409static const uint32_t FGR64SubClassMask[] = {
410 0x00000000, 0x00000040, 0x00000000,
411 0x00000001, 0x00000000, 0x0000003e, // sub_64
412};
413
414static const uint32_t GPR64SubClassMask[] = {
415 0x00000000, 0x3a7dfd80, 0x00000001,
416};
417
418static const uint32_t GPR64_with_sub_32_in_GPR32NONZEROSubClassMask[] = {
419 0x00000000, 0x1a75cd00, 0x00000001,
420};
421
422static const uint32_t AFGR64SubClassMask[] = {
423 0x00000000, 0x00000200, 0x00000000,
424};
425
426static const uint32_t GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask[] = {
427 0x00000000, 0x02744c00, 0x00000001,
428};
429
430static const uint32_t GPR64_with_sub_32_in_CPU16RegsSubClassMask[] = {
431 0x00000000, 0x02744800, 0x00000000,
432};
433
434static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePSubClassMask[] = {
435 0x00000000, 0x204c9000, 0x00000000,
436};
437
438static const uint32_t GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask[] = {
439 0x00000000, 0x22786000, 0x00000000,
440};
441
442static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
443 0x00000000, 0x02704000, 0x00000000,
444};
445
446static const uint32_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
447 0x00000000, 0x00448000, 0x00000000,
448};
449
450static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask[] = {
451 0x00000000, 0x02110000, 0x00000000,
452};
453
454static const uint32_t ACC64DSPSubClassMask[] = {
455 0x00000000, 0x04020000, 0x00000000,
456 0x00000000, 0x00000000, 0x00000040, // sub_32_sub_hi_then_sub_32
457};
458
459static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
460 0x00000000, 0x00440000, 0x00000000,
461};
462
463static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
464 0x00000000, 0x20480000, 0x00000000,
465};
466
467static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {
468 0x00000000, 0x02100000, 0x00000000,
469};
470
471static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask[] = {
472 0x00000000, 0x02200000, 0x00000000,
473};
474
475static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
476 0x00000000, 0x00400000, 0x00000000,
477};
478
479static const uint32_t OCTEON_MPLSubClassMask[] = {
480 0x00000000, 0x00800000, 0x00000000,
481};
482
483static const uint32_t OCTEON_PSubClassMask[] = {
484 0x00000000, 0x01000000, 0x00000000,
485};
486
487static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {
488 0x00000000, 0x02000000, 0x00000000,
489};
490
491static const uint32_t ACC64SubClassMask[] = {
492 0x00000000, 0x04000000, 0x00000000,
493 0x00000000, 0x00000000, 0x00000040, // sub_32_sub_hi_then_sub_32
494};
495
496static const uint32_t GP64SubClassMask[] = {
497 0x00000000, 0x08000000, 0x00000000,
498};
499
500static const uint32_t GPR64_with_sub_32_in_CPURARegSubClassMask[] = {
501 0x00000000, 0x10000000, 0x00000000,
502};
503
504static const uint32_t GPR64_with_sub_32_in_GPR32ZEROSubClassMask[] = {
505 0x00000000, 0x20000000, 0x00000000,
506};
507
508static const uint32_t HI64SubClassMask[] = {
509 0x00000000, 0x40000000, 0x00000000,
510 0x00000000, 0x00000000, 0x00000040, // sub_hi
511};
512
513static const uint32_t LO64SubClassMask[] = {
514 0x00000000, 0x80000000, 0x00000000,
515 0x00000000, 0x00000000, 0x00000040, // sub_lo
516};
517
518static const uint32_t SP64SubClassMask[] = {
519 0x00000000, 0x00000000, 0x00000001,
520};
521
522static const uint32_t MSA128BSubClassMask[] = {
523 0x00000000, 0x00000000, 0x0000003e,
524};
525
526static const uint32_t MSA128DSubClassMask[] = {
527 0x00000000, 0x00000000, 0x0000003e,
528};
529
530static const uint32_t MSA128HSubClassMask[] = {
531 0x00000000, 0x00000000, 0x0000003e,
532};
533
534static const uint32_t MSA128WSubClassMask[] = {
535 0x00000000, 0x00000000, 0x0000003e,
536};
537
538static const uint32_t MSA128WEvensSubClassMask[] = {
539 0x00000000, 0x00000000, 0x00000020,
540};
541
542static const uint32_t ACC128SubClassMask[] = {
543 0x00000000, 0x00000000, 0x00000040,
544};
545
546static const uint16_t SuperRegIdxSeqs[] = {
547 /* 0 */ 1, 0,
548 /* 2 */ 2, 0,
549 /* 4 */ 8, 0,
550 /* 6 */ 1, 9, 0,
551 /* 9 */ 8, 9, 0,
552 /* 12 */ 1, 8, 10, 0,
553 /* 16 */ 11, 0,
554};
555
556static unsigned const FGR32Superclasses[] = {
557 Mips::FGR32CCRegClassID,
558};
559
560static unsigned const FGR32CCSuperclasses[] = {
561 Mips::FGR32RegClassID,
562};
563
564static unsigned const GPR32Superclasses[] = {
565 Mips::DSPRRegClassID,
566};
567
568static unsigned const GPR32NONZEROSuperclasses[] = {
569 Mips::DSPRRegClassID,
570 Mips::GPR32RegClassID,
571};
572
573static unsigned const CPU16RegsPlusSPSuperclasses[] = {
574 Mips::DSPRRegClassID,
575 Mips::GPR32RegClassID,
576 Mips::GPR32NONZERORegClassID,
577};
578
579static unsigned const CPU16RegsSuperclasses[] = {
580 Mips::DSPRRegClassID,
581 Mips::GPR32RegClassID,
582 Mips::GPR32NONZERORegClassID,
583 Mips::CPU16RegsPlusSPRegClassID,
584};
585
586static unsigned const GPRMM16Superclasses[] = {
587 Mips::DSPRRegClassID,
588 Mips::GPR32RegClassID,
589 Mips::GPR32NONZERORegClassID,
590 Mips::CPU16RegsPlusSPRegClassID,
591 Mips::CPU16RegsRegClassID,
592};
593
594static unsigned const GPRMM16MovePSuperclasses[] = {
595 Mips::DSPRRegClassID,
596 Mips::GPR32RegClassID,
597};
598
599static unsigned const GPRMM16ZeroSuperclasses[] = {
600 Mips::DSPRRegClassID,
601 Mips::GPR32RegClassID,
602};
603
604static unsigned const CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
605 Mips::DSPRRegClassID,
606 Mips::GPR32RegClassID,
607 Mips::GPR32NONZERORegClassID,
608 Mips::CPU16RegsPlusSPRegClassID,
609 Mips::CPU16RegsRegClassID,
610 Mips::GPRMM16RegClassID,
611 Mips::GPRMM16ZeroRegClassID,
612};
613
614static unsigned const GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
615 Mips::DSPRRegClassID,
616 Mips::GPR32RegClassID,
617 Mips::GPR32NONZERORegClassID,
618 Mips::GPRMM16MovePRegClassID,
619};
620
621static unsigned const GPRMM16MovePPairSecondSuperclasses[] = {
622 Mips::DSPRRegClassID,
623 Mips::GPR32RegClassID,
624 Mips::GPR32NONZERORegClassID,
625};
626
627static unsigned const CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
628 Mips::DSPRRegClassID,
629 Mips::GPR32RegClassID,
630 Mips::GPR32NONZERORegClassID,
631 Mips::CPU16RegsPlusSPRegClassID,
632 Mips::CPU16RegsRegClassID,
633 Mips::GPRMM16RegClassID,
634 Mips::GPRMM16MovePRegClassID,
635 Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID,
636};
637
638static unsigned const GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
639 Mips::DSPRRegClassID,
640 Mips::GPR32RegClassID,
641 Mips::GPRMM16MovePRegClassID,
642 Mips::GPRMM16ZeroRegClassID,
643};
644
645static unsigned const CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
646 Mips::DSPRRegClassID,
647 Mips::GPR32RegClassID,
648 Mips::GPR32NONZERORegClassID,
649 Mips::CPU16RegsPlusSPRegClassID,
650 Mips::CPU16RegsRegClassID,
651 Mips::GPRMM16RegClassID,
652 Mips::GPRMM16ZeroRegClassID,
653 Mips::CPU16Regs_and_GPRMM16ZeroRegClassID,
654 Mips::GPRMM16MovePPairSecondRegClassID,
655};
656
657static unsigned const GPRMM16MovePPairFirstSuperclasses[] = {
658 Mips::DSPRRegClassID,
659 Mips::GPR32RegClassID,
660 Mips::GPR32NONZERORegClassID,
661 Mips::CPU16RegsPlusSPRegClassID,
662 Mips::CPU16RegsRegClassID,
663 Mips::GPRMM16RegClassID,
664 Mips::GPRMM16ZeroRegClassID,
665 Mips::CPU16Regs_and_GPRMM16ZeroRegClassID,
666};
667
668static unsigned const GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
669 Mips::DSPRRegClassID,
670 Mips::GPR32RegClassID,
671 Mips::GPR32NONZERORegClassID,
672 Mips::CPU16RegsPlusSPRegClassID,
673 Mips::CPU16RegsRegClassID,
674 Mips::GPRMM16RegClassID,
675 Mips::GPRMM16MovePRegClassID,
676 Mips::GPRMM16ZeroRegClassID,
677 Mips::CPU16Regs_and_GPRMM16ZeroRegClassID,
678 Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID,
679 Mips::CPU16Regs_and_GPRMM16MovePRegClassID,
680 Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID,
681};
682
683static unsigned const GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
684 Mips::DSPRRegClassID,
685 Mips::GPR32RegClassID,
686 Mips::GPR32NONZERORegClassID,
687 Mips::CPU16RegsPlusSPRegClassID,
688 Mips::CPU16RegsRegClassID,
689 Mips::GPRMM16RegClassID,
690 Mips::GPRMM16ZeroRegClassID,
691 Mips::CPU16Regs_and_GPRMM16ZeroRegClassID,
692 Mips::GPRMM16MovePPairSecondRegClassID,
693 Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID,
694 Mips::GPRMM16MovePPairFirstRegClassID,
695};
696
697static unsigned const CPURARegSuperclasses[] = {
698 Mips::DSPRRegClassID,
699 Mips::GPR32RegClassID,
700 Mips::GPR32NONZERORegClassID,
701};
702
703static unsigned const CPUSPRegSuperclasses[] = {
704 Mips::DSPRRegClassID,
705 Mips::GPR32RegClassID,
706 Mips::GPR32NONZERORegClassID,
707 Mips::CPU16RegsPlusSPRegClassID,
708};
709
710static unsigned const GP32Superclasses[] = {
711 Mips::DSPRRegClassID,
712 Mips::GPR32RegClassID,
713 Mips::GPR32NONZERORegClassID,
714};
715
716static unsigned const GPR32ZEROSuperclasses[] = {
717 Mips::DSPRRegClassID,
718 Mips::GPR32RegClassID,
719 Mips::GPRMM16MovePRegClassID,
720 Mips::GPRMM16ZeroRegClassID,
721 Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID,
722};
723
724static unsigned const HI32Superclasses[] = {
725 Mips::HI32DSPRegClassID,
726};
727
728static unsigned const LO32Superclasses[] = {
729 Mips::LO32DSPRegClassID,
730};
731
732static unsigned const SP32Superclasses[] = {
733 Mips::DSPRRegClassID,
734 Mips::GPR32RegClassID,
735 Mips::GPR32NONZERORegClassID,
736 Mips::CPU16RegsPlusSPRegClassID,
737 Mips::CPUSPRegRegClassID,
738};
739
740static unsigned const FGR64Superclasses[] = {
741 Mips::FGR64CCRegClassID,
742};
743
744static unsigned const GPR64_with_sub_32_in_GPR32NONZEROSuperclasses[] = {
745 Mips::GPR64RegClassID,
746};
747
748static unsigned const GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses[] = {
749 Mips::GPR64RegClassID,
750 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
751};
752
753static unsigned const GPR64_with_sub_32_in_CPU16RegsSuperclasses[] = {
754 Mips::GPR64RegClassID,
755 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
756 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
757};
758
759static unsigned const GPR64_with_sub_32_in_GPRMM16MovePSuperclasses[] = {
760 Mips::GPR64RegClassID,
761};
762
763static unsigned const GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses[] = {
764 Mips::GPR64RegClassID,
765};
766
767static unsigned const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
768 Mips::GPR64RegClassID,
769 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
770 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
771 Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
772 Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
773};
774
775static unsigned const GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
776 Mips::GPR64RegClassID,
777 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
778 Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
779};
780
781static unsigned const GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses[] = {
782 Mips::GPR64RegClassID,
783 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
784};
785
786static unsigned const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
787 Mips::GPR64RegClassID,
788 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
789 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
790 Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
791 Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
792 Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID,
793};
794
795static unsigned const GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
796 Mips::GPR64RegClassID,
797 Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
798 Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
799};
800
801static unsigned const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
802 Mips::GPR64RegClassID,
803 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
804 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
805 Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
806 Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
807 Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID,
808 Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID,
809};
810
811static unsigned const GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses[] = {
812 Mips::GPR64RegClassID,
813 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
814 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
815 Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
816 Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
817 Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID,
818};
819
820static unsigned const GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
821 Mips::GPR64RegClassID,
822 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
823 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
824 Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
825 Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
826 Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
827 Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID,
828 Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID,
829 Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID,
830 Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID,
831};
832
833static unsigned const GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
834 Mips::GPR64RegClassID,
835 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
836 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
837 Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
838 Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
839 Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID,
840 Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID,
841 Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID,
842 Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID,
843};
844
845static unsigned const ACC64Superclasses[] = {
846 Mips::ACC64DSPRegClassID,
847};
848
849static unsigned const GP64Superclasses[] = {
850 Mips::GPR64RegClassID,
851 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
852};
853
854static unsigned const GPR64_with_sub_32_in_CPURARegSuperclasses[] = {
855 Mips::GPR64RegClassID,
856 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
857};
858
859static unsigned const GPR64_with_sub_32_in_GPR32ZEROSuperclasses[] = {
860 Mips::GPR64RegClassID,
861 Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
862 Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
863 Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID,
864};
865
866static unsigned const SP64Superclasses[] = {
867 Mips::GPR64RegClassID,
868 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
869 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
870};
871
872static unsigned const MSA128BSuperclasses[] = {
873 Mips::MSA128F16RegClassID,
874 Mips::MSA128DRegClassID,
875 Mips::MSA128HRegClassID,
876 Mips::MSA128WRegClassID,
877};
878
879static unsigned const MSA128DSuperclasses[] = {
880 Mips::MSA128F16RegClassID,
881 Mips::MSA128BRegClassID,
882 Mips::MSA128HRegClassID,
883 Mips::MSA128WRegClassID,
884};
885
886static unsigned const MSA128HSuperclasses[] = {
887 Mips::MSA128F16RegClassID,
888 Mips::MSA128BRegClassID,
889 Mips::MSA128DRegClassID,
890 Mips::MSA128WRegClassID,
891};
892
893static unsigned const MSA128WSuperclasses[] = {
894 Mips::MSA128F16RegClassID,
895 Mips::MSA128BRegClassID,
896 Mips::MSA128DRegClassID,
897 Mips::MSA128HRegClassID,
898};
899
900static unsigned const MSA128WEvensSuperclasses[] = {
901 Mips::MSA128F16RegClassID,
902 Mips::MSA128BRegClassID,
903 Mips::MSA128DRegClassID,
904 Mips::MSA128HRegClassID,
905 Mips::MSA128WRegClassID,
906};
907
908
909static inline unsigned FGR32AltOrderSelect(const MachineFunction &MF, bool Rev) {
910 const auto & S = MF.getSubtarget<MipsSubtarget>();
911 return S.isABI_O32() && !S.useOddSPReg();
912 }
913
914static ArrayRef<MCPhysReg> FGR32GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
915 static const MCPhysReg AltOrder1[] = { Mips::F0, Mips::F2, Mips::F4, Mips::F6, Mips::F8, Mips::F10, Mips::F12, Mips::F14, Mips::F16, Mips::F18, Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30 };
916 const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR32RegClassID];
917 const ArrayRef<MCPhysReg> Order[] = {
918 ArrayRef(MCR.begin(), MCR.getNumRegs()),
919 ArrayRef(AltOrder1)
920 };
921 const unsigned Select = FGR32AltOrderSelect(MF, Rev);
922 assert(Select < 2);
923 return Order[Select];
924}
925
926static inline unsigned FGR64AltOrderSelect(const MachineFunction &MF, bool Rev) {
927 const auto & S = MF.getSubtarget<MipsSubtarget>();
928 return S.isABI_O32() && !S.useOddSPReg();
929 }
930
931static ArrayRef<MCPhysReg> FGR64GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
932 static const MCPhysReg AltOrder1[] = { Mips::D0_64, Mips::D2_64, Mips::D4_64, Mips::D6_64, Mips::D8_64, Mips::D10_64, Mips::D12_64, Mips::D14_64, Mips::D16_64, Mips::D18_64, Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64 };
933 const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR64RegClassID];
934 const ArrayRef<MCPhysReg> Order[] = {
935 ArrayRef(MCR.begin(), MCR.getNumRegs()),
936 ArrayRef(AltOrder1)
937 };
938 const unsigned Select = FGR64AltOrderSelect(MF, Rev);
939 assert(Select < 2);
940 return Order[Select];
941}
942
943namespace Mips { // Register class instances
944 extern const TargetRegisterClass MSA128F16RegClass = {
945 .MC: &MipsMCRegisterClasses[MSA128F16RegClassID],
946 .SubClassMask: MSA128F16SubClassMask,
947 .SuperRegIndices: SuperRegIdxSeqs + 1,
948 .LaneMask: LaneBitmask(0x0000000000000041),
949 .AllocationPriority: 0,
950 .GlobalPriority: false,
951 .TSFlags: 0x00, /* TSFlags */
952 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
953 .CoveredBySubRegs: false, /* CoveredBySubRegs */
954 .SuperClasses: nullptr, .SuperClassesSize: 0,
955 .OrderFunc: nullptr
956 };
957
958 extern const TargetRegisterClass CCRRegClass = {
959 .MC: &MipsMCRegisterClasses[CCRRegClassID],
960 .SubClassMask: CCRSubClassMask,
961 .SuperRegIndices: SuperRegIdxSeqs + 1,
962 .LaneMask: LaneBitmask(0x0000000000000001),
963 .AllocationPriority: 0,
964 .GlobalPriority: false,
965 .TSFlags: 0x00, /* TSFlags */
966 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
967 .CoveredBySubRegs: false, /* CoveredBySubRegs */
968 .SuperClasses: nullptr, .SuperClassesSize: 0,
969 .OrderFunc: nullptr
970 };
971
972 extern const TargetRegisterClass COP0RegClass = {
973 .MC: &MipsMCRegisterClasses[COP0RegClassID],
974 .SubClassMask: COP0SubClassMask,
975 .SuperRegIndices: SuperRegIdxSeqs + 1,
976 .LaneMask: LaneBitmask(0x0000000000000001),
977 .AllocationPriority: 0,
978 .GlobalPriority: false,
979 .TSFlags: 0x00, /* TSFlags */
980 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
981 .CoveredBySubRegs: false, /* CoveredBySubRegs */
982 .SuperClasses: nullptr, .SuperClassesSize: 0,
983 .OrderFunc: nullptr
984 };
985
986 extern const TargetRegisterClass COP2RegClass = {
987 .MC: &MipsMCRegisterClasses[COP2RegClassID],
988 .SubClassMask: COP2SubClassMask,
989 .SuperRegIndices: SuperRegIdxSeqs + 1,
990 .LaneMask: LaneBitmask(0x0000000000000001),
991 .AllocationPriority: 0,
992 .GlobalPriority: false,
993 .TSFlags: 0x00, /* TSFlags */
994 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
995 .CoveredBySubRegs: false, /* CoveredBySubRegs */
996 .SuperClasses: nullptr, .SuperClassesSize: 0,
997 .OrderFunc: nullptr
998 };
999
1000 extern const TargetRegisterClass COP3RegClass = {
1001 .MC: &MipsMCRegisterClasses[COP3RegClassID],
1002 .SubClassMask: COP3SubClassMask,
1003 .SuperRegIndices: SuperRegIdxSeqs + 1,
1004 .LaneMask: LaneBitmask(0x0000000000000001),
1005 .AllocationPriority: 0,
1006 .GlobalPriority: false,
1007 .TSFlags: 0x00, /* TSFlags */
1008 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1009 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1010 .SuperClasses: nullptr, .SuperClassesSize: 0,
1011 .OrderFunc: nullptr
1012 };
1013
1014 extern const TargetRegisterClass DSPRRegClass = {
1015 .MC: &MipsMCRegisterClasses[DSPRRegClassID],
1016 .SubClassMask: DSPRSubClassMask,
1017 .SuperRegIndices: SuperRegIdxSeqs + 0,
1018 .LaneMask: LaneBitmask(0x0000000000000001),
1019 .AllocationPriority: 0,
1020 .GlobalPriority: false,
1021 .TSFlags: 0x00, /* TSFlags */
1022 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1023 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1024 .SuperClasses: nullptr, .SuperClassesSize: 0,
1025 .OrderFunc: nullptr
1026 };
1027
1028 extern const TargetRegisterClass FGR32RegClass = {
1029 .MC: &MipsMCRegisterClasses[FGR32RegClassID],
1030 .SubClassMask: FGR32SubClassMask,
1031 .SuperRegIndices: SuperRegIdxSeqs + 9,
1032 .LaneMask: LaneBitmask(0x0000000000000001),
1033 .AllocationPriority: 0,
1034 .GlobalPriority: false,
1035 .TSFlags: 0x00, /* TSFlags */
1036 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1037 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1038 .SuperClasses: FGR32Superclasses, .SuperClassesSize: 1,
1039 .OrderFunc: FGR32GetRawAllocationOrder
1040 };
1041
1042 extern const TargetRegisterClass FGR32CCRegClass = {
1043 .MC: &MipsMCRegisterClasses[FGR32CCRegClassID],
1044 .SubClassMask: FGR32CCSubClassMask,
1045 .SuperRegIndices: SuperRegIdxSeqs + 9,
1046 .LaneMask: LaneBitmask(0x0000000000000001),
1047 .AllocationPriority: 0,
1048 .GlobalPriority: false,
1049 .TSFlags: 0x00, /* TSFlags */
1050 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1051 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1052 .SuperClasses: FGR32CCSuperclasses, .SuperClassesSize: 1,
1053 .OrderFunc: nullptr
1054 };
1055
1056 extern const TargetRegisterClass GPR32RegClass = {
1057 .MC: &MipsMCRegisterClasses[GPR32RegClassID],
1058 .SubClassMask: GPR32SubClassMask,
1059 .SuperRegIndices: SuperRegIdxSeqs + 0,
1060 .LaneMask: LaneBitmask(0x0000000000000001),
1061 .AllocationPriority: 0,
1062 .GlobalPriority: false,
1063 .TSFlags: 0x00, /* TSFlags */
1064 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1065 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1066 .SuperClasses: GPR32Superclasses, .SuperClassesSize: 1,
1067 .OrderFunc: nullptr
1068 };
1069
1070 extern const TargetRegisterClass HWRegsRegClass = {
1071 .MC: &MipsMCRegisterClasses[HWRegsRegClassID],
1072 .SubClassMask: HWRegsSubClassMask,
1073 .SuperRegIndices: SuperRegIdxSeqs + 1,
1074 .LaneMask: LaneBitmask(0x0000000000000001),
1075 .AllocationPriority: 0,
1076 .GlobalPriority: false,
1077 .TSFlags: 0x00, /* TSFlags */
1078 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1079 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1080 .SuperClasses: nullptr, .SuperClassesSize: 0,
1081 .OrderFunc: nullptr
1082 };
1083
1084 extern const TargetRegisterClass MSACtrlRegClass = {
1085 .MC: &MipsMCRegisterClasses[MSACtrlRegClassID],
1086 .SubClassMask: MSACtrlSubClassMask,
1087 .SuperRegIndices: SuperRegIdxSeqs + 1,
1088 .LaneMask: LaneBitmask(0x0000000000000001),
1089 .AllocationPriority: 0,
1090 .GlobalPriority: false,
1091 .TSFlags: 0x00, /* TSFlags */
1092 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1093 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1094 .SuperClasses: nullptr, .SuperClassesSize: 0,
1095 .OrderFunc: nullptr
1096 };
1097
1098 extern const TargetRegisterClass GPR32NONZERORegClass = {
1099 .MC: &MipsMCRegisterClasses[GPR32NONZERORegClassID],
1100 .SubClassMask: GPR32NONZEROSubClassMask,
1101 .SuperRegIndices: SuperRegIdxSeqs + 0,
1102 .LaneMask: LaneBitmask(0x0000000000000001),
1103 .AllocationPriority: 0,
1104 .GlobalPriority: false,
1105 .TSFlags: 0x00, /* TSFlags */
1106 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1107 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1108 .SuperClasses: GPR32NONZEROSuperclasses, .SuperClassesSize: 2,
1109 .OrderFunc: nullptr
1110 };
1111
1112 extern const TargetRegisterClass CPU16RegsPlusSPRegClass = {
1113 .MC: &MipsMCRegisterClasses[CPU16RegsPlusSPRegClassID],
1114 .SubClassMask: CPU16RegsPlusSPSubClassMask,
1115 .SuperRegIndices: SuperRegIdxSeqs + 0,
1116 .LaneMask: LaneBitmask(0x0000000000000001),
1117 .AllocationPriority: 0,
1118 .GlobalPriority: false,
1119 .TSFlags: 0x00, /* TSFlags */
1120 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1121 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1122 .SuperClasses: CPU16RegsPlusSPSuperclasses, .SuperClassesSize: 3,
1123 .OrderFunc: nullptr
1124 };
1125
1126 extern const TargetRegisterClass CPU16RegsRegClass = {
1127 .MC: &MipsMCRegisterClasses[CPU16RegsRegClassID],
1128 .SubClassMask: CPU16RegsSubClassMask,
1129 .SuperRegIndices: SuperRegIdxSeqs + 0,
1130 .LaneMask: LaneBitmask(0x0000000000000001),
1131 .AllocationPriority: 0,
1132 .GlobalPriority: false,
1133 .TSFlags: 0x00, /* TSFlags */
1134 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1135 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1136 .SuperClasses: CPU16RegsSuperclasses, .SuperClassesSize: 4,
1137 .OrderFunc: nullptr
1138 };
1139
1140 extern const TargetRegisterClass FCCRegClass = {
1141 .MC: &MipsMCRegisterClasses[FCCRegClassID],
1142 .SubClassMask: FCCSubClassMask,
1143 .SuperRegIndices: SuperRegIdxSeqs + 1,
1144 .LaneMask: LaneBitmask(0x0000000000000001),
1145 .AllocationPriority: 0,
1146 .GlobalPriority: false,
1147 .TSFlags: 0x00, /* TSFlags */
1148 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1149 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1150 .SuperClasses: nullptr, .SuperClassesSize: 0,
1151 .OrderFunc: nullptr
1152 };
1153
1154 extern const TargetRegisterClass GPRMM16RegClass = {
1155 .MC: &MipsMCRegisterClasses[GPRMM16RegClassID],
1156 .SubClassMask: GPRMM16SubClassMask,
1157 .SuperRegIndices: SuperRegIdxSeqs + 0,
1158 .LaneMask: LaneBitmask(0x0000000000000001),
1159 .AllocationPriority: 0,
1160 .GlobalPriority: false,
1161 .TSFlags: 0x00, /* TSFlags */
1162 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1163 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1164 .SuperClasses: GPRMM16Superclasses, .SuperClassesSize: 5,
1165 .OrderFunc: nullptr
1166 };
1167
1168 extern const TargetRegisterClass GPRMM16MovePRegClass = {
1169 .MC: &MipsMCRegisterClasses[GPRMM16MovePRegClassID],
1170 .SubClassMask: GPRMM16MovePSubClassMask,
1171 .SuperRegIndices: SuperRegIdxSeqs + 0,
1172 .LaneMask: LaneBitmask(0x0000000000000001),
1173 .AllocationPriority: 0,
1174 .GlobalPriority: false,
1175 .TSFlags: 0x00, /* TSFlags */
1176 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1177 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1178 .SuperClasses: GPRMM16MovePSuperclasses, .SuperClassesSize: 2,
1179 .OrderFunc: nullptr
1180 };
1181
1182 extern const TargetRegisterClass GPRMM16ZeroRegClass = {
1183 .MC: &MipsMCRegisterClasses[GPRMM16ZeroRegClassID],
1184 .SubClassMask: GPRMM16ZeroSubClassMask,
1185 .SuperRegIndices: SuperRegIdxSeqs + 0,
1186 .LaneMask: LaneBitmask(0x0000000000000001),
1187 .AllocationPriority: 0,
1188 .GlobalPriority: false,
1189 .TSFlags: 0x00, /* TSFlags */
1190 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1191 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1192 .SuperClasses: GPRMM16ZeroSuperclasses, .SuperClassesSize: 2,
1193 .OrderFunc: nullptr
1194 };
1195
1196 extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass = {
1197 .MC: &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16ZeroRegClassID],
1198 .SubClassMask: CPU16Regs_and_GPRMM16ZeroSubClassMask,
1199 .SuperRegIndices: SuperRegIdxSeqs + 0,
1200 .LaneMask: LaneBitmask(0x0000000000000001),
1201 .AllocationPriority: 0,
1202 .GlobalPriority: false,
1203 .TSFlags: 0x00, /* TSFlags */
1204 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1205 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1206 .SuperClasses: CPU16Regs_and_GPRMM16ZeroSuperclasses, .SuperClassesSize: 7,
1207 .OrderFunc: nullptr
1208 };
1209
1210 extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass = {
1211 .MC: &MipsMCRegisterClasses[GPR32NONZERO_and_GPRMM16MovePRegClassID],
1212 .SubClassMask: GPR32NONZERO_and_GPRMM16MovePSubClassMask,
1213 .SuperRegIndices: SuperRegIdxSeqs + 0,
1214 .LaneMask: LaneBitmask(0x0000000000000001),
1215 .AllocationPriority: 0,
1216 .GlobalPriority: false,
1217 .TSFlags: 0x00, /* TSFlags */
1218 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1219 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1220 .SuperClasses: GPR32NONZERO_and_GPRMM16MovePSuperclasses, .SuperClassesSize: 4,
1221 .OrderFunc: nullptr
1222 };
1223
1224 extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass = {
1225 .MC: &MipsMCRegisterClasses[GPRMM16MovePPairSecondRegClassID],
1226 .SubClassMask: GPRMM16MovePPairSecondSubClassMask,
1227 .SuperRegIndices: SuperRegIdxSeqs + 0,
1228 .LaneMask: LaneBitmask(0x0000000000000001),
1229 .AllocationPriority: 0,
1230 .GlobalPriority: false,
1231 .TSFlags: 0x00, /* TSFlags */
1232 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1233 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1234 .SuperClasses: GPRMM16MovePPairSecondSuperclasses, .SuperClassesSize: 3,
1235 .OrderFunc: nullptr
1236 };
1237
1238 extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass = {
1239 .MC: &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePRegClassID],
1240 .SubClassMask: CPU16Regs_and_GPRMM16MovePSubClassMask,
1241 .SuperRegIndices: SuperRegIdxSeqs + 0,
1242 .LaneMask: LaneBitmask(0x0000000000000001),
1243 .AllocationPriority: 0,
1244 .GlobalPriority: false,
1245 .TSFlags: 0x00, /* TSFlags */
1246 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1247 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1248 .SuperClasses: CPU16Regs_and_GPRMM16MovePSuperclasses, .SuperClassesSize: 8,
1249 .OrderFunc: nullptr
1250 };
1251
1252 extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
1253 .MC: &MipsMCRegisterClasses[GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
1254 .SubClassMask: GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
1255 .SuperRegIndices: SuperRegIdxSeqs + 0,
1256 .LaneMask: LaneBitmask(0x0000000000000001),
1257 .AllocationPriority: 0,
1258 .GlobalPriority: false,
1259 .TSFlags: 0x00, /* TSFlags */
1260 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1261 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1262 .SuperClasses: GPRMM16MoveP_and_GPRMM16ZeroSuperclasses, .SuperClassesSize: 4,
1263 .OrderFunc: nullptr
1264 };
1265
1266 extern const TargetRegisterClass HI32DSPRegClass = {
1267 .MC: &MipsMCRegisterClasses[HI32DSPRegClassID],
1268 .SubClassMask: HI32DSPSubClassMask,
1269 .SuperRegIndices: SuperRegIdxSeqs + 12,
1270 .LaneMask: LaneBitmask(0x0000000000000001),
1271 .AllocationPriority: 0,
1272 .GlobalPriority: false,
1273 .TSFlags: 0x00, /* TSFlags */
1274 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1275 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1276 .SuperClasses: nullptr, .SuperClassesSize: 0,
1277 .OrderFunc: nullptr
1278 };
1279
1280 extern const TargetRegisterClass LO32DSPRegClass = {
1281 .MC: &MipsMCRegisterClasses[LO32DSPRegClassID],
1282 .SubClassMask: LO32DSPSubClassMask,
1283 .SuperRegIndices: SuperRegIdxSeqs + 6,
1284 .LaneMask: LaneBitmask(0x0000000000000001),
1285 .AllocationPriority: 0,
1286 .GlobalPriority: false,
1287 .TSFlags: 0x00, /* TSFlags */
1288 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1289 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1290 .SuperClasses: nullptr, .SuperClassesSize: 0,
1291 .OrderFunc: nullptr
1292 };
1293
1294 extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
1295 .MC: &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],
1296 .SubClassMask: CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,
1297 .SuperRegIndices: SuperRegIdxSeqs + 0,
1298 .LaneMask: LaneBitmask(0x0000000000000001),
1299 .AllocationPriority: 0,
1300 .GlobalPriority: false,
1301 .TSFlags: 0x00, /* TSFlags */
1302 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1303 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1304 .SuperClasses: CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses, .SuperClassesSize: 9,
1305 .OrderFunc: nullptr
1306 };
1307
1308 extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass = {
1309 .MC: &MipsMCRegisterClasses[GPRMM16MovePPairFirstRegClassID],
1310 .SubClassMask: GPRMM16MovePPairFirstSubClassMask,
1311 .SuperRegIndices: SuperRegIdxSeqs + 0,
1312 .LaneMask: LaneBitmask(0x0000000000000001),
1313 .AllocationPriority: 0,
1314 .GlobalPriority: false,
1315 .TSFlags: 0x00, /* TSFlags */
1316 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1317 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1318 .SuperClasses: GPRMM16MovePPairFirstSuperclasses, .SuperClassesSize: 8,
1319 .OrderFunc: nullptr
1320 };
1321
1322 extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
1323 .MC: &MipsMCRegisterClasses[GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
1324 .SubClassMask: GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
1325 .SuperRegIndices: SuperRegIdxSeqs + 0,
1326 .LaneMask: LaneBitmask(0x0000000000000001),
1327 .AllocationPriority: 0,
1328 .GlobalPriority: false,
1329 .TSFlags: 0x00, /* TSFlags */
1330 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1331 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1332 .SuperClasses: GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses, .SuperClassesSize: 12,
1333 .OrderFunc: nullptr
1334 };
1335
1336 extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
1337 .MC: &MipsMCRegisterClasses[GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],
1338 .SubClassMask: GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,
1339 .SuperRegIndices: SuperRegIdxSeqs + 0,
1340 .LaneMask: LaneBitmask(0x0000000000000001),
1341 .AllocationPriority: 0,
1342 .GlobalPriority: false,
1343 .TSFlags: 0x00, /* TSFlags */
1344 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1345 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1346 .SuperClasses: GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses, .SuperClassesSize: 11,
1347 .OrderFunc: nullptr
1348 };
1349
1350 extern const TargetRegisterClass CPURARegRegClass = {
1351 .MC: &MipsMCRegisterClasses[CPURARegRegClassID],
1352 .SubClassMask: CPURARegSubClassMask,
1353 .SuperRegIndices: SuperRegIdxSeqs + 0,
1354 .LaneMask: LaneBitmask(0x0000000000000001),
1355 .AllocationPriority: 0,
1356 .GlobalPriority: false,
1357 .TSFlags: 0x00, /* TSFlags */
1358 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1359 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1360 .SuperClasses: CPURARegSuperclasses, .SuperClassesSize: 3,
1361 .OrderFunc: nullptr
1362 };
1363
1364 extern const TargetRegisterClass CPUSPRegRegClass = {
1365 .MC: &MipsMCRegisterClasses[CPUSPRegRegClassID],
1366 .SubClassMask: CPUSPRegSubClassMask,
1367 .SuperRegIndices: SuperRegIdxSeqs + 0,
1368 .LaneMask: LaneBitmask(0x0000000000000001),
1369 .AllocationPriority: 0,
1370 .GlobalPriority: false,
1371 .TSFlags: 0x00, /* TSFlags */
1372 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1373 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1374 .SuperClasses: CPUSPRegSuperclasses, .SuperClassesSize: 4,
1375 .OrderFunc: nullptr
1376 };
1377
1378 extern const TargetRegisterClass DSPCCRegClass = {
1379 .MC: &MipsMCRegisterClasses[DSPCCRegClassID],
1380 .SubClassMask: DSPCCSubClassMask,
1381 .SuperRegIndices: SuperRegIdxSeqs + 1,
1382 .LaneMask: LaneBitmask(0x0000000000000001),
1383 .AllocationPriority: 0,
1384 .GlobalPriority: false,
1385 .TSFlags: 0x00, /* TSFlags */
1386 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1387 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1388 .SuperClasses: nullptr, .SuperClassesSize: 0,
1389 .OrderFunc: nullptr
1390 };
1391
1392 extern const TargetRegisterClass GP32RegClass = {
1393 .MC: &MipsMCRegisterClasses[GP32RegClassID],
1394 .SubClassMask: GP32SubClassMask,
1395 .SuperRegIndices: SuperRegIdxSeqs + 0,
1396 .LaneMask: LaneBitmask(0x0000000000000001),
1397 .AllocationPriority: 0,
1398 .GlobalPriority: false,
1399 .TSFlags: 0x00, /* TSFlags */
1400 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1401 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1402 .SuperClasses: GP32Superclasses, .SuperClassesSize: 3,
1403 .OrderFunc: nullptr
1404 };
1405
1406 extern const TargetRegisterClass GPR32ZERORegClass = {
1407 .MC: &MipsMCRegisterClasses[GPR32ZERORegClassID],
1408 .SubClassMask: GPR32ZEROSubClassMask,
1409 .SuperRegIndices: SuperRegIdxSeqs + 0,
1410 .LaneMask: LaneBitmask(0x0000000000000001),
1411 .AllocationPriority: 0,
1412 .GlobalPriority: false,
1413 .TSFlags: 0x00, /* TSFlags */
1414 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1415 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1416 .SuperClasses: GPR32ZEROSuperclasses, .SuperClassesSize: 5,
1417 .OrderFunc: nullptr
1418 };
1419
1420 extern const TargetRegisterClass HI32RegClass = {
1421 .MC: &MipsMCRegisterClasses[HI32RegClassID],
1422 .SubClassMask: HI32SubClassMask,
1423 .SuperRegIndices: SuperRegIdxSeqs + 12,
1424 .LaneMask: LaneBitmask(0x0000000000000001),
1425 .AllocationPriority: 0,
1426 .GlobalPriority: false,
1427 .TSFlags: 0x00, /* TSFlags */
1428 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1429 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1430 .SuperClasses: HI32Superclasses, .SuperClassesSize: 1,
1431 .OrderFunc: nullptr
1432 };
1433
1434 extern const TargetRegisterClass LO32RegClass = {
1435 .MC: &MipsMCRegisterClasses[LO32RegClassID],
1436 .SubClassMask: LO32SubClassMask,
1437 .SuperRegIndices: SuperRegIdxSeqs + 6,
1438 .LaneMask: LaneBitmask(0x0000000000000001),
1439 .AllocationPriority: 0,
1440 .GlobalPriority: false,
1441 .TSFlags: 0x00, /* TSFlags */
1442 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1443 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1444 .SuperClasses: LO32Superclasses, .SuperClassesSize: 1,
1445 .OrderFunc: nullptr
1446 };
1447
1448 extern const TargetRegisterClass SP32RegClass = {
1449 .MC: &MipsMCRegisterClasses[SP32RegClassID],
1450 .SubClassMask: SP32SubClassMask,
1451 .SuperRegIndices: SuperRegIdxSeqs + 0,
1452 .LaneMask: LaneBitmask(0x0000000000000001),
1453 .AllocationPriority: 0,
1454 .GlobalPriority: false,
1455 .TSFlags: 0x00, /* TSFlags */
1456 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1457 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1458 .SuperClasses: SP32Superclasses, .SuperClassesSize: 5,
1459 .OrderFunc: nullptr
1460 };
1461
1462 extern const TargetRegisterClass FGR64CCRegClass = {
1463 .MC: &MipsMCRegisterClasses[FGR64CCRegClassID],
1464 .SubClassMask: FGR64CCSubClassMask,
1465 .SuperRegIndices: SuperRegIdxSeqs + 2,
1466 .LaneMask: LaneBitmask(0x0000000000000041),
1467 .AllocationPriority: 0,
1468 .GlobalPriority: false,
1469 .TSFlags: 0x00, /* TSFlags */
1470 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1471 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1472 .SuperClasses: nullptr, .SuperClassesSize: 0,
1473 .OrderFunc: nullptr
1474 };
1475
1476 extern const TargetRegisterClass FGR64RegClass = {
1477 .MC: &MipsMCRegisterClasses[FGR64RegClassID],
1478 .SubClassMask: FGR64SubClassMask,
1479 .SuperRegIndices: SuperRegIdxSeqs + 2,
1480 .LaneMask: LaneBitmask(0x0000000000000041),
1481 .AllocationPriority: 0,
1482 .GlobalPriority: false,
1483 .TSFlags: 0x00, /* TSFlags */
1484 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1485 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1486 .SuperClasses: FGR64Superclasses, .SuperClassesSize: 1,
1487 .OrderFunc: FGR64GetRawAllocationOrder
1488 };
1489
1490 extern const TargetRegisterClass GPR64RegClass = {
1491 .MC: &MipsMCRegisterClasses[GPR64RegClassID],
1492 .SubClassMask: GPR64SubClassMask,
1493 .SuperRegIndices: SuperRegIdxSeqs + 1,
1494 .LaneMask: LaneBitmask(0x0000000000000001),
1495 .AllocationPriority: 0,
1496 .GlobalPriority: false,
1497 .TSFlags: 0x00, /* TSFlags */
1498 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1499 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1500 .SuperClasses: nullptr, .SuperClassesSize: 0,
1501 .OrderFunc: nullptr
1502 };
1503
1504 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass = {
1505 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERORegClassID],
1506 .SubClassMask: GPR64_with_sub_32_in_GPR32NONZEROSubClassMask,
1507 .SuperRegIndices: SuperRegIdxSeqs + 1,
1508 .LaneMask: LaneBitmask(0x0000000000000001),
1509 .AllocationPriority: 0,
1510 .GlobalPriority: false,
1511 .TSFlags: 0x00, /* TSFlags */
1512 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1513 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1514 .SuperClasses: GPR64_with_sub_32_in_GPR32NONZEROSuperclasses, .SuperClassesSize: 1,
1515 .OrderFunc: nullptr
1516 };
1517
1518 extern const TargetRegisterClass AFGR64RegClass = {
1519 .MC: &MipsMCRegisterClasses[AFGR64RegClassID],
1520 .SubClassMask: AFGR64SubClassMask,
1521 .SuperRegIndices: SuperRegIdxSeqs + 1,
1522 .LaneMask: LaneBitmask(0x0000000000000041),
1523 .AllocationPriority: 0,
1524 .GlobalPriority: false,
1525 .TSFlags: 0x00, /* TSFlags */
1526 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1527 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1528 .SuperClasses: nullptr, .SuperClassesSize: 0,
1529 .OrderFunc: nullptr
1530 };
1531
1532 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass = {
1533 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID],
1534 .SubClassMask: GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask,
1535 .SuperRegIndices: SuperRegIdxSeqs + 1,
1536 .LaneMask: LaneBitmask(0x0000000000000001),
1537 .AllocationPriority: 0,
1538 .GlobalPriority: false,
1539 .TSFlags: 0x00, /* TSFlags */
1540 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1541 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1542 .SuperClasses: GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses, .SuperClassesSize: 2,
1543 .OrderFunc: nullptr
1544 };
1545
1546 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass = {
1547 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsRegClassID],
1548 .SubClassMask: GPR64_with_sub_32_in_CPU16RegsSubClassMask,
1549 .SuperRegIndices: SuperRegIdxSeqs + 1,
1550 .LaneMask: LaneBitmask(0x0000000000000001),
1551 .AllocationPriority: 0,
1552 .GlobalPriority: false,
1553 .TSFlags: 0x00, /* TSFlags */
1554 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1555 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1556 .SuperClasses: GPR64_with_sub_32_in_CPU16RegsSuperclasses, .SuperClassesSize: 3,
1557 .OrderFunc: nullptr
1558 };
1559
1560 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass = {
1561 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePRegClassID],
1562 .SubClassMask: GPR64_with_sub_32_in_GPRMM16MovePSubClassMask,
1563 .SuperRegIndices: SuperRegIdxSeqs + 1,
1564 .LaneMask: LaneBitmask(0x0000000000000001),
1565 .AllocationPriority: 0,
1566 .GlobalPriority: false,
1567 .TSFlags: 0x00, /* TSFlags */
1568 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1569 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1570 .SuperClasses: GPR64_with_sub_32_in_GPRMM16MovePSuperclasses, .SuperClassesSize: 1,
1571 .OrderFunc: nullptr
1572 };
1573
1574 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass = {
1575 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16ZeroRegClassID],
1576 .SubClassMask: GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask,
1577 .SuperRegIndices: SuperRegIdxSeqs + 1,
1578 .LaneMask: LaneBitmask(0x0000000000000001),
1579 .AllocationPriority: 0,
1580 .GlobalPriority: false,
1581 .TSFlags: 0x00, /* TSFlags */
1582 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1583 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1584 .SuperClasses: GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses, .SuperClassesSize: 1,
1585 .OrderFunc: nullptr
1586 };
1587
1588 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass = {
1589 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID],
1590 .SubClassMask: GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask,
1591 .SuperRegIndices: SuperRegIdxSeqs + 1,
1592 .LaneMask: LaneBitmask(0x0000000000000001),
1593 .AllocationPriority: 0,
1594 .GlobalPriority: false,
1595 .TSFlags: 0x00, /* TSFlags */
1596 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1597 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1598 .SuperClasses: GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses, .SuperClassesSize: 5,
1599 .OrderFunc: nullptr
1600 };
1601
1602 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass = {
1603 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID],
1604 .SubClassMask: GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask,
1605 .SuperRegIndices: SuperRegIdxSeqs + 1,
1606 .LaneMask: LaneBitmask(0x0000000000000001),
1607 .AllocationPriority: 0,
1608 .GlobalPriority: false,
1609 .TSFlags: 0x00, /* TSFlags */
1610 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1611 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1612 .SuperClasses: GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses, .SuperClassesSize: 3,
1613 .OrderFunc: nullptr
1614 };
1615
1616 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass = {
1617 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID],
1618 .SubClassMask: GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask,
1619 .SuperRegIndices: SuperRegIdxSeqs + 1,
1620 .LaneMask: LaneBitmask(0x0000000000000001),
1621 .AllocationPriority: 0,
1622 .GlobalPriority: false,
1623 .TSFlags: 0x00, /* TSFlags */
1624 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1625 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1626 .SuperClasses: GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses, .SuperClassesSize: 2,
1627 .OrderFunc: nullptr
1628 };
1629
1630 extern const TargetRegisterClass ACC64DSPRegClass = {
1631 .MC: &MipsMCRegisterClasses[ACC64DSPRegClassID],
1632 .SubClassMask: ACC64DSPSubClassMask,
1633 .SuperRegIndices: SuperRegIdxSeqs + 16,
1634 .LaneMask: LaneBitmask(0x0000000000000041),
1635 .AllocationPriority: 0,
1636 .GlobalPriority: false,
1637 .TSFlags: 0x00, /* TSFlags */
1638 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1639 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1640 .SuperClasses: nullptr, .SuperClassesSize: 0,
1641 .OrderFunc: nullptr
1642 };
1643
1644 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass = {
1645 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID],
1646 .SubClassMask: GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask,
1647 .SuperRegIndices: SuperRegIdxSeqs + 1,
1648 .LaneMask: LaneBitmask(0x0000000000000001),
1649 .AllocationPriority: 0,
1650 .GlobalPriority: false,
1651 .TSFlags: 0x00, /* TSFlags */
1652 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1653 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1654 .SuperClasses: GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses, .SuperClassesSize: 6,
1655 .OrderFunc: nullptr
1656 };
1657
1658 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
1659 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
1660 .SubClassMask: GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
1661 .SuperRegIndices: SuperRegIdxSeqs + 1,
1662 .LaneMask: LaneBitmask(0x0000000000000001),
1663 .AllocationPriority: 0,
1664 .GlobalPriority: false,
1665 .TSFlags: 0x00, /* TSFlags */
1666 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1667 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1668 .SuperClasses: GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses, .SuperClassesSize: 3,
1669 .OrderFunc: nullptr
1670 };
1671
1672 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
1673 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],
1674 .SubClassMask: GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,
1675 .SuperRegIndices: SuperRegIdxSeqs + 1,
1676 .LaneMask: LaneBitmask(0x0000000000000001),
1677 .AllocationPriority: 0,
1678 .GlobalPriority: false,
1679 .TSFlags: 0x00, /* TSFlags */
1680 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1681 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1682 .SuperClasses: GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses, .SuperClassesSize: 7,
1683 .OrderFunc: nullptr
1684 };
1685
1686 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass = {
1687 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID],
1688 .SubClassMask: GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask,
1689 .SuperRegIndices: SuperRegIdxSeqs + 1,
1690 .LaneMask: LaneBitmask(0x0000000000000001),
1691 .AllocationPriority: 0,
1692 .GlobalPriority: false,
1693 .TSFlags: 0x00, /* TSFlags */
1694 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1695 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1696 .SuperClasses: GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses, .SuperClassesSize: 6,
1697 .OrderFunc: nullptr
1698 };
1699
1700 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
1701 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
1702 .SubClassMask: GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
1703 .SuperRegIndices: SuperRegIdxSeqs + 1,
1704 .LaneMask: LaneBitmask(0x0000000000000001),
1705 .AllocationPriority: 0,
1706 .GlobalPriority: false,
1707 .TSFlags: 0x00, /* TSFlags */
1708 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1709 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1710 .SuperClasses: GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses, .SuperClassesSize: 10,
1711 .OrderFunc: nullptr
1712 };
1713
1714 extern const TargetRegisterClass OCTEON_MPLRegClass = {
1715 .MC: &MipsMCRegisterClasses[OCTEON_MPLRegClassID],
1716 .SubClassMask: OCTEON_MPLSubClassMask,
1717 .SuperRegIndices: SuperRegIdxSeqs + 1,
1718 .LaneMask: LaneBitmask(0x0000000000000001),
1719 .AllocationPriority: 0,
1720 .GlobalPriority: false,
1721 .TSFlags: 0x00, /* TSFlags */
1722 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1723 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1724 .SuperClasses: nullptr, .SuperClassesSize: 0,
1725 .OrderFunc: nullptr
1726 };
1727
1728 extern const TargetRegisterClass OCTEON_PRegClass = {
1729 .MC: &MipsMCRegisterClasses[OCTEON_PRegClassID],
1730 .SubClassMask: OCTEON_PSubClassMask,
1731 .SuperRegIndices: SuperRegIdxSeqs + 1,
1732 .LaneMask: LaneBitmask(0x0000000000000001),
1733 .AllocationPriority: 0,
1734 .GlobalPriority: false,
1735 .TSFlags: 0x00, /* TSFlags */
1736 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1737 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1738 .SuperClasses: nullptr, .SuperClassesSize: 0,
1739 .OrderFunc: nullptr
1740 };
1741
1742 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
1743 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],
1744 .SubClassMask: GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,
1745 .SuperRegIndices: SuperRegIdxSeqs + 1,
1746 .LaneMask: LaneBitmask(0x0000000000000001),
1747 .AllocationPriority: 0,
1748 .GlobalPriority: false,
1749 .TSFlags: 0x00, /* TSFlags */
1750 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1751 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1752 .SuperClasses: GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses, .SuperClassesSize: 9,
1753 .OrderFunc: nullptr
1754 };
1755
1756 extern const TargetRegisterClass ACC64RegClass = {
1757 .MC: &MipsMCRegisterClasses[ACC64RegClassID],
1758 .SubClassMask: ACC64SubClassMask,
1759 .SuperRegIndices: SuperRegIdxSeqs + 16,
1760 .LaneMask: LaneBitmask(0x0000000000000041),
1761 .AllocationPriority: 0,
1762 .GlobalPriority: false,
1763 .TSFlags: 0x00, /* TSFlags */
1764 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1765 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1766 .SuperClasses: ACC64Superclasses, .SuperClassesSize: 1,
1767 .OrderFunc: nullptr
1768 };
1769
1770 extern const TargetRegisterClass GP64RegClass = {
1771 .MC: &MipsMCRegisterClasses[GP64RegClassID],
1772 .SubClassMask: GP64SubClassMask,
1773 .SuperRegIndices: SuperRegIdxSeqs + 1,
1774 .LaneMask: LaneBitmask(0x0000000000000001),
1775 .AllocationPriority: 0,
1776 .GlobalPriority: false,
1777 .TSFlags: 0x00, /* TSFlags */
1778 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1779 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1780 .SuperClasses: GP64Superclasses, .SuperClassesSize: 2,
1781 .OrderFunc: nullptr
1782 };
1783
1784 extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass = {
1785 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPURARegRegClassID],
1786 .SubClassMask: GPR64_with_sub_32_in_CPURARegSubClassMask,
1787 .SuperRegIndices: SuperRegIdxSeqs + 1,
1788 .LaneMask: LaneBitmask(0x0000000000000001),
1789 .AllocationPriority: 0,
1790 .GlobalPriority: false,
1791 .TSFlags: 0x00, /* TSFlags */
1792 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1793 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1794 .SuperClasses: GPR64_with_sub_32_in_CPURARegSuperclasses, .SuperClassesSize: 2,
1795 .OrderFunc: nullptr
1796 };
1797
1798 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass = {
1799 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32ZERORegClassID],
1800 .SubClassMask: GPR64_with_sub_32_in_GPR32ZEROSubClassMask,
1801 .SuperRegIndices: SuperRegIdxSeqs + 1,
1802 .LaneMask: LaneBitmask(0x0000000000000001),
1803 .AllocationPriority: 0,
1804 .GlobalPriority: false,
1805 .TSFlags: 0x00, /* TSFlags */
1806 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1807 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1808 .SuperClasses: GPR64_with_sub_32_in_GPR32ZEROSuperclasses, .SuperClassesSize: 4,
1809 .OrderFunc: nullptr
1810 };
1811
1812 extern const TargetRegisterClass HI64RegClass = {
1813 .MC: &MipsMCRegisterClasses[HI64RegClassID],
1814 .SubClassMask: HI64SubClassMask,
1815 .SuperRegIndices: SuperRegIdxSeqs + 4,
1816 .LaneMask: LaneBitmask(0x0000000000000001),
1817 .AllocationPriority: 0,
1818 .GlobalPriority: false,
1819 .TSFlags: 0x00, /* TSFlags */
1820 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1821 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1822 .SuperClasses: nullptr, .SuperClassesSize: 0,
1823 .OrderFunc: nullptr
1824 };
1825
1826 extern const TargetRegisterClass LO64RegClass = {
1827 .MC: &MipsMCRegisterClasses[LO64RegClassID],
1828 .SubClassMask: LO64SubClassMask,
1829 .SuperRegIndices: SuperRegIdxSeqs + 7,
1830 .LaneMask: LaneBitmask(0x0000000000000001),
1831 .AllocationPriority: 0,
1832 .GlobalPriority: false,
1833 .TSFlags: 0x00, /* TSFlags */
1834 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1835 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1836 .SuperClasses: nullptr, .SuperClassesSize: 0,
1837 .OrderFunc: nullptr
1838 };
1839
1840 extern const TargetRegisterClass SP64RegClass = {
1841 .MC: &MipsMCRegisterClasses[SP64RegClassID],
1842 .SubClassMask: SP64SubClassMask,
1843 .SuperRegIndices: SuperRegIdxSeqs + 1,
1844 .LaneMask: LaneBitmask(0x0000000000000001),
1845 .AllocationPriority: 0,
1846 .GlobalPriority: false,
1847 .TSFlags: 0x00, /* TSFlags */
1848 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1849 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1850 .SuperClasses: SP64Superclasses, .SuperClassesSize: 3,
1851 .OrderFunc: nullptr
1852 };
1853
1854 extern const TargetRegisterClass MSA128BRegClass = {
1855 .MC: &MipsMCRegisterClasses[MSA128BRegClassID],
1856 .SubClassMask: MSA128BSubClassMask,
1857 .SuperRegIndices: SuperRegIdxSeqs + 1,
1858 .LaneMask: LaneBitmask(0x0000000000000041),
1859 .AllocationPriority: 0,
1860 .GlobalPriority: false,
1861 .TSFlags: 0x00, /* TSFlags */
1862 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1863 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1864 .SuperClasses: MSA128BSuperclasses, .SuperClassesSize: 4,
1865 .OrderFunc: nullptr
1866 };
1867
1868 extern const TargetRegisterClass MSA128DRegClass = {
1869 .MC: &MipsMCRegisterClasses[MSA128DRegClassID],
1870 .SubClassMask: MSA128DSubClassMask,
1871 .SuperRegIndices: SuperRegIdxSeqs + 1,
1872 .LaneMask: LaneBitmask(0x0000000000000041),
1873 .AllocationPriority: 0,
1874 .GlobalPriority: false,
1875 .TSFlags: 0x00, /* TSFlags */
1876 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1877 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1878 .SuperClasses: MSA128DSuperclasses, .SuperClassesSize: 4,
1879 .OrderFunc: nullptr
1880 };
1881
1882 extern const TargetRegisterClass MSA128HRegClass = {
1883 .MC: &MipsMCRegisterClasses[MSA128HRegClassID],
1884 .SubClassMask: MSA128HSubClassMask,
1885 .SuperRegIndices: SuperRegIdxSeqs + 1,
1886 .LaneMask: LaneBitmask(0x0000000000000041),
1887 .AllocationPriority: 0,
1888 .GlobalPriority: false,
1889 .TSFlags: 0x00, /* TSFlags */
1890 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1891 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1892 .SuperClasses: MSA128HSuperclasses, .SuperClassesSize: 4,
1893 .OrderFunc: nullptr
1894 };
1895
1896 extern const TargetRegisterClass MSA128WRegClass = {
1897 .MC: &MipsMCRegisterClasses[MSA128WRegClassID],
1898 .SubClassMask: MSA128WSubClassMask,
1899 .SuperRegIndices: SuperRegIdxSeqs + 1,
1900 .LaneMask: LaneBitmask(0x0000000000000041),
1901 .AllocationPriority: 0,
1902 .GlobalPriority: false,
1903 .TSFlags: 0x00, /* TSFlags */
1904 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1905 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1906 .SuperClasses: MSA128WSuperclasses, .SuperClassesSize: 4,
1907 .OrderFunc: nullptr
1908 };
1909
1910 extern const TargetRegisterClass MSA128WEvensRegClass = {
1911 .MC: &MipsMCRegisterClasses[MSA128WEvensRegClassID],
1912 .SubClassMask: MSA128WEvensSubClassMask,
1913 .SuperRegIndices: SuperRegIdxSeqs + 1,
1914 .LaneMask: LaneBitmask(0x0000000000000041),
1915 .AllocationPriority: 0,
1916 .GlobalPriority: false,
1917 .TSFlags: 0x00, /* TSFlags */
1918 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1919 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1920 .SuperClasses: MSA128WEvensSuperclasses, .SuperClassesSize: 5,
1921 .OrderFunc: nullptr
1922 };
1923
1924 extern const TargetRegisterClass ACC128RegClass = {
1925 .MC: &MipsMCRegisterClasses[ACC128RegClassID],
1926 .SubClassMask: ACC128SubClassMask,
1927 .SuperRegIndices: SuperRegIdxSeqs + 1,
1928 .LaneMask: LaneBitmask(0x0000000000000041),
1929 .AllocationPriority: 0,
1930 .GlobalPriority: false,
1931 .TSFlags: 0x00, /* TSFlags */
1932 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1933 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1934 .SuperClasses: nullptr, .SuperClassesSize: 0,
1935 .OrderFunc: nullptr
1936 };
1937
1938} // end namespace Mips
1939
1940namespace {
1941 const TargetRegisterClass *const RegisterClasses[] = {
1942 &Mips::MSA128F16RegClass,
1943 &Mips::CCRRegClass,
1944 &Mips::COP0RegClass,
1945 &Mips::COP2RegClass,
1946 &Mips::COP3RegClass,
1947 &Mips::DSPRRegClass,
1948 &Mips::FGR32RegClass,
1949 &Mips::FGR32CCRegClass,
1950 &Mips::GPR32RegClass,
1951 &Mips::HWRegsRegClass,
1952 &Mips::MSACtrlRegClass,
1953 &Mips::GPR32NONZERORegClass,
1954 &Mips::CPU16RegsPlusSPRegClass,
1955 &Mips::CPU16RegsRegClass,
1956 &Mips::FCCRegClass,
1957 &Mips::GPRMM16RegClass,
1958 &Mips::GPRMM16MovePRegClass,
1959 &Mips::GPRMM16ZeroRegClass,
1960 &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
1961 &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
1962 &Mips::GPRMM16MovePPairSecondRegClass,
1963 &Mips::CPU16Regs_and_GPRMM16MovePRegClass,
1964 &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
1965 &Mips::HI32DSPRegClass,
1966 &Mips::LO32DSPRegClass,
1967 &Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
1968 &Mips::GPRMM16MovePPairFirstRegClass,
1969 &Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
1970 &Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,
1971 &Mips::CPURARegRegClass,
1972 &Mips::CPUSPRegRegClass,
1973 &Mips::DSPCCRegClass,
1974 &Mips::GP32RegClass,
1975 &Mips::GPR32ZERORegClass,
1976 &Mips::HI32RegClass,
1977 &Mips::LO32RegClass,
1978 &Mips::SP32RegClass,
1979 &Mips::FGR64CCRegClass,
1980 &Mips::FGR64RegClass,
1981 &Mips::GPR64RegClass,
1982 &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
1983 &Mips::AFGR64RegClass,
1984 &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
1985 &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
1986 &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
1987 &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
1988 &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
1989 &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
1990 &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,
1991 &Mips::ACC64DSPRegClass,
1992 &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,
1993 &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
1994 &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
1995 &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,
1996 &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
1997 &Mips::OCTEON_MPLRegClass,
1998 &Mips::OCTEON_PRegClass,
1999 &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,
2000 &Mips::ACC64RegClass,
2001 &Mips::GP64RegClass,
2002 &Mips::GPR64_with_sub_32_in_CPURARegRegClass,
2003 &Mips::GPR64_with_sub_32_in_GPR32ZERORegClass,
2004 &Mips::HI64RegClass,
2005 &Mips::LO64RegClass,
2006 &Mips::SP64RegClass,
2007 &Mips::MSA128BRegClass,
2008 &Mips::MSA128DRegClass,
2009 &Mips::MSA128HRegClass,
2010 &Mips::MSA128WRegClass,
2011 &Mips::MSA128WEvensRegClass,
2012 &Mips::ACC128RegClass,
2013 };
2014} // end anonymous namespace
2015
2016static const uint8_t CostPerUseTable[] = {
20170, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
2018
2019
2020static const bool InAllocatableClassTable[] = {
2021false, true, true, false, false, false, false, false, true, true, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
2022
2023
2024static const TargetRegisterInfoDesc MipsRegInfoDesc = { // Extra Descriptors
2025.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
2026
2027unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
2028 static const uint8_t RowMap[11] = {
2029 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
2030 };
2031 static const uint8_t Rows[2][11] = {
2032 { Mips::sub_hi_then_sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, 0, 0, },
2033 { Mips::sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi_then_sub_32, Mips::sub_32, 0, 0, },
2034 };
2035
2036 --IdxA; assert(IdxA < 11); (void) IdxA;
2037 --IdxB; assert(IdxB < 11);
2038 return Rows[RowMap[IdxA]][IdxB];
2039}
2040
2041unsigned MipsGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
2042 static const uint8_t Table[11][11] = {
2043 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
2044 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
2045 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
2046 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
2047 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
2048 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
2049 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
2050 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
2051 { Mips::sub_32, 0, 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, 0, },
2052 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
2053 { Mips::sub_32, 0, 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, 0, },
2054 };
2055
2056 --IdxA; assert(IdxA < 11);
2057 --IdxB; assert(IdxB < 11);
2058 return Table[IdxA][IdxB];
2059 }
2060
2061 struct MaskRolOp {
2062 LaneBitmask Mask;
2063 uint8_t RotateLeft;
2064 };
2065 static const MaskRolOp LaneMaskComposeSequences[] = {
2066 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
2067 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
2068 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
2069 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 6
2070 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 4 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 8
2071 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 5 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 10
2072 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 6 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 12
2073 };
2074 static const uint8_t CompositeSequences[] = {
2075 0, // to sub_32
2076 0, // to sub_64
2077 2, // to sub_dsp16_19
2078 4, // to sub_dsp20
2079 6, // to sub_dsp21
2080 8, // to sub_dsp22
2081 10, // to sub_dsp23
2082 12, // to sub_hi
2083 0, // to sub_lo
2084 12, // to sub_hi_then_sub_32
2085 0 // to sub_32_sub_hi_then_sub_32
2086 };
2087
2088LaneBitmask MipsGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
2089 --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
2090 LaneBitmask Result;
2091 for (const MaskRolOp *Ops =
2092 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
2093 Ops->Mask.any(); ++Ops) {
2094 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
2095 if (unsigned S = Ops->RotateLeft)
2096 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
2097 else
2098 Result |= LaneBitmask(M);
2099 }
2100 return Result;
2101}
2102
2103LaneBitmask MipsGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
2104 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
2105 --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
2106 LaneBitmask Result;
2107 for (const MaskRolOp *Ops =
2108 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
2109 Ops->Mask.any(); ++Ops) {
2110 LaneBitmask::Type M = LaneMask.getAsInteger();
2111 if (unsigned S = Ops->RotateLeft)
2112 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
2113 else
2114 Result |= LaneBitmask(M);
2115 }
2116 return Result;
2117}
2118
2119const TargetRegisterClass *MipsGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
2120 static const uint8_t Table[71][11] = {
2121 { // MSA128F16
2122 0, // sub_32
2123 1, // sub_64 -> MSA128F16
2124 0, // sub_dsp16_19
2125 0, // sub_dsp20
2126 0, // sub_dsp21
2127 0, // sub_dsp22
2128 0, // sub_dsp23
2129 1, // sub_hi -> MSA128F16
2130 1, // sub_lo -> MSA128F16
2131 0, // sub_hi_then_sub_32
2132 0, // sub_32_sub_hi_then_sub_32
2133 },
2134 { // CCR
2135 0, // sub_32
2136 0, // sub_64
2137 0, // sub_dsp16_19
2138 0, // sub_dsp20
2139 0, // sub_dsp21
2140 0, // sub_dsp22
2141 0, // sub_dsp23
2142 0, // sub_hi
2143 0, // sub_lo
2144 0, // sub_hi_then_sub_32
2145 0, // sub_32_sub_hi_then_sub_32
2146 },
2147 { // COP0
2148 0, // sub_32
2149 0, // sub_64
2150 0, // sub_dsp16_19
2151 0, // sub_dsp20
2152 0, // sub_dsp21
2153 0, // sub_dsp22
2154 0, // sub_dsp23
2155 0, // sub_hi
2156 0, // sub_lo
2157 0, // sub_hi_then_sub_32
2158 0, // sub_32_sub_hi_then_sub_32
2159 },
2160 { // COP2
2161 0, // sub_32
2162 0, // sub_64
2163 0, // sub_dsp16_19
2164 0, // sub_dsp20
2165 0, // sub_dsp21
2166 0, // sub_dsp22
2167 0, // sub_dsp23
2168 0, // sub_hi
2169 0, // sub_lo
2170 0, // sub_hi_then_sub_32
2171 0, // sub_32_sub_hi_then_sub_32
2172 },
2173 { // COP3
2174 0, // sub_32
2175 0, // sub_64
2176 0, // sub_dsp16_19
2177 0, // sub_dsp20
2178 0, // sub_dsp21
2179 0, // sub_dsp22
2180 0, // sub_dsp23
2181 0, // sub_hi
2182 0, // sub_lo
2183 0, // sub_hi_then_sub_32
2184 0, // sub_32_sub_hi_then_sub_32
2185 },
2186 { // DSPR
2187 0, // sub_32
2188 0, // sub_64
2189 0, // sub_dsp16_19
2190 0, // sub_dsp20
2191 0, // sub_dsp21
2192 0, // sub_dsp22
2193 0, // sub_dsp23
2194 0, // sub_hi
2195 0, // sub_lo
2196 0, // sub_hi_then_sub_32
2197 0, // sub_32_sub_hi_then_sub_32
2198 },
2199 { // FGR32
2200 0, // sub_32
2201 0, // sub_64
2202 0, // sub_dsp16_19
2203 0, // sub_dsp20
2204 0, // sub_dsp21
2205 0, // sub_dsp22
2206 0, // sub_dsp23
2207 0, // sub_hi
2208 0, // sub_lo
2209 0, // sub_hi_then_sub_32
2210 0, // sub_32_sub_hi_then_sub_32
2211 },
2212 { // FGR32CC
2213 0, // sub_32
2214 0, // sub_64
2215 0, // sub_dsp16_19
2216 0, // sub_dsp20
2217 0, // sub_dsp21
2218 0, // sub_dsp22
2219 0, // sub_dsp23
2220 0, // sub_hi
2221 0, // sub_lo
2222 0, // sub_hi_then_sub_32
2223 0, // sub_32_sub_hi_then_sub_32
2224 },
2225 { // GPR32
2226 0, // sub_32
2227 0, // sub_64
2228 0, // sub_dsp16_19
2229 0, // sub_dsp20
2230 0, // sub_dsp21
2231 0, // sub_dsp22
2232 0, // sub_dsp23
2233 0, // sub_hi
2234 0, // sub_lo
2235 0, // sub_hi_then_sub_32
2236 0, // sub_32_sub_hi_then_sub_32
2237 },
2238 { // HWRegs
2239 0, // sub_32
2240 0, // sub_64
2241 0, // sub_dsp16_19
2242 0, // sub_dsp20
2243 0, // sub_dsp21
2244 0, // sub_dsp22
2245 0, // sub_dsp23
2246 0, // sub_hi
2247 0, // sub_lo
2248 0, // sub_hi_then_sub_32
2249 0, // sub_32_sub_hi_then_sub_32
2250 },
2251 { // MSACtrl
2252 0, // sub_32
2253 0, // sub_64
2254 0, // sub_dsp16_19
2255 0, // sub_dsp20
2256 0, // sub_dsp21
2257 0, // sub_dsp22
2258 0, // sub_dsp23
2259 0, // sub_hi
2260 0, // sub_lo
2261 0, // sub_hi_then_sub_32
2262 0, // sub_32_sub_hi_then_sub_32
2263 },
2264 { // GPR32NONZERO
2265 0, // sub_32
2266 0, // sub_64
2267 0, // sub_dsp16_19
2268 0, // sub_dsp20
2269 0, // sub_dsp21
2270 0, // sub_dsp22
2271 0, // sub_dsp23
2272 0, // sub_hi
2273 0, // sub_lo
2274 0, // sub_hi_then_sub_32
2275 0, // sub_32_sub_hi_then_sub_32
2276 },
2277 { // CPU16RegsPlusSP
2278 0, // sub_32
2279 0, // sub_64
2280 0, // sub_dsp16_19
2281 0, // sub_dsp20
2282 0, // sub_dsp21
2283 0, // sub_dsp22
2284 0, // sub_dsp23
2285 0, // sub_hi
2286 0, // sub_lo
2287 0, // sub_hi_then_sub_32
2288 0, // sub_32_sub_hi_then_sub_32
2289 },
2290 { // CPU16Regs
2291 0, // sub_32
2292 0, // sub_64
2293 0, // sub_dsp16_19
2294 0, // sub_dsp20
2295 0, // sub_dsp21
2296 0, // sub_dsp22
2297 0, // sub_dsp23
2298 0, // sub_hi
2299 0, // sub_lo
2300 0, // sub_hi_then_sub_32
2301 0, // sub_32_sub_hi_then_sub_32
2302 },
2303 { // FCC
2304 0, // sub_32
2305 0, // sub_64
2306 0, // sub_dsp16_19
2307 0, // sub_dsp20
2308 0, // sub_dsp21
2309 0, // sub_dsp22
2310 0, // sub_dsp23
2311 0, // sub_hi
2312 0, // sub_lo
2313 0, // sub_hi_then_sub_32
2314 0, // sub_32_sub_hi_then_sub_32
2315 },
2316 { // GPRMM16
2317 0, // sub_32
2318 0, // sub_64
2319 0, // sub_dsp16_19
2320 0, // sub_dsp20
2321 0, // sub_dsp21
2322 0, // sub_dsp22
2323 0, // sub_dsp23
2324 0, // sub_hi
2325 0, // sub_lo
2326 0, // sub_hi_then_sub_32
2327 0, // sub_32_sub_hi_then_sub_32
2328 },
2329 { // GPRMM16MoveP
2330 0, // sub_32
2331 0, // sub_64
2332 0, // sub_dsp16_19
2333 0, // sub_dsp20
2334 0, // sub_dsp21
2335 0, // sub_dsp22
2336 0, // sub_dsp23
2337 0, // sub_hi
2338 0, // sub_lo
2339 0, // sub_hi_then_sub_32
2340 0, // sub_32_sub_hi_then_sub_32
2341 },
2342 { // GPRMM16Zero
2343 0, // sub_32
2344 0, // sub_64
2345 0, // sub_dsp16_19
2346 0, // sub_dsp20
2347 0, // sub_dsp21
2348 0, // sub_dsp22
2349 0, // sub_dsp23
2350 0, // sub_hi
2351 0, // sub_lo
2352 0, // sub_hi_then_sub_32
2353 0, // sub_32_sub_hi_then_sub_32
2354 },
2355 { // CPU16Regs_and_GPRMM16Zero
2356 0, // sub_32
2357 0, // sub_64
2358 0, // sub_dsp16_19
2359 0, // sub_dsp20
2360 0, // sub_dsp21
2361 0, // sub_dsp22
2362 0, // sub_dsp23
2363 0, // sub_hi
2364 0, // sub_lo
2365 0, // sub_hi_then_sub_32
2366 0, // sub_32_sub_hi_then_sub_32
2367 },
2368 { // GPR32NONZERO_and_GPRMM16MoveP
2369 0, // sub_32
2370 0, // sub_64
2371 0, // sub_dsp16_19
2372 0, // sub_dsp20
2373 0, // sub_dsp21
2374 0, // sub_dsp22
2375 0, // sub_dsp23
2376 0, // sub_hi
2377 0, // sub_lo
2378 0, // sub_hi_then_sub_32
2379 0, // sub_32_sub_hi_then_sub_32
2380 },
2381 { // GPRMM16MovePPairSecond
2382 0, // sub_32
2383 0, // sub_64
2384 0, // sub_dsp16_19
2385 0, // sub_dsp20
2386 0, // sub_dsp21
2387 0, // sub_dsp22
2388 0, // sub_dsp23
2389 0, // sub_hi
2390 0, // sub_lo
2391 0, // sub_hi_then_sub_32
2392 0, // sub_32_sub_hi_then_sub_32
2393 },
2394 { // CPU16Regs_and_GPRMM16MoveP
2395 0, // sub_32
2396 0, // sub_64
2397 0, // sub_dsp16_19
2398 0, // sub_dsp20
2399 0, // sub_dsp21
2400 0, // sub_dsp22
2401 0, // sub_dsp23
2402 0, // sub_hi
2403 0, // sub_lo
2404 0, // sub_hi_then_sub_32
2405 0, // sub_32_sub_hi_then_sub_32
2406 },
2407 { // GPRMM16MoveP_and_GPRMM16Zero
2408 0, // sub_32
2409 0, // sub_64
2410 0, // sub_dsp16_19
2411 0, // sub_dsp20
2412 0, // sub_dsp21
2413 0, // sub_dsp22
2414 0, // sub_dsp23
2415 0, // sub_hi
2416 0, // sub_lo
2417 0, // sub_hi_then_sub_32
2418 0, // sub_32_sub_hi_then_sub_32
2419 },
2420 { // HI32DSP
2421 0, // sub_32
2422 0, // sub_64
2423 0, // sub_dsp16_19
2424 0, // sub_dsp20
2425 0, // sub_dsp21
2426 0, // sub_dsp22
2427 0, // sub_dsp23
2428 0, // sub_hi
2429 0, // sub_lo
2430 0, // sub_hi_then_sub_32
2431 0, // sub_32_sub_hi_then_sub_32
2432 },
2433 { // LO32DSP
2434 0, // sub_32
2435 0, // sub_64
2436 0, // sub_dsp16_19
2437 0, // sub_dsp20
2438 0, // sub_dsp21
2439 0, // sub_dsp22
2440 0, // sub_dsp23
2441 0, // sub_hi
2442 0, // sub_lo
2443 0, // sub_hi_then_sub_32
2444 0, // sub_32_sub_hi_then_sub_32
2445 },
2446 { // CPU16Regs_and_GPRMM16MovePPairSecond
2447 0, // sub_32
2448 0, // sub_64
2449 0, // sub_dsp16_19
2450 0, // sub_dsp20
2451 0, // sub_dsp21
2452 0, // sub_dsp22
2453 0, // sub_dsp23
2454 0, // sub_hi
2455 0, // sub_lo
2456 0, // sub_hi_then_sub_32
2457 0, // sub_32_sub_hi_then_sub_32
2458 },
2459 { // GPRMM16MovePPairFirst
2460 0, // sub_32
2461 0, // sub_64
2462 0, // sub_dsp16_19
2463 0, // sub_dsp20
2464 0, // sub_dsp21
2465 0, // sub_dsp22
2466 0, // sub_dsp23
2467 0, // sub_hi
2468 0, // sub_lo
2469 0, // sub_hi_then_sub_32
2470 0, // sub_32_sub_hi_then_sub_32
2471 },
2472 { // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
2473 0, // sub_32
2474 0, // sub_64
2475 0, // sub_dsp16_19
2476 0, // sub_dsp20
2477 0, // sub_dsp21
2478 0, // sub_dsp22
2479 0, // sub_dsp23
2480 0, // sub_hi
2481 0, // sub_lo
2482 0, // sub_hi_then_sub_32
2483 0, // sub_32_sub_hi_then_sub_32
2484 },
2485 { // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
2486 0, // sub_32
2487 0, // sub_64
2488 0, // sub_dsp16_19
2489 0, // sub_dsp20
2490 0, // sub_dsp21
2491 0, // sub_dsp22
2492 0, // sub_dsp23
2493 0, // sub_hi
2494 0, // sub_lo
2495 0, // sub_hi_then_sub_32
2496 0, // sub_32_sub_hi_then_sub_32
2497 },
2498 { // CPURAReg
2499 0, // sub_32
2500 0, // sub_64
2501 0, // sub_dsp16_19
2502 0, // sub_dsp20
2503 0, // sub_dsp21
2504 0, // sub_dsp22
2505 0, // sub_dsp23
2506 0, // sub_hi
2507 0, // sub_lo
2508 0, // sub_hi_then_sub_32
2509 0, // sub_32_sub_hi_then_sub_32
2510 },
2511 { // CPUSPReg
2512 0, // sub_32
2513 0, // sub_64
2514 0, // sub_dsp16_19
2515 0, // sub_dsp20
2516 0, // sub_dsp21
2517 0, // sub_dsp22
2518 0, // sub_dsp23
2519 0, // sub_hi
2520 0, // sub_lo
2521 0, // sub_hi_then_sub_32
2522 0, // sub_32_sub_hi_then_sub_32
2523 },
2524 { // DSPCC
2525 0, // sub_32
2526 0, // sub_64
2527 0, // sub_dsp16_19
2528 0, // sub_dsp20
2529 0, // sub_dsp21
2530 0, // sub_dsp22
2531 0, // sub_dsp23
2532 0, // sub_hi
2533 0, // sub_lo
2534 0, // sub_hi_then_sub_32
2535 0, // sub_32_sub_hi_then_sub_32
2536 },
2537 { // GP32
2538 0, // sub_32
2539 0, // sub_64
2540 0, // sub_dsp16_19
2541 0, // sub_dsp20
2542 0, // sub_dsp21
2543 0, // sub_dsp22
2544 0, // sub_dsp23
2545 0, // sub_hi
2546 0, // sub_lo
2547 0, // sub_hi_then_sub_32
2548 0, // sub_32_sub_hi_then_sub_32
2549 },
2550 { // GPR32ZERO
2551 0, // sub_32
2552 0, // sub_64
2553 0, // sub_dsp16_19
2554 0, // sub_dsp20
2555 0, // sub_dsp21
2556 0, // sub_dsp22
2557 0, // sub_dsp23
2558 0, // sub_hi
2559 0, // sub_lo
2560 0, // sub_hi_then_sub_32
2561 0, // sub_32_sub_hi_then_sub_32
2562 },
2563 { // HI32
2564 0, // sub_32
2565 0, // sub_64
2566 0, // sub_dsp16_19
2567 0, // sub_dsp20
2568 0, // sub_dsp21
2569 0, // sub_dsp22
2570 0, // sub_dsp23
2571 0, // sub_hi
2572 0, // sub_lo
2573 0, // sub_hi_then_sub_32
2574 0, // sub_32_sub_hi_then_sub_32
2575 },
2576 { // LO32
2577 0, // sub_32
2578 0, // sub_64
2579 0, // sub_dsp16_19
2580 0, // sub_dsp20
2581 0, // sub_dsp21
2582 0, // sub_dsp22
2583 0, // sub_dsp23
2584 0, // sub_hi
2585 0, // sub_lo
2586 0, // sub_hi_then_sub_32
2587 0, // sub_32_sub_hi_then_sub_32
2588 },
2589 { // SP32
2590 0, // sub_32
2591 0, // sub_64
2592 0, // sub_dsp16_19
2593 0, // sub_dsp20
2594 0, // sub_dsp21
2595 0, // sub_dsp22
2596 0, // sub_dsp23
2597 0, // sub_hi
2598 0, // sub_lo
2599 0, // sub_hi_then_sub_32
2600 0, // sub_32_sub_hi_then_sub_32
2601 },
2602 { // FGR64CC
2603 0, // sub_32
2604 0, // sub_64
2605 0, // sub_dsp16_19
2606 0, // sub_dsp20
2607 0, // sub_dsp21
2608 0, // sub_dsp22
2609 0, // sub_dsp23
2610 38, // sub_hi -> FGR64CC
2611 38, // sub_lo -> FGR64CC
2612 0, // sub_hi_then_sub_32
2613 0, // sub_32_sub_hi_then_sub_32
2614 },
2615 { // FGR64
2616 0, // sub_32
2617 0, // sub_64
2618 0, // sub_dsp16_19
2619 0, // sub_dsp20
2620 0, // sub_dsp21
2621 0, // sub_dsp22
2622 0, // sub_dsp23
2623 39, // sub_hi -> FGR64
2624 39, // sub_lo -> FGR64
2625 0, // sub_hi_then_sub_32
2626 0, // sub_32_sub_hi_then_sub_32
2627 },
2628 { // GPR64
2629 40, // sub_32 -> GPR64
2630 0, // sub_64
2631 0, // sub_dsp16_19
2632 0, // sub_dsp20
2633 0, // sub_dsp21
2634 0, // sub_dsp22
2635 0, // sub_dsp23
2636 0, // sub_hi
2637 0, // sub_lo
2638 0, // sub_hi_then_sub_32
2639 0, // sub_32_sub_hi_then_sub_32
2640 },
2641 { // GPR64_with_sub_32_in_GPR32NONZERO
2642 41, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO
2643 0, // sub_64
2644 0, // sub_dsp16_19
2645 0, // sub_dsp20
2646 0, // sub_dsp21
2647 0, // sub_dsp22
2648 0, // sub_dsp23
2649 0, // sub_hi
2650 0, // sub_lo
2651 0, // sub_hi_then_sub_32
2652 0, // sub_32_sub_hi_then_sub_32
2653 },
2654 { // AFGR64
2655 0, // sub_32
2656 0, // sub_64
2657 0, // sub_dsp16_19
2658 0, // sub_dsp20
2659 0, // sub_dsp21
2660 0, // sub_dsp22
2661 0, // sub_dsp23
2662 42, // sub_hi -> AFGR64
2663 42, // sub_lo -> AFGR64
2664 0, // sub_hi_then_sub_32
2665 0, // sub_32_sub_hi_then_sub_32
2666 },
2667 { // GPR64_with_sub_32_in_CPU16RegsPlusSP
2668 43, // sub_32 -> GPR64_with_sub_32_in_CPU16RegsPlusSP
2669 0, // sub_64
2670 0, // sub_dsp16_19
2671 0, // sub_dsp20
2672 0, // sub_dsp21
2673 0, // sub_dsp22
2674 0, // sub_dsp23
2675 0, // sub_hi
2676 0, // sub_lo
2677 0, // sub_hi_then_sub_32
2678 0, // sub_32_sub_hi_then_sub_32
2679 },
2680 { // GPR64_with_sub_32_in_CPU16Regs
2681 44, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs
2682 0, // sub_64
2683 0, // sub_dsp16_19
2684 0, // sub_dsp20
2685 0, // sub_dsp21
2686 0, // sub_dsp22
2687 0, // sub_dsp23
2688 0, // sub_hi
2689 0, // sub_lo
2690 0, // sub_hi_then_sub_32
2691 0, // sub_32_sub_hi_then_sub_32
2692 },
2693 { // GPR64_with_sub_32_in_GPRMM16MoveP
2694 45, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP
2695 0, // sub_64
2696 0, // sub_dsp16_19
2697 0, // sub_dsp20
2698 0, // sub_dsp21
2699 0, // sub_dsp22
2700 0, // sub_dsp23
2701 0, // sub_hi
2702 0, // sub_lo
2703 0, // sub_hi_then_sub_32
2704 0, // sub_32_sub_hi_then_sub_32
2705 },
2706 { // GPR64_with_sub_32_in_GPRMM16Zero
2707 46, // sub_32 -> GPR64_with_sub_32_in_GPRMM16Zero
2708 0, // sub_64
2709 0, // sub_dsp16_19
2710 0, // sub_dsp20
2711 0, // sub_dsp21
2712 0, // sub_dsp22
2713 0, // sub_dsp23
2714 0, // sub_hi
2715 0, // sub_lo
2716 0, // sub_hi_then_sub_32
2717 0, // sub_32_sub_hi_then_sub_32
2718 },
2719 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
2720 47, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
2721 0, // sub_64
2722 0, // sub_dsp16_19
2723 0, // sub_dsp20
2724 0, // sub_dsp21
2725 0, // sub_dsp22
2726 0, // sub_dsp23
2727 0, // sub_hi
2728 0, // sub_lo
2729 0, // sub_hi_then_sub_32
2730 0, // sub_32_sub_hi_then_sub_32
2731 },
2732 { // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
2733 48, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
2734 0, // sub_64
2735 0, // sub_dsp16_19
2736 0, // sub_dsp20
2737 0, // sub_dsp21
2738 0, // sub_dsp22
2739 0, // sub_dsp23
2740 0, // sub_hi
2741 0, // sub_lo
2742 0, // sub_hi_then_sub_32
2743 0, // sub_32_sub_hi_then_sub_32
2744 },
2745 { // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
2746 49, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairSecond
2747 0, // sub_64
2748 0, // sub_dsp16_19
2749 0, // sub_dsp20
2750 0, // sub_dsp21
2751 0, // sub_dsp22
2752 0, // sub_dsp23
2753 0, // sub_hi
2754 0, // sub_lo
2755 0, // sub_hi_then_sub_32
2756 0, // sub_32_sub_hi_then_sub_32
2757 },
2758 { // ACC64DSP
2759 0, // sub_32
2760 0, // sub_64
2761 0, // sub_dsp16_19
2762 0, // sub_dsp20
2763 0, // sub_dsp21
2764 0, // sub_dsp22
2765 0, // sub_dsp23
2766 50, // sub_hi -> ACC64DSP
2767 50, // sub_lo -> ACC64DSP
2768 0, // sub_hi_then_sub_32
2769 0, // sub_32_sub_hi_then_sub_32
2770 },
2771 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
2772 51, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
2773 0, // sub_64
2774 0, // sub_dsp16_19
2775 0, // sub_dsp20
2776 0, // sub_dsp21
2777 0, // sub_dsp22
2778 0, // sub_dsp23
2779 0, // sub_hi
2780 0, // sub_lo
2781 0, // sub_hi_then_sub_32
2782 0, // sub_32_sub_hi_then_sub_32
2783 },
2784 { // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
2785 52, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
2786 0, // sub_64
2787 0, // sub_dsp16_19
2788 0, // sub_dsp20
2789 0, // sub_dsp21
2790 0, // sub_dsp22
2791 0, // sub_dsp23
2792 0, // sub_hi
2793 0, // sub_lo
2794 0, // sub_hi_then_sub_32
2795 0, // sub_32_sub_hi_then_sub_32
2796 },
2797 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
2798 53, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
2799 0, // sub_64
2800 0, // sub_dsp16_19
2801 0, // sub_dsp20
2802 0, // sub_dsp21
2803 0, // sub_dsp22
2804 0, // sub_dsp23
2805 0, // sub_hi
2806 0, // sub_lo
2807 0, // sub_hi_then_sub_32
2808 0, // sub_32_sub_hi_then_sub_32
2809 },
2810 { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
2811 54, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst
2812 0, // sub_64
2813 0, // sub_dsp16_19
2814 0, // sub_dsp20
2815 0, // sub_dsp21
2816 0, // sub_dsp22
2817 0, // sub_dsp23
2818 0, // sub_hi
2819 0, // sub_lo
2820 0, // sub_hi_then_sub_32
2821 0, // sub_32_sub_hi_then_sub_32
2822 },
2823 { // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
2824 55, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
2825 0, // sub_64
2826 0, // sub_dsp16_19
2827 0, // sub_dsp20
2828 0, // sub_dsp21
2829 0, // sub_dsp22
2830 0, // sub_dsp23
2831 0, // sub_hi
2832 0, // sub_lo
2833 0, // sub_hi_then_sub_32
2834 0, // sub_32_sub_hi_then_sub_32
2835 },
2836 { // OCTEON_MPL
2837 0, // sub_32
2838 0, // sub_64
2839 0, // sub_dsp16_19
2840 0, // sub_dsp20
2841 0, // sub_dsp21
2842 0, // sub_dsp22
2843 0, // sub_dsp23
2844 0, // sub_hi
2845 0, // sub_lo
2846 0, // sub_hi_then_sub_32
2847 0, // sub_32_sub_hi_then_sub_32
2848 },
2849 { // OCTEON_P
2850 0, // sub_32
2851 0, // sub_64
2852 0, // sub_dsp16_19
2853 0, // sub_dsp20
2854 0, // sub_dsp21
2855 0, // sub_dsp22
2856 0, // sub_dsp23
2857 0, // sub_hi
2858 0, // sub_lo
2859 0, // sub_hi_then_sub_32
2860 0, // sub_32_sub_hi_then_sub_32
2861 },
2862 { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
2863 58, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
2864 0, // sub_64
2865 0, // sub_dsp16_19
2866 0, // sub_dsp20
2867 0, // sub_dsp21
2868 0, // sub_dsp22
2869 0, // sub_dsp23
2870 0, // sub_hi
2871 0, // sub_lo
2872 0, // sub_hi_then_sub_32
2873 0, // sub_32_sub_hi_then_sub_32
2874 },
2875 { // ACC64
2876 0, // sub_32
2877 0, // sub_64
2878 0, // sub_dsp16_19
2879 0, // sub_dsp20
2880 0, // sub_dsp21
2881 0, // sub_dsp22
2882 0, // sub_dsp23
2883 59, // sub_hi -> ACC64
2884 59, // sub_lo -> ACC64
2885 0, // sub_hi_then_sub_32
2886 0, // sub_32_sub_hi_then_sub_32
2887 },
2888 { // GP64
2889 60, // sub_32 -> GP64
2890 0, // sub_64
2891 0, // sub_dsp16_19
2892 0, // sub_dsp20
2893 0, // sub_dsp21
2894 0, // sub_dsp22
2895 0, // sub_dsp23
2896 0, // sub_hi
2897 0, // sub_lo
2898 0, // sub_hi_then_sub_32
2899 0, // sub_32_sub_hi_then_sub_32
2900 },
2901 { // GPR64_with_sub_32_in_CPURAReg
2902 61, // sub_32 -> GPR64_with_sub_32_in_CPURAReg
2903 0, // sub_64
2904 0, // sub_dsp16_19
2905 0, // sub_dsp20
2906 0, // sub_dsp21
2907 0, // sub_dsp22
2908 0, // sub_dsp23
2909 0, // sub_hi
2910 0, // sub_lo
2911 0, // sub_hi_then_sub_32
2912 0, // sub_32_sub_hi_then_sub_32
2913 },
2914 { // GPR64_with_sub_32_in_GPR32ZERO
2915 62, // sub_32 -> GPR64_with_sub_32_in_GPR32ZERO
2916 0, // sub_64
2917 0, // sub_dsp16_19
2918 0, // sub_dsp20
2919 0, // sub_dsp21
2920 0, // sub_dsp22
2921 0, // sub_dsp23
2922 0, // sub_hi
2923 0, // sub_lo
2924 0, // sub_hi_then_sub_32
2925 0, // sub_32_sub_hi_then_sub_32
2926 },
2927 { // HI64
2928 63, // sub_32 -> HI64
2929 0, // sub_64
2930 0, // sub_dsp16_19
2931 0, // sub_dsp20
2932 0, // sub_dsp21
2933 0, // sub_dsp22
2934 0, // sub_dsp23
2935 0, // sub_hi
2936 0, // sub_lo
2937 0, // sub_hi_then_sub_32
2938 0, // sub_32_sub_hi_then_sub_32
2939 },
2940 { // LO64
2941 64, // sub_32 -> LO64
2942 0, // sub_64
2943 0, // sub_dsp16_19
2944 0, // sub_dsp20
2945 0, // sub_dsp21
2946 0, // sub_dsp22
2947 0, // sub_dsp23
2948 0, // sub_hi
2949 0, // sub_lo
2950 0, // sub_hi_then_sub_32
2951 0, // sub_32_sub_hi_then_sub_32
2952 },
2953 { // SP64
2954 65, // sub_32 -> SP64
2955 0, // sub_64
2956 0, // sub_dsp16_19
2957 0, // sub_dsp20
2958 0, // sub_dsp21
2959 0, // sub_dsp22
2960 0, // sub_dsp23
2961 0, // sub_hi
2962 0, // sub_lo
2963 0, // sub_hi_then_sub_32
2964 0, // sub_32_sub_hi_then_sub_32
2965 },
2966 { // MSA128B
2967 0, // sub_32
2968 66, // sub_64 -> MSA128B
2969 0, // sub_dsp16_19
2970 0, // sub_dsp20
2971 0, // sub_dsp21
2972 0, // sub_dsp22
2973 0, // sub_dsp23
2974 66, // sub_hi -> MSA128B
2975 66, // sub_lo -> MSA128B
2976 0, // sub_hi_then_sub_32
2977 0, // sub_32_sub_hi_then_sub_32
2978 },
2979 { // MSA128D
2980 0, // sub_32
2981 67, // sub_64 -> MSA128D
2982 0, // sub_dsp16_19
2983 0, // sub_dsp20
2984 0, // sub_dsp21
2985 0, // sub_dsp22
2986 0, // sub_dsp23
2987 67, // sub_hi -> MSA128D
2988 67, // sub_lo -> MSA128D
2989 0, // sub_hi_then_sub_32
2990 0, // sub_32_sub_hi_then_sub_32
2991 },
2992 { // MSA128H
2993 0, // sub_32
2994 68, // sub_64 -> MSA128H
2995 0, // sub_dsp16_19
2996 0, // sub_dsp20
2997 0, // sub_dsp21
2998 0, // sub_dsp22
2999 0, // sub_dsp23
3000 68, // sub_hi -> MSA128H
3001 68, // sub_lo -> MSA128H
3002 0, // sub_hi_then_sub_32
3003 0, // sub_32_sub_hi_then_sub_32
3004 },
3005 { // MSA128W
3006 0, // sub_32
3007 69, // sub_64 -> MSA128W
3008 0, // sub_dsp16_19
3009 0, // sub_dsp20
3010 0, // sub_dsp21
3011 0, // sub_dsp22
3012 0, // sub_dsp23
3013 69, // sub_hi -> MSA128W
3014 69, // sub_lo -> MSA128W
3015 0, // sub_hi_then_sub_32
3016 0, // sub_32_sub_hi_then_sub_32
3017 },
3018 { // MSA128WEvens
3019 0, // sub_32
3020 70, // sub_64 -> MSA128WEvens
3021 0, // sub_dsp16_19
3022 0, // sub_dsp20
3023 0, // sub_dsp21
3024 0, // sub_dsp22
3025 0, // sub_dsp23
3026 70, // sub_hi -> MSA128WEvens
3027 70, // sub_lo -> MSA128WEvens
3028 0, // sub_hi_then_sub_32
3029 0, // sub_32_sub_hi_then_sub_32
3030 },
3031 { // ACC128
3032 71, // sub_32 -> ACC128
3033 0, // sub_64
3034 0, // sub_dsp16_19
3035 0, // sub_dsp20
3036 0, // sub_dsp21
3037 0, // sub_dsp22
3038 0, // sub_dsp23
3039 71, // sub_hi -> ACC128
3040 71, // sub_lo -> ACC128
3041 71, // sub_hi_then_sub_32 -> ACC128
3042 71, // sub_32_sub_hi_then_sub_32 -> ACC128
3043 },
3044 };
3045 assert(RC && "Missing regclass");
3046 if (!Idx) return RC;
3047 --Idx;
3048 assert(Idx < 11 && "Bad subreg");
3049 unsigned TV = Table[RC->getID()][Idx];
3050 return TV ? getRegClass(i: TV - 1) : nullptr;
3051}
3052
3053const TargetRegisterClass *MipsGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
3054 static const uint8_t Table[71][11] = {
3055 { // MSA128F16
3056 0, // MSA128F16:sub_32
3057 38, // MSA128F16:sub_64 -> FGR64CC
3058 0, // MSA128F16:sub_dsp16_19
3059 0, // MSA128F16:sub_dsp20
3060 0, // MSA128F16:sub_dsp21
3061 0, // MSA128F16:sub_dsp22
3062 0, // MSA128F16:sub_dsp23
3063 0, // MSA128F16:sub_hi
3064 7, // MSA128F16:sub_lo -> FGR32
3065 0, // MSA128F16:sub_hi_then_sub_32
3066 0, // MSA128F16:sub_32_sub_hi_then_sub_32
3067 },
3068 { // CCR
3069 0, // CCR:sub_32
3070 0, // CCR:sub_64
3071 0, // CCR:sub_dsp16_19
3072 0, // CCR:sub_dsp20
3073 0, // CCR:sub_dsp21
3074 0, // CCR:sub_dsp22
3075 0, // CCR:sub_dsp23
3076 0, // CCR:sub_hi
3077 0, // CCR:sub_lo
3078 0, // CCR:sub_hi_then_sub_32
3079 0, // CCR:sub_32_sub_hi_then_sub_32
3080 },
3081 { // COP0
3082 0, // COP0:sub_32
3083 0, // COP0:sub_64
3084 0, // COP0:sub_dsp16_19
3085 0, // COP0:sub_dsp20
3086 0, // COP0:sub_dsp21
3087 0, // COP0:sub_dsp22
3088 0, // COP0:sub_dsp23
3089 0, // COP0:sub_hi
3090 0, // COP0:sub_lo
3091 0, // COP0:sub_hi_then_sub_32
3092 0, // COP0:sub_32_sub_hi_then_sub_32
3093 },
3094 { // COP2
3095 0, // COP2:sub_32
3096 0, // COP2:sub_64
3097 0, // COP2:sub_dsp16_19
3098 0, // COP2:sub_dsp20
3099 0, // COP2:sub_dsp21
3100 0, // COP2:sub_dsp22
3101 0, // COP2:sub_dsp23
3102 0, // COP2:sub_hi
3103 0, // COP2:sub_lo
3104 0, // COP2:sub_hi_then_sub_32
3105 0, // COP2:sub_32_sub_hi_then_sub_32
3106 },
3107 { // COP3
3108 0, // COP3:sub_32
3109 0, // COP3:sub_64
3110 0, // COP3:sub_dsp16_19
3111 0, // COP3:sub_dsp20
3112 0, // COP3:sub_dsp21
3113 0, // COP3:sub_dsp22
3114 0, // COP3:sub_dsp23
3115 0, // COP3:sub_hi
3116 0, // COP3:sub_lo
3117 0, // COP3:sub_hi_then_sub_32
3118 0, // COP3:sub_32_sub_hi_then_sub_32
3119 },
3120 { // DSPR
3121 0, // DSPR:sub_32
3122 0, // DSPR:sub_64
3123 0, // DSPR:sub_dsp16_19
3124 0, // DSPR:sub_dsp20
3125 0, // DSPR:sub_dsp21
3126 0, // DSPR:sub_dsp22
3127 0, // DSPR:sub_dsp23
3128 0, // DSPR:sub_hi
3129 0, // DSPR:sub_lo
3130 0, // DSPR:sub_hi_then_sub_32
3131 0, // DSPR:sub_32_sub_hi_then_sub_32
3132 },
3133 { // FGR32
3134 0, // FGR32:sub_32
3135 0, // FGR32:sub_64
3136 0, // FGR32:sub_dsp16_19
3137 0, // FGR32:sub_dsp20
3138 0, // FGR32:sub_dsp21
3139 0, // FGR32:sub_dsp22
3140 0, // FGR32:sub_dsp23
3141 0, // FGR32:sub_hi
3142 0, // FGR32:sub_lo
3143 0, // FGR32:sub_hi_then_sub_32
3144 0, // FGR32:sub_32_sub_hi_then_sub_32
3145 },
3146 { // FGR32CC
3147 0, // FGR32CC:sub_32
3148 0, // FGR32CC:sub_64
3149 0, // FGR32CC:sub_dsp16_19
3150 0, // FGR32CC:sub_dsp20
3151 0, // FGR32CC:sub_dsp21
3152 0, // FGR32CC:sub_dsp22
3153 0, // FGR32CC:sub_dsp23
3154 0, // FGR32CC:sub_hi
3155 0, // FGR32CC:sub_lo
3156 0, // FGR32CC:sub_hi_then_sub_32
3157 0, // FGR32CC:sub_32_sub_hi_then_sub_32
3158 },
3159 { // GPR32
3160 0, // GPR32:sub_32
3161 0, // GPR32:sub_64
3162 0, // GPR32:sub_dsp16_19
3163 0, // GPR32:sub_dsp20
3164 0, // GPR32:sub_dsp21
3165 0, // GPR32:sub_dsp22
3166 0, // GPR32:sub_dsp23
3167 0, // GPR32:sub_hi
3168 0, // GPR32:sub_lo
3169 0, // GPR32:sub_hi_then_sub_32
3170 0, // GPR32:sub_32_sub_hi_then_sub_32
3171 },
3172 { // HWRegs
3173 0, // HWRegs:sub_32
3174 0, // HWRegs:sub_64
3175 0, // HWRegs:sub_dsp16_19
3176 0, // HWRegs:sub_dsp20
3177 0, // HWRegs:sub_dsp21
3178 0, // HWRegs:sub_dsp22
3179 0, // HWRegs:sub_dsp23
3180 0, // HWRegs:sub_hi
3181 0, // HWRegs:sub_lo
3182 0, // HWRegs:sub_hi_then_sub_32
3183 0, // HWRegs:sub_32_sub_hi_then_sub_32
3184 },
3185 { // MSACtrl
3186 0, // MSACtrl:sub_32
3187 0, // MSACtrl:sub_64
3188 0, // MSACtrl:sub_dsp16_19
3189 0, // MSACtrl:sub_dsp20
3190 0, // MSACtrl:sub_dsp21
3191 0, // MSACtrl:sub_dsp22
3192 0, // MSACtrl:sub_dsp23
3193 0, // MSACtrl:sub_hi
3194 0, // MSACtrl:sub_lo
3195 0, // MSACtrl:sub_hi_then_sub_32
3196 0, // MSACtrl:sub_32_sub_hi_then_sub_32
3197 },
3198 { // GPR32NONZERO
3199 0, // GPR32NONZERO:sub_32
3200 0, // GPR32NONZERO:sub_64
3201 0, // GPR32NONZERO:sub_dsp16_19
3202 0, // GPR32NONZERO:sub_dsp20
3203 0, // GPR32NONZERO:sub_dsp21
3204 0, // GPR32NONZERO:sub_dsp22
3205 0, // GPR32NONZERO:sub_dsp23
3206 0, // GPR32NONZERO:sub_hi
3207 0, // GPR32NONZERO:sub_lo
3208 0, // GPR32NONZERO:sub_hi_then_sub_32
3209 0, // GPR32NONZERO:sub_32_sub_hi_then_sub_32
3210 },
3211 { // CPU16RegsPlusSP
3212 0, // CPU16RegsPlusSP:sub_32
3213 0, // CPU16RegsPlusSP:sub_64
3214 0, // CPU16RegsPlusSP:sub_dsp16_19
3215 0, // CPU16RegsPlusSP:sub_dsp20
3216 0, // CPU16RegsPlusSP:sub_dsp21
3217 0, // CPU16RegsPlusSP:sub_dsp22
3218 0, // CPU16RegsPlusSP:sub_dsp23
3219 0, // CPU16RegsPlusSP:sub_hi
3220 0, // CPU16RegsPlusSP:sub_lo
3221 0, // CPU16RegsPlusSP:sub_hi_then_sub_32
3222 0, // CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32
3223 },
3224 { // CPU16Regs
3225 0, // CPU16Regs:sub_32
3226 0, // CPU16Regs:sub_64
3227 0, // CPU16Regs:sub_dsp16_19
3228 0, // CPU16Regs:sub_dsp20
3229 0, // CPU16Regs:sub_dsp21
3230 0, // CPU16Regs:sub_dsp22
3231 0, // CPU16Regs:sub_dsp23
3232 0, // CPU16Regs:sub_hi
3233 0, // CPU16Regs:sub_lo
3234 0, // CPU16Regs:sub_hi_then_sub_32
3235 0, // CPU16Regs:sub_32_sub_hi_then_sub_32
3236 },
3237 { // FCC
3238 0, // FCC:sub_32
3239 0, // FCC:sub_64
3240 0, // FCC:sub_dsp16_19
3241 0, // FCC:sub_dsp20
3242 0, // FCC:sub_dsp21
3243 0, // FCC:sub_dsp22
3244 0, // FCC:sub_dsp23
3245 0, // FCC:sub_hi
3246 0, // FCC:sub_lo
3247 0, // FCC:sub_hi_then_sub_32
3248 0, // FCC:sub_32_sub_hi_then_sub_32
3249 },
3250 { // GPRMM16
3251 0, // GPRMM16:sub_32
3252 0, // GPRMM16:sub_64
3253 0, // GPRMM16:sub_dsp16_19
3254 0, // GPRMM16:sub_dsp20
3255 0, // GPRMM16:sub_dsp21
3256 0, // GPRMM16:sub_dsp22
3257 0, // GPRMM16:sub_dsp23
3258 0, // GPRMM16:sub_hi
3259 0, // GPRMM16:sub_lo
3260 0, // GPRMM16:sub_hi_then_sub_32
3261 0, // GPRMM16:sub_32_sub_hi_then_sub_32
3262 },
3263 { // GPRMM16MoveP
3264 0, // GPRMM16MoveP:sub_32
3265 0, // GPRMM16MoveP:sub_64
3266 0, // GPRMM16MoveP:sub_dsp16_19
3267 0, // GPRMM16MoveP:sub_dsp20
3268 0, // GPRMM16MoveP:sub_dsp21
3269 0, // GPRMM16MoveP:sub_dsp22
3270 0, // GPRMM16MoveP:sub_dsp23
3271 0, // GPRMM16MoveP:sub_hi
3272 0, // GPRMM16MoveP:sub_lo
3273 0, // GPRMM16MoveP:sub_hi_then_sub_32
3274 0, // GPRMM16MoveP:sub_32_sub_hi_then_sub_32
3275 },
3276 { // GPRMM16Zero
3277 0, // GPRMM16Zero:sub_32
3278 0, // GPRMM16Zero:sub_64
3279 0, // GPRMM16Zero:sub_dsp16_19
3280 0, // GPRMM16Zero:sub_dsp20
3281 0, // GPRMM16Zero:sub_dsp21
3282 0, // GPRMM16Zero:sub_dsp22
3283 0, // GPRMM16Zero:sub_dsp23
3284 0, // GPRMM16Zero:sub_hi
3285 0, // GPRMM16Zero:sub_lo
3286 0, // GPRMM16Zero:sub_hi_then_sub_32
3287 0, // GPRMM16Zero:sub_32_sub_hi_then_sub_32
3288 },
3289 { // CPU16Regs_and_GPRMM16Zero
3290 0, // CPU16Regs_and_GPRMM16Zero:sub_32
3291 0, // CPU16Regs_and_GPRMM16Zero:sub_64
3292 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
3293 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp20
3294 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp21
3295 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp22
3296 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp23
3297 0, // CPU16Regs_and_GPRMM16Zero:sub_hi
3298 0, // CPU16Regs_and_GPRMM16Zero:sub_lo
3299 0, // CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
3300 0, // CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
3301 },
3302 { // GPR32NONZERO_and_GPRMM16MoveP
3303 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_32
3304 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_64
3305 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19
3306 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20
3307 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21
3308 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22
3309 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23
3310 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi
3311 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_lo
3312 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32
3313 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
3314 },
3315 { // GPRMM16MovePPairSecond
3316 0, // GPRMM16MovePPairSecond:sub_32
3317 0, // GPRMM16MovePPairSecond:sub_64
3318 0, // GPRMM16MovePPairSecond:sub_dsp16_19
3319 0, // GPRMM16MovePPairSecond:sub_dsp20
3320 0, // GPRMM16MovePPairSecond:sub_dsp21
3321 0, // GPRMM16MovePPairSecond:sub_dsp22
3322 0, // GPRMM16MovePPairSecond:sub_dsp23
3323 0, // GPRMM16MovePPairSecond:sub_hi
3324 0, // GPRMM16MovePPairSecond:sub_lo
3325 0, // GPRMM16MovePPairSecond:sub_hi_then_sub_32
3326 0, // GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
3327 },
3328 { // CPU16Regs_and_GPRMM16MoveP
3329 0, // CPU16Regs_and_GPRMM16MoveP:sub_32
3330 0, // CPU16Regs_and_GPRMM16MoveP:sub_64
3331 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19
3332 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp20
3333 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp21
3334 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp22
3335 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp23
3336 0, // CPU16Regs_and_GPRMM16MoveP:sub_hi
3337 0, // CPU16Regs_and_GPRMM16MoveP:sub_lo
3338 0, // CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32
3339 0, // CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
3340 },
3341 { // GPRMM16MoveP_and_GPRMM16Zero
3342 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_32
3343 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_64
3344 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19
3345 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20
3346 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21
3347 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22
3348 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23
3349 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi
3350 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_lo
3351 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32
3352 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
3353 },
3354 { // HI32DSP
3355 0, // HI32DSP:sub_32
3356 0, // HI32DSP:sub_64
3357 0, // HI32DSP:sub_dsp16_19
3358 0, // HI32DSP:sub_dsp20
3359 0, // HI32DSP:sub_dsp21
3360 0, // HI32DSP:sub_dsp22
3361 0, // HI32DSP:sub_dsp23
3362 0, // HI32DSP:sub_hi
3363 0, // HI32DSP:sub_lo
3364 0, // HI32DSP:sub_hi_then_sub_32
3365 0, // HI32DSP:sub_32_sub_hi_then_sub_32
3366 },
3367 { // LO32DSP
3368 0, // LO32DSP:sub_32
3369 0, // LO32DSP:sub_64
3370 0, // LO32DSP:sub_dsp16_19
3371 0, // LO32DSP:sub_dsp20
3372 0, // LO32DSP:sub_dsp21
3373 0, // LO32DSP:sub_dsp22
3374 0, // LO32DSP:sub_dsp23
3375 0, // LO32DSP:sub_hi
3376 0, // LO32DSP:sub_lo
3377 0, // LO32DSP:sub_hi_then_sub_32
3378 0, // LO32DSP:sub_32_sub_hi_then_sub_32
3379 },
3380 { // CPU16Regs_and_GPRMM16MovePPairSecond
3381 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32
3382 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_64
3383 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19
3384 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20
3385 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21
3386 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22
3387 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23
3388 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi
3389 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo
3390 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
3391 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
3392 },
3393 { // GPRMM16MovePPairFirst
3394 0, // GPRMM16MovePPairFirst:sub_32
3395 0, // GPRMM16MovePPairFirst:sub_64
3396 0, // GPRMM16MovePPairFirst:sub_dsp16_19
3397 0, // GPRMM16MovePPairFirst:sub_dsp20
3398 0, // GPRMM16MovePPairFirst:sub_dsp21
3399 0, // GPRMM16MovePPairFirst:sub_dsp22
3400 0, // GPRMM16MovePPairFirst:sub_dsp23
3401 0, // GPRMM16MovePPairFirst:sub_hi
3402 0, // GPRMM16MovePPairFirst:sub_lo
3403 0, // GPRMM16MovePPairFirst:sub_hi_then_sub_32
3404 0, // GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32
3405 },
3406 { // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
3407 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32
3408 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64
3409 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
3410 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20
3411 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21
3412 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22
3413 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23
3414 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi
3415 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo
3416 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
3417 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
3418 },
3419 { // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
3420 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32
3421 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64
3422 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19
3423 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20
3424 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21
3425 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22
3426 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23
3427 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi
3428 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo
3429 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
3430 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
3431 },
3432 { // CPURAReg
3433 0, // CPURAReg:sub_32
3434 0, // CPURAReg:sub_64
3435 0, // CPURAReg:sub_dsp16_19
3436 0, // CPURAReg:sub_dsp20
3437 0, // CPURAReg:sub_dsp21
3438 0, // CPURAReg:sub_dsp22
3439 0, // CPURAReg:sub_dsp23
3440 0, // CPURAReg:sub_hi
3441 0, // CPURAReg:sub_lo
3442 0, // CPURAReg:sub_hi_then_sub_32
3443 0, // CPURAReg:sub_32_sub_hi_then_sub_32
3444 },
3445 { // CPUSPReg
3446 0, // CPUSPReg:sub_32
3447 0, // CPUSPReg:sub_64
3448 0, // CPUSPReg:sub_dsp16_19
3449 0, // CPUSPReg:sub_dsp20
3450 0, // CPUSPReg:sub_dsp21
3451 0, // CPUSPReg:sub_dsp22
3452 0, // CPUSPReg:sub_dsp23
3453 0, // CPUSPReg:sub_hi
3454 0, // CPUSPReg:sub_lo
3455 0, // CPUSPReg:sub_hi_then_sub_32
3456 0, // CPUSPReg:sub_32_sub_hi_then_sub_32
3457 },
3458 { // DSPCC
3459 0, // DSPCC:sub_32
3460 0, // DSPCC:sub_64
3461 0, // DSPCC:sub_dsp16_19
3462 0, // DSPCC:sub_dsp20
3463 0, // DSPCC:sub_dsp21
3464 0, // DSPCC:sub_dsp22
3465 0, // DSPCC:sub_dsp23
3466 0, // DSPCC:sub_hi
3467 0, // DSPCC:sub_lo
3468 0, // DSPCC:sub_hi_then_sub_32
3469 0, // DSPCC:sub_32_sub_hi_then_sub_32
3470 },
3471 { // GP32
3472 0, // GP32:sub_32
3473 0, // GP32:sub_64
3474 0, // GP32:sub_dsp16_19
3475 0, // GP32:sub_dsp20
3476 0, // GP32:sub_dsp21
3477 0, // GP32:sub_dsp22
3478 0, // GP32:sub_dsp23
3479 0, // GP32:sub_hi
3480 0, // GP32:sub_lo
3481 0, // GP32:sub_hi_then_sub_32
3482 0, // GP32:sub_32_sub_hi_then_sub_32
3483 },
3484 { // GPR32ZERO
3485 0, // GPR32ZERO:sub_32
3486 0, // GPR32ZERO:sub_64
3487 0, // GPR32ZERO:sub_dsp16_19
3488 0, // GPR32ZERO:sub_dsp20
3489 0, // GPR32ZERO:sub_dsp21
3490 0, // GPR32ZERO:sub_dsp22
3491 0, // GPR32ZERO:sub_dsp23
3492 0, // GPR32ZERO:sub_hi
3493 0, // GPR32ZERO:sub_lo
3494 0, // GPR32ZERO:sub_hi_then_sub_32
3495 0, // GPR32ZERO:sub_32_sub_hi_then_sub_32
3496 },
3497 { // HI32
3498 0, // HI32:sub_32
3499 0, // HI32:sub_64
3500 0, // HI32:sub_dsp16_19
3501 0, // HI32:sub_dsp20
3502 0, // HI32:sub_dsp21
3503 0, // HI32:sub_dsp22
3504 0, // HI32:sub_dsp23
3505 0, // HI32:sub_hi
3506 0, // HI32:sub_lo
3507 0, // HI32:sub_hi_then_sub_32
3508 0, // HI32:sub_32_sub_hi_then_sub_32
3509 },
3510 { // LO32
3511 0, // LO32:sub_32
3512 0, // LO32:sub_64
3513 0, // LO32:sub_dsp16_19
3514 0, // LO32:sub_dsp20
3515 0, // LO32:sub_dsp21
3516 0, // LO32:sub_dsp22
3517 0, // LO32:sub_dsp23
3518 0, // LO32:sub_hi
3519 0, // LO32:sub_lo
3520 0, // LO32:sub_hi_then_sub_32
3521 0, // LO32:sub_32_sub_hi_then_sub_32
3522 },
3523 { // SP32
3524 0, // SP32:sub_32
3525 0, // SP32:sub_64
3526 0, // SP32:sub_dsp16_19
3527 0, // SP32:sub_dsp20
3528 0, // SP32:sub_dsp21
3529 0, // SP32:sub_dsp22
3530 0, // SP32:sub_dsp23
3531 0, // SP32:sub_hi
3532 0, // SP32:sub_lo
3533 0, // SP32:sub_hi_then_sub_32
3534 0, // SP32:sub_32_sub_hi_then_sub_32
3535 },
3536 { // FGR64CC
3537 0, // FGR64CC:sub_32
3538 0, // FGR64CC:sub_64
3539 0, // FGR64CC:sub_dsp16_19
3540 0, // FGR64CC:sub_dsp20
3541 0, // FGR64CC:sub_dsp21
3542 0, // FGR64CC:sub_dsp22
3543 0, // FGR64CC:sub_dsp23
3544 0, // FGR64CC:sub_hi
3545 7, // FGR64CC:sub_lo -> FGR32
3546 0, // FGR64CC:sub_hi_then_sub_32
3547 0, // FGR64CC:sub_32_sub_hi_then_sub_32
3548 },
3549 { // FGR64
3550 0, // FGR64:sub_32
3551 0, // FGR64:sub_64
3552 0, // FGR64:sub_dsp16_19
3553 0, // FGR64:sub_dsp20
3554 0, // FGR64:sub_dsp21
3555 0, // FGR64:sub_dsp22
3556 0, // FGR64:sub_dsp23
3557 0, // FGR64:sub_hi
3558 7, // FGR64:sub_lo -> FGR32
3559 0, // FGR64:sub_hi_then_sub_32
3560 0, // FGR64:sub_32_sub_hi_then_sub_32
3561 },
3562 { // GPR64
3563 6, // GPR64:sub_32 -> DSPR
3564 0, // GPR64:sub_64
3565 0, // GPR64:sub_dsp16_19
3566 0, // GPR64:sub_dsp20
3567 0, // GPR64:sub_dsp21
3568 0, // GPR64:sub_dsp22
3569 0, // GPR64:sub_dsp23
3570 0, // GPR64:sub_hi
3571 0, // GPR64:sub_lo
3572 0, // GPR64:sub_hi_then_sub_32
3573 0, // GPR64:sub_32_sub_hi_then_sub_32
3574 },
3575 { // GPR64_with_sub_32_in_GPR32NONZERO
3576 12, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32 -> GPR32NONZERO
3577 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_64
3578 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp16_19
3579 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp20
3580 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp21
3581 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp22
3582 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp23
3583 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi
3584 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_lo
3585 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi_then_sub_32
3586 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32_sub_hi_then_sub_32
3587 },
3588 { // AFGR64
3589 0, // AFGR64:sub_32
3590 0, // AFGR64:sub_64
3591 0, // AFGR64:sub_dsp16_19
3592 0, // AFGR64:sub_dsp20
3593 0, // AFGR64:sub_dsp21
3594 0, // AFGR64:sub_dsp22
3595 0, // AFGR64:sub_dsp23
3596 8, // AFGR64:sub_hi -> FGR32CC
3597 8, // AFGR64:sub_lo -> FGR32CC
3598 0, // AFGR64:sub_hi_then_sub_32
3599 0, // AFGR64:sub_32_sub_hi_then_sub_32
3600 },
3601 { // GPR64_with_sub_32_in_CPU16RegsPlusSP
3602 13, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32 -> CPU16RegsPlusSP
3603 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_64
3604 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp16_19
3605 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp20
3606 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp21
3607 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp22
3608 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp23
3609 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi
3610 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_lo
3611 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi_then_sub_32
3612 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32
3613 },
3614 { // GPR64_with_sub_32_in_CPU16Regs
3615 14, // GPR64_with_sub_32_in_CPU16Regs:sub_32 -> CPU16Regs
3616 0, // GPR64_with_sub_32_in_CPU16Regs:sub_64
3617 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp16_19
3618 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp20
3619 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp21
3620 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp22
3621 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp23
3622 0, // GPR64_with_sub_32_in_CPU16Regs:sub_hi
3623 0, // GPR64_with_sub_32_in_CPU16Regs:sub_lo
3624 0, // GPR64_with_sub_32_in_CPU16Regs:sub_hi_then_sub_32
3625 0, // GPR64_with_sub_32_in_CPU16Regs:sub_32_sub_hi_then_sub_32
3626 },
3627 { // GPR64_with_sub_32_in_GPRMM16MoveP
3628 17, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32 -> GPRMM16MoveP
3629 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_64
3630 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp16_19
3631 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp20
3632 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp21
3633 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp22
3634 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp23
3635 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi
3636 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_lo
3637 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi_then_sub_32
3638 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
3639 },
3640 { // GPR64_with_sub_32_in_GPRMM16Zero
3641 18, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32 -> GPRMM16Zero
3642 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_64
3643 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp16_19
3644 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp20
3645 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp21
3646 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp22
3647 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp23
3648 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi
3649 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_lo
3650 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi_then_sub_32
3651 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32_sub_hi_then_sub_32
3652 },
3653 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
3654 19, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32 -> CPU16Regs_and_GPRMM16Zero
3655 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_64
3656 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
3657 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp20
3658 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp21
3659 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp22
3660 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp23
3661 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi
3662 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_lo
3663 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
3664 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
3665 },
3666 { // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
3667 20, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32 -> GPR32NONZERO_and_GPRMM16MoveP
3668 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_64
3669 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19
3670 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20
3671 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21
3672 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22
3673 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23
3674 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi
3675 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_lo
3676 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32
3677 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
3678 },
3679 { // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
3680 21, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairSecond
3681 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_64
3682 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp16_19
3683 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp20
3684 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp21
3685 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp22
3686 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp23
3687 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi
3688 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_lo
3689 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi_then_sub_32
3690 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
3691 },
3692 { // ACC64DSP
3693 0, // ACC64DSP:sub_32
3694 0, // ACC64DSP:sub_64
3695 0, // ACC64DSP:sub_dsp16_19
3696 0, // ACC64DSP:sub_dsp20
3697 0, // ACC64DSP:sub_dsp21
3698 0, // ACC64DSP:sub_dsp22
3699 0, // ACC64DSP:sub_dsp23
3700 24, // ACC64DSP:sub_hi -> HI32DSP
3701 25, // ACC64DSP:sub_lo -> LO32DSP
3702 0, // ACC64DSP:sub_hi_then_sub_32
3703 0, // ACC64DSP:sub_32_sub_hi_then_sub_32
3704 },
3705 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
3706 22, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32 -> CPU16Regs_and_GPRMM16MoveP
3707 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_64
3708 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19
3709 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp20
3710 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp21
3711 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp22
3712 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp23
3713 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi
3714 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_lo
3715 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32
3716 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
3717 },
3718 { // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
3719 23, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_GPRMM16Zero
3720 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_64
3721 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19
3722 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20
3723 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21
3724 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22
3725 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23
3726 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi
3727 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_lo
3728 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32
3729 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
3730 },
3731 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
3732 26, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32 -> CPU16Regs_and_GPRMM16MovePPairSecond
3733 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_64
3734 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19
3735 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20
3736 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21
3737 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22
3738 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23
3739 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi
3740 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo
3741 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
3742 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
3743 },
3744 { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
3745 27, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32 -> GPRMM16MovePPairFirst
3746 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_64
3747 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp16_19
3748 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp20
3749 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp21
3750 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp22
3751 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp23
3752 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi
3753 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_lo
3754 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi_then_sub_32
3755 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32
3756 },
3757 { // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
3758 28, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
3759 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64
3760 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
3761 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20
3762 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21
3763 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22
3764 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23
3765 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi
3766 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo
3767 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
3768 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
3769 },
3770 { // OCTEON_MPL
3771 0, // OCTEON_MPL:sub_32
3772 0, // OCTEON_MPL:sub_64
3773 0, // OCTEON_MPL:sub_dsp16_19
3774 0, // OCTEON_MPL:sub_dsp20
3775 0, // OCTEON_MPL:sub_dsp21
3776 0, // OCTEON_MPL:sub_dsp22
3777 0, // OCTEON_MPL:sub_dsp23
3778 0, // OCTEON_MPL:sub_hi
3779 0, // OCTEON_MPL:sub_lo
3780 0, // OCTEON_MPL:sub_hi_then_sub_32
3781 0, // OCTEON_MPL:sub_32_sub_hi_then_sub_32
3782 },
3783 { // OCTEON_P
3784 0, // OCTEON_P:sub_32
3785 0, // OCTEON_P:sub_64
3786 0, // OCTEON_P:sub_dsp16_19
3787 0, // OCTEON_P:sub_dsp20
3788 0, // OCTEON_P:sub_dsp21
3789 0, // OCTEON_P:sub_dsp22
3790 0, // OCTEON_P:sub_dsp23
3791 0, // OCTEON_P:sub_hi
3792 0, // OCTEON_P:sub_lo
3793 0, // OCTEON_P:sub_hi_then_sub_32
3794 0, // OCTEON_P:sub_32_sub_hi_then_sub_32
3795 },
3796 { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
3797 29, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
3798 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64
3799 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19
3800 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20
3801 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21
3802 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22
3803 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23
3804 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi
3805 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo
3806 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
3807 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
3808 },
3809 { // ACC64
3810 0, // ACC64:sub_32
3811 0, // ACC64:sub_64
3812 0, // ACC64:sub_dsp16_19
3813 0, // ACC64:sub_dsp20
3814 0, // ACC64:sub_dsp21
3815 0, // ACC64:sub_dsp22
3816 0, // ACC64:sub_dsp23
3817 35, // ACC64:sub_hi -> HI32
3818 36, // ACC64:sub_lo -> LO32
3819 0, // ACC64:sub_hi_then_sub_32
3820 0, // ACC64:sub_32_sub_hi_then_sub_32
3821 },
3822 { // GP64
3823 33, // GP64:sub_32 -> GP32
3824 0, // GP64:sub_64
3825 0, // GP64:sub_dsp16_19
3826 0, // GP64:sub_dsp20
3827 0, // GP64:sub_dsp21
3828 0, // GP64:sub_dsp22
3829 0, // GP64:sub_dsp23
3830 0, // GP64:sub_hi
3831 0, // GP64:sub_lo
3832 0, // GP64:sub_hi_then_sub_32
3833 0, // GP64:sub_32_sub_hi_then_sub_32
3834 },
3835 { // GPR64_with_sub_32_in_CPURAReg
3836 30, // GPR64_with_sub_32_in_CPURAReg:sub_32 -> CPURAReg
3837 0, // GPR64_with_sub_32_in_CPURAReg:sub_64
3838 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp16_19
3839 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp20
3840 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp21
3841 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp22
3842 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp23
3843 0, // GPR64_with_sub_32_in_CPURAReg:sub_hi
3844 0, // GPR64_with_sub_32_in_CPURAReg:sub_lo
3845 0, // GPR64_with_sub_32_in_CPURAReg:sub_hi_then_sub_32
3846 0, // GPR64_with_sub_32_in_CPURAReg:sub_32_sub_hi_then_sub_32
3847 },
3848 { // GPR64_with_sub_32_in_GPR32ZERO
3849 34, // GPR64_with_sub_32_in_GPR32ZERO:sub_32 -> GPR32ZERO
3850 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_64
3851 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp16_19
3852 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp20
3853 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp21
3854 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp22
3855 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp23
3856 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi
3857 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_lo
3858 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi_then_sub_32
3859 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_32_sub_hi_then_sub_32
3860 },
3861 { // HI64
3862 35, // HI64:sub_32 -> HI32
3863 0, // HI64:sub_64
3864 0, // HI64:sub_dsp16_19
3865 0, // HI64:sub_dsp20
3866 0, // HI64:sub_dsp21
3867 0, // HI64:sub_dsp22
3868 0, // HI64:sub_dsp23
3869 0, // HI64:sub_hi
3870 0, // HI64:sub_lo
3871 0, // HI64:sub_hi_then_sub_32
3872 0, // HI64:sub_32_sub_hi_then_sub_32
3873 },
3874 { // LO64
3875 36, // LO64:sub_32 -> LO32
3876 0, // LO64:sub_64
3877 0, // LO64:sub_dsp16_19
3878 0, // LO64:sub_dsp20
3879 0, // LO64:sub_dsp21
3880 0, // LO64:sub_dsp22
3881 0, // LO64:sub_dsp23
3882 0, // LO64:sub_hi
3883 0, // LO64:sub_lo
3884 0, // LO64:sub_hi_then_sub_32
3885 0, // LO64:sub_32_sub_hi_then_sub_32
3886 },
3887 { // SP64
3888 31, // SP64:sub_32 -> CPUSPReg
3889 0, // SP64:sub_64
3890 0, // SP64:sub_dsp16_19
3891 0, // SP64:sub_dsp20
3892 0, // SP64:sub_dsp21
3893 0, // SP64:sub_dsp22
3894 0, // SP64:sub_dsp23
3895 0, // SP64:sub_hi
3896 0, // SP64:sub_lo
3897 0, // SP64:sub_hi_then_sub_32
3898 0, // SP64:sub_32_sub_hi_then_sub_32
3899 },
3900 { // MSA128B
3901 0, // MSA128B:sub_32
3902 38, // MSA128B:sub_64 -> FGR64CC
3903 0, // MSA128B:sub_dsp16_19
3904 0, // MSA128B:sub_dsp20
3905 0, // MSA128B:sub_dsp21
3906 0, // MSA128B:sub_dsp22
3907 0, // MSA128B:sub_dsp23
3908 0, // MSA128B:sub_hi
3909 7, // MSA128B:sub_lo -> FGR32
3910 0, // MSA128B:sub_hi_then_sub_32
3911 0, // MSA128B:sub_32_sub_hi_then_sub_32
3912 },
3913 { // MSA128D
3914 0, // MSA128D:sub_32
3915 38, // MSA128D:sub_64 -> FGR64CC
3916 0, // MSA128D:sub_dsp16_19
3917 0, // MSA128D:sub_dsp20
3918 0, // MSA128D:sub_dsp21
3919 0, // MSA128D:sub_dsp22
3920 0, // MSA128D:sub_dsp23
3921 0, // MSA128D:sub_hi
3922 7, // MSA128D:sub_lo -> FGR32
3923 0, // MSA128D:sub_hi_then_sub_32
3924 0, // MSA128D:sub_32_sub_hi_then_sub_32
3925 },
3926 { // MSA128H
3927 0, // MSA128H:sub_32
3928 38, // MSA128H:sub_64 -> FGR64CC
3929 0, // MSA128H:sub_dsp16_19
3930 0, // MSA128H:sub_dsp20
3931 0, // MSA128H:sub_dsp21
3932 0, // MSA128H:sub_dsp22
3933 0, // MSA128H:sub_dsp23
3934 0, // MSA128H:sub_hi
3935 7, // MSA128H:sub_lo -> FGR32
3936 0, // MSA128H:sub_hi_then_sub_32
3937 0, // MSA128H:sub_32_sub_hi_then_sub_32
3938 },
3939 { // MSA128W
3940 0, // MSA128W:sub_32
3941 38, // MSA128W:sub_64 -> FGR64CC
3942 0, // MSA128W:sub_dsp16_19
3943 0, // MSA128W:sub_dsp20
3944 0, // MSA128W:sub_dsp21
3945 0, // MSA128W:sub_dsp22
3946 0, // MSA128W:sub_dsp23
3947 0, // MSA128W:sub_hi
3948 7, // MSA128W:sub_lo -> FGR32
3949 0, // MSA128W:sub_hi_then_sub_32
3950 0, // MSA128W:sub_32_sub_hi_then_sub_32
3951 },
3952 { // MSA128WEvens
3953 0, // MSA128WEvens:sub_32
3954 39, // MSA128WEvens:sub_64 -> FGR64
3955 0, // MSA128WEvens:sub_dsp16_19
3956 0, // MSA128WEvens:sub_dsp20
3957 0, // MSA128WEvens:sub_dsp21
3958 0, // MSA128WEvens:sub_dsp22
3959 0, // MSA128WEvens:sub_dsp23
3960 0, // MSA128WEvens:sub_hi
3961 8, // MSA128WEvens:sub_lo -> FGR32CC
3962 0, // MSA128WEvens:sub_hi_then_sub_32
3963 0, // MSA128WEvens:sub_32_sub_hi_then_sub_32
3964 },
3965 { // ACC128
3966 36, // ACC128:sub_32 -> LO32
3967 0, // ACC128:sub_64
3968 0, // ACC128:sub_dsp16_19
3969 0, // ACC128:sub_dsp20
3970 0, // ACC128:sub_dsp21
3971 0, // ACC128:sub_dsp22
3972 0, // ACC128:sub_dsp23
3973 63, // ACC128:sub_hi -> HI64
3974 64, // ACC128:sub_lo -> LO64
3975 35, // ACC128:sub_hi_then_sub_32 -> HI32
3976 59, // ACC128:sub_32_sub_hi_then_sub_32 -> ACC64
3977 },
3978 };
3979 assert(RC && "Missing regclass");
3980 if (!Idx) return RC;
3981 --Idx;
3982 assert(Idx < 11 && "Bad subreg");
3983 unsigned TV = Table[RC->getID()][Idx];
3984 return TV ? getRegClass(i: TV - 1) : nullptr;
3985}
3986
3987/// Get the weight in units of pressure for this register class.
3988const RegClassWeight &MipsGenRegisterInfo::
3989getRegClassWeight(const TargetRegisterClass *RC) const {
3990 static const RegClassWeight RCWeightTable[] = {
3991 {.RegWeight: 2, .WeightLimit: 64}, // MSA128F16
3992 {.RegWeight: 0, .WeightLimit: 0}, // CCR
3993 {.RegWeight: 0, .WeightLimit: 0}, // COP0
3994 {.RegWeight: 0, .WeightLimit: 0}, // COP2
3995 {.RegWeight: 0, .WeightLimit: 0}, // COP3
3996 {.RegWeight: 1, .WeightLimit: 32}, // DSPR
3997 {.RegWeight: 1, .WeightLimit: 32}, // FGR32
3998 {.RegWeight: 1, .WeightLimit: 32}, // FGR32CC
3999 {.RegWeight: 1, .WeightLimit: 32}, // GPR32
4000 {.RegWeight: 0, .WeightLimit: 0}, // HWRegs
4001 {.RegWeight: 0, .WeightLimit: 0}, // MSACtrl
4002 {.RegWeight: 1, .WeightLimit: 31}, // GPR32NONZERO
4003 {.RegWeight: 1, .WeightLimit: 9}, // CPU16RegsPlusSP
4004 {.RegWeight: 1, .WeightLimit: 8}, // CPU16Regs
4005 {.RegWeight: 0, .WeightLimit: 0}, // FCC
4006 {.RegWeight: 1, .WeightLimit: 8}, // GPRMM16
4007 {.RegWeight: 1, .WeightLimit: 8}, // GPRMM16MoveP
4008 {.RegWeight: 1, .WeightLimit: 8}, // GPRMM16Zero
4009 {.RegWeight: 1, .WeightLimit: 7}, // CPU16Regs_and_GPRMM16Zero
4010 {.RegWeight: 1, .WeightLimit: 7}, // GPR32NONZERO_and_GPRMM16MoveP
4011 {.RegWeight: 1, .WeightLimit: 5}, // GPRMM16MovePPairSecond
4012 {.RegWeight: 1, .WeightLimit: 4}, // CPU16Regs_and_GPRMM16MoveP
4013 {.RegWeight: 1, .WeightLimit: 4}, // GPRMM16MoveP_and_GPRMM16Zero
4014 {.RegWeight: 1, .WeightLimit: 4}, // HI32DSP
4015 {.RegWeight: 1, .WeightLimit: 4}, // LO32DSP
4016 {.RegWeight: 1, .WeightLimit: 3}, // CPU16Regs_and_GPRMM16MovePPairSecond
4017 {.RegWeight: 1, .WeightLimit: 3}, // GPRMM16MovePPairFirst
4018 {.RegWeight: 1, .WeightLimit: 3}, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
4019 {.RegWeight: 1, .WeightLimit: 2}, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
4020 {.RegWeight: 1, .WeightLimit: 1}, // CPURAReg
4021 {.RegWeight: 1, .WeightLimit: 1}, // CPUSPReg
4022 {.RegWeight: 1, .WeightLimit: 1}, // DSPCC
4023 {.RegWeight: 1, .WeightLimit: 1}, // GP32
4024 {.RegWeight: 1, .WeightLimit: 1}, // GPR32ZERO
4025 {.RegWeight: 1, .WeightLimit: 1}, // HI32
4026 {.RegWeight: 1, .WeightLimit: 1}, // LO32
4027 {.RegWeight: 1, .WeightLimit: 1}, // SP32
4028 {.RegWeight: 2, .WeightLimit: 64}, // FGR64CC
4029 {.RegWeight: 2, .WeightLimit: 64}, // FGR64
4030 {.RegWeight: 1, .WeightLimit: 32}, // GPR64
4031 {.RegWeight: 1, .WeightLimit: 31}, // GPR64_with_sub_32_in_GPR32NONZERO
4032 {.RegWeight: 2, .WeightLimit: 32}, // AFGR64
4033 {.RegWeight: 1, .WeightLimit: 9}, // GPR64_with_sub_32_in_CPU16RegsPlusSP
4034 {.RegWeight: 1, .WeightLimit: 8}, // GPR64_with_sub_32_in_CPU16Regs
4035 {.RegWeight: 1, .WeightLimit: 8}, // GPR64_with_sub_32_in_GPRMM16MoveP
4036 {.RegWeight: 1, .WeightLimit: 8}, // GPR64_with_sub_32_in_GPRMM16Zero
4037 {.RegWeight: 1, .WeightLimit: 7}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
4038 {.RegWeight: 1, .WeightLimit: 7}, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
4039 {.RegWeight: 1, .WeightLimit: 5}, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
4040 {.RegWeight: 2, .WeightLimit: 8}, // ACC64DSP
4041 {.RegWeight: 1, .WeightLimit: 4}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
4042 {.RegWeight: 1, .WeightLimit: 4}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
4043 {.RegWeight: 1, .WeightLimit: 3}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
4044 {.RegWeight: 1, .WeightLimit: 3}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
4045 {.RegWeight: 1, .WeightLimit: 3}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
4046 {.RegWeight: 0, .WeightLimit: 0}, // OCTEON_MPL
4047 {.RegWeight: 0, .WeightLimit: 0}, // OCTEON_P
4048 {.RegWeight: 1, .WeightLimit: 2}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
4049 {.RegWeight: 2, .WeightLimit: 2}, // ACC64
4050 {.RegWeight: 1, .WeightLimit: 1}, // GP64
4051 {.RegWeight: 1, .WeightLimit: 1}, // GPR64_with_sub_32_in_CPURAReg
4052 {.RegWeight: 1, .WeightLimit: 1}, // GPR64_with_sub_32_in_GPR32ZERO
4053 {.RegWeight: 1, .WeightLimit: 1}, // HI64
4054 {.RegWeight: 1, .WeightLimit: 1}, // LO64
4055 {.RegWeight: 1, .WeightLimit: 1}, // SP64
4056 {.RegWeight: 2, .WeightLimit: 64}, // MSA128B
4057 {.RegWeight: 2, .WeightLimit: 64}, // MSA128D
4058 {.RegWeight: 2, .WeightLimit: 64}, // MSA128H
4059 {.RegWeight: 2, .WeightLimit: 64}, // MSA128W
4060 {.RegWeight: 2, .WeightLimit: 32}, // MSA128WEvens
4061 {.RegWeight: 2, .WeightLimit: 2}, // ACC128
4062 };
4063 return RCWeightTable[RC->getID()];
4064}
4065
4066/// Get the weight in units of pressure for this register unit.
4067unsigned MipsGenRegisterInfo::
4068getRegUnitWeight(MCRegUnit RegUnit) const {
4069 assert(static_cast<unsigned>(RegUnit) < 321 && "invalid register unit");
4070 // All register units have unit weight.
4071 return 1;
4072}
4073
4074
4075// Get the number of dimensions of register pressure.
4076unsigned MipsGenRegisterInfo::getNumRegPressureSets() const {
4077 return 20;
4078}
4079
4080// Get the name of this register unit pressure set.
4081const char *MipsGenRegisterInfo::
4082getRegPressureSetName(unsigned Idx) const {
4083 static const char *PressureNameTable[] = {
4084 "DSPCC",
4085 "GPR32ZERO",
4086 "GPR64_with_sub_32_in_CPURAReg",
4087 "HI32",
4088 "GPRMM16MovePPairFirst",
4089 "CPU16Regs_and_GPRMM16MoveP",
4090 "HI32DSP",
4091 "LO32DSP",
4092 "GPRMM16MovePPairSecond",
4093 "GPRMM16MoveP",
4094 "ACC64DSP",
4095 "CPU16Regs",
4096 "GPRMM16Zero_with_GPRMM16MovePPairSecond",
4097 "CPU16Regs_with_GPRMM16MovePPairSecond",
4098 "CPU16Regs_with_GPRMM16MoveP",
4099 "DSPR",
4100 "FGR32",
4101 "MSA128WEvens",
4102 "FGR32_with_MSA128WEvens",
4103 "MSA128F16",
4104 };
4105 return PressureNameTable[Idx];
4106}
4107
4108// Get the register unit pressure limit for this dimension.
4109// This limit must be adjusted dynamically for reserved registers.
4110unsigned MipsGenRegisterInfo::
4111getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
4112 static const uint8_t PressureLimitTable[] = {
4113 1, // 0: DSPCC
4114 1, // 1: GPR32ZERO
4115 1, // 2: GPR64_with_sub_32_in_CPURAReg
4116 2, // 3: HI32
4117 3, // 4: GPRMM16MovePPairFirst
4118 5, // 5: CPU16Regs_and_GPRMM16MoveP
4119 5, // 6: HI32DSP
4120 5, // 7: LO32DSP
4121 6, // 8: GPRMM16MovePPairSecond
4122 8, // 9: GPRMM16MoveP
4123 8, // 10: ACC64DSP
4124 10, // 11: CPU16Regs
4125 10, // 12: GPRMM16Zero_with_GPRMM16MovePPairSecond
4126 11, // 13: CPU16Regs_with_GPRMM16MovePPairSecond
4127 13, // 14: CPU16Regs_with_GPRMM16MoveP
4128 32, // 15: DSPR
4129 32, // 16: FGR32
4130 32, // 17: MSA128WEvens
4131 48, // 18: FGR32_with_MSA128WEvens
4132 64, // 19: MSA128F16
4133 };
4134 return PressureLimitTable[Idx];
4135}
4136
4137/// Table of pressure sets per register class or unit.
4138static const int RCSetsTable[] = {
4139 /* 0 */ 0, -1,
4140 /* 2 */ 6, 10, -1,
4141 /* 5 */ 3, 6, 7, 10, -1,
4142 /* 10 */ 2, 15, -1,
4143 /* 13 */ 8, 12, 13, 15, -1,
4144 /* 18 */ 9, 14, 15, -1,
4145 /* 22 */ 1, 5, 9, 11, 12, 14, 15, -1,
4146 /* 30 */ 5, 9, 11, 13, 14, 15, -1,
4147 /* 37 */ 4, 8, 11, 12, 13, 14, 15, -1,
4148 /* 45 */ 5, 9, 11, 12, 13, 14, 15, -1,
4149 /* 53 */ 16, 18, 19, -1,
4150 /* 57 */ 16, 17, 18, 19, -1,
4151};
4152
4153/// Get the dimensions of register pressure impacted by this register class.
4154/// Returns a -1 terminated array of pressure set IDs
4155const int *MipsGenRegisterInfo::
4156getRegClassPressureSets(const TargetRegisterClass *RC) const {
4157 static const uint8_t RCSetStartTable[] = {
4158 55,1,1,1,1,11,53,53,11,1,1,11,32,32,1,32,18,25,39,18,13,30,23,2,7,38,37,45,37,1,1,0,1,22,5,5,1,55,55,11,11,53,32,32,18,25,39,18,13,3,30,23,38,37,45,1,1,37,5,1,10,22,5,5,1,55,55,55,55,58,5,};
4159 return &RCSetsTable[RCSetStartTable[RC->getID()]];
4160}
4161
4162/// Get the dimensions of register pressure impacted by this register unit.
4163/// Returns a -1 terminated array of pressure set IDs
4164const int *MipsGenRegisterInfo::
4165getRegUnitPressureSets(MCRegUnit RegUnit) const {
4166 assert(static_cast<unsigned>(RegUnit) < 321 && "invalid register unit");
4167 static const uint8_t RUSetStartTable[] = {
4168 11,0,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,10,32,22,37,37,37,38,5,5,7,2,7,2,7,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,30,45,18,18,18,13,13,11,11,11,11,11,11,11,11,11,11,11,45,45,};
4169 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
4170}
4171
4172extern const MCRegisterDesc MipsRegDesc[];
4173extern const int16_t MipsRegDiffLists[];
4174extern const LaneBitmask MipsLaneMaskLists[];
4175extern const char MipsRegStrings[];
4176extern const char MipsRegClassStrings[];
4177extern const MCPhysReg MipsRegUnitRoots[][2];
4178extern const uint16_t MipsSubRegIdxLists[];
4179extern const uint16_t MipsRegEncodingTable[];
4180// Mips Dwarf<->LLVM register mappings.
4181extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[];
4182extern const unsigned MipsDwarfFlavour0Dwarf2LSize;
4183
4184extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[];
4185extern const unsigned MipsEHFlavour0Dwarf2LSize;
4186
4187extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[];
4188extern const unsigned MipsDwarfFlavour0L2DwarfSize;
4189
4190extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[];
4191extern const unsigned MipsEHFlavour0L2DwarfSize;
4192
4193MipsGenRegisterInfo::
4194MipsGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
4195 unsigned PC, unsigned HwMode)
4196 : TargetRegisterInfo(&MipsRegInfoDesc, RegisterClasses, RegisterClasses+71,
4197 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
4198 LaneBitmask(0xFFFFFFFFFFFFFF80), RegClassInfos, VTLists, HwMode) {
4199 InitMCRegisterInfo(D: MipsRegDesc, NR: 442, RA, PC,
4200 C: MipsMCRegisterClasses, NC: 71,
4201 RURoots: MipsRegUnitRoots,
4202 NRU: 321,
4203 DL: MipsRegDiffLists,
4204 RUMS: MipsLaneMaskLists,
4205 Strings: MipsRegStrings,
4206 ClassStrings: MipsRegClassStrings,
4207 SubIndices: MipsSubRegIdxLists,
4208 NumIndices: 12,
4209 RET: MipsRegEncodingTable);
4210
4211 switch (DwarfFlavour) {
4212 default:
4213 llvm_unreachable("Unknown DWARF flavour");
4214 case 0:
4215 mapDwarfRegsToLLVMRegs(Map: MipsDwarfFlavour0Dwarf2L, Size: MipsDwarfFlavour0Dwarf2LSize, isEH: false);
4216 break;
4217 }
4218 switch (EHFlavour) {
4219 default:
4220 llvm_unreachable("Unknown DWARF flavour");
4221 case 0:
4222 mapDwarfRegsToLLVMRegs(Map: MipsEHFlavour0Dwarf2L, Size: MipsEHFlavour0Dwarf2LSize, isEH: true);
4223 break;
4224 }
4225 switch (DwarfFlavour) {
4226 default:
4227 llvm_unreachable("Unknown DWARF flavour");
4228 case 0:
4229 mapLLVMRegsToDwarfRegs(Map: MipsDwarfFlavour0L2Dwarf, Size: MipsDwarfFlavour0L2DwarfSize, isEH: false);
4230 break;
4231 }
4232 switch (EHFlavour) {
4233 default:
4234 llvm_unreachable("Unknown DWARF flavour");
4235 case 0:
4236 mapLLVMRegsToDwarfRegs(Map: MipsEHFlavour0L2Dwarf, Size: MipsEHFlavour0L2DwarfSize, isEH: true);
4237 break;
4238 }
4239}
4240
4241static const MCPhysReg CSR_Interrupt_32_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, Mips::LO0, Mips::HI0, 0 };
4242static const uint32_t CSR_Interrupt_32_RegMask[] = { 0x07e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000, 0x00000008, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };
4243static const MCPhysReg CSR_Interrupt_32R6_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, 0 };
4244static const uint32_t CSR_Interrupt_32R6_RegMask[] = { 0x03e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };
4245static const MCPhysReg CSR_Interrupt_64_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::V1_64, Mips::V0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, Mips::LO0_64, Mips::HI0_64, 0 };
4246static const uint32_t CSR_Interrupt_64_RegMask[] = { 0x47e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x30000000, 0x00000000, 0x00000008, 0x07ffbfe0, 0xf8000000, 0x00000001, 0x03ffffe4, };
4247static const MCPhysReg CSR_Interrupt_64R6_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::V1_64, Mips::V0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, 0 };
4248static const uint32_t CSR_Interrupt_64R6_RegMask[] = { 0x43e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x07ffbfe0, 0xf8000000, 0x00000000, 0x03ffffc0, };
4249static const MCPhysReg CSR_Mips16RetHelper_SaveList[] = { Mips::V0, Mips::V1, Mips::FP, Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, 0 };
4250static const uint32_t CSR_Mips16RetHelper_RegMask[] = { 0x03e00100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06003fc0, 0x08000000, 0x00000000, 0x00000000, };
4251static const MCPhysReg CSR_N32_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
4252static const uint32_t CSR_N32_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x08000000, 0x15550000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xaaa00000, 0x00003fc0, };
4253static const MCPhysReg CSR_N32_SingleFloat_SaveList[] = { Mips::F30, Mips::F28, Mips::F26, Mips::F24, Mips::F22, Mips::F20, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
4254static const uint32_t CSR_N32_SingleFloat_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0x00000000, 0x00003fc0, };
4255static const MCPhysReg CSR_N64_SaveList[] = { Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64, Mips::D26_64, Mips::D25_64, Mips::D24_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
4256static const uint32_t CSR_N64_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00007800, 0x0007f800, 0x08000000, 0x1ff00000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xfe000000, 0x00003fc1, };
4257static const MCPhysReg CSR_N64_SingleFloat_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
4258static const uint32_t CSR_N64_SingleFloat_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00007800, 0x0007f800, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0x00000000, 0x00003fc0, };
4259static const MCPhysReg CSR_O32_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
4260static const uint32_t CSR_O32_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };
4261static const MCPhysReg CSR_O32_FP64_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
4262static const uint32_t CSR_O32_FP64_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x00000000, 0x05550000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0xaaa00000, 0x00000000, };
4263static const MCPhysReg CSR_O32_FPXX_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
4264static const uint32_t CSR_O32_FPXX_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };
4265static const MCPhysReg CSR_O32_SingleFloat_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
4266static const uint32_t CSR_O32_SingleFloat_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };
4267
4268
4269ArrayRef<const uint32_t *> MipsGenRegisterInfo::getRegMasks() const {
4270 static const uint32_t *const Masks[] = {
4271 CSR_Interrupt_32_RegMask,
4272 CSR_Interrupt_32R6_RegMask,
4273 CSR_Interrupt_64_RegMask,
4274 CSR_Interrupt_64R6_RegMask,
4275 CSR_Mips16RetHelper_RegMask,
4276 CSR_N32_RegMask,
4277 CSR_N32_SingleFloat_RegMask,
4278 CSR_N64_RegMask,
4279 CSR_N64_SingleFloat_RegMask,
4280 CSR_O32_RegMask,
4281 CSR_O32_FP64_RegMask,
4282 CSR_O32_FPXX_RegMask,
4283 CSR_O32_SingleFloat_RegMask,
4284 };
4285 return ArrayRef(Masks);
4286}
4287
4288bool MipsGenRegisterInfo::
4289isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
4290 return
4291 false;
4292}
4293
4294bool MipsGenRegisterInfo::
4295isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
4296 return
4297 false;
4298}
4299
4300bool MipsGenRegisterInfo::
4301isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
4302 return
4303 false;
4304}
4305
4306bool MipsGenRegisterInfo::
4307isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
4308 return
4309 false;
4310}
4311
4312bool MipsGenRegisterInfo::
4313isConstantPhysReg(MCRegister PhysReg) const {
4314 return
4315 PhysReg == Mips::ZERO ||
4316 PhysReg == Mips::ZERO_64 ||
4317 false;
4318}
4319
4320ArrayRef<const char *> MipsGenRegisterInfo::getRegMaskNames() const {
4321 static const char *Names[] = {
4322 "CSR_Interrupt_32",
4323 "CSR_Interrupt_32R6",
4324 "CSR_Interrupt_64",
4325 "CSR_Interrupt_64R6",
4326 "CSR_Mips16RetHelper",
4327 "CSR_N32",
4328 "CSR_N32_SingleFloat",
4329 "CSR_N64",
4330 "CSR_N64_SingleFloat",
4331 "CSR_O32",
4332 "CSR_O32_FP64",
4333 "CSR_O32_FPXX",
4334 "CSR_O32_SingleFloat",
4335 };
4336 return ArrayRef(Names);
4337}
4338
4339const MipsFrameLowering *
4340MipsGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
4341 return static_cast<const MipsFrameLowering *>(
4342 MF.getSubtarget().getFrameLowering());
4343}
4344
4345} // end namespace llvm
4346
4347