| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Target Register and Register Classes Information *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | namespace llvm { |
| 10 | |
| 11 | extern const MCRegisterClassStorage<70, 830, 2580, 336, 18, 197> MipsMCRegisterClassStorage; |
| 12 | |
| 13 | static const MVT::SimpleValueType MipsVTLists[] = { |
| 14 | /* 0 */ MVT::v4i8, MVT::v2i16, MVT::i32, MVT::Other, |
| 15 | /* 4 */ MVT::i64, MVT::Other, |
| 16 | /* 6 */ MVT::f32, MVT::Other, |
| 17 | /* 8 */ MVT::i32, MVT::f32, MVT::f64, MVT::Other, |
| 18 | /* 12 */ MVT::v16i8, MVT::Other, |
| 19 | /* 14 */ MVT::v4i8, MVT::v2i16, MVT::Other, |
| 20 | /* 17 */ MVT::v8i16, MVT::v8f16, MVT::Other, |
| 21 | /* 20 */ MVT::v4i32, MVT::v4f32, MVT::Other, |
| 22 | /* 23 */ MVT::v2i64, MVT::v2f64, MVT::Other, |
| 23 | /* 26 */ MVT::Untyped, MVT::Other, |
| 24 | }; |
| 25 | |
| 26 | #ifdef __GNUC__ |
| 27 | #pragma GCC diagnostic push |
| 28 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 29 | #endif |
| 30 | static constexpr char MipsSubRegIndexStrings[] = { |
| 31 | /* 0 */ "sub_dsp20\000" |
| 32 | /* 10 */ "sub_dsp21\000" |
| 33 | /* 20 */ "sub_dsp22\000" |
| 34 | /* 30 */ "sub_32_sub_hi_then_sub_32\000" |
| 35 | /* 56 */ "sub_dsp23\000" |
| 36 | /* 66 */ "sub_64\000" |
| 37 | /* 73 */ "sub_dsp16_19\000" |
| 38 | /* 86 */ "sub_hi\000" |
| 39 | /* 93 */ "sub_lo\000" |
| 40 | }; |
| 41 | #ifdef __GNUC__ |
| 42 | #pragma GCC diagnostic pop |
| 43 | #endif |
| 44 | |
| 45 | |
| 46 | static constexpr uint32_t MipsSubRegIndexNameOffsets[] = { |
| 47 | 49, |
| 48 | 66, |
| 49 | 73, |
| 50 | 0, |
| 51 | 10, |
| 52 | 20, |
| 53 | 56, |
| 54 | 86, |
| 55 | 93, |
| 56 | 37, |
| 57 | 30, |
| 58 | }; |
| 59 | |
| 60 | static const TargetRegisterInfo::SubRegCoveredBits MipsSubRegIdxRangeTable[] = { |
| 61 | { .Offset: 4294967295, .Size: 4294967295 }, |
| 62 | { .Offset: 0, .Size: 32 }, // sub_32 |
| 63 | { .Offset: 0, .Size: 64 }, // sub_64 |
| 64 | { .Offset: 16, .Size: 4 }, // sub_dsp16_19 |
| 65 | { .Offset: 20, .Size: 1 }, // sub_dsp20 |
| 66 | { .Offset: 21, .Size: 1 }, // sub_dsp21 |
| 67 | { .Offset: 22, .Size: 1 }, // sub_dsp22 |
| 68 | { .Offset: 23, .Size: 1 }, // sub_dsp23 |
| 69 | { .Offset: 32, .Size: 32 }, // sub_hi |
| 70 | { .Offset: 0, .Size: 32 }, // sub_lo |
| 71 | { .Offset: 32, .Size: 32 }, // sub_hi_then_sub_32 |
| 72 | { .Offset: 0, .Size: 64 }, // sub_32_sub_hi_then_sub_32 |
| 73 | { .Offset: 4294967295, .Size: 4294967295 }, |
| 74 | { .Offset: 0, .Size: 32 }, // sub_32 |
| 75 | { .Offset: 0, .Size: 64 }, // sub_64 |
| 76 | { .Offset: 16, .Size: 4 }, // sub_dsp16_19 |
| 77 | { .Offset: 20, .Size: 1 }, // sub_dsp20 |
| 78 | { .Offset: 21, .Size: 1 }, // sub_dsp21 |
| 79 | { .Offset: 22, .Size: 1 }, // sub_dsp22 |
| 80 | { .Offset: 23, .Size: 1 }, // sub_dsp23 |
| 81 | { .Offset: 32, .Size: 32 }, // sub_hi |
| 82 | { .Offset: 0, .Size: 32 }, // sub_lo |
| 83 | { .Offset: 32, .Size: 32 }, // sub_hi_then_sub_32 |
| 84 | { .Offset: 0, .Size: 64 }, // sub_32_sub_hi_then_sub_32 |
| 85 | }; |
| 86 | |
| 87 | |
| 88 | static const LaneBitmask MipsSubRegIndexLaneMaskTable[] = { |
| 89 | LaneBitmask::getAll(), |
| 90 | LaneBitmask(0x0000000000000001), // sub_32 |
| 91 | LaneBitmask(0x0000000000000041), // sub_64 |
| 92 | LaneBitmask(0x0000000000000002), // sub_dsp16_19 |
| 93 | LaneBitmask(0x0000000000000004), // sub_dsp20 |
| 94 | LaneBitmask(0x0000000000000008), // sub_dsp21 |
| 95 | LaneBitmask(0x0000000000000010), // sub_dsp22 |
| 96 | LaneBitmask(0x0000000000000020), // sub_dsp23 |
| 97 | LaneBitmask(0x0000000000000040), // sub_hi |
| 98 | LaneBitmask(0x0000000000000001), // sub_lo |
| 99 | LaneBitmask(0x0000000000000040), // sub_hi_then_sub_32 |
| 100 | LaneBitmask(0x0000000000000041), // sub_32_sub_hi_then_sub_32 |
| 101 | }; |
| 102 | |
| 103 | |
| 104 | |
| 105 | static const TargetRegisterInfo::RegClassInfo MipsRegClassInfos[] = { |
| 106 | // Mode = 0 (DefaultMode) |
| 107 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CCR |
| 108 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // COP0 |
| 109 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // COP2 |
| 110 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // COP3 |
| 111 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 0 }, // DSPR |
| 112 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 6 }, // FGR32 |
| 113 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // FGR32CC |
| 114 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPR32 |
| 115 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // HWRegs |
| 116 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // MSACtrl |
| 117 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPR32NONZERO |
| 118 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPU16RegsPlusSP |
| 119 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPU16Regs |
| 120 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // FCC |
| 121 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16 |
| 122 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MoveP |
| 123 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16Zero |
| 124 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPU16Regs_and_GPRMM16Zero |
| 125 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPR32NONZERO_and_GPRMM16MoveP |
| 126 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MovePPairSecond |
| 127 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPU16Regs_and_GPRMM16MoveP |
| 128 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MoveP_and_GPRMM16Zero |
| 129 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // HI32DSP |
| 130 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // LO32DSP |
| 131 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPU16Regs_and_GPRMM16MovePPairSecond |
| 132 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MovePPairFirst |
| 133 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero |
| 134 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond |
| 135 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPURAReg |
| 136 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPUSPReg |
| 137 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 14 }, // DSPCC |
| 138 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GP32 |
| 139 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPR32ZERO |
| 140 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // HI32 |
| 141 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // LO32 |
| 142 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // SP32 |
| 143 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 8 }, // FGR64CC |
| 144 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 10 }, // FGR64 |
| 145 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64 |
| 146 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPR32NONZERO |
| 147 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 10 }, // AFGR64 |
| 148 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16RegsPlusSP |
| 149 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs |
| 150 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MoveP |
| 151 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16Zero |
| 152 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero |
| 153 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP |
| 154 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond |
| 155 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 26 }, // ACC64DSP |
| 156 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP |
| 157 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero |
| 158 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond |
| 159 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst |
| 160 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero |
| 161 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // OCTEON_MPL |
| 162 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // OCTEON_P |
| 163 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond |
| 164 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 26 }, // ACC64 |
| 165 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GP64 |
| 166 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPURAReg |
| 167 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPR32ZERO |
| 168 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // HI64 |
| 169 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // LO64 |
| 170 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // SP64 |
| 171 | { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 12 }, // MSA128B |
| 172 | { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 23 }, // MSA128D |
| 173 | { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 17 }, // MSA128H |
| 174 | { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 20 }, // MSA128W |
| 175 | { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 20 }, // MSA128WEvens |
| 176 | { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 26 }, // ACC128 |
| 177 | // Mode = 1 (MIPS64) |
| 178 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CCR |
| 179 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // COP0 |
| 180 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // COP2 |
| 181 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // COP3 |
| 182 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 0 }, // DSPR |
| 183 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 6 }, // FGR32 |
| 184 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // FGR32CC |
| 185 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPR32 |
| 186 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // HWRegs |
| 187 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // MSACtrl |
| 188 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPR32NONZERO |
| 189 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPU16RegsPlusSP |
| 190 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPU16Regs |
| 191 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // FCC |
| 192 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16 |
| 193 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MoveP |
| 194 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16Zero |
| 195 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPU16Regs_and_GPRMM16Zero |
| 196 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPR32NONZERO_and_GPRMM16MoveP |
| 197 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MovePPairSecond |
| 198 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPU16Regs_and_GPRMM16MoveP |
| 199 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MoveP_and_GPRMM16Zero |
| 200 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // HI32DSP |
| 201 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // LO32DSP |
| 202 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPU16Regs_and_GPRMM16MovePPairSecond |
| 203 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MovePPairFirst |
| 204 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero |
| 205 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond |
| 206 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPURAReg |
| 207 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPUSPReg |
| 208 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 14 }, // DSPCC |
| 209 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GP32 |
| 210 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPR32ZERO |
| 211 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // HI32 |
| 212 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // LO32 |
| 213 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // SP32 |
| 214 | { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 8 }, // FGR64CC |
| 215 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 10 }, // FGR64 |
| 216 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64 |
| 217 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPR32NONZERO |
| 218 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 10 }, // AFGR64 |
| 219 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16RegsPlusSP |
| 220 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs |
| 221 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MoveP |
| 222 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16Zero |
| 223 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero |
| 224 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP |
| 225 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond |
| 226 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 26 }, // ACC64DSP |
| 227 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP |
| 228 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero |
| 229 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond |
| 230 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst |
| 231 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero |
| 232 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // OCTEON_MPL |
| 233 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // OCTEON_P |
| 234 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond |
| 235 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 26 }, // ACC64 |
| 236 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GP64 |
| 237 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPURAReg |
| 238 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPR32ZERO |
| 239 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // HI64 |
| 240 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // LO64 |
| 241 | { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // SP64 |
| 242 | { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 12 }, // MSA128B |
| 243 | { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 23 }, // MSA128D |
| 244 | { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 17 }, // MSA128H |
| 245 | { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 20 }, // MSA128W |
| 246 | { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 20 }, // MSA128WEvens |
| 247 | { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 26 }, // ACC128 |
| 248 | }; |
| 249 | |
| 250 | static inline unsigned FGR32AltOrderSelect(const MachineFunction &MF, bool Rev) { |
| 251 | const auto & S = MF.getSubtarget<MipsSubtarget>(); |
| 252 | return S.isABI_O32() && !S.useOddSPReg(); |
| 253 | } |
| 254 | |
| 255 | static ArrayRef<MCPhysReg> FGR32GetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) { |
| 256 | static const MCPhysReg AltOrder1[] = { Mips::F0, Mips::F2, Mips::F4, Mips::F6, Mips::F8, Mips::F10, Mips::F12, Mips::F14, Mips::F16, Mips::F18, Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30 }; |
| 257 | const ArrayRef<MCPhysReg> Order[] = { |
| 258 | RC.getRegisters(), |
| 259 | ArrayRef(AltOrder1) |
| 260 | }; |
| 261 | const unsigned Select = FGR32AltOrderSelect(MF, Rev); |
| 262 | assert(Select < 2); |
| 263 | return Order[Select]; |
| 264 | } |
| 265 | |
| 266 | static inline unsigned FGR64AltOrderSelect(const MachineFunction &MF, bool Rev) { |
| 267 | const auto & S = MF.getSubtarget<MipsSubtarget>(); |
| 268 | return S.isABI_O32() && !S.useOddSPReg(); |
| 269 | } |
| 270 | |
| 271 | static ArrayRef<MCPhysReg> FGR64GetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) { |
| 272 | static const MCPhysReg AltOrder1[] = { Mips::D0_64, Mips::D2_64, Mips::D4_64, Mips::D6_64, Mips::D8_64, Mips::D10_64, Mips::D12_64, Mips::D14_64, Mips::D16_64, Mips::D18_64, Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64 }; |
| 273 | const ArrayRef<MCPhysReg> Order[] = { |
| 274 | RC.getRegisters(), |
| 275 | ArrayRef(AltOrder1) |
| 276 | }; |
| 277 | const unsigned Select = FGR64AltOrderSelect(MF, Rev); |
| 278 | assert(Select < 2); |
| 279 | return Order[Select]; |
| 280 | } |
| 281 | |
| 282 | static const uint8_t MipsCostPerUseTable[] = { |
| 283 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; |
| 284 | |
| 285 | |
| 286 | static const bool MipsInAllocatableClassTable[] = { |
| 287 | false, true, true, false, false, false, false, false, true, true, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, }; |
| 288 | |
| 289 | |
| 290 | static const TargetRegisterInfoDesc MipsRegInfoDesc = { // Extra Descriptors |
| 291 | .CostPerUse: MipsCostPerUseTable, .NumCosts: 1, .InAllocatableClass: MipsInAllocatableClassTable}; |
| 292 | |
| 293 | unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const { |
| 294 | static const uint8_t RowMap[11] = { |
| 295 | 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, |
| 296 | }; |
| 297 | static const uint8_t Rows[2][11] = { |
| 298 | { Mips::sub_hi_then_sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, 0, 0, }, |
| 299 | { Mips::sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi_then_sub_32, Mips::sub_32, 0, 0, }, |
| 300 | }; |
| 301 | |
| 302 | --IdxA; assert(IdxA < 11); (void) IdxA; |
| 303 | --IdxB; assert(IdxB < 11); |
| 304 | return Rows[RowMap[IdxA]][IdxB]; |
| 305 | } |
| 306 | |
| 307 | unsigned MipsGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const { |
| 308 | static const uint8_t Table[11][11] = { |
| 309 | { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, }, |
| 310 | { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, }, |
| 311 | { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, }, |
| 312 | { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, }, |
| 313 | { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, }, |
| 314 | { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, }, |
| 315 | { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, }, |
| 316 | { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, }, |
| 317 | { Mips::sub_32, 0, 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, 0, }, |
| 318 | { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, }, |
| 319 | { Mips::sub_32, 0, 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, 0, }, |
| 320 | }; |
| 321 | |
| 322 | --IdxA; assert(IdxA < 11); |
| 323 | --IdxB; assert(IdxB < 11); |
| 324 | return Table[IdxA][IdxB]; |
| 325 | } |
| 326 | |
| 327 | struct MaskRolOp { |
| 328 | LaneBitmask Mask; |
| 329 | uint8_t RotateLeft; |
| 330 | }; |
| 331 | static const MaskRolOp LaneMaskComposeSequences[] = { |
| 332 | { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0 |
| 333 | { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2 |
| 334 | { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4 |
| 335 | { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 6 |
| 336 | { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 4 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 8 |
| 337 | { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 5 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 10 |
| 338 | { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 6 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 12 |
| 339 | }; |
| 340 | static const uint8_t CompositeSequences[] = { |
| 341 | 0, // to sub_32 |
| 342 | 0, // to sub_64 |
| 343 | 2, // to sub_dsp16_19 |
| 344 | 4, // to sub_dsp20 |
| 345 | 6, // to sub_dsp21 |
| 346 | 8, // to sub_dsp22 |
| 347 | 10, // to sub_dsp23 |
| 348 | 12, // to sub_hi |
| 349 | 0, // to sub_lo |
| 350 | 12, // to sub_hi_then_sub_32 |
| 351 | 0 // to sub_32_sub_hi_then_sub_32 |
| 352 | }; |
| 353 | |
| 354 | LaneBitmask MipsGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { |
| 355 | --IdxA; assert(IdxA < 11 && "Subregister index out of bounds"); |
| 356 | LaneBitmask Result; |
| 357 | for (const MaskRolOp *Ops = |
| 358 | &LaneMaskComposeSequences[CompositeSequences[IdxA]]; |
| 359 | Ops->Mask.any(); ++Ops) { |
| 360 | LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger(); |
| 361 | if (unsigned S = Ops->RotateLeft) |
| 362 | Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S))); |
| 363 | else |
| 364 | Result |= LaneBitmask(M); |
| 365 | } |
| 366 | return Result; |
| 367 | } |
| 368 | |
| 369 | LaneBitmask MipsGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { |
| 370 | LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA); |
| 371 | --IdxA; assert(IdxA < 11 && "Subregister index out of bounds"); |
| 372 | LaneBitmask Result; |
| 373 | for (const MaskRolOp *Ops = |
| 374 | &LaneMaskComposeSequences[CompositeSequences[IdxA]]; |
| 375 | Ops->Mask.any(); ++Ops) { |
| 376 | LaneBitmask::Type M = LaneMask.getAsInteger(); |
| 377 | if (unsigned S = Ops->RotateLeft) |
| 378 | Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S))); |
| 379 | else |
| 380 | Result |= LaneBitmask(M); |
| 381 | } |
| 382 | return Result; |
| 383 | } |
| 384 | |
| 385 | const TargetRegisterClass *MipsGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { |
| 386 | static constexpr uint8_t Table[70][11] = { |
| 387 | { // CCR |
| 388 | 0, // sub_32 |
| 389 | 0, // sub_64 |
| 390 | 0, // sub_dsp16_19 |
| 391 | 0, // sub_dsp20 |
| 392 | 0, // sub_dsp21 |
| 393 | 0, // sub_dsp22 |
| 394 | 0, // sub_dsp23 |
| 395 | 0, // sub_hi |
| 396 | 0, // sub_lo |
| 397 | 0, // sub_hi_then_sub_32 |
| 398 | 0, // sub_32_sub_hi_then_sub_32 |
| 399 | }, |
| 400 | { // COP0 |
| 401 | 0, // sub_32 |
| 402 | 0, // sub_64 |
| 403 | 0, // sub_dsp16_19 |
| 404 | 0, // sub_dsp20 |
| 405 | 0, // sub_dsp21 |
| 406 | 0, // sub_dsp22 |
| 407 | 0, // sub_dsp23 |
| 408 | 0, // sub_hi |
| 409 | 0, // sub_lo |
| 410 | 0, // sub_hi_then_sub_32 |
| 411 | 0, // sub_32_sub_hi_then_sub_32 |
| 412 | }, |
| 413 | { // COP2 |
| 414 | 0, // sub_32 |
| 415 | 0, // sub_64 |
| 416 | 0, // sub_dsp16_19 |
| 417 | 0, // sub_dsp20 |
| 418 | 0, // sub_dsp21 |
| 419 | 0, // sub_dsp22 |
| 420 | 0, // sub_dsp23 |
| 421 | 0, // sub_hi |
| 422 | 0, // sub_lo |
| 423 | 0, // sub_hi_then_sub_32 |
| 424 | 0, // sub_32_sub_hi_then_sub_32 |
| 425 | }, |
| 426 | { // COP3 |
| 427 | 0, // sub_32 |
| 428 | 0, // sub_64 |
| 429 | 0, // sub_dsp16_19 |
| 430 | 0, // sub_dsp20 |
| 431 | 0, // sub_dsp21 |
| 432 | 0, // sub_dsp22 |
| 433 | 0, // sub_dsp23 |
| 434 | 0, // sub_hi |
| 435 | 0, // sub_lo |
| 436 | 0, // sub_hi_then_sub_32 |
| 437 | 0, // sub_32_sub_hi_then_sub_32 |
| 438 | }, |
| 439 | { // DSPR |
| 440 | 0, // sub_32 |
| 441 | 0, // sub_64 |
| 442 | 0, // sub_dsp16_19 |
| 443 | 0, // sub_dsp20 |
| 444 | 0, // sub_dsp21 |
| 445 | 0, // sub_dsp22 |
| 446 | 0, // sub_dsp23 |
| 447 | 0, // sub_hi |
| 448 | 0, // sub_lo |
| 449 | 0, // sub_hi_then_sub_32 |
| 450 | 0, // sub_32_sub_hi_then_sub_32 |
| 451 | }, |
| 452 | { // FGR32 |
| 453 | 0, // sub_32 |
| 454 | 0, // sub_64 |
| 455 | 0, // sub_dsp16_19 |
| 456 | 0, // sub_dsp20 |
| 457 | 0, // sub_dsp21 |
| 458 | 0, // sub_dsp22 |
| 459 | 0, // sub_dsp23 |
| 460 | 0, // sub_hi |
| 461 | 0, // sub_lo |
| 462 | 0, // sub_hi_then_sub_32 |
| 463 | 0, // sub_32_sub_hi_then_sub_32 |
| 464 | }, |
| 465 | { // FGR32CC |
| 466 | 0, // sub_32 |
| 467 | 0, // sub_64 |
| 468 | 0, // sub_dsp16_19 |
| 469 | 0, // sub_dsp20 |
| 470 | 0, // sub_dsp21 |
| 471 | 0, // sub_dsp22 |
| 472 | 0, // sub_dsp23 |
| 473 | 0, // sub_hi |
| 474 | 0, // sub_lo |
| 475 | 0, // sub_hi_then_sub_32 |
| 476 | 0, // sub_32_sub_hi_then_sub_32 |
| 477 | }, |
| 478 | { // GPR32 |
| 479 | 0, // sub_32 |
| 480 | 0, // sub_64 |
| 481 | 0, // sub_dsp16_19 |
| 482 | 0, // sub_dsp20 |
| 483 | 0, // sub_dsp21 |
| 484 | 0, // sub_dsp22 |
| 485 | 0, // sub_dsp23 |
| 486 | 0, // sub_hi |
| 487 | 0, // sub_lo |
| 488 | 0, // sub_hi_then_sub_32 |
| 489 | 0, // sub_32_sub_hi_then_sub_32 |
| 490 | }, |
| 491 | { // HWRegs |
| 492 | 0, // sub_32 |
| 493 | 0, // sub_64 |
| 494 | 0, // sub_dsp16_19 |
| 495 | 0, // sub_dsp20 |
| 496 | 0, // sub_dsp21 |
| 497 | 0, // sub_dsp22 |
| 498 | 0, // sub_dsp23 |
| 499 | 0, // sub_hi |
| 500 | 0, // sub_lo |
| 501 | 0, // sub_hi_then_sub_32 |
| 502 | 0, // sub_32_sub_hi_then_sub_32 |
| 503 | }, |
| 504 | { // MSACtrl |
| 505 | 0, // sub_32 |
| 506 | 0, // sub_64 |
| 507 | 0, // sub_dsp16_19 |
| 508 | 0, // sub_dsp20 |
| 509 | 0, // sub_dsp21 |
| 510 | 0, // sub_dsp22 |
| 511 | 0, // sub_dsp23 |
| 512 | 0, // sub_hi |
| 513 | 0, // sub_lo |
| 514 | 0, // sub_hi_then_sub_32 |
| 515 | 0, // sub_32_sub_hi_then_sub_32 |
| 516 | }, |
| 517 | { // GPR32NONZERO |
| 518 | 0, // sub_32 |
| 519 | 0, // sub_64 |
| 520 | 0, // sub_dsp16_19 |
| 521 | 0, // sub_dsp20 |
| 522 | 0, // sub_dsp21 |
| 523 | 0, // sub_dsp22 |
| 524 | 0, // sub_dsp23 |
| 525 | 0, // sub_hi |
| 526 | 0, // sub_lo |
| 527 | 0, // sub_hi_then_sub_32 |
| 528 | 0, // sub_32_sub_hi_then_sub_32 |
| 529 | }, |
| 530 | { // CPU16RegsPlusSP |
| 531 | 0, // sub_32 |
| 532 | 0, // sub_64 |
| 533 | 0, // sub_dsp16_19 |
| 534 | 0, // sub_dsp20 |
| 535 | 0, // sub_dsp21 |
| 536 | 0, // sub_dsp22 |
| 537 | 0, // sub_dsp23 |
| 538 | 0, // sub_hi |
| 539 | 0, // sub_lo |
| 540 | 0, // sub_hi_then_sub_32 |
| 541 | 0, // sub_32_sub_hi_then_sub_32 |
| 542 | }, |
| 543 | { // CPU16Regs |
| 544 | 0, // sub_32 |
| 545 | 0, // sub_64 |
| 546 | 0, // sub_dsp16_19 |
| 547 | 0, // sub_dsp20 |
| 548 | 0, // sub_dsp21 |
| 549 | 0, // sub_dsp22 |
| 550 | 0, // sub_dsp23 |
| 551 | 0, // sub_hi |
| 552 | 0, // sub_lo |
| 553 | 0, // sub_hi_then_sub_32 |
| 554 | 0, // sub_32_sub_hi_then_sub_32 |
| 555 | }, |
| 556 | { // FCC |
| 557 | 0, // sub_32 |
| 558 | 0, // sub_64 |
| 559 | 0, // sub_dsp16_19 |
| 560 | 0, // sub_dsp20 |
| 561 | 0, // sub_dsp21 |
| 562 | 0, // sub_dsp22 |
| 563 | 0, // sub_dsp23 |
| 564 | 0, // sub_hi |
| 565 | 0, // sub_lo |
| 566 | 0, // sub_hi_then_sub_32 |
| 567 | 0, // sub_32_sub_hi_then_sub_32 |
| 568 | }, |
| 569 | { // GPRMM16 |
| 570 | 0, // sub_32 |
| 571 | 0, // sub_64 |
| 572 | 0, // sub_dsp16_19 |
| 573 | 0, // sub_dsp20 |
| 574 | 0, // sub_dsp21 |
| 575 | 0, // sub_dsp22 |
| 576 | 0, // sub_dsp23 |
| 577 | 0, // sub_hi |
| 578 | 0, // sub_lo |
| 579 | 0, // sub_hi_then_sub_32 |
| 580 | 0, // sub_32_sub_hi_then_sub_32 |
| 581 | }, |
| 582 | { // GPRMM16MoveP |
| 583 | 0, // sub_32 |
| 584 | 0, // sub_64 |
| 585 | 0, // sub_dsp16_19 |
| 586 | 0, // sub_dsp20 |
| 587 | 0, // sub_dsp21 |
| 588 | 0, // sub_dsp22 |
| 589 | 0, // sub_dsp23 |
| 590 | 0, // sub_hi |
| 591 | 0, // sub_lo |
| 592 | 0, // sub_hi_then_sub_32 |
| 593 | 0, // sub_32_sub_hi_then_sub_32 |
| 594 | }, |
| 595 | { // GPRMM16Zero |
| 596 | 0, // sub_32 |
| 597 | 0, // sub_64 |
| 598 | 0, // sub_dsp16_19 |
| 599 | 0, // sub_dsp20 |
| 600 | 0, // sub_dsp21 |
| 601 | 0, // sub_dsp22 |
| 602 | 0, // sub_dsp23 |
| 603 | 0, // sub_hi |
| 604 | 0, // sub_lo |
| 605 | 0, // sub_hi_then_sub_32 |
| 606 | 0, // sub_32_sub_hi_then_sub_32 |
| 607 | }, |
| 608 | { // CPU16Regs_and_GPRMM16Zero |
| 609 | 0, // sub_32 |
| 610 | 0, // sub_64 |
| 611 | 0, // sub_dsp16_19 |
| 612 | 0, // sub_dsp20 |
| 613 | 0, // sub_dsp21 |
| 614 | 0, // sub_dsp22 |
| 615 | 0, // sub_dsp23 |
| 616 | 0, // sub_hi |
| 617 | 0, // sub_lo |
| 618 | 0, // sub_hi_then_sub_32 |
| 619 | 0, // sub_32_sub_hi_then_sub_32 |
| 620 | }, |
| 621 | { // GPR32NONZERO_and_GPRMM16MoveP |
| 622 | 0, // sub_32 |
| 623 | 0, // sub_64 |
| 624 | 0, // sub_dsp16_19 |
| 625 | 0, // sub_dsp20 |
| 626 | 0, // sub_dsp21 |
| 627 | 0, // sub_dsp22 |
| 628 | 0, // sub_dsp23 |
| 629 | 0, // sub_hi |
| 630 | 0, // sub_lo |
| 631 | 0, // sub_hi_then_sub_32 |
| 632 | 0, // sub_32_sub_hi_then_sub_32 |
| 633 | }, |
| 634 | { // GPRMM16MovePPairSecond |
| 635 | 0, // sub_32 |
| 636 | 0, // sub_64 |
| 637 | 0, // sub_dsp16_19 |
| 638 | 0, // sub_dsp20 |
| 639 | 0, // sub_dsp21 |
| 640 | 0, // sub_dsp22 |
| 641 | 0, // sub_dsp23 |
| 642 | 0, // sub_hi |
| 643 | 0, // sub_lo |
| 644 | 0, // sub_hi_then_sub_32 |
| 645 | 0, // sub_32_sub_hi_then_sub_32 |
| 646 | }, |
| 647 | { // CPU16Regs_and_GPRMM16MoveP |
| 648 | 0, // sub_32 |
| 649 | 0, // sub_64 |
| 650 | 0, // sub_dsp16_19 |
| 651 | 0, // sub_dsp20 |
| 652 | 0, // sub_dsp21 |
| 653 | 0, // sub_dsp22 |
| 654 | 0, // sub_dsp23 |
| 655 | 0, // sub_hi |
| 656 | 0, // sub_lo |
| 657 | 0, // sub_hi_then_sub_32 |
| 658 | 0, // sub_32_sub_hi_then_sub_32 |
| 659 | }, |
| 660 | { // GPRMM16MoveP_and_GPRMM16Zero |
| 661 | 0, // sub_32 |
| 662 | 0, // sub_64 |
| 663 | 0, // sub_dsp16_19 |
| 664 | 0, // sub_dsp20 |
| 665 | 0, // sub_dsp21 |
| 666 | 0, // sub_dsp22 |
| 667 | 0, // sub_dsp23 |
| 668 | 0, // sub_hi |
| 669 | 0, // sub_lo |
| 670 | 0, // sub_hi_then_sub_32 |
| 671 | 0, // sub_32_sub_hi_then_sub_32 |
| 672 | }, |
| 673 | { // HI32DSP |
| 674 | 0, // sub_32 |
| 675 | 0, // sub_64 |
| 676 | 0, // sub_dsp16_19 |
| 677 | 0, // sub_dsp20 |
| 678 | 0, // sub_dsp21 |
| 679 | 0, // sub_dsp22 |
| 680 | 0, // sub_dsp23 |
| 681 | 0, // sub_hi |
| 682 | 0, // sub_lo |
| 683 | 0, // sub_hi_then_sub_32 |
| 684 | 0, // sub_32_sub_hi_then_sub_32 |
| 685 | }, |
| 686 | { // LO32DSP |
| 687 | 0, // sub_32 |
| 688 | 0, // sub_64 |
| 689 | 0, // sub_dsp16_19 |
| 690 | 0, // sub_dsp20 |
| 691 | 0, // sub_dsp21 |
| 692 | 0, // sub_dsp22 |
| 693 | 0, // sub_dsp23 |
| 694 | 0, // sub_hi |
| 695 | 0, // sub_lo |
| 696 | 0, // sub_hi_then_sub_32 |
| 697 | 0, // sub_32_sub_hi_then_sub_32 |
| 698 | }, |
| 699 | { // CPU16Regs_and_GPRMM16MovePPairSecond |
| 700 | 0, // sub_32 |
| 701 | 0, // sub_64 |
| 702 | 0, // sub_dsp16_19 |
| 703 | 0, // sub_dsp20 |
| 704 | 0, // sub_dsp21 |
| 705 | 0, // sub_dsp22 |
| 706 | 0, // sub_dsp23 |
| 707 | 0, // sub_hi |
| 708 | 0, // sub_lo |
| 709 | 0, // sub_hi_then_sub_32 |
| 710 | 0, // sub_32_sub_hi_then_sub_32 |
| 711 | }, |
| 712 | { // GPRMM16MovePPairFirst |
| 713 | 0, // sub_32 |
| 714 | 0, // sub_64 |
| 715 | 0, // sub_dsp16_19 |
| 716 | 0, // sub_dsp20 |
| 717 | 0, // sub_dsp21 |
| 718 | 0, // sub_dsp22 |
| 719 | 0, // sub_dsp23 |
| 720 | 0, // sub_hi |
| 721 | 0, // sub_lo |
| 722 | 0, // sub_hi_then_sub_32 |
| 723 | 0, // sub_32_sub_hi_then_sub_32 |
| 724 | }, |
| 725 | { // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero |
| 726 | 0, // sub_32 |
| 727 | 0, // sub_64 |
| 728 | 0, // sub_dsp16_19 |
| 729 | 0, // sub_dsp20 |
| 730 | 0, // sub_dsp21 |
| 731 | 0, // sub_dsp22 |
| 732 | 0, // sub_dsp23 |
| 733 | 0, // sub_hi |
| 734 | 0, // sub_lo |
| 735 | 0, // sub_hi_then_sub_32 |
| 736 | 0, // sub_32_sub_hi_then_sub_32 |
| 737 | }, |
| 738 | { // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond |
| 739 | 0, // sub_32 |
| 740 | 0, // sub_64 |
| 741 | 0, // sub_dsp16_19 |
| 742 | 0, // sub_dsp20 |
| 743 | 0, // sub_dsp21 |
| 744 | 0, // sub_dsp22 |
| 745 | 0, // sub_dsp23 |
| 746 | 0, // sub_hi |
| 747 | 0, // sub_lo |
| 748 | 0, // sub_hi_then_sub_32 |
| 749 | 0, // sub_32_sub_hi_then_sub_32 |
| 750 | }, |
| 751 | { // CPURAReg |
| 752 | 0, // sub_32 |
| 753 | 0, // sub_64 |
| 754 | 0, // sub_dsp16_19 |
| 755 | 0, // sub_dsp20 |
| 756 | 0, // sub_dsp21 |
| 757 | 0, // sub_dsp22 |
| 758 | 0, // sub_dsp23 |
| 759 | 0, // sub_hi |
| 760 | 0, // sub_lo |
| 761 | 0, // sub_hi_then_sub_32 |
| 762 | 0, // sub_32_sub_hi_then_sub_32 |
| 763 | }, |
| 764 | { // CPUSPReg |
| 765 | 0, // sub_32 |
| 766 | 0, // sub_64 |
| 767 | 0, // sub_dsp16_19 |
| 768 | 0, // sub_dsp20 |
| 769 | 0, // sub_dsp21 |
| 770 | 0, // sub_dsp22 |
| 771 | 0, // sub_dsp23 |
| 772 | 0, // sub_hi |
| 773 | 0, // sub_lo |
| 774 | 0, // sub_hi_then_sub_32 |
| 775 | 0, // sub_32_sub_hi_then_sub_32 |
| 776 | }, |
| 777 | { // DSPCC |
| 778 | 0, // sub_32 |
| 779 | 0, // sub_64 |
| 780 | 0, // sub_dsp16_19 |
| 781 | 0, // sub_dsp20 |
| 782 | 0, // sub_dsp21 |
| 783 | 0, // sub_dsp22 |
| 784 | 0, // sub_dsp23 |
| 785 | 0, // sub_hi |
| 786 | 0, // sub_lo |
| 787 | 0, // sub_hi_then_sub_32 |
| 788 | 0, // sub_32_sub_hi_then_sub_32 |
| 789 | }, |
| 790 | { // GP32 |
| 791 | 0, // sub_32 |
| 792 | 0, // sub_64 |
| 793 | 0, // sub_dsp16_19 |
| 794 | 0, // sub_dsp20 |
| 795 | 0, // sub_dsp21 |
| 796 | 0, // sub_dsp22 |
| 797 | 0, // sub_dsp23 |
| 798 | 0, // sub_hi |
| 799 | 0, // sub_lo |
| 800 | 0, // sub_hi_then_sub_32 |
| 801 | 0, // sub_32_sub_hi_then_sub_32 |
| 802 | }, |
| 803 | { // GPR32ZERO |
| 804 | 0, // sub_32 |
| 805 | 0, // sub_64 |
| 806 | 0, // sub_dsp16_19 |
| 807 | 0, // sub_dsp20 |
| 808 | 0, // sub_dsp21 |
| 809 | 0, // sub_dsp22 |
| 810 | 0, // sub_dsp23 |
| 811 | 0, // sub_hi |
| 812 | 0, // sub_lo |
| 813 | 0, // sub_hi_then_sub_32 |
| 814 | 0, // sub_32_sub_hi_then_sub_32 |
| 815 | }, |
| 816 | { // HI32 |
| 817 | 0, // sub_32 |
| 818 | 0, // sub_64 |
| 819 | 0, // sub_dsp16_19 |
| 820 | 0, // sub_dsp20 |
| 821 | 0, // sub_dsp21 |
| 822 | 0, // sub_dsp22 |
| 823 | 0, // sub_dsp23 |
| 824 | 0, // sub_hi |
| 825 | 0, // sub_lo |
| 826 | 0, // sub_hi_then_sub_32 |
| 827 | 0, // sub_32_sub_hi_then_sub_32 |
| 828 | }, |
| 829 | { // LO32 |
| 830 | 0, // sub_32 |
| 831 | 0, // sub_64 |
| 832 | 0, // sub_dsp16_19 |
| 833 | 0, // sub_dsp20 |
| 834 | 0, // sub_dsp21 |
| 835 | 0, // sub_dsp22 |
| 836 | 0, // sub_dsp23 |
| 837 | 0, // sub_hi |
| 838 | 0, // sub_lo |
| 839 | 0, // sub_hi_then_sub_32 |
| 840 | 0, // sub_32_sub_hi_then_sub_32 |
| 841 | }, |
| 842 | { // SP32 |
| 843 | 0, // sub_32 |
| 844 | 0, // sub_64 |
| 845 | 0, // sub_dsp16_19 |
| 846 | 0, // sub_dsp20 |
| 847 | 0, // sub_dsp21 |
| 848 | 0, // sub_dsp22 |
| 849 | 0, // sub_dsp23 |
| 850 | 0, // sub_hi |
| 851 | 0, // sub_lo |
| 852 | 0, // sub_hi_then_sub_32 |
| 853 | 0, // sub_32_sub_hi_then_sub_32 |
| 854 | }, |
| 855 | { // FGR64CC |
| 856 | 0, // sub_32 |
| 857 | 0, // sub_64 |
| 858 | 0, // sub_dsp16_19 |
| 859 | 0, // sub_dsp20 |
| 860 | 0, // sub_dsp21 |
| 861 | 0, // sub_dsp22 |
| 862 | 0, // sub_dsp23 |
| 863 | 37, // sub_hi -> FGR64CC |
| 864 | 37, // sub_lo -> FGR64CC |
| 865 | 0, // sub_hi_then_sub_32 |
| 866 | 0, // sub_32_sub_hi_then_sub_32 |
| 867 | }, |
| 868 | { // FGR64 |
| 869 | 0, // sub_32 |
| 870 | 0, // sub_64 |
| 871 | 0, // sub_dsp16_19 |
| 872 | 0, // sub_dsp20 |
| 873 | 0, // sub_dsp21 |
| 874 | 0, // sub_dsp22 |
| 875 | 0, // sub_dsp23 |
| 876 | 38, // sub_hi -> FGR64 |
| 877 | 38, // sub_lo -> FGR64 |
| 878 | 0, // sub_hi_then_sub_32 |
| 879 | 0, // sub_32_sub_hi_then_sub_32 |
| 880 | }, |
| 881 | { // GPR64 |
| 882 | 39, // sub_32 -> GPR64 |
| 883 | 0, // sub_64 |
| 884 | 0, // sub_dsp16_19 |
| 885 | 0, // sub_dsp20 |
| 886 | 0, // sub_dsp21 |
| 887 | 0, // sub_dsp22 |
| 888 | 0, // sub_dsp23 |
| 889 | 0, // sub_hi |
| 890 | 0, // sub_lo |
| 891 | 0, // sub_hi_then_sub_32 |
| 892 | 0, // sub_32_sub_hi_then_sub_32 |
| 893 | }, |
| 894 | { // GPR64_with_sub_32_in_GPR32NONZERO |
| 895 | 40, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO |
| 896 | 0, // sub_64 |
| 897 | 0, // sub_dsp16_19 |
| 898 | 0, // sub_dsp20 |
| 899 | 0, // sub_dsp21 |
| 900 | 0, // sub_dsp22 |
| 901 | 0, // sub_dsp23 |
| 902 | 0, // sub_hi |
| 903 | 0, // sub_lo |
| 904 | 0, // sub_hi_then_sub_32 |
| 905 | 0, // sub_32_sub_hi_then_sub_32 |
| 906 | }, |
| 907 | { // AFGR64 |
| 908 | 0, // sub_32 |
| 909 | 0, // sub_64 |
| 910 | 0, // sub_dsp16_19 |
| 911 | 0, // sub_dsp20 |
| 912 | 0, // sub_dsp21 |
| 913 | 0, // sub_dsp22 |
| 914 | 0, // sub_dsp23 |
| 915 | 41, // sub_hi -> AFGR64 |
| 916 | 41, // sub_lo -> AFGR64 |
| 917 | 0, // sub_hi_then_sub_32 |
| 918 | 0, // sub_32_sub_hi_then_sub_32 |
| 919 | }, |
| 920 | { // GPR64_with_sub_32_in_CPU16RegsPlusSP |
| 921 | 42, // sub_32 -> GPR64_with_sub_32_in_CPU16RegsPlusSP |
| 922 | 0, // sub_64 |
| 923 | 0, // sub_dsp16_19 |
| 924 | 0, // sub_dsp20 |
| 925 | 0, // sub_dsp21 |
| 926 | 0, // sub_dsp22 |
| 927 | 0, // sub_dsp23 |
| 928 | 0, // sub_hi |
| 929 | 0, // sub_lo |
| 930 | 0, // sub_hi_then_sub_32 |
| 931 | 0, // sub_32_sub_hi_then_sub_32 |
| 932 | }, |
| 933 | { // GPR64_with_sub_32_in_CPU16Regs |
| 934 | 43, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs |
| 935 | 0, // sub_64 |
| 936 | 0, // sub_dsp16_19 |
| 937 | 0, // sub_dsp20 |
| 938 | 0, // sub_dsp21 |
| 939 | 0, // sub_dsp22 |
| 940 | 0, // sub_dsp23 |
| 941 | 0, // sub_hi |
| 942 | 0, // sub_lo |
| 943 | 0, // sub_hi_then_sub_32 |
| 944 | 0, // sub_32_sub_hi_then_sub_32 |
| 945 | }, |
| 946 | { // GPR64_with_sub_32_in_GPRMM16MoveP |
| 947 | 44, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP |
| 948 | 0, // sub_64 |
| 949 | 0, // sub_dsp16_19 |
| 950 | 0, // sub_dsp20 |
| 951 | 0, // sub_dsp21 |
| 952 | 0, // sub_dsp22 |
| 953 | 0, // sub_dsp23 |
| 954 | 0, // sub_hi |
| 955 | 0, // sub_lo |
| 956 | 0, // sub_hi_then_sub_32 |
| 957 | 0, // sub_32_sub_hi_then_sub_32 |
| 958 | }, |
| 959 | { // GPR64_with_sub_32_in_GPRMM16Zero |
| 960 | 45, // sub_32 -> GPR64_with_sub_32_in_GPRMM16Zero |
| 961 | 0, // sub_64 |
| 962 | 0, // sub_dsp16_19 |
| 963 | 0, // sub_dsp20 |
| 964 | 0, // sub_dsp21 |
| 965 | 0, // sub_dsp22 |
| 966 | 0, // sub_dsp23 |
| 967 | 0, // sub_hi |
| 968 | 0, // sub_lo |
| 969 | 0, // sub_hi_then_sub_32 |
| 970 | 0, // sub_32_sub_hi_then_sub_32 |
| 971 | }, |
| 972 | { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero |
| 973 | 46, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero |
| 974 | 0, // sub_64 |
| 975 | 0, // sub_dsp16_19 |
| 976 | 0, // sub_dsp20 |
| 977 | 0, // sub_dsp21 |
| 978 | 0, // sub_dsp22 |
| 979 | 0, // sub_dsp23 |
| 980 | 0, // sub_hi |
| 981 | 0, // sub_lo |
| 982 | 0, // sub_hi_then_sub_32 |
| 983 | 0, // sub_32_sub_hi_then_sub_32 |
| 984 | }, |
| 985 | { // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP |
| 986 | 47, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP |
| 987 | 0, // sub_64 |
| 988 | 0, // sub_dsp16_19 |
| 989 | 0, // sub_dsp20 |
| 990 | 0, // sub_dsp21 |
| 991 | 0, // sub_dsp22 |
| 992 | 0, // sub_dsp23 |
| 993 | 0, // sub_hi |
| 994 | 0, // sub_lo |
| 995 | 0, // sub_hi_then_sub_32 |
| 996 | 0, // sub_32_sub_hi_then_sub_32 |
| 997 | }, |
| 998 | { // GPR64_with_sub_32_in_GPRMM16MovePPairSecond |
| 999 | 48, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairSecond |
| 1000 | 0, // sub_64 |
| 1001 | 0, // sub_dsp16_19 |
| 1002 | 0, // sub_dsp20 |
| 1003 | 0, // sub_dsp21 |
| 1004 | 0, // sub_dsp22 |
| 1005 | 0, // sub_dsp23 |
| 1006 | 0, // sub_hi |
| 1007 | 0, // sub_lo |
| 1008 | 0, // sub_hi_then_sub_32 |
| 1009 | 0, // sub_32_sub_hi_then_sub_32 |
| 1010 | }, |
| 1011 | { // ACC64DSP |
| 1012 | 0, // sub_32 |
| 1013 | 0, // sub_64 |
| 1014 | 0, // sub_dsp16_19 |
| 1015 | 0, // sub_dsp20 |
| 1016 | 0, // sub_dsp21 |
| 1017 | 0, // sub_dsp22 |
| 1018 | 0, // sub_dsp23 |
| 1019 | 49, // sub_hi -> ACC64DSP |
| 1020 | 49, // sub_lo -> ACC64DSP |
| 1021 | 0, // sub_hi_then_sub_32 |
| 1022 | 0, // sub_32_sub_hi_then_sub_32 |
| 1023 | }, |
| 1024 | { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP |
| 1025 | 50, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP |
| 1026 | 0, // sub_64 |
| 1027 | 0, // sub_dsp16_19 |
| 1028 | 0, // sub_dsp20 |
| 1029 | 0, // sub_dsp21 |
| 1030 | 0, // sub_dsp22 |
| 1031 | 0, // sub_dsp23 |
| 1032 | 0, // sub_hi |
| 1033 | 0, // sub_lo |
| 1034 | 0, // sub_hi_then_sub_32 |
| 1035 | 0, // sub_32_sub_hi_then_sub_32 |
| 1036 | }, |
| 1037 | { // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero |
| 1038 | 51, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero |
| 1039 | 0, // sub_64 |
| 1040 | 0, // sub_dsp16_19 |
| 1041 | 0, // sub_dsp20 |
| 1042 | 0, // sub_dsp21 |
| 1043 | 0, // sub_dsp22 |
| 1044 | 0, // sub_dsp23 |
| 1045 | 0, // sub_hi |
| 1046 | 0, // sub_lo |
| 1047 | 0, // sub_hi_then_sub_32 |
| 1048 | 0, // sub_32_sub_hi_then_sub_32 |
| 1049 | }, |
| 1050 | { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond |
| 1051 | 52, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond |
| 1052 | 0, // sub_64 |
| 1053 | 0, // sub_dsp16_19 |
| 1054 | 0, // sub_dsp20 |
| 1055 | 0, // sub_dsp21 |
| 1056 | 0, // sub_dsp22 |
| 1057 | 0, // sub_dsp23 |
| 1058 | 0, // sub_hi |
| 1059 | 0, // sub_lo |
| 1060 | 0, // sub_hi_then_sub_32 |
| 1061 | 0, // sub_32_sub_hi_then_sub_32 |
| 1062 | }, |
| 1063 | { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst |
| 1064 | 53, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst |
| 1065 | 0, // sub_64 |
| 1066 | 0, // sub_dsp16_19 |
| 1067 | 0, // sub_dsp20 |
| 1068 | 0, // sub_dsp21 |
| 1069 | 0, // sub_dsp22 |
| 1070 | 0, // sub_dsp23 |
| 1071 | 0, // sub_hi |
| 1072 | 0, // sub_lo |
| 1073 | 0, // sub_hi_then_sub_32 |
| 1074 | 0, // sub_32_sub_hi_then_sub_32 |
| 1075 | }, |
| 1076 | { // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero |
| 1077 | 54, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero |
| 1078 | 0, // sub_64 |
| 1079 | 0, // sub_dsp16_19 |
| 1080 | 0, // sub_dsp20 |
| 1081 | 0, // sub_dsp21 |
| 1082 | 0, // sub_dsp22 |
| 1083 | 0, // sub_dsp23 |
| 1084 | 0, // sub_hi |
| 1085 | 0, // sub_lo |
| 1086 | 0, // sub_hi_then_sub_32 |
| 1087 | 0, // sub_32_sub_hi_then_sub_32 |
| 1088 | }, |
| 1089 | { // OCTEON_MPL |
| 1090 | 0, // sub_32 |
| 1091 | 0, // sub_64 |
| 1092 | 0, // sub_dsp16_19 |
| 1093 | 0, // sub_dsp20 |
| 1094 | 0, // sub_dsp21 |
| 1095 | 0, // sub_dsp22 |
| 1096 | 0, // sub_dsp23 |
| 1097 | 0, // sub_hi |
| 1098 | 0, // sub_lo |
| 1099 | 0, // sub_hi_then_sub_32 |
| 1100 | 0, // sub_32_sub_hi_then_sub_32 |
| 1101 | }, |
| 1102 | { // OCTEON_P |
| 1103 | 0, // sub_32 |
| 1104 | 0, // sub_64 |
| 1105 | 0, // sub_dsp16_19 |
| 1106 | 0, // sub_dsp20 |
| 1107 | 0, // sub_dsp21 |
| 1108 | 0, // sub_dsp22 |
| 1109 | 0, // sub_dsp23 |
| 1110 | 0, // sub_hi |
| 1111 | 0, // sub_lo |
| 1112 | 0, // sub_hi_then_sub_32 |
| 1113 | 0, // sub_32_sub_hi_then_sub_32 |
| 1114 | }, |
| 1115 | { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond |
| 1116 | 57, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond |
| 1117 | 0, // sub_64 |
| 1118 | 0, // sub_dsp16_19 |
| 1119 | 0, // sub_dsp20 |
| 1120 | 0, // sub_dsp21 |
| 1121 | 0, // sub_dsp22 |
| 1122 | 0, // sub_dsp23 |
| 1123 | 0, // sub_hi |
| 1124 | 0, // sub_lo |
| 1125 | 0, // sub_hi_then_sub_32 |
| 1126 | 0, // sub_32_sub_hi_then_sub_32 |
| 1127 | }, |
| 1128 | { // ACC64 |
| 1129 | 0, // sub_32 |
| 1130 | 0, // sub_64 |
| 1131 | 0, // sub_dsp16_19 |
| 1132 | 0, // sub_dsp20 |
| 1133 | 0, // sub_dsp21 |
| 1134 | 0, // sub_dsp22 |
| 1135 | 0, // sub_dsp23 |
| 1136 | 58, // sub_hi -> ACC64 |
| 1137 | 58, // sub_lo -> ACC64 |
| 1138 | 0, // sub_hi_then_sub_32 |
| 1139 | 0, // sub_32_sub_hi_then_sub_32 |
| 1140 | }, |
| 1141 | { // GP64 |
| 1142 | 59, // sub_32 -> GP64 |
| 1143 | 0, // sub_64 |
| 1144 | 0, // sub_dsp16_19 |
| 1145 | 0, // sub_dsp20 |
| 1146 | 0, // sub_dsp21 |
| 1147 | 0, // sub_dsp22 |
| 1148 | 0, // sub_dsp23 |
| 1149 | 0, // sub_hi |
| 1150 | 0, // sub_lo |
| 1151 | 0, // sub_hi_then_sub_32 |
| 1152 | 0, // sub_32_sub_hi_then_sub_32 |
| 1153 | }, |
| 1154 | { // GPR64_with_sub_32_in_CPURAReg |
| 1155 | 60, // sub_32 -> GPR64_with_sub_32_in_CPURAReg |
| 1156 | 0, // sub_64 |
| 1157 | 0, // sub_dsp16_19 |
| 1158 | 0, // sub_dsp20 |
| 1159 | 0, // sub_dsp21 |
| 1160 | 0, // sub_dsp22 |
| 1161 | 0, // sub_dsp23 |
| 1162 | 0, // sub_hi |
| 1163 | 0, // sub_lo |
| 1164 | 0, // sub_hi_then_sub_32 |
| 1165 | 0, // sub_32_sub_hi_then_sub_32 |
| 1166 | }, |
| 1167 | { // GPR64_with_sub_32_in_GPR32ZERO |
| 1168 | 61, // sub_32 -> GPR64_with_sub_32_in_GPR32ZERO |
| 1169 | 0, // sub_64 |
| 1170 | 0, // sub_dsp16_19 |
| 1171 | 0, // sub_dsp20 |
| 1172 | 0, // sub_dsp21 |
| 1173 | 0, // sub_dsp22 |
| 1174 | 0, // sub_dsp23 |
| 1175 | 0, // sub_hi |
| 1176 | 0, // sub_lo |
| 1177 | 0, // sub_hi_then_sub_32 |
| 1178 | 0, // sub_32_sub_hi_then_sub_32 |
| 1179 | }, |
| 1180 | { // HI64 |
| 1181 | 62, // sub_32 -> HI64 |
| 1182 | 0, // sub_64 |
| 1183 | 0, // sub_dsp16_19 |
| 1184 | 0, // sub_dsp20 |
| 1185 | 0, // sub_dsp21 |
| 1186 | 0, // sub_dsp22 |
| 1187 | 0, // sub_dsp23 |
| 1188 | 0, // sub_hi |
| 1189 | 0, // sub_lo |
| 1190 | 0, // sub_hi_then_sub_32 |
| 1191 | 0, // sub_32_sub_hi_then_sub_32 |
| 1192 | }, |
| 1193 | { // LO64 |
| 1194 | 63, // sub_32 -> LO64 |
| 1195 | 0, // sub_64 |
| 1196 | 0, // sub_dsp16_19 |
| 1197 | 0, // sub_dsp20 |
| 1198 | 0, // sub_dsp21 |
| 1199 | 0, // sub_dsp22 |
| 1200 | 0, // sub_dsp23 |
| 1201 | 0, // sub_hi |
| 1202 | 0, // sub_lo |
| 1203 | 0, // sub_hi_then_sub_32 |
| 1204 | 0, // sub_32_sub_hi_then_sub_32 |
| 1205 | }, |
| 1206 | { // SP64 |
| 1207 | 64, // sub_32 -> SP64 |
| 1208 | 0, // sub_64 |
| 1209 | 0, // sub_dsp16_19 |
| 1210 | 0, // sub_dsp20 |
| 1211 | 0, // sub_dsp21 |
| 1212 | 0, // sub_dsp22 |
| 1213 | 0, // sub_dsp23 |
| 1214 | 0, // sub_hi |
| 1215 | 0, // sub_lo |
| 1216 | 0, // sub_hi_then_sub_32 |
| 1217 | 0, // sub_32_sub_hi_then_sub_32 |
| 1218 | }, |
| 1219 | { // MSA128B |
| 1220 | 0, // sub_32 |
| 1221 | 65, // sub_64 -> MSA128B |
| 1222 | 0, // sub_dsp16_19 |
| 1223 | 0, // sub_dsp20 |
| 1224 | 0, // sub_dsp21 |
| 1225 | 0, // sub_dsp22 |
| 1226 | 0, // sub_dsp23 |
| 1227 | 65, // sub_hi -> MSA128B |
| 1228 | 65, // sub_lo -> MSA128B |
| 1229 | 0, // sub_hi_then_sub_32 |
| 1230 | 0, // sub_32_sub_hi_then_sub_32 |
| 1231 | }, |
| 1232 | { // MSA128D |
| 1233 | 0, // sub_32 |
| 1234 | 66, // sub_64 -> MSA128D |
| 1235 | 0, // sub_dsp16_19 |
| 1236 | 0, // sub_dsp20 |
| 1237 | 0, // sub_dsp21 |
| 1238 | 0, // sub_dsp22 |
| 1239 | 0, // sub_dsp23 |
| 1240 | 66, // sub_hi -> MSA128D |
| 1241 | 66, // sub_lo -> MSA128D |
| 1242 | 0, // sub_hi_then_sub_32 |
| 1243 | 0, // sub_32_sub_hi_then_sub_32 |
| 1244 | }, |
| 1245 | { // MSA128H |
| 1246 | 0, // sub_32 |
| 1247 | 67, // sub_64 -> MSA128H |
| 1248 | 0, // sub_dsp16_19 |
| 1249 | 0, // sub_dsp20 |
| 1250 | 0, // sub_dsp21 |
| 1251 | 0, // sub_dsp22 |
| 1252 | 0, // sub_dsp23 |
| 1253 | 67, // sub_hi -> MSA128H |
| 1254 | 67, // sub_lo -> MSA128H |
| 1255 | 0, // sub_hi_then_sub_32 |
| 1256 | 0, // sub_32_sub_hi_then_sub_32 |
| 1257 | }, |
| 1258 | { // MSA128W |
| 1259 | 0, // sub_32 |
| 1260 | 68, // sub_64 -> MSA128W |
| 1261 | 0, // sub_dsp16_19 |
| 1262 | 0, // sub_dsp20 |
| 1263 | 0, // sub_dsp21 |
| 1264 | 0, // sub_dsp22 |
| 1265 | 0, // sub_dsp23 |
| 1266 | 68, // sub_hi -> MSA128W |
| 1267 | 68, // sub_lo -> MSA128W |
| 1268 | 0, // sub_hi_then_sub_32 |
| 1269 | 0, // sub_32_sub_hi_then_sub_32 |
| 1270 | }, |
| 1271 | { // MSA128WEvens |
| 1272 | 0, // sub_32 |
| 1273 | 69, // sub_64 -> MSA128WEvens |
| 1274 | 0, // sub_dsp16_19 |
| 1275 | 0, // sub_dsp20 |
| 1276 | 0, // sub_dsp21 |
| 1277 | 0, // sub_dsp22 |
| 1278 | 0, // sub_dsp23 |
| 1279 | 69, // sub_hi -> MSA128WEvens |
| 1280 | 69, // sub_lo -> MSA128WEvens |
| 1281 | 0, // sub_hi_then_sub_32 |
| 1282 | 0, // sub_32_sub_hi_then_sub_32 |
| 1283 | }, |
| 1284 | { // ACC128 |
| 1285 | 70, // sub_32 -> ACC128 |
| 1286 | 0, // sub_64 |
| 1287 | 0, // sub_dsp16_19 |
| 1288 | 0, // sub_dsp20 |
| 1289 | 0, // sub_dsp21 |
| 1290 | 0, // sub_dsp22 |
| 1291 | 0, // sub_dsp23 |
| 1292 | 70, // sub_hi -> ACC128 |
| 1293 | 70, // sub_lo -> ACC128 |
| 1294 | 70, // sub_hi_then_sub_32 -> ACC128 |
| 1295 | 70, // sub_32_sub_hi_then_sub_32 -> ACC128 |
| 1296 | }, |
| 1297 | |
| 1298 | }; |
| 1299 | assert(RC && "Missing regclass"); |
| 1300 | if (!Idx) return RC; |
| 1301 | --Idx; |
| 1302 | assert(Idx < 11 && "Bad subreg"); |
| 1303 | unsigned TV = Table[RC->getID()][Idx]; |
| 1304 | return TV ? getRegClass(i: TV - 1) : nullptr; |
| 1305 | }const TargetRegisterClass *MipsGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const { |
| 1306 | static constexpr uint8_t Table[70][11] = { |
| 1307 | { // CCR |
| 1308 | 0, // CCR:sub_32 |
| 1309 | 0, // CCR:sub_64 |
| 1310 | 0, // CCR:sub_dsp16_19 |
| 1311 | 0, // CCR:sub_dsp20 |
| 1312 | 0, // CCR:sub_dsp21 |
| 1313 | 0, // CCR:sub_dsp22 |
| 1314 | 0, // CCR:sub_dsp23 |
| 1315 | 0, // CCR:sub_hi |
| 1316 | 0, // CCR:sub_lo |
| 1317 | 0, // CCR:sub_hi_then_sub_32 |
| 1318 | 0, // CCR:sub_32_sub_hi_then_sub_32 |
| 1319 | }, |
| 1320 | { // COP0 |
| 1321 | 0, // COP0:sub_32 |
| 1322 | 0, // COP0:sub_64 |
| 1323 | 0, // COP0:sub_dsp16_19 |
| 1324 | 0, // COP0:sub_dsp20 |
| 1325 | 0, // COP0:sub_dsp21 |
| 1326 | 0, // COP0:sub_dsp22 |
| 1327 | 0, // COP0:sub_dsp23 |
| 1328 | 0, // COP0:sub_hi |
| 1329 | 0, // COP0:sub_lo |
| 1330 | 0, // COP0:sub_hi_then_sub_32 |
| 1331 | 0, // COP0:sub_32_sub_hi_then_sub_32 |
| 1332 | }, |
| 1333 | { // COP2 |
| 1334 | 0, // COP2:sub_32 |
| 1335 | 0, // COP2:sub_64 |
| 1336 | 0, // COP2:sub_dsp16_19 |
| 1337 | 0, // COP2:sub_dsp20 |
| 1338 | 0, // COP2:sub_dsp21 |
| 1339 | 0, // COP2:sub_dsp22 |
| 1340 | 0, // COP2:sub_dsp23 |
| 1341 | 0, // COP2:sub_hi |
| 1342 | 0, // COP2:sub_lo |
| 1343 | 0, // COP2:sub_hi_then_sub_32 |
| 1344 | 0, // COP2:sub_32_sub_hi_then_sub_32 |
| 1345 | }, |
| 1346 | { // COP3 |
| 1347 | 0, // COP3:sub_32 |
| 1348 | 0, // COP3:sub_64 |
| 1349 | 0, // COP3:sub_dsp16_19 |
| 1350 | 0, // COP3:sub_dsp20 |
| 1351 | 0, // COP3:sub_dsp21 |
| 1352 | 0, // COP3:sub_dsp22 |
| 1353 | 0, // COP3:sub_dsp23 |
| 1354 | 0, // COP3:sub_hi |
| 1355 | 0, // COP3:sub_lo |
| 1356 | 0, // COP3:sub_hi_then_sub_32 |
| 1357 | 0, // COP3:sub_32_sub_hi_then_sub_32 |
| 1358 | }, |
| 1359 | { // DSPR |
| 1360 | 0, // DSPR:sub_32 |
| 1361 | 0, // DSPR:sub_64 |
| 1362 | 0, // DSPR:sub_dsp16_19 |
| 1363 | 0, // DSPR:sub_dsp20 |
| 1364 | 0, // DSPR:sub_dsp21 |
| 1365 | 0, // DSPR:sub_dsp22 |
| 1366 | 0, // DSPR:sub_dsp23 |
| 1367 | 0, // DSPR:sub_hi |
| 1368 | 0, // DSPR:sub_lo |
| 1369 | 0, // DSPR:sub_hi_then_sub_32 |
| 1370 | 0, // DSPR:sub_32_sub_hi_then_sub_32 |
| 1371 | }, |
| 1372 | { // FGR32 |
| 1373 | 0, // FGR32:sub_32 |
| 1374 | 0, // FGR32:sub_64 |
| 1375 | 0, // FGR32:sub_dsp16_19 |
| 1376 | 0, // FGR32:sub_dsp20 |
| 1377 | 0, // FGR32:sub_dsp21 |
| 1378 | 0, // FGR32:sub_dsp22 |
| 1379 | 0, // FGR32:sub_dsp23 |
| 1380 | 0, // FGR32:sub_hi |
| 1381 | 0, // FGR32:sub_lo |
| 1382 | 0, // FGR32:sub_hi_then_sub_32 |
| 1383 | 0, // FGR32:sub_32_sub_hi_then_sub_32 |
| 1384 | }, |
| 1385 | { // FGR32CC |
| 1386 | 0, // FGR32CC:sub_32 |
| 1387 | 0, // FGR32CC:sub_64 |
| 1388 | 0, // FGR32CC:sub_dsp16_19 |
| 1389 | 0, // FGR32CC:sub_dsp20 |
| 1390 | 0, // FGR32CC:sub_dsp21 |
| 1391 | 0, // FGR32CC:sub_dsp22 |
| 1392 | 0, // FGR32CC:sub_dsp23 |
| 1393 | 0, // FGR32CC:sub_hi |
| 1394 | 0, // FGR32CC:sub_lo |
| 1395 | 0, // FGR32CC:sub_hi_then_sub_32 |
| 1396 | 0, // FGR32CC:sub_32_sub_hi_then_sub_32 |
| 1397 | }, |
| 1398 | { // GPR32 |
| 1399 | 0, // GPR32:sub_32 |
| 1400 | 0, // GPR32:sub_64 |
| 1401 | 0, // GPR32:sub_dsp16_19 |
| 1402 | 0, // GPR32:sub_dsp20 |
| 1403 | 0, // GPR32:sub_dsp21 |
| 1404 | 0, // GPR32:sub_dsp22 |
| 1405 | 0, // GPR32:sub_dsp23 |
| 1406 | 0, // GPR32:sub_hi |
| 1407 | 0, // GPR32:sub_lo |
| 1408 | 0, // GPR32:sub_hi_then_sub_32 |
| 1409 | 0, // GPR32:sub_32_sub_hi_then_sub_32 |
| 1410 | }, |
| 1411 | { // HWRegs |
| 1412 | 0, // HWRegs:sub_32 |
| 1413 | 0, // HWRegs:sub_64 |
| 1414 | 0, // HWRegs:sub_dsp16_19 |
| 1415 | 0, // HWRegs:sub_dsp20 |
| 1416 | 0, // HWRegs:sub_dsp21 |
| 1417 | 0, // HWRegs:sub_dsp22 |
| 1418 | 0, // HWRegs:sub_dsp23 |
| 1419 | 0, // HWRegs:sub_hi |
| 1420 | 0, // HWRegs:sub_lo |
| 1421 | 0, // HWRegs:sub_hi_then_sub_32 |
| 1422 | 0, // HWRegs:sub_32_sub_hi_then_sub_32 |
| 1423 | }, |
| 1424 | { // MSACtrl |
| 1425 | 0, // MSACtrl:sub_32 |
| 1426 | 0, // MSACtrl:sub_64 |
| 1427 | 0, // MSACtrl:sub_dsp16_19 |
| 1428 | 0, // MSACtrl:sub_dsp20 |
| 1429 | 0, // MSACtrl:sub_dsp21 |
| 1430 | 0, // MSACtrl:sub_dsp22 |
| 1431 | 0, // MSACtrl:sub_dsp23 |
| 1432 | 0, // MSACtrl:sub_hi |
| 1433 | 0, // MSACtrl:sub_lo |
| 1434 | 0, // MSACtrl:sub_hi_then_sub_32 |
| 1435 | 0, // MSACtrl:sub_32_sub_hi_then_sub_32 |
| 1436 | }, |
| 1437 | { // GPR32NONZERO |
| 1438 | 0, // GPR32NONZERO:sub_32 |
| 1439 | 0, // GPR32NONZERO:sub_64 |
| 1440 | 0, // GPR32NONZERO:sub_dsp16_19 |
| 1441 | 0, // GPR32NONZERO:sub_dsp20 |
| 1442 | 0, // GPR32NONZERO:sub_dsp21 |
| 1443 | 0, // GPR32NONZERO:sub_dsp22 |
| 1444 | 0, // GPR32NONZERO:sub_dsp23 |
| 1445 | 0, // GPR32NONZERO:sub_hi |
| 1446 | 0, // GPR32NONZERO:sub_lo |
| 1447 | 0, // GPR32NONZERO:sub_hi_then_sub_32 |
| 1448 | 0, // GPR32NONZERO:sub_32_sub_hi_then_sub_32 |
| 1449 | }, |
| 1450 | { // CPU16RegsPlusSP |
| 1451 | 0, // CPU16RegsPlusSP:sub_32 |
| 1452 | 0, // CPU16RegsPlusSP:sub_64 |
| 1453 | 0, // CPU16RegsPlusSP:sub_dsp16_19 |
| 1454 | 0, // CPU16RegsPlusSP:sub_dsp20 |
| 1455 | 0, // CPU16RegsPlusSP:sub_dsp21 |
| 1456 | 0, // CPU16RegsPlusSP:sub_dsp22 |
| 1457 | 0, // CPU16RegsPlusSP:sub_dsp23 |
| 1458 | 0, // CPU16RegsPlusSP:sub_hi |
| 1459 | 0, // CPU16RegsPlusSP:sub_lo |
| 1460 | 0, // CPU16RegsPlusSP:sub_hi_then_sub_32 |
| 1461 | 0, // CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32 |
| 1462 | }, |
| 1463 | { // CPU16Regs |
| 1464 | 0, // CPU16Regs:sub_32 |
| 1465 | 0, // CPU16Regs:sub_64 |
| 1466 | 0, // CPU16Regs:sub_dsp16_19 |
| 1467 | 0, // CPU16Regs:sub_dsp20 |
| 1468 | 0, // CPU16Regs:sub_dsp21 |
| 1469 | 0, // CPU16Regs:sub_dsp22 |
| 1470 | 0, // CPU16Regs:sub_dsp23 |
| 1471 | 0, // CPU16Regs:sub_hi |
| 1472 | 0, // CPU16Regs:sub_lo |
| 1473 | 0, // CPU16Regs:sub_hi_then_sub_32 |
| 1474 | 0, // CPU16Regs:sub_32_sub_hi_then_sub_32 |
| 1475 | }, |
| 1476 | { // FCC |
| 1477 | 0, // FCC:sub_32 |
| 1478 | 0, // FCC:sub_64 |
| 1479 | 0, // FCC:sub_dsp16_19 |
| 1480 | 0, // FCC:sub_dsp20 |
| 1481 | 0, // FCC:sub_dsp21 |
| 1482 | 0, // FCC:sub_dsp22 |
| 1483 | 0, // FCC:sub_dsp23 |
| 1484 | 0, // FCC:sub_hi |
| 1485 | 0, // FCC:sub_lo |
| 1486 | 0, // FCC:sub_hi_then_sub_32 |
| 1487 | 0, // FCC:sub_32_sub_hi_then_sub_32 |
| 1488 | }, |
| 1489 | { // GPRMM16 |
| 1490 | 0, // GPRMM16:sub_32 |
| 1491 | 0, // GPRMM16:sub_64 |
| 1492 | 0, // GPRMM16:sub_dsp16_19 |
| 1493 | 0, // GPRMM16:sub_dsp20 |
| 1494 | 0, // GPRMM16:sub_dsp21 |
| 1495 | 0, // GPRMM16:sub_dsp22 |
| 1496 | 0, // GPRMM16:sub_dsp23 |
| 1497 | 0, // GPRMM16:sub_hi |
| 1498 | 0, // GPRMM16:sub_lo |
| 1499 | 0, // GPRMM16:sub_hi_then_sub_32 |
| 1500 | 0, // GPRMM16:sub_32_sub_hi_then_sub_32 |
| 1501 | }, |
| 1502 | { // GPRMM16MoveP |
| 1503 | 0, // GPRMM16MoveP:sub_32 |
| 1504 | 0, // GPRMM16MoveP:sub_64 |
| 1505 | 0, // GPRMM16MoveP:sub_dsp16_19 |
| 1506 | 0, // GPRMM16MoveP:sub_dsp20 |
| 1507 | 0, // GPRMM16MoveP:sub_dsp21 |
| 1508 | 0, // GPRMM16MoveP:sub_dsp22 |
| 1509 | 0, // GPRMM16MoveP:sub_dsp23 |
| 1510 | 0, // GPRMM16MoveP:sub_hi |
| 1511 | 0, // GPRMM16MoveP:sub_lo |
| 1512 | 0, // GPRMM16MoveP:sub_hi_then_sub_32 |
| 1513 | 0, // GPRMM16MoveP:sub_32_sub_hi_then_sub_32 |
| 1514 | }, |
| 1515 | { // GPRMM16Zero |
| 1516 | 0, // GPRMM16Zero:sub_32 |
| 1517 | 0, // GPRMM16Zero:sub_64 |
| 1518 | 0, // GPRMM16Zero:sub_dsp16_19 |
| 1519 | 0, // GPRMM16Zero:sub_dsp20 |
| 1520 | 0, // GPRMM16Zero:sub_dsp21 |
| 1521 | 0, // GPRMM16Zero:sub_dsp22 |
| 1522 | 0, // GPRMM16Zero:sub_dsp23 |
| 1523 | 0, // GPRMM16Zero:sub_hi |
| 1524 | 0, // GPRMM16Zero:sub_lo |
| 1525 | 0, // GPRMM16Zero:sub_hi_then_sub_32 |
| 1526 | 0, // GPRMM16Zero:sub_32_sub_hi_then_sub_32 |
| 1527 | }, |
| 1528 | { // CPU16Regs_and_GPRMM16Zero |
| 1529 | 0, // CPU16Regs_and_GPRMM16Zero:sub_32 |
| 1530 | 0, // CPU16Regs_and_GPRMM16Zero:sub_64 |
| 1531 | 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp16_19 |
| 1532 | 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp20 |
| 1533 | 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp21 |
| 1534 | 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp22 |
| 1535 | 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp23 |
| 1536 | 0, // CPU16Regs_and_GPRMM16Zero:sub_hi |
| 1537 | 0, // CPU16Regs_and_GPRMM16Zero:sub_lo |
| 1538 | 0, // CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32 |
| 1539 | 0, // CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32 |
| 1540 | }, |
| 1541 | { // GPR32NONZERO_and_GPRMM16MoveP |
| 1542 | 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_32 |
| 1543 | 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_64 |
| 1544 | 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19 |
| 1545 | 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20 |
| 1546 | 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21 |
| 1547 | 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22 |
| 1548 | 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23 |
| 1549 | 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi |
| 1550 | 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_lo |
| 1551 | 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32 |
| 1552 | 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32 |
| 1553 | }, |
| 1554 | { // GPRMM16MovePPairSecond |
| 1555 | 0, // GPRMM16MovePPairSecond:sub_32 |
| 1556 | 0, // GPRMM16MovePPairSecond:sub_64 |
| 1557 | 0, // GPRMM16MovePPairSecond:sub_dsp16_19 |
| 1558 | 0, // GPRMM16MovePPairSecond:sub_dsp20 |
| 1559 | 0, // GPRMM16MovePPairSecond:sub_dsp21 |
| 1560 | 0, // GPRMM16MovePPairSecond:sub_dsp22 |
| 1561 | 0, // GPRMM16MovePPairSecond:sub_dsp23 |
| 1562 | 0, // GPRMM16MovePPairSecond:sub_hi |
| 1563 | 0, // GPRMM16MovePPairSecond:sub_lo |
| 1564 | 0, // GPRMM16MovePPairSecond:sub_hi_then_sub_32 |
| 1565 | 0, // GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32 |
| 1566 | }, |
| 1567 | { // CPU16Regs_and_GPRMM16MoveP |
| 1568 | 0, // CPU16Regs_and_GPRMM16MoveP:sub_32 |
| 1569 | 0, // CPU16Regs_and_GPRMM16MoveP:sub_64 |
| 1570 | 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19 |
| 1571 | 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp20 |
| 1572 | 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp21 |
| 1573 | 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp22 |
| 1574 | 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp23 |
| 1575 | 0, // CPU16Regs_and_GPRMM16MoveP:sub_hi |
| 1576 | 0, // CPU16Regs_and_GPRMM16MoveP:sub_lo |
| 1577 | 0, // CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32 |
| 1578 | 0, // CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32 |
| 1579 | }, |
| 1580 | { // GPRMM16MoveP_and_GPRMM16Zero |
| 1581 | 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_32 |
| 1582 | 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_64 |
| 1583 | 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19 |
| 1584 | 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20 |
| 1585 | 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21 |
| 1586 | 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22 |
| 1587 | 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23 |
| 1588 | 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi |
| 1589 | 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_lo |
| 1590 | 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32 |
| 1591 | 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32 |
| 1592 | }, |
| 1593 | { // HI32DSP |
| 1594 | 0, // HI32DSP:sub_32 |
| 1595 | 0, // HI32DSP:sub_64 |
| 1596 | 0, // HI32DSP:sub_dsp16_19 |
| 1597 | 0, // HI32DSP:sub_dsp20 |
| 1598 | 0, // HI32DSP:sub_dsp21 |
| 1599 | 0, // HI32DSP:sub_dsp22 |
| 1600 | 0, // HI32DSP:sub_dsp23 |
| 1601 | 0, // HI32DSP:sub_hi |
| 1602 | 0, // HI32DSP:sub_lo |
| 1603 | 0, // HI32DSP:sub_hi_then_sub_32 |
| 1604 | 0, // HI32DSP:sub_32_sub_hi_then_sub_32 |
| 1605 | }, |
| 1606 | { // LO32DSP |
| 1607 | 0, // LO32DSP:sub_32 |
| 1608 | 0, // LO32DSP:sub_64 |
| 1609 | 0, // LO32DSP:sub_dsp16_19 |
| 1610 | 0, // LO32DSP:sub_dsp20 |
| 1611 | 0, // LO32DSP:sub_dsp21 |
| 1612 | 0, // LO32DSP:sub_dsp22 |
| 1613 | 0, // LO32DSP:sub_dsp23 |
| 1614 | 0, // LO32DSP:sub_hi |
| 1615 | 0, // LO32DSP:sub_lo |
| 1616 | 0, // LO32DSP:sub_hi_then_sub_32 |
| 1617 | 0, // LO32DSP:sub_32_sub_hi_then_sub_32 |
| 1618 | }, |
| 1619 | { // CPU16Regs_and_GPRMM16MovePPairSecond |
| 1620 | 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32 |
| 1621 | 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_64 |
| 1622 | 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19 |
| 1623 | 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20 |
| 1624 | 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21 |
| 1625 | 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22 |
| 1626 | 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23 |
| 1627 | 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi |
| 1628 | 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo |
| 1629 | 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32 |
| 1630 | 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32 |
| 1631 | }, |
| 1632 | { // GPRMM16MovePPairFirst |
| 1633 | 0, // GPRMM16MovePPairFirst:sub_32 |
| 1634 | 0, // GPRMM16MovePPairFirst:sub_64 |
| 1635 | 0, // GPRMM16MovePPairFirst:sub_dsp16_19 |
| 1636 | 0, // GPRMM16MovePPairFirst:sub_dsp20 |
| 1637 | 0, // GPRMM16MovePPairFirst:sub_dsp21 |
| 1638 | 0, // GPRMM16MovePPairFirst:sub_dsp22 |
| 1639 | 0, // GPRMM16MovePPairFirst:sub_dsp23 |
| 1640 | 0, // GPRMM16MovePPairFirst:sub_hi |
| 1641 | 0, // GPRMM16MovePPairFirst:sub_lo |
| 1642 | 0, // GPRMM16MovePPairFirst:sub_hi_then_sub_32 |
| 1643 | 0, // GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32 |
| 1644 | }, |
| 1645 | { // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero |
| 1646 | 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32 |
| 1647 | 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64 |
| 1648 | 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19 |
| 1649 | 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20 |
| 1650 | 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21 |
| 1651 | 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22 |
| 1652 | 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23 |
| 1653 | 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi |
| 1654 | 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo |
| 1655 | 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32 |
| 1656 | 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32 |
| 1657 | }, |
| 1658 | { // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond |
| 1659 | 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32 |
| 1660 | 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64 |
| 1661 | 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19 |
| 1662 | 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20 |
| 1663 | 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21 |
| 1664 | 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22 |
| 1665 | 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23 |
| 1666 | 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi |
| 1667 | 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo |
| 1668 | 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32 |
| 1669 | 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32 |
| 1670 | }, |
| 1671 | { // CPURAReg |
| 1672 | 0, // CPURAReg:sub_32 |
| 1673 | 0, // CPURAReg:sub_64 |
| 1674 | 0, // CPURAReg:sub_dsp16_19 |
| 1675 | 0, // CPURAReg:sub_dsp20 |
| 1676 | 0, // CPURAReg:sub_dsp21 |
| 1677 | 0, // CPURAReg:sub_dsp22 |
| 1678 | 0, // CPURAReg:sub_dsp23 |
| 1679 | 0, // CPURAReg:sub_hi |
| 1680 | 0, // CPURAReg:sub_lo |
| 1681 | 0, // CPURAReg:sub_hi_then_sub_32 |
| 1682 | 0, // CPURAReg:sub_32_sub_hi_then_sub_32 |
| 1683 | }, |
| 1684 | { // CPUSPReg |
| 1685 | 0, // CPUSPReg:sub_32 |
| 1686 | 0, // CPUSPReg:sub_64 |
| 1687 | 0, // CPUSPReg:sub_dsp16_19 |
| 1688 | 0, // CPUSPReg:sub_dsp20 |
| 1689 | 0, // CPUSPReg:sub_dsp21 |
| 1690 | 0, // CPUSPReg:sub_dsp22 |
| 1691 | 0, // CPUSPReg:sub_dsp23 |
| 1692 | 0, // CPUSPReg:sub_hi |
| 1693 | 0, // CPUSPReg:sub_lo |
| 1694 | 0, // CPUSPReg:sub_hi_then_sub_32 |
| 1695 | 0, // CPUSPReg:sub_32_sub_hi_then_sub_32 |
| 1696 | }, |
| 1697 | { // DSPCC |
| 1698 | 0, // DSPCC:sub_32 |
| 1699 | 0, // DSPCC:sub_64 |
| 1700 | 0, // DSPCC:sub_dsp16_19 |
| 1701 | 0, // DSPCC:sub_dsp20 |
| 1702 | 0, // DSPCC:sub_dsp21 |
| 1703 | 0, // DSPCC:sub_dsp22 |
| 1704 | 0, // DSPCC:sub_dsp23 |
| 1705 | 0, // DSPCC:sub_hi |
| 1706 | 0, // DSPCC:sub_lo |
| 1707 | 0, // DSPCC:sub_hi_then_sub_32 |
| 1708 | 0, // DSPCC:sub_32_sub_hi_then_sub_32 |
| 1709 | }, |
| 1710 | { // GP32 |
| 1711 | 0, // GP32:sub_32 |
| 1712 | 0, // GP32:sub_64 |
| 1713 | 0, // GP32:sub_dsp16_19 |
| 1714 | 0, // GP32:sub_dsp20 |
| 1715 | 0, // GP32:sub_dsp21 |
| 1716 | 0, // GP32:sub_dsp22 |
| 1717 | 0, // GP32:sub_dsp23 |
| 1718 | 0, // GP32:sub_hi |
| 1719 | 0, // GP32:sub_lo |
| 1720 | 0, // GP32:sub_hi_then_sub_32 |
| 1721 | 0, // GP32:sub_32_sub_hi_then_sub_32 |
| 1722 | }, |
| 1723 | { // GPR32ZERO |
| 1724 | 0, // GPR32ZERO:sub_32 |
| 1725 | 0, // GPR32ZERO:sub_64 |
| 1726 | 0, // GPR32ZERO:sub_dsp16_19 |
| 1727 | 0, // GPR32ZERO:sub_dsp20 |
| 1728 | 0, // GPR32ZERO:sub_dsp21 |
| 1729 | 0, // GPR32ZERO:sub_dsp22 |
| 1730 | 0, // GPR32ZERO:sub_dsp23 |
| 1731 | 0, // GPR32ZERO:sub_hi |
| 1732 | 0, // GPR32ZERO:sub_lo |
| 1733 | 0, // GPR32ZERO:sub_hi_then_sub_32 |
| 1734 | 0, // GPR32ZERO:sub_32_sub_hi_then_sub_32 |
| 1735 | }, |
| 1736 | { // HI32 |
| 1737 | 0, // HI32:sub_32 |
| 1738 | 0, // HI32:sub_64 |
| 1739 | 0, // HI32:sub_dsp16_19 |
| 1740 | 0, // HI32:sub_dsp20 |
| 1741 | 0, // HI32:sub_dsp21 |
| 1742 | 0, // HI32:sub_dsp22 |
| 1743 | 0, // HI32:sub_dsp23 |
| 1744 | 0, // HI32:sub_hi |
| 1745 | 0, // HI32:sub_lo |
| 1746 | 0, // HI32:sub_hi_then_sub_32 |
| 1747 | 0, // HI32:sub_32_sub_hi_then_sub_32 |
| 1748 | }, |
| 1749 | { // LO32 |
| 1750 | 0, // LO32:sub_32 |
| 1751 | 0, // LO32:sub_64 |
| 1752 | 0, // LO32:sub_dsp16_19 |
| 1753 | 0, // LO32:sub_dsp20 |
| 1754 | 0, // LO32:sub_dsp21 |
| 1755 | 0, // LO32:sub_dsp22 |
| 1756 | 0, // LO32:sub_dsp23 |
| 1757 | 0, // LO32:sub_hi |
| 1758 | 0, // LO32:sub_lo |
| 1759 | 0, // LO32:sub_hi_then_sub_32 |
| 1760 | 0, // LO32:sub_32_sub_hi_then_sub_32 |
| 1761 | }, |
| 1762 | { // SP32 |
| 1763 | 0, // SP32:sub_32 |
| 1764 | 0, // SP32:sub_64 |
| 1765 | 0, // SP32:sub_dsp16_19 |
| 1766 | 0, // SP32:sub_dsp20 |
| 1767 | 0, // SP32:sub_dsp21 |
| 1768 | 0, // SP32:sub_dsp22 |
| 1769 | 0, // SP32:sub_dsp23 |
| 1770 | 0, // SP32:sub_hi |
| 1771 | 0, // SP32:sub_lo |
| 1772 | 0, // SP32:sub_hi_then_sub_32 |
| 1773 | 0, // SP32:sub_32_sub_hi_then_sub_32 |
| 1774 | }, |
| 1775 | { // FGR64CC |
| 1776 | 0, // FGR64CC:sub_32 |
| 1777 | 0, // FGR64CC:sub_64 |
| 1778 | 0, // FGR64CC:sub_dsp16_19 |
| 1779 | 0, // FGR64CC:sub_dsp20 |
| 1780 | 0, // FGR64CC:sub_dsp21 |
| 1781 | 0, // FGR64CC:sub_dsp22 |
| 1782 | 0, // FGR64CC:sub_dsp23 |
| 1783 | 0, // FGR64CC:sub_hi |
| 1784 | 6, // FGR64CC:sub_lo -> FGR32 |
| 1785 | 0, // FGR64CC:sub_hi_then_sub_32 |
| 1786 | 0, // FGR64CC:sub_32_sub_hi_then_sub_32 |
| 1787 | }, |
| 1788 | { // FGR64 |
| 1789 | 0, // FGR64:sub_32 |
| 1790 | 0, // FGR64:sub_64 |
| 1791 | 0, // FGR64:sub_dsp16_19 |
| 1792 | 0, // FGR64:sub_dsp20 |
| 1793 | 0, // FGR64:sub_dsp21 |
| 1794 | 0, // FGR64:sub_dsp22 |
| 1795 | 0, // FGR64:sub_dsp23 |
| 1796 | 0, // FGR64:sub_hi |
| 1797 | 6, // FGR64:sub_lo -> FGR32 |
| 1798 | 0, // FGR64:sub_hi_then_sub_32 |
| 1799 | 0, // FGR64:sub_32_sub_hi_then_sub_32 |
| 1800 | }, |
| 1801 | { // GPR64 |
| 1802 | 5, // GPR64:sub_32 -> DSPR |
| 1803 | 0, // GPR64:sub_64 |
| 1804 | 0, // GPR64:sub_dsp16_19 |
| 1805 | 0, // GPR64:sub_dsp20 |
| 1806 | 0, // GPR64:sub_dsp21 |
| 1807 | 0, // GPR64:sub_dsp22 |
| 1808 | 0, // GPR64:sub_dsp23 |
| 1809 | 0, // GPR64:sub_hi |
| 1810 | 0, // GPR64:sub_lo |
| 1811 | 0, // GPR64:sub_hi_then_sub_32 |
| 1812 | 0, // GPR64:sub_32_sub_hi_then_sub_32 |
| 1813 | }, |
| 1814 | { // GPR64_with_sub_32_in_GPR32NONZERO |
| 1815 | 11, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32 -> GPR32NONZERO |
| 1816 | 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_64 |
| 1817 | 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp16_19 |
| 1818 | 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp20 |
| 1819 | 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp21 |
| 1820 | 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp22 |
| 1821 | 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp23 |
| 1822 | 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi |
| 1823 | 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_lo |
| 1824 | 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi_then_sub_32 |
| 1825 | 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32_sub_hi_then_sub_32 |
| 1826 | }, |
| 1827 | { // AFGR64 |
| 1828 | 0, // AFGR64:sub_32 |
| 1829 | 0, // AFGR64:sub_64 |
| 1830 | 0, // AFGR64:sub_dsp16_19 |
| 1831 | 0, // AFGR64:sub_dsp20 |
| 1832 | 0, // AFGR64:sub_dsp21 |
| 1833 | 0, // AFGR64:sub_dsp22 |
| 1834 | 0, // AFGR64:sub_dsp23 |
| 1835 | 7, // AFGR64:sub_hi -> FGR32CC |
| 1836 | 7, // AFGR64:sub_lo -> FGR32CC |
| 1837 | 0, // AFGR64:sub_hi_then_sub_32 |
| 1838 | 0, // AFGR64:sub_32_sub_hi_then_sub_32 |
| 1839 | }, |
| 1840 | { // GPR64_with_sub_32_in_CPU16RegsPlusSP |
| 1841 | 12, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32 -> CPU16RegsPlusSP |
| 1842 | 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_64 |
| 1843 | 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp16_19 |
| 1844 | 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp20 |
| 1845 | 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp21 |
| 1846 | 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp22 |
| 1847 | 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp23 |
| 1848 | 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi |
| 1849 | 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_lo |
| 1850 | 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi_then_sub_32 |
| 1851 | 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32 |
| 1852 | }, |
| 1853 | { // GPR64_with_sub_32_in_CPU16Regs |
| 1854 | 13, // GPR64_with_sub_32_in_CPU16Regs:sub_32 -> CPU16Regs |
| 1855 | 0, // GPR64_with_sub_32_in_CPU16Regs:sub_64 |
| 1856 | 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp16_19 |
| 1857 | 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp20 |
| 1858 | 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp21 |
| 1859 | 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp22 |
| 1860 | 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp23 |
| 1861 | 0, // GPR64_with_sub_32_in_CPU16Regs:sub_hi |
| 1862 | 0, // GPR64_with_sub_32_in_CPU16Regs:sub_lo |
| 1863 | 0, // GPR64_with_sub_32_in_CPU16Regs:sub_hi_then_sub_32 |
| 1864 | 0, // GPR64_with_sub_32_in_CPU16Regs:sub_32_sub_hi_then_sub_32 |
| 1865 | }, |
| 1866 | { // GPR64_with_sub_32_in_GPRMM16MoveP |
| 1867 | 16, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32 -> GPRMM16MoveP |
| 1868 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_64 |
| 1869 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp16_19 |
| 1870 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp20 |
| 1871 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp21 |
| 1872 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp22 |
| 1873 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp23 |
| 1874 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi |
| 1875 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_lo |
| 1876 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi_then_sub_32 |
| 1877 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32_sub_hi_then_sub_32 |
| 1878 | }, |
| 1879 | { // GPR64_with_sub_32_in_GPRMM16Zero |
| 1880 | 17, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32 -> GPRMM16Zero |
| 1881 | 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_64 |
| 1882 | 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp16_19 |
| 1883 | 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp20 |
| 1884 | 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp21 |
| 1885 | 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp22 |
| 1886 | 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp23 |
| 1887 | 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi |
| 1888 | 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_lo |
| 1889 | 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi_then_sub_32 |
| 1890 | 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32_sub_hi_then_sub_32 |
| 1891 | }, |
| 1892 | { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero |
| 1893 | 18, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32 -> CPU16Regs_and_GPRMM16Zero |
| 1894 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_64 |
| 1895 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19 |
| 1896 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp20 |
| 1897 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp21 |
| 1898 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp22 |
| 1899 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp23 |
| 1900 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi |
| 1901 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_lo |
| 1902 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32 |
| 1903 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32 |
| 1904 | }, |
| 1905 | { // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP |
| 1906 | 19, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32 -> GPR32NONZERO_and_GPRMM16MoveP |
| 1907 | 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_64 |
| 1908 | 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19 |
| 1909 | 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20 |
| 1910 | 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21 |
| 1911 | 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22 |
| 1912 | 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23 |
| 1913 | 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi |
| 1914 | 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_lo |
| 1915 | 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32 |
| 1916 | 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32 |
| 1917 | }, |
| 1918 | { // GPR64_with_sub_32_in_GPRMM16MovePPairSecond |
| 1919 | 20, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairSecond |
| 1920 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_64 |
| 1921 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp16_19 |
| 1922 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp20 |
| 1923 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp21 |
| 1924 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp22 |
| 1925 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp23 |
| 1926 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi |
| 1927 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_lo |
| 1928 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi_then_sub_32 |
| 1929 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32 |
| 1930 | }, |
| 1931 | { // ACC64DSP |
| 1932 | 0, // ACC64DSP:sub_32 |
| 1933 | 0, // ACC64DSP:sub_64 |
| 1934 | 0, // ACC64DSP:sub_dsp16_19 |
| 1935 | 0, // ACC64DSP:sub_dsp20 |
| 1936 | 0, // ACC64DSP:sub_dsp21 |
| 1937 | 0, // ACC64DSP:sub_dsp22 |
| 1938 | 0, // ACC64DSP:sub_dsp23 |
| 1939 | 23, // ACC64DSP:sub_hi -> HI32DSP |
| 1940 | 24, // ACC64DSP:sub_lo -> LO32DSP |
| 1941 | 0, // ACC64DSP:sub_hi_then_sub_32 |
| 1942 | 0, // ACC64DSP:sub_32_sub_hi_then_sub_32 |
| 1943 | }, |
| 1944 | { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP |
| 1945 | 21, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32 -> CPU16Regs_and_GPRMM16MoveP |
| 1946 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_64 |
| 1947 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19 |
| 1948 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp20 |
| 1949 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp21 |
| 1950 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp22 |
| 1951 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp23 |
| 1952 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi |
| 1953 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_lo |
| 1954 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32 |
| 1955 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32 |
| 1956 | }, |
| 1957 | { // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero |
| 1958 | 22, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_GPRMM16Zero |
| 1959 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_64 |
| 1960 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19 |
| 1961 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20 |
| 1962 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21 |
| 1963 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22 |
| 1964 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23 |
| 1965 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi |
| 1966 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_lo |
| 1967 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32 |
| 1968 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32 |
| 1969 | }, |
| 1970 | { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond |
| 1971 | 25, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32 -> CPU16Regs_and_GPRMM16MovePPairSecond |
| 1972 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_64 |
| 1973 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19 |
| 1974 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20 |
| 1975 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21 |
| 1976 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22 |
| 1977 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23 |
| 1978 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi |
| 1979 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo |
| 1980 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32 |
| 1981 | 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32 |
| 1982 | }, |
| 1983 | { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst |
| 1984 | 26, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32 -> GPRMM16MovePPairFirst |
| 1985 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_64 |
| 1986 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp16_19 |
| 1987 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp20 |
| 1988 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp21 |
| 1989 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp22 |
| 1990 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp23 |
| 1991 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi |
| 1992 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_lo |
| 1993 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi_then_sub_32 |
| 1994 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32 |
| 1995 | }, |
| 1996 | { // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero |
| 1997 | 27, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero |
| 1998 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64 |
| 1999 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19 |
| 2000 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20 |
| 2001 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21 |
| 2002 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22 |
| 2003 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23 |
| 2004 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi |
| 2005 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo |
| 2006 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32 |
| 2007 | 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32 |
| 2008 | }, |
| 2009 | { // OCTEON_MPL |
| 2010 | 0, // OCTEON_MPL:sub_32 |
| 2011 | 0, // OCTEON_MPL:sub_64 |
| 2012 | 0, // OCTEON_MPL:sub_dsp16_19 |
| 2013 | 0, // OCTEON_MPL:sub_dsp20 |
| 2014 | 0, // OCTEON_MPL:sub_dsp21 |
| 2015 | 0, // OCTEON_MPL:sub_dsp22 |
| 2016 | 0, // OCTEON_MPL:sub_dsp23 |
| 2017 | 0, // OCTEON_MPL:sub_hi |
| 2018 | 0, // OCTEON_MPL:sub_lo |
| 2019 | 0, // OCTEON_MPL:sub_hi_then_sub_32 |
| 2020 | 0, // OCTEON_MPL:sub_32_sub_hi_then_sub_32 |
| 2021 | }, |
| 2022 | { // OCTEON_P |
| 2023 | 0, // OCTEON_P:sub_32 |
| 2024 | 0, // OCTEON_P:sub_64 |
| 2025 | 0, // OCTEON_P:sub_dsp16_19 |
| 2026 | 0, // OCTEON_P:sub_dsp20 |
| 2027 | 0, // OCTEON_P:sub_dsp21 |
| 2028 | 0, // OCTEON_P:sub_dsp22 |
| 2029 | 0, // OCTEON_P:sub_dsp23 |
| 2030 | 0, // OCTEON_P:sub_hi |
| 2031 | 0, // OCTEON_P:sub_lo |
| 2032 | 0, // OCTEON_P:sub_hi_then_sub_32 |
| 2033 | 0, // OCTEON_P:sub_32_sub_hi_then_sub_32 |
| 2034 | }, |
| 2035 | { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond |
| 2036 | 28, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond |
| 2037 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64 |
| 2038 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19 |
| 2039 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20 |
| 2040 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21 |
| 2041 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22 |
| 2042 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23 |
| 2043 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi |
| 2044 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo |
| 2045 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32 |
| 2046 | 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32 |
| 2047 | }, |
| 2048 | { // ACC64 |
| 2049 | 0, // ACC64:sub_32 |
| 2050 | 0, // ACC64:sub_64 |
| 2051 | 0, // ACC64:sub_dsp16_19 |
| 2052 | 0, // ACC64:sub_dsp20 |
| 2053 | 0, // ACC64:sub_dsp21 |
| 2054 | 0, // ACC64:sub_dsp22 |
| 2055 | 0, // ACC64:sub_dsp23 |
| 2056 | 34, // ACC64:sub_hi -> HI32 |
| 2057 | 35, // ACC64:sub_lo -> LO32 |
| 2058 | 0, // ACC64:sub_hi_then_sub_32 |
| 2059 | 0, // ACC64:sub_32_sub_hi_then_sub_32 |
| 2060 | }, |
| 2061 | { // GP64 |
| 2062 | 32, // GP64:sub_32 -> GP32 |
| 2063 | 0, // GP64:sub_64 |
| 2064 | 0, // GP64:sub_dsp16_19 |
| 2065 | 0, // GP64:sub_dsp20 |
| 2066 | 0, // GP64:sub_dsp21 |
| 2067 | 0, // GP64:sub_dsp22 |
| 2068 | 0, // GP64:sub_dsp23 |
| 2069 | 0, // GP64:sub_hi |
| 2070 | 0, // GP64:sub_lo |
| 2071 | 0, // GP64:sub_hi_then_sub_32 |
| 2072 | 0, // GP64:sub_32_sub_hi_then_sub_32 |
| 2073 | }, |
| 2074 | { // GPR64_with_sub_32_in_CPURAReg |
| 2075 | 29, // GPR64_with_sub_32_in_CPURAReg:sub_32 -> CPURAReg |
| 2076 | 0, // GPR64_with_sub_32_in_CPURAReg:sub_64 |
| 2077 | 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp16_19 |
| 2078 | 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp20 |
| 2079 | 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp21 |
| 2080 | 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp22 |
| 2081 | 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp23 |
| 2082 | 0, // GPR64_with_sub_32_in_CPURAReg:sub_hi |
| 2083 | 0, // GPR64_with_sub_32_in_CPURAReg:sub_lo |
| 2084 | 0, // GPR64_with_sub_32_in_CPURAReg:sub_hi_then_sub_32 |
| 2085 | 0, // GPR64_with_sub_32_in_CPURAReg:sub_32_sub_hi_then_sub_32 |
| 2086 | }, |
| 2087 | { // GPR64_with_sub_32_in_GPR32ZERO |
| 2088 | 33, // GPR64_with_sub_32_in_GPR32ZERO:sub_32 -> GPR32ZERO |
| 2089 | 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_64 |
| 2090 | 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp16_19 |
| 2091 | 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp20 |
| 2092 | 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp21 |
| 2093 | 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp22 |
| 2094 | 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp23 |
| 2095 | 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi |
| 2096 | 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_lo |
| 2097 | 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi_then_sub_32 |
| 2098 | 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_32_sub_hi_then_sub_32 |
| 2099 | }, |
| 2100 | { // HI64 |
| 2101 | 34, // HI64:sub_32 -> HI32 |
| 2102 | 0, // HI64:sub_64 |
| 2103 | 0, // HI64:sub_dsp16_19 |
| 2104 | 0, // HI64:sub_dsp20 |
| 2105 | 0, // HI64:sub_dsp21 |
| 2106 | 0, // HI64:sub_dsp22 |
| 2107 | 0, // HI64:sub_dsp23 |
| 2108 | 0, // HI64:sub_hi |
| 2109 | 0, // HI64:sub_lo |
| 2110 | 0, // HI64:sub_hi_then_sub_32 |
| 2111 | 0, // HI64:sub_32_sub_hi_then_sub_32 |
| 2112 | }, |
| 2113 | { // LO64 |
| 2114 | 35, // LO64:sub_32 -> LO32 |
| 2115 | 0, // LO64:sub_64 |
| 2116 | 0, // LO64:sub_dsp16_19 |
| 2117 | 0, // LO64:sub_dsp20 |
| 2118 | 0, // LO64:sub_dsp21 |
| 2119 | 0, // LO64:sub_dsp22 |
| 2120 | 0, // LO64:sub_dsp23 |
| 2121 | 0, // LO64:sub_hi |
| 2122 | 0, // LO64:sub_lo |
| 2123 | 0, // LO64:sub_hi_then_sub_32 |
| 2124 | 0, // LO64:sub_32_sub_hi_then_sub_32 |
| 2125 | }, |
| 2126 | { // SP64 |
| 2127 | 30, // SP64:sub_32 -> CPUSPReg |
| 2128 | 0, // SP64:sub_64 |
| 2129 | 0, // SP64:sub_dsp16_19 |
| 2130 | 0, // SP64:sub_dsp20 |
| 2131 | 0, // SP64:sub_dsp21 |
| 2132 | 0, // SP64:sub_dsp22 |
| 2133 | 0, // SP64:sub_dsp23 |
| 2134 | 0, // SP64:sub_hi |
| 2135 | 0, // SP64:sub_lo |
| 2136 | 0, // SP64:sub_hi_then_sub_32 |
| 2137 | 0, // SP64:sub_32_sub_hi_then_sub_32 |
| 2138 | }, |
| 2139 | { // MSA128B |
| 2140 | 0, // MSA128B:sub_32 |
| 2141 | 37, // MSA128B:sub_64 -> FGR64CC |
| 2142 | 0, // MSA128B:sub_dsp16_19 |
| 2143 | 0, // MSA128B:sub_dsp20 |
| 2144 | 0, // MSA128B:sub_dsp21 |
| 2145 | 0, // MSA128B:sub_dsp22 |
| 2146 | 0, // MSA128B:sub_dsp23 |
| 2147 | 0, // MSA128B:sub_hi |
| 2148 | 6, // MSA128B:sub_lo -> FGR32 |
| 2149 | 0, // MSA128B:sub_hi_then_sub_32 |
| 2150 | 0, // MSA128B:sub_32_sub_hi_then_sub_32 |
| 2151 | }, |
| 2152 | { // MSA128D |
| 2153 | 0, // MSA128D:sub_32 |
| 2154 | 37, // MSA128D:sub_64 -> FGR64CC |
| 2155 | 0, // MSA128D:sub_dsp16_19 |
| 2156 | 0, // MSA128D:sub_dsp20 |
| 2157 | 0, // MSA128D:sub_dsp21 |
| 2158 | 0, // MSA128D:sub_dsp22 |
| 2159 | 0, // MSA128D:sub_dsp23 |
| 2160 | 0, // MSA128D:sub_hi |
| 2161 | 6, // MSA128D:sub_lo -> FGR32 |
| 2162 | 0, // MSA128D:sub_hi_then_sub_32 |
| 2163 | 0, // MSA128D:sub_32_sub_hi_then_sub_32 |
| 2164 | }, |
| 2165 | { // MSA128H |
| 2166 | 0, // MSA128H:sub_32 |
| 2167 | 37, // MSA128H:sub_64 -> FGR64CC |
| 2168 | 0, // MSA128H:sub_dsp16_19 |
| 2169 | 0, // MSA128H:sub_dsp20 |
| 2170 | 0, // MSA128H:sub_dsp21 |
| 2171 | 0, // MSA128H:sub_dsp22 |
| 2172 | 0, // MSA128H:sub_dsp23 |
| 2173 | 0, // MSA128H:sub_hi |
| 2174 | 6, // MSA128H:sub_lo -> FGR32 |
| 2175 | 0, // MSA128H:sub_hi_then_sub_32 |
| 2176 | 0, // MSA128H:sub_32_sub_hi_then_sub_32 |
| 2177 | }, |
| 2178 | { // MSA128W |
| 2179 | 0, // MSA128W:sub_32 |
| 2180 | 37, // MSA128W:sub_64 -> FGR64CC |
| 2181 | 0, // MSA128W:sub_dsp16_19 |
| 2182 | 0, // MSA128W:sub_dsp20 |
| 2183 | 0, // MSA128W:sub_dsp21 |
| 2184 | 0, // MSA128W:sub_dsp22 |
| 2185 | 0, // MSA128W:sub_dsp23 |
| 2186 | 0, // MSA128W:sub_hi |
| 2187 | 6, // MSA128W:sub_lo -> FGR32 |
| 2188 | 0, // MSA128W:sub_hi_then_sub_32 |
| 2189 | 0, // MSA128W:sub_32_sub_hi_then_sub_32 |
| 2190 | }, |
| 2191 | { // MSA128WEvens |
| 2192 | 0, // MSA128WEvens:sub_32 |
| 2193 | 38, // MSA128WEvens:sub_64 -> FGR64 |
| 2194 | 0, // MSA128WEvens:sub_dsp16_19 |
| 2195 | 0, // MSA128WEvens:sub_dsp20 |
| 2196 | 0, // MSA128WEvens:sub_dsp21 |
| 2197 | 0, // MSA128WEvens:sub_dsp22 |
| 2198 | 0, // MSA128WEvens:sub_dsp23 |
| 2199 | 0, // MSA128WEvens:sub_hi |
| 2200 | 7, // MSA128WEvens:sub_lo -> FGR32CC |
| 2201 | 0, // MSA128WEvens:sub_hi_then_sub_32 |
| 2202 | 0, // MSA128WEvens:sub_32_sub_hi_then_sub_32 |
| 2203 | }, |
| 2204 | { // ACC128 |
| 2205 | 35, // ACC128:sub_32 -> LO32 |
| 2206 | 0, // ACC128:sub_64 |
| 2207 | 0, // ACC128:sub_dsp16_19 |
| 2208 | 0, // ACC128:sub_dsp20 |
| 2209 | 0, // ACC128:sub_dsp21 |
| 2210 | 0, // ACC128:sub_dsp22 |
| 2211 | 0, // ACC128:sub_dsp23 |
| 2212 | 62, // ACC128:sub_hi -> HI64 |
| 2213 | 63, // ACC128:sub_lo -> LO64 |
| 2214 | 34, // ACC128:sub_hi_then_sub_32 -> HI32 |
| 2215 | 58, // ACC128:sub_32_sub_hi_then_sub_32 -> ACC64 |
| 2216 | }, |
| 2217 | |
| 2218 | }; |
| 2219 | assert(RC && "Missing regclass"); |
| 2220 | if (!Idx) return RC; |
| 2221 | --Idx; |
| 2222 | assert(Idx < 11 && "Bad subreg"); |
| 2223 | unsigned TV = Table[RC->getID()][Idx]; |
| 2224 | return TV ? getRegClass(i: TV - 1) : nullptr; |
| 2225 | }/// Get the weight in units of pressure for this register class. |
| 2226 | const RegClassWeight &MipsGenRegisterInfo:: |
| 2227 | getRegClassWeight(const TargetRegisterClass *RC) const { |
| 2228 | static const RegClassWeight RCWeightTable[] = { |
| 2229 | {.RegWeight: 0, .WeightLimit: 0}, // CCR |
| 2230 | {.RegWeight: 0, .WeightLimit: 0}, // COP0 |
| 2231 | {.RegWeight: 0, .WeightLimit: 0}, // COP2 |
| 2232 | {.RegWeight: 0, .WeightLimit: 0}, // COP3 |
| 2233 | {.RegWeight: 1, .WeightLimit: 32}, // DSPR |
| 2234 | {.RegWeight: 1, .WeightLimit: 32}, // FGR32 |
| 2235 | {.RegWeight: 1, .WeightLimit: 32}, // FGR32CC |
| 2236 | {.RegWeight: 1, .WeightLimit: 32}, // GPR32 |
| 2237 | {.RegWeight: 0, .WeightLimit: 0}, // HWRegs |
| 2238 | {.RegWeight: 0, .WeightLimit: 0}, // MSACtrl |
| 2239 | {.RegWeight: 1, .WeightLimit: 31}, // GPR32NONZERO |
| 2240 | {.RegWeight: 1, .WeightLimit: 9}, // CPU16RegsPlusSP |
| 2241 | {.RegWeight: 1, .WeightLimit: 8}, // CPU16Regs |
| 2242 | {.RegWeight: 0, .WeightLimit: 0}, // FCC |
| 2243 | {.RegWeight: 1, .WeightLimit: 8}, // GPRMM16 |
| 2244 | {.RegWeight: 1, .WeightLimit: 8}, // GPRMM16MoveP |
| 2245 | {.RegWeight: 1, .WeightLimit: 8}, // GPRMM16Zero |
| 2246 | {.RegWeight: 1, .WeightLimit: 7}, // CPU16Regs_and_GPRMM16Zero |
| 2247 | {.RegWeight: 1, .WeightLimit: 7}, // GPR32NONZERO_and_GPRMM16MoveP |
| 2248 | {.RegWeight: 1, .WeightLimit: 5}, // GPRMM16MovePPairSecond |
| 2249 | {.RegWeight: 1, .WeightLimit: 4}, // CPU16Regs_and_GPRMM16MoveP |
| 2250 | {.RegWeight: 1, .WeightLimit: 4}, // GPRMM16MoveP_and_GPRMM16Zero |
| 2251 | {.RegWeight: 1, .WeightLimit: 4}, // HI32DSP |
| 2252 | {.RegWeight: 1, .WeightLimit: 4}, // LO32DSP |
| 2253 | {.RegWeight: 1, .WeightLimit: 3}, // CPU16Regs_and_GPRMM16MovePPairSecond |
| 2254 | {.RegWeight: 1, .WeightLimit: 3}, // GPRMM16MovePPairFirst |
| 2255 | {.RegWeight: 1, .WeightLimit: 3}, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero |
| 2256 | {.RegWeight: 1, .WeightLimit: 2}, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond |
| 2257 | {.RegWeight: 1, .WeightLimit: 1}, // CPURAReg |
| 2258 | {.RegWeight: 1, .WeightLimit: 1}, // CPUSPReg |
| 2259 | {.RegWeight: 1, .WeightLimit: 1}, // DSPCC |
| 2260 | {.RegWeight: 1, .WeightLimit: 1}, // GP32 |
| 2261 | {.RegWeight: 1, .WeightLimit: 1}, // GPR32ZERO |
| 2262 | {.RegWeight: 1, .WeightLimit: 1}, // HI32 |
| 2263 | {.RegWeight: 1, .WeightLimit: 1}, // LO32 |
| 2264 | {.RegWeight: 1, .WeightLimit: 1}, // SP32 |
| 2265 | {.RegWeight: 2, .WeightLimit: 64}, // FGR64CC |
| 2266 | {.RegWeight: 2, .WeightLimit: 64}, // FGR64 |
| 2267 | {.RegWeight: 1, .WeightLimit: 32}, // GPR64 |
| 2268 | {.RegWeight: 1, .WeightLimit: 31}, // GPR64_with_sub_32_in_GPR32NONZERO |
| 2269 | {.RegWeight: 2, .WeightLimit: 32}, // AFGR64 |
| 2270 | {.RegWeight: 1, .WeightLimit: 9}, // GPR64_with_sub_32_in_CPU16RegsPlusSP |
| 2271 | {.RegWeight: 1, .WeightLimit: 8}, // GPR64_with_sub_32_in_CPU16Regs |
| 2272 | {.RegWeight: 1, .WeightLimit: 8}, // GPR64_with_sub_32_in_GPRMM16MoveP |
| 2273 | {.RegWeight: 1, .WeightLimit: 8}, // GPR64_with_sub_32_in_GPRMM16Zero |
| 2274 | {.RegWeight: 1, .WeightLimit: 7}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero |
| 2275 | {.RegWeight: 1, .WeightLimit: 7}, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP |
| 2276 | {.RegWeight: 1, .WeightLimit: 5}, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond |
| 2277 | {.RegWeight: 2, .WeightLimit: 8}, // ACC64DSP |
| 2278 | {.RegWeight: 1, .WeightLimit: 4}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP |
| 2279 | {.RegWeight: 1, .WeightLimit: 4}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero |
| 2280 | {.RegWeight: 1, .WeightLimit: 3}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond |
| 2281 | {.RegWeight: 1, .WeightLimit: 3}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst |
| 2282 | {.RegWeight: 1, .WeightLimit: 3}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero |
| 2283 | {.RegWeight: 0, .WeightLimit: 0}, // OCTEON_MPL |
| 2284 | {.RegWeight: 0, .WeightLimit: 0}, // OCTEON_P |
| 2285 | {.RegWeight: 1, .WeightLimit: 2}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond |
| 2286 | {.RegWeight: 2, .WeightLimit: 2}, // ACC64 |
| 2287 | {.RegWeight: 1, .WeightLimit: 1}, // GP64 |
| 2288 | {.RegWeight: 1, .WeightLimit: 1}, // GPR64_with_sub_32_in_CPURAReg |
| 2289 | {.RegWeight: 1, .WeightLimit: 1}, // GPR64_with_sub_32_in_GPR32ZERO |
| 2290 | {.RegWeight: 1, .WeightLimit: 1}, // HI64 |
| 2291 | {.RegWeight: 1, .WeightLimit: 1}, // LO64 |
| 2292 | {.RegWeight: 1, .WeightLimit: 1}, // SP64 |
| 2293 | {.RegWeight: 2, .WeightLimit: 64}, // MSA128B |
| 2294 | {.RegWeight: 2, .WeightLimit: 64}, // MSA128D |
| 2295 | {.RegWeight: 2, .WeightLimit: 64}, // MSA128H |
| 2296 | {.RegWeight: 2, .WeightLimit: 64}, // MSA128W |
| 2297 | {.RegWeight: 2, .WeightLimit: 32}, // MSA128WEvens |
| 2298 | {.RegWeight: 2, .WeightLimit: 2}, // ACC128 |
| 2299 | }; |
| 2300 | return RCWeightTable[RC->getID()]; |
| 2301 | } |
| 2302 | |
| 2303 | /// Get the weight in units of pressure for this register unit. |
| 2304 | unsigned MipsGenRegisterInfo:: |
| 2305 | getRegUnitWeight(MCRegUnit RegUnit) const { |
| 2306 | assert(static_cast<unsigned>(RegUnit) < 321 && "invalid register unit"); |
| 2307 | // All register units have unit weight. |
| 2308 | return 1; |
| 2309 | } |
| 2310 | |
| 2311 | |
| 2312 | // Get the number of dimensions of register pressure. |
| 2313 | unsigned MipsGenRegisterInfo::getNumRegPressureSets() const { |
| 2314 | return 20; |
| 2315 | } |
| 2316 | |
| 2317 | // Get the name of this register unit pressure set. |
| 2318 | const char *MipsGenRegisterInfo:: |
| 2319 | getRegPressureSetName(unsigned Idx) const { |
| 2320 | static const char *PressureNameTable[] = { |
| 2321 | "DSPCC", |
| 2322 | "GPR32ZERO", |
| 2323 | "GPR64_with_sub_32_in_CPURAReg", |
| 2324 | "HI32", |
| 2325 | "GPRMM16MovePPairFirst", |
| 2326 | "CPU16Regs_and_GPRMM16MoveP", |
| 2327 | "HI32DSP", |
| 2328 | "LO32DSP", |
| 2329 | "GPRMM16MovePPairSecond", |
| 2330 | "GPRMM16MoveP", |
| 2331 | "ACC64DSP", |
| 2332 | "CPU16Regs", |
| 2333 | "GPRMM16Zero_with_GPRMM16MovePPairSecond", |
| 2334 | "CPU16Regs_with_GPRMM16MovePPairSecond", |
| 2335 | "CPU16Regs_with_GPRMM16MoveP", |
| 2336 | "DSPR", |
| 2337 | "FGR32", |
| 2338 | "MSA128WEvens", |
| 2339 | "FGR32_with_MSA128WEvens", |
| 2340 | "FGR64CC", |
| 2341 | }; |
| 2342 | return PressureNameTable[Idx]; |
| 2343 | } |
| 2344 | |
| 2345 | // Get the register unit pressure limit for this dimension. |
| 2346 | // This limit must be adjusted dynamically for reserved registers. |
| 2347 | unsigned MipsGenRegisterInfo:: |
| 2348 | getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const { |
| 2349 | static const uint8_t PressureLimitTable[] = { |
| 2350 | 1, // 0: DSPCC |
| 2351 | 1, // 1: GPR32ZERO |
| 2352 | 1, // 2: GPR64_with_sub_32_in_CPURAReg |
| 2353 | 2, // 3: HI32 |
| 2354 | 3, // 4: GPRMM16MovePPairFirst |
| 2355 | 5, // 5: CPU16Regs_and_GPRMM16MoveP |
| 2356 | 5, // 6: HI32DSP |
| 2357 | 5, // 7: LO32DSP |
| 2358 | 6, // 8: GPRMM16MovePPairSecond |
| 2359 | 8, // 9: GPRMM16MoveP |
| 2360 | 8, // 10: ACC64DSP |
| 2361 | 10, // 11: CPU16Regs |
| 2362 | 10, // 12: GPRMM16Zero_with_GPRMM16MovePPairSecond |
| 2363 | 11, // 13: CPU16Regs_with_GPRMM16MovePPairSecond |
| 2364 | 13, // 14: CPU16Regs_with_GPRMM16MoveP |
| 2365 | 32, // 15: DSPR |
| 2366 | 32, // 16: FGR32 |
| 2367 | 32, // 17: MSA128WEvens |
| 2368 | 48, // 18: FGR32_with_MSA128WEvens |
| 2369 | 64, // 19: FGR64CC |
| 2370 | }; |
| 2371 | return PressureLimitTable[Idx]; |
| 2372 | } |
| 2373 | |
| 2374 | /// Table of pressure sets per register class or unit. |
| 2375 | static const int RCSetsTable[] = { |
| 2376 | /* 0 */ 0, -1, |
| 2377 | /* 2 */ 6, 10, -1, |
| 2378 | /* 5 */ 3, 6, 7, 10, -1, |
| 2379 | /* 10 */ 2, 15, -1, |
| 2380 | /* 13 */ 8, 12, 13, 15, -1, |
| 2381 | /* 18 */ 9, 14, 15, -1, |
| 2382 | /* 22 */ 1, 5, 9, 11, 12, 14, 15, -1, |
| 2383 | /* 30 */ 5, 9, 11, 13, 14, 15, -1, |
| 2384 | /* 37 */ 4, 8, 11, 12, 13, 14, 15, -1, |
| 2385 | /* 45 */ 5, 9, 11, 12, 13, 14, 15, -1, |
| 2386 | /* 53 */ 16, 18, 19, -1, |
| 2387 | /* 57 */ 16, 17, 18, 19, -1, |
| 2388 | }; |
| 2389 | |
| 2390 | /// Get the dimensions of register pressure impacted by this register class. |
| 2391 | /// Returns a -1 terminated array of pressure set IDs |
| 2392 | const int *MipsGenRegisterInfo:: |
| 2393 | getRegClassPressureSets(const TargetRegisterClass *RC) const { |
| 2394 | static const uint8_t RCSetStartTable[] = { |
| 2395 | 1,1,1,1,11,53,53,11,1,1,11,32,32,1,32,18,25,39,18,13,30,23,2,7,38,37,45,37,1,1,0,1,22,5,5,1,55,55,11,11,53,32,32,18,25,39,18,13,3,30,23,38,37,45,1,1,37,5,1,10,22,5,5,1,55,55,55,55,58,5,}; |
| 2396 | return &RCSetsTable[RCSetStartTable[RC->getID()]]; |
| 2397 | } |
| 2398 | |
| 2399 | /// Get the dimensions of register pressure impacted by this register unit. |
| 2400 | /// Returns a -1 terminated array of pressure set IDs |
| 2401 | const int *MipsGenRegisterInfo:: |
| 2402 | getRegUnitPressureSets(MCRegUnit RegUnit) const { |
| 2403 | assert(static_cast<unsigned>(RegUnit) < 321 && "invalid register unit"); |
| 2404 | static const uint8_t RUSetStartTable[] = { |
| 2405 | 11,0,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,10,32,22,37,37,37,38,5,5,7,2,7,2,7,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,30,45,18,18,18,13,13,11,11,11,11,11,11,11,11,11,11,11,45,45,}; |
| 2406 | return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]]; |
| 2407 | } |
| 2408 | |
| 2409 | ArrayRef<MCPhysReg> MipsGenRegisterInfo::getRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) const { |
| 2410 | switch (RC.getID()) { |
| 2411 | case Mips::FGR32RegClassID: |
| 2412 | return FGR32GetRawAllocationOrder(RC, MF, Rev); |
| 2413 | case Mips::FGR64RegClassID: |
| 2414 | return FGR64GetRawAllocationOrder(RC, MF, Rev); |
| 2415 | } |
| 2416 | return RC.getRegisters(); |
| 2417 | } |
| 2418 | |
| 2419 | |
| 2420 | // Register to minimal register class mapping |
| 2421 | |
| 2422 | const TargetRegisterClass *MipsGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const { |
| 2423 | static const uint16_t InvalidRegClassID = UINT16_MAX; |
| 2424 | |
| 2425 | static const uint16_t Mapping[442] = { |
| 2426 | InvalidRegClassID, // NoRegister |
| 2427 | Mips::GPR32NONZERORegClassID, // AT |
| 2428 | Mips::DSPCCRegClassID, // DSPCCond |
| 2429 | InvalidRegClassID, // DSPCarry |
| 2430 | InvalidRegClassID, // DSPEFI |
| 2431 | InvalidRegClassID, // DSPOutFlag |
| 2432 | InvalidRegClassID, // DSPPos |
| 2433 | InvalidRegClassID, // DSPSCount |
| 2434 | Mips::GPR32NONZERORegClassID, // FP |
| 2435 | Mips::GP32RegClassID, // GP |
| 2436 | Mips::MSACtrlRegClassID, // MSAAccess |
| 2437 | Mips::MSACtrlRegClassID, // MSACSR |
| 2438 | Mips::MSACtrlRegClassID, // MSAIR |
| 2439 | Mips::MSACtrlRegClassID, // MSAMap |
| 2440 | Mips::MSACtrlRegClassID, // MSAModify |
| 2441 | Mips::MSACtrlRegClassID, // MSARequest |
| 2442 | Mips::MSACtrlRegClassID, // MSASave |
| 2443 | Mips::MSACtrlRegClassID, // MSAUnmap |
| 2444 | InvalidRegClassID, // PC |
| 2445 | Mips::CPURARegRegClassID, // RA |
| 2446 | Mips::SP32RegClassID, // SP |
| 2447 | Mips::GPR32ZERORegClassID, // ZERO |
| 2448 | Mips::GPRMM16MovePPairFirstRegClassID, // A0 |
| 2449 | Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, // A1 |
| 2450 | Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, // A2 |
| 2451 | Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, // A3 |
| 2452 | Mips::ACC64RegClassID, // AC0 |
| 2453 | Mips::ACC64DSPRegClassID, // AC1 |
| 2454 | Mips::ACC64DSPRegClassID, // AC2 |
| 2455 | Mips::ACC64DSPRegClassID, // AC3 |
| 2456 | Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // AT_64 |
| 2457 | Mips::COP0RegClassID, // COP00 |
| 2458 | Mips::COP0RegClassID, // COP01 |
| 2459 | Mips::COP0RegClassID, // COP02 |
| 2460 | Mips::COP0RegClassID, // COP03 |
| 2461 | Mips::COP0RegClassID, // COP04 |
| 2462 | Mips::COP0RegClassID, // COP05 |
| 2463 | Mips::COP0RegClassID, // COP06 |
| 2464 | Mips::COP0RegClassID, // COP07 |
| 2465 | Mips::COP0RegClassID, // COP08 |
| 2466 | Mips::COP0RegClassID, // COP09 |
| 2467 | Mips::COP2RegClassID, // COP20 |
| 2468 | Mips::COP2RegClassID, // COP21 |
| 2469 | Mips::COP2RegClassID, // COP22 |
| 2470 | Mips::COP2RegClassID, // COP23 |
| 2471 | Mips::COP2RegClassID, // COP24 |
| 2472 | Mips::COP2RegClassID, // COP25 |
| 2473 | Mips::COP2RegClassID, // COP26 |
| 2474 | Mips::COP2RegClassID, // COP27 |
| 2475 | Mips::COP2RegClassID, // COP28 |
| 2476 | Mips::COP2RegClassID, // COP29 |
| 2477 | Mips::COP3RegClassID, // COP30 |
| 2478 | Mips::COP3RegClassID, // COP31 |
| 2479 | Mips::COP3RegClassID, // COP32 |
| 2480 | Mips::COP3RegClassID, // COP33 |
| 2481 | Mips::COP3RegClassID, // COP34 |
| 2482 | Mips::COP3RegClassID, // COP35 |
| 2483 | Mips::COP3RegClassID, // COP36 |
| 2484 | Mips::COP3RegClassID, // COP37 |
| 2485 | Mips::COP3RegClassID, // COP38 |
| 2486 | Mips::COP3RegClassID, // COP39 |
| 2487 | Mips::COP0RegClassID, // COP010 |
| 2488 | Mips::COP0RegClassID, // COP011 |
| 2489 | Mips::COP0RegClassID, // COP012 |
| 2490 | Mips::COP0RegClassID, // COP013 |
| 2491 | Mips::COP0RegClassID, // COP014 |
| 2492 | Mips::COP0RegClassID, // COP015 |
| 2493 | Mips::COP0RegClassID, // COP016 |
| 2494 | Mips::COP0RegClassID, // COP017 |
| 2495 | Mips::COP0RegClassID, // COP018 |
| 2496 | Mips::COP0RegClassID, // COP019 |
| 2497 | Mips::COP0RegClassID, // COP020 |
| 2498 | Mips::COP0RegClassID, // COP021 |
| 2499 | Mips::COP0RegClassID, // COP022 |
| 2500 | Mips::COP0RegClassID, // COP023 |
| 2501 | Mips::COP0RegClassID, // COP024 |
| 2502 | Mips::COP0RegClassID, // COP025 |
| 2503 | Mips::COP0RegClassID, // COP026 |
| 2504 | Mips::COP0RegClassID, // COP027 |
| 2505 | Mips::COP0RegClassID, // COP028 |
| 2506 | Mips::COP0RegClassID, // COP029 |
| 2507 | Mips::COP0RegClassID, // COP030 |
| 2508 | Mips::COP0RegClassID, // COP031 |
| 2509 | Mips::COP2RegClassID, // COP210 |
| 2510 | Mips::COP2RegClassID, // COP211 |
| 2511 | Mips::COP2RegClassID, // COP212 |
| 2512 | Mips::COP2RegClassID, // COP213 |
| 2513 | Mips::COP2RegClassID, // COP214 |
| 2514 | Mips::COP2RegClassID, // COP215 |
| 2515 | Mips::COP2RegClassID, // COP216 |
| 2516 | Mips::COP2RegClassID, // COP217 |
| 2517 | Mips::COP2RegClassID, // COP218 |
| 2518 | Mips::COP2RegClassID, // COP219 |
| 2519 | Mips::COP2RegClassID, // COP220 |
| 2520 | Mips::COP2RegClassID, // COP221 |
| 2521 | Mips::COP2RegClassID, // COP222 |
| 2522 | Mips::COP2RegClassID, // COP223 |
| 2523 | Mips::COP2RegClassID, // COP224 |
| 2524 | Mips::COP2RegClassID, // COP225 |
| 2525 | Mips::COP2RegClassID, // COP226 |
| 2526 | Mips::COP2RegClassID, // COP227 |
| 2527 | Mips::COP2RegClassID, // COP228 |
| 2528 | Mips::COP2RegClassID, // COP229 |
| 2529 | Mips::COP2RegClassID, // COP230 |
| 2530 | Mips::COP2RegClassID, // COP231 |
| 2531 | Mips::COP3RegClassID, // COP310 |
| 2532 | Mips::COP3RegClassID, // COP311 |
| 2533 | Mips::COP3RegClassID, // COP312 |
| 2534 | Mips::COP3RegClassID, // COP313 |
| 2535 | Mips::COP3RegClassID, // COP314 |
| 2536 | Mips::COP3RegClassID, // COP315 |
| 2537 | Mips::COP3RegClassID, // COP316 |
| 2538 | Mips::COP3RegClassID, // COP317 |
| 2539 | Mips::COP3RegClassID, // COP318 |
| 2540 | Mips::COP3RegClassID, // COP319 |
| 2541 | Mips::COP3RegClassID, // COP320 |
| 2542 | Mips::COP3RegClassID, // COP321 |
| 2543 | Mips::COP3RegClassID, // COP322 |
| 2544 | Mips::COP3RegClassID, // COP323 |
| 2545 | Mips::COP3RegClassID, // COP324 |
| 2546 | Mips::COP3RegClassID, // COP325 |
| 2547 | Mips::COP3RegClassID, // COP326 |
| 2548 | Mips::COP3RegClassID, // COP327 |
| 2549 | Mips::COP3RegClassID, // COP328 |
| 2550 | Mips::COP3RegClassID, // COP329 |
| 2551 | Mips::COP3RegClassID, // COP330 |
| 2552 | Mips::COP3RegClassID, // COP331 |
| 2553 | Mips::AFGR64RegClassID, // D0 |
| 2554 | Mips::AFGR64RegClassID, // D1 |
| 2555 | Mips::AFGR64RegClassID, // D2 |
| 2556 | Mips::AFGR64RegClassID, // D3 |
| 2557 | Mips::AFGR64RegClassID, // D4 |
| 2558 | Mips::AFGR64RegClassID, // D5 |
| 2559 | Mips::AFGR64RegClassID, // D6 |
| 2560 | Mips::AFGR64RegClassID, // D7 |
| 2561 | Mips::AFGR64RegClassID, // D8 |
| 2562 | Mips::AFGR64RegClassID, // D9 |
| 2563 | Mips::AFGR64RegClassID, // D10 |
| 2564 | Mips::AFGR64RegClassID, // D11 |
| 2565 | Mips::AFGR64RegClassID, // D12 |
| 2566 | Mips::AFGR64RegClassID, // D13 |
| 2567 | Mips::AFGR64RegClassID, // D14 |
| 2568 | Mips::AFGR64RegClassID, // D15 |
| 2569 | InvalidRegClassID, // DSPOutFlag20 |
| 2570 | InvalidRegClassID, // DSPOutFlag21 |
| 2571 | InvalidRegClassID, // DSPOutFlag22 |
| 2572 | InvalidRegClassID, // DSPOutFlag23 |
| 2573 | Mips::FGR32CCRegClassID, // F0 |
| 2574 | Mips::FGR32CCRegClassID, // F1 |
| 2575 | Mips::FGR32CCRegClassID, // F2 |
| 2576 | Mips::FGR32CCRegClassID, // F3 |
| 2577 | Mips::FGR32CCRegClassID, // F4 |
| 2578 | Mips::FGR32CCRegClassID, // F5 |
| 2579 | Mips::FGR32CCRegClassID, // F6 |
| 2580 | Mips::FGR32CCRegClassID, // F7 |
| 2581 | Mips::FGR32CCRegClassID, // F8 |
| 2582 | Mips::FGR32CCRegClassID, // F9 |
| 2583 | Mips::FGR32CCRegClassID, // F10 |
| 2584 | Mips::FGR32CCRegClassID, // F11 |
| 2585 | Mips::FGR32CCRegClassID, // F12 |
| 2586 | Mips::FGR32CCRegClassID, // F13 |
| 2587 | Mips::FGR32CCRegClassID, // F14 |
| 2588 | Mips::FGR32CCRegClassID, // F15 |
| 2589 | Mips::FGR32CCRegClassID, // F16 |
| 2590 | Mips::FGR32CCRegClassID, // F17 |
| 2591 | Mips::FGR32CCRegClassID, // F18 |
| 2592 | Mips::FGR32CCRegClassID, // F19 |
| 2593 | Mips::FGR32CCRegClassID, // F20 |
| 2594 | Mips::FGR32CCRegClassID, // F21 |
| 2595 | Mips::FGR32CCRegClassID, // F22 |
| 2596 | Mips::FGR32CCRegClassID, // F23 |
| 2597 | Mips::FGR32CCRegClassID, // F24 |
| 2598 | Mips::FGR32CCRegClassID, // F25 |
| 2599 | Mips::FGR32CCRegClassID, // F26 |
| 2600 | Mips::FGR32CCRegClassID, // F27 |
| 2601 | Mips::FGR32CCRegClassID, // F28 |
| 2602 | Mips::FGR32CCRegClassID, // F29 |
| 2603 | Mips::FGR32CCRegClassID, // F30 |
| 2604 | Mips::FGR32CCRegClassID, // F31 |
| 2605 | Mips::FCCRegClassID, // FCC0 |
| 2606 | Mips::FCCRegClassID, // FCC1 |
| 2607 | Mips::FCCRegClassID, // FCC2 |
| 2608 | Mips::FCCRegClassID, // FCC3 |
| 2609 | Mips::FCCRegClassID, // FCC4 |
| 2610 | Mips::FCCRegClassID, // FCC5 |
| 2611 | Mips::FCCRegClassID, // FCC6 |
| 2612 | Mips::FCCRegClassID, // FCC7 |
| 2613 | Mips::CCRRegClassID, // FCR0 |
| 2614 | Mips::CCRRegClassID, // FCR1 |
| 2615 | Mips::CCRRegClassID, // FCR2 |
| 2616 | Mips::CCRRegClassID, // FCR3 |
| 2617 | Mips::CCRRegClassID, // FCR4 |
| 2618 | Mips::CCRRegClassID, // FCR5 |
| 2619 | Mips::CCRRegClassID, // FCR6 |
| 2620 | Mips::CCRRegClassID, // FCR7 |
| 2621 | Mips::CCRRegClassID, // FCR8 |
| 2622 | Mips::CCRRegClassID, // FCR9 |
| 2623 | Mips::CCRRegClassID, // FCR10 |
| 2624 | Mips::CCRRegClassID, // FCR11 |
| 2625 | Mips::CCRRegClassID, // FCR12 |
| 2626 | Mips::CCRRegClassID, // FCR13 |
| 2627 | Mips::CCRRegClassID, // FCR14 |
| 2628 | Mips::CCRRegClassID, // FCR15 |
| 2629 | Mips::CCRRegClassID, // FCR16 |
| 2630 | Mips::CCRRegClassID, // FCR17 |
| 2631 | Mips::CCRRegClassID, // FCR18 |
| 2632 | Mips::CCRRegClassID, // FCR19 |
| 2633 | Mips::CCRRegClassID, // FCR20 |
| 2634 | Mips::CCRRegClassID, // FCR21 |
| 2635 | Mips::CCRRegClassID, // FCR22 |
| 2636 | Mips::CCRRegClassID, // FCR23 |
| 2637 | Mips::CCRRegClassID, // FCR24 |
| 2638 | Mips::CCRRegClassID, // FCR25 |
| 2639 | Mips::CCRRegClassID, // FCR26 |
| 2640 | Mips::CCRRegClassID, // FCR27 |
| 2641 | Mips::CCRRegClassID, // FCR28 |
| 2642 | Mips::CCRRegClassID, // FCR29 |
| 2643 | Mips::CCRRegClassID, // FCR30 |
| 2644 | Mips::CCRRegClassID, // FCR31 |
| 2645 | Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // FP_64 |
| 2646 | InvalidRegClassID, // F_HI0 |
| 2647 | InvalidRegClassID, // F_HI1 |
| 2648 | InvalidRegClassID, // F_HI2 |
| 2649 | InvalidRegClassID, // F_HI3 |
| 2650 | InvalidRegClassID, // F_HI4 |
| 2651 | InvalidRegClassID, // F_HI5 |
| 2652 | InvalidRegClassID, // F_HI6 |
| 2653 | InvalidRegClassID, // F_HI7 |
| 2654 | InvalidRegClassID, // F_HI8 |
| 2655 | InvalidRegClassID, // F_HI9 |
| 2656 | InvalidRegClassID, // F_HI10 |
| 2657 | InvalidRegClassID, // F_HI11 |
| 2658 | InvalidRegClassID, // F_HI12 |
| 2659 | InvalidRegClassID, // F_HI13 |
| 2660 | InvalidRegClassID, // F_HI14 |
| 2661 | InvalidRegClassID, // F_HI15 |
| 2662 | InvalidRegClassID, // F_HI16 |
| 2663 | InvalidRegClassID, // F_HI17 |
| 2664 | InvalidRegClassID, // F_HI18 |
| 2665 | InvalidRegClassID, // F_HI19 |
| 2666 | InvalidRegClassID, // F_HI20 |
| 2667 | InvalidRegClassID, // F_HI21 |
| 2668 | InvalidRegClassID, // F_HI22 |
| 2669 | InvalidRegClassID, // F_HI23 |
| 2670 | InvalidRegClassID, // F_HI24 |
| 2671 | InvalidRegClassID, // F_HI25 |
| 2672 | InvalidRegClassID, // F_HI26 |
| 2673 | InvalidRegClassID, // F_HI27 |
| 2674 | InvalidRegClassID, // F_HI28 |
| 2675 | InvalidRegClassID, // F_HI29 |
| 2676 | InvalidRegClassID, // F_HI30 |
| 2677 | InvalidRegClassID, // F_HI31 |
| 2678 | Mips::GP64RegClassID, // GP_64 |
| 2679 | Mips::HI32RegClassID, // HI0 |
| 2680 | Mips::HI32DSPRegClassID, // HI1 |
| 2681 | Mips::HI32DSPRegClassID, // HI2 |
| 2682 | Mips::HI32DSPRegClassID, // HI3 |
| 2683 | Mips::HWRegsRegClassID, // HWR0 |
| 2684 | Mips::HWRegsRegClassID, // HWR1 |
| 2685 | Mips::HWRegsRegClassID, // HWR2 |
| 2686 | Mips::HWRegsRegClassID, // HWR3 |
| 2687 | Mips::HWRegsRegClassID, // HWR4 |
| 2688 | Mips::HWRegsRegClassID, // HWR5 |
| 2689 | Mips::HWRegsRegClassID, // HWR6 |
| 2690 | Mips::HWRegsRegClassID, // HWR7 |
| 2691 | Mips::HWRegsRegClassID, // HWR8 |
| 2692 | Mips::HWRegsRegClassID, // HWR9 |
| 2693 | Mips::HWRegsRegClassID, // HWR10 |
| 2694 | Mips::HWRegsRegClassID, // HWR11 |
| 2695 | Mips::HWRegsRegClassID, // HWR12 |
| 2696 | Mips::HWRegsRegClassID, // HWR13 |
| 2697 | Mips::HWRegsRegClassID, // HWR14 |
| 2698 | Mips::HWRegsRegClassID, // HWR15 |
| 2699 | Mips::HWRegsRegClassID, // HWR16 |
| 2700 | Mips::HWRegsRegClassID, // HWR17 |
| 2701 | Mips::HWRegsRegClassID, // HWR18 |
| 2702 | Mips::HWRegsRegClassID, // HWR19 |
| 2703 | Mips::HWRegsRegClassID, // HWR20 |
| 2704 | Mips::HWRegsRegClassID, // HWR21 |
| 2705 | Mips::HWRegsRegClassID, // HWR22 |
| 2706 | Mips::HWRegsRegClassID, // HWR23 |
| 2707 | Mips::HWRegsRegClassID, // HWR24 |
| 2708 | Mips::HWRegsRegClassID, // HWR25 |
| 2709 | Mips::HWRegsRegClassID, // HWR26 |
| 2710 | Mips::HWRegsRegClassID, // HWR27 |
| 2711 | Mips::HWRegsRegClassID, // HWR28 |
| 2712 | Mips::HWRegsRegClassID, // HWR29 |
| 2713 | Mips::HWRegsRegClassID, // HWR30 |
| 2714 | Mips::HWRegsRegClassID, // HWR31 |
| 2715 | Mips::GPR32NONZERORegClassID, // K0 |
| 2716 | Mips::GPR32NONZERORegClassID, // K1 |
| 2717 | Mips::LO32RegClassID, // LO0 |
| 2718 | Mips::LO32DSPRegClassID, // LO1 |
| 2719 | Mips::LO32DSPRegClassID, // LO2 |
| 2720 | Mips::LO32DSPRegClassID, // LO3 |
| 2721 | Mips::OCTEON_MPLRegClassID, // MPL0 |
| 2722 | Mips::OCTEON_MPLRegClassID, // MPL1 |
| 2723 | Mips::OCTEON_MPLRegClassID, // MPL2 |
| 2724 | Mips::MSACtrlRegClassID, // MSA8 |
| 2725 | Mips::MSACtrlRegClassID, // MSA9 |
| 2726 | Mips::MSACtrlRegClassID, // MSA10 |
| 2727 | Mips::MSACtrlRegClassID, // MSA11 |
| 2728 | Mips::MSACtrlRegClassID, // MSA12 |
| 2729 | Mips::MSACtrlRegClassID, // MSA13 |
| 2730 | Mips::MSACtrlRegClassID, // MSA14 |
| 2731 | Mips::MSACtrlRegClassID, // MSA15 |
| 2732 | Mips::MSACtrlRegClassID, // MSA16 |
| 2733 | Mips::MSACtrlRegClassID, // MSA17 |
| 2734 | Mips::MSACtrlRegClassID, // MSA18 |
| 2735 | Mips::MSACtrlRegClassID, // MSA19 |
| 2736 | Mips::MSACtrlRegClassID, // MSA20 |
| 2737 | Mips::MSACtrlRegClassID, // MSA21 |
| 2738 | Mips::MSACtrlRegClassID, // MSA22 |
| 2739 | Mips::MSACtrlRegClassID, // MSA23 |
| 2740 | Mips::MSACtrlRegClassID, // MSA24 |
| 2741 | Mips::MSACtrlRegClassID, // MSA25 |
| 2742 | Mips::MSACtrlRegClassID, // MSA26 |
| 2743 | Mips::MSACtrlRegClassID, // MSA27 |
| 2744 | Mips::MSACtrlRegClassID, // MSA28 |
| 2745 | Mips::MSACtrlRegClassID, // MSA29 |
| 2746 | Mips::MSACtrlRegClassID, // MSA30 |
| 2747 | Mips::MSACtrlRegClassID, // MSA31 |
| 2748 | Mips::OCTEON_PRegClassID, // P0 |
| 2749 | Mips::OCTEON_PRegClassID, // P1 |
| 2750 | Mips::OCTEON_PRegClassID, // P2 |
| 2751 | Mips::GPR64_with_sub_32_in_CPURARegRegClassID, // RA_64 |
| 2752 | Mips::CPU16Regs_and_GPRMM16MovePRegClassID, // S0 |
| 2753 | Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, // S1 |
| 2754 | Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, // S2 |
| 2755 | Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, // S3 |
| 2756 | Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, // S4 |
| 2757 | Mips::GPRMM16MovePPairSecondRegClassID, // S5 |
| 2758 | Mips::GPRMM16MovePPairSecondRegClassID, // S6 |
| 2759 | Mips::GPR32NONZERORegClassID, // S7 |
| 2760 | Mips::SP64RegClassID, // SP_64 |
| 2761 | Mips::GPR32NONZERORegClassID, // T0 |
| 2762 | Mips::GPR32NONZERORegClassID, // T1 |
| 2763 | Mips::GPR32NONZERORegClassID, // T2 |
| 2764 | Mips::GPR32NONZERORegClassID, // T3 |
| 2765 | Mips::GPR32NONZERORegClassID, // T4 |
| 2766 | Mips::GPR32NONZERORegClassID, // T5 |
| 2767 | Mips::GPR32NONZERORegClassID, // T6 |
| 2768 | Mips::GPR32NONZERORegClassID, // T7 |
| 2769 | Mips::GPR32NONZERORegClassID, // T8 |
| 2770 | Mips::GPR32NONZERORegClassID, // T9 |
| 2771 | Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, // V0 |
| 2772 | Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, // V1 |
| 2773 | Mips::MSA128WEvensRegClassID, // W0 |
| 2774 | Mips::MSA128WRegClassID, // W1 |
| 2775 | Mips::MSA128WEvensRegClassID, // W2 |
| 2776 | Mips::MSA128WRegClassID, // W3 |
| 2777 | Mips::MSA128WEvensRegClassID, // W4 |
| 2778 | Mips::MSA128WRegClassID, // W5 |
| 2779 | Mips::MSA128WEvensRegClassID, // W6 |
| 2780 | Mips::MSA128WRegClassID, // W7 |
| 2781 | Mips::MSA128WEvensRegClassID, // W8 |
| 2782 | Mips::MSA128WRegClassID, // W9 |
| 2783 | Mips::MSA128WEvensRegClassID, // W10 |
| 2784 | Mips::MSA128WRegClassID, // W11 |
| 2785 | Mips::MSA128WEvensRegClassID, // W12 |
| 2786 | Mips::MSA128WRegClassID, // W13 |
| 2787 | Mips::MSA128WEvensRegClassID, // W14 |
| 2788 | Mips::MSA128WRegClassID, // W15 |
| 2789 | Mips::MSA128WEvensRegClassID, // W16 |
| 2790 | Mips::MSA128WRegClassID, // W17 |
| 2791 | Mips::MSA128WEvensRegClassID, // W18 |
| 2792 | Mips::MSA128WRegClassID, // W19 |
| 2793 | Mips::MSA128WEvensRegClassID, // W20 |
| 2794 | Mips::MSA128WRegClassID, // W21 |
| 2795 | Mips::MSA128WEvensRegClassID, // W22 |
| 2796 | Mips::MSA128WRegClassID, // W23 |
| 2797 | Mips::MSA128WEvensRegClassID, // W24 |
| 2798 | Mips::MSA128WRegClassID, // W25 |
| 2799 | Mips::MSA128WEvensRegClassID, // W26 |
| 2800 | Mips::MSA128WRegClassID, // W27 |
| 2801 | Mips::MSA128WEvensRegClassID, // W28 |
| 2802 | Mips::MSA128WRegClassID, // W29 |
| 2803 | Mips::MSA128WEvensRegClassID, // W30 |
| 2804 | Mips::MSA128WRegClassID, // W31 |
| 2805 | Mips::GPR64_with_sub_32_in_GPR32ZERORegClassID, // ZERO_64 |
| 2806 | Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID, // A0_64 |
| 2807 | Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, // A1_64 |
| 2808 | Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, // A2_64 |
| 2809 | Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, // A3_64 |
| 2810 | Mips::ACC128RegClassID, // AC0_64 |
| 2811 | Mips::FGR64RegClassID, // D0_64 |
| 2812 | Mips::FGR64RegClassID, // D1_64 |
| 2813 | Mips::FGR64RegClassID, // D2_64 |
| 2814 | Mips::FGR64RegClassID, // D3_64 |
| 2815 | Mips::FGR64RegClassID, // D4_64 |
| 2816 | Mips::FGR64RegClassID, // D5_64 |
| 2817 | Mips::FGR64RegClassID, // D6_64 |
| 2818 | Mips::FGR64RegClassID, // D7_64 |
| 2819 | Mips::FGR64RegClassID, // D8_64 |
| 2820 | Mips::FGR64RegClassID, // D9_64 |
| 2821 | Mips::FGR64RegClassID, // D10_64 |
| 2822 | Mips::FGR64RegClassID, // D11_64 |
| 2823 | Mips::FGR64RegClassID, // D12_64 |
| 2824 | Mips::FGR64RegClassID, // D13_64 |
| 2825 | Mips::FGR64RegClassID, // D14_64 |
| 2826 | Mips::FGR64RegClassID, // D15_64 |
| 2827 | Mips::FGR64RegClassID, // D16_64 |
| 2828 | Mips::FGR64RegClassID, // D17_64 |
| 2829 | Mips::FGR64RegClassID, // D18_64 |
| 2830 | Mips::FGR64RegClassID, // D19_64 |
| 2831 | Mips::FGR64RegClassID, // D20_64 |
| 2832 | Mips::FGR64RegClassID, // D21_64 |
| 2833 | Mips::FGR64RegClassID, // D22_64 |
| 2834 | Mips::FGR64RegClassID, // D23_64 |
| 2835 | Mips::FGR64RegClassID, // D24_64 |
| 2836 | Mips::FGR64RegClassID, // D25_64 |
| 2837 | Mips::FGR64RegClassID, // D26_64 |
| 2838 | Mips::FGR64RegClassID, // D27_64 |
| 2839 | Mips::FGR64RegClassID, // D28_64 |
| 2840 | Mips::FGR64RegClassID, // D29_64 |
| 2841 | Mips::FGR64RegClassID, // D30_64 |
| 2842 | Mips::FGR64RegClassID, // D31_64 |
| 2843 | InvalidRegClassID, // DSPOutFlag16_19 |
| 2844 | Mips::HI64RegClassID, // HI0_64 |
| 2845 | Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // K0_64 |
| 2846 | Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // K1_64 |
| 2847 | Mips::LO64RegClassID, // LO0_64 |
| 2848 | Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, // S0_64 |
| 2849 | Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, // S1_64 |
| 2850 | Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, // S2_64 |
| 2851 | Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, // S3_64 |
| 2852 | Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, // S4_64 |
| 2853 | Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID, // S5_64 |
| 2854 | Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID, // S6_64 |
| 2855 | Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // S7_64 |
| 2856 | Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // T0_64 |
| 2857 | Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // T1_64 |
| 2858 | Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // T2_64 |
| 2859 | Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // T3_64 |
| 2860 | Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // T4_64 |
| 2861 | Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // T5_64 |
| 2862 | Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // T6_64 |
| 2863 | Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // T7_64 |
| 2864 | Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // T8_64 |
| 2865 | Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // T9_64 |
| 2866 | Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, // V0_64 |
| 2867 | Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, // V1_64 |
| 2868 | }; |
| 2869 | |
| 2870 | assert(Reg < ArrayRef(Mapping).size()); |
| 2871 | unsigned RCID = Mapping[Reg.id()]; |
| 2872 | if (RCID == InvalidRegClassID) |
| 2873 | return nullptr; |
| 2874 | return &MipsMCRegisterClassStorage.Classes[RCID]; |
| 2875 | } |
| 2876 | extern const MCRegisterDesc MipsRegDesc[]; |
| 2877 | extern const int16_t MipsRegDiffLists[]; |
| 2878 | extern const LaneBitmask MipsLaneMaskLists[]; |
| 2879 | extern const char MipsRegStrings[]; |
| 2880 | extern const char MipsRegClassStrings[]; |
| 2881 | extern const MCPhysReg MipsRegUnitRoots[][2]; |
| 2882 | extern const uint16_t MipsSubRegIdxLists[]; |
| 2883 | extern const uint16_t MipsRegEncodingTable[]; |
| 2884 | // Mips Dwarf<->LLVM register mappings. |
| 2885 | extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[]; |
| 2886 | extern const unsigned MipsDwarfFlavour0Dwarf2LSize; |
| 2887 | |
| 2888 | extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[]; |
| 2889 | extern const unsigned MipsEHFlavour0Dwarf2LSize; |
| 2890 | |
| 2891 | extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[]; |
| 2892 | extern const unsigned MipsDwarfFlavour0L2DwarfSize; |
| 2893 | |
| 2894 | extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[]; |
| 2895 | extern const unsigned MipsEHFlavour0L2DwarfSize; |
| 2896 | |
| 2897 | |
| 2898 | MipsGenRegisterInfo:: |
| 2899 | MipsGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, |
| 2900 | unsigned PC, unsigned HwMode) |
| 2901 | : TargetRegisterInfo(&MipsRegInfoDesc, |
| 2902 | MipsSubRegIndexStrings, MipsSubRegIndexNameOffsets, |
| 2903 | MipsSubRegIdxRangeTable, MipsSubRegIndexLaneMaskTable, |
| 2904 | |
| 2905 | LaneBitmask(0xFFFFFFFFFFFFFF80), MipsRegClassInfos, MipsVTLists, HwMode) { |
| 2906 | InitMCRegisterInfo(D: MipsRegDesc, NR: 442, RA, PC, |
| 2907 | C: &getMipsMCRegisterClass(RC: 0), NC: 70, RURoots: MipsRegUnitRoots, NRU: 321, DL: MipsRegDiffLists, |
| 2908 | RUMS: MipsLaneMaskLists, Strings: MipsRegStrings, ClassStrings: MipsRegClassStrings, SubIndices: MipsSubRegIdxLists, NumIndices: 12, |
| 2909 | RET: MipsRegEncodingTable, RUI: nullptr); |
| 2910 | |
| 2911 | switch (DwarfFlavour) { |
| 2912 | default: |
| 2913 | llvm_unreachable("Unknown DWARF flavour"); |
| 2914 | case 0: |
| 2915 | mapDwarfRegsToLLVMRegs(Map: MipsDwarfFlavour0Dwarf2L, Size: MipsDwarfFlavour0Dwarf2LSize, isEH: false); |
| 2916 | break; |
| 2917 | } |
| 2918 | switch (EHFlavour) { |
| 2919 | default: |
| 2920 | llvm_unreachable("Unknown DWARF flavour"); |
| 2921 | case 0: |
| 2922 | mapDwarfRegsToLLVMRegs(Map: MipsEHFlavour0Dwarf2L, Size: MipsEHFlavour0Dwarf2LSize, isEH: true); |
| 2923 | break; |
| 2924 | } |
| 2925 | switch (DwarfFlavour) { |
| 2926 | default: |
| 2927 | llvm_unreachable("Unknown DWARF flavour"); |
| 2928 | case 0: |
| 2929 | mapLLVMRegsToDwarfRegs(Map: MipsDwarfFlavour0L2Dwarf, Size: MipsDwarfFlavour0L2DwarfSize, isEH: false); |
| 2930 | break; |
| 2931 | } |
| 2932 | switch (EHFlavour) { |
| 2933 | default: |
| 2934 | llvm_unreachable("Unknown DWARF flavour"); |
| 2935 | case 0: |
| 2936 | mapLLVMRegsToDwarfRegs(Map: MipsEHFlavour0L2Dwarf, Size: MipsEHFlavour0L2DwarfSize, isEH: true); |
| 2937 | break; |
| 2938 | } |
| 2939 | } |
| 2940 | |
| 2941 | static const MCPhysReg CSR_Interrupt_32_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, Mips::LO0, Mips::HI0, 0 }; |
| 2942 | static const uint32_t CSR_Interrupt_32_RegMask[] = { 0x07e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000, 0x00000008, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, }; |
| 2943 | static const MCPhysReg CSR_Interrupt_32R6_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, 0 }; |
| 2944 | static const uint32_t CSR_Interrupt_32R6_RegMask[] = { 0x03e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, }; |
| 2945 | static const MCPhysReg CSR_Interrupt_64_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::V1_64, Mips::V0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, Mips::LO0_64, Mips::HI0_64, 0 }; |
| 2946 | static const uint32_t CSR_Interrupt_64_RegMask[] = { 0x47e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x30000000, 0x00000000, 0x00000008, 0x07ffbfe0, 0xf8000000, 0x00000001, 0x03ffffe4, }; |
| 2947 | static const MCPhysReg CSR_Interrupt_64R6_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::V1_64, Mips::V0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, 0 }; |
| 2948 | static const uint32_t CSR_Interrupt_64R6_RegMask[] = { 0x43e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x07ffbfe0, 0xf8000000, 0x00000000, 0x03ffffc0, }; |
| 2949 | static const MCPhysReg CSR_Mips16RetHelper_SaveList[] = { Mips::V0, Mips::V1, Mips::FP, Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, 0 }; |
| 2950 | static const uint32_t CSR_Mips16RetHelper_RegMask[] = { 0x03e00100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06003fc0, 0x08000000, 0x00000000, 0x00000000, }; |
| 2951 | static const MCPhysReg CSR_N32_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 }; |
| 2952 | static const uint32_t CSR_N32_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x08000000, 0x15550000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xaaa00000, 0x00003fc0, }; |
| 2953 | static const MCPhysReg CSR_N32_SingleFloat_SaveList[] = { Mips::F30, Mips::F28, Mips::F26, Mips::F24, Mips::F22, Mips::F20, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 }; |
| 2954 | static const uint32_t CSR_N32_SingleFloat_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0x00000000, 0x00003fc0, }; |
| 2955 | static const MCPhysReg CSR_N64_SaveList[] = { Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64, Mips::D26_64, Mips::D25_64, Mips::D24_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 }; |
| 2956 | static const uint32_t CSR_N64_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00007800, 0x0007f800, 0x08000000, 0x1ff00000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xfe000000, 0x00003fc1, }; |
| 2957 | static const MCPhysReg CSR_N64_SingleFloat_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 }; |
| 2958 | static const uint32_t CSR_N64_SingleFloat_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00007800, 0x0007f800, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0x00000000, 0x00003fc0, }; |
| 2959 | static const MCPhysReg CSR_O32_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 }; |
| 2960 | static const uint32_t CSR_O32_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, }; |
| 2961 | static const MCPhysReg CSR_O32_FP64_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 }; |
| 2962 | static const uint32_t CSR_O32_FP64_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x00000000, 0x05550000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0xaaa00000, 0x00000000, }; |
| 2963 | static const MCPhysReg CSR_O32_FPXX_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 }; |
| 2964 | static const uint32_t CSR_O32_FPXX_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, }; |
| 2965 | static const MCPhysReg CSR_O32_SingleFloat_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 }; |
| 2966 | static const uint32_t CSR_O32_SingleFloat_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, }; |
| 2967 | |
| 2968 | |
| 2969 | ArrayRef<const uint32_t *> MipsGenRegisterInfo::getRegMasks() const { |
| 2970 | static const uint32_t *const Masks[] = { |
| 2971 | CSR_Interrupt_32_RegMask, |
| 2972 | CSR_Interrupt_32R6_RegMask, |
| 2973 | CSR_Interrupt_64_RegMask, |
| 2974 | CSR_Interrupt_64R6_RegMask, |
| 2975 | CSR_Mips16RetHelper_RegMask, |
| 2976 | CSR_N32_RegMask, |
| 2977 | CSR_N32_SingleFloat_RegMask, |
| 2978 | CSR_N64_RegMask, |
| 2979 | CSR_N64_SingleFloat_RegMask, |
| 2980 | CSR_O32_RegMask, |
| 2981 | CSR_O32_FP64_RegMask, |
| 2982 | CSR_O32_FPXX_RegMask, |
| 2983 | CSR_O32_SingleFloat_RegMask, |
| 2984 | }; |
| 2985 | return ArrayRef(Masks); |
| 2986 | } |
| 2987 | |
| 2988 | bool MipsGenRegisterInfo:: |
| 2989 | isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const { |
| 2990 | return |
| 2991 | false; |
| 2992 | } |
| 2993 | |
| 2994 | bool MipsGenRegisterInfo:: |
| 2995 | isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const { |
| 2996 | return |
| 2997 | false; |
| 2998 | } |
| 2999 | |
| 3000 | bool MipsGenRegisterInfo:: |
| 3001 | isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const { |
| 3002 | return |
| 3003 | false; |
| 3004 | } |
| 3005 | |
| 3006 | bool MipsGenRegisterInfo:: |
| 3007 | isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const { |
| 3008 | return |
| 3009 | false; |
| 3010 | } |
| 3011 | |
| 3012 | bool MipsGenRegisterInfo:: |
| 3013 | isConstantPhysReg(MCRegister PhysReg) const { |
| 3014 | return |
| 3015 | PhysReg == Mips::ZERO || |
| 3016 | PhysReg == Mips::ZERO_64 || |
| 3017 | false; |
| 3018 | } |
| 3019 | |
| 3020 | ArrayRef<const char *> MipsGenRegisterInfo::getRegMaskNames() const { |
| 3021 | static const char *Names[] = { |
| 3022 | "CSR_Interrupt_32", |
| 3023 | "CSR_Interrupt_32R6", |
| 3024 | "CSR_Interrupt_64", |
| 3025 | "CSR_Interrupt_64R6", |
| 3026 | "CSR_Mips16RetHelper", |
| 3027 | "CSR_N32", |
| 3028 | "CSR_N32_SingleFloat", |
| 3029 | "CSR_N64", |
| 3030 | "CSR_N64_SingleFloat", |
| 3031 | "CSR_O32", |
| 3032 | "CSR_O32_FP64", |
| 3033 | "CSR_O32_FPXX", |
| 3034 | "CSR_O32_SingleFloat", |
| 3035 | }; |
| 3036 | return ArrayRef(Names); |
| 3037 | } |
| 3038 | |
| 3039 | const MipsFrameLowering * |
| 3040 | MipsGenRegisterInfo::getFrameLowering(const MachineFunction &MF) { |
| 3041 | return static_cast<const MipsFrameLowering *>( |
| 3042 | MF.getSubtarget().getFrameLowering()); |
| 3043 | } |
| 3044 | |
| 3045 | |
| 3046 | } // namespace llvm |
| 3047 |
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