MipsGenRegisterInfoTargetDesc.inc source code [llvm_projects/build/lib/Target/Mips/MipsGenRegisterInfoTargetDesc.inc]

1	/===- TableGen'erated file -------------------------------------- C++ --===\
2	\| \|
3	\| Target Register and Register Classes Information \|
4	\| \|
5	\| Automatically generated file, do not edit! \|
6	\| \|
7	\===----------------------------------------------------------------------===/
8
9	namespace llvm {
10
11	extern const MCRegisterClassStorage<`68`, `766`, `205`, `321`, `18`, `194`> MipsMCRegisterClassStorage;
12
13	static const MVT::SimpleValueType MipsVTLists[] = {
14	/ 0 / MVT::v4i8, MVT::v2i16, MVT::i32, MVT::Other,
15	/ 4 / MVT::i64, MVT::Other,
16	/ 6 / MVT::f32, MVT::Other,
17	/ 8 / MVT::f64, MVT::Other,
18	/ 10 / MVT::v16i8, MVT::Other,
19	/ 12 / MVT::v4i8, MVT::v2i16, MVT::Other,
20	/ 15 / MVT::v8i16, MVT::v8f16, MVT::Other,
21	/ 18 / MVT::v4i32, MVT::v4f32, MVT::Other,
22	/ 21 / MVT::v2i64, MVT::v2f64, MVT::Other,
23	/ 24 / MVT::Untyped, MVT::Other,
24	};
25
26	#ifdef __GNUC__
27	#pragma GCC diagnostic push
28	#pragma GCC diagnostic ignored "-Woverlength-strings"
29	#endif
30	static constexpr char MipsSubRegIndexStrings[] = {
31	/ 0 / "sub_dsp20\000"
32	/ 10 / "sub_dsp21\000"
33	/ 20 / "sub_dsp22\000"
34	/ 30 / "sub_32_sub_hi_then_sub_32\000"
35	/ 56 / "sub_dsp23\000"
36	/ 66 / "sub_64\000"
37	/ 73 / "sub_dsp16_19\000"
38	/ 86 / "sub_hi\000"
39	/ 93 / "sub_lo\000"
40	};
41	#ifdef __GNUC__
42	#pragma GCC diagnostic pop
43	#endif
44
45
46	static constexpr uint32_t MipsSubRegIndexNameOffsets[] = {
47	`49`,
48	`66`,
49	`73`,
50	`0`,
51	`10`,
52	`20`,
53	`56`,
54	`86`,
55	`93`,
56	`37`,
57	`30`,
58	};
59
60	static const TargetRegisterInfo::SubRegCoveredBits MipsSubRegIdxRangeTable[] = {
61	{ .Offset: `4294967295`, .Size: `4294967295` },
62	{ .Offset: `0`, .Size: `32` }, // sub_32
63	{ .Offset: `0`, .Size: `64` }, // sub_64
64	{ .Offset: `16`, .Size: `4` }, // sub_dsp16_19
65	{ .Offset: `20`, .Size: `1` }, // sub_dsp20
66	{ .Offset: `21`, .Size: `1` }, // sub_dsp21
67	{ .Offset: `22`, .Size: `1` }, // sub_dsp22
68	{ .Offset: `23`, .Size: `1` }, // sub_dsp23
69	{ .Offset: `32`, .Size: `32` }, // sub_hi
70	{ .Offset: `0`, .Size: `32` }, // sub_lo
71	{ .Offset: `32`, .Size: `32` }, // sub_hi_then_sub_32
72	{ .Offset: `0`, .Size: `64` }, // sub_32_sub_hi_then_sub_32
73	{ .Offset: `4294967295`, .Size: `4294967295` },
74	{ .Offset: `0`, .Size: `32` }, // sub_32
75	{ .Offset: `0`, .Size: `64` }, // sub_64
76	{ .Offset: `16`, .Size: `4` }, // sub_dsp16_19
77	{ .Offset: `20`, .Size: `1` }, // sub_dsp20
78	{ .Offset: `21`, .Size: `1` }, // sub_dsp21
79	{ .Offset: `22`, .Size: `1` }, // sub_dsp22
80	{ .Offset: `23`, .Size: `1` }, // sub_dsp23
81	{ .Offset: `32`, .Size: `32` }, // sub_hi
82	{ .Offset: `0`, .Size: `32` }, // sub_lo
83	{ .Offset: `32`, .Size: `32` }, // sub_hi_then_sub_32
84	{ .Offset: `0`, .Size: `64` }, // sub_32_sub_hi_then_sub_32
85	};
86
87
88	static const LaneBitmask MipsSubRegIndexLaneMaskTable[] = {
89	LaneBitmask::getAll(),
90	LaneBitmask (`0x0000000000000001`), // sub_32
91	LaneBitmask (`0x0000000000000041`), // sub_64
92	LaneBitmask (`0x0000000000000002`), // sub_dsp16_19
93	LaneBitmask (`0x0000000000000004`), // sub_dsp20
94	LaneBitmask (`0x0000000000000008`), // sub_dsp21
95	LaneBitmask (`0x0000000000000010`), // sub_dsp22
96	LaneBitmask (`0x0000000000000020`), // sub_dsp23
97	LaneBitmask (`0x0000000000000040`), // sub_hi
98	LaneBitmask (`0x0000000000000001`), // sub_lo
99	LaneBitmask (`0x0000000000000040`), // sub_hi_then_sub_32
100	LaneBitmask (`0x0000000000000041`), // sub_32_sub_hi_then_sub_32
101	};
102
103
104
105	static const TargetRegisterInfo::RegClassInfo MipsRegClassInfos[] = {
106	// Mode = 0 (DefaultMode)
107	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // CCR
108	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // COP0
109	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // COP2
110	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // COP3
111	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `0` }, // DSPR
112	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `6` }, // FGR32
113	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPR32
114	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // HWRegs
115	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // MSACtrl
116	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPR32NONZERO
117	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // CPU16RegsPlusSP
118	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // CPU16Regs
119	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // FCC
120	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPRMM16
121	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPRMM16MoveP
122	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPRMM16Zero
123	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // CPU16Regs_and_GPRMM16Zero
124	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPR32NONZERO_and_GPRMM16MoveP
125	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPRMM16MovePPairSecond
126	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // CPU16Regs_and_GPRMM16MoveP
127	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPRMM16MoveP_and_GPRMM16Zero
128	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // HI32DSP
129	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // LO32DSP
130	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // CPU16Regs_and_GPRMM16MovePPairSecond
131	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPRMM16MovePPairFirst
132	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
133	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
134	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // CPURAReg
135	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // CPUSPReg
136	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `12` }, // DSPCC
137	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GP32
138	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPR32ZERO
139	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // HI32
140	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // LO32
141	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // SP32
142	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `8` }, // FGR64
143	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64
144	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPR32NONZERO
145	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `8` }, // AFGR64
146	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPU16RegsPlusSP
147	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPU16Regs
148	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MoveP
149	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16Zero
150	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
151	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
152	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
153	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `24` }, // ACC64DSP
154	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
155	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
156	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
157	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
158	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
159	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // OCTEON_MPL
160	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // OCTEON_P
161	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
162	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `24` }, // ACC64
163	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GP64
164	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPURAReg
165	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPR32ZERO
166	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // HI64
167	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // LO64
168	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // SP64
169	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /MipsVTLists+/.VTListOffset: `10` }, // MSA128B
170	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /MipsVTLists+/.VTListOffset: `21` }, // MSA128D
171	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /MipsVTLists+/.VTListOffset: `15` }, // MSA128H
172	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /MipsVTLists+/.VTListOffset: `18` }, // MSA128W
173	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /MipsVTLists+/.VTListOffset: `18` }, // MSA128WEvens
174	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /MipsVTLists+/.VTListOffset: `24` }, // ACC128
175	// Mode = 1 (MIPS64)
176	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // CCR
177	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // COP0
178	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // COP2
179	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // COP3
180	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `0` }, // DSPR
181	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `6` }, // FGR32
182	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPR32
183	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // HWRegs
184	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // MSACtrl
185	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPR32NONZERO
186	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // CPU16RegsPlusSP
187	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // CPU16Regs
188	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // FCC
189	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPRMM16
190	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPRMM16MoveP
191	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPRMM16Zero
192	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // CPU16Regs_and_GPRMM16Zero
193	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPR32NONZERO_and_GPRMM16MoveP
194	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPRMM16MovePPairSecond
195	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // CPU16Regs_and_GPRMM16MoveP
196	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPRMM16MoveP_and_GPRMM16Zero
197	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // HI32DSP
198	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // LO32DSP
199	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // CPU16Regs_and_GPRMM16MovePPairSecond
200	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPRMM16MovePPairFirst
201	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
202	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
203	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // CPURAReg
204	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // CPUSPReg
205	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `12` }, // DSPCC
206	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GP32
207	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // GPR32ZERO
208	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // HI32
209	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // LO32
210	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /MipsVTLists+/.VTListOffset: `2` }, // SP32
211	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `8` }, // FGR64
212	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64
213	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPR32NONZERO
214	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `8` }, // AFGR64
215	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPU16RegsPlusSP
216	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPU16Regs
217	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MoveP
218	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16Zero
219	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
220	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
221	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
222	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `24` }, // ACC64DSP
223	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
224	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
225	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
226	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
227	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
228	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // OCTEON_MPL
229	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // OCTEON_P
230	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
231	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `24` }, // ACC64
232	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GP64
233	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPURAReg
234	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPR32ZERO
235	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // HI64
236	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // LO64
237	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /MipsVTLists+/.VTListOffset: `4` }, // SP64
238	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /MipsVTLists+/.VTListOffset: `10` }, // MSA128B
239	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /MipsVTLists+/.VTListOffset: `21` }, // MSA128D
240	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /MipsVTLists+/.VTListOffset: `15` }, // MSA128H
241	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /MipsVTLists+/.VTListOffset: `18` }, // MSA128W
242	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /MipsVTLists+/.VTListOffset: `18` }, // MSA128WEvens
243	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /MipsVTLists+/.VTListOffset: `24` }, // ACC128
244	};
245
246	static inline unsigned FGR32AltOrderSelect(const MachineFunction &MF, bool Rev) {
247	const auto & S = MF.getSubtarget<MipsSubtarget>();
248	return S.isABI_O32() && !S.useOddSPReg();
249	}
250
251	static ArrayRef<MCPhysReg> FGR32GetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
252	static const MCPhysReg AltOrder1[] = { Mips::F0, Mips::F2, Mips::F4, Mips::F6, Mips::F8, Mips::F10, Mips::F12, Mips::F14, Mips::F16, Mips::F18, Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30 };
253	const ArrayRef<MCPhysReg> Order[] = {
254	RC.getRegisters(),
255	ArrayRef(AltOrder1)
256	};
257	const unsigned Select = FGR32AltOrderSelect(MF, Rev);
258	assert(Select < `2`);
259	return Order[Select];
260	}
261
262	static inline unsigned FGR64AltOrderSelect(const MachineFunction &MF, bool Rev) {
263	const auto & S = MF.getSubtarget<MipsSubtarget>();
264	return S.isABI_O32() && !S.useOddSPReg();
265	}
266
267	static ArrayRef<MCPhysReg> FGR64GetRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) {
268	static const MCPhysReg AltOrder1[] = { Mips::D0_64, Mips::D2_64, Mips::D4_64, Mips::D6_64, Mips::D8_64, Mips::D10_64, Mips::D12_64, Mips::D14_64, Mips::D16_64, Mips::D18_64, Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64 };
269	const ArrayRef<MCPhysReg> Order[] = {
270	RC.getRegisters(),
271	ArrayRef(AltOrder1)
272	};
273	const unsigned Select = FGR64AltOrderSelect(MF, Rev);
274	assert(Select < `2`);
275	return Order[Select];
276	}
277
278	static const uint8_t MipsCostPerUseTable[] = {
279	`0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, };
280
281
282	static const bool MipsInAllocatableClassTable[] = {
283	false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
284
285
286	static const TargetRegisterInfoDesc MipsRegInfoDesc = { // Extra Descriptors
287	.CostPerUse: MipsCostPerUseTable, .NumCosts: `1`, .InAllocatableClass: MipsInAllocatableClassTable};
288
289	unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
290	static const uint8_t RowMap[`11`] = {
291	`0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, `0`, `1`,
292	};
293	static const uint8_t Rows[`2`][`11`] = {
294	{ Mips::sub_hi_then_sub_32, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, Mips::sub_lo, `0`, `0`, },
295	{ Mips::sub_32, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi_then_sub_32, Mips::sub_32, `0`, `0`, },
296	};
297
298	--IdxA; assert(IdxA < `11`); (void) IdxA;
299	--IdxB; assert(IdxB < `11`);
300	return Rows[RowMap[IdxA]][IdxB];
301	}
302
303	unsigned MipsGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
304	static const uint8_t Table[`11`][`11`] = {
305	{ `0`, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, `0`, },
306	{ `0`, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, `0`, },
307	{ `0`, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, `0`, },
308	{ `0`, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, `0`, },
309	{ `0`, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, `0`, },
310	{ `0`, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, `0`, },
311	{ `0`, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, `0`, },
312	{ `0`, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, `0`, },
313	{ Mips::sub_32, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, `0`, },
314	{ `0`, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, `0`, },
315	{ Mips::sub_32, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, `0`, },
316	};
317
318	--IdxA; assert(IdxA < `11`);
319	--IdxB; assert(IdxB < `11`);
320	return Table[IdxA][IdxB];
321	}
322
323	struct MaskRolOp {
324	LaneBitmask Mask;
325	uint8_t RotateLeft;
326	};
327	static const MaskRolOp LaneMaskComposeSequences[] = {
328	{ .Mask: LaneBitmask (`0xFFFFFFFFFFFFFFFF`), .RotateLeft: `0` }, { .Mask: LaneBitmask::getNone(), .RotateLeft: `0` }, // Sequence 0
329	{ .Mask: LaneBitmask (`0xFFFFFFFFFFFFFFFF`), .RotateLeft: `1` }, { .Mask: LaneBitmask::getNone(), .RotateLeft: `0` }, // Sequence 2
330	{ .Mask: LaneBitmask (`0xFFFFFFFFFFFFFFFF`), .RotateLeft: `2` }, { .Mask: LaneBitmask::getNone(), .RotateLeft: `0` }, // Sequence 4
331	{ .Mask: LaneBitmask (`0xFFFFFFFFFFFFFFFF`), .RotateLeft: `3` }, { .Mask: LaneBitmask::getNone(), .RotateLeft: `0` }, // Sequence 6
332	{ .Mask: LaneBitmask (`0xFFFFFFFFFFFFFFFF`), .RotateLeft: `4` }, { .Mask: LaneBitmask::getNone(), .RotateLeft: `0` }, // Sequence 8
333	{ .Mask: LaneBitmask (`0xFFFFFFFFFFFFFFFF`), .RotateLeft: `5` }, { .Mask: LaneBitmask::getNone(), .RotateLeft: `0` }, // Sequence 10
334	{ .Mask: LaneBitmask (`0xFFFFFFFFFFFFFFFF`), .RotateLeft: `6` }, { .Mask: LaneBitmask::getNone(), .RotateLeft: `0` } // Sequence 12
335	};
336	static const uint8_t CompositeSequences[] = {
337	`0`, // to sub_32
338	`0`, // to sub_64
339	`2`, // to sub_dsp16_19
340	`4`, // to sub_dsp20
341	`6`, // to sub_dsp21
342	`8`, // to sub_dsp22
343	`10`, // to sub_dsp23
344	`12`, // to sub_hi
345	`0`, // to sub_lo
346	`12`, // to sub_hi_then_sub_32
347	`0` // to sub_32_sub_hi_then_sub_32
348	};
349
350	LaneBitmask MipsGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
351	--IdxA; assert(IdxA < `11` && "Subregister index out of bounds");
352	LaneBitmask Result;
353	for (const MaskRolOp *Ops =
354	&LaneMaskComposeSequences[CompositeSequences[IdxA]];
355	Ops->Mask.any(); ++Ops) {
356	LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
357	if (unsigned S = Ops->RotateLeft)
358	Result \|= LaneBitmask ((M << S) \| (M >> (LaneBitmask::BitWidth - S)));
359	else
360	Result \|= LaneBitmask (M);
361	}
362	return Result;
363	}
364
365	LaneBitmask MipsGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
366	LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
367	--IdxA; assert(IdxA < `11` && "Subregister index out of bounds");
368	LaneBitmask Result;
369	for (const MaskRolOp *Ops =
370	&LaneMaskComposeSequences[CompositeSequences[IdxA]];
371	Ops->Mask.any(); ++Ops) {
372	LaneBitmask::Type M = LaneMask.getAsInteger();
373	if (unsigned S = Ops->RotateLeft)
374	Result \|= LaneBitmask ((M >> S) \| (M << (LaneBitmask::BitWidth - S)));
375	else
376	Result \|= LaneBitmask (M);
377	}
378	return Result;
379	}
380
381	const TargetRegisterClass MipsGenRegisterInfo::getSubClassWithSubReg(const* TargetRegisterClass RC, unsigned* Idx) const {
382	static constexpr uint8_t Table[`68`][`11`] = {
383	{ // CCR
384	`0`, // sub_32
385	`0`, // sub_64
386	`0`, // sub_dsp16_19
387	`0`, // sub_dsp20
388	`0`, // sub_dsp21
389	`0`, // sub_dsp22
390	`0`, // sub_dsp23
391	`0`, // sub_hi
392	`0`, // sub_lo
393	`0`, // sub_hi_then_sub_32
394	`0`, // sub_32_sub_hi_then_sub_32
395	},
396	{ // COP0
397	`0`, // sub_32
398	`0`, // sub_64
399	`0`, // sub_dsp16_19
400	`0`, // sub_dsp20
401	`0`, // sub_dsp21
402	`0`, // sub_dsp22
403	`0`, // sub_dsp23
404	`0`, // sub_hi
405	`0`, // sub_lo
406	`0`, // sub_hi_then_sub_32
407	`0`, // sub_32_sub_hi_then_sub_32
408	},
409	{ // COP2
410	`0`, // sub_32
411	`0`, // sub_64
412	`0`, // sub_dsp16_19
413	`0`, // sub_dsp20
414	`0`, // sub_dsp21
415	`0`, // sub_dsp22
416	`0`, // sub_dsp23
417	`0`, // sub_hi
418	`0`, // sub_lo
419	`0`, // sub_hi_then_sub_32
420	`0`, // sub_32_sub_hi_then_sub_32
421	},
422	{ // COP3
423	`0`, // sub_32
424	`0`, // sub_64
425	`0`, // sub_dsp16_19
426	`0`, // sub_dsp20
427	`0`, // sub_dsp21
428	`0`, // sub_dsp22
429	`0`, // sub_dsp23
430	`0`, // sub_hi
431	`0`, // sub_lo
432	`0`, // sub_hi_then_sub_32
433	`0`, // sub_32_sub_hi_then_sub_32
434	},
435	{ // DSPR
436	`0`, // sub_32
437	`0`, // sub_64
438	`0`, // sub_dsp16_19
439	`0`, // sub_dsp20
440	`0`, // sub_dsp21
441	`0`, // sub_dsp22
442	`0`, // sub_dsp23
443	`0`, // sub_hi
444	`0`, // sub_lo
445	`0`, // sub_hi_then_sub_32
446	`0`, // sub_32_sub_hi_then_sub_32
447	},
448	{ // FGR32
449	`0`, // sub_32
450	`0`, // sub_64
451	`0`, // sub_dsp16_19
452	`0`, // sub_dsp20
453	`0`, // sub_dsp21
454	`0`, // sub_dsp22
455	`0`, // sub_dsp23
456	`0`, // sub_hi
457	`0`, // sub_lo
458	`0`, // sub_hi_then_sub_32
459	`0`, // sub_32_sub_hi_then_sub_32
460	},
461	{ // GPR32
462	`0`, // sub_32
463	`0`, // sub_64
464	`0`, // sub_dsp16_19
465	`0`, // sub_dsp20
466	`0`, // sub_dsp21
467	`0`, // sub_dsp22
468	`0`, // sub_dsp23
469	`0`, // sub_hi
470	`0`, // sub_lo
471	`0`, // sub_hi_then_sub_32
472	`0`, // sub_32_sub_hi_then_sub_32
473	},
474	{ // HWRegs
475	`0`, // sub_32
476	`0`, // sub_64
477	`0`, // sub_dsp16_19
478	`0`, // sub_dsp20
479	`0`, // sub_dsp21
480	`0`, // sub_dsp22
481	`0`, // sub_dsp23
482	`0`, // sub_hi
483	`0`, // sub_lo
484	`0`, // sub_hi_then_sub_32
485	`0`, // sub_32_sub_hi_then_sub_32
486	},
487	{ // MSACtrl
488	`0`, // sub_32
489	`0`, // sub_64
490	`0`, // sub_dsp16_19
491	`0`, // sub_dsp20
492	`0`, // sub_dsp21
493	`0`, // sub_dsp22
494	`0`, // sub_dsp23
495	`0`, // sub_hi
496	`0`, // sub_lo
497	`0`, // sub_hi_then_sub_32
498	`0`, // sub_32_sub_hi_then_sub_32
499	},
500	{ // GPR32NONZERO
501	`0`, // sub_32
502	`0`, // sub_64
503	`0`, // sub_dsp16_19
504	`0`, // sub_dsp20
505	`0`, // sub_dsp21
506	`0`, // sub_dsp22
507	`0`, // sub_dsp23
508	`0`, // sub_hi
509	`0`, // sub_lo
510	`0`, // sub_hi_then_sub_32
511	`0`, // sub_32_sub_hi_then_sub_32
512	},
513	{ // CPU16RegsPlusSP
514	`0`, // sub_32
515	`0`, // sub_64
516	`0`, // sub_dsp16_19
517	`0`, // sub_dsp20
518	`0`, // sub_dsp21
519	`0`, // sub_dsp22
520	`0`, // sub_dsp23
521	`0`, // sub_hi
522	`0`, // sub_lo
523	`0`, // sub_hi_then_sub_32
524	`0`, // sub_32_sub_hi_then_sub_32
525	},
526	{ // CPU16Regs
527	`0`, // sub_32
528	`0`, // sub_64
529	`0`, // sub_dsp16_19
530	`0`, // sub_dsp20
531	`0`, // sub_dsp21
532	`0`, // sub_dsp22
533	`0`, // sub_dsp23
534	`0`, // sub_hi
535	`0`, // sub_lo
536	`0`, // sub_hi_then_sub_32
537	`0`, // sub_32_sub_hi_then_sub_32
538	},
539	{ // FCC
540	`0`, // sub_32
541	`0`, // sub_64
542	`0`, // sub_dsp16_19
543	`0`, // sub_dsp20
544	`0`, // sub_dsp21
545	`0`, // sub_dsp22
546	`0`, // sub_dsp23
547	`0`, // sub_hi
548	`0`, // sub_lo
549	`0`, // sub_hi_then_sub_32
550	`0`, // sub_32_sub_hi_then_sub_32
551	},
552	{ // GPRMM16
553	`0`, // sub_32
554	`0`, // sub_64
555	`0`, // sub_dsp16_19
556	`0`, // sub_dsp20
557	`0`, // sub_dsp21
558	`0`, // sub_dsp22
559	`0`, // sub_dsp23
560	`0`, // sub_hi
561	`0`, // sub_lo
562	`0`, // sub_hi_then_sub_32
563	`0`, // sub_32_sub_hi_then_sub_32
564	},
565	{ // GPRMM16MoveP
566	`0`, // sub_32
567	`0`, // sub_64
568	`0`, // sub_dsp16_19
569	`0`, // sub_dsp20
570	`0`, // sub_dsp21
571	`0`, // sub_dsp22
572	`0`, // sub_dsp23
573	`0`, // sub_hi
574	`0`, // sub_lo
575	`0`, // sub_hi_then_sub_32
576	`0`, // sub_32_sub_hi_then_sub_32
577	},
578	{ // GPRMM16Zero
579	`0`, // sub_32
580	`0`, // sub_64
581	`0`, // sub_dsp16_19
582	`0`, // sub_dsp20
583	`0`, // sub_dsp21
584	`0`, // sub_dsp22
585	`0`, // sub_dsp23
586	`0`, // sub_hi
587	`0`, // sub_lo
588	`0`, // sub_hi_then_sub_32
589	`0`, // sub_32_sub_hi_then_sub_32
590	},
591	{ // CPU16Regs_and_GPRMM16Zero
592	`0`, // sub_32
593	`0`, // sub_64
594	`0`, // sub_dsp16_19
595	`0`, // sub_dsp20
596	`0`, // sub_dsp21
597	`0`, // sub_dsp22
598	`0`, // sub_dsp23
599	`0`, // sub_hi
600	`0`, // sub_lo
601	`0`, // sub_hi_then_sub_32
602	`0`, // sub_32_sub_hi_then_sub_32
603	},
604	{ // GPR32NONZERO_and_GPRMM16MoveP
605	`0`, // sub_32
606	`0`, // sub_64
607	`0`, // sub_dsp16_19
608	`0`, // sub_dsp20
609	`0`, // sub_dsp21
610	`0`, // sub_dsp22
611	`0`, // sub_dsp23
612	`0`, // sub_hi
613	`0`, // sub_lo
614	`0`, // sub_hi_then_sub_32
615	`0`, // sub_32_sub_hi_then_sub_32
616	},
617	{ // GPRMM16MovePPairSecond
618	`0`, // sub_32
619	`0`, // sub_64
620	`0`, // sub_dsp16_19
621	`0`, // sub_dsp20
622	`0`, // sub_dsp21
623	`0`, // sub_dsp22
624	`0`, // sub_dsp23
625	`0`, // sub_hi
626	`0`, // sub_lo
627	`0`, // sub_hi_then_sub_32
628	`0`, // sub_32_sub_hi_then_sub_32
629	},
630	{ // CPU16Regs_and_GPRMM16MoveP
631	`0`, // sub_32
632	`0`, // sub_64
633	`0`, // sub_dsp16_19
634	`0`, // sub_dsp20
635	`0`, // sub_dsp21
636	`0`, // sub_dsp22
637	`0`, // sub_dsp23
638	`0`, // sub_hi
639	`0`, // sub_lo
640	`0`, // sub_hi_then_sub_32
641	`0`, // sub_32_sub_hi_then_sub_32
642	},
643	{ // GPRMM16MoveP_and_GPRMM16Zero
644	`0`, // sub_32
645	`0`, // sub_64
646	`0`, // sub_dsp16_19
647	`0`, // sub_dsp20
648	`0`, // sub_dsp21
649	`0`, // sub_dsp22
650	`0`, // sub_dsp23
651	`0`, // sub_hi
652	`0`, // sub_lo
653	`0`, // sub_hi_then_sub_32
654	`0`, // sub_32_sub_hi_then_sub_32
655	},
656	{ // HI32DSP
657	`0`, // sub_32
658	`0`, // sub_64
659	`0`, // sub_dsp16_19
660	`0`, // sub_dsp20
661	`0`, // sub_dsp21
662	`0`, // sub_dsp22
663	`0`, // sub_dsp23
664	`0`, // sub_hi
665	`0`, // sub_lo
666	`0`, // sub_hi_then_sub_32
667	`0`, // sub_32_sub_hi_then_sub_32
668	},
669	{ // LO32DSP
670	`0`, // sub_32
671	`0`, // sub_64
672	`0`, // sub_dsp16_19
673	`0`, // sub_dsp20
674	`0`, // sub_dsp21
675	`0`, // sub_dsp22
676	`0`, // sub_dsp23
677	`0`, // sub_hi
678	`0`, // sub_lo
679	`0`, // sub_hi_then_sub_32
680	`0`, // sub_32_sub_hi_then_sub_32
681	},
682	{ // CPU16Regs_and_GPRMM16MovePPairSecond
683	`0`, // sub_32
684	`0`, // sub_64
685	`0`, // sub_dsp16_19
686	`0`, // sub_dsp20
687	`0`, // sub_dsp21
688	`0`, // sub_dsp22
689	`0`, // sub_dsp23
690	`0`, // sub_hi
691	`0`, // sub_lo
692	`0`, // sub_hi_then_sub_32
693	`0`, // sub_32_sub_hi_then_sub_32
694	},
695	{ // GPRMM16MovePPairFirst
696	`0`, // sub_32
697	`0`, // sub_64
698	`0`, // sub_dsp16_19
699	`0`, // sub_dsp20
700	`0`, // sub_dsp21
701	`0`, // sub_dsp22
702	`0`, // sub_dsp23
703	`0`, // sub_hi
704	`0`, // sub_lo
705	`0`, // sub_hi_then_sub_32
706	`0`, // sub_32_sub_hi_then_sub_32
707	},
708	{ // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
709	`0`, // sub_32
710	`0`, // sub_64
711	`0`, // sub_dsp16_19
712	`0`, // sub_dsp20
713	`0`, // sub_dsp21
714	`0`, // sub_dsp22
715	`0`, // sub_dsp23
716	`0`, // sub_hi
717	`0`, // sub_lo
718	`0`, // sub_hi_then_sub_32
719	`0`, // sub_32_sub_hi_then_sub_32
720	},
721	{ // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
722	`0`, // sub_32
723	`0`, // sub_64
724	`0`, // sub_dsp16_19
725	`0`, // sub_dsp20
726	`0`, // sub_dsp21
727	`0`, // sub_dsp22
728	`0`, // sub_dsp23
729	`0`, // sub_hi
730	`0`, // sub_lo
731	`0`, // sub_hi_then_sub_32
732	`0`, // sub_32_sub_hi_then_sub_32
733	},
734	{ // CPURAReg
735	`0`, // sub_32
736	`0`, // sub_64
737	`0`, // sub_dsp16_19
738	`0`, // sub_dsp20
739	`0`, // sub_dsp21
740	`0`, // sub_dsp22
741	`0`, // sub_dsp23
742	`0`, // sub_hi
743	`0`, // sub_lo
744	`0`, // sub_hi_then_sub_32
745	`0`, // sub_32_sub_hi_then_sub_32
746	},
747	{ // CPUSPReg
748	`0`, // sub_32
749	`0`, // sub_64
750	`0`, // sub_dsp16_19
751	`0`, // sub_dsp20
752	`0`, // sub_dsp21
753	`0`, // sub_dsp22
754	`0`, // sub_dsp23
755	`0`, // sub_hi
756	`0`, // sub_lo
757	`0`, // sub_hi_then_sub_32
758	`0`, // sub_32_sub_hi_then_sub_32
759	},
760	{ // DSPCC
761	`0`, // sub_32
762	`0`, // sub_64
763	`0`, // sub_dsp16_19
764	`0`, // sub_dsp20
765	`0`, // sub_dsp21
766	`0`, // sub_dsp22
767	`0`, // sub_dsp23
768	`0`, // sub_hi
769	`0`, // sub_lo
770	`0`, // sub_hi_then_sub_32
771	`0`, // sub_32_sub_hi_then_sub_32
772	},
773	{ // GP32
774	`0`, // sub_32
775	`0`, // sub_64
776	`0`, // sub_dsp16_19
777	`0`, // sub_dsp20
778	`0`, // sub_dsp21
779	`0`, // sub_dsp22
780	`0`, // sub_dsp23
781	`0`, // sub_hi
782	`0`, // sub_lo
783	`0`, // sub_hi_then_sub_32
784	`0`, // sub_32_sub_hi_then_sub_32
785	},
786	{ // GPR32ZERO
787	`0`, // sub_32
788	`0`, // sub_64
789	`0`, // sub_dsp16_19
790	`0`, // sub_dsp20
791	`0`, // sub_dsp21
792	`0`, // sub_dsp22
793	`0`, // sub_dsp23
794	`0`, // sub_hi
795	`0`, // sub_lo
796	`0`, // sub_hi_then_sub_32
797	`0`, // sub_32_sub_hi_then_sub_32
798	},
799	{ // HI32
800	`0`, // sub_32
801	`0`, // sub_64
802	`0`, // sub_dsp16_19
803	`0`, // sub_dsp20
804	`0`, // sub_dsp21
805	`0`, // sub_dsp22
806	`0`, // sub_dsp23
807	`0`, // sub_hi
808	`0`, // sub_lo
809	`0`, // sub_hi_then_sub_32
810	`0`, // sub_32_sub_hi_then_sub_32
811	},
812	{ // LO32
813	`0`, // sub_32
814	`0`, // sub_64
815	`0`, // sub_dsp16_19
816	`0`, // sub_dsp20
817	`0`, // sub_dsp21
818	`0`, // sub_dsp22
819	`0`, // sub_dsp23
820	`0`, // sub_hi
821	`0`, // sub_lo
822	`0`, // sub_hi_then_sub_32
823	`0`, // sub_32_sub_hi_then_sub_32
824	},
825	{ // SP32
826	`0`, // sub_32
827	`0`, // sub_64
828	`0`, // sub_dsp16_19
829	`0`, // sub_dsp20
830	`0`, // sub_dsp21
831	`0`, // sub_dsp22
832	`0`, // sub_dsp23
833	`0`, // sub_hi
834	`0`, // sub_lo
835	`0`, // sub_hi_then_sub_32
836	`0`, // sub_32_sub_hi_then_sub_32
837	},
838	{ // FGR64
839	`0`, // sub_32
840	`0`, // sub_64
841	`0`, // sub_dsp16_19
842	`0`, // sub_dsp20
843	`0`, // sub_dsp21
844	`0`, // sub_dsp22
845	`0`, // sub_dsp23
846	`36`, // sub_hi -> FGR64
847	`36`, // sub_lo -> FGR64
848	`0`, // sub_hi_then_sub_32
849	`0`, // sub_32_sub_hi_then_sub_32
850	},
851	{ // GPR64
852	`37`, // sub_32 -> GPR64
853	`0`, // sub_64
854	`0`, // sub_dsp16_19
855	`0`, // sub_dsp20
856	`0`, // sub_dsp21
857	`0`, // sub_dsp22
858	`0`, // sub_dsp23
859	`0`, // sub_hi
860	`0`, // sub_lo
861	`0`, // sub_hi_then_sub_32
862	`0`, // sub_32_sub_hi_then_sub_32
863	},
864	{ // GPR64_with_sub_32_in_GPR32NONZERO
865	`38`, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO
866	`0`, // sub_64
867	`0`, // sub_dsp16_19
868	`0`, // sub_dsp20
869	`0`, // sub_dsp21
870	`0`, // sub_dsp22
871	`0`, // sub_dsp23
872	`0`, // sub_hi
873	`0`, // sub_lo
874	`0`, // sub_hi_then_sub_32
875	`0`, // sub_32_sub_hi_then_sub_32
876	},
877	{ // AFGR64
878	`0`, // sub_32
879	`0`, // sub_64
880	`0`, // sub_dsp16_19
881	`0`, // sub_dsp20
882	`0`, // sub_dsp21
883	`0`, // sub_dsp22
884	`0`, // sub_dsp23
885	`39`, // sub_hi -> AFGR64
886	`39`, // sub_lo -> AFGR64
887	`0`, // sub_hi_then_sub_32
888	`0`, // sub_32_sub_hi_then_sub_32
889	},
890	{ // GPR64_with_sub_32_in_CPU16RegsPlusSP
891	`40`, // sub_32 -> GPR64_with_sub_32_in_CPU16RegsPlusSP
892	`0`, // sub_64
893	`0`, // sub_dsp16_19
894	`0`, // sub_dsp20
895	`0`, // sub_dsp21
896	`0`, // sub_dsp22
897	`0`, // sub_dsp23
898	`0`, // sub_hi
899	`0`, // sub_lo
900	`0`, // sub_hi_then_sub_32
901	`0`, // sub_32_sub_hi_then_sub_32
902	},
903	{ // GPR64_with_sub_32_in_CPU16Regs
904	`41`, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs
905	`0`, // sub_64
906	`0`, // sub_dsp16_19
907	`0`, // sub_dsp20
908	`0`, // sub_dsp21
909	`0`, // sub_dsp22
910	`0`, // sub_dsp23
911	`0`, // sub_hi
912	`0`, // sub_lo
913	`0`, // sub_hi_then_sub_32
914	`0`, // sub_32_sub_hi_then_sub_32
915	},
916	{ // GPR64_with_sub_32_in_GPRMM16MoveP
917	`42`, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP
918	`0`, // sub_64
919	`0`, // sub_dsp16_19
920	`0`, // sub_dsp20
921	`0`, // sub_dsp21
922	`0`, // sub_dsp22
923	`0`, // sub_dsp23
924	`0`, // sub_hi
925	`0`, // sub_lo
926	`0`, // sub_hi_then_sub_32
927	`0`, // sub_32_sub_hi_then_sub_32
928	},
929	{ // GPR64_with_sub_32_in_GPRMM16Zero
930	`43`, // sub_32 -> GPR64_with_sub_32_in_GPRMM16Zero
931	`0`, // sub_64
932	`0`, // sub_dsp16_19
933	`0`, // sub_dsp20
934	`0`, // sub_dsp21
935	`0`, // sub_dsp22
936	`0`, // sub_dsp23
937	`0`, // sub_hi
938	`0`, // sub_lo
939	`0`, // sub_hi_then_sub_32
940	`0`, // sub_32_sub_hi_then_sub_32
941	},
942	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
943	`44`, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
944	`0`, // sub_64
945	`0`, // sub_dsp16_19
946	`0`, // sub_dsp20
947	`0`, // sub_dsp21
948	`0`, // sub_dsp22
949	`0`, // sub_dsp23
950	`0`, // sub_hi
951	`0`, // sub_lo
952	`0`, // sub_hi_then_sub_32
953	`0`, // sub_32_sub_hi_then_sub_32
954	},
955	{ // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
956	`45`, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
957	`0`, // sub_64
958	`0`, // sub_dsp16_19
959	`0`, // sub_dsp20
960	`0`, // sub_dsp21
961	`0`, // sub_dsp22
962	`0`, // sub_dsp23
963	`0`, // sub_hi
964	`0`, // sub_lo
965	`0`, // sub_hi_then_sub_32
966	`0`, // sub_32_sub_hi_then_sub_32
967	},
968	{ // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
969	`46`, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairSecond
970	`0`, // sub_64
971	`0`, // sub_dsp16_19
972	`0`, // sub_dsp20
973	`0`, // sub_dsp21
974	`0`, // sub_dsp22
975	`0`, // sub_dsp23
976	`0`, // sub_hi
977	`0`, // sub_lo
978	`0`, // sub_hi_then_sub_32
979	`0`, // sub_32_sub_hi_then_sub_32
980	},
981	{ // ACC64DSP
982	`0`, // sub_32
983	`0`, // sub_64
984	`0`, // sub_dsp16_19
985	`0`, // sub_dsp20
986	`0`, // sub_dsp21
987	`0`, // sub_dsp22
988	`0`, // sub_dsp23
989	`47`, // sub_hi -> ACC64DSP
990	`47`, // sub_lo -> ACC64DSP
991	`0`, // sub_hi_then_sub_32
992	`0`, // sub_32_sub_hi_then_sub_32
993	},
994	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
995	`48`, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
996	`0`, // sub_64
997	`0`, // sub_dsp16_19
998	`0`, // sub_dsp20
999	`0`, // sub_dsp21
1000	`0`, // sub_dsp22
1001	`0`, // sub_dsp23
1002	`0`, // sub_hi
1003	`0`, // sub_lo
1004	`0`, // sub_hi_then_sub_32
1005	`0`, // sub_32_sub_hi_then_sub_32
1006	},
1007	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
1008	`49`, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
1009	`0`, // sub_64
1010	`0`, // sub_dsp16_19
1011	`0`, // sub_dsp20
1012	`0`, // sub_dsp21
1013	`0`, // sub_dsp22
1014	`0`, // sub_dsp23
1015	`0`, // sub_hi
1016	`0`, // sub_lo
1017	`0`, // sub_hi_then_sub_32
1018	`0`, // sub_32_sub_hi_then_sub_32
1019	},
1020	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
1021	`50`, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
1022	`0`, // sub_64
1023	`0`, // sub_dsp16_19
1024	`0`, // sub_dsp20
1025	`0`, // sub_dsp21
1026	`0`, // sub_dsp22
1027	`0`, // sub_dsp23
1028	`0`, // sub_hi
1029	`0`, // sub_lo
1030	`0`, // sub_hi_then_sub_32
1031	`0`, // sub_32_sub_hi_then_sub_32
1032	},
1033	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
1034	`51`, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst
1035	`0`, // sub_64
1036	`0`, // sub_dsp16_19
1037	`0`, // sub_dsp20
1038	`0`, // sub_dsp21
1039	`0`, // sub_dsp22
1040	`0`, // sub_dsp23
1041	`0`, // sub_hi
1042	`0`, // sub_lo
1043	`0`, // sub_hi_then_sub_32
1044	`0`, // sub_32_sub_hi_then_sub_32
1045	},
1046	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
1047	`52`, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
1048	`0`, // sub_64
1049	`0`, // sub_dsp16_19
1050	`0`, // sub_dsp20
1051	`0`, // sub_dsp21
1052	`0`, // sub_dsp22
1053	`0`, // sub_dsp23
1054	`0`, // sub_hi
1055	`0`, // sub_lo
1056	`0`, // sub_hi_then_sub_32
1057	`0`, // sub_32_sub_hi_then_sub_32
1058	},
1059	{ // OCTEON_MPL
1060	`0`, // sub_32
1061	`0`, // sub_64
1062	`0`, // sub_dsp16_19
1063	`0`, // sub_dsp20
1064	`0`, // sub_dsp21
1065	`0`, // sub_dsp22
1066	`0`, // sub_dsp23
1067	`0`, // sub_hi
1068	`0`, // sub_lo
1069	`0`, // sub_hi_then_sub_32
1070	`0`, // sub_32_sub_hi_then_sub_32
1071	},
1072	{ // OCTEON_P
1073	`0`, // sub_32
1074	`0`, // sub_64
1075	`0`, // sub_dsp16_19
1076	`0`, // sub_dsp20
1077	`0`, // sub_dsp21
1078	`0`, // sub_dsp22
1079	`0`, // sub_dsp23
1080	`0`, // sub_hi
1081	`0`, // sub_lo
1082	`0`, // sub_hi_then_sub_32
1083	`0`, // sub_32_sub_hi_then_sub_32
1084	},
1085	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
1086	`55`, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
1087	`0`, // sub_64
1088	`0`, // sub_dsp16_19
1089	`0`, // sub_dsp20
1090	`0`, // sub_dsp21
1091	`0`, // sub_dsp22
1092	`0`, // sub_dsp23
1093	`0`, // sub_hi
1094	`0`, // sub_lo
1095	`0`, // sub_hi_then_sub_32
1096	`0`, // sub_32_sub_hi_then_sub_32
1097	},
1098	{ // ACC64
1099	`0`, // sub_32
1100	`0`, // sub_64
1101	`0`, // sub_dsp16_19
1102	`0`, // sub_dsp20
1103	`0`, // sub_dsp21
1104	`0`, // sub_dsp22
1105	`0`, // sub_dsp23
1106	`56`, // sub_hi -> ACC64
1107	`56`, // sub_lo -> ACC64
1108	`0`, // sub_hi_then_sub_32
1109	`0`, // sub_32_sub_hi_then_sub_32
1110	},
1111	{ // GP64
1112	`57`, // sub_32 -> GP64
1113	`0`, // sub_64
1114	`0`, // sub_dsp16_19
1115	`0`, // sub_dsp20
1116	`0`, // sub_dsp21
1117	`0`, // sub_dsp22
1118	`0`, // sub_dsp23
1119	`0`, // sub_hi
1120	`0`, // sub_lo
1121	`0`, // sub_hi_then_sub_32
1122	`0`, // sub_32_sub_hi_then_sub_32
1123	},
1124	{ // GPR64_with_sub_32_in_CPURAReg
1125	`58`, // sub_32 -> GPR64_with_sub_32_in_CPURAReg
1126	`0`, // sub_64
1127	`0`, // sub_dsp16_19
1128	`0`, // sub_dsp20
1129	`0`, // sub_dsp21
1130	`0`, // sub_dsp22
1131	`0`, // sub_dsp23
1132	`0`, // sub_hi
1133	`0`, // sub_lo
1134	`0`, // sub_hi_then_sub_32
1135	`0`, // sub_32_sub_hi_then_sub_32
1136	},
1137	{ // GPR64_with_sub_32_in_GPR32ZERO
1138	`59`, // sub_32 -> GPR64_with_sub_32_in_GPR32ZERO
1139	`0`, // sub_64
1140	`0`, // sub_dsp16_19
1141	`0`, // sub_dsp20
1142	`0`, // sub_dsp21
1143	`0`, // sub_dsp22
1144	`0`, // sub_dsp23
1145	`0`, // sub_hi
1146	`0`, // sub_lo
1147	`0`, // sub_hi_then_sub_32
1148	`0`, // sub_32_sub_hi_then_sub_32
1149	},
1150	{ // HI64
1151	`60`, // sub_32 -> HI64
1152	`0`, // sub_64
1153	`0`, // sub_dsp16_19
1154	`0`, // sub_dsp20
1155	`0`, // sub_dsp21
1156	`0`, // sub_dsp22
1157	`0`, // sub_dsp23
1158	`0`, // sub_hi
1159	`0`, // sub_lo
1160	`0`, // sub_hi_then_sub_32
1161	`0`, // sub_32_sub_hi_then_sub_32
1162	},
1163	{ // LO64
1164	`61`, // sub_32 -> LO64
1165	`0`, // sub_64
1166	`0`, // sub_dsp16_19
1167	`0`, // sub_dsp20
1168	`0`, // sub_dsp21
1169	`0`, // sub_dsp22
1170	`0`, // sub_dsp23
1171	`0`, // sub_hi
1172	`0`, // sub_lo
1173	`0`, // sub_hi_then_sub_32
1174	`0`, // sub_32_sub_hi_then_sub_32
1175	},
1176	{ // SP64
1177	`62`, // sub_32 -> SP64
1178	`0`, // sub_64
1179	`0`, // sub_dsp16_19
1180	`0`, // sub_dsp20
1181	`0`, // sub_dsp21
1182	`0`, // sub_dsp22
1183	`0`, // sub_dsp23
1184	`0`, // sub_hi
1185	`0`, // sub_lo
1186	`0`, // sub_hi_then_sub_32
1187	`0`, // sub_32_sub_hi_then_sub_32
1188	},
1189	{ // MSA128B
1190	`0`, // sub_32
1191	`63`, // sub_64 -> MSA128B
1192	`0`, // sub_dsp16_19
1193	`0`, // sub_dsp20
1194	`0`, // sub_dsp21
1195	`0`, // sub_dsp22
1196	`0`, // sub_dsp23
1197	`63`, // sub_hi -> MSA128B
1198	`63`, // sub_lo -> MSA128B
1199	`0`, // sub_hi_then_sub_32
1200	`0`, // sub_32_sub_hi_then_sub_32
1201	},
1202	{ // MSA128D
1203	`0`, // sub_32
1204	`64`, // sub_64 -> MSA128D
1205	`0`, // sub_dsp16_19
1206	`0`, // sub_dsp20
1207	`0`, // sub_dsp21
1208	`0`, // sub_dsp22
1209	`0`, // sub_dsp23
1210	`64`, // sub_hi -> MSA128D
1211	`64`, // sub_lo -> MSA128D
1212	`0`, // sub_hi_then_sub_32
1213	`0`, // sub_32_sub_hi_then_sub_32
1214	},
1215	{ // MSA128H
1216	`0`, // sub_32
1217	`65`, // sub_64 -> MSA128H
1218	`0`, // sub_dsp16_19
1219	`0`, // sub_dsp20
1220	`0`, // sub_dsp21
1221	`0`, // sub_dsp22
1222	`0`, // sub_dsp23
1223	`65`, // sub_hi -> MSA128H
1224	`65`, // sub_lo -> MSA128H
1225	`0`, // sub_hi_then_sub_32
1226	`0`, // sub_32_sub_hi_then_sub_32
1227	},
1228	{ // MSA128W
1229	`0`, // sub_32
1230	`66`, // sub_64 -> MSA128W
1231	`0`, // sub_dsp16_19
1232	`0`, // sub_dsp20
1233	`0`, // sub_dsp21
1234	`0`, // sub_dsp22
1235	`0`, // sub_dsp23
1236	`66`, // sub_hi -> MSA128W
1237	`66`, // sub_lo -> MSA128W
1238	`0`, // sub_hi_then_sub_32
1239	`0`, // sub_32_sub_hi_then_sub_32
1240	},
1241	{ // MSA128WEvens
1242	`0`, // sub_32
1243	`67`, // sub_64 -> MSA128WEvens
1244	`0`, // sub_dsp16_19
1245	`0`, // sub_dsp20
1246	`0`, // sub_dsp21
1247	`0`, // sub_dsp22
1248	`0`, // sub_dsp23
1249	`67`, // sub_hi -> MSA128WEvens
1250	`67`, // sub_lo -> MSA128WEvens
1251	`0`, // sub_hi_then_sub_32
1252	`0`, // sub_32_sub_hi_then_sub_32
1253	},
1254	{ // ACC128
1255	`68`, // sub_32 -> ACC128
1256	`0`, // sub_64
1257	`0`, // sub_dsp16_19
1258	`0`, // sub_dsp20
1259	`0`, // sub_dsp21
1260	`0`, // sub_dsp22
1261	`0`, // sub_dsp23
1262	`68`, // sub_hi -> ACC128
1263	`68`, // sub_lo -> ACC128
1264	`68`, // sub_hi_then_sub_32 -> ACC128
1265	`68`, // sub_32_sub_hi_then_sub_32 -> ACC128
1266	},
1267
1268	};
1269	assert(RC && "Missing regclass");
1270	if (!Idx) return RC;
1271	--Idx;
1272	assert(Idx < `11` && "Bad subreg");
1273	unsigned TV = Table[RC->getID()][Idx];
1274	return TV ? getRegClass(i: TV - `1`) : nullptr;
1275	}const TargetRegisterClass MipsGenRegisterInfo::getSubRegisterClass(const* TargetRegisterClass RC, unsigned* Idx) const {
1276	static constexpr uint8_t Table[`68`][`11`] = {
1277	{ // CCR
1278	`0`, // CCR:sub_32
1279	`0`, // CCR:sub_64
1280	`0`, // CCR:sub_dsp16_19
1281	`0`, // CCR:sub_dsp20
1282	`0`, // CCR:sub_dsp21
1283	`0`, // CCR:sub_dsp22
1284	`0`, // CCR:sub_dsp23
1285	`0`, // CCR:sub_hi
1286	`0`, // CCR:sub_lo
1287	`0`, // CCR:sub_hi_then_sub_32
1288	`0`, // CCR:sub_32_sub_hi_then_sub_32
1289	},
1290	{ // COP0
1291	`0`, // COP0:sub_32
1292	`0`, // COP0:sub_64
1293	`0`, // COP0:sub_dsp16_19
1294	`0`, // COP0:sub_dsp20
1295	`0`, // COP0:sub_dsp21
1296	`0`, // COP0:sub_dsp22
1297	`0`, // COP0:sub_dsp23
1298	`0`, // COP0:sub_hi
1299	`0`, // COP0:sub_lo
1300	`0`, // COP0:sub_hi_then_sub_32
1301	`0`, // COP0:sub_32_sub_hi_then_sub_32
1302	},
1303	{ // COP2
1304	`0`, // COP2:sub_32
1305	`0`, // COP2:sub_64
1306	`0`, // COP2:sub_dsp16_19
1307	`0`, // COP2:sub_dsp20
1308	`0`, // COP2:sub_dsp21
1309	`0`, // COP2:sub_dsp22
1310	`0`, // COP2:sub_dsp23
1311	`0`, // COP2:sub_hi
1312	`0`, // COP2:sub_lo
1313	`0`, // COP2:sub_hi_then_sub_32
1314	`0`, // COP2:sub_32_sub_hi_then_sub_32
1315	},
1316	{ // COP3
1317	`0`, // COP3:sub_32
1318	`0`, // COP3:sub_64
1319	`0`, // COP3:sub_dsp16_19
1320	`0`, // COP3:sub_dsp20
1321	`0`, // COP3:sub_dsp21
1322	`0`, // COP3:sub_dsp22
1323	`0`, // COP3:sub_dsp23
1324	`0`, // COP3:sub_hi
1325	`0`, // COP3:sub_lo
1326	`0`, // COP3:sub_hi_then_sub_32
1327	`0`, // COP3:sub_32_sub_hi_then_sub_32
1328	},
1329	{ // DSPR
1330	`0`, // DSPR:sub_32
1331	`0`, // DSPR:sub_64
1332	`0`, // DSPR:sub_dsp16_19
1333	`0`, // DSPR:sub_dsp20
1334	`0`, // DSPR:sub_dsp21
1335	`0`, // DSPR:sub_dsp22
1336	`0`, // DSPR:sub_dsp23
1337	`0`, // DSPR:sub_hi
1338	`0`, // DSPR:sub_lo
1339	`0`, // DSPR:sub_hi_then_sub_32
1340	`0`, // DSPR:sub_32_sub_hi_then_sub_32
1341	},
1342	{ // FGR32
1343	`0`, // FGR32:sub_32
1344	`0`, // FGR32:sub_64
1345	`0`, // FGR32:sub_dsp16_19
1346	`0`, // FGR32:sub_dsp20
1347	`0`, // FGR32:sub_dsp21
1348	`0`, // FGR32:sub_dsp22
1349	`0`, // FGR32:sub_dsp23
1350	`0`, // FGR32:sub_hi
1351	`0`, // FGR32:sub_lo
1352	`0`, // FGR32:sub_hi_then_sub_32
1353	`0`, // FGR32:sub_32_sub_hi_then_sub_32
1354	},
1355	{ // GPR32
1356	`0`, // GPR32:sub_32
1357	`0`, // GPR32:sub_64
1358	`0`, // GPR32:sub_dsp16_19
1359	`0`, // GPR32:sub_dsp20
1360	`0`, // GPR32:sub_dsp21
1361	`0`, // GPR32:sub_dsp22
1362	`0`, // GPR32:sub_dsp23
1363	`0`, // GPR32:sub_hi
1364	`0`, // GPR32:sub_lo
1365	`0`, // GPR32:sub_hi_then_sub_32
1366	`0`, // GPR32:sub_32_sub_hi_then_sub_32
1367	},
1368	{ // HWRegs
1369	`0`, // HWRegs:sub_32
1370	`0`, // HWRegs:sub_64
1371	`0`, // HWRegs:sub_dsp16_19
1372	`0`, // HWRegs:sub_dsp20
1373	`0`, // HWRegs:sub_dsp21
1374	`0`, // HWRegs:sub_dsp22
1375	`0`, // HWRegs:sub_dsp23
1376	`0`, // HWRegs:sub_hi
1377	`0`, // HWRegs:sub_lo
1378	`0`, // HWRegs:sub_hi_then_sub_32
1379	`0`, // HWRegs:sub_32_sub_hi_then_sub_32
1380	},
1381	{ // MSACtrl
1382	`0`, // MSACtrl:sub_32
1383	`0`, // MSACtrl:sub_64
1384	`0`, // MSACtrl:sub_dsp16_19
1385	`0`, // MSACtrl:sub_dsp20
1386	`0`, // MSACtrl:sub_dsp21
1387	`0`, // MSACtrl:sub_dsp22
1388	`0`, // MSACtrl:sub_dsp23
1389	`0`, // MSACtrl:sub_hi
1390	`0`, // MSACtrl:sub_lo
1391	`0`, // MSACtrl:sub_hi_then_sub_32
1392	`0`, // MSACtrl:sub_32_sub_hi_then_sub_32
1393	},
1394	{ // GPR32NONZERO
1395	`0`, // GPR32NONZERO:sub_32
1396	`0`, // GPR32NONZERO:sub_64
1397	`0`, // GPR32NONZERO:sub_dsp16_19
1398	`0`, // GPR32NONZERO:sub_dsp20
1399	`0`, // GPR32NONZERO:sub_dsp21
1400	`0`, // GPR32NONZERO:sub_dsp22
1401	`0`, // GPR32NONZERO:sub_dsp23
1402	`0`, // GPR32NONZERO:sub_hi
1403	`0`, // GPR32NONZERO:sub_lo
1404	`0`, // GPR32NONZERO:sub_hi_then_sub_32
1405	`0`, // GPR32NONZERO:sub_32_sub_hi_then_sub_32
1406	},
1407	{ // CPU16RegsPlusSP
1408	`0`, // CPU16RegsPlusSP:sub_32
1409	`0`, // CPU16RegsPlusSP:sub_64
1410	`0`, // CPU16RegsPlusSP:sub_dsp16_19
1411	`0`, // CPU16RegsPlusSP:sub_dsp20
1412	`0`, // CPU16RegsPlusSP:sub_dsp21
1413	`0`, // CPU16RegsPlusSP:sub_dsp22
1414	`0`, // CPU16RegsPlusSP:sub_dsp23
1415	`0`, // CPU16RegsPlusSP:sub_hi
1416	`0`, // CPU16RegsPlusSP:sub_lo
1417	`0`, // CPU16RegsPlusSP:sub_hi_then_sub_32
1418	`0`, // CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32
1419	},
1420	{ // CPU16Regs
1421	`0`, // CPU16Regs:sub_32
1422	`0`, // CPU16Regs:sub_64
1423	`0`, // CPU16Regs:sub_dsp16_19
1424	`0`, // CPU16Regs:sub_dsp20
1425	`0`, // CPU16Regs:sub_dsp21
1426	`0`, // CPU16Regs:sub_dsp22
1427	`0`, // CPU16Regs:sub_dsp23
1428	`0`, // CPU16Regs:sub_hi
1429	`0`, // CPU16Regs:sub_lo
1430	`0`, // CPU16Regs:sub_hi_then_sub_32
1431	`0`, // CPU16Regs:sub_32_sub_hi_then_sub_32
1432	},
1433	{ // FCC
1434	`0`, // FCC:sub_32
1435	`0`, // FCC:sub_64
1436	`0`, // FCC:sub_dsp16_19
1437	`0`, // FCC:sub_dsp20
1438	`0`, // FCC:sub_dsp21
1439	`0`, // FCC:sub_dsp22
1440	`0`, // FCC:sub_dsp23
1441	`0`, // FCC:sub_hi
1442	`0`, // FCC:sub_lo
1443	`0`, // FCC:sub_hi_then_sub_32
1444	`0`, // FCC:sub_32_sub_hi_then_sub_32
1445	},
1446	{ // GPRMM16
1447	`0`, // GPRMM16:sub_32
1448	`0`, // GPRMM16:sub_64
1449	`0`, // GPRMM16:sub_dsp16_19
1450	`0`, // GPRMM16:sub_dsp20
1451	`0`, // GPRMM16:sub_dsp21
1452	`0`, // GPRMM16:sub_dsp22
1453	`0`, // GPRMM16:sub_dsp23
1454	`0`, // GPRMM16:sub_hi
1455	`0`, // GPRMM16:sub_lo
1456	`0`, // GPRMM16:sub_hi_then_sub_32
1457	`0`, // GPRMM16:sub_32_sub_hi_then_sub_32
1458	},
1459	{ // GPRMM16MoveP
1460	`0`, // GPRMM16MoveP:sub_32
1461	`0`, // GPRMM16MoveP:sub_64
1462	`0`, // GPRMM16MoveP:sub_dsp16_19
1463	`0`, // GPRMM16MoveP:sub_dsp20
1464	`0`, // GPRMM16MoveP:sub_dsp21
1465	`0`, // GPRMM16MoveP:sub_dsp22
1466	`0`, // GPRMM16MoveP:sub_dsp23
1467	`0`, // GPRMM16MoveP:sub_hi
1468	`0`, // GPRMM16MoveP:sub_lo
1469	`0`, // GPRMM16MoveP:sub_hi_then_sub_32
1470	`0`, // GPRMM16MoveP:sub_32_sub_hi_then_sub_32
1471	},
1472	{ // GPRMM16Zero
1473	`0`, // GPRMM16Zero:sub_32
1474	`0`, // GPRMM16Zero:sub_64
1475	`0`, // GPRMM16Zero:sub_dsp16_19
1476	`0`, // GPRMM16Zero:sub_dsp20
1477	`0`, // GPRMM16Zero:sub_dsp21
1478	`0`, // GPRMM16Zero:sub_dsp22
1479	`0`, // GPRMM16Zero:sub_dsp23
1480	`0`, // GPRMM16Zero:sub_hi
1481	`0`, // GPRMM16Zero:sub_lo
1482	`0`, // GPRMM16Zero:sub_hi_then_sub_32
1483	`0`, // GPRMM16Zero:sub_32_sub_hi_then_sub_32
1484	},
1485	{ // CPU16Regs_and_GPRMM16Zero
1486	`0`, // CPU16Regs_and_GPRMM16Zero:sub_32
1487	`0`, // CPU16Regs_and_GPRMM16Zero:sub_64
1488	`0`, // CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
1489	`0`, // CPU16Regs_and_GPRMM16Zero:sub_dsp20
1490	`0`, // CPU16Regs_and_GPRMM16Zero:sub_dsp21
1491	`0`, // CPU16Regs_and_GPRMM16Zero:sub_dsp22
1492	`0`, // CPU16Regs_and_GPRMM16Zero:sub_dsp23
1493	`0`, // CPU16Regs_and_GPRMM16Zero:sub_hi
1494	`0`, // CPU16Regs_and_GPRMM16Zero:sub_lo
1495	`0`, // CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
1496	`0`, // CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
1497	},
1498	{ // GPR32NONZERO_and_GPRMM16MoveP
1499	`0`, // GPR32NONZERO_and_GPRMM16MoveP:sub_32
1500	`0`, // GPR32NONZERO_and_GPRMM16MoveP:sub_64
1501	`0`, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19
1502	`0`, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20
1503	`0`, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21
1504	`0`, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22
1505	`0`, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23
1506	`0`, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi
1507	`0`, // GPR32NONZERO_and_GPRMM16MoveP:sub_lo
1508	`0`, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32
1509	`0`, // GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
1510	},
1511	{ // GPRMM16MovePPairSecond
1512	`0`, // GPRMM16MovePPairSecond:sub_32
1513	`0`, // GPRMM16MovePPairSecond:sub_64
1514	`0`, // GPRMM16MovePPairSecond:sub_dsp16_19
1515	`0`, // GPRMM16MovePPairSecond:sub_dsp20
1516	`0`, // GPRMM16MovePPairSecond:sub_dsp21
1517	`0`, // GPRMM16MovePPairSecond:sub_dsp22
1518	`0`, // GPRMM16MovePPairSecond:sub_dsp23
1519	`0`, // GPRMM16MovePPairSecond:sub_hi
1520	`0`, // GPRMM16MovePPairSecond:sub_lo
1521	`0`, // GPRMM16MovePPairSecond:sub_hi_then_sub_32
1522	`0`, // GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
1523	},
1524	{ // CPU16Regs_and_GPRMM16MoveP
1525	`0`, // CPU16Regs_and_GPRMM16MoveP:sub_32
1526	`0`, // CPU16Regs_and_GPRMM16MoveP:sub_64
1527	`0`, // CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19
1528	`0`, // CPU16Regs_and_GPRMM16MoveP:sub_dsp20
1529	`0`, // CPU16Regs_and_GPRMM16MoveP:sub_dsp21
1530	`0`, // CPU16Regs_and_GPRMM16MoveP:sub_dsp22
1531	`0`, // CPU16Regs_and_GPRMM16MoveP:sub_dsp23
1532	`0`, // CPU16Regs_and_GPRMM16MoveP:sub_hi
1533	`0`, // CPU16Regs_and_GPRMM16MoveP:sub_lo
1534	`0`, // CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32
1535	`0`, // CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
1536	},
1537	{ // GPRMM16MoveP_and_GPRMM16Zero
1538	`0`, // GPRMM16MoveP_and_GPRMM16Zero:sub_32
1539	`0`, // GPRMM16MoveP_and_GPRMM16Zero:sub_64
1540	`0`, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19
1541	`0`, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20
1542	`0`, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21
1543	`0`, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22
1544	`0`, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23
1545	`0`, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi
1546	`0`, // GPRMM16MoveP_and_GPRMM16Zero:sub_lo
1547	`0`, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32
1548	`0`, // GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
1549	},
1550	{ // HI32DSP
1551	`0`, // HI32DSP:sub_32
1552	`0`, // HI32DSP:sub_64
1553	`0`, // HI32DSP:sub_dsp16_19
1554	`0`, // HI32DSP:sub_dsp20
1555	`0`, // HI32DSP:sub_dsp21
1556	`0`, // HI32DSP:sub_dsp22
1557	`0`, // HI32DSP:sub_dsp23
1558	`0`, // HI32DSP:sub_hi
1559	`0`, // HI32DSP:sub_lo
1560	`0`, // HI32DSP:sub_hi_then_sub_32
1561	`0`, // HI32DSP:sub_32_sub_hi_then_sub_32
1562	},
1563	{ // LO32DSP
1564	`0`, // LO32DSP:sub_32
1565	`0`, // LO32DSP:sub_64
1566	`0`, // LO32DSP:sub_dsp16_19
1567	`0`, // LO32DSP:sub_dsp20
1568	`0`, // LO32DSP:sub_dsp21
1569	`0`, // LO32DSP:sub_dsp22
1570	`0`, // LO32DSP:sub_dsp23
1571	`0`, // LO32DSP:sub_hi
1572	`0`, // LO32DSP:sub_lo
1573	`0`, // LO32DSP:sub_hi_then_sub_32
1574	`0`, // LO32DSP:sub_32_sub_hi_then_sub_32
1575	},
1576	{ // CPU16Regs_and_GPRMM16MovePPairSecond
1577	`0`, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32
1578	`0`, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_64
1579	`0`, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19
1580	`0`, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20
1581	`0`, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21
1582	`0`, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22
1583	`0`, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23
1584	`0`, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi
1585	`0`, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo
1586	`0`, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
1587	`0`, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
1588	},
1589	{ // GPRMM16MovePPairFirst
1590	`0`, // GPRMM16MovePPairFirst:sub_32
1591	`0`, // GPRMM16MovePPairFirst:sub_64
1592	`0`, // GPRMM16MovePPairFirst:sub_dsp16_19
1593	`0`, // GPRMM16MovePPairFirst:sub_dsp20
1594	`0`, // GPRMM16MovePPairFirst:sub_dsp21
1595	`0`, // GPRMM16MovePPairFirst:sub_dsp22
1596	`0`, // GPRMM16MovePPairFirst:sub_dsp23
1597	`0`, // GPRMM16MovePPairFirst:sub_hi
1598	`0`, // GPRMM16MovePPairFirst:sub_lo
1599	`0`, // GPRMM16MovePPairFirst:sub_hi_then_sub_32
1600	`0`, // GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32
1601	},
1602	{ // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
1603	`0`, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32
1604	`0`, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64
1605	`0`, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
1606	`0`, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20
1607	`0`, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21
1608	`0`, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22
1609	`0`, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23
1610	`0`, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi
1611	`0`, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo
1612	`0`, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
1613	`0`, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
1614	},
1615	{ // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
1616	`0`, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32
1617	`0`, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64
1618	`0`, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19
1619	`0`, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20
1620	`0`, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21
1621	`0`, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22
1622	`0`, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23
1623	`0`, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi
1624	`0`, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo
1625	`0`, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
1626	`0`, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
1627	},
1628	{ // CPURAReg
1629	`0`, // CPURAReg:sub_32
1630	`0`, // CPURAReg:sub_64
1631	`0`, // CPURAReg:sub_dsp16_19
1632	`0`, // CPURAReg:sub_dsp20
1633	`0`, // CPURAReg:sub_dsp21
1634	`0`, // CPURAReg:sub_dsp22
1635	`0`, // CPURAReg:sub_dsp23
1636	`0`, // CPURAReg:sub_hi
1637	`0`, // CPURAReg:sub_lo
1638	`0`, // CPURAReg:sub_hi_then_sub_32
1639	`0`, // CPURAReg:sub_32_sub_hi_then_sub_32
1640	},
1641	{ // CPUSPReg
1642	`0`, // CPUSPReg:sub_32
1643	`0`, // CPUSPReg:sub_64
1644	`0`, // CPUSPReg:sub_dsp16_19
1645	`0`, // CPUSPReg:sub_dsp20
1646	`0`, // CPUSPReg:sub_dsp21
1647	`0`, // CPUSPReg:sub_dsp22
1648	`0`, // CPUSPReg:sub_dsp23
1649	`0`, // CPUSPReg:sub_hi
1650	`0`, // CPUSPReg:sub_lo
1651	`0`, // CPUSPReg:sub_hi_then_sub_32
1652	`0`, // CPUSPReg:sub_32_sub_hi_then_sub_32
1653	},
1654	{ // DSPCC
1655	`0`, // DSPCC:sub_32
1656	`0`, // DSPCC:sub_64
1657	`0`, // DSPCC:sub_dsp16_19
1658	`0`, // DSPCC:sub_dsp20
1659	`0`, // DSPCC:sub_dsp21
1660	`0`, // DSPCC:sub_dsp22
1661	`0`, // DSPCC:sub_dsp23
1662	`0`, // DSPCC:sub_hi
1663	`0`, // DSPCC:sub_lo
1664	`0`, // DSPCC:sub_hi_then_sub_32
1665	`0`, // DSPCC:sub_32_sub_hi_then_sub_32
1666	},
1667	{ // GP32
1668	`0`, // GP32:sub_32
1669	`0`, // GP32:sub_64
1670	`0`, // GP32:sub_dsp16_19
1671	`0`, // GP32:sub_dsp20
1672	`0`, // GP32:sub_dsp21
1673	`0`, // GP32:sub_dsp22
1674	`0`, // GP32:sub_dsp23
1675	`0`, // GP32:sub_hi
1676	`0`, // GP32:sub_lo
1677	`0`, // GP32:sub_hi_then_sub_32
1678	`0`, // GP32:sub_32_sub_hi_then_sub_32
1679	},
1680	{ // GPR32ZERO
1681	`0`, // GPR32ZERO:sub_32
1682	`0`, // GPR32ZERO:sub_64
1683	`0`, // GPR32ZERO:sub_dsp16_19
1684	`0`, // GPR32ZERO:sub_dsp20
1685	`0`, // GPR32ZERO:sub_dsp21
1686	`0`, // GPR32ZERO:sub_dsp22
1687	`0`, // GPR32ZERO:sub_dsp23
1688	`0`, // GPR32ZERO:sub_hi
1689	`0`, // GPR32ZERO:sub_lo
1690	`0`, // GPR32ZERO:sub_hi_then_sub_32
1691	`0`, // GPR32ZERO:sub_32_sub_hi_then_sub_32
1692	},
1693	{ // HI32
1694	`0`, // HI32:sub_32
1695	`0`, // HI32:sub_64
1696	`0`, // HI32:sub_dsp16_19
1697	`0`, // HI32:sub_dsp20
1698	`0`, // HI32:sub_dsp21
1699	`0`, // HI32:sub_dsp22
1700	`0`, // HI32:sub_dsp23
1701	`0`, // HI32:sub_hi
1702	`0`, // HI32:sub_lo
1703	`0`, // HI32:sub_hi_then_sub_32
1704	`0`, // HI32:sub_32_sub_hi_then_sub_32
1705	},
1706	{ // LO32
1707	`0`, // LO32:sub_32
1708	`0`, // LO32:sub_64
1709	`0`, // LO32:sub_dsp16_19
1710	`0`, // LO32:sub_dsp20
1711	`0`, // LO32:sub_dsp21
1712	`0`, // LO32:sub_dsp22
1713	`0`, // LO32:sub_dsp23
1714	`0`, // LO32:sub_hi
1715	`0`, // LO32:sub_lo
1716	`0`, // LO32:sub_hi_then_sub_32
1717	`0`, // LO32:sub_32_sub_hi_then_sub_32
1718	},
1719	{ // SP32
1720	`0`, // SP32:sub_32
1721	`0`, // SP32:sub_64
1722	`0`, // SP32:sub_dsp16_19
1723	`0`, // SP32:sub_dsp20
1724	`0`, // SP32:sub_dsp21
1725	`0`, // SP32:sub_dsp22
1726	`0`, // SP32:sub_dsp23
1727	`0`, // SP32:sub_hi
1728	`0`, // SP32:sub_lo
1729	`0`, // SP32:sub_hi_then_sub_32
1730	`0`, // SP32:sub_32_sub_hi_then_sub_32
1731	},
1732	{ // FGR64
1733	`0`, // FGR64:sub_32
1734	`0`, // FGR64:sub_64
1735	`0`, // FGR64:sub_dsp16_19
1736	`0`, // FGR64:sub_dsp20
1737	`0`, // FGR64:sub_dsp21
1738	`0`, // FGR64:sub_dsp22
1739	`0`, // FGR64:sub_dsp23
1740	`0`, // FGR64:sub_hi
1741	`6`, // FGR64:sub_lo -> FGR32
1742	`0`, // FGR64:sub_hi_then_sub_32
1743	`0`, // FGR64:sub_32_sub_hi_then_sub_32
1744	},
1745	{ // GPR64
1746	`5`, // GPR64:sub_32 -> DSPR
1747	`0`, // GPR64:sub_64
1748	`0`, // GPR64:sub_dsp16_19
1749	`0`, // GPR64:sub_dsp20
1750	`0`, // GPR64:sub_dsp21
1751	`0`, // GPR64:sub_dsp22
1752	`0`, // GPR64:sub_dsp23
1753	`0`, // GPR64:sub_hi
1754	`0`, // GPR64:sub_lo
1755	`0`, // GPR64:sub_hi_then_sub_32
1756	`0`, // GPR64:sub_32_sub_hi_then_sub_32
1757	},
1758	{ // GPR64_with_sub_32_in_GPR32NONZERO
1759	`10`, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32 -> GPR32NONZERO
1760	`0`, // GPR64_with_sub_32_in_GPR32NONZERO:sub_64
1761	`0`, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp16_19
1762	`0`, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp20
1763	`0`, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp21
1764	`0`, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp22
1765	`0`, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp23
1766	`0`, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi
1767	`0`, // GPR64_with_sub_32_in_GPR32NONZERO:sub_lo
1768	`0`, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi_then_sub_32
1769	`0`, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32_sub_hi_then_sub_32
1770	},
1771	{ // AFGR64
1772	`0`, // AFGR64:sub_32
1773	`0`, // AFGR64:sub_64
1774	`0`, // AFGR64:sub_dsp16_19
1775	`0`, // AFGR64:sub_dsp20
1776	`0`, // AFGR64:sub_dsp21
1777	`0`, // AFGR64:sub_dsp22
1778	`0`, // AFGR64:sub_dsp23
1779	`6`, // AFGR64:sub_hi -> FGR32
1780	`6`, // AFGR64:sub_lo -> FGR32
1781	`0`, // AFGR64:sub_hi_then_sub_32
1782	`0`, // AFGR64:sub_32_sub_hi_then_sub_32
1783	},
1784	{ // GPR64_with_sub_32_in_CPU16RegsPlusSP
1785	`11`, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32 -> CPU16RegsPlusSP
1786	`0`, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_64
1787	`0`, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp16_19
1788	`0`, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp20
1789	`0`, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp21
1790	`0`, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp22
1791	`0`, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp23
1792	`0`, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi
1793	`0`, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_lo
1794	`0`, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi_then_sub_32
1795	`0`, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32
1796	},
1797	{ // GPR64_with_sub_32_in_CPU16Regs
1798	`12`, // GPR64_with_sub_32_in_CPU16Regs:sub_32 -> CPU16Regs
1799	`0`, // GPR64_with_sub_32_in_CPU16Regs:sub_64
1800	`0`, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp16_19
1801	`0`, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp20
1802	`0`, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp21
1803	`0`, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp22
1804	`0`, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp23
1805	`0`, // GPR64_with_sub_32_in_CPU16Regs:sub_hi
1806	`0`, // GPR64_with_sub_32_in_CPU16Regs:sub_lo
1807	`0`, // GPR64_with_sub_32_in_CPU16Regs:sub_hi_then_sub_32
1808	`0`, // GPR64_with_sub_32_in_CPU16Regs:sub_32_sub_hi_then_sub_32
1809	},
1810	{ // GPR64_with_sub_32_in_GPRMM16MoveP
1811	`15`, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32 -> GPRMM16MoveP
1812	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_64
1813	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp16_19
1814	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp20
1815	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp21
1816	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp22
1817	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp23
1818	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi
1819	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_lo
1820	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi_then_sub_32
1821	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
1822	},
1823	{ // GPR64_with_sub_32_in_GPRMM16Zero
1824	`16`, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32 -> GPRMM16Zero
1825	`0`, // GPR64_with_sub_32_in_GPRMM16Zero:sub_64
1826	`0`, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp16_19
1827	`0`, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp20
1828	`0`, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp21
1829	`0`, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp22
1830	`0`, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp23
1831	`0`, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi
1832	`0`, // GPR64_with_sub_32_in_GPRMM16Zero:sub_lo
1833	`0`, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi_then_sub_32
1834	`0`, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32_sub_hi_then_sub_32
1835	},
1836	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
1837	`17`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32 -> CPU16Regs_and_GPRMM16Zero
1838	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_64
1839	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
1840	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp20
1841	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp21
1842	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp22
1843	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp23
1844	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi
1845	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_lo
1846	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
1847	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
1848	},
1849	{ // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
1850	`18`, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32 -> GPR32NONZERO_and_GPRMM16MoveP
1851	`0`, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_64
1852	`0`, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19
1853	`0`, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20
1854	`0`, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21
1855	`0`, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22
1856	`0`, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23
1857	`0`, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi
1858	`0`, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_lo
1859	`0`, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32
1860	`0`, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
1861	},
1862	{ // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
1863	`19`, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairSecond
1864	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_64
1865	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp16_19
1866	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp20
1867	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp21
1868	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp22
1869	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp23
1870	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi
1871	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_lo
1872	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi_then_sub_32
1873	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
1874	},
1875	{ // ACC64DSP
1876	`0`, // ACC64DSP:sub_32
1877	`0`, // ACC64DSP:sub_64
1878	`0`, // ACC64DSP:sub_dsp16_19
1879	`0`, // ACC64DSP:sub_dsp20
1880	`0`, // ACC64DSP:sub_dsp21
1881	`0`, // ACC64DSP:sub_dsp22
1882	`0`, // ACC64DSP:sub_dsp23
1883	`22`, // ACC64DSP:sub_hi -> HI32DSP
1884	`23`, // ACC64DSP:sub_lo -> LO32DSP
1885	`0`, // ACC64DSP:sub_hi_then_sub_32
1886	`0`, // ACC64DSP:sub_32_sub_hi_then_sub_32
1887	},
1888	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
1889	`20`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32 -> CPU16Regs_and_GPRMM16MoveP
1890	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_64
1891	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19
1892	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp20
1893	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp21
1894	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp22
1895	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp23
1896	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi
1897	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_lo
1898	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32
1899	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
1900	},
1901	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
1902	`21`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_GPRMM16Zero
1903	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_64
1904	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19
1905	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20
1906	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21
1907	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22
1908	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23
1909	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi
1910	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_lo
1911	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32
1912	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
1913	},
1914	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
1915	`24`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32 -> CPU16Regs_and_GPRMM16MovePPairSecond
1916	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_64
1917	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19
1918	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20
1919	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21
1920	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22
1921	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23
1922	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi
1923	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo
1924	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
1925	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
1926	},
1927	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
1928	`25`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32 -> GPRMM16MovePPairFirst
1929	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_64
1930	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp16_19
1931	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp20
1932	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp21
1933	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp22
1934	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp23
1935	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi
1936	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_lo
1937	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi_then_sub_32
1938	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32
1939	},
1940	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
1941	`26`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
1942	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64
1943	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
1944	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20
1945	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21
1946	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22
1947	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23
1948	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi
1949	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo
1950	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
1951	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
1952	},
1953	{ // OCTEON_MPL
1954	`0`, // OCTEON_MPL:sub_32
1955	`0`, // OCTEON_MPL:sub_64
1956	`0`, // OCTEON_MPL:sub_dsp16_19
1957	`0`, // OCTEON_MPL:sub_dsp20
1958	`0`, // OCTEON_MPL:sub_dsp21
1959	`0`, // OCTEON_MPL:sub_dsp22
1960	`0`, // OCTEON_MPL:sub_dsp23
1961	`0`, // OCTEON_MPL:sub_hi
1962	`0`, // OCTEON_MPL:sub_lo
1963	`0`, // OCTEON_MPL:sub_hi_then_sub_32
1964	`0`, // OCTEON_MPL:sub_32_sub_hi_then_sub_32
1965	},
1966	{ // OCTEON_P
1967	`0`, // OCTEON_P:sub_32
1968	`0`, // OCTEON_P:sub_64
1969	`0`, // OCTEON_P:sub_dsp16_19
1970	`0`, // OCTEON_P:sub_dsp20
1971	`0`, // OCTEON_P:sub_dsp21
1972	`0`, // OCTEON_P:sub_dsp22
1973	`0`, // OCTEON_P:sub_dsp23
1974	`0`, // OCTEON_P:sub_hi
1975	`0`, // OCTEON_P:sub_lo
1976	`0`, // OCTEON_P:sub_hi_then_sub_32
1977	`0`, // OCTEON_P:sub_32_sub_hi_then_sub_32
1978	},
1979	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
1980	`27`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
1981	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64
1982	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19
1983	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20
1984	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21
1985	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22
1986	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23
1987	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi
1988	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo
1989	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
1990	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
1991	},
1992	{ // ACC64
1993	`0`, // ACC64:sub_32
1994	`0`, // ACC64:sub_64
1995	`0`, // ACC64:sub_dsp16_19
1996	`0`, // ACC64:sub_dsp20
1997	`0`, // ACC64:sub_dsp21
1998	`0`, // ACC64:sub_dsp22
1999	`0`, // ACC64:sub_dsp23
2000	`33`, // ACC64:sub_hi -> HI32
2001	`34`, // ACC64:sub_lo -> LO32
2002	`0`, // ACC64:sub_hi_then_sub_32
2003	`0`, // ACC64:sub_32_sub_hi_then_sub_32
2004	},
2005	{ // GP64
2006	`31`, // GP64:sub_32 -> GP32
2007	`0`, // GP64:sub_64
2008	`0`, // GP64:sub_dsp16_19
2009	`0`, // GP64:sub_dsp20
2010	`0`, // GP64:sub_dsp21
2011	`0`, // GP64:sub_dsp22
2012	`0`, // GP64:sub_dsp23
2013	`0`, // GP64:sub_hi
2014	`0`, // GP64:sub_lo
2015	`0`, // GP64:sub_hi_then_sub_32
2016	`0`, // GP64:sub_32_sub_hi_then_sub_32
2017	},
2018	{ // GPR64_with_sub_32_in_CPURAReg
2019	`28`, // GPR64_with_sub_32_in_CPURAReg:sub_32 -> CPURAReg
2020	`0`, // GPR64_with_sub_32_in_CPURAReg:sub_64
2021	`0`, // GPR64_with_sub_32_in_CPURAReg:sub_dsp16_19
2022	`0`, // GPR64_with_sub_32_in_CPURAReg:sub_dsp20
2023	`0`, // GPR64_with_sub_32_in_CPURAReg:sub_dsp21
2024	`0`, // GPR64_with_sub_32_in_CPURAReg:sub_dsp22
2025	`0`, // GPR64_with_sub_32_in_CPURAReg:sub_dsp23
2026	`0`, // GPR64_with_sub_32_in_CPURAReg:sub_hi
2027	`0`, // GPR64_with_sub_32_in_CPURAReg:sub_lo
2028	`0`, // GPR64_with_sub_32_in_CPURAReg:sub_hi_then_sub_32
2029	`0`, // GPR64_with_sub_32_in_CPURAReg:sub_32_sub_hi_then_sub_32
2030	},
2031	{ // GPR64_with_sub_32_in_GPR32ZERO
2032	`32`, // GPR64_with_sub_32_in_GPR32ZERO:sub_32 -> GPR32ZERO
2033	`0`, // GPR64_with_sub_32_in_GPR32ZERO:sub_64
2034	`0`, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp16_19
2035	`0`, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp20
2036	`0`, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp21
2037	`0`, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp22
2038	`0`, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp23
2039	`0`, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi
2040	`0`, // GPR64_with_sub_32_in_GPR32ZERO:sub_lo
2041	`0`, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi_then_sub_32
2042	`0`, // GPR64_with_sub_32_in_GPR32ZERO:sub_32_sub_hi_then_sub_32
2043	},
2044	{ // HI64
2045	`33`, // HI64:sub_32 -> HI32
2046	`0`, // HI64:sub_64
2047	`0`, // HI64:sub_dsp16_19
2048	`0`, // HI64:sub_dsp20
2049	`0`, // HI64:sub_dsp21
2050	`0`, // HI64:sub_dsp22
2051	`0`, // HI64:sub_dsp23
2052	`0`, // HI64:sub_hi
2053	`0`, // HI64:sub_lo
2054	`0`, // HI64:sub_hi_then_sub_32
2055	`0`, // HI64:sub_32_sub_hi_then_sub_32
2056	},
2057	{ // LO64
2058	`34`, // LO64:sub_32 -> LO32
2059	`0`, // LO64:sub_64
2060	`0`, // LO64:sub_dsp16_19
2061	`0`, // LO64:sub_dsp20
2062	`0`, // LO64:sub_dsp21
2063	`0`, // LO64:sub_dsp22
2064	`0`, // LO64:sub_dsp23
2065	`0`, // LO64:sub_hi
2066	`0`, // LO64:sub_lo
2067	`0`, // LO64:sub_hi_then_sub_32
2068	`0`, // LO64:sub_32_sub_hi_then_sub_32
2069	},
2070	{ // SP64
2071	`29`, // SP64:sub_32 -> CPUSPReg
2072	`0`, // SP64:sub_64
2073	`0`, // SP64:sub_dsp16_19
2074	`0`, // SP64:sub_dsp20
2075	`0`, // SP64:sub_dsp21
2076	`0`, // SP64:sub_dsp22
2077	`0`, // SP64:sub_dsp23
2078	`0`, // SP64:sub_hi
2079	`0`, // SP64:sub_lo
2080	`0`, // SP64:sub_hi_then_sub_32
2081	`0`, // SP64:sub_32_sub_hi_then_sub_32
2082	},
2083	{ // MSA128B
2084	`0`, // MSA128B:sub_32
2085	`36`, // MSA128B:sub_64 -> FGR64
2086	`0`, // MSA128B:sub_dsp16_19
2087	`0`, // MSA128B:sub_dsp20
2088	`0`, // MSA128B:sub_dsp21
2089	`0`, // MSA128B:sub_dsp22
2090	`0`, // MSA128B:sub_dsp23
2091	`0`, // MSA128B:sub_hi
2092	`6`, // MSA128B:sub_lo -> FGR32
2093	`0`, // MSA128B:sub_hi_then_sub_32
2094	`0`, // MSA128B:sub_32_sub_hi_then_sub_32
2095	},
2096	{ // MSA128D
2097	`0`, // MSA128D:sub_32
2098	`36`, // MSA128D:sub_64 -> FGR64
2099	`0`, // MSA128D:sub_dsp16_19
2100	`0`, // MSA128D:sub_dsp20
2101	`0`, // MSA128D:sub_dsp21
2102	`0`, // MSA128D:sub_dsp22
2103	`0`, // MSA128D:sub_dsp23
2104	`0`, // MSA128D:sub_hi
2105	`6`, // MSA128D:sub_lo -> FGR32
2106	`0`, // MSA128D:sub_hi_then_sub_32
2107	`0`, // MSA128D:sub_32_sub_hi_then_sub_32
2108	},
2109	{ // MSA128H
2110	`0`, // MSA128H:sub_32
2111	`36`, // MSA128H:sub_64 -> FGR64
2112	`0`, // MSA128H:sub_dsp16_19
2113	`0`, // MSA128H:sub_dsp20
2114	`0`, // MSA128H:sub_dsp21
2115	`0`, // MSA128H:sub_dsp22
2116	`0`, // MSA128H:sub_dsp23
2117	`0`, // MSA128H:sub_hi
2118	`6`, // MSA128H:sub_lo -> FGR32
2119	`0`, // MSA128H:sub_hi_then_sub_32
2120	`0`, // MSA128H:sub_32_sub_hi_then_sub_32
2121	},
2122	{ // MSA128W
2123	`0`, // MSA128W:sub_32
2124	`36`, // MSA128W:sub_64 -> FGR64
2125	`0`, // MSA128W:sub_dsp16_19
2126	`0`, // MSA128W:sub_dsp20
2127	`0`, // MSA128W:sub_dsp21
2128	`0`, // MSA128W:sub_dsp22
2129	`0`, // MSA128W:sub_dsp23
2130	`0`, // MSA128W:sub_hi
2131	`6`, // MSA128W:sub_lo -> FGR32
2132	`0`, // MSA128W:sub_hi_then_sub_32
2133	`0`, // MSA128W:sub_32_sub_hi_then_sub_32
2134	},
2135	{ // MSA128WEvens
2136	`0`, // MSA128WEvens:sub_32
2137	`36`, // MSA128WEvens:sub_64 -> FGR64
2138	`0`, // MSA128WEvens:sub_dsp16_19
2139	`0`, // MSA128WEvens:sub_dsp20
2140	`0`, // MSA128WEvens:sub_dsp21
2141	`0`, // MSA128WEvens:sub_dsp22
2142	`0`, // MSA128WEvens:sub_dsp23
2143	`0`, // MSA128WEvens:sub_hi
2144	`6`, // MSA128WEvens:sub_lo -> FGR32
2145	`0`, // MSA128WEvens:sub_hi_then_sub_32
2146	`0`, // MSA128WEvens:sub_32_sub_hi_then_sub_32
2147	},
2148	{ // ACC128
2149	`34`, // ACC128:sub_32 -> LO32
2150	`0`, // ACC128:sub_64
2151	`0`, // ACC128:sub_dsp16_19
2152	`0`, // ACC128:sub_dsp20
2153	`0`, // ACC128:sub_dsp21
2154	`0`, // ACC128:sub_dsp22
2155	`0`, // ACC128:sub_dsp23
2156	`60`, // ACC128:sub_hi -> HI64
2157	`61`, // ACC128:sub_lo -> LO64
2158	`33`, // ACC128:sub_hi_then_sub_32 -> HI32
2159	`56`, // ACC128:sub_32_sub_hi_then_sub_32 -> ACC64
2160	},
2161
2162	};
2163	assert(RC && "Missing regclass");
2164	if (!Idx) return RC;
2165	--Idx;
2166	assert(Idx < `11` && "Bad subreg");
2167	unsigned TV = Table[RC->getID()][Idx];
2168	return TV ? getRegClass(i: TV - `1`) : nullptr;
2169	}/// Get the weight in units of pressure for this register class.
2170	const RegClassWeight &MipsGenRegisterInfo::
2171	getRegClassWeight(const TargetRegisterClass RC) const* {
2172	static const RegClassWeight RCWeightTable[] = {
2173	{.RegWeight: `0`, .WeightLimit: `0`}, // CCR
2174	{.RegWeight: `0`, .WeightLimit: `0`}, // COP0
2175	{.RegWeight: `0`, .WeightLimit: `0`}, // COP2
2176	{.RegWeight: `0`, .WeightLimit: `0`}, // COP3
2177	{.RegWeight: `1`, .WeightLimit: `32`}, // DSPR
2178	{.RegWeight: `1`, .WeightLimit: `32`}, // FGR32
2179	{.RegWeight: `1`, .WeightLimit: `32`}, // GPR32
2180	{.RegWeight: `0`, .WeightLimit: `0`}, // HWRegs
2181	{.RegWeight: `0`, .WeightLimit: `0`}, // MSACtrl
2182	{.RegWeight: `1`, .WeightLimit: `31`}, // GPR32NONZERO
2183	{.RegWeight: `1`, .WeightLimit: `9`}, // CPU16RegsPlusSP
2184	{.RegWeight: `1`, .WeightLimit: `8`}, // CPU16Regs
2185	{.RegWeight: `0`, .WeightLimit: `0`}, // FCC
2186	{.RegWeight: `1`, .WeightLimit: `8`}, // GPRMM16
2187	{.RegWeight: `1`, .WeightLimit: `8`}, // GPRMM16MoveP
2188	{.RegWeight: `1`, .WeightLimit: `8`}, // GPRMM16Zero
2189	{.RegWeight: `1`, .WeightLimit: `7`}, // CPU16Regs_and_GPRMM16Zero
2190	{.RegWeight: `1`, .WeightLimit: `7`}, // GPR32NONZERO_and_GPRMM16MoveP
2191	{.RegWeight: `1`, .WeightLimit: `5`}, // GPRMM16MovePPairSecond
2192	{.RegWeight: `1`, .WeightLimit: `4`}, // CPU16Regs_and_GPRMM16MoveP
2193	{.RegWeight: `1`, .WeightLimit: `4`}, // GPRMM16MoveP_and_GPRMM16Zero
2194	{.RegWeight: `1`, .WeightLimit: `4`}, // HI32DSP
2195	{.RegWeight: `1`, .WeightLimit: `4`}, // LO32DSP
2196	{.RegWeight: `1`, .WeightLimit: `3`}, // CPU16Regs_and_GPRMM16MovePPairSecond
2197	{.RegWeight: `1`, .WeightLimit: `3`}, // GPRMM16MovePPairFirst
2198	{.RegWeight: `1`, .WeightLimit: `3`}, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
2199	{.RegWeight: `1`, .WeightLimit: `2`}, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
2200	{.RegWeight: `1`, .WeightLimit: `1`}, // CPURAReg
2201	{.RegWeight: `1`, .WeightLimit: `1`}, // CPUSPReg
2202	{.RegWeight: `1`, .WeightLimit: `1`}, // DSPCC
2203	{.RegWeight: `1`, .WeightLimit: `1`}, // GP32
2204	{.RegWeight: `1`, .WeightLimit: `1`}, // GPR32ZERO
2205	{.RegWeight: `1`, .WeightLimit: `1`}, // HI32
2206	{.RegWeight: `1`, .WeightLimit: `1`}, // LO32
2207	{.RegWeight: `1`, .WeightLimit: `1`}, // SP32
2208	{.RegWeight: `2`, .WeightLimit: `64`}, // FGR64
2209	{.RegWeight: `1`, .WeightLimit: `32`}, // GPR64
2210	{.RegWeight: `1`, .WeightLimit: `31`}, // GPR64_with_sub_32_in_GPR32NONZERO
2211	{.RegWeight: `2`, .WeightLimit: `32`}, // AFGR64
2212	{.RegWeight: `1`, .WeightLimit: `9`}, // GPR64_with_sub_32_in_CPU16RegsPlusSP
2213	{.RegWeight: `1`, .WeightLimit: `8`}, // GPR64_with_sub_32_in_CPU16Regs
2214	{.RegWeight: `1`, .WeightLimit: `8`}, // GPR64_with_sub_32_in_GPRMM16MoveP
2215	{.RegWeight: `1`, .WeightLimit: `8`}, // GPR64_with_sub_32_in_GPRMM16Zero
2216	{.RegWeight: `1`, .WeightLimit: `7`}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
2217	{.RegWeight: `1`, .WeightLimit: `7`}, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
2218	{.RegWeight: `1`, .WeightLimit: `5`}, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
2219	{.RegWeight: `2`, .WeightLimit: `8`}, // ACC64DSP
2220	{.RegWeight: `1`, .WeightLimit: `4`}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
2221	{.RegWeight: `1`, .WeightLimit: `4`}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
2222	{.RegWeight: `1`, .WeightLimit: `3`}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
2223	{.RegWeight: `1`, .WeightLimit: `3`}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
2224	{.RegWeight: `1`, .WeightLimit: `3`}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
2225	{.RegWeight: `0`, .WeightLimit: `0`}, // OCTEON_MPL
2226	{.RegWeight: `0`, .WeightLimit: `0`}, // OCTEON_P
2227	{.RegWeight: `1`, .WeightLimit: `2`}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
2228	{.RegWeight: `2`, .WeightLimit: `2`}, // ACC64
2229	{.RegWeight: `1`, .WeightLimit: `1`}, // GP64
2230	{.RegWeight: `1`, .WeightLimit: `1`}, // GPR64_with_sub_32_in_CPURAReg
2231	{.RegWeight: `1`, .WeightLimit: `1`}, // GPR64_with_sub_32_in_GPR32ZERO
2232	{.RegWeight: `1`, .WeightLimit: `1`}, // HI64
2233	{.RegWeight: `1`, .WeightLimit: `1`}, // LO64
2234	{.RegWeight: `1`, .WeightLimit: `1`}, // SP64
2235	{.RegWeight: `2`, .WeightLimit: `64`}, // MSA128B
2236	{.RegWeight: `2`, .WeightLimit: `64`}, // MSA128D
2237	{.RegWeight: `2`, .WeightLimit: `64`}, // MSA128H
2238	{.RegWeight: `2`, .WeightLimit: `64`}, // MSA128W
2239	{.RegWeight: `2`, .WeightLimit: `32`}, // MSA128WEvens
2240	{.RegWeight: `2`, .WeightLimit: `2`}, // ACC128
2241	};
2242	return RCWeightTable[RC->getID()];
2243	}
2244
2245	/// Get the weight in units of pressure for this register unit.
2246	unsigned MipsGenRegisterInfo::
2247	getRegUnitWeight(MCRegUnit RegUnit) const {
2248	assert(static_cast<unsigned>(RegUnit) < `321` && "invalid register unit");
2249	// All register units have unit weight.
2250	return `1`;
2251	}
2252
2253
2254	// Get the number of dimensions of register pressure.
2255	unsigned MipsGenRegisterInfo::getNumRegPressureSets() const {
2256	return `20`;
2257	}
2258
2259	// Get the name of this register unit pressure set.
2260	const char *MipsGenRegisterInfo::
2261	getRegPressureSetName(unsigned Idx) const {
2262	static const char *PressureNameTable[] = {
2263	"DSPCC",
2264	"GPR32ZERO",
2265	"GPR64_with_sub_32_in_CPURAReg",
2266	"HI32",
2267	"GPRMM16MovePPairFirst",
2268	"CPU16Regs_and_GPRMM16MoveP",
2269	"HI32DSP",
2270	"LO32DSP",
2271	"GPRMM16MovePPairSecond",
2272	"GPRMM16MoveP",
2273	"ACC64DSP",
2274	"CPU16Regs",
2275	"GPRMM16Zero_with_GPRMM16MovePPairSecond",
2276	"CPU16Regs_with_GPRMM16MovePPairSecond",
2277	"CPU16Regs_with_GPRMM16MoveP",
2278	"DSPR",
2279	"FGR32",
2280	"MSA128WEvens",
2281	"FGR32_with_MSA128WEvens",
2282	"FGR64",
2283	};
2284	return PressureNameTable[Idx];
2285	}
2286
2287	// Get the register unit pressure limit for this dimension.
2288	// This limit must be adjusted dynamically for reserved registers.
2289	unsigned MipsGenRegisterInfo::
2290	getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
2291	static const uint8_t PressureLimitTable[] = {
2292	`1`, // 0: DSPCC
2293	`1`, // 1: GPR32ZERO
2294	`1`, // 2: GPR64_with_sub_32_in_CPURAReg
2295	`2`, // 3: HI32
2296	`3`, // 4: GPRMM16MovePPairFirst
2297	`5`, // 5: CPU16Regs_and_GPRMM16MoveP
2298	`5`, // 6: HI32DSP
2299	`5`, // 7: LO32DSP
2300	`6`, // 8: GPRMM16MovePPairSecond
2301	`8`, // 9: GPRMM16MoveP
2302	`8`, // 10: ACC64DSP
2303	`10`, // 11: CPU16Regs
2304	`10`, // 12: GPRMM16Zero_with_GPRMM16MovePPairSecond
2305	`11`, // 13: CPU16Regs_with_GPRMM16MovePPairSecond
2306	`13`, // 14: CPU16Regs_with_GPRMM16MoveP
2307	`32`, // 15: DSPR
2308	`32`, // 16: FGR32
2309	`32`, // 17: MSA128WEvens
2310	`48`, // 18: FGR32_with_MSA128WEvens
2311	`64`, // 19: FGR64
2312	};
2313	return PressureLimitTable[Idx];
2314	}
2315
2316	/// Get the register class for this pressure set with the largest
2317	/// `RegClassWeight::WeightLimit`.
2318	const TargetRegisterClass *MipsGenRegisterInfo::
2319	getLargestRegClassForRegPressureSet(unsigned Idx) const {
2320	static const uint8_t PSetRegClassTable[] = {
2321	Mips::DSPCCRegClassID, // 0: DSPCC
2322	Mips::GPR32ZERORegClassID, // 1: GPR32ZERO
2323	Mips::GPR64_with_sub_32_in_CPURARegRegClassID, // 2: GPR64_with_sub_32_in_CPURAReg
2324	Mips::ACC64RegClassID, // 3: HI32
2325	Mips::GPRMM16MovePPairFirstRegClassID, // 4: GPRMM16MovePPairFirst
2326	Mips::CPU16Regs_and_GPRMM16MovePRegClassID, // 5: CPU16Regs_and_GPRMM16MoveP
2327	Mips::HI32DSPRegClassID, // 6: HI32DSP
2328	Mips::LO32DSPRegClassID, // 7: LO32DSP
2329	Mips::GPRMM16MovePPairSecondRegClassID, // 8: GPRMM16MovePPairSecond
2330	Mips::GPRMM16MovePRegClassID, // 9: GPRMM16MoveP
2331	Mips::ACC64DSPRegClassID, // 10: ACC64DSP
2332	Mips::CPU16RegsPlusSPRegClassID, // 11: CPU16Regs
2333	Mips::GPRMM16ZeroRegClassID, // 12: GPRMM16Zero_with_GPRMM16MovePPairSecond
2334	Mips::CPU16RegsPlusSPRegClassID, // 13: CPU16Regs_with_GPRMM16MovePPairSecond
2335	Mips::CPU16RegsPlusSPRegClassID, // 14: CPU16Regs_with_GPRMM16MoveP
2336	Mips::DSPRRegClassID, // 15: DSPR
2337	Mips::FGR32RegClassID, // 16: FGR32
2338	Mips::MSA128WEvensRegClassID, // 17: MSA128WEvens
2339	Mips::FGR32RegClassID, // 18: FGR32_with_MSA128WEvens
2340	Mips::FGR64RegClassID, // 19: FGR64
2341	};
2342	return getRegClass(i: PSetRegClassTable[Idx]);
2343	}
2344
2345	/// Table of pressure sets per register class or unit.
2346	static const int RCSetsTable[] = {
2347	/ 0 / `0`, -`1`,
2348	/ 2 / `6`, `10`, -`1`,
2349	/ 5 / `3`, `6`, `7`, `10`, -`1`,
2350	/ 10 / `2`, `15`, -`1`,
2351	/ 13 / `8`, `12`, `13`, `15`, -`1`,
2352	/ 18 / `9`, `14`, `15`, -`1`,
2353	/ 22 / `1`, `5`, `9`, `11`, `12`, `14`, `15`, -`1`,
2354	/ 30 / `5`, `9`, `11`, `13`, `14`, `15`, -`1`,
2355	/ 37 / `4`, `8`, `11`, `12`, `13`, `14`, `15`, -`1`,
2356	/ 45 / `5`, `9`, `11`, `12`, `13`, `14`, `15`, -`1`,
2357	/ 53 / `16`, `18`, `19`, -`1`,
2358	/ 57 / `16`, `17`, `18`, `19`, -`1`,
2359	};
2360
2361	/// Get the dimensions of register pressure impacted by this register class.
2362	/// Returns a -1 terminated array of pressure set IDs
2363	const int *MipsGenRegisterInfo::
2364	getRegClassPressureSets(const TargetRegisterClass RC) const* {
2365	static const uint8_t RCSetStartTable[] = {
2366	`1`,`1`,`1`,`1`,`11`,`53`,`11`,`1`,`1`,`11`,`32`,`32`,`1`,`32`,`18`,`25`,`39`,`18`,`13`,`30`,`23`,`2`,`7`,`38`,`37`,`45`,`37`,`1`,`1`,`0`,`1`,`22`,`5`,`5`,`1`,`55`,`11`,`11`,`53`,`32`,`32`,`18`,`25`,`39`,`18`,`13`,`3`,`30`,`23`,`38`,`37`,`45`,`1`,`1`,`37`,`5`,`1`,`10`,`22`,`5`,`5`,`1`,`55`,`55`,`55`,`55`,`58`,`5`,};
2367	return &RCSetsTable[RCSetStartTable[RC->getID()]];
2368	}
2369
2370	/// Get the dimensions of register pressure impacted by this register unit.
2371	/// Returns a -1 terminated array of pressure set IDs
2372	const int *MipsGenRegisterInfo::
2373	getRegUnitPressureSets(MCRegUnit RegUnit) const {
2374	assert(static_cast<unsigned>(RegUnit) < `321` && "invalid register unit");
2375	static const uint8_t RUSetStartTable[] = {
2376	`0`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`5`,`5`,`7`,`2`,`7`,`2`,`7`,`2`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`22`,`11`,`45`,`45`,`37`,`37`,`37`,`38`,`11`,`11`,`11`,`11`,`11`,`11`,`11`,`11`,`30`,`45`,`18`,`18`,`18`,`13`,`13`,`11`,`11`,`11`,`11`,`11`,`11`,`32`,`11`,`10`,};
2377	return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
2378	}
2379
2380	ArrayRef<MCPhysReg> MipsGenRegisterInfo::getRawAllocationOrder(const TargetRegisterClass &RC, const MachineFunction &MF, bool Rev) const {
2381	switch (RC.getID()) {
2382	case Mips::FGR32RegClassID:
2383	return FGR32GetRawAllocationOrder(RC, MF, Rev);
2384	case Mips::FGR64RegClassID:
2385	return FGR64GetRawAllocationOrder(RC, MF, Rev);
2386	}
2387	return RC.getRegisters();
2388	}
2389
2390
2391	// Register to minimal register class mapping
2392
2393	const TargetRegisterClass MipsGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const* {
2394	static const uint16_t InvalidRegClassID = UINT16_MAX;
2395
2396	static const uint16_t Mapping[`442`] = {
2397	InvalidRegClassID, // NoRegister
2398	Mips::DSPCCRegClassID, // DSPCCond
2399	InvalidRegClassID, // DSPCarry
2400	InvalidRegClassID, // DSPEFI
2401	InvalidRegClassID, // DSPOutFlag
2402	InvalidRegClassID, // DSPPos
2403	InvalidRegClassID, // DSPSCount
2404	Mips::MSACtrlRegClassID, // MSAAccess
2405	Mips::MSACtrlRegClassID, // MSACSR
2406	Mips::MSACtrlRegClassID, // MSAIR
2407	Mips::MSACtrlRegClassID, // MSAMap
2408	Mips::MSACtrlRegClassID, // MSAModify
2409	Mips::MSACtrlRegClassID, // MSARequest
2410	Mips::MSACtrlRegClassID, // MSASave
2411	Mips::MSACtrlRegClassID, // MSAUnmap
2412	InvalidRegClassID, // PC
2413	Mips::ACC64RegClassID, // AC0
2414	Mips::ACC64DSPRegClassID, // AC1
2415	Mips::ACC64DSPRegClassID, // AC2
2416	Mips::ACC64DSPRegClassID, // AC3
2417	Mips::COP0RegClassID, // COP00
2418	Mips::COP0RegClassID, // COP01
2419	Mips::COP0RegClassID, // COP02
2420	Mips::COP0RegClassID, // COP03
2421	Mips::COP0RegClassID, // COP04
2422	Mips::COP0RegClassID, // COP05
2423	Mips::COP0RegClassID, // COP06
2424	Mips::COP0RegClassID, // COP07
2425	Mips::COP0RegClassID, // COP08
2426	Mips::COP0RegClassID, // COP09
2427	Mips::COP2RegClassID, // COP20
2428	Mips::COP2RegClassID, // COP21
2429	Mips::COP2RegClassID, // COP22
2430	Mips::COP2RegClassID, // COP23
2431	Mips::COP2RegClassID, // COP24
2432	Mips::COP2RegClassID, // COP25
2433	Mips::COP2RegClassID, // COP26
2434	Mips::COP2RegClassID, // COP27
2435	Mips::COP2RegClassID, // COP28
2436	Mips::COP2RegClassID, // COP29
2437	Mips::COP3RegClassID, // COP30
2438	Mips::COP3RegClassID, // COP31
2439	Mips::COP3RegClassID, // COP32
2440	Mips::COP3RegClassID, // COP33
2441	Mips::COP3RegClassID, // COP34
2442	Mips::COP3RegClassID, // COP35
2443	Mips::COP3RegClassID, // COP36
2444	Mips::COP3RegClassID, // COP37
2445	Mips::COP3RegClassID, // COP38
2446	Mips::COP3RegClassID, // COP39
2447	Mips::COP0RegClassID, // COP010
2448	Mips::COP0RegClassID, // COP011
2449	Mips::COP0RegClassID, // COP012
2450	Mips::COP0RegClassID, // COP013
2451	Mips::COP0RegClassID, // COP014
2452	Mips::COP0RegClassID, // COP015
2453	Mips::COP0RegClassID, // COP016
2454	Mips::COP0RegClassID, // COP017
2455	Mips::COP0RegClassID, // COP018
2456	Mips::COP0RegClassID, // COP019
2457	Mips::COP0RegClassID, // COP020
2458	Mips::COP0RegClassID, // COP021
2459	Mips::COP0RegClassID, // COP022
2460	Mips::COP0RegClassID, // COP023
2461	Mips::COP0RegClassID, // COP024
2462	Mips::COP0RegClassID, // COP025
2463	Mips::COP0RegClassID, // COP026
2464	Mips::COP0RegClassID, // COP027
2465	Mips::COP0RegClassID, // COP028
2466	Mips::COP0RegClassID, // COP029
2467	Mips::COP0RegClassID, // COP030
2468	Mips::COP0RegClassID, // COP031
2469	Mips::COP2RegClassID, // COP210
2470	Mips::COP2RegClassID, // COP211
2471	Mips::COP2RegClassID, // COP212
2472	Mips::COP2RegClassID, // COP213
2473	Mips::COP2RegClassID, // COP214
2474	Mips::COP2RegClassID, // COP215
2475	Mips::COP2RegClassID, // COP216
2476	Mips::COP2RegClassID, // COP217
2477	Mips::COP2RegClassID, // COP218
2478	Mips::COP2RegClassID, // COP219
2479	Mips::COP2RegClassID, // COP220
2480	Mips::COP2RegClassID, // COP221
2481	Mips::COP2RegClassID, // COP222
2482	Mips::COP2RegClassID, // COP223
2483	Mips::COP2RegClassID, // COP224
2484	Mips::COP2RegClassID, // COP225
2485	Mips::COP2RegClassID, // COP226
2486	Mips::COP2RegClassID, // COP227
2487	Mips::COP2RegClassID, // COP228
2488	Mips::COP2RegClassID, // COP229
2489	Mips::COP2RegClassID, // COP230
2490	Mips::COP2RegClassID, // COP231
2491	Mips::COP3RegClassID, // COP310
2492	Mips::COP3RegClassID, // COP311
2493	Mips::COP3RegClassID, // COP312
2494	Mips::COP3RegClassID, // COP313
2495	Mips::COP3RegClassID, // COP314
2496	Mips::COP3RegClassID, // COP315
2497	Mips::COP3RegClassID, // COP316
2498	Mips::COP3RegClassID, // COP317
2499	Mips::COP3RegClassID, // COP318
2500	Mips::COP3RegClassID, // COP319
2501	Mips::COP3RegClassID, // COP320
2502	Mips::COP3RegClassID, // COP321
2503	Mips::COP3RegClassID, // COP322
2504	Mips::COP3RegClassID, // COP323
2505	Mips::COP3RegClassID, // COP324
2506	Mips::COP3RegClassID, // COP325
2507	Mips::COP3RegClassID, // COP326
2508	Mips::COP3RegClassID, // COP327
2509	Mips::COP3RegClassID, // COP328
2510	Mips::COP3RegClassID, // COP329
2511	Mips::COP3RegClassID, // COP330
2512	Mips::COP3RegClassID, // COP331
2513	Mips::AFGR64RegClassID, // D0
2514	Mips::AFGR64RegClassID, // D1
2515	Mips::AFGR64RegClassID, // D2
2516	Mips::AFGR64RegClassID, // D3
2517	Mips::AFGR64RegClassID, // D4
2518	Mips::AFGR64RegClassID, // D5
2519	Mips::AFGR64RegClassID, // D6
2520	Mips::AFGR64RegClassID, // D7
2521	Mips::AFGR64RegClassID, // D8
2522	Mips::AFGR64RegClassID, // D9
2523	Mips::AFGR64RegClassID, // D10
2524	Mips::AFGR64RegClassID, // D11
2525	Mips::AFGR64RegClassID, // D12
2526	Mips::AFGR64RegClassID, // D13
2527	Mips::AFGR64RegClassID, // D14
2528	Mips::AFGR64RegClassID, // D15
2529	InvalidRegClassID, // DSPOutFlag20
2530	InvalidRegClassID, // DSPOutFlag21
2531	InvalidRegClassID, // DSPOutFlag22
2532	InvalidRegClassID, // DSPOutFlag23
2533	Mips::FGR32RegClassID, // F0
2534	Mips::FGR32RegClassID, // F1
2535	Mips::FGR32RegClassID, // F2
2536	Mips::FGR32RegClassID, // F3
2537	Mips::FGR32RegClassID, // F4
2538	Mips::FGR32RegClassID, // F5
2539	Mips::FGR32RegClassID, // F6
2540	Mips::FGR32RegClassID, // F7
2541	Mips::FGR32RegClassID, // F8
2542	Mips::FGR32RegClassID, // F9
2543	Mips::FGR32RegClassID, // F10
2544	Mips::FGR32RegClassID, // F11
2545	Mips::FGR32RegClassID, // F12
2546	Mips::FGR32RegClassID, // F13
2547	Mips::FGR32RegClassID, // F14
2548	Mips::FGR32RegClassID, // F15
2549	Mips::FGR32RegClassID, // F16
2550	Mips::FGR32RegClassID, // F17
2551	Mips::FGR32RegClassID, // F18
2552	Mips::FGR32RegClassID, // F19
2553	Mips::FGR32RegClassID, // F20
2554	Mips::FGR32RegClassID, // F21
2555	Mips::FGR32RegClassID, // F22
2556	Mips::FGR32RegClassID, // F23
2557	Mips::FGR32RegClassID, // F24
2558	Mips::FGR32RegClassID, // F25
2559	Mips::FGR32RegClassID, // F26
2560	Mips::FGR32RegClassID, // F27
2561	Mips::FGR32RegClassID, // F28
2562	Mips::FGR32RegClassID, // F29
2563	Mips::FGR32RegClassID, // F30
2564	Mips::FGR32RegClassID, // F31
2565	Mips::FCCRegClassID, // FCC0
2566	Mips::FCCRegClassID, // FCC1
2567	Mips::FCCRegClassID, // FCC2
2568	Mips::FCCRegClassID, // FCC3
2569	Mips::FCCRegClassID, // FCC4
2570	Mips::FCCRegClassID, // FCC5
2571	Mips::FCCRegClassID, // FCC6
2572	Mips::FCCRegClassID, // FCC7
2573	Mips::CCRRegClassID, // FCR0
2574	Mips::CCRRegClassID, // FCR1
2575	Mips::CCRRegClassID, // FCR2
2576	Mips::CCRRegClassID, // FCR3
2577	Mips::CCRRegClassID, // FCR4
2578	Mips::CCRRegClassID, // FCR5
2579	Mips::CCRRegClassID, // FCR6
2580	Mips::CCRRegClassID, // FCR7
2581	Mips::CCRRegClassID, // FCR8
2582	Mips::CCRRegClassID, // FCR9
2583	Mips::CCRRegClassID, // FCR10
2584	Mips::CCRRegClassID, // FCR11
2585	Mips::CCRRegClassID, // FCR12
2586	Mips::CCRRegClassID, // FCR13
2587	Mips::CCRRegClassID, // FCR14
2588	Mips::CCRRegClassID, // FCR15
2589	Mips::CCRRegClassID, // FCR16
2590	Mips::CCRRegClassID, // FCR17
2591	Mips::CCRRegClassID, // FCR18
2592	Mips::CCRRegClassID, // FCR19
2593	Mips::CCRRegClassID, // FCR20
2594	Mips::CCRRegClassID, // FCR21
2595	Mips::CCRRegClassID, // FCR22
2596	Mips::CCRRegClassID, // FCR23
2597	Mips::CCRRegClassID, // FCR24
2598	Mips::CCRRegClassID, // FCR25
2599	Mips::CCRRegClassID, // FCR26
2600	Mips::CCRRegClassID, // FCR27
2601	Mips::CCRRegClassID, // FCR28
2602	Mips::CCRRegClassID, // FCR29
2603	Mips::CCRRegClassID, // FCR30
2604	Mips::CCRRegClassID, // FCR31
2605	InvalidRegClassID, // F_HI0
2606	InvalidRegClassID, // F_HI1
2607	InvalidRegClassID, // F_HI2
2608	InvalidRegClassID, // F_HI3
2609	InvalidRegClassID, // F_HI4
2610	InvalidRegClassID, // F_HI5
2611	InvalidRegClassID, // F_HI6
2612	InvalidRegClassID, // F_HI7
2613	InvalidRegClassID, // F_HI8
2614	InvalidRegClassID, // F_HI9
2615	InvalidRegClassID, // F_HI10
2616	InvalidRegClassID, // F_HI11
2617	InvalidRegClassID, // F_HI12
2618	InvalidRegClassID, // F_HI13
2619	InvalidRegClassID, // F_HI14
2620	InvalidRegClassID, // F_HI15
2621	InvalidRegClassID, // F_HI16
2622	InvalidRegClassID, // F_HI17
2623	InvalidRegClassID, // F_HI18
2624	InvalidRegClassID, // F_HI19
2625	InvalidRegClassID, // F_HI20
2626	InvalidRegClassID, // F_HI21
2627	InvalidRegClassID, // F_HI22
2628	InvalidRegClassID, // F_HI23
2629	InvalidRegClassID, // F_HI24
2630	InvalidRegClassID, // F_HI25
2631	InvalidRegClassID, // F_HI26
2632	InvalidRegClassID, // F_HI27
2633	InvalidRegClassID, // F_HI28
2634	InvalidRegClassID, // F_HI29
2635	InvalidRegClassID, // F_HI30
2636	InvalidRegClassID, // F_HI31
2637	Mips::HI32RegClassID, // HI0
2638	Mips::HI32DSPRegClassID, // HI1
2639	Mips::HI32DSPRegClassID, // HI2
2640	Mips::HI32DSPRegClassID, // HI3
2641	Mips::HWRegsRegClassID, // HWR0
2642	Mips::HWRegsRegClassID, // HWR1
2643	Mips::HWRegsRegClassID, // HWR2
2644	Mips::HWRegsRegClassID, // HWR3
2645	Mips::HWRegsRegClassID, // HWR4
2646	Mips::HWRegsRegClassID, // HWR5
2647	Mips::HWRegsRegClassID, // HWR6
2648	Mips::HWRegsRegClassID, // HWR7
2649	Mips::HWRegsRegClassID, // HWR8
2650	Mips::HWRegsRegClassID, // HWR9
2651	Mips::HWRegsRegClassID, // HWR10
2652	Mips::HWRegsRegClassID, // HWR11
2653	Mips::HWRegsRegClassID, // HWR12
2654	Mips::HWRegsRegClassID, // HWR13
2655	Mips::HWRegsRegClassID, // HWR14
2656	Mips::HWRegsRegClassID, // HWR15
2657	Mips::HWRegsRegClassID, // HWR16
2658	Mips::HWRegsRegClassID, // HWR17
2659	Mips::HWRegsRegClassID, // HWR18
2660	Mips::HWRegsRegClassID, // HWR19
2661	Mips::HWRegsRegClassID, // HWR20
2662	Mips::HWRegsRegClassID, // HWR21
2663	Mips::HWRegsRegClassID, // HWR22
2664	Mips::HWRegsRegClassID, // HWR23
2665	Mips::HWRegsRegClassID, // HWR24
2666	Mips::HWRegsRegClassID, // HWR25
2667	Mips::HWRegsRegClassID, // HWR26
2668	Mips::HWRegsRegClassID, // HWR27
2669	Mips::HWRegsRegClassID, // HWR28
2670	Mips::HWRegsRegClassID, // HWR29
2671	Mips::HWRegsRegClassID, // HWR30
2672	Mips::HWRegsRegClassID, // HWR31
2673	Mips::LO32RegClassID, // LO0
2674	Mips::LO32DSPRegClassID, // LO1
2675	Mips::LO32DSPRegClassID, // LO2
2676	Mips::LO32DSPRegClassID, // LO3
2677	Mips::OCTEON_MPLRegClassID, // MPL0
2678	Mips::OCTEON_MPLRegClassID, // MPL1
2679	Mips::OCTEON_MPLRegClassID, // MPL2
2680	Mips::MSACtrlRegClassID, // MSA8
2681	Mips::MSACtrlRegClassID, // MSA9
2682	Mips::MSACtrlRegClassID, // MSA10
2683	Mips::MSACtrlRegClassID, // MSA11
2684	Mips::MSACtrlRegClassID, // MSA12
2685	Mips::MSACtrlRegClassID, // MSA13
2686	Mips::MSACtrlRegClassID, // MSA14
2687	Mips::MSACtrlRegClassID, // MSA15
2688	Mips::MSACtrlRegClassID, // MSA16
2689	Mips::MSACtrlRegClassID, // MSA17
2690	Mips::MSACtrlRegClassID, // MSA18
2691	Mips::MSACtrlRegClassID, // MSA19
2692	Mips::MSACtrlRegClassID, // MSA20
2693	Mips::MSACtrlRegClassID, // MSA21
2694	Mips::MSACtrlRegClassID, // MSA22
2695	Mips::MSACtrlRegClassID, // MSA23
2696	Mips::MSACtrlRegClassID, // MSA24
2697	Mips::MSACtrlRegClassID, // MSA25
2698	Mips::MSACtrlRegClassID, // MSA26
2699	Mips::MSACtrlRegClassID, // MSA27
2700	Mips::MSACtrlRegClassID, // MSA28
2701	Mips::MSACtrlRegClassID, // MSA29
2702	Mips::MSACtrlRegClassID, // MSA30
2703	Mips::MSACtrlRegClassID, // MSA31
2704	Mips::OCTEON_PRegClassID, // P0
2705	Mips::OCTEON_PRegClassID, // P1
2706	Mips::OCTEON_PRegClassID, // P2
2707	Mips::GPR32ZERORegClassID, // R0
2708	Mips::GPR32NONZERORegClassID, // R1
2709	Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, // R2
2710	Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, // R3
2711	Mips::GPRMM16MovePPairFirstRegClassID, // R4
2712	Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, // R5
2713	Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, // R6
2714	Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, // R7
2715	Mips::GPR32NONZERORegClassID, // R8
2716	Mips::GPR32NONZERORegClassID, // R9
2717	Mips::GPR32NONZERORegClassID, // R10
2718	Mips::GPR32NONZERORegClassID, // R11
2719	Mips::GPR32NONZERORegClassID, // R12
2720	Mips::GPR32NONZERORegClassID, // R13
2721	Mips::GPR32NONZERORegClassID, // R14
2722	Mips::GPR32NONZERORegClassID, // R15
2723	Mips::CPU16Regs_and_GPRMM16MovePRegClassID, // R16
2724	Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, // R17
2725	Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, // R18
2726	Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, // R19
2727	Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, // R20
2728	Mips::GPRMM16MovePPairSecondRegClassID, // R21
2729	Mips::GPRMM16MovePPairSecondRegClassID, // R22
2730	Mips::GPR32NONZERORegClassID, // R23
2731	Mips::GPR32NONZERORegClassID, // R24
2732	Mips::GPR32NONZERORegClassID, // R25
2733	Mips::GPR32NONZERORegClassID, // R26
2734	Mips::GPR32NONZERORegClassID, // R27
2735	Mips::GP32RegClassID, // R28
2736	Mips::SP32RegClassID, // R29
2737	Mips::GPR32NONZERORegClassID, // R30
2738	Mips::CPURARegRegClassID, // R31
2739	Mips::MSA128WEvensRegClassID, // W0
2740	Mips::MSA128WRegClassID, // W1
2741	Mips::MSA128WEvensRegClassID, // W2
2742	Mips::MSA128WRegClassID, // W3
2743	Mips::MSA128WEvensRegClassID, // W4
2744	Mips::MSA128WRegClassID, // W5
2745	Mips::MSA128WEvensRegClassID, // W6
2746	Mips::MSA128WRegClassID, // W7
2747	Mips::MSA128WEvensRegClassID, // W8
2748	Mips::MSA128WRegClassID, // W9
2749	Mips::MSA128WEvensRegClassID, // W10
2750	Mips::MSA128WRegClassID, // W11
2751	Mips::MSA128WEvensRegClassID, // W12
2752	Mips::MSA128WRegClassID, // W13
2753	Mips::MSA128WEvensRegClassID, // W14
2754	Mips::MSA128WRegClassID, // W15
2755	Mips::MSA128WEvensRegClassID, // W16
2756	Mips::MSA128WRegClassID, // W17
2757	Mips::MSA128WEvensRegClassID, // W18
2758	Mips::MSA128WRegClassID, // W19
2759	Mips::MSA128WEvensRegClassID, // W20
2760	Mips::MSA128WRegClassID, // W21
2761	Mips::MSA128WEvensRegClassID, // W22
2762	Mips::MSA128WRegClassID, // W23
2763	Mips::MSA128WEvensRegClassID, // W24
2764	Mips::MSA128WRegClassID, // W25
2765	Mips::MSA128WEvensRegClassID, // W26
2766	Mips::MSA128WRegClassID, // W27
2767	Mips::MSA128WEvensRegClassID, // W28
2768	Mips::MSA128WRegClassID, // W29
2769	Mips::MSA128WEvensRegClassID, // W30
2770	Mips::MSA128WRegClassID, // W31
2771	Mips::ACC128RegClassID, // AC0_64
2772	Mips::FGR64RegClassID, // D0_64
2773	Mips::FGR64RegClassID, // D1_64
2774	Mips::FGR64RegClassID, // D2_64
2775	Mips::FGR64RegClassID, // D3_64
2776	Mips::FGR64RegClassID, // D4_64
2777	Mips::FGR64RegClassID, // D5_64
2778	Mips::FGR64RegClassID, // D6_64
2779	Mips::FGR64RegClassID, // D7_64
2780	Mips::FGR64RegClassID, // D8_64
2781	Mips::FGR64RegClassID, // D9_64
2782	Mips::FGR64RegClassID, // D10_64
2783	Mips::FGR64RegClassID, // D11_64
2784	Mips::FGR64RegClassID, // D12_64
2785	Mips::FGR64RegClassID, // D13_64
2786	Mips::FGR64RegClassID, // D14_64
2787	Mips::FGR64RegClassID, // D15_64
2788	Mips::FGR64RegClassID, // D16_64
2789	Mips::FGR64RegClassID, // D17_64
2790	Mips::FGR64RegClassID, // D18_64
2791	Mips::FGR64RegClassID, // D19_64
2792	Mips::FGR64RegClassID, // D20_64
2793	Mips::FGR64RegClassID, // D21_64
2794	Mips::FGR64RegClassID, // D22_64
2795	Mips::FGR64RegClassID, // D23_64
2796	Mips::FGR64RegClassID, // D24_64
2797	Mips::FGR64RegClassID, // D25_64
2798	Mips::FGR64RegClassID, // D26_64
2799	Mips::FGR64RegClassID, // D27_64
2800	Mips::FGR64RegClassID, // D28_64
2801	Mips::FGR64RegClassID, // D29_64
2802	Mips::FGR64RegClassID, // D30_64
2803	Mips::FGR64RegClassID, // D31_64
2804	InvalidRegClassID, // DSPOutFlag16_19
2805	Mips::HI64RegClassID, // HI0_64
2806	Mips::LO64RegClassID, // LO0_64
2807	Mips::GPR64_with_sub_32_in_GPR32ZERORegClassID, // R0_64
2808	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // R1_64
2809	Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, // R2_64
2810	Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, // R3_64
2811	Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID, // R4_64
2812	Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, // R5_64
2813	Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, // R6_64
2814	Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, // R7_64
2815	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // R8_64
2816	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // R9_64
2817	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // R10_64
2818	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // R11_64
2819	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // R12_64
2820	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // R13_64
2821	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // R14_64
2822	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // R15_64
2823	Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, // R16_64
2824	Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, // R17_64
2825	Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, // R18_64
2826	Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, // R19_64
2827	Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, // R20_64
2828	Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID, // R21_64
2829	Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID, // R22_64
2830	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // R23_64
2831	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // R24_64
2832	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // R25_64
2833	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // R26_64
2834	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // R27_64
2835	Mips::GP64RegClassID, // R28_64
2836	Mips::SP64RegClassID, // R29_64
2837	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // R30_64
2838	Mips::GPR64_with_sub_32_in_CPURARegRegClassID, // R31_64
2839	};
2840
2841	assert(Reg < ArrayRef(Mapping).size());
2842	unsigned RCID = Mapping[Reg.id()];
2843	if (RCID == InvalidRegClassID)
2844	return nullptr;
2845	return &MipsMCRegisterClassStorage.Classes[RCID];
2846	}
2847	extern const MCRegisterDesc MipsRegDesc[];
2848	extern const int16_t MipsRegDiffLists[];
2849	extern const LaneBitmask MipsLaneMaskLists[];
2850	extern const char MipsRegStrings[];
2851	extern const char MipsRegClassStrings[];
2852	extern const MCPhysReg MipsRegUnitRoots[][`2`];
2853	extern const uint16_t MipsSubRegIdxLists[];
2854	extern const uint16_t MipsRegEncodingTable[];
2855	// Mips Dwarf<->LLVM register mappings.
2856	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[];
2857	extern const unsigned MipsDwarfFlavour0Dwarf2LSize;
2858
2859	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[];
2860	extern const unsigned MipsEHFlavour0Dwarf2LSize;
2861
2862	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[];
2863	extern const unsigned MipsDwarfFlavour0L2DwarfSize;
2864
2865	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[];
2866	extern const unsigned MipsEHFlavour0L2DwarfSize;
2867
2868
2869	MipsGenRegisterInfo::
2870	MipsGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
2871	unsigned PC, unsigned HwMode)
2872	: TargetRegisterInfo (&MipsRegInfoDesc,
2873	MipsSubRegIndexStrings, MipsSubRegIndexNameOffsets,
2874	MipsSubRegIdxRangeTable, MipsSubRegIndexLaneMaskTable,
2875
2876	LaneBitmask (`0xFFFFFFFFFFFFFF80`), MipsRegClassInfos, MipsVTLists, HwMode) {
2877	InitMCRegisterInfo(D: MipsRegDesc, NR: `442`, RA, PC,
2878	C: &getMipsMCRegisterClass(RC: `0`), NC: `68`, RURoots: MipsRegUnitRoots, NRU: `321`, DL: MipsRegDiffLists,
2879	RUMS: MipsLaneMaskLists, Strings: MipsRegStrings, ClassStrings: MipsRegClassStrings, SubIndices: MipsSubRegIdxLists, NumIndices: `12`,
2880	RET: MipsRegEncodingTable, RUI: nullptr);
2881
2882	switch (DwarfFlavour) {
2883	default:
2884	llvm_unreachable("Unknown DWARF flavour");
2885	case `0`:
2886	mapDwarfRegsToLLVMRegs(Map: MipsDwarfFlavour0Dwarf2L, Size: MipsDwarfFlavour0Dwarf2LSize, isEH: false);
2887	break;
2888	}
2889	switch (EHFlavour) {
2890	default:
2891	llvm_unreachable("Unknown DWARF flavour");
2892	case `0`:
2893	mapDwarfRegsToLLVMRegs(Map: MipsEHFlavour0Dwarf2L, Size: MipsEHFlavour0Dwarf2LSize, isEH: true);
2894	break;
2895	}
2896	switch (DwarfFlavour) {
2897	default:
2898	llvm_unreachable("Unknown DWARF flavour");
2899	case `0`:
2900	mapLLVMRegsToDwarfRegs(Map: MipsDwarfFlavour0L2Dwarf, Size: MipsDwarfFlavour0L2DwarfSize, isEH: false);
2901	break;
2902	}
2903	switch (EHFlavour) {
2904	default:
2905	llvm_unreachable("Unknown DWARF flavour");
2906	case `0`:
2907	mapLLVMRegsToDwarfRegs(Map: MipsEHFlavour0L2Dwarf, Size: MipsEHFlavour0L2DwarfSize, isEH: true);
2908	break;
2909	}
2910	}
2911
2912	static const MCPhysReg CSR_Interrupt_32_SaveList[] = { Mips::R7, Mips::R6, Mips::R5, Mips::R4, Mips::R23, Mips::R22, Mips::R21, Mips::R20, Mips::R19, Mips::R18, Mips::R17, Mips::R16, Mips::R3, Mips::R2, Mips::R25, Mips::R24, Mips::R15, Mips::R14, Mips::R13, Mips::R12, Mips::R11, Mips::R10, Mips::R9, Mips::R8, Mips::R31, Mips::R30, Mips::R28, Mips::R1, Mips::LO0, Mips::HI0, `0` };
2913	static const uint32_t CSR_Interrupt_32_RegMask[] = { `0x00010000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00010000`, `0x00100000`, `0xffc00000`, `0x0034ffff`, `0x00000000`, `0x04000000`, `0x00000000`, };
2914	static const MCPhysReg CSR_Interrupt_32R6_SaveList[] = { Mips::R7, Mips::R6, Mips::R5, Mips::R4, Mips::R23, Mips::R22, Mips::R21, Mips::R20, Mips::R19, Mips::R18, Mips::R17, Mips::R16, Mips::R3, Mips::R2, Mips::R25, Mips::R24, Mips::R15, Mips::R14, Mips::R13, Mips::R12, Mips::R11, Mips::R10, Mips::R9, Mips::R8, Mips::R31, Mips::R30, Mips::R28, Mips::R1, `0` };
2915	static const uint32_t CSR_Interrupt_32R6_RegMask[] = { `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0xffc00000`, `0x0034ffff`, `0x00000000`, `0x04000000`, `0x00000000`, };
2916	static const MCPhysReg CSR_Interrupt_64_SaveList[] = { Mips::R7_64, Mips::R6_64, Mips::R5_64, Mips::R4_64, Mips::R23_64, Mips::R22_64, Mips::R21_64, Mips::R20_64, Mips::R19_64, Mips::R18_64, Mips::R17_64, Mips::R16_64, Mips::R25_64, Mips::R24_64, Mips::R15_64, Mips::R14_64, Mips::R13_64, Mips::R12_64, Mips::R11_64, Mips::R10_64, Mips::R9_64, Mips::R8_64, Mips::R3_64, Mips::R2_64, Mips::R31_64, Mips::R30_64, Mips::R28_64, Mips::R1_64, Mips::LO0_64, Mips::HI0_64, `0` };
2917	static const uint32_t CSR_Interrupt_64_RegMask[] = { `0x00010000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00010000`, `0x00100000`, `0xffc00000`, `0x0034ffff`, `0x00400000`, `0xff000000`, `0x034fffff`, };
2918	static const MCPhysReg CSR_Interrupt_64R6_SaveList[] = { Mips::R7_64, Mips::R6_64, Mips::R5_64, Mips::R4_64, Mips::R3_64, Mips::R2_64, Mips::R23_64, Mips::R22_64, Mips::R21_64, Mips::R20_64, Mips::R19_64, Mips::R18_64, Mips::R17_64, Mips::R16_64, Mips::R25_64, Mips::R24_64, Mips::R15_64, Mips::R14_64, Mips::R13_64, Mips::R12_64, Mips::R11_64, Mips::R10_64, Mips::R9_64, Mips::R8_64, Mips::R31_64, Mips::R30_64, Mips::R28_64, Mips::R1_64, `0` };
2919	static const uint32_t CSR_Interrupt_64R6_RegMask[] = { `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0xffc00000`, `0x0034ffff`, `0x00000000`, `0xfc000000`, `0x034fffff`, };
2920	static const MCPhysReg CSR_Mips16RetHelper_SaveList[] = { Mips::R2, Mips::R3, Mips::R30, Mips::R7, Mips::R6, Mips::R5, Mips::R4, Mips::R23, Mips::R22, Mips::R21, Mips::R20, Mips::R19, Mips::R18, Mips::R17, Mips::R16, Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, `0` };
2921	static const uint32_t CSR_Mips16RetHelper_RegMask[] = { `0x00000000`, `0x00000000`, `0x00000000`, `0xc0000000`, `0xf000000f`, `0x000000ff`, `0x00000000`, `0x00000000`, `0x00000000`, `0x3f400000`, `0x00103fc0`, `0x00000000`, `0x04000000`, `0x00000000`, };
2922	static const MCPhysReg CSR_N32_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::R31_64, Mips::R30_64, Mips::R28_64, Mips::R23_64, Mips::R22_64, Mips::R21_64, Mips::R20_64, Mips::R19_64, Mips::R18_64, Mips::R17_64, Mips::R16_64, `0` };
2923	static const uint32_t CSR_N32_RegMask[] = { `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x50000000`, `0x00000055`, `0x00000000`, `0x00005550`, `0x00000000`, `0x00400000`, `0x00343fc0`, `0x00000000`, `0x042aa800`, `0x0343fc00`, };
2924	static const MCPhysReg CSR_N32_NoGP_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::R31_64, Mips::R30_64, Mips::R23_64, Mips::R22_64, Mips::R21_64, Mips::R20_64, Mips::R19_64, Mips::R18_64, Mips::R17_64, Mips::R16_64, `0` };
2925	static const uint32_t CSR_N32_NoGP_RegMask[] = { `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x50000000`, `0x00000055`, `0x00000000`, `0x00005550`, `0x00000000`, `0x00400000`, `0x00303fc0`, `0x00000000`, `0x042aa800`, `0x0303fc00`, };
2926	static const MCPhysReg CSR_N32_SingleFloat_SaveList[] = { Mips::F30, Mips::F28, Mips::F26, Mips::F24, Mips::F22, Mips::F20, Mips::R31_64, Mips::R30_64, Mips::R28_64, Mips::R23_64, Mips::R22_64, Mips::R21_64, Mips::R20_64, Mips::R19_64, Mips::R18_64, Mips::R17_64, Mips::R16_64, `0` };
2927	static const uint32_t CSR_N32_SingleFloat_RegMask[] = { `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x50000000`, `0x00000055`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00400000`, `0x00343fc0`, `0x00000000`, `0x04000000`, `0x0343fc00`, };
2928	static const MCPhysReg CSR_N32_SingleFloat_NoGP_SaveList[] = { Mips::F30, Mips::F28, Mips::F26, Mips::F24, Mips::F22, Mips::F20, Mips::R31_64, Mips::R30_64, Mips::R23_64, Mips::R22_64, Mips::R21_64, Mips::R20_64, Mips::R19_64, Mips::R18_64, Mips::R17_64, Mips::R16_64, `0` };
2929	static const uint32_t CSR_N32_SingleFloat_NoGP_RegMask[] = { `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x50000000`, `0x00000055`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00400000`, `0x00303fc0`, `0x00000000`, `0x04000000`, `0x0303fc00`, };
2930	static const MCPhysReg CSR_N64_SaveList[] = { Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64, Mips::D26_64, Mips::D25_64, Mips::D24_64, Mips::R31_64, Mips::R30_64, Mips::R28_64, Mips::R23_64, Mips::R22_64, Mips::R21_64, Mips::R20_64, Mips::R19_64, Mips::R18_64, Mips::R17_64, Mips::R16_64, `0` };
2931	static const uint32_t CSR_N64_RegMask[] = { `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x0000000f`, `0x000000ff`, `0x00000000`, `0x0000ff00`, `0x00000000`, `0x00400000`, `0x00343fc0`, `0x00000000`, `0x047f8000`, `0x0343fc00`, };
2932	static const MCPhysReg CSR_N64_NoGP_SaveList[] = { Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64, Mips::D26_64, Mips::D25_64, Mips::D24_64, Mips::R31_64, Mips::R30_64, Mips::R23_64, Mips::R22_64, Mips::R21_64, Mips::R20_64, Mips::R19_64, Mips::R18_64, Mips::R17_64, Mips::R16_64, `0` };
2933	static const uint32_t CSR_N64_NoGP_RegMask[] = { `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x0000000f`, `0x000000ff`, `0x00000000`, `0x0000ff00`, `0x00000000`, `0x00400000`, `0x00303fc0`, `0x00000000`, `0x047f8000`, `0x0303fc00`, };
2934	static const MCPhysReg CSR_N64_SingleFloat_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::R31_64, Mips::R30_64, Mips::R28_64, Mips::R23_64, Mips::R22_64, Mips::R21_64, Mips::R20_64, Mips::R19_64, Mips::R18_64, Mips::R17_64, Mips::R16_64, `0` };
2935	static const uint32_t CSR_N64_SingleFloat_RegMask[] = { `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x0000000f`, `0x000000ff`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00400000`, `0x00343fc0`, `0x00000000`, `0x04000000`, `0x0343fc00`, };
2936	static const MCPhysReg CSR_N64_SingleFloat_NoGP_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::R31_64, Mips::R30_64, Mips::R23_64, Mips::R22_64, Mips::R21_64, Mips::R20_64, Mips::R19_64, Mips::R18_64, Mips::R17_64, Mips::R16_64, `0` };
2937	static const uint32_t CSR_N64_SingleFloat_NoGP_RegMask[] = { `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x0000000f`, `0x000000ff`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00400000`, `0x00303fc0`, `0x00000000`, `0x04000000`, `0x0303fc00`, };
2938	static const MCPhysReg CSR_O32_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::R31, Mips::R30, Mips::R23, Mips::R22, Mips::R21, Mips::R20, Mips::R19, Mips::R18, Mips::R17, Mips::R16, `0` };
2939	static const uint32_t CSR_O32_RegMask[] = { `0x00000000`, `0x00000000`, `0x00000000`, `0xc0000000`, `0xf000000f`, `0x000000ff`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00400000`, `0x00303fc0`, `0x00000000`, `0x04000000`, `0x00000000`, };
2940	static const MCPhysReg CSR_O32_FP64_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::R31, Mips::R30, Mips::R23, Mips::R22, Mips::R21, Mips::R20, Mips::R19, Mips::R18, Mips::R17, Mips::R16, `0` };
2941	static const uint32_t CSR_O32_FP64_RegMask[] = { `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x50000000`, `0x00000055`, `0x00000000`, `0x00005550`, `0x00000000`, `0x00400000`, `0x00303fc0`, `0x00000000`, `0x042aa800`, `0x00000000`, };
2942	static const MCPhysReg CSR_O32_FPXX_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::R31, Mips::R30, Mips::R23, Mips::R22, Mips::R21, Mips::R20, Mips::R19, Mips::R18, Mips::R17, Mips::R16, `0` };
2943	static const uint32_t CSR_O32_FPXX_RegMask[] = { `0x00000000`, `0x00000000`, `0x00000000`, `0xc0000000`, `0xf000000f`, `0x000000ff`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00400000`, `0x00303fc0`, `0x00000000`, `0x04000000`, `0x00000000`, };
2944	static const MCPhysReg CSR_O32_SingleFloat_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20, Mips::R31, Mips::R30, Mips::R23, Mips::R22, Mips::R21, Mips::R20, Mips::R19, Mips::R18, Mips::R17, Mips::R16, `0` };
2945	static const uint32_t CSR_O32_SingleFloat_RegMask[] = { `0x00000000`, `0x00000000`, `0x00000000`, `0xc0000000`, `0xf000000f`, `0x000000ff`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00400000`, `0x00303fc0`, `0x00000000`, `0x04000000`, `0x00000000`, };
2946
2947
2948	ArrayRef<const uint32_t > MipsGenRegisterInfo::getRegMasks() const* {
2949	static const uint32_t *const Masks[] = {
2950	CSR_Interrupt_32_RegMask,
2951	CSR_Interrupt_32R6_RegMask,
2952	CSR_Interrupt_64_RegMask,
2953	CSR_Interrupt_64R6_RegMask,
2954	CSR_Mips16RetHelper_RegMask,
2955	CSR_N32_RegMask,
2956	CSR_N32_NoGP_RegMask,
2957	CSR_N32_SingleFloat_RegMask,
2958	CSR_N32_SingleFloat_NoGP_RegMask,
2959	CSR_N64_RegMask,
2960	CSR_N64_NoGP_RegMask,
2961	CSR_N64_SingleFloat_RegMask,
2962	CSR_N64_SingleFloat_NoGP_RegMask,
2963	CSR_O32_RegMask,
2964	CSR_O32_FP64_RegMask,
2965	CSR_O32_FPXX_RegMask,
2966	CSR_O32_SingleFloat_RegMask,
2967	};
2968	return ArrayRef(Masks);
2969	}
2970
2971	bool MipsGenRegisterInfo::
2972	isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2973	return
2974	false;
2975	}
2976
2977	bool MipsGenRegisterInfo::
2978	isGeneralPurposeRegisterClass(const TargetRegisterClass RC) const* {
2979	return
2980	false;
2981	}
2982
2983	bool MipsGenRegisterInfo::
2984	isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2985	return
2986	false;
2987	}
2988
2989	bool MipsGenRegisterInfo::
2990	isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2991	return
2992	false;
2993	}
2994
2995	bool MipsGenRegisterInfo::
2996	isConstantPhysReg(MCRegister PhysReg) const {
2997	return
2998	PhysReg == Mips::R0 \|\|
2999	PhysReg == Mips::R0_64 \|\|
3000	false;
3001	}
3002
3003	ArrayRef<const char > MipsGenRegisterInfo::getRegMaskNames() const* {
3004	static const char *Names[] = {
3005	"CSR_Interrupt_32",
3006	"CSR_Interrupt_32R6",
3007	"CSR_Interrupt_64",
3008	"CSR_Interrupt_64R6",
3009	"CSR_Mips16RetHelper",
3010	"CSR_N32",
3011	"CSR_N32_NoGP",
3012	"CSR_N32_SingleFloat",
3013	"CSR_N32_SingleFloat_NoGP",
3014	"CSR_N64",
3015	"CSR_N64_NoGP",
3016	"CSR_N64_SingleFloat",
3017	"CSR_N64_SingleFloat_NoGP",
3018	"CSR_O32",
3019	"CSR_O32_FP64",
3020	"CSR_O32_FPXX",
3021	"CSR_O32_SingleFloat",
3022	};
3023	return ArrayRef(Names);
3024	}
3025
3026	const MipsFrameLowering *
3027	MipsGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
3028	return static_cast<const MipsFrameLowering *>(
3029	MF.getSubtarget().getFrameLowering());
3030	}
3031
3032
3033	} // namespace llvm
3034

Browse the source code of llvm_projects/build/lib/Target/Mips/MipsGenRegisterInfoTargetDesc.inc