1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass MipsMCRegisterClasses[];
12
13static const MVT::SimpleValueType MipsVTLists[] = {
14 /* 0 */ MVT::v4i8, MVT::v2i16, MVT::i32, MVT::Other,
15 /* 4 */ MVT::i64, MVT::Other,
16 /* 6 */ MVT::f32, MVT::Other,
17 /* 8 */ MVT::i32, MVT::f32, MVT::f64, MVT::Other,
18 /* 12 */ MVT::v16i8, MVT::Other,
19 /* 14 */ MVT::v4i8, MVT::v2i16, MVT::Other,
20 /* 17 */ MVT::v8i16, MVT::v8f16, MVT::Other,
21 /* 20 */ MVT::v4i32, MVT::v4f32, MVT::Other,
22 /* 23 */ MVT::v2i64, MVT::v2f64, MVT::Other,
23 /* 26 */ MVT::Untyped, MVT::Other,
24};
25
26#ifdef __GNUC__
27#pragma GCC diagnostic push
28#pragma GCC diagnostic ignored "-Woverlength-strings"
29#endif
30static constexpr char MipsSubRegIndexStrings[] = {
31 /* 0 */ "sub_dsp20\000"
32 /* 10 */ "sub_dsp21\000"
33 /* 20 */ "sub_dsp22\000"
34 /* 30 */ "sub_32_sub_hi_then_sub_32\000"
35 /* 56 */ "sub_dsp23\000"
36 /* 66 */ "sub_64\000"
37 /* 73 */ "sub_dsp16_19\000"
38 /* 86 */ "sub_hi\000"
39 /* 93 */ "sub_lo\000"
40};
41#ifdef __GNUC__
42#pragma GCC diagnostic pop
43#endif
44
45
46static constexpr uint32_t MipsSubRegIndexNameOffsets[] = {
47 49,
48 66,
49 73,
50 0,
51 10,
52 20,
53 56,
54 86,
55 93,
56 37,
57 30,
58};
59
60static const TargetRegisterInfo::SubRegCoveredBits MipsSubRegIdxRangeTable[] = {
61 { .Offset: 4294967295, .Size: 4294967295 },
62 { .Offset: 0, .Size: 32 }, // sub_32
63 { .Offset: 0, .Size: 64 }, // sub_64
64 { .Offset: 16, .Size: 4 }, // sub_dsp16_19
65 { .Offset: 20, .Size: 1 }, // sub_dsp20
66 { .Offset: 21, .Size: 1 }, // sub_dsp21
67 { .Offset: 22, .Size: 1 }, // sub_dsp22
68 { .Offset: 23, .Size: 1 }, // sub_dsp23
69 { .Offset: 32, .Size: 32 }, // sub_hi
70 { .Offset: 0, .Size: 32 }, // sub_lo
71 { .Offset: 32, .Size: 32 }, // sub_hi_then_sub_32
72 { .Offset: 0, .Size: 64 }, // sub_32_sub_hi_then_sub_32
73 { .Offset: 4294967295, .Size: 4294967295 },
74 { .Offset: 0, .Size: 32 }, // sub_32
75 { .Offset: 0, .Size: 64 }, // sub_64
76 { .Offset: 16, .Size: 4 }, // sub_dsp16_19
77 { .Offset: 20, .Size: 1 }, // sub_dsp20
78 { .Offset: 21, .Size: 1 }, // sub_dsp21
79 { .Offset: 22, .Size: 1 }, // sub_dsp22
80 { .Offset: 23, .Size: 1 }, // sub_dsp23
81 { .Offset: 32, .Size: 32 }, // sub_hi
82 { .Offset: 0, .Size: 32 }, // sub_lo
83 { .Offset: 32, .Size: 32 }, // sub_hi_then_sub_32
84 { .Offset: 0, .Size: 64 }, // sub_32_sub_hi_then_sub_32
85};
86
87
88static const LaneBitmask MipsSubRegIndexLaneMaskTable[] = {
89 LaneBitmask::getAll(),
90 LaneBitmask(0x0000000000000001), // sub_32
91 LaneBitmask(0x0000000000000041), // sub_64
92 LaneBitmask(0x0000000000000002), // sub_dsp16_19
93 LaneBitmask(0x0000000000000004), // sub_dsp20
94 LaneBitmask(0x0000000000000008), // sub_dsp21
95 LaneBitmask(0x0000000000000010), // sub_dsp22
96 LaneBitmask(0x0000000000000020), // sub_dsp23
97 LaneBitmask(0x0000000000000040), // sub_hi
98 LaneBitmask(0x0000000000000001), // sub_lo
99 LaneBitmask(0x0000000000000040), // sub_hi_then_sub_32
100 LaneBitmask(0x0000000000000041), // sub_32_sub_hi_then_sub_32
101 };
102
103
104
105static const TargetRegisterInfo::RegClassInfo MipsRegClassInfos[] = {
106 // Mode = 0 (DefaultMode)
107 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CCR
108 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // COP0
109 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // COP2
110 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // COP3
111 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 0 }, // DSPR
112 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 6 }, // FGR32
113 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // FGR32CC
114 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPR32
115 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // HWRegs
116 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // MSACtrl
117 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPR32NONZERO
118 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPU16RegsPlusSP
119 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPU16Regs
120 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // FCC
121 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16
122 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MoveP
123 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16Zero
124 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPU16Regs_and_GPRMM16Zero
125 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPR32NONZERO_and_GPRMM16MoveP
126 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MovePPairSecond
127 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPU16Regs_and_GPRMM16MoveP
128 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MoveP_and_GPRMM16Zero
129 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // HI32DSP
130 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // LO32DSP
131 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPU16Regs_and_GPRMM16MovePPairSecond
132 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MovePPairFirst
133 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
134 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
135 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPURAReg
136 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPUSPReg
137 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 14 }, // DSPCC
138 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GP32
139 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPR32ZERO
140 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // HI32
141 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // LO32
142 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // SP32
143 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 8 }, // FGR64CC
144 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 10 }, // FGR64
145 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64
146 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPR32NONZERO
147 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 10 }, // AFGR64
148 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16RegsPlusSP
149 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs
150 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MoveP
151 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16Zero
152 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
153 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
154 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
155 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 26 }, // ACC64DSP
156 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
157 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
158 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
159 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
160 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
161 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // OCTEON_MPL
162 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // OCTEON_P
163 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
164 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 26 }, // ACC64
165 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GP64
166 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPURAReg
167 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPR32ZERO
168 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // HI64
169 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // LO64
170 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // SP64
171 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 12 }, // MSA128B
172 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 23 }, // MSA128D
173 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 17 }, // MSA128H
174 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 20 }, // MSA128W
175 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 20 }, // MSA128WEvens
176 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 26 }, // ACC128
177 // Mode = 1 (MIPS64)
178 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CCR
179 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // COP0
180 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // COP2
181 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // COP3
182 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 0 }, // DSPR
183 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 6 }, // FGR32
184 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // FGR32CC
185 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPR32
186 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // HWRegs
187 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // MSACtrl
188 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPR32NONZERO
189 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPU16RegsPlusSP
190 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPU16Regs
191 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // FCC
192 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16
193 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MoveP
194 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16Zero
195 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPU16Regs_and_GPRMM16Zero
196 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPR32NONZERO_and_GPRMM16MoveP
197 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MovePPairSecond
198 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPU16Regs_and_GPRMM16MoveP
199 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MoveP_and_GPRMM16Zero
200 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // HI32DSP
201 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // LO32DSP
202 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPU16Regs_and_GPRMM16MovePPairSecond
203 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MovePPairFirst
204 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
205 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
206 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPURAReg
207 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // CPUSPReg
208 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 14 }, // DSPCC
209 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GP32
210 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // GPR32ZERO
211 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // HI32
212 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // LO32
213 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*MipsVTLists+*/.VTListOffset: 2 }, // SP32
214 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 8 }, // FGR64CC
215 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 10 }, // FGR64
216 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64
217 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPR32NONZERO
218 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 10 }, // AFGR64
219 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16RegsPlusSP
220 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs
221 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MoveP
222 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16Zero
223 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
224 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
225 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
226 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 26 }, // ACC64DSP
227 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
228 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
229 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
230 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
231 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
232 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // OCTEON_MPL
233 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // OCTEON_P
234 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
235 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 26 }, // ACC64
236 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GP64
237 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_CPURAReg
238 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // GPR64_with_sub_32_in_GPR32ZERO
239 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // HI64
240 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // LO64
241 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*MipsVTLists+*/.VTListOffset: 4 }, // SP64
242 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 12 }, // MSA128B
243 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 23 }, // MSA128D
244 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 17 }, // MSA128H
245 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 20 }, // MSA128W
246 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 20 }, // MSA128WEvens
247 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*MipsVTLists+*/.VTListOffset: 26 }, // ACC128
248};
249static const uint32_t CCRSubClassMask[] = {
250 0x00000001, 0x00000000, 0x00000000,
251};
252
253static const uint32_t COP0SubClassMask[] = {
254 0x00000002, 0x00000000, 0x00000000,
255};
256
257static const uint32_t COP2SubClassMask[] = {
258 0x00000004, 0x00000000, 0x00000000,
259};
260
261static const uint32_t COP3SubClassMask[] = {
262 0x00000008, 0x00000000, 0x00000000,
263};
264
265static const uint32_t DSPRSubClassMask[] = {
266 0xbf3fdc90, 0x00000009, 0x00000000,
267 0x00000000, 0x9d3efec0, 0x00000000, // sub_32
268};
269
270static const uint32_t FGR32SubClassMask[] = {
271 0x00000060, 0x00000000, 0x00000000,
272 0x00000000, 0x00000100, 0x00000000, // sub_hi
273 0x00000000, 0x00000130, 0x0000001f, // sub_lo
274};
275
276static const uint32_t FGR32CCSubClassMask[] = {
277 0x00000060, 0x00000000, 0x00000000,
278 0x00000000, 0x00000100, 0x00000000, // sub_hi
279 0x00000000, 0x00000130, 0x0000001f, // sub_lo
280};
281
282static const uint32_t GPR32SubClassMask[] = {
283 0xbf3fdc80, 0x00000009, 0x00000000,
284 0x00000000, 0x9d3efec0, 0x00000000, // sub_32
285};
286
287static const uint32_t HWRegsSubClassMask[] = {
288 0x00000100, 0x00000000, 0x00000000,
289};
290
291static const uint32_t MSACtrlSubClassMask[] = {
292 0x00000200, 0x00000000, 0x00000000,
293};
294
295static const uint32_t GPR32NONZEROSubClassMask[] = {
296 0xbf1e5c00, 0x00000008, 0x00000000,
297 0x00000000, 0x8d3ae680, 0x00000000, // sub_32
298};
299
300static const uint32_t CPU16RegsPlusSPSubClassMask[] = {
301 0x2f125800, 0x00000008, 0x00000000,
302 0x00000000, 0x813a2600, 0x00000000, // sub_32
303};
304
305static const uint32_t CPU16RegsSubClassMask[] = {
306 0x0f125000, 0x00000000, 0x00000000,
307 0x00000000, 0x013a2400, 0x00000000, // sub_32
308};
309
310static const uint32_t FCCSubClassMask[] = {
311 0x00002000, 0x00000000, 0x00000000,
312};
313
314static const uint32_t GPRMM16SubClassMask[] = {
315 0x0f124000, 0x00000000, 0x00000000,
316 0x00000000, 0x013a2400, 0x00000000, // sub_32
317};
318
319static const uint32_t GPRMM16MovePSubClassMask[] = {
320 0x04348000, 0x00000001, 0x00000000,
321 0x00000000, 0x10264800, 0x00000000, // sub_32
322};
323
324static const uint32_t GPRMM16ZeroSubClassMask[] = {
325 0x0f230000, 0x00000001, 0x00000000,
326 0x00000000, 0x113c3000, 0x00000000, // sub_32
327};
328
329static const uint32_t CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
330 0x0f020000, 0x00000000, 0x00000000,
331 0x00000000, 0x01382000, 0x00000000, // sub_32
332};
333
334static const uint32_t GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
335 0x04140000, 0x00000000, 0x00000000,
336 0x00000000, 0x00224000, 0x00000000, // sub_32
337};
338
339static const uint32_t GPRMM16MovePPairSecondSubClassMask[] = {
340 0x09080000, 0x00000000, 0x00000000,
341 0x00000000, 0x01088000, 0x00000000, // sub_32
342};
343
344static const uint32_t CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
345 0x04100000, 0x00000000, 0x00000000,
346 0x00000000, 0x00220000, 0x00000000, // sub_32
347};
348
349static const uint32_t GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
350 0x04200000, 0x00000001, 0x00000000,
351 0x00000000, 0x10240000, 0x00000000, // sub_32
352};
353
354static const uint32_t HI32DSPSubClassMask[] = {
355 0x00400000, 0x00000002, 0x00000000,
356 0x00000000, 0x20000000, 0x00000000, // sub_32
357 0x00000000, 0x02010000, 0x00000000, // sub_hi
358 0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32
359};
360
361static const uint32_t LO32DSPSubClassMask[] = {
362 0x00800000, 0x00000004, 0x00000000,
363 0x00000000, 0x40000000, 0x00000020, // sub_32
364 0x00000000, 0x02010000, 0x00000000, // sub_lo
365};
366
367static const uint32_t CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {
368 0x09000000, 0x00000000, 0x00000000,
369 0x00000000, 0x01080000, 0x00000000, // sub_32
370};
371
372static const uint32_t GPRMM16MovePPairFirstSubClassMask[] = {
373 0x0a000000, 0x00000000, 0x00000000,
374 0x00000000, 0x01100000, 0x00000000, // sub_32
375};
376
377static const uint32_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
378 0x04000000, 0x00000000, 0x00000000,
379 0x00000000, 0x00200000, 0x00000000, // sub_32
380};
381
382static const uint32_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {
383 0x08000000, 0x00000000, 0x00000000,
384 0x00000000, 0x01000000, 0x00000000, // sub_32
385};
386
387static const uint32_t CPURARegSubClassMask[] = {
388 0x10000000, 0x00000000, 0x00000000,
389 0x00000000, 0x08000000, 0x00000000, // sub_32
390};
391
392static const uint32_t CPUSPRegSubClassMask[] = {
393 0x20000000, 0x00000008, 0x00000000,
394 0x00000000, 0x80000000, 0x00000000, // sub_32
395};
396
397static const uint32_t DSPCCSubClassMask[] = {
398 0x40000000, 0x00000000, 0x00000000,
399};
400
401static const uint32_t GP32SubClassMask[] = {
402 0x80000000, 0x00000000, 0x00000000,
403 0x00000000, 0x04000000, 0x00000000, // sub_32
404};
405
406static const uint32_t GPR32ZEROSubClassMask[] = {
407 0x00000000, 0x00000001, 0x00000000,
408 0x00000000, 0x10000000, 0x00000000, // sub_32
409};
410
411static const uint32_t HI32SubClassMask[] = {
412 0x00000000, 0x00000002, 0x00000000,
413 0x00000000, 0x20000000, 0x00000000, // sub_32
414 0x00000000, 0x02000000, 0x00000000, // sub_hi
415 0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32
416};
417
418static const uint32_t LO32SubClassMask[] = {
419 0x00000000, 0x00000004, 0x00000000,
420 0x00000000, 0x40000000, 0x00000020, // sub_32
421 0x00000000, 0x02000000, 0x00000000, // sub_lo
422};
423
424static const uint32_t SP32SubClassMask[] = {
425 0x00000000, 0x00000008, 0x00000000,
426 0x00000000, 0x80000000, 0x00000000, // sub_32
427};
428
429static const uint32_t FGR64CCSubClassMask[] = {
430 0x00000000, 0x00000030, 0x00000000,
431 0x00000000, 0x00000000, 0x0000001f, // sub_64
432};
433
434static const uint32_t FGR64SubClassMask[] = {
435 0x00000000, 0x00000020, 0x00000000,
436 0x00000000, 0x00000000, 0x0000001f, // sub_64
437};
438
439static const uint32_t GPR64SubClassMask[] = {
440 0x00000000, 0x9d3efec0, 0x00000000,
441};
442
443static const uint32_t GPR64_with_sub_32_in_GPR32NONZEROSubClassMask[] = {
444 0x00000000, 0x8d3ae680, 0x00000000,
445};
446
447static const uint32_t AFGR64SubClassMask[] = {
448 0x00000000, 0x00000100, 0x00000000,
449};
450
451static const uint32_t GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask[] = {
452 0x00000000, 0x813a2600, 0x00000000,
453};
454
455static const uint32_t GPR64_with_sub_32_in_CPU16RegsSubClassMask[] = {
456 0x00000000, 0x013a2400, 0x00000000,
457};
458
459static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePSubClassMask[] = {
460 0x00000000, 0x10264800, 0x00000000,
461};
462
463static const uint32_t GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask[] = {
464 0x00000000, 0x113c3000, 0x00000000,
465};
466
467static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
468 0x00000000, 0x01382000, 0x00000000,
469};
470
471static const uint32_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
472 0x00000000, 0x00224000, 0x00000000,
473};
474
475static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask[] = {
476 0x00000000, 0x01088000, 0x00000000,
477};
478
479static const uint32_t ACC64DSPSubClassMask[] = {
480 0x00000000, 0x02010000, 0x00000000,
481 0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32
482};
483
484static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
485 0x00000000, 0x00220000, 0x00000000,
486};
487
488static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
489 0x00000000, 0x10240000, 0x00000000,
490};
491
492static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {
493 0x00000000, 0x01080000, 0x00000000,
494};
495
496static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask[] = {
497 0x00000000, 0x01100000, 0x00000000,
498};
499
500static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
501 0x00000000, 0x00200000, 0x00000000,
502};
503
504static const uint32_t OCTEON_MPLSubClassMask[] = {
505 0x00000000, 0x00400000, 0x00000000,
506};
507
508static const uint32_t OCTEON_PSubClassMask[] = {
509 0x00000000, 0x00800000, 0x00000000,
510};
511
512static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {
513 0x00000000, 0x01000000, 0x00000000,
514};
515
516static const uint32_t ACC64SubClassMask[] = {
517 0x00000000, 0x02000000, 0x00000000,
518 0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32
519};
520
521static const uint32_t GP64SubClassMask[] = {
522 0x00000000, 0x04000000, 0x00000000,
523};
524
525static const uint32_t GPR64_with_sub_32_in_CPURARegSubClassMask[] = {
526 0x00000000, 0x08000000, 0x00000000,
527};
528
529static const uint32_t GPR64_with_sub_32_in_GPR32ZEROSubClassMask[] = {
530 0x00000000, 0x10000000, 0x00000000,
531};
532
533static const uint32_t HI64SubClassMask[] = {
534 0x00000000, 0x20000000, 0x00000000,
535 0x00000000, 0x00000000, 0x00000020, // sub_hi
536};
537
538static const uint32_t LO64SubClassMask[] = {
539 0x00000000, 0x40000000, 0x00000000,
540 0x00000000, 0x00000000, 0x00000020, // sub_lo
541};
542
543static const uint32_t SP64SubClassMask[] = {
544 0x00000000, 0x80000000, 0x00000000,
545};
546
547static const uint32_t MSA128BSubClassMask[] = {
548 0x00000000, 0x00000000, 0x0000001f,
549};
550
551static const uint32_t MSA128DSubClassMask[] = {
552 0x00000000, 0x00000000, 0x0000001f,
553};
554
555static const uint32_t MSA128HSubClassMask[] = {
556 0x00000000, 0x00000000, 0x0000001f,
557};
558
559static const uint32_t MSA128WSubClassMask[] = {
560 0x00000000, 0x00000000, 0x0000001f,
561};
562
563static const uint32_t MSA128WEvensSubClassMask[] = {
564 0x00000000, 0x00000000, 0x00000010,
565};
566
567static const uint32_t ACC128SubClassMask[] = {
568 0x00000000, 0x00000000, 0x00000020,
569};
570
571static const uint16_t SuperRegIdxSeqs[] = {
572 /* 0 */ 1, 0,
573 /* 2 */ 2, 0,
574 /* 4 */ 8, 0,
575 /* 6 */ 1, 9, 0,
576 /* 9 */ 8, 9, 0,
577 /* 12 */ 1, 8, 10, 0,
578 /* 16 */ 11, 0,
579};
580
581static unsigned const FGR32Superclasses[] = {
582 Mips::FGR32CCRegClassID,
583};
584
585static unsigned const FGR32CCSuperclasses[] = {
586 Mips::FGR32RegClassID,
587};
588
589static unsigned const GPR32Superclasses[] = {
590 Mips::DSPRRegClassID,
591};
592
593static unsigned const GPR32NONZEROSuperclasses[] = {
594 Mips::DSPRRegClassID,
595 Mips::GPR32RegClassID,
596};
597
598static unsigned const CPU16RegsPlusSPSuperclasses[] = {
599 Mips::DSPRRegClassID,
600 Mips::GPR32RegClassID,
601 Mips::GPR32NONZERORegClassID,
602};
603
604static unsigned const CPU16RegsSuperclasses[] = {
605 Mips::DSPRRegClassID,
606 Mips::GPR32RegClassID,
607 Mips::GPR32NONZERORegClassID,
608 Mips::CPU16RegsPlusSPRegClassID,
609};
610
611static unsigned const GPRMM16Superclasses[] = {
612 Mips::DSPRRegClassID,
613 Mips::GPR32RegClassID,
614 Mips::GPR32NONZERORegClassID,
615 Mips::CPU16RegsPlusSPRegClassID,
616 Mips::CPU16RegsRegClassID,
617};
618
619static unsigned const GPRMM16MovePSuperclasses[] = {
620 Mips::DSPRRegClassID,
621 Mips::GPR32RegClassID,
622};
623
624static unsigned const GPRMM16ZeroSuperclasses[] = {
625 Mips::DSPRRegClassID,
626 Mips::GPR32RegClassID,
627};
628
629static unsigned const CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
630 Mips::DSPRRegClassID,
631 Mips::GPR32RegClassID,
632 Mips::GPR32NONZERORegClassID,
633 Mips::CPU16RegsPlusSPRegClassID,
634 Mips::CPU16RegsRegClassID,
635 Mips::GPRMM16RegClassID,
636 Mips::GPRMM16ZeroRegClassID,
637};
638
639static unsigned const GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
640 Mips::DSPRRegClassID,
641 Mips::GPR32RegClassID,
642 Mips::GPR32NONZERORegClassID,
643 Mips::GPRMM16MovePRegClassID,
644};
645
646static unsigned const GPRMM16MovePPairSecondSuperclasses[] = {
647 Mips::DSPRRegClassID,
648 Mips::GPR32RegClassID,
649 Mips::GPR32NONZERORegClassID,
650};
651
652static unsigned const CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
653 Mips::DSPRRegClassID,
654 Mips::GPR32RegClassID,
655 Mips::GPR32NONZERORegClassID,
656 Mips::CPU16RegsPlusSPRegClassID,
657 Mips::CPU16RegsRegClassID,
658 Mips::GPRMM16RegClassID,
659 Mips::GPRMM16MovePRegClassID,
660 Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID,
661};
662
663static unsigned const GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
664 Mips::DSPRRegClassID,
665 Mips::GPR32RegClassID,
666 Mips::GPRMM16MovePRegClassID,
667 Mips::GPRMM16ZeroRegClassID,
668};
669
670static unsigned const CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
671 Mips::DSPRRegClassID,
672 Mips::GPR32RegClassID,
673 Mips::GPR32NONZERORegClassID,
674 Mips::CPU16RegsPlusSPRegClassID,
675 Mips::CPU16RegsRegClassID,
676 Mips::GPRMM16RegClassID,
677 Mips::GPRMM16ZeroRegClassID,
678 Mips::CPU16Regs_and_GPRMM16ZeroRegClassID,
679 Mips::GPRMM16MovePPairSecondRegClassID,
680};
681
682static unsigned const GPRMM16MovePPairFirstSuperclasses[] = {
683 Mips::DSPRRegClassID,
684 Mips::GPR32RegClassID,
685 Mips::GPR32NONZERORegClassID,
686 Mips::CPU16RegsPlusSPRegClassID,
687 Mips::CPU16RegsRegClassID,
688 Mips::GPRMM16RegClassID,
689 Mips::GPRMM16ZeroRegClassID,
690 Mips::CPU16Regs_and_GPRMM16ZeroRegClassID,
691};
692
693static unsigned const GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
694 Mips::DSPRRegClassID,
695 Mips::GPR32RegClassID,
696 Mips::GPR32NONZERORegClassID,
697 Mips::CPU16RegsPlusSPRegClassID,
698 Mips::CPU16RegsRegClassID,
699 Mips::GPRMM16RegClassID,
700 Mips::GPRMM16MovePRegClassID,
701 Mips::GPRMM16ZeroRegClassID,
702 Mips::CPU16Regs_and_GPRMM16ZeroRegClassID,
703 Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID,
704 Mips::CPU16Regs_and_GPRMM16MovePRegClassID,
705 Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID,
706};
707
708static unsigned const GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
709 Mips::DSPRRegClassID,
710 Mips::GPR32RegClassID,
711 Mips::GPR32NONZERORegClassID,
712 Mips::CPU16RegsPlusSPRegClassID,
713 Mips::CPU16RegsRegClassID,
714 Mips::GPRMM16RegClassID,
715 Mips::GPRMM16ZeroRegClassID,
716 Mips::CPU16Regs_and_GPRMM16ZeroRegClassID,
717 Mips::GPRMM16MovePPairSecondRegClassID,
718 Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID,
719 Mips::GPRMM16MovePPairFirstRegClassID,
720};
721
722static unsigned const CPURARegSuperclasses[] = {
723 Mips::DSPRRegClassID,
724 Mips::GPR32RegClassID,
725 Mips::GPR32NONZERORegClassID,
726};
727
728static unsigned const CPUSPRegSuperclasses[] = {
729 Mips::DSPRRegClassID,
730 Mips::GPR32RegClassID,
731 Mips::GPR32NONZERORegClassID,
732 Mips::CPU16RegsPlusSPRegClassID,
733};
734
735static unsigned const GP32Superclasses[] = {
736 Mips::DSPRRegClassID,
737 Mips::GPR32RegClassID,
738 Mips::GPR32NONZERORegClassID,
739};
740
741static unsigned const GPR32ZEROSuperclasses[] = {
742 Mips::DSPRRegClassID,
743 Mips::GPR32RegClassID,
744 Mips::GPRMM16MovePRegClassID,
745 Mips::GPRMM16ZeroRegClassID,
746 Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID,
747};
748
749static unsigned const HI32Superclasses[] = {
750 Mips::HI32DSPRegClassID,
751};
752
753static unsigned const LO32Superclasses[] = {
754 Mips::LO32DSPRegClassID,
755};
756
757static unsigned const SP32Superclasses[] = {
758 Mips::DSPRRegClassID,
759 Mips::GPR32RegClassID,
760 Mips::GPR32NONZERORegClassID,
761 Mips::CPU16RegsPlusSPRegClassID,
762 Mips::CPUSPRegRegClassID,
763};
764
765static unsigned const FGR64Superclasses[] = {
766 Mips::FGR64CCRegClassID,
767};
768
769static unsigned const GPR64_with_sub_32_in_GPR32NONZEROSuperclasses[] = {
770 Mips::GPR64RegClassID,
771};
772
773static unsigned const GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses[] = {
774 Mips::GPR64RegClassID,
775 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
776};
777
778static unsigned const GPR64_with_sub_32_in_CPU16RegsSuperclasses[] = {
779 Mips::GPR64RegClassID,
780 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
781 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
782};
783
784static unsigned const GPR64_with_sub_32_in_GPRMM16MovePSuperclasses[] = {
785 Mips::GPR64RegClassID,
786};
787
788static unsigned const GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses[] = {
789 Mips::GPR64RegClassID,
790};
791
792static unsigned const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
793 Mips::GPR64RegClassID,
794 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
795 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
796 Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
797 Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
798};
799
800static unsigned const GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
801 Mips::GPR64RegClassID,
802 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
803 Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
804};
805
806static unsigned const GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses[] = {
807 Mips::GPR64RegClassID,
808 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
809};
810
811static unsigned const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
812 Mips::GPR64RegClassID,
813 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
814 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
815 Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
816 Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
817 Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID,
818};
819
820static unsigned const GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
821 Mips::GPR64RegClassID,
822 Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
823 Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
824};
825
826static unsigned const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
827 Mips::GPR64RegClassID,
828 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
829 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
830 Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
831 Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
832 Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID,
833 Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID,
834};
835
836static unsigned const GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses[] = {
837 Mips::GPR64RegClassID,
838 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
839 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
840 Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
841 Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
842 Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID,
843};
844
845static unsigned const GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
846 Mips::GPR64RegClassID,
847 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
848 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
849 Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
850 Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
851 Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
852 Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID,
853 Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID,
854 Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID,
855 Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID,
856};
857
858static unsigned const GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
859 Mips::GPR64RegClassID,
860 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
861 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
862 Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
863 Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
864 Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID,
865 Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID,
866 Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID,
867 Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID,
868};
869
870static unsigned const ACC64Superclasses[] = {
871 Mips::ACC64DSPRegClassID,
872};
873
874static unsigned const GP64Superclasses[] = {
875 Mips::GPR64RegClassID,
876 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
877};
878
879static unsigned const GPR64_with_sub_32_in_CPURARegSuperclasses[] = {
880 Mips::GPR64RegClassID,
881 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
882};
883
884static unsigned const GPR64_with_sub_32_in_GPR32ZEROSuperclasses[] = {
885 Mips::GPR64RegClassID,
886 Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
887 Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
888 Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID,
889};
890
891static unsigned const SP64Superclasses[] = {
892 Mips::GPR64RegClassID,
893 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
894 Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
895};
896
897static unsigned const MSA128BSuperclasses[] = {
898 Mips::MSA128DRegClassID,
899 Mips::MSA128HRegClassID,
900 Mips::MSA128WRegClassID,
901};
902
903static unsigned const MSA128DSuperclasses[] = {
904 Mips::MSA128BRegClassID,
905 Mips::MSA128HRegClassID,
906 Mips::MSA128WRegClassID,
907};
908
909static unsigned const MSA128HSuperclasses[] = {
910 Mips::MSA128BRegClassID,
911 Mips::MSA128DRegClassID,
912 Mips::MSA128WRegClassID,
913};
914
915static unsigned const MSA128WSuperclasses[] = {
916 Mips::MSA128BRegClassID,
917 Mips::MSA128DRegClassID,
918 Mips::MSA128HRegClassID,
919};
920
921static unsigned const MSA128WEvensSuperclasses[] = {
922 Mips::MSA128BRegClassID,
923 Mips::MSA128DRegClassID,
924 Mips::MSA128HRegClassID,
925 Mips::MSA128WRegClassID,
926};
927
928
929static inline unsigned FGR32AltOrderSelect(const MachineFunction &MF, bool Rev) {
930 const auto & S = MF.getSubtarget<MipsSubtarget>();
931 return S.isABI_O32() && !S.useOddSPReg();
932 }
933
934static ArrayRef<MCPhysReg> FGR32GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
935 static const MCPhysReg AltOrder1[] = { Mips::F0, Mips::F2, Mips::F4, Mips::F6, Mips::F8, Mips::F10, Mips::F12, Mips::F14, Mips::F16, Mips::F18, Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30 };
936 const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR32RegClassID];
937 const ArrayRef<MCPhysReg> Order[] = {
938 ArrayRef(MCR.begin(), MCR.getNumRegs()),
939 ArrayRef(AltOrder1)
940 };
941 const unsigned Select = FGR32AltOrderSelect(MF, Rev);
942 assert(Select < 2);
943 return Order[Select];
944}
945
946static inline unsigned FGR64AltOrderSelect(const MachineFunction &MF, bool Rev) {
947 const auto & S = MF.getSubtarget<MipsSubtarget>();
948 return S.isABI_O32() && !S.useOddSPReg();
949 }
950
951static ArrayRef<MCPhysReg> FGR64GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
952 static const MCPhysReg AltOrder1[] = { Mips::D0_64, Mips::D2_64, Mips::D4_64, Mips::D6_64, Mips::D8_64, Mips::D10_64, Mips::D12_64, Mips::D14_64, Mips::D16_64, Mips::D18_64, Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64 };
953 const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR64RegClassID];
954 const ArrayRef<MCPhysReg> Order[] = {
955 ArrayRef(MCR.begin(), MCR.getNumRegs()),
956 ArrayRef(AltOrder1)
957 };
958 const unsigned Select = FGR64AltOrderSelect(MF, Rev);
959 assert(Select < 2);
960 return Order[Select];
961}
962namespace Mips {
963
964// Register class instances.
965 extern const TargetRegisterClass CCRRegClass = {
966 .MC: &MipsMCRegisterClasses[CCRRegClassID],
967 .SubClassMask: CCRSubClassMask,
968 .SuperRegIndices: SuperRegIdxSeqs + 1,
969 .LaneMask: LaneBitmask(0x0000000000000001),
970 .AllocationPriority: 0,
971 .GlobalPriority: false,
972 .TSFlags: 0x00, /* TSFlags */
973 .SpillStackID: 0, /* SpillStackID */
974 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
975 .CoveredBySubRegs: false, /* CoveredBySubRegs */
976 .SuperClasses: nullptr, .SuperClassesSize: 0,
977 .OrderFunc: nullptr
978 };
979
980 extern const TargetRegisterClass COP0RegClass = {
981 .MC: &MipsMCRegisterClasses[COP0RegClassID],
982 .SubClassMask: COP0SubClassMask,
983 .SuperRegIndices: SuperRegIdxSeqs + 1,
984 .LaneMask: LaneBitmask(0x0000000000000001),
985 .AllocationPriority: 0,
986 .GlobalPriority: false,
987 .TSFlags: 0x00, /* TSFlags */
988 .SpillStackID: 0, /* SpillStackID */
989 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
990 .CoveredBySubRegs: false, /* CoveredBySubRegs */
991 .SuperClasses: nullptr, .SuperClassesSize: 0,
992 .OrderFunc: nullptr
993 };
994
995 extern const TargetRegisterClass COP2RegClass = {
996 .MC: &MipsMCRegisterClasses[COP2RegClassID],
997 .SubClassMask: COP2SubClassMask,
998 .SuperRegIndices: SuperRegIdxSeqs + 1,
999 .LaneMask: LaneBitmask(0x0000000000000001),
1000 .AllocationPriority: 0,
1001 .GlobalPriority: false,
1002 .TSFlags: 0x00, /* TSFlags */
1003 .SpillStackID: 0, /* SpillStackID */
1004 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1005 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1006 .SuperClasses: nullptr, .SuperClassesSize: 0,
1007 .OrderFunc: nullptr
1008 };
1009
1010 extern const TargetRegisterClass COP3RegClass = {
1011 .MC: &MipsMCRegisterClasses[COP3RegClassID],
1012 .SubClassMask: COP3SubClassMask,
1013 .SuperRegIndices: SuperRegIdxSeqs + 1,
1014 .LaneMask: LaneBitmask(0x0000000000000001),
1015 .AllocationPriority: 0,
1016 .GlobalPriority: false,
1017 .TSFlags: 0x00, /* TSFlags */
1018 .SpillStackID: 0, /* SpillStackID */
1019 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1020 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1021 .SuperClasses: nullptr, .SuperClassesSize: 0,
1022 .OrderFunc: nullptr
1023 };
1024
1025 extern const TargetRegisterClass DSPRRegClass = {
1026 .MC: &MipsMCRegisterClasses[DSPRRegClassID],
1027 .SubClassMask: DSPRSubClassMask,
1028 .SuperRegIndices: SuperRegIdxSeqs + 0,
1029 .LaneMask: LaneBitmask(0x0000000000000001),
1030 .AllocationPriority: 0,
1031 .GlobalPriority: false,
1032 .TSFlags: 0x00, /* TSFlags */
1033 .SpillStackID: 0, /* SpillStackID */
1034 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1035 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1036 .SuperClasses: nullptr, .SuperClassesSize: 0,
1037 .OrderFunc: nullptr
1038 };
1039
1040 extern const TargetRegisterClass FGR32RegClass = {
1041 .MC: &MipsMCRegisterClasses[FGR32RegClassID],
1042 .SubClassMask: FGR32SubClassMask,
1043 .SuperRegIndices: SuperRegIdxSeqs + 9,
1044 .LaneMask: LaneBitmask(0x0000000000000001),
1045 .AllocationPriority: 0,
1046 .GlobalPriority: false,
1047 .TSFlags: 0x00, /* TSFlags */
1048 .SpillStackID: 0, /* SpillStackID */
1049 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1050 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1051 .SuperClasses: FGR32Superclasses, .SuperClassesSize: 1,
1052 .OrderFunc: FGR32GetRawAllocationOrder
1053 };
1054
1055 extern const TargetRegisterClass FGR32CCRegClass = {
1056 .MC: &MipsMCRegisterClasses[FGR32CCRegClassID],
1057 .SubClassMask: FGR32CCSubClassMask,
1058 .SuperRegIndices: SuperRegIdxSeqs + 9,
1059 .LaneMask: LaneBitmask(0x0000000000000001),
1060 .AllocationPriority: 0,
1061 .GlobalPriority: false,
1062 .TSFlags: 0x00, /* TSFlags */
1063 .SpillStackID: 0, /* SpillStackID */
1064 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1065 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1066 .SuperClasses: FGR32CCSuperclasses, .SuperClassesSize: 1,
1067 .OrderFunc: nullptr
1068 };
1069
1070 extern const TargetRegisterClass GPR32RegClass = {
1071 .MC: &MipsMCRegisterClasses[GPR32RegClassID],
1072 .SubClassMask: GPR32SubClassMask,
1073 .SuperRegIndices: SuperRegIdxSeqs + 0,
1074 .LaneMask: LaneBitmask(0x0000000000000001),
1075 .AllocationPriority: 0,
1076 .GlobalPriority: false,
1077 .TSFlags: 0x00, /* TSFlags */
1078 .SpillStackID: 0, /* SpillStackID */
1079 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1080 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1081 .SuperClasses: GPR32Superclasses, .SuperClassesSize: 1,
1082 .OrderFunc: nullptr
1083 };
1084
1085 extern const TargetRegisterClass HWRegsRegClass = {
1086 .MC: &MipsMCRegisterClasses[HWRegsRegClassID],
1087 .SubClassMask: HWRegsSubClassMask,
1088 .SuperRegIndices: SuperRegIdxSeqs + 1,
1089 .LaneMask: LaneBitmask(0x0000000000000001),
1090 .AllocationPriority: 0,
1091 .GlobalPriority: false,
1092 .TSFlags: 0x00, /* TSFlags */
1093 .SpillStackID: 0, /* SpillStackID */
1094 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1095 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1096 .SuperClasses: nullptr, .SuperClassesSize: 0,
1097 .OrderFunc: nullptr
1098 };
1099
1100 extern const TargetRegisterClass MSACtrlRegClass = {
1101 .MC: &MipsMCRegisterClasses[MSACtrlRegClassID],
1102 .SubClassMask: MSACtrlSubClassMask,
1103 .SuperRegIndices: SuperRegIdxSeqs + 1,
1104 .LaneMask: LaneBitmask(0x0000000000000001),
1105 .AllocationPriority: 0,
1106 .GlobalPriority: false,
1107 .TSFlags: 0x00, /* TSFlags */
1108 .SpillStackID: 0, /* SpillStackID */
1109 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1110 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1111 .SuperClasses: nullptr, .SuperClassesSize: 0,
1112 .OrderFunc: nullptr
1113 };
1114
1115 extern const TargetRegisterClass GPR32NONZERORegClass = {
1116 .MC: &MipsMCRegisterClasses[GPR32NONZERORegClassID],
1117 .SubClassMask: GPR32NONZEROSubClassMask,
1118 .SuperRegIndices: SuperRegIdxSeqs + 0,
1119 .LaneMask: LaneBitmask(0x0000000000000001),
1120 .AllocationPriority: 0,
1121 .GlobalPriority: false,
1122 .TSFlags: 0x00, /* TSFlags */
1123 .SpillStackID: 0, /* SpillStackID */
1124 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1125 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1126 .SuperClasses: GPR32NONZEROSuperclasses, .SuperClassesSize: 2,
1127 .OrderFunc: nullptr
1128 };
1129
1130 extern const TargetRegisterClass CPU16RegsPlusSPRegClass = {
1131 .MC: &MipsMCRegisterClasses[CPU16RegsPlusSPRegClassID],
1132 .SubClassMask: CPU16RegsPlusSPSubClassMask,
1133 .SuperRegIndices: SuperRegIdxSeqs + 0,
1134 .LaneMask: LaneBitmask(0x0000000000000001),
1135 .AllocationPriority: 0,
1136 .GlobalPriority: false,
1137 .TSFlags: 0x00, /* TSFlags */
1138 .SpillStackID: 0, /* SpillStackID */
1139 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1140 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1141 .SuperClasses: CPU16RegsPlusSPSuperclasses, .SuperClassesSize: 3,
1142 .OrderFunc: nullptr
1143 };
1144
1145 extern const TargetRegisterClass CPU16RegsRegClass = {
1146 .MC: &MipsMCRegisterClasses[CPU16RegsRegClassID],
1147 .SubClassMask: CPU16RegsSubClassMask,
1148 .SuperRegIndices: SuperRegIdxSeqs + 0,
1149 .LaneMask: LaneBitmask(0x0000000000000001),
1150 .AllocationPriority: 0,
1151 .GlobalPriority: false,
1152 .TSFlags: 0x00, /* TSFlags */
1153 .SpillStackID: 0, /* SpillStackID */
1154 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1155 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1156 .SuperClasses: CPU16RegsSuperclasses, .SuperClassesSize: 4,
1157 .OrderFunc: nullptr
1158 };
1159
1160 extern const TargetRegisterClass FCCRegClass = {
1161 .MC: &MipsMCRegisterClasses[FCCRegClassID],
1162 .SubClassMask: FCCSubClassMask,
1163 .SuperRegIndices: SuperRegIdxSeqs + 1,
1164 .LaneMask: LaneBitmask(0x0000000000000001),
1165 .AllocationPriority: 0,
1166 .GlobalPriority: false,
1167 .TSFlags: 0x00, /* TSFlags */
1168 .SpillStackID: 0, /* SpillStackID */
1169 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1170 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1171 .SuperClasses: nullptr, .SuperClassesSize: 0,
1172 .OrderFunc: nullptr
1173 };
1174
1175 extern const TargetRegisterClass GPRMM16RegClass = {
1176 .MC: &MipsMCRegisterClasses[GPRMM16RegClassID],
1177 .SubClassMask: GPRMM16SubClassMask,
1178 .SuperRegIndices: SuperRegIdxSeqs + 0,
1179 .LaneMask: LaneBitmask(0x0000000000000001),
1180 .AllocationPriority: 0,
1181 .GlobalPriority: false,
1182 .TSFlags: 0x00, /* TSFlags */
1183 .SpillStackID: 0, /* SpillStackID */
1184 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1185 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1186 .SuperClasses: GPRMM16Superclasses, .SuperClassesSize: 5,
1187 .OrderFunc: nullptr
1188 };
1189
1190 extern const TargetRegisterClass GPRMM16MovePRegClass = {
1191 .MC: &MipsMCRegisterClasses[GPRMM16MovePRegClassID],
1192 .SubClassMask: GPRMM16MovePSubClassMask,
1193 .SuperRegIndices: SuperRegIdxSeqs + 0,
1194 .LaneMask: LaneBitmask(0x0000000000000001),
1195 .AllocationPriority: 0,
1196 .GlobalPriority: false,
1197 .TSFlags: 0x00, /* TSFlags */
1198 .SpillStackID: 0, /* SpillStackID */
1199 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1200 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1201 .SuperClasses: GPRMM16MovePSuperclasses, .SuperClassesSize: 2,
1202 .OrderFunc: nullptr
1203 };
1204
1205 extern const TargetRegisterClass GPRMM16ZeroRegClass = {
1206 .MC: &MipsMCRegisterClasses[GPRMM16ZeroRegClassID],
1207 .SubClassMask: GPRMM16ZeroSubClassMask,
1208 .SuperRegIndices: SuperRegIdxSeqs + 0,
1209 .LaneMask: LaneBitmask(0x0000000000000001),
1210 .AllocationPriority: 0,
1211 .GlobalPriority: false,
1212 .TSFlags: 0x00, /* TSFlags */
1213 .SpillStackID: 0, /* SpillStackID */
1214 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1215 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1216 .SuperClasses: GPRMM16ZeroSuperclasses, .SuperClassesSize: 2,
1217 .OrderFunc: nullptr
1218 };
1219
1220 extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass = {
1221 .MC: &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16ZeroRegClassID],
1222 .SubClassMask: CPU16Regs_and_GPRMM16ZeroSubClassMask,
1223 .SuperRegIndices: SuperRegIdxSeqs + 0,
1224 .LaneMask: LaneBitmask(0x0000000000000001),
1225 .AllocationPriority: 0,
1226 .GlobalPriority: false,
1227 .TSFlags: 0x00, /* TSFlags */
1228 .SpillStackID: 0, /* SpillStackID */
1229 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1230 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1231 .SuperClasses: CPU16Regs_and_GPRMM16ZeroSuperclasses, .SuperClassesSize: 7,
1232 .OrderFunc: nullptr
1233 };
1234
1235 extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass = {
1236 .MC: &MipsMCRegisterClasses[GPR32NONZERO_and_GPRMM16MovePRegClassID],
1237 .SubClassMask: GPR32NONZERO_and_GPRMM16MovePSubClassMask,
1238 .SuperRegIndices: SuperRegIdxSeqs + 0,
1239 .LaneMask: LaneBitmask(0x0000000000000001),
1240 .AllocationPriority: 0,
1241 .GlobalPriority: false,
1242 .TSFlags: 0x00, /* TSFlags */
1243 .SpillStackID: 0, /* SpillStackID */
1244 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1245 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1246 .SuperClasses: GPR32NONZERO_and_GPRMM16MovePSuperclasses, .SuperClassesSize: 4,
1247 .OrderFunc: nullptr
1248 };
1249
1250 extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass = {
1251 .MC: &MipsMCRegisterClasses[GPRMM16MovePPairSecondRegClassID],
1252 .SubClassMask: GPRMM16MovePPairSecondSubClassMask,
1253 .SuperRegIndices: SuperRegIdxSeqs + 0,
1254 .LaneMask: LaneBitmask(0x0000000000000001),
1255 .AllocationPriority: 0,
1256 .GlobalPriority: false,
1257 .TSFlags: 0x00, /* TSFlags */
1258 .SpillStackID: 0, /* SpillStackID */
1259 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1260 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1261 .SuperClasses: GPRMM16MovePPairSecondSuperclasses, .SuperClassesSize: 3,
1262 .OrderFunc: nullptr
1263 };
1264
1265 extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass = {
1266 .MC: &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePRegClassID],
1267 .SubClassMask: CPU16Regs_and_GPRMM16MovePSubClassMask,
1268 .SuperRegIndices: SuperRegIdxSeqs + 0,
1269 .LaneMask: LaneBitmask(0x0000000000000001),
1270 .AllocationPriority: 0,
1271 .GlobalPriority: false,
1272 .TSFlags: 0x00, /* TSFlags */
1273 .SpillStackID: 0, /* SpillStackID */
1274 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1275 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1276 .SuperClasses: CPU16Regs_and_GPRMM16MovePSuperclasses, .SuperClassesSize: 8,
1277 .OrderFunc: nullptr
1278 };
1279
1280 extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
1281 .MC: &MipsMCRegisterClasses[GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
1282 .SubClassMask: GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
1283 .SuperRegIndices: SuperRegIdxSeqs + 0,
1284 .LaneMask: LaneBitmask(0x0000000000000001),
1285 .AllocationPriority: 0,
1286 .GlobalPriority: false,
1287 .TSFlags: 0x00, /* TSFlags */
1288 .SpillStackID: 0, /* SpillStackID */
1289 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1290 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1291 .SuperClasses: GPRMM16MoveP_and_GPRMM16ZeroSuperclasses, .SuperClassesSize: 4,
1292 .OrderFunc: nullptr
1293 };
1294
1295 extern const TargetRegisterClass HI32DSPRegClass = {
1296 .MC: &MipsMCRegisterClasses[HI32DSPRegClassID],
1297 .SubClassMask: HI32DSPSubClassMask,
1298 .SuperRegIndices: SuperRegIdxSeqs + 12,
1299 .LaneMask: LaneBitmask(0x0000000000000001),
1300 .AllocationPriority: 0,
1301 .GlobalPriority: false,
1302 .TSFlags: 0x00, /* TSFlags */
1303 .SpillStackID: 0, /* SpillStackID */
1304 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1305 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1306 .SuperClasses: nullptr, .SuperClassesSize: 0,
1307 .OrderFunc: nullptr
1308 };
1309
1310 extern const TargetRegisterClass LO32DSPRegClass = {
1311 .MC: &MipsMCRegisterClasses[LO32DSPRegClassID],
1312 .SubClassMask: LO32DSPSubClassMask,
1313 .SuperRegIndices: SuperRegIdxSeqs + 6,
1314 .LaneMask: LaneBitmask(0x0000000000000001),
1315 .AllocationPriority: 0,
1316 .GlobalPriority: false,
1317 .TSFlags: 0x00, /* TSFlags */
1318 .SpillStackID: 0, /* SpillStackID */
1319 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1320 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1321 .SuperClasses: nullptr, .SuperClassesSize: 0,
1322 .OrderFunc: nullptr
1323 };
1324
1325 extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
1326 .MC: &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],
1327 .SubClassMask: CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,
1328 .SuperRegIndices: SuperRegIdxSeqs + 0,
1329 .LaneMask: LaneBitmask(0x0000000000000001),
1330 .AllocationPriority: 0,
1331 .GlobalPriority: false,
1332 .TSFlags: 0x00, /* TSFlags */
1333 .SpillStackID: 0, /* SpillStackID */
1334 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1335 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1336 .SuperClasses: CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses, .SuperClassesSize: 9,
1337 .OrderFunc: nullptr
1338 };
1339
1340 extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass = {
1341 .MC: &MipsMCRegisterClasses[GPRMM16MovePPairFirstRegClassID],
1342 .SubClassMask: GPRMM16MovePPairFirstSubClassMask,
1343 .SuperRegIndices: SuperRegIdxSeqs + 0,
1344 .LaneMask: LaneBitmask(0x0000000000000001),
1345 .AllocationPriority: 0,
1346 .GlobalPriority: false,
1347 .TSFlags: 0x00, /* TSFlags */
1348 .SpillStackID: 0, /* SpillStackID */
1349 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1350 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1351 .SuperClasses: GPRMM16MovePPairFirstSuperclasses, .SuperClassesSize: 8,
1352 .OrderFunc: nullptr
1353 };
1354
1355 extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
1356 .MC: &MipsMCRegisterClasses[GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
1357 .SubClassMask: GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
1358 .SuperRegIndices: SuperRegIdxSeqs + 0,
1359 .LaneMask: LaneBitmask(0x0000000000000001),
1360 .AllocationPriority: 0,
1361 .GlobalPriority: false,
1362 .TSFlags: 0x00, /* TSFlags */
1363 .SpillStackID: 0, /* SpillStackID */
1364 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1365 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1366 .SuperClasses: GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses, .SuperClassesSize: 12,
1367 .OrderFunc: nullptr
1368 };
1369
1370 extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
1371 .MC: &MipsMCRegisterClasses[GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],
1372 .SubClassMask: GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,
1373 .SuperRegIndices: SuperRegIdxSeqs + 0,
1374 .LaneMask: LaneBitmask(0x0000000000000001),
1375 .AllocationPriority: 0,
1376 .GlobalPriority: false,
1377 .TSFlags: 0x00, /* TSFlags */
1378 .SpillStackID: 0, /* SpillStackID */
1379 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1380 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1381 .SuperClasses: GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses, .SuperClassesSize: 11,
1382 .OrderFunc: nullptr
1383 };
1384
1385 extern const TargetRegisterClass CPURARegRegClass = {
1386 .MC: &MipsMCRegisterClasses[CPURARegRegClassID],
1387 .SubClassMask: CPURARegSubClassMask,
1388 .SuperRegIndices: SuperRegIdxSeqs + 0,
1389 .LaneMask: LaneBitmask(0x0000000000000001),
1390 .AllocationPriority: 0,
1391 .GlobalPriority: false,
1392 .TSFlags: 0x00, /* TSFlags */
1393 .SpillStackID: 0, /* SpillStackID */
1394 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1395 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1396 .SuperClasses: CPURARegSuperclasses, .SuperClassesSize: 3,
1397 .OrderFunc: nullptr
1398 };
1399
1400 extern const TargetRegisterClass CPUSPRegRegClass = {
1401 .MC: &MipsMCRegisterClasses[CPUSPRegRegClassID],
1402 .SubClassMask: CPUSPRegSubClassMask,
1403 .SuperRegIndices: SuperRegIdxSeqs + 0,
1404 .LaneMask: LaneBitmask(0x0000000000000001),
1405 .AllocationPriority: 0,
1406 .GlobalPriority: false,
1407 .TSFlags: 0x00, /* TSFlags */
1408 .SpillStackID: 0, /* SpillStackID */
1409 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1410 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1411 .SuperClasses: CPUSPRegSuperclasses, .SuperClassesSize: 4,
1412 .OrderFunc: nullptr
1413 };
1414
1415 extern const TargetRegisterClass DSPCCRegClass = {
1416 .MC: &MipsMCRegisterClasses[DSPCCRegClassID],
1417 .SubClassMask: DSPCCSubClassMask,
1418 .SuperRegIndices: SuperRegIdxSeqs + 1,
1419 .LaneMask: LaneBitmask(0x0000000000000001),
1420 .AllocationPriority: 0,
1421 .GlobalPriority: false,
1422 .TSFlags: 0x00, /* TSFlags */
1423 .SpillStackID: 0, /* SpillStackID */
1424 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1425 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1426 .SuperClasses: nullptr, .SuperClassesSize: 0,
1427 .OrderFunc: nullptr
1428 };
1429
1430 extern const TargetRegisterClass GP32RegClass = {
1431 .MC: &MipsMCRegisterClasses[GP32RegClassID],
1432 .SubClassMask: GP32SubClassMask,
1433 .SuperRegIndices: SuperRegIdxSeqs + 0,
1434 .LaneMask: LaneBitmask(0x0000000000000001),
1435 .AllocationPriority: 0,
1436 .GlobalPriority: false,
1437 .TSFlags: 0x00, /* TSFlags */
1438 .SpillStackID: 0, /* SpillStackID */
1439 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1440 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1441 .SuperClasses: GP32Superclasses, .SuperClassesSize: 3,
1442 .OrderFunc: nullptr
1443 };
1444
1445 extern const TargetRegisterClass GPR32ZERORegClass = {
1446 .MC: &MipsMCRegisterClasses[GPR32ZERORegClassID],
1447 .SubClassMask: GPR32ZEROSubClassMask,
1448 .SuperRegIndices: SuperRegIdxSeqs + 0,
1449 .LaneMask: LaneBitmask(0x0000000000000001),
1450 .AllocationPriority: 0,
1451 .GlobalPriority: false,
1452 .TSFlags: 0x00, /* TSFlags */
1453 .SpillStackID: 0, /* SpillStackID */
1454 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1455 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1456 .SuperClasses: GPR32ZEROSuperclasses, .SuperClassesSize: 5,
1457 .OrderFunc: nullptr
1458 };
1459
1460 extern const TargetRegisterClass HI32RegClass = {
1461 .MC: &MipsMCRegisterClasses[HI32RegClassID],
1462 .SubClassMask: HI32SubClassMask,
1463 .SuperRegIndices: SuperRegIdxSeqs + 12,
1464 .LaneMask: LaneBitmask(0x0000000000000001),
1465 .AllocationPriority: 0,
1466 .GlobalPriority: false,
1467 .TSFlags: 0x00, /* TSFlags */
1468 .SpillStackID: 0, /* SpillStackID */
1469 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1470 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1471 .SuperClasses: HI32Superclasses, .SuperClassesSize: 1,
1472 .OrderFunc: nullptr
1473 };
1474
1475 extern const TargetRegisterClass LO32RegClass = {
1476 .MC: &MipsMCRegisterClasses[LO32RegClassID],
1477 .SubClassMask: LO32SubClassMask,
1478 .SuperRegIndices: SuperRegIdxSeqs + 6,
1479 .LaneMask: LaneBitmask(0x0000000000000001),
1480 .AllocationPriority: 0,
1481 .GlobalPriority: false,
1482 .TSFlags: 0x00, /* TSFlags */
1483 .SpillStackID: 0, /* SpillStackID */
1484 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1485 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1486 .SuperClasses: LO32Superclasses, .SuperClassesSize: 1,
1487 .OrderFunc: nullptr
1488 };
1489
1490 extern const TargetRegisterClass SP32RegClass = {
1491 .MC: &MipsMCRegisterClasses[SP32RegClassID],
1492 .SubClassMask: SP32SubClassMask,
1493 .SuperRegIndices: SuperRegIdxSeqs + 0,
1494 .LaneMask: LaneBitmask(0x0000000000000001),
1495 .AllocationPriority: 0,
1496 .GlobalPriority: false,
1497 .TSFlags: 0x00, /* TSFlags */
1498 .SpillStackID: 0, /* SpillStackID */
1499 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1500 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1501 .SuperClasses: SP32Superclasses, .SuperClassesSize: 5,
1502 .OrderFunc: nullptr
1503 };
1504
1505 extern const TargetRegisterClass FGR64CCRegClass = {
1506 .MC: &MipsMCRegisterClasses[FGR64CCRegClassID],
1507 .SubClassMask: FGR64CCSubClassMask,
1508 .SuperRegIndices: SuperRegIdxSeqs + 2,
1509 .LaneMask: LaneBitmask(0x0000000000000041),
1510 .AllocationPriority: 0,
1511 .GlobalPriority: false,
1512 .TSFlags: 0x00, /* TSFlags */
1513 .SpillStackID: 0, /* SpillStackID */
1514 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1515 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1516 .SuperClasses: nullptr, .SuperClassesSize: 0,
1517 .OrderFunc: nullptr
1518 };
1519
1520 extern const TargetRegisterClass FGR64RegClass = {
1521 .MC: &MipsMCRegisterClasses[FGR64RegClassID],
1522 .SubClassMask: FGR64SubClassMask,
1523 .SuperRegIndices: SuperRegIdxSeqs + 2,
1524 .LaneMask: LaneBitmask(0x0000000000000041),
1525 .AllocationPriority: 0,
1526 .GlobalPriority: false,
1527 .TSFlags: 0x00, /* TSFlags */
1528 .SpillStackID: 0, /* SpillStackID */
1529 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1530 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1531 .SuperClasses: FGR64Superclasses, .SuperClassesSize: 1,
1532 .OrderFunc: FGR64GetRawAllocationOrder
1533 };
1534
1535 extern const TargetRegisterClass GPR64RegClass = {
1536 .MC: &MipsMCRegisterClasses[GPR64RegClassID],
1537 .SubClassMask: GPR64SubClassMask,
1538 .SuperRegIndices: SuperRegIdxSeqs + 1,
1539 .LaneMask: LaneBitmask(0x0000000000000001),
1540 .AllocationPriority: 0,
1541 .GlobalPriority: false,
1542 .TSFlags: 0x00, /* TSFlags */
1543 .SpillStackID: 0, /* SpillStackID */
1544 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1545 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1546 .SuperClasses: nullptr, .SuperClassesSize: 0,
1547 .OrderFunc: nullptr
1548 };
1549
1550 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass = {
1551 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERORegClassID],
1552 .SubClassMask: GPR64_with_sub_32_in_GPR32NONZEROSubClassMask,
1553 .SuperRegIndices: SuperRegIdxSeqs + 1,
1554 .LaneMask: LaneBitmask(0x0000000000000001),
1555 .AllocationPriority: 0,
1556 .GlobalPriority: false,
1557 .TSFlags: 0x00, /* TSFlags */
1558 .SpillStackID: 0, /* SpillStackID */
1559 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1560 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1561 .SuperClasses: GPR64_with_sub_32_in_GPR32NONZEROSuperclasses, .SuperClassesSize: 1,
1562 .OrderFunc: nullptr
1563 };
1564
1565 extern const TargetRegisterClass AFGR64RegClass = {
1566 .MC: &MipsMCRegisterClasses[AFGR64RegClassID],
1567 .SubClassMask: AFGR64SubClassMask,
1568 .SuperRegIndices: SuperRegIdxSeqs + 1,
1569 .LaneMask: LaneBitmask(0x0000000000000041),
1570 .AllocationPriority: 0,
1571 .GlobalPriority: false,
1572 .TSFlags: 0x00, /* TSFlags */
1573 .SpillStackID: 0, /* SpillStackID */
1574 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1575 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1576 .SuperClasses: nullptr, .SuperClassesSize: 0,
1577 .OrderFunc: nullptr
1578 };
1579
1580 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass = {
1581 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID],
1582 .SubClassMask: GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask,
1583 .SuperRegIndices: SuperRegIdxSeqs + 1,
1584 .LaneMask: LaneBitmask(0x0000000000000001),
1585 .AllocationPriority: 0,
1586 .GlobalPriority: false,
1587 .TSFlags: 0x00, /* TSFlags */
1588 .SpillStackID: 0, /* SpillStackID */
1589 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1590 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1591 .SuperClasses: GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses, .SuperClassesSize: 2,
1592 .OrderFunc: nullptr
1593 };
1594
1595 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass = {
1596 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsRegClassID],
1597 .SubClassMask: GPR64_with_sub_32_in_CPU16RegsSubClassMask,
1598 .SuperRegIndices: SuperRegIdxSeqs + 1,
1599 .LaneMask: LaneBitmask(0x0000000000000001),
1600 .AllocationPriority: 0,
1601 .GlobalPriority: false,
1602 .TSFlags: 0x00, /* TSFlags */
1603 .SpillStackID: 0, /* SpillStackID */
1604 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1605 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1606 .SuperClasses: GPR64_with_sub_32_in_CPU16RegsSuperclasses, .SuperClassesSize: 3,
1607 .OrderFunc: nullptr
1608 };
1609
1610 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass = {
1611 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePRegClassID],
1612 .SubClassMask: GPR64_with_sub_32_in_GPRMM16MovePSubClassMask,
1613 .SuperRegIndices: SuperRegIdxSeqs + 1,
1614 .LaneMask: LaneBitmask(0x0000000000000001),
1615 .AllocationPriority: 0,
1616 .GlobalPriority: false,
1617 .TSFlags: 0x00, /* TSFlags */
1618 .SpillStackID: 0, /* SpillStackID */
1619 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1620 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1621 .SuperClasses: GPR64_with_sub_32_in_GPRMM16MovePSuperclasses, .SuperClassesSize: 1,
1622 .OrderFunc: nullptr
1623 };
1624
1625 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass = {
1626 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16ZeroRegClassID],
1627 .SubClassMask: GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask,
1628 .SuperRegIndices: SuperRegIdxSeqs + 1,
1629 .LaneMask: LaneBitmask(0x0000000000000001),
1630 .AllocationPriority: 0,
1631 .GlobalPriority: false,
1632 .TSFlags: 0x00, /* TSFlags */
1633 .SpillStackID: 0, /* SpillStackID */
1634 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1635 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1636 .SuperClasses: GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses, .SuperClassesSize: 1,
1637 .OrderFunc: nullptr
1638 };
1639
1640 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass = {
1641 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID],
1642 .SubClassMask: GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask,
1643 .SuperRegIndices: SuperRegIdxSeqs + 1,
1644 .LaneMask: LaneBitmask(0x0000000000000001),
1645 .AllocationPriority: 0,
1646 .GlobalPriority: false,
1647 .TSFlags: 0x00, /* TSFlags */
1648 .SpillStackID: 0, /* SpillStackID */
1649 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1650 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1651 .SuperClasses: GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses, .SuperClassesSize: 5,
1652 .OrderFunc: nullptr
1653 };
1654
1655 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass = {
1656 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID],
1657 .SubClassMask: GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask,
1658 .SuperRegIndices: SuperRegIdxSeqs + 1,
1659 .LaneMask: LaneBitmask(0x0000000000000001),
1660 .AllocationPriority: 0,
1661 .GlobalPriority: false,
1662 .TSFlags: 0x00, /* TSFlags */
1663 .SpillStackID: 0, /* SpillStackID */
1664 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1665 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1666 .SuperClasses: GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses, .SuperClassesSize: 3,
1667 .OrderFunc: nullptr
1668 };
1669
1670 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass = {
1671 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID],
1672 .SubClassMask: GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask,
1673 .SuperRegIndices: SuperRegIdxSeqs + 1,
1674 .LaneMask: LaneBitmask(0x0000000000000001),
1675 .AllocationPriority: 0,
1676 .GlobalPriority: false,
1677 .TSFlags: 0x00, /* TSFlags */
1678 .SpillStackID: 0, /* SpillStackID */
1679 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1680 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1681 .SuperClasses: GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses, .SuperClassesSize: 2,
1682 .OrderFunc: nullptr
1683 };
1684
1685 extern const TargetRegisterClass ACC64DSPRegClass = {
1686 .MC: &MipsMCRegisterClasses[ACC64DSPRegClassID],
1687 .SubClassMask: ACC64DSPSubClassMask,
1688 .SuperRegIndices: SuperRegIdxSeqs + 16,
1689 .LaneMask: LaneBitmask(0x0000000000000041),
1690 .AllocationPriority: 0,
1691 .GlobalPriority: false,
1692 .TSFlags: 0x00, /* TSFlags */
1693 .SpillStackID: 0, /* SpillStackID */
1694 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1695 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1696 .SuperClasses: nullptr, .SuperClassesSize: 0,
1697 .OrderFunc: nullptr
1698 };
1699
1700 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass = {
1701 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID],
1702 .SubClassMask: GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask,
1703 .SuperRegIndices: SuperRegIdxSeqs + 1,
1704 .LaneMask: LaneBitmask(0x0000000000000001),
1705 .AllocationPriority: 0,
1706 .GlobalPriority: false,
1707 .TSFlags: 0x00, /* TSFlags */
1708 .SpillStackID: 0, /* SpillStackID */
1709 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1710 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1711 .SuperClasses: GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses, .SuperClassesSize: 6,
1712 .OrderFunc: nullptr
1713 };
1714
1715 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
1716 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
1717 .SubClassMask: GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
1718 .SuperRegIndices: SuperRegIdxSeqs + 1,
1719 .LaneMask: LaneBitmask(0x0000000000000001),
1720 .AllocationPriority: 0,
1721 .GlobalPriority: false,
1722 .TSFlags: 0x00, /* TSFlags */
1723 .SpillStackID: 0, /* SpillStackID */
1724 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1725 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1726 .SuperClasses: GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses, .SuperClassesSize: 3,
1727 .OrderFunc: nullptr
1728 };
1729
1730 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
1731 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],
1732 .SubClassMask: GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,
1733 .SuperRegIndices: SuperRegIdxSeqs + 1,
1734 .LaneMask: LaneBitmask(0x0000000000000001),
1735 .AllocationPriority: 0,
1736 .GlobalPriority: false,
1737 .TSFlags: 0x00, /* TSFlags */
1738 .SpillStackID: 0, /* SpillStackID */
1739 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1740 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1741 .SuperClasses: GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses, .SuperClassesSize: 7,
1742 .OrderFunc: nullptr
1743 };
1744
1745 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass = {
1746 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID],
1747 .SubClassMask: GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask,
1748 .SuperRegIndices: SuperRegIdxSeqs + 1,
1749 .LaneMask: LaneBitmask(0x0000000000000001),
1750 .AllocationPriority: 0,
1751 .GlobalPriority: false,
1752 .TSFlags: 0x00, /* TSFlags */
1753 .SpillStackID: 0, /* SpillStackID */
1754 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1755 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1756 .SuperClasses: GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses, .SuperClassesSize: 6,
1757 .OrderFunc: nullptr
1758 };
1759
1760 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
1761 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
1762 .SubClassMask: GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
1763 .SuperRegIndices: SuperRegIdxSeqs + 1,
1764 .LaneMask: LaneBitmask(0x0000000000000001),
1765 .AllocationPriority: 0,
1766 .GlobalPriority: false,
1767 .TSFlags: 0x00, /* TSFlags */
1768 .SpillStackID: 0, /* SpillStackID */
1769 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1770 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1771 .SuperClasses: GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses, .SuperClassesSize: 10,
1772 .OrderFunc: nullptr
1773 };
1774
1775 extern const TargetRegisterClass OCTEON_MPLRegClass = {
1776 .MC: &MipsMCRegisterClasses[OCTEON_MPLRegClassID],
1777 .SubClassMask: OCTEON_MPLSubClassMask,
1778 .SuperRegIndices: SuperRegIdxSeqs + 1,
1779 .LaneMask: LaneBitmask(0x0000000000000001),
1780 .AllocationPriority: 0,
1781 .GlobalPriority: false,
1782 .TSFlags: 0x00, /* TSFlags */
1783 .SpillStackID: 0, /* SpillStackID */
1784 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1785 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1786 .SuperClasses: nullptr, .SuperClassesSize: 0,
1787 .OrderFunc: nullptr
1788 };
1789
1790 extern const TargetRegisterClass OCTEON_PRegClass = {
1791 .MC: &MipsMCRegisterClasses[OCTEON_PRegClassID],
1792 .SubClassMask: OCTEON_PSubClassMask,
1793 .SuperRegIndices: SuperRegIdxSeqs + 1,
1794 .LaneMask: LaneBitmask(0x0000000000000001),
1795 .AllocationPriority: 0,
1796 .GlobalPriority: false,
1797 .TSFlags: 0x00, /* TSFlags */
1798 .SpillStackID: 0, /* SpillStackID */
1799 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1800 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1801 .SuperClasses: nullptr, .SuperClassesSize: 0,
1802 .OrderFunc: nullptr
1803 };
1804
1805 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
1806 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],
1807 .SubClassMask: GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,
1808 .SuperRegIndices: SuperRegIdxSeqs + 1,
1809 .LaneMask: LaneBitmask(0x0000000000000001),
1810 .AllocationPriority: 0,
1811 .GlobalPriority: false,
1812 .TSFlags: 0x00, /* TSFlags */
1813 .SpillStackID: 0, /* SpillStackID */
1814 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1815 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1816 .SuperClasses: GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses, .SuperClassesSize: 9,
1817 .OrderFunc: nullptr
1818 };
1819
1820 extern const TargetRegisterClass ACC64RegClass = {
1821 .MC: &MipsMCRegisterClasses[ACC64RegClassID],
1822 .SubClassMask: ACC64SubClassMask,
1823 .SuperRegIndices: SuperRegIdxSeqs + 16,
1824 .LaneMask: LaneBitmask(0x0000000000000041),
1825 .AllocationPriority: 0,
1826 .GlobalPriority: false,
1827 .TSFlags: 0x00, /* TSFlags */
1828 .SpillStackID: 0, /* SpillStackID */
1829 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1830 .CoveredBySubRegs: true, /* CoveredBySubRegs */
1831 .SuperClasses: ACC64Superclasses, .SuperClassesSize: 1,
1832 .OrderFunc: nullptr
1833 };
1834
1835 extern const TargetRegisterClass GP64RegClass = {
1836 .MC: &MipsMCRegisterClasses[GP64RegClassID],
1837 .SubClassMask: GP64SubClassMask,
1838 .SuperRegIndices: SuperRegIdxSeqs + 1,
1839 .LaneMask: LaneBitmask(0x0000000000000001),
1840 .AllocationPriority: 0,
1841 .GlobalPriority: false,
1842 .TSFlags: 0x00, /* TSFlags */
1843 .SpillStackID: 0, /* SpillStackID */
1844 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1845 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1846 .SuperClasses: GP64Superclasses, .SuperClassesSize: 2,
1847 .OrderFunc: nullptr
1848 };
1849
1850 extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass = {
1851 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPURARegRegClassID],
1852 .SubClassMask: GPR64_with_sub_32_in_CPURARegSubClassMask,
1853 .SuperRegIndices: SuperRegIdxSeqs + 1,
1854 .LaneMask: LaneBitmask(0x0000000000000001),
1855 .AllocationPriority: 0,
1856 .GlobalPriority: false,
1857 .TSFlags: 0x00, /* TSFlags */
1858 .SpillStackID: 0, /* SpillStackID */
1859 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1860 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1861 .SuperClasses: GPR64_with_sub_32_in_CPURARegSuperclasses, .SuperClassesSize: 2,
1862 .OrderFunc: nullptr
1863 };
1864
1865 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass = {
1866 .MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32ZERORegClassID],
1867 .SubClassMask: GPR64_with_sub_32_in_GPR32ZEROSubClassMask,
1868 .SuperRegIndices: SuperRegIdxSeqs + 1,
1869 .LaneMask: LaneBitmask(0x0000000000000001),
1870 .AllocationPriority: 0,
1871 .GlobalPriority: false,
1872 .TSFlags: 0x00, /* TSFlags */
1873 .SpillStackID: 0, /* SpillStackID */
1874 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1875 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1876 .SuperClasses: GPR64_with_sub_32_in_GPR32ZEROSuperclasses, .SuperClassesSize: 4,
1877 .OrderFunc: nullptr
1878 };
1879
1880 extern const TargetRegisterClass HI64RegClass = {
1881 .MC: &MipsMCRegisterClasses[HI64RegClassID],
1882 .SubClassMask: HI64SubClassMask,
1883 .SuperRegIndices: SuperRegIdxSeqs + 4,
1884 .LaneMask: LaneBitmask(0x0000000000000001),
1885 .AllocationPriority: 0,
1886 .GlobalPriority: false,
1887 .TSFlags: 0x00, /* TSFlags */
1888 .SpillStackID: 0, /* SpillStackID */
1889 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1890 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1891 .SuperClasses: nullptr, .SuperClassesSize: 0,
1892 .OrderFunc: nullptr
1893 };
1894
1895 extern const TargetRegisterClass LO64RegClass = {
1896 .MC: &MipsMCRegisterClasses[LO64RegClassID],
1897 .SubClassMask: LO64SubClassMask,
1898 .SuperRegIndices: SuperRegIdxSeqs + 7,
1899 .LaneMask: LaneBitmask(0x0000000000000001),
1900 .AllocationPriority: 0,
1901 .GlobalPriority: false,
1902 .TSFlags: 0x00, /* TSFlags */
1903 .SpillStackID: 0, /* SpillStackID */
1904 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1905 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1906 .SuperClasses: nullptr, .SuperClassesSize: 0,
1907 .OrderFunc: nullptr
1908 };
1909
1910 extern const TargetRegisterClass SP64RegClass = {
1911 .MC: &MipsMCRegisterClasses[SP64RegClassID],
1912 .SubClassMask: SP64SubClassMask,
1913 .SuperRegIndices: SuperRegIdxSeqs + 1,
1914 .LaneMask: LaneBitmask(0x0000000000000001),
1915 .AllocationPriority: 0,
1916 .GlobalPriority: false,
1917 .TSFlags: 0x00, /* TSFlags */
1918 .SpillStackID: 0, /* SpillStackID */
1919 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
1920 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1921 .SuperClasses: SP64Superclasses, .SuperClassesSize: 3,
1922 .OrderFunc: nullptr
1923 };
1924
1925 extern const TargetRegisterClass MSA128BRegClass = {
1926 .MC: &MipsMCRegisterClasses[MSA128BRegClassID],
1927 .SubClassMask: MSA128BSubClassMask,
1928 .SuperRegIndices: SuperRegIdxSeqs + 1,
1929 .LaneMask: LaneBitmask(0x0000000000000041),
1930 .AllocationPriority: 0,
1931 .GlobalPriority: false,
1932 .TSFlags: 0x00, /* TSFlags */
1933 .SpillStackID: 0, /* SpillStackID */
1934 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1935 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1936 .SuperClasses: MSA128BSuperclasses, .SuperClassesSize: 3,
1937 .OrderFunc: nullptr
1938 };
1939
1940 extern const TargetRegisterClass MSA128DRegClass = {
1941 .MC: &MipsMCRegisterClasses[MSA128DRegClassID],
1942 .SubClassMask: MSA128DSubClassMask,
1943 .SuperRegIndices: SuperRegIdxSeqs + 1,
1944 .LaneMask: LaneBitmask(0x0000000000000041),
1945 .AllocationPriority: 0,
1946 .GlobalPriority: false,
1947 .TSFlags: 0x00, /* TSFlags */
1948 .SpillStackID: 0, /* SpillStackID */
1949 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1950 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1951 .SuperClasses: MSA128DSuperclasses, .SuperClassesSize: 3,
1952 .OrderFunc: nullptr
1953 };
1954
1955 extern const TargetRegisterClass MSA128HRegClass = {
1956 .MC: &MipsMCRegisterClasses[MSA128HRegClassID],
1957 .SubClassMask: MSA128HSubClassMask,
1958 .SuperRegIndices: SuperRegIdxSeqs + 1,
1959 .LaneMask: LaneBitmask(0x0000000000000041),
1960 .AllocationPriority: 0,
1961 .GlobalPriority: false,
1962 .TSFlags: 0x00, /* TSFlags */
1963 .SpillStackID: 0, /* SpillStackID */
1964 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1965 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1966 .SuperClasses: MSA128HSuperclasses, .SuperClassesSize: 3,
1967 .OrderFunc: nullptr
1968 };
1969
1970 extern const TargetRegisterClass MSA128WRegClass = {
1971 .MC: &MipsMCRegisterClasses[MSA128WRegClassID],
1972 .SubClassMask: MSA128WSubClassMask,
1973 .SuperRegIndices: SuperRegIdxSeqs + 1,
1974 .LaneMask: LaneBitmask(0x0000000000000041),
1975 .AllocationPriority: 0,
1976 .GlobalPriority: false,
1977 .TSFlags: 0x00, /* TSFlags */
1978 .SpillStackID: 0, /* SpillStackID */
1979 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1980 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1981 .SuperClasses: MSA128WSuperclasses, .SuperClassesSize: 3,
1982 .OrderFunc: nullptr
1983 };
1984
1985 extern const TargetRegisterClass MSA128WEvensRegClass = {
1986 .MC: &MipsMCRegisterClasses[MSA128WEvensRegClassID],
1987 .SubClassMask: MSA128WEvensSubClassMask,
1988 .SuperRegIndices: SuperRegIdxSeqs + 1,
1989 .LaneMask: LaneBitmask(0x0000000000000041),
1990 .AllocationPriority: 0,
1991 .GlobalPriority: false,
1992 .TSFlags: 0x00, /* TSFlags */
1993 .SpillStackID: 0, /* SpillStackID */
1994 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
1995 .CoveredBySubRegs: false, /* CoveredBySubRegs */
1996 .SuperClasses: MSA128WEvensSuperclasses, .SuperClassesSize: 4,
1997 .OrderFunc: nullptr
1998 };
1999
2000 extern const TargetRegisterClass ACC128RegClass = {
2001 .MC: &MipsMCRegisterClasses[ACC128RegClassID],
2002 .SubClassMask: ACC128SubClassMask,
2003 .SuperRegIndices: SuperRegIdxSeqs + 1,
2004 .LaneMask: LaneBitmask(0x0000000000000041),
2005 .AllocationPriority: 0,
2006 .GlobalPriority: false,
2007 .TSFlags: 0x00, /* TSFlags */
2008 .SpillStackID: 0, /* SpillStackID */
2009 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
2010 .CoveredBySubRegs: true, /* CoveredBySubRegs */
2011 .SuperClasses: nullptr, .SuperClassesSize: 0,
2012 .OrderFunc: nullptr
2013 };
2014
2015
2016} // namespace Mips
2017static const TargetRegisterClass *const MipsRegisterClasses[] = {
2018 &Mips::CCRRegClass,
2019 &Mips::COP0RegClass,
2020 &Mips::COP2RegClass,
2021 &Mips::COP3RegClass,
2022 &Mips::DSPRRegClass,
2023 &Mips::FGR32RegClass,
2024 &Mips::FGR32CCRegClass,
2025 &Mips::GPR32RegClass,
2026 &Mips::HWRegsRegClass,
2027 &Mips::MSACtrlRegClass,
2028 &Mips::GPR32NONZERORegClass,
2029 &Mips::CPU16RegsPlusSPRegClass,
2030 &Mips::CPU16RegsRegClass,
2031 &Mips::FCCRegClass,
2032 &Mips::GPRMM16RegClass,
2033 &Mips::GPRMM16MovePRegClass,
2034 &Mips::GPRMM16ZeroRegClass,
2035 &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
2036 &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
2037 &Mips::GPRMM16MovePPairSecondRegClass,
2038 &Mips::CPU16Regs_and_GPRMM16MovePRegClass,
2039 &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
2040 &Mips::HI32DSPRegClass,
2041 &Mips::LO32DSPRegClass,
2042 &Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
2043 &Mips::GPRMM16MovePPairFirstRegClass,
2044 &Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
2045 &Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,
2046 &Mips::CPURARegRegClass,
2047 &Mips::CPUSPRegRegClass,
2048 &Mips::DSPCCRegClass,
2049 &Mips::GP32RegClass,
2050 &Mips::GPR32ZERORegClass,
2051 &Mips::HI32RegClass,
2052 &Mips::LO32RegClass,
2053 &Mips::SP32RegClass,
2054 &Mips::FGR64CCRegClass,
2055 &Mips::FGR64RegClass,
2056 &Mips::GPR64RegClass,
2057 &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
2058 &Mips::AFGR64RegClass,
2059 &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
2060 &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
2061 &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
2062 &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
2063 &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
2064 &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
2065 &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,
2066 &Mips::ACC64DSPRegClass,
2067 &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,
2068 &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
2069 &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
2070 &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,
2071 &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
2072 &Mips::OCTEON_MPLRegClass,
2073 &Mips::OCTEON_PRegClass,
2074 &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,
2075 &Mips::ACC64RegClass,
2076 &Mips::GP64RegClass,
2077 &Mips::GPR64_with_sub_32_in_CPURARegRegClass,
2078 &Mips::GPR64_with_sub_32_in_GPR32ZERORegClass,
2079 &Mips::HI64RegClass,
2080 &Mips::LO64RegClass,
2081 &Mips::SP64RegClass,
2082 &Mips::MSA128BRegClass,
2083 &Mips::MSA128DRegClass,
2084 &Mips::MSA128HRegClass,
2085 &Mips::MSA128WRegClass,
2086 &Mips::MSA128WEvensRegClass,
2087 &Mips::ACC128RegClass,
2088 };
2089
2090static const uint8_t MipsCostPerUseTable[] = {
20910, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
2092
2093
2094static const bool MipsInAllocatableClassTable[] = {
2095false, true, true, false, false, false, false, false, true, true, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
2096
2097
2098static const TargetRegisterInfoDesc MipsRegInfoDesc = { // Extra Descriptors
2099.CostPerUse: MipsCostPerUseTable, .NumCosts: 1, .InAllocatableClass: MipsInAllocatableClassTable};
2100
2101unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
2102 static const uint8_t RowMap[11] = {
2103 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
2104 };
2105 static const uint8_t Rows[2][11] = {
2106 { Mips::sub_hi_then_sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, 0, 0, },
2107 { Mips::sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi_then_sub_32, Mips::sub_32, 0, 0, },
2108 };
2109
2110 --IdxA; assert(IdxA < 11); (void) IdxA;
2111 --IdxB; assert(IdxB < 11);
2112 return Rows[RowMap[IdxA]][IdxB];
2113}
2114
2115unsigned MipsGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
2116 static const uint8_t Table[11][11] = {
2117 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
2118 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
2119 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
2120 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
2121 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
2122 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
2123 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
2124 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
2125 { Mips::sub_32, 0, 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, 0, },
2126 { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
2127 { Mips::sub_32, 0, 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, 0, },
2128 };
2129
2130 --IdxA; assert(IdxA < 11);
2131 --IdxB; assert(IdxB < 11);
2132 return Table[IdxA][IdxB];
2133 }
2134
2135 struct MaskRolOp {
2136 LaneBitmask Mask;
2137 uint8_t RotateLeft;
2138 };
2139 static const MaskRolOp LaneMaskComposeSequences[] = {
2140 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
2141 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
2142 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
2143 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 6
2144 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 4 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 8
2145 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 5 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 10
2146 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 6 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 12
2147 };
2148 static const uint8_t CompositeSequences[] = {
2149 0, // to sub_32
2150 0, // to sub_64
2151 2, // to sub_dsp16_19
2152 4, // to sub_dsp20
2153 6, // to sub_dsp21
2154 8, // to sub_dsp22
2155 10, // to sub_dsp23
2156 12, // to sub_hi
2157 0, // to sub_lo
2158 12, // to sub_hi_then_sub_32
2159 0 // to sub_32_sub_hi_then_sub_32
2160 };
2161
2162LaneBitmask MipsGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
2163 --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
2164 LaneBitmask Result;
2165 for (const MaskRolOp *Ops =
2166 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
2167 Ops->Mask.any(); ++Ops) {
2168 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
2169 if (unsigned S = Ops->RotateLeft)
2170 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
2171 else
2172 Result |= LaneBitmask(M);
2173 }
2174 return Result;
2175}
2176
2177LaneBitmask MipsGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
2178 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
2179 --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
2180 LaneBitmask Result;
2181 for (const MaskRolOp *Ops =
2182 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
2183 Ops->Mask.any(); ++Ops) {
2184 LaneBitmask::Type M = LaneMask.getAsInteger();
2185 if (unsigned S = Ops->RotateLeft)
2186 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
2187 else
2188 Result |= LaneBitmask(M);
2189 }
2190 return Result;
2191}
2192
2193const TargetRegisterClass *MipsGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
2194 static constexpr uint8_t Table[70][11] = {
2195 { // CCR
2196 0, // sub_32
2197 0, // sub_64
2198 0, // sub_dsp16_19
2199 0, // sub_dsp20
2200 0, // sub_dsp21
2201 0, // sub_dsp22
2202 0, // sub_dsp23
2203 0, // sub_hi
2204 0, // sub_lo
2205 0, // sub_hi_then_sub_32
2206 0, // sub_32_sub_hi_then_sub_32
2207 },
2208 { // COP0
2209 0, // sub_32
2210 0, // sub_64
2211 0, // sub_dsp16_19
2212 0, // sub_dsp20
2213 0, // sub_dsp21
2214 0, // sub_dsp22
2215 0, // sub_dsp23
2216 0, // sub_hi
2217 0, // sub_lo
2218 0, // sub_hi_then_sub_32
2219 0, // sub_32_sub_hi_then_sub_32
2220 },
2221 { // COP2
2222 0, // sub_32
2223 0, // sub_64
2224 0, // sub_dsp16_19
2225 0, // sub_dsp20
2226 0, // sub_dsp21
2227 0, // sub_dsp22
2228 0, // sub_dsp23
2229 0, // sub_hi
2230 0, // sub_lo
2231 0, // sub_hi_then_sub_32
2232 0, // sub_32_sub_hi_then_sub_32
2233 },
2234 { // COP3
2235 0, // sub_32
2236 0, // sub_64
2237 0, // sub_dsp16_19
2238 0, // sub_dsp20
2239 0, // sub_dsp21
2240 0, // sub_dsp22
2241 0, // sub_dsp23
2242 0, // sub_hi
2243 0, // sub_lo
2244 0, // sub_hi_then_sub_32
2245 0, // sub_32_sub_hi_then_sub_32
2246 },
2247 { // DSPR
2248 0, // sub_32
2249 0, // sub_64
2250 0, // sub_dsp16_19
2251 0, // sub_dsp20
2252 0, // sub_dsp21
2253 0, // sub_dsp22
2254 0, // sub_dsp23
2255 0, // sub_hi
2256 0, // sub_lo
2257 0, // sub_hi_then_sub_32
2258 0, // sub_32_sub_hi_then_sub_32
2259 },
2260 { // FGR32
2261 0, // sub_32
2262 0, // sub_64
2263 0, // sub_dsp16_19
2264 0, // sub_dsp20
2265 0, // sub_dsp21
2266 0, // sub_dsp22
2267 0, // sub_dsp23
2268 0, // sub_hi
2269 0, // sub_lo
2270 0, // sub_hi_then_sub_32
2271 0, // sub_32_sub_hi_then_sub_32
2272 },
2273 { // FGR32CC
2274 0, // sub_32
2275 0, // sub_64
2276 0, // sub_dsp16_19
2277 0, // sub_dsp20
2278 0, // sub_dsp21
2279 0, // sub_dsp22
2280 0, // sub_dsp23
2281 0, // sub_hi
2282 0, // sub_lo
2283 0, // sub_hi_then_sub_32
2284 0, // sub_32_sub_hi_then_sub_32
2285 },
2286 { // GPR32
2287 0, // sub_32
2288 0, // sub_64
2289 0, // sub_dsp16_19
2290 0, // sub_dsp20
2291 0, // sub_dsp21
2292 0, // sub_dsp22
2293 0, // sub_dsp23
2294 0, // sub_hi
2295 0, // sub_lo
2296 0, // sub_hi_then_sub_32
2297 0, // sub_32_sub_hi_then_sub_32
2298 },
2299 { // HWRegs
2300 0, // sub_32
2301 0, // sub_64
2302 0, // sub_dsp16_19
2303 0, // sub_dsp20
2304 0, // sub_dsp21
2305 0, // sub_dsp22
2306 0, // sub_dsp23
2307 0, // sub_hi
2308 0, // sub_lo
2309 0, // sub_hi_then_sub_32
2310 0, // sub_32_sub_hi_then_sub_32
2311 },
2312 { // MSACtrl
2313 0, // sub_32
2314 0, // sub_64
2315 0, // sub_dsp16_19
2316 0, // sub_dsp20
2317 0, // sub_dsp21
2318 0, // sub_dsp22
2319 0, // sub_dsp23
2320 0, // sub_hi
2321 0, // sub_lo
2322 0, // sub_hi_then_sub_32
2323 0, // sub_32_sub_hi_then_sub_32
2324 },
2325 { // GPR32NONZERO
2326 0, // sub_32
2327 0, // sub_64
2328 0, // sub_dsp16_19
2329 0, // sub_dsp20
2330 0, // sub_dsp21
2331 0, // sub_dsp22
2332 0, // sub_dsp23
2333 0, // sub_hi
2334 0, // sub_lo
2335 0, // sub_hi_then_sub_32
2336 0, // sub_32_sub_hi_then_sub_32
2337 },
2338 { // CPU16RegsPlusSP
2339 0, // sub_32
2340 0, // sub_64
2341 0, // sub_dsp16_19
2342 0, // sub_dsp20
2343 0, // sub_dsp21
2344 0, // sub_dsp22
2345 0, // sub_dsp23
2346 0, // sub_hi
2347 0, // sub_lo
2348 0, // sub_hi_then_sub_32
2349 0, // sub_32_sub_hi_then_sub_32
2350 },
2351 { // CPU16Regs
2352 0, // sub_32
2353 0, // sub_64
2354 0, // sub_dsp16_19
2355 0, // sub_dsp20
2356 0, // sub_dsp21
2357 0, // sub_dsp22
2358 0, // sub_dsp23
2359 0, // sub_hi
2360 0, // sub_lo
2361 0, // sub_hi_then_sub_32
2362 0, // sub_32_sub_hi_then_sub_32
2363 },
2364 { // FCC
2365 0, // sub_32
2366 0, // sub_64
2367 0, // sub_dsp16_19
2368 0, // sub_dsp20
2369 0, // sub_dsp21
2370 0, // sub_dsp22
2371 0, // sub_dsp23
2372 0, // sub_hi
2373 0, // sub_lo
2374 0, // sub_hi_then_sub_32
2375 0, // sub_32_sub_hi_then_sub_32
2376 },
2377 { // GPRMM16
2378 0, // sub_32
2379 0, // sub_64
2380 0, // sub_dsp16_19
2381 0, // sub_dsp20
2382 0, // sub_dsp21
2383 0, // sub_dsp22
2384 0, // sub_dsp23
2385 0, // sub_hi
2386 0, // sub_lo
2387 0, // sub_hi_then_sub_32
2388 0, // sub_32_sub_hi_then_sub_32
2389 },
2390 { // GPRMM16MoveP
2391 0, // sub_32
2392 0, // sub_64
2393 0, // sub_dsp16_19
2394 0, // sub_dsp20
2395 0, // sub_dsp21
2396 0, // sub_dsp22
2397 0, // sub_dsp23
2398 0, // sub_hi
2399 0, // sub_lo
2400 0, // sub_hi_then_sub_32
2401 0, // sub_32_sub_hi_then_sub_32
2402 },
2403 { // GPRMM16Zero
2404 0, // sub_32
2405 0, // sub_64
2406 0, // sub_dsp16_19
2407 0, // sub_dsp20
2408 0, // sub_dsp21
2409 0, // sub_dsp22
2410 0, // sub_dsp23
2411 0, // sub_hi
2412 0, // sub_lo
2413 0, // sub_hi_then_sub_32
2414 0, // sub_32_sub_hi_then_sub_32
2415 },
2416 { // CPU16Regs_and_GPRMM16Zero
2417 0, // sub_32
2418 0, // sub_64
2419 0, // sub_dsp16_19
2420 0, // sub_dsp20
2421 0, // sub_dsp21
2422 0, // sub_dsp22
2423 0, // sub_dsp23
2424 0, // sub_hi
2425 0, // sub_lo
2426 0, // sub_hi_then_sub_32
2427 0, // sub_32_sub_hi_then_sub_32
2428 },
2429 { // GPR32NONZERO_and_GPRMM16MoveP
2430 0, // sub_32
2431 0, // sub_64
2432 0, // sub_dsp16_19
2433 0, // sub_dsp20
2434 0, // sub_dsp21
2435 0, // sub_dsp22
2436 0, // sub_dsp23
2437 0, // sub_hi
2438 0, // sub_lo
2439 0, // sub_hi_then_sub_32
2440 0, // sub_32_sub_hi_then_sub_32
2441 },
2442 { // GPRMM16MovePPairSecond
2443 0, // sub_32
2444 0, // sub_64
2445 0, // sub_dsp16_19
2446 0, // sub_dsp20
2447 0, // sub_dsp21
2448 0, // sub_dsp22
2449 0, // sub_dsp23
2450 0, // sub_hi
2451 0, // sub_lo
2452 0, // sub_hi_then_sub_32
2453 0, // sub_32_sub_hi_then_sub_32
2454 },
2455 { // CPU16Regs_and_GPRMM16MoveP
2456 0, // sub_32
2457 0, // sub_64
2458 0, // sub_dsp16_19
2459 0, // sub_dsp20
2460 0, // sub_dsp21
2461 0, // sub_dsp22
2462 0, // sub_dsp23
2463 0, // sub_hi
2464 0, // sub_lo
2465 0, // sub_hi_then_sub_32
2466 0, // sub_32_sub_hi_then_sub_32
2467 },
2468 { // GPRMM16MoveP_and_GPRMM16Zero
2469 0, // sub_32
2470 0, // sub_64
2471 0, // sub_dsp16_19
2472 0, // sub_dsp20
2473 0, // sub_dsp21
2474 0, // sub_dsp22
2475 0, // sub_dsp23
2476 0, // sub_hi
2477 0, // sub_lo
2478 0, // sub_hi_then_sub_32
2479 0, // sub_32_sub_hi_then_sub_32
2480 },
2481 { // HI32DSP
2482 0, // sub_32
2483 0, // sub_64
2484 0, // sub_dsp16_19
2485 0, // sub_dsp20
2486 0, // sub_dsp21
2487 0, // sub_dsp22
2488 0, // sub_dsp23
2489 0, // sub_hi
2490 0, // sub_lo
2491 0, // sub_hi_then_sub_32
2492 0, // sub_32_sub_hi_then_sub_32
2493 },
2494 { // LO32DSP
2495 0, // sub_32
2496 0, // sub_64
2497 0, // sub_dsp16_19
2498 0, // sub_dsp20
2499 0, // sub_dsp21
2500 0, // sub_dsp22
2501 0, // sub_dsp23
2502 0, // sub_hi
2503 0, // sub_lo
2504 0, // sub_hi_then_sub_32
2505 0, // sub_32_sub_hi_then_sub_32
2506 },
2507 { // CPU16Regs_and_GPRMM16MovePPairSecond
2508 0, // sub_32
2509 0, // sub_64
2510 0, // sub_dsp16_19
2511 0, // sub_dsp20
2512 0, // sub_dsp21
2513 0, // sub_dsp22
2514 0, // sub_dsp23
2515 0, // sub_hi
2516 0, // sub_lo
2517 0, // sub_hi_then_sub_32
2518 0, // sub_32_sub_hi_then_sub_32
2519 },
2520 { // GPRMM16MovePPairFirst
2521 0, // sub_32
2522 0, // sub_64
2523 0, // sub_dsp16_19
2524 0, // sub_dsp20
2525 0, // sub_dsp21
2526 0, // sub_dsp22
2527 0, // sub_dsp23
2528 0, // sub_hi
2529 0, // sub_lo
2530 0, // sub_hi_then_sub_32
2531 0, // sub_32_sub_hi_then_sub_32
2532 },
2533 { // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
2534 0, // sub_32
2535 0, // sub_64
2536 0, // sub_dsp16_19
2537 0, // sub_dsp20
2538 0, // sub_dsp21
2539 0, // sub_dsp22
2540 0, // sub_dsp23
2541 0, // sub_hi
2542 0, // sub_lo
2543 0, // sub_hi_then_sub_32
2544 0, // sub_32_sub_hi_then_sub_32
2545 },
2546 { // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
2547 0, // sub_32
2548 0, // sub_64
2549 0, // sub_dsp16_19
2550 0, // sub_dsp20
2551 0, // sub_dsp21
2552 0, // sub_dsp22
2553 0, // sub_dsp23
2554 0, // sub_hi
2555 0, // sub_lo
2556 0, // sub_hi_then_sub_32
2557 0, // sub_32_sub_hi_then_sub_32
2558 },
2559 { // CPURAReg
2560 0, // sub_32
2561 0, // sub_64
2562 0, // sub_dsp16_19
2563 0, // sub_dsp20
2564 0, // sub_dsp21
2565 0, // sub_dsp22
2566 0, // sub_dsp23
2567 0, // sub_hi
2568 0, // sub_lo
2569 0, // sub_hi_then_sub_32
2570 0, // sub_32_sub_hi_then_sub_32
2571 },
2572 { // CPUSPReg
2573 0, // sub_32
2574 0, // sub_64
2575 0, // sub_dsp16_19
2576 0, // sub_dsp20
2577 0, // sub_dsp21
2578 0, // sub_dsp22
2579 0, // sub_dsp23
2580 0, // sub_hi
2581 0, // sub_lo
2582 0, // sub_hi_then_sub_32
2583 0, // sub_32_sub_hi_then_sub_32
2584 },
2585 { // DSPCC
2586 0, // sub_32
2587 0, // sub_64
2588 0, // sub_dsp16_19
2589 0, // sub_dsp20
2590 0, // sub_dsp21
2591 0, // sub_dsp22
2592 0, // sub_dsp23
2593 0, // sub_hi
2594 0, // sub_lo
2595 0, // sub_hi_then_sub_32
2596 0, // sub_32_sub_hi_then_sub_32
2597 },
2598 { // GP32
2599 0, // sub_32
2600 0, // sub_64
2601 0, // sub_dsp16_19
2602 0, // sub_dsp20
2603 0, // sub_dsp21
2604 0, // sub_dsp22
2605 0, // sub_dsp23
2606 0, // sub_hi
2607 0, // sub_lo
2608 0, // sub_hi_then_sub_32
2609 0, // sub_32_sub_hi_then_sub_32
2610 },
2611 { // GPR32ZERO
2612 0, // sub_32
2613 0, // sub_64
2614 0, // sub_dsp16_19
2615 0, // sub_dsp20
2616 0, // sub_dsp21
2617 0, // sub_dsp22
2618 0, // sub_dsp23
2619 0, // sub_hi
2620 0, // sub_lo
2621 0, // sub_hi_then_sub_32
2622 0, // sub_32_sub_hi_then_sub_32
2623 },
2624 { // HI32
2625 0, // sub_32
2626 0, // sub_64
2627 0, // sub_dsp16_19
2628 0, // sub_dsp20
2629 0, // sub_dsp21
2630 0, // sub_dsp22
2631 0, // sub_dsp23
2632 0, // sub_hi
2633 0, // sub_lo
2634 0, // sub_hi_then_sub_32
2635 0, // sub_32_sub_hi_then_sub_32
2636 },
2637 { // LO32
2638 0, // sub_32
2639 0, // sub_64
2640 0, // sub_dsp16_19
2641 0, // sub_dsp20
2642 0, // sub_dsp21
2643 0, // sub_dsp22
2644 0, // sub_dsp23
2645 0, // sub_hi
2646 0, // sub_lo
2647 0, // sub_hi_then_sub_32
2648 0, // sub_32_sub_hi_then_sub_32
2649 },
2650 { // SP32
2651 0, // sub_32
2652 0, // sub_64
2653 0, // sub_dsp16_19
2654 0, // sub_dsp20
2655 0, // sub_dsp21
2656 0, // sub_dsp22
2657 0, // sub_dsp23
2658 0, // sub_hi
2659 0, // sub_lo
2660 0, // sub_hi_then_sub_32
2661 0, // sub_32_sub_hi_then_sub_32
2662 },
2663 { // FGR64CC
2664 0, // sub_32
2665 0, // sub_64
2666 0, // sub_dsp16_19
2667 0, // sub_dsp20
2668 0, // sub_dsp21
2669 0, // sub_dsp22
2670 0, // sub_dsp23
2671 37, // sub_hi -> FGR64CC
2672 37, // sub_lo -> FGR64CC
2673 0, // sub_hi_then_sub_32
2674 0, // sub_32_sub_hi_then_sub_32
2675 },
2676 { // FGR64
2677 0, // sub_32
2678 0, // sub_64
2679 0, // sub_dsp16_19
2680 0, // sub_dsp20
2681 0, // sub_dsp21
2682 0, // sub_dsp22
2683 0, // sub_dsp23
2684 38, // sub_hi -> FGR64
2685 38, // sub_lo -> FGR64
2686 0, // sub_hi_then_sub_32
2687 0, // sub_32_sub_hi_then_sub_32
2688 },
2689 { // GPR64
2690 39, // sub_32 -> GPR64
2691 0, // sub_64
2692 0, // sub_dsp16_19
2693 0, // sub_dsp20
2694 0, // sub_dsp21
2695 0, // sub_dsp22
2696 0, // sub_dsp23
2697 0, // sub_hi
2698 0, // sub_lo
2699 0, // sub_hi_then_sub_32
2700 0, // sub_32_sub_hi_then_sub_32
2701 },
2702 { // GPR64_with_sub_32_in_GPR32NONZERO
2703 40, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO
2704 0, // sub_64
2705 0, // sub_dsp16_19
2706 0, // sub_dsp20
2707 0, // sub_dsp21
2708 0, // sub_dsp22
2709 0, // sub_dsp23
2710 0, // sub_hi
2711 0, // sub_lo
2712 0, // sub_hi_then_sub_32
2713 0, // sub_32_sub_hi_then_sub_32
2714 },
2715 { // AFGR64
2716 0, // sub_32
2717 0, // sub_64
2718 0, // sub_dsp16_19
2719 0, // sub_dsp20
2720 0, // sub_dsp21
2721 0, // sub_dsp22
2722 0, // sub_dsp23
2723 41, // sub_hi -> AFGR64
2724 41, // sub_lo -> AFGR64
2725 0, // sub_hi_then_sub_32
2726 0, // sub_32_sub_hi_then_sub_32
2727 },
2728 { // GPR64_with_sub_32_in_CPU16RegsPlusSP
2729 42, // sub_32 -> GPR64_with_sub_32_in_CPU16RegsPlusSP
2730 0, // sub_64
2731 0, // sub_dsp16_19
2732 0, // sub_dsp20
2733 0, // sub_dsp21
2734 0, // sub_dsp22
2735 0, // sub_dsp23
2736 0, // sub_hi
2737 0, // sub_lo
2738 0, // sub_hi_then_sub_32
2739 0, // sub_32_sub_hi_then_sub_32
2740 },
2741 { // GPR64_with_sub_32_in_CPU16Regs
2742 43, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs
2743 0, // sub_64
2744 0, // sub_dsp16_19
2745 0, // sub_dsp20
2746 0, // sub_dsp21
2747 0, // sub_dsp22
2748 0, // sub_dsp23
2749 0, // sub_hi
2750 0, // sub_lo
2751 0, // sub_hi_then_sub_32
2752 0, // sub_32_sub_hi_then_sub_32
2753 },
2754 { // GPR64_with_sub_32_in_GPRMM16MoveP
2755 44, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP
2756 0, // sub_64
2757 0, // sub_dsp16_19
2758 0, // sub_dsp20
2759 0, // sub_dsp21
2760 0, // sub_dsp22
2761 0, // sub_dsp23
2762 0, // sub_hi
2763 0, // sub_lo
2764 0, // sub_hi_then_sub_32
2765 0, // sub_32_sub_hi_then_sub_32
2766 },
2767 { // GPR64_with_sub_32_in_GPRMM16Zero
2768 45, // sub_32 -> GPR64_with_sub_32_in_GPRMM16Zero
2769 0, // sub_64
2770 0, // sub_dsp16_19
2771 0, // sub_dsp20
2772 0, // sub_dsp21
2773 0, // sub_dsp22
2774 0, // sub_dsp23
2775 0, // sub_hi
2776 0, // sub_lo
2777 0, // sub_hi_then_sub_32
2778 0, // sub_32_sub_hi_then_sub_32
2779 },
2780 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
2781 46, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
2782 0, // sub_64
2783 0, // sub_dsp16_19
2784 0, // sub_dsp20
2785 0, // sub_dsp21
2786 0, // sub_dsp22
2787 0, // sub_dsp23
2788 0, // sub_hi
2789 0, // sub_lo
2790 0, // sub_hi_then_sub_32
2791 0, // sub_32_sub_hi_then_sub_32
2792 },
2793 { // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
2794 47, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
2795 0, // sub_64
2796 0, // sub_dsp16_19
2797 0, // sub_dsp20
2798 0, // sub_dsp21
2799 0, // sub_dsp22
2800 0, // sub_dsp23
2801 0, // sub_hi
2802 0, // sub_lo
2803 0, // sub_hi_then_sub_32
2804 0, // sub_32_sub_hi_then_sub_32
2805 },
2806 { // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
2807 48, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairSecond
2808 0, // sub_64
2809 0, // sub_dsp16_19
2810 0, // sub_dsp20
2811 0, // sub_dsp21
2812 0, // sub_dsp22
2813 0, // sub_dsp23
2814 0, // sub_hi
2815 0, // sub_lo
2816 0, // sub_hi_then_sub_32
2817 0, // sub_32_sub_hi_then_sub_32
2818 },
2819 { // ACC64DSP
2820 0, // sub_32
2821 0, // sub_64
2822 0, // sub_dsp16_19
2823 0, // sub_dsp20
2824 0, // sub_dsp21
2825 0, // sub_dsp22
2826 0, // sub_dsp23
2827 49, // sub_hi -> ACC64DSP
2828 49, // sub_lo -> ACC64DSP
2829 0, // sub_hi_then_sub_32
2830 0, // sub_32_sub_hi_then_sub_32
2831 },
2832 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
2833 50, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
2834 0, // sub_64
2835 0, // sub_dsp16_19
2836 0, // sub_dsp20
2837 0, // sub_dsp21
2838 0, // sub_dsp22
2839 0, // sub_dsp23
2840 0, // sub_hi
2841 0, // sub_lo
2842 0, // sub_hi_then_sub_32
2843 0, // sub_32_sub_hi_then_sub_32
2844 },
2845 { // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
2846 51, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
2847 0, // sub_64
2848 0, // sub_dsp16_19
2849 0, // sub_dsp20
2850 0, // sub_dsp21
2851 0, // sub_dsp22
2852 0, // sub_dsp23
2853 0, // sub_hi
2854 0, // sub_lo
2855 0, // sub_hi_then_sub_32
2856 0, // sub_32_sub_hi_then_sub_32
2857 },
2858 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
2859 52, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
2860 0, // sub_64
2861 0, // sub_dsp16_19
2862 0, // sub_dsp20
2863 0, // sub_dsp21
2864 0, // sub_dsp22
2865 0, // sub_dsp23
2866 0, // sub_hi
2867 0, // sub_lo
2868 0, // sub_hi_then_sub_32
2869 0, // sub_32_sub_hi_then_sub_32
2870 },
2871 { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
2872 53, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst
2873 0, // sub_64
2874 0, // sub_dsp16_19
2875 0, // sub_dsp20
2876 0, // sub_dsp21
2877 0, // sub_dsp22
2878 0, // sub_dsp23
2879 0, // sub_hi
2880 0, // sub_lo
2881 0, // sub_hi_then_sub_32
2882 0, // sub_32_sub_hi_then_sub_32
2883 },
2884 { // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
2885 54, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
2886 0, // sub_64
2887 0, // sub_dsp16_19
2888 0, // sub_dsp20
2889 0, // sub_dsp21
2890 0, // sub_dsp22
2891 0, // sub_dsp23
2892 0, // sub_hi
2893 0, // sub_lo
2894 0, // sub_hi_then_sub_32
2895 0, // sub_32_sub_hi_then_sub_32
2896 },
2897 { // OCTEON_MPL
2898 0, // sub_32
2899 0, // sub_64
2900 0, // sub_dsp16_19
2901 0, // sub_dsp20
2902 0, // sub_dsp21
2903 0, // sub_dsp22
2904 0, // sub_dsp23
2905 0, // sub_hi
2906 0, // sub_lo
2907 0, // sub_hi_then_sub_32
2908 0, // sub_32_sub_hi_then_sub_32
2909 },
2910 { // OCTEON_P
2911 0, // sub_32
2912 0, // sub_64
2913 0, // sub_dsp16_19
2914 0, // sub_dsp20
2915 0, // sub_dsp21
2916 0, // sub_dsp22
2917 0, // sub_dsp23
2918 0, // sub_hi
2919 0, // sub_lo
2920 0, // sub_hi_then_sub_32
2921 0, // sub_32_sub_hi_then_sub_32
2922 },
2923 { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
2924 57, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
2925 0, // sub_64
2926 0, // sub_dsp16_19
2927 0, // sub_dsp20
2928 0, // sub_dsp21
2929 0, // sub_dsp22
2930 0, // sub_dsp23
2931 0, // sub_hi
2932 0, // sub_lo
2933 0, // sub_hi_then_sub_32
2934 0, // sub_32_sub_hi_then_sub_32
2935 },
2936 { // ACC64
2937 0, // sub_32
2938 0, // sub_64
2939 0, // sub_dsp16_19
2940 0, // sub_dsp20
2941 0, // sub_dsp21
2942 0, // sub_dsp22
2943 0, // sub_dsp23
2944 58, // sub_hi -> ACC64
2945 58, // sub_lo -> ACC64
2946 0, // sub_hi_then_sub_32
2947 0, // sub_32_sub_hi_then_sub_32
2948 },
2949 { // GP64
2950 59, // sub_32 -> GP64
2951 0, // sub_64
2952 0, // sub_dsp16_19
2953 0, // sub_dsp20
2954 0, // sub_dsp21
2955 0, // sub_dsp22
2956 0, // sub_dsp23
2957 0, // sub_hi
2958 0, // sub_lo
2959 0, // sub_hi_then_sub_32
2960 0, // sub_32_sub_hi_then_sub_32
2961 },
2962 { // GPR64_with_sub_32_in_CPURAReg
2963 60, // sub_32 -> GPR64_with_sub_32_in_CPURAReg
2964 0, // sub_64
2965 0, // sub_dsp16_19
2966 0, // sub_dsp20
2967 0, // sub_dsp21
2968 0, // sub_dsp22
2969 0, // sub_dsp23
2970 0, // sub_hi
2971 0, // sub_lo
2972 0, // sub_hi_then_sub_32
2973 0, // sub_32_sub_hi_then_sub_32
2974 },
2975 { // GPR64_with_sub_32_in_GPR32ZERO
2976 61, // sub_32 -> GPR64_with_sub_32_in_GPR32ZERO
2977 0, // sub_64
2978 0, // sub_dsp16_19
2979 0, // sub_dsp20
2980 0, // sub_dsp21
2981 0, // sub_dsp22
2982 0, // sub_dsp23
2983 0, // sub_hi
2984 0, // sub_lo
2985 0, // sub_hi_then_sub_32
2986 0, // sub_32_sub_hi_then_sub_32
2987 },
2988 { // HI64
2989 62, // sub_32 -> HI64
2990 0, // sub_64
2991 0, // sub_dsp16_19
2992 0, // sub_dsp20
2993 0, // sub_dsp21
2994 0, // sub_dsp22
2995 0, // sub_dsp23
2996 0, // sub_hi
2997 0, // sub_lo
2998 0, // sub_hi_then_sub_32
2999 0, // sub_32_sub_hi_then_sub_32
3000 },
3001 { // LO64
3002 63, // sub_32 -> LO64
3003 0, // sub_64
3004 0, // sub_dsp16_19
3005 0, // sub_dsp20
3006 0, // sub_dsp21
3007 0, // sub_dsp22
3008 0, // sub_dsp23
3009 0, // sub_hi
3010 0, // sub_lo
3011 0, // sub_hi_then_sub_32
3012 0, // sub_32_sub_hi_then_sub_32
3013 },
3014 { // SP64
3015 64, // sub_32 -> SP64
3016 0, // sub_64
3017 0, // sub_dsp16_19
3018 0, // sub_dsp20
3019 0, // sub_dsp21
3020 0, // sub_dsp22
3021 0, // sub_dsp23
3022 0, // sub_hi
3023 0, // sub_lo
3024 0, // sub_hi_then_sub_32
3025 0, // sub_32_sub_hi_then_sub_32
3026 },
3027 { // MSA128B
3028 0, // sub_32
3029 65, // sub_64 -> MSA128B
3030 0, // sub_dsp16_19
3031 0, // sub_dsp20
3032 0, // sub_dsp21
3033 0, // sub_dsp22
3034 0, // sub_dsp23
3035 65, // sub_hi -> MSA128B
3036 65, // sub_lo -> MSA128B
3037 0, // sub_hi_then_sub_32
3038 0, // sub_32_sub_hi_then_sub_32
3039 },
3040 { // MSA128D
3041 0, // sub_32
3042 66, // sub_64 -> MSA128D
3043 0, // sub_dsp16_19
3044 0, // sub_dsp20
3045 0, // sub_dsp21
3046 0, // sub_dsp22
3047 0, // sub_dsp23
3048 66, // sub_hi -> MSA128D
3049 66, // sub_lo -> MSA128D
3050 0, // sub_hi_then_sub_32
3051 0, // sub_32_sub_hi_then_sub_32
3052 },
3053 { // MSA128H
3054 0, // sub_32
3055 67, // sub_64 -> MSA128H
3056 0, // sub_dsp16_19
3057 0, // sub_dsp20
3058 0, // sub_dsp21
3059 0, // sub_dsp22
3060 0, // sub_dsp23
3061 67, // sub_hi -> MSA128H
3062 67, // sub_lo -> MSA128H
3063 0, // sub_hi_then_sub_32
3064 0, // sub_32_sub_hi_then_sub_32
3065 },
3066 { // MSA128W
3067 0, // sub_32
3068 68, // sub_64 -> MSA128W
3069 0, // sub_dsp16_19
3070 0, // sub_dsp20
3071 0, // sub_dsp21
3072 0, // sub_dsp22
3073 0, // sub_dsp23
3074 68, // sub_hi -> MSA128W
3075 68, // sub_lo -> MSA128W
3076 0, // sub_hi_then_sub_32
3077 0, // sub_32_sub_hi_then_sub_32
3078 },
3079 { // MSA128WEvens
3080 0, // sub_32
3081 69, // sub_64 -> MSA128WEvens
3082 0, // sub_dsp16_19
3083 0, // sub_dsp20
3084 0, // sub_dsp21
3085 0, // sub_dsp22
3086 0, // sub_dsp23
3087 69, // sub_hi -> MSA128WEvens
3088 69, // sub_lo -> MSA128WEvens
3089 0, // sub_hi_then_sub_32
3090 0, // sub_32_sub_hi_then_sub_32
3091 },
3092 { // ACC128
3093 70, // sub_32 -> ACC128
3094 0, // sub_64
3095 0, // sub_dsp16_19
3096 0, // sub_dsp20
3097 0, // sub_dsp21
3098 0, // sub_dsp22
3099 0, // sub_dsp23
3100 70, // sub_hi -> ACC128
3101 70, // sub_lo -> ACC128
3102 70, // sub_hi_then_sub_32 -> ACC128
3103 70, // sub_32_sub_hi_then_sub_32 -> ACC128
3104 },
3105
3106 };
3107 assert(RC && "Missing regclass");
3108 if (!Idx) return RC;
3109 --Idx;
3110 assert(Idx < 11 && "Bad subreg");
3111 unsigned TV = Table[RC->getID()][Idx];
3112 return TV ? getRegClass(i: TV - 1) : nullptr;
3113}const TargetRegisterClass *MipsGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
3114 static constexpr uint8_t Table[70][11] = {
3115 { // CCR
3116 0, // CCR:sub_32
3117 0, // CCR:sub_64
3118 0, // CCR:sub_dsp16_19
3119 0, // CCR:sub_dsp20
3120 0, // CCR:sub_dsp21
3121 0, // CCR:sub_dsp22
3122 0, // CCR:sub_dsp23
3123 0, // CCR:sub_hi
3124 0, // CCR:sub_lo
3125 0, // CCR:sub_hi_then_sub_32
3126 0, // CCR:sub_32_sub_hi_then_sub_32
3127 },
3128 { // COP0
3129 0, // COP0:sub_32
3130 0, // COP0:sub_64
3131 0, // COP0:sub_dsp16_19
3132 0, // COP0:sub_dsp20
3133 0, // COP0:sub_dsp21
3134 0, // COP0:sub_dsp22
3135 0, // COP0:sub_dsp23
3136 0, // COP0:sub_hi
3137 0, // COP0:sub_lo
3138 0, // COP0:sub_hi_then_sub_32
3139 0, // COP0:sub_32_sub_hi_then_sub_32
3140 },
3141 { // COP2
3142 0, // COP2:sub_32
3143 0, // COP2:sub_64
3144 0, // COP2:sub_dsp16_19
3145 0, // COP2:sub_dsp20
3146 0, // COP2:sub_dsp21
3147 0, // COP2:sub_dsp22
3148 0, // COP2:sub_dsp23
3149 0, // COP2:sub_hi
3150 0, // COP2:sub_lo
3151 0, // COP2:sub_hi_then_sub_32
3152 0, // COP2:sub_32_sub_hi_then_sub_32
3153 },
3154 { // COP3
3155 0, // COP3:sub_32
3156 0, // COP3:sub_64
3157 0, // COP3:sub_dsp16_19
3158 0, // COP3:sub_dsp20
3159 0, // COP3:sub_dsp21
3160 0, // COP3:sub_dsp22
3161 0, // COP3:sub_dsp23
3162 0, // COP3:sub_hi
3163 0, // COP3:sub_lo
3164 0, // COP3:sub_hi_then_sub_32
3165 0, // COP3:sub_32_sub_hi_then_sub_32
3166 },
3167 { // DSPR
3168 0, // DSPR:sub_32
3169 0, // DSPR:sub_64
3170 0, // DSPR:sub_dsp16_19
3171 0, // DSPR:sub_dsp20
3172 0, // DSPR:sub_dsp21
3173 0, // DSPR:sub_dsp22
3174 0, // DSPR:sub_dsp23
3175 0, // DSPR:sub_hi
3176 0, // DSPR:sub_lo
3177 0, // DSPR:sub_hi_then_sub_32
3178 0, // DSPR:sub_32_sub_hi_then_sub_32
3179 },
3180 { // FGR32
3181 0, // FGR32:sub_32
3182 0, // FGR32:sub_64
3183 0, // FGR32:sub_dsp16_19
3184 0, // FGR32:sub_dsp20
3185 0, // FGR32:sub_dsp21
3186 0, // FGR32:sub_dsp22
3187 0, // FGR32:sub_dsp23
3188 0, // FGR32:sub_hi
3189 0, // FGR32:sub_lo
3190 0, // FGR32:sub_hi_then_sub_32
3191 0, // FGR32:sub_32_sub_hi_then_sub_32
3192 },
3193 { // FGR32CC
3194 0, // FGR32CC:sub_32
3195 0, // FGR32CC:sub_64
3196 0, // FGR32CC:sub_dsp16_19
3197 0, // FGR32CC:sub_dsp20
3198 0, // FGR32CC:sub_dsp21
3199 0, // FGR32CC:sub_dsp22
3200 0, // FGR32CC:sub_dsp23
3201 0, // FGR32CC:sub_hi
3202 0, // FGR32CC:sub_lo
3203 0, // FGR32CC:sub_hi_then_sub_32
3204 0, // FGR32CC:sub_32_sub_hi_then_sub_32
3205 },
3206 { // GPR32
3207 0, // GPR32:sub_32
3208 0, // GPR32:sub_64
3209 0, // GPR32:sub_dsp16_19
3210 0, // GPR32:sub_dsp20
3211 0, // GPR32:sub_dsp21
3212 0, // GPR32:sub_dsp22
3213 0, // GPR32:sub_dsp23
3214 0, // GPR32:sub_hi
3215 0, // GPR32:sub_lo
3216 0, // GPR32:sub_hi_then_sub_32
3217 0, // GPR32:sub_32_sub_hi_then_sub_32
3218 },
3219 { // HWRegs
3220 0, // HWRegs:sub_32
3221 0, // HWRegs:sub_64
3222 0, // HWRegs:sub_dsp16_19
3223 0, // HWRegs:sub_dsp20
3224 0, // HWRegs:sub_dsp21
3225 0, // HWRegs:sub_dsp22
3226 0, // HWRegs:sub_dsp23
3227 0, // HWRegs:sub_hi
3228 0, // HWRegs:sub_lo
3229 0, // HWRegs:sub_hi_then_sub_32
3230 0, // HWRegs:sub_32_sub_hi_then_sub_32
3231 },
3232 { // MSACtrl
3233 0, // MSACtrl:sub_32
3234 0, // MSACtrl:sub_64
3235 0, // MSACtrl:sub_dsp16_19
3236 0, // MSACtrl:sub_dsp20
3237 0, // MSACtrl:sub_dsp21
3238 0, // MSACtrl:sub_dsp22
3239 0, // MSACtrl:sub_dsp23
3240 0, // MSACtrl:sub_hi
3241 0, // MSACtrl:sub_lo
3242 0, // MSACtrl:sub_hi_then_sub_32
3243 0, // MSACtrl:sub_32_sub_hi_then_sub_32
3244 },
3245 { // GPR32NONZERO
3246 0, // GPR32NONZERO:sub_32
3247 0, // GPR32NONZERO:sub_64
3248 0, // GPR32NONZERO:sub_dsp16_19
3249 0, // GPR32NONZERO:sub_dsp20
3250 0, // GPR32NONZERO:sub_dsp21
3251 0, // GPR32NONZERO:sub_dsp22
3252 0, // GPR32NONZERO:sub_dsp23
3253 0, // GPR32NONZERO:sub_hi
3254 0, // GPR32NONZERO:sub_lo
3255 0, // GPR32NONZERO:sub_hi_then_sub_32
3256 0, // GPR32NONZERO:sub_32_sub_hi_then_sub_32
3257 },
3258 { // CPU16RegsPlusSP
3259 0, // CPU16RegsPlusSP:sub_32
3260 0, // CPU16RegsPlusSP:sub_64
3261 0, // CPU16RegsPlusSP:sub_dsp16_19
3262 0, // CPU16RegsPlusSP:sub_dsp20
3263 0, // CPU16RegsPlusSP:sub_dsp21
3264 0, // CPU16RegsPlusSP:sub_dsp22
3265 0, // CPU16RegsPlusSP:sub_dsp23
3266 0, // CPU16RegsPlusSP:sub_hi
3267 0, // CPU16RegsPlusSP:sub_lo
3268 0, // CPU16RegsPlusSP:sub_hi_then_sub_32
3269 0, // CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32
3270 },
3271 { // CPU16Regs
3272 0, // CPU16Regs:sub_32
3273 0, // CPU16Regs:sub_64
3274 0, // CPU16Regs:sub_dsp16_19
3275 0, // CPU16Regs:sub_dsp20
3276 0, // CPU16Regs:sub_dsp21
3277 0, // CPU16Regs:sub_dsp22
3278 0, // CPU16Regs:sub_dsp23
3279 0, // CPU16Regs:sub_hi
3280 0, // CPU16Regs:sub_lo
3281 0, // CPU16Regs:sub_hi_then_sub_32
3282 0, // CPU16Regs:sub_32_sub_hi_then_sub_32
3283 },
3284 { // FCC
3285 0, // FCC:sub_32
3286 0, // FCC:sub_64
3287 0, // FCC:sub_dsp16_19
3288 0, // FCC:sub_dsp20
3289 0, // FCC:sub_dsp21
3290 0, // FCC:sub_dsp22
3291 0, // FCC:sub_dsp23
3292 0, // FCC:sub_hi
3293 0, // FCC:sub_lo
3294 0, // FCC:sub_hi_then_sub_32
3295 0, // FCC:sub_32_sub_hi_then_sub_32
3296 },
3297 { // GPRMM16
3298 0, // GPRMM16:sub_32
3299 0, // GPRMM16:sub_64
3300 0, // GPRMM16:sub_dsp16_19
3301 0, // GPRMM16:sub_dsp20
3302 0, // GPRMM16:sub_dsp21
3303 0, // GPRMM16:sub_dsp22
3304 0, // GPRMM16:sub_dsp23
3305 0, // GPRMM16:sub_hi
3306 0, // GPRMM16:sub_lo
3307 0, // GPRMM16:sub_hi_then_sub_32
3308 0, // GPRMM16:sub_32_sub_hi_then_sub_32
3309 },
3310 { // GPRMM16MoveP
3311 0, // GPRMM16MoveP:sub_32
3312 0, // GPRMM16MoveP:sub_64
3313 0, // GPRMM16MoveP:sub_dsp16_19
3314 0, // GPRMM16MoveP:sub_dsp20
3315 0, // GPRMM16MoveP:sub_dsp21
3316 0, // GPRMM16MoveP:sub_dsp22
3317 0, // GPRMM16MoveP:sub_dsp23
3318 0, // GPRMM16MoveP:sub_hi
3319 0, // GPRMM16MoveP:sub_lo
3320 0, // GPRMM16MoveP:sub_hi_then_sub_32
3321 0, // GPRMM16MoveP:sub_32_sub_hi_then_sub_32
3322 },
3323 { // GPRMM16Zero
3324 0, // GPRMM16Zero:sub_32
3325 0, // GPRMM16Zero:sub_64
3326 0, // GPRMM16Zero:sub_dsp16_19
3327 0, // GPRMM16Zero:sub_dsp20
3328 0, // GPRMM16Zero:sub_dsp21
3329 0, // GPRMM16Zero:sub_dsp22
3330 0, // GPRMM16Zero:sub_dsp23
3331 0, // GPRMM16Zero:sub_hi
3332 0, // GPRMM16Zero:sub_lo
3333 0, // GPRMM16Zero:sub_hi_then_sub_32
3334 0, // GPRMM16Zero:sub_32_sub_hi_then_sub_32
3335 },
3336 { // CPU16Regs_and_GPRMM16Zero
3337 0, // CPU16Regs_and_GPRMM16Zero:sub_32
3338 0, // CPU16Regs_and_GPRMM16Zero:sub_64
3339 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
3340 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp20
3341 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp21
3342 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp22
3343 0, // CPU16Regs_and_GPRMM16Zero:sub_dsp23
3344 0, // CPU16Regs_and_GPRMM16Zero:sub_hi
3345 0, // CPU16Regs_and_GPRMM16Zero:sub_lo
3346 0, // CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
3347 0, // CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
3348 },
3349 { // GPR32NONZERO_and_GPRMM16MoveP
3350 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_32
3351 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_64
3352 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19
3353 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20
3354 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21
3355 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22
3356 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23
3357 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi
3358 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_lo
3359 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32
3360 0, // GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
3361 },
3362 { // GPRMM16MovePPairSecond
3363 0, // GPRMM16MovePPairSecond:sub_32
3364 0, // GPRMM16MovePPairSecond:sub_64
3365 0, // GPRMM16MovePPairSecond:sub_dsp16_19
3366 0, // GPRMM16MovePPairSecond:sub_dsp20
3367 0, // GPRMM16MovePPairSecond:sub_dsp21
3368 0, // GPRMM16MovePPairSecond:sub_dsp22
3369 0, // GPRMM16MovePPairSecond:sub_dsp23
3370 0, // GPRMM16MovePPairSecond:sub_hi
3371 0, // GPRMM16MovePPairSecond:sub_lo
3372 0, // GPRMM16MovePPairSecond:sub_hi_then_sub_32
3373 0, // GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
3374 },
3375 { // CPU16Regs_and_GPRMM16MoveP
3376 0, // CPU16Regs_and_GPRMM16MoveP:sub_32
3377 0, // CPU16Regs_and_GPRMM16MoveP:sub_64
3378 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19
3379 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp20
3380 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp21
3381 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp22
3382 0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp23
3383 0, // CPU16Regs_and_GPRMM16MoveP:sub_hi
3384 0, // CPU16Regs_and_GPRMM16MoveP:sub_lo
3385 0, // CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32
3386 0, // CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
3387 },
3388 { // GPRMM16MoveP_and_GPRMM16Zero
3389 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_32
3390 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_64
3391 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19
3392 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20
3393 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21
3394 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22
3395 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23
3396 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi
3397 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_lo
3398 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32
3399 0, // GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
3400 },
3401 { // HI32DSP
3402 0, // HI32DSP:sub_32
3403 0, // HI32DSP:sub_64
3404 0, // HI32DSP:sub_dsp16_19
3405 0, // HI32DSP:sub_dsp20
3406 0, // HI32DSP:sub_dsp21
3407 0, // HI32DSP:sub_dsp22
3408 0, // HI32DSP:sub_dsp23
3409 0, // HI32DSP:sub_hi
3410 0, // HI32DSP:sub_lo
3411 0, // HI32DSP:sub_hi_then_sub_32
3412 0, // HI32DSP:sub_32_sub_hi_then_sub_32
3413 },
3414 { // LO32DSP
3415 0, // LO32DSP:sub_32
3416 0, // LO32DSP:sub_64
3417 0, // LO32DSP:sub_dsp16_19
3418 0, // LO32DSP:sub_dsp20
3419 0, // LO32DSP:sub_dsp21
3420 0, // LO32DSP:sub_dsp22
3421 0, // LO32DSP:sub_dsp23
3422 0, // LO32DSP:sub_hi
3423 0, // LO32DSP:sub_lo
3424 0, // LO32DSP:sub_hi_then_sub_32
3425 0, // LO32DSP:sub_32_sub_hi_then_sub_32
3426 },
3427 { // CPU16Regs_and_GPRMM16MovePPairSecond
3428 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32
3429 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_64
3430 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19
3431 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20
3432 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21
3433 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22
3434 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23
3435 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi
3436 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo
3437 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
3438 0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
3439 },
3440 { // GPRMM16MovePPairFirst
3441 0, // GPRMM16MovePPairFirst:sub_32
3442 0, // GPRMM16MovePPairFirst:sub_64
3443 0, // GPRMM16MovePPairFirst:sub_dsp16_19
3444 0, // GPRMM16MovePPairFirst:sub_dsp20
3445 0, // GPRMM16MovePPairFirst:sub_dsp21
3446 0, // GPRMM16MovePPairFirst:sub_dsp22
3447 0, // GPRMM16MovePPairFirst:sub_dsp23
3448 0, // GPRMM16MovePPairFirst:sub_hi
3449 0, // GPRMM16MovePPairFirst:sub_lo
3450 0, // GPRMM16MovePPairFirst:sub_hi_then_sub_32
3451 0, // GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32
3452 },
3453 { // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
3454 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32
3455 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64
3456 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
3457 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20
3458 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21
3459 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22
3460 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23
3461 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi
3462 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo
3463 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
3464 0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
3465 },
3466 { // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
3467 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32
3468 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64
3469 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19
3470 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20
3471 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21
3472 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22
3473 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23
3474 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi
3475 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo
3476 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
3477 0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
3478 },
3479 { // CPURAReg
3480 0, // CPURAReg:sub_32
3481 0, // CPURAReg:sub_64
3482 0, // CPURAReg:sub_dsp16_19
3483 0, // CPURAReg:sub_dsp20
3484 0, // CPURAReg:sub_dsp21
3485 0, // CPURAReg:sub_dsp22
3486 0, // CPURAReg:sub_dsp23
3487 0, // CPURAReg:sub_hi
3488 0, // CPURAReg:sub_lo
3489 0, // CPURAReg:sub_hi_then_sub_32
3490 0, // CPURAReg:sub_32_sub_hi_then_sub_32
3491 },
3492 { // CPUSPReg
3493 0, // CPUSPReg:sub_32
3494 0, // CPUSPReg:sub_64
3495 0, // CPUSPReg:sub_dsp16_19
3496 0, // CPUSPReg:sub_dsp20
3497 0, // CPUSPReg:sub_dsp21
3498 0, // CPUSPReg:sub_dsp22
3499 0, // CPUSPReg:sub_dsp23
3500 0, // CPUSPReg:sub_hi
3501 0, // CPUSPReg:sub_lo
3502 0, // CPUSPReg:sub_hi_then_sub_32
3503 0, // CPUSPReg:sub_32_sub_hi_then_sub_32
3504 },
3505 { // DSPCC
3506 0, // DSPCC:sub_32
3507 0, // DSPCC:sub_64
3508 0, // DSPCC:sub_dsp16_19
3509 0, // DSPCC:sub_dsp20
3510 0, // DSPCC:sub_dsp21
3511 0, // DSPCC:sub_dsp22
3512 0, // DSPCC:sub_dsp23
3513 0, // DSPCC:sub_hi
3514 0, // DSPCC:sub_lo
3515 0, // DSPCC:sub_hi_then_sub_32
3516 0, // DSPCC:sub_32_sub_hi_then_sub_32
3517 },
3518 { // GP32
3519 0, // GP32:sub_32
3520 0, // GP32:sub_64
3521 0, // GP32:sub_dsp16_19
3522 0, // GP32:sub_dsp20
3523 0, // GP32:sub_dsp21
3524 0, // GP32:sub_dsp22
3525 0, // GP32:sub_dsp23
3526 0, // GP32:sub_hi
3527 0, // GP32:sub_lo
3528 0, // GP32:sub_hi_then_sub_32
3529 0, // GP32:sub_32_sub_hi_then_sub_32
3530 },
3531 { // GPR32ZERO
3532 0, // GPR32ZERO:sub_32
3533 0, // GPR32ZERO:sub_64
3534 0, // GPR32ZERO:sub_dsp16_19
3535 0, // GPR32ZERO:sub_dsp20
3536 0, // GPR32ZERO:sub_dsp21
3537 0, // GPR32ZERO:sub_dsp22
3538 0, // GPR32ZERO:sub_dsp23
3539 0, // GPR32ZERO:sub_hi
3540 0, // GPR32ZERO:sub_lo
3541 0, // GPR32ZERO:sub_hi_then_sub_32
3542 0, // GPR32ZERO:sub_32_sub_hi_then_sub_32
3543 },
3544 { // HI32
3545 0, // HI32:sub_32
3546 0, // HI32:sub_64
3547 0, // HI32:sub_dsp16_19
3548 0, // HI32:sub_dsp20
3549 0, // HI32:sub_dsp21
3550 0, // HI32:sub_dsp22
3551 0, // HI32:sub_dsp23
3552 0, // HI32:sub_hi
3553 0, // HI32:sub_lo
3554 0, // HI32:sub_hi_then_sub_32
3555 0, // HI32:sub_32_sub_hi_then_sub_32
3556 },
3557 { // LO32
3558 0, // LO32:sub_32
3559 0, // LO32:sub_64
3560 0, // LO32:sub_dsp16_19
3561 0, // LO32:sub_dsp20
3562 0, // LO32:sub_dsp21
3563 0, // LO32:sub_dsp22
3564 0, // LO32:sub_dsp23
3565 0, // LO32:sub_hi
3566 0, // LO32:sub_lo
3567 0, // LO32:sub_hi_then_sub_32
3568 0, // LO32:sub_32_sub_hi_then_sub_32
3569 },
3570 { // SP32
3571 0, // SP32:sub_32
3572 0, // SP32:sub_64
3573 0, // SP32:sub_dsp16_19
3574 0, // SP32:sub_dsp20
3575 0, // SP32:sub_dsp21
3576 0, // SP32:sub_dsp22
3577 0, // SP32:sub_dsp23
3578 0, // SP32:sub_hi
3579 0, // SP32:sub_lo
3580 0, // SP32:sub_hi_then_sub_32
3581 0, // SP32:sub_32_sub_hi_then_sub_32
3582 },
3583 { // FGR64CC
3584 0, // FGR64CC:sub_32
3585 0, // FGR64CC:sub_64
3586 0, // FGR64CC:sub_dsp16_19
3587 0, // FGR64CC:sub_dsp20
3588 0, // FGR64CC:sub_dsp21
3589 0, // FGR64CC:sub_dsp22
3590 0, // FGR64CC:sub_dsp23
3591 0, // FGR64CC:sub_hi
3592 6, // FGR64CC:sub_lo -> FGR32
3593 0, // FGR64CC:sub_hi_then_sub_32
3594 0, // FGR64CC:sub_32_sub_hi_then_sub_32
3595 },
3596 { // FGR64
3597 0, // FGR64:sub_32
3598 0, // FGR64:sub_64
3599 0, // FGR64:sub_dsp16_19
3600 0, // FGR64:sub_dsp20
3601 0, // FGR64:sub_dsp21
3602 0, // FGR64:sub_dsp22
3603 0, // FGR64:sub_dsp23
3604 0, // FGR64:sub_hi
3605 6, // FGR64:sub_lo -> FGR32
3606 0, // FGR64:sub_hi_then_sub_32
3607 0, // FGR64:sub_32_sub_hi_then_sub_32
3608 },
3609 { // GPR64
3610 5, // GPR64:sub_32 -> DSPR
3611 0, // GPR64:sub_64
3612 0, // GPR64:sub_dsp16_19
3613 0, // GPR64:sub_dsp20
3614 0, // GPR64:sub_dsp21
3615 0, // GPR64:sub_dsp22
3616 0, // GPR64:sub_dsp23
3617 0, // GPR64:sub_hi
3618 0, // GPR64:sub_lo
3619 0, // GPR64:sub_hi_then_sub_32
3620 0, // GPR64:sub_32_sub_hi_then_sub_32
3621 },
3622 { // GPR64_with_sub_32_in_GPR32NONZERO
3623 11, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32 -> GPR32NONZERO
3624 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_64
3625 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp16_19
3626 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp20
3627 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp21
3628 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp22
3629 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp23
3630 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi
3631 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_lo
3632 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi_then_sub_32
3633 0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32_sub_hi_then_sub_32
3634 },
3635 { // AFGR64
3636 0, // AFGR64:sub_32
3637 0, // AFGR64:sub_64
3638 0, // AFGR64:sub_dsp16_19
3639 0, // AFGR64:sub_dsp20
3640 0, // AFGR64:sub_dsp21
3641 0, // AFGR64:sub_dsp22
3642 0, // AFGR64:sub_dsp23
3643 7, // AFGR64:sub_hi -> FGR32CC
3644 7, // AFGR64:sub_lo -> FGR32CC
3645 0, // AFGR64:sub_hi_then_sub_32
3646 0, // AFGR64:sub_32_sub_hi_then_sub_32
3647 },
3648 { // GPR64_with_sub_32_in_CPU16RegsPlusSP
3649 12, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32 -> CPU16RegsPlusSP
3650 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_64
3651 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp16_19
3652 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp20
3653 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp21
3654 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp22
3655 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp23
3656 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi
3657 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_lo
3658 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi_then_sub_32
3659 0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32
3660 },
3661 { // GPR64_with_sub_32_in_CPU16Regs
3662 13, // GPR64_with_sub_32_in_CPU16Regs:sub_32 -> CPU16Regs
3663 0, // GPR64_with_sub_32_in_CPU16Regs:sub_64
3664 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp16_19
3665 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp20
3666 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp21
3667 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp22
3668 0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp23
3669 0, // GPR64_with_sub_32_in_CPU16Regs:sub_hi
3670 0, // GPR64_with_sub_32_in_CPU16Regs:sub_lo
3671 0, // GPR64_with_sub_32_in_CPU16Regs:sub_hi_then_sub_32
3672 0, // GPR64_with_sub_32_in_CPU16Regs:sub_32_sub_hi_then_sub_32
3673 },
3674 { // GPR64_with_sub_32_in_GPRMM16MoveP
3675 16, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32 -> GPRMM16MoveP
3676 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_64
3677 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp16_19
3678 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp20
3679 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp21
3680 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp22
3681 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp23
3682 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi
3683 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_lo
3684 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi_then_sub_32
3685 0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
3686 },
3687 { // GPR64_with_sub_32_in_GPRMM16Zero
3688 17, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32 -> GPRMM16Zero
3689 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_64
3690 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp16_19
3691 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp20
3692 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp21
3693 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp22
3694 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp23
3695 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi
3696 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_lo
3697 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi_then_sub_32
3698 0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32_sub_hi_then_sub_32
3699 },
3700 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
3701 18, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32 -> CPU16Regs_and_GPRMM16Zero
3702 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_64
3703 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
3704 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp20
3705 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp21
3706 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp22
3707 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp23
3708 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi
3709 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_lo
3710 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
3711 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
3712 },
3713 { // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
3714 19, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32 -> GPR32NONZERO_and_GPRMM16MoveP
3715 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_64
3716 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19
3717 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20
3718 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21
3719 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22
3720 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23
3721 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi
3722 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_lo
3723 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32
3724 0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
3725 },
3726 { // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
3727 20, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairSecond
3728 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_64
3729 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp16_19
3730 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp20
3731 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp21
3732 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp22
3733 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp23
3734 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi
3735 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_lo
3736 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi_then_sub_32
3737 0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
3738 },
3739 { // ACC64DSP
3740 0, // ACC64DSP:sub_32
3741 0, // ACC64DSP:sub_64
3742 0, // ACC64DSP:sub_dsp16_19
3743 0, // ACC64DSP:sub_dsp20
3744 0, // ACC64DSP:sub_dsp21
3745 0, // ACC64DSP:sub_dsp22
3746 0, // ACC64DSP:sub_dsp23
3747 23, // ACC64DSP:sub_hi -> HI32DSP
3748 24, // ACC64DSP:sub_lo -> LO32DSP
3749 0, // ACC64DSP:sub_hi_then_sub_32
3750 0, // ACC64DSP:sub_32_sub_hi_then_sub_32
3751 },
3752 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
3753 21, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32 -> CPU16Regs_and_GPRMM16MoveP
3754 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_64
3755 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19
3756 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp20
3757 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp21
3758 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp22
3759 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp23
3760 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi
3761 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_lo
3762 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32
3763 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
3764 },
3765 { // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
3766 22, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_GPRMM16Zero
3767 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_64
3768 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19
3769 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20
3770 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21
3771 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22
3772 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23
3773 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi
3774 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_lo
3775 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32
3776 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
3777 },
3778 { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
3779 25, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32 -> CPU16Regs_and_GPRMM16MovePPairSecond
3780 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_64
3781 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19
3782 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20
3783 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21
3784 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22
3785 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23
3786 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi
3787 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo
3788 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
3789 0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
3790 },
3791 { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
3792 26, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32 -> GPRMM16MovePPairFirst
3793 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_64
3794 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp16_19
3795 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp20
3796 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp21
3797 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp22
3798 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp23
3799 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi
3800 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_lo
3801 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi_then_sub_32
3802 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32
3803 },
3804 { // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
3805 27, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
3806 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64
3807 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
3808 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20
3809 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21
3810 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22
3811 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23
3812 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi
3813 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo
3814 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
3815 0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
3816 },
3817 { // OCTEON_MPL
3818 0, // OCTEON_MPL:sub_32
3819 0, // OCTEON_MPL:sub_64
3820 0, // OCTEON_MPL:sub_dsp16_19
3821 0, // OCTEON_MPL:sub_dsp20
3822 0, // OCTEON_MPL:sub_dsp21
3823 0, // OCTEON_MPL:sub_dsp22
3824 0, // OCTEON_MPL:sub_dsp23
3825 0, // OCTEON_MPL:sub_hi
3826 0, // OCTEON_MPL:sub_lo
3827 0, // OCTEON_MPL:sub_hi_then_sub_32
3828 0, // OCTEON_MPL:sub_32_sub_hi_then_sub_32
3829 },
3830 { // OCTEON_P
3831 0, // OCTEON_P:sub_32
3832 0, // OCTEON_P:sub_64
3833 0, // OCTEON_P:sub_dsp16_19
3834 0, // OCTEON_P:sub_dsp20
3835 0, // OCTEON_P:sub_dsp21
3836 0, // OCTEON_P:sub_dsp22
3837 0, // OCTEON_P:sub_dsp23
3838 0, // OCTEON_P:sub_hi
3839 0, // OCTEON_P:sub_lo
3840 0, // OCTEON_P:sub_hi_then_sub_32
3841 0, // OCTEON_P:sub_32_sub_hi_then_sub_32
3842 },
3843 { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
3844 28, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
3845 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64
3846 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19
3847 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20
3848 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21
3849 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22
3850 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23
3851 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi
3852 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo
3853 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
3854 0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
3855 },
3856 { // ACC64
3857 0, // ACC64:sub_32
3858 0, // ACC64:sub_64
3859 0, // ACC64:sub_dsp16_19
3860 0, // ACC64:sub_dsp20
3861 0, // ACC64:sub_dsp21
3862 0, // ACC64:sub_dsp22
3863 0, // ACC64:sub_dsp23
3864 34, // ACC64:sub_hi -> HI32
3865 35, // ACC64:sub_lo -> LO32
3866 0, // ACC64:sub_hi_then_sub_32
3867 0, // ACC64:sub_32_sub_hi_then_sub_32
3868 },
3869 { // GP64
3870 32, // GP64:sub_32 -> GP32
3871 0, // GP64:sub_64
3872 0, // GP64:sub_dsp16_19
3873 0, // GP64:sub_dsp20
3874 0, // GP64:sub_dsp21
3875 0, // GP64:sub_dsp22
3876 0, // GP64:sub_dsp23
3877 0, // GP64:sub_hi
3878 0, // GP64:sub_lo
3879 0, // GP64:sub_hi_then_sub_32
3880 0, // GP64:sub_32_sub_hi_then_sub_32
3881 },
3882 { // GPR64_with_sub_32_in_CPURAReg
3883 29, // GPR64_with_sub_32_in_CPURAReg:sub_32 -> CPURAReg
3884 0, // GPR64_with_sub_32_in_CPURAReg:sub_64
3885 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp16_19
3886 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp20
3887 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp21
3888 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp22
3889 0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp23
3890 0, // GPR64_with_sub_32_in_CPURAReg:sub_hi
3891 0, // GPR64_with_sub_32_in_CPURAReg:sub_lo
3892 0, // GPR64_with_sub_32_in_CPURAReg:sub_hi_then_sub_32
3893 0, // GPR64_with_sub_32_in_CPURAReg:sub_32_sub_hi_then_sub_32
3894 },
3895 { // GPR64_with_sub_32_in_GPR32ZERO
3896 33, // GPR64_with_sub_32_in_GPR32ZERO:sub_32 -> GPR32ZERO
3897 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_64
3898 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp16_19
3899 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp20
3900 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp21
3901 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp22
3902 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp23
3903 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi
3904 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_lo
3905 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi_then_sub_32
3906 0, // GPR64_with_sub_32_in_GPR32ZERO:sub_32_sub_hi_then_sub_32
3907 },
3908 { // HI64
3909 34, // HI64:sub_32 -> HI32
3910 0, // HI64:sub_64
3911 0, // HI64:sub_dsp16_19
3912 0, // HI64:sub_dsp20
3913 0, // HI64:sub_dsp21
3914 0, // HI64:sub_dsp22
3915 0, // HI64:sub_dsp23
3916 0, // HI64:sub_hi
3917 0, // HI64:sub_lo
3918 0, // HI64:sub_hi_then_sub_32
3919 0, // HI64:sub_32_sub_hi_then_sub_32
3920 },
3921 { // LO64
3922 35, // LO64:sub_32 -> LO32
3923 0, // LO64:sub_64
3924 0, // LO64:sub_dsp16_19
3925 0, // LO64:sub_dsp20
3926 0, // LO64:sub_dsp21
3927 0, // LO64:sub_dsp22
3928 0, // LO64:sub_dsp23
3929 0, // LO64:sub_hi
3930 0, // LO64:sub_lo
3931 0, // LO64:sub_hi_then_sub_32
3932 0, // LO64:sub_32_sub_hi_then_sub_32
3933 },
3934 { // SP64
3935 30, // SP64:sub_32 -> CPUSPReg
3936 0, // SP64:sub_64
3937 0, // SP64:sub_dsp16_19
3938 0, // SP64:sub_dsp20
3939 0, // SP64:sub_dsp21
3940 0, // SP64:sub_dsp22
3941 0, // SP64:sub_dsp23
3942 0, // SP64:sub_hi
3943 0, // SP64:sub_lo
3944 0, // SP64:sub_hi_then_sub_32
3945 0, // SP64:sub_32_sub_hi_then_sub_32
3946 },
3947 { // MSA128B
3948 0, // MSA128B:sub_32
3949 37, // MSA128B:sub_64 -> FGR64CC
3950 0, // MSA128B:sub_dsp16_19
3951 0, // MSA128B:sub_dsp20
3952 0, // MSA128B:sub_dsp21
3953 0, // MSA128B:sub_dsp22
3954 0, // MSA128B:sub_dsp23
3955 0, // MSA128B:sub_hi
3956 6, // MSA128B:sub_lo -> FGR32
3957 0, // MSA128B:sub_hi_then_sub_32
3958 0, // MSA128B:sub_32_sub_hi_then_sub_32
3959 },
3960 { // MSA128D
3961 0, // MSA128D:sub_32
3962 37, // MSA128D:sub_64 -> FGR64CC
3963 0, // MSA128D:sub_dsp16_19
3964 0, // MSA128D:sub_dsp20
3965 0, // MSA128D:sub_dsp21
3966 0, // MSA128D:sub_dsp22
3967 0, // MSA128D:sub_dsp23
3968 0, // MSA128D:sub_hi
3969 6, // MSA128D:sub_lo -> FGR32
3970 0, // MSA128D:sub_hi_then_sub_32
3971 0, // MSA128D:sub_32_sub_hi_then_sub_32
3972 },
3973 { // MSA128H
3974 0, // MSA128H:sub_32
3975 37, // MSA128H:sub_64 -> FGR64CC
3976 0, // MSA128H:sub_dsp16_19
3977 0, // MSA128H:sub_dsp20
3978 0, // MSA128H:sub_dsp21
3979 0, // MSA128H:sub_dsp22
3980 0, // MSA128H:sub_dsp23
3981 0, // MSA128H:sub_hi
3982 6, // MSA128H:sub_lo -> FGR32
3983 0, // MSA128H:sub_hi_then_sub_32
3984 0, // MSA128H:sub_32_sub_hi_then_sub_32
3985 },
3986 { // MSA128W
3987 0, // MSA128W:sub_32
3988 37, // MSA128W:sub_64 -> FGR64CC
3989 0, // MSA128W:sub_dsp16_19
3990 0, // MSA128W:sub_dsp20
3991 0, // MSA128W:sub_dsp21
3992 0, // MSA128W:sub_dsp22
3993 0, // MSA128W:sub_dsp23
3994 0, // MSA128W:sub_hi
3995 6, // MSA128W:sub_lo -> FGR32
3996 0, // MSA128W:sub_hi_then_sub_32
3997 0, // MSA128W:sub_32_sub_hi_then_sub_32
3998 },
3999 { // MSA128WEvens
4000 0, // MSA128WEvens:sub_32
4001 38, // MSA128WEvens:sub_64 -> FGR64
4002 0, // MSA128WEvens:sub_dsp16_19
4003 0, // MSA128WEvens:sub_dsp20
4004 0, // MSA128WEvens:sub_dsp21
4005 0, // MSA128WEvens:sub_dsp22
4006 0, // MSA128WEvens:sub_dsp23
4007 0, // MSA128WEvens:sub_hi
4008 7, // MSA128WEvens:sub_lo -> FGR32CC
4009 0, // MSA128WEvens:sub_hi_then_sub_32
4010 0, // MSA128WEvens:sub_32_sub_hi_then_sub_32
4011 },
4012 { // ACC128
4013 35, // ACC128:sub_32 -> LO32
4014 0, // ACC128:sub_64
4015 0, // ACC128:sub_dsp16_19
4016 0, // ACC128:sub_dsp20
4017 0, // ACC128:sub_dsp21
4018 0, // ACC128:sub_dsp22
4019 0, // ACC128:sub_dsp23
4020 62, // ACC128:sub_hi -> HI64
4021 63, // ACC128:sub_lo -> LO64
4022 34, // ACC128:sub_hi_then_sub_32 -> HI32
4023 58, // ACC128:sub_32_sub_hi_then_sub_32 -> ACC64
4024 },
4025
4026 };
4027 assert(RC && "Missing regclass");
4028 if (!Idx) return RC;
4029 --Idx;
4030 assert(Idx < 11 && "Bad subreg");
4031 unsigned TV = Table[RC->getID()][Idx];
4032 return TV ? getRegClass(i: TV - 1) : nullptr;
4033}/// Get the weight in units of pressure for this register class.
4034const RegClassWeight &MipsGenRegisterInfo::
4035getRegClassWeight(const TargetRegisterClass *RC) const {
4036 static const RegClassWeight RCWeightTable[] = {
4037 {.RegWeight: 0, .WeightLimit: 0}, // CCR
4038 {.RegWeight: 0, .WeightLimit: 0}, // COP0
4039 {.RegWeight: 0, .WeightLimit: 0}, // COP2
4040 {.RegWeight: 0, .WeightLimit: 0}, // COP3
4041 {.RegWeight: 1, .WeightLimit: 32}, // DSPR
4042 {.RegWeight: 1, .WeightLimit: 32}, // FGR32
4043 {.RegWeight: 1, .WeightLimit: 32}, // FGR32CC
4044 {.RegWeight: 1, .WeightLimit: 32}, // GPR32
4045 {.RegWeight: 0, .WeightLimit: 0}, // HWRegs
4046 {.RegWeight: 0, .WeightLimit: 0}, // MSACtrl
4047 {.RegWeight: 1, .WeightLimit: 31}, // GPR32NONZERO
4048 {.RegWeight: 1, .WeightLimit: 9}, // CPU16RegsPlusSP
4049 {.RegWeight: 1, .WeightLimit: 8}, // CPU16Regs
4050 {.RegWeight: 0, .WeightLimit: 0}, // FCC
4051 {.RegWeight: 1, .WeightLimit: 8}, // GPRMM16
4052 {.RegWeight: 1, .WeightLimit: 8}, // GPRMM16MoveP
4053 {.RegWeight: 1, .WeightLimit: 8}, // GPRMM16Zero
4054 {.RegWeight: 1, .WeightLimit: 7}, // CPU16Regs_and_GPRMM16Zero
4055 {.RegWeight: 1, .WeightLimit: 7}, // GPR32NONZERO_and_GPRMM16MoveP
4056 {.RegWeight: 1, .WeightLimit: 5}, // GPRMM16MovePPairSecond
4057 {.RegWeight: 1, .WeightLimit: 4}, // CPU16Regs_and_GPRMM16MoveP
4058 {.RegWeight: 1, .WeightLimit: 4}, // GPRMM16MoveP_and_GPRMM16Zero
4059 {.RegWeight: 1, .WeightLimit: 4}, // HI32DSP
4060 {.RegWeight: 1, .WeightLimit: 4}, // LO32DSP
4061 {.RegWeight: 1, .WeightLimit: 3}, // CPU16Regs_and_GPRMM16MovePPairSecond
4062 {.RegWeight: 1, .WeightLimit: 3}, // GPRMM16MovePPairFirst
4063 {.RegWeight: 1, .WeightLimit: 3}, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
4064 {.RegWeight: 1, .WeightLimit: 2}, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
4065 {.RegWeight: 1, .WeightLimit: 1}, // CPURAReg
4066 {.RegWeight: 1, .WeightLimit: 1}, // CPUSPReg
4067 {.RegWeight: 1, .WeightLimit: 1}, // DSPCC
4068 {.RegWeight: 1, .WeightLimit: 1}, // GP32
4069 {.RegWeight: 1, .WeightLimit: 1}, // GPR32ZERO
4070 {.RegWeight: 1, .WeightLimit: 1}, // HI32
4071 {.RegWeight: 1, .WeightLimit: 1}, // LO32
4072 {.RegWeight: 1, .WeightLimit: 1}, // SP32
4073 {.RegWeight: 2, .WeightLimit: 64}, // FGR64CC
4074 {.RegWeight: 2, .WeightLimit: 64}, // FGR64
4075 {.RegWeight: 1, .WeightLimit: 32}, // GPR64
4076 {.RegWeight: 1, .WeightLimit: 31}, // GPR64_with_sub_32_in_GPR32NONZERO
4077 {.RegWeight: 2, .WeightLimit: 32}, // AFGR64
4078 {.RegWeight: 1, .WeightLimit: 9}, // GPR64_with_sub_32_in_CPU16RegsPlusSP
4079 {.RegWeight: 1, .WeightLimit: 8}, // GPR64_with_sub_32_in_CPU16Regs
4080 {.RegWeight: 1, .WeightLimit: 8}, // GPR64_with_sub_32_in_GPRMM16MoveP
4081 {.RegWeight: 1, .WeightLimit: 8}, // GPR64_with_sub_32_in_GPRMM16Zero
4082 {.RegWeight: 1, .WeightLimit: 7}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
4083 {.RegWeight: 1, .WeightLimit: 7}, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
4084 {.RegWeight: 1, .WeightLimit: 5}, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
4085 {.RegWeight: 2, .WeightLimit: 8}, // ACC64DSP
4086 {.RegWeight: 1, .WeightLimit: 4}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
4087 {.RegWeight: 1, .WeightLimit: 4}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
4088 {.RegWeight: 1, .WeightLimit: 3}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
4089 {.RegWeight: 1, .WeightLimit: 3}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
4090 {.RegWeight: 1, .WeightLimit: 3}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
4091 {.RegWeight: 0, .WeightLimit: 0}, // OCTEON_MPL
4092 {.RegWeight: 0, .WeightLimit: 0}, // OCTEON_P
4093 {.RegWeight: 1, .WeightLimit: 2}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
4094 {.RegWeight: 2, .WeightLimit: 2}, // ACC64
4095 {.RegWeight: 1, .WeightLimit: 1}, // GP64
4096 {.RegWeight: 1, .WeightLimit: 1}, // GPR64_with_sub_32_in_CPURAReg
4097 {.RegWeight: 1, .WeightLimit: 1}, // GPR64_with_sub_32_in_GPR32ZERO
4098 {.RegWeight: 1, .WeightLimit: 1}, // HI64
4099 {.RegWeight: 1, .WeightLimit: 1}, // LO64
4100 {.RegWeight: 1, .WeightLimit: 1}, // SP64
4101 {.RegWeight: 2, .WeightLimit: 64}, // MSA128B
4102 {.RegWeight: 2, .WeightLimit: 64}, // MSA128D
4103 {.RegWeight: 2, .WeightLimit: 64}, // MSA128H
4104 {.RegWeight: 2, .WeightLimit: 64}, // MSA128W
4105 {.RegWeight: 2, .WeightLimit: 32}, // MSA128WEvens
4106 {.RegWeight: 2, .WeightLimit: 2}, // ACC128
4107 };
4108 return RCWeightTable[RC->getID()];
4109}
4110
4111/// Get the weight in units of pressure for this register unit.
4112unsigned MipsGenRegisterInfo::
4113getRegUnitWeight(MCRegUnit RegUnit) const {
4114 assert(static_cast<unsigned>(RegUnit) < 321 && "invalid register unit");
4115 // All register units have unit weight.
4116 return 1;
4117}
4118
4119
4120// Get the number of dimensions of register pressure.
4121unsigned MipsGenRegisterInfo::getNumRegPressureSets() const {
4122 return 20;
4123}
4124
4125// Get the name of this register unit pressure set.
4126const char *MipsGenRegisterInfo::
4127getRegPressureSetName(unsigned Idx) const {
4128 static const char *PressureNameTable[] = {
4129 "DSPCC",
4130 "GPR32ZERO",
4131 "GPR64_with_sub_32_in_CPURAReg",
4132 "HI32",
4133 "GPRMM16MovePPairFirst",
4134 "CPU16Regs_and_GPRMM16MoveP",
4135 "HI32DSP",
4136 "LO32DSP",
4137 "GPRMM16MovePPairSecond",
4138 "GPRMM16MoveP",
4139 "ACC64DSP",
4140 "CPU16Regs",
4141 "GPRMM16Zero_with_GPRMM16MovePPairSecond",
4142 "CPU16Regs_with_GPRMM16MovePPairSecond",
4143 "CPU16Regs_with_GPRMM16MoveP",
4144 "DSPR",
4145 "FGR32",
4146 "MSA128WEvens",
4147 "FGR32_with_MSA128WEvens",
4148 "FGR64CC",
4149 };
4150 return PressureNameTable[Idx];
4151}
4152
4153// Get the register unit pressure limit for this dimension.
4154// This limit must be adjusted dynamically for reserved registers.
4155unsigned MipsGenRegisterInfo::
4156getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
4157 static const uint8_t PressureLimitTable[] = {
4158 1, // 0: DSPCC
4159 1, // 1: GPR32ZERO
4160 1, // 2: GPR64_with_sub_32_in_CPURAReg
4161 2, // 3: HI32
4162 3, // 4: GPRMM16MovePPairFirst
4163 5, // 5: CPU16Regs_and_GPRMM16MoveP
4164 5, // 6: HI32DSP
4165 5, // 7: LO32DSP
4166 6, // 8: GPRMM16MovePPairSecond
4167 8, // 9: GPRMM16MoveP
4168 8, // 10: ACC64DSP
4169 10, // 11: CPU16Regs
4170 10, // 12: GPRMM16Zero_with_GPRMM16MovePPairSecond
4171 11, // 13: CPU16Regs_with_GPRMM16MovePPairSecond
4172 13, // 14: CPU16Regs_with_GPRMM16MoveP
4173 32, // 15: DSPR
4174 32, // 16: FGR32
4175 32, // 17: MSA128WEvens
4176 48, // 18: FGR32_with_MSA128WEvens
4177 64, // 19: FGR64CC
4178 };
4179 return PressureLimitTable[Idx];
4180}
4181
4182/// Table of pressure sets per register class or unit.
4183static const int RCSetsTable[] = {
4184 /* 0 */ 0, -1,
4185 /* 2 */ 6, 10, -1,
4186 /* 5 */ 3, 6, 7, 10, -1,
4187 /* 10 */ 2, 15, -1,
4188 /* 13 */ 8, 12, 13, 15, -1,
4189 /* 18 */ 9, 14, 15, -1,
4190 /* 22 */ 1, 5, 9, 11, 12, 14, 15, -1,
4191 /* 30 */ 5, 9, 11, 13, 14, 15, -1,
4192 /* 37 */ 4, 8, 11, 12, 13, 14, 15, -1,
4193 /* 45 */ 5, 9, 11, 12, 13, 14, 15, -1,
4194 /* 53 */ 16, 18, 19, -1,
4195 /* 57 */ 16, 17, 18, 19, -1,
4196};
4197
4198/// Get the dimensions of register pressure impacted by this register class.
4199/// Returns a -1 terminated array of pressure set IDs
4200const int *MipsGenRegisterInfo::
4201getRegClassPressureSets(const TargetRegisterClass *RC) const {
4202 static const uint8_t RCSetStartTable[] = {
4203 1,1,1,1,11,53,53,11,1,1,11,32,32,1,32,18,25,39,18,13,30,23,2,7,38,37,45,37,1,1,0,1,22,5,5,1,55,55,11,11,53,32,32,18,25,39,18,13,3,30,23,38,37,45,1,1,37,5,1,10,22,5,5,1,55,55,55,55,58,5,};
4204 return &RCSetsTable[RCSetStartTable[RC->getID()]];
4205}
4206
4207/// Get the dimensions of register pressure impacted by this register unit.
4208/// Returns a -1 terminated array of pressure set IDs
4209const int *MipsGenRegisterInfo::
4210getRegUnitPressureSets(MCRegUnit RegUnit) const {
4211 assert(static_cast<unsigned>(RegUnit) < 321 && "invalid register unit");
4212 static const uint8_t RUSetStartTable[] = {
4213 11,0,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,10,32,22,37,37,37,38,5,5,7,2,7,2,7,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,30,45,18,18,18,13,13,11,11,11,11,11,11,11,11,11,11,11,45,45,};
4214 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
4215}
4216
4217
4218// Register to minimal register class mapping
4219
4220const TargetRegisterClass *MipsGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
4221 static const uint16_t InvalidRegClassID = UINT16_MAX;
4222
4223 static const uint16_t Mapping[442] = {
4224 InvalidRegClassID, // NoRegister
4225 Mips::GPR32NONZERORegClassID, // AT
4226 Mips::DSPCCRegClassID, // DSPCCond
4227 InvalidRegClassID, // DSPCarry
4228 InvalidRegClassID, // DSPEFI
4229 InvalidRegClassID, // DSPOutFlag
4230 InvalidRegClassID, // DSPPos
4231 InvalidRegClassID, // DSPSCount
4232 Mips::GPR32NONZERORegClassID, // FP
4233 Mips::GP32RegClassID, // GP
4234 Mips::MSACtrlRegClassID, // MSAAccess
4235 Mips::MSACtrlRegClassID, // MSACSR
4236 Mips::MSACtrlRegClassID, // MSAIR
4237 Mips::MSACtrlRegClassID, // MSAMap
4238 Mips::MSACtrlRegClassID, // MSAModify
4239 Mips::MSACtrlRegClassID, // MSARequest
4240 Mips::MSACtrlRegClassID, // MSASave
4241 Mips::MSACtrlRegClassID, // MSAUnmap
4242 InvalidRegClassID, // PC
4243 Mips::CPURARegRegClassID, // RA
4244 Mips::SP32RegClassID, // SP
4245 Mips::GPR32ZERORegClassID, // ZERO
4246 Mips::GPRMM16MovePPairFirstRegClassID, // A0
4247 Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, // A1
4248 Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, // A2
4249 Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, // A3
4250 Mips::ACC64RegClassID, // AC0
4251 Mips::ACC64DSPRegClassID, // AC1
4252 Mips::ACC64DSPRegClassID, // AC2
4253 Mips::ACC64DSPRegClassID, // AC3
4254 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // AT_64
4255 Mips::COP0RegClassID, // COP00
4256 Mips::COP0RegClassID, // COP01
4257 Mips::COP0RegClassID, // COP02
4258 Mips::COP0RegClassID, // COP03
4259 Mips::COP0RegClassID, // COP04
4260 Mips::COP0RegClassID, // COP05
4261 Mips::COP0RegClassID, // COP06
4262 Mips::COP0RegClassID, // COP07
4263 Mips::COP0RegClassID, // COP08
4264 Mips::COP0RegClassID, // COP09
4265 Mips::COP2RegClassID, // COP20
4266 Mips::COP2RegClassID, // COP21
4267 Mips::COP2RegClassID, // COP22
4268 Mips::COP2RegClassID, // COP23
4269 Mips::COP2RegClassID, // COP24
4270 Mips::COP2RegClassID, // COP25
4271 Mips::COP2RegClassID, // COP26
4272 Mips::COP2RegClassID, // COP27
4273 Mips::COP2RegClassID, // COP28
4274 Mips::COP2RegClassID, // COP29
4275 Mips::COP3RegClassID, // COP30
4276 Mips::COP3RegClassID, // COP31
4277 Mips::COP3RegClassID, // COP32
4278 Mips::COP3RegClassID, // COP33
4279 Mips::COP3RegClassID, // COP34
4280 Mips::COP3RegClassID, // COP35
4281 Mips::COP3RegClassID, // COP36
4282 Mips::COP3RegClassID, // COP37
4283 Mips::COP3RegClassID, // COP38
4284 Mips::COP3RegClassID, // COP39
4285 Mips::COP0RegClassID, // COP010
4286 Mips::COP0RegClassID, // COP011
4287 Mips::COP0RegClassID, // COP012
4288 Mips::COP0RegClassID, // COP013
4289 Mips::COP0RegClassID, // COP014
4290 Mips::COP0RegClassID, // COP015
4291 Mips::COP0RegClassID, // COP016
4292 Mips::COP0RegClassID, // COP017
4293 Mips::COP0RegClassID, // COP018
4294 Mips::COP0RegClassID, // COP019
4295 Mips::COP0RegClassID, // COP020
4296 Mips::COP0RegClassID, // COP021
4297 Mips::COP0RegClassID, // COP022
4298 Mips::COP0RegClassID, // COP023
4299 Mips::COP0RegClassID, // COP024
4300 Mips::COP0RegClassID, // COP025
4301 Mips::COP0RegClassID, // COP026
4302 Mips::COP0RegClassID, // COP027
4303 Mips::COP0RegClassID, // COP028
4304 Mips::COP0RegClassID, // COP029
4305 Mips::COP0RegClassID, // COP030
4306 Mips::COP0RegClassID, // COP031
4307 Mips::COP2RegClassID, // COP210
4308 Mips::COP2RegClassID, // COP211
4309 Mips::COP2RegClassID, // COP212
4310 Mips::COP2RegClassID, // COP213
4311 Mips::COP2RegClassID, // COP214
4312 Mips::COP2RegClassID, // COP215
4313 Mips::COP2RegClassID, // COP216
4314 Mips::COP2RegClassID, // COP217
4315 Mips::COP2RegClassID, // COP218
4316 Mips::COP2RegClassID, // COP219
4317 Mips::COP2RegClassID, // COP220
4318 Mips::COP2RegClassID, // COP221
4319 Mips::COP2RegClassID, // COP222
4320 Mips::COP2RegClassID, // COP223
4321 Mips::COP2RegClassID, // COP224
4322 Mips::COP2RegClassID, // COP225
4323 Mips::COP2RegClassID, // COP226
4324 Mips::COP2RegClassID, // COP227
4325 Mips::COP2RegClassID, // COP228
4326 Mips::COP2RegClassID, // COP229
4327 Mips::COP2RegClassID, // COP230
4328 Mips::COP2RegClassID, // COP231
4329 Mips::COP3RegClassID, // COP310
4330 Mips::COP3RegClassID, // COP311
4331 Mips::COP3RegClassID, // COP312
4332 Mips::COP3RegClassID, // COP313
4333 Mips::COP3RegClassID, // COP314
4334 Mips::COP3RegClassID, // COP315
4335 Mips::COP3RegClassID, // COP316
4336 Mips::COP3RegClassID, // COP317
4337 Mips::COP3RegClassID, // COP318
4338 Mips::COP3RegClassID, // COP319
4339 Mips::COP3RegClassID, // COP320
4340 Mips::COP3RegClassID, // COP321
4341 Mips::COP3RegClassID, // COP322
4342 Mips::COP3RegClassID, // COP323
4343 Mips::COP3RegClassID, // COP324
4344 Mips::COP3RegClassID, // COP325
4345 Mips::COP3RegClassID, // COP326
4346 Mips::COP3RegClassID, // COP327
4347 Mips::COP3RegClassID, // COP328
4348 Mips::COP3RegClassID, // COP329
4349 Mips::COP3RegClassID, // COP330
4350 Mips::COP3RegClassID, // COP331
4351 Mips::AFGR64RegClassID, // D0
4352 Mips::AFGR64RegClassID, // D1
4353 Mips::AFGR64RegClassID, // D2
4354 Mips::AFGR64RegClassID, // D3
4355 Mips::AFGR64RegClassID, // D4
4356 Mips::AFGR64RegClassID, // D5
4357 Mips::AFGR64RegClassID, // D6
4358 Mips::AFGR64RegClassID, // D7
4359 Mips::AFGR64RegClassID, // D8
4360 Mips::AFGR64RegClassID, // D9
4361 Mips::AFGR64RegClassID, // D10
4362 Mips::AFGR64RegClassID, // D11
4363 Mips::AFGR64RegClassID, // D12
4364 Mips::AFGR64RegClassID, // D13
4365 Mips::AFGR64RegClassID, // D14
4366 Mips::AFGR64RegClassID, // D15
4367 InvalidRegClassID, // DSPOutFlag20
4368 InvalidRegClassID, // DSPOutFlag21
4369 InvalidRegClassID, // DSPOutFlag22
4370 InvalidRegClassID, // DSPOutFlag23
4371 Mips::FGR32CCRegClassID, // F0
4372 Mips::FGR32CCRegClassID, // F1
4373 Mips::FGR32CCRegClassID, // F2
4374 Mips::FGR32CCRegClassID, // F3
4375 Mips::FGR32CCRegClassID, // F4
4376 Mips::FGR32CCRegClassID, // F5
4377 Mips::FGR32CCRegClassID, // F6
4378 Mips::FGR32CCRegClassID, // F7
4379 Mips::FGR32CCRegClassID, // F8
4380 Mips::FGR32CCRegClassID, // F9
4381 Mips::FGR32CCRegClassID, // F10
4382 Mips::FGR32CCRegClassID, // F11
4383 Mips::FGR32CCRegClassID, // F12
4384 Mips::FGR32CCRegClassID, // F13
4385 Mips::FGR32CCRegClassID, // F14
4386 Mips::FGR32CCRegClassID, // F15
4387 Mips::FGR32CCRegClassID, // F16
4388 Mips::FGR32CCRegClassID, // F17
4389 Mips::FGR32CCRegClassID, // F18
4390 Mips::FGR32CCRegClassID, // F19
4391 Mips::FGR32CCRegClassID, // F20
4392 Mips::FGR32CCRegClassID, // F21
4393 Mips::FGR32CCRegClassID, // F22
4394 Mips::FGR32CCRegClassID, // F23
4395 Mips::FGR32CCRegClassID, // F24
4396 Mips::FGR32CCRegClassID, // F25
4397 Mips::FGR32CCRegClassID, // F26
4398 Mips::FGR32CCRegClassID, // F27
4399 Mips::FGR32CCRegClassID, // F28
4400 Mips::FGR32CCRegClassID, // F29
4401 Mips::FGR32CCRegClassID, // F30
4402 Mips::FGR32CCRegClassID, // F31
4403 Mips::FCCRegClassID, // FCC0
4404 Mips::FCCRegClassID, // FCC1
4405 Mips::FCCRegClassID, // FCC2
4406 Mips::FCCRegClassID, // FCC3
4407 Mips::FCCRegClassID, // FCC4
4408 Mips::FCCRegClassID, // FCC5
4409 Mips::FCCRegClassID, // FCC6
4410 Mips::FCCRegClassID, // FCC7
4411 Mips::CCRRegClassID, // FCR0
4412 Mips::CCRRegClassID, // FCR1
4413 Mips::CCRRegClassID, // FCR2
4414 Mips::CCRRegClassID, // FCR3
4415 Mips::CCRRegClassID, // FCR4
4416 Mips::CCRRegClassID, // FCR5
4417 Mips::CCRRegClassID, // FCR6
4418 Mips::CCRRegClassID, // FCR7
4419 Mips::CCRRegClassID, // FCR8
4420 Mips::CCRRegClassID, // FCR9
4421 Mips::CCRRegClassID, // FCR10
4422 Mips::CCRRegClassID, // FCR11
4423 Mips::CCRRegClassID, // FCR12
4424 Mips::CCRRegClassID, // FCR13
4425 Mips::CCRRegClassID, // FCR14
4426 Mips::CCRRegClassID, // FCR15
4427 Mips::CCRRegClassID, // FCR16
4428 Mips::CCRRegClassID, // FCR17
4429 Mips::CCRRegClassID, // FCR18
4430 Mips::CCRRegClassID, // FCR19
4431 Mips::CCRRegClassID, // FCR20
4432 Mips::CCRRegClassID, // FCR21
4433 Mips::CCRRegClassID, // FCR22
4434 Mips::CCRRegClassID, // FCR23
4435 Mips::CCRRegClassID, // FCR24
4436 Mips::CCRRegClassID, // FCR25
4437 Mips::CCRRegClassID, // FCR26
4438 Mips::CCRRegClassID, // FCR27
4439 Mips::CCRRegClassID, // FCR28
4440 Mips::CCRRegClassID, // FCR29
4441 Mips::CCRRegClassID, // FCR30
4442 Mips::CCRRegClassID, // FCR31
4443 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // FP_64
4444 InvalidRegClassID, // F_HI0
4445 InvalidRegClassID, // F_HI1
4446 InvalidRegClassID, // F_HI2
4447 InvalidRegClassID, // F_HI3
4448 InvalidRegClassID, // F_HI4
4449 InvalidRegClassID, // F_HI5
4450 InvalidRegClassID, // F_HI6
4451 InvalidRegClassID, // F_HI7
4452 InvalidRegClassID, // F_HI8
4453 InvalidRegClassID, // F_HI9
4454 InvalidRegClassID, // F_HI10
4455 InvalidRegClassID, // F_HI11
4456 InvalidRegClassID, // F_HI12
4457 InvalidRegClassID, // F_HI13
4458 InvalidRegClassID, // F_HI14
4459 InvalidRegClassID, // F_HI15
4460 InvalidRegClassID, // F_HI16
4461 InvalidRegClassID, // F_HI17
4462 InvalidRegClassID, // F_HI18
4463 InvalidRegClassID, // F_HI19
4464 InvalidRegClassID, // F_HI20
4465 InvalidRegClassID, // F_HI21
4466 InvalidRegClassID, // F_HI22
4467 InvalidRegClassID, // F_HI23
4468 InvalidRegClassID, // F_HI24
4469 InvalidRegClassID, // F_HI25
4470 InvalidRegClassID, // F_HI26
4471 InvalidRegClassID, // F_HI27
4472 InvalidRegClassID, // F_HI28
4473 InvalidRegClassID, // F_HI29
4474 InvalidRegClassID, // F_HI30
4475 InvalidRegClassID, // F_HI31
4476 Mips::GP64RegClassID, // GP_64
4477 Mips::HI32RegClassID, // HI0
4478 Mips::HI32DSPRegClassID, // HI1
4479 Mips::HI32DSPRegClassID, // HI2
4480 Mips::HI32DSPRegClassID, // HI3
4481 Mips::HWRegsRegClassID, // HWR0
4482 Mips::HWRegsRegClassID, // HWR1
4483 Mips::HWRegsRegClassID, // HWR2
4484 Mips::HWRegsRegClassID, // HWR3
4485 Mips::HWRegsRegClassID, // HWR4
4486 Mips::HWRegsRegClassID, // HWR5
4487 Mips::HWRegsRegClassID, // HWR6
4488 Mips::HWRegsRegClassID, // HWR7
4489 Mips::HWRegsRegClassID, // HWR8
4490 Mips::HWRegsRegClassID, // HWR9
4491 Mips::HWRegsRegClassID, // HWR10
4492 Mips::HWRegsRegClassID, // HWR11
4493 Mips::HWRegsRegClassID, // HWR12
4494 Mips::HWRegsRegClassID, // HWR13
4495 Mips::HWRegsRegClassID, // HWR14
4496 Mips::HWRegsRegClassID, // HWR15
4497 Mips::HWRegsRegClassID, // HWR16
4498 Mips::HWRegsRegClassID, // HWR17
4499 Mips::HWRegsRegClassID, // HWR18
4500 Mips::HWRegsRegClassID, // HWR19
4501 Mips::HWRegsRegClassID, // HWR20
4502 Mips::HWRegsRegClassID, // HWR21
4503 Mips::HWRegsRegClassID, // HWR22
4504 Mips::HWRegsRegClassID, // HWR23
4505 Mips::HWRegsRegClassID, // HWR24
4506 Mips::HWRegsRegClassID, // HWR25
4507 Mips::HWRegsRegClassID, // HWR26
4508 Mips::HWRegsRegClassID, // HWR27
4509 Mips::HWRegsRegClassID, // HWR28
4510 Mips::HWRegsRegClassID, // HWR29
4511 Mips::HWRegsRegClassID, // HWR30
4512 Mips::HWRegsRegClassID, // HWR31
4513 Mips::GPR32NONZERORegClassID, // K0
4514 Mips::GPR32NONZERORegClassID, // K1
4515 Mips::LO32RegClassID, // LO0
4516 Mips::LO32DSPRegClassID, // LO1
4517 Mips::LO32DSPRegClassID, // LO2
4518 Mips::LO32DSPRegClassID, // LO3
4519 Mips::OCTEON_MPLRegClassID, // MPL0
4520 Mips::OCTEON_MPLRegClassID, // MPL1
4521 Mips::OCTEON_MPLRegClassID, // MPL2
4522 Mips::MSACtrlRegClassID, // MSA8
4523 Mips::MSACtrlRegClassID, // MSA9
4524 Mips::MSACtrlRegClassID, // MSA10
4525 Mips::MSACtrlRegClassID, // MSA11
4526 Mips::MSACtrlRegClassID, // MSA12
4527 Mips::MSACtrlRegClassID, // MSA13
4528 Mips::MSACtrlRegClassID, // MSA14
4529 Mips::MSACtrlRegClassID, // MSA15
4530 Mips::MSACtrlRegClassID, // MSA16
4531 Mips::MSACtrlRegClassID, // MSA17
4532 Mips::MSACtrlRegClassID, // MSA18
4533 Mips::MSACtrlRegClassID, // MSA19
4534 Mips::MSACtrlRegClassID, // MSA20
4535 Mips::MSACtrlRegClassID, // MSA21
4536 Mips::MSACtrlRegClassID, // MSA22
4537 Mips::MSACtrlRegClassID, // MSA23
4538 Mips::MSACtrlRegClassID, // MSA24
4539 Mips::MSACtrlRegClassID, // MSA25
4540 Mips::MSACtrlRegClassID, // MSA26
4541 Mips::MSACtrlRegClassID, // MSA27
4542 Mips::MSACtrlRegClassID, // MSA28
4543 Mips::MSACtrlRegClassID, // MSA29
4544 Mips::MSACtrlRegClassID, // MSA30
4545 Mips::MSACtrlRegClassID, // MSA31
4546 Mips::OCTEON_PRegClassID, // P0
4547 Mips::OCTEON_PRegClassID, // P1
4548 Mips::OCTEON_PRegClassID, // P2
4549 Mips::GPR64_with_sub_32_in_CPURARegRegClassID, // RA_64
4550 Mips::CPU16Regs_and_GPRMM16MovePRegClassID, // S0
4551 Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, // S1
4552 Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, // S2
4553 Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, // S3
4554 Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, // S4
4555 Mips::GPRMM16MovePPairSecondRegClassID, // S5
4556 Mips::GPRMM16MovePPairSecondRegClassID, // S6
4557 Mips::GPR32NONZERORegClassID, // S7
4558 Mips::SP64RegClassID, // SP_64
4559 Mips::GPR32NONZERORegClassID, // T0
4560 Mips::GPR32NONZERORegClassID, // T1
4561 Mips::GPR32NONZERORegClassID, // T2
4562 Mips::GPR32NONZERORegClassID, // T3
4563 Mips::GPR32NONZERORegClassID, // T4
4564 Mips::GPR32NONZERORegClassID, // T5
4565 Mips::GPR32NONZERORegClassID, // T6
4566 Mips::GPR32NONZERORegClassID, // T7
4567 Mips::GPR32NONZERORegClassID, // T8
4568 Mips::GPR32NONZERORegClassID, // T9
4569 Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, // V0
4570 Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, // V1
4571 Mips::MSA128WEvensRegClassID, // W0
4572 Mips::MSA128WRegClassID, // W1
4573 Mips::MSA128WEvensRegClassID, // W2
4574 Mips::MSA128WRegClassID, // W3
4575 Mips::MSA128WEvensRegClassID, // W4
4576 Mips::MSA128WRegClassID, // W5
4577 Mips::MSA128WEvensRegClassID, // W6
4578 Mips::MSA128WRegClassID, // W7
4579 Mips::MSA128WEvensRegClassID, // W8
4580 Mips::MSA128WRegClassID, // W9
4581 Mips::MSA128WEvensRegClassID, // W10
4582 Mips::MSA128WRegClassID, // W11
4583 Mips::MSA128WEvensRegClassID, // W12
4584 Mips::MSA128WRegClassID, // W13
4585 Mips::MSA128WEvensRegClassID, // W14
4586 Mips::MSA128WRegClassID, // W15
4587 Mips::MSA128WEvensRegClassID, // W16
4588 Mips::MSA128WRegClassID, // W17
4589 Mips::MSA128WEvensRegClassID, // W18
4590 Mips::MSA128WRegClassID, // W19
4591 Mips::MSA128WEvensRegClassID, // W20
4592 Mips::MSA128WRegClassID, // W21
4593 Mips::MSA128WEvensRegClassID, // W22
4594 Mips::MSA128WRegClassID, // W23
4595 Mips::MSA128WEvensRegClassID, // W24
4596 Mips::MSA128WRegClassID, // W25
4597 Mips::MSA128WEvensRegClassID, // W26
4598 Mips::MSA128WRegClassID, // W27
4599 Mips::MSA128WEvensRegClassID, // W28
4600 Mips::MSA128WRegClassID, // W29
4601 Mips::MSA128WEvensRegClassID, // W30
4602 Mips::MSA128WRegClassID, // W31
4603 Mips::GPR64_with_sub_32_in_GPR32ZERORegClassID, // ZERO_64
4604 Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID, // A0_64
4605 Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, // A1_64
4606 Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, // A2_64
4607 Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, // A3_64
4608 Mips::ACC128RegClassID, // AC0_64
4609 Mips::FGR64RegClassID, // D0_64
4610 Mips::FGR64RegClassID, // D1_64
4611 Mips::FGR64RegClassID, // D2_64
4612 Mips::FGR64RegClassID, // D3_64
4613 Mips::FGR64RegClassID, // D4_64
4614 Mips::FGR64RegClassID, // D5_64
4615 Mips::FGR64RegClassID, // D6_64
4616 Mips::FGR64RegClassID, // D7_64
4617 Mips::FGR64RegClassID, // D8_64
4618 Mips::FGR64RegClassID, // D9_64
4619 Mips::FGR64RegClassID, // D10_64
4620 Mips::FGR64RegClassID, // D11_64
4621 Mips::FGR64RegClassID, // D12_64
4622 Mips::FGR64RegClassID, // D13_64
4623 Mips::FGR64RegClassID, // D14_64
4624 Mips::FGR64RegClassID, // D15_64
4625 Mips::FGR64RegClassID, // D16_64
4626 Mips::FGR64RegClassID, // D17_64
4627 Mips::FGR64RegClassID, // D18_64
4628 Mips::FGR64RegClassID, // D19_64
4629 Mips::FGR64RegClassID, // D20_64
4630 Mips::FGR64RegClassID, // D21_64
4631 Mips::FGR64RegClassID, // D22_64
4632 Mips::FGR64RegClassID, // D23_64
4633 Mips::FGR64RegClassID, // D24_64
4634 Mips::FGR64RegClassID, // D25_64
4635 Mips::FGR64RegClassID, // D26_64
4636 Mips::FGR64RegClassID, // D27_64
4637 Mips::FGR64RegClassID, // D28_64
4638 Mips::FGR64RegClassID, // D29_64
4639 Mips::FGR64RegClassID, // D30_64
4640 Mips::FGR64RegClassID, // D31_64
4641 InvalidRegClassID, // DSPOutFlag16_19
4642 Mips::HI64RegClassID, // HI0_64
4643 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // K0_64
4644 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // K1_64
4645 Mips::LO64RegClassID, // LO0_64
4646 Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, // S0_64
4647 Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, // S1_64
4648 Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, // S2_64
4649 Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, // S3_64
4650 Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, // S4_64
4651 Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID, // S5_64
4652 Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID, // S6_64
4653 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // S7_64
4654 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // T0_64
4655 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // T1_64
4656 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // T2_64
4657 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // T3_64
4658 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // T4_64
4659 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // T5_64
4660 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // T6_64
4661 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // T7_64
4662 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // T8_64
4663 Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, // T9_64
4664 Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, // V0_64
4665 Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, // V1_64
4666 };
4667
4668 assert(Reg < ArrayRef(Mapping).size());
4669 unsigned RCID = Mapping[Reg.id()];
4670 if (RCID == InvalidRegClassID)
4671 return nullptr;
4672 return MipsRegisterClasses[RCID];
4673}
4674extern const MCRegisterDesc MipsRegDesc[];
4675extern const int16_t MipsRegDiffLists[];
4676extern const LaneBitmask MipsLaneMaskLists[];
4677extern const char MipsRegStrings[];
4678extern const char MipsRegClassStrings[];
4679extern const MCPhysReg MipsRegUnitRoots[][2];
4680extern const uint16_t MipsSubRegIdxLists[];
4681extern const uint16_t MipsRegEncodingTable[];
4682// Mips Dwarf<->LLVM register mappings.
4683extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[];
4684extern const unsigned MipsDwarfFlavour0Dwarf2LSize;
4685
4686extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[];
4687extern const unsigned MipsEHFlavour0Dwarf2LSize;
4688
4689extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[];
4690extern const unsigned MipsDwarfFlavour0L2DwarfSize;
4691
4692extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[];
4693extern const unsigned MipsEHFlavour0L2DwarfSize;
4694
4695
4696MipsGenRegisterInfo::
4697MipsGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
4698 unsigned PC, unsigned HwMode)
4699 : TargetRegisterInfo(&MipsRegInfoDesc, MipsRegisterClasses,
4700 MipsSubRegIndexStrings, MipsSubRegIndexNameOffsets,
4701 MipsSubRegIdxRangeTable, MipsSubRegIndexLaneMaskTable,
4702
4703 LaneBitmask(0xFFFFFFFFFFFFFF80), MipsRegClassInfos, MipsVTLists, HwMode) {
4704 InitMCRegisterInfo(D: MipsRegDesc, NR: 442, RA, PC,
4705 C: MipsMCRegisterClasses, NC: 70, RURoots: MipsRegUnitRoots, NRU: 321, DL: MipsRegDiffLists,
4706 RUMS: MipsLaneMaskLists, Strings: MipsRegStrings, ClassStrings: MipsRegClassStrings, SubIndices: MipsSubRegIdxLists, NumIndices: 12,
4707 RET: MipsRegEncodingTable, RUI: nullptr);
4708
4709 switch (DwarfFlavour) {
4710 default:
4711 llvm_unreachable("Unknown DWARF flavour");
4712 case 0:
4713 mapDwarfRegsToLLVMRegs(Map: MipsDwarfFlavour0Dwarf2L, Size: MipsDwarfFlavour0Dwarf2LSize, isEH: false);
4714 break;
4715 }
4716 switch (EHFlavour) {
4717 default:
4718 llvm_unreachable("Unknown DWARF flavour");
4719 case 0:
4720 mapDwarfRegsToLLVMRegs(Map: MipsEHFlavour0Dwarf2L, Size: MipsEHFlavour0Dwarf2LSize, isEH: true);
4721 break;
4722 }
4723 switch (DwarfFlavour) {
4724 default:
4725 llvm_unreachable("Unknown DWARF flavour");
4726 case 0:
4727 mapLLVMRegsToDwarfRegs(Map: MipsDwarfFlavour0L2Dwarf, Size: MipsDwarfFlavour0L2DwarfSize, isEH: false);
4728 break;
4729 }
4730 switch (EHFlavour) {
4731 default:
4732 llvm_unreachable("Unknown DWARF flavour");
4733 case 0:
4734 mapLLVMRegsToDwarfRegs(Map: MipsEHFlavour0L2Dwarf, Size: MipsEHFlavour0L2DwarfSize, isEH: true);
4735 break;
4736 }
4737}
4738
4739static const MCPhysReg CSR_Interrupt_32_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, Mips::LO0, Mips::HI0, 0 };
4740static const uint32_t CSR_Interrupt_32_RegMask[] = { 0x07e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000, 0x00000008, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };
4741static const MCPhysReg CSR_Interrupt_32R6_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, 0 };
4742static const uint32_t CSR_Interrupt_32R6_RegMask[] = { 0x03e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };
4743static const MCPhysReg CSR_Interrupt_64_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::V1_64, Mips::V0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, Mips::LO0_64, Mips::HI0_64, 0 };
4744static const uint32_t CSR_Interrupt_64_RegMask[] = { 0x47e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x30000000, 0x00000000, 0x00000008, 0x07ffbfe0, 0xf8000000, 0x00000001, 0x03ffffe4, };
4745static const MCPhysReg CSR_Interrupt_64R6_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::V1_64, Mips::V0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, 0 };
4746static const uint32_t CSR_Interrupt_64R6_RegMask[] = { 0x43e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x07ffbfe0, 0xf8000000, 0x00000000, 0x03ffffc0, };
4747static const MCPhysReg CSR_Mips16RetHelper_SaveList[] = { Mips::V0, Mips::V1, Mips::FP, Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, 0 };
4748static const uint32_t CSR_Mips16RetHelper_RegMask[] = { 0x03e00100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06003fc0, 0x08000000, 0x00000000, 0x00000000, };
4749static const MCPhysReg CSR_N32_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
4750static const uint32_t CSR_N32_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x08000000, 0x15550000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xaaa00000, 0x00003fc0, };
4751static const MCPhysReg CSR_N32_SingleFloat_SaveList[] = { Mips::F30, Mips::F28, Mips::F26, Mips::F24, Mips::F22, Mips::F20, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
4752static const uint32_t CSR_N32_SingleFloat_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0x00000000, 0x00003fc0, };
4753static const MCPhysReg CSR_N64_SaveList[] = { Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64, Mips::D26_64, Mips::D25_64, Mips::D24_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
4754static const uint32_t CSR_N64_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00007800, 0x0007f800, 0x08000000, 0x1ff00000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xfe000000, 0x00003fc1, };
4755static const MCPhysReg CSR_N64_SingleFloat_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
4756static const uint32_t CSR_N64_SingleFloat_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00007800, 0x0007f800, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0x00000000, 0x00003fc0, };
4757static const MCPhysReg CSR_O32_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
4758static const uint32_t CSR_O32_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };
4759static const MCPhysReg CSR_O32_FP64_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
4760static const uint32_t CSR_O32_FP64_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x00000000, 0x05550000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0xaaa00000, 0x00000000, };
4761static const MCPhysReg CSR_O32_FPXX_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
4762static const uint32_t CSR_O32_FPXX_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };
4763static const MCPhysReg CSR_O32_SingleFloat_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
4764static const uint32_t CSR_O32_SingleFloat_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };
4765
4766
4767ArrayRef<const uint32_t *> MipsGenRegisterInfo::getRegMasks() const {
4768 static const uint32_t *const Masks[] = {
4769 CSR_Interrupt_32_RegMask,
4770 CSR_Interrupt_32R6_RegMask,
4771 CSR_Interrupt_64_RegMask,
4772 CSR_Interrupt_64R6_RegMask,
4773 CSR_Mips16RetHelper_RegMask,
4774 CSR_N32_RegMask,
4775 CSR_N32_SingleFloat_RegMask,
4776 CSR_N64_RegMask,
4777 CSR_N64_SingleFloat_RegMask,
4778 CSR_O32_RegMask,
4779 CSR_O32_FP64_RegMask,
4780 CSR_O32_FPXX_RegMask,
4781 CSR_O32_SingleFloat_RegMask,
4782 };
4783 return ArrayRef(Masks);
4784}
4785
4786bool MipsGenRegisterInfo::
4787isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
4788 return
4789 false;
4790}
4791
4792bool MipsGenRegisterInfo::
4793isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
4794 return
4795 false;
4796}
4797
4798bool MipsGenRegisterInfo::
4799isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
4800 return
4801 false;
4802}
4803
4804bool MipsGenRegisterInfo::
4805isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
4806 return
4807 false;
4808}
4809
4810bool MipsGenRegisterInfo::
4811isConstantPhysReg(MCRegister PhysReg) const {
4812 return
4813 PhysReg == Mips::ZERO ||
4814 PhysReg == Mips::ZERO_64 ||
4815 false;
4816}
4817
4818ArrayRef<const char *> MipsGenRegisterInfo::getRegMaskNames() const {
4819 static const char *Names[] = {
4820 "CSR_Interrupt_32",
4821 "CSR_Interrupt_32R6",
4822 "CSR_Interrupt_64",
4823 "CSR_Interrupt_64R6",
4824 "CSR_Mips16RetHelper",
4825 "CSR_N32",
4826 "CSR_N32_SingleFloat",
4827 "CSR_N64",
4828 "CSR_N64_SingleFloat",
4829 "CSR_O32",
4830 "CSR_O32_FP64",
4831 "CSR_O32_FPXX",
4832 "CSR_O32_SingleFloat",
4833 };
4834 return ArrayRef(Names);
4835}
4836
4837const MipsFrameLowering *
4838MipsGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
4839 return static_cast<const MipsFrameLowering *>(
4840 MF.getSubtarget().getFrameLowering());
4841}
4842
4843
4844} // namespace llvm
4845