MipsGenRegisterInfoTargetDesc.inc source code [llvm_projects/build/lib/Target/Mips/MipsGenRegisterInfoTargetDesc.inc]

1	/===- TableGen'erated file -------------------------------------- C++ --===\
2	\| \|
3	\| Target Register and Register Classes Information \|
4	\| \|
5	\| Automatically generated file, do not edit! \|
6	\| \|
7	\===----------------------------------------------------------------------===/
8
9	namespace llvm {
10
11	extern const MCRegisterClass MipsMCRegisterClasses[];
12
13	static const MVT::SimpleValueType VTLists[] = {
14	/ 0 / MVT::v4i8, MVT::v2i16, MVT::i32, MVT::Other,
15	/ 4 / MVT::i64, MVT::Other,
16	/ 6 / MVT::f16, MVT::Other,
17	/ 8 / MVT::f32, MVT::Other,
18	/ 10 / MVT::i32, MVT::f32, MVT::f64, MVT::Other,
19	/ 14 / MVT::v16i8, MVT::Other,
20	/ 16 / MVT::v4i8, MVT::v2i16, MVT::Other,
21	/ 19 / MVT::v8i16, MVT::v8f16, MVT::Other,
22	/ 22 / MVT::v4i32, MVT::v4f32, MVT::Other,
23	/ 25 / MVT::v2i64, MVT::v2f64, MVT::Other,
24	/ 28 / MVT::Untyped, MVT::Other,
25	};
26
27	#ifdef __GNUC__
28	#pragma GCC diagnostic push
29	#pragma GCC diagnostic ignored "-Woverlength-strings"
30	#endif
31	static constexpr char MipsSubRegIndexStrings[] = {
32	/ 0 / "sub_dsp20\000"
33	/ 10 / "sub_dsp21\000"
34	/ 20 / "sub_dsp22\000"
35	/ 30 / "sub_32_sub_hi_then_sub_32\000"
36	/ 56 / "sub_dsp23\000"
37	/ 66 / "sub_64\000"
38	/ 73 / "sub_dsp16_19\000"
39	/ 86 / "sub_hi\000"
40	/ 93 / "sub_lo\000"
41	};
42	#ifdef __GNUC__
43	#pragma GCC diagnostic pop
44	#endif
45
46
47	static constexpr uint32_t MipsSubRegIndexNameOffsets[] = {
48	`49`,
49	`66`,
50	`73`,
51	`0`,
52	`10`,
53	`20`,
54	`56`,
55	`86`,
56	`93`,
57	`37`,
58	`30`,
59	};
60
61	static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
62	{ .Offset: `65535`, .Size: `65535` },
63	{ .Offset: `0`, .Size: `32` }, // sub_32
64	{ .Offset: `0`, .Size: `64` }, // sub_64
65	{ .Offset: `16`, .Size: `4` }, // sub_dsp16_19
66	{ .Offset: `20`, .Size: `1` }, // sub_dsp20
67	{ .Offset: `21`, .Size: `1` }, // sub_dsp21
68	{ .Offset: `22`, .Size: `1` }, // sub_dsp22
69	{ .Offset: `23`, .Size: `1` }, // sub_dsp23
70	{ .Offset: `32`, .Size: `32` }, // sub_hi
71	{ .Offset: `0`, .Size: `32` }, // sub_lo
72	{ .Offset: `32`, .Size: `32` }, // sub_hi_then_sub_32
73	{ .Offset: `0`, .Size: `64` }, // sub_32_sub_hi_then_sub_32
74	{ .Offset: `65535`, .Size: `65535` },
75	{ .Offset: `0`, .Size: `32` }, // sub_32
76	{ .Offset: `0`, .Size: `64` }, // sub_64
77	{ .Offset: `16`, .Size: `4` }, // sub_dsp16_19
78	{ .Offset: `20`, .Size: `1` }, // sub_dsp20
79	{ .Offset: `21`, .Size: `1` }, // sub_dsp21
80	{ .Offset: `22`, .Size: `1` }, // sub_dsp22
81	{ .Offset: `23`, .Size: `1` }, // sub_dsp23
82	{ .Offset: `32`, .Size: `32` }, // sub_hi
83	{ .Offset: `0`, .Size: `32` }, // sub_lo
84	{ .Offset: `32`, .Size: `32` }, // sub_hi_then_sub_32
85	{ .Offset: `0`, .Size: `64` }, // sub_32_sub_hi_then_sub_32
86	};
87
88
89	static const LaneBitmask SubRegIndexLaneMaskTable[] = {
90	LaneBitmask::getAll(),
91	LaneBitmask (`0x0000000000000001`), // sub_32
92	LaneBitmask (`0x0000000000000041`), // sub_64
93	LaneBitmask (`0x0000000000000002`), // sub_dsp16_19
94	LaneBitmask (`0x0000000000000004`), // sub_dsp20
95	LaneBitmask (`0x0000000000000008`), // sub_dsp21
96	LaneBitmask (`0x0000000000000010`), // sub_dsp22
97	LaneBitmask (`0x0000000000000020`), // sub_dsp23
98	LaneBitmask (`0x0000000000000040`), // sub_hi
99	LaneBitmask (`0x0000000000000001`), // sub_lo
100	LaneBitmask (`0x0000000000000040`), // sub_hi_then_sub_32
101	LaneBitmask (`0x0000000000000041`), // sub_32_sub_hi_then_sub_32
102	};
103
104
105
106	static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
107	// Mode = 0 (DefaultMode)
108	{ .RegSize: `16`, .SpillSize: `16`, .SpillAlignment: `128`, /VTLists+/.VTListOffset: `6` }, // MSA128F16
109	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // CCR
110	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // COP0
111	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // COP2
112	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // COP3
113	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `0` }, // DSPR
114	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `8` }, // FGR32
115	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // FGR32CC
116	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPR32
117	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // HWRegs
118	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // MSACtrl
119	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPR32NONZERO
120	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // CPU16RegsPlusSP
121	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // CPU16Regs
122	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // FCC
123	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPRMM16
124	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPRMM16MoveP
125	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPRMM16Zero
126	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // CPU16Regs_and_GPRMM16Zero
127	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPR32NONZERO_and_GPRMM16MoveP
128	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPRMM16MovePPairSecond
129	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // CPU16Regs_and_GPRMM16MoveP
130	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPRMM16MoveP_and_GPRMM16Zero
131	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // HI32DSP
132	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // LO32DSP
133	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // CPU16Regs_and_GPRMM16MovePPairSecond
134	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPRMM16MovePPairFirst
135	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
136	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
137	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // CPURAReg
138	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // CPUSPReg
139	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `16` }, // DSPCC
140	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GP32
141	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPR32ZERO
142	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // HI32
143	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // LO32
144	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // SP32
145	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `10` }, // FGR64CC
146	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `12` }, // FGR64
147	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64
148	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPR32NONZERO
149	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `12` }, // AFGR64
150	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPU16RegsPlusSP
151	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPU16Regs
152	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MoveP
153	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16Zero
154	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
155	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
156	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
157	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `28` }, // ACC64DSP
158	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
159	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
160	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
161	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
162	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
163	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // OCTEON_MPL
164	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // OCTEON_P
165	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
166	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `28` }, // ACC64
167	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GP64
168	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPURAReg
169	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPR32ZERO
170	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // HI64
171	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // LO64
172	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // SP64
173	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /VTLists+/.VTListOffset: `14` }, // MSA128B
174	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /VTLists+/.VTListOffset: `25` }, // MSA128D
175	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /VTLists+/.VTListOffset: `19` }, // MSA128H
176	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /VTLists+/.VTListOffset: `22` }, // MSA128W
177	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /VTLists+/.VTListOffset: `22` }, // MSA128WEvens
178	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /VTLists+/.VTListOffset: `28` }, // ACC128
179	// Mode = 1 (MIPS64)
180	{ .RegSize: `16`, .SpillSize: `16`, .SpillAlignment: `128`, /VTLists+/.VTListOffset: `6` }, // MSA128F16
181	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // CCR
182	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // COP0
183	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // COP2
184	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // COP3
185	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `0` }, // DSPR
186	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `8` }, // FGR32
187	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // FGR32CC
188	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPR32
189	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // HWRegs
190	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // MSACtrl
191	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPR32NONZERO
192	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // CPU16RegsPlusSP
193	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // CPU16Regs
194	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // FCC
195	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPRMM16
196	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPRMM16MoveP
197	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPRMM16Zero
198	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // CPU16Regs_and_GPRMM16Zero
199	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPR32NONZERO_and_GPRMM16MoveP
200	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPRMM16MovePPairSecond
201	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // CPU16Regs_and_GPRMM16MoveP
202	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPRMM16MoveP_and_GPRMM16Zero
203	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // HI32DSP
204	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // LO32DSP
205	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // CPU16Regs_and_GPRMM16MovePPairSecond
206	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPRMM16MovePPairFirst
207	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
208	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
209	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // CPURAReg
210	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // CPUSPReg
211	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `16` }, // DSPCC
212	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GP32
213	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // GPR32ZERO
214	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // HI32
215	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // LO32
216	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `32`, /VTLists+/.VTListOffset: `2` }, // SP32
217	{ .RegSize: `32`, .SpillSize: `32`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `10` }, // FGR64CC
218	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `12` }, // FGR64
219	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64
220	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPR32NONZERO
221	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `12` }, // AFGR64
222	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPU16RegsPlusSP
223	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPU16Regs
224	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MoveP
225	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16Zero
226	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
227	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
228	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
229	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `28` }, // ACC64DSP
230	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
231	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
232	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
233	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
234	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
235	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // OCTEON_MPL
236	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // OCTEON_P
237	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
238	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `28` }, // ACC64
239	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GP64
240	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_CPURAReg
241	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // GPR64_with_sub_32_in_GPR32ZERO
242	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // HI64
243	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // LO64
244	{ .RegSize: `64`, .SpillSize: `64`, .SpillAlignment: `64`, /VTLists+/.VTListOffset: `4` }, // SP64
245	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /VTLists+/.VTListOffset: `14` }, // MSA128B
246	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /VTLists+/.VTListOffset: `25` }, // MSA128D
247	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /VTLists+/.VTListOffset: `19` }, // MSA128H
248	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /VTLists+/.VTListOffset: `22` }, // MSA128W
249	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /VTLists+/.VTListOffset: `22` }, // MSA128WEvens
250	{ .RegSize: `128`, .SpillSize: `128`, .SpillAlignment: `128`, /VTLists+/.VTListOffset: `28` }, // ACC128
251	};
252	static const uint32_t MSA128F16SubClassMask[] = {
253	`0x00000001`, `0x00000000`, `0x0000003e`,
254	};
255
256	static const uint32_t CCRSubClassMask[] = {
257	`0x00000002`, `0x00000000`, `0x00000000`,
258	};
259
260	static const uint32_t COP0SubClassMask[] = {
261	`0x00000004`, `0x00000000`, `0x00000000`,
262	};
263
264	static const uint32_t COP2SubClassMask[] = {
265	`0x00000008`, `0x00000000`, `0x00000000`,
266	};
267
268	static const uint32_t COP3SubClassMask[] = {
269	`0x00000010`, `0x00000000`, `0x00000000`,
270	};
271
272	static const uint32_t DSPRSubClassMask[] = {
273	`0x7e7fb920`, `0x00000013`, `0x00000000`,
274	`0x00000000`, `0x3a7dfd80`, `0x00000001`, // sub_32
275	};
276
277	static const uint32_t FGR32SubClassMask[] = {
278	`0x000000c0`, `0x00000000`, `0x00000000`,
279	`0x00000000`, `0x00000200`, `0x00000000`, // sub_hi
280	`0x00000001`, `0x00000260`, `0x0000003e`, // sub_lo
281	};
282
283	static const uint32_t FGR32CCSubClassMask[] = {
284	`0x000000c0`, `0x00000000`, `0x00000000`,
285	`0x00000000`, `0x00000200`, `0x00000000`, // sub_hi
286	`0x00000001`, `0x00000260`, `0x0000003e`, // sub_lo
287	};
288
289	static const uint32_t GPR32SubClassMask[] = {
290	`0x7e7fb900`, `0x00000013`, `0x00000000`,
291	`0x00000000`, `0x3a7dfd80`, `0x00000001`, // sub_32
292	};
293
294	static const uint32_t HWRegsSubClassMask[] = {
295	`0x00000200`, `0x00000000`, `0x00000000`,
296	};
297
298	static const uint32_t MSACtrlSubClassMask[] = {
299	`0x00000400`, `0x00000000`, `0x00000000`,
300	};
301
302	static const uint32_t GPR32NONZEROSubClassMask[] = {
303	`0x7e3cb800`, `0x00000011`, `0x00000000`,
304	`0x00000000`, `0x1a75cd00`, `0x00000001`, // sub_32
305	};
306
307	static const uint32_t CPU16RegsPlusSPSubClassMask[] = {
308	`0x5e24b000`, `0x00000010`, `0x00000000`,
309	`0x00000000`, `0x02744c00`, `0x00000001`, // sub_32
310	};
311
312	static const uint32_t CPU16RegsSubClassMask[] = {
313	`0x1e24a000`, `0x00000000`, `0x00000000`,
314	`0x00000000`, `0x02744800`, `0x00000000`, // sub_32
315	};
316
317	static const uint32_t FCCSubClassMask[] = {
318	`0x00004000`, `0x00000000`, `0x00000000`,
319	};
320
321	static const uint32_t GPRMM16SubClassMask[] = {
322	`0x1e248000`, `0x00000000`, `0x00000000`,
323	`0x00000000`, `0x02744800`, `0x00000000`, // sub_32
324	};
325
326	static const uint32_t GPRMM16MovePSubClassMask[] = {
327	`0x08690000`, `0x00000002`, `0x00000000`,
328	`0x00000000`, `0x204c9000`, `0x00000000`, // sub_32
329	};
330
331	static const uint32_t GPRMM16ZeroSubClassMask[] = {
332	`0x1e460000`, `0x00000002`, `0x00000000`,
333	`0x00000000`, `0x22786000`, `0x00000000`, // sub_32
334	};
335
336	static const uint32_t CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
337	`0x1e040000`, `0x00000000`, `0x00000000`,
338	`0x00000000`, `0x02704000`, `0x00000000`, // sub_32
339	};
340
341	static const uint32_t GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
342	`0x08280000`, `0x00000000`, `0x00000000`,
343	`0x00000000`, `0x00448000`, `0x00000000`, // sub_32
344	};
345
346	static const uint32_t GPRMM16MovePPairSecondSubClassMask[] = {
347	`0x12100000`, `0x00000000`, `0x00000000`,
348	`0x00000000`, `0x02110000`, `0x00000000`, // sub_32
349	};
350
351	static const uint32_t CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
352	`0x08200000`, `0x00000000`, `0x00000000`,
353	`0x00000000`, `0x00440000`, `0x00000000`, // sub_32
354	};
355
356	static const uint32_t GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
357	`0x08400000`, `0x00000002`, `0x00000000`,
358	`0x00000000`, `0x20480000`, `0x00000000`, // sub_32
359	};
360
361	static const uint32_t HI32DSPSubClassMask[] = {
362	`0x00800000`, `0x00000004`, `0x00000000`,
363	`0x00000000`, `0x40000000`, `0x00000000`, // sub_32
364	`0x00000000`, `0x04020000`, `0x00000000`, // sub_hi
365	`0x00000000`, `0x00000000`, `0x00000040`, // sub_hi_then_sub_32
366	};
367
368	static const uint32_t LO32DSPSubClassMask[] = {
369	`0x01000000`, `0x00000008`, `0x00000000`,
370	`0x00000000`, `0x80000000`, `0x00000040`, // sub_32
371	`0x00000000`, `0x04020000`, `0x00000000`, // sub_lo
372	};
373
374	static const uint32_t CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {
375	`0x12000000`, `0x00000000`, `0x00000000`,
376	`0x00000000`, `0x02100000`, `0x00000000`, // sub_32
377	};
378
379	static const uint32_t GPRMM16MovePPairFirstSubClassMask[] = {
380	`0x14000000`, `0x00000000`, `0x00000000`,
381	`0x00000000`, `0x02200000`, `0x00000000`, // sub_32
382	};
383
384	static const uint32_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
385	`0x08000000`, `0x00000000`, `0x00000000`,
386	`0x00000000`, `0x00400000`, `0x00000000`, // sub_32
387	};
388
389	static const uint32_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {
390	`0x10000000`, `0x00000000`, `0x00000000`,
391	`0x00000000`, `0x02000000`, `0x00000000`, // sub_32
392	};
393
394	static const uint32_t CPURARegSubClassMask[] = {
395	`0x20000000`, `0x00000000`, `0x00000000`,
396	`0x00000000`, `0x10000000`, `0x00000000`, // sub_32
397	};
398
399	static const uint32_t CPUSPRegSubClassMask[] = {
400	`0x40000000`, `0x00000010`, `0x00000000`,
401	`0x00000000`, `0x00000000`, `0x00000001`, // sub_32
402	};
403
404	static const uint32_t DSPCCSubClassMask[] = {
405	`0x80000000`, `0x00000000`, `0x00000000`,
406	};
407
408	static const uint32_t GP32SubClassMask[] = {
409	`0x00000000`, `0x00000001`, `0x00000000`,
410	`0x00000000`, `0x08000000`, `0x00000000`, // sub_32
411	};
412
413	static const uint32_t GPR32ZEROSubClassMask[] = {
414	`0x00000000`, `0x00000002`, `0x00000000`,
415	`0x00000000`, `0x20000000`, `0x00000000`, // sub_32
416	};
417
418	static const uint32_t HI32SubClassMask[] = {
419	`0x00000000`, `0x00000004`, `0x00000000`,
420	`0x00000000`, `0x40000000`, `0x00000000`, // sub_32
421	`0x00000000`, `0x04000000`, `0x00000000`, // sub_hi
422	`0x00000000`, `0x00000000`, `0x00000040`, // sub_hi_then_sub_32
423	};
424
425	static const uint32_t LO32SubClassMask[] = {
426	`0x00000000`, `0x00000008`, `0x00000000`,
427	`0x00000000`, `0x80000000`, `0x00000040`, // sub_32
428	`0x00000000`, `0x04000000`, `0x00000000`, // sub_lo
429	};
430
431	static const uint32_t SP32SubClassMask[] = {
432	`0x00000000`, `0x00000010`, `0x00000000`,
433	`0x00000000`, `0x00000000`, `0x00000001`, // sub_32
434	};
435
436	static const uint32_t FGR64CCSubClassMask[] = {
437	`0x00000000`, `0x00000060`, `0x00000000`,
438	`0x00000001`, `0x00000000`, `0x0000003e`, // sub_64
439	};
440
441	static const uint32_t FGR64SubClassMask[] = {
442	`0x00000000`, `0x00000040`, `0x00000000`,
443	`0x00000001`, `0x00000000`, `0x0000003e`, // sub_64
444	};
445
446	static const uint32_t GPR64SubClassMask[] = {
447	`0x00000000`, `0x3a7dfd80`, `0x00000001`,
448	};
449
450	static const uint32_t GPR64_with_sub_32_in_GPR32NONZEROSubClassMask[] = {
451	`0x00000000`, `0x1a75cd00`, `0x00000001`,
452	};
453
454	static const uint32_t AFGR64SubClassMask[] = {
455	`0x00000000`, `0x00000200`, `0x00000000`,
456	};
457
458	static const uint32_t GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask[] = {
459	`0x00000000`, `0x02744c00`, `0x00000001`,
460	};
461
462	static const uint32_t GPR64_with_sub_32_in_CPU16RegsSubClassMask[] = {
463	`0x00000000`, `0x02744800`, `0x00000000`,
464	};
465
466	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePSubClassMask[] = {
467	`0x00000000`, `0x204c9000`, `0x00000000`,
468	};
469
470	static const uint32_t GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask[] = {
471	`0x00000000`, `0x22786000`, `0x00000000`,
472	};
473
474	static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
475	`0x00000000`, `0x02704000`, `0x00000000`,
476	};
477
478	static const uint32_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
479	`0x00000000`, `0x00448000`, `0x00000000`,
480	};
481
482	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask[] = {
483	`0x00000000`, `0x02110000`, `0x00000000`,
484	};
485
486	static const uint32_t ACC64DSPSubClassMask[] = {
487	`0x00000000`, `0x04020000`, `0x00000000`,
488	`0x00000000`, `0x00000000`, `0x00000040`, // sub_32_sub_hi_then_sub_32
489	};
490
491	static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
492	`0x00000000`, `0x00440000`, `0x00000000`,
493	};
494
495	static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
496	`0x00000000`, `0x20480000`, `0x00000000`,
497	};
498
499	static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {
500	`0x00000000`, `0x02100000`, `0x00000000`,
501	};
502
503	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask[] = {
504	`0x00000000`, `0x02200000`, `0x00000000`,
505	};
506
507	static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
508	`0x00000000`, `0x00400000`, `0x00000000`,
509	};
510
511	static const uint32_t OCTEON_MPLSubClassMask[] = {
512	`0x00000000`, `0x00800000`, `0x00000000`,
513	};
514
515	static const uint32_t OCTEON_PSubClassMask[] = {
516	`0x00000000`, `0x01000000`, `0x00000000`,
517	};
518
519	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {
520	`0x00000000`, `0x02000000`, `0x00000000`,
521	};
522
523	static const uint32_t ACC64SubClassMask[] = {
524	`0x00000000`, `0x04000000`, `0x00000000`,
525	`0x00000000`, `0x00000000`, `0x00000040`, // sub_32_sub_hi_then_sub_32
526	};
527
528	static const uint32_t GP64SubClassMask[] = {
529	`0x00000000`, `0x08000000`, `0x00000000`,
530	};
531
532	static const uint32_t GPR64_with_sub_32_in_CPURARegSubClassMask[] = {
533	`0x00000000`, `0x10000000`, `0x00000000`,
534	};
535
536	static const uint32_t GPR64_with_sub_32_in_GPR32ZEROSubClassMask[] = {
537	`0x00000000`, `0x20000000`, `0x00000000`,
538	};
539
540	static const uint32_t HI64SubClassMask[] = {
541	`0x00000000`, `0x40000000`, `0x00000000`,
542	`0x00000000`, `0x00000000`, `0x00000040`, // sub_hi
543	};
544
545	static const uint32_t LO64SubClassMask[] = {
546	`0x00000000`, `0x80000000`, `0x00000000`,
547	`0x00000000`, `0x00000000`, `0x00000040`, // sub_lo
548	};
549
550	static const uint32_t SP64SubClassMask[] = {
551	`0x00000000`, `0x00000000`, `0x00000001`,
552	};
553
554	static const uint32_t MSA128BSubClassMask[] = {
555	`0x00000000`, `0x00000000`, `0x0000003e`,
556	};
557
558	static const uint32_t MSA128DSubClassMask[] = {
559	`0x00000000`, `0x00000000`, `0x0000003e`,
560	};
561
562	static const uint32_t MSA128HSubClassMask[] = {
563	`0x00000000`, `0x00000000`, `0x0000003e`,
564	};
565
566	static const uint32_t MSA128WSubClassMask[] = {
567	`0x00000000`, `0x00000000`, `0x0000003e`,
568	};
569
570	static const uint32_t MSA128WEvensSubClassMask[] = {
571	`0x00000000`, `0x00000000`, `0x00000020`,
572	};
573
574	static const uint32_t ACC128SubClassMask[] = {
575	`0x00000000`, `0x00000000`, `0x00000040`,
576	};
577
578	static const uint16_t SuperRegIdxSeqs[] = {
579	/ 0 / `1`, `0`,
580	/ 2 / `2`, `0`,
581	/ 4 / `8`, `0`,
582	/ 6 / `1`, `9`, `0`,
583	/ 9 / `8`, `9`, `0`,
584	/ 12 / `1`, `8`, `10`, `0`,
585	/ 16 / `11`, `0`,
586	};
587
588	static unsigned const FGR32Superclasses[] = {
589	Mips::FGR32CCRegClassID,
590	};
591
592	static unsigned const FGR32CCSuperclasses[] = {
593	Mips::FGR32RegClassID,
594	};
595
596	static unsigned const GPR32Superclasses[] = {
597	Mips::DSPRRegClassID,
598	};
599
600	static unsigned const GPR32NONZEROSuperclasses[] = {
601	Mips::DSPRRegClassID,
602	Mips::GPR32RegClassID,
603	};
604
605	static unsigned const CPU16RegsPlusSPSuperclasses[] = {
606	Mips::DSPRRegClassID,
607	Mips::GPR32RegClassID,
608	Mips::GPR32NONZERORegClassID,
609	};
610
611	static unsigned const CPU16RegsSuperclasses[] = {
612	Mips::DSPRRegClassID,
613	Mips::GPR32RegClassID,
614	Mips::GPR32NONZERORegClassID,
615	Mips::CPU16RegsPlusSPRegClassID,
616	};
617
618	static unsigned const GPRMM16Superclasses[] = {
619	Mips::DSPRRegClassID,
620	Mips::GPR32RegClassID,
621	Mips::GPR32NONZERORegClassID,
622	Mips::CPU16RegsPlusSPRegClassID,
623	Mips::CPU16RegsRegClassID,
624	};
625
626	static unsigned const GPRMM16MovePSuperclasses[] = {
627	Mips::DSPRRegClassID,
628	Mips::GPR32RegClassID,
629	};
630
631	static unsigned const GPRMM16ZeroSuperclasses[] = {
632	Mips::DSPRRegClassID,
633	Mips::GPR32RegClassID,
634	};
635
636	static unsigned const CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
637	Mips::DSPRRegClassID,
638	Mips::GPR32RegClassID,
639	Mips::GPR32NONZERORegClassID,
640	Mips::CPU16RegsPlusSPRegClassID,
641	Mips::CPU16RegsRegClassID,
642	Mips::GPRMM16RegClassID,
643	Mips::GPRMM16ZeroRegClassID,
644	};
645
646	static unsigned const GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
647	Mips::DSPRRegClassID,
648	Mips::GPR32RegClassID,
649	Mips::GPR32NONZERORegClassID,
650	Mips::GPRMM16MovePRegClassID,
651	};
652
653	static unsigned const GPRMM16MovePPairSecondSuperclasses[] = {
654	Mips::DSPRRegClassID,
655	Mips::GPR32RegClassID,
656	Mips::GPR32NONZERORegClassID,
657	};
658
659	static unsigned const CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
660	Mips::DSPRRegClassID,
661	Mips::GPR32RegClassID,
662	Mips::GPR32NONZERORegClassID,
663	Mips::CPU16RegsPlusSPRegClassID,
664	Mips::CPU16RegsRegClassID,
665	Mips::GPRMM16RegClassID,
666	Mips::GPRMM16MovePRegClassID,
667	Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID,
668	};
669
670	static unsigned const GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
671	Mips::DSPRRegClassID,
672	Mips::GPR32RegClassID,
673	Mips::GPRMM16MovePRegClassID,
674	Mips::GPRMM16ZeroRegClassID,
675	};
676
677	static unsigned const CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
678	Mips::DSPRRegClassID,
679	Mips::GPR32RegClassID,
680	Mips::GPR32NONZERORegClassID,
681	Mips::CPU16RegsPlusSPRegClassID,
682	Mips::CPU16RegsRegClassID,
683	Mips::GPRMM16RegClassID,
684	Mips::GPRMM16ZeroRegClassID,
685	Mips::CPU16Regs_and_GPRMM16ZeroRegClassID,
686	Mips::GPRMM16MovePPairSecondRegClassID,
687	};
688
689	static unsigned const GPRMM16MovePPairFirstSuperclasses[] = {
690	Mips::DSPRRegClassID,
691	Mips::GPR32RegClassID,
692	Mips::GPR32NONZERORegClassID,
693	Mips::CPU16RegsPlusSPRegClassID,
694	Mips::CPU16RegsRegClassID,
695	Mips::GPRMM16RegClassID,
696	Mips::GPRMM16ZeroRegClassID,
697	Mips::CPU16Regs_and_GPRMM16ZeroRegClassID,
698	};
699
700	static unsigned const GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
701	Mips::DSPRRegClassID,
702	Mips::GPR32RegClassID,
703	Mips::GPR32NONZERORegClassID,
704	Mips::CPU16RegsPlusSPRegClassID,
705	Mips::CPU16RegsRegClassID,
706	Mips::GPRMM16RegClassID,
707	Mips::GPRMM16MovePRegClassID,
708	Mips::GPRMM16ZeroRegClassID,
709	Mips::CPU16Regs_and_GPRMM16ZeroRegClassID,
710	Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID,
711	Mips::CPU16Regs_and_GPRMM16MovePRegClassID,
712	Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID,
713	};
714
715	static unsigned const GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
716	Mips::DSPRRegClassID,
717	Mips::GPR32RegClassID,
718	Mips::GPR32NONZERORegClassID,
719	Mips::CPU16RegsPlusSPRegClassID,
720	Mips::CPU16RegsRegClassID,
721	Mips::GPRMM16RegClassID,
722	Mips::GPRMM16ZeroRegClassID,
723	Mips::CPU16Regs_and_GPRMM16ZeroRegClassID,
724	Mips::GPRMM16MovePPairSecondRegClassID,
725	Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID,
726	Mips::GPRMM16MovePPairFirstRegClassID,
727	};
728
729	static unsigned const CPURARegSuperclasses[] = {
730	Mips::DSPRRegClassID,
731	Mips::GPR32RegClassID,
732	Mips::GPR32NONZERORegClassID,
733	};
734
735	static unsigned const CPUSPRegSuperclasses[] = {
736	Mips::DSPRRegClassID,
737	Mips::GPR32RegClassID,
738	Mips::GPR32NONZERORegClassID,
739	Mips::CPU16RegsPlusSPRegClassID,
740	};
741
742	static unsigned const GP32Superclasses[] = {
743	Mips::DSPRRegClassID,
744	Mips::GPR32RegClassID,
745	Mips::GPR32NONZERORegClassID,
746	};
747
748	static unsigned const GPR32ZEROSuperclasses[] = {
749	Mips::DSPRRegClassID,
750	Mips::GPR32RegClassID,
751	Mips::GPRMM16MovePRegClassID,
752	Mips::GPRMM16ZeroRegClassID,
753	Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID,
754	};
755
756	static unsigned const HI32Superclasses[] = {
757	Mips::HI32DSPRegClassID,
758	};
759
760	static unsigned const LO32Superclasses[] = {
761	Mips::LO32DSPRegClassID,
762	};
763
764	static unsigned const SP32Superclasses[] = {
765	Mips::DSPRRegClassID,
766	Mips::GPR32RegClassID,
767	Mips::GPR32NONZERORegClassID,
768	Mips::CPU16RegsPlusSPRegClassID,
769	Mips::CPUSPRegRegClassID,
770	};
771
772	static unsigned const FGR64Superclasses[] = {
773	Mips::FGR64CCRegClassID,
774	};
775
776	static unsigned const GPR64_with_sub_32_in_GPR32NONZEROSuperclasses[] = {
777	Mips::GPR64RegClassID,
778	};
779
780	static unsigned const GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses[] = {
781	Mips::GPR64RegClassID,
782	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
783	};
784
785	static unsigned const GPR64_with_sub_32_in_CPU16RegsSuperclasses[] = {
786	Mips::GPR64RegClassID,
787	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
788	Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
789	};
790
791	static unsigned const GPR64_with_sub_32_in_GPRMM16MovePSuperclasses[] = {
792	Mips::GPR64RegClassID,
793	};
794
795	static unsigned const GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses[] = {
796	Mips::GPR64RegClassID,
797	};
798
799	static unsigned const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
800	Mips::GPR64RegClassID,
801	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
802	Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
803	Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
804	Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
805	};
806
807	static unsigned const GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
808	Mips::GPR64RegClassID,
809	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
810	Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
811	};
812
813	static unsigned const GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses[] = {
814	Mips::GPR64RegClassID,
815	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
816	};
817
818	static unsigned const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
819	Mips::GPR64RegClassID,
820	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
821	Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
822	Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
823	Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
824	Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID,
825	};
826
827	static unsigned const GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
828	Mips::GPR64RegClassID,
829	Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
830	Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
831	};
832
833	static unsigned const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
834	Mips::GPR64RegClassID,
835	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
836	Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
837	Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
838	Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
839	Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID,
840	Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID,
841	};
842
843	static unsigned const GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses[] = {
844	Mips::GPR64RegClassID,
845	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
846	Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
847	Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
848	Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
849	Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID,
850	};
851
852	static unsigned const GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
853	Mips::GPR64RegClassID,
854	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
855	Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
856	Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
857	Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
858	Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
859	Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID,
860	Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID,
861	Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID,
862	Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID,
863	};
864
865	static unsigned const GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
866	Mips::GPR64RegClassID,
867	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
868	Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
869	Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
870	Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
871	Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID,
872	Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID,
873	Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID,
874	Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID,
875	};
876
877	static unsigned const ACC64Superclasses[] = {
878	Mips::ACC64DSPRegClassID,
879	};
880
881	static unsigned const GP64Superclasses[] = {
882	Mips::GPR64RegClassID,
883	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
884	};
885
886	static unsigned const GPR64_with_sub_32_in_CPURARegSuperclasses[] = {
887	Mips::GPR64RegClassID,
888	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
889	};
890
891	static unsigned const GPR64_with_sub_32_in_GPR32ZEROSuperclasses[] = {
892	Mips::GPR64RegClassID,
893	Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
894	Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
895	Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID,
896	};
897
898	static unsigned const SP64Superclasses[] = {
899	Mips::GPR64RegClassID,
900	Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
901	Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
902	};
903
904	static unsigned const MSA128BSuperclasses[] = {
905	Mips::MSA128F16RegClassID,
906	Mips::MSA128DRegClassID,
907	Mips::MSA128HRegClassID,
908	Mips::MSA128WRegClassID,
909	};
910
911	static unsigned const MSA128DSuperclasses[] = {
912	Mips::MSA128F16RegClassID,
913	Mips::MSA128BRegClassID,
914	Mips::MSA128HRegClassID,
915	Mips::MSA128WRegClassID,
916	};
917
918	static unsigned const MSA128HSuperclasses[] = {
919	Mips::MSA128F16RegClassID,
920	Mips::MSA128BRegClassID,
921	Mips::MSA128DRegClassID,
922	Mips::MSA128WRegClassID,
923	};
924
925	static unsigned const MSA128WSuperclasses[] = {
926	Mips::MSA128F16RegClassID,
927	Mips::MSA128BRegClassID,
928	Mips::MSA128DRegClassID,
929	Mips::MSA128HRegClassID,
930	};
931
932	static unsigned const MSA128WEvensSuperclasses[] = {
933	Mips::MSA128F16RegClassID,
934	Mips::MSA128BRegClassID,
935	Mips::MSA128DRegClassID,
936	Mips::MSA128HRegClassID,
937	Mips::MSA128WRegClassID,
938	};
939
940
941	static inline unsigned FGR32AltOrderSelect(const MachineFunction &MF, bool Rev) {
942	const auto & S = MF.getSubtarget<MipsSubtarget>();
943	return S.isABI_O32() && !S.useOddSPReg();
944	}
945
946	static ArrayRef<MCPhysReg> FGR32GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
947	static const MCPhysReg AltOrder1[] = { Mips::F0, Mips::F2, Mips::F4, Mips::F6, Mips::F8, Mips::F10, Mips::F12, Mips::F14, Mips::F16, Mips::F18, Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30 };
948	const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR32RegClassID];
949	const ArrayRef<MCPhysReg> Order[] = {
950	ArrayRef(MCR.begin(), MCR.getNumRegs()),
951	ArrayRef(AltOrder1)
952	};
953	const unsigned Select = FGR32AltOrderSelect(MF, Rev);
954	assert(Select < `2`);
955	return Order[Select];
956	}
957
958	static inline unsigned FGR64AltOrderSelect(const MachineFunction &MF, bool Rev) {
959	const auto & S = MF.getSubtarget<MipsSubtarget>();
960	return S.isABI_O32() && !S.useOddSPReg();
961	}
962
963	static ArrayRef<MCPhysReg> FGR64GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
964	static const MCPhysReg AltOrder1[] = { Mips::D0_64, Mips::D2_64, Mips::D4_64, Mips::D6_64, Mips::D8_64, Mips::D10_64, Mips::D12_64, Mips::D14_64, Mips::D16_64, Mips::D18_64, Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64 };
965	const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR64RegClassID];
966	const ArrayRef<MCPhysReg> Order[] = {
967	ArrayRef(MCR.begin(), MCR.getNumRegs()),
968	ArrayRef(AltOrder1)
969	};
970	const unsigned Select = FGR64AltOrderSelect(MF, Rev);
971	assert(Select < `2`);
972	return Order[Select];
973	}
974	namespace Mips {
975
976	// Register class instances
977	extern const TargetRegisterClass MSA128F16RegClass = {
978	.MC: &MipsMCRegisterClasses[MSA128F16RegClassID],
979	.SubClassMask: MSA128F16SubClassMask,
980	.SuperRegIndices: SuperRegIdxSeqs + `1`,
981	.LaneMask: LaneBitmask (`0x0000000000000041`),
982	.AllocationPriority: `0`,
983	.GlobalPriority: false,
984	.TSFlags: `0x00`, / TSFlags /
985	.HasDisjunctSubRegs: true, / HasDisjunctSubRegs /
986	.CoveredBySubRegs: false, / CoveredBySubRegs /
987	.SuperClasses: nullptr, .SuperClassesSize: `0`,
988	.OrderFunc: nullptr
989	};
990
991	extern const TargetRegisterClass CCRRegClass = {
992	.MC: &MipsMCRegisterClasses[CCRRegClassID],
993	.SubClassMask: CCRSubClassMask,
994	.SuperRegIndices: SuperRegIdxSeqs + `1`,
995	.LaneMask: LaneBitmask (`0x0000000000000001`),
996	.AllocationPriority: `0`,
997	.GlobalPriority: false,
998	.TSFlags: `0x00`, / TSFlags /
999	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1000	.CoveredBySubRegs: false, / CoveredBySubRegs /
1001	.SuperClasses: nullptr, .SuperClassesSize: `0`,
1002	.OrderFunc: nullptr
1003	};
1004
1005	extern const TargetRegisterClass COP0RegClass = {
1006	.MC: &MipsMCRegisterClasses[COP0RegClassID],
1007	.SubClassMask: COP0SubClassMask,
1008	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1009	.LaneMask: LaneBitmask (`0x0000000000000001`),
1010	.AllocationPriority: `0`,
1011	.GlobalPriority: false,
1012	.TSFlags: `0x00`, / TSFlags /
1013	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1014	.CoveredBySubRegs: false, / CoveredBySubRegs /
1015	.SuperClasses: nullptr, .SuperClassesSize: `0`,
1016	.OrderFunc: nullptr
1017	};
1018
1019	extern const TargetRegisterClass COP2RegClass = {
1020	.MC: &MipsMCRegisterClasses[COP2RegClassID],
1021	.SubClassMask: COP2SubClassMask,
1022	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1023	.LaneMask: LaneBitmask (`0x0000000000000001`),
1024	.AllocationPriority: `0`,
1025	.GlobalPriority: false,
1026	.TSFlags: `0x00`, / TSFlags /
1027	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1028	.CoveredBySubRegs: false, / CoveredBySubRegs /
1029	.SuperClasses: nullptr, .SuperClassesSize: `0`,
1030	.OrderFunc: nullptr
1031	};
1032
1033	extern const TargetRegisterClass COP3RegClass = {
1034	.MC: &MipsMCRegisterClasses[COP3RegClassID],
1035	.SubClassMask: COP3SubClassMask,
1036	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1037	.LaneMask: LaneBitmask (`0x0000000000000001`),
1038	.AllocationPriority: `0`,
1039	.GlobalPriority: false,
1040	.TSFlags: `0x00`, / TSFlags /
1041	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1042	.CoveredBySubRegs: false, / CoveredBySubRegs /
1043	.SuperClasses: nullptr, .SuperClassesSize: `0`,
1044	.OrderFunc: nullptr
1045	};
1046
1047	extern const TargetRegisterClass DSPRRegClass = {
1048	.MC: &MipsMCRegisterClasses[DSPRRegClassID],
1049	.SubClassMask: DSPRSubClassMask,
1050	.SuperRegIndices: SuperRegIdxSeqs + `0`,
1051	.LaneMask: LaneBitmask (`0x0000000000000001`),
1052	.AllocationPriority: `0`,
1053	.GlobalPriority: false,
1054	.TSFlags: `0x00`, / TSFlags /
1055	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1056	.CoveredBySubRegs: false, / CoveredBySubRegs /
1057	.SuperClasses: nullptr, .SuperClassesSize: `0`,
1058	.OrderFunc: nullptr
1059	};
1060
1061	extern const TargetRegisterClass FGR32RegClass = {
1062	.MC: &MipsMCRegisterClasses[FGR32RegClassID],
1063	.SubClassMask: FGR32SubClassMask,
1064	.SuperRegIndices: SuperRegIdxSeqs + `9`,
1065	.LaneMask: LaneBitmask (`0x0000000000000001`),
1066	.AllocationPriority: `0`,
1067	.GlobalPriority: false,
1068	.TSFlags: `0x00`, / TSFlags /
1069	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1070	.CoveredBySubRegs: false, / CoveredBySubRegs /
1071	.SuperClasses: FGR32Superclasses, .SuperClassesSize: `1`,
1072	.OrderFunc: FGR32GetRawAllocationOrder
1073	};
1074
1075	extern const TargetRegisterClass FGR32CCRegClass = {
1076	.MC: &MipsMCRegisterClasses[FGR32CCRegClassID],
1077	.SubClassMask: FGR32CCSubClassMask,
1078	.SuperRegIndices: SuperRegIdxSeqs + `9`,
1079	.LaneMask: LaneBitmask (`0x0000000000000001`),
1080	.AllocationPriority: `0`,
1081	.GlobalPriority: false,
1082	.TSFlags: `0x00`, / TSFlags /
1083	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1084	.CoveredBySubRegs: false, / CoveredBySubRegs /
1085	.SuperClasses: FGR32CCSuperclasses, .SuperClassesSize: `1`,
1086	.OrderFunc: nullptr
1087	};
1088
1089	extern const TargetRegisterClass GPR32RegClass = {
1090	.MC: &MipsMCRegisterClasses[GPR32RegClassID],
1091	.SubClassMask: GPR32SubClassMask,
1092	.SuperRegIndices: SuperRegIdxSeqs + `0`,
1093	.LaneMask: LaneBitmask (`0x0000000000000001`),
1094	.AllocationPriority: `0`,
1095	.GlobalPriority: false,
1096	.TSFlags: `0x00`, / TSFlags /
1097	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1098	.CoveredBySubRegs: false, / CoveredBySubRegs /
1099	.SuperClasses: GPR32Superclasses, .SuperClassesSize: `1`,
1100	.OrderFunc: nullptr
1101	};
1102
1103	extern const TargetRegisterClass HWRegsRegClass = {
1104	.MC: &MipsMCRegisterClasses[HWRegsRegClassID],
1105	.SubClassMask: HWRegsSubClassMask,
1106	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1107	.LaneMask: LaneBitmask (`0x0000000000000001`),
1108	.AllocationPriority: `0`,
1109	.GlobalPriority: false,
1110	.TSFlags: `0x00`, / TSFlags /
1111	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1112	.CoveredBySubRegs: false, / CoveredBySubRegs /
1113	.SuperClasses: nullptr, .SuperClassesSize: `0`,
1114	.OrderFunc: nullptr
1115	};
1116
1117	extern const TargetRegisterClass MSACtrlRegClass = {
1118	.MC: &MipsMCRegisterClasses[MSACtrlRegClassID],
1119	.SubClassMask: MSACtrlSubClassMask,
1120	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1121	.LaneMask: LaneBitmask (`0x0000000000000001`),
1122	.AllocationPriority: `0`,
1123	.GlobalPriority: false,
1124	.TSFlags: `0x00`, / TSFlags /
1125	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1126	.CoveredBySubRegs: false, / CoveredBySubRegs /
1127	.SuperClasses: nullptr, .SuperClassesSize: `0`,
1128	.OrderFunc: nullptr
1129	};
1130
1131	extern const TargetRegisterClass GPR32NONZERORegClass = {
1132	.MC: &MipsMCRegisterClasses[GPR32NONZERORegClassID],
1133	.SubClassMask: GPR32NONZEROSubClassMask,
1134	.SuperRegIndices: SuperRegIdxSeqs + `0`,
1135	.LaneMask: LaneBitmask (`0x0000000000000001`),
1136	.AllocationPriority: `0`,
1137	.GlobalPriority: false,
1138	.TSFlags: `0x00`, / TSFlags /
1139	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1140	.CoveredBySubRegs: false, / CoveredBySubRegs /
1141	.SuperClasses: GPR32NONZEROSuperclasses, .SuperClassesSize: `2`,
1142	.OrderFunc: nullptr
1143	};
1144
1145	extern const TargetRegisterClass CPU16RegsPlusSPRegClass = {
1146	.MC: &MipsMCRegisterClasses[CPU16RegsPlusSPRegClassID],
1147	.SubClassMask: CPU16RegsPlusSPSubClassMask,
1148	.SuperRegIndices: SuperRegIdxSeqs + `0`,
1149	.LaneMask: LaneBitmask (`0x0000000000000001`),
1150	.AllocationPriority: `0`,
1151	.GlobalPriority: false,
1152	.TSFlags: `0x00`, / TSFlags /
1153	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1154	.CoveredBySubRegs: false, / CoveredBySubRegs /
1155	.SuperClasses: CPU16RegsPlusSPSuperclasses, .SuperClassesSize: `3`,
1156	.OrderFunc: nullptr
1157	};
1158
1159	extern const TargetRegisterClass CPU16RegsRegClass = {
1160	.MC: &MipsMCRegisterClasses[CPU16RegsRegClassID],
1161	.SubClassMask: CPU16RegsSubClassMask,
1162	.SuperRegIndices: SuperRegIdxSeqs + `0`,
1163	.LaneMask: LaneBitmask (`0x0000000000000001`),
1164	.AllocationPriority: `0`,
1165	.GlobalPriority: false,
1166	.TSFlags: `0x00`, / TSFlags /
1167	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1168	.CoveredBySubRegs: false, / CoveredBySubRegs /
1169	.SuperClasses: CPU16RegsSuperclasses, .SuperClassesSize: `4`,
1170	.OrderFunc: nullptr
1171	};
1172
1173	extern const TargetRegisterClass FCCRegClass = {
1174	.MC: &MipsMCRegisterClasses[FCCRegClassID],
1175	.SubClassMask: FCCSubClassMask,
1176	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1177	.LaneMask: LaneBitmask (`0x0000000000000001`),
1178	.AllocationPriority: `0`,
1179	.GlobalPriority: false,
1180	.TSFlags: `0x00`, / TSFlags /
1181	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1182	.CoveredBySubRegs: false, / CoveredBySubRegs /
1183	.SuperClasses: nullptr, .SuperClassesSize: `0`,
1184	.OrderFunc: nullptr
1185	};
1186
1187	extern const TargetRegisterClass GPRMM16RegClass = {
1188	.MC: &MipsMCRegisterClasses[GPRMM16RegClassID],
1189	.SubClassMask: GPRMM16SubClassMask,
1190	.SuperRegIndices: SuperRegIdxSeqs + `0`,
1191	.LaneMask: LaneBitmask (`0x0000000000000001`),
1192	.AllocationPriority: `0`,
1193	.GlobalPriority: false,
1194	.TSFlags: `0x00`, / TSFlags /
1195	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1196	.CoveredBySubRegs: false, / CoveredBySubRegs /
1197	.SuperClasses: GPRMM16Superclasses, .SuperClassesSize: `5`,
1198	.OrderFunc: nullptr
1199	};
1200
1201	extern const TargetRegisterClass GPRMM16MovePRegClass = {
1202	.MC: &MipsMCRegisterClasses[GPRMM16MovePRegClassID],
1203	.SubClassMask: GPRMM16MovePSubClassMask,
1204	.SuperRegIndices: SuperRegIdxSeqs + `0`,
1205	.LaneMask: LaneBitmask (`0x0000000000000001`),
1206	.AllocationPriority: `0`,
1207	.GlobalPriority: false,
1208	.TSFlags: `0x00`, / TSFlags /
1209	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1210	.CoveredBySubRegs: false, / CoveredBySubRegs /
1211	.SuperClasses: GPRMM16MovePSuperclasses, .SuperClassesSize: `2`,
1212	.OrderFunc: nullptr
1213	};
1214
1215	extern const TargetRegisterClass GPRMM16ZeroRegClass = {
1216	.MC: &MipsMCRegisterClasses[GPRMM16ZeroRegClassID],
1217	.SubClassMask: GPRMM16ZeroSubClassMask,
1218	.SuperRegIndices: SuperRegIdxSeqs + `0`,
1219	.LaneMask: LaneBitmask (`0x0000000000000001`),
1220	.AllocationPriority: `0`,
1221	.GlobalPriority: false,
1222	.TSFlags: `0x00`, / TSFlags /
1223	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1224	.CoveredBySubRegs: false, / CoveredBySubRegs /
1225	.SuperClasses: GPRMM16ZeroSuperclasses, .SuperClassesSize: `2`,
1226	.OrderFunc: nullptr
1227	};
1228
1229	extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass = {
1230	.MC: &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16ZeroRegClassID],
1231	.SubClassMask: CPU16Regs_and_GPRMM16ZeroSubClassMask,
1232	.SuperRegIndices: SuperRegIdxSeqs + `0`,
1233	.LaneMask: LaneBitmask (`0x0000000000000001`),
1234	.AllocationPriority: `0`,
1235	.GlobalPriority: false,
1236	.TSFlags: `0x00`, / TSFlags /
1237	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1238	.CoveredBySubRegs: false, / CoveredBySubRegs /
1239	.SuperClasses: CPU16Regs_and_GPRMM16ZeroSuperclasses, .SuperClassesSize: `7`,
1240	.OrderFunc: nullptr
1241	};
1242
1243	extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass = {
1244	.MC: &MipsMCRegisterClasses[GPR32NONZERO_and_GPRMM16MovePRegClassID],
1245	.SubClassMask: GPR32NONZERO_and_GPRMM16MovePSubClassMask,
1246	.SuperRegIndices: SuperRegIdxSeqs + `0`,
1247	.LaneMask: LaneBitmask (`0x0000000000000001`),
1248	.AllocationPriority: `0`,
1249	.GlobalPriority: false,
1250	.TSFlags: `0x00`, / TSFlags /
1251	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1252	.CoveredBySubRegs: false, / CoveredBySubRegs /
1253	.SuperClasses: GPR32NONZERO_and_GPRMM16MovePSuperclasses, .SuperClassesSize: `4`,
1254	.OrderFunc: nullptr
1255	};
1256
1257	extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass = {
1258	.MC: &MipsMCRegisterClasses[GPRMM16MovePPairSecondRegClassID],
1259	.SubClassMask: GPRMM16MovePPairSecondSubClassMask,
1260	.SuperRegIndices: SuperRegIdxSeqs + `0`,
1261	.LaneMask: LaneBitmask (`0x0000000000000001`),
1262	.AllocationPriority: `0`,
1263	.GlobalPriority: false,
1264	.TSFlags: `0x00`, / TSFlags /
1265	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1266	.CoveredBySubRegs: false, / CoveredBySubRegs /
1267	.SuperClasses: GPRMM16MovePPairSecondSuperclasses, .SuperClassesSize: `3`,
1268	.OrderFunc: nullptr
1269	};
1270
1271	extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass = {
1272	.MC: &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePRegClassID],
1273	.SubClassMask: CPU16Regs_and_GPRMM16MovePSubClassMask,
1274	.SuperRegIndices: SuperRegIdxSeqs + `0`,
1275	.LaneMask: LaneBitmask (`0x0000000000000001`),
1276	.AllocationPriority: `0`,
1277	.GlobalPriority: false,
1278	.TSFlags: `0x00`, / TSFlags /
1279	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1280	.CoveredBySubRegs: false, / CoveredBySubRegs /
1281	.SuperClasses: CPU16Regs_and_GPRMM16MovePSuperclasses, .SuperClassesSize: `8`,
1282	.OrderFunc: nullptr
1283	};
1284
1285	extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
1286	.MC: &MipsMCRegisterClasses[GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
1287	.SubClassMask: GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
1288	.SuperRegIndices: SuperRegIdxSeqs + `0`,
1289	.LaneMask: LaneBitmask (`0x0000000000000001`),
1290	.AllocationPriority: `0`,
1291	.GlobalPriority: false,
1292	.TSFlags: `0x00`, / TSFlags /
1293	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1294	.CoveredBySubRegs: false, / CoveredBySubRegs /
1295	.SuperClasses: GPRMM16MoveP_and_GPRMM16ZeroSuperclasses, .SuperClassesSize: `4`,
1296	.OrderFunc: nullptr
1297	};
1298
1299	extern const TargetRegisterClass HI32DSPRegClass = {
1300	.MC: &MipsMCRegisterClasses[HI32DSPRegClassID],
1301	.SubClassMask: HI32DSPSubClassMask,
1302	.SuperRegIndices: SuperRegIdxSeqs + `12`,
1303	.LaneMask: LaneBitmask (`0x0000000000000001`),
1304	.AllocationPriority: `0`,
1305	.GlobalPriority: false,
1306	.TSFlags: `0x00`, / TSFlags /
1307	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1308	.CoveredBySubRegs: false, / CoveredBySubRegs /
1309	.SuperClasses: nullptr, .SuperClassesSize: `0`,
1310	.OrderFunc: nullptr
1311	};
1312
1313	extern const TargetRegisterClass LO32DSPRegClass = {
1314	.MC: &MipsMCRegisterClasses[LO32DSPRegClassID],
1315	.SubClassMask: LO32DSPSubClassMask,
1316	.SuperRegIndices: SuperRegIdxSeqs + `6`,
1317	.LaneMask: LaneBitmask (`0x0000000000000001`),
1318	.AllocationPriority: `0`,
1319	.GlobalPriority: false,
1320	.TSFlags: `0x00`, / TSFlags /
1321	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1322	.CoveredBySubRegs: false, / CoveredBySubRegs /
1323	.SuperClasses: nullptr, .SuperClassesSize: `0`,
1324	.OrderFunc: nullptr
1325	};
1326
1327	extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
1328	.MC: &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],
1329	.SubClassMask: CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,
1330	.SuperRegIndices: SuperRegIdxSeqs + `0`,
1331	.LaneMask: LaneBitmask (`0x0000000000000001`),
1332	.AllocationPriority: `0`,
1333	.GlobalPriority: false,
1334	.TSFlags: `0x00`, / TSFlags /
1335	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1336	.CoveredBySubRegs: false, / CoveredBySubRegs /
1337	.SuperClasses: CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses, .SuperClassesSize: `9`,
1338	.OrderFunc: nullptr
1339	};
1340
1341	extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass = {
1342	.MC: &MipsMCRegisterClasses[GPRMM16MovePPairFirstRegClassID],
1343	.SubClassMask: GPRMM16MovePPairFirstSubClassMask,
1344	.SuperRegIndices: SuperRegIdxSeqs + `0`,
1345	.LaneMask: LaneBitmask (`0x0000000000000001`),
1346	.AllocationPriority: `0`,
1347	.GlobalPriority: false,
1348	.TSFlags: `0x00`, / TSFlags /
1349	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1350	.CoveredBySubRegs: false, / CoveredBySubRegs /
1351	.SuperClasses: GPRMM16MovePPairFirstSuperclasses, .SuperClassesSize: `8`,
1352	.OrderFunc: nullptr
1353	};
1354
1355	extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
1356	.MC: &MipsMCRegisterClasses[GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
1357	.SubClassMask: GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
1358	.SuperRegIndices: SuperRegIdxSeqs + `0`,
1359	.LaneMask: LaneBitmask (`0x0000000000000001`),
1360	.AllocationPriority: `0`,
1361	.GlobalPriority: false,
1362	.TSFlags: `0x00`, / TSFlags /
1363	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1364	.CoveredBySubRegs: false, / CoveredBySubRegs /
1365	.SuperClasses: GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses, .SuperClassesSize: `12`,
1366	.OrderFunc: nullptr
1367	};
1368
1369	extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
1370	.MC: &MipsMCRegisterClasses[GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],
1371	.SubClassMask: GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,
1372	.SuperRegIndices: SuperRegIdxSeqs + `0`,
1373	.LaneMask: LaneBitmask (`0x0000000000000001`),
1374	.AllocationPriority: `0`,
1375	.GlobalPriority: false,
1376	.TSFlags: `0x00`, / TSFlags /
1377	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1378	.CoveredBySubRegs: false, / CoveredBySubRegs /
1379	.SuperClasses: GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses, .SuperClassesSize: `11`,
1380	.OrderFunc: nullptr
1381	};
1382
1383	extern const TargetRegisterClass CPURARegRegClass = {
1384	.MC: &MipsMCRegisterClasses[CPURARegRegClassID],
1385	.SubClassMask: CPURARegSubClassMask,
1386	.SuperRegIndices: SuperRegIdxSeqs + `0`,
1387	.LaneMask: LaneBitmask (`0x0000000000000001`),
1388	.AllocationPriority: `0`,
1389	.GlobalPriority: false,
1390	.TSFlags: `0x00`, / TSFlags /
1391	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1392	.CoveredBySubRegs: false, / CoveredBySubRegs /
1393	.SuperClasses: CPURARegSuperclasses, .SuperClassesSize: `3`,
1394	.OrderFunc: nullptr
1395	};
1396
1397	extern const TargetRegisterClass CPUSPRegRegClass = {
1398	.MC: &MipsMCRegisterClasses[CPUSPRegRegClassID],
1399	.SubClassMask: CPUSPRegSubClassMask,
1400	.SuperRegIndices: SuperRegIdxSeqs + `0`,
1401	.LaneMask: LaneBitmask (`0x0000000000000001`),
1402	.AllocationPriority: `0`,
1403	.GlobalPriority: false,
1404	.TSFlags: `0x00`, / TSFlags /
1405	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1406	.CoveredBySubRegs: false, / CoveredBySubRegs /
1407	.SuperClasses: CPUSPRegSuperclasses, .SuperClassesSize: `4`,
1408	.OrderFunc: nullptr
1409	};
1410
1411	extern const TargetRegisterClass DSPCCRegClass = {
1412	.MC: &MipsMCRegisterClasses[DSPCCRegClassID],
1413	.SubClassMask: DSPCCSubClassMask,
1414	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1415	.LaneMask: LaneBitmask (`0x0000000000000001`),
1416	.AllocationPriority: `0`,
1417	.GlobalPriority: false,
1418	.TSFlags: `0x00`, / TSFlags /
1419	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1420	.CoveredBySubRegs: false, / CoveredBySubRegs /
1421	.SuperClasses: nullptr, .SuperClassesSize: `0`,
1422	.OrderFunc: nullptr
1423	};
1424
1425	extern const TargetRegisterClass GP32RegClass = {
1426	.MC: &MipsMCRegisterClasses[GP32RegClassID],
1427	.SubClassMask: GP32SubClassMask,
1428	.SuperRegIndices: SuperRegIdxSeqs + `0`,
1429	.LaneMask: LaneBitmask (`0x0000000000000001`),
1430	.AllocationPriority: `0`,
1431	.GlobalPriority: false,
1432	.TSFlags: `0x00`, / TSFlags /
1433	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1434	.CoveredBySubRegs: false, / CoveredBySubRegs /
1435	.SuperClasses: GP32Superclasses, .SuperClassesSize: `3`,
1436	.OrderFunc: nullptr
1437	};
1438
1439	extern const TargetRegisterClass GPR32ZERORegClass = {
1440	.MC: &MipsMCRegisterClasses[GPR32ZERORegClassID],
1441	.SubClassMask: GPR32ZEROSubClassMask,
1442	.SuperRegIndices: SuperRegIdxSeqs + `0`,
1443	.LaneMask: LaneBitmask (`0x0000000000000001`),
1444	.AllocationPriority: `0`,
1445	.GlobalPriority: false,
1446	.TSFlags: `0x00`, / TSFlags /
1447	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1448	.CoveredBySubRegs: false, / CoveredBySubRegs /
1449	.SuperClasses: GPR32ZEROSuperclasses, .SuperClassesSize: `5`,
1450	.OrderFunc: nullptr
1451	};
1452
1453	extern const TargetRegisterClass HI32RegClass = {
1454	.MC: &MipsMCRegisterClasses[HI32RegClassID],
1455	.SubClassMask: HI32SubClassMask,
1456	.SuperRegIndices: SuperRegIdxSeqs + `12`,
1457	.LaneMask: LaneBitmask (`0x0000000000000001`),
1458	.AllocationPriority: `0`,
1459	.GlobalPriority: false,
1460	.TSFlags: `0x00`, / TSFlags /
1461	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1462	.CoveredBySubRegs: false, / CoveredBySubRegs /
1463	.SuperClasses: HI32Superclasses, .SuperClassesSize: `1`,
1464	.OrderFunc: nullptr
1465	};
1466
1467	extern const TargetRegisterClass LO32RegClass = {
1468	.MC: &MipsMCRegisterClasses[LO32RegClassID],
1469	.SubClassMask: LO32SubClassMask,
1470	.SuperRegIndices: SuperRegIdxSeqs + `6`,
1471	.LaneMask: LaneBitmask (`0x0000000000000001`),
1472	.AllocationPriority: `0`,
1473	.GlobalPriority: false,
1474	.TSFlags: `0x00`, / TSFlags /
1475	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1476	.CoveredBySubRegs: false, / CoveredBySubRegs /
1477	.SuperClasses: LO32Superclasses, .SuperClassesSize: `1`,
1478	.OrderFunc: nullptr
1479	};
1480
1481	extern const TargetRegisterClass SP32RegClass = {
1482	.MC: &MipsMCRegisterClasses[SP32RegClassID],
1483	.SubClassMask: SP32SubClassMask,
1484	.SuperRegIndices: SuperRegIdxSeqs + `0`,
1485	.LaneMask: LaneBitmask (`0x0000000000000001`),
1486	.AllocationPriority: `0`,
1487	.GlobalPriority: false,
1488	.TSFlags: `0x00`, / TSFlags /
1489	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1490	.CoveredBySubRegs: false, / CoveredBySubRegs /
1491	.SuperClasses: SP32Superclasses, .SuperClassesSize: `5`,
1492	.OrderFunc: nullptr
1493	};
1494
1495	extern const TargetRegisterClass FGR64CCRegClass = {
1496	.MC: &MipsMCRegisterClasses[FGR64CCRegClassID],
1497	.SubClassMask: FGR64CCSubClassMask,
1498	.SuperRegIndices: SuperRegIdxSeqs + `2`,
1499	.LaneMask: LaneBitmask (`0x0000000000000041`),
1500	.AllocationPriority: `0`,
1501	.GlobalPriority: false,
1502	.TSFlags: `0x00`, / TSFlags /
1503	.HasDisjunctSubRegs: true, / HasDisjunctSubRegs /
1504	.CoveredBySubRegs: true, / CoveredBySubRegs /
1505	.SuperClasses: nullptr, .SuperClassesSize: `0`,
1506	.OrderFunc: nullptr
1507	};
1508
1509	extern const TargetRegisterClass FGR64RegClass = {
1510	.MC: &MipsMCRegisterClasses[FGR64RegClassID],
1511	.SubClassMask: FGR64SubClassMask,
1512	.SuperRegIndices: SuperRegIdxSeqs + `2`,
1513	.LaneMask: LaneBitmask (`0x0000000000000041`),
1514	.AllocationPriority: `0`,
1515	.GlobalPriority: false,
1516	.TSFlags: `0x00`, / TSFlags /
1517	.HasDisjunctSubRegs: true, / HasDisjunctSubRegs /
1518	.CoveredBySubRegs: true, / CoveredBySubRegs /
1519	.SuperClasses: FGR64Superclasses, .SuperClassesSize: `1`,
1520	.OrderFunc: FGR64GetRawAllocationOrder
1521	};
1522
1523	extern const TargetRegisterClass GPR64RegClass = {
1524	.MC: &MipsMCRegisterClasses[GPR64RegClassID],
1525	.SubClassMask: GPR64SubClassMask,
1526	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1527	.LaneMask: LaneBitmask (`0x0000000000000001`),
1528	.AllocationPriority: `0`,
1529	.GlobalPriority: false,
1530	.TSFlags: `0x00`, / TSFlags /
1531	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1532	.CoveredBySubRegs: false, / CoveredBySubRegs /
1533	.SuperClasses: nullptr, .SuperClassesSize: `0`,
1534	.OrderFunc: nullptr
1535	};
1536
1537	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass = {
1538	.MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERORegClassID],
1539	.SubClassMask: GPR64_with_sub_32_in_GPR32NONZEROSubClassMask,
1540	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1541	.LaneMask: LaneBitmask (`0x0000000000000001`),
1542	.AllocationPriority: `0`,
1543	.GlobalPriority: false,
1544	.TSFlags: `0x00`, / TSFlags /
1545	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1546	.CoveredBySubRegs: false, / CoveredBySubRegs /
1547	.SuperClasses: GPR64_with_sub_32_in_GPR32NONZEROSuperclasses, .SuperClassesSize: `1`,
1548	.OrderFunc: nullptr
1549	};
1550
1551	extern const TargetRegisterClass AFGR64RegClass = {
1552	.MC: &MipsMCRegisterClasses[AFGR64RegClassID],
1553	.SubClassMask: AFGR64SubClassMask,
1554	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1555	.LaneMask: LaneBitmask (`0x0000000000000041`),
1556	.AllocationPriority: `0`,
1557	.GlobalPriority: false,
1558	.TSFlags: `0x00`, / TSFlags /
1559	.HasDisjunctSubRegs: true, / HasDisjunctSubRegs /
1560	.CoveredBySubRegs: true, / CoveredBySubRegs /
1561	.SuperClasses: nullptr, .SuperClassesSize: `0`,
1562	.OrderFunc: nullptr
1563	};
1564
1565	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass = {
1566	.MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID],
1567	.SubClassMask: GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask,
1568	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1569	.LaneMask: LaneBitmask (`0x0000000000000001`),
1570	.AllocationPriority: `0`,
1571	.GlobalPriority: false,
1572	.TSFlags: `0x00`, / TSFlags /
1573	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1574	.CoveredBySubRegs: false, / CoveredBySubRegs /
1575	.SuperClasses: GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses, .SuperClassesSize: `2`,
1576	.OrderFunc: nullptr
1577	};
1578
1579	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass = {
1580	.MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsRegClassID],
1581	.SubClassMask: GPR64_with_sub_32_in_CPU16RegsSubClassMask,
1582	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1583	.LaneMask: LaneBitmask (`0x0000000000000001`),
1584	.AllocationPriority: `0`,
1585	.GlobalPriority: false,
1586	.TSFlags: `0x00`, / TSFlags /
1587	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1588	.CoveredBySubRegs: false, / CoveredBySubRegs /
1589	.SuperClasses: GPR64_with_sub_32_in_CPU16RegsSuperclasses, .SuperClassesSize: `3`,
1590	.OrderFunc: nullptr
1591	};
1592
1593	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass = {
1594	.MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePRegClassID],
1595	.SubClassMask: GPR64_with_sub_32_in_GPRMM16MovePSubClassMask,
1596	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1597	.LaneMask: LaneBitmask (`0x0000000000000001`),
1598	.AllocationPriority: `0`,
1599	.GlobalPriority: false,
1600	.TSFlags: `0x00`, / TSFlags /
1601	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1602	.CoveredBySubRegs: false, / CoveredBySubRegs /
1603	.SuperClasses: GPR64_with_sub_32_in_GPRMM16MovePSuperclasses, .SuperClassesSize: `1`,
1604	.OrderFunc: nullptr
1605	};
1606
1607	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass = {
1608	.MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16ZeroRegClassID],
1609	.SubClassMask: GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask,
1610	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1611	.LaneMask: LaneBitmask (`0x0000000000000001`),
1612	.AllocationPriority: `0`,
1613	.GlobalPriority: false,
1614	.TSFlags: `0x00`, / TSFlags /
1615	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1616	.CoveredBySubRegs: false, / CoveredBySubRegs /
1617	.SuperClasses: GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses, .SuperClassesSize: `1`,
1618	.OrderFunc: nullptr
1619	};
1620
1621	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass = {
1622	.MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID],
1623	.SubClassMask: GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask,
1624	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1625	.LaneMask: LaneBitmask (`0x0000000000000001`),
1626	.AllocationPriority: `0`,
1627	.GlobalPriority: false,
1628	.TSFlags: `0x00`, / TSFlags /
1629	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1630	.CoveredBySubRegs: false, / CoveredBySubRegs /
1631	.SuperClasses: GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses, .SuperClassesSize: `5`,
1632	.OrderFunc: nullptr
1633	};
1634
1635	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass = {
1636	.MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID],
1637	.SubClassMask: GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask,
1638	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1639	.LaneMask: LaneBitmask (`0x0000000000000001`),
1640	.AllocationPriority: `0`,
1641	.GlobalPriority: false,
1642	.TSFlags: `0x00`, / TSFlags /
1643	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1644	.CoveredBySubRegs: false, / CoveredBySubRegs /
1645	.SuperClasses: GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses, .SuperClassesSize: `3`,
1646	.OrderFunc: nullptr
1647	};
1648
1649	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass = {
1650	.MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID],
1651	.SubClassMask: GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask,
1652	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1653	.LaneMask: LaneBitmask (`0x0000000000000001`),
1654	.AllocationPriority: `0`,
1655	.GlobalPriority: false,
1656	.TSFlags: `0x00`, / TSFlags /
1657	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1658	.CoveredBySubRegs: false, / CoveredBySubRegs /
1659	.SuperClasses: GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses, .SuperClassesSize: `2`,
1660	.OrderFunc: nullptr
1661	};
1662
1663	extern const TargetRegisterClass ACC64DSPRegClass = {
1664	.MC: &MipsMCRegisterClasses[ACC64DSPRegClassID],
1665	.SubClassMask: ACC64DSPSubClassMask,
1666	.SuperRegIndices: SuperRegIdxSeqs + `16`,
1667	.LaneMask: LaneBitmask (`0x0000000000000041`),
1668	.AllocationPriority: `0`,
1669	.GlobalPriority: false,
1670	.TSFlags: `0x00`, / TSFlags /
1671	.HasDisjunctSubRegs: true, / HasDisjunctSubRegs /
1672	.CoveredBySubRegs: true, / CoveredBySubRegs /
1673	.SuperClasses: nullptr, .SuperClassesSize: `0`,
1674	.OrderFunc: nullptr
1675	};
1676
1677	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass = {
1678	.MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID],
1679	.SubClassMask: GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask,
1680	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1681	.LaneMask: LaneBitmask (`0x0000000000000001`),
1682	.AllocationPriority: `0`,
1683	.GlobalPriority: false,
1684	.TSFlags: `0x00`, / TSFlags /
1685	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1686	.CoveredBySubRegs: false, / CoveredBySubRegs /
1687	.SuperClasses: GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses, .SuperClassesSize: `6`,
1688	.OrderFunc: nullptr
1689	};
1690
1691	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
1692	.MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
1693	.SubClassMask: GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
1694	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1695	.LaneMask: LaneBitmask (`0x0000000000000001`),
1696	.AllocationPriority: `0`,
1697	.GlobalPriority: false,
1698	.TSFlags: `0x00`, / TSFlags /
1699	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1700	.CoveredBySubRegs: false, / CoveredBySubRegs /
1701	.SuperClasses: GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses, .SuperClassesSize: `3`,
1702	.OrderFunc: nullptr
1703	};
1704
1705	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
1706	.MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],
1707	.SubClassMask: GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,
1708	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1709	.LaneMask: LaneBitmask (`0x0000000000000001`),
1710	.AllocationPriority: `0`,
1711	.GlobalPriority: false,
1712	.TSFlags: `0x00`, / TSFlags /
1713	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1714	.CoveredBySubRegs: false, / CoveredBySubRegs /
1715	.SuperClasses: GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses, .SuperClassesSize: `7`,
1716	.OrderFunc: nullptr
1717	};
1718
1719	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass = {
1720	.MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID],
1721	.SubClassMask: GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask,
1722	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1723	.LaneMask: LaneBitmask (`0x0000000000000001`),
1724	.AllocationPriority: `0`,
1725	.GlobalPriority: false,
1726	.TSFlags: `0x00`, / TSFlags /
1727	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1728	.CoveredBySubRegs: false, / CoveredBySubRegs /
1729	.SuperClasses: GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses, .SuperClassesSize: `6`,
1730	.OrderFunc: nullptr
1731	};
1732
1733	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
1734	.MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
1735	.SubClassMask: GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
1736	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1737	.LaneMask: LaneBitmask (`0x0000000000000001`),
1738	.AllocationPriority: `0`,
1739	.GlobalPriority: false,
1740	.TSFlags: `0x00`, / TSFlags /
1741	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1742	.CoveredBySubRegs: false, / CoveredBySubRegs /
1743	.SuperClasses: GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses, .SuperClassesSize: `10`,
1744	.OrderFunc: nullptr
1745	};
1746
1747	extern const TargetRegisterClass OCTEON_MPLRegClass = {
1748	.MC: &MipsMCRegisterClasses[OCTEON_MPLRegClassID],
1749	.SubClassMask: OCTEON_MPLSubClassMask,
1750	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1751	.LaneMask: LaneBitmask (`0x0000000000000001`),
1752	.AllocationPriority: `0`,
1753	.GlobalPriority: false,
1754	.TSFlags: `0x00`, / TSFlags /
1755	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1756	.CoveredBySubRegs: false, / CoveredBySubRegs /
1757	.SuperClasses: nullptr, .SuperClassesSize: `0`,
1758	.OrderFunc: nullptr
1759	};
1760
1761	extern const TargetRegisterClass OCTEON_PRegClass = {
1762	.MC: &MipsMCRegisterClasses[OCTEON_PRegClassID],
1763	.SubClassMask: OCTEON_PSubClassMask,
1764	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1765	.LaneMask: LaneBitmask (`0x0000000000000001`),
1766	.AllocationPriority: `0`,
1767	.GlobalPriority: false,
1768	.TSFlags: `0x00`, / TSFlags /
1769	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1770	.CoveredBySubRegs: false, / CoveredBySubRegs /
1771	.SuperClasses: nullptr, .SuperClassesSize: `0`,
1772	.OrderFunc: nullptr
1773	};
1774
1775	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
1776	.MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],
1777	.SubClassMask: GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,
1778	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1779	.LaneMask: LaneBitmask (`0x0000000000000001`),
1780	.AllocationPriority: `0`,
1781	.GlobalPriority: false,
1782	.TSFlags: `0x00`, / TSFlags /
1783	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1784	.CoveredBySubRegs: false, / CoveredBySubRegs /
1785	.SuperClasses: GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses, .SuperClassesSize: `9`,
1786	.OrderFunc: nullptr
1787	};
1788
1789	extern const TargetRegisterClass ACC64RegClass = {
1790	.MC: &MipsMCRegisterClasses[ACC64RegClassID],
1791	.SubClassMask: ACC64SubClassMask,
1792	.SuperRegIndices: SuperRegIdxSeqs + `16`,
1793	.LaneMask: LaneBitmask (`0x0000000000000041`),
1794	.AllocationPriority: `0`,
1795	.GlobalPriority: false,
1796	.TSFlags: `0x00`, / TSFlags /
1797	.HasDisjunctSubRegs: true, / HasDisjunctSubRegs /
1798	.CoveredBySubRegs: true, / CoveredBySubRegs /
1799	.SuperClasses: ACC64Superclasses, .SuperClassesSize: `1`,
1800	.OrderFunc: nullptr
1801	};
1802
1803	extern const TargetRegisterClass GP64RegClass = {
1804	.MC: &MipsMCRegisterClasses[GP64RegClassID],
1805	.SubClassMask: GP64SubClassMask,
1806	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1807	.LaneMask: LaneBitmask (`0x0000000000000001`),
1808	.AllocationPriority: `0`,
1809	.GlobalPriority: false,
1810	.TSFlags: `0x00`, / TSFlags /
1811	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1812	.CoveredBySubRegs: false, / CoveredBySubRegs /
1813	.SuperClasses: GP64Superclasses, .SuperClassesSize: `2`,
1814	.OrderFunc: nullptr
1815	};
1816
1817	extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass = {
1818	.MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPURARegRegClassID],
1819	.SubClassMask: GPR64_with_sub_32_in_CPURARegSubClassMask,
1820	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1821	.LaneMask: LaneBitmask (`0x0000000000000001`),
1822	.AllocationPriority: `0`,
1823	.GlobalPriority: false,
1824	.TSFlags: `0x00`, / TSFlags /
1825	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1826	.CoveredBySubRegs: false, / CoveredBySubRegs /
1827	.SuperClasses: GPR64_with_sub_32_in_CPURARegSuperclasses, .SuperClassesSize: `2`,
1828	.OrderFunc: nullptr
1829	};
1830
1831	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass = {
1832	.MC: &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32ZERORegClassID],
1833	.SubClassMask: GPR64_with_sub_32_in_GPR32ZEROSubClassMask,
1834	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1835	.LaneMask: LaneBitmask (`0x0000000000000001`),
1836	.AllocationPriority: `0`,
1837	.GlobalPriority: false,
1838	.TSFlags: `0x00`, / TSFlags /
1839	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1840	.CoveredBySubRegs: false, / CoveredBySubRegs /
1841	.SuperClasses: GPR64_with_sub_32_in_GPR32ZEROSuperclasses, .SuperClassesSize: `4`,
1842	.OrderFunc: nullptr
1843	};
1844
1845	extern const TargetRegisterClass HI64RegClass = {
1846	.MC: &MipsMCRegisterClasses[HI64RegClassID],
1847	.SubClassMask: HI64SubClassMask,
1848	.SuperRegIndices: SuperRegIdxSeqs + `4`,
1849	.LaneMask: LaneBitmask (`0x0000000000000001`),
1850	.AllocationPriority: `0`,
1851	.GlobalPriority: false,
1852	.TSFlags: `0x00`, / TSFlags /
1853	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1854	.CoveredBySubRegs: false, / CoveredBySubRegs /
1855	.SuperClasses: nullptr, .SuperClassesSize: `0`,
1856	.OrderFunc: nullptr
1857	};
1858
1859	extern const TargetRegisterClass LO64RegClass = {
1860	.MC: &MipsMCRegisterClasses[LO64RegClassID],
1861	.SubClassMask: LO64SubClassMask,
1862	.SuperRegIndices: SuperRegIdxSeqs + `7`,
1863	.LaneMask: LaneBitmask (`0x0000000000000001`),
1864	.AllocationPriority: `0`,
1865	.GlobalPriority: false,
1866	.TSFlags: `0x00`, / TSFlags /
1867	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1868	.CoveredBySubRegs: false, / CoveredBySubRegs /
1869	.SuperClasses: nullptr, .SuperClassesSize: `0`,
1870	.OrderFunc: nullptr
1871	};
1872
1873	extern const TargetRegisterClass SP64RegClass = {
1874	.MC: &MipsMCRegisterClasses[SP64RegClassID],
1875	.SubClassMask: SP64SubClassMask,
1876	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1877	.LaneMask: LaneBitmask (`0x0000000000000001`),
1878	.AllocationPriority: `0`,
1879	.GlobalPriority: false,
1880	.TSFlags: `0x00`, / TSFlags /
1881	.HasDisjunctSubRegs: false, / HasDisjunctSubRegs /
1882	.CoveredBySubRegs: false, / CoveredBySubRegs /
1883	.SuperClasses: SP64Superclasses, .SuperClassesSize: `3`,
1884	.OrderFunc: nullptr
1885	};
1886
1887	extern const TargetRegisterClass MSA128BRegClass = {
1888	.MC: &MipsMCRegisterClasses[MSA128BRegClassID],
1889	.SubClassMask: MSA128BSubClassMask,
1890	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1891	.LaneMask: LaneBitmask (`0x0000000000000041`),
1892	.AllocationPriority: `0`,
1893	.GlobalPriority: false,
1894	.TSFlags: `0x00`, / TSFlags /
1895	.HasDisjunctSubRegs: true, / HasDisjunctSubRegs /
1896	.CoveredBySubRegs: false, / CoveredBySubRegs /
1897	.SuperClasses: MSA128BSuperclasses, .SuperClassesSize: `4`,
1898	.OrderFunc: nullptr
1899	};
1900
1901	extern const TargetRegisterClass MSA128DRegClass = {
1902	.MC: &MipsMCRegisterClasses[MSA128DRegClassID],
1903	.SubClassMask: MSA128DSubClassMask,
1904	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1905	.LaneMask: LaneBitmask (`0x0000000000000041`),
1906	.AllocationPriority: `0`,
1907	.GlobalPriority: false,
1908	.TSFlags: `0x00`, / TSFlags /
1909	.HasDisjunctSubRegs: true, / HasDisjunctSubRegs /
1910	.CoveredBySubRegs: false, / CoveredBySubRegs /
1911	.SuperClasses: MSA128DSuperclasses, .SuperClassesSize: `4`,
1912	.OrderFunc: nullptr
1913	};
1914
1915	extern const TargetRegisterClass MSA128HRegClass = {
1916	.MC: &MipsMCRegisterClasses[MSA128HRegClassID],
1917	.SubClassMask: MSA128HSubClassMask,
1918	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1919	.LaneMask: LaneBitmask (`0x0000000000000041`),
1920	.AllocationPriority: `0`,
1921	.GlobalPriority: false,
1922	.TSFlags: `0x00`, / TSFlags /
1923	.HasDisjunctSubRegs: true, / HasDisjunctSubRegs /
1924	.CoveredBySubRegs: false, / CoveredBySubRegs /
1925	.SuperClasses: MSA128HSuperclasses, .SuperClassesSize: `4`,
1926	.OrderFunc: nullptr
1927	};
1928
1929	extern const TargetRegisterClass MSA128WRegClass = {
1930	.MC: &MipsMCRegisterClasses[MSA128WRegClassID],
1931	.SubClassMask: MSA128WSubClassMask,
1932	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1933	.LaneMask: LaneBitmask (`0x0000000000000041`),
1934	.AllocationPriority: `0`,
1935	.GlobalPriority: false,
1936	.TSFlags: `0x00`, / TSFlags /
1937	.HasDisjunctSubRegs: true, / HasDisjunctSubRegs /
1938	.CoveredBySubRegs: false, / CoveredBySubRegs /
1939	.SuperClasses: MSA128WSuperclasses, .SuperClassesSize: `4`,
1940	.OrderFunc: nullptr
1941	};
1942
1943	extern const TargetRegisterClass MSA128WEvensRegClass = {
1944	.MC: &MipsMCRegisterClasses[MSA128WEvensRegClassID],
1945	.SubClassMask: MSA128WEvensSubClassMask,
1946	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1947	.LaneMask: LaneBitmask (`0x0000000000000041`),
1948	.AllocationPriority: `0`,
1949	.GlobalPriority: false,
1950	.TSFlags: `0x00`, / TSFlags /
1951	.HasDisjunctSubRegs: true, / HasDisjunctSubRegs /
1952	.CoveredBySubRegs: false, / CoveredBySubRegs /
1953	.SuperClasses: MSA128WEvensSuperclasses, .SuperClassesSize: `5`,
1954	.OrderFunc: nullptr
1955	};
1956
1957	extern const TargetRegisterClass ACC128RegClass = {
1958	.MC: &MipsMCRegisterClasses[ACC128RegClassID],
1959	.SubClassMask: ACC128SubClassMask,
1960	.SuperRegIndices: SuperRegIdxSeqs + `1`,
1961	.LaneMask: LaneBitmask (`0x0000000000000041`),
1962	.AllocationPriority: `0`,
1963	.GlobalPriority: false,
1964	.TSFlags: `0x00`, / TSFlags /
1965	.HasDisjunctSubRegs: true, / HasDisjunctSubRegs /
1966	.CoveredBySubRegs: true, / CoveredBySubRegs /
1967	.SuperClasses: nullptr, .SuperClassesSize: `0`,
1968	.OrderFunc: nullptr
1969	};
1970
1971
1972	} // namespace Mips
1973	namespace {
1974
1975	const TargetRegisterClass *const RegisterClasses[] = {
1976	&Mips::MSA128F16RegClass,
1977	&Mips::CCRRegClass,
1978	&Mips::COP0RegClass,
1979	&Mips::COP2RegClass,
1980	&Mips::COP3RegClass,
1981	&Mips::DSPRRegClass,
1982	&Mips::FGR32RegClass,
1983	&Mips::FGR32CCRegClass,
1984	&Mips::GPR32RegClass,
1985	&Mips::HWRegsRegClass,
1986	&Mips::MSACtrlRegClass,
1987	&Mips::GPR32NONZERORegClass,
1988	&Mips::CPU16RegsPlusSPRegClass,
1989	&Mips::CPU16RegsRegClass,
1990	&Mips::FCCRegClass,
1991	&Mips::GPRMM16RegClass,
1992	&Mips::GPRMM16MovePRegClass,
1993	&Mips::GPRMM16ZeroRegClass,
1994	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
1995	&Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
1996	&Mips::GPRMM16MovePPairSecondRegClass,
1997	&Mips::CPU16Regs_and_GPRMM16MovePRegClass,
1998	&Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
1999	&Mips::HI32DSPRegClass,
2000	&Mips::LO32DSPRegClass,
2001	&Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
2002	&Mips::GPRMM16MovePPairFirstRegClass,
2003	&Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
2004	&Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,
2005	&Mips::CPURARegRegClass,
2006	&Mips::CPUSPRegRegClass,
2007	&Mips::DSPCCRegClass,
2008	&Mips::GP32RegClass,
2009	&Mips::GPR32ZERORegClass,
2010	&Mips::HI32RegClass,
2011	&Mips::LO32RegClass,
2012	&Mips::SP32RegClass,
2013	&Mips::FGR64CCRegClass,
2014	&Mips::FGR64RegClass,
2015	&Mips::GPR64RegClass,
2016	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
2017	&Mips::AFGR64RegClass,
2018	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
2019	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
2020	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
2021	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
2022	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
2023	&Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
2024	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,
2025	&Mips::ACC64DSPRegClass,
2026	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,
2027	&Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
2028	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
2029	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,
2030	&Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
2031	&Mips::OCTEON_MPLRegClass,
2032	&Mips::OCTEON_PRegClass,
2033	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,
2034	&Mips::ACC64RegClass,
2035	&Mips::GP64RegClass,
2036	&Mips::GPR64_with_sub_32_in_CPURARegRegClass,
2037	&Mips::GPR64_with_sub_32_in_GPR32ZERORegClass,
2038	&Mips::HI64RegClass,
2039	&Mips::LO64RegClass,
2040	&Mips::SP64RegClass,
2041	&Mips::MSA128BRegClass,
2042	&Mips::MSA128DRegClass,
2043	&Mips::MSA128HRegClass,
2044	&Mips::MSA128WRegClass,
2045	&Mips::MSA128WEvensRegClass,
2046	&Mips::ACC128RegClass,
2047	};
2048	} // namespace
2049
2050	static const uint8_t CostPerUseTable[] = {
2051	`0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, };
2052
2053
2054	static const bool InAllocatableClassTable[] = {
2055	false, true, true, false, false, false, false, false, true, true, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
2056
2057
2058	static const TargetRegisterInfoDesc MipsRegInfoDesc = { // Extra Descriptors
2059	.CostPerUse: CostPerUseTable, .NumCosts: `1`, .InAllocatableClass: InAllocatableClassTable};
2060
2061	unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
2062	static const uint8_t RowMap[`11`] = {
2063	`0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, `0`, `1`,
2064	};
2065	static const uint8_t Rows[`2`][`11`] = {
2066	{ Mips::sub_hi_then_sub_32, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, Mips::sub_lo, `0`, `0`, },
2067	{ Mips::sub_32, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi_then_sub_32, Mips::sub_32, `0`, `0`, },
2068	};
2069
2070	--IdxA; assert(IdxA < `11`); (void) IdxA;
2071	--IdxB; assert(IdxB < `11`);
2072	return Rows[RowMap[IdxA]][IdxB];
2073	}
2074
2075	unsigned MipsGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
2076	static const uint8_t Table[`11`][`11`] = {
2077	{ `0`, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, `0`, },
2078	{ `0`, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, `0`, },
2079	{ `0`, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, `0`, },
2080	{ `0`, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, `0`, },
2081	{ `0`, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, `0`, },
2082	{ `0`, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, `0`, },
2083	{ `0`, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, `0`, },
2084	{ `0`, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, `0`, },
2085	{ Mips::sub_32, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, `0`, },
2086	{ `0`, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, `0`, },
2087	{ Mips::sub_32, `0`, `0`, `0`, `0`, `0`, `0`, `0`, `0`, Mips::sub_hi, `0`, },
2088	};
2089
2090	--IdxA; assert(IdxA < `11`);
2091	--IdxB; assert(IdxB < `11`);
2092	return Table[IdxA][IdxB];
2093	}
2094
2095	struct MaskRolOp {
2096	LaneBitmask Mask;
2097	uint8_t RotateLeft;
2098	};
2099	static const MaskRolOp LaneMaskComposeSequences[] = {
2100	{ .Mask: LaneBitmask (`0xFFFFFFFFFFFFFFFF`), .RotateLeft: `0` }, { .Mask: LaneBitmask::getNone(), .RotateLeft: `0` }, // Sequence 0
2101	{ .Mask: LaneBitmask (`0xFFFFFFFFFFFFFFFF`), .RotateLeft: `1` }, { .Mask: LaneBitmask::getNone(), .RotateLeft: `0` }, // Sequence 2
2102	{ .Mask: LaneBitmask (`0xFFFFFFFFFFFFFFFF`), .RotateLeft: `2` }, { .Mask: LaneBitmask::getNone(), .RotateLeft: `0` }, // Sequence 4
2103	{ .Mask: LaneBitmask (`0xFFFFFFFFFFFFFFFF`), .RotateLeft: `3` }, { .Mask: LaneBitmask::getNone(), .RotateLeft: `0` }, // Sequence 6
2104	{ .Mask: LaneBitmask (`0xFFFFFFFFFFFFFFFF`), .RotateLeft: `4` }, { .Mask: LaneBitmask::getNone(), .RotateLeft: `0` }, // Sequence 8
2105	{ .Mask: LaneBitmask (`0xFFFFFFFFFFFFFFFF`), .RotateLeft: `5` }, { .Mask: LaneBitmask::getNone(), .RotateLeft: `0` }, // Sequence 10
2106	{ .Mask: LaneBitmask (`0xFFFFFFFFFFFFFFFF`), .RotateLeft: `6` }, { .Mask: LaneBitmask::getNone(), .RotateLeft: `0` } // Sequence 12
2107	};
2108	static const uint8_t CompositeSequences[] = {
2109	`0`, // to sub_32
2110	`0`, // to sub_64
2111	`2`, // to sub_dsp16_19
2112	`4`, // to sub_dsp20
2113	`6`, // to sub_dsp21
2114	`8`, // to sub_dsp22
2115	`10`, // to sub_dsp23
2116	`12`, // to sub_hi
2117	`0`, // to sub_lo
2118	`12`, // to sub_hi_then_sub_32
2119	`0` // to sub_32_sub_hi_then_sub_32
2120	};
2121
2122	LaneBitmask MipsGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
2123	--IdxA; assert(IdxA < `11` && "Subregister index out of bounds");
2124	LaneBitmask Result;
2125	for (const MaskRolOp *Ops =
2126	&LaneMaskComposeSequences[CompositeSequences[IdxA]];
2127	Ops->Mask.any(); ++Ops) {
2128	LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
2129	if (unsigned S = Ops->RotateLeft)
2130	Result \|= LaneBitmask ((M << S) \| (M >> (LaneBitmask::BitWidth - S)));
2131	else
2132	Result \|= LaneBitmask (M);
2133	}
2134	return Result;
2135	}
2136
2137	LaneBitmask MipsGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
2138	LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
2139	--IdxA; assert(IdxA < `11` && "Subregister index out of bounds");
2140	LaneBitmask Result;
2141	for (const MaskRolOp *Ops =
2142	&LaneMaskComposeSequences[CompositeSequences[IdxA]];
2143	Ops->Mask.any(); ++Ops) {
2144	LaneBitmask::Type M = LaneMask.getAsInteger();
2145	if (unsigned S = Ops->RotateLeft)
2146	Result \|= LaneBitmask ((M >> S) \| (M << (LaneBitmask::BitWidth - S)));
2147	else
2148	Result \|= LaneBitmask (M);
2149	}
2150	return Result;
2151	}
2152
2153	const TargetRegisterClass MipsGenRegisterInfo::getSubClassWithSubReg(const* TargetRegisterClass RC, unsigned* Idx) const {
2154	static constexpr uint8_t Table[`71`][`11`] = {
2155	{ // MSA128F16
2156	`0`, // sub_32
2157	`1`, // sub_64 -> MSA128F16
2158	`0`, // sub_dsp16_19
2159	`0`, // sub_dsp20
2160	`0`, // sub_dsp21
2161	`0`, // sub_dsp22
2162	`0`, // sub_dsp23
2163	`1`, // sub_hi -> MSA128F16
2164	`1`, // sub_lo -> MSA128F16
2165	`0`, // sub_hi_then_sub_32
2166	`0`, // sub_32_sub_hi_then_sub_32
2167	},
2168	{ // CCR
2169	`0`, // sub_32
2170	`0`, // sub_64
2171	`0`, // sub_dsp16_19
2172	`0`, // sub_dsp20
2173	`0`, // sub_dsp21
2174	`0`, // sub_dsp22
2175	`0`, // sub_dsp23
2176	`0`, // sub_hi
2177	`0`, // sub_lo
2178	`0`, // sub_hi_then_sub_32
2179	`0`, // sub_32_sub_hi_then_sub_32
2180	},
2181	{ // COP0
2182	`0`, // sub_32
2183	`0`, // sub_64
2184	`0`, // sub_dsp16_19
2185	`0`, // sub_dsp20
2186	`0`, // sub_dsp21
2187	`0`, // sub_dsp22
2188	`0`, // sub_dsp23
2189	`0`, // sub_hi
2190	`0`, // sub_lo
2191	`0`, // sub_hi_then_sub_32
2192	`0`, // sub_32_sub_hi_then_sub_32
2193	},
2194	{ // COP2
2195	`0`, // sub_32
2196	`0`, // sub_64
2197	`0`, // sub_dsp16_19
2198	`0`, // sub_dsp20
2199	`0`, // sub_dsp21
2200	`0`, // sub_dsp22
2201	`0`, // sub_dsp23
2202	`0`, // sub_hi
2203	`0`, // sub_lo
2204	`0`, // sub_hi_then_sub_32
2205	`0`, // sub_32_sub_hi_then_sub_32
2206	},
2207	{ // COP3
2208	`0`, // sub_32
2209	`0`, // sub_64
2210	`0`, // sub_dsp16_19
2211	`0`, // sub_dsp20
2212	`0`, // sub_dsp21
2213	`0`, // sub_dsp22
2214	`0`, // sub_dsp23
2215	`0`, // sub_hi
2216	`0`, // sub_lo
2217	`0`, // sub_hi_then_sub_32
2218	`0`, // sub_32_sub_hi_then_sub_32
2219	},
2220	{ // DSPR
2221	`0`, // sub_32
2222	`0`, // sub_64
2223	`0`, // sub_dsp16_19
2224	`0`, // sub_dsp20
2225	`0`, // sub_dsp21
2226	`0`, // sub_dsp22
2227	`0`, // sub_dsp23
2228	`0`, // sub_hi
2229	`0`, // sub_lo
2230	`0`, // sub_hi_then_sub_32
2231	`0`, // sub_32_sub_hi_then_sub_32
2232	},
2233	{ // FGR32
2234	`0`, // sub_32
2235	`0`, // sub_64
2236	`0`, // sub_dsp16_19
2237	`0`, // sub_dsp20
2238	`0`, // sub_dsp21
2239	`0`, // sub_dsp22
2240	`0`, // sub_dsp23
2241	`0`, // sub_hi
2242	`0`, // sub_lo
2243	`0`, // sub_hi_then_sub_32
2244	`0`, // sub_32_sub_hi_then_sub_32
2245	},
2246	{ // FGR32CC
2247	`0`, // sub_32
2248	`0`, // sub_64
2249	`0`, // sub_dsp16_19
2250	`0`, // sub_dsp20
2251	`0`, // sub_dsp21
2252	`0`, // sub_dsp22
2253	`0`, // sub_dsp23
2254	`0`, // sub_hi
2255	`0`, // sub_lo
2256	`0`, // sub_hi_then_sub_32
2257	`0`, // sub_32_sub_hi_then_sub_32
2258	},
2259	{ // GPR32
2260	`0`, // sub_32
2261	`0`, // sub_64
2262	`0`, // sub_dsp16_19
2263	`0`, // sub_dsp20
2264	`0`, // sub_dsp21
2265	`0`, // sub_dsp22
2266	`0`, // sub_dsp23
2267	`0`, // sub_hi
2268	`0`, // sub_lo
2269	`0`, // sub_hi_then_sub_32
2270	`0`, // sub_32_sub_hi_then_sub_32
2271	},
2272	{ // HWRegs
2273	`0`, // sub_32
2274	`0`, // sub_64
2275	`0`, // sub_dsp16_19
2276	`0`, // sub_dsp20
2277	`0`, // sub_dsp21
2278	`0`, // sub_dsp22
2279	`0`, // sub_dsp23
2280	`0`, // sub_hi
2281	`0`, // sub_lo
2282	`0`, // sub_hi_then_sub_32
2283	`0`, // sub_32_sub_hi_then_sub_32
2284	},
2285	{ // MSACtrl
2286	`0`, // sub_32
2287	`0`, // sub_64
2288	`0`, // sub_dsp16_19
2289	`0`, // sub_dsp20
2290	`0`, // sub_dsp21
2291	`0`, // sub_dsp22
2292	`0`, // sub_dsp23
2293	`0`, // sub_hi
2294	`0`, // sub_lo
2295	`0`, // sub_hi_then_sub_32
2296	`0`, // sub_32_sub_hi_then_sub_32
2297	},
2298	{ // GPR32NONZERO
2299	`0`, // sub_32
2300	`0`, // sub_64
2301	`0`, // sub_dsp16_19
2302	`0`, // sub_dsp20
2303	`0`, // sub_dsp21
2304	`0`, // sub_dsp22
2305	`0`, // sub_dsp23
2306	`0`, // sub_hi
2307	`0`, // sub_lo
2308	`0`, // sub_hi_then_sub_32
2309	`0`, // sub_32_sub_hi_then_sub_32
2310	},
2311	{ // CPU16RegsPlusSP
2312	`0`, // sub_32
2313	`0`, // sub_64
2314	`0`, // sub_dsp16_19
2315	`0`, // sub_dsp20
2316	`0`, // sub_dsp21
2317	`0`, // sub_dsp22
2318	`0`, // sub_dsp23
2319	`0`, // sub_hi
2320	`0`, // sub_lo
2321	`0`, // sub_hi_then_sub_32
2322	`0`, // sub_32_sub_hi_then_sub_32
2323	},
2324	{ // CPU16Regs
2325	`0`, // sub_32
2326	`0`, // sub_64
2327	`0`, // sub_dsp16_19
2328	`0`, // sub_dsp20
2329	`0`, // sub_dsp21
2330	`0`, // sub_dsp22
2331	`0`, // sub_dsp23
2332	`0`, // sub_hi
2333	`0`, // sub_lo
2334	`0`, // sub_hi_then_sub_32
2335	`0`, // sub_32_sub_hi_then_sub_32
2336	},
2337	{ // FCC
2338	`0`, // sub_32
2339	`0`, // sub_64
2340	`0`, // sub_dsp16_19
2341	`0`, // sub_dsp20
2342	`0`, // sub_dsp21
2343	`0`, // sub_dsp22
2344	`0`, // sub_dsp23
2345	`0`, // sub_hi
2346	`0`, // sub_lo
2347	`0`, // sub_hi_then_sub_32
2348	`0`, // sub_32_sub_hi_then_sub_32
2349	},
2350	{ // GPRMM16
2351	`0`, // sub_32
2352	`0`, // sub_64
2353	`0`, // sub_dsp16_19
2354	`0`, // sub_dsp20
2355	`0`, // sub_dsp21
2356	`0`, // sub_dsp22
2357	`0`, // sub_dsp23
2358	`0`, // sub_hi
2359	`0`, // sub_lo
2360	`0`, // sub_hi_then_sub_32
2361	`0`, // sub_32_sub_hi_then_sub_32
2362	},
2363	{ // GPRMM16MoveP
2364	`0`, // sub_32
2365	`0`, // sub_64
2366	`0`, // sub_dsp16_19
2367	`0`, // sub_dsp20
2368	`0`, // sub_dsp21
2369	`0`, // sub_dsp22
2370	`0`, // sub_dsp23
2371	`0`, // sub_hi
2372	`0`, // sub_lo
2373	`0`, // sub_hi_then_sub_32
2374	`0`, // sub_32_sub_hi_then_sub_32
2375	},
2376	{ // GPRMM16Zero
2377	`0`, // sub_32
2378	`0`, // sub_64
2379	`0`, // sub_dsp16_19
2380	`0`, // sub_dsp20
2381	`0`, // sub_dsp21
2382	`0`, // sub_dsp22
2383	`0`, // sub_dsp23
2384	`0`, // sub_hi
2385	`0`, // sub_lo
2386	`0`, // sub_hi_then_sub_32
2387	`0`, // sub_32_sub_hi_then_sub_32
2388	},
2389	{ // CPU16Regs_and_GPRMM16Zero
2390	`0`, // sub_32
2391	`0`, // sub_64
2392	`0`, // sub_dsp16_19
2393	`0`, // sub_dsp20
2394	`0`, // sub_dsp21
2395	`0`, // sub_dsp22
2396	`0`, // sub_dsp23
2397	`0`, // sub_hi
2398	`0`, // sub_lo
2399	`0`, // sub_hi_then_sub_32
2400	`0`, // sub_32_sub_hi_then_sub_32
2401	},
2402	{ // GPR32NONZERO_and_GPRMM16MoveP
2403	`0`, // sub_32
2404	`0`, // sub_64
2405	`0`, // sub_dsp16_19
2406	`0`, // sub_dsp20
2407	`0`, // sub_dsp21
2408	`0`, // sub_dsp22
2409	`0`, // sub_dsp23
2410	`0`, // sub_hi
2411	`0`, // sub_lo
2412	`0`, // sub_hi_then_sub_32
2413	`0`, // sub_32_sub_hi_then_sub_32
2414	},
2415	{ // GPRMM16MovePPairSecond
2416	`0`, // sub_32
2417	`0`, // sub_64
2418	`0`, // sub_dsp16_19
2419	`0`, // sub_dsp20
2420	`0`, // sub_dsp21
2421	`0`, // sub_dsp22
2422	`0`, // sub_dsp23
2423	`0`, // sub_hi
2424	`0`, // sub_lo
2425	`0`, // sub_hi_then_sub_32
2426	`0`, // sub_32_sub_hi_then_sub_32
2427	},
2428	{ // CPU16Regs_and_GPRMM16MoveP
2429	`0`, // sub_32
2430	`0`, // sub_64
2431	`0`, // sub_dsp16_19
2432	`0`, // sub_dsp20
2433	`0`, // sub_dsp21
2434	`0`, // sub_dsp22
2435	`0`, // sub_dsp23
2436	`0`, // sub_hi
2437	`0`, // sub_lo
2438	`0`, // sub_hi_then_sub_32
2439	`0`, // sub_32_sub_hi_then_sub_32
2440	},
2441	{ // GPRMM16MoveP_and_GPRMM16Zero
2442	`0`, // sub_32
2443	`0`, // sub_64
2444	`0`, // sub_dsp16_19
2445	`0`, // sub_dsp20
2446	`0`, // sub_dsp21
2447	`0`, // sub_dsp22
2448	`0`, // sub_dsp23
2449	`0`, // sub_hi
2450	`0`, // sub_lo
2451	`0`, // sub_hi_then_sub_32
2452	`0`, // sub_32_sub_hi_then_sub_32
2453	},
2454	{ // HI32DSP
2455	`0`, // sub_32
2456	`0`, // sub_64
2457	`0`, // sub_dsp16_19
2458	`0`, // sub_dsp20
2459	`0`, // sub_dsp21
2460	`0`, // sub_dsp22
2461	`0`, // sub_dsp23
2462	`0`, // sub_hi
2463	`0`, // sub_lo
2464	`0`, // sub_hi_then_sub_32
2465	`0`, // sub_32_sub_hi_then_sub_32
2466	},
2467	{ // LO32DSP
2468	`0`, // sub_32
2469	`0`, // sub_64
2470	`0`, // sub_dsp16_19
2471	`0`, // sub_dsp20
2472	`0`, // sub_dsp21
2473	`0`, // sub_dsp22
2474	`0`, // sub_dsp23
2475	`0`, // sub_hi
2476	`0`, // sub_lo
2477	`0`, // sub_hi_then_sub_32
2478	`0`, // sub_32_sub_hi_then_sub_32
2479	},
2480	{ // CPU16Regs_and_GPRMM16MovePPairSecond
2481	`0`, // sub_32
2482	`0`, // sub_64
2483	`0`, // sub_dsp16_19
2484	`0`, // sub_dsp20
2485	`0`, // sub_dsp21
2486	`0`, // sub_dsp22
2487	`0`, // sub_dsp23
2488	`0`, // sub_hi
2489	`0`, // sub_lo
2490	`0`, // sub_hi_then_sub_32
2491	`0`, // sub_32_sub_hi_then_sub_32
2492	},
2493	{ // GPRMM16MovePPairFirst
2494	`0`, // sub_32
2495	`0`, // sub_64
2496	`0`, // sub_dsp16_19
2497	`0`, // sub_dsp20
2498	`0`, // sub_dsp21
2499	`0`, // sub_dsp22
2500	`0`, // sub_dsp23
2501	`0`, // sub_hi
2502	`0`, // sub_lo
2503	`0`, // sub_hi_then_sub_32
2504	`0`, // sub_32_sub_hi_then_sub_32
2505	},
2506	{ // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
2507	`0`, // sub_32
2508	`0`, // sub_64
2509	`0`, // sub_dsp16_19
2510	`0`, // sub_dsp20
2511	`0`, // sub_dsp21
2512	`0`, // sub_dsp22
2513	`0`, // sub_dsp23
2514	`0`, // sub_hi
2515	`0`, // sub_lo
2516	`0`, // sub_hi_then_sub_32
2517	`0`, // sub_32_sub_hi_then_sub_32
2518	},
2519	{ // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
2520	`0`, // sub_32
2521	`0`, // sub_64
2522	`0`, // sub_dsp16_19
2523	`0`, // sub_dsp20
2524	`0`, // sub_dsp21
2525	`0`, // sub_dsp22
2526	`0`, // sub_dsp23
2527	`0`, // sub_hi
2528	`0`, // sub_lo
2529	`0`, // sub_hi_then_sub_32
2530	`0`, // sub_32_sub_hi_then_sub_32
2531	},
2532	{ // CPURAReg
2533	`0`, // sub_32
2534	`0`, // sub_64
2535	`0`, // sub_dsp16_19
2536	`0`, // sub_dsp20
2537	`0`, // sub_dsp21
2538	`0`, // sub_dsp22
2539	`0`, // sub_dsp23
2540	`0`, // sub_hi
2541	`0`, // sub_lo
2542	`0`, // sub_hi_then_sub_32
2543	`0`, // sub_32_sub_hi_then_sub_32
2544	},
2545	{ // CPUSPReg
2546	`0`, // sub_32
2547	`0`, // sub_64
2548	`0`, // sub_dsp16_19
2549	`0`, // sub_dsp20
2550	`0`, // sub_dsp21
2551	`0`, // sub_dsp22
2552	`0`, // sub_dsp23
2553	`0`, // sub_hi
2554	`0`, // sub_lo
2555	`0`, // sub_hi_then_sub_32
2556	`0`, // sub_32_sub_hi_then_sub_32
2557	},
2558	{ // DSPCC
2559	`0`, // sub_32
2560	`0`, // sub_64
2561	`0`, // sub_dsp16_19
2562	`0`, // sub_dsp20
2563	`0`, // sub_dsp21
2564	`0`, // sub_dsp22
2565	`0`, // sub_dsp23
2566	`0`, // sub_hi
2567	`0`, // sub_lo
2568	`0`, // sub_hi_then_sub_32
2569	`0`, // sub_32_sub_hi_then_sub_32
2570	},
2571	{ // GP32
2572	`0`, // sub_32
2573	`0`, // sub_64
2574	`0`, // sub_dsp16_19
2575	`0`, // sub_dsp20
2576	`0`, // sub_dsp21
2577	`0`, // sub_dsp22
2578	`0`, // sub_dsp23
2579	`0`, // sub_hi
2580	`0`, // sub_lo
2581	`0`, // sub_hi_then_sub_32
2582	`0`, // sub_32_sub_hi_then_sub_32
2583	},
2584	{ // GPR32ZERO
2585	`0`, // sub_32
2586	`0`, // sub_64
2587	`0`, // sub_dsp16_19
2588	`0`, // sub_dsp20
2589	`0`, // sub_dsp21
2590	`0`, // sub_dsp22
2591	`0`, // sub_dsp23
2592	`0`, // sub_hi
2593	`0`, // sub_lo
2594	`0`, // sub_hi_then_sub_32
2595	`0`, // sub_32_sub_hi_then_sub_32
2596	},
2597	{ // HI32
2598	`0`, // sub_32
2599	`0`, // sub_64
2600	`0`, // sub_dsp16_19
2601	`0`, // sub_dsp20
2602	`0`, // sub_dsp21
2603	`0`, // sub_dsp22
2604	`0`, // sub_dsp23
2605	`0`, // sub_hi
2606	`0`, // sub_lo
2607	`0`, // sub_hi_then_sub_32
2608	`0`, // sub_32_sub_hi_then_sub_32
2609	},
2610	{ // LO32
2611	`0`, // sub_32
2612	`0`, // sub_64
2613	`0`, // sub_dsp16_19
2614	`0`, // sub_dsp20
2615	`0`, // sub_dsp21
2616	`0`, // sub_dsp22
2617	`0`, // sub_dsp23
2618	`0`, // sub_hi
2619	`0`, // sub_lo
2620	`0`, // sub_hi_then_sub_32
2621	`0`, // sub_32_sub_hi_then_sub_32
2622	},
2623	{ // SP32
2624	`0`, // sub_32
2625	`0`, // sub_64
2626	`0`, // sub_dsp16_19
2627	`0`, // sub_dsp20
2628	`0`, // sub_dsp21
2629	`0`, // sub_dsp22
2630	`0`, // sub_dsp23
2631	`0`, // sub_hi
2632	`0`, // sub_lo
2633	`0`, // sub_hi_then_sub_32
2634	`0`, // sub_32_sub_hi_then_sub_32
2635	},
2636	{ // FGR64CC
2637	`0`, // sub_32
2638	`0`, // sub_64
2639	`0`, // sub_dsp16_19
2640	`0`, // sub_dsp20
2641	`0`, // sub_dsp21
2642	`0`, // sub_dsp22
2643	`0`, // sub_dsp23
2644	`38`, // sub_hi -> FGR64CC
2645	`38`, // sub_lo -> FGR64CC
2646	`0`, // sub_hi_then_sub_32
2647	`0`, // sub_32_sub_hi_then_sub_32
2648	},
2649	{ // FGR64
2650	`0`, // sub_32
2651	`0`, // sub_64
2652	`0`, // sub_dsp16_19
2653	`0`, // sub_dsp20
2654	`0`, // sub_dsp21
2655	`0`, // sub_dsp22
2656	`0`, // sub_dsp23
2657	`39`, // sub_hi -> FGR64
2658	`39`, // sub_lo -> FGR64
2659	`0`, // sub_hi_then_sub_32
2660	`0`, // sub_32_sub_hi_then_sub_32
2661	},
2662	{ // GPR64
2663	`40`, // sub_32 -> GPR64
2664	`0`, // sub_64
2665	`0`, // sub_dsp16_19
2666	`0`, // sub_dsp20
2667	`0`, // sub_dsp21
2668	`0`, // sub_dsp22
2669	`0`, // sub_dsp23
2670	`0`, // sub_hi
2671	`0`, // sub_lo
2672	`0`, // sub_hi_then_sub_32
2673	`0`, // sub_32_sub_hi_then_sub_32
2674	},
2675	{ // GPR64_with_sub_32_in_GPR32NONZERO
2676	`41`, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO
2677	`0`, // sub_64
2678	`0`, // sub_dsp16_19
2679	`0`, // sub_dsp20
2680	`0`, // sub_dsp21
2681	`0`, // sub_dsp22
2682	`0`, // sub_dsp23
2683	`0`, // sub_hi
2684	`0`, // sub_lo
2685	`0`, // sub_hi_then_sub_32
2686	`0`, // sub_32_sub_hi_then_sub_32
2687	},
2688	{ // AFGR64
2689	`0`, // sub_32
2690	`0`, // sub_64
2691	`0`, // sub_dsp16_19
2692	`0`, // sub_dsp20
2693	`0`, // sub_dsp21
2694	`0`, // sub_dsp22
2695	`0`, // sub_dsp23
2696	`42`, // sub_hi -> AFGR64
2697	`42`, // sub_lo -> AFGR64
2698	`0`, // sub_hi_then_sub_32
2699	`0`, // sub_32_sub_hi_then_sub_32
2700	},
2701	{ // GPR64_with_sub_32_in_CPU16RegsPlusSP
2702	`43`, // sub_32 -> GPR64_with_sub_32_in_CPU16RegsPlusSP
2703	`0`, // sub_64
2704	`0`, // sub_dsp16_19
2705	`0`, // sub_dsp20
2706	`0`, // sub_dsp21
2707	`0`, // sub_dsp22
2708	`0`, // sub_dsp23
2709	`0`, // sub_hi
2710	`0`, // sub_lo
2711	`0`, // sub_hi_then_sub_32
2712	`0`, // sub_32_sub_hi_then_sub_32
2713	},
2714	{ // GPR64_with_sub_32_in_CPU16Regs
2715	`44`, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs
2716	`0`, // sub_64
2717	`0`, // sub_dsp16_19
2718	`0`, // sub_dsp20
2719	`0`, // sub_dsp21
2720	`0`, // sub_dsp22
2721	`0`, // sub_dsp23
2722	`0`, // sub_hi
2723	`0`, // sub_lo
2724	`0`, // sub_hi_then_sub_32
2725	`0`, // sub_32_sub_hi_then_sub_32
2726	},
2727	{ // GPR64_with_sub_32_in_GPRMM16MoveP
2728	`45`, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP
2729	`0`, // sub_64
2730	`0`, // sub_dsp16_19
2731	`0`, // sub_dsp20
2732	`0`, // sub_dsp21
2733	`0`, // sub_dsp22
2734	`0`, // sub_dsp23
2735	`0`, // sub_hi
2736	`0`, // sub_lo
2737	`0`, // sub_hi_then_sub_32
2738	`0`, // sub_32_sub_hi_then_sub_32
2739	},
2740	{ // GPR64_with_sub_32_in_GPRMM16Zero
2741	`46`, // sub_32 -> GPR64_with_sub_32_in_GPRMM16Zero
2742	`0`, // sub_64
2743	`0`, // sub_dsp16_19
2744	`0`, // sub_dsp20
2745	`0`, // sub_dsp21
2746	`0`, // sub_dsp22
2747	`0`, // sub_dsp23
2748	`0`, // sub_hi
2749	`0`, // sub_lo
2750	`0`, // sub_hi_then_sub_32
2751	`0`, // sub_32_sub_hi_then_sub_32
2752	},
2753	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
2754	`47`, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
2755	`0`, // sub_64
2756	`0`, // sub_dsp16_19
2757	`0`, // sub_dsp20
2758	`0`, // sub_dsp21
2759	`0`, // sub_dsp22
2760	`0`, // sub_dsp23
2761	`0`, // sub_hi
2762	`0`, // sub_lo
2763	`0`, // sub_hi_then_sub_32
2764	`0`, // sub_32_sub_hi_then_sub_32
2765	},
2766	{ // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
2767	`48`, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
2768	`0`, // sub_64
2769	`0`, // sub_dsp16_19
2770	`0`, // sub_dsp20
2771	`0`, // sub_dsp21
2772	`0`, // sub_dsp22
2773	`0`, // sub_dsp23
2774	`0`, // sub_hi
2775	`0`, // sub_lo
2776	`0`, // sub_hi_then_sub_32
2777	`0`, // sub_32_sub_hi_then_sub_32
2778	},
2779	{ // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
2780	`49`, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairSecond
2781	`0`, // sub_64
2782	`0`, // sub_dsp16_19
2783	`0`, // sub_dsp20
2784	`0`, // sub_dsp21
2785	`0`, // sub_dsp22
2786	`0`, // sub_dsp23
2787	`0`, // sub_hi
2788	`0`, // sub_lo
2789	`0`, // sub_hi_then_sub_32
2790	`0`, // sub_32_sub_hi_then_sub_32
2791	},
2792	{ // ACC64DSP
2793	`0`, // sub_32
2794	`0`, // sub_64
2795	`0`, // sub_dsp16_19
2796	`0`, // sub_dsp20
2797	`0`, // sub_dsp21
2798	`0`, // sub_dsp22
2799	`0`, // sub_dsp23
2800	`50`, // sub_hi -> ACC64DSP
2801	`50`, // sub_lo -> ACC64DSP
2802	`0`, // sub_hi_then_sub_32
2803	`0`, // sub_32_sub_hi_then_sub_32
2804	},
2805	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
2806	`51`, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
2807	`0`, // sub_64
2808	`0`, // sub_dsp16_19
2809	`0`, // sub_dsp20
2810	`0`, // sub_dsp21
2811	`0`, // sub_dsp22
2812	`0`, // sub_dsp23
2813	`0`, // sub_hi
2814	`0`, // sub_lo
2815	`0`, // sub_hi_then_sub_32
2816	`0`, // sub_32_sub_hi_then_sub_32
2817	},
2818	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
2819	`52`, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
2820	`0`, // sub_64
2821	`0`, // sub_dsp16_19
2822	`0`, // sub_dsp20
2823	`0`, // sub_dsp21
2824	`0`, // sub_dsp22
2825	`0`, // sub_dsp23
2826	`0`, // sub_hi
2827	`0`, // sub_lo
2828	`0`, // sub_hi_then_sub_32
2829	`0`, // sub_32_sub_hi_then_sub_32
2830	},
2831	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
2832	`53`, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
2833	`0`, // sub_64
2834	`0`, // sub_dsp16_19
2835	`0`, // sub_dsp20
2836	`0`, // sub_dsp21
2837	`0`, // sub_dsp22
2838	`0`, // sub_dsp23
2839	`0`, // sub_hi
2840	`0`, // sub_lo
2841	`0`, // sub_hi_then_sub_32
2842	`0`, // sub_32_sub_hi_then_sub_32
2843	},
2844	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
2845	`54`, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst
2846	`0`, // sub_64
2847	`0`, // sub_dsp16_19
2848	`0`, // sub_dsp20
2849	`0`, // sub_dsp21
2850	`0`, // sub_dsp22
2851	`0`, // sub_dsp23
2852	`0`, // sub_hi
2853	`0`, // sub_lo
2854	`0`, // sub_hi_then_sub_32
2855	`0`, // sub_32_sub_hi_then_sub_32
2856	},
2857	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
2858	`55`, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
2859	`0`, // sub_64
2860	`0`, // sub_dsp16_19
2861	`0`, // sub_dsp20
2862	`0`, // sub_dsp21
2863	`0`, // sub_dsp22
2864	`0`, // sub_dsp23
2865	`0`, // sub_hi
2866	`0`, // sub_lo
2867	`0`, // sub_hi_then_sub_32
2868	`0`, // sub_32_sub_hi_then_sub_32
2869	},
2870	{ // OCTEON_MPL
2871	`0`, // sub_32
2872	`0`, // sub_64
2873	`0`, // sub_dsp16_19
2874	`0`, // sub_dsp20
2875	`0`, // sub_dsp21
2876	`0`, // sub_dsp22
2877	`0`, // sub_dsp23
2878	`0`, // sub_hi
2879	`0`, // sub_lo
2880	`0`, // sub_hi_then_sub_32
2881	`0`, // sub_32_sub_hi_then_sub_32
2882	},
2883	{ // OCTEON_P
2884	`0`, // sub_32
2885	`0`, // sub_64
2886	`0`, // sub_dsp16_19
2887	`0`, // sub_dsp20
2888	`0`, // sub_dsp21
2889	`0`, // sub_dsp22
2890	`0`, // sub_dsp23
2891	`0`, // sub_hi
2892	`0`, // sub_lo
2893	`0`, // sub_hi_then_sub_32
2894	`0`, // sub_32_sub_hi_then_sub_32
2895	},
2896	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
2897	`58`, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
2898	`0`, // sub_64
2899	`0`, // sub_dsp16_19
2900	`0`, // sub_dsp20
2901	`0`, // sub_dsp21
2902	`0`, // sub_dsp22
2903	`0`, // sub_dsp23
2904	`0`, // sub_hi
2905	`0`, // sub_lo
2906	`0`, // sub_hi_then_sub_32
2907	`0`, // sub_32_sub_hi_then_sub_32
2908	},
2909	{ // ACC64
2910	`0`, // sub_32
2911	`0`, // sub_64
2912	`0`, // sub_dsp16_19
2913	`0`, // sub_dsp20
2914	`0`, // sub_dsp21
2915	`0`, // sub_dsp22
2916	`0`, // sub_dsp23
2917	`59`, // sub_hi -> ACC64
2918	`59`, // sub_lo -> ACC64
2919	`0`, // sub_hi_then_sub_32
2920	`0`, // sub_32_sub_hi_then_sub_32
2921	},
2922	{ // GP64
2923	`60`, // sub_32 -> GP64
2924	`0`, // sub_64
2925	`0`, // sub_dsp16_19
2926	`0`, // sub_dsp20
2927	`0`, // sub_dsp21
2928	`0`, // sub_dsp22
2929	`0`, // sub_dsp23
2930	`0`, // sub_hi
2931	`0`, // sub_lo
2932	`0`, // sub_hi_then_sub_32
2933	`0`, // sub_32_sub_hi_then_sub_32
2934	},
2935	{ // GPR64_with_sub_32_in_CPURAReg
2936	`61`, // sub_32 -> GPR64_with_sub_32_in_CPURAReg
2937	`0`, // sub_64
2938	`0`, // sub_dsp16_19
2939	`0`, // sub_dsp20
2940	`0`, // sub_dsp21
2941	`0`, // sub_dsp22
2942	`0`, // sub_dsp23
2943	`0`, // sub_hi
2944	`0`, // sub_lo
2945	`0`, // sub_hi_then_sub_32
2946	`0`, // sub_32_sub_hi_then_sub_32
2947	},
2948	{ // GPR64_with_sub_32_in_GPR32ZERO
2949	`62`, // sub_32 -> GPR64_with_sub_32_in_GPR32ZERO
2950	`0`, // sub_64
2951	`0`, // sub_dsp16_19
2952	`0`, // sub_dsp20
2953	`0`, // sub_dsp21
2954	`0`, // sub_dsp22
2955	`0`, // sub_dsp23
2956	`0`, // sub_hi
2957	`0`, // sub_lo
2958	`0`, // sub_hi_then_sub_32
2959	`0`, // sub_32_sub_hi_then_sub_32
2960	},
2961	{ // HI64
2962	`63`, // sub_32 -> HI64
2963	`0`, // sub_64
2964	`0`, // sub_dsp16_19
2965	`0`, // sub_dsp20
2966	`0`, // sub_dsp21
2967	`0`, // sub_dsp22
2968	`0`, // sub_dsp23
2969	`0`, // sub_hi
2970	`0`, // sub_lo
2971	`0`, // sub_hi_then_sub_32
2972	`0`, // sub_32_sub_hi_then_sub_32
2973	},
2974	{ // LO64
2975	`64`, // sub_32 -> LO64
2976	`0`, // sub_64
2977	`0`, // sub_dsp16_19
2978	`0`, // sub_dsp20
2979	`0`, // sub_dsp21
2980	`0`, // sub_dsp22
2981	`0`, // sub_dsp23
2982	`0`, // sub_hi
2983	`0`, // sub_lo
2984	`0`, // sub_hi_then_sub_32
2985	`0`, // sub_32_sub_hi_then_sub_32
2986	},
2987	{ // SP64
2988	`65`, // sub_32 -> SP64
2989	`0`, // sub_64
2990	`0`, // sub_dsp16_19
2991	`0`, // sub_dsp20
2992	`0`, // sub_dsp21
2993	`0`, // sub_dsp22
2994	`0`, // sub_dsp23
2995	`0`, // sub_hi
2996	`0`, // sub_lo
2997	`0`, // sub_hi_then_sub_32
2998	`0`, // sub_32_sub_hi_then_sub_32
2999	},
3000	{ // MSA128B
3001	`0`, // sub_32
3002	`66`, // sub_64 -> MSA128B
3003	`0`, // sub_dsp16_19
3004	`0`, // sub_dsp20
3005	`0`, // sub_dsp21
3006	`0`, // sub_dsp22
3007	`0`, // sub_dsp23
3008	`66`, // sub_hi -> MSA128B
3009	`66`, // sub_lo -> MSA128B
3010	`0`, // sub_hi_then_sub_32
3011	`0`, // sub_32_sub_hi_then_sub_32
3012	},
3013	{ // MSA128D
3014	`0`, // sub_32
3015	`67`, // sub_64 -> MSA128D
3016	`0`, // sub_dsp16_19
3017	`0`, // sub_dsp20
3018	`0`, // sub_dsp21
3019	`0`, // sub_dsp22
3020	`0`, // sub_dsp23
3021	`67`, // sub_hi -> MSA128D
3022	`67`, // sub_lo -> MSA128D
3023	`0`, // sub_hi_then_sub_32
3024	`0`, // sub_32_sub_hi_then_sub_32
3025	},
3026	{ // MSA128H
3027	`0`, // sub_32
3028	`68`, // sub_64 -> MSA128H
3029	`0`, // sub_dsp16_19
3030	`0`, // sub_dsp20
3031	`0`, // sub_dsp21
3032	`0`, // sub_dsp22
3033	`0`, // sub_dsp23
3034	`68`, // sub_hi -> MSA128H
3035	`68`, // sub_lo -> MSA128H
3036	`0`, // sub_hi_then_sub_32
3037	`0`, // sub_32_sub_hi_then_sub_32
3038	},
3039	{ // MSA128W
3040	`0`, // sub_32
3041	`69`, // sub_64 -> MSA128W
3042	`0`, // sub_dsp16_19
3043	`0`, // sub_dsp20
3044	`0`, // sub_dsp21
3045	`0`, // sub_dsp22
3046	`0`, // sub_dsp23
3047	`69`, // sub_hi -> MSA128W
3048	`69`, // sub_lo -> MSA128W
3049	`0`, // sub_hi_then_sub_32
3050	`0`, // sub_32_sub_hi_then_sub_32
3051	},
3052	{ // MSA128WEvens
3053	`0`, // sub_32
3054	`70`, // sub_64 -> MSA128WEvens
3055	`0`, // sub_dsp16_19
3056	`0`, // sub_dsp20
3057	`0`, // sub_dsp21
3058	`0`, // sub_dsp22
3059	`0`, // sub_dsp23
3060	`70`, // sub_hi -> MSA128WEvens
3061	`70`, // sub_lo -> MSA128WEvens
3062	`0`, // sub_hi_then_sub_32
3063	`0`, // sub_32_sub_hi_then_sub_32
3064	},
3065	{ // ACC128
3066	`71`, // sub_32 -> ACC128
3067	`0`, // sub_64
3068	`0`, // sub_dsp16_19
3069	`0`, // sub_dsp20
3070	`0`, // sub_dsp21
3071	`0`, // sub_dsp22
3072	`0`, // sub_dsp23
3073	`71`, // sub_hi -> ACC128
3074	`71`, // sub_lo -> ACC128
3075	`71`, // sub_hi_then_sub_32 -> ACC128
3076	`71`, // sub_32_sub_hi_then_sub_32 -> ACC128
3077	},
3078
3079	};
3080	assert(RC && "Missing regclass");
3081	if (!Idx) return RC;
3082	--Idx;
3083	assert(Idx < `11` && "Bad subreg");
3084	unsigned TV = Table[RC->getID()][Idx];
3085	return TV ? getRegClass(i: TV - `1`) : nullptr;
3086	}const TargetRegisterClass MipsGenRegisterInfo::getSubRegisterClass(const* TargetRegisterClass RC, unsigned* Idx) const {
3087	static constexpr uint8_t Table[`71`][`11`] = {
3088	{ // MSA128F16
3089	`0`, // MSA128F16:sub_32
3090	`38`, // MSA128F16:sub_64 -> FGR64CC
3091	`0`, // MSA128F16:sub_dsp16_19
3092	`0`, // MSA128F16:sub_dsp20
3093	`0`, // MSA128F16:sub_dsp21
3094	`0`, // MSA128F16:sub_dsp22
3095	`0`, // MSA128F16:sub_dsp23
3096	`0`, // MSA128F16:sub_hi
3097	`7`, // MSA128F16:sub_lo -> FGR32
3098	`0`, // MSA128F16:sub_hi_then_sub_32
3099	`0`, // MSA128F16:sub_32_sub_hi_then_sub_32
3100	},
3101	{ // CCR
3102	`0`, // CCR:sub_32
3103	`0`, // CCR:sub_64
3104	`0`, // CCR:sub_dsp16_19
3105	`0`, // CCR:sub_dsp20
3106	`0`, // CCR:sub_dsp21
3107	`0`, // CCR:sub_dsp22
3108	`0`, // CCR:sub_dsp23
3109	`0`, // CCR:sub_hi
3110	`0`, // CCR:sub_lo
3111	`0`, // CCR:sub_hi_then_sub_32
3112	`0`, // CCR:sub_32_sub_hi_then_sub_32
3113	},
3114	{ // COP0
3115	`0`, // COP0:sub_32
3116	`0`, // COP0:sub_64
3117	`0`, // COP0:sub_dsp16_19
3118	`0`, // COP0:sub_dsp20
3119	`0`, // COP0:sub_dsp21
3120	`0`, // COP0:sub_dsp22
3121	`0`, // COP0:sub_dsp23
3122	`0`, // COP0:sub_hi
3123	`0`, // COP0:sub_lo
3124	`0`, // COP0:sub_hi_then_sub_32
3125	`0`, // COP0:sub_32_sub_hi_then_sub_32
3126	},
3127	{ // COP2
3128	`0`, // COP2:sub_32
3129	`0`, // COP2:sub_64
3130	`0`, // COP2:sub_dsp16_19
3131	`0`, // COP2:sub_dsp20
3132	`0`, // COP2:sub_dsp21
3133	`0`, // COP2:sub_dsp22
3134	`0`, // COP2:sub_dsp23
3135	`0`, // COP2:sub_hi
3136	`0`, // COP2:sub_lo
3137	`0`, // COP2:sub_hi_then_sub_32
3138	`0`, // COP2:sub_32_sub_hi_then_sub_32
3139	},
3140	{ // COP3
3141	`0`, // COP3:sub_32
3142	`0`, // COP3:sub_64
3143	`0`, // COP3:sub_dsp16_19
3144	`0`, // COP3:sub_dsp20
3145	`0`, // COP3:sub_dsp21
3146	`0`, // COP3:sub_dsp22
3147	`0`, // COP3:sub_dsp23
3148	`0`, // COP3:sub_hi
3149	`0`, // COP3:sub_lo
3150	`0`, // COP3:sub_hi_then_sub_32
3151	`0`, // COP3:sub_32_sub_hi_then_sub_32
3152	},
3153	{ // DSPR
3154	`0`, // DSPR:sub_32
3155	`0`, // DSPR:sub_64
3156	`0`, // DSPR:sub_dsp16_19
3157	`0`, // DSPR:sub_dsp20
3158	`0`, // DSPR:sub_dsp21
3159	`0`, // DSPR:sub_dsp22
3160	`0`, // DSPR:sub_dsp23
3161	`0`, // DSPR:sub_hi
3162	`0`, // DSPR:sub_lo
3163	`0`, // DSPR:sub_hi_then_sub_32
3164	`0`, // DSPR:sub_32_sub_hi_then_sub_32
3165	},
3166	{ // FGR32
3167	`0`, // FGR32:sub_32
3168	`0`, // FGR32:sub_64
3169	`0`, // FGR32:sub_dsp16_19
3170	`0`, // FGR32:sub_dsp20
3171	`0`, // FGR32:sub_dsp21
3172	`0`, // FGR32:sub_dsp22
3173	`0`, // FGR32:sub_dsp23
3174	`0`, // FGR32:sub_hi
3175	`0`, // FGR32:sub_lo
3176	`0`, // FGR32:sub_hi_then_sub_32
3177	`0`, // FGR32:sub_32_sub_hi_then_sub_32
3178	},
3179	{ // FGR32CC
3180	`0`, // FGR32CC:sub_32
3181	`0`, // FGR32CC:sub_64
3182	`0`, // FGR32CC:sub_dsp16_19
3183	`0`, // FGR32CC:sub_dsp20
3184	`0`, // FGR32CC:sub_dsp21
3185	`0`, // FGR32CC:sub_dsp22
3186	`0`, // FGR32CC:sub_dsp23
3187	`0`, // FGR32CC:sub_hi
3188	`0`, // FGR32CC:sub_lo
3189	`0`, // FGR32CC:sub_hi_then_sub_32
3190	`0`, // FGR32CC:sub_32_sub_hi_then_sub_32
3191	},
3192	{ // GPR32
3193	`0`, // GPR32:sub_32
3194	`0`, // GPR32:sub_64
3195	`0`, // GPR32:sub_dsp16_19
3196	`0`, // GPR32:sub_dsp20
3197	`0`, // GPR32:sub_dsp21
3198	`0`, // GPR32:sub_dsp22
3199	`0`, // GPR32:sub_dsp23
3200	`0`, // GPR32:sub_hi
3201	`0`, // GPR32:sub_lo
3202	`0`, // GPR32:sub_hi_then_sub_32
3203	`0`, // GPR32:sub_32_sub_hi_then_sub_32
3204	},
3205	{ // HWRegs
3206	`0`, // HWRegs:sub_32
3207	`0`, // HWRegs:sub_64
3208	`0`, // HWRegs:sub_dsp16_19
3209	`0`, // HWRegs:sub_dsp20
3210	`0`, // HWRegs:sub_dsp21
3211	`0`, // HWRegs:sub_dsp22
3212	`0`, // HWRegs:sub_dsp23
3213	`0`, // HWRegs:sub_hi
3214	`0`, // HWRegs:sub_lo
3215	`0`, // HWRegs:sub_hi_then_sub_32
3216	`0`, // HWRegs:sub_32_sub_hi_then_sub_32
3217	},
3218	{ // MSACtrl
3219	`0`, // MSACtrl:sub_32
3220	`0`, // MSACtrl:sub_64
3221	`0`, // MSACtrl:sub_dsp16_19
3222	`0`, // MSACtrl:sub_dsp20
3223	`0`, // MSACtrl:sub_dsp21
3224	`0`, // MSACtrl:sub_dsp22
3225	`0`, // MSACtrl:sub_dsp23
3226	`0`, // MSACtrl:sub_hi
3227	`0`, // MSACtrl:sub_lo
3228	`0`, // MSACtrl:sub_hi_then_sub_32
3229	`0`, // MSACtrl:sub_32_sub_hi_then_sub_32
3230	},
3231	{ // GPR32NONZERO
3232	`0`, // GPR32NONZERO:sub_32
3233	`0`, // GPR32NONZERO:sub_64
3234	`0`, // GPR32NONZERO:sub_dsp16_19
3235	`0`, // GPR32NONZERO:sub_dsp20
3236	`0`, // GPR32NONZERO:sub_dsp21
3237	`0`, // GPR32NONZERO:sub_dsp22
3238	`0`, // GPR32NONZERO:sub_dsp23
3239	`0`, // GPR32NONZERO:sub_hi
3240	`0`, // GPR32NONZERO:sub_lo
3241	`0`, // GPR32NONZERO:sub_hi_then_sub_32
3242	`0`, // GPR32NONZERO:sub_32_sub_hi_then_sub_32
3243	},
3244	{ // CPU16RegsPlusSP
3245	`0`, // CPU16RegsPlusSP:sub_32
3246	`0`, // CPU16RegsPlusSP:sub_64
3247	`0`, // CPU16RegsPlusSP:sub_dsp16_19
3248	`0`, // CPU16RegsPlusSP:sub_dsp20
3249	`0`, // CPU16RegsPlusSP:sub_dsp21
3250	`0`, // CPU16RegsPlusSP:sub_dsp22
3251	`0`, // CPU16RegsPlusSP:sub_dsp23
3252	`0`, // CPU16RegsPlusSP:sub_hi
3253	`0`, // CPU16RegsPlusSP:sub_lo
3254	`0`, // CPU16RegsPlusSP:sub_hi_then_sub_32
3255	`0`, // CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32
3256	},
3257	{ // CPU16Regs
3258	`0`, // CPU16Regs:sub_32
3259	`0`, // CPU16Regs:sub_64
3260	`0`, // CPU16Regs:sub_dsp16_19
3261	`0`, // CPU16Regs:sub_dsp20
3262	`0`, // CPU16Regs:sub_dsp21
3263	`0`, // CPU16Regs:sub_dsp22
3264	`0`, // CPU16Regs:sub_dsp23
3265	`0`, // CPU16Regs:sub_hi
3266	`0`, // CPU16Regs:sub_lo
3267	`0`, // CPU16Regs:sub_hi_then_sub_32
3268	`0`, // CPU16Regs:sub_32_sub_hi_then_sub_32
3269	},
3270	{ // FCC
3271	`0`, // FCC:sub_32
3272	`0`, // FCC:sub_64
3273	`0`, // FCC:sub_dsp16_19
3274	`0`, // FCC:sub_dsp20
3275	`0`, // FCC:sub_dsp21
3276	`0`, // FCC:sub_dsp22
3277	`0`, // FCC:sub_dsp23
3278	`0`, // FCC:sub_hi
3279	`0`, // FCC:sub_lo
3280	`0`, // FCC:sub_hi_then_sub_32
3281	`0`, // FCC:sub_32_sub_hi_then_sub_32
3282	},
3283	{ // GPRMM16
3284	`0`, // GPRMM16:sub_32
3285	`0`, // GPRMM16:sub_64
3286	`0`, // GPRMM16:sub_dsp16_19
3287	`0`, // GPRMM16:sub_dsp20
3288	`0`, // GPRMM16:sub_dsp21
3289	`0`, // GPRMM16:sub_dsp22
3290	`0`, // GPRMM16:sub_dsp23
3291	`0`, // GPRMM16:sub_hi
3292	`0`, // GPRMM16:sub_lo
3293	`0`, // GPRMM16:sub_hi_then_sub_32
3294	`0`, // GPRMM16:sub_32_sub_hi_then_sub_32
3295	},
3296	{ // GPRMM16MoveP
3297	`0`, // GPRMM16MoveP:sub_32
3298	`0`, // GPRMM16MoveP:sub_64
3299	`0`, // GPRMM16MoveP:sub_dsp16_19
3300	`0`, // GPRMM16MoveP:sub_dsp20
3301	`0`, // GPRMM16MoveP:sub_dsp21
3302	`0`, // GPRMM16MoveP:sub_dsp22
3303	`0`, // GPRMM16MoveP:sub_dsp23
3304	`0`, // GPRMM16MoveP:sub_hi
3305	`0`, // GPRMM16MoveP:sub_lo
3306	`0`, // GPRMM16MoveP:sub_hi_then_sub_32
3307	`0`, // GPRMM16MoveP:sub_32_sub_hi_then_sub_32
3308	},
3309	{ // GPRMM16Zero
3310	`0`, // GPRMM16Zero:sub_32
3311	`0`, // GPRMM16Zero:sub_64
3312	`0`, // GPRMM16Zero:sub_dsp16_19
3313	`0`, // GPRMM16Zero:sub_dsp20
3314	`0`, // GPRMM16Zero:sub_dsp21
3315	`0`, // GPRMM16Zero:sub_dsp22
3316	`0`, // GPRMM16Zero:sub_dsp23
3317	`0`, // GPRMM16Zero:sub_hi
3318	`0`, // GPRMM16Zero:sub_lo
3319	`0`, // GPRMM16Zero:sub_hi_then_sub_32
3320	`0`, // GPRMM16Zero:sub_32_sub_hi_then_sub_32
3321	},
3322	{ // CPU16Regs_and_GPRMM16Zero
3323	`0`, // CPU16Regs_and_GPRMM16Zero:sub_32
3324	`0`, // CPU16Regs_and_GPRMM16Zero:sub_64
3325	`0`, // CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
3326	`0`, // CPU16Regs_and_GPRMM16Zero:sub_dsp20
3327	`0`, // CPU16Regs_and_GPRMM16Zero:sub_dsp21
3328	`0`, // CPU16Regs_and_GPRMM16Zero:sub_dsp22
3329	`0`, // CPU16Regs_and_GPRMM16Zero:sub_dsp23
3330	`0`, // CPU16Regs_and_GPRMM16Zero:sub_hi
3331	`0`, // CPU16Regs_and_GPRMM16Zero:sub_lo
3332	`0`, // CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
3333	`0`, // CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
3334	},
3335	{ // GPR32NONZERO_and_GPRMM16MoveP
3336	`0`, // GPR32NONZERO_and_GPRMM16MoveP:sub_32
3337	`0`, // GPR32NONZERO_and_GPRMM16MoveP:sub_64
3338	`0`, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19
3339	`0`, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20
3340	`0`, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21
3341	`0`, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22
3342	`0`, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23
3343	`0`, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi
3344	`0`, // GPR32NONZERO_and_GPRMM16MoveP:sub_lo
3345	`0`, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32
3346	`0`, // GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
3347	},
3348	{ // GPRMM16MovePPairSecond
3349	`0`, // GPRMM16MovePPairSecond:sub_32
3350	`0`, // GPRMM16MovePPairSecond:sub_64
3351	`0`, // GPRMM16MovePPairSecond:sub_dsp16_19
3352	`0`, // GPRMM16MovePPairSecond:sub_dsp20
3353	`0`, // GPRMM16MovePPairSecond:sub_dsp21
3354	`0`, // GPRMM16MovePPairSecond:sub_dsp22
3355	`0`, // GPRMM16MovePPairSecond:sub_dsp23
3356	`0`, // GPRMM16MovePPairSecond:sub_hi
3357	`0`, // GPRMM16MovePPairSecond:sub_lo
3358	`0`, // GPRMM16MovePPairSecond:sub_hi_then_sub_32
3359	`0`, // GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
3360	},
3361	{ // CPU16Regs_and_GPRMM16MoveP
3362	`0`, // CPU16Regs_and_GPRMM16MoveP:sub_32
3363	`0`, // CPU16Regs_and_GPRMM16MoveP:sub_64
3364	`0`, // CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19
3365	`0`, // CPU16Regs_and_GPRMM16MoveP:sub_dsp20
3366	`0`, // CPU16Regs_and_GPRMM16MoveP:sub_dsp21
3367	`0`, // CPU16Regs_and_GPRMM16MoveP:sub_dsp22
3368	`0`, // CPU16Regs_and_GPRMM16MoveP:sub_dsp23
3369	`0`, // CPU16Regs_and_GPRMM16MoveP:sub_hi
3370	`0`, // CPU16Regs_and_GPRMM16MoveP:sub_lo
3371	`0`, // CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32
3372	`0`, // CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
3373	},
3374	{ // GPRMM16MoveP_and_GPRMM16Zero
3375	`0`, // GPRMM16MoveP_and_GPRMM16Zero:sub_32
3376	`0`, // GPRMM16MoveP_and_GPRMM16Zero:sub_64
3377	`0`, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19
3378	`0`, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20
3379	`0`, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21
3380	`0`, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22
3381	`0`, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23
3382	`0`, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi
3383	`0`, // GPRMM16MoveP_and_GPRMM16Zero:sub_lo
3384	`0`, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32
3385	`0`, // GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
3386	},
3387	{ // HI32DSP
3388	`0`, // HI32DSP:sub_32
3389	`0`, // HI32DSP:sub_64
3390	`0`, // HI32DSP:sub_dsp16_19
3391	`0`, // HI32DSP:sub_dsp20
3392	`0`, // HI32DSP:sub_dsp21
3393	`0`, // HI32DSP:sub_dsp22
3394	`0`, // HI32DSP:sub_dsp23
3395	`0`, // HI32DSP:sub_hi
3396	`0`, // HI32DSP:sub_lo
3397	`0`, // HI32DSP:sub_hi_then_sub_32
3398	`0`, // HI32DSP:sub_32_sub_hi_then_sub_32
3399	},
3400	{ // LO32DSP
3401	`0`, // LO32DSP:sub_32
3402	`0`, // LO32DSP:sub_64
3403	`0`, // LO32DSP:sub_dsp16_19
3404	`0`, // LO32DSP:sub_dsp20
3405	`0`, // LO32DSP:sub_dsp21
3406	`0`, // LO32DSP:sub_dsp22
3407	`0`, // LO32DSP:sub_dsp23
3408	`0`, // LO32DSP:sub_hi
3409	`0`, // LO32DSP:sub_lo
3410	`0`, // LO32DSP:sub_hi_then_sub_32
3411	`0`, // LO32DSP:sub_32_sub_hi_then_sub_32
3412	},
3413	{ // CPU16Regs_and_GPRMM16MovePPairSecond
3414	`0`, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32
3415	`0`, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_64
3416	`0`, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19
3417	`0`, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20
3418	`0`, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21
3419	`0`, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22
3420	`0`, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23
3421	`0`, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi
3422	`0`, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo
3423	`0`, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
3424	`0`, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
3425	},
3426	{ // GPRMM16MovePPairFirst
3427	`0`, // GPRMM16MovePPairFirst:sub_32
3428	`0`, // GPRMM16MovePPairFirst:sub_64
3429	`0`, // GPRMM16MovePPairFirst:sub_dsp16_19
3430	`0`, // GPRMM16MovePPairFirst:sub_dsp20
3431	`0`, // GPRMM16MovePPairFirst:sub_dsp21
3432	`0`, // GPRMM16MovePPairFirst:sub_dsp22
3433	`0`, // GPRMM16MovePPairFirst:sub_dsp23
3434	`0`, // GPRMM16MovePPairFirst:sub_hi
3435	`0`, // GPRMM16MovePPairFirst:sub_lo
3436	`0`, // GPRMM16MovePPairFirst:sub_hi_then_sub_32
3437	`0`, // GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32
3438	},
3439	{ // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
3440	`0`, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32
3441	`0`, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64
3442	`0`, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
3443	`0`, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20
3444	`0`, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21
3445	`0`, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22
3446	`0`, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23
3447	`0`, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi
3448	`0`, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo
3449	`0`, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
3450	`0`, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
3451	},
3452	{ // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
3453	`0`, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32
3454	`0`, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64
3455	`0`, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19
3456	`0`, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20
3457	`0`, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21
3458	`0`, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22
3459	`0`, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23
3460	`0`, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi
3461	`0`, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo
3462	`0`, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
3463	`0`, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
3464	},
3465	{ // CPURAReg
3466	`0`, // CPURAReg:sub_32
3467	`0`, // CPURAReg:sub_64
3468	`0`, // CPURAReg:sub_dsp16_19
3469	`0`, // CPURAReg:sub_dsp20
3470	`0`, // CPURAReg:sub_dsp21
3471	`0`, // CPURAReg:sub_dsp22
3472	`0`, // CPURAReg:sub_dsp23
3473	`0`, // CPURAReg:sub_hi
3474	`0`, // CPURAReg:sub_lo
3475	`0`, // CPURAReg:sub_hi_then_sub_32
3476	`0`, // CPURAReg:sub_32_sub_hi_then_sub_32
3477	},
3478	{ // CPUSPReg
3479	`0`, // CPUSPReg:sub_32
3480	`0`, // CPUSPReg:sub_64
3481	`0`, // CPUSPReg:sub_dsp16_19
3482	`0`, // CPUSPReg:sub_dsp20
3483	`0`, // CPUSPReg:sub_dsp21
3484	`0`, // CPUSPReg:sub_dsp22
3485	`0`, // CPUSPReg:sub_dsp23
3486	`0`, // CPUSPReg:sub_hi
3487	`0`, // CPUSPReg:sub_lo
3488	`0`, // CPUSPReg:sub_hi_then_sub_32
3489	`0`, // CPUSPReg:sub_32_sub_hi_then_sub_32
3490	},
3491	{ // DSPCC
3492	`0`, // DSPCC:sub_32
3493	`0`, // DSPCC:sub_64
3494	`0`, // DSPCC:sub_dsp16_19
3495	`0`, // DSPCC:sub_dsp20
3496	`0`, // DSPCC:sub_dsp21
3497	`0`, // DSPCC:sub_dsp22
3498	`0`, // DSPCC:sub_dsp23
3499	`0`, // DSPCC:sub_hi
3500	`0`, // DSPCC:sub_lo
3501	`0`, // DSPCC:sub_hi_then_sub_32
3502	`0`, // DSPCC:sub_32_sub_hi_then_sub_32
3503	},
3504	{ // GP32
3505	`0`, // GP32:sub_32
3506	`0`, // GP32:sub_64
3507	`0`, // GP32:sub_dsp16_19
3508	`0`, // GP32:sub_dsp20
3509	`0`, // GP32:sub_dsp21
3510	`0`, // GP32:sub_dsp22
3511	`0`, // GP32:sub_dsp23
3512	`0`, // GP32:sub_hi
3513	`0`, // GP32:sub_lo
3514	`0`, // GP32:sub_hi_then_sub_32
3515	`0`, // GP32:sub_32_sub_hi_then_sub_32
3516	},
3517	{ // GPR32ZERO
3518	`0`, // GPR32ZERO:sub_32
3519	`0`, // GPR32ZERO:sub_64
3520	`0`, // GPR32ZERO:sub_dsp16_19
3521	`0`, // GPR32ZERO:sub_dsp20
3522	`0`, // GPR32ZERO:sub_dsp21
3523	`0`, // GPR32ZERO:sub_dsp22
3524	`0`, // GPR32ZERO:sub_dsp23
3525	`0`, // GPR32ZERO:sub_hi
3526	`0`, // GPR32ZERO:sub_lo
3527	`0`, // GPR32ZERO:sub_hi_then_sub_32
3528	`0`, // GPR32ZERO:sub_32_sub_hi_then_sub_32
3529	},
3530	{ // HI32
3531	`0`, // HI32:sub_32
3532	`0`, // HI32:sub_64
3533	`0`, // HI32:sub_dsp16_19
3534	`0`, // HI32:sub_dsp20
3535	`0`, // HI32:sub_dsp21
3536	`0`, // HI32:sub_dsp22
3537	`0`, // HI32:sub_dsp23
3538	`0`, // HI32:sub_hi
3539	`0`, // HI32:sub_lo
3540	`0`, // HI32:sub_hi_then_sub_32
3541	`0`, // HI32:sub_32_sub_hi_then_sub_32
3542	},
3543	{ // LO32
3544	`0`, // LO32:sub_32
3545	`0`, // LO32:sub_64
3546	`0`, // LO32:sub_dsp16_19
3547	`0`, // LO32:sub_dsp20
3548	`0`, // LO32:sub_dsp21
3549	`0`, // LO32:sub_dsp22
3550	`0`, // LO32:sub_dsp23
3551	`0`, // LO32:sub_hi
3552	`0`, // LO32:sub_lo
3553	`0`, // LO32:sub_hi_then_sub_32
3554	`0`, // LO32:sub_32_sub_hi_then_sub_32
3555	},
3556	{ // SP32
3557	`0`, // SP32:sub_32
3558	`0`, // SP32:sub_64
3559	`0`, // SP32:sub_dsp16_19
3560	`0`, // SP32:sub_dsp20
3561	`0`, // SP32:sub_dsp21
3562	`0`, // SP32:sub_dsp22
3563	`0`, // SP32:sub_dsp23
3564	`0`, // SP32:sub_hi
3565	`0`, // SP32:sub_lo
3566	`0`, // SP32:sub_hi_then_sub_32
3567	`0`, // SP32:sub_32_sub_hi_then_sub_32
3568	},
3569	{ // FGR64CC
3570	`0`, // FGR64CC:sub_32
3571	`0`, // FGR64CC:sub_64
3572	`0`, // FGR64CC:sub_dsp16_19
3573	`0`, // FGR64CC:sub_dsp20
3574	`0`, // FGR64CC:sub_dsp21
3575	`0`, // FGR64CC:sub_dsp22
3576	`0`, // FGR64CC:sub_dsp23
3577	`0`, // FGR64CC:sub_hi
3578	`7`, // FGR64CC:sub_lo -> FGR32
3579	`0`, // FGR64CC:sub_hi_then_sub_32
3580	`0`, // FGR64CC:sub_32_sub_hi_then_sub_32
3581	},
3582	{ // FGR64
3583	`0`, // FGR64:sub_32
3584	`0`, // FGR64:sub_64
3585	`0`, // FGR64:sub_dsp16_19
3586	`0`, // FGR64:sub_dsp20
3587	`0`, // FGR64:sub_dsp21
3588	`0`, // FGR64:sub_dsp22
3589	`0`, // FGR64:sub_dsp23
3590	`0`, // FGR64:sub_hi
3591	`7`, // FGR64:sub_lo -> FGR32
3592	`0`, // FGR64:sub_hi_then_sub_32
3593	`0`, // FGR64:sub_32_sub_hi_then_sub_32
3594	},
3595	{ // GPR64
3596	`6`, // GPR64:sub_32 -> DSPR
3597	`0`, // GPR64:sub_64
3598	`0`, // GPR64:sub_dsp16_19
3599	`0`, // GPR64:sub_dsp20
3600	`0`, // GPR64:sub_dsp21
3601	`0`, // GPR64:sub_dsp22
3602	`0`, // GPR64:sub_dsp23
3603	`0`, // GPR64:sub_hi
3604	`0`, // GPR64:sub_lo
3605	`0`, // GPR64:sub_hi_then_sub_32
3606	`0`, // GPR64:sub_32_sub_hi_then_sub_32
3607	},
3608	{ // GPR64_with_sub_32_in_GPR32NONZERO
3609	`12`, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32 -> GPR32NONZERO
3610	`0`, // GPR64_with_sub_32_in_GPR32NONZERO:sub_64
3611	`0`, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp16_19
3612	`0`, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp20
3613	`0`, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp21
3614	`0`, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp22
3615	`0`, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp23
3616	`0`, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi
3617	`0`, // GPR64_with_sub_32_in_GPR32NONZERO:sub_lo
3618	`0`, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi_then_sub_32
3619	`0`, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32_sub_hi_then_sub_32
3620	},
3621	{ // AFGR64
3622	`0`, // AFGR64:sub_32
3623	`0`, // AFGR64:sub_64
3624	`0`, // AFGR64:sub_dsp16_19
3625	`0`, // AFGR64:sub_dsp20
3626	`0`, // AFGR64:sub_dsp21
3627	`0`, // AFGR64:sub_dsp22
3628	`0`, // AFGR64:sub_dsp23
3629	`8`, // AFGR64:sub_hi -> FGR32CC
3630	`8`, // AFGR64:sub_lo -> FGR32CC
3631	`0`, // AFGR64:sub_hi_then_sub_32
3632	`0`, // AFGR64:sub_32_sub_hi_then_sub_32
3633	},
3634	{ // GPR64_with_sub_32_in_CPU16RegsPlusSP
3635	`13`, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32 -> CPU16RegsPlusSP
3636	`0`, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_64
3637	`0`, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp16_19
3638	`0`, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp20
3639	`0`, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp21
3640	`0`, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp22
3641	`0`, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp23
3642	`0`, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi
3643	`0`, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_lo
3644	`0`, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi_then_sub_32
3645	`0`, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32
3646	},
3647	{ // GPR64_with_sub_32_in_CPU16Regs
3648	`14`, // GPR64_with_sub_32_in_CPU16Regs:sub_32 -> CPU16Regs
3649	`0`, // GPR64_with_sub_32_in_CPU16Regs:sub_64
3650	`0`, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp16_19
3651	`0`, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp20
3652	`0`, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp21
3653	`0`, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp22
3654	`0`, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp23
3655	`0`, // GPR64_with_sub_32_in_CPU16Regs:sub_hi
3656	`0`, // GPR64_with_sub_32_in_CPU16Regs:sub_lo
3657	`0`, // GPR64_with_sub_32_in_CPU16Regs:sub_hi_then_sub_32
3658	`0`, // GPR64_with_sub_32_in_CPU16Regs:sub_32_sub_hi_then_sub_32
3659	},
3660	{ // GPR64_with_sub_32_in_GPRMM16MoveP
3661	`17`, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32 -> GPRMM16MoveP
3662	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_64
3663	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp16_19
3664	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp20
3665	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp21
3666	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp22
3667	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp23
3668	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi
3669	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_lo
3670	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi_then_sub_32
3671	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
3672	},
3673	{ // GPR64_with_sub_32_in_GPRMM16Zero
3674	`18`, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32 -> GPRMM16Zero
3675	`0`, // GPR64_with_sub_32_in_GPRMM16Zero:sub_64
3676	`0`, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp16_19
3677	`0`, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp20
3678	`0`, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp21
3679	`0`, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp22
3680	`0`, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp23
3681	`0`, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi
3682	`0`, // GPR64_with_sub_32_in_GPRMM16Zero:sub_lo
3683	`0`, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi_then_sub_32
3684	`0`, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32_sub_hi_then_sub_32
3685	},
3686	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
3687	`19`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32 -> CPU16Regs_and_GPRMM16Zero
3688	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_64
3689	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
3690	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp20
3691	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp21
3692	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp22
3693	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp23
3694	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi
3695	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_lo
3696	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
3697	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
3698	},
3699	{ // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
3700	`20`, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32 -> GPR32NONZERO_and_GPRMM16MoveP
3701	`0`, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_64
3702	`0`, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19
3703	`0`, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20
3704	`0`, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21
3705	`0`, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22
3706	`0`, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23
3707	`0`, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi
3708	`0`, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_lo
3709	`0`, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32
3710	`0`, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
3711	},
3712	{ // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
3713	`21`, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairSecond
3714	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_64
3715	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp16_19
3716	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp20
3717	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp21
3718	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp22
3719	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp23
3720	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi
3721	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_lo
3722	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi_then_sub_32
3723	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
3724	},
3725	{ // ACC64DSP
3726	`0`, // ACC64DSP:sub_32
3727	`0`, // ACC64DSP:sub_64
3728	`0`, // ACC64DSP:sub_dsp16_19
3729	`0`, // ACC64DSP:sub_dsp20
3730	`0`, // ACC64DSP:sub_dsp21
3731	`0`, // ACC64DSP:sub_dsp22
3732	`0`, // ACC64DSP:sub_dsp23
3733	`24`, // ACC64DSP:sub_hi -> HI32DSP
3734	`25`, // ACC64DSP:sub_lo -> LO32DSP
3735	`0`, // ACC64DSP:sub_hi_then_sub_32
3736	`0`, // ACC64DSP:sub_32_sub_hi_then_sub_32
3737	},
3738	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
3739	`22`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32 -> CPU16Regs_and_GPRMM16MoveP
3740	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_64
3741	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19
3742	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp20
3743	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp21
3744	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp22
3745	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp23
3746	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi
3747	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_lo
3748	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32
3749	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
3750	},
3751	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
3752	`23`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_GPRMM16Zero
3753	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_64
3754	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19
3755	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20
3756	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21
3757	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22
3758	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23
3759	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi
3760	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_lo
3761	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32
3762	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
3763	},
3764	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
3765	`26`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32 -> CPU16Regs_and_GPRMM16MovePPairSecond
3766	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_64
3767	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19
3768	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20
3769	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21
3770	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22
3771	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23
3772	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi
3773	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo
3774	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
3775	`0`, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
3776	},
3777	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
3778	`27`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32 -> GPRMM16MovePPairFirst
3779	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_64
3780	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp16_19
3781	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp20
3782	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp21
3783	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp22
3784	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp23
3785	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi
3786	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_lo
3787	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi_then_sub_32
3788	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32
3789	},
3790	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
3791	`28`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
3792	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64
3793	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
3794	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20
3795	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21
3796	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22
3797	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23
3798	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi
3799	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo
3800	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
3801	`0`, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
3802	},
3803	{ // OCTEON_MPL
3804	`0`, // OCTEON_MPL:sub_32
3805	`0`, // OCTEON_MPL:sub_64
3806	`0`, // OCTEON_MPL:sub_dsp16_19
3807	`0`, // OCTEON_MPL:sub_dsp20
3808	`0`, // OCTEON_MPL:sub_dsp21
3809	`0`, // OCTEON_MPL:sub_dsp22
3810	`0`, // OCTEON_MPL:sub_dsp23
3811	`0`, // OCTEON_MPL:sub_hi
3812	`0`, // OCTEON_MPL:sub_lo
3813	`0`, // OCTEON_MPL:sub_hi_then_sub_32
3814	`0`, // OCTEON_MPL:sub_32_sub_hi_then_sub_32
3815	},
3816	{ // OCTEON_P
3817	`0`, // OCTEON_P:sub_32
3818	`0`, // OCTEON_P:sub_64
3819	`0`, // OCTEON_P:sub_dsp16_19
3820	`0`, // OCTEON_P:sub_dsp20
3821	`0`, // OCTEON_P:sub_dsp21
3822	`0`, // OCTEON_P:sub_dsp22
3823	`0`, // OCTEON_P:sub_dsp23
3824	`0`, // OCTEON_P:sub_hi
3825	`0`, // OCTEON_P:sub_lo
3826	`0`, // OCTEON_P:sub_hi_then_sub_32
3827	`0`, // OCTEON_P:sub_32_sub_hi_then_sub_32
3828	},
3829	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
3830	`29`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
3831	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64
3832	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19
3833	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20
3834	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21
3835	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22
3836	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23
3837	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi
3838	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo
3839	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
3840	`0`, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
3841	},
3842	{ // ACC64
3843	`0`, // ACC64:sub_32
3844	`0`, // ACC64:sub_64
3845	`0`, // ACC64:sub_dsp16_19
3846	`0`, // ACC64:sub_dsp20
3847	`0`, // ACC64:sub_dsp21
3848	`0`, // ACC64:sub_dsp22
3849	`0`, // ACC64:sub_dsp23
3850	`35`, // ACC64:sub_hi -> HI32
3851	`36`, // ACC64:sub_lo -> LO32
3852	`0`, // ACC64:sub_hi_then_sub_32
3853	`0`, // ACC64:sub_32_sub_hi_then_sub_32
3854	},
3855	{ // GP64
3856	`33`, // GP64:sub_32 -> GP32
3857	`0`, // GP64:sub_64
3858	`0`, // GP64:sub_dsp16_19
3859	`0`, // GP64:sub_dsp20
3860	`0`, // GP64:sub_dsp21
3861	`0`, // GP64:sub_dsp22
3862	`0`, // GP64:sub_dsp23
3863	`0`, // GP64:sub_hi
3864	`0`, // GP64:sub_lo
3865	`0`, // GP64:sub_hi_then_sub_32
3866	`0`, // GP64:sub_32_sub_hi_then_sub_32
3867	},
3868	{ // GPR64_with_sub_32_in_CPURAReg
3869	`30`, // GPR64_with_sub_32_in_CPURAReg:sub_32 -> CPURAReg
3870	`0`, // GPR64_with_sub_32_in_CPURAReg:sub_64
3871	`0`, // GPR64_with_sub_32_in_CPURAReg:sub_dsp16_19
3872	`0`, // GPR64_with_sub_32_in_CPURAReg:sub_dsp20
3873	`0`, // GPR64_with_sub_32_in_CPURAReg:sub_dsp21
3874	`0`, // GPR64_with_sub_32_in_CPURAReg:sub_dsp22
3875	`0`, // GPR64_with_sub_32_in_CPURAReg:sub_dsp23
3876	`0`, // GPR64_with_sub_32_in_CPURAReg:sub_hi
3877	`0`, // GPR64_with_sub_32_in_CPURAReg:sub_lo
3878	`0`, // GPR64_with_sub_32_in_CPURAReg:sub_hi_then_sub_32
3879	`0`, // GPR64_with_sub_32_in_CPURAReg:sub_32_sub_hi_then_sub_32
3880	},
3881	{ // GPR64_with_sub_32_in_GPR32ZERO
3882	`34`, // GPR64_with_sub_32_in_GPR32ZERO:sub_32 -> GPR32ZERO
3883	`0`, // GPR64_with_sub_32_in_GPR32ZERO:sub_64
3884	`0`, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp16_19
3885	`0`, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp20
3886	`0`, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp21
3887	`0`, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp22
3888	`0`, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp23
3889	`0`, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi
3890	`0`, // GPR64_with_sub_32_in_GPR32ZERO:sub_lo
3891	`0`, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi_then_sub_32
3892	`0`, // GPR64_with_sub_32_in_GPR32ZERO:sub_32_sub_hi_then_sub_32
3893	},
3894	{ // HI64
3895	`35`, // HI64:sub_32 -> HI32
3896	`0`, // HI64:sub_64
3897	`0`, // HI64:sub_dsp16_19
3898	`0`, // HI64:sub_dsp20
3899	`0`, // HI64:sub_dsp21
3900	`0`, // HI64:sub_dsp22
3901	`0`, // HI64:sub_dsp23
3902	`0`, // HI64:sub_hi
3903	`0`, // HI64:sub_lo
3904	`0`, // HI64:sub_hi_then_sub_32
3905	`0`, // HI64:sub_32_sub_hi_then_sub_32
3906	},
3907	{ // LO64
3908	`36`, // LO64:sub_32 -> LO32
3909	`0`, // LO64:sub_64
3910	`0`, // LO64:sub_dsp16_19
3911	`0`, // LO64:sub_dsp20
3912	`0`, // LO64:sub_dsp21
3913	`0`, // LO64:sub_dsp22
3914	`0`, // LO64:sub_dsp23
3915	`0`, // LO64:sub_hi
3916	`0`, // LO64:sub_lo
3917	`0`, // LO64:sub_hi_then_sub_32
3918	`0`, // LO64:sub_32_sub_hi_then_sub_32
3919	},
3920	{ // SP64
3921	`31`, // SP64:sub_32 -> CPUSPReg
3922	`0`, // SP64:sub_64
3923	`0`, // SP64:sub_dsp16_19
3924	`0`, // SP64:sub_dsp20
3925	`0`, // SP64:sub_dsp21
3926	`0`, // SP64:sub_dsp22
3927	`0`, // SP64:sub_dsp23
3928	`0`, // SP64:sub_hi
3929	`0`, // SP64:sub_lo
3930	`0`, // SP64:sub_hi_then_sub_32
3931	`0`, // SP64:sub_32_sub_hi_then_sub_32
3932	},
3933	{ // MSA128B
3934	`0`, // MSA128B:sub_32
3935	`38`, // MSA128B:sub_64 -> FGR64CC
3936	`0`, // MSA128B:sub_dsp16_19
3937	`0`, // MSA128B:sub_dsp20
3938	`0`, // MSA128B:sub_dsp21
3939	`0`, // MSA128B:sub_dsp22
3940	`0`, // MSA128B:sub_dsp23
3941	`0`, // MSA128B:sub_hi
3942	`7`, // MSA128B:sub_lo -> FGR32
3943	`0`, // MSA128B:sub_hi_then_sub_32
3944	`0`, // MSA128B:sub_32_sub_hi_then_sub_32
3945	},
3946	{ // MSA128D
3947	`0`, // MSA128D:sub_32
3948	`38`, // MSA128D:sub_64 -> FGR64CC
3949	`0`, // MSA128D:sub_dsp16_19
3950	`0`, // MSA128D:sub_dsp20
3951	`0`, // MSA128D:sub_dsp21
3952	`0`, // MSA128D:sub_dsp22
3953	`0`, // MSA128D:sub_dsp23
3954	`0`, // MSA128D:sub_hi
3955	`7`, // MSA128D:sub_lo -> FGR32
3956	`0`, // MSA128D:sub_hi_then_sub_32
3957	`0`, // MSA128D:sub_32_sub_hi_then_sub_32
3958	},
3959	{ // MSA128H
3960	`0`, // MSA128H:sub_32
3961	`38`, // MSA128H:sub_64 -> FGR64CC
3962	`0`, // MSA128H:sub_dsp16_19
3963	`0`, // MSA128H:sub_dsp20
3964	`0`, // MSA128H:sub_dsp21
3965	`0`, // MSA128H:sub_dsp22
3966	`0`, // MSA128H:sub_dsp23
3967	`0`, // MSA128H:sub_hi
3968	`7`, // MSA128H:sub_lo -> FGR32
3969	`0`, // MSA128H:sub_hi_then_sub_32
3970	`0`, // MSA128H:sub_32_sub_hi_then_sub_32
3971	},
3972	{ // MSA128W
3973	`0`, // MSA128W:sub_32
3974	`38`, // MSA128W:sub_64 -> FGR64CC
3975	`0`, // MSA128W:sub_dsp16_19
3976	`0`, // MSA128W:sub_dsp20
3977	`0`, // MSA128W:sub_dsp21
3978	`0`, // MSA128W:sub_dsp22
3979	`0`, // MSA128W:sub_dsp23
3980	`0`, // MSA128W:sub_hi
3981	`7`, // MSA128W:sub_lo -> FGR32
3982	`0`, // MSA128W:sub_hi_then_sub_32
3983	`0`, // MSA128W:sub_32_sub_hi_then_sub_32
3984	},
3985	{ // MSA128WEvens
3986	`0`, // MSA128WEvens:sub_32
3987	`39`, // MSA128WEvens:sub_64 -> FGR64
3988	`0`, // MSA128WEvens:sub_dsp16_19
3989	`0`, // MSA128WEvens:sub_dsp20
3990	`0`, // MSA128WEvens:sub_dsp21
3991	`0`, // MSA128WEvens:sub_dsp22
3992	`0`, // MSA128WEvens:sub_dsp23
3993	`0`, // MSA128WEvens:sub_hi
3994	`8`, // MSA128WEvens:sub_lo -> FGR32CC
3995	`0`, // MSA128WEvens:sub_hi_then_sub_32
3996	`0`, // MSA128WEvens:sub_32_sub_hi_then_sub_32
3997	},
3998	{ // ACC128
3999	`36`, // ACC128:sub_32 -> LO32
4000	`0`, // ACC128:sub_64
4001	`0`, // ACC128:sub_dsp16_19
4002	`0`, // ACC128:sub_dsp20
4003	`0`, // ACC128:sub_dsp21
4004	`0`, // ACC128:sub_dsp22
4005	`0`, // ACC128:sub_dsp23
4006	`63`, // ACC128:sub_hi -> HI64
4007	`64`, // ACC128:sub_lo -> LO64
4008	`35`, // ACC128:sub_hi_then_sub_32 -> HI32
4009	`59`, // ACC128:sub_32_sub_hi_then_sub_32 -> ACC64
4010	},
4011
4012	};
4013	assert(RC && "Missing regclass");
4014	if (!Idx) return RC;
4015	--Idx;
4016	assert(Idx < `11` && "Bad subreg");
4017	unsigned TV = Table[RC->getID()][Idx];
4018	return TV ? getRegClass(i: TV - `1`) : nullptr;
4019	}/// Get the weight in units of pressure for this register class.
4020	const RegClassWeight &MipsGenRegisterInfo::
4021	getRegClassWeight(const TargetRegisterClass RC) const* {
4022	static const RegClassWeight RCWeightTable[] = {
4023	{.RegWeight: `2`, .WeightLimit: `64`}, // MSA128F16
4024	{.RegWeight: `0`, .WeightLimit: `0`}, // CCR
4025	{.RegWeight: `0`, .WeightLimit: `0`}, // COP0
4026	{.RegWeight: `0`, .WeightLimit: `0`}, // COP2
4027	{.RegWeight: `0`, .WeightLimit: `0`}, // COP3
4028	{.RegWeight: `1`, .WeightLimit: `32`}, // DSPR
4029	{.RegWeight: `1`, .WeightLimit: `32`}, // FGR32
4030	{.RegWeight: `1`, .WeightLimit: `32`}, // FGR32CC
4031	{.RegWeight: `1`, .WeightLimit: `32`}, // GPR32
4032	{.RegWeight: `0`, .WeightLimit: `0`}, // HWRegs
4033	{.RegWeight: `0`, .WeightLimit: `0`}, // MSACtrl
4034	{.RegWeight: `1`, .WeightLimit: `31`}, // GPR32NONZERO
4035	{.RegWeight: `1`, .WeightLimit: `9`}, // CPU16RegsPlusSP
4036	{.RegWeight: `1`, .WeightLimit: `8`}, // CPU16Regs
4037	{.RegWeight: `0`, .WeightLimit: `0`}, // FCC
4038	{.RegWeight: `1`, .WeightLimit: `8`}, // GPRMM16
4039	{.RegWeight: `1`, .WeightLimit: `8`}, // GPRMM16MoveP
4040	{.RegWeight: `1`, .WeightLimit: `8`}, // GPRMM16Zero
4041	{.RegWeight: `1`, .WeightLimit: `7`}, // CPU16Regs_and_GPRMM16Zero
4042	{.RegWeight: `1`, .WeightLimit: `7`}, // GPR32NONZERO_and_GPRMM16MoveP
4043	{.RegWeight: `1`, .WeightLimit: `5`}, // GPRMM16MovePPairSecond
4044	{.RegWeight: `1`, .WeightLimit: `4`}, // CPU16Regs_and_GPRMM16MoveP
4045	{.RegWeight: `1`, .WeightLimit: `4`}, // GPRMM16MoveP_and_GPRMM16Zero
4046	{.RegWeight: `1`, .WeightLimit: `4`}, // HI32DSP
4047	{.RegWeight: `1`, .WeightLimit: `4`}, // LO32DSP
4048	{.RegWeight: `1`, .WeightLimit: `3`}, // CPU16Regs_and_GPRMM16MovePPairSecond
4049	{.RegWeight: `1`, .WeightLimit: `3`}, // GPRMM16MovePPairFirst
4050	{.RegWeight: `1`, .WeightLimit: `3`}, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
4051	{.RegWeight: `1`, .WeightLimit: `2`}, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
4052	{.RegWeight: `1`, .WeightLimit: `1`}, // CPURAReg
4053	{.RegWeight: `1`, .WeightLimit: `1`}, // CPUSPReg
4054	{.RegWeight: `1`, .WeightLimit: `1`}, // DSPCC
4055	{.RegWeight: `1`, .WeightLimit: `1`}, // GP32
4056	{.RegWeight: `1`, .WeightLimit: `1`}, // GPR32ZERO
4057	{.RegWeight: `1`, .WeightLimit: `1`}, // HI32
4058	{.RegWeight: `1`, .WeightLimit: `1`}, // LO32
4059	{.RegWeight: `1`, .WeightLimit: `1`}, // SP32
4060	{.RegWeight: `2`, .WeightLimit: `64`}, // FGR64CC
4061	{.RegWeight: `2`, .WeightLimit: `64`}, // FGR64
4062	{.RegWeight: `1`, .WeightLimit: `32`}, // GPR64
4063	{.RegWeight: `1`, .WeightLimit: `31`}, // GPR64_with_sub_32_in_GPR32NONZERO
4064	{.RegWeight: `2`, .WeightLimit: `32`}, // AFGR64
4065	{.RegWeight: `1`, .WeightLimit: `9`}, // GPR64_with_sub_32_in_CPU16RegsPlusSP
4066	{.RegWeight: `1`, .WeightLimit: `8`}, // GPR64_with_sub_32_in_CPU16Regs
4067	{.RegWeight: `1`, .WeightLimit: `8`}, // GPR64_with_sub_32_in_GPRMM16MoveP
4068	{.RegWeight: `1`, .WeightLimit: `8`}, // GPR64_with_sub_32_in_GPRMM16Zero
4069	{.RegWeight: `1`, .WeightLimit: `7`}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
4070	{.RegWeight: `1`, .WeightLimit: `7`}, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
4071	{.RegWeight: `1`, .WeightLimit: `5`}, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
4072	{.RegWeight: `2`, .WeightLimit: `8`}, // ACC64DSP
4073	{.RegWeight: `1`, .WeightLimit: `4`}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
4074	{.RegWeight: `1`, .WeightLimit: `4`}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
4075	{.RegWeight: `1`, .WeightLimit: `3`}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
4076	{.RegWeight: `1`, .WeightLimit: `3`}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
4077	{.RegWeight: `1`, .WeightLimit: `3`}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
4078	{.RegWeight: `0`, .WeightLimit: `0`}, // OCTEON_MPL
4079	{.RegWeight: `0`, .WeightLimit: `0`}, // OCTEON_P
4080	{.RegWeight: `1`, .WeightLimit: `2`}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
4081	{.RegWeight: `2`, .WeightLimit: `2`}, // ACC64
4082	{.RegWeight: `1`, .WeightLimit: `1`}, // GP64
4083	{.RegWeight: `1`, .WeightLimit: `1`}, // GPR64_with_sub_32_in_CPURAReg
4084	{.RegWeight: `1`, .WeightLimit: `1`}, // GPR64_with_sub_32_in_GPR32ZERO
4085	{.RegWeight: `1`, .WeightLimit: `1`}, // HI64
4086	{.RegWeight: `1`, .WeightLimit: `1`}, // LO64
4087	{.RegWeight: `1`, .WeightLimit: `1`}, // SP64
4088	{.RegWeight: `2`, .WeightLimit: `64`}, // MSA128B
4089	{.RegWeight: `2`, .WeightLimit: `64`}, // MSA128D
4090	{.RegWeight: `2`, .WeightLimit: `64`}, // MSA128H
4091	{.RegWeight: `2`, .WeightLimit: `64`}, // MSA128W
4092	{.RegWeight: `2`, .WeightLimit: `32`}, // MSA128WEvens
4093	{.RegWeight: `2`, .WeightLimit: `2`}, // ACC128
4094	};
4095	return RCWeightTable[RC->getID()];
4096	}
4097
4098	/// Get the weight in units of pressure for this register unit.
4099	unsigned MipsGenRegisterInfo::
4100	getRegUnitWeight(MCRegUnit RegUnit) const {
4101	assert(static_cast<unsigned>(RegUnit) < `321` && "invalid register unit");
4102	// All register units have unit weight.
4103	return `1`;
4104	}
4105
4106
4107	// Get the number of dimensions of register pressure.
4108	unsigned MipsGenRegisterInfo::getNumRegPressureSets() const {
4109	return `20`;
4110	}
4111
4112	// Get the name of this register unit pressure set.
4113	const char *MipsGenRegisterInfo::
4114	getRegPressureSetName(unsigned Idx) const {
4115	static const char *PressureNameTable[] = {
4116	"DSPCC",
4117	"GPR32ZERO",
4118	"GPR64_with_sub_32_in_CPURAReg",
4119	"HI32",
4120	"GPRMM16MovePPairFirst",
4121	"CPU16Regs_and_GPRMM16MoveP",
4122	"HI32DSP",
4123	"LO32DSP",
4124	"GPRMM16MovePPairSecond",
4125	"GPRMM16MoveP",
4126	"ACC64DSP",
4127	"CPU16Regs",
4128	"GPRMM16Zero_with_GPRMM16MovePPairSecond",
4129	"CPU16Regs_with_GPRMM16MovePPairSecond",
4130	"CPU16Regs_with_GPRMM16MoveP",
4131	"DSPR",
4132	"FGR32",
4133	"MSA128WEvens",
4134	"FGR32_with_MSA128WEvens",
4135	"MSA128F16",
4136	};
4137	return PressureNameTable[Idx];
4138	}
4139
4140	// Get the register unit pressure limit for this dimension.
4141	// This limit must be adjusted dynamically for reserved registers.
4142	unsigned MipsGenRegisterInfo::
4143	getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
4144	static const uint8_t PressureLimitTable[] = {
4145	`1`, // 0: DSPCC
4146	`1`, // 1: GPR32ZERO
4147	`1`, // 2: GPR64_with_sub_32_in_CPURAReg
4148	`2`, // 3: HI32
4149	`3`, // 4: GPRMM16MovePPairFirst
4150	`5`, // 5: CPU16Regs_and_GPRMM16MoveP
4151	`5`, // 6: HI32DSP
4152	`5`, // 7: LO32DSP
4153	`6`, // 8: GPRMM16MovePPairSecond
4154	`8`, // 9: GPRMM16MoveP
4155	`8`, // 10: ACC64DSP
4156	`10`, // 11: CPU16Regs
4157	`10`, // 12: GPRMM16Zero_with_GPRMM16MovePPairSecond
4158	`11`, // 13: CPU16Regs_with_GPRMM16MovePPairSecond
4159	`13`, // 14: CPU16Regs_with_GPRMM16MoveP
4160	`32`, // 15: DSPR
4161	`32`, // 16: FGR32
4162	`32`, // 17: MSA128WEvens
4163	`48`, // 18: FGR32_with_MSA128WEvens
4164	`64`, // 19: MSA128F16
4165	};
4166	return PressureLimitTable[Idx];
4167	}
4168
4169	/// Table of pressure sets per register class or unit.
4170	static const int RCSetsTable[] = {
4171	/ 0 / `0`, -`1`,
4172	/ 2 / `6`, `10`, -`1`,
4173	/ 5 / `3`, `6`, `7`, `10`, -`1`,
4174	/ 10 / `2`, `15`, -`1`,
4175	/ 13 / `8`, `12`, `13`, `15`, -`1`,
4176	/ 18 / `9`, `14`, `15`, -`1`,
4177	/ 22 / `1`, `5`, `9`, `11`, `12`, `14`, `15`, -`1`,
4178	/ 30 / `5`, `9`, `11`, `13`, `14`, `15`, -`1`,
4179	/ 37 / `4`, `8`, `11`, `12`, `13`, `14`, `15`, -`1`,
4180	/ 45 / `5`, `9`, `11`, `12`, `13`, `14`, `15`, -`1`,
4181	/ 53 / `16`, `18`, `19`, -`1`,
4182	/ 57 / `16`, `17`, `18`, `19`, -`1`,
4183	};
4184
4185	/// Get the dimensions of register pressure impacted by this register class.
4186	/// Returns a -1 terminated array of pressure set IDs
4187	const int *MipsGenRegisterInfo::
4188	getRegClassPressureSets(const TargetRegisterClass RC) const* {
4189	static const uint8_t RCSetStartTable[] = {
4190	`55`,`1`,`1`,`1`,`1`,`11`,`53`,`53`,`11`,`1`,`1`,`11`,`32`,`32`,`1`,`32`,`18`,`25`,`39`,`18`,`13`,`30`,`23`,`2`,`7`,`38`,`37`,`45`,`37`,`1`,`1`,`0`,`1`,`22`,`5`,`5`,`1`,`55`,`55`,`11`,`11`,`53`,`32`,`32`,`18`,`25`,`39`,`18`,`13`,`3`,`30`,`23`,`38`,`37`,`45`,`1`,`1`,`37`,`5`,`1`,`10`,`22`,`5`,`5`,`1`,`55`,`55`,`55`,`55`,`58`,`5`,};
4191	return &RCSetsTable[RCSetStartTable[RC->getID()]];
4192	}
4193
4194	/// Get the dimensions of register pressure impacted by this register unit.
4195	/// Returns a -1 terminated array of pressure set IDs
4196	const int *MipsGenRegisterInfo::
4197	getRegUnitPressureSets(MCRegUnit RegUnit) const {
4198	assert(static_cast<unsigned>(RegUnit) < `321` && "invalid register unit");
4199	static const uint8_t RUSetStartTable[] = {
4200	`11`,`0`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`11`,`11`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`10`,`32`,`22`,`37`,`37`,`37`,`38`,`5`,`5`,`7`,`2`,`7`,`2`,`7`,`2`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`57`,`53`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`58`,`55`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`11`,`11`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`1`,`30`,`45`,`18`,`18`,`18`,`13`,`13`,`11`,`11`,`11`,`11`,`11`,`11`,`11`,`11`,`11`,`11`,`11`,`45`,`45`,};
4201	return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
4202	}
4203
4204	extern const MCRegisterDesc MipsRegDesc[];
4205	extern const int16_t MipsRegDiffLists[];
4206	extern const LaneBitmask MipsLaneMaskLists[];
4207	extern const char MipsRegStrings[];
4208	extern const char MipsRegClassStrings[];
4209	extern const MCPhysReg MipsRegUnitRoots[][`2`];
4210	extern const uint16_t MipsSubRegIdxLists[];
4211	extern const uint16_t MipsRegEncodingTable[];
4212	// Mips Dwarf<->LLVM register mappings.
4213	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[];
4214	extern const unsigned MipsDwarfFlavour0Dwarf2LSize;
4215
4216	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[];
4217	extern const unsigned MipsEHFlavour0Dwarf2LSize;
4218
4219	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[];
4220	extern const unsigned MipsDwarfFlavour0L2DwarfSize;
4221
4222	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[];
4223	extern const unsigned MipsEHFlavour0L2DwarfSize;
4224
4225
4226	MipsGenRegisterInfo::
4227	MipsGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
4228	unsigned PC, unsigned HwMode)
4229	: TargetRegisterInfo (&MipsRegInfoDesc, RegisterClasses, RegisterClasses+`71`,
4230	MipsSubRegIndexStrings, MipsSubRegIndexNameOffsets,
4231	SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
4232
4233	LaneBitmask (`0xFFFFFFFFFFFFFF80`), RegClassInfos, VTLists, HwMode) {
4234	InitMCRegisterInfo(D: MipsRegDesc, NR: `442`, RA, PC,
4235	C: MipsMCRegisterClasses, NC: `71`,
4236	RURoots: MipsRegUnitRoots,
4237	NRU: `321`,
4238	DL: MipsRegDiffLists,
4239	RUMS: MipsLaneMaskLists,
4240	Strings: MipsRegStrings,
4241	ClassStrings: MipsRegClassStrings,
4242	SubIndices: MipsSubRegIdxLists,
4243	NumIndices: `12`,
4244	RET: MipsRegEncodingTable,
4245	RUI: nullptr);
4246
4247	switch (DwarfFlavour) {
4248	default:
4249	llvm_unreachable("Unknown DWARF flavour");
4250	case `0`:
4251	mapDwarfRegsToLLVMRegs(Map: MipsDwarfFlavour0Dwarf2L, Size: MipsDwarfFlavour0Dwarf2LSize, isEH: false);
4252	break;
4253	}
4254	switch (EHFlavour) {
4255	default:
4256	llvm_unreachable("Unknown DWARF flavour");
4257	case `0`:
4258	mapDwarfRegsToLLVMRegs(Map: MipsEHFlavour0Dwarf2L, Size: MipsEHFlavour0Dwarf2LSize, isEH: true);
4259	break;
4260	}
4261	switch (DwarfFlavour) {
4262	default:
4263	llvm_unreachable("Unknown DWARF flavour");
4264	case `0`:
4265	mapLLVMRegsToDwarfRegs(Map: MipsDwarfFlavour0L2Dwarf, Size: MipsDwarfFlavour0L2DwarfSize, isEH: false);
4266	break;
4267	}
4268	switch (EHFlavour) {
4269	default:
4270	llvm_unreachable("Unknown DWARF flavour");
4271	case `0`:
4272	mapLLVMRegsToDwarfRegs(Map: MipsEHFlavour0L2Dwarf, Size: MipsEHFlavour0L2DwarfSize, isEH: true);
4273	break;
4274	}
4275	}
4276
4277	static const MCPhysReg CSR_Interrupt_32_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, Mips::LO0, Mips::HI0, `0` };
4278	static const uint32_t CSR_Interrupt_32_RegMask[] = { `0x07e80302`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x20000000`, `0x00000000`, `0x00000008`, `0x07ffbfc0`, `0x08000000`, `0x00000000`, `0x00000000`, };
4279	static const MCPhysReg CSR_Interrupt_32R6_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, `0` };
4280	static const uint32_t CSR_Interrupt_32R6_RegMask[] = { `0x03e80302`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x07ffbfc0`, `0x08000000`, `0x00000000`, `0x00000000`, };
4281	static const MCPhysReg CSR_Interrupt_64_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::V1_64, Mips::V0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, Mips::LO0_64, Mips::HI0_64, `0` };
4282	static const uint32_t CSR_Interrupt_64_RegMask[] = { `0x47e80302`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x08000000`, `0x30000000`, `0x00000000`, `0x00000008`, `0x07ffbfe0`, `0xf8000000`, `0x00000001`, `0x03ffffe4`, };
4283	static const MCPhysReg CSR_Interrupt_64R6_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::V1_64, Mips::V0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, `0` };
4284	static const uint32_t CSR_Interrupt_64R6_RegMask[] = { `0x43e80302`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x08000000`, `0x10000000`, `0x00000000`, `0x00000000`, `0x07ffbfe0`, `0xf8000000`, `0x00000000`, `0x03ffffc0`, };
4285	static const MCPhysReg CSR_Mips16RetHelper_SaveList[] = { Mips::V0, Mips::V1, Mips::FP, Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, `0` };
4286	static const uint32_t CSR_Mips16RetHelper_RegMask[] = { `0x03e00100`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00007e00`, `0x0007ff80`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x06003fc0`, `0x08000000`, `0x00000000`, `0x00000000`, };
4287	static const MCPhysReg CSR_N32_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, `0` };
4288	static const uint32_t CSR_N32_RegMask[] = { `0x00280300`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x0002aa80`, `0x08000000`, `0x15550000`, `0x00000000`, `0x00000000`, `0x00003fe0`, `0x08000000`, `0xaaa00000`, `0x00003fc0`, };
4289	static const MCPhysReg CSR_N32_SingleFloat_SaveList[] = { Mips::F30, Mips::F28, Mips::F26, Mips::F24, Mips::F22, Mips::F20, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, `0` };
4290	static const uint32_t CSR_N32_SingleFloat_RegMask[] = { `0x00280300`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x0002aa80`, `0x08000000`, `0x10000000`, `0x00000000`, `0x00000000`, `0x00003fe0`, `0x08000000`, `0x00000000`, `0x00003fc0`, };
4291	static const MCPhysReg CSR_N64_SaveList[] = { Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64, Mips::D26_64, Mips::D25_64, Mips::D24_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, `0` };
4292	static const uint32_t CSR_N64_RegMask[] = { `0x00280300`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00007800`, `0x0007f800`, `0x08000000`, `0x1ff00000`, `0x00000000`, `0x00000000`, `0x00003fe0`, `0x08000000`, `0xfe000000`, `0x00003fc1`, };
4293	static const MCPhysReg CSR_N64_SingleFloat_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, `0` };
4294	static const uint32_t CSR_N64_SingleFloat_RegMask[] = { `0x00280300`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00007800`, `0x0007f800`, `0x08000000`, `0x10000000`, `0x00000000`, `0x00000000`, `0x00003fe0`, `0x08000000`, `0x00000000`, `0x00003fc0`, };
4295	static const MCPhysReg CSR_O32_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, `0` };
4296	static const uint32_t CSR_O32_RegMask[] = { `0x00280100`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00007e00`, `0x0007ff80`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00003fc0`, `0x08000000`, `0x00000000`, `0x00000000`, };
4297	static const MCPhysReg CSR_O32_FP64_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, `0` };
4298	static const uint32_t CSR_O32_FP64_RegMask[] = { `0x00280100`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x0002aa80`, `0x00000000`, `0x05550000`, `0x00000000`, `0x00000000`, `0x00003fc0`, `0x08000000`, `0xaaa00000`, `0x00000000`, };
4299	static const MCPhysReg CSR_O32_FPXX_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, `0` };
4300	static const uint32_t CSR_O32_FPXX_RegMask[] = { `0x00280100`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00007e00`, `0x0007ff80`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00003fc0`, `0x08000000`, `0x00000000`, `0x00000000`, };
4301	static const MCPhysReg CSR_O32_SingleFloat_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, `0` };
4302	static const uint32_t CSR_O32_SingleFloat_RegMask[] = { `0x00280100`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00007e00`, `0x0007ff80`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00000000`, `0x00003fc0`, `0x08000000`, `0x00000000`, `0x00000000`, };
4303
4304
4305	ArrayRef<const uint32_t > MipsGenRegisterInfo::getRegMasks() const* {
4306	static const uint32_t *const Masks[] = {
4307	CSR_Interrupt_32_RegMask,
4308	CSR_Interrupt_32R6_RegMask,
4309	CSR_Interrupt_64_RegMask,
4310	CSR_Interrupt_64R6_RegMask,
4311	CSR_Mips16RetHelper_RegMask,
4312	CSR_N32_RegMask,
4313	CSR_N32_SingleFloat_RegMask,
4314	CSR_N64_RegMask,
4315	CSR_N64_SingleFloat_RegMask,
4316	CSR_O32_RegMask,
4317	CSR_O32_FP64_RegMask,
4318	CSR_O32_FPXX_RegMask,
4319	CSR_O32_SingleFloat_RegMask,
4320	};
4321	return ArrayRef(Masks);
4322	}
4323
4324	bool MipsGenRegisterInfo::
4325	isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
4326	return
4327	false;
4328	}
4329
4330	bool MipsGenRegisterInfo::
4331	isGeneralPurposeRegisterClass(const TargetRegisterClass RC) const* {
4332	return
4333	false;
4334	}
4335
4336	bool MipsGenRegisterInfo::
4337	isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
4338	return
4339	false;
4340	}
4341
4342	bool MipsGenRegisterInfo::
4343	isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
4344	return
4345	false;
4346	}
4347
4348	bool MipsGenRegisterInfo::
4349	isConstantPhysReg(MCRegister PhysReg) const {
4350	return
4351	PhysReg == Mips::ZERO \|\|
4352	PhysReg == Mips::ZERO_64 \|\|
4353	false;
4354	}
4355
4356	ArrayRef<const char > MipsGenRegisterInfo::getRegMaskNames() const* {
4357	static const char *Names[] = {
4358	"CSR_Interrupt_32",
4359	"CSR_Interrupt_32R6",
4360	"CSR_Interrupt_64",
4361	"CSR_Interrupt_64R6",
4362	"CSR_Mips16RetHelper",
4363	"CSR_N32",
4364	"CSR_N32_SingleFloat",
4365	"CSR_N64",
4366	"CSR_N64_SingleFloat",
4367	"CSR_O32",
4368	"CSR_O32_FP64",
4369	"CSR_O32_FPXX",
4370	"CSR_O32_SingleFloat",
4371	};
4372	return ArrayRef(Names);
4373	}
4374
4375	const MipsFrameLowering *
4376	MipsGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
4377	return static_cast<const MipsFrameLowering *>(
4378	MF.getSubtarget().getFrameLowering());
4379	}
4380
4381
4382	} // namespace llvm
4383

Browse the source code of llvm_projects/build/lib/Target/Mips/MipsGenRegisterInfoTargetDesc.inc