1//===- MipsRegisterInfo.cpp - MIPS Register Information -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the MIPS implementation of the TargetRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MipsRegisterInfo.h"
14#include "MCTargetDesc/MipsABIInfo.h"
15#include "Mips.h"
16#include "MipsMachineFunction.h"
17#include "MipsSubtarget.h"
18#include "MipsTargetMachine.h"
19#include "llvm/ADT/BitVector.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstr.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/TargetFrameLowering.h"
25#include "llvm/CodeGen/TargetRegisterInfo.h"
26#include "llvm/CodeGen/TargetSubtargetInfo.h"
27#include "llvm/IR/Function.h"
28#include "llvm/IR/Module.h"
29#include "llvm/Support/Debug.h"
30#include "llvm/Support/ErrorHandling.h"
31#include "llvm/Support/raw_ostream.h"
32#include <cstdint>
33
34using namespace llvm;
35
36#define DEBUG_TYPE "mips-reg-info"
37
38#define GET_REGINFO_TARGET_DESC
39#include "MipsGenRegisterInfo.inc"
40
41MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &STI)
42 : MipsGenRegisterInfo(Mips::RA), ArePtrs64bit(STI.getABI().ArePtrs64bit()) {
43 MIPS_MC::initLLVMToCVRegMapping(MRI: this);
44}
45
46unsigned MipsRegisterInfo::getPICCallReg() { return Mips::R25; }
47
48unsigned
49MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
50 MachineFunction &MF) const {
51 switch (RC->getID()) {
52 default:
53 return 0;
54 case Mips::GPR32RegClassID:
55 case Mips::GPR64RegClassID:
56 case Mips::DSPRRegClassID: {
57 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
58 return 28 - TFI->hasFP(MF);
59 }
60 case Mips::FGR32RegClassID:
61 return 32;
62 case Mips::AFGR64RegClassID:
63 return 16;
64 case Mips::FGR64RegClassID:
65 return 32;
66 }
67}
68
69//===----------------------------------------------------------------------===//
70// Callee Saved Registers methods
71//===----------------------------------------------------------------------===//
72
73/// Check if the user has declared $gp/$28 as a global regiater.
74bool isGPUsedAsGlobalRegister(const MachineFunction &MF) {
75 const Module *Module = MF.getFunction().getParent();
76
77 return Module->getNamedMetadata(Name: "llvm.named.register.$28");
78}
79
80/// Mips Callee Saved Registers
81const MCPhysReg *
82MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
83 const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
84 const Function &F = MF->getFunction();
85 if (F.hasFnAttribute(Kind: "interrupt")) {
86 if (Subtarget.hasMips64())
87 return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList
88 : CSR_Interrupt_64_SaveList;
89 else
90 return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList
91 : CSR_Interrupt_32_SaveList;
92 }
93
94 bool GPIsGlobal = isGPUsedAsGlobalRegister(MF: *MF);
95 // N64 ABI
96 if (Subtarget.isABI_N64()) {
97 if (Subtarget.isSingleFloat())
98 return GPIsGlobal ? CSR_N64_SingleFloat_NoGP_SaveList
99 : CSR_N64_SingleFloat_SaveList;
100
101 return GPIsGlobal ? CSR_N64_NoGP_SaveList : CSR_N64_SaveList;
102 }
103
104 // N32 ABI
105 if (Subtarget.isABI_N32()) {
106 if (Subtarget.isSingleFloat())
107 return GPIsGlobal ? CSR_N32_SingleFloat_NoGP_SaveList
108 : CSR_N32_SingleFloat_SaveList;
109
110 return GPIsGlobal ? CSR_N32_NoGP_SaveList : CSR_N32_SaveList;
111 }
112
113 // O32 ABI
114 if (Subtarget.isSingleFloat())
115 return CSR_O32_SingleFloat_SaveList;
116
117 if (Subtarget.isFP64bit())
118 return CSR_O32_FP64_SaveList;
119
120 if (Subtarget.isFPXX())
121 return CSR_O32_FPXX_SaveList;
122
123 return CSR_O32_SaveList;
124}
125
126const uint32_t *
127MipsRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
128 CallingConv::ID) const {
129 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
130 // N64 ABI
131 if (Subtarget.isABI_N64()) {
132 if (Subtarget.isSingleFloat())
133 return CSR_N64_SingleFloat_RegMask;
134
135 return CSR_N64_RegMask;
136 }
137
138 // N32 ABI
139 if (Subtarget.isABI_N32()) {
140 if (Subtarget.isSingleFloat())
141 return CSR_N32_SingleFloat_RegMask;
142
143 return CSR_N32_RegMask;
144 }
145
146 // O32 ABI
147 if (Subtarget.isSingleFloat())
148 return CSR_O32_SingleFloat_RegMask;
149
150 if (Subtarget.isFP64bit())
151 return CSR_O32_FP64_RegMask;
152
153 if (Subtarget.isFPXX())
154 return CSR_O32_FPXX_RegMask;
155
156 return CSR_O32_RegMask;
157}
158
159const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
160 return CSR_Mips16RetHelper_RegMask;
161}
162
163BitVector MipsRegisterInfo::
164getReservedRegs(const MachineFunction &MF) const {
165 static const MCPhysReg ReservedGPR32[] = {Mips::R0, Mips::R26, Mips::R27,
166 Mips::SP};
167
168 static const MCPhysReg ReservedGPR64[] = {Mips::R0_64, Mips::R26_64,
169 Mips::R27_64, Mips::SP_64};
170
171 BitVector Reserved(getNumRegs());
172 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
173
174 for (MCPhysReg R : ReservedGPR32)
175 Reserved.set(R);
176
177 for (MCPhysReg R : ReservedGPR64)
178 Reserved.set(R);
179
180 // Static JIT code uses t9 in RuntimeDyld stubs for R_MIPS_26 relocations,
181 // including jumps within a function. Keep it out of register allocation.
182 const auto &TM = static_cast<const MipsTargetMachine &>(MF.getTarget());
183 if (TM.isJIT() && TM.getRelocationModel() == Reloc::Static)
184 markSuperRegs(RegisterSet&: Reserved, Reg: Mips::R25);
185
186 // Mark user-reserved GPRs and their 64-bit super-registers.
187 for (unsigned I = 1; I < 32; ++I)
188 if (Subtarget.isGPRReservedByUser(GPR: I))
189 markSuperRegs(RegisterSet&: Reserved, Reg: Mips::GPR32RegClass.getRegister(i: I));
190
191 // For mno-abicalls, GP is a program invariant!
192 bool GPIsGlobal = isGPUsedAsGlobalRegister(MF);
193 if (!Subtarget.isABICalls() || GPIsGlobal) {
194 Reserved.set(Mips::GP);
195 Reserved.set(Mips::GP_64);
196 }
197
198 if (Subtarget.isFP64bit()) {
199 // Reserve all registers in AFGR64.
200 for (MCPhysReg Reg : Mips::AFGR64RegClass)
201 Reserved.set(Reg);
202 } else {
203 // Reserve all registers in FGR64.
204 for (MCPhysReg Reg : Mips::FGR64RegClass)
205 Reserved.set(Reg);
206 }
207 // Reserve FP if this function should have a dedicated frame pointer register.
208 if (Subtarget.getFrameLowering()->hasFP(MF)) {
209 if (Subtarget.inMips16Mode())
210 Reserved.set(Mips::R16);
211 else {
212 Reserved.set(Mips::FP);
213 Reserved.set(Mips::FP_64);
214
215 // Reserve the base register if we need to both realign the stack and
216 // allocate variable-sized objects at runtime. This should test the
217 // same conditions as MipsFrameLowering::hasBP().
218 if (hasStackRealignment(MF) && MF.getFrameInfo().hasVarSizedObjects()) {
219 const MipsABIInfo &ABI = Subtarget.getABI();
220 Reserved.set(ABI.getSavedReg(I: 7, Is64Bit: false));
221 Reserved.set(ABI.getSavedReg(I: 7, Is64Bit: true));
222 }
223 }
224 }
225 // Reserve fp control and status register
226 Reserved.set(Mips::FCR31);
227
228 // Reserve hardware registers.
229 Reserved.set(Mips::HWR29);
230 Reserved.set(Mips::HWR2);
231
232 // Reserve DSP control register.
233 Reserved.set(Mips::DSPPos);
234 Reserved.set(Mips::DSPSCount);
235 Reserved.set(Mips::DSPCarry);
236 Reserved.set(Mips::DSPEFI);
237 Reserved.set(Mips::DSPOutFlag);
238
239 // Reserve MSA control registers.
240 for (MCPhysReg Reg : Mips::MSACtrlRegClass)
241 Reserved.set(Reg);
242
243 // Reserve RA if in mips16 mode.
244 if (Subtarget.inMips16Mode()) {
245 const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
246 Reserved.set(Mips::RA);
247 Reserved.set(Mips::RA_64);
248 Reserved.set(Mips::R8);
249 Reserved.set(Mips::R9);
250 if (MF.getFunction().hasFnAttribute(Kind: "saveS2") || MipsFI->hasSaveS2())
251 Reserved.set(Mips::R18);
252 }
253
254 // Reserve GP if small section is used.
255 if (Subtarget.useSmallSection()) {
256 Reserved.set(Mips::GP);
257 Reserved.set(Mips::GP_64);
258 }
259
260 return Reserved;
261}
262
263// FrameIndex represent objects inside a abstract stack.
264// We must replace FrameIndex with an stack/frame pointer
265// direct reference.
266bool MipsRegisterInfo::
267eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
268 unsigned FIOperandNum, RegScavenger *RS) const {
269 MachineInstr &MI = *II;
270 MachineFunction &MF = *MI.getParent()->getParent();
271
272 LLVM_DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
273 errs() << "<--------->\n"
274 << MI);
275
276 int FrameIndex = MI.getOperand(i: FIOperandNum).getIndex();
277 uint64_t stackSize = MF.getFrameInfo().getStackSize();
278 int64_t spOffset = MF.getFrameInfo().getObjectOffset(ObjectIdx: FrameIndex);
279
280 LLVM_DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
281 << "spOffset : " << spOffset << "\n"
282 << "stackSize : " << stackSize << "\n"
283 << "alignment : "
284 << DebugStr(MF.getFrameInfo().getObjectAlign(FrameIndex))
285 << "\n");
286
287 eliminateFI(II: MI, OpNo: FIOperandNum, FrameIndex, StackSize: stackSize, SPOffset: spOffset);
288 return false;
289}
290
291Register MipsRegisterInfo::
292getFrameRegister(const MachineFunction &MF) const {
293 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
294 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
295 bool IsN64 = Subtarget.getABI().IsN64();
296
297 if (Subtarget.inMips16Mode())
298 return TFI->hasFP(MF) ? Mips::R16 : Mips::SP;
299 else
300 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
301 (IsN64 ? Mips::SP_64 : Mips::SP);
302}
303
304bool MipsRegisterInfo::canRealignStack(const MachineFunction &MF) const {
305 // Avoid realigning functions that explicitly do not want to be realigned.
306 // Normally, we should report an error when a function should be dynamically
307 // realigned but also has the attribute no-realign-stack. Unfortunately,
308 // with this attribute, MachineFrameInfo clamps each new object's alignment
309 // to that of the stack's alignment as specified by the ABI. As a result,
310 // the information of whether we have objects with larger alignment
311 // requirement than the stack's alignment is already lost at this point.
312 if (!TargetRegisterInfo::canRealignStack(MF))
313 return false;
314
315 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
316 unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64;
317 unsigned BP = Subtarget.getABI().getSavedReg(I: 7, Is64Bit: Subtarget.isGP64bit());
318
319 // Support dynamic stack realignment for all targets except Mips16.
320 if (Subtarget.inMips16Mode())
321 return false;
322
323 // We can't perform dynamic stack realignment if we can't reserve the
324 // frame pointer register.
325 if (!MF.getRegInfo().canReserveReg(PhysReg: FP))
326 return false;
327
328 // We can realign the stack if we know the maximum call frame size and we
329 // don't have variable sized objects.
330 if (Subtarget.getFrameLowering()->hasReservedCallFrame(MF))
331 return true;
332
333 // We have to reserve the base pointer register in the presence of variable
334 // sized objects.
335 return MF.getRegInfo().canReserveReg(PhysReg: BP);
336}
337