1//===- MipsRegisterInfo.cpp - MIPS Register Information -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the MIPS implementation of the TargetRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MipsRegisterInfo.h"
14#include "MCTargetDesc/MipsABIInfo.h"
15#include "Mips.h"
16#include "MipsMachineFunction.h"
17#include "MipsSubtarget.h"
18#include "MipsTargetMachine.h"
19#include "llvm/ADT/BitVector.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstr.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/TargetFrameLowering.h"
25#include "llvm/CodeGen/TargetRegisterInfo.h"
26#include "llvm/CodeGen/TargetSubtargetInfo.h"
27#include "llvm/IR/Function.h"
28#include "llvm/IR/Module.h"
29#include "llvm/Support/Debug.h"
30#include "llvm/Support/ErrorHandling.h"
31#include "llvm/Support/raw_ostream.h"
32#include <cstdint>
33
34using namespace llvm;
35
36#define DEBUG_TYPE "mips-reg-info"
37
38#define GET_REGINFO_TARGET_DESC
39#include "MipsGenRegisterInfo.inc"
40
41MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &STI)
42 : MipsGenRegisterInfo(Mips::RA), ArePtrs64bit(STI.getABI().ArePtrs64bit()) {
43 MIPS_MC::initLLVMToCVRegMapping(MRI: this);
44}
45
46unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
47
48unsigned
49MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
50 MachineFunction &MF) const {
51 switch (RC->getID()) {
52 default:
53 return 0;
54 case Mips::GPR32RegClassID:
55 case Mips::GPR64RegClassID:
56 case Mips::DSPRRegClassID: {
57 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
58 return 28 - TFI->hasFP(MF);
59 }
60 case Mips::FGR32RegClassID:
61 return 32;
62 case Mips::AFGR64RegClassID:
63 return 16;
64 case Mips::FGR64RegClassID:
65 return 32;
66 }
67}
68
69//===----------------------------------------------------------------------===//
70// Callee Saved Registers methods
71//===----------------------------------------------------------------------===//
72
73/// Check if the user has declared $gp/$28 as a global regiater.
74bool isGPUsedAsGlobalRegister(const MachineFunction &MF) {
75 const Module *Module = MF.getFunction().getParent();
76
77 return Module->getNamedMetadata(Name: "llvm.named.register.$28");
78}
79
80/// Mips Callee Saved Registers
81const MCPhysReg *
82MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
83 const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
84 const Function &F = MF->getFunction();
85 if (F.hasFnAttribute(Kind: "interrupt")) {
86 if (Subtarget.hasMips64())
87 return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList
88 : CSR_Interrupt_64_SaveList;
89 else
90 return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList
91 : CSR_Interrupt_32_SaveList;
92 }
93
94 bool GPIsGlobal = isGPUsedAsGlobalRegister(MF: *MF);
95 // N64 ABI
96 if (Subtarget.isABI_N64()) {
97 if (Subtarget.isSingleFloat())
98 return GPIsGlobal ? CSR_N64_SingleFloat_NoGP_SaveList
99 : CSR_N64_SingleFloat_SaveList;
100
101 return GPIsGlobal ? CSR_N64_NoGP_SaveList : CSR_N64_SaveList;
102 }
103
104 // N32 ABI
105 if (Subtarget.isABI_N32()) {
106 if (Subtarget.isSingleFloat())
107 return GPIsGlobal ? CSR_N32_SingleFloat_NoGP_SaveList
108 : CSR_N32_SingleFloat_SaveList;
109
110 return GPIsGlobal ? CSR_N32_NoGP_SaveList : CSR_N32_SaveList;
111 }
112
113 // O32 ABI
114 if (Subtarget.isSingleFloat())
115 return CSR_O32_SingleFloat_SaveList;
116
117 if (Subtarget.isFP64bit())
118 return CSR_O32_FP64_SaveList;
119
120 if (Subtarget.isFPXX())
121 return CSR_O32_FPXX_SaveList;
122
123 return CSR_O32_SaveList;
124}
125
126const uint32_t *
127MipsRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
128 CallingConv::ID) const {
129 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
130 // N64 ABI
131 if (Subtarget.isABI_N64()) {
132 if (Subtarget.isSingleFloat())
133 return CSR_N64_SingleFloat_RegMask;
134
135 return CSR_N64_RegMask;
136 }
137
138 // N32 ABI
139 if (Subtarget.isABI_N32()) {
140 if (Subtarget.isSingleFloat())
141 return CSR_N32_SingleFloat_RegMask;
142
143 return CSR_N32_RegMask;
144 }
145
146 // O32 ABI
147 if (Subtarget.isSingleFloat())
148 return CSR_O32_SingleFloat_RegMask;
149
150 if (Subtarget.isFP64bit())
151 return CSR_O32_FP64_RegMask;
152
153 if (Subtarget.isFPXX())
154 return CSR_O32_FPXX_RegMask;
155
156 return CSR_O32_RegMask;
157}
158
159const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
160 return CSR_Mips16RetHelper_RegMask;
161}
162
163BitVector MipsRegisterInfo::
164getReservedRegs(const MachineFunction &MF) const {
165 static const MCPhysReg ReservedGPR32[] = {
166 Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
167 };
168
169 static const MCPhysReg ReservedGPR64[] = {
170 Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
171 };
172
173 BitVector Reserved(getNumRegs());
174 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
175
176 for (MCPhysReg R : ReservedGPR32)
177 Reserved.set(R);
178
179 for (MCPhysReg R : ReservedGPR64)
180 Reserved.set(R);
181
182 // Mark user-reserved GPRs and their 64-bit super-registers.
183 for (unsigned I = 1; I < 32; ++I)
184 if (Subtarget.isGPRReservedByUser(GPR: I))
185 markSuperRegs(RegisterSet&: Reserved, Reg: Mips::GPR32RegClass.getRegister(i: I));
186
187 // For mno-abicalls, GP is a program invariant!
188 bool GPIsGlobal = isGPUsedAsGlobalRegister(MF);
189 if (!Subtarget.isABICalls() || GPIsGlobal) {
190 Reserved.set(Mips::GP);
191 Reserved.set(Mips::GP_64);
192 }
193
194 if (Subtarget.isFP64bit()) {
195 // Reserve all registers in AFGR64.
196 for (MCPhysReg Reg : Mips::AFGR64RegClass)
197 Reserved.set(Reg);
198 } else {
199 // Reserve all registers in FGR64.
200 for (MCPhysReg Reg : Mips::FGR64RegClass)
201 Reserved.set(Reg);
202 }
203 // Reserve FP if this function should have a dedicated frame pointer register.
204 if (Subtarget.getFrameLowering()->hasFP(MF)) {
205 if (Subtarget.inMips16Mode())
206 Reserved.set(Mips::S0);
207 else {
208 Reserved.set(Mips::FP);
209 Reserved.set(Mips::FP_64);
210
211 // Reserve the base register if we need to both realign the stack and
212 // allocate variable-sized objects at runtime. This should test the
213 // same conditions as MipsFrameLowering::hasBP().
214 if (hasStackRealignment(MF) && MF.getFrameInfo().hasVarSizedObjects()) {
215 Reserved.set(Mips::S7);
216 Reserved.set(Mips::S7_64);
217 }
218 }
219 }
220 // Reserve fp control and status register
221 Reserved.set(Mips::FCR31);
222
223 // Reserve hardware registers.
224 Reserved.set(Mips::HWR29);
225 Reserved.set(Mips::HWR2);
226
227 // Reserve DSP control register.
228 Reserved.set(Mips::DSPPos);
229 Reserved.set(Mips::DSPSCount);
230 Reserved.set(Mips::DSPCarry);
231 Reserved.set(Mips::DSPEFI);
232 Reserved.set(Mips::DSPOutFlag);
233
234 // Reserve MSA control registers.
235 for (MCPhysReg Reg : Mips::MSACtrlRegClass)
236 Reserved.set(Reg);
237
238 // Reserve RA if in mips16 mode.
239 if (Subtarget.inMips16Mode()) {
240 const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
241 Reserved.set(Mips::RA);
242 Reserved.set(Mips::RA_64);
243 Reserved.set(Mips::T0);
244 Reserved.set(Mips::T1);
245 if (MF.getFunction().hasFnAttribute(Kind: "saveS2") || MipsFI->hasSaveS2())
246 Reserved.set(Mips::S2);
247 }
248
249 // Reserve GP if small section is used.
250 if (Subtarget.useSmallSection()) {
251 Reserved.set(Mips::GP);
252 Reserved.set(Mips::GP_64);
253 }
254
255 return Reserved;
256}
257
258// FrameIndex represent objects inside a abstract stack.
259// We must replace FrameIndex with an stack/frame pointer
260// direct reference.
261bool MipsRegisterInfo::
262eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
263 unsigned FIOperandNum, RegScavenger *RS) const {
264 MachineInstr &MI = *II;
265 MachineFunction &MF = *MI.getParent()->getParent();
266
267 LLVM_DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
268 errs() << "<--------->\n"
269 << MI);
270
271 int FrameIndex = MI.getOperand(i: FIOperandNum).getIndex();
272 uint64_t stackSize = MF.getFrameInfo().getStackSize();
273 int64_t spOffset = MF.getFrameInfo().getObjectOffset(ObjectIdx: FrameIndex);
274
275 LLVM_DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
276 << "spOffset : " << spOffset << "\n"
277 << "stackSize : " << stackSize << "\n"
278 << "alignment : "
279 << DebugStr(MF.getFrameInfo().getObjectAlign(FrameIndex))
280 << "\n");
281
282 eliminateFI(II: MI, OpNo: FIOperandNum, FrameIndex, StackSize: stackSize, SPOffset: spOffset);
283 return false;
284}
285
286Register MipsRegisterInfo::
287getFrameRegister(const MachineFunction &MF) const {
288 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
289 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
290 bool IsN64 =
291 static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64();
292
293 if (Subtarget.inMips16Mode())
294 return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
295 else
296 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
297 (IsN64 ? Mips::SP_64 : Mips::SP);
298}
299
300bool MipsRegisterInfo::canRealignStack(const MachineFunction &MF) const {
301 // Avoid realigning functions that explicitly do not want to be realigned.
302 // Normally, we should report an error when a function should be dynamically
303 // realigned but also has the attribute no-realign-stack. Unfortunately,
304 // with this attribute, MachineFrameInfo clamps each new object's alignment
305 // to that of the stack's alignment as specified by the ABI. As a result,
306 // the information of whether we have objects with larger alignment
307 // requirement than the stack's alignment is already lost at this point.
308 if (!TargetRegisterInfo::canRealignStack(MF))
309 return false;
310
311 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
312 unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64;
313 unsigned BP = Subtarget.isGP32bit() ? Mips::S7 : Mips::S7_64;
314
315 // Support dynamic stack realignment for all targets except Mips16.
316 if (Subtarget.inMips16Mode())
317 return false;
318
319 // We can't perform dynamic stack realignment if we can't reserve the
320 // frame pointer register.
321 if (!MF.getRegInfo().canReserveReg(PhysReg: FP))
322 return false;
323
324 // We can realign the stack if we know the maximum call frame size and we
325 // don't have variable sized objects.
326 if (Subtarget.getFrameLowering()->hasReservedCallFrame(MF))
327 return true;
328
329 // We have to reserve the base pointer register in the presence of variable
330 // sized objects.
331 return MF.getRegInfo().canReserveReg(PhysReg: BP);
332}
333