1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Writer Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: Sparc.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10/// getMnemonic - This method is automatically generated by tablegen
11/// from the instruction set description.
12std::pair<const char *, uint64_t>
13SparcInstPrinter::getMnemonic(const MCInst &MI) const {
14
15#ifdef __GNUC__
16#pragma GCC diagnostic push
17#pragma GCC diagnostic ignored "-Woverlength-strings"
18#endif
19 static const char AsmStrs[] = {
20 /* 0 */ "fcmpd %fcc0, \000"
21 /* 14 */ "fcmpq %fcc0, \000"
22 /* 28 */ "fcmps %fcc0, \000"
23 /* 42 */ "rd %wim, \000"
24 /* 52 */ "rdpr %fq, \000"
25 /* 63 */ "rd %tbr, \000"
26 /* 73 */ "rd %psr, \000"
27 /* 83 */ "aes_kexpand0 \000"
28 /* 97 */ "aes_dround01 \000"
29 /* 111 */ "aes_eround01 \000"
30 /* 125 */ "fsrc1 \000"
31 /* 132 */ "aes_kexpand1 \000"
32 /* 146 */ "fandnot1 \000"
33 /* 156 */ "fnot1 \000"
34 /* 163 */ "fornot1 \000"
35 /* 172 */ "fsra32 \000"
36 /* 180 */ "fpsub32 \000"
37 /* 189 */ "fpadd32 \000"
38 /* 198 */ "edge32 \000"
39 /* 206 */ "fcmple32 \000"
40 /* 216 */ "fcmpne32 \000"
41 /* 226 */ "fpack32 \000"
42 /* 235 */ "cmask32 \000"
43 /* 244 */ "fsll32 \000"
44 /* 252 */ "fsrl32 \000"
45 /* 260 */ "fcmpeq32 \000"
46 /* 270 */ "fslas32 \000"
47 /* 279 */ "fcmpgt32 \000"
48 /* 289 */ "array32 \000"
49 /* 298 */ "fsrc2 \000"
50 /* 305 */ "aes_kexpand2 \000"
51 /* 319 */ "fandnot2 \000"
52 /* 329 */ "fnot2 \000"
53 /* 336 */ "fornot2 \000"
54 /* 345 */ "aes_dround23 \000"
55 /* 359 */ "aes_eround23 \000"
56 /* 373 */ "fpadd64 \000"
57 /* 382 */ "fsra16 \000"
58 /* 390 */ "fpsub16 \000"
59 /* 399 */ "fpadd16 \000"
60 /* 408 */ "edge16 \000"
61 /* 416 */ "fcmple16 \000"
62 /* 426 */ "fcmpne16 \000"
63 /* 436 */ "fpack16 \000"
64 /* 445 */ "cmask16 \000"
65 /* 454 */ "fsll16 \000"
66 /* 462 */ "fsrl16 \000"
67 /* 470 */ "fchksm16 \000"
68 /* 480 */ "fmean16 \000"
69 /* 489 */ "fcmpeq16 \000"
70 /* 499 */ "fslas16 \000"
71 /* 508 */ "fcmpgt16 \000"
72 /* 518 */ "fmul8x16 \000"
73 /* 528 */ "fmuld8ulx16 \000"
74 /* 541 */ "fmul8ulx16 \000"
75 /* 553 */ "fmuld8sux16 \000"
76 /* 566 */ "fmul8sux16 \000"
77 /* 578 */ "array16 \000"
78 /* 587 */ "edge8 \000"
79 /* 594 */ "cmask8 \000"
80 /* 602 */ "array8 \000"
81 /* 610 */ "!ADJCALLSTACKDOWN \000"
82 /* 629 */ "!ADJCALLSTACKUP \000"
83 /* 646 */ "stba \000"
84 /* 652 */ "stda \000"
85 /* 658 */ "stha \000"
86 /* 664 */ "stqa \000"
87 /* 670 */ "sra \000"
88 /* 675 */ "faligndata \000"
89 /* 687 */ "sta \000"
90 /* 692 */ "stxa \000"
91 /* 698 */ "stb \000"
92 /* 703 */ "sub \000"
93 /* 708 */ "crc32c \000"
94 /* 716 */ "smac \000"
95 /* 722 */ "umac \000"
96 /* 728 */ "tsubcc \000"
97 /* 736 */ "addxccc \000"
98 /* 745 */ "taddcc \000"
99 /* 753 */ "andcc \000"
100 /* 760 */ "smulcc \000"
101 /* 768 */ "umulcc \000"
102 /* 776 */ "andncc \000"
103 /* 784 */ "orncc \000"
104 /* 791 */ "xnorcc \000"
105 /* 799 */ "xorcc \000"
106 /* 806 */ "mulscc \000"
107 /* 814 */ "sdivcc \000"
108 /* 822 */ "udivcc \000"
109 /* 830 */ "subxcc \000"
110 /* 838 */ "addxcc \000"
111 /* 846 */ "popc \000"
112 /* 852 */ "addxc \000"
113 /* 859 */ "fsubd \000"
114 /* 866 */ "fhsubd \000"
115 /* 874 */ "fmsubd \000"
116 /* 882 */ "fnmsubd \000"
117 /* 891 */ "add \000"
118 /* 896 */ "faddd \000"
119 /* 903 */ "fhaddd \000"
120 /* 911 */ "fnhaddd \000"
121 /* 920 */ "fmaddd \000"
122 /* 928 */ "fnmaddd \000"
123 /* 937 */ "fnaddd \000"
124 /* 945 */ "fcmped \000"
125 /* 953 */ "fnegd \000"
126 /* 960 */ "fmuld \000"
127 /* 967 */ "fnmuld \000"
128 /* 975 */ "fsmuld \000"
129 /* 983 */ "fnsmuld \000"
130 /* 992 */ "fand \000"
131 /* 998 */ "fnand \000"
132 /* 1005 */ "fexpand \000"
133 /* 1014 */ "des_kexpand \000"
134 /* 1027 */ "des_round \000"
135 /* 1038 */ "fitod \000"
136 /* 1045 */ "fqtod \000"
137 /* 1052 */ "fstod \000"
138 /* 1059 */ "fxtod \000"
139 /* 1066 */ "movxtod \000"
140 /* 1075 */ "fcmpd \000"
141 /* 1082 */ "flcmpd \000"
142 /* 1090 */ "rd \000"
143 /* 1094 */ "fabsd \000"
144 /* 1101 */ "fsqrtd \000"
145 /* 1109 */ "std \000"
146 /* 1114 */ "fdivd \000"
147 /* 1121 */ "fmovd \000"
148 /* 1128 */ "fpmerge \000"
149 /* 1137 */ "bshuffle \000"
150 /* 1147 */ "fone \000"
151 /* 1153 */ "restore \000"
152 /* 1162 */ "save \000"
153 /* 1168 */ "camellia_f \000"
154 /* 1180 */ "flush \000"
155 /* 1187 */ "sth \000"
156 /* 1192 */ "sethi \000"
157 /* 1199 */ "fpmaddxhi \000"
158 /* 1210 */ "umulxhi \000"
159 /* 1219 */ "xmulxhi \000"
160 /* 1228 */ "camellia_fli \000"
161 /* 1242 */ "fdtoi \000"
162 /* 1249 */ "fqtoi \000"
163 /* 1256 */ "fstoi \000"
164 /* 1263 */ "bmask \000"
165 /* 1270 */ "edge32l \000"
166 /* 1279 */ "edge16l \000"
167 /* 1288 */ "edge8l \000"
168 /* 1296 */ "aes_dround01_l \000"
169 /* 1312 */ "aes_eround01_l \000"
170 /* 1328 */ "aes_dround23_l \000"
171 /* 1344 */ "aes_eround23_l \000"
172 /* 1360 */ "fmul8x16al \000"
173 /* 1372 */ "camellia_fl \000"
174 /* 1385 */ "call \000"
175 /* 1391 */ "sll \000"
176 /* 1396 */ "jmpl \000"
177 /* 1402 */ "alignaddrl \000"
178 /* 1414 */ "srl \000"
179 /* 1419 */ "mpmul \000"
180 /* 1426 */ "smul \000"
181 /* 1432 */ "montmul \000"
182 /* 1441 */ "umul \000"
183 /* 1447 */ "siam \000"
184 /* 1453 */ "edge32n \000"
185 /* 1462 */ "edge16n \000"
186 /* 1471 */ "edge8n \000"
187 /* 1479 */ "andn \000"
188 /* 1485 */ "edge32ln \000"
189 /* 1495 */ "edge16ln \000"
190 /* 1505 */ "edge8ln \000"
191 /* 1514 */ "orn \000"
192 /* 1519 */ "pdistn \000"
193 /* 1527 */ "fzero \000"
194 /* 1534 */ "des_ip \000"
195 /* 1542 */ "des_iip \000"
196 /* 1551 */ "unimp \000"
197 /* 1558 */ "jmp \000"
198 /* 1563 */ "fsubq \000"
199 /* 1570 */ "faddq \000"
200 /* 1577 */ "fcmpeq \000"
201 /* 1585 */ "fnegq \000"
202 /* 1592 */ "fdmulq \000"
203 /* 1600 */ "fmulq \000"
204 /* 1607 */ "fdtoq \000"
205 /* 1614 */ "fitoq \000"
206 /* 1621 */ "fstoq \000"
207 /* 1628 */ "fxtoq \000"
208 /* 1635 */ "fcmpq \000"
209 /* 1642 */ "fabsq \000"
210 /* 1649 */ "fsqrtq \000"
211 /* 1657 */ "stq \000"
212 /* 1662 */ "fdivq \000"
213 /* 1669 */ "fmovq \000"
214 /* 1676 */ "membar \000"
215 /* 1684 */ "alignaddr \000"
216 /* 1695 */ "sir \000"
217 /* 1700 */ "for \000"
218 /* 1705 */ "fnor \000"
219 /* 1711 */ "fxnor \000"
220 /* 1718 */ "fxor \000"
221 /* 1724 */ "rdpr \000"
222 /* 1730 */ "wrpr \000"
223 /* 1736 */ "montsqr \000"
224 /* 1745 */ "pwr \000"
225 /* 1750 */ "fsrc1s \000"
226 /* 1758 */ "fandnot1s \000"
227 /* 1769 */ "fnot1s \000"
228 /* 1777 */ "fornot1s \000"
229 /* 1787 */ "fpsub32s \000"
230 /* 1797 */ "fpadd32s \000"
231 /* 1807 */ "fsrc2s \000"
232 /* 1815 */ "fandnot2s \000"
233 /* 1826 */ "fnot2s \000"
234 /* 1834 */ "fornot2s \000"
235 /* 1844 */ "fpsub16s \000"
236 /* 1854 */ "fpadd16s \000"
237 /* 1864 */ "fsubs \000"
238 /* 1871 */ "fhsubs \000"
239 /* 1879 */ "fmsubs \000"
240 /* 1887 */ "fnmsubs \000"
241 /* 1896 */ "fadds \000"
242 /* 1903 */ "fhadds \000"
243 /* 1911 */ "fnhadds \000"
244 /* 1920 */ "fmadds \000"
245 /* 1928 */ "fnmadds \000"
246 /* 1937 */ "fnadds \000"
247 /* 1945 */ "fands \000"
248 /* 1952 */ "fnands \000"
249 /* 1960 */ "fones \000"
250 /* 1967 */ "fcmpes \000"
251 /* 1975 */ "fnegs \000"
252 /* 1982 */ "fmuls \000"
253 /* 1989 */ "fnmuls \000"
254 /* 1997 */ "fzeros \000"
255 /* 2005 */ "fdtos \000"
256 /* 2012 */ "fitos \000"
257 /* 2019 */ "fqtos \000"
258 /* 2026 */ "movwtos \000"
259 /* 2035 */ "fxtos \000"
260 /* 2042 */ "fcmps \000"
261 /* 2049 */ "flcmps \000"
262 /* 2057 */ "fors \000"
263 /* 2063 */ "fnors \000"
264 /* 2070 */ "fxnors \000"
265 /* 2078 */ "fxors \000"
266 /* 2085 */ "fabss \000"
267 /* 2092 */ "fsqrts \000"
268 /* 2100 */ "fdivs \000"
269 /* 2107 */ "fmovs \000"
270 /* 2114 */ "set \000"
271 /* 2119 */ "lzcnt \000"
272 /* 2126 */ "pdist \000"
273 /* 2133 */ "rett \000"
274 /* 2139 */ "fmul8x16au \000"
275 /* 2151 */ "sdiv \000"
276 /* 2157 */ "udiv \000"
277 /* 2163 */ "tsubcctv \000"
278 /* 2173 */ "taddcctv \000"
279 /* 2183 */ "movstosw \000"
280 /* 2193 */ "setsw \000"
281 /* 2200 */ "movstouw \000"
282 /* 2210 */ "srax \000"
283 /* 2216 */ "subx \000"
284 /* 2222 */ "fpmaddx \000"
285 /* 2231 */ "fpackfix \000"
286 /* 2241 */ "sllx \000"
287 /* 2247 */ "srlx \000"
288 /* 2253 */ "xmulx \000"
289 /* 2260 */ "fdtox \000"
290 /* 2267 */ "movdtox \000"
291 /* 2276 */ "fqtox \000"
292 /* 2283 */ "fstox \000"
293 /* 2290 */ "setx \000"
294 /* 2296 */ "stx \000"
295 /* 2301 */ "sdivx \000"
296 /* 2308 */ "udivx \000"
297 /* 2315 */ "; SELECT_CC_DFP_FCC PSEUDO!\000"
298 /* 2343 */ "; SELECT_CC_QFP_FCC PSEUDO!\000"
299 /* 2371 */ "; SELECT_CC_FP_FCC PSEUDO!\000"
300 /* 2398 */ "; SELECT_CC_Int_FCC PSEUDO!\000"
301 /* 2426 */ "; SELECT_CC_DFP_ICC PSEUDO!\000"
302 /* 2454 */ "; SELECT_CC_QFP_ICC PSEUDO!\000"
303 /* 2482 */ "; SELECT_CC_FP_ICC PSEUDO!\000"
304 /* 2509 */ "; SELECT_CC_Int_ICC PSEUDO!\000"
305 /* 2537 */ "; SELECT_CC_DFP_XCC PSEUDO!\000"
306 /* 2565 */ "; SELECT_CC_QFP_XCC PSEUDO!\000"
307 /* 2593 */ "; SELECT_CC_FP_XCC PSEUDO!\000"
308 /* 2620 */ "; SELECT_CC_Int_XCC PSEUDO!\000"
309 /* 2648 */ "jmp %i7+\000"
310 /* 2657 */ "jmp %o7+\000"
311 /* 2666 */ "# XRay Function Patchable RET.\000"
312 /* 2697 */ "# XRay Typed Event Log.\000"
313 /* 2721 */ "# XRay Custom Event Log.\000"
314 /* 2746 */ "# XRay Function Enter.\000"
315 /* 2769 */ "# XRay Tail Call Exit.\000"
316 /* 2792 */ "# XRay Function Exit.\000"
317 /* 2814 */ "flush %g0\000"
318 /* 2824 */ "ta 1\000"
319 /* 2829 */ "sha1\000"
320 /* 2834 */ "sha512\000"
321 /* 2841 */ "ta 3\000"
322 /* 2846 */ "ta 5\000"
323 /* 2851 */ "md5\000"
324 /* 2855 */ "sha256\000"
325 /* 2862 */ "LIFETIME_END\000"
326 /* 2875 */ "PSEUDO_PROBE\000"
327 /* 2888 */ "BUNDLE\000"
328 /* 2895 */ "FAKE_USE\000"
329 /* 2904 */ "DBG_VALUE\000"
330 /* 2914 */ "DBG_INSTR_REF\000"
331 /* 2928 */ "DBG_PHI\000"
332 /* 2936 */ "DBG_LABEL\000"
333 /* 2946 */ "!V8BAR\000"
334 /* 2953 */ "LIFETIME_START\000"
335 /* 2968 */ "DBG_VALUE_LIST\000"
336 /* 2983 */ "std %cq, [\000"
337 /* 2994 */ "std %fq, [\000"
338 /* 3005 */ "st %csr, [\000"
339 /* 3016 */ "st %fsr, [\000"
340 /* 3027 */ "stx %fsr, [\000"
341 /* 3039 */ "ldsba [\000"
342 /* 3047 */ "lduba [\000"
343 /* 3055 */ "ldstuba [\000"
344 /* 3065 */ "ldda [\000"
345 /* 3072 */ "lda [\000"
346 /* 3078 */ "prefetcha [\000"
347 /* 3090 */ "ldsha [\000"
348 /* 3098 */ "lduha [\000"
349 /* 3106 */ "swapa [\000"
350 /* 3114 */ "ldqa [\000"
351 /* 3121 */ "casa [\000"
352 /* 3128 */ "ldswa [\000"
353 /* 3136 */ "ldxa [\000"
354 /* 3143 */ "casxa [\000"
355 /* 3151 */ "ldsb [\000"
356 /* 3158 */ "ldub [\000"
357 /* 3165 */ "ldstub [\000"
358 /* 3174 */ "ldd [\000"
359 /* 3180 */ "ld [\000"
360 /* 3185 */ "prefetch [\000"
361 /* 3196 */ "ldsh [\000"
362 /* 3203 */ "lduh [\000"
363 /* 3210 */ "swap [\000"
364 /* 3217 */ "ldq [\000"
365 /* 3223 */ "ldsw [\000"
366 /* 3230 */ "ldx [\000"
367 /* 3236 */ "cb\000"
368 /* 3239 */ "fb\000"
369 /* 3242 */ "cwb\000"
370 /* 3246 */ "cxb\000"
371 /* 3250 */ "restored\000"
372 /* 3259 */ "saved\000"
373 /* 3265 */ "fmovrd\000"
374 /* 3272 */ "fmovd\000"
375 /* 3278 */ "done\000"
376 /* 3283 */ "# FEntry call\000"
377 /* 3297 */ "allclean\000"
378 /* 3306 */ "shutdown\000"
379 /* 3315 */ "nop\000"
380 /* 3319 */ "fmovrq\000"
381 /* 3326 */ "fmovq\000"
382 /* 3332 */ "stbar\000"
383 /* 3338 */ "br\000"
384 /* 3341 */ "movr\000"
385 /* 3346 */ "fmovrs\000"
386 /* 3353 */ "fmovs\000"
387 /* 3359 */ "t\000"
388 /* 3361 */ "mov\000"
389 /* 3365 */ "flushw\000"
390 /* 3372 */ "normalw\000"
391 /* 3380 */ "invalw\000"
392 /* 3387 */ "otherw\000"
393 /* 3394 */ "retry\000"
394};
395#ifdef __GNUC__
396#pragma GCC diagnostic pop
397#endif
398
399 static const uint32_t OpInfo0[] = {
400 0U, // PHI
401 0U, // INLINEASM
402 0U, // INLINEASM_BR
403 0U, // CFI_INSTRUCTION
404 0U, // EH_LABEL
405 0U, // GC_LABEL
406 0U, // ANNOTATION_LABEL
407 0U, // KILL
408 0U, // EXTRACT_SUBREG
409 0U, // INSERT_SUBREG
410 0U, // IMPLICIT_DEF
411 0U, // INIT_UNDEF
412 0U, // SUBREG_TO_REG
413 0U, // COPY_TO_REGCLASS
414 2905U, // DBG_VALUE
415 2969U, // DBG_VALUE_LIST
416 2915U, // DBG_INSTR_REF
417 2929U, // DBG_PHI
418 2937U, // DBG_LABEL
419 0U, // REG_SEQUENCE
420 0U, // COPY
421 0U, // COPY_LANEMASK
422 2889U, // BUNDLE
423 2954U, // LIFETIME_START
424 2863U, // LIFETIME_END
425 2876U, // PSEUDO_PROBE
426 0U, // ARITH_FENCE
427 0U, // STACKMAP
428 3284U, // FENTRY_CALL
429 0U, // PATCHPOINT
430 0U, // LOAD_STACK_GUARD
431 0U, // PREALLOCATED_SETUP
432 0U, // PREALLOCATED_ARG
433 0U, // STATEPOINT
434 0U, // LOCAL_ESCAPE
435 0U, // FAULTING_OP
436 0U, // PATCHABLE_OP
437 2747U, // PATCHABLE_FUNCTION_ENTER
438 2667U, // PATCHABLE_RET
439 2793U, // PATCHABLE_FUNCTION_EXIT
440 2770U, // PATCHABLE_TAIL_CALL
441 2722U, // PATCHABLE_EVENT_CALL
442 2698U, // PATCHABLE_TYPED_EVENT_CALL
443 0U, // ICALL_BRANCH_FUNNEL
444 2896U, // FAKE_USE
445 0U, // MEMBARRIER
446 0U, // JUMP_TABLE_DEBUG_INFO
447 0U, // RELOC_NONE
448 0U, // CONVERGENCECTRL_ENTRY
449 0U, // CONVERGENCECTRL_ANCHOR
450 0U, // CONVERGENCECTRL_LOOP
451 0U, // CONVERGENCECTRL_GLUE
452 0U, // G_ASSERT_SEXT
453 0U, // G_ASSERT_ZEXT
454 0U, // G_ASSERT_ALIGN
455 0U, // G_ADD
456 0U, // G_SUB
457 0U, // G_MUL
458 0U, // G_SDIV
459 0U, // G_UDIV
460 0U, // G_SREM
461 0U, // G_UREM
462 0U, // G_SDIVREM
463 0U, // G_UDIVREM
464 0U, // G_AND
465 0U, // G_OR
466 0U, // G_XOR
467 0U, // G_ABDS
468 0U, // G_ABDU
469 0U, // G_UAVGFLOOR
470 0U, // G_UAVGCEIL
471 0U, // G_SAVGFLOOR
472 0U, // G_SAVGCEIL
473 0U, // G_IMPLICIT_DEF
474 0U, // G_PHI
475 0U, // G_FRAME_INDEX
476 0U, // G_GLOBAL_VALUE
477 0U, // G_PTRAUTH_GLOBAL_VALUE
478 0U, // G_CONSTANT_POOL
479 0U, // G_EXTRACT
480 0U, // G_UNMERGE_VALUES
481 0U, // G_INSERT
482 0U, // G_MERGE_VALUES
483 0U, // G_BUILD_VECTOR
484 0U, // G_BUILD_VECTOR_TRUNC
485 0U, // G_CONCAT_VECTORS
486 0U, // G_PTRTOINT
487 0U, // G_INTTOPTR
488 0U, // G_BITCAST
489 0U, // G_FREEZE
490 0U, // G_CONSTANT_FOLD_BARRIER
491 0U, // G_INTRINSIC_FPTRUNC_ROUND
492 0U, // G_INTRINSIC_TRUNC
493 0U, // G_INTRINSIC_ROUND
494 0U, // G_INTRINSIC_LRINT
495 0U, // G_INTRINSIC_LLRINT
496 0U, // G_INTRINSIC_ROUNDEVEN
497 0U, // G_READCYCLECOUNTER
498 0U, // G_READSTEADYCOUNTER
499 0U, // G_LOAD
500 0U, // G_SEXTLOAD
501 0U, // G_ZEXTLOAD
502 0U, // G_FPEXTLOAD
503 0U, // G_INDEXED_LOAD
504 0U, // G_INDEXED_SEXTLOAD
505 0U, // G_INDEXED_ZEXTLOAD
506 0U, // G_STORE
507 0U, // G_FPTRUNCSTORE
508 0U, // G_INDEXED_STORE
509 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
510 0U, // G_ATOMIC_CMPXCHG
511 0U, // G_ATOMICRMW_XCHG
512 0U, // G_ATOMICRMW_ADD
513 0U, // G_ATOMICRMW_SUB
514 0U, // G_ATOMICRMW_AND
515 0U, // G_ATOMICRMW_NAND
516 0U, // G_ATOMICRMW_OR
517 0U, // G_ATOMICRMW_XOR
518 0U, // G_ATOMICRMW_MAX
519 0U, // G_ATOMICRMW_MIN
520 0U, // G_ATOMICRMW_UMAX
521 0U, // G_ATOMICRMW_UMIN
522 0U, // G_ATOMICRMW_FADD
523 0U, // G_ATOMICRMW_FSUB
524 0U, // G_ATOMICRMW_FMAX
525 0U, // G_ATOMICRMW_FMIN
526 0U, // G_ATOMICRMW_FMAXIMUM
527 0U, // G_ATOMICRMW_FMINIMUM
528 0U, // G_ATOMICRMW_FMAXIMUMNUM
529 0U, // G_ATOMICRMW_FMINIMUMNUM
530 0U, // G_ATOMICRMW_UINC_WRAP
531 0U, // G_ATOMICRMW_UDEC_WRAP
532 0U, // G_ATOMICRMW_USUB_COND
533 0U, // G_ATOMICRMW_USUB_SAT
534 0U, // G_FENCE
535 0U, // G_PREFETCH
536 0U, // G_BRCOND
537 0U, // G_BRINDIRECT
538 0U, // G_INVOKE_REGION_START
539 0U, // G_INTRINSIC
540 0U, // G_INTRINSIC_W_SIDE_EFFECTS
541 0U, // G_INTRINSIC_CONVERGENT
542 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
543 0U, // G_ANYEXT
544 0U, // G_TRUNC
545 0U, // G_TRUNC_SSAT_S
546 0U, // G_TRUNC_SSAT_U
547 0U, // G_TRUNC_USAT_U
548 0U, // G_CONSTANT
549 0U, // G_FCONSTANT
550 0U, // G_VASTART
551 0U, // G_VAARG
552 0U, // G_SEXT
553 0U, // G_SEXT_INREG
554 0U, // G_ZEXT
555 0U, // G_SHL
556 0U, // G_LSHR
557 0U, // G_ASHR
558 0U, // G_FSHL
559 0U, // G_FSHR
560 0U, // G_ROTR
561 0U, // G_ROTL
562 0U, // G_ICMP
563 0U, // G_FCMP
564 0U, // G_SCMP
565 0U, // G_UCMP
566 0U, // G_SELECT
567 0U, // G_UADDO
568 0U, // G_UADDE
569 0U, // G_USUBO
570 0U, // G_USUBE
571 0U, // G_SADDO
572 0U, // G_SADDE
573 0U, // G_SSUBO
574 0U, // G_SSUBE
575 0U, // G_UMULO
576 0U, // G_SMULO
577 0U, // G_UMULH
578 0U, // G_SMULH
579 0U, // G_UADDSAT
580 0U, // G_SADDSAT
581 0U, // G_USUBSAT
582 0U, // G_SSUBSAT
583 0U, // G_USHLSAT
584 0U, // G_SSHLSAT
585 0U, // G_SMULFIX
586 0U, // G_UMULFIX
587 0U, // G_SMULFIXSAT
588 0U, // G_UMULFIXSAT
589 0U, // G_SDIVFIX
590 0U, // G_UDIVFIX
591 0U, // G_SDIVFIXSAT
592 0U, // G_UDIVFIXSAT
593 0U, // G_FADD
594 0U, // G_FSUB
595 0U, // G_FMUL
596 0U, // G_FMA
597 0U, // G_FMAD
598 0U, // G_FDIV
599 0U, // G_FREM
600 0U, // G_FMODF
601 0U, // G_FPOW
602 0U, // G_FPOWI
603 0U, // G_FEXP
604 0U, // G_FEXP2
605 0U, // G_FEXP10
606 0U, // G_FLOG
607 0U, // G_FLOG2
608 0U, // G_FLOG10
609 0U, // G_FLDEXP
610 0U, // G_FFREXP
611 0U, // G_FNEG
612 0U, // G_FPEXT
613 0U, // G_FPTRUNC
614 0U, // G_FPTOSI
615 0U, // G_FPTOUI
616 0U, // G_SITOFP
617 0U, // G_UITOFP
618 0U, // G_FPTOSI_SAT
619 0U, // G_FPTOUI_SAT
620 0U, // G_FABS
621 0U, // G_FCOPYSIGN
622 0U, // G_IS_FPCLASS
623 0U, // G_FCANONICALIZE
624 0U, // G_FMINNUM
625 0U, // G_FMAXNUM
626 0U, // G_FMINNUM_IEEE
627 0U, // G_FMAXNUM_IEEE
628 0U, // G_FMINIMUM
629 0U, // G_FMAXIMUM
630 0U, // G_FMINIMUMNUM
631 0U, // G_FMAXIMUMNUM
632 0U, // G_GET_FPENV
633 0U, // G_SET_FPENV
634 0U, // G_RESET_FPENV
635 0U, // G_GET_FPMODE
636 0U, // G_SET_FPMODE
637 0U, // G_RESET_FPMODE
638 0U, // G_GET_ROUNDING
639 0U, // G_SET_ROUNDING
640 0U, // G_PTR_ADD
641 0U, // G_PTRMASK
642 0U, // G_SMIN
643 0U, // G_SMAX
644 0U, // G_UMIN
645 0U, // G_UMAX
646 0U, // G_ABS
647 0U, // G_LROUND
648 0U, // G_LLROUND
649 0U, // G_BR
650 0U, // G_BRJT
651 0U, // G_VSCALE
652 0U, // G_INSERT_SUBVECTOR
653 0U, // G_EXTRACT_SUBVECTOR
654 0U, // G_INSERT_VECTOR_ELT
655 0U, // G_EXTRACT_VECTOR_ELT
656 0U, // G_SHUFFLE_VECTOR
657 0U, // G_SPLAT_VECTOR
658 0U, // G_STEP_VECTOR
659 0U, // G_VECTOR_COMPRESS
660 0U, // G_CTTZ
661 0U, // G_CTTZ_ZERO_POISON
662 0U, // G_CTLZ
663 0U, // G_CTLZ_ZERO_POISON
664 0U, // G_CTLS
665 0U, // G_CTPOP
666 0U, // G_BSWAP
667 0U, // G_BITREVERSE
668 0U, // G_CLMUL
669 0U, // G_CLMULH
670 0U, // G_CLMULR
671 0U, // G_FCEIL
672 0U, // G_FCOS
673 0U, // G_FSIN
674 0U, // G_FSINCOS
675 0U, // G_FTAN
676 0U, // G_FACOS
677 0U, // G_FASIN
678 0U, // G_FATAN
679 0U, // G_FATAN2
680 0U, // G_FCOSH
681 0U, // G_FSINH
682 0U, // G_FTANH
683 0U, // G_FSQRT
684 0U, // G_FFLOOR
685 0U, // G_FRINT
686 0U, // G_FNEARBYINT
687 0U, // G_ADDRSPACE_CAST
688 0U, // G_BLOCK_ADDR
689 0U, // G_JUMP_TABLE
690 0U, // G_DYN_STACKALLOC
691 0U, // G_STACKSAVE
692 0U, // G_STACKRESTORE
693 0U, // G_STRICT_FADD
694 0U, // G_STRICT_FSUB
695 0U, // G_STRICT_FMUL
696 0U, // G_STRICT_FDIV
697 0U, // G_STRICT_FREM
698 0U, // G_STRICT_FMA
699 0U, // G_STRICT_FSQRT
700 0U, // G_STRICT_FLDEXP
701 0U, // G_STRICT_FCMP
702 0U, // G_STRICT_FCMPS
703 0U, // G_READ_REGISTER
704 0U, // G_WRITE_REGISTER
705 0U, // G_MEMCPY
706 0U, // G_MEMCPY_INLINE
707 0U, // G_MEMMOVE
708 0U, // G_MEMSET
709 0U, // G_BZERO
710 0U, // G_MEMSET_INLINE
711 0U, // G_TRAP
712 0U, // G_DEBUGTRAP
713 0U, // G_UBSANTRAP
714 0U, // G_VECREDUCE_SEQ_FADD
715 0U, // G_VECREDUCE_SEQ_FMUL
716 0U, // G_VECREDUCE_FADD
717 0U, // G_VECREDUCE_FMUL
718 0U, // G_VECREDUCE_FMAX
719 0U, // G_VECREDUCE_FMIN
720 0U, // G_VECREDUCE_FMAXIMUM
721 0U, // G_VECREDUCE_FMINIMUM
722 0U, // G_VECREDUCE_FMAXIMUMNUM
723 0U, // G_VECREDUCE_FMINIMUMNUM
724 0U, // G_VECREDUCE_ADD
725 0U, // G_VECREDUCE_MUL
726 0U, // G_VECREDUCE_AND
727 0U, // G_VECREDUCE_OR
728 0U, // G_VECREDUCE_XOR
729 0U, // G_VECREDUCE_SMAX
730 0U, // G_VECREDUCE_SMIN
731 0U, // G_VECREDUCE_UMAX
732 0U, // G_VECREDUCE_UMIN
733 0U, // G_SBFX
734 0U, // G_UBFX
735 4707U, // ADJCALLSTACKDOWN
736 70262U, // ADJCALLSTACKUP
737 8206U, // GETPCX
738 2316U, // SELECT_CC_DFP_FCC
739 2427U, // SELECT_CC_DFP_ICC
740 2538U, // SELECT_CC_DFP_XCC
741 2372U, // SELECT_CC_FP_FCC
742 2483U, // SELECT_CC_FP_ICC
743 2594U, // SELECT_CC_FP_XCC
744 2399U, // SELECT_CC_Int_FCC
745 2510U, // SELECT_CC_Int_ICC
746 2621U, // SELECT_CC_Int_XCC
747 2344U, // SELECT_CC_QFP_FCC
748 2455U, // SELECT_CC_QFP_ICC
749 2566U, // SELECT_CC_QFP_XCC
750 2111555U, // SET
751 2111634U, // SETSW
752 20986099U, // SETX
753 2947U, // V8BAR
754 20984555U, // ADDCCri
755 20984555U, // ADDCCrr
756 20986034U, // ADDCri
757 20986034U, // ADDCrr
758 20984647U, // ADDEri
759 20984647U, // ADDErr
760 20984661U, // ADDXC
761 20984545U, // ADDXCCC
762 20984700U, // ADDri
763 20984700U, // ADDrr
764 692072546U, // AES_DROUND01
765 692073745U, // AES_DROUND01_LAST
766 692072794U, // AES_DROUND23
767 692073777U, // AES_DROUND23_LAST
768 692072560U, // AES_EROUND01
769 692073761U, // AES_EROUND01_LAST
770 692072808U, // AES_EROUND23
771 692073793U, // AES_EROUND23_LAST
772 20983892U, // AES_KEXPAND0
773 692072581U, // AES_KEXPAND1
774 20984114U, // AES_KEXPAND2
775 20985493U, // ALIGNADDR
776 20985211U, // ALIGNADDRL
777 3298U, // ALLCLEAN
778 20984562U, // ANDCCri
779 20984562U, // ANDCCrr
780 20984585U, // ANDNCCri
781 20984585U, // ANDNCCrr
782 20985288U, // ANDNri
783 20985288U, // ANDNrr
784 20984802U, // ANDri
785 20984802U, // ANDrr
786 20984387U, // ARRAY16
787 20984098U, // ARRAY32
788 20984411U, // ARRAY8
789 82569U, // BA
790 6446246U, // BCOND
791 6511782U, // BCONDA
792 91671U, // BINDri
793 91671U, // BINDrr
794 20985072U, // BMASK
795 289561768U, // BPFCC
796 289627304U, // BPFCCA
797 285864U, // BPFCCANT
798 351400U, // BPFCCNT
799 6708390U, // BPICC
800 482470U, // BPICCA
801 548006U, // BPICCANT
802 613542U, // BPICCNT
803 289561867U, // BPR
804 289627403U, // BPRA
805 285963U, // BPRANT
806 351499U, // BPRNT
807 6970534U, // BPXCC
808 744614U, // BPXCCA
809 810150U, // BPXCCANT
810 875686U, // BPXCCNT
811 20984946U, // BSHUFFLE
812 83306U, // CALL
813 17770U, // CALLi
814 91498U, // CALLri
815 4220266U, // CALLrii
816 91498U, // CALLrr
817 4220266U, // CALLrri
818 692073617U, // CAMELLIA_F
819 20985181U, // CAMELLIA_FL
820 20985037U, // CAMELLIA_FLI
821 21904434U, // CASAri
822 9387058U, // CASArr
823 21904456U, // CASXAri
824 9387080U, // CASXArr
825 70078U, // CMASK16
826 69868U, // CMASK32
827 70227U, // CMASK8
828 6446245U, // CPBCOND
829 6511781U, // CPBCONDA
830 20984517U, // CRC32C
831 1765956779U, // CWBCONDri
832 1765956779U, // CWBCONDrr
833 1765956783U, // CXBCONDri
834 1765956783U, // CXBCONDrr
835 2110983U, // DES_IIP
836 2110975U, // DES_IP
837 20984823U, // DES_KEXPAND
838 692073476U, // DES_ROUND
839 3279U, // DONE
840 20984217U, // EDGE16
841 20985088U, // EDGE16L
842 20985304U, // EDGE16LN
843 20985271U, // EDGE16N
844 20984007U, // EDGE32
845 20985079U, // EDGE32L
846 20985294U, // EDGE32LN
847 20985262U, // EDGE32N
848 20984396U, // EDGE8
849 20985097U, // EDGE8L
850 20985314U, // EDGE8LN
851 20985280U, // EDGE8N
852 2110535U, // FABSD
853 2111083U, // FABSQ
854 2111526U, // FABSS
855 20984705U, // FADDD
856 20985379U, // FADDQ
857 20985705U, // FADDS
858 20984484U, // FALIGNADATA
859 20984801U, // FAND
860 20983955U, // FANDNOT1
861 20985567U, // FANDNOT1S
862 20984128U, // FANDNOT2
863 20985624U, // FANDNOT2S
864 20985754U, // FANDS
865 6446248U, // FBCOND
866 6511784U, // FBCONDA
867 1072296U, // FBCONDA_V9
868 7429288U, // FBCOND_V9
869 20984279U, // FCHKSM16
870 5172U, // FCMPD
871 4097U, // FCMPD_V9
872 20984298U, // FCMPEQ16
873 20984069U, // FCMPEQ32
874 20984317U, // FCMPGT16
875 20984088U, // FCMPGT32
876 20984225U, // FCMPLE16
877 20984015U, // FCMPLE32
878 20984235U, // FCMPNE16
879 20984025U, // FCMPNE32
880 5732U, // FCMPQ
881 4111U, // FCMPQ_V9
882 6139U, // FCMPS
883 4125U, // FCMPS_V9
884 20984923U, // FDIVD
885 20985471U, // FDIVQ
886 20985909U, // FDIVS
887 20985401U, // FDMULQ
888 2110683U, // FDTOI
889 2111048U, // FDTOQ
890 2111446U, // FDTOS
891 2111701U, // FDTOX
892 2110446U, // FEXPAND
893 20984712U, // FHADDD
894 20985712U, // FHADDS
895 20984675U, // FHSUBD
896 20985680U, // FHSUBS
897 2110479U, // FITOD
898 2111055U, // FITOQ
899 2111453U, // FITOS
900 419435579U, // FLCMPD
901 419436546U, // FLCMPS
902 2815U, // FLUSH
903 3366U, // FLUSHW
904 91293U, // FLUSHri
905 91293U, // FLUSHrr
906 692073369U, // FMADDD
907 692074369U, // FMADDS
908 20984289U, // FMEAN16
909 2110562U, // FMOVD
910 17923273U, // FMOVD_FCC
911 17202377U, // FMOVD_ICC
912 17464521U, // FMOVD_XCC
913 2111110U, // FMOVQ
914 17923327U, // FMOVQ_FCC
915 17202431U, // FMOVQ_ICC
916 17464575U, // FMOVQ_XCC
917 36034U, // FMOVRD
918 36088U, // FMOVRQ
919 36115U, // FMOVRS
920 2111548U, // FMOVS
921 17923354U, // FMOVS_FCC
922 17202458U, // FMOVS_ICC
923 17464602U, // FMOVS_XCC
924 692073323U, // FMSUBD
925 692074328U, // FMSUBS
926 20984375U, // FMUL8SUX16
927 20984350U, // FMUL8ULX16
928 20984327U, // FMUL8X16
929 20985169U, // FMUL8X16AL
930 20985948U, // FMUL8X16AU
931 20984769U, // FMULD
932 20984362U, // FMULD8SUX16
933 20984337U, // FMULD8ULX16
934 20985409U, // FMULQ
935 20985791U, // FMULS
936 20984746U, // FNADDD
937 20985746U, // FNADDS
938 20984807U, // FNAND
939 20985761U, // FNANDS
940 2110394U, // FNEGD
941 2111026U, // FNEGQ
942 2111416U, // FNEGS
943 20984720U, // FNHADDD
944 20985720U, // FNHADDS
945 692073377U, // FNMADDD
946 692074377U, // FNMADDS
947 692073331U, // FNMSUBD
948 692074336U, // FNMSUBS
949 20984776U, // FNMULD
950 20985798U, // FNMULS
951 20985514U, // FNOR
952 20985872U, // FNORS
953 2109597U, // FNOT1
954 2111210U, // FNOT1S
955 2109770U, // FNOT2
956 2111267U, // FNOT2S
957 20984792U, // FNSMULD
958 70780U, // FONE
959 71593U, // FONES
960 20985509U, // FOR
961 20983972U, // FORNOT1
962 20985586U, // FORNOT1S
963 20984145U, // FORNOT2
964 20985643U, // FORNOT2S
965 20985866U, // FORS
966 2109877U, // FPACK16
967 20984035U, // FPACK32
968 2111672U, // FPACKFIX
969 20984208U, // FPADD16
970 20985663U, // FPADD16S
971 20983998U, // FPADD32
972 20985606U, // FPADD32S
973 20984182U, // FPADD64
974 692074671U, // FPMADDX
975 692073648U, // FPMADDXHI
976 20984937U, // FPMERGE
977 20984199U, // FPSUB16
978 20985653U, // FPSUB16S
979 20983989U, // FPSUB32
980 20985596U, // FPSUB32S
981 2110486U, // FQTOD
982 2110690U, // FQTOI
983 2111460U, // FQTOS
984 2111717U, // FQTOX
985 20984308U, // FSLAS16
986 20984079U, // FSLAS32
987 20984263U, // FSLL16
988 20984053U, // FSLL32
989 20984784U, // FSMULD
990 2110542U, // FSQRTD
991 2111090U, // FSQRTQ
992 2111533U, // FSQRTS
993 20984191U, // FSRA16
994 20983981U, // FSRA32
995 2109566U, // FSRC1
996 2111191U, // FSRC1S
997 2109739U, // FSRC2
998 2111248U, // FSRC2S
999 20984271U, // FSRL16
1000 20984061U, // FSRL32
1001 2110493U, // FSTOD
1002 2110697U, // FSTOI
1003 2111062U, // FSTOQ
1004 2111724U, // FSTOX
1005 20984668U, // FSUBD
1006 20985372U, // FSUBQ
1007 20985673U, // FSUBS
1008 20985520U, // FXNOR
1009 20985879U, // FXNORS
1010 20985527U, // FXOR
1011 20985887U, // FXORS
1012 2110500U, // FXTOD
1013 2111069U, // FXTOQ
1014 2111476U, // FXTOS
1015 71160U, // FZERO
1016 71630U, // FZEROS
1017 154311839U, // GDOP_LDXrr
1018 154311789U, // GDOP_LDrr
1019 3381U, // INVALW
1020 2135413U, // JMPLri
1021 2135413U, // JMPLrr
1022 3054593U, // LDAri
1023 28285953U, // LDArr
1024 1272941U, // LDCSRri
1025 1272941U, // LDCSRrr
1026 3316845U, // LDCri
1027 3316845U, // LDCrr
1028 3054586U, // LDDAri
1029 28285946U, // LDDArr
1030 3316839U, // LDDCri
1031 3316839U, // LDDCrr
1032 3054586U, // LDDFAri
1033 28285946U, // LDDFArr
1034 3316839U, // LDDFri
1035 3316839U, // LDDFrr
1036 3316839U, // LDDri
1037 3316839U, // LDDrr
1038 3054593U, // LDFAri
1039 28285953U, // LDFArr
1040 1338477U, // LDFSRri
1041 1338477U, // LDFSRrr
1042 3316845U, // LDFri
1043 3316845U, // LDFrr
1044 3054635U, // LDQFAri
1045 28285995U, // LDQFArr
1046 3316882U, // LDQFri
1047 3316882U, // LDQFrr
1048 3054560U, // LDSBAri
1049 28285920U, // LDSBArr
1050 3316816U, // LDSBri
1051 3316816U, // LDSBrr
1052 3054611U, // LDSHAri
1053 28285971U, // LDSHArr
1054 3316861U, // LDSHri
1055 3316861U, // LDSHrr
1056 3054576U, // LDSTUBAri
1057 28285936U, // LDSTUBArr
1058 3316830U, // LDSTUBri
1059 3316830U, // LDSTUBrr
1060 3054649U, // LDSWAri
1061 28286009U, // LDSWArr
1062 3316888U, // LDSWri
1063 3316888U, // LDSWrr
1064 3054568U, // LDUBAri
1065 28285928U, // LDUBArr
1066 3316823U, // LDUBri
1067 3316823U, // LDUBrr
1068 3054619U, // LDUHAri
1069 28285979U, // LDUHArr
1070 3316868U, // LDUHri
1071 3316868U, // LDUHrr
1072 3054657U, // LDXAri
1073 28286017U, // LDXArr
1074 1338527U, // LDXFSRri
1075 1338527U, // LDXFSRrr
1076 3316895U, // LDXri
1077 3316895U, // LDXrr
1078 3316845U, // LDri
1079 3316845U, // LDrr
1080 2111560U, // LZCNT
1081 2852U, // MD5
1082 42637U, // MEMBARi
1083 71065U, // MONTMUL
1084 71369U, // MONTSQR
1085 2111708U, // MOVDTOX
1086 17923362U, // MOVFCCri
1087 17923362U, // MOVFCCrr
1088 17202466U, // MOVICCri
1089 17202466U, // MOVICCrr
1090 36110U, // MOVRri
1091 36110U, // MOVRrr
1092 2111624U, // MOVSTOSW
1093 2111641U, // MOVSTOUW
1094 2111467U, // MOVWTOS
1095 17464610U, // MOVXCCri
1096 17464610U, // MOVXCCrr
1097 2110507U, // MOVXTOD
1098 71052U, // MPMUL
1099 20984615U, // MULSCCri
1100 20984615U, // MULSCCrr
1101 20986063U, // MULXri
1102 20986063U, // MULXrr
1103 3316U, // NOP
1104 3373U, // NORMALW
1105 20984602U, // ORCCri
1106 20984602U, // ORCCrr
1107 20984593U, // ORNCCri
1108 20984593U, // ORNCCrr
1109 20985323U, // ORNri
1110 20985323U, // ORNrr
1111 20985510U, // ORri
1112 20985510U, // ORrr
1113 3388U, // OTHERW
1114 20985935U, // PDIST
1115 20985328U, // PDISTN
1116 2110287U, // POPCrr
1117 13528071U, // PREFETCHAi
1118 15690759U, // PREFETCHAr
1119 13790322U, // PREFETCHi
1120 13790322U, // PREFETCHr
1121 33560274U, // PWRPSRri
1122 33560274U, // PWRPSRrr
1123 2110531U, // RDASR
1124 69685U, // RDFQ
1125 2111165U, // RDPR
1126 69706U, // RDPSR
1127 69696U, // RDTBR
1128 69675U, // RDWIM
1129 3251U, // RESTORED
1130 20984962U, // RESTOREri
1131 20984962U, // RESTORErr
1132 72281U, // RET
1133 72290U, // RETL
1134 3395U, // RETRY
1135 92246U, // RETTri
1136 92246U, // RETTrr
1137 3260U, // SAVED
1138 20984971U, // SAVEri
1139 20984971U, // SAVErr
1140 20984623U, // SDIVCCri
1141 20984623U, // SDIVCCrr
1142 20986110U, // SDIVXri
1143 20986110U, // SDIVXrr
1144 20985960U, // SDIVri
1145 20985960U, // SDIVrr
1146 2110633U, // SETHIi
1147 2830U, // SHA1
1148 2856U, // SHA256
1149 2835U, // SHA512
1150 3307U, // SHUTDOWN
1151 71080U, // SIAM
1152 71328U, // SIR
1153 20986050U, // SLLXri
1154 20986050U, // SLLXrr
1155 20985200U, // SLLri
1156 20985200U, // SLLrr
1157 20984525U, // SMACri
1158 20984525U, // SMACrr
1159 20984569U, // SMULCCri
1160 20984569U, // SMULCCrr
1161 20985235U, // SMULri
1162 20985235U, // SMULrr
1163 20986019U, // SRAXri
1164 20986019U, // SRAXrr
1165 20984479U, // SRAri
1166 20984479U, // SRArr
1167 20986056U, // SRLXri
1168 20986056U, // SRLXrr
1169 20985223U, // SRLri
1170 20985223U, // SRLrr
1171 1422000U, // STAri
1172 11514544U, // STArr
1173 3333U, // STBAR
1174 1421959U, // STBAri
1175 11514503U, // STBArr
1176 1487547U, // STBri
1177 1487547U, // STBrr
1178 1469374U, // STCSRri
1179 1469374U, // STCSRrr
1180 1488978U, // STCri
1181 1488978U, // STCrr
1182 1421965U, // STDAri
1183 11514509U, // STDArr
1184 1469352U, // STDCQri
1185 1469352U, // STDCQrr
1186 1487958U, // STDCri
1187 1487958U, // STDCrr
1188 1421965U, // STDFAri
1189 11514509U, // STDFArr
1190 1469363U, // STDFQri
1191 1469363U, // STDFQrr
1192 1487958U, // STDFri
1193 1487958U, // STDFrr
1194 1487958U, // STDri
1195 1487958U, // STDrr
1196 1422000U, // STFAri
1197 11514544U, // STFArr
1198 1469385U, // STFSRri
1199 1469385U, // STFSRrr
1200 1488978U, // STFri
1201 1488978U, // STFrr
1202 1421971U, // STHAri
1203 11514515U, // STHArr
1204 1488036U, // STHri
1205 1488036U, // STHrr
1206 1421977U, // STQFAri
1207 11514521U, // STQFArr
1208 1488506U, // STQFri
1209 1488506U, // STQFrr
1210 1422005U, // STXAri
1211 11514549U, // STXArr
1212 1469396U, // STXFSRri
1213 1469396U, // STXFSRrr
1214 1489145U, // STXri
1215 1489145U, // STXrr
1216 1488978U, // STri
1217 1488978U, // STrr
1218 20984538U, // SUBCCri
1219 20984538U, // SUBCCrr
1220 20986025U, // SUBCri
1221 20986025U, // SUBCrr
1222 20984639U, // SUBEri
1223 20984639U, // SUBErr
1224 20984512U, // SUBri
1225 20984512U, // SUBrr
1226 3054627U, // SWAPAri
1227 28285987U, // SWAPArr
1228 3316875U, // SWAPri
1229 3316875U, // SWAPrr
1230 2825U, // TA1
1231 2842U, // TA3
1232 2847U, // TA5
1233 20985982U, // TADDCCTVri
1234 20985982U, // TADDCCTVrr
1235 20984554U, // TADDCCri
1236 20984554U, // TADDCCrr
1237 83306U, // TAIL_CALL
1238 91671U, // TAIL_CALLri
1239 52874528U, // TICCri
1240 52874528U, // TICCrr
1241 2705339260U, // TLS_ADDrr
1242 17770U, // TLS_CALL
1243 154311839U, // TLS_LDXrr
1244 154311789U, // TLS_LDrr
1245 52612384U, // TRAPri
1246 52612384U, // TRAPrr
1247 20985972U, // TSUBCCTVri
1248 20985972U, // TSUBCCTVrr
1249 20984537U, // TSUBCCri
1250 20984537U, // TSUBCCrr
1251 53136672U, // TXCCri
1252 53136672U, // TXCCrr
1253 20984631U, // UDIVCCri
1254 20984631U, // UDIVCCrr
1255 20986117U, // UDIVXri
1256 20986117U, // UDIVXrr
1257 20985966U, // UDIVri
1258 20985966U, // UDIVrr
1259 20984531U, // UMACri
1260 20984531U, // UMACrr
1261 20984577U, // UMULCCri
1262 20984577U, // UMULCCrr
1263 20985019U, // UMULXHI
1264 20985250U, // UMULri
1265 20985250U, // UMULrr
1266 71184U, // UNIMP
1267 419435572U, // V9FCMPD
1268 419435442U, // V9FCMPED
1269 419436074U, // V9FCMPEQ
1270 419436464U, // V9FCMPES
1271 419436132U, // V9FCMPQ
1272 419436539U, // V9FCMPS
1273 36041U, // V9FMOVD_FCC
1274 36095U, // V9FMOVQ_FCC
1275 36122U, // V9FMOVS_FCC
1276 36130U, // V9MOVFCCri
1277 36130U, // V9MOVFCCrr
1278 20985555U, // WRASRri
1279 20985555U, // WRASRrr
1280 20985539U, // WRPRri
1281 20985539U, // WRPRrr
1282 33560275U, // WRPSRri
1283 33560275U, // WRPSRrr
1284 67114707U, // WRTBRri
1285 67114707U, // WRTBRrr
1286 83891923U, // WRWIMri
1287 83891923U, // WRWIMrr
1288 20986062U, // XMULX
1289 20985028U, // XMULXHI
1290 20984600U, // XNORCCri
1291 20984600U, // XNORCCrr
1292 20985521U, // XNORri
1293 20985521U, // XNORrr
1294 20984608U, // XORCCri
1295 20984608U, // XORCCrr
1296 20985528U, // XORri
1297 20985528U, // XORrr
1298 };
1299
1300 // Emit the opcode for the instruction.
1301 uint32_t Bits = 0;
1302 Bits |= OpInfo0[MI.getOpcode()] << 0;
1303 if (Bits == 0)
1304 return {nullptr, Bits};
1305 return {AsmStrs+(Bits & 4095)-1, Bits};
1306
1307}
1308/// printInstruction - This method is automatically generated by tablegen
1309/// from the instruction set description.
1310LLVM_NO_PROFILE_INSTRUMENT_FUNCTION
1311void SparcInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) {
1312 O << "\t";
1313
1314 auto MnemonicInfo = getMnemonic(MI: *MI);
1315
1316 O << MnemonicInfo.first;
1317
1318 uint32_t Bits = MnemonicInfo.second;
1319 assert(Bits != 0 && "Cannot print this instruction.");
1320
1321 // Fragment 0 encoded into 4 bits for 13 unique commands.
1322 switch ((Bits >> 12) & 15) {
1323 default: llvm_unreachable("Invalid command number.");
1324 case 0:
1325 // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
1326 return;
1327 break;
1328 case 1:
1329 // ADJCALLSTACKDOWN, ADJCALLSTACKUP, CMASK16, CMASK32, CMASK8, FCMPD, FCM...
1330 printOperand(MI, opNum: 0, STI, OS&: O);
1331 break;
1332 case 2:
1333 // GETPCX
1334 printGetPCX(MI, OpNo: 0, STI, OS&: O);
1335 return;
1336 break;
1337 case 3:
1338 // SET, SETSW, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, AD...
1339 printOperand(MI, opNum: 1, STI, OS&: O);
1340 break;
1341 case 4:
1342 // BA, CALL, CALLi, TAIL_CALL, TLS_CALL
1343 printCTILabel(MI, Address, OpNum: 0, STI, O);
1344 break;
1345 case 5:
1346 // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
1347 printCCOperand(MI, opNum: 1, STI, OS&: O);
1348 break;
1349 case 6:
1350 // BINDri, BINDrr, CALLri, CALLrii, CALLrr, CALLrri, FLUSHri, FLUSHrr, LD...
1351 printMemOperand(MI, opNum: 0, STI, OS&: O);
1352 break;
1353 case 7:
1354 // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
1355 printCCOperand(MI, opNum: 3, STI, OS&: O);
1356 break;
1357 case 8:
1358 // FMOVRD, FMOVRQ, FMOVRS, MOVRri, MOVRrr, V9FMOVD_FCC, V9FMOVQ_FCC, V9FM...
1359 printCCOperand(MI, opNum: 4, STI, OS&: O);
1360 O << ' ';
1361 printOperand(MI, opNum: 1, STI, OS&: O);
1362 O << ", ";
1363 printOperand(MI, opNum: 2, STI, OS&: O);
1364 O << ", ";
1365 printOperand(MI, opNum: 0, STI, OS&: O);
1366 return;
1367 break;
1368 case 9:
1369 // GDOP_LDXrr, GDOP_LDrr, JMPLri, JMPLrr, LDAri, LDArr, LDCri, LDCrr, LDD...
1370 printMemOperand(MI, opNum: 1, STI, OS&: O);
1371 break;
1372 case 10:
1373 // MEMBARi
1374 printMembarTag(MI, opNum: 0, STI, O);
1375 return;
1376 break;
1377 case 11:
1378 // STAri, STArr, STBAri, STBArr, STBri, STBrr, STCri, STCrr, STDAri, STDA...
1379 printOperand(MI, opNum: 2, STI, OS&: O);
1380 O << ", [";
1381 printMemOperand(MI, opNum: 0, STI, OS&: O);
1382 break;
1383 case 12:
1384 // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr
1385 printCCOperand(MI, opNum: 2, STI, OS&: O);
1386 break;
1387 }
1388
1389
1390 // Fragment 1 encoded into 5 bits for 23 unique commands.
1391 switch ((Bits >> 16) & 31) {
1392 default: llvm_unreachable("Invalid command number.");
1393 case 0:
1394 // ADJCALLSTACKDOWN, SET, SETSW, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ...
1395 O << ", ";
1396 break;
1397 case 1:
1398 // ADJCALLSTACKUP, BA, BINDri, BINDrr, CALL, CALLri, CALLrr, CMASK16, CMA...
1399 return;
1400 break;
1401 case 2:
1402 // BCOND, BPFCC, BPR, CPBCOND, CWBCONDri, CWBCONDrr, CXBCONDri, CXBCONDrr...
1403 O << ' ';
1404 break;
1405 case 3:
1406 // BCONDA, BPFCCA, BPRA, CPBCONDA, FBCONDA
1407 O << ",a ";
1408 break;
1409 case 4:
1410 // BPFCCANT, BPRANT
1411 O << ",a,pn ";
1412 printOperand(MI, opNum: 2, STI, OS&: O);
1413 O << ", ";
1414 printCTILabel(MI, Address, OpNum: 0, STI, O);
1415 return;
1416 break;
1417 case 5:
1418 // BPFCCNT, BPRNT
1419 O << ",pn ";
1420 printOperand(MI, opNum: 2, STI, OS&: O);
1421 O << ", ";
1422 printCTILabel(MI, Address, OpNum: 0, STI, O);
1423 return;
1424 break;
1425 case 6:
1426 // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
1427 O << " %icc, ";
1428 break;
1429 case 7:
1430 // BPICCA
1431 O << ",a %icc, ";
1432 printCTILabel(MI, Address, OpNum: 0, STI, O);
1433 return;
1434 break;
1435 case 8:
1436 // BPICCANT
1437 O << ",a,pn %icc, ";
1438 printCTILabel(MI, Address, OpNum: 0, STI, O);
1439 return;
1440 break;
1441 case 9:
1442 // BPICCNT
1443 O << ",pn %icc, ";
1444 printCTILabel(MI, Address, OpNum: 0, STI, O);
1445 return;
1446 break;
1447 case 10:
1448 // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
1449 O << " %xcc, ";
1450 break;
1451 case 11:
1452 // BPXCCA
1453 O << ",a %xcc, ";
1454 printCTILabel(MI, Address, OpNum: 0, STI, O);
1455 return;
1456 break;
1457 case 12:
1458 // BPXCCANT
1459 O << ",a,pn %xcc, ";
1460 printCTILabel(MI, Address, OpNum: 0, STI, O);
1461 return;
1462 break;
1463 case 13:
1464 // BPXCCNT
1465 O << ",pn %xcc, ";
1466 printCTILabel(MI, Address, OpNum: 0, STI, O);
1467 return;
1468 break;
1469 case 14:
1470 // CASAri, CASXAri, LDAri, LDDAri, LDDFAri, LDFAri, LDQFAri, LDSBAri, LDS...
1471 O << "] %asi, ";
1472 break;
1473 case 15:
1474 // CASArr, CASXArr, LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDS...
1475 O << "] ";
1476 break;
1477 case 16:
1478 // FBCONDA_V9
1479 O << ",a %fcc0, ";
1480 printCTILabel(MI, Address, OpNum: 0, STI, O);
1481 return;
1482 break;
1483 case 17:
1484 // FBCOND_V9, FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1485 O << " %fcc0, ";
1486 break;
1487 case 18:
1488 // GDOP_LDXrr, GDOP_LDrr, LDCri, LDCrr, LDDCri, LDDCrr, LDDFri, LDDFrr, L...
1489 O << "], ";
1490 break;
1491 case 19:
1492 // LDCSRri, LDCSRrr
1493 O << "], %csr";
1494 return;
1495 break;
1496 case 20:
1497 // LDFSRri, LDFSRrr, LDXFSRri, LDXFSRrr
1498 O << "], %fsr";
1499 return;
1500 break;
1501 case 21:
1502 // STAri, STBAri, STDAri, STDFAri, STFAri, STHAri, STQFAri, STXAri
1503 O << "] %asi";
1504 return;
1505 break;
1506 case 22:
1507 // STBri, STBrr, STCSRri, STCSRrr, STCri, STCrr, STDCQri, STDCQrr, STDCri...
1508 O << ']';
1509 return;
1510 break;
1511 }
1512
1513
1514 // Fragment 2 encoded into 3 bits for 8 unique commands.
1515 switch ((Bits >> 21) & 7) {
1516 default: llvm_unreachable("Invalid command number.");
1517 case 0:
1518 // ADJCALLSTACKDOWN, CALLi, FCMPD, FCMPD_V9, FCMPQ, FCMPQ_V9, FCMPS, FCMP...
1519 printOperand(MI, opNum: 1, STI, OS&: O);
1520 break;
1521 case 1:
1522 // SET, SETSW, DES_IIP, DES_IP, FABSD, FABSQ, FABSS, FDTOI, FDTOQ, FDTOS,...
1523 printOperand(MI, opNum: 0, STI, OS&: O);
1524 break;
1525 case 2:
1526 // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1527 printOperand(MI, opNum: 2, STI, OS&: O);
1528 break;
1529 case 3:
1530 // BCOND, BCONDA, BPICC, BPXCC, CPBCOND, CPBCONDA, FBCOND, FBCONDA, FBCON...
1531 printCTILabel(MI, Address, OpNum: 0, STI, O);
1532 return;
1533 break;
1534 case 4:
1535 // CASArr, CASXArr
1536 printASITag(MI, opNum: 4, STI, O);
1537 O << ", ";
1538 printOperand(MI, opNum: 2, STI, OS&: O);
1539 O << ", ";
1540 printOperand(MI, opNum: 0, STI, OS&: O);
1541 return;
1542 break;
1543 case 5:
1544 // LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDSHArr, LDSTUBArr, ...
1545 printASITag(MI, opNum: 3, STI, O);
1546 break;
1547 case 6:
1548 // PREFETCHAi, PREFETCHi, PREFETCHr
1549 printPrefetchTag(MI, opNum: 2, STI, O);
1550 return;
1551 break;
1552 case 7:
1553 // PREFETCHAr
1554 printASITag(MI, opNum: 2, STI, O);
1555 O << ", ";
1556 printPrefetchTag(MI, opNum: 3, STI, O);
1557 return;
1558 break;
1559 }
1560
1561
1562 // Fragment 3 encoded into 3 bits for 6 unique commands.
1563 switch ((Bits >> 24) & 7) {
1564 default: llvm_unreachable("Invalid command number.");
1565 case 0:
1566 // ADJCALLSTACKDOWN, SET, SETSW, CALLi, CALLrii, CALLrri, DES_IIP, DES_IP...
1567 return;
1568 break;
1569 case 1:
1570 // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1571 O << ", ";
1572 break;
1573 case 2:
1574 // PWRPSRri, PWRPSRrr, WRPSRri, WRPSRrr
1575 O << ", %psr";
1576 return;
1577 break;
1578 case 3:
1579 // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr
1580 O << " + ";
1581 printOperand(MI, opNum: 1, STI, OS&: O);
1582 return;
1583 break;
1584 case 4:
1585 // WRTBRri, WRTBRrr
1586 O << ", %tbr";
1587 return;
1588 break;
1589 case 5:
1590 // WRWIMri, WRWIMrr
1591 O << ", %wim";
1592 return;
1593 break;
1594 }
1595
1596
1597 // Fragment 4 encoded into 2 bits for 4 unique commands.
1598 switch ((Bits >> 27) & 3) {
1599 default: llvm_unreachable("Invalid command number.");
1600 case 0:
1601 // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1602 printOperand(MI, opNum: 0, STI, OS&: O);
1603 break;
1604 case 1:
1605 // AES_DROUND01, AES_DROUND01_LAST, AES_DROUND23, AES_DROUND23_LAST, AES_...
1606 printOperand(MI, opNum: 3, STI, OS&: O);
1607 break;
1608 case 2:
1609 // BPFCC, BPFCCA, BPR, BPRA
1610 printCTILabel(MI, Address, OpNum: 0, STI, O);
1611 return;
1612 break;
1613 case 3:
1614 // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1615 printOperand(MI, opNum: 2, STI, OS&: O);
1616 return;
1617 break;
1618 }
1619
1620
1621 // Fragment 5 encoded into 1 bits for 2 unique commands.
1622 if ((Bits >> 29) & 1) {
1623 // AES_DROUND01, AES_DROUND01_LAST, AES_DROUND23, AES_DROUND23_LAST, AES_...
1624 O << ", ";
1625 } else {
1626 // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1627 return;
1628 }
1629
1630
1631 // Fragment 6 encoded into 2 bits for 3 unique commands.
1632 switch ((Bits >> 30) & 3) {
1633 default: llvm_unreachable("Invalid command number.");
1634 case 0:
1635 // AES_DROUND01, AES_DROUND01_LAST, AES_DROUND23, AES_DROUND23_LAST, AES_...
1636 printOperand(MI, opNum: 0, STI, OS&: O);
1637 return;
1638 break;
1639 case 1:
1640 // CWBCONDri, CWBCONDrr, CXBCONDri, CXBCONDrr
1641 printCTILabel(MI, Address, OpNum: 0, STI, O);
1642 return;
1643 break;
1644 case 2:
1645 // TLS_ADDrr
1646 printOperand(MI, opNum: 3, STI, OS&: O);
1647 return;
1648 break;
1649 }
1650
1651}
1652
1653
1654/// getRegisterName - This method is automatically generated by tblgen
1655/// from the register set description. This returns the assembler name
1656/// for the specified register.
1657const char *SparcInstPrinter::
1658getRegisterName(MCRegister Reg, unsigned AltIdx) {
1659 unsigned RegNo = Reg.id();
1660 assert(RegNo && RegNo < 238 && "Invalid register number!");
1661
1662
1663#ifdef __GNUC__
1664#pragma GCC diagnostic push
1665#pragma GCC diagnostic ignored "-Woverlength-strings"
1666#endif
1667 static const char AsmStrsNoRegAltName[] = {
1668 /* 0 */ "c10\000"
1669 /* 4 */ "f10\000"
1670 /* 8 */ "asr10\000"
1671 /* 14 */ "c20\000"
1672 /* 18 */ "f20\000"
1673 /* 22 */ "asr20\000"
1674 /* 28 */ "c30\000"
1675 /* 32 */ "f30\000"
1676 /* 36 */ "asr30\000"
1677 /* 42 */ "f40\000"
1678 /* 46 */ "f50\000"
1679 /* 50 */ "f60\000"
1680 /* 54 */ "fcc0\000"
1681 /* 59 */ "f0\000"
1682 /* 62 */ "g0\000"
1683 /* 65 */ "i0\000"
1684 /* 68 */ "l0\000"
1685 /* 71 */ "o0\000"
1686 /* 74 */ "c11\000"
1687 /* 78 */ "f11\000"
1688 /* 82 */ "asr11\000"
1689 /* 88 */ "c21\000"
1690 /* 92 */ "f21\000"
1691 /* 96 */ "asr21\000"
1692 /* 102 */ "c31\000"
1693 /* 106 */ "f31\000"
1694 /* 110 */ "asr31\000"
1695 /* 116 */ "fcc1\000"
1696 /* 121 */ "f1\000"
1697 /* 124 */ "g1\000"
1698 /* 127 */ "i1\000"
1699 /* 130 */ "l1\000"
1700 /* 133 */ "o1\000"
1701 /* 136 */ "asr1\000"
1702 /* 141 */ "c12\000"
1703 /* 145 */ "f12\000"
1704 /* 149 */ "asr12\000"
1705 /* 155 */ "c22\000"
1706 /* 159 */ "f22\000"
1707 /* 163 */ "asr22\000"
1708 /* 169 */ "f32\000"
1709 /* 173 */ "f42\000"
1710 /* 177 */ "f52\000"
1711 /* 181 */ "f62\000"
1712 /* 185 */ "fcc2\000"
1713 /* 190 */ "f2\000"
1714 /* 193 */ "g2\000"
1715 /* 196 */ "i2\000"
1716 /* 199 */ "l2\000"
1717 /* 202 */ "o2\000"
1718 /* 205 */ "asr2\000"
1719 /* 210 */ "c13\000"
1720 /* 214 */ "f13\000"
1721 /* 218 */ "asr13\000"
1722 /* 224 */ "c23\000"
1723 /* 228 */ "f23\000"
1724 /* 232 */ "asr23\000"
1725 /* 238 */ "fcc3\000"
1726 /* 243 */ "f3\000"
1727 /* 246 */ "g3\000"
1728 /* 249 */ "i3\000"
1729 /* 252 */ "l3\000"
1730 /* 255 */ "o3\000"
1731 /* 258 */ "asr3\000"
1732 /* 263 */ "c14\000"
1733 /* 267 */ "f14\000"
1734 /* 271 */ "asr14\000"
1735 /* 277 */ "c24\000"
1736 /* 281 */ "f24\000"
1737 /* 285 */ "asr24\000"
1738 /* 291 */ "f34\000"
1739 /* 295 */ "f44\000"
1740 /* 299 */ "f54\000"
1741 /* 303 */ "c4\000"
1742 /* 306 */ "f4\000"
1743 /* 309 */ "g4\000"
1744 /* 312 */ "i4\000"
1745 /* 315 */ "l4\000"
1746 /* 318 */ "o4\000"
1747 /* 321 */ "asr4\000"
1748 /* 326 */ "c15\000"
1749 /* 330 */ "f15\000"
1750 /* 334 */ "asr15\000"
1751 /* 340 */ "c25\000"
1752 /* 344 */ "f25\000"
1753 /* 348 */ "asr25\000"
1754 /* 354 */ "c5\000"
1755 /* 357 */ "f5\000"
1756 /* 360 */ "g5\000"
1757 /* 363 */ "i5\000"
1758 /* 366 */ "l5\000"
1759 /* 369 */ "o5\000"
1760 /* 372 */ "asr5\000"
1761 /* 377 */ "c16\000"
1762 /* 381 */ "f16\000"
1763 /* 385 */ "asr16\000"
1764 /* 391 */ "c26\000"
1765 /* 395 */ "f26\000"
1766 /* 399 */ "asr26\000"
1767 /* 405 */ "f36\000"
1768 /* 409 */ "f46\000"
1769 /* 413 */ "f56\000"
1770 /* 417 */ "c6\000"
1771 /* 420 */ "f6\000"
1772 /* 423 */ "g6\000"
1773 /* 426 */ "i6\000"
1774 /* 429 */ "l6\000"
1775 /* 432 */ "o6\000"
1776 /* 435 */ "asr6\000"
1777 /* 440 */ "c17\000"
1778 /* 444 */ "f17\000"
1779 /* 448 */ "asr17\000"
1780 /* 454 */ "c27\000"
1781 /* 458 */ "f27\000"
1782 /* 462 */ "asr27\000"
1783 /* 468 */ "c7\000"
1784 /* 471 */ "f7\000"
1785 /* 474 */ "g7\000"
1786 /* 477 */ "i7\000"
1787 /* 480 */ "l7\000"
1788 /* 483 */ "o7\000"
1789 /* 486 */ "asr7\000"
1790 /* 491 */ "c18\000"
1791 /* 495 */ "f18\000"
1792 /* 499 */ "asr18\000"
1793 /* 505 */ "c28\000"
1794 /* 509 */ "f28\000"
1795 /* 513 */ "asr28\000"
1796 /* 519 */ "f38\000"
1797 /* 523 */ "f48\000"
1798 /* 527 */ "f58\000"
1799 /* 531 */ "c8\000"
1800 /* 534 */ "f8\000"
1801 /* 537 */ "asr8\000"
1802 /* 542 */ "c19\000"
1803 /* 546 */ "f19\000"
1804 /* 550 */ "asr19\000"
1805 /* 556 */ "c29\000"
1806 /* 560 */ "f29\000"
1807 /* 564 */ "asr29\000"
1808 /* 570 */ "c9\000"
1809 /* 573 */ "f9\000"
1810 /* 576 */ "asr9\000"
1811 /* 581 */ "tba\000"
1812 /* 585 */ "icc\000"
1813 /* 589 */ "tnpc\000"
1814 /* 594 */ "tpc\000"
1815 /* 598 */ "canrestore\000"
1816 /* 609 */ "pstate\000"
1817 /* 616 */ "tstate\000"
1818 /* 623 */ "wstate\000"
1819 /* 630 */ "cansave\000"
1820 /* 638 */ "tick\000"
1821 /* 643 */ "gl\000"
1822 /* 646 */ "pil\000"
1823 /* 650 */ "tl\000"
1824 /* 653 */ "wim\000"
1825 /* 657 */ "cleanwin\000"
1826 /* 666 */ "otherwin\000"
1827 /* 675 */ "fp\000"
1828 /* 678 */ "sp\000"
1829 /* 681 */ "cwp\000"
1830 /* 685 */ "cq\000"
1831 /* 688 */ "fq\000"
1832 /* 691 */ "tbr\000"
1833 /* 695 */ "ver\000"
1834 /* 699 */ "csr\000"
1835 /* 703 */ "fsr\000"
1836 /* 707 */ "psr\000"
1837 /* 711 */ "tt\000"
1838 /* 714 */ "y\000"
1839};
1840#ifdef __GNUC__
1841#pragma GCC diagnostic pop
1842#endif
1843
1844 static const uint16_t RegAsmOffsetNoRegAltName[] = {
1845 598, 630, 657, 685, 699, 681, 688, 703, 643, 585, 666, 646, 707, 609,
1846 581, 691, 638, 650, 589, 594, 616, 711, 695, 653, 623, 714, 136, 205,
1847 258, 321, 372, 435, 486, 537, 576, 8, 82, 149, 218, 271, 334, 385,
1848 448, 499, 550, 22, 96, 163, 232, 285, 348, 399, 462, 513, 564, 36,
1849 110, 56, 118, 187, 240, 303, 354, 417, 468, 531, 570, 0, 74, 141,
1850 210, 263, 326, 377, 440, 491, 542, 14, 88, 155, 224, 277, 340, 391,
1851 454, 505, 556, 28, 102, 59, 190, 306, 420, 534, 4, 145, 267, 381,
1852 495, 18, 159, 281, 395, 509, 32, 169, 291, 405, 519, 42, 173, 295,
1853 409, 523, 46, 177, 299, 413, 527, 50, 181, 59, 121, 190, 243, 306,
1854 357, 420, 471, 534, 573, 4, 78, 145, 214, 267, 330, 381, 444, 495,
1855 546, 18, 92, 159, 228, 281, 344, 395, 458, 509, 560, 32, 106, 54,
1856 116, 185, 238, 62, 124, 193, 246, 309, 360, 423, 474, 65, 127, 196,
1857 249, 312, 363, 675, 477, 68, 130, 199, 252, 315, 366, 429, 480, 71,
1858 133, 202, 255, 318, 369, 678, 483, 59, 306, 534, 145, 381, 18, 281,
1859 509, 169, 405, 42, 295, 523, 177, 413, 50, 56, 187, 303, 417, 531,
1860 0, 141, 263, 377, 491, 14, 155, 277, 391, 505, 28, 62, 193, 309,
1861 423, 65, 196, 312, 426, 68, 199, 315, 429, 71, 202, 318, 432,
1862 };
1863
1864
1865#ifdef __GNUC__
1866#pragma GCC diagnostic push
1867#pragma GCC diagnostic ignored "-Woverlength-strings"
1868#endif
1869 static const char AsmStrsRegNamesStateReg[] = {
1870 /* 0 */ "pc\000"
1871 /* 3 */ "asi\000"
1872 /* 7 */ "tick\000"
1873 /* 12 */ "ccr\000"
1874 /* 16 */ "fprs\000"
1875};
1876#ifdef __GNUC__
1877#pragma GCC diagnostic pop
1878#endif
1879
1880 static const uint8_t RegAsmOffsetRegNamesStateReg[] = {
1881 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1882 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 12,
1883 3, 7, 0, 16, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1884 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1885 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1886 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1887 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1888 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1889 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1890 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1891 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1892 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1893 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1894 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1895 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1896 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1897 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1898 };
1899
1900 switch(AltIdx) {
1901 default: llvm_unreachable("Invalid register alt name index!");
1902 case SP::NoRegAltName:
1903 assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) &&
1904 "Invalid alt name index for register!");
1905 return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
1906 case SP::RegNamesStateReg:
1907 if (!*(AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1]))
1908 return getRegisterName(Reg: RegNo, AltIdx: SP::NoRegAltName);
1909 return AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1];
1910 }
1911}
1912
1913#ifdef PRINT_ALIAS_INSTR
1914#undef PRINT_ALIAS_INSTR
1915
1916bool SparcInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS) {
1917 static const PatternsForOpcode OpToPatterns[] = {
1918 {.Opcode: SP::BCOND, .PatternStart: 0, .NumPatterns: 16 },
1919 {.Opcode: SP::BCONDA, .PatternStart: 16, .NumPatterns: 16 },
1920 {.Opcode: SP::BPFCCANT, .PatternStart: 32, .NumPatterns: 16 },
1921 {.Opcode: SP::BPFCCNT, .PatternStart: 48, .NumPatterns: 16 },
1922 {.Opcode: SP::BPICCANT, .PatternStart: 64, .NumPatterns: 32 },
1923 {.Opcode: SP::BPICCNT, .PatternStart: 96, .NumPatterns: 32 },
1924 {.Opcode: SP::BPRANT, .PatternStart: 128, .NumPatterns: 4 },
1925 {.Opcode: SP::BPRNT, .PatternStart: 132, .NumPatterns: 4 },
1926 {.Opcode: SP::CASArr, .PatternStart: 136, .NumPatterns: 2 },
1927 {.Opcode: SP::CASXArr, .PatternStart: 138, .NumPatterns: 2 },
1928 {.Opcode: SP::CWBCONDri, .PatternStart: 140, .NumPatterns: 14 },
1929 {.Opcode: SP::CWBCONDrr, .PatternStart: 154, .NumPatterns: 14 },
1930 {.Opcode: SP::CXBCONDri, .PatternStart: 168, .NumPatterns: 14 },
1931 {.Opcode: SP::CXBCONDrr, .PatternStart: 182, .NumPatterns: 14 },
1932 {.Opcode: SP::FMOVD_ICC, .PatternStart: 196, .NumPatterns: 32 },
1933 {.Opcode: SP::FMOVQ_ICC, .PatternStart: 228, .NumPatterns: 32 },
1934 {.Opcode: SP::FMOVRD, .PatternStart: 260, .NumPatterns: 4 },
1935 {.Opcode: SP::FMOVRQ, .PatternStart: 264, .NumPatterns: 4 },
1936 {.Opcode: SP::FMOVRS, .PatternStart: 268, .NumPatterns: 4 },
1937 {.Opcode: SP::FMOVS_ICC, .PatternStart: 272, .NumPatterns: 32 },
1938 {.Opcode: SP::MOVICCri, .PatternStart: 304, .NumPatterns: 32 },
1939 {.Opcode: SP::MOVICCrr, .PatternStart: 336, .NumPatterns: 32 },
1940 {.Opcode: SP::MOVRri, .PatternStart: 368, .NumPatterns: 4 },
1941 {.Opcode: SP::MOVRrr, .PatternStart: 372, .NumPatterns: 4 },
1942 {.Opcode: SP::ORCCrr, .PatternStart: 376, .NumPatterns: 1 },
1943 {.Opcode: SP::ORri, .PatternStart: 377, .NumPatterns: 1 },
1944 {.Opcode: SP::ORrr, .PatternStart: 378, .NumPatterns: 1 },
1945 {.Opcode: SP::RESTORErr, .PatternStart: 379, .NumPatterns: 1 },
1946 {.Opcode: SP::RET, .PatternStart: 380, .NumPatterns: 1 },
1947 {.Opcode: SP::RETL, .PatternStart: 381, .NumPatterns: 1 },
1948 {.Opcode: SP::SAVErr, .PatternStart: 382, .NumPatterns: 1 },
1949 {.Opcode: SP::SUBCCri, .PatternStart: 383, .NumPatterns: 1 },
1950 {.Opcode: SP::SUBCCrr, .PatternStart: 384, .NumPatterns: 1 },
1951 {.Opcode: SP::TICCri, .PatternStart: 385, .NumPatterns: 64 },
1952 {.Opcode: SP::TICCrr, .PatternStart: 449, .NumPatterns: 64 },
1953 {.Opcode: SP::TRAPri, .PatternStart: 513, .NumPatterns: 32 },
1954 {.Opcode: SP::TRAPrr, .PatternStart: 545, .NumPatterns: 32 },
1955 {.Opcode: SP::TXCCri, .PatternStart: 577, .NumPatterns: 64 },
1956 {.Opcode: SP::TXCCrr, .PatternStart: 641, .NumPatterns: 64 },
1957 {.Opcode: SP::V9FCMPD, .PatternStart: 705, .NumPatterns: 1 },
1958 {.Opcode: SP::V9FCMPED, .PatternStart: 706, .NumPatterns: 1 },
1959 {.Opcode: SP::V9FCMPEQ, .PatternStart: 707, .NumPatterns: 1 },
1960 {.Opcode: SP::V9FCMPES, .PatternStart: 708, .NumPatterns: 1 },
1961 {.Opcode: SP::V9FCMPQ, .PatternStart: 709, .NumPatterns: 1 },
1962 {.Opcode: SP::V9FCMPS, .PatternStart: 710, .NumPatterns: 1 },
1963 {.Opcode: SP::V9FMOVD_FCC, .PatternStart: 711, .NumPatterns: 16 },
1964 {.Opcode: SP::V9FMOVQ_FCC, .PatternStart: 727, .NumPatterns: 16 },
1965 {.Opcode: SP::V9FMOVS_FCC, .PatternStart: 743, .NumPatterns: 16 },
1966 {.Opcode: SP::V9MOVFCCri, .PatternStart: 759, .NumPatterns: 16 },
1967 {.Opcode: SP::V9MOVFCCrr, .PatternStart: 775, .NumPatterns: 16 },
1968 {.Opcode: SP::WRASRri, .PatternStart: 791, .NumPatterns: 1 },
1969 {.Opcode: SP::WRASRrr, .PatternStart: 792, .NumPatterns: 1 },
1970 };
1971
1972 static const AliasPattern Patterns[] = {
1973 // SP::BCOND - 0
1974 {.AsmStrOffset: 0, .AliasCondStart: 0, .NumOperands: 2, .NumConds: 2 },
1975 {.AsmStrOffset: 8, .AliasCondStart: 2, .NumOperands: 2, .NumConds: 2 },
1976 {.AsmStrOffset: 16, .AliasCondStart: 4, .NumOperands: 2, .NumConds: 2 },
1977 {.AsmStrOffset: 25, .AliasCondStart: 6, .NumOperands: 2, .NumConds: 2 },
1978 {.AsmStrOffset: 33, .AliasCondStart: 8, .NumOperands: 2, .NumConds: 2 },
1979 {.AsmStrOffset: 41, .AliasCondStart: 10, .NumOperands: 2, .NumConds: 2 },
1980 {.AsmStrOffset: 50, .AliasCondStart: 12, .NumOperands: 2, .NumConds: 2 },
1981 {.AsmStrOffset: 59, .AliasCondStart: 14, .NumOperands: 2, .NumConds: 2 },
1982 {.AsmStrOffset: 67, .AliasCondStart: 16, .NumOperands: 2, .NumConds: 2 },
1983 {.AsmStrOffset: 76, .AliasCondStart: 18, .NumOperands: 2, .NumConds: 2 },
1984 {.AsmStrOffset: 86, .AliasCondStart: 20, .NumOperands: 2, .NumConds: 2 },
1985 {.AsmStrOffset: 95, .AliasCondStart: 22, .NumOperands: 2, .NumConds: 2 },
1986 {.AsmStrOffset: 104, .AliasCondStart: 24, .NumOperands: 2, .NumConds: 2 },
1987 {.AsmStrOffset: 114, .AliasCondStart: 26, .NumOperands: 2, .NumConds: 2 },
1988 {.AsmStrOffset: 124, .AliasCondStart: 28, .NumOperands: 2, .NumConds: 2 },
1989 {.AsmStrOffset: 133, .AliasCondStart: 30, .NumOperands: 2, .NumConds: 2 },
1990 // SP::BCONDA - 16
1991 {.AsmStrOffset: 142, .AliasCondStart: 32, .NumOperands: 2, .NumConds: 2 },
1992 {.AsmStrOffset: 152, .AliasCondStart: 34, .NumOperands: 2, .NumConds: 2 },
1993 {.AsmStrOffset: 162, .AliasCondStart: 36, .NumOperands: 2, .NumConds: 2 },
1994 {.AsmStrOffset: 173, .AliasCondStart: 38, .NumOperands: 2, .NumConds: 2 },
1995 {.AsmStrOffset: 183, .AliasCondStart: 40, .NumOperands: 2, .NumConds: 2 },
1996 {.AsmStrOffset: 193, .AliasCondStart: 42, .NumOperands: 2, .NumConds: 2 },
1997 {.AsmStrOffset: 204, .AliasCondStart: 44, .NumOperands: 2, .NumConds: 2 },
1998 {.AsmStrOffset: 215, .AliasCondStart: 46, .NumOperands: 2, .NumConds: 2 },
1999 {.AsmStrOffset: 225, .AliasCondStart: 48, .NumOperands: 2, .NumConds: 2 },
2000 {.AsmStrOffset: 236, .AliasCondStart: 50, .NumOperands: 2, .NumConds: 2 },
2001 {.AsmStrOffset: 248, .AliasCondStart: 52, .NumOperands: 2, .NumConds: 2 },
2002 {.AsmStrOffset: 259, .AliasCondStart: 54, .NumOperands: 2, .NumConds: 2 },
2003 {.AsmStrOffset: 270, .AliasCondStart: 56, .NumOperands: 2, .NumConds: 2 },
2004 {.AsmStrOffset: 282, .AliasCondStart: 58, .NumOperands: 2, .NumConds: 2 },
2005 {.AsmStrOffset: 294, .AliasCondStart: 60, .NumOperands: 2, .NumConds: 2 },
2006 {.AsmStrOffset: 305, .AliasCondStart: 62, .NumOperands: 2, .NumConds: 2 },
2007 // SP::BPFCCANT - 32
2008 {.AsmStrOffset: 316, .AliasCondStart: 64, .NumOperands: 3, .NumConds: 4 },
2009 {.AsmStrOffset: 334, .AliasCondStart: 68, .NumOperands: 3, .NumConds: 4 },
2010 {.AsmStrOffset: 352, .AliasCondStart: 72, .NumOperands: 3, .NumConds: 4 },
2011 {.AsmStrOffset: 370, .AliasCondStart: 76, .NumOperands: 3, .NumConds: 4 },
2012 {.AsmStrOffset: 388, .AliasCondStart: 80, .NumOperands: 3, .NumConds: 4 },
2013 {.AsmStrOffset: 407, .AliasCondStart: 84, .NumOperands: 3, .NumConds: 4 },
2014 {.AsmStrOffset: 425, .AliasCondStart: 88, .NumOperands: 3, .NumConds: 4 },
2015 {.AsmStrOffset: 444, .AliasCondStart: 92, .NumOperands: 3, .NumConds: 4 },
2016 {.AsmStrOffset: 463, .AliasCondStart: 96, .NumOperands: 3, .NumConds: 4 },
2017 {.AsmStrOffset: 482, .AliasCondStart: 100, .NumOperands: 3, .NumConds: 4 },
2018 {.AsmStrOffset: 500, .AliasCondStart: 104, .NumOperands: 3, .NumConds: 4 },
2019 {.AsmStrOffset: 519, .AliasCondStart: 108, .NumOperands: 3, .NumConds: 4 },
2020 {.AsmStrOffset: 538, .AliasCondStart: 112, .NumOperands: 3, .NumConds: 4 },
2021 {.AsmStrOffset: 558, .AliasCondStart: 116, .NumOperands: 3, .NumConds: 4 },
2022 {.AsmStrOffset: 577, .AliasCondStart: 120, .NumOperands: 3, .NumConds: 4 },
2023 {.AsmStrOffset: 597, .AliasCondStart: 124, .NumOperands: 3, .NumConds: 4 },
2024 // SP::BPFCCNT - 48
2025 {.AsmStrOffset: 615, .AliasCondStart: 128, .NumOperands: 3, .NumConds: 4 },
2026 {.AsmStrOffset: 631, .AliasCondStart: 132, .NumOperands: 3, .NumConds: 4 },
2027 {.AsmStrOffset: 647, .AliasCondStart: 136, .NumOperands: 3, .NumConds: 4 },
2028 {.AsmStrOffset: 663, .AliasCondStart: 140, .NumOperands: 3, .NumConds: 4 },
2029 {.AsmStrOffset: 679, .AliasCondStart: 144, .NumOperands: 3, .NumConds: 4 },
2030 {.AsmStrOffset: 696, .AliasCondStart: 148, .NumOperands: 3, .NumConds: 4 },
2031 {.AsmStrOffset: 712, .AliasCondStart: 152, .NumOperands: 3, .NumConds: 4 },
2032 {.AsmStrOffset: 729, .AliasCondStart: 156, .NumOperands: 3, .NumConds: 4 },
2033 {.AsmStrOffset: 746, .AliasCondStart: 160, .NumOperands: 3, .NumConds: 4 },
2034 {.AsmStrOffset: 763, .AliasCondStart: 164, .NumOperands: 3, .NumConds: 4 },
2035 {.AsmStrOffset: 779, .AliasCondStart: 168, .NumOperands: 3, .NumConds: 4 },
2036 {.AsmStrOffset: 796, .AliasCondStart: 172, .NumOperands: 3, .NumConds: 4 },
2037 {.AsmStrOffset: 813, .AliasCondStart: 176, .NumOperands: 3, .NumConds: 4 },
2038 {.AsmStrOffset: 831, .AliasCondStart: 180, .NumOperands: 3, .NumConds: 4 },
2039 {.AsmStrOffset: 848, .AliasCondStart: 184, .NumOperands: 3, .NumConds: 4 },
2040 {.AsmStrOffset: 866, .AliasCondStart: 188, .NumOperands: 3, .NumConds: 4 },
2041 // SP::BPICCANT - 64
2042 {.AsmStrOffset: 882, .AliasCondStart: 192, .NumOperands: 2, .NumConds: 3 },
2043 {.AsmStrOffset: 901, .AliasCondStart: 195, .NumOperands: 2, .NumConds: 4 },
2044 {.AsmStrOffset: 920, .AliasCondStart: 199, .NumOperands: 2, .NumConds: 3 },
2045 {.AsmStrOffset: 939, .AliasCondStart: 202, .NumOperands: 2, .NumConds: 4 },
2046 {.AsmStrOffset: 958, .AliasCondStart: 206, .NumOperands: 2, .NumConds: 3 },
2047 {.AsmStrOffset: 978, .AliasCondStart: 209, .NumOperands: 2, .NumConds: 4 },
2048 {.AsmStrOffset: 998, .AliasCondStart: 213, .NumOperands: 2, .NumConds: 3 },
2049 {.AsmStrOffset: 1017, .AliasCondStart: 216, .NumOperands: 2, .NumConds: 4 },
2050 {.AsmStrOffset: 1036, .AliasCondStart: 220, .NumOperands: 2, .NumConds: 3 },
2051 {.AsmStrOffset: 1055, .AliasCondStart: 223, .NumOperands: 2, .NumConds: 4 },
2052 {.AsmStrOffset: 1074, .AliasCondStart: 227, .NumOperands: 2, .NumConds: 3 },
2053 {.AsmStrOffset: 1094, .AliasCondStart: 230, .NumOperands: 2, .NumConds: 4 },
2054 {.AsmStrOffset: 1114, .AliasCondStart: 234, .NumOperands: 2, .NumConds: 3 },
2055 {.AsmStrOffset: 1134, .AliasCondStart: 237, .NumOperands: 2, .NumConds: 4 },
2056 {.AsmStrOffset: 1154, .AliasCondStart: 241, .NumOperands: 2, .NumConds: 3 },
2057 {.AsmStrOffset: 1173, .AliasCondStart: 244, .NumOperands: 2, .NumConds: 4 },
2058 {.AsmStrOffset: 1192, .AliasCondStart: 248, .NumOperands: 2, .NumConds: 3 },
2059 {.AsmStrOffset: 1212, .AliasCondStart: 251, .NumOperands: 2, .NumConds: 4 },
2060 {.AsmStrOffset: 1232, .AliasCondStart: 255, .NumOperands: 2, .NumConds: 3 },
2061 {.AsmStrOffset: 1253, .AliasCondStart: 258, .NumOperands: 2, .NumConds: 4 },
2062 {.AsmStrOffset: 1274, .AliasCondStart: 262, .NumOperands: 2, .NumConds: 3 },
2063 {.AsmStrOffset: 1294, .AliasCondStart: 265, .NumOperands: 2, .NumConds: 4 },
2064 {.AsmStrOffset: 1314, .AliasCondStart: 269, .NumOperands: 2, .NumConds: 3 },
2065 {.AsmStrOffset: 1334, .AliasCondStart: 272, .NumOperands: 2, .NumConds: 4 },
2066 {.AsmStrOffset: 1354, .AliasCondStart: 276, .NumOperands: 2, .NumConds: 3 },
2067 {.AsmStrOffset: 1375, .AliasCondStart: 279, .NumOperands: 2, .NumConds: 4 },
2068 {.AsmStrOffset: 1396, .AliasCondStart: 283, .NumOperands: 2, .NumConds: 3 },
2069 {.AsmStrOffset: 1417, .AliasCondStart: 286, .NumOperands: 2, .NumConds: 4 },
2070 {.AsmStrOffset: 1438, .AliasCondStart: 290, .NumOperands: 2, .NumConds: 3 },
2071 {.AsmStrOffset: 1458, .AliasCondStart: 293, .NumOperands: 2, .NumConds: 4 },
2072 {.AsmStrOffset: 1478, .AliasCondStart: 297, .NumOperands: 2, .NumConds: 3 },
2073 {.AsmStrOffset: 1498, .AliasCondStart: 300, .NumOperands: 2, .NumConds: 4 },
2074 // SP::BPICCNT - 96
2075 {.AsmStrOffset: 1518, .AliasCondStart: 304, .NumOperands: 2, .NumConds: 3 },
2076 {.AsmStrOffset: 1535, .AliasCondStart: 307, .NumOperands: 2, .NumConds: 4 },
2077 {.AsmStrOffset: 1552, .AliasCondStart: 311, .NumOperands: 2, .NumConds: 3 },
2078 {.AsmStrOffset: 1569, .AliasCondStart: 314, .NumOperands: 2, .NumConds: 4 },
2079 {.AsmStrOffset: 1586, .AliasCondStart: 318, .NumOperands: 2, .NumConds: 3 },
2080 {.AsmStrOffset: 1604, .AliasCondStart: 321, .NumOperands: 2, .NumConds: 4 },
2081 {.AsmStrOffset: 1622, .AliasCondStart: 325, .NumOperands: 2, .NumConds: 3 },
2082 {.AsmStrOffset: 1639, .AliasCondStart: 328, .NumOperands: 2, .NumConds: 4 },
2083 {.AsmStrOffset: 1656, .AliasCondStart: 332, .NumOperands: 2, .NumConds: 3 },
2084 {.AsmStrOffset: 1673, .AliasCondStart: 335, .NumOperands: 2, .NumConds: 4 },
2085 {.AsmStrOffset: 1690, .AliasCondStart: 339, .NumOperands: 2, .NumConds: 3 },
2086 {.AsmStrOffset: 1708, .AliasCondStart: 342, .NumOperands: 2, .NumConds: 4 },
2087 {.AsmStrOffset: 1726, .AliasCondStart: 346, .NumOperands: 2, .NumConds: 3 },
2088 {.AsmStrOffset: 1744, .AliasCondStart: 349, .NumOperands: 2, .NumConds: 4 },
2089 {.AsmStrOffset: 1762, .AliasCondStart: 353, .NumOperands: 2, .NumConds: 3 },
2090 {.AsmStrOffset: 1779, .AliasCondStart: 356, .NumOperands: 2, .NumConds: 4 },
2091 {.AsmStrOffset: 1796, .AliasCondStart: 360, .NumOperands: 2, .NumConds: 3 },
2092 {.AsmStrOffset: 1814, .AliasCondStart: 363, .NumOperands: 2, .NumConds: 4 },
2093 {.AsmStrOffset: 1832, .AliasCondStart: 367, .NumOperands: 2, .NumConds: 3 },
2094 {.AsmStrOffset: 1851, .AliasCondStart: 370, .NumOperands: 2, .NumConds: 4 },
2095 {.AsmStrOffset: 1870, .AliasCondStart: 374, .NumOperands: 2, .NumConds: 3 },
2096 {.AsmStrOffset: 1888, .AliasCondStart: 377, .NumOperands: 2, .NumConds: 4 },
2097 {.AsmStrOffset: 1906, .AliasCondStart: 381, .NumOperands: 2, .NumConds: 3 },
2098 {.AsmStrOffset: 1924, .AliasCondStart: 384, .NumOperands: 2, .NumConds: 4 },
2099 {.AsmStrOffset: 1942, .AliasCondStart: 388, .NumOperands: 2, .NumConds: 3 },
2100 {.AsmStrOffset: 1961, .AliasCondStart: 391, .NumOperands: 2, .NumConds: 4 },
2101 {.AsmStrOffset: 1980, .AliasCondStart: 395, .NumOperands: 2, .NumConds: 3 },
2102 {.AsmStrOffset: 1999, .AliasCondStart: 398, .NumOperands: 2, .NumConds: 4 },
2103 {.AsmStrOffset: 2018, .AliasCondStart: 402, .NumOperands: 2, .NumConds: 3 },
2104 {.AsmStrOffset: 2036, .AliasCondStart: 405, .NumOperands: 2, .NumConds: 4 },
2105 {.AsmStrOffset: 2054, .AliasCondStart: 409, .NumOperands: 2, .NumConds: 3 },
2106 {.AsmStrOffset: 2072, .AliasCondStart: 412, .NumOperands: 2, .NumConds: 4 },
2107 // SP::BPRANT - 128
2108 {.AsmStrOffset: 2090, .AliasCondStart: 416, .NumOperands: 3, .NumConds: 4 },
2109 {.AsmStrOffset: 2110, .AliasCondStart: 420, .NumOperands: 3, .NumConds: 4 },
2110 {.AsmStrOffset: 2129, .AliasCondStart: 424, .NumOperands: 3, .NumConds: 4 },
2111 {.AsmStrOffset: 2148, .AliasCondStart: 428, .NumOperands: 3, .NumConds: 4 },
2112 // SP::BPRNT - 132
2113 {.AsmStrOffset: 2168, .AliasCondStart: 432, .NumOperands: 3, .NumConds: 4 },
2114 {.AsmStrOffset: 2186, .AliasCondStart: 436, .NumOperands: 3, .NumConds: 4 },
2115 {.AsmStrOffset: 2203, .AliasCondStart: 440, .NumOperands: 3, .NumConds: 4 },
2116 {.AsmStrOffset: 2220, .AliasCondStart: 444, .NumOperands: 3, .NumConds: 4 },
2117 // SP::CASArr - 136
2118 {.AsmStrOffset: 2238, .AliasCondStart: 448, .NumOperands: 5, .NumConds: 6 },
2119 {.AsmStrOffset: 2255, .AliasCondStart: 454, .NumOperands: 5, .NumConds: 6 },
2120 // SP::CASXArr - 138
2121 {.AsmStrOffset: 2273, .AliasCondStart: 460, .NumOperands: 5, .NumConds: 6 },
2122 {.AsmStrOffset: 2291, .AliasCondStart: 466, .NumOperands: 5, .NumConds: 6 },
2123 // SP::CWBCONDri - 140
2124 {.AsmStrOffset: 2310, .AliasCondStart: 472, .NumOperands: 4, .NumConds: 4 },
2125 {.AsmStrOffset: 2329, .AliasCondStart: 476, .NumOperands: 4, .NumConds: 4 },
2126 {.AsmStrOffset: 2347, .AliasCondStart: 480, .NumOperands: 4, .NumConds: 4 },
2127 {.AsmStrOffset: 2365, .AliasCondStart: 484, .NumOperands: 4, .NumConds: 4 },
2128 {.AsmStrOffset: 2384, .AliasCondStart: 488, .NumOperands: 4, .NumConds: 4 },
2129 {.AsmStrOffset: 2403, .AliasCondStart: 492, .NumOperands: 4, .NumConds: 4 },
2130 {.AsmStrOffset: 2421, .AliasCondStart: 496, .NumOperands: 4, .NumConds: 4 },
2131 {.AsmStrOffset: 2440, .AliasCondStart: 500, .NumOperands: 4, .NumConds: 4 },
2132 {.AsmStrOffset: 2460, .AliasCondStart: 504, .NumOperands: 4, .NumConds: 4 },
2133 {.AsmStrOffset: 2479, .AliasCondStart: 508, .NumOperands: 4, .NumConds: 4 },
2134 {.AsmStrOffset: 2498, .AliasCondStart: 512, .NumOperands: 4, .NumConds: 4 },
2135 {.AsmStrOffset: 2518, .AliasCondStart: 516, .NumOperands: 4, .NumConds: 4 },
2136 {.AsmStrOffset: 2538, .AliasCondStart: 520, .NumOperands: 4, .NumConds: 4 },
2137 {.AsmStrOffset: 2557, .AliasCondStart: 524, .NumOperands: 4, .NumConds: 4 },
2138 // SP::CWBCONDrr - 154
2139 {.AsmStrOffset: 2310, .AliasCondStart: 528, .NumOperands: 4, .NumConds: 5 },
2140 {.AsmStrOffset: 2329, .AliasCondStart: 533, .NumOperands: 4, .NumConds: 5 },
2141 {.AsmStrOffset: 2347, .AliasCondStart: 538, .NumOperands: 4, .NumConds: 5 },
2142 {.AsmStrOffset: 2365, .AliasCondStart: 543, .NumOperands: 4, .NumConds: 5 },
2143 {.AsmStrOffset: 2384, .AliasCondStart: 548, .NumOperands: 4, .NumConds: 5 },
2144 {.AsmStrOffset: 2403, .AliasCondStart: 553, .NumOperands: 4, .NumConds: 5 },
2145 {.AsmStrOffset: 2421, .AliasCondStart: 558, .NumOperands: 4, .NumConds: 5 },
2146 {.AsmStrOffset: 2440, .AliasCondStart: 563, .NumOperands: 4, .NumConds: 5 },
2147 {.AsmStrOffset: 2460, .AliasCondStart: 568, .NumOperands: 4, .NumConds: 5 },
2148 {.AsmStrOffset: 2479, .AliasCondStart: 573, .NumOperands: 4, .NumConds: 5 },
2149 {.AsmStrOffset: 2498, .AliasCondStart: 578, .NumOperands: 4, .NumConds: 5 },
2150 {.AsmStrOffset: 2518, .AliasCondStart: 583, .NumOperands: 4, .NumConds: 5 },
2151 {.AsmStrOffset: 2538, .AliasCondStart: 588, .NumOperands: 4, .NumConds: 5 },
2152 {.AsmStrOffset: 2557, .AliasCondStart: 593, .NumOperands: 4, .NumConds: 5 },
2153 // SP::CXBCONDri - 168
2154 {.AsmStrOffset: 2576, .AliasCondStart: 598, .NumOperands: 4, .NumConds: 4 },
2155 {.AsmStrOffset: 2595, .AliasCondStart: 602, .NumOperands: 4, .NumConds: 4 },
2156 {.AsmStrOffset: 2613, .AliasCondStart: 606, .NumOperands: 4, .NumConds: 4 },
2157 {.AsmStrOffset: 2631, .AliasCondStart: 610, .NumOperands: 4, .NumConds: 4 },
2158 {.AsmStrOffset: 2650, .AliasCondStart: 614, .NumOperands: 4, .NumConds: 4 },
2159 {.AsmStrOffset: 2669, .AliasCondStart: 618, .NumOperands: 4, .NumConds: 4 },
2160 {.AsmStrOffset: 2687, .AliasCondStart: 622, .NumOperands: 4, .NumConds: 4 },
2161 {.AsmStrOffset: 2706, .AliasCondStart: 626, .NumOperands: 4, .NumConds: 4 },
2162 {.AsmStrOffset: 2726, .AliasCondStart: 630, .NumOperands: 4, .NumConds: 4 },
2163 {.AsmStrOffset: 2745, .AliasCondStart: 634, .NumOperands: 4, .NumConds: 4 },
2164 {.AsmStrOffset: 2764, .AliasCondStart: 638, .NumOperands: 4, .NumConds: 4 },
2165 {.AsmStrOffset: 2784, .AliasCondStart: 642, .NumOperands: 4, .NumConds: 4 },
2166 {.AsmStrOffset: 2804, .AliasCondStart: 646, .NumOperands: 4, .NumConds: 4 },
2167 {.AsmStrOffset: 2823, .AliasCondStart: 650, .NumOperands: 4, .NumConds: 4 },
2168 // SP::CXBCONDrr - 182
2169 {.AsmStrOffset: 2576, .AliasCondStart: 654, .NumOperands: 4, .NumConds: 5 },
2170 {.AsmStrOffset: 2595, .AliasCondStart: 659, .NumOperands: 4, .NumConds: 5 },
2171 {.AsmStrOffset: 2613, .AliasCondStart: 664, .NumOperands: 4, .NumConds: 5 },
2172 {.AsmStrOffset: 2631, .AliasCondStart: 669, .NumOperands: 4, .NumConds: 5 },
2173 {.AsmStrOffset: 2650, .AliasCondStart: 674, .NumOperands: 4, .NumConds: 5 },
2174 {.AsmStrOffset: 2669, .AliasCondStart: 679, .NumOperands: 4, .NumConds: 5 },
2175 {.AsmStrOffset: 2687, .AliasCondStart: 684, .NumOperands: 4, .NumConds: 5 },
2176 {.AsmStrOffset: 2706, .AliasCondStart: 689, .NumOperands: 4, .NumConds: 5 },
2177 {.AsmStrOffset: 2726, .AliasCondStart: 694, .NumOperands: 4, .NumConds: 5 },
2178 {.AsmStrOffset: 2745, .AliasCondStart: 699, .NumOperands: 4, .NumConds: 5 },
2179 {.AsmStrOffset: 2764, .AliasCondStart: 704, .NumOperands: 4, .NumConds: 5 },
2180 {.AsmStrOffset: 2784, .AliasCondStart: 709, .NumOperands: 4, .NumConds: 5 },
2181 {.AsmStrOffset: 2804, .AliasCondStart: 714, .NumOperands: 4, .NumConds: 5 },
2182 {.AsmStrOffset: 2823, .AliasCondStart: 719, .NumOperands: 4, .NumConds: 5 },
2183 // SP::FMOVD_ICC - 196
2184 {.AsmStrOffset: 2842, .AliasCondStart: 724, .NumOperands: 4, .NumConds: 5 },
2185 {.AsmStrOffset: 2862, .AliasCondStart: 729, .NumOperands: 4, .NumConds: 6 },
2186 {.AsmStrOffset: 2882, .AliasCondStart: 735, .NumOperands: 4, .NumConds: 5 },
2187 {.AsmStrOffset: 2902, .AliasCondStart: 740, .NumOperands: 4, .NumConds: 6 },
2188 {.AsmStrOffset: 2922, .AliasCondStart: 746, .NumOperands: 4, .NumConds: 5 },
2189 {.AsmStrOffset: 2943, .AliasCondStart: 751, .NumOperands: 4, .NumConds: 6 },
2190 {.AsmStrOffset: 2964, .AliasCondStart: 757, .NumOperands: 4, .NumConds: 5 },
2191 {.AsmStrOffset: 2984, .AliasCondStart: 762, .NumOperands: 4, .NumConds: 6 },
2192 {.AsmStrOffset: 3004, .AliasCondStart: 768, .NumOperands: 4, .NumConds: 5 },
2193 {.AsmStrOffset: 3024, .AliasCondStart: 773, .NumOperands: 4, .NumConds: 6 },
2194 {.AsmStrOffset: 3044, .AliasCondStart: 779, .NumOperands: 4, .NumConds: 5 },
2195 {.AsmStrOffset: 3065, .AliasCondStart: 784, .NumOperands: 4, .NumConds: 6 },
2196 {.AsmStrOffset: 3086, .AliasCondStart: 790, .NumOperands: 4, .NumConds: 5 },
2197 {.AsmStrOffset: 3107, .AliasCondStart: 795, .NumOperands: 4, .NumConds: 6 },
2198 {.AsmStrOffset: 3128, .AliasCondStart: 801, .NumOperands: 4, .NumConds: 5 },
2199 {.AsmStrOffset: 3148, .AliasCondStart: 806, .NumOperands: 4, .NumConds: 6 },
2200 {.AsmStrOffset: 3168, .AliasCondStart: 812, .NumOperands: 4, .NumConds: 5 },
2201 {.AsmStrOffset: 3189, .AliasCondStart: 817, .NumOperands: 4, .NumConds: 6 },
2202 {.AsmStrOffset: 3210, .AliasCondStart: 823, .NumOperands: 4, .NumConds: 5 },
2203 {.AsmStrOffset: 3232, .AliasCondStart: 828, .NumOperands: 4, .NumConds: 6 },
2204 {.AsmStrOffset: 3254, .AliasCondStart: 834, .NumOperands: 4, .NumConds: 5 },
2205 {.AsmStrOffset: 3275, .AliasCondStart: 839, .NumOperands: 4, .NumConds: 6 },
2206 {.AsmStrOffset: 3296, .AliasCondStart: 845, .NumOperands: 4, .NumConds: 5 },
2207 {.AsmStrOffset: 3317, .AliasCondStart: 850, .NumOperands: 4, .NumConds: 6 },
2208 {.AsmStrOffset: 3338, .AliasCondStart: 856, .NumOperands: 4, .NumConds: 5 },
2209 {.AsmStrOffset: 3360, .AliasCondStart: 861, .NumOperands: 4, .NumConds: 6 },
2210 {.AsmStrOffset: 3382, .AliasCondStart: 867, .NumOperands: 4, .NumConds: 5 },
2211 {.AsmStrOffset: 3404, .AliasCondStart: 872, .NumOperands: 4, .NumConds: 6 },
2212 {.AsmStrOffset: 3426, .AliasCondStart: 878, .NumOperands: 4, .NumConds: 5 },
2213 {.AsmStrOffset: 3447, .AliasCondStart: 883, .NumOperands: 4, .NumConds: 6 },
2214 {.AsmStrOffset: 3468, .AliasCondStart: 889, .NumOperands: 4, .NumConds: 5 },
2215 {.AsmStrOffset: 3489, .AliasCondStart: 894, .NumOperands: 4, .NumConds: 6 },
2216 // SP::FMOVQ_ICC - 228
2217 {.AsmStrOffset: 3510, .AliasCondStart: 900, .NumOperands: 4, .NumConds: 5 },
2218 {.AsmStrOffset: 3530, .AliasCondStart: 905, .NumOperands: 4, .NumConds: 6 },
2219 {.AsmStrOffset: 3550, .AliasCondStart: 911, .NumOperands: 4, .NumConds: 5 },
2220 {.AsmStrOffset: 3570, .AliasCondStart: 916, .NumOperands: 4, .NumConds: 6 },
2221 {.AsmStrOffset: 3590, .AliasCondStart: 922, .NumOperands: 4, .NumConds: 5 },
2222 {.AsmStrOffset: 3611, .AliasCondStart: 927, .NumOperands: 4, .NumConds: 6 },
2223 {.AsmStrOffset: 3632, .AliasCondStart: 933, .NumOperands: 4, .NumConds: 5 },
2224 {.AsmStrOffset: 3652, .AliasCondStart: 938, .NumOperands: 4, .NumConds: 6 },
2225 {.AsmStrOffset: 3672, .AliasCondStart: 944, .NumOperands: 4, .NumConds: 5 },
2226 {.AsmStrOffset: 3692, .AliasCondStart: 949, .NumOperands: 4, .NumConds: 6 },
2227 {.AsmStrOffset: 3712, .AliasCondStart: 955, .NumOperands: 4, .NumConds: 5 },
2228 {.AsmStrOffset: 3733, .AliasCondStart: 960, .NumOperands: 4, .NumConds: 6 },
2229 {.AsmStrOffset: 3754, .AliasCondStart: 966, .NumOperands: 4, .NumConds: 5 },
2230 {.AsmStrOffset: 3775, .AliasCondStart: 971, .NumOperands: 4, .NumConds: 6 },
2231 {.AsmStrOffset: 3796, .AliasCondStart: 977, .NumOperands: 4, .NumConds: 5 },
2232 {.AsmStrOffset: 3816, .AliasCondStart: 982, .NumOperands: 4, .NumConds: 6 },
2233 {.AsmStrOffset: 3836, .AliasCondStart: 988, .NumOperands: 4, .NumConds: 5 },
2234 {.AsmStrOffset: 3857, .AliasCondStart: 993, .NumOperands: 4, .NumConds: 6 },
2235 {.AsmStrOffset: 3878, .AliasCondStart: 999, .NumOperands: 4, .NumConds: 5 },
2236 {.AsmStrOffset: 3900, .AliasCondStart: 1004, .NumOperands: 4, .NumConds: 6 },
2237 {.AsmStrOffset: 3922, .AliasCondStart: 1010, .NumOperands: 4, .NumConds: 5 },
2238 {.AsmStrOffset: 3943, .AliasCondStart: 1015, .NumOperands: 4, .NumConds: 6 },
2239 {.AsmStrOffset: 3964, .AliasCondStart: 1021, .NumOperands: 4, .NumConds: 5 },
2240 {.AsmStrOffset: 3985, .AliasCondStart: 1026, .NumOperands: 4, .NumConds: 6 },
2241 {.AsmStrOffset: 4006, .AliasCondStart: 1032, .NumOperands: 4, .NumConds: 5 },
2242 {.AsmStrOffset: 4028, .AliasCondStart: 1037, .NumOperands: 4, .NumConds: 6 },
2243 {.AsmStrOffset: 4050, .AliasCondStart: 1043, .NumOperands: 4, .NumConds: 5 },
2244 {.AsmStrOffset: 4072, .AliasCondStart: 1048, .NumOperands: 4, .NumConds: 6 },
2245 {.AsmStrOffset: 4094, .AliasCondStart: 1054, .NumOperands: 4, .NumConds: 5 },
2246 {.AsmStrOffset: 4115, .AliasCondStart: 1059, .NumOperands: 4, .NumConds: 6 },
2247 {.AsmStrOffset: 4136, .AliasCondStart: 1065, .NumOperands: 4, .NumConds: 5 },
2248 {.AsmStrOffset: 4157, .AliasCondStart: 1070, .NumOperands: 4, .NumConds: 6 },
2249 // SP::FMOVRD - 260
2250 {.AsmStrOffset: 4178, .AliasCondStart: 1076, .NumOperands: 5, .NumConds: 6 },
2251 {.AsmStrOffset: 4199, .AliasCondStart: 1082, .NumOperands: 5, .NumConds: 6 },
2252 {.AsmStrOffset: 4219, .AliasCondStart: 1088, .NumOperands: 5, .NumConds: 6 },
2253 {.AsmStrOffset: 4239, .AliasCondStart: 1094, .NumOperands: 5, .NumConds: 6 },
2254 // SP::FMOVRQ - 264
2255 {.AsmStrOffset: 4260, .AliasCondStart: 1100, .NumOperands: 5, .NumConds: 6 },
2256 {.AsmStrOffset: 4281, .AliasCondStart: 1106, .NumOperands: 5, .NumConds: 6 },
2257 {.AsmStrOffset: 4301, .AliasCondStart: 1112, .NumOperands: 5, .NumConds: 6 },
2258 {.AsmStrOffset: 4321, .AliasCondStart: 1118, .NumOperands: 5, .NumConds: 6 },
2259 // SP::FMOVRS - 268
2260 {.AsmStrOffset: 4342, .AliasCondStart: 1124, .NumOperands: 5, .NumConds: 6 },
2261 {.AsmStrOffset: 4363, .AliasCondStart: 1130, .NumOperands: 5, .NumConds: 6 },
2262 {.AsmStrOffset: 4383, .AliasCondStart: 1136, .NumOperands: 5, .NumConds: 6 },
2263 {.AsmStrOffset: 4403, .AliasCondStart: 1142, .NumOperands: 5, .NumConds: 6 },
2264 // SP::FMOVS_ICC - 272
2265 {.AsmStrOffset: 4424, .AliasCondStart: 1148, .NumOperands: 4, .NumConds: 5 },
2266 {.AsmStrOffset: 4444, .AliasCondStart: 1153, .NumOperands: 4, .NumConds: 6 },
2267 {.AsmStrOffset: 4464, .AliasCondStart: 1159, .NumOperands: 4, .NumConds: 5 },
2268 {.AsmStrOffset: 4484, .AliasCondStart: 1164, .NumOperands: 4, .NumConds: 6 },
2269 {.AsmStrOffset: 4504, .AliasCondStart: 1170, .NumOperands: 4, .NumConds: 5 },
2270 {.AsmStrOffset: 4525, .AliasCondStart: 1175, .NumOperands: 4, .NumConds: 6 },
2271 {.AsmStrOffset: 4546, .AliasCondStart: 1181, .NumOperands: 4, .NumConds: 5 },
2272 {.AsmStrOffset: 4566, .AliasCondStart: 1186, .NumOperands: 4, .NumConds: 6 },
2273 {.AsmStrOffset: 4586, .AliasCondStart: 1192, .NumOperands: 4, .NumConds: 5 },
2274 {.AsmStrOffset: 4606, .AliasCondStart: 1197, .NumOperands: 4, .NumConds: 6 },
2275 {.AsmStrOffset: 4626, .AliasCondStart: 1203, .NumOperands: 4, .NumConds: 5 },
2276 {.AsmStrOffset: 4647, .AliasCondStart: 1208, .NumOperands: 4, .NumConds: 6 },
2277 {.AsmStrOffset: 4668, .AliasCondStart: 1214, .NumOperands: 4, .NumConds: 5 },
2278 {.AsmStrOffset: 4689, .AliasCondStart: 1219, .NumOperands: 4, .NumConds: 6 },
2279 {.AsmStrOffset: 4710, .AliasCondStart: 1225, .NumOperands: 4, .NumConds: 5 },
2280 {.AsmStrOffset: 4730, .AliasCondStart: 1230, .NumOperands: 4, .NumConds: 6 },
2281 {.AsmStrOffset: 4750, .AliasCondStart: 1236, .NumOperands: 4, .NumConds: 5 },
2282 {.AsmStrOffset: 4771, .AliasCondStart: 1241, .NumOperands: 4, .NumConds: 6 },
2283 {.AsmStrOffset: 4792, .AliasCondStart: 1247, .NumOperands: 4, .NumConds: 5 },
2284 {.AsmStrOffset: 4814, .AliasCondStart: 1252, .NumOperands: 4, .NumConds: 6 },
2285 {.AsmStrOffset: 4836, .AliasCondStart: 1258, .NumOperands: 4, .NumConds: 5 },
2286 {.AsmStrOffset: 4857, .AliasCondStart: 1263, .NumOperands: 4, .NumConds: 6 },
2287 {.AsmStrOffset: 4878, .AliasCondStart: 1269, .NumOperands: 4, .NumConds: 5 },
2288 {.AsmStrOffset: 4899, .AliasCondStart: 1274, .NumOperands: 4, .NumConds: 6 },
2289 {.AsmStrOffset: 4920, .AliasCondStart: 1280, .NumOperands: 4, .NumConds: 5 },
2290 {.AsmStrOffset: 4942, .AliasCondStart: 1285, .NumOperands: 4, .NumConds: 6 },
2291 {.AsmStrOffset: 4964, .AliasCondStart: 1291, .NumOperands: 4, .NumConds: 5 },
2292 {.AsmStrOffset: 4986, .AliasCondStart: 1296, .NumOperands: 4, .NumConds: 6 },
2293 {.AsmStrOffset: 5008, .AliasCondStart: 1302, .NumOperands: 4, .NumConds: 5 },
2294 {.AsmStrOffset: 5029, .AliasCondStart: 1307, .NumOperands: 4, .NumConds: 6 },
2295 {.AsmStrOffset: 5050, .AliasCondStart: 1313, .NumOperands: 4, .NumConds: 5 },
2296 {.AsmStrOffset: 5071, .AliasCondStart: 1318, .NumOperands: 4, .NumConds: 6 },
2297 // SP::MOVICCri - 304
2298 {.AsmStrOffset: 5092, .AliasCondStart: 1324, .NumOperands: 4, .NumConds: 5 },
2299 {.AsmStrOffset: 5110, .AliasCondStart: 1329, .NumOperands: 4, .NumConds: 6 },
2300 {.AsmStrOffset: 5128, .AliasCondStart: 1335, .NumOperands: 4, .NumConds: 5 },
2301 {.AsmStrOffset: 5146, .AliasCondStart: 1340, .NumOperands: 4, .NumConds: 6 },
2302 {.AsmStrOffset: 5164, .AliasCondStart: 1346, .NumOperands: 4, .NumConds: 5 },
2303 {.AsmStrOffset: 5183, .AliasCondStart: 1351, .NumOperands: 4, .NumConds: 6 },
2304 {.AsmStrOffset: 5202, .AliasCondStart: 1357, .NumOperands: 4, .NumConds: 5 },
2305 {.AsmStrOffset: 5220, .AliasCondStart: 1362, .NumOperands: 4, .NumConds: 6 },
2306 {.AsmStrOffset: 5238, .AliasCondStart: 1368, .NumOperands: 4, .NumConds: 5 },
2307 {.AsmStrOffset: 5256, .AliasCondStart: 1373, .NumOperands: 4, .NumConds: 6 },
2308 {.AsmStrOffset: 5274, .AliasCondStart: 1379, .NumOperands: 4, .NumConds: 5 },
2309 {.AsmStrOffset: 5293, .AliasCondStart: 1384, .NumOperands: 4, .NumConds: 6 },
2310 {.AsmStrOffset: 5312, .AliasCondStart: 1390, .NumOperands: 4, .NumConds: 5 },
2311 {.AsmStrOffset: 5331, .AliasCondStart: 1395, .NumOperands: 4, .NumConds: 6 },
2312 {.AsmStrOffset: 5350, .AliasCondStart: 1401, .NumOperands: 4, .NumConds: 5 },
2313 {.AsmStrOffset: 5368, .AliasCondStart: 1406, .NumOperands: 4, .NumConds: 6 },
2314 {.AsmStrOffset: 5386, .AliasCondStart: 1412, .NumOperands: 4, .NumConds: 5 },
2315 {.AsmStrOffset: 5405, .AliasCondStart: 1417, .NumOperands: 4, .NumConds: 6 },
2316 {.AsmStrOffset: 5424, .AliasCondStart: 1423, .NumOperands: 4, .NumConds: 5 },
2317 {.AsmStrOffset: 5444, .AliasCondStart: 1428, .NumOperands: 4, .NumConds: 6 },
2318 {.AsmStrOffset: 5464, .AliasCondStart: 1434, .NumOperands: 4, .NumConds: 5 },
2319 {.AsmStrOffset: 5483, .AliasCondStart: 1439, .NumOperands: 4, .NumConds: 6 },
2320 {.AsmStrOffset: 5502, .AliasCondStart: 1445, .NumOperands: 4, .NumConds: 5 },
2321 {.AsmStrOffset: 5521, .AliasCondStart: 1450, .NumOperands: 4, .NumConds: 6 },
2322 {.AsmStrOffset: 5540, .AliasCondStart: 1456, .NumOperands: 4, .NumConds: 5 },
2323 {.AsmStrOffset: 5560, .AliasCondStart: 1461, .NumOperands: 4, .NumConds: 6 },
2324 {.AsmStrOffset: 5580, .AliasCondStart: 1467, .NumOperands: 4, .NumConds: 5 },
2325 {.AsmStrOffset: 5600, .AliasCondStart: 1472, .NumOperands: 4, .NumConds: 6 },
2326 {.AsmStrOffset: 5620, .AliasCondStart: 1478, .NumOperands: 4, .NumConds: 5 },
2327 {.AsmStrOffset: 5639, .AliasCondStart: 1483, .NumOperands: 4, .NumConds: 6 },
2328 {.AsmStrOffset: 5658, .AliasCondStart: 1489, .NumOperands: 4, .NumConds: 5 },
2329 {.AsmStrOffset: 5677, .AliasCondStart: 1494, .NumOperands: 4, .NumConds: 6 },
2330 // SP::MOVICCrr - 336
2331 {.AsmStrOffset: 5092, .AliasCondStart: 1500, .NumOperands: 4, .NumConds: 5 },
2332 {.AsmStrOffset: 5110, .AliasCondStart: 1505, .NumOperands: 4, .NumConds: 6 },
2333 {.AsmStrOffset: 5128, .AliasCondStart: 1511, .NumOperands: 4, .NumConds: 5 },
2334 {.AsmStrOffset: 5146, .AliasCondStart: 1516, .NumOperands: 4, .NumConds: 6 },
2335 {.AsmStrOffset: 5164, .AliasCondStart: 1522, .NumOperands: 4, .NumConds: 5 },
2336 {.AsmStrOffset: 5183, .AliasCondStart: 1527, .NumOperands: 4, .NumConds: 6 },
2337 {.AsmStrOffset: 5202, .AliasCondStart: 1533, .NumOperands: 4, .NumConds: 5 },
2338 {.AsmStrOffset: 5220, .AliasCondStart: 1538, .NumOperands: 4, .NumConds: 6 },
2339 {.AsmStrOffset: 5238, .AliasCondStart: 1544, .NumOperands: 4, .NumConds: 5 },
2340 {.AsmStrOffset: 5256, .AliasCondStart: 1549, .NumOperands: 4, .NumConds: 6 },
2341 {.AsmStrOffset: 5274, .AliasCondStart: 1555, .NumOperands: 4, .NumConds: 5 },
2342 {.AsmStrOffset: 5293, .AliasCondStart: 1560, .NumOperands: 4, .NumConds: 6 },
2343 {.AsmStrOffset: 5312, .AliasCondStart: 1566, .NumOperands: 4, .NumConds: 5 },
2344 {.AsmStrOffset: 5331, .AliasCondStart: 1571, .NumOperands: 4, .NumConds: 6 },
2345 {.AsmStrOffset: 5350, .AliasCondStart: 1577, .NumOperands: 4, .NumConds: 5 },
2346 {.AsmStrOffset: 5368, .AliasCondStart: 1582, .NumOperands: 4, .NumConds: 6 },
2347 {.AsmStrOffset: 5386, .AliasCondStart: 1588, .NumOperands: 4, .NumConds: 5 },
2348 {.AsmStrOffset: 5405, .AliasCondStart: 1593, .NumOperands: 4, .NumConds: 6 },
2349 {.AsmStrOffset: 5424, .AliasCondStart: 1599, .NumOperands: 4, .NumConds: 5 },
2350 {.AsmStrOffset: 5444, .AliasCondStart: 1604, .NumOperands: 4, .NumConds: 6 },
2351 {.AsmStrOffset: 5464, .AliasCondStart: 1610, .NumOperands: 4, .NumConds: 5 },
2352 {.AsmStrOffset: 5483, .AliasCondStart: 1615, .NumOperands: 4, .NumConds: 6 },
2353 {.AsmStrOffset: 5502, .AliasCondStart: 1621, .NumOperands: 4, .NumConds: 5 },
2354 {.AsmStrOffset: 5521, .AliasCondStart: 1626, .NumOperands: 4, .NumConds: 6 },
2355 {.AsmStrOffset: 5540, .AliasCondStart: 1632, .NumOperands: 4, .NumConds: 5 },
2356 {.AsmStrOffset: 5560, .AliasCondStart: 1637, .NumOperands: 4, .NumConds: 6 },
2357 {.AsmStrOffset: 5580, .AliasCondStart: 1643, .NumOperands: 4, .NumConds: 5 },
2358 {.AsmStrOffset: 5600, .AliasCondStart: 1648, .NumOperands: 4, .NumConds: 6 },
2359 {.AsmStrOffset: 5620, .AliasCondStart: 1654, .NumOperands: 4, .NumConds: 5 },
2360 {.AsmStrOffset: 5639, .AliasCondStart: 1659, .NumOperands: 4, .NumConds: 6 },
2361 {.AsmStrOffset: 5658, .AliasCondStart: 1665, .NumOperands: 4, .NumConds: 5 },
2362 {.AsmStrOffset: 5677, .AliasCondStart: 1670, .NumOperands: 4, .NumConds: 6 },
2363 // SP::MOVRri - 368
2364 {.AsmStrOffset: 5696, .AliasCondStart: 1676, .NumOperands: 5, .NumConds: 6 },
2365 {.AsmStrOffset: 5715, .AliasCondStart: 1682, .NumOperands: 5, .NumConds: 6 },
2366 {.AsmStrOffset: 5733, .AliasCondStart: 1688, .NumOperands: 5, .NumConds: 6 },
2367 {.AsmStrOffset: 5751, .AliasCondStart: 1694, .NumOperands: 5, .NumConds: 6 },
2368 // SP::MOVRrr - 372
2369 {.AsmStrOffset: 5696, .AliasCondStart: 1700, .NumOperands: 5, .NumConds: 6 },
2370 {.AsmStrOffset: 5715, .AliasCondStart: 1706, .NumOperands: 5, .NumConds: 6 },
2371 {.AsmStrOffset: 5733, .AliasCondStart: 1712, .NumOperands: 5, .NumConds: 6 },
2372 {.AsmStrOffset: 5751, .AliasCondStart: 1718, .NumOperands: 5, .NumConds: 6 },
2373 // SP::ORCCrr - 376
2374 {.AsmStrOffset: 5770, .AliasCondStart: 1724, .NumOperands: 3, .NumConds: 3 },
2375 // SP::ORri - 377
2376 {.AsmStrOffset: 5777, .AliasCondStart: 1727, .NumOperands: 3, .NumConds: 2 },
2377 // SP::ORrr - 378
2378 {.AsmStrOffset: 5777, .AliasCondStart: 1729, .NumOperands: 3, .NumConds: 3 },
2379 // SP::RESTORErr - 379
2380 {.AsmStrOffset: 5788, .AliasCondStart: 1732, .NumOperands: 3, .NumConds: 3 },
2381 // SP::RET - 380
2382 {.AsmStrOffset: 5796, .AliasCondStart: 1735, .NumOperands: 1, .NumConds: 1 },
2383 // SP::RETL - 381
2384 {.AsmStrOffset: 5800, .AliasCondStart: 1736, .NumOperands: 1, .NumConds: 1 },
2385 // SP::SAVErr - 382
2386 {.AsmStrOffset: 5805, .AliasCondStart: 1737, .NumOperands: 3, .NumConds: 3 },
2387 // SP::SUBCCri - 383
2388 {.AsmStrOffset: 5810, .AliasCondStart: 1740, .NumOperands: 3, .NumConds: 2 },
2389 // SP::SUBCCrr - 384
2390 {.AsmStrOffset: 5810, .AliasCondStart: 1742, .NumOperands: 3, .NumConds: 3 },
2391 // SP::TICCri - 385
2392 {.AsmStrOffset: 5821, .AliasCondStart: 1745, .NumOperands: 3, .NumConds: 4 },
2393 {.AsmStrOffset: 5833, .AliasCondStart: 1749, .NumOperands: 3, .NumConds: 5 },
2394 {.AsmStrOffset: 5845, .AliasCondStart: 1754, .NumOperands: 3, .NumConds: 4 },
2395 {.AsmStrOffset: 5862, .AliasCondStart: 1758, .NumOperands: 3, .NumConds: 5 },
2396 {.AsmStrOffset: 5879, .AliasCondStart: 1763, .NumOperands: 3, .NumConds: 4 },
2397 {.AsmStrOffset: 5891, .AliasCondStart: 1767, .NumOperands: 3, .NumConds: 5 },
2398 {.AsmStrOffset: 5903, .AliasCondStart: 1772, .NumOperands: 3, .NumConds: 4 },
2399 {.AsmStrOffset: 5920, .AliasCondStart: 1776, .NumOperands: 3, .NumConds: 5 },
2400 {.AsmStrOffset: 5937, .AliasCondStart: 1781, .NumOperands: 3, .NumConds: 4 },
2401 {.AsmStrOffset: 5950, .AliasCondStart: 1785, .NumOperands: 3, .NumConds: 5 },
2402 {.AsmStrOffset: 5963, .AliasCondStart: 1790, .NumOperands: 3, .NumConds: 4 },
2403 {.AsmStrOffset: 5981, .AliasCondStart: 1794, .NumOperands: 3, .NumConds: 5 },
2404 {.AsmStrOffset: 5999, .AliasCondStart: 1799, .NumOperands: 3, .NumConds: 4 },
2405 {.AsmStrOffset: 6011, .AliasCondStart: 1803, .NumOperands: 3, .NumConds: 5 },
2406 {.AsmStrOffset: 6023, .AliasCondStart: 1808, .NumOperands: 3, .NumConds: 4 },
2407 {.AsmStrOffset: 6040, .AliasCondStart: 1812, .NumOperands: 3, .NumConds: 5 },
2408 {.AsmStrOffset: 6057, .AliasCondStart: 1817, .NumOperands: 3, .NumConds: 4 },
2409 {.AsmStrOffset: 6069, .AliasCondStart: 1821, .NumOperands: 3, .NumConds: 5 },
2410 {.AsmStrOffset: 6081, .AliasCondStart: 1826, .NumOperands: 3, .NumConds: 4 },
2411 {.AsmStrOffset: 6098, .AliasCondStart: 1830, .NumOperands: 3, .NumConds: 5 },
2412 {.AsmStrOffset: 6115, .AliasCondStart: 1835, .NumOperands: 3, .NumConds: 4 },
2413 {.AsmStrOffset: 6128, .AliasCondStart: 1839, .NumOperands: 3, .NumConds: 5 },
2414 {.AsmStrOffset: 6141, .AliasCondStart: 1844, .NumOperands: 3, .NumConds: 4 },
2415 {.AsmStrOffset: 6159, .AliasCondStart: 1848, .NumOperands: 3, .NumConds: 5 },
2416 {.AsmStrOffset: 6177, .AliasCondStart: 1853, .NumOperands: 3, .NumConds: 4 },
2417 {.AsmStrOffset: 6190, .AliasCondStart: 1857, .NumOperands: 3, .NumConds: 5 },
2418 {.AsmStrOffset: 6203, .AliasCondStart: 1862, .NumOperands: 3, .NumConds: 4 },
2419 {.AsmStrOffset: 6221, .AliasCondStart: 1866, .NumOperands: 3, .NumConds: 5 },
2420 {.AsmStrOffset: 6239, .AliasCondStart: 1871, .NumOperands: 3, .NumConds: 4 },
2421 {.AsmStrOffset: 6251, .AliasCondStart: 1875, .NumOperands: 3, .NumConds: 5 },
2422 {.AsmStrOffset: 6263, .AliasCondStart: 1880, .NumOperands: 3, .NumConds: 4 },
2423 {.AsmStrOffset: 6280, .AliasCondStart: 1884, .NumOperands: 3, .NumConds: 5 },
2424 {.AsmStrOffset: 6297, .AliasCondStart: 1889, .NumOperands: 3, .NumConds: 4 },
2425 {.AsmStrOffset: 6310, .AliasCondStart: 1893, .NumOperands: 3, .NumConds: 5 },
2426 {.AsmStrOffset: 6323, .AliasCondStart: 1898, .NumOperands: 3, .NumConds: 4 },
2427 {.AsmStrOffset: 6341, .AliasCondStart: 1902, .NumOperands: 3, .NumConds: 5 },
2428 {.AsmStrOffset: 6359, .AliasCondStart: 1907, .NumOperands: 3, .NumConds: 4 },
2429 {.AsmStrOffset: 6373, .AliasCondStart: 1911, .NumOperands: 3, .NumConds: 5 },
2430 {.AsmStrOffset: 6387, .AliasCondStart: 1916, .NumOperands: 3, .NumConds: 4 },
2431 {.AsmStrOffset: 6406, .AliasCondStart: 1920, .NumOperands: 3, .NumConds: 5 },
2432 {.AsmStrOffset: 6425, .AliasCondStart: 1925, .NumOperands: 3, .NumConds: 4 },
2433 {.AsmStrOffset: 6438, .AliasCondStart: 1929, .NumOperands: 3, .NumConds: 5 },
2434 {.AsmStrOffset: 6451, .AliasCondStart: 1934, .NumOperands: 3, .NumConds: 4 },
2435 {.AsmStrOffset: 6469, .AliasCondStart: 1938, .NumOperands: 3, .NumConds: 5 },
2436 {.AsmStrOffset: 6487, .AliasCondStart: 1943, .NumOperands: 3, .NumConds: 4 },
2437 {.AsmStrOffset: 6500, .AliasCondStart: 1947, .NumOperands: 3, .NumConds: 5 },
2438 {.AsmStrOffset: 6513, .AliasCondStart: 1952, .NumOperands: 3, .NumConds: 4 },
2439 {.AsmStrOffset: 6531, .AliasCondStart: 1956, .NumOperands: 3, .NumConds: 5 },
2440 {.AsmStrOffset: 6549, .AliasCondStart: 1961, .NumOperands: 3, .NumConds: 4 },
2441 {.AsmStrOffset: 6563, .AliasCondStart: 1965, .NumOperands: 3, .NumConds: 5 },
2442 {.AsmStrOffset: 6577, .AliasCondStart: 1970, .NumOperands: 3, .NumConds: 4 },
2443 {.AsmStrOffset: 6596, .AliasCondStart: 1974, .NumOperands: 3, .NumConds: 5 },
2444 {.AsmStrOffset: 6615, .AliasCondStart: 1979, .NumOperands: 3, .NumConds: 4 },
2445 {.AsmStrOffset: 6629, .AliasCondStart: 1983, .NumOperands: 3, .NumConds: 5 },
2446 {.AsmStrOffset: 6643, .AliasCondStart: 1988, .NumOperands: 3, .NumConds: 4 },
2447 {.AsmStrOffset: 6662, .AliasCondStart: 1992, .NumOperands: 3, .NumConds: 5 },
2448 {.AsmStrOffset: 6681, .AliasCondStart: 1997, .NumOperands: 3, .NumConds: 4 },
2449 {.AsmStrOffset: 6694, .AliasCondStart: 2001, .NumOperands: 3, .NumConds: 5 },
2450 {.AsmStrOffset: 6707, .AliasCondStart: 2006, .NumOperands: 3, .NumConds: 4 },
2451 {.AsmStrOffset: 6725, .AliasCondStart: 2010, .NumOperands: 3, .NumConds: 5 },
2452 {.AsmStrOffset: 6743, .AliasCondStart: 2015, .NumOperands: 3, .NumConds: 4 },
2453 {.AsmStrOffset: 6756, .AliasCondStart: 2019, .NumOperands: 3, .NumConds: 5 },
2454 {.AsmStrOffset: 6769, .AliasCondStart: 2024, .NumOperands: 3, .NumConds: 4 },
2455 {.AsmStrOffset: 6787, .AliasCondStart: 2028, .NumOperands: 3, .NumConds: 5 },
2456 // SP::TICCrr - 449
2457 {.AsmStrOffset: 5821, .AliasCondStart: 2033, .NumOperands: 3, .NumConds: 4 },
2458 {.AsmStrOffset: 5833, .AliasCondStart: 2037, .NumOperands: 3, .NumConds: 5 },
2459 {.AsmStrOffset: 5845, .AliasCondStart: 2042, .NumOperands: 3, .NumConds: 4 },
2460 {.AsmStrOffset: 5862, .AliasCondStart: 2046, .NumOperands: 3, .NumConds: 5 },
2461 {.AsmStrOffset: 5879, .AliasCondStart: 2051, .NumOperands: 3, .NumConds: 4 },
2462 {.AsmStrOffset: 5891, .AliasCondStart: 2055, .NumOperands: 3, .NumConds: 5 },
2463 {.AsmStrOffset: 5903, .AliasCondStart: 2060, .NumOperands: 3, .NumConds: 4 },
2464 {.AsmStrOffset: 5920, .AliasCondStart: 2064, .NumOperands: 3, .NumConds: 5 },
2465 {.AsmStrOffset: 5937, .AliasCondStart: 2069, .NumOperands: 3, .NumConds: 4 },
2466 {.AsmStrOffset: 5950, .AliasCondStart: 2073, .NumOperands: 3, .NumConds: 5 },
2467 {.AsmStrOffset: 5963, .AliasCondStart: 2078, .NumOperands: 3, .NumConds: 4 },
2468 {.AsmStrOffset: 5981, .AliasCondStart: 2082, .NumOperands: 3, .NumConds: 5 },
2469 {.AsmStrOffset: 5999, .AliasCondStart: 2087, .NumOperands: 3, .NumConds: 4 },
2470 {.AsmStrOffset: 6011, .AliasCondStart: 2091, .NumOperands: 3, .NumConds: 5 },
2471 {.AsmStrOffset: 6023, .AliasCondStart: 2096, .NumOperands: 3, .NumConds: 4 },
2472 {.AsmStrOffset: 6040, .AliasCondStart: 2100, .NumOperands: 3, .NumConds: 5 },
2473 {.AsmStrOffset: 6057, .AliasCondStart: 2105, .NumOperands: 3, .NumConds: 4 },
2474 {.AsmStrOffset: 6069, .AliasCondStart: 2109, .NumOperands: 3, .NumConds: 5 },
2475 {.AsmStrOffset: 6081, .AliasCondStart: 2114, .NumOperands: 3, .NumConds: 4 },
2476 {.AsmStrOffset: 6098, .AliasCondStart: 2118, .NumOperands: 3, .NumConds: 5 },
2477 {.AsmStrOffset: 6115, .AliasCondStart: 2123, .NumOperands: 3, .NumConds: 4 },
2478 {.AsmStrOffset: 6128, .AliasCondStart: 2127, .NumOperands: 3, .NumConds: 5 },
2479 {.AsmStrOffset: 6141, .AliasCondStart: 2132, .NumOperands: 3, .NumConds: 4 },
2480 {.AsmStrOffset: 6159, .AliasCondStart: 2136, .NumOperands: 3, .NumConds: 5 },
2481 {.AsmStrOffset: 6177, .AliasCondStart: 2141, .NumOperands: 3, .NumConds: 4 },
2482 {.AsmStrOffset: 6190, .AliasCondStart: 2145, .NumOperands: 3, .NumConds: 5 },
2483 {.AsmStrOffset: 6203, .AliasCondStart: 2150, .NumOperands: 3, .NumConds: 4 },
2484 {.AsmStrOffset: 6221, .AliasCondStart: 2154, .NumOperands: 3, .NumConds: 5 },
2485 {.AsmStrOffset: 6239, .AliasCondStart: 2159, .NumOperands: 3, .NumConds: 4 },
2486 {.AsmStrOffset: 6251, .AliasCondStart: 2163, .NumOperands: 3, .NumConds: 5 },
2487 {.AsmStrOffset: 6263, .AliasCondStart: 2168, .NumOperands: 3, .NumConds: 4 },
2488 {.AsmStrOffset: 6280, .AliasCondStart: 2172, .NumOperands: 3, .NumConds: 5 },
2489 {.AsmStrOffset: 6297, .AliasCondStart: 2177, .NumOperands: 3, .NumConds: 4 },
2490 {.AsmStrOffset: 6310, .AliasCondStart: 2181, .NumOperands: 3, .NumConds: 5 },
2491 {.AsmStrOffset: 6323, .AliasCondStart: 2186, .NumOperands: 3, .NumConds: 4 },
2492 {.AsmStrOffset: 6341, .AliasCondStart: 2190, .NumOperands: 3, .NumConds: 5 },
2493 {.AsmStrOffset: 6359, .AliasCondStart: 2195, .NumOperands: 3, .NumConds: 4 },
2494 {.AsmStrOffset: 6373, .AliasCondStart: 2199, .NumOperands: 3, .NumConds: 5 },
2495 {.AsmStrOffset: 6387, .AliasCondStart: 2204, .NumOperands: 3, .NumConds: 4 },
2496 {.AsmStrOffset: 6406, .AliasCondStart: 2208, .NumOperands: 3, .NumConds: 5 },
2497 {.AsmStrOffset: 6425, .AliasCondStart: 2213, .NumOperands: 3, .NumConds: 4 },
2498 {.AsmStrOffset: 6438, .AliasCondStart: 2217, .NumOperands: 3, .NumConds: 5 },
2499 {.AsmStrOffset: 6451, .AliasCondStart: 2222, .NumOperands: 3, .NumConds: 4 },
2500 {.AsmStrOffset: 6469, .AliasCondStart: 2226, .NumOperands: 3, .NumConds: 5 },
2501 {.AsmStrOffset: 6487, .AliasCondStart: 2231, .NumOperands: 3, .NumConds: 4 },
2502 {.AsmStrOffset: 6500, .AliasCondStart: 2235, .NumOperands: 3, .NumConds: 5 },
2503 {.AsmStrOffset: 6513, .AliasCondStart: 2240, .NumOperands: 3, .NumConds: 4 },
2504 {.AsmStrOffset: 6531, .AliasCondStart: 2244, .NumOperands: 3, .NumConds: 5 },
2505 {.AsmStrOffset: 6549, .AliasCondStart: 2249, .NumOperands: 3, .NumConds: 4 },
2506 {.AsmStrOffset: 6563, .AliasCondStart: 2253, .NumOperands: 3, .NumConds: 5 },
2507 {.AsmStrOffset: 6577, .AliasCondStart: 2258, .NumOperands: 3, .NumConds: 4 },
2508 {.AsmStrOffset: 6596, .AliasCondStart: 2262, .NumOperands: 3, .NumConds: 5 },
2509 {.AsmStrOffset: 6615, .AliasCondStart: 2267, .NumOperands: 3, .NumConds: 4 },
2510 {.AsmStrOffset: 6629, .AliasCondStart: 2271, .NumOperands: 3, .NumConds: 5 },
2511 {.AsmStrOffset: 6643, .AliasCondStart: 2276, .NumOperands: 3, .NumConds: 4 },
2512 {.AsmStrOffset: 6662, .AliasCondStart: 2280, .NumOperands: 3, .NumConds: 5 },
2513 {.AsmStrOffset: 6681, .AliasCondStart: 2285, .NumOperands: 3, .NumConds: 4 },
2514 {.AsmStrOffset: 6694, .AliasCondStart: 2289, .NumOperands: 3, .NumConds: 5 },
2515 {.AsmStrOffset: 6707, .AliasCondStart: 2294, .NumOperands: 3, .NumConds: 4 },
2516 {.AsmStrOffset: 6725, .AliasCondStart: 2298, .NumOperands: 3, .NumConds: 5 },
2517 {.AsmStrOffset: 6743, .AliasCondStart: 2303, .NumOperands: 3, .NumConds: 4 },
2518 {.AsmStrOffset: 6756, .AliasCondStart: 2307, .NumOperands: 3, .NumConds: 5 },
2519 {.AsmStrOffset: 6769, .AliasCondStart: 2312, .NumOperands: 3, .NumConds: 4 },
2520 {.AsmStrOffset: 6787, .AliasCondStart: 2316, .NumOperands: 3, .NumConds: 5 },
2521 // SP::TRAPri - 513
2522 {.AsmStrOffset: 6805, .AliasCondStart: 2321, .NumOperands: 3, .NumConds: 3 },
2523 {.AsmStrOffset: 6811, .AliasCondStart: 2324, .NumOperands: 3, .NumConds: 3 },
2524 {.AsmStrOffset: 6822, .AliasCondStart: 2327, .NumOperands: 3, .NumConds: 3 },
2525 {.AsmStrOffset: 6828, .AliasCondStart: 2330, .NumOperands: 3, .NumConds: 3 },
2526 {.AsmStrOffset: 6839, .AliasCondStart: 2333, .NumOperands: 3, .NumConds: 3 },
2527 {.AsmStrOffset: 6846, .AliasCondStart: 2336, .NumOperands: 3, .NumConds: 3 },
2528 {.AsmStrOffset: 6858, .AliasCondStart: 2339, .NumOperands: 3, .NumConds: 3 },
2529 {.AsmStrOffset: 6864, .AliasCondStart: 2342, .NumOperands: 3, .NumConds: 3 },
2530 {.AsmStrOffset: 6875, .AliasCondStart: 2345, .NumOperands: 3, .NumConds: 3 },
2531 {.AsmStrOffset: 6881, .AliasCondStart: 2348, .NumOperands: 3, .NumConds: 3 },
2532 {.AsmStrOffset: 6892, .AliasCondStart: 2351, .NumOperands: 3, .NumConds: 3 },
2533 {.AsmStrOffset: 6899, .AliasCondStart: 2354, .NumOperands: 3, .NumConds: 3 },
2534 {.AsmStrOffset: 6911, .AliasCondStart: 2357, .NumOperands: 3, .NumConds: 3 },
2535 {.AsmStrOffset: 6918, .AliasCondStart: 2360, .NumOperands: 3, .NumConds: 3 },
2536 {.AsmStrOffset: 6930, .AliasCondStart: 2363, .NumOperands: 3, .NumConds: 3 },
2537 {.AsmStrOffset: 6936, .AliasCondStart: 2366, .NumOperands: 3, .NumConds: 3 },
2538 {.AsmStrOffset: 6947, .AliasCondStart: 2369, .NumOperands: 3, .NumConds: 3 },
2539 {.AsmStrOffset: 6954, .AliasCondStart: 2372, .NumOperands: 3, .NumConds: 3 },
2540 {.AsmStrOffset: 6966, .AliasCondStart: 2375, .NumOperands: 3, .NumConds: 3 },
2541 {.AsmStrOffset: 6974, .AliasCondStart: 2378, .NumOperands: 3, .NumConds: 3 },
2542 {.AsmStrOffset: 6987, .AliasCondStart: 2381, .NumOperands: 3, .NumConds: 3 },
2543 {.AsmStrOffset: 6994, .AliasCondStart: 2384, .NumOperands: 3, .NumConds: 3 },
2544 {.AsmStrOffset: 7006, .AliasCondStart: 2387, .NumOperands: 3, .NumConds: 3 },
2545 {.AsmStrOffset: 7013, .AliasCondStart: 2390, .NumOperands: 3, .NumConds: 3 },
2546 {.AsmStrOffset: 7025, .AliasCondStart: 2393, .NumOperands: 3, .NumConds: 3 },
2547 {.AsmStrOffset: 7033, .AliasCondStart: 2396, .NumOperands: 3, .NumConds: 3 },
2548 {.AsmStrOffset: 7046, .AliasCondStart: 2399, .NumOperands: 3, .NumConds: 3 },
2549 {.AsmStrOffset: 7054, .AliasCondStart: 2402, .NumOperands: 3, .NumConds: 3 },
2550 {.AsmStrOffset: 7067, .AliasCondStart: 2405, .NumOperands: 3, .NumConds: 3 },
2551 {.AsmStrOffset: 7074, .AliasCondStart: 2408, .NumOperands: 3, .NumConds: 3 },
2552 {.AsmStrOffset: 7086, .AliasCondStart: 2411, .NumOperands: 3, .NumConds: 3 },
2553 {.AsmStrOffset: 7093, .AliasCondStart: 2414, .NumOperands: 3, .NumConds: 3 },
2554 // SP::TRAPrr - 545
2555 {.AsmStrOffset: 6805, .AliasCondStart: 2417, .NumOperands: 3, .NumConds: 3 },
2556 {.AsmStrOffset: 6811, .AliasCondStart: 2420, .NumOperands: 3, .NumConds: 3 },
2557 {.AsmStrOffset: 6822, .AliasCondStart: 2423, .NumOperands: 3, .NumConds: 3 },
2558 {.AsmStrOffset: 6828, .AliasCondStart: 2426, .NumOperands: 3, .NumConds: 3 },
2559 {.AsmStrOffset: 6839, .AliasCondStart: 2429, .NumOperands: 3, .NumConds: 3 },
2560 {.AsmStrOffset: 6846, .AliasCondStart: 2432, .NumOperands: 3, .NumConds: 3 },
2561 {.AsmStrOffset: 6858, .AliasCondStart: 2435, .NumOperands: 3, .NumConds: 3 },
2562 {.AsmStrOffset: 6864, .AliasCondStart: 2438, .NumOperands: 3, .NumConds: 3 },
2563 {.AsmStrOffset: 6875, .AliasCondStart: 2441, .NumOperands: 3, .NumConds: 3 },
2564 {.AsmStrOffset: 6881, .AliasCondStart: 2444, .NumOperands: 3, .NumConds: 3 },
2565 {.AsmStrOffset: 6892, .AliasCondStart: 2447, .NumOperands: 3, .NumConds: 3 },
2566 {.AsmStrOffset: 6899, .AliasCondStart: 2450, .NumOperands: 3, .NumConds: 3 },
2567 {.AsmStrOffset: 6911, .AliasCondStart: 2453, .NumOperands: 3, .NumConds: 3 },
2568 {.AsmStrOffset: 6918, .AliasCondStart: 2456, .NumOperands: 3, .NumConds: 3 },
2569 {.AsmStrOffset: 6930, .AliasCondStart: 2459, .NumOperands: 3, .NumConds: 3 },
2570 {.AsmStrOffset: 6936, .AliasCondStart: 2462, .NumOperands: 3, .NumConds: 3 },
2571 {.AsmStrOffset: 6947, .AliasCondStart: 2465, .NumOperands: 3, .NumConds: 3 },
2572 {.AsmStrOffset: 6954, .AliasCondStart: 2468, .NumOperands: 3, .NumConds: 3 },
2573 {.AsmStrOffset: 6966, .AliasCondStart: 2471, .NumOperands: 3, .NumConds: 3 },
2574 {.AsmStrOffset: 6974, .AliasCondStart: 2474, .NumOperands: 3, .NumConds: 3 },
2575 {.AsmStrOffset: 6987, .AliasCondStart: 2477, .NumOperands: 3, .NumConds: 3 },
2576 {.AsmStrOffset: 6994, .AliasCondStart: 2480, .NumOperands: 3, .NumConds: 3 },
2577 {.AsmStrOffset: 7006, .AliasCondStart: 2483, .NumOperands: 3, .NumConds: 3 },
2578 {.AsmStrOffset: 7013, .AliasCondStart: 2486, .NumOperands: 3, .NumConds: 3 },
2579 {.AsmStrOffset: 7025, .AliasCondStart: 2489, .NumOperands: 3, .NumConds: 3 },
2580 {.AsmStrOffset: 7033, .AliasCondStart: 2492, .NumOperands: 3, .NumConds: 3 },
2581 {.AsmStrOffset: 7046, .AliasCondStart: 2495, .NumOperands: 3, .NumConds: 3 },
2582 {.AsmStrOffset: 7054, .AliasCondStart: 2498, .NumOperands: 3, .NumConds: 3 },
2583 {.AsmStrOffset: 7067, .AliasCondStart: 2501, .NumOperands: 3, .NumConds: 3 },
2584 {.AsmStrOffset: 7074, .AliasCondStart: 2504, .NumOperands: 3, .NumConds: 3 },
2585 {.AsmStrOffset: 7086, .AliasCondStart: 2507, .NumOperands: 3, .NumConds: 3 },
2586 {.AsmStrOffset: 7093, .AliasCondStart: 2510, .NumOperands: 3, .NumConds: 3 },
2587 // SP::TXCCri - 577
2588 {.AsmStrOffset: 7105, .AliasCondStart: 2513, .NumOperands: 3, .NumConds: 4 },
2589 {.AsmStrOffset: 5833, .AliasCondStart: 2517, .NumOperands: 3, .NumConds: 5 },
2590 {.AsmStrOffset: 7117, .AliasCondStart: 2522, .NumOperands: 3, .NumConds: 4 },
2591 {.AsmStrOffset: 5862, .AliasCondStart: 2526, .NumOperands: 3, .NumConds: 5 },
2592 {.AsmStrOffset: 7134, .AliasCondStart: 2531, .NumOperands: 3, .NumConds: 4 },
2593 {.AsmStrOffset: 5891, .AliasCondStart: 2535, .NumOperands: 3, .NumConds: 5 },
2594 {.AsmStrOffset: 7146, .AliasCondStart: 2540, .NumOperands: 3, .NumConds: 4 },
2595 {.AsmStrOffset: 5920, .AliasCondStart: 2544, .NumOperands: 3, .NumConds: 5 },
2596 {.AsmStrOffset: 7163, .AliasCondStart: 2549, .NumOperands: 3, .NumConds: 4 },
2597 {.AsmStrOffset: 5950, .AliasCondStart: 2553, .NumOperands: 3, .NumConds: 5 },
2598 {.AsmStrOffset: 7176, .AliasCondStart: 2558, .NumOperands: 3, .NumConds: 4 },
2599 {.AsmStrOffset: 5981, .AliasCondStart: 2562, .NumOperands: 3, .NumConds: 5 },
2600 {.AsmStrOffset: 7194, .AliasCondStart: 2567, .NumOperands: 3, .NumConds: 4 },
2601 {.AsmStrOffset: 6011, .AliasCondStart: 2571, .NumOperands: 3, .NumConds: 5 },
2602 {.AsmStrOffset: 7206, .AliasCondStart: 2576, .NumOperands: 3, .NumConds: 4 },
2603 {.AsmStrOffset: 6040, .AliasCondStart: 2580, .NumOperands: 3, .NumConds: 5 },
2604 {.AsmStrOffset: 7223, .AliasCondStart: 2585, .NumOperands: 3, .NumConds: 4 },
2605 {.AsmStrOffset: 6069, .AliasCondStart: 2589, .NumOperands: 3, .NumConds: 5 },
2606 {.AsmStrOffset: 7235, .AliasCondStart: 2594, .NumOperands: 3, .NumConds: 4 },
2607 {.AsmStrOffset: 6098, .AliasCondStart: 2598, .NumOperands: 3, .NumConds: 5 },
2608 {.AsmStrOffset: 7252, .AliasCondStart: 2603, .NumOperands: 3, .NumConds: 4 },
2609 {.AsmStrOffset: 6128, .AliasCondStart: 2607, .NumOperands: 3, .NumConds: 5 },
2610 {.AsmStrOffset: 7265, .AliasCondStart: 2612, .NumOperands: 3, .NumConds: 4 },
2611 {.AsmStrOffset: 6159, .AliasCondStart: 2616, .NumOperands: 3, .NumConds: 5 },
2612 {.AsmStrOffset: 7283, .AliasCondStart: 2621, .NumOperands: 3, .NumConds: 4 },
2613 {.AsmStrOffset: 6190, .AliasCondStart: 2625, .NumOperands: 3, .NumConds: 5 },
2614 {.AsmStrOffset: 7296, .AliasCondStart: 2630, .NumOperands: 3, .NumConds: 4 },
2615 {.AsmStrOffset: 6221, .AliasCondStart: 2634, .NumOperands: 3, .NumConds: 5 },
2616 {.AsmStrOffset: 7314, .AliasCondStart: 2639, .NumOperands: 3, .NumConds: 4 },
2617 {.AsmStrOffset: 6251, .AliasCondStart: 2643, .NumOperands: 3, .NumConds: 5 },
2618 {.AsmStrOffset: 7326, .AliasCondStart: 2648, .NumOperands: 3, .NumConds: 4 },
2619 {.AsmStrOffset: 6280, .AliasCondStart: 2652, .NumOperands: 3, .NumConds: 5 },
2620 {.AsmStrOffset: 7343, .AliasCondStart: 2657, .NumOperands: 3, .NumConds: 4 },
2621 {.AsmStrOffset: 6310, .AliasCondStart: 2661, .NumOperands: 3, .NumConds: 5 },
2622 {.AsmStrOffset: 7356, .AliasCondStart: 2666, .NumOperands: 3, .NumConds: 4 },
2623 {.AsmStrOffset: 6341, .AliasCondStart: 2670, .NumOperands: 3, .NumConds: 5 },
2624 {.AsmStrOffset: 7374, .AliasCondStart: 2675, .NumOperands: 3, .NumConds: 4 },
2625 {.AsmStrOffset: 6373, .AliasCondStart: 2679, .NumOperands: 3, .NumConds: 5 },
2626 {.AsmStrOffset: 7388, .AliasCondStart: 2684, .NumOperands: 3, .NumConds: 4 },
2627 {.AsmStrOffset: 6406, .AliasCondStart: 2688, .NumOperands: 3, .NumConds: 5 },
2628 {.AsmStrOffset: 7407, .AliasCondStart: 2693, .NumOperands: 3, .NumConds: 4 },
2629 {.AsmStrOffset: 6438, .AliasCondStart: 2697, .NumOperands: 3, .NumConds: 5 },
2630 {.AsmStrOffset: 7420, .AliasCondStart: 2702, .NumOperands: 3, .NumConds: 4 },
2631 {.AsmStrOffset: 6469, .AliasCondStart: 2706, .NumOperands: 3, .NumConds: 5 },
2632 {.AsmStrOffset: 7438, .AliasCondStart: 2711, .NumOperands: 3, .NumConds: 4 },
2633 {.AsmStrOffset: 6500, .AliasCondStart: 2715, .NumOperands: 3, .NumConds: 5 },
2634 {.AsmStrOffset: 7451, .AliasCondStart: 2720, .NumOperands: 3, .NumConds: 4 },
2635 {.AsmStrOffset: 6531, .AliasCondStart: 2724, .NumOperands: 3, .NumConds: 5 },
2636 {.AsmStrOffset: 7469, .AliasCondStart: 2729, .NumOperands: 3, .NumConds: 4 },
2637 {.AsmStrOffset: 6563, .AliasCondStart: 2733, .NumOperands: 3, .NumConds: 5 },
2638 {.AsmStrOffset: 7483, .AliasCondStart: 2738, .NumOperands: 3, .NumConds: 4 },
2639 {.AsmStrOffset: 6596, .AliasCondStart: 2742, .NumOperands: 3, .NumConds: 5 },
2640 {.AsmStrOffset: 7502, .AliasCondStart: 2747, .NumOperands: 3, .NumConds: 4 },
2641 {.AsmStrOffset: 6629, .AliasCondStart: 2751, .NumOperands: 3, .NumConds: 5 },
2642 {.AsmStrOffset: 7516, .AliasCondStart: 2756, .NumOperands: 3, .NumConds: 4 },
2643 {.AsmStrOffset: 6662, .AliasCondStart: 2760, .NumOperands: 3, .NumConds: 5 },
2644 {.AsmStrOffset: 7535, .AliasCondStart: 2765, .NumOperands: 3, .NumConds: 4 },
2645 {.AsmStrOffset: 6694, .AliasCondStart: 2769, .NumOperands: 3, .NumConds: 5 },
2646 {.AsmStrOffset: 7548, .AliasCondStart: 2774, .NumOperands: 3, .NumConds: 4 },
2647 {.AsmStrOffset: 6725, .AliasCondStart: 2778, .NumOperands: 3, .NumConds: 5 },
2648 {.AsmStrOffset: 7566, .AliasCondStart: 2783, .NumOperands: 3, .NumConds: 4 },
2649 {.AsmStrOffset: 6756, .AliasCondStart: 2787, .NumOperands: 3, .NumConds: 5 },
2650 {.AsmStrOffset: 7579, .AliasCondStart: 2792, .NumOperands: 3, .NumConds: 4 },
2651 {.AsmStrOffset: 6787, .AliasCondStart: 2796, .NumOperands: 3, .NumConds: 5 },
2652 // SP::TXCCrr - 641
2653 {.AsmStrOffset: 7105, .AliasCondStart: 2801, .NumOperands: 3, .NumConds: 4 },
2654 {.AsmStrOffset: 5833, .AliasCondStart: 2805, .NumOperands: 3, .NumConds: 5 },
2655 {.AsmStrOffset: 7117, .AliasCondStart: 2810, .NumOperands: 3, .NumConds: 4 },
2656 {.AsmStrOffset: 5862, .AliasCondStart: 2814, .NumOperands: 3, .NumConds: 5 },
2657 {.AsmStrOffset: 7134, .AliasCondStart: 2819, .NumOperands: 3, .NumConds: 4 },
2658 {.AsmStrOffset: 5891, .AliasCondStart: 2823, .NumOperands: 3, .NumConds: 5 },
2659 {.AsmStrOffset: 7146, .AliasCondStart: 2828, .NumOperands: 3, .NumConds: 4 },
2660 {.AsmStrOffset: 5920, .AliasCondStart: 2832, .NumOperands: 3, .NumConds: 5 },
2661 {.AsmStrOffset: 7163, .AliasCondStart: 2837, .NumOperands: 3, .NumConds: 4 },
2662 {.AsmStrOffset: 5950, .AliasCondStart: 2841, .NumOperands: 3, .NumConds: 5 },
2663 {.AsmStrOffset: 7176, .AliasCondStart: 2846, .NumOperands: 3, .NumConds: 4 },
2664 {.AsmStrOffset: 5981, .AliasCondStart: 2850, .NumOperands: 3, .NumConds: 5 },
2665 {.AsmStrOffset: 7194, .AliasCondStart: 2855, .NumOperands: 3, .NumConds: 4 },
2666 {.AsmStrOffset: 6011, .AliasCondStart: 2859, .NumOperands: 3, .NumConds: 5 },
2667 {.AsmStrOffset: 7206, .AliasCondStart: 2864, .NumOperands: 3, .NumConds: 4 },
2668 {.AsmStrOffset: 6040, .AliasCondStart: 2868, .NumOperands: 3, .NumConds: 5 },
2669 {.AsmStrOffset: 7223, .AliasCondStart: 2873, .NumOperands: 3, .NumConds: 4 },
2670 {.AsmStrOffset: 6069, .AliasCondStart: 2877, .NumOperands: 3, .NumConds: 5 },
2671 {.AsmStrOffset: 7235, .AliasCondStart: 2882, .NumOperands: 3, .NumConds: 4 },
2672 {.AsmStrOffset: 6098, .AliasCondStart: 2886, .NumOperands: 3, .NumConds: 5 },
2673 {.AsmStrOffset: 7252, .AliasCondStart: 2891, .NumOperands: 3, .NumConds: 4 },
2674 {.AsmStrOffset: 6128, .AliasCondStart: 2895, .NumOperands: 3, .NumConds: 5 },
2675 {.AsmStrOffset: 7265, .AliasCondStart: 2900, .NumOperands: 3, .NumConds: 4 },
2676 {.AsmStrOffset: 6159, .AliasCondStart: 2904, .NumOperands: 3, .NumConds: 5 },
2677 {.AsmStrOffset: 7283, .AliasCondStart: 2909, .NumOperands: 3, .NumConds: 4 },
2678 {.AsmStrOffset: 6190, .AliasCondStart: 2913, .NumOperands: 3, .NumConds: 5 },
2679 {.AsmStrOffset: 7296, .AliasCondStart: 2918, .NumOperands: 3, .NumConds: 4 },
2680 {.AsmStrOffset: 6221, .AliasCondStart: 2922, .NumOperands: 3, .NumConds: 5 },
2681 {.AsmStrOffset: 7314, .AliasCondStart: 2927, .NumOperands: 3, .NumConds: 4 },
2682 {.AsmStrOffset: 6251, .AliasCondStart: 2931, .NumOperands: 3, .NumConds: 5 },
2683 {.AsmStrOffset: 7326, .AliasCondStart: 2936, .NumOperands: 3, .NumConds: 4 },
2684 {.AsmStrOffset: 6280, .AliasCondStart: 2940, .NumOperands: 3, .NumConds: 5 },
2685 {.AsmStrOffset: 7343, .AliasCondStart: 2945, .NumOperands: 3, .NumConds: 4 },
2686 {.AsmStrOffset: 6310, .AliasCondStart: 2949, .NumOperands: 3, .NumConds: 5 },
2687 {.AsmStrOffset: 7356, .AliasCondStart: 2954, .NumOperands: 3, .NumConds: 4 },
2688 {.AsmStrOffset: 6341, .AliasCondStart: 2958, .NumOperands: 3, .NumConds: 5 },
2689 {.AsmStrOffset: 7374, .AliasCondStart: 2963, .NumOperands: 3, .NumConds: 4 },
2690 {.AsmStrOffset: 6373, .AliasCondStart: 2967, .NumOperands: 3, .NumConds: 5 },
2691 {.AsmStrOffset: 7388, .AliasCondStart: 2972, .NumOperands: 3, .NumConds: 4 },
2692 {.AsmStrOffset: 6406, .AliasCondStart: 2976, .NumOperands: 3, .NumConds: 5 },
2693 {.AsmStrOffset: 7407, .AliasCondStart: 2981, .NumOperands: 3, .NumConds: 4 },
2694 {.AsmStrOffset: 6438, .AliasCondStart: 2985, .NumOperands: 3, .NumConds: 5 },
2695 {.AsmStrOffset: 7420, .AliasCondStart: 2990, .NumOperands: 3, .NumConds: 4 },
2696 {.AsmStrOffset: 6469, .AliasCondStart: 2994, .NumOperands: 3, .NumConds: 5 },
2697 {.AsmStrOffset: 7438, .AliasCondStart: 2999, .NumOperands: 3, .NumConds: 4 },
2698 {.AsmStrOffset: 6500, .AliasCondStart: 3003, .NumOperands: 3, .NumConds: 5 },
2699 {.AsmStrOffset: 7451, .AliasCondStart: 3008, .NumOperands: 3, .NumConds: 4 },
2700 {.AsmStrOffset: 6531, .AliasCondStart: 3012, .NumOperands: 3, .NumConds: 5 },
2701 {.AsmStrOffset: 7469, .AliasCondStart: 3017, .NumOperands: 3, .NumConds: 4 },
2702 {.AsmStrOffset: 6563, .AliasCondStart: 3021, .NumOperands: 3, .NumConds: 5 },
2703 {.AsmStrOffset: 7483, .AliasCondStart: 3026, .NumOperands: 3, .NumConds: 4 },
2704 {.AsmStrOffset: 6596, .AliasCondStart: 3030, .NumOperands: 3, .NumConds: 5 },
2705 {.AsmStrOffset: 7502, .AliasCondStart: 3035, .NumOperands: 3, .NumConds: 4 },
2706 {.AsmStrOffset: 6629, .AliasCondStart: 3039, .NumOperands: 3, .NumConds: 5 },
2707 {.AsmStrOffset: 7516, .AliasCondStart: 3044, .NumOperands: 3, .NumConds: 4 },
2708 {.AsmStrOffset: 6662, .AliasCondStart: 3048, .NumOperands: 3, .NumConds: 5 },
2709 {.AsmStrOffset: 7535, .AliasCondStart: 3053, .NumOperands: 3, .NumConds: 4 },
2710 {.AsmStrOffset: 6694, .AliasCondStart: 3057, .NumOperands: 3, .NumConds: 5 },
2711 {.AsmStrOffset: 7548, .AliasCondStart: 3062, .NumOperands: 3, .NumConds: 4 },
2712 {.AsmStrOffset: 6725, .AliasCondStart: 3066, .NumOperands: 3, .NumConds: 5 },
2713 {.AsmStrOffset: 7566, .AliasCondStart: 3071, .NumOperands: 3, .NumConds: 4 },
2714 {.AsmStrOffset: 6756, .AliasCondStart: 3075, .NumOperands: 3, .NumConds: 5 },
2715 {.AsmStrOffset: 7579, .AliasCondStart: 3080, .NumOperands: 3, .NumConds: 4 },
2716 {.AsmStrOffset: 6787, .AliasCondStart: 3084, .NumOperands: 3, .NumConds: 5 },
2717 // SP::V9FCMPD - 705
2718 {.AsmStrOffset: 7597, .AliasCondStart: 3089, .NumOperands: 3, .NumConds: 3 },
2719 // SP::V9FCMPED - 706
2720 {.AsmStrOffset: 7610, .AliasCondStart: 3092, .NumOperands: 3, .NumConds: 3 },
2721 // SP::V9FCMPEQ - 707
2722 {.AsmStrOffset: 7624, .AliasCondStart: 3095, .NumOperands: 3, .NumConds: 3 },
2723 // SP::V9FCMPES - 708
2724 {.AsmStrOffset: 7638, .AliasCondStart: 3098, .NumOperands: 3, .NumConds: 3 },
2725 // SP::V9FCMPQ - 709
2726 {.AsmStrOffset: 7652, .AliasCondStart: 3101, .NumOperands: 3, .NumConds: 3 },
2727 // SP::V9FCMPS - 710
2728 {.AsmStrOffset: 7665, .AliasCondStart: 3104, .NumOperands: 3, .NumConds: 3 },
2729 // SP::V9FMOVD_FCC - 711
2730 {.AsmStrOffset: 7678, .AliasCondStart: 3107, .NumOperands: 5, .NumConds: 6 },
2731 {.AsmStrOffset: 7696, .AliasCondStart: 3113, .NumOperands: 5, .NumConds: 6 },
2732 {.AsmStrOffset: 7714, .AliasCondStart: 3119, .NumOperands: 5, .NumConds: 6 },
2733 {.AsmStrOffset: 7732, .AliasCondStart: 3125, .NumOperands: 5, .NumConds: 6 },
2734 {.AsmStrOffset: 7750, .AliasCondStart: 3131, .NumOperands: 5, .NumConds: 6 },
2735 {.AsmStrOffset: 7769, .AliasCondStart: 3137, .NumOperands: 5, .NumConds: 6 },
2736 {.AsmStrOffset: 7787, .AliasCondStart: 3143, .NumOperands: 5, .NumConds: 6 },
2737 {.AsmStrOffset: 7806, .AliasCondStart: 3149, .NumOperands: 5, .NumConds: 6 },
2738 {.AsmStrOffset: 7825, .AliasCondStart: 3155, .NumOperands: 5, .NumConds: 6 },
2739 {.AsmStrOffset: 7844, .AliasCondStart: 3161, .NumOperands: 5, .NumConds: 6 },
2740 {.AsmStrOffset: 7862, .AliasCondStart: 3167, .NumOperands: 5, .NumConds: 6 },
2741 {.AsmStrOffset: 7881, .AliasCondStart: 3173, .NumOperands: 5, .NumConds: 6 },
2742 {.AsmStrOffset: 7900, .AliasCondStart: 3179, .NumOperands: 5, .NumConds: 6 },
2743 {.AsmStrOffset: 7920, .AliasCondStart: 3185, .NumOperands: 5, .NumConds: 6 },
2744 {.AsmStrOffset: 7939, .AliasCondStart: 3191, .NumOperands: 5, .NumConds: 6 },
2745 {.AsmStrOffset: 7959, .AliasCondStart: 3197, .NumOperands: 5, .NumConds: 6 },
2746 // SP::V9FMOVQ_FCC - 727
2747 {.AsmStrOffset: 7977, .AliasCondStart: 3203, .NumOperands: 5, .NumConds: 6 },
2748 {.AsmStrOffset: 7995, .AliasCondStart: 3209, .NumOperands: 5, .NumConds: 6 },
2749 {.AsmStrOffset: 8013, .AliasCondStart: 3215, .NumOperands: 5, .NumConds: 6 },
2750 {.AsmStrOffset: 8031, .AliasCondStart: 3221, .NumOperands: 5, .NumConds: 6 },
2751 {.AsmStrOffset: 8049, .AliasCondStart: 3227, .NumOperands: 5, .NumConds: 6 },
2752 {.AsmStrOffset: 8068, .AliasCondStart: 3233, .NumOperands: 5, .NumConds: 6 },
2753 {.AsmStrOffset: 8086, .AliasCondStart: 3239, .NumOperands: 5, .NumConds: 6 },
2754 {.AsmStrOffset: 8105, .AliasCondStart: 3245, .NumOperands: 5, .NumConds: 6 },
2755 {.AsmStrOffset: 8124, .AliasCondStart: 3251, .NumOperands: 5, .NumConds: 6 },
2756 {.AsmStrOffset: 8143, .AliasCondStart: 3257, .NumOperands: 5, .NumConds: 6 },
2757 {.AsmStrOffset: 8161, .AliasCondStart: 3263, .NumOperands: 5, .NumConds: 6 },
2758 {.AsmStrOffset: 8180, .AliasCondStart: 3269, .NumOperands: 5, .NumConds: 6 },
2759 {.AsmStrOffset: 8199, .AliasCondStart: 3275, .NumOperands: 5, .NumConds: 6 },
2760 {.AsmStrOffset: 8219, .AliasCondStart: 3281, .NumOperands: 5, .NumConds: 6 },
2761 {.AsmStrOffset: 8238, .AliasCondStart: 3287, .NumOperands: 5, .NumConds: 6 },
2762 {.AsmStrOffset: 8258, .AliasCondStart: 3293, .NumOperands: 5, .NumConds: 6 },
2763 // SP::V9FMOVS_FCC - 743
2764 {.AsmStrOffset: 8276, .AliasCondStart: 3299, .NumOperands: 5, .NumConds: 6 },
2765 {.AsmStrOffset: 8294, .AliasCondStart: 3305, .NumOperands: 5, .NumConds: 6 },
2766 {.AsmStrOffset: 8312, .AliasCondStart: 3311, .NumOperands: 5, .NumConds: 6 },
2767 {.AsmStrOffset: 8330, .AliasCondStart: 3317, .NumOperands: 5, .NumConds: 6 },
2768 {.AsmStrOffset: 8348, .AliasCondStart: 3323, .NumOperands: 5, .NumConds: 6 },
2769 {.AsmStrOffset: 8367, .AliasCondStart: 3329, .NumOperands: 5, .NumConds: 6 },
2770 {.AsmStrOffset: 8385, .AliasCondStart: 3335, .NumOperands: 5, .NumConds: 6 },
2771 {.AsmStrOffset: 8404, .AliasCondStart: 3341, .NumOperands: 5, .NumConds: 6 },
2772 {.AsmStrOffset: 8423, .AliasCondStart: 3347, .NumOperands: 5, .NumConds: 6 },
2773 {.AsmStrOffset: 8442, .AliasCondStart: 3353, .NumOperands: 5, .NumConds: 6 },
2774 {.AsmStrOffset: 8460, .AliasCondStart: 3359, .NumOperands: 5, .NumConds: 6 },
2775 {.AsmStrOffset: 8479, .AliasCondStart: 3365, .NumOperands: 5, .NumConds: 6 },
2776 {.AsmStrOffset: 8498, .AliasCondStart: 3371, .NumOperands: 5, .NumConds: 6 },
2777 {.AsmStrOffset: 8518, .AliasCondStart: 3377, .NumOperands: 5, .NumConds: 6 },
2778 {.AsmStrOffset: 8537, .AliasCondStart: 3383, .NumOperands: 5, .NumConds: 6 },
2779 {.AsmStrOffset: 8557, .AliasCondStart: 3389, .NumOperands: 5, .NumConds: 6 },
2780 // SP::V9MOVFCCri - 759
2781 {.AsmStrOffset: 8575, .AliasCondStart: 3395, .NumOperands: 5, .NumConds: 6 },
2782 {.AsmStrOffset: 8591, .AliasCondStart: 3401, .NumOperands: 5, .NumConds: 6 },
2783 {.AsmStrOffset: 8607, .AliasCondStart: 3407, .NumOperands: 5, .NumConds: 6 },
2784 {.AsmStrOffset: 8623, .AliasCondStart: 3413, .NumOperands: 5, .NumConds: 6 },
2785 {.AsmStrOffset: 8639, .AliasCondStart: 3419, .NumOperands: 5, .NumConds: 6 },
2786 {.AsmStrOffset: 8656, .AliasCondStart: 3425, .NumOperands: 5, .NumConds: 6 },
2787 {.AsmStrOffset: 8672, .AliasCondStart: 3431, .NumOperands: 5, .NumConds: 6 },
2788 {.AsmStrOffset: 8689, .AliasCondStart: 3437, .NumOperands: 5, .NumConds: 6 },
2789 {.AsmStrOffset: 8706, .AliasCondStart: 3443, .NumOperands: 5, .NumConds: 6 },
2790 {.AsmStrOffset: 8723, .AliasCondStart: 3449, .NumOperands: 5, .NumConds: 6 },
2791 {.AsmStrOffset: 8739, .AliasCondStart: 3455, .NumOperands: 5, .NumConds: 6 },
2792 {.AsmStrOffset: 8756, .AliasCondStart: 3461, .NumOperands: 5, .NumConds: 6 },
2793 {.AsmStrOffset: 8773, .AliasCondStart: 3467, .NumOperands: 5, .NumConds: 6 },
2794 {.AsmStrOffset: 8791, .AliasCondStart: 3473, .NumOperands: 5, .NumConds: 6 },
2795 {.AsmStrOffset: 8808, .AliasCondStart: 3479, .NumOperands: 5, .NumConds: 6 },
2796 {.AsmStrOffset: 8826, .AliasCondStart: 3485, .NumOperands: 5, .NumConds: 6 },
2797 // SP::V9MOVFCCrr - 775
2798 {.AsmStrOffset: 8575, .AliasCondStart: 3491, .NumOperands: 5, .NumConds: 6 },
2799 {.AsmStrOffset: 8591, .AliasCondStart: 3497, .NumOperands: 5, .NumConds: 6 },
2800 {.AsmStrOffset: 8607, .AliasCondStart: 3503, .NumOperands: 5, .NumConds: 6 },
2801 {.AsmStrOffset: 8623, .AliasCondStart: 3509, .NumOperands: 5, .NumConds: 6 },
2802 {.AsmStrOffset: 8639, .AliasCondStart: 3515, .NumOperands: 5, .NumConds: 6 },
2803 {.AsmStrOffset: 8656, .AliasCondStart: 3521, .NumOperands: 5, .NumConds: 6 },
2804 {.AsmStrOffset: 8672, .AliasCondStart: 3527, .NumOperands: 5, .NumConds: 6 },
2805 {.AsmStrOffset: 8689, .AliasCondStart: 3533, .NumOperands: 5, .NumConds: 6 },
2806 {.AsmStrOffset: 8706, .AliasCondStart: 3539, .NumOperands: 5, .NumConds: 6 },
2807 {.AsmStrOffset: 8723, .AliasCondStart: 3545, .NumOperands: 5, .NumConds: 6 },
2808 {.AsmStrOffset: 8739, .AliasCondStart: 3551, .NumOperands: 5, .NumConds: 6 },
2809 {.AsmStrOffset: 8756, .AliasCondStart: 3557, .NumOperands: 5, .NumConds: 6 },
2810 {.AsmStrOffset: 8773, .AliasCondStart: 3563, .NumOperands: 5, .NumConds: 6 },
2811 {.AsmStrOffset: 8791, .AliasCondStart: 3569, .NumOperands: 5, .NumConds: 6 },
2812 {.AsmStrOffset: 8808, .AliasCondStart: 3575, .NumOperands: 5, .NumConds: 6 },
2813 {.AsmStrOffset: 8826, .AliasCondStart: 3581, .NumOperands: 5, .NumConds: 6 },
2814 // SP::WRASRri - 791
2815 {.AsmStrOffset: 8842, .AliasCondStart: 3587, .NumOperands: 3, .NumConds: 3 },
2816 // SP::WRASRrr - 792
2817 {.AsmStrOffset: 8842, .AliasCondStart: 3590, .NumOperands: 3, .NumConds: 4 },
2818 };
2819
2820 static const AliasPatternCond Conds[] = {
2821 // (BCOND brtarget:$imm, 8) - 0
2822 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2823 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2824 // (BCOND brtarget:$imm, 0) - 2
2825 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2826 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2827 // (BCOND brtarget:$imm, 9) - 4
2828 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2829 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2830 // (BCOND brtarget:$imm, 1) - 6
2831 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2832 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2833 // (BCOND brtarget:$imm, 10) - 8
2834 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2835 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2836 // (BCOND brtarget:$imm, 2) - 10
2837 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2838 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2839 // (BCOND brtarget:$imm, 11) - 12
2840 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2841 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2842 // (BCOND brtarget:$imm, 3) - 14
2843 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2844 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2845 // (BCOND brtarget:$imm, 12) - 16
2846 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2847 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2848 // (BCOND brtarget:$imm, 4) - 18
2849 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2850 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2851 // (BCOND brtarget:$imm, 13) - 20
2852 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2853 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2854 // (BCOND brtarget:$imm, 5) - 22
2855 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2856 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2857 // (BCOND brtarget:$imm, 14) - 24
2858 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2859 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2860 // (BCOND brtarget:$imm, 6) - 26
2861 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2862 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2863 // (BCOND brtarget:$imm, 15) - 28
2864 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2865 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2866 // (BCOND brtarget:$imm, 7) - 30
2867 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2868 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2869 // (BCONDA brtarget:$imm, 8) - 32
2870 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2871 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2872 // (BCONDA brtarget:$imm, 0) - 34
2873 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2874 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2875 // (BCONDA brtarget:$imm, 9) - 36
2876 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2877 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2878 // (BCONDA brtarget:$imm, 1) - 38
2879 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2880 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2881 // (BCONDA brtarget:$imm, 10) - 40
2882 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2883 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2884 // (BCONDA brtarget:$imm, 2) - 42
2885 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2886 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2887 // (BCONDA brtarget:$imm, 11) - 44
2888 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2889 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2890 // (BCONDA brtarget:$imm, 3) - 46
2891 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2892 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2893 // (BCONDA brtarget:$imm, 12) - 48
2894 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2895 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2896 // (BCONDA brtarget:$imm, 4) - 50
2897 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2898 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2899 // (BCONDA brtarget:$imm, 13) - 52
2900 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2901 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2902 // (BCONDA brtarget:$imm, 5) - 54
2903 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2904 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2905 // (BCONDA brtarget:$imm, 14) - 56
2906 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2907 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2908 // (BCONDA brtarget:$imm, 6) - 58
2909 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2910 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2911 // (BCONDA brtarget:$imm, 15) - 60
2912 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2913 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2914 // (BCONDA brtarget:$imm, 7) - 62
2915 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2916 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2917 // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc) - 64
2918 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2919 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2920 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2921 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2922 // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc) - 68
2923 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2924 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2925 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2926 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2927 // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc) - 72
2928 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2929 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2930 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2931 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2932 // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc) - 76
2933 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2934 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2935 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2936 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2937 // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc) - 80
2938 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2939 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2940 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2941 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2942 // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc) - 84
2943 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2944 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2945 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2946 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2947 // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc) - 88
2948 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2949 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2950 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2951 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2952 // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc) - 92
2953 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2954 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2955 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2956 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2957 // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc) - 96
2958 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2959 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2960 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2961 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2962 // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc) - 100
2963 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2964 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2965 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2966 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2967 // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc) - 104
2968 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2969 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2970 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2971 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2972 // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc) - 108
2973 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2974 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2975 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2976 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2977 // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc) - 112
2978 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2979 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2980 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2981 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2982 // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc) - 116
2983 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2984 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2985 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2986 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2987 // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc) - 120
2988 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2989 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2990 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2991 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2992 // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc) - 124
2993 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2994 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2995 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2996 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2997 // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc) - 128
2998 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2999 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3000 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3001 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3002 // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc) - 132
3003 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3004 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3005 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3006 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3007 // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc) - 136
3008 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3009 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3010 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3011 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3012 // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc) - 140
3013 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3014 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3015 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3016 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3017 // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc) - 144
3018 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3019 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3020 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3021 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3022 // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc) - 148
3023 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3024 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3025 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3026 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3027 // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc) - 152
3028 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3029 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3030 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3031 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3032 // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc) - 156
3033 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3034 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3035 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3036 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3037 // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc) - 160
3038 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3039 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3040 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3041 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3042 // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc) - 164
3043 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3044 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3045 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3046 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3047 // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc) - 168
3048 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3049 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3050 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3051 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3052 // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc) - 172
3053 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3054 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3055 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3056 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3057 // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc) - 176
3058 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3059 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3060 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3061 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3062 // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc) - 180
3063 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3064 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3065 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3066 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3067 // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc) - 184
3068 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3069 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3070 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3071 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3072 // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc) - 188
3073 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3074 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3075 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3076 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3077 // (BPICCANT brtarget:$imm, 8) - 192
3078 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3079 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3080 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3081 // (BPICCANT brtarget:$imm, 8) - 195
3082 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3083 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3084 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3085 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3086 // (BPICCANT brtarget:$imm, 0) - 199
3087 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3088 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3089 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3090 // (BPICCANT brtarget:$imm, 0) - 202
3091 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3092 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3093 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3094 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3095 // (BPICCANT brtarget:$imm, 9) - 206
3096 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3097 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3098 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3099 // (BPICCANT brtarget:$imm, 9) - 209
3100 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3101 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3102 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3103 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3104 // (BPICCANT brtarget:$imm, 1) - 213
3105 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3106 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3107 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3108 // (BPICCANT brtarget:$imm, 1) - 216
3109 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3110 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3111 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3112 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3113 // (BPICCANT brtarget:$imm, 10) - 220
3114 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3115 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3116 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3117 // (BPICCANT brtarget:$imm, 10) - 223
3118 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3119 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3120 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3121 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3122 // (BPICCANT brtarget:$imm, 2) - 227
3123 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3124 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3125 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3126 // (BPICCANT brtarget:$imm, 2) - 230
3127 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3128 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3129 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3130 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3131 // (BPICCANT brtarget:$imm, 11) - 234
3132 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3133 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3134 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3135 // (BPICCANT brtarget:$imm, 11) - 237
3136 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3137 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3138 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3139 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3140 // (BPICCANT brtarget:$imm, 3) - 241
3141 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3142 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3143 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3144 // (BPICCANT brtarget:$imm, 3) - 244
3145 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3146 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3147 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3148 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3149 // (BPICCANT brtarget:$imm, 12) - 248
3150 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3151 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3152 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3153 // (BPICCANT brtarget:$imm, 12) - 251
3154 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3155 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3156 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3157 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3158 // (BPICCANT brtarget:$imm, 4) - 255
3159 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3160 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3161 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3162 // (BPICCANT brtarget:$imm, 4) - 258
3163 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3164 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3165 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3166 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3167 // (BPICCANT brtarget:$imm, 13) - 262
3168 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3169 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3170 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3171 // (BPICCANT brtarget:$imm, 13) - 265
3172 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3173 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3174 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3175 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3176 // (BPICCANT brtarget:$imm, 5) - 269
3177 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3178 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3179 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3180 // (BPICCANT brtarget:$imm, 5) - 272
3181 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3182 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3183 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3184 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3185 // (BPICCANT brtarget:$imm, 14) - 276
3186 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3187 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3188 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3189 // (BPICCANT brtarget:$imm, 14) - 279
3190 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3191 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3192 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3193 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3194 // (BPICCANT brtarget:$imm, 6) - 283
3195 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3196 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3197 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3198 // (BPICCANT brtarget:$imm, 6) - 286
3199 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3200 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3201 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3202 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3203 // (BPICCANT brtarget:$imm, 15) - 290
3204 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3205 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3206 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3207 // (BPICCANT brtarget:$imm, 15) - 293
3208 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3209 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3210 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3211 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3212 // (BPICCANT brtarget:$imm, 7) - 297
3213 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3214 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3215 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3216 // (BPICCANT brtarget:$imm, 7) - 300
3217 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3218 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3219 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3220 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3221 // (BPICCNT brtarget:$imm, 8) - 304
3222 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3223 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3224 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3225 // (BPICCNT brtarget:$imm, 8) - 307
3226 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3227 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3228 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3229 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3230 // (BPICCNT brtarget:$imm, 0) - 311
3231 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3232 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3233 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3234 // (BPICCNT brtarget:$imm, 0) - 314
3235 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3236 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3237 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3238 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3239 // (BPICCNT brtarget:$imm, 9) - 318
3240 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3241 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3242 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3243 // (BPICCNT brtarget:$imm, 9) - 321
3244 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3245 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3246 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3247 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3248 // (BPICCNT brtarget:$imm, 1) - 325
3249 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3250 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3251 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3252 // (BPICCNT brtarget:$imm, 1) - 328
3253 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3254 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3255 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3256 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3257 // (BPICCNT brtarget:$imm, 10) - 332
3258 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3259 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3260 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3261 // (BPICCNT brtarget:$imm, 10) - 335
3262 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3263 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3264 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3265 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3266 // (BPICCNT brtarget:$imm, 2) - 339
3267 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3268 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3269 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3270 // (BPICCNT brtarget:$imm, 2) - 342
3271 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3272 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3273 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3274 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3275 // (BPICCNT brtarget:$imm, 11) - 346
3276 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3277 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3278 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3279 // (BPICCNT brtarget:$imm, 11) - 349
3280 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3281 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3282 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3283 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3284 // (BPICCNT brtarget:$imm, 3) - 353
3285 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3286 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3287 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3288 // (BPICCNT brtarget:$imm, 3) - 356
3289 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3290 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3291 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3292 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3293 // (BPICCNT brtarget:$imm, 12) - 360
3294 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3295 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3296 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3297 // (BPICCNT brtarget:$imm, 12) - 363
3298 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3299 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3300 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3301 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3302 // (BPICCNT brtarget:$imm, 4) - 367
3303 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3304 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3305 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3306 // (BPICCNT brtarget:$imm, 4) - 370
3307 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3308 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3309 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3310 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3311 // (BPICCNT brtarget:$imm, 13) - 374
3312 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3313 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3314 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3315 // (BPICCNT brtarget:$imm, 13) - 377
3316 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3317 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3318 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3319 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3320 // (BPICCNT brtarget:$imm, 5) - 381
3321 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3322 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3323 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3324 // (BPICCNT brtarget:$imm, 5) - 384
3325 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3326 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3327 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3328 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3329 // (BPICCNT brtarget:$imm, 14) - 388
3330 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3331 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3332 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3333 // (BPICCNT brtarget:$imm, 14) - 391
3334 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3335 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3336 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3337 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3338 // (BPICCNT brtarget:$imm, 6) - 395
3339 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3340 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3341 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3342 // (BPICCNT brtarget:$imm, 6) - 398
3343 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3344 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3345 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3346 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3347 // (BPICCNT brtarget:$imm, 15) - 402
3348 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3349 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3350 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3351 // (BPICCNT brtarget:$imm, 15) - 405
3352 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3353 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3354 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3355 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3356 // (BPICCNT brtarget:$imm, 7) - 409
3357 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3358 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3359 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3360 // (BPICCNT brtarget:$imm, 7) - 412
3361 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3362 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3363 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3364 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3365 // (BPRANT bprtarget16:$imm, 2, I64Regs:$rs1) - 416
3366 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3367 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3368 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3369 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3370 // (BPRANT bprtarget16:$imm, 3, I64Regs:$rs1) - 420
3371 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3372 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3373 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3374 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3375 // (BPRANT bprtarget16:$imm, 6, I64Regs:$rs1) - 424
3376 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3377 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3378 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3379 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3380 // (BPRANT bprtarget16:$imm, 7, I64Regs:$rs1) - 428
3381 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3382 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3383 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3384 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3385 // (BPRNT bprtarget16:$imm, 2, I64Regs:$rs1) - 432
3386 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3387 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3388 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3389 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3390 // (BPRNT bprtarget16:$imm, 3, I64Regs:$rs1) - 436
3391 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3392 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3393 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3394 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3395 // (BPRNT bprtarget16:$imm, 6, I64Regs:$rs1) - 440
3396 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3397 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3398 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3399 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3400 // (BPRNT bprtarget16:$imm, 7, I64Regs:$rs1) - 444
3401 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3402 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3403 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3404 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3405 // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 128) - 448
3406 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3407 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3408 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3409 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3410 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(128)},
3411 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3412 // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 136) - 454
3413 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3414 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3415 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3416 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3417 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(136)},
3418 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3419 // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 128) - 460
3420 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3421 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3422 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3423 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3424 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(128)},
3425 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3426 // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 136) - 466
3427 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3428 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3429 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3430 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3431 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(136)},
3432 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3433 // (CWBCONDri cbtarget:$imm, 9, IntRegs:$rs1, simm5Op:$simm5) - 472
3434 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3435 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3436 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3437 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3438 // (CWBCONDri cbtarget:$imm, 1, IntRegs:$rs1, simm5Op:$simm5) - 476
3439 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3440 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3441 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3442 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3443 // (CWBCONDri cbtarget:$imm, 10, IntRegs:$rs1, simm5Op:$simm5) - 480
3444 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3445 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3446 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3447 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3448 // (CWBCONDri cbtarget:$imm, 2, IntRegs:$rs1, simm5Op:$simm5) - 484
3449 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3450 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3451 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3452 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3453 // (CWBCONDri cbtarget:$imm, 11, IntRegs:$rs1, simm5Op:$simm5) - 488
3454 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3455 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3456 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3457 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3458 // (CWBCONDri cbtarget:$imm, 3, IntRegs:$rs1, simm5Op:$simm5) - 492
3459 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3460 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3461 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3462 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3463 // (CWBCONDri cbtarget:$imm, 12, IntRegs:$rs1, simm5Op:$simm5) - 496
3464 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3465 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3466 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3467 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3468 // (CWBCONDri cbtarget:$imm, 4, IntRegs:$rs1, simm5Op:$simm5) - 500
3469 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3470 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3471 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3472 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3473 // (CWBCONDri cbtarget:$imm, 13, IntRegs:$rs1, simm5Op:$simm5) - 504
3474 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3475 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3476 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3477 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3478 // (CWBCONDri cbtarget:$imm, 5, IntRegs:$rs1, simm5Op:$simm5) - 508
3479 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3480 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3481 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3482 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3483 // (CWBCONDri cbtarget:$imm, 14, IntRegs:$rs1, simm5Op:$simm5) - 512
3484 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3485 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3486 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3487 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3488 // (CWBCONDri cbtarget:$imm, 6, IntRegs:$rs1, simm5Op:$simm5) - 516
3489 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3490 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3491 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3492 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3493 // (CWBCONDri cbtarget:$imm, 15, IntRegs:$rs1, simm5Op:$simm5) - 520
3494 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3495 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3496 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3497 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3498 // (CWBCONDri cbtarget:$imm, 7, IntRegs:$rs1, simm5Op:$simm5) - 524
3499 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3500 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3501 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3502 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3503 // (CWBCONDrr cbtarget:$imm, 9, IntRegs:$rs1, IntRegs:$rs2) - 528
3504 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3505 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3506 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3507 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3508 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3509 // (CWBCONDrr cbtarget:$imm, 1, IntRegs:$rs1, IntRegs:$rs2) - 533
3510 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3511 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3512 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3513 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3514 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3515 // (CWBCONDrr cbtarget:$imm, 10, IntRegs:$rs1, IntRegs:$rs2) - 538
3516 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3517 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3518 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3519 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3520 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3521 // (CWBCONDrr cbtarget:$imm, 2, IntRegs:$rs1, IntRegs:$rs2) - 543
3522 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3523 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3524 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3525 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3526 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3527 // (CWBCONDrr cbtarget:$imm, 11, IntRegs:$rs1, IntRegs:$rs2) - 548
3528 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3529 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3530 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3531 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3532 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3533 // (CWBCONDrr cbtarget:$imm, 3, IntRegs:$rs1, IntRegs:$rs2) - 553
3534 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3535 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3536 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3537 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3538 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3539 // (CWBCONDrr cbtarget:$imm, 12, IntRegs:$rs1, IntRegs:$rs2) - 558
3540 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3541 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3542 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3543 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3544 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3545 // (CWBCONDrr cbtarget:$imm, 4, IntRegs:$rs1, IntRegs:$rs2) - 563
3546 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3547 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3548 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3549 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3550 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3551 // (CWBCONDrr cbtarget:$imm, 13, IntRegs:$rs1, IntRegs:$rs2) - 568
3552 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3553 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3554 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3555 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3556 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3557 // (CWBCONDrr cbtarget:$imm, 5, IntRegs:$rs1, IntRegs:$rs2) - 573
3558 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3559 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3560 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3561 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3562 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3563 // (CWBCONDrr cbtarget:$imm, 14, IntRegs:$rs1, IntRegs:$rs2) - 578
3564 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3565 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3566 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3567 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3568 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3569 // (CWBCONDrr cbtarget:$imm, 6, IntRegs:$rs1, IntRegs:$rs2) - 583
3570 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3571 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3572 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3573 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3574 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3575 // (CWBCONDrr cbtarget:$imm, 15, IntRegs:$rs1, IntRegs:$rs2) - 588
3576 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3577 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3578 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3579 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3580 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3581 // (CWBCONDrr cbtarget:$imm, 7, IntRegs:$rs1, IntRegs:$rs2) - 593
3582 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3583 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3584 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3585 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3586 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3587 // (CXBCONDri cbtarget:$imm, 9, IntRegs:$rs1, simm5Op:$simm5) - 598
3588 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3589 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3590 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3591 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3592 // (CXBCONDri cbtarget:$imm, 1, IntRegs:$rs1, simm5Op:$simm5) - 602
3593 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3594 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3595 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3596 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3597 // (CXBCONDri cbtarget:$imm, 10, IntRegs:$rs1, simm5Op:$simm5) - 606
3598 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3599 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3600 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3601 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3602 // (CXBCONDri cbtarget:$imm, 2, IntRegs:$rs1, simm5Op:$simm5) - 610
3603 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3604 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3605 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3606 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3607 // (CXBCONDri cbtarget:$imm, 11, IntRegs:$rs1, simm5Op:$simm5) - 614
3608 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3609 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3610 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3611 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3612 // (CXBCONDri cbtarget:$imm, 3, IntRegs:$rs1, simm5Op:$simm5) - 618
3613 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3614 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3615 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3616 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3617 // (CXBCONDri cbtarget:$imm, 12, IntRegs:$rs1, simm5Op:$simm5) - 622
3618 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3619 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3620 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3621 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3622 // (CXBCONDri cbtarget:$imm, 4, IntRegs:$rs1, simm5Op:$simm5) - 626
3623 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3624 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3625 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3626 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3627 // (CXBCONDri cbtarget:$imm, 13, IntRegs:$rs1, simm5Op:$simm5) - 630
3628 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3629 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3630 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3631 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3632 // (CXBCONDri cbtarget:$imm, 5, IntRegs:$rs1, simm5Op:$simm5) - 634
3633 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3634 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3635 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3636 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3637 // (CXBCONDri cbtarget:$imm, 14, IntRegs:$rs1, simm5Op:$simm5) - 638
3638 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3639 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3640 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3641 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3642 // (CXBCONDri cbtarget:$imm, 6, IntRegs:$rs1, simm5Op:$simm5) - 642
3643 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3644 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3645 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3646 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3647 // (CXBCONDri cbtarget:$imm, 15, IntRegs:$rs1, simm5Op:$simm5) - 646
3648 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3649 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3650 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3651 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3652 // (CXBCONDri cbtarget:$imm, 7, IntRegs:$rs1, simm5Op:$simm5) - 650
3653 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3654 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3655 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3656 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3657 // (CXBCONDrr cbtarget:$imm, 9, IntRegs:$rs1, IntRegs:$rs2) - 654
3658 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3659 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3660 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3661 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3662 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3663 // (CXBCONDrr cbtarget:$imm, 1, IntRegs:$rs1, IntRegs:$rs2) - 659
3664 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3665 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3666 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3667 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3668 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3669 // (CXBCONDrr cbtarget:$imm, 10, IntRegs:$rs1, IntRegs:$rs2) - 664
3670 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3671 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3672 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3673 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3674 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3675 // (CXBCONDrr cbtarget:$imm, 2, IntRegs:$rs1, IntRegs:$rs2) - 669
3676 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3677 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3678 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3679 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3680 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3681 // (CXBCONDrr cbtarget:$imm, 11, IntRegs:$rs1, IntRegs:$rs2) - 674
3682 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3683 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3684 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3685 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3686 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3687 // (CXBCONDrr cbtarget:$imm, 3, IntRegs:$rs1, IntRegs:$rs2) - 679
3688 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3689 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3690 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3691 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3692 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3693 // (CXBCONDrr cbtarget:$imm, 12, IntRegs:$rs1, IntRegs:$rs2) - 684
3694 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3695 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3696 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3697 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3698 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3699 // (CXBCONDrr cbtarget:$imm, 4, IntRegs:$rs1, IntRegs:$rs2) - 689
3700 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3701 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3702 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3703 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3704 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3705 // (CXBCONDrr cbtarget:$imm, 13, IntRegs:$rs1, IntRegs:$rs2) - 694
3706 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3707 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3708 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3709 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3710 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3711 // (CXBCONDrr cbtarget:$imm, 5, IntRegs:$rs1, IntRegs:$rs2) - 699
3712 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3713 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3714 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3715 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3716 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3717 // (CXBCONDrr cbtarget:$imm, 14, IntRegs:$rs1, IntRegs:$rs2) - 704
3718 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3719 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3720 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3721 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3722 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3723 // (CXBCONDrr cbtarget:$imm, 6, IntRegs:$rs1, IntRegs:$rs2) - 709
3724 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3725 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3726 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3727 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3728 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3729 // (CXBCONDrr cbtarget:$imm, 15, IntRegs:$rs1, IntRegs:$rs2) - 714
3730 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3731 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3732 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3733 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3734 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3735 // (CXBCONDrr cbtarget:$imm, 7, IntRegs:$rs1, IntRegs:$rs2) - 719
3736 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3737 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3738 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3739 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3740 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3741 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8) - 724
3742 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3743 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3744 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3745 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3746 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3747 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8) - 729
3748 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3749 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3750 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3751 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3752 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3753 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3754 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0) - 735
3755 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3756 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3757 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3758 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3759 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3760 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0) - 740
3761 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3762 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3763 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3764 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3765 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3766 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3767 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9) - 746
3768 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3769 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3770 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3771 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3772 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3773 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9) - 751
3774 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3775 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3776 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3777 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3778 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3779 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3780 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1) - 757
3781 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3782 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3783 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3784 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3785 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3786 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1) - 762
3787 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3788 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3789 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3790 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3791 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3792 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3793 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10) - 768
3794 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3795 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3796 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3797 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3798 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3799 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10) - 773
3800 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3801 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3802 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3803 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3804 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3805 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3806 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2) - 779
3807 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3808 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3809 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3810 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3811 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3812 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2) - 784
3813 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3814 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3815 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3816 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3817 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3818 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3819 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11) - 790
3820 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3821 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3822 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3823 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3824 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3825 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11) - 795
3826 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3827 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3828 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3829 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3830 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3831 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3832 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3) - 801
3833 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3834 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3835 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3836 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3837 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3838 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3) - 806
3839 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3840 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3841 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3842 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3843 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3844 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3845 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12) - 812
3846 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3847 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3848 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3849 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3850 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3851 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12) - 817
3852 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3853 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3854 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3855 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3856 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3857 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3858 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4) - 823
3859 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3860 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3861 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3862 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3863 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3864 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4) - 828
3865 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3866 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3867 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3868 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3869 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3870 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3871 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13) - 834
3872 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3873 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3874 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3875 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3876 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3877 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13) - 839
3878 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3879 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3880 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3881 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3882 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3883 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3884 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5) - 845
3885 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3886 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3887 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3888 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3889 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3890 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5) - 850
3891 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3892 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3893 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3894 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3895 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3896 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3897 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14) - 856
3898 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3899 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3900 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3901 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3902 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3903 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14) - 861
3904 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3905 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3906 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3907 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3908 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3909 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3910 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6) - 867
3911 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3912 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3913 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3914 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3915 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3916 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6) - 872
3917 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3918 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3919 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3920 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3921 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3922 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3923 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15) - 878
3924 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3925 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3926 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3927 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3928 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3929 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15) - 883
3930 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3931 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3932 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3933 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3934 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3935 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3936 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7) - 889
3937 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3938 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3939 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3940 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3941 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3942 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7) - 894
3943 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3944 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3945 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3946 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3947 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3948 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3949 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8) - 900
3950 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3951 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3952 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3953 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3954 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3955 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8) - 905
3956 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3957 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3958 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3959 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3960 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3961 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3962 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0) - 911
3963 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3964 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3965 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3966 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3967 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3968 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0) - 916
3969 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3970 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3971 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3972 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3973 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3974 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3975 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9) - 922
3976 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3977 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3978 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3979 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3980 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3981 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9) - 927
3982 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3983 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3984 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3985 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3986 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3987 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3988 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1) - 933
3989 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3990 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3991 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3992 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3993 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3994 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1) - 938
3995 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3996 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3997 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3998 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3999 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4000 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4001 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10) - 944
4002 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4003 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4004 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4005 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4006 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4007 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10) - 949
4008 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4009 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4010 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4011 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4012 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4013 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4014 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2) - 955
4015 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4016 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4017 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4018 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4019 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4020 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2) - 960
4021 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4022 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4023 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4024 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4025 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4026 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4027 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11) - 966
4028 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4029 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4030 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4031 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4032 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4033 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11) - 971
4034 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4035 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4036 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4037 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4038 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4039 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4040 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3) - 977
4041 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4042 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4043 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4044 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4045 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4046 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3) - 982
4047 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4048 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4049 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4050 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4051 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4052 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4053 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12) - 988
4054 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4055 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4056 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4057 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4058 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4059 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12) - 993
4060 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4061 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4062 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4063 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4064 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4065 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4066 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4) - 999
4067 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4068 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4069 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4070 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4071 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4072 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4) - 1004
4073 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4074 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4075 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4076 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4077 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4078 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4079 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13) - 1010
4080 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4081 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4082 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4083 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4084 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4085 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13) - 1015
4086 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4087 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4088 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4089 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4090 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4091 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4092 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5) - 1021
4093 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4094 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4095 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4096 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4097 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4098 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5) - 1026
4099 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4100 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4101 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4102 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4103 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4104 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4105 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14) - 1032
4106 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4107 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4108 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4109 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4110 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4111 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14) - 1037
4112 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4113 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4114 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4115 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4116 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4117 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4118 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6) - 1043
4119 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4120 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4121 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4122 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4123 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4124 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6) - 1048
4125 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4126 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4127 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4128 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4129 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4130 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4131 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15) - 1054
4132 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4133 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4134 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4135 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4136 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4137 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15) - 1059
4138 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4139 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4140 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4141 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4142 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4143 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4144 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7) - 1065
4145 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4146 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4147 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4148 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4149 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4150 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7) - 1070
4151 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4152 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4153 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4154 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4155 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4156 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4157 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 2) - 1076
4158 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4159 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4160 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4161 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4162 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4163 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4164 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 3) - 1082
4165 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4166 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4167 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4168 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4169 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4170 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4171 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 6) - 1088
4172 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4173 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4174 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4175 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4176 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4177 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4178 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 7) - 1094
4179 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4180 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4181 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4182 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4183 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4184 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4185 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 2) - 1100
4186 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4187 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4188 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4189 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4190 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4191 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4192 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 3) - 1106
4193 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4194 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4195 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4196 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4197 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4198 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4199 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 6) - 1112
4200 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4201 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4202 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4203 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4204 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4205 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4206 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 7) - 1118
4207 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4208 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4209 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4210 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4211 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4212 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4213 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 2) - 1124
4214 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4215 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4216 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4217 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4218 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4219 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4220 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 3) - 1130
4221 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4222 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4223 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4224 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4225 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4226 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4227 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 6) - 1136
4228 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4229 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4230 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4231 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4232 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4233 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4234 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 7) - 1142
4235 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4236 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4237 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4238 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4239 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4240 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4241 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8) - 1148
4242 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4243 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4244 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4245 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4246 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4247 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8) - 1153
4248 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4249 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4250 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4251 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4252 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4253 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4254 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0) - 1159
4255 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4256 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4257 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4258 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4259 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4260 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0) - 1164
4261 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4262 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4263 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4264 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4265 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4266 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4267 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9) - 1170
4268 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4269 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4270 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4271 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4272 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4273 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9) - 1175
4274 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4275 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4276 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4277 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4278 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4279 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4280 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1) - 1181
4281 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4282 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4283 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4284 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4285 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4286 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1) - 1186
4287 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4288 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4289 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4290 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4291 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4292 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4293 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10) - 1192
4294 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4295 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4296 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4297 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4298 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4299 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10) - 1197
4300 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4301 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4302 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4303 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4304 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4305 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4306 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2) - 1203
4307 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4308 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4309 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4310 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4311 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4312 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2) - 1208
4313 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4314 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4315 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4316 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4317 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4318 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4319 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11) - 1214
4320 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4321 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4322 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4323 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4324 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4325 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11) - 1219
4326 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4327 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4328 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4329 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4330 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4331 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4332 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3) - 1225
4333 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4334 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4335 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4336 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4337 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4338 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3) - 1230
4339 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4340 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4341 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4342 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4343 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4344 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4345 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12) - 1236
4346 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4347 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4348 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4349 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4350 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4351 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12) - 1241
4352 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4353 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4354 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4355 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4356 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4357 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4358 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4) - 1247
4359 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4360 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4361 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4362 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4363 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4364 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4) - 1252
4365 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4366 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4367 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4368 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4369 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4370 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4371 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13) - 1258
4372 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4373 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4374 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4375 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4376 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4377 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13) - 1263
4378 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4379 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4380 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4381 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4382 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4383 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4384 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5) - 1269
4385 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4386 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4387 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4388 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4389 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4390 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5) - 1274
4391 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4392 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4393 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4394 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4395 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4396 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4397 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14) - 1280
4398 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4399 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4400 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4401 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4402 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4403 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14) - 1285
4404 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4405 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4406 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4407 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4408 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4409 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4410 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6) - 1291
4411 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4412 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4413 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4414 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4415 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4416 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6) - 1296
4417 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4418 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4419 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4420 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4421 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4422 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4423 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15) - 1302
4424 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4425 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4426 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4427 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4428 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4429 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15) - 1307
4430 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4431 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4432 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4433 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4434 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4435 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4436 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7) - 1313
4437 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4438 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4439 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4440 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4441 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4442 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7) - 1318
4443 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4444 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4445 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4446 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4447 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4448 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4449 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8) - 1324
4450 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4451 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4452 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4453 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4454 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4455 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8) - 1329
4456 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4457 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4458 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4459 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4460 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4461 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4462 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0) - 1335
4463 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4464 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4465 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4466 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4467 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4468 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0) - 1340
4469 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4470 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4471 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4472 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4473 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4474 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4475 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9) - 1346
4476 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4477 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4478 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4479 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4480 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4481 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9) - 1351
4482 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4483 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4484 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4485 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4486 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4487 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4488 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1) - 1357
4489 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4490 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4491 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4492 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4493 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4494 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1) - 1362
4495 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4496 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4497 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4498 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4499 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4500 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4501 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10) - 1368
4502 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4503 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4504 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4505 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4506 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4507 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10) - 1373
4508 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4509 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4510 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4511 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4512 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4513 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4514 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2) - 1379
4515 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4516 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4517 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4518 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4519 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4520 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2) - 1384
4521 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4522 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4523 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4524 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4525 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4526 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4527 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11) - 1390
4528 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4529 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4530 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4531 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4532 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4533 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11) - 1395
4534 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4535 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4536 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4537 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4538 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4539 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4540 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3) - 1401
4541 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4542 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4543 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4544 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4545 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4546 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3) - 1406
4547 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4548 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4549 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4550 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4551 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4552 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4553 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12) - 1412
4554 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4555 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4556 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4557 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4558 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4559 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12) - 1417
4560 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4561 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4562 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4563 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4564 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4565 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4566 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4) - 1423
4567 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4568 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4569 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4570 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4571 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4572 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4) - 1428
4573 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4574 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4575 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4576 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4577 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4578 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4579 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13) - 1434
4580 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4581 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4582 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4583 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4584 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4585 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13) - 1439
4586 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4587 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4588 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4589 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4590 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4591 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4592 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5) - 1445
4593 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4594 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4595 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4596 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4597 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4598 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5) - 1450
4599 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4600 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4601 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4602 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4603 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4604 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4605 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14) - 1456
4606 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4607 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4608 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4609 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4610 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4611 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14) - 1461
4612 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4613 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4614 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4615 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4616 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4617 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4618 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6) - 1467
4619 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4620 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4621 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4622 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4623 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4624 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6) - 1472
4625 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4626 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4627 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4628 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4629 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4630 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4631 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15) - 1478
4632 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4633 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4634 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4635 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4636 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4637 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15) - 1483
4638 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4639 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4640 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4641 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4642 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4643 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4644 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7) - 1489
4645 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4646 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4647 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4648 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4649 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4650 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7) - 1494
4651 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4652 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4653 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4654 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4655 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4656 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4657 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1500
4658 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4659 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4660 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4661 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4662 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4663 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1505
4664 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4665 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4666 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4667 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4668 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4669 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4670 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1511
4671 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4672 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4673 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4674 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4675 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4676 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1516
4677 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4678 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4679 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4680 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4681 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4682 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4683 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1522
4684 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4685 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4686 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4687 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4688 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4689 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1527
4690 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4691 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4692 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4693 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4694 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4695 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4696 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1533
4697 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4698 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4699 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4700 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4701 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4702 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1538
4703 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4704 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4705 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4706 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4707 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4708 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4709 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1544
4710 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4711 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4712 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4713 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4714 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4715 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1549
4716 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4717 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4718 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4719 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4720 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4721 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4722 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1555
4723 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4724 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4725 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4726 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4727 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4728 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1560
4729 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4730 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4731 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4732 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4733 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4734 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4735 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1566
4736 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4737 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4738 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4739 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4740 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4741 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1571
4742 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4743 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4744 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4745 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4746 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4747 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4748 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1577
4749 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4750 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4751 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4752 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4753 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4754 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1582
4755 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4756 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4757 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4758 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4759 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4760 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4761 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1588
4762 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4763 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4764 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4765 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4766 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4767 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1593
4768 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4769 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4770 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4771 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4772 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4773 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4774 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1599
4775 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4776 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4777 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4778 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4779 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4780 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1604
4781 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4782 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4783 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4784 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4785 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4786 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4787 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1610
4788 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4789 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4790 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4791 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4792 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4793 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1615
4794 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4795 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4796 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4797 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4798 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4799 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4800 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1621
4801 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4802 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4803 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4804 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4805 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4806 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1626
4807 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4808 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4809 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4810 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4811 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4812 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4813 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1632
4814 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4815 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4816 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4817 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4818 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4819 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1637
4820 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4821 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4822 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4823 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4824 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4825 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4826 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1643
4827 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4828 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4829 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4830 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4831 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4832 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1648
4833 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4834 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4835 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4836 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4837 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4838 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4839 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1654
4840 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4841 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4842 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4843 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4844 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4845 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1659
4846 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4847 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4848 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4849 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4850 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4851 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4852 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1665
4853 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4854 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4855 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4856 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4857 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4858 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1670
4859 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4860 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4861 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4862 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4863 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4864 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4865 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 2) - 1676
4866 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4867 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4868 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4869 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4870 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4871 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4872 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 3) - 1682
4873 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4874 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4875 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4876 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4877 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4878 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4879 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 6) - 1688
4880 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4881 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4882 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4883 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4884 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4885 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4886 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 7) - 1694
4887 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4888 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4889 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4890 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4891 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4892 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4893 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 2) - 1700
4894 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4895 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4896 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4897 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4898 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4899 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4900 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 3) - 1706
4901 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4902 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4903 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4904 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4905 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4906 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4907 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 6) - 1712
4908 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4909 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4910 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4911 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4912 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4913 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4914 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 7) - 1718
4915 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4916 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4917 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4918 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4919 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4920 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4921 // (ORCCrr G0, IntRegs:$rs2, G0) - 1724
4922 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4923 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4924 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4925 // (ORri IntRegs:$rd, G0, simm13Op:$simm13) - 1727
4926 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4927 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4928 // (ORrr IntRegs:$rd, G0, IntRegs:$rs2) - 1729
4929 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4930 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4931 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4932 // (RESTORErr G0, G0, G0) - 1732
4933 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4934 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4935 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4936 // (RET 8) - 1735
4937 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4938 // (RETL 8) - 1736
4939 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4940 // (SAVErr G0, G0, G0) - 1737
4941 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4942 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4943 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4944 // (SUBCCri G0, IntRegs:$rs1, simm13Op:$imm) - 1740
4945 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4946 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4947 // (SUBCCrr G0, IntRegs:$rs1, IntRegs:$rs2) - 1742
4948 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4949 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4950 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4951 // (TICCri G0, i32imm:$imm, 8) - 1745
4952 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4953 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4954 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4955 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4956 // (TICCri G0, i32imm:$imm, 8) - 1749
4957 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4958 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4959 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4960 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4961 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4962 // (TICCri IntRegs:$rs1, i32imm:$imm, 8) - 1754
4963 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4964 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4965 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4966 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4967 // (TICCri IntRegs:$rs1, i32imm:$imm, 8) - 1758
4968 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4969 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4970 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4971 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4972 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4973 // (TICCri G0, i32imm:$imm, 0) - 1763
4974 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4975 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4976 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4977 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4978 // (TICCri G0, i32imm:$imm, 0) - 1767
4979 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4980 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4981 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4982 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4983 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4984 // (TICCri IntRegs:$rs1, i32imm:$imm, 0) - 1772
4985 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4986 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4987 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4988 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4989 // (TICCri IntRegs:$rs1, i32imm:$imm, 0) - 1776
4990 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4991 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4992 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4993 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4994 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4995 // (TICCri G0, i32imm:$imm, 9) - 1781
4996 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4997 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4998 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4999 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5000 // (TICCri G0, i32imm:$imm, 9) - 1785
5001 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5002 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5003 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5004 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5005 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5006 // (TICCri IntRegs:$rs1, i32imm:$imm, 9) - 1790
5007 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5008 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5009 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5010 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5011 // (TICCri IntRegs:$rs1, i32imm:$imm, 9) - 1794
5012 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5013 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5014 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5015 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5016 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5017 // (TICCri G0, i32imm:$imm, 1) - 1799
5018 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5019 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5020 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5021 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5022 // (TICCri G0, i32imm:$imm, 1) - 1803
5023 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5024 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5025 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5026 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5027 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5028 // (TICCri IntRegs:$rs1, i32imm:$imm, 1) - 1808
5029 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5030 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5031 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5032 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5033 // (TICCri IntRegs:$rs1, i32imm:$imm, 1) - 1812
5034 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5035 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5036 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5037 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5038 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5039 // (TICCri G0, i32imm:$imm, 10) - 1817
5040 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5041 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5042 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5043 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5044 // (TICCri G0, i32imm:$imm, 10) - 1821
5045 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5046 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5047 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5048 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5049 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5050 // (TICCri IntRegs:$rs1, i32imm:$imm, 10) - 1826
5051 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5052 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5053 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5054 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5055 // (TICCri IntRegs:$rs1, i32imm:$imm, 10) - 1830
5056 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5057 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5058 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5059 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5060 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5061 // (TICCri G0, i32imm:$imm, 2) - 1835
5062 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5063 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5064 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5065 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5066 // (TICCri G0, i32imm:$imm, 2) - 1839
5067 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5068 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5069 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5070 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5071 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5072 // (TICCri IntRegs:$rs1, i32imm:$imm, 2) - 1844
5073 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5074 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5075 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5076 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5077 // (TICCri IntRegs:$rs1, i32imm:$imm, 2) - 1848
5078 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5079 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5080 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5081 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5082 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5083 // (TICCri G0, i32imm:$imm, 11) - 1853
5084 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5085 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5086 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5087 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5088 // (TICCri G0, i32imm:$imm, 11) - 1857
5089 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5090 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5091 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5092 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5093 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5094 // (TICCri IntRegs:$rs1, i32imm:$imm, 11) - 1862
5095 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5096 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5097 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5098 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5099 // (TICCri IntRegs:$rs1, i32imm:$imm, 11) - 1866
5100 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5101 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5102 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5103 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5104 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5105 // (TICCri G0, i32imm:$imm, 3) - 1871
5106 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5107 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5108 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5109 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5110 // (TICCri G0, i32imm:$imm, 3) - 1875
5111 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5112 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5113 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5114 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5115 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5116 // (TICCri IntRegs:$rs1, i32imm:$imm, 3) - 1880
5117 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5118 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5119 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5120 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5121 // (TICCri IntRegs:$rs1, i32imm:$imm, 3) - 1884
5122 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5123 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5124 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5125 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5126 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5127 // (TICCri G0, i32imm:$imm, 12) - 1889
5128 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5129 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5130 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5131 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5132 // (TICCri G0, i32imm:$imm, 12) - 1893
5133 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5134 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5135 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5136 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5137 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5138 // (TICCri IntRegs:$rs1, i32imm:$imm, 12) - 1898
5139 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5140 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5141 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5142 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5143 // (TICCri IntRegs:$rs1, i32imm:$imm, 12) - 1902
5144 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5145 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5146 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5147 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5148 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5149 // (TICCri G0, i32imm:$imm, 4) - 1907
5150 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5151 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5152 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5153 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5154 // (TICCri G0, i32imm:$imm, 4) - 1911
5155 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5156 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5157 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5158 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5159 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5160 // (TICCri IntRegs:$rs1, i32imm:$imm, 4) - 1916
5161 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5162 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5163 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5164 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5165 // (TICCri IntRegs:$rs1, i32imm:$imm, 4) - 1920
5166 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5167 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5168 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5169 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5170 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5171 // (TICCri G0, i32imm:$imm, 13) - 1925
5172 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5173 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5174 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5175 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5176 // (TICCri G0, i32imm:$imm, 13) - 1929
5177 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5178 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5179 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5180 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5181 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5182 // (TICCri IntRegs:$rs1, i32imm:$imm, 13) - 1934
5183 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5184 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5185 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5186 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5187 // (TICCri IntRegs:$rs1, i32imm:$imm, 13) - 1938
5188 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5189 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5190 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5191 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5192 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5193 // (TICCri G0, i32imm:$imm, 5) - 1943
5194 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5195 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5196 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5197 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5198 // (TICCri G0, i32imm:$imm, 5) - 1947
5199 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5200 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5201 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5202 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5203 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5204 // (TICCri IntRegs:$rs1, i32imm:$imm, 5) - 1952
5205 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5206 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5207 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5208 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5209 // (TICCri IntRegs:$rs1, i32imm:$imm, 5) - 1956
5210 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5211 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5212 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5213 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5214 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5215 // (TICCri G0, i32imm:$imm, 14) - 1961
5216 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5217 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5218 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5219 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5220 // (TICCri G0, i32imm:$imm, 14) - 1965
5221 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5222 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5223 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5224 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5225 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5226 // (TICCri IntRegs:$rs1, i32imm:$imm, 14) - 1970
5227 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5228 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5229 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5230 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5231 // (TICCri IntRegs:$rs1, i32imm:$imm, 14) - 1974
5232 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5233 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5234 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5235 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5236 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5237 // (TICCri G0, i32imm:$imm, 6) - 1979
5238 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5239 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5240 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5241 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5242 // (TICCri G0, i32imm:$imm, 6) - 1983
5243 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5244 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5245 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5246 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5247 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5248 // (TICCri IntRegs:$rs1, i32imm:$imm, 6) - 1988
5249 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5250 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5251 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5252 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5253 // (TICCri IntRegs:$rs1, i32imm:$imm, 6) - 1992
5254 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5255 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5256 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5257 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5258 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5259 // (TICCri G0, i32imm:$imm, 15) - 1997
5260 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5261 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5262 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5263 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5264 // (TICCri G0, i32imm:$imm, 15) - 2001
5265 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5266 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5267 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5268 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5269 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5270 // (TICCri IntRegs:$rs1, i32imm:$imm, 15) - 2006
5271 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5272 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5273 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5274 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5275 // (TICCri IntRegs:$rs1, i32imm:$imm, 15) - 2010
5276 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5277 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5278 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5279 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5280 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5281 // (TICCri G0, i32imm:$imm, 7) - 2015
5282 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5283 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5284 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5285 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5286 // (TICCri G0, i32imm:$imm, 7) - 2019
5287 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5288 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5289 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5290 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5291 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5292 // (TICCri IntRegs:$rs1, i32imm:$imm, 7) - 2024
5293 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5294 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5295 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5296 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5297 // (TICCri IntRegs:$rs1, i32imm:$imm, 7) - 2028
5298 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5299 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5300 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5301 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5302 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5303 // (TICCrr G0, IntRegs:$rs2, 8) - 2033
5304 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5305 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5306 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5307 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5308 // (TICCrr G0, IntRegs:$rs2, 8) - 2037
5309 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5310 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5311 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5312 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5313 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5314 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2042
5315 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5316 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5317 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5318 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5319 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2046
5320 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5321 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5322 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5323 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5324 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5325 // (TICCrr G0, IntRegs:$rs2, 0) - 2051
5326 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5327 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5328 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5329 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5330 // (TICCrr G0, IntRegs:$rs2, 0) - 2055
5331 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5332 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5333 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5334 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5335 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5336 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2060
5337 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5338 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5339 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5340 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5341 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2064
5342 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5343 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5344 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5345 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5346 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5347 // (TICCrr G0, IntRegs:$rs2, 9) - 2069
5348 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5349 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5350 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5351 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5352 // (TICCrr G0, IntRegs:$rs2, 9) - 2073
5353 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5354 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5355 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5356 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5357 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5358 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2078
5359 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5360 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5361 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5362 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5363 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2082
5364 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5365 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5366 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5367 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5368 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5369 // (TICCrr G0, IntRegs:$rs2, 1) - 2087
5370 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5371 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5372 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5373 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5374 // (TICCrr G0, IntRegs:$rs2, 1) - 2091
5375 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5376 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5377 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5378 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5379 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5380 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2096
5381 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5382 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5383 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5384 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5385 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2100
5386 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5387 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5388 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5389 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5390 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5391 // (TICCrr G0, IntRegs:$rs2, 10) - 2105
5392 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5393 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5394 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5395 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5396 // (TICCrr G0, IntRegs:$rs2, 10) - 2109
5397 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5398 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5399 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5400 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5401 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5402 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2114
5403 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5404 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5405 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5406 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5407 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2118
5408 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5409 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5410 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5411 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5412 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5413 // (TICCrr G0, IntRegs:$rs2, 2) - 2123
5414 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5415 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5416 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5417 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5418 // (TICCrr G0, IntRegs:$rs2, 2) - 2127
5419 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5420 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5421 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5422 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5423 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5424 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2132
5425 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5426 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5427 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5428 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5429 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2136
5430 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5431 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5432 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5433 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5434 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5435 // (TICCrr G0, IntRegs:$rs2, 11) - 2141
5436 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5437 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5438 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5439 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5440 // (TICCrr G0, IntRegs:$rs2, 11) - 2145
5441 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5442 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5443 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5444 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5445 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5446 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2150
5447 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5448 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5449 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5450 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5451 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2154
5452 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5453 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5454 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5455 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5456 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5457 // (TICCrr G0, IntRegs:$rs2, 3) - 2159
5458 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5459 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5460 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5461 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5462 // (TICCrr G0, IntRegs:$rs2, 3) - 2163
5463 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5464 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5465 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5466 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5467 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5468 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2168
5469 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5470 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5471 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5472 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5473 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2172
5474 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5475 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5476 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5477 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5478 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5479 // (TICCrr G0, IntRegs:$rs2, 12) - 2177
5480 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5481 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5482 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5483 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5484 // (TICCrr G0, IntRegs:$rs2, 12) - 2181
5485 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5486 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5487 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5488 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5489 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5490 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2186
5491 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5492 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5493 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5494 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5495 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2190
5496 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5497 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5498 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5499 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5500 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5501 // (TICCrr G0, IntRegs:$rs2, 4) - 2195
5502 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5503 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5504 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5505 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5506 // (TICCrr G0, IntRegs:$rs2, 4) - 2199
5507 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5508 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5509 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5510 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5511 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5512 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2204
5513 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5514 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5515 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5516 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5517 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2208
5518 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5519 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5520 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5521 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5522 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5523 // (TICCrr G0, IntRegs:$rs2, 13) - 2213
5524 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5525 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5526 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5527 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5528 // (TICCrr G0, IntRegs:$rs2, 13) - 2217
5529 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5530 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5531 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5532 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5533 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5534 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2222
5535 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5536 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5537 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5538 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5539 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2226
5540 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5541 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5542 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5543 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5544 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5545 // (TICCrr G0, IntRegs:$rs2, 5) - 2231
5546 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5547 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5548 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5549 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5550 // (TICCrr G0, IntRegs:$rs2, 5) - 2235
5551 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5552 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5553 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5554 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5555 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5556 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 2240
5557 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5558 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5559 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5560 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5561 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 2244
5562 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5563 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5564 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5565 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5566 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5567 // (TICCrr G0, IntRegs:$rs2, 14) - 2249
5568 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5569 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5570 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5571 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5572 // (TICCrr G0, IntRegs:$rs2, 14) - 2253
5573 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5574 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5575 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5576 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5577 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5578 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 2258
5579 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5580 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5581 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5582 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5583 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 2262
5584 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5585 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5586 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5587 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5588 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5589 // (TICCrr G0, IntRegs:$rs2, 6) - 2267
5590 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5591 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5592 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5593 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5594 // (TICCrr G0, IntRegs:$rs2, 6) - 2271
5595 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5596 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5597 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5598 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5599 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5600 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 2276
5601 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5602 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5603 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5604 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5605 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 2280
5606 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5607 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5608 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5609 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5610 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5611 // (TICCrr G0, IntRegs:$rs2, 15) - 2285
5612 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5613 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5614 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5615 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5616 // (TICCrr G0, IntRegs:$rs2, 15) - 2289
5617 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5618 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5619 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5620 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5621 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5622 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 2294
5623 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5624 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5625 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5626 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5627 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 2298
5628 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5629 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5630 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5631 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5632 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5633 // (TICCrr G0, IntRegs:$rs2, 7) - 2303
5634 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5635 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5636 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5637 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5638 // (TICCrr G0, IntRegs:$rs2, 7) - 2307
5639 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5640 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5641 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5642 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5643 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5644 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 2312
5645 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5646 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5647 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5648 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5649 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 2316
5650 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5651 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5652 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5653 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5654 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5655 // (TRAPri G0, i32imm:$imm, 8) - 2321
5656 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5657 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5658 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5659 // (TRAPri IntRegs:$rs1, i32imm:$imm, 8) - 2324
5660 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5661 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5662 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5663 // (TRAPri G0, i32imm:$imm, 0) - 2327
5664 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5665 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5666 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5667 // (TRAPri IntRegs:$rs1, i32imm:$imm, 0) - 2330
5668 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5669 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5670 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5671 // (TRAPri G0, i32imm:$imm, 9) - 2333
5672 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5673 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5674 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5675 // (TRAPri IntRegs:$rs1, i32imm:$imm, 9) - 2336
5676 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5677 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5678 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5679 // (TRAPri G0, i32imm:$imm, 1) - 2339
5680 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5681 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5682 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5683 // (TRAPri IntRegs:$rs1, i32imm:$imm, 1) - 2342
5684 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5685 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5686 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5687 // (TRAPri G0, i32imm:$imm, 10) - 2345
5688 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5689 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5690 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5691 // (TRAPri IntRegs:$rs1, i32imm:$imm, 10) - 2348
5692 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5693 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5694 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5695 // (TRAPri G0, i32imm:$imm, 2) - 2351
5696 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5697 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5698 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5699 // (TRAPri IntRegs:$rs1, i32imm:$imm, 2) - 2354
5700 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5701 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5702 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5703 // (TRAPri G0, i32imm:$imm, 11) - 2357
5704 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5705 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5706 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5707 // (TRAPri IntRegs:$rs1, i32imm:$imm, 11) - 2360
5708 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5709 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5710 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5711 // (TRAPri G0, i32imm:$imm, 3) - 2363
5712 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5713 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5714 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5715 // (TRAPri IntRegs:$rs1, i32imm:$imm, 3) - 2366
5716 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5717 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5718 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5719 // (TRAPri G0, i32imm:$imm, 12) - 2369
5720 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5721 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5722 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5723 // (TRAPri IntRegs:$rs1, i32imm:$imm, 12) - 2372
5724 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5725 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5726 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5727 // (TRAPri G0, i32imm:$imm, 4) - 2375
5728 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5729 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5730 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5731 // (TRAPri IntRegs:$rs1, i32imm:$imm, 4) - 2378
5732 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5733 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5734 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5735 // (TRAPri G0, i32imm:$imm, 13) - 2381
5736 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5737 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5738 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5739 // (TRAPri IntRegs:$rs1, i32imm:$imm, 13) - 2384
5740 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5741 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5742 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5743 // (TRAPri G0, i32imm:$imm, 5) - 2387
5744 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5745 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5746 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5747 // (TRAPri IntRegs:$rs1, i32imm:$imm, 5) - 2390
5748 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5749 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5750 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5751 // (TRAPri G0, i32imm:$imm, 14) - 2393
5752 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5753 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5754 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5755 // (TRAPri IntRegs:$rs1, i32imm:$imm, 14) - 2396
5756 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5757 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5758 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5759 // (TRAPri G0, i32imm:$imm, 6) - 2399
5760 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5761 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5762 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5763 // (TRAPri IntRegs:$rs1, i32imm:$imm, 6) - 2402
5764 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5765 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5766 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5767 // (TRAPri G0, i32imm:$imm, 15) - 2405
5768 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5769 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5770 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5771 // (TRAPri IntRegs:$rs1, i32imm:$imm, 15) - 2408
5772 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5773 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5774 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5775 // (TRAPri G0, i32imm:$imm, 7) - 2411
5776 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5777 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5778 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5779 // (TRAPri IntRegs:$rs1, i32imm:$imm, 7) - 2414
5780 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5781 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5782 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5783 // (TRAPrr G0, IntRegs:$rs1, 8) - 2417
5784 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5785 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5786 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5787 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2420
5788 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5789 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5790 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5791 // (TRAPrr G0, IntRegs:$rs1, 0) - 2423
5792 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5793 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5794 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5795 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2426
5796 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5797 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5798 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5799 // (TRAPrr G0, IntRegs:$rs1, 9) - 2429
5800 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5801 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5802 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5803 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2432
5804 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5805 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5806 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5807 // (TRAPrr G0, IntRegs:$rs1, 1) - 2435
5808 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5809 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5810 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5811 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2438
5812 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5813 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5814 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5815 // (TRAPrr G0, IntRegs:$rs1, 10) - 2441
5816 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5817 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5818 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5819 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2444
5820 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5821 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5822 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5823 // (TRAPrr G0, IntRegs:$rs1, 2) - 2447
5824 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5825 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5826 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5827 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2450
5828 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5829 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5830 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5831 // (TRAPrr G0, IntRegs:$rs1, 11) - 2453
5832 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5833 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5834 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5835 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2456
5836 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5837 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5838 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5839 // (TRAPrr G0, IntRegs:$rs1, 3) - 2459
5840 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5841 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5842 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5843 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2462
5844 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5845 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5846 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5847 // (TRAPrr G0, IntRegs:$rs1, 12) - 2465
5848 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5849 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5850 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5851 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2468
5852 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5853 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5854 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5855 // (TRAPrr G0, IntRegs:$rs1, 4) - 2471
5856 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5857 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5858 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5859 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2474
5860 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5861 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5862 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5863 // (TRAPrr G0, IntRegs:$rs1, 13) - 2477
5864 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5865 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5866 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5867 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2480
5868 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5869 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5870 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5871 // (TRAPrr G0, IntRegs:$rs1, 5) - 2483
5872 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5873 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5874 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5875 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 5) - 2486
5876 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5877 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5878 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5879 // (TRAPrr G0, IntRegs:$rs1, 14) - 2489
5880 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5881 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5882 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5883 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 14) - 2492
5884 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5885 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5886 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5887 // (TRAPrr G0, IntRegs:$rs1, 6) - 2495
5888 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5889 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5890 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5891 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 6) - 2498
5892 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5893 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5894 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5895 // (TRAPrr G0, IntRegs:$rs1, 15) - 2501
5896 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5897 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5898 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5899 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 15) - 2504
5900 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5901 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5902 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5903 // (TRAPrr G0, IntRegs:$rs1, 7) - 2507
5904 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5905 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5906 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5907 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 7) - 2510
5908 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5909 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5910 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5911 // (TXCCri G0, i32imm:$imm, 8) - 2513
5912 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5913 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5914 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5915 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5916 // (TXCCri G0, i32imm:$imm, 8) - 2517
5917 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5918 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5919 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5920 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5921 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5922 // (TXCCri IntRegs:$rs1, i32imm:$imm, 8) - 2522
5923 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5924 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5925 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5926 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5927 // (TXCCri IntRegs:$rs1, i32imm:$imm, 8) - 2526
5928 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5929 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5930 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5931 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5932 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5933 // (TXCCri G0, i32imm:$imm, 0) - 2531
5934 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5935 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5936 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5937 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5938 // (TXCCri G0, i32imm:$imm, 0) - 2535
5939 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5940 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5941 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5942 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5943 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5944 // (TXCCri IntRegs:$rs1, i32imm:$imm, 0) - 2540
5945 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5946 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5947 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5948 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5949 // (TXCCri IntRegs:$rs1, i32imm:$imm, 0) - 2544
5950 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5951 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5952 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5953 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5954 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5955 // (TXCCri G0, i32imm:$imm, 9) - 2549
5956 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5957 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5958 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5959 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5960 // (TXCCri G0, i32imm:$imm, 9) - 2553
5961 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5962 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5963 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5964 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5965 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5966 // (TXCCri IntRegs:$rs1, i32imm:$imm, 9) - 2558
5967 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5968 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5969 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5970 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5971 // (TXCCri IntRegs:$rs1, i32imm:$imm, 9) - 2562
5972 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5973 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5974 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5975 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5976 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5977 // (TXCCri G0, i32imm:$imm, 1) - 2567
5978 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5979 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5980 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5981 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5982 // (TXCCri G0, i32imm:$imm, 1) - 2571
5983 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5984 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5985 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5986 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5987 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5988 // (TXCCri IntRegs:$rs1, i32imm:$imm, 1) - 2576
5989 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5990 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5991 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5992 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5993 // (TXCCri IntRegs:$rs1, i32imm:$imm, 1) - 2580
5994 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5995 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5996 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5997 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5998 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5999 // (TXCCri G0, i32imm:$imm, 10) - 2585
6000 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6001 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6002 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6003 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6004 // (TXCCri G0, i32imm:$imm, 10) - 2589
6005 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6006 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6007 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6008 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6009 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6010 // (TXCCri IntRegs:$rs1, i32imm:$imm, 10) - 2594
6011 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6012 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6013 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6014 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6015 // (TXCCri IntRegs:$rs1, i32imm:$imm, 10) - 2598
6016 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6017 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6018 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6019 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6020 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6021 // (TXCCri G0, i32imm:$imm, 2) - 2603
6022 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6023 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6024 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6025 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6026 // (TXCCri G0, i32imm:$imm, 2) - 2607
6027 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6028 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6029 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6030 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6031 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6032 // (TXCCri IntRegs:$rs1, i32imm:$imm, 2) - 2612
6033 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6034 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6035 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6036 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6037 // (TXCCri IntRegs:$rs1, i32imm:$imm, 2) - 2616
6038 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6039 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6040 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6041 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6042 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6043 // (TXCCri G0, i32imm:$imm, 11) - 2621
6044 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6045 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6046 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6047 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6048 // (TXCCri G0, i32imm:$imm, 11) - 2625
6049 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6050 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6051 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6052 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6053 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6054 // (TXCCri IntRegs:$rs1, i32imm:$imm, 11) - 2630
6055 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6056 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6057 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6058 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6059 // (TXCCri IntRegs:$rs1, i32imm:$imm, 11) - 2634
6060 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6061 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6062 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6063 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6064 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6065 // (TXCCri G0, i32imm:$imm, 3) - 2639
6066 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6067 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6068 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6069 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6070 // (TXCCri G0, i32imm:$imm, 3) - 2643
6071 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6072 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6073 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6074 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6075 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6076 // (TXCCri IntRegs:$rs1, i32imm:$imm, 3) - 2648
6077 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6078 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6079 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6080 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6081 // (TXCCri IntRegs:$rs1, i32imm:$imm, 3) - 2652
6082 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6083 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6084 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6085 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6086 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6087 // (TXCCri G0, i32imm:$imm, 12) - 2657
6088 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6089 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6090 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6091 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6092 // (TXCCri G0, i32imm:$imm, 12) - 2661
6093 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6094 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6095 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6096 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6097 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6098 // (TXCCri IntRegs:$rs1, i32imm:$imm, 12) - 2666
6099 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6100 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6101 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6102 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6103 // (TXCCri IntRegs:$rs1, i32imm:$imm, 12) - 2670
6104 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6105 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6106 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6107 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6108 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6109 // (TXCCri G0, i32imm:$imm, 4) - 2675
6110 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6111 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6112 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6113 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6114 // (TXCCri G0, i32imm:$imm, 4) - 2679
6115 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6116 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6117 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6118 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6119 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6120 // (TXCCri IntRegs:$rs1, i32imm:$imm, 4) - 2684
6121 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6122 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6123 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6124 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6125 // (TXCCri IntRegs:$rs1, i32imm:$imm, 4) - 2688
6126 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6127 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6128 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6129 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6130 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6131 // (TXCCri G0, i32imm:$imm, 13) - 2693
6132 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6133 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6134 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6135 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6136 // (TXCCri G0, i32imm:$imm, 13) - 2697
6137 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6138 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6139 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6140 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6141 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6142 // (TXCCri IntRegs:$rs1, i32imm:$imm, 13) - 2702
6143 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6144 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6145 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6146 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6147 // (TXCCri IntRegs:$rs1, i32imm:$imm, 13) - 2706
6148 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6149 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6150 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6151 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6152 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6153 // (TXCCri G0, i32imm:$imm, 5) - 2711
6154 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6155 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6156 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6157 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6158 // (TXCCri G0, i32imm:$imm, 5) - 2715
6159 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6160 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6161 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6162 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6163 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6164 // (TXCCri IntRegs:$rs1, i32imm:$imm, 5) - 2720
6165 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6166 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6167 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6168 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6169 // (TXCCri IntRegs:$rs1, i32imm:$imm, 5) - 2724
6170 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6171 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6172 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6173 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6174 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6175 // (TXCCri G0, i32imm:$imm, 14) - 2729
6176 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6177 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6178 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6179 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6180 // (TXCCri G0, i32imm:$imm, 14) - 2733
6181 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6182 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6183 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6184 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6185 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6186 // (TXCCri IntRegs:$rs1, i32imm:$imm, 14) - 2738
6187 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6188 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6189 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6190 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6191 // (TXCCri IntRegs:$rs1, i32imm:$imm, 14) - 2742
6192 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6193 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6194 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6195 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6196 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6197 // (TXCCri G0, i32imm:$imm, 6) - 2747
6198 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6199 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6200 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6201 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6202 // (TXCCri G0, i32imm:$imm, 6) - 2751
6203 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6204 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6205 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6206 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6207 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6208 // (TXCCri IntRegs:$rs1, i32imm:$imm, 6) - 2756
6209 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6210 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6211 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6212 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6213 // (TXCCri IntRegs:$rs1, i32imm:$imm, 6) - 2760
6214 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6215 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6216 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6217 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6218 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6219 // (TXCCri G0, i32imm:$imm, 15) - 2765
6220 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6221 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6222 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6223 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6224 // (TXCCri G0, i32imm:$imm, 15) - 2769
6225 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6226 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6227 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6228 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6229 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6230 // (TXCCri IntRegs:$rs1, i32imm:$imm, 15) - 2774
6231 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6232 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6233 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6234 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6235 // (TXCCri IntRegs:$rs1, i32imm:$imm, 15) - 2778
6236 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6237 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6238 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6239 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6240 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6241 // (TXCCri G0, i32imm:$imm, 7) - 2783
6242 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6243 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6244 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6245 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6246 // (TXCCri G0, i32imm:$imm, 7) - 2787
6247 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6248 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6249 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6250 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6251 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6252 // (TXCCri IntRegs:$rs1, i32imm:$imm, 7) - 2792
6253 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6254 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6255 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6256 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6257 // (TXCCri IntRegs:$rs1, i32imm:$imm, 7) - 2796
6258 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6259 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6260 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6261 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6262 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6263 // (TXCCrr G0, IntRegs:$rs2, 8) - 2801
6264 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6265 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6266 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6267 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6268 // (TXCCrr G0, IntRegs:$rs2, 8) - 2805
6269 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6270 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6271 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6272 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6273 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6274 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2810
6275 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6276 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6277 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6278 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6279 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2814
6280 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6281 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6282 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6283 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6284 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6285 // (TXCCrr G0, IntRegs:$rs2, 0) - 2819
6286 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6287 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6288 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6289 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6290 // (TXCCrr G0, IntRegs:$rs2, 0) - 2823
6291 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6292 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6293 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6294 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6295 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6296 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2828
6297 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6298 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6299 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6300 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6301 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2832
6302 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6303 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6304 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6305 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6306 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6307 // (TXCCrr G0, IntRegs:$rs2, 9) - 2837
6308 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6309 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6310 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6311 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6312 // (TXCCrr G0, IntRegs:$rs2, 9) - 2841
6313 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6314 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6315 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6316 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6317 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6318 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2846
6319 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6320 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6321 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6322 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6323 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2850
6324 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6325 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6326 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6327 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6328 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6329 // (TXCCrr G0, IntRegs:$rs2, 1) - 2855
6330 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6331 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6332 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6333 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6334 // (TXCCrr G0, IntRegs:$rs2, 1) - 2859
6335 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6336 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6337 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6338 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6339 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6340 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2864
6341 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6342 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6343 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6344 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6345 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2868
6346 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6347 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6348 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6349 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6350 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6351 // (TXCCrr G0, IntRegs:$rs2, 10) - 2873
6352 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6353 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6354 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6355 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6356 // (TXCCrr G0, IntRegs:$rs2, 10) - 2877
6357 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6358 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6359 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6360 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6361 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6362 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2882
6363 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6364 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6365 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6366 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6367 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2886
6368 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6369 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6370 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6371 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6372 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6373 // (TXCCrr G0, IntRegs:$rs2, 2) - 2891
6374 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6375 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6376 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6377 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6378 // (TXCCrr G0, IntRegs:$rs2, 2) - 2895
6379 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6380 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6381 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6382 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6383 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6384 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2900
6385 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6386 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6387 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6388 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6389 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2904
6390 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6391 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6392 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6393 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6394 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6395 // (TXCCrr G0, IntRegs:$rs2, 11) - 2909
6396 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6397 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6398 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6399 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6400 // (TXCCrr G0, IntRegs:$rs2, 11) - 2913
6401 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6402 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6403 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6404 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6405 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6406 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2918
6407 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6408 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6409 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6410 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6411 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2922
6412 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6413 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6414 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6415 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6416 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6417 // (TXCCrr G0, IntRegs:$rs2, 3) - 2927
6418 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6419 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6420 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6421 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6422 // (TXCCrr G0, IntRegs:$rs2, 3) - 2931
6423 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6424 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6425 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6426 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6427 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6428 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2936
6429 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6430 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6431 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6432 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6433 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2940
6434 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6435 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6436 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6437 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6438 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6439 // (TXCCrr G0, IntRegs:$rs2, 12) - 2945
6440 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6441 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6442 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6443 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6444 // (TXCCrr G0, IntRegs:$rs2, 12) - 2949
6445 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6446 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6447 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6448 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6449 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6450 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2954
6451 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6452 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6453 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6454 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6455 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2958
6456 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6457 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6458 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6459 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6460 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6461 // (TXCCrr G0, IntRegs:$rs2, 4) - 2963
6462 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6463 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6464 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6465 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6466 // (TXCCrr G0, IntRegs:$rs2, 4) - 2967
6467 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6468 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6469 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6470 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6471 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6472 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2972
6473 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6474 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6475 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6476 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6477 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2976
6478 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6479 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6480 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6481 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6482 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6483 // (TXCCrr G0, IntRegs:$rs2, 13) - 2981
6484 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6485 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6486 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6487 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6488 // (TXCCrr G0, IntRegs:$rs2, 13) - 2985
6489 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6490 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6491 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6492 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6493 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6494 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2990
6495 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6496 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6497 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6498 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6499 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2994
6500 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6501 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6502 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6503 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6504 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6505 // (TXCCrr G0, IntRegs:$rs2, 5) - 2999
6506 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6507 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6508 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6509 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6510 // (TXCCrr G0, IntRegs:$rs2, 5) - 3003
6511 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6512 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6513 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6514 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6515 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6516 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 3008
6517 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6518 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6519 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6520 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6521 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 3012
6522 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6523 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6524 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6525 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6526 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6527 // (TXCCrr G0, IntRegs:$rs2, 14) - 3017
6528 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6529 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6530 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6531 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6532 // (TXCCrr G0, IntRegs:$rs2, 14) - 3021
6533 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6534 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6535 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6536 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6537 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6538 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 3026
6539 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6540 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6541 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6542 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6543 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 3030
6544 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6545 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6546 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6547 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6548 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6549 // (TXCCrr G0, IntRegs:$rs2, 6) - 3035
6550 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6551 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6552 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6553 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6554 // (TXCCrr G0, IntRegs:$rs2, 6) - 3039
6555 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6556 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6557 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6558 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6559 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6560 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 3044
6561 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6562 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6563 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6564 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6565 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 3048
6566 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6567 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6568 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6569 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6570 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6571 // (TXCCrr G0, IntRegs:$rs2, 15) - 3053
6572 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6573 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6574 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6575 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6576 // (TXCCrr G0, IntRegs:$rs2, 15) - 3057
6577 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6578 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6579 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6580 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6581 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6582 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 3062
6583 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6584 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6585 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6586 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6587 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 3066
6588 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6589 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6590 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6591 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6592 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6593 // (TXCCrr G0, IntRegs:$rs2, 7) - 3071
6594 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6595 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6596 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6597 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6598 // (TXCCrr G0, IntRegs:$rs2, 7) - 3075
6599 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6600 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6601 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6602 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6603 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6604 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 3080
6605 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6606 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6607 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6608 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6609 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 3084
6610 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6611 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6612 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6613 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6614 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6615 // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 3089
6616 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6617 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6618 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6619 // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 3092
6620 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6621 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6622 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6623 // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 3095
6624 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6625 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6626 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6627 // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2) - 3098
6628 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6629 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6630 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6631 // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 3101
6632 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6633 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6634 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6635 // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2) - 3104
6636 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6637 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6638 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6639 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8) - 3107
6640 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6641 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6642 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6643 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6644 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6645 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6646 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0) - 3113
6647 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6648 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6649 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6650 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6651 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6652 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6653 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7) - 3119
6654 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6655 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6656 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6657 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6658 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6659 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6660 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6) - 3125
6661 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6662 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6663 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6664 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6665 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6666 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6667 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5) - 3131
6668 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6669 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6670 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6671 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6672 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6673 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6674 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4) - 3137
6675 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6676 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6677 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6678 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6679 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6680 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6681 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3) - 3143
6682 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6683 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6684 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6685 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6686 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6687 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6688 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2) - 3149
6689 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6690 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6691 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6692 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6693 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6694 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6695 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1) - 3155
6696 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6697 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6698 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6699 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6700 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6701 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6702 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9) - 3161
6703 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6704 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6705 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6706 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6707 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6708 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6709 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10) - 3167
6710 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6711 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6712 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6713 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6714 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6715 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6716 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11) - 3173
6717 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6718 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6719 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6720 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6721 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6722 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6723 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12) - 3179
6724 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6725 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6726 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6727 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6728 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6729 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6730 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13) - 3185
6731 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6732 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6733 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6734 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6735 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6736 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6737 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14) - 3191
6738 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6739 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6740 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6741 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6742 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6743 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6744 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15) - 3197
6745 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6746 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6747 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6748 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6749 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6750 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6751 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8) - 3203
6752 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6753 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6754 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6755 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6756 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6757 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6758 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0) - 3209
6759 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6760 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6761 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6762 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6763 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6764 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6765 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7) - 3215
6766 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6767 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6768 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6769 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6770 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6771 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6772 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6) - 3221
6773 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6774 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6775 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6776 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6777 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6778 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6779 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5) - 3227
6780 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6781 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6782 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6783 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6784 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6785 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6786 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4) - 3233
6787 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6788 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6789 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6790 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6791 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6792 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6793 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3) - 3239
6794 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6795 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6796 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6797 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6798 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6799 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6800 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2) - 3245
6801 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6802 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6803 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6804 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6805 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6806 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6807 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1) - 3251
6808 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6809 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6810 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6811 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6812 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6813 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6814 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9) - 3257
6815 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6816 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6817 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6818 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6819 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6820 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6821 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10) - 3263
6822 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6823 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6824 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6825 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6826 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6827 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6828 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11) - 3269
6829 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6830 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6831 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6832 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6833 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6834 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6835 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12) - 3275
6836 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6837 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6838 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6839 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6840 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6841 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6842 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13) - 3281
6843 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6844 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6845 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6846 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6847 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6848 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6849 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14) - 3287
6850 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6851 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6852 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6853 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6854 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6855 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6856 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15) - 3293
6857 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6858 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6859 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6860 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6861 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6862 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6863 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8) - 3299
6864 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6865 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6866 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6867 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6868 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6869 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6870 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0) - 3305
6871 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6872 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6873 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6874 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6875 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6876 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6877 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7) - 3311
6878 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6879 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6880 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6881 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6882 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6883 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6884 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6) - 3317
6885 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6886 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6887 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6888 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6889 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6890 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6891 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5) - 3323
6892 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6893 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6894 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6895 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6896 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6897 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6898 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4) - 3329
6899 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6900 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6901 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6902 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6903 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6904 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6905 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3) - 3335
6906 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6907 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6908 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6909 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6910 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6911 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6912 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2) - 3341
6913 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6914 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6915 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6916 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6917 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6918 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6919 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1) - 3347
6920 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6921 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6922 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6923 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6924 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6925 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6926 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9) - 3353
6927 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6928 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6929 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6930 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6931 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6932 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6933 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10) - 3359
6934 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6935 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6936 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6937 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6938 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6939 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6940 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11) - 3365
6941 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6942 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6943 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6944 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6945 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6946 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6947 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12) - 3371
6948 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6949 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6950 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6951 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6952 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6953 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6954 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13) - 3377
6955 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6956 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6957 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6958 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6959 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6960 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6961 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14) - 3383
6962 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6963 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6964 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6965 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6966 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6967 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6968 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15) - 3389
6969 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6970 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6971 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6972 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6973 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6974 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6975 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8) - 3395
6976 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6977 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6978 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6979 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6980 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6981 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6982 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0) - 3401
6983 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6984 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6985 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6986 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6987 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6988 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6989 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7) - 3407
6990 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6991 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6992 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6993 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6994 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6995 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6996 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6) - 3413
6997 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6998 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6999 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7000 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7001 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
7002 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7003 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5) - 3419
7004 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7005 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7006 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7007 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7008 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
7009 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7010 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4) - 3425
7011 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7012 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7013 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7014 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7015 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
7016 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7017 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3) - 3431
7018 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7019 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7020 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7021 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7022 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
7023 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7024 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2) - 3437
7025 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7026 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7027 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7028 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7029 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
7030 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7031 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1) - 3443
7032 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7033 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7034 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7035 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7036 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
7037 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7038 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9) - 3449
7039 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7040 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7041 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7042 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7043 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
7044 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7045 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10) - 3455
7046 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7047 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7048 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7049 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7050 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
7051 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7052 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11) - 3461
7053 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7054 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7055 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7056 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7057 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
7058 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7059 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12) - 3467
7060 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7061 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7062 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7063 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7064 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
7065 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7066 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13) - 3473
7067 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7068 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7069 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7070 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7071 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
7072 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7073 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14) - 3479
7074 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7075 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7076 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7077 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7078 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
7079 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7080 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15) - 3485
7081 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7082 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7083 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7084 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7085 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
7086 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7087 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8) - 3491
7088 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7089 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7090 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7091 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7092 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
7093 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7094 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0) - 3497
7095 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7096 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7097 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7098 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7099 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
7100 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7101 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7) - 3503
7102 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7103 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7104 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7105 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7106 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
7107 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7108 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6) - 3509
7109 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7110 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7111 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7112 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7113 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
7114 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7115 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5) - 3515
7116 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7117 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7118 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7119 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7120 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
7121 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7122 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4) - 3521
7123 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7124 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7125 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7126 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7127 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
7128 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7129 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3) - 3527
7130 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7131 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7132 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7133 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7134 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
7135 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7136 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2) - 3533
7137 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7138 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7139 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7140 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7141 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
7142 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7143 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1) - 3539
7144 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7145 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7146 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7147 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7148 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
7149 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7150 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9) - 3545
7151 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7152 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7153 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7154 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7155 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
7156 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7157 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10) - 3551
7158 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7159 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7160 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7161 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7162 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
7163 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7164 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11) - 3557
7165 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7166 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7167 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7168 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7169 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
7170 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7171 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12) - 3563
7172 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7173 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7174 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7175 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7176 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
7177 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7178 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13) - 3569
7179 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7180 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7181 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7182 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7183 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
7184 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7185 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14) - 3575
7186 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7187 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7188 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7189 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7190 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
7191 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7192 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15) - 3581
7193 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7194 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7195 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7196 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7197 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
7198 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7199 // (WRASRri ASR27, G0, simm13Op:$simm13) - 3587
7200 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::ASR27},
7201 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
7202 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
7203 // (WRASRrr ASR27, G0, IntRegs:$rs2) - 3590
7204 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::ASR27},
7205 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
7206 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7207 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
7208 };
7209
7210 static const char AsmStrings[] =
7211 /* 0 */ "ba $\xFF\x01\x01\0"
7212 /* 8 */ "bn $\xFF\x01\x01\0"
7213 /* 16 */ "bne $\xFF\x01\x01\0"
7214 /* 25 */ "be $\xFF\x01\x01\0"
7215 /* 33 */ "bg $\xFF\x01\x01\0"
7216 /* 41 */ "ble $\xFF\x01\x01\0"
7217 /* 50 */ "bge $\xFF\x01\x01\0"
7218 /* 59 */ "bl $\xFF\x01\x01\0"
7219 /* 67 */ "bgu $\xFF\x01\x01\0"
7220 /* 76 */ "bleu $\xFF\x01\x01\0"
7221 /* 86 */ "bcc $\xFF\x01\x01\0"
7222 /* 95 */ "bcs $\xFF\x01\x01\0"
7223 /* 104 */ "bpos $\xFF\x01\x01\0"
7224 /* 114 */ "bneg $\xFF\x01\x01\0"
7225 /* 124 */ "bvc $\xFF\x01\x01\0"
7226 /* 133 */ "bvs $\xFF\x01\x01\0"
7227 /* 142 */ "ba,a $\xFF\x01\x01\0"
7228 /* 152 */ "bn,a $\xFF\x01\x01\0"
7229 /* 162 */ "bne,a $\xFF\x01\x01\0"
7230 /* 173 */ "be,a $\xFF\x01\x01\0"
7231 /* 183 */ "bg,a $\xFF\x01\x01\0"
7232 /* 193 */ "ble,a $\xFF\x01\x01\0"
7233 /* 204 */ "bge,a $\xFF\x01\x01\0"
7234 /* 215 */ "bl,a $\xFF\x01\x01\0"
7235 /* 225 */ "bgu,a $\xFF\x01\x01\0"
7236 /* 236 */ "bleu,a $\xFF\x01\x01\0"
7237 /* 248 */ "bcc,a $\xFF\x01\x01\0"
7238 /* 259 */ "bcs,a $\xFF\x01\x01\0"
7239 /* 270 */ "bpos,a $\xFF\x01\x01\0"
7240 /* 282 */ "bneg,a $\xFF\x01\x01\0"
7241 /* 294 */ "bvc,a $\xFF\x01\x01\0"
7242 /* 305 */ "bvs,a $\xFF\x01\x01\0"
7243 /* 316 */ "fba,a,pn $\x03, $\xFF\x01\x01\0"
7244 /* 334 */ "fbn,a,pn $\x03, $\xFF\x01\x01\0"
7245 /* 352 */ "fbu,a,pn $\x03, $\xFF\x01\x01\0"
7246 /* 370 */ "fbg,a,pn $\x03, $\xFF\x01\x01\0"
7247 /* 388 */ "fbug,a,pn $\x03, $\xFF\x01\x01\0"
7248 /* 407 */ "fbl,a,pn $\x03, $\xFF\x01\x01\0"
7249 /* 425 */ "fbul,a,pn $\x03, $\xFF\x01\x01\0"
7250 /* 444 */ "fblg,a,pn $\x03, $\xFF\x01\x01\0"
7251 /* 463 */ "fbne,a,pn $\x03, $\xFF\x01\x01\0"
7252 /* 482 */ "fbe,a,pn $\x03, $\xFF\x01\x01\0"
7253 /* 500 */ "fbue,a,pn $\x03, $\xFF\x01\x01\0"
7254 /* 519 */ "fbge,a,pn $\x03, $\xFF\x01\x01\0"
7255 /* 538 */ "fbuge,a,pn $\x03, $\xFF\x01\x01\0"
7256 /* 558 */ "fble,a,pn $\x03, $\xFF\x01\x01\0"
7257 /* 577 */ "fbule,a,pn $\x03, $\xFF\x01\x01\0"
7258 /* 597 */ "fbo,a,pn $\x03, $\xFF\x01\x01\0"
7259 /* 615 */ "fba,pn $\x03, $\xFF\x01\x01\0"
7260 /* 631 */ "fbn,pn $\x03, $\xFF\x01\x01\0"
7261 /* 647 */ "fbu,pn $\x03, $\xFF\x01\x01\0"
7262 /* 663 */ "fbg,pn $\x03, $\xFF\x01\x01\0"
7263 /* 679 */ "fbug,pn $\x03, $\xFF\x01\x01\0"
7264 /* 696 */ "fbl,pn $\x03, $\xFF\x01\x01\0"
7265 /* 712 */ "fbul,pn $\x03, $\xFF\x01\x01\0"
7266 /* 729 */ "fblg,pn $\x03, $\xFF\x01\x01\0"
7267 /* 746 */ "fbne,pn $\x03, $\xFF\x01\x01\0"
7268 /* 763 */ "fbe,pn $\x03, $\xFF\x01\x01\0"
7269 /* 779 */ "fbue,pn $\x03, $\xFF\x01\x01\0"
7270 /* 796 */ "fbge,pn $\x03, $\xFF\x01\x01\0"
7271 /* 813 */ "fbuge,pn $\x03, $\xFF\x01\x01\0"
7272 /* 831 */ "fble,pn $\x03, $\xFF\x01\x01\0"
7273 /* 848 */ "fbule,pn $\x03, $\xFF\x01\x01\0"
7274 /* 866 */ "fbo,pn $\x03, $\xFF\x01\x01\0"
7275 /* 882 */ "ba,a,pn %icc, $\xFF\x01\x01\0"
7276 /* 901 */ "ba,a,pn %ncc, $\xFF\x01\x01\0"
7277 /* 920 */ "bn,a,pn %icc, $\xFF\x01\x01\0"
7278 /* 939 */ "bn,a,pn %ncc, $\xFF\x01\x01\0"
7279 /* 958 */ "bne,a,pn %icc, $\xFF\x01\x01\0"
7280 /* 978 */ "bne,a,pn %ncc, $\xFF\x01\x01\0"
7281 /* 998 */ "be,a,pn %icc, $\xFF\x01\x01\0"
7282 /* 1017 */ "be,a,pn %ncc, $\xFF\x01\x01\0"
7283 /* 1036 */ "bg,a,pn %icc, $\xFF\x01\x01\0"
7284 /* 1055 */ "bg,a,pn %ncc, $\xFF\x01\x01\0"
7285 /* 1074 */ "ble,a,pn %icc, $\xFF\x01\x01\0"
7286 /* 1094 */ "ble,a,pn %ncc, $\xFF\x01\x01\0"
7287 /* 1114 */ "bge,a,pn %icc, $\xFF\x01\x01\0"
7288 /* 1134 */ "bge,a,pn %ncc, $\xFF\x01\x01\0"
7289 /* 1154 */ "bl,a,pn %icc, $\xFF\x01\x01\0"
7290 /* 1173 */ "bl,a,pn %ncc, $\xFF\x01\x01\0"
7291 /* 1192 */ "bgu,a,pn %icc, $\xFF\x01\x01\0"
7292 /* 1212 */ "bgu,a,pn %ncc, $\xFF\x01\x01\0"
7293 /* 1232 */ "bleu,a,pn %icc, $\xFF\x01\x01\0"
7294 /* 1253 */ "bleu,a,pn %ncc, $\xFF\x01\x01\0"
7295 /* 1274 */ "bcc,a,pn %icc, $\xFF\x01\x01\0"
7296 /* 1294 */ "bcc,a,pn %ncc, $\xFF\x01\x01\0"
7297 /* 1314 */ "bcs,a,pn %icc, $\xFF\x01\x01\0"
7298 /* 1334 */ "bcs,a,pn %ncc, $\xFF\x01\x01\0"
7299 /* 1354 */ "bpos,a,pn %icc, $\xFF\x01\x01\0"
7300 /* 1375 */ "bpos,a,pn %ncc, $\xFF\x01\x01\0"
7301 /* 1396 */ "bneg,a,pn %icc, $\xFF\x01\x01\0"
7302 /* 1417 */ "bneg,a,pn %ncc, $\xFF\x01\x01\0"
7303 /* 1438 */ "bvc,a,pn %icc, $\xFF\x01\x01\0"
7304 /* 1458 */ "bvc,a,pn %ncc, $\xFF\x01\x01\0"
7305 /* 1478 */ "bvs,a,pn %icc, $\xFF\x01\x01\0"
7306 /* 1498 */ "bvs,a,pn %ncc, $\xFF\x01\x01\0"
7307 /* 1518 */ "ba,pn %icc, $\xFF\x01\x01\0"
7308 /* 1535 */ "ba,pn %ncc, $\xFF\x01\x01\0"
7309 /* 1552 */ "bn,pn %icc, $\xFF\x01\x01\0"
7310 /* 1569 */ "bn,pn %ncc, $\xFF\x01\x01\0"
7311 /* 1586 */ "bne,pn %icc, $\xFF\x01\x01\0"
7312 /* 1604 */ "bne,pn %ncc, $\xFF\x01\x01\0"
7313 /* 1622 */ "be,pn %icc, $\xFF\x01\x01\0"
7314 /* 1639 */ "be,pn %ncc, $\xFF\x01\x01\0"
7315 /* 1656 */ "bg,pn %icc, $\xFF\x01\x01\0"
7316 /* 1673 */ "bg,pn %ncc, $\xFF\x01\x01\0"
7317 /* 1690 */ "ble,pn %icc, $\xFF\x01\x01\0"
7318 /* 1708 */ "ble,pn %ncc, $\xFF\x01\x01\0"
7319 /* 1726 */ "bge,pn %icc, $\xFF\x01\x01\0"
7320 /* 1744 */ "bge,pn %ncc, $\xFF\x01\x01\0"
7321 /* 1762 */ "bl,pn %icc, $\xFF\x01\x01\0"
7322 /* 1779 */ "bl,pn %ncc, $\xFF\x01\x01\0"
7323 /* 1796 */ "bgu,pn %icc, $\xFF\x01\x01\0"
7324 /* 1814 */ "bgu,pn %ncc, $\xFF\x01\x01\0"
7325 /* 1832 */ "bleu,pn %icc, $\xFF\x01\x01\0"
7326 /* 1851 */ "bleu,pn %ncc, $\xFF\x01\x01\0"
7327 /* 1870 */ "bcc,pn %icc, $\xFF\x01\x01\0"
7328 /* 1888 */ "bcc,pn %ncc, $\xFF\x01\x01\0"
7329 /* 1906 */ "bcs,pn %icc, $\xFF\x01\x01\0"
7330 /* 1924 */ "bcs,pn %ncc, $\xFF\x01\x01\0"
7331 /* 1942 */ "bpos,pn %icc, $\xFF\x01\x01\0"
7332 /* 1961 */ "bpos,pn %ncc, $\xFF\x01\x01\0"
7333 /* 1980 */ "bneg,pn %icc, $\xFF\x01\x01\0"
7334 /* 1999 */ "bneg,pn %ncc, $\xFF\x01\x01\0"
7335 /* 2018 */ "bvc,pn %icc, $\xFF\x01\x01\0"
7336 /* 2036 */ "bvc,pn %ncc, $\xFF\x01\x01\0"
7337 /* 2054 */ "bvs,pn %icc, $\xFF\x01\x01\0"
7338 /* 2072 */ "bvs,pn %ncc, $\xFF\x01\x01\0"
7339 /* 2090 */ "brlez,a,pn $\x03, $\xFF\x01\x01\0"
7340 /* 2110 */ "brlz,a,pn $\x03, $\xFF\x01\x01\0"
7341 /* 2129 */ "brgz,a,pn $\x03, $\xFF\x01\x01\0"
7342 /* 2148 */ "brgez,a,pn $\x03, $\xFF\x01\x01\0"
7343 /* 2168 */ "brlez,pn $\x03, $\xFF\x01\x01\0"
7344 /* 2186 */ "brlz,pn $\x03, $\xFF\x01\x01\0"
7345 /* 2203 */ "brgz,pn $\x03, $\xFF\x01\x01\0"
7346 /* 2220 */ "brgez,pn $\x03, $\xFF\x01\x01\0"
7347 /* 2238 */ "cas [$\x02], $\x03, $\x01\0"
7348 /* 2255 */ "casl [$\x02], $\x03, $\x01\0"
7349 /* 2273 */ "casx [$\x02], $\x03, $\x01\0"
7350 /* 2291 */ "casxl [$\x02], $\x03, $\x01\0"
7351 /* 2310 */ "cwbne $\x03, $\x04, $\xFF\x01\x01\0"
7352 /* 2329 */ "cwbe $\x03, $\x04, $\xFF\x01\x01\0"
7353 /* 2347 */ "cwbg $\x03, $\x04, $\xFF\x01\x01\0"
7354 /* 2365 */ "cwble $\x03, $\x04, $\xFF\x01\x01\0"
7355 /* 2384 */ "cwbge $\x03, $\x04, $\xFF\x01\x01\0"
7356 /* 2403 */ "cwbl $\x03, $\x04, $\xFF\x01\x01\0"
7357 /* 2421 */ "cwbgu $\x03, $\x04, $\xFF\x01\x01\0"
7358 /* 2440 */ "cwbleu $\x03, $\x04, $\xFF\x01\x01\0"
7359 /* 2460 */ "cwbcc $\x03, $\x04, $\xFF\x01\x01\0"
7360 /* 2479 */ "cwbcs $\x03, $\x04, $\xFF\x01\x01\0"
7361 /* 2498 */ "cwbpos $\x03, $\x04, $\xFF\x01\x01\0"
7362 /* 2518 */ "cwbneg $\x03, $\x04, $\xFF\x01\x01\0"
7363 /* 2538 */ "cwbvc $\x03, $\x04, $\xFF\x01\x01\0"
7364 /* 2557 */ "cwbvs $\x03, $\x04, $\xFF\x01\x01\0"
7365 /* 2576 */ "cxbne $\x03, $\x04, $\xFF\x01\x01\0"
7366 /* 2595 */ "cxbe $\x03, $\x04, $\xFF\x01\x01\0"
7367 /* 2613 */ "cxbg $\x03, $\x04, $\xFF\x01\x01\0"
7368 /* 2631 */ "cxble $\x03, $\x04, $\xFF\x01\x01\0"
7369 /* 2650 */ "cxbge $\x03, $\x04, $\xFF\x01\x01\0"
7370 /* 2669 */ "cxbl $\x03, $\x04, $\xFF\x01\x01\0"
7371 /* 2687 */ "cxbgu $\x03, $\x04, $\xFF\x01\x01\0"
7372 /* 2706 */ "cxbleu $\x03, $\x04, $\xFF\x01\x01\0"
7373 /* 2726 */ "cxbcc $\x03, $\x04, $\xFF\x01\x01\0"
7374 /* 2745 */ "cxbcs $\x03, $\x04, $\xFF\x01\x01\0"
7375 /* 2764 */ "cxbpos $\x03, $\x04, $\xFF\x01\x01\0"
7376 /* 2784 */ "cxbneg $\x03, $\x04, $\xFF\x01\x01\0"
7377 /* 2804 */ "cxbvc $\x03, $\x04, $\xFF\x01\x01\0"
7378 /* 2823 */ "cxbvs $\x03, $\x04, $\xFF\x01\x01\0"
7379 /* 2842 */ "fmovda %icc, $\x02, $\x01\0"
7380 /* 2862 */ "fmovda %ncc, $\x02, $\x01\0"
7381 /* 2882 */ "fmovdn %icc, $\x02, $\x01\0"
7382 /* 2902 */ "fmovdn %ncc, $\x02, $\x01\0"
7383 /* 2922 */ "fmovdne %icc, $\x02, $\x01\0"
7384 /* 2943 */ "fmovdne %ncc, $\x02, $\x01\0"
7385 /* 2964 */ "fmovde %icc, $\x02, $\x01\0"
7386 /* 2984 */ "fmovde %ncc, $\x02, $\x01\0"
7387 /* 3004 */ "fmovdg %icc, $\x02, $\x01\0"
7388 /* 3024 */ "fmovdg %ncc, $\x02, $\x01\0"
7389 /* 3044 */ "fmovdle %icc, $\x02, $\x01\0"
7390 /* 3065 */ "fmovdle %ncc, $\x02, $\x01\0"
7391 /* 3086 */ "fmovdge %icc, $\x02, $\x01\0"
7392 /* 3107 */ "fmovdge %ncc, $\x02, $\x01\0"
7393 /* 3128 */ "fmovdl %icc, $\x02, $\x01\0"
7394 /* 3148 */ "fmovdl %ncc, $\x02, $\x01\0"
7395 /* 3168 */ "fmovdgu %icc, $\x02, $\x01\0"
7396 /* 3189 */ "fmovdgu %ncc, $\x02, $\x01\0"
7397 /* 3210 */ "fmovdleu %icc, $\x02, $\x01\0"
7398 /* 3232 */ "fmovdleu %ncc, $\x02, $\x01\0"
7399 /* 3254 */ "fmovdcc %icc, $\x02, $\x01\0"
7400 /* 3275 */ "fmovdcc %ncc, $\x02, $\x01\0"
7401 /* 3296 */ "fmovdcs %icc, $\x02, $\x01\0"
7402 /* 3317 */ "fmovdcs %ncc, $\x02, $\x01\0"
7403 /* 3338 */ "fmovdpos %icc, $\x02, $\x01\0"
7404 /* 3360 */ "fmovdpos %ncc, $\x02, $\x01\0"
7405 /* 3382 */ "fmovdneg %icc, $\x02, $\x01\0"
7406 /* 3404 */ "fmovdneg %ncc, $\x02, $\x01\0"
7407 /* 3426 */ "fmovdvc %icc, $\x02, $\x01\0"
7408 /* 3447 */ "fmovdvc %ncc, $\x02, $\x01\0"
7409 /* 3468 */ "fmovdvs %icc, $\x02, $\x01\0"
7410 /* 3489 */ "fmovdvs %ncc, $\x02, $\x01\0"
7411 /* 3510 */ "fmovqa %icc, $\x02, $\x01\0"
7412 /* 3530 */ "fmovqa %ncc, $\x02, $\x01\0"
7413 /* 3550 */ "fmovqn %icc, $\x02, $\x01\0"
7414 /* 3570 */ "fmovqn %ncc, $\x02, $\x01\0"
7415 /* 3590 */ "fmovqne %icc, $\x02, $\x01\0"
7416 /* 3611 */ "fmovqne %ncc, $\x02, $\x01\0"
7417 /* 3632 */ "fmovqe %icc, $\x02, $\x01\0"
7418 /* 3652 */ "fmovqe %ncc, $\x02, $\x01\0"
7419 /* 3672 */ "fmovqg %icc, $\x02, $\x01\0"
7420 /* 3692 */ "fmovqg %ncc, $\x02, $\x01\0"
7421 /* 3712 */ "fmovqle %icc, $\x02, $\x01\0"
7422 /* 3733 */ "fmovqle %ncc, $\x02, $\x01\0"
7423 /* 3754 */ "fmovqge %icc, $\x02, $\x01\0"
7424 /* 3775 */ "fmovqge %ncc, $\x02, $\x01\0"
7425 /* 3796 */ "fmovql %icc, $\x02, $\x01\0"
7426 /* 3816 */ "fmovql %ncc, $\x02, $\x01\0"
7427 /* 3836 */ "fmovqgu %icc, $\x02, $\x01\0"
7428 /* 3857 */ "fmovqgu %ncc, $\x02, $\x01\0"
7429 /* 3878 */ "fmovqleu %icc, $\x02, $\x01\0"
7430 /* 3900 */ "fmovqleu %ncc, $\x02, $\x01\0"
7431 /* 3922 */ "fmovqcc %icc, $\x02, $\x01\0"
7432 /* 3943 */ "fmovqcc %ncc, $\x02, $\x01\0"
7433 /* 3964 */ "fmovqcs %icc, $\x02, $\x01\0"
7434 /* 3985 */ "fmovqcs %ncc, $\x02, $\x01\0"
7435 /* 4006 */ "fmovqpos %icc, $\x02, $\x01\0"
7436 /* 4028 */ "fmovqpos %ncc, $\x02, $\x01\0"
7437 /* 4050 */ "fmovqneg %icc, $\x02, $\x01\0"
7438 /* 4072 */ "fmovqneg %ncc, $\x02, $\x01\0"
7439 /* 4094 */ "fmovqvc %icc, $\x02, $\x01\0"
7440 /* 4115 */ "fmovqvc %ncc, $\x02, $\x01\0"
7441 /* 4136 */ "fmovqvs %icc, $\x02, $\x01\0"
7442 /* 4157 */ "fmovqvs %ncc, $\x02, $\x01\0"
7443 /* 4178 */ "fmovrdlez $\x02, $\x03, $\x01\0"
7444 /* 4199 */ "fmovrdlz $\x02, $\x03, $\x01\0"
7445 /* 4219 */ "fmovrdgz $\x02, $\x03, $\x01\0"
7446 /* 4239 */ "fmovrdgez $\x02, $\x03, $\x01\0"
7447 /* 4260 */ "fmovrqlez $\x02, $\x03, $\x01\0"
7448 /* 4281 */ "fmovrqlz $\x02, $\x03, $\x01\0"
7449 /* 4301 */ "fmovrqgz $\x02, $\x03, $\x01\0"
7450 /* 4321 */ "fmovrqgez $\x02, $\x03, $\x01\0"
7451 /* 4342 */ "fmovrslez $\x02, $\x03, $\x01\0"
7452 /* 4363 */ "fmovrslz $\x02, $\x03, $\x01\0"
7453 /* 4383 */ "fmovrsgz $\x02, $\x03, $\x01\0"
7454 /* 4403 */ "fmovrsgez $\x02, $\x03, $\x01\0"
7455 /* 4424 */ "fmovsa %icc, $\x02, $\x01\0"
7456 /* 4444 */ "fmovsa %ncc, $\x02, $\x01\0"
7457 /* 4464 */ "fmovsn %icc, $\x02, $\x01\0"
7458 /* 4484 */ "fmovsn %ncc, $\x02, $\x01\0"
7459 /* 4504 */ "fmovsne %icc, $\x02, $\x01\0"
7460 /* 4525 */ "fmovsne %ncc, $\x02, $\x01\0"
7461 /* 4546 */ "fmovse %icc, $\x02, $\x01\0"
7462 /* 4566 */ "fmovse %ncc, $\x02, $\x01\0"
7463 /* 4586 */ "fmovsg %icc, $\x02, $\x01\0"
7464 /* 4606 */ "fmovsg %ncc, $\x02, $\x01\0"
7465 /* 4626 */ "fmovsle %icc, $\x02, $\x01\0"
7466 /* 4647 */ "fmovsle %ncc, $\x02, $\x01\0"
7467 /* 4668 */ "fmovsge %icc, $\x02, $\x01\0"
7468 /* 4689 */ "fmovsge %ncc, $\x02, $\x01\0"
7469 /* 4710 */ "fmovsl %icc, $\x02, $\x01\0"
7470 /* 4730 */ "fmovsl %ncc, $\x02, $\x01\0"
7471 /* 4750 */ "fmovsgu %icc, $\x02, $\x01\0"
7472 /* 4771 */ "fmovsgu %ncc, $\x02, $\x01\0"
7473 /* 4792 */ "fmovsleu %icc, $\x02, $\x01\0"
7474 /* 4814 */ "fmovsleu %ncc, $\x02, $\x01\0"
7475 /* 4836 */ "fmovscc %icc, $\x02, $\x01\0"
7476 /* 4857 */ "fmovscc %ncc, $\x02, $\x01\0"
7477 /* 4878 */ "fmovscs %icc, $\x02, $\x01\0"
7478 /* 4899 */ "fmovscs %ncc, $\x02, $\x01\0"
7479 /* 4920 */ "fmovspos %icc, $\x02, $\x01\0"
7480 /* 4942 */ "fmovspos %ncc, $\x02, $\x01\0"
7481 /* 4964 */ "fmovsneg %icc, $\x02, $\x01\0"
7482 /* 4986 */ "fmovsneg %ncc, $\x02, $\x01\0"
7483 /* 5008 */ "fmovsvc %icc, $\x02, $\x01\0"
7484 /* 5029 */ "fmovsvc %ncc, $\x02, $\x01\0"
7485 /* 5050 */ "fmovsvs %icc, $\x02, $\x01\0"
7486 /* 5071 */ "fmovsvs %ncc, $\x02, $\x01\0"
7487 /* 5092 */ "mova %icc, $\x02, $\x01\0"
7488 /* 5110 */ "mova %ncc, $\x02, $\x01\0"
7489 /* 5128 */ "movn %icc, $\x02, $\x01\0"
7490 /* 5146 */ "movn %ncc, $\x02, $\x01\0"
7491 /* 5164 */ "movne %icc, $\x02, $\x01\0"
7492 /* 5183 */ "movne %ncc, $\x02, $\x01\0"
7493 /* 5202 */ "move %icc, $\x02, $\x01\0"
7494 /* 5220 */ "move %ncc, $\x02, $\x01\0"
7495 /* 5238 */ "movg %icc, $\x02, $\x01\0"
7496 /* 5256 */ "movg %ncc, $\x02, $\x01\0"
7497 /* 5274 */ "movle %icc, $\x02, $\x01\0"
7498 /* 5293 */ "movle %ncc, $\x02, $\x01\0"
7499 /* 5312 */ "movge %icc, $\x02, $\x01\0"
7500 /* 5331 */ "movge %ncc, $\x02, $\x01\0"
7501 /* 5350 */ "movl %icc, $\x02, $\x01\0"
7502 /* 5368 */ "movl %ncc, $\x02, $\x01\0"
7503 /* 5386 */ "movgu %icc, $\x02, $\x01\0"
7504 /* 5405 */ "movgu %ncc, $\x02, $\x01\0"
7505 /* 5424 */ "movleu %icc, $\x02, $\x01\0"
7506 /* 5444 */ "movleu %ncc, $\x02, $\x01\0"
7507 /* 5464 */ "movcc %icc, $\x02, $\x01\0"
7508 /* 5483 */ "movcc %ncc, $\x02, $\x01\0"
7509 /* 5502 */ "movcs %icc, $\x02, $\x01\0"
7510 /* 5521 */ "movcs %ncc, $\x02, $\x01\0"
7511 /* 5540 */ "movpos %icc, $\x02, $\x01\0"
7512 /* 5560 */ "movpos %ncc, $\x02, $\x01\0"
7513 /* 5580 */ "movneg %icc, $\x02, $\x01\0"
7514 /* 5600 */ "movneg %ncc, $\x02, $\x01\0"
7515 /* 5620 */ "movvc %icc, $\x02, $\x01\0"
7516 /* 5639 */ "movvc %ncc, $\x02, $\x01\0"
7517 /* 5658 */ "movvs %icc, $\x02, $\x01\0"
7518 /* 5677 */ "movvs %ncc, $\x02, $\x01\0"
7519 /* 5696 */ "movrlez $\x02, $\x03, $\x01\0"
7520 /* 5715 */ "movrlz $\x02, $\x03, $\x01\0"
7521 /* 5733 */ "movrgz $\x02, $\x03, $\x01\0"
7522 /* 5751 */ "movrgez $\x02, $\x03, $\x01\0"
7523 /* 5770 */ "tst $\x02\0"
7524 /* 5777 */ "mov $\x03, $\x01\0"
7525 /* 5788 */ "restore\0"
7526 /* 5796 */ "ret\0"
7527 /* 5800 */ "retl\0"
7528 /* 5805 */ "save\0"
7529 /* 5810 */ "cmp $\x02, $\x03\0"
7530 /* 5821 */ "ta %icc, $\x02\0"
7531 /* 5833 */ "ta %ncc, $\x02\0"
7532 /* 5845 */ "ta %icc, $\x01 + $\x02\0"
7533 /* 5862 */ "ta %ncc, $\x01 + $\x02\0"
7534 /* 5879 */ "tn %icc, $\x02\0"
7535 /* 5891 */ "tn %ncc, $\x02\0"
7536 /* 5903 */ "tn %icc, $\x01 + $\x02\0"
7537 /* 5920 */ "tn %ncc, $\x01 + $\x02\0"
7538 /* 5937 */ "tne %icc, $\x02\0"
7539 /* 5950 */ "tne %ncc, $\x02\0"
7540 /* 5963 */ "tne %icc, $\x01 + $\x02\0"
7541 /* 5981 */ "tne %ncc, $\x01 + $\x02\0"
7542 /* 5999 */ "te %icc, $\x02\0"
7543 /* 6011 */ "te %ncc, $\x02\0"
7544 /* 6023 */ "te %icc, $\x01 + $\x02\0"
7545 /* 6040 */ "te %ncc, $\x01 + $\x02\0"
7546 /* 6057 */ "tg %icc, $\x02\0"
7547 /* 6069 */ "tg %ncc, $\x02\0"
7548 /* 6081 */ "tg %icc, $\x01 + $\x02\0"
7549 /* 6098 */ "tg %ncc, $\x01 + $\x02\0"
7550 /* 6115 */ "tle %icc, $\x02\0"
7551 /* 6128 */ "tle %ncc, $\x02\0"
7552 /* 6141 */ "tle %icc, $\x01 + $\x02\0"
7553 /* 6159 */ "tle %ncc, $\x01 + $\x02\0"
7554 /* 6177 */ "tge %icc, $\x02\0"
7555 /* 6190 */ "tge %ncc, $\x02\0"
7556 /* 6203 */ "tge %icc, $\x01 + $\x02\0"
7557 /* 6221 */ "tge %ncc, $\x01 + $\x02\0"
7558 /* 6239 */ "tl %icc, $\x02\0"
7559 /* 6251 */ "tl %ncc, $\x02\0"
7560 /* 6263 */ "tl %icc, $\x01 + $\x02\0"
7561 /* 6280 */ "tl %ncc, $\x01 + $\x02\0"
7562 /* 6297 */ "tgu %icc, $\x02\0"
7563 /* 6310 */ "tgu %ncc, $\x02\0"
7564 /* 6323 */ "tgu %icc, $\x01 + $\x02\0"
7565 /* 6341 */ "tgu %ncc, $\x01 + $\x02\0"
7566 /* 6359 */ "tleu %icc, $\x02\0"
7567 /* 6373 */ "tleu %ncc, $\x02\0"
7568 /* 6387 */ "tleu %icc, $\x01 + $\x02\0"
7569 /* 6406 */ "tleu %ncc, $\x01 + $\x02\0"
7570 /* 6425 */ "tcc %icc, $\x02\0"
7571 /* 6438 */ "tcc %ncc, $\x02\0"
7572 /* 6451 */ "tcc %icc, $\x01 + $\x02\0"
7573 /* 6469 */ "tcc %ncc, $\x01 + $\x02\0"
7574 /* 6487 */ "tcs %icc, $\x02\0"
7575 /* 6500 */ "tcs %ncc, $\x02\0"
7576 /* 6513 */ "tcs %icc, $\x01 + $\x02\0"
7577 /* 6531 */ "tcs %ncc, $\x01 + $\x02\0"
7578 /* 6549 */ "tpos %icc, $\x02\0"
7579 /* 6563 */ "tpos %ncc, $\x02\0"
7580 /* 6577 */ "tpos %icc, $\x01 + $\x02\0"
7581 /* 6596 */ "tpos %ncc, $\x01 + $\x02\0"
7582 /* 6615 */ "tneg %icc, $\x02\0"
7583 /* 6629 */ "tneg %ncc, $\x02\0"
7584 /* 6643 */ "tneg %icc, $\x01 + $\x02\0"
7585 /* 6662 */ "tneg %ncc, $\x01 + $\x02\0"
7586 /* 6681 */ "tvc %icc, $\x02\0"
7587 /* 6694 */ "tvc %ncc, $\x02\0"
7588 /* 6707 */ "tvc %icc, $\x01 + $\x02\0"
7589 /* 6725 */ "tvc %ncc, $\x01 + $\x02\0"
7590 /* 6743 */ "tvs %icc, $\x02\0"
7591 /* 6756 */ "tvs %ncc, $\x02\0"
7592 /* 6769 */ "tvs %icc, $\x01 + $\x02\0"
7593 /* 6787 */ "tvs %ncc, $\x01 + $\x02\0"
7594 /* 6805 */ "ta $\x02\0"
7595 /* 6811 */ "ta $\x01 + $\x02\0"
7596 /* 6822 */ "tn $\x02\0"
7597 /* 6828 */ "tn $\x01 + $\x02\0"
7598 /* 6839 */ "tne $\x02\0"
7599 /* 6846 */ "tne $\x01 + $\x02\0"
7600 /* 6858 */ "te $\x02\0"
7601 /* 6864 */ "te $\x01 + $\x02\0"
7602 /* 6875 */ "tg $\x02\0"
7603 /* 6881 */ "tg $\x01 + $\x02\0"
7604 /* 6892 */ "tle $\x02\0"
7605 /* 6899 */ "tle $\x01 + $\x02\0"
7606 /* 6911 */ "tge $\x02\0"
7607 /* 6918 */ "tge $\x01 + $\x02\0"
7608 /* 6930 */ "tl $\x02\0"
7609 /* 6936 */ "tl $\x01 + $\x02\0"
7610 /* 6947 */ "tgu $\x02\0"
7611 /* 6954 */ "tgu $\x01 + $\x02\0"
7612 /* 6966 */ "tleu $\x02\0"
7613 /* 6974 */ "tleu $\x01 + $\x02\0"
7614 /* 6987 */ "tcc $\x02\0"
7615 /* 6994 */ "tcc $\x01 + $\x02\0"
7616 /* 7006 */ "tcs $\x02\0"
7617 /* 7013 */ "tcs $\x01 + $\x02\0"
7618 /* 7025 */ "tpos $\x02\0"
7619 /* 7033 */ "tpos $\x01 + $\x02\0"
7620 /* 7046 */ "tneg $\x02\0"
7621 /* 7054 */ "tneg $\x01 + $\x02\0"
7622 /* 7067 */ "tvc $\x02\0"
7623 /* 7074 */ "tvc $\x01 + $\x02\0"
7624 /* 7086 */ "tvs $\x02\0"
7625 /* 7093 */ "tvs $\x01 + $\x02\0"
7626 /* 7105 */ "ta %xcc, $\x02\0"
7627 /* 7117 */ "ta %xcc, $\x01 + $\x02\0"
7628 /* 7134 */ "tn %xcc, $\x02\0"
7629 /* 7146 */ "tn %xcc, $\x01 + $\x02\0"
7630 /* 7163 */ "tne %xcc, $\x02\0"
7631 /* 7176 */ "tne %xcc, $\x01 + $\x02\0"
7632 /* 7194 */ "te %xcc, $\x02\0"
7633 /* 7206 */ "te %xcc, $\x01 + $\x02\0"
7634 /* 7223 */ "tg %xcc, $\x02\0"
7635 /* 7235 */ "tg %xcc, $\x01 + $\x02\0"
7636 /* 7252 */ "tle %xcc, $\x02\0"
7637 /* 7265 */ "tle %xcc, $\x01 + $\x02\0"
7638 /* 7283 */ "tge %xcc, $\x02\0"
7639 /* 7296 */ "tge %xcc, $\x01 + $\x02\0"
7640 /* 7314 */ "tl %xcc, $\x02\0"
7641 /* 7326 */ "tl %xcc, $\x01 + $\x02\0"
7642 /* 7343 */ "tgu %xcc, $\x02\0"
7643 /* 7356 */ "tgu %xcc, $\x01 + $\x02\0"
7644 /* 7374 */ "tleu %xcc, $\x02\0"
7645 /* 7388 */ "tleu %xcc, $\x01 + $\x02\0"
7646 /* 7407 */ "tcc %xcc, $\x02\0"
7647 /* 7420 */ "tcc %xcc, $\x01 + $\x02\0"
7648 /* 7438 */ "tcs %xcc, $\x02\0"
7649 /* 7451 */ "tcs %xcc, $\x01 + $\x02\0"
7650 /* 7469 */ "tpos %xcc, $\x02\0"
7651 /* 7483 */ "tpos %xcc, $\x01 + $\x02\0"
7652 /* 7502 */ "tneg %xcc, $\x02\0"
7653 /* 7516 */ "tneg %xcc, $\x01 + $\x02\0"
7654 /* 7535 */ "tvc %xcc, $\x02\0"
7655 /* 7548 */ "tvc %xcc, $\x01 + $\x02\0"
7656 /* 7566 */ "tvs %xcc, $\x02\0"
7657 /* 7579 */ "tvs %xcc, $\x01 + $\x02\0"
7658 /* 7597 */ "fcmpd $\x02, $\x03\0"
7659 /* 7610 */ "fcmped $\x02, $\x03\0"
7660 /* 7624 */ "fcmpeq $\x02, $\x03\0"
7661 /* 7638 */ "fcmpes $\x02, $\x03\0"
7662 /* 7652 */ "fcmpq $\x02, $\x03\0"
7663 /* 7665 */ "fcmps $\x02, $\x03\0"
7664 /* 7678 */ "fmovda $\x02, $\x03, $\x01\0"
7665 /* 7696 */ "fmovdn $\x02, $\x03, $\x01\0"
7666 /* 7714 */ "fmovdu $\x02, $\x03, $\x01\0"
7667 /* 7732 */ "fmovdg $\x02, $\x03, $\x01\0"
7668 /* 7750 */ "fmovdug $\x02, $\x03, $\x01\0"
7669 /* 7769 */ "fmovdl $\x02, $\x03, $\x01\0"
7670 /* 7787 */ "fmovdul $\x02, $\x03, $\x01\0"
7671 /* 7806 */ "fmovdlg $\x02, $\x03, $\x01\0"
7672 /* 7825 */ "fmovdne $\x02, $\x03, $\x01\0"
7673 /* 7844 */ "fmovde $\x02, $\x03, $\x01\0"
7674 /* 7862 */ "fmovdue $\x02, $\x03, $\x01\0"
7675 /* 7881 */ "fmovdge $\x02, $\x03, $\x01\0"
7676 /* 7900 */ "fmovduge $\x02, $\x03, $\x01\0"
7677 /* 7920 */ "fmovdle $\x02, $\x03, $\x01\0"
7678 /* 7939 */ "fmovdule $\x02, $\x03, $\x01\0"
7679 /* 7959 */ "fmovdo $\x02, $\x03, $\x01\0"
7680 /* 7977 */ "fmovqa $\x02, $\x03, $\x01\0"
7681 /* 7995 */ "fmovqn $\x02, $\x03, $\x01\0"
7682 /* 8013 */ "fmovqu $\x02, $\x03, $\x01\0"
7683 /* 8031 */ "fmovqg $\x02, $\x03, $\x01\0"
7684 /* 8049 */ "fmovqug $\x02, $\x03, $\x01\0"
7685 /* 8068 */ "fmovql $\x02, $\x03, $\x01\0"
7686 /* 8086 */ "fmovqul $\x02, $\x03, $\x01\0"
7687 /* 8105 */ "fmovqlg $\x02, $\x03, $\x01\0"
7688 /* 8124 */ "fmovqne $\x02, $\x03, $\x01\0"
7689 /* 8143 */ "fmovqe $\x02, $\x03, $\x01\0"
7690 /* 8161 */ "fmovque $\x02, $\x03, $\x01\0"
7691 /* 8180 */ "fmovqge $\x02, $\x03, $\x01\0"
7692 /* 8199 */ "fmovquge $\x02, $\x03, $\x01\0"
7693 /* 8219 */ "fmovqle $\x02, $\x03, $\x01\0"
7694 /* 8238 */ "fmovqule $\x02, $\x03, $\x01\0"
7695 /* 8258 */ "fmovqo $\x02, $\x03, $\x01\0"
7696 /* 8276 */ "fmovsa $\x02, $\x03, $\x01\0"
7697 /* 8294 */ "fmovsn $\x02, $\x03, $\x01\0"
7698 /* 8312 */ "fmovsu $\x02, $\x03, $\x01\0"
7699 /* 8330 */ "fmovsg $\x02, $\x03, $\x01\0"
7700 /* 8348 */ "fmovsug $\x02, $\x03, $\x01\0"
7701 /* 8367 */ "fmovsl $\x02, $\x03, $\x01\0"
7702 /* 8385 */ "fmovsul $\x02, $\x03, $\x01\0"
7703 /* 8404 */ "fmovslg $\x02, $\x03, $\x01\0"
7704 /* 8423 */ "fmovsne $\x02, $\x03, $\x01\0"
7705 /* 8442 */ "fmovse $\x02, $\x03, $\x01\0"
7706 /* 8460 */ "fmovsue $\x02, $\x03, $\x01\0"
7707 /* 8479 */ "fmovsge $\x02, $\x03, $\x01\0"
7708 /* 8498 */ "fmovsuge $\x02, $\x03, $\x01\0"
7709 /* 8518 */ "fmovsle $\x02, $\x03, $\x01\0"
7710 /* 8537 */ "fmovsule $\x02, $\x03, $\x01\0"
7711 /* 8557 */ "fmovso $\x02, $\x03, $\x01\0"
7712 /* 8575 */ "mova $\x02, $\x03, $\x01\0"
7713 /* 8591 */ "movn $\x02, $\x03, $\x01\0"
7714 /* 8607 */ "movu $\x02, $\x03, $\x01\0"
7715 /* 8623 */ "movg $\x02, $\x03, $\x01\0"
7716 /* 8639 */ "movug $\x02, $\x03, $\x01\0"
7717 /* 8656 */ "movl $\x02, $\x03, $\x01\0"
7718 /* 8672 */ "movul $\x02, $\x03, $\x01\0"
7719 /* 8689 */ "movlg $\x02, $\x03, $\x01\0"
7720 /* 8706 */ "movne $\x02, $\x03, $\x01\0"
7721 /* 8723 */ "move $\x02, $\x03, $\x01\0"
7722 /* 8739 */ "movue $\x02, $\x03, $\x01\0"
7723 /* 8756 */ "movge $\x02, $\x03, $\x01\0"
7724 /* 8773 */ "movuge $\x02, $\x03, $\x01\0"
7725 /* 8791 */ "movle $\x02, $\x03, $\x01\0"
7726 /* 8808 */ "movule $\x02, $\x03, $\x01\0"
7727 /* 8826 */ "movo $\x02, $\x03, $\x01\0"
7728 /* 8842 */ "pause $\x03\0"
7729 ;
7730
7731#ifndef NDEBUG
7732 static struct SortCheck {
7733 SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
7734 assert(std::is_sorted(
7735 OpToPatterns.begin(), OpToPatterns.end(),
7736 [](const PatternsForOpcode &L, const PatternsForOpcode &R) {
7737 return L.Opcode < R.Opcode;
7738 }) &&
7739 "tablegen failed to sort opcode patterns");
7740 }
7741 } sortCheckVar(OpToPatterns);
7742#endif
7743
7744 AliasMatchingData M {
7745 .OpToPatterns: ArrayRef(OpToPatterns),
7746 .Patterns: ArrayRef(Patterns),
7747 .PatternConds: ArrayRef(Conds),
7748 .AsmStrings: StringRef(AsmStrings, std::size(AsmStrings)),
7749 .ValidateMCOperand: nullptr,
7750 };
7751 const char *AsmString = matchAliasPatterns(MI, STI: &STI, M);
7752 if (!AsmString) return false;
7753
7754 unsigned I = 0;
7755 while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
7756 AsmString[I] != '$' && AsmString[I] != '\0')
7757 ++I;
7758 OS << '\t' << StringRef(AsmString, I);
7759 if (AsmString[I] != '\0') {
7760 if (AsmString[I] == ' ' || AsmString[I] == '\t') {
7761 OS << '\t';
7762 ++I;
7763 }
7764 do {
7765 if (AsmString[I] == '$') {
7766 ++I;
7767 if (AsmString[I] == (char)0xff) {
7768 ++I;
7769 int OpIdx = AsmString[I++] - 1;
7770 int PrintMethodIdx = AsmString[I++] - 1;
7771 printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, STI, O&: OS);
7772 } else
7773 printOperand(MI, opNum: unsigned(AsmString[I++]) - 1, STI, OS);
7774 } else {
7775 OS << AsmString[I++];
7776 }
7777 } while (AsmString[I] != '\0');
7778 }
7779
7780 return true;
7781}
7782
7783void SparcInstPrinter::printCustomAliasOperand(
7784 const MCInst *MI, uint64_t Address, unsigned OpIdx,
7785 unsigned PrintMethodIdx,
7786 const MCSubtargetInfo &STI,
7787 raw_ostream &OS) {
7788 switch (PrintMethodIdx) {
7789 default:
7790 llvm_unreachable("Unknown PrintMethod kind");
7791 break;
7792 case 0:
7793 printCTILabel(MI, Address, OpNum: OpIdx, STI, O&: OS);
7794 break;
7795 }
7796}
7797
7798#endif // PRINT_ALIAS_INSTR
7799