| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Assembly Writer Source Fragment *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* From: Sparc.td *| |
| 7 | |* *| |
| 8 | \*===----------------------------------------------------------------------===*/ |
| 9 | |
| 10 | /// getMnemonic - This method is automatically generated by tablegen |
| 11 | /// from the instruction set description. |
| 12 | std::pair<const char *, uint64_t> |
| 13 | SparcInstPrinter::getMnemonic(const MCInst &MI) const { |
| 14 | |
| 15 | #ifdef __GNUC__ |
| 16 | #pragma GCC diagnostic push |
| 17 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 18 | #endif |
| 19 | static const char AsmStrs[] = { |
| 20 | /* 0 */ "fcmpd %fcc0, \000" |
| 21 | /* 14 */ "fcmpq %fcc0, \000" |
| 22 | /* 28 */ "fcmps %fcc0, \000" |
| 23 | /* 42 */ "rd %wim, \000" |
| 24 | /* 52 */ "rdpr %fq, \000" |
| 25 | /* 63 */ "rd %tbr, \000" |
| 26 | /* 73 */ "rd %psr, \000" |
| 27 | /* 83 */ "aes_kexpand0 \000" |
| 28 | /* 97 */ "aes_dround01 \000" |
| 29 | /* 111 */ "aes_eround01 \000" |
| 30 | /* 125 */ "fsrc1 \000" |
| 31 | /* 132 */ "aes_kexpand1 \000" |
| 32 | /* 146 */ "fandnot1 \000" |
| 33 | /* 156 */ "fnot1 \000" |
| 34 | /* 163 */ "fornot1 \000" |
| 35 | /* 172 */ "fsra32 \000" |
| 36 | /* 180 */ "fpsub32 \000" |
| 37 | /* 189 */ "fpadd32 \000" |
| 38 | /* 198 */ "edge32 \000" |
| 39 | /* 206 */ "fcmple32 \000" |
| 40 | /* 216 */ "fcmpne32 \000" |
| 41 | /* 226 */ "fpack32 \000" |
| 42 | /* 235 */ "cmask32 \000" |
| 43 | /* 244 */ "fsll32 \000" |
| 44 | /* 252 */ "fsrl32 \000" |
| 45 | /* 260 */ "fcmpeq32 \000" |
| 46 | /* 270 */ "fslas32 \000" |
| 47 | /* 279 */ "fcmpgt32 \000" |
| 48 | /* 289 */ "array32 \000" |
| 49 | /* 298 */ "fsrc2 \000" |
| 50 | /* 305 */ "aes_kexpand2 \000" |
| 51 | /* 319 */ "fandnot2 \000" |
| 52 | /* 329 */ "fnot2 \000" |
| 53 | /* 336 */ "fornot2 \000" |
| 54 | /* 345 */ "aes_dround23 \000" |
| 55 | /* 359 */ "aes_eround23 \000" |
| 56 | /* 373 */ "fpadd64 \000" |
| 57 | /* 382 */ "fsra16 \000" |
| 58 | /* 390 */ "fpsub16 \000" |
| 59 | /* 399 */ "fpadd16 \000" |
| 60 | /* 408 */ "edge16 \000" |
| 61 | /* 416 */ "fcmple16 \000" |
| 62 | /* 426 */ "fcmpne16 \000" |
| 63 | /* 436 */ "fpack16 \000" |
| 64 | /* 445 */ "cmask16 \000" |
| 65 | /* 454 */ "fsll16 \000" |
| 66 | /* 462 */ "fsrl16 \000" |
| 67 | /* 470 */ "fchksm16 \000" |
| 68 | /* 480 */ "fmean16 \000" |
| 69 | /* 489 */ "fcmpeq16 \000" |
| 70 | /* 499 */ "fslas16 \000" |
| 71 | /* 508 */ "fcmpgt16 \000" |
| 72 | /* 518 */ "fmul8x16 \000" |
| 73 | /* 528 */ "fmuld8ulx16 \000" |
| 74 | /* 541 */ "fmul8ulx16 \000" |
| 75 | /* 553 */ "fmuld8sux16 \000" |
| 76 | /* 566 */ "fmul8sux16 \000" |
| 77 | /* 578 */ "array16 \000" |
| 78 | /* 587 */ "edge8 \000" |
| 79 | /* 594 */ "cmask8 \000" |
| 80 | /* 602 */ "array8 \000" |
| 81 | /* 610 */ "!ADJCALLSTACKDOWN \000" |
| 82 | /* 629 */ "!ADJCALLSTACKUP \000" |
| 83 | /* 646 */ "stba \000" |
| 84 | /* 652 */ "stda \000" |
| 85 | /* 658 */ "stha \000" |
| 86 | /* 664 */ "stqa \000" |
| 87 | /* 670 */ "sra \000" |
| 88 | /* 675 */ "faligndata \000" |
| 89 | /* 687 */ "sta \000" |
| 90 | /* 692 */ "stxa \000" |
| 91 | /* 698 */ "stb \000" |
| 92 | /* 703 */ "sub \000" |
| 93 | /* 708 */ "crc32c \000" |
| 94 | /* 716 */ "smac \000" |
| 95 | /* 722 */ "umac \000" |
| 96 | /* 728 */ "tsubcc \000" |
| 97 | /* 736 */ "addxccc \000" |
| 98 | /* 745 */ "taddcc \000" |
| 99 | /* 753 */ "andcc \000" |
| 100 | /* 760 */ "smulcc \000" |
| 101 | /* 768 */ "umulcc \000" |
| 102 | /* 776 */ "andncc \000" |
| 103 | /* 784 */ "orncc \000" |
| 104 | /* 791 */ "xnorcc \000" |
| 105 | /* 799 */ "xorcc \000" |
| 106 | /* 806 */ "mulscc \000" |
| 107 | /* 814 */ "sdivcc \000" |
| 108 | /* 822 */ "udivcc \000" |
| 109 | /* 830 */ "subxcc \000" |
| 110 | /* 838 */ "addxcc \000" |
| 111 | /* 846 */ "popc \000" |
| 112 | /* 852 */ "addxc \000" |
| 113 | /* 859 */ "fsubd \000" |
| 114 | /* 866 */ "fhsubd \000" |
| 115 | /* 874 */ "fmsubd \000" |
| 116 | /* 882 */ "fnmsubd \000" |
| 117 | /* 891 */ "add \000" |
| 118 | /* 896 */ "faddd \000" |
| 119 | /* 903 */ "fhaddd \000" |
| 120 | /* 911 */ "fnhaddd \000" |
| 121 | /* 920 */ "fmaddd \000" |
| 122 | /* 928 */ "fnmaddd \000" |
| 123 | /* 937 */ "fnaddd \000" |
| 124 | /* 945 */ "fcmped \000" |
| 125 | /* 953 */ "fnegd \000" |
| 126 | /* 960 */ "fmuld \000" |
| 127 | /* 967 */ "fnmuld \000" |
| 128 | /* 975 */ "fsmuld \000" |
| 129 | /* 983 */ "fnsmuld \000" |
| 130 | /* 992 */ "fand \000" |
| 131 | /* 998 */ "fnand \000" |
| 132 | /* 1005 */ "fexpand \000" |
| 133 | /* 1014 */ "des_kexpand \000" |
| 134 | /* 1027 */ "des_round \000" |
| 135 | /* 1038 */ "fitod \000" |
| 136 | /* 1045 */ "fqtod \000" |
| 137 | /* 1052 */ "fstod \000" |
| 138 | /* 1059 */ "fxtod \000" |
| 139 | /* 1066 */ "movxtod \000" |
| 140 | /* 1075 */ "fcmpd \000" |
| 141 | /* 1082 */ "flcmpd \000" |
| 142 | /* 1090 */ "rd \000" |
| 143 | /* 1094 */ "fabsd \000" |
| 144 | /* 1101 */ "fsqrtd \000" |
| 145 | /* 1109 */ "std \000" |
| 146 | /* 1114 */ "fdivd \000" |
| 147 | /* 1121 */ "fmovd \000" |
| 148 | /* 1128 */ "fpmerge \000" |
| 149 | /* 1137 */ "bshuffle \000" |
| 150 | /* 1147 */ "fone \000" |
| 151 | /* 1153 */ "restore \000" |
| 152 | /* 1162 */ "save \000" |
| 153 | /* 1168 */ "camellia_f \000" |
| 154 | /* 1180 */ "flush \000" |
| 155 | /* 1187 */ "sth \000" |
| 156 | /* 1192 */ "sethi \000" |
| 157 | /* 1199 */ "fpmaddxhi \000" |
| 158 | /* 1210 */ "umulxhi \000" |
| 159 | /* 1219 */ "xmulxhi \000" |
| 160 | /* 1228 */ "camellia_fli \000" |
| 161 | /* 1242 */ "fdtoi \000" |
| 162 | /* 1249 */ "fqtoi \000" |
| 163 | /* 1256 */ "fstoi \000" |
| 164 | /* 1263 */ "bmask \000" |
| 165 | /* 1270 */ "edge32l \000" |
| 166 | /* 1279 */ "edge16l \000" |
| 167 | /* 1288 */ "edge8l \000" |
| 168 | /* 1296 */ "aes_dround01_l \000" |
| 169 | /* 1312 */ "aes_eround01_l \000" |
| 170 | /* 1328 */ "aes_dround23_l \000" |
| 171 | /* 1344 */ "aes_eround23_l \000" |
| 172 | /* 1360 */ "fmul8x16al \000" |
| 173 | /* 1372 */ "camellia_fl \000" |
| 174 | /* 1385 */ "call \000" |
| 175 | /* 1391 */ "sll \000" |
| 176 | /* 1396 */ "jmpl \000" |
| 177 | /* 1402 */ "alignaddrl \000" |
| 178 | /* 1414 */ "srl \000" |
| 179 | /* 1419 */ "mpmul \000" |
| 180 | /* 1426 */ "smul \000" |
| 181 | /* 1432 */ "montmul \000" |
| 182 | /* 1441 */ "umul \000" |
| 183 | /* 1447 */ "siam \000" |
| 184 | /* 1453 */ "edge32n \000" |
| 185 | /* 1462 */ "edge16n \000" |
| 186 | /* 1471 */ "edge8n \000" |
| 187 | /* 1479 */ "andn \000" |
| 188 | /* 1485 */ "edge32ln \000" |
| 189 | /* 1495 */ "edge16ln \000" |
| 190 | /* 1505 */ "edge8ln \000" |
| 191 | /* 1514 */ "orn \000" |
| 192 | /* 1519 */ "pdistn \000" |
| 193 | /* 1527 */ "fzero \000" |
| 194 | /* 1534 */ "des_ip \000" |
| 195 | /* 1542 */ "des_iip \000" |
| 196 | /* 1551 */ "unimp \000" |
| 197 | /* 1558 */ "jmp \000" |
| 198 | /* 1563 */ "fsubq \000" |
| 199 | /* 1570 */ "faddq \000" |
| 200 | /* 1577 */ "fcmpeq \000" |
| 201 | /* 1585 */ "fnegq \000" |
| 202 | /* 1592 */ "fdmulq \000" |
| 203 | /* 1600 */ "fmulq \000" |
| 204 | /* 1607 */ "fdtoq \000" |
| 205 | /* 1614 */ "fitoq \000" |
| 206 | /* 1621 */ "fstoq \000" |
| 207 | /* 1628 */ "fxtoq \000" |
| 208 | /* 1635 */ "fcmpq \000" |
| 209 | /* 1642 */ "fabsq \000" |
| 210 | /* 1649 */ "fsqrtq \000" |
| 211 | /* 1657 */ "stq \000" |
| 212 | /* 1662 */ "fdivq \000" |
| 213 | /* 1669 */ "fmovq \000" |
| 214 | /* 1676 */ "membar \000" |
| 215 | /* 1684 */ "alignaddr \000" |
| 216 | /* 1695 */ "sir \000" |
| 217 | /* 1700 */ "for \000" |
| 218 | /* 1705 */ "fnor \000" |
| 219 | /* 1711 */ "fxnor \000" |
| 220 | /* 1718 */ "fxor \000" |
| 221 | /* 1724 */ "rdpr \000" |
| 222 | /* 1730 */ "wrpr \000" |
| 223 | /* 1736 */ "montsqr \000" |
| 224 | /* 1745 */ "pwr \000" |
| 225 | /* 1750 */ "fsrc1s \000" |
| 226 | /* 1758 */ "fandnot1s \000" |
| 227 | /* 1769 */ "fnot1s \000" |
| 228 | /* 1777 */ "fornot1s \000" |
| 229 | /* 1787 */ "fpsub32s \000" |
| 230 | /* 1797 */ "fpadd32s \000" |
| 231 | /* 1807 */ "fsrc2s \000" |
| 232 | /* 1815 */ "fandnot2s \000" |
| 233 | /* 1826 */ "fnot2s \000" |
| 234 | /* 1834 */ "fornot2s \000" |
| 235 | /* 1844 */ "fpsub16s \000" |
| 236 | /* 1854 */ "fpadd16s \000" |
| 237 | /* 1864 */ "fsubs \000" |
| 238 | /* 1871 */ "fhsubs \000" |
| 239 | /* 1879 */ "fmsubs \000" |
| 240 | /* 1887 */ "fnmsubs \000" |
| 241 | /* 1896 */ "fadds \000" |
| 242 | /* 1903 */ "fhadds \000" |
| 243 | /* 1911 */ "fnhadds \000" |
| 244 | /* 1920 */ "fmadds \000" |
| 245 | /* 1928 */ "fnmadds \000" |
| 246 | /* 1937 */ "fnadds \000" |
| 247 | /* 1945 */ "fands \000" |
| 248 | /* 1952 */ "fnands \000" |
| 249 | /* 1960 */ "fones \000" |
| 250 | /* 1967 */ "fcmpes \000" |
| 251 | /* 1975 */ "fnegs \000" |
| 252 | /* 1982 */ "fmuls \000" |
| 253 | /* 1989 */ "fnmuls \000" |
| 254 | /* 1997 */ "fzeros \000" |
| 255 | /* 2005 */ "fdtos \000" |
| 256 | /* 2012 */ "fitos \000" |
| 257 | /* 2019 */ "fqtos \000" |
| 258 | /* 2026 */ "movwtos \000" |
| 259 | /* 2035 */ "fxtos \000" |
| 260 | /* 2042 */ "fcmps \000" |
| 261 | /* 2049 */ "flcmps \000" |
| 262 | /* 2057 */ "fors \000" |
| 263 | /* 2063 */ "fnors \000" |
| 264 | /* 2070 */ "fxnors \000" |
| 265 | /* 2078 */ "fxors \000" |
| 266 | /* 2085 */ "fabss \000" |
| 267 | /* 2092 */ "fsqrts \000" |
| 268 | /* 2100 */ "fdivs \000" |
| 269 | /* 2107 */ "fmovs \000" |
| 270 | /* 2114 */ "set \000" |
| 271 | /* 2119 */ "lzcnt \000" |
| 272 | /* 2126 */ "pdist \000" |
| 273 | /* 2133 */ "rett \000" |
| 274 | /* 2139 */ "fmul8x16au \000" |
| 275 | /* 2151 */ "sdiv \000" |
| 276 | /* 2157 */ "udiv \000" |
| 277 | /* 2163 */ "tsubcctv \000" |
| 278 | /* 2173 */ "taddcctv \000" |
| 279 | /* 2183 */ "movstosw \000" |
| 280 | /* 2193 */ "setsw \000" |
| 281 | /* 2200 */ "movstouw \000" |
| 282 | /* 2210 */ "srax \000" |
| 283 | /* 2216 */ "subx \000" |
| 284 | /* 2222 */ "fpmaddx \000" |
| 285 | /* 2231 */ "fpackfix \000" |
| 286 | /* 2241 */ "sllx \000" |
| 287 | /* 2247 */ "srlx \000" |
| 288 | /* 2253 */ "xmulx \000" |
| 289 | /* 2260 */ "fdtox \000" |
| 290 | /* 2267 */ "movdtox \000" |
| 291 | /* 2276 */ "fqtox \000" |
| 292 | /* 2283 */ "fstox \000" |
| 293 | /* 2290 */ "setx \000" |
| 294 | /* 2296 */ "stx \000" |
| 295 | /* 2301 */ "sdivx \000" |
| 296 | /* 2308 */ "udivx \000" |
| 297 | /* 2315 */ "; SELECT_CC_DFP_FCC PSEUDO!\000" |
| 298 | /* 2343 */ "; SELECT_CC_QFP_FCC PSEUDO!\000" |
| 299 | /* 2371 */ "; SELECT_CC_FP_FCC PSEUDO!\000" |
| 300 | /* 2398 */ "; SELECT_CC_Int_FCC PSEUDO!\000" |
| 301 | /* 2426 */ "; SELECT_CC_DFP_ICC PSEUDO!\000" |
| 302 | /* 2454 */ "; SELECT_CC_QFP_ICC PSEUDO!\000" |
| 303 | /* 2482 */ "; SELECT_CC_FP_ICC PSEUDO!\000" |
| 304 | /* 2509 */ "; SELECT_CC_Int_ICC PSEUDO!\000" |
| 305 | /* 2537 */ "; SELECT_CC_DFP_XCC PSEUDO!\000" |
| 306 | /* 2565 */ "; SELECT_CC_QFP_XCC PSEUDO!\000" |
| 307 | /* 2593 */ "; SELECT_CC_FP_XCC PSEUDO!\000" |
| 308 | /* 2620 */ "; SELECT_CC_Int_XCC PSEUDO!\000" |
| 309 | /* 2648 */ "jmp %i7+\000" |
| 310 | /* 2657 */ "jmp %o7+\000" |
| 311 | /* 2666 */ "# XRay Function Patchable RET.\000" |
| 312 | /* 2697 */ "# XRay Typed Event Log.\000" |
| 313 | /* 2721 */ "# XRay Custom Event Log.\000" |
| 314 | /* 2746 */ "# XRay Function Enter.\000" |
| 315 | /* 2769 */ "# XRay Tail Call Exit.\000" |
| 316 | /* 2792 */ "# XRay Function Exit.\000" |
| 317 | /* 2814 */ "flush %g0\000" |
| 318 | /* 2824 */ "ta 1\000" |
| 319 | /* 2829 */ "sha1\000" |
| 320 | /* 2834 */ "sha512\000" |
| 321 | /* 2841 */ "ta 3\000" |
| 322 | /* 2846 */ "ta 5\000" |
| 323 | /* 2851 */ "md5\000" |
| 324 | /* 2855 */ "sha256\000" |
| 325 | /* 2862 */ "LIFETIME_END\000" |
| 326 | /* 2875 */ "PSEUDO_PROBE\000" |
| 327 | /* 2888 */ "BUNDLE\000" |
| 328 | /* 2895 */ "FAKE_USE\000" |
| 329 | /* 2904 */ "DBG_VALUE\000" |
| 330 | /* 2914 */ "DBG_INSTR_REF\000" |
| 331 | /* 2928 */ "DBG_PHI\000" |
| 332 | /* 2936 */ "DBG_LABEL\000" |
| 333 | /* 2946 */ "!V8BAR\000" |
| 334 | /* 2953 */ "LIFETIME_START\000" |
| 335 | /* 2968 */ "DBG_VALUE_LIST\000" |
| 336 | /* 2983 */ "std %cq, [\000" |
| 337 | /* 2994 */ "std %fq, [\000" |
| 338 | /* 3005 */ "st %csr, [\000" |
| 339 | /* 3016 */ "st %fsr, [\000" |
| 340 | /* 3027 */ "stx %fsr, [\000" |
| 341 | /* 3039 */ "ldsba [\000" |
| 342 | /* 3047 */ "lduba [\000" |
| 343 | /* 3055 */ "ldstuba [\000" |
| 344 | /* 3065 */ "ldda [\000" |
| 345 | /* 3072 */ "lda [\000" |
| 346 | /* 3078 */ "prefetcha [\000" |
| 347 | /* 3090 */ "ldsha [\000" |
| 348 | /* 3098 */ "lduha [\000" |
| 349 | /* 3106 */ "swapa [\000" |
| 350 | /* 3114 */ "ldqa [\000" |
| 351 | /* 3121 */ "casa [\000" |
| 352 | /* 3128 */ "ldswa [\000" |
| 353 | /* 3136 */ "ldxa [\000" |
| 354 | /* 3143 */ "casxa [\000" |
| 355 | /* 3151 */ "ldsb [\000" |
| 356 | /* 3158 */ "ldub [\000" |
| 357 | /* 3165 */ "ldstub [\000" |
| 358 | /* 3174 */ "ldd [\000" |
| 359 | /* 3180 */ "ld [\000" |
| 360 | /* 3185 */ "prefetch [\000" |
| 361 | /* 3196 */ "ldsh [\000" |
| 362 | /* 3203 */ "lduh [\000" |
| 363 | /* 3210 */ "swap [\000" |
| 364 | /* 3217 */ "ldq [\000" |
| 365 | /* 3223 */ "ldsw [\000" |
| 366 | /* 3230 */ "ldx [\000" |
| 367 | /* 3236 */ "cb\000" |
| 368 | /* 3239 */ "fb\000" |
| 369 | /* 3242 */ "cwb\000" |
| 370 | /* 3246 */ "cxb\000" |
| 371 | /* 3250 */ "restored\000" |
| 372 | /* 3259 */ "saved\000" |
| 373 | /* 3265 */ "fmovrd\000" |
| 374 | /* 3272 */ "fmovd\000" |
| 375 | /* 3278 */ "done\000" |
| 376 | /* 3283 */ "# FEntry call\000" |
| 377 | /* 3297 */ "allclean\000" |
| 378 | /* 3306 */ "shutdown\000" |
| 379 | /* 3315 */ "nop\000" |
| 380 | /* 3319 */ "fmovrq\000" |
| 381 | /* 3326 */ "fmovq\000" |
| 382 | /* 3332 */ "stbar\000" |
| 383 | /* 3338 */ "br\000" |
| 384 | /* 3341 */ "movr\000" |
| 385 | /* 3346 */ "fmovrs\000" |
| 386 | /* 3353 */ "fmovs\000" |
| 387 | /* 3359 */ "t\000" |
| 388 | /* 3361 */ "mov\000" |
| 389 | /* 3365 */ "flushw\000" |
| 390 | /* 3372 */ "normalw\000" |
| 391 | /* 3380 */ "invalw\000" |
| 392 | /* 3387 */ "otherw\000" |
| 393 | /* 3394 */ "retry\000" |
| 394 | }; |
| 395 | #ifdef __GNUC__ |
| 396 | #pragma GCC diagnostic pop |
| 397 | #endif |
| 398 | |
| 399 | static const uint32_t OpInfo0[] = { |
| 400 | 0U, // PHI |
| 401 | 0U, // INLINEASM |
| 402 | 0U, // INLINEASM_BR |
| 403 | 0U, // CFI_INSTRUCTION |
| 404 | 0U, // EH_LABEL |
| 405 | 0U, // GC_LABEL |
| 406 | 0U, // ANNOTATION_LABEL |
| 407 | 0U, // KILL |
| 408 | 0U, // EXTRACT_SUBREG |
| 409 | 0U, // INSERT_SUBREG |
| 410 | 0U, // IMPLICIT_DEF |
| 411 | 0U, // INIT_UNDEF |
| 412 | 0U, // SUBREG_TO_REG |
| 413 | 0U, // COPY_TO_REGCLASS |
| 414 | 2905U, // DBG_VALUE |
| 415 | 2969U, // DBG_VALUE_LIST |
| 416 | 2915U, // DBG_INSTR_REF |
| 417 | 2929U, // DBG_PHI |
| 418 | 2937U, // DBG_LABEL |
| 419 | 0U, // REG_SEQUENCE |
| 420 | 0U, // COPY |
| 421 | 0U, // COPY_LANEMASK |
| 422 | 2889U, // BUNDLE |
| 423 | 2954U, // LIFETIME_START |
| 424 | 2863U, // LIFETIME_END |
| 425 | 2876U, // PSEUDO_PROBE |
| 426 | 0U, // ARITH_FENCE |
| 427 | 0U, // STACKMAP |
| 428 | 3284U, // FENTRY_CALL |
| 429 | 0U, // PATCHPOINT |
| 430 | 0U, // LOAD_STACK_GUARD |
| 431 | 0U, // PREALLOCATED_SETUP |
| 432 | 0U, // PREALLOCATED_ARG |
| 433 | 0U, // STATEPOINT |
| 434 | 0U, // LOCAL_ESCAPE |
| 435 | 0U, // FAULTING_OP |
| 436 | 0U, // PATCHABLE_OP |
| 437 | 2747U, // PATCHABLE_FUNCTION_ENTER |
| 438 | 2667U, // PATCHABLE_RET |
| 439 | 2793U, // PATCHABLE_FUNCTION_EXIT |
| 440 | 2770U, // PATCHABLE_TAIL_CALL |
| 441 | 2722U, // PATCHABLE_EVENT_CALL |
| 442 | 2698U, // PATCHABLE_TYPED_EVENT_CALL |
| 443 | 0U, // ICALL_BRANCH_FUNNEL |
| 444 | 2896U, // FAKE_USE |
| 445 | 0U, // MEMBARRIER |
| 446 | 0U, // JUMP_TABLE_DEBUG_INFO |
| 447 | 0U, // RELOC_NONE |
| 448 | 0U, // CONVERGENCECTRL_ENTRY |
| 449 | 0U, // CONVERGENCECTRL_ANCHOR |
| 450 | 0U, // CONVERGENCECTRL_LOOP |
| 451 | 0U, // CONVERGENCECTRL_GLUE |
| 452 | 0U, // G_ASSERT_SEXT |
| 453 | 0U, // G_ASSERT_ZEXT |
| 454 | 0U, // G_ASSERT_ALIGN |
| 455 | 0U, // G_ADD |
| 456 | 0U, // G_SUB |
| 457 | 0U, // G_MUL |
| 458 | 0U, // G_SDIV |
| 459 | 0U, // G_UDIV |
| 460 | 0U, // G_SREM |
| 461 | 0U, // G_UREM |
| 462 | 0U, // G_SDIVREM |
| 463 | 0U, // G_UDIVREM |
| 464 | 0U, // G_AND |
| 465 | 0U, // G_OR |
| 466 | 0U, // G_XOR |
| 467 | 0U, // G_ABDS |
| 468 | 0U, // G_ABDU |
| 469 | 0U, // G_UAVGFLOOR |
| 470 | 0U, // G_UAVGCEIL |
| 471 | 0U, // G_SAVGFLOOR |
| 472 | 0U, // G_SAVGCEIL |
| 473 | 0U, // G_IMPLICIT_DEF |
| 474 | 0U, // G_PHI |
| 475 | 0U, // G_FRAME_INDEX |
| 476 | 0U, // G_GLOBAL_VALUE |
| 477 | 0U, // G_PTRAUTH_GLOBAL_VALUE |
| 478 | 0U, // G_CONSTANT_POOL |
| 479 | 0U, // G_EXTRACT |
| 480 | 0U, // G_UNMERGE_VALUES |
| 481 | 0U, // G_INSERT |
| 482 | 0U, // G_MERGE_VALUES |
| 483 | 0U, // G_BUILD_VECTOR |
| 484 | 0U, // G_BUILD_VECTOR_TRUNC |
| 485 | 0U, // G_CONCAT_VECTORS |
| 486 | 0U, // G_PTRTOINT |
| 487 | 0U, // G_INTTOPTR |
| 488 | 0U, // G_BITCAST |
| 489 | 0U, // G_FREEZE |
| 490 | 0U, // G_CONSTANT_FOLD_BARRIER |
| 491 | 0U, // G_INTRINSIC_FPTRUNC_ROUND |
| 492 | 0U, // G_INTRINSIC_TRUNC |
| 493 | 0U, // G_INTRINSIC_ROUND |
| 494 | 0U, // G_INTRINSIC_LRINT |
| 495 | 0U, // G_INTRINSIC_LLRINT |
| 496 | 0U, // G_INTRINSIC_ROUNDEVEN |
| 497 | 0U, // G_READCYCLECOUNTER |
| 498 | 0U, // G_READSTEADYCOUNTER |
| 499 | 0U, // G_LOAD |
| 500 | 0U, // G_SEXTLOAD |
| 501 | 0U, // G_ZEXTLOAD |
| 502 | 0U, // G_INDEXED_LOAD |
| 503 | 0U, // G_INDEXED_SEXTLOAD |
| 504 | 0U, // G_INDEXED_ZEXTLOAD |
| 505 | 0U, // G_STORE |
| 506 | 0U, // G_INDEXED_STORE |
| 507 | 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 508 | 0U, // G_ATOMIC_CMPXCHG |
| 509 | 0U, // G_ATOMICRMW_XCHG |
| 510 | 0U, // G_ATOMICRMW_ADD |
| 511 | 0U, // G_ATOMICRMW_SUB |
| 512 | 0U, // G_ATOMICRMW_AND |
| 513 | 0U, // G_ATOMICRMW_NAND |
| 514 | 0U, // G_ATOMICRMW_OR |
| 515 | 0U, // G_ATOMICRMW_XOR |
| 516 | 0U, // G_ATOMICRMW_MAX |
| 517 | 0U, // G_ATOMICRMW_MIN |
| 518 | 0U, // G_ATOMICRMW_UMAX |
| 519 | 0U, // G_ATOMICRMW_UMIN |
| 520 | 0U, // G_ATOMICRMW_FADD |
| 521 | 0U, // G_ATOMICRMW_FSUB |
| 522 | 0U, // G_ATOMICRMW_FMAX |
| 523 | 0U, // G_ATOMICRMW_FMIN |
| 524 | 0U, // G_ATOMICRMW_FMAXIMUM |
| 525 | 0U, // G_ATOMICRMW_FMINIMUM |
| 526 | 0U, // G_ATOMICRMW_FMAXIMUMNUM |
| 527 | 0U, // G_ATOMICRMW_FMINIMUMNUM |
| 528 | 0U, // G_ATOMICRMW_UINC_WRAP |
| 529 | 0U, // G_ATOMICRMW_UDEC_WRAP |
| 530 | 0U, // G_ATOMICRMW_USUB_COND |
| 531 | 0U, // G_ATOMICRMW_USUB_SAT |
| 532 | 0U, // G_FENCE |
| 533 | 0U, // G_PREFETCH |
| 534 | 0U, // G_BRCOND |
| 535 | 0U, // G_BRINDIRECT |
| 536 | 0U, // G_INVOKE_REGION_START |
| 537 | 0U, // G_INTRINSIC |
| 538 | 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 539 | 0U, // G_INTRINSIC_CONVERGENT |
| 540 | 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
| 541 | 0U, // G_ANYEXT |
| 542 | 0U, // G_TRUNC |
| 543 | 0U, // G_TRUNC_SSAT_S |
| 544 | 0U, // G_TRUNC_SSAT_U |
| 545 | 0U, // G_TRUNC_USAT_U |
| 546 | 0U, // G_CONSTANT |
| 547 | 0U, // G_FCONSTANT |
| 548 | 0U, // G_VASTART |
| 549 | 0U, // G_VAARG |
| 550 | 0U, // G_SEXT |
| 551 | 0U, // G_SEXT_INREG |
| 552 | 0U, // G_ZEXT |
| 553 | 0U, // G_SHL |
| 554 | 0U, // G_LSHR |
| 555 | 0U, // G_ASHR |
| 556 | 0U, // G_FSHL |
| 557 | 0U, // G_FSHR |
| 558 | 0U, // G_ROTR |
| 559 | 0U, // G_ROTL |
| 560 | 0U, // G_ICMP |
| 561 | 0U, // G_FCMP |
| 562 | 0U, // G_SCMP |
| 563 | 0U, // G_UCMP |
| 564 | 0U, // G_SELECT |
| 565 | 0U, // G_UADDO |
| 566 | 0U, // G_UADDE |
| 567 | 0U, // G_USUBO |
| 568 | 0U, // G_USUBE |
| 569 | 0U, // G_SADDO |
| 570 | 0U, // G_SADDE |
| 571 | 0U, // G_SSUBO |
| 572 | 0U, // G_SSUBE |
| 573 | 0U, // G_UMULO |
| 574 | 0U, // G_SMULO |
| 575 | 0U, // G_UMULH |
| 576 | 0U, // G_SMULH |
| 577 | 0U, // G_UADDSAT |
| 578 | 0U, // G_SADDSAT |
| 579 | 0U, // G_USUBSAT |
| 580 | 0U, // G_SSUBSAT |
| 581 | 0U, // G_USHLSAT |
| 582 | 0U, // G_SSHLSAT |
| 583 | 0U, // G_SMULFIX |
| 584 | 0U, // G_UMULFIX |
| 585 | 0U, // G_SMULFIXSAT |
| 586 | 0U, // G_UMULFIXSAT |
| 587 | 0U, // G_SDIVFIX |
| 588 | 0U, // G_UDIVFIX |
| 589 | 0U, // G_SDIVFIXSAT |
| 590 | 0U, // G_UDIVFIXSAT |
| 591 | 0U, // G_FADD |
| 592 | 0U, // G_FSUB |
| 593 | 0U, // G_FMUL |
| 594 | 0U, // G_FMA |
| 595 | 0U, // G_FMAD |
| 596 | 0U, // G_FDIV |
| 597 | 0U, // G_FREM |
| 598 | 0U, // G_FMODF |
| 599 | 0U, // G_FPOW |
| 600 | 0U, // G_FPOWI |
| 601 | 0U, // G_FEXP |
| 602 | 0U, // G_FEXP2 |
| 603 | 0U, // G_FEXP10 |
| 604 | 0U, // G_FLOG |
| 605 | 0U, // G_FLOG2 |
| 606 | 0U, // G_FLOG10 |
| 607 | 0U, // G_FLDEXP |
| 608 | 0U, // G_FFREXP |
| 609 | 0U, // G_FNEG |
| 610 | 0U, // G_FPEXT |
| 611 | 0U, // G_FPTRUNC |
| 612 | 0U, // G_FPTOSI |
| 613 | 0U, // G_FPTOUI |
| 614 | 0U, // G_SITOFP |
| 615 | 0U, // G_UITOFP |
| 616 | 0U, // G_FPTOSI_SAT |
| 617 | 0U, // G_FPTOUI_SAT |
| 618 | 0U, // G_FABS |
| 619 | 0U, // G_FCOPYSIGN |
| 620 | 0U, // G_IS_FPCLASS |
| 621 | 0U, // G_FCANONICALIZE |
| 622 | 0U, // G_FMINNUM |
| 623 | 0U, // G_FMAXNUM |
| 624 | 0U, // G_FMINNUM_IEEE |
| 625 | 0U, // G_FMAXNUM_IEEE |
| 626 | 0U, // G_FMINIMUM |
| 627 | 0U, // G_FMAXIMUM |
| 628 | 0U, // G_FMINIMUMNUM |
| 629 | 0U, // G_FMAXIMUMNUM |
| 630 | 0U, // G_GET_FPENV |
| 631 | 0U, // G_SET_FPENV |
| 632 | 0U, // G_RESET_FPENV |
| 633 | 0U, // G_GET_FPMODE |
| 634 | 0U, // G_SET_FPMODE |
| 635 | 0U, // G_RESET_FPMODE |
| 636 | 0U, // G_GET_ROUNDING |
| 637 | 0U, // G_SET_ROUNDING |
| 638 | 0U, // G_PTR_ADD |
| 639 | 0U, // G_PTRMASK |
| 640 | 0U, // G_SMIN |
| 641 | 0U, // G_SMAX |
| 642 | 0U, // G_UMIN |
| 643 | 0U, // G_UMAX |
| 644 | 0U, // G_ABS |
| 645 | 0U, // G_LROUND |
| 646 | 0U, // G_LLROUND |
| 647 | 0U, // G_BR |
| 648 | 0U, // G_BRJT |
| 649 | 0U, // G_VSCALE |
| 650 | 0U, // G_INSERT_SUBVECTOR |
| 651 | 0U, // G_EXTRACT_SUBVECTOR |
| 652 | 0U, // G_INSERT_VECTOR_ELT |
| 653 | 0U, // G_EXTRACT_VECTOR_ELT |
| 654 | 0U, // G_SHUFFLE_VECTOR |
| 655 | 0U, // G_SPLAT_VECTOR |
| 656 | 0U, // G_STEP_VECTOR |
| 657 | 0U, // G_VECTOR_COMPRESS |
| 658 | 0U, // G_CTTZ |
| 659 | 0U, // G_CTTZ_ZERO_UNDEF |
| 660 | 0U, // G_CTLZ |
| 661 | 0U, // G_CTLZ_ZERO_UNDEF |
| 662 | 0U, // G_CTLS |
| 663 | 0U, // G_CTPOP |
| 664 | 0U, // G_BSWAP |
| 665 | 0U, // G_BITREVERSE |
| 666 | 0U, // G_FCEIL |
| 667 | 0U, // G_FCOS |
| 668 | 0U, // G_FSIN |
| 669 | 0U, // G_FSINCOS |
| 670 | 0U, // G_FTAN |
| 671 | 0U, // G_FACOS |
| 672 | 0U, // G_FASIN |
| 673 | 0U, // G_FATAN |
| 674 | 0U, // G_FATAN2 |
| 675 | 0U, // G_FCOSH |
| 676 | 0U, // G_FSINH |
| 677 | 0U, // G_FTANH |
| 678 | 0U, // G_FSQRT |
| 679 | 0U, // G_FFLOOR |
| 680 | 0U, // G_FRINT |
| 681 | 0U, // G_FNEARBYINT |
| 682 | 0U, // G_ADDRSPACE_CAST |
| 683 | 0U, // G_BLOCK_ADDR |
| 684 | 0U, // G_JUMP_TABLE |
| 685 | 0U, // G_DYN_STACKALLOC |
| 686 | 0U, // G_STACKSAVE |
| 687 | 0U, // G_STACKRESTORE |
| 688 | 0U, // G_STRICT_FADD |
| 689 | 0U, // G_STRICT_FSUB |
| 690 | 0U, // G_STRICT_FMUL |
| 691 | 0U, // G_STRICT_FDIV |
| 692 | 0U, // G_STRICT_FREM |
| 693 | 0U, // G_STRICT_FMA |
| 694 | 0U, // G_STRICT_FSQRT |
| 695 | 0U, // G_STRICT_FLDEXP |
| 696 | 0U, // G_READ_REGISTER |
| 697 | 0U, // G_WRITE_REGISTER |
| 698 | 0U, // G_MEMCPY |
| 699 | 0U, // G_MEMCPY_INLINE |
| 700 | 0U, // G_MEMMOVE |
| 701 | 0U, // G_MEMSET |
| 702 | 0U, // G_BZERO |
| 703 | 0U, // G_TRAP |
| 704 | 0U, // G_DEBUGTRAP |
| 705 | 0U, // G_UBSANTRAP |
| 706 | 0U, // G_VECREDUCE_SEQ_FADD |
| 707 | 0U, // G_VECREDUCE_SEQ_FMUL |
| 708 | 0U, // G_VECREDUCE_FADD |
| 709 | 0U, // G_VECREDUCE_FMUL |
| 710 | 0U, // G_VECREDUCE_FMAX |
| 711 | 0U, // G_VECREDUCE_FMIN |
| 712 | 0U, // G_VECREDUCE_FMAXIMUM |
| 713 | 0U, // G_VECREDUCE_FMINIMUM |
| 714 | 0U, // G_VECREDUCE_ADD |
| 715 | 0U, // G_VECREDUCE_MUL |
| 716 | 0U, // G_VECREDUCE_AND |
| 717 | 0U, // G_VECREDUCE_OR |
| 718 | 0U, // G_VECREDUCE_XOR |
| 719 | 0U, // G_VECREDUCE_SMAX |
| 720 | 0U, // G_VECREDUCE_SMIN |
| 721 | 0U, // G_VECREDUCE_UMAX |
| 722 | 0U, // G_VECREDUCE_UMIN |
| 723 | 0U, // G_SBFX |
| 724 | 0U, // G_UBFX |
| 725 | 4707U, // ADJCALLSTACKDOWN |
| 726 | 70262U, // ADJCALLSTACKUP |
| 727 | 8206U, // GETPCX |
| 728 | 2316U, // SELECT_CC_DFP_FCC |
| 729 | 2427U, // SELECT_CC_DFP_ICC |
| 730 | 2538U, // SELECT_CC_DFP_XCC |
| 731 | 2372U, // SELECT_CC_FP_FCC |
| 732 | 2483U, // SELECT_CC_FP_ICC |
| 733 | 2594U, // SELECT_CC_FP_XCC |
| 734 | 2399U, // SELECT_CC_Int_FCC |
| 735 | 2510U, // SELECT_CC_Int_ICC |
| 736 | 2621U, // SELECT_CC_Int_XCC |
| 737 | 2344U, // SELECT_CC_QFP_FCC |
| 738 | 2455U, // SELECT_CC_QFP_ICC |
| 739 | 2566U, // SELECT_CC_QFP_XCC |
| 740 | 2111555U, // SET |
| 741 | 2111634U, // SETSW |
| 742 | 20986099U, // SETX |
| 743 | 2947U, // V8BAR |
| 744 | 20984555U, // ADDCCri |
| 745 | 20984555U, // ADDCCrr |
| 746 | 20986034U, // ADDCri |
| 747 | 20986034U, // ADDCrr |
| 748 | 20984647U, // ADDEri |
| 749 | 20984647U, // ADDErr |
| 750 | 20984661U, // ADDXC |
| 751 | 20984545U, // ADDXCCC |
| 752 | 20984700U, // ADDri |
| 753 | 20984700U, // ADDrr |
| 754 | 692072546U, // AES_DROUND01 |
| 755 | 692073745U, // AES_DROUND01_LAST |
| 756 | 692072794U, // AES_DROUND23 |
| 757 | 692073777U, // AES_DROUND23_LAST |
| 758 | 692072560U, // AES_EROUND01 |
| 759 | 692073761U, // AES_EROUND01_LAST |
| 760 | 692072808U, // AES_EROUND23 |
| 761 | 692073793U, // AES_EROUND23_LAST |
| 762 | 20983892U, // AES_KEXPAND0 |
| 763 | 692072581U, // AES_KEXPAND1 |
| 764 | 20984114U, // AES_KEXPAND2 |
| 765 | 20985493U, // ALIGNADDR |
| 766 | 20985211U, // ALIGNADDRL |
| 767 | 3298U, // ALLCLEAN |
| 768 | 20984562U, // ANDCCri |
| 769 | 20984562U, // ANDCCrr |
| 770 | 20984585U, // ANDNCCri |
| 771 | 20984585U, // ANDNCCrr |
| 772 | 20985288U, // ANDNri |
| 773 | 20985288U, // ANDNrr |
| 774 | 20984802U, // ANDri |
| 775 | 20984802U, // ANDrr |
| 776 | 20984387U, // ARRAY16 |
| 777 | 20984098U, // ARRAY32 |
| 778 | 20984411U, // ARRAY8 |
| 779 | 82569U, // BA |
| 780 | 6446246U, // BCOND |
| 781 | 6511782U, // BCONDA |
| 782 | 91671U, // BINDri |
| 783 | 91671U, // BINDrr |
| 784 | 20985072U, // BMASK |
| 785 | 289561768U, // BPFCC |
| 786 | 289627304U, // BPFCCA |
| 787 | 285864U, // BPFCCANT |
| 788 | 351400U, // BPFCCNT |
| 789 | 6708390U, // BPICC |
| 790 | 482470U, // BPICCA |
| 791 | 548006U, // BPICCANT |
| 792 | 613542U, // BPICCNT |
| 793 | 289561867U, // BPR |
| 794 | 289627403U, // BPRA |
| 795 | 285963U, // BPRANT |
| 796 | 351499U, // BPRNT |
| 797 | 6970534U, // BPXCC |
| 798 | 744614U, // BPXCCA |
| 799 | 810150U, // BPXCCANT |
| 800 | 875686U, // BPXCCNT |
| 801 | 20984946U, // BSHUFFLE |
| 802 | 83306U, // CALL |
| 803 | 17770U, // CALLi |
| 804 | 91498U, // CALLri |
| 805 | 4220266U, // CALLrii |
| 806 | 91498U, // CALLrr |
| 807 | 4220266U, // CALLrri |
| 808 | 692073617U, // CAMELLIA_F |
| 809 | 20985181U, // CAMELLIA_FL |
| 810 | 20985037U, // CAMELLIA_FLI |
| 811 | 21904434U, // CASAri |
| 812 | 9387058U, // CASArr |
| 813 | 21904456U, // CASXAri |
| 814 | 9387080U, // CASXArr |
| 815 | 70078U, // CMASK16 |
| 816 | 69868U, // CMASK32 |
| 817 | 70227U, // CMASK8 |
| 818 | 6446245U, // CPBCOND |
| 819 | 6511781U, // CPBCONDA |
| 820 | 20984517U, // CRC32C |
| 821 | 1765956779U, // CWBCONDri |
| 822 | 1765956779U, // CWBCONDrr |
| 823 | 1765956783U, // CXBCONDri |
| 824 | 1765956783U, // CXBCONDrr |
| 825 | 2110983U, // DES_IIP |
| 826 | 2110975U, // DES_IP |
| 827 | 20984823U, // DES_KEXPAND |
| 828 | 692073476U, // DES_ROUND |
| 829 | 3279U, // DONE |
| 830 | 20984217U, // EDGE16 |
| 831 | 20985088U, // EDGE16L |
| 832 | 20985304U, // EDGE16LN |
| 833 | 20985271U, // EDGE16N |
| 834 | 20984007U, // EDGE32 |
| 835 | 20985079U, // EDGE32L |
| 836 | 20985294U, // EDGE32LN |
| 837 | 20985262U, // EDGE32N |
| 838 | 20984396U, // EDGE8 |
| 839 | 20985097U, // EDGE8L |
| 840 | 20985314U, // EDGE8LN |
| 841 | 20985280U, // EDGE8N |
| 842 | 2110535U, // FABSD |
| 843 | 2111083U, // FABSQ |
| 844 | 2111526U, // FABSS |
| 845 | 20984705U, // FADDD |
| 846 | 20985379U, // FADDQ |
| 847 | 20985705U, // FADDS |
| 848 | 20984484U, // FALIGNADATA |
| 849 | 20984801U, // FAND |
| 850 | 20983955U, // FANDNOT1 |
| 851 | 20985567U, // FANDNOT1S |
| 852 | 20984128U, // FANDNOT2 |
| 853 | 20985624U, // FANDNOT2S |
| 854 | 20985754U, // FANDS |
| 855 | 6446248U, // FBCOND |
| 856 | 6511784U, // FBCONDA |
| 857 | 1072296U, // FBCONDA_V9 |
| 858 | 7429288U, // FBCOND_V9 |
| 859 | 20984279U, // FCHKSM16 |
| 860 | 5172U, // FCMPD |
| 861 | 4097U, // FCMPD_V9 |
| 862 | 20984298U, // FCMPEQ16 |
| 863 | 20984069U, // FCMPEQ32 |
| 864 | 20984317U, // FCMPGT16 |
| 865 | 20984088U, // FCMPGT32 |
| 866 | 20984225U, // FCMPLE16 |
| 867 | 20984015U, // FCMPLE32 |
| 868 | 20984235U, // FCMPNE16 |
| 869 | 20984025U, // FCMPNE32 |
| 870 | 5732U, // FCMPQ |
| 871 | 4111U, // FCMPQ_V9 |
| 872 | 6139U, // FCMPS |
| 873 | 4125U, // FCMPS_V9 |
| 874 | 20984923U, // FDIVD |
| 875 | 20985471U, // FDIVQ |
| 876 | 20985909U, // FDIVS |
| 877 | 20985401U, // FDMULQ |
| 878 | 2110683U, // FDTOI |
| 879 | 2111048U, // FDTOQ |
| 880 | 2111446U, // FDTOS |
| 881 | 2111701U, // FDTOX |
| 882 | 2110446U, // FEXPAND |
| 883 | 20984712U, // FHADDD |
| 884 | 20985712U, // FHADDS |
| 885 | 20984675U, // FHSUBD |
| 886 | 20985680U, // FHSUBS |
| 887 | 2110479U, // FITOD |
| 888 | 2111055U, // FITOQ |
| 889 | 2111453U, // FITOS |
| 890 | 419435579U, // FLCMPD |
| 891 | 419436546U, // FLCMPS |
| 892 | 2815U, // FLUSH |
| 893 | 3366U, // FLUSHW |
| 894 | 91293U, // FLUSHri |
| 895 | 91293U, // FLUSHrr |
| 896 | 692073369U, // FMADDD |
| 897 | 692074369U, // FMADDS |
| 898 | 20984289U, // FMEAN16 |
| 899 | 2110562U, // FMOVD |
| 900 | 17923273U, // FMOVD_FCC |
| 901 | 17202377U, // FMOVD_ICC |
| 902 | 17464521U, // FMOVD_XCC |
| 903 | 2111110U, // FMOVQ |
| 904 | 17923327U, // FMOVQ_FCC |
| 905 | 17202431U, // FMOVQ_ICC |
| 906 | 17464575U, // FMOVQ_XCC |
| 907 | 36034U, // FMOVRD |
| 908 | 36088U, // FMOVRQ |
| 909 | 36115U, // FMOVRS |
| 910 | 2111548U, // FMOVS |
| 911 | 17923354U, // FMOVS_FCC |
| 912 | 17202458U, // FMOVS_ICC |
| 913 | 17464602U, // FMOVS_XCC |
| 914 | 692073323U, // FMSUBD |
| 915 | 692074328U, // FMSUBS |
| 916 | 20984375U, // FMUL8SUX16 |
| 917 | 20984350U, // FMUL8ULX16 |
| 918 | 20984327U, // FMUL8X16 |
| 919 | 20985169U, // FMUL8X16AL |
| 920 | 20985948U, // FMUL8X16AU |
| 921 | 20984769U, // FMULD |
| 922 | 20984362U, // FMULD8SUX16 |
| 923 | 20984337U, // FMULD8ULX16 |
| 924 | 20985409U, // FMULQ |
| 925 | 20985791U, // FMULS |
| 926 | 20984746U, // FNADDD |
| 927 | 20985746U, // FNADDS |
| 928 | 20984807U, // FNAND |
| 929 | 20985761U, // FNANDS |
| 930 | 2110394U, // FNEGD |
| 931 | 2111026U, // FNEGQ |
| 932 | 2111416U, // FNEGS |
| 933 | 20984720U, // FNHADDD |
| 934 | 20985720U, // FNHADDS |
| 935 | 692073377U, // FNMADDD |
| 936 | 692074377U, // FNMADDS |
| 937 | 692073331U, // FNMSUBD |
| 938 | 692074336U, // FNMSUBS |
| 939 | 20984776U, // FNMULD |
| 940 | 20985798U, // FNMULS |
| 941 | 20985514U, // FNOR |
| 942 | 20985872U, // FNORS |
| 943 | 2109597U, // FNOT1 |
| 944 | 2111210U, // FNOT1S |
| 945 | 2109770U, // FNOT2 |
| 946 | 2111267U, // FNOT2S |
| 947 | 20984792U, // FNSMULD |
| 948 | 70780U, // FONE |
| 949 | 71593U, // FONES |
| 950 | 20985509U, // FOR |
| 951 | 20983972U, // FORNOT1 |
| 952 | 20985586U, // FORNOT1S |
| 953 | 20984145U, // FORNOT2 |
| 954 | 20985643U, // FORNOT2S |
| 955 | 20985866U, // FORS |
| 956 | 2109877U, // FPACK16 |
| 957 | 20984035U, // FPACK32 |
| 958 | 2111672U, // FPACKFIX |
| 959 | 20984208U, // FPADD16 |
| 960 | 20985663U, // FPADD16S |
| 961 | 20983998U, // FPADD32 |
| 962 | 20985606U, // FPADD32S |
| 963 | 20984182U, // FPADD64 |
| 964 | 692074671U, // FPMADDX |
| 965 | 692073648U, // FPMADDXHI |
| 966 | 20984937U, // FPMERGE |
| 967 | 20984199U, // FPSUB16 |
| 968 | 20985653U, // FPSUB16S |
| 969 | 20983989U, // FPSUB32 |
| 970 | 20985596U, // FPSUB32S |
| 971 | 2110486U, // FQTOD |
| 972 | 2110690U, // FQTOI |
| 973 | 2111460U, // FQTOS |
| 974 | 2111717U, // FQTOX |
| 975 | 20984308U, // FSLAS16 |
| 976 | 20984079U, // FSLAS32 |
| 977 | 20984263U, // FSLL16 |
| 978 | 20984053U, // FSLL32 |
| 979 | 20984784U, // FSMULD |
| 980 | 2110542U, // FSQRTD |
| 981 | 2111090U, // FSQRTQ |
| 982 | 2111533U, // FSQRTS |
| 983 | 20984191U, // FSRA16 |
| 984 | 20983981U, // FSRA32 |
| 985 | 2109566U, // FSRC1 |
| 986 | 2111191U, // FSRC1S |
| 987 | 2109739U, // FSRC2 |
| 988 | 2111248U, // FSRC2S |
| 989 | 20984271U, // FSRL16 |
| 990 | 20984061U, // FSRL32 |
| 991 | 2110493U, // FSTOD |
| 992 | 2110697U, // FSTOI |
| 993 | 2111062U, // FSTOQ |
| 994 | 2111724U, // FSTOX |
| 995 | 20984668U, // FSUBD |
| 996 | 20985372U, // FSUBQ |
| 997 | 20985673U, // FSUBS |
| 998 | 20985520U, // FXNOR |
| 999 | 20985879U, // FXNORS |
| 1000 | 20985527U, // FXOR |
| 1001 | 20985887U, // FXORS |
| 1002 | 2110500U, // FXTOD |
| 1003 | 2111069U, // FXTOQ |
| 1004 | 2111476U, // FXTOS |
| 1005 | 71160U, // FZERO |
| 1006 | 71630U, // FZEROS |
| 1007 | 154311839U, // GDOP_LDXrr |
| 1008 | 154311789U, // GDOP_LDrr |
| 1009 | 3381U, // INVALW |
| 1010 | 2135413U, // JMPLri |
| 1011 | 2135413U, // JMPLrr |
| 1012 | 3054593U, // LDAri |
| 1013 | 28285953U, // LDArr |
| 1014 | 1272941U, // LDCSRri |
| 1015 | 1272941U, // LDCSRrr |
| 1016 | 3316845U, // LDCri |
| 1017 | 3316845U, // LDCrr |
| 1018 | 3054586U, // LDDAri |
| 1019 | 28285946U, // LDDArr |
| 1020 | 3316839U, // LDDCri |
| 1021 | 3316839U, // LDDCrr |
| 1022 | 3054586U, // LDDFAri |
| 1023 | 28285946U, // LDDFArr |
| 1024 | 3316839U, // LDDFri |
| 1025 | 3316839U, // LDDFrr |
| 1026 | 3316839U, // LDDri |
| 1027 | 3316839U, // LDDrr |
| 1028 | 3054593U, // LDFAri |
| 1029 | 28285953U, // LDFArr |
| 1030 | 1338477U, // LDFSRri |
| 1031 | 1338477U, // LDFSRrr |
| 1032 | 3316845U, // LDFri |
| 1033 | 3316845U, // LDFrr |
| 1034 | 3054635U, // LDQFAri |
| 1035 | 28285995U, // LDQFArr |
| 1036 | 3316882U, // LDQFri |
| 1037 | 3316882U, // LDQFrr |
| 1038 | 3054560U, // LDSBAri |
| 1039 | 28285920U, // LDSBArr |
| 1040 | 3316816U, // LDSBri |
| 1041 | 3316816U, // LDSBrr |
| 1042 | 3054611U, // LDSHAri |
| 1043 | 28285971U, // LDSHArr |
| 1044 | 3316861U, // LDSHri |
| 1045 | 3316861U, // LDSHrr |
| 1046 | 3054576U, // LDSTUBAri |
| 1047 | 28285936U, // LDSTUBArr |
| 1048 | 3316830U, // LDSTUBri |
| 1049 | 3316830U, // LDSTUBrr |
| 1050 | 3054649U, // LDSWAri |
| 1051 | 28286009U, // LDSWArr |
| 1052 | 3316888U, // LDSWri |
| 1053 | 3316888U, // LDSWrr |
| 1054 | 3054568U, // LDUBAri |
| 1055 | 28285928U, // LDUBArr |
| 1056 | 3316823U, // LDUBri |
| 1057 | 3316823U, // LDUBrr |
| 1058 | 3054619U, // LDUHAri |
| 1059 | 28285979U, // LDUHArr |
| 1060 | 3316868U, // LDUHri |
| 1061 | 3316868U, // LDUHrr |
| 1062 | 3054657U, // LDXAri |
| 1063 | 28286017U, // LDXArr |
| 1064 | 1338527U, // LDXFSRri |
| 1065 | 1338527U, // LDXFSRrr |
| 1066 | 3316895U, // LDXri |
| 1067 | 3316895U, // LDXrr |
| 1068 | 3316845U, // LDri |
| 1069 | 3316845U, // LDrr |
| 1070 | 2111560U, // LZCNT |
| 1071 | 2852U, // MD5 |
| 1072 | 42637U, // MEMBARi |
| 1073 | 71065U, // MONTMUL |
| 1074 | 71369U, // MONTSQR |
| 1075 | 2111708U, // MOVDTOX |
| 1076 | 17923362U, // MOVFCCri |
| 1077 | 17923362U, // MOVFCCrr |
| 1078 | 17202466U, // MOVICCri |
| 1079 | 17202466U, // MOVICCrr |
| 1080 | 36110U, // MOVRri |
| 1081 | 36110U, // MOVRrr |
| 1082 | 2111624U, // MOVSTOSW |
| 1083 | 2111641U, // MOVSTOUW |
| 1084 | 2111467U, // MOVWTOS |
| 1085 | 17464610U, // MOVXCCri |
| 1086 | 17464610U, // MOVXCCrr |
| 1087 | 2110507U, // MOVXTOD |
| 1088 | 71052U, // MPMUL |
| 1089 | 20984615U, // MULSCCri |
| 1090 | 20984615U, // MULSCCrr |
| 1091 | 20986063U, // MULXri |
| 1092 | 20986063U, // MULXrr |
| 1093 | 3316U, // NOP |
| 1094 | 3373U, // NORMALW |
| 1095 | 20984602U, // ORCCri |
| 1096 | 20984602U, // ORCCrr |
| 1097 | 20984593U, // ORNCCri |
| 1098 | 20984593U, // ORNCCrr |
| 1099 | 20985323U, // ORNri |
| 1100 | 20985323U, // ORNrr |
| 1101 | 20985510U, // ORri |
| 1102 | 20985510U, // ORrr |
| 1103 | 3388U, // OTHERW |
| 1104 | 20985935U, // PDIST |
| 1105 | 20985328U, // PDISTN |
| 1106 | 2110287U, // POPCrr |
| 1107 | 13528071U, // PREFETCHAi |
| 1108 | 15690759U, // PREFETCHAr |
| 1109 | 13790322U, // PREFETCHi |
| 1110 | 13790322U, // PREFETCHr |
| 1111 | 33560274U, // PWRPSRri |
| 1112 | 33560274U, // PWRPSRrr |
| 1113 | 2110531U, // RDASR |
| 1114 | 69685U, // RDFQ |
| 1115 | 2111165U, // RDPR |
| 1116 | 69706U, // RDPSR |
| 1117 | 69696U, // RDTBR |
| 1118 | 69675U, // RDWIM |
| 1119 | 3251U, // RESTORED |
| 1120 | 20984962U, // RESTOREri |
| 1121 | 20984962U, // RESTORErr |
| 1122 | 72281U, // RET |
| 1123 | 72290U, // RETL |
| 1124 | 3395U, // RETRY |
| 1125 | 92246U, // RETTri |
| 1126 | 92246U, // RETTrr |
| 1127 | 3260U, // SAVED |
| 1128 | 20984971U, // SAVEri |
| 1129 | 20984971U, // SAVErr |
| 1130 | 20984623U, // SDIVCCri |
| 1131 | 20984623U, // SDIVCCrr |
| 1132 | 20986110U, // SDIVXri |
| 1133 | 20986110U, // SDIVXrr |
| 1134 | 20985960U, // SDIVri |
| 1135 | 20985960U, // SDIVrr |
| 1136 | 2110633U, // SETHIi |
| 1137 | 2830U, // SHA1 |
| 1138 | 2856U, // SHA256 |
| 1139 | 2835U, // SHA512 |
| 1140 | 3307U, // SHUTDOWN |
| 1141 | 71080U, // SIAM |
| 1142 | 71328U, // SIR |
| 1143 | 20986050U, // SLLXri |
| 1144 | 20986050U, // SLLXrr |
| 1145 | 20985200U, // SLLri |
| 1146 | 20985200U, // SLLrr |
| 1147 | 20984525U, // SMACri |
| 1148 | 20984525U, // SMACrr |
| 1149 | 20984569U, // SMULCCri |
| 1150 | 20984569U, // SMULCCrr |
| 1151 | 20985235U, // SMULri |
| 1152 | 20985235U, // SMULrr |
| 1153 | 20986019U, // SRAXri |
| 1154 | 20986019U, // SRAXrr |
| 1155 | 20984479U, // SRAri |
| 1156 | 20984479U, // SRArr |
| 1157 | 20986056U, // SRLXri |
| 1158 | 20986056U, // SRLXrr |
| 1159 | 20985223U, // SRLri |
| 1160 | 20985223U, // SRLrr |
| 1161 | 1422000U, // STAri |
| 1162 | 11514544U, // STArr |
| 1163 | 3333U, // STBAR |
| 1164 | 1421959U, // STBAri |
| 1165 | 11514503U, // STBArr |
| 1166 | 1487547U, // STBri |
| 1167 | 1487547U, // STBrr |
| 1168 | 1469374U, // STCSRri |
| 1169 | 1469374U, // STCSRrr |
| 1170 | 1488978U, // STCri |
| 1171 | 1488978U, // STCrr |
| 1172 | 1421965U, // STDAri |
| 1173 | 11514509U, // STDArr |
| 1174 | 1469352U, // STDCQri |
| 1175 | 1469352U, // STDCQrr |
| 1176 | 1487958U, // STDCri |
| 1177 | 1487958U, // STDCrr |
| 1178 | 1421965U, // STDFAri |
| 1179 | 11514509U, // STDFArr |
| 1180 | 1469363U, // STDFQri |
| 1181 | 1469363U, // STDFQrr |
| 1182 | 1487958U, // STDFri |
| 1183 | 1487958U, // STDFrr |
| 1184 | 1487958U, // STDri |
| 1185 | 1487958U, // STDrr |
| 1186 | 1422000U, // STFAri |
| 1187 | 11514544U, // STFArr |
| 1188 | 1469385U, // STFSRri |
| 1189 | 1469385U, // STFSRrr |
| 1190 | 1488978U, // STFri |
| 1191 | 1488978U, // STFrr |
| 1192 | 1421971U, // STHAri |
| 1193 | 11514515U, // STHArr |
| 1194 | 1488036U, // STHri |
| 1195 | 1488036U, // STHrr |
| 1196 | 1421977U, // STQFAri |
| 1197 | 11514521U, // STQFArr |
| 1198 | 1488506U, // STQFri |
| 1199 | 1488506U, // STQFrr |
| 1200 | 1422005U, // STXAri |
| 1201 | 11514549U, // STXArr |
| 1202 | 1469396U, // STXFSRri |
| 1203 | 1469396U, // STXFSRrr |
| 1204 | 1489145U, // STXri |
| 1205 | 1489145U, // STXrr |
| 1206 | 1488978U, // STri |
| 1207 | 1488978U, // STrr |
| 1208 | 20984538U, // SUBCCri |
| 1209 | 20984538U, // SUBCCrr |
| 1210 | 20986025U, // SUBCri |
| 1211 | 20986025U, // SUBCrr |
| 1212 | 20984639U, // SUBEri |
| 1213 | 20984639U, // SUBErr |
| 1214 | 20984512U, // SUBri |
| 1215 | 20984512U, // SUBrr |
| 1216 | 3054627U, // SWAPAri |
| 1217 | 28285987U, // SWAPArr |
| 1218 | 3316875U, // SWAPri |
| 1219 | 3316875U, // SWAPrr |
| 1220 | 2825U, // TA1 |
| 1221 | 2842U, // TA3 |
| 1222 | 2847U, // TA5 |
| 1223 | 20985982U, // TADDCCTVri |
| 1224 | 20985982U, // TADDCCTVrr |
| 1225 | 20984554U, // TADDCCri |
| 1226 | 20984554U, // TADDCCrr |
| 1227 | 83306U, // TAIL_CALL |
| 1228 | 91671U, // TAIL_CALLri |
| 1229 | 52874528U, // TICCri |
| 1230 | 52874528U, // TICCrr |
| 1231 | 2705339260U, // TLS_ADDrr |
| 1232 | 17770U, // TLS_CALL |
| 1233 | 154311839U, // TLS_LDXrr |
| 1234 | 154311789U, // TLS_LDrr |
| 1235 | 52612384U, // TRAPri |
| 1236 | 52612384U, // TRAPrr |
| 1237 | 20985972U, // TSUBCCTVri |
| 1238 | 20985972U, // TSUBCCTVrr |
| 1239 | 20984537U, // TSUBCCri |
| 1240 | 20984537U, // TSUBCCrr |
| 1241 | 53136672U, // TXCCri |
| 1242 | 53136672U, // TXCCrr |
| 1243 | 20984631U, // UDIVCCri |
| 1244 | 20984631U, // UDIVCCrr |
| 1245 | 20986117U, // UDIVXri |
| 1246 | 20986117U, // UDIVXrr |
| 1247 | 20985966U, // UDIVri |
| 1248 | 20985966U, // UDIVrr |
| 1249 | 20984531U, // UMACri |
| 1250 | 20984531U, // UMACrr |
| 1251 | 20984577U, // UMULCCri |
| 1252 | 20984577U, // UMULCCrr |
| 1253 | 20985019U, // UMULXHI |
| 1254 | 20985250U, // UMULri |
| 1255 | 20985250U, // UMULrr |
| 1256 | 71184U, // UNIMP |
| 1257 | 419435572U, // V9FCMPD |
| 1258 | 419435442U, // V9FCMPED |
| 1259 | 419436074U, // V9FCMPEQ |
| 1260 | 419436464U, // V9FCMPES |
| 1261 | 419436132U, // V9FCMPQ |
| 1262 | 419436539U, // V9FCMPS |
| 1263 | 36041U, // V9FMOVD_FCC |
| 1264 | 36095U, // V9FMOVQ_FCC |
| 1265 | 36122U, // V9FMOVS_FCC |
| 1266 | 36130U, // V9MOVFCCri |
| 1267 | 36130U, // V9MOVFCCrr |
| 1268 | 20985555U, // WRASRri |
| 1269 | 20985555U, // WRASRrr |
| 1270 | 20985539U, // WRPRri |
| 1271 | 20985539U, // WRPRrr |
| 1272 | 33560275U, // WRPSRri |
| 1273 | 33560275U, // WRPSRrr |
| 1274 | 67114707U, // WRTBRri |
| 1275 | 67114707U, // WRTBRrr |
| 1276 | 83891923U, // WRWIMri |
| 1277 | 83891923U, // WRWIMrr |
| 1278 | 20986062U, // XMULX |
| 1279 | 20985028U, // XMULXHI |
| 1280 | 20984600U, // XNORCCri |
| 1281 | 20984600U, // XNORCCrr |
| 1282 | 20985521U, // XNORri |
| 1283 | 20985521U, // XNORrr |
| 1284 | 20984608U, // XORCCri |
| 1285 | 20984608U, // XORCCrr |
| 1286 | 20985528U, // XORri |
| 1287 | 20985528U, // XORrr |
| 1288 | }; |
| 1289 | |
| 1290 | // Emit the opcode for the instruction. |
| 1291 | uint32_t Bits = 0; |
| 1292 | Bits |= OpInfo0[MI.getOpcode()] << 0; |
| 1293 | if (Bits == 0) |
| 1294 | return {nullptr, Bits}; |
| 1295 | return {AsmStrs+(Bits & 4095)-1, Bits}; |
| 1296 | |
| 1297 | } |
| 1298 | /// printInstruction - This method is automatically generated by tablegen |
| 1299 | /// from the instruction set description. |
| 1300 | LLVM_NO_PROFILE_INSTRUMENT_FUNCTION |
| 1301 | void SparcInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) { |
| 1302 | O << "\t"; |
| 1303 | |
| 1304 | auto MnemonicInfo = getMnemonic(MI: *MI); |
| 1305 | |
| 1306 | O << MnemonicInfo.first; |
| 1307 | |
| 1308 | uint32_t Bits = MnemonicInfo.second; |
| 1309 | assert(Bits != 0 && "Cannot print this instruction."); |
| 1310 | |
| 1311 | // Fragment 0 encoded into 4 bits for 13 unique commands. |
| 1312 | switch ((Bits >> 12) & 15) { |
| 1313 | default: llvm_unreachable("Invalid command number."); |
| 1314 | case 0: |
| 1315 | // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... |
| 1316 | return; |
| 1317 | break; |
| 1318 | case 1: |
| 1319 | // ADJCALLSTACKDOWN, ADJCALLSTACKUP, CMASK16, CMASK32, CMASK8, FCMPD, FCM... |
| 1320 | printOperand(MI, opNum: 0, STI, OS&: O); |
| 1321 | break; |
| 1322 | case 2: |
| 1323 | // GETPCX |
| 1324 | printGetPCX(MI, OpNo: 0, STI, OS&: O); |
| 1325 | return; |
| 1326 | break; |
| 1327 | case 3: |
| 1328 | // SET, SETSW, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, AD... |
| 1329 | printOperand(MI, opNum: 1, STI, OS&: O); |
| 1330 | break; |
| 1331 | case 4: |
| 1332 | // BA, CALL, CALLi, TAIL_CALL, TLS_CALL |
| 1333 | printCTILabel(MI, Address, OpNum: 0, STI, O); |
| 1334 | break; |
| 1335 | case 5: |
| 1336 | // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA... |
| 1337 | printCCOperand(MI, opNum: 1, STI, OS&: O); |
| 1338 | break; |
| 1339 | case 6: |
| 1340 | // BINDri, BINDrr, CALLri, CALLrii, CALLrr, CALLrri, FLUSHri, FLUSHrr, LD... |
| 1341 | printMemOperand(MI, opNum: 0, STI, OS&: O); |
| 1342 | break; |
| 1343 | case 7: |
| 1344 | // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV... |
| 1345 | printCCOperand(MI, opNum: 3, STI, OS&: O); |
| 1346 | break; |
| 1347 | case 8: |
| 1348 | // FMOVRD, FMOVRQ, FMOVRS, MOVRri, MOVRrr, V9FMOVD_FCC, V9FMOVQ_FCC, V9FM... |
| 1349 | printCCOperand(MI, opNum: 4, STI, OS&: O); |
| 1350 | O << ' '; |
| 1351 | printOperand(MI, opNum: 1, STI, OS&: O); |
| 1352 | O << ", "; |
| 1353 | printOperand(MI, opNum: 2, STI, OS&: O); |
| 1354 | O << ", "; |
| 1355 | printOperand(MI, opNum: 0, STI, OS&: O); |
| 1356 | return; |
| 1357 | break; |
| 1358 | case 9: |
| 1359 | // GDOP_LDXrr, GDOP_LDrr, JMPLri, JMPLrr, LDAri, LDArr, LDCri, LDCrr, LDD... |
| 1360 | printMemOperand(MI, opNum: 1, STI, OS&: O); |
| 1361 | break; |
| 1362 | case 10: |
| 1363 | // MEMBARi |
| 1364 | printMembarTag(MI, opNum: 0, STI, O); |
| 1365 | return; |
| 1366 | break; |
| 1367 | case 11: |
| 1368 | // STAri, STArr, STBAri, STBArr, STBri, STBrr, STCri, STCrr, STDAri, STDA... |
| 1369 | printOperand(MI, opNum: 2, STI, OS&: O); |
| 1370 | O << ", ["; |
| 1371 | printMemOperand(MI, opNum: 0, STI, OS&: O); |
| 1372 | break; |
| 1373 | case 12: |
| 1374 | // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr |
| 1375 | printCCOperand(MI, opNum: 2, STI, OS&: O); |
| 1376 | break; |
| 1377 | } |
| 1378 | |
| 1379 | |
| 1380 | // Fragment 1 encoded into 5 bits for 23 unique commands. |
| 1381 | switch ((Bits >> 16) & 31) { |
| 1382 | default: llvm_unreachable("Invalid command number."); |
| 1383 | case 0: |
| 1384 | // ADJCALLSTACKDOWN, SET, SETSW, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ... |
| 1385 | O << ", "; |
| 1386 | break; |
| 1387 | case 1: |
| 1388 | // ADJCALLSTACKUP, BA, BINDri, BINDrr, CALL, CALLri, CALLrr, CMASK16, CMA... |
| 1389 | return; |
| 1390 | break; |
| 1391 | case 2: |
| 1392 | // BCOND, BPFCC, BPR, CPBCOND, CWBCONDri, CWBCONDrr, CXBCONDri, CXBCONDrr... |
| 1393 | O << ' '; |
| 1394 | break; |
| 1395 | case 3: |
| 1396 | // BCONDA, BPFCCA, BPRA, CPBCONDA, FBCONDA |
| 1397 | O << ",a "; |
| 1398 | break; |
| 1399 | case 4: |
| 1400 | // BPFCCANT, BPRANT |
| 1401 | O << ",a,pn "; |
| 1402 | printOperand(MI, opNum: 2, STI, OS&: O); |
| 1403 | O << ", "; |
| 1404 | printCTILabel(MI, Address, OpNum: 0, STI, O); |
| 1405 | return; |
| 1406 | break; |
| 1407 | case 5: |
| 1408 | // BPFCCNT, BPRNT |
| 1409 | O << ",pn "; |
| 1410 | printOperand(MI, opNum: 2, STI, OS&: O); |
| 1411 | O << ", "; |
| 1412 | printCTILabel(MI, Address, OpNum: 0, STI, O); |
| 1413 | return; |
| 1414 | break; |
| 1415 | case 6: |
| 1416 | // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI... |
| 1417 | O << " %icc, "; |
| 1418 | break; |
| 1419 | case 7: |
| 1420 | // BPICCA |
| 1421 | O << ",a %icc, "; |
| 1422 | printCTILabel(MI, Address, OpNum: 0, STI, O); |
| 1423 | return; |
| 1424 | break; |
| 1425 | case 8: |
| 1426 | // BPICCANT |
| 1427 | O << ",a,pn %icc, "; |
| 1428 | printCTILabel(MI, Address, OpNum: 0, STI, O); |
| 1429 | return; |
| 1430 | break; |
| 1431 | case 9: |
| 1432 | // BPICCNT |
| 1433 | O << ",pn %icc, "; |
| 1434 | printCTILabel(MI, Address, OpNum: 0, STI, O); |
| 1435 | return; |
| 1436 | break; |
| 1437 | case 10: |
| 1438 | // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX... |
| 1439 | O << " %xcc, "; |
| 1440 | break; |
| 1441 | case 11: |
| 1442 | // BPXCCA |
| 1443 | O << ",a %xcc, "; |
| 1444 | printCTILabel(MI, Address, OpNum: 0, STI, O); |
| 1445 | return; |
| 1446 | break; |
| 1447 | case 12: |
| 1448 | // BPXCCANT |
| 1449 | O << ",a,pn %xcc, "; |
| 1450 | printCTILabel(MI, Address, OpNum: 0, STI, O); |
| 1451 | return; |
| 1452 | break; |
| 1453 | case 13: |
| 1454 | // BPXCCNT |
| 1455 | O << ",pn %xcc, "; |
| 1456 | printCTILabel(MI, Address, OpNum: 0, STI, O); |
| 1457 | return; |
| 1458 | break; |
| 1459 | case 14: |
| 1460 | // CASAri, CASXAri, LDAri, LDDAri, LDDFAri, LDFAri, LDQFAri, LDSBAri, LDS... |
| 1461 | O << "] %asi, "; |
| 1462 | break; |
| 1463 | case 15: |
| 1464 | // CASArr, CASXArr, LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDS... |
| 1465 | O << "] "; |
| 1466 | break; |
| 1467 | case 16: |
| 1468 | // FBCONDA_V9 |
| 1469 | O << ",a %fcc0, "; |
| 1470 | printCTILabel(MI, Address, OpNum: 0, STI, O); |
| 1471 | return; |
| 1472 | break; |
| 1473 | case 17: |
| 1474 | // FBCOND_V9, FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr |
| 1475 | O << " %fcc0, "; |
| 1476 | break; |
| 1477 | case 18: |
| 1478 | // GDOP_LDXrr, GDOP_LDrr, LDCri, LDCrr, LDDCri, LDDCrr, LDDFri, LDDFrr, L... |
| 1479 | O << "], "; |
| 1480 | break; |
| 1481 | case 19: |
| 1482 | // LDCSRri, LDCSRrr |
| 1483 | O << "], %csr"; |
| 1484 | return; |
| 1485 | break; |
| 1486 | case 20: |
| 1487 | // LDFSRri, LDFSRrr, LDXFSRri, LDXFSRrr |
| 1488 | O << "], %fsr"; |
| 1489 | return; |
| 1490 | break; |
| 1491 | case 21: |
| 1492 | // STAri, STBAri, STDAri, STDFAri, STFAri, STHAri, STQFAri, STXAri |
| 1493 | O << "] %asi"; |
| 1494 | return; |
| 1495 | break; |
| 1496 | case 22: |
| 1497 | // STBri, STBrr, STCSRri, STCSRrr, STCri, STCrr, STDCQri, STDCQrr, STDCri... |
| 1498 | O << ']'; |
| 1499 | return; |
| 1500 | break; |
| 1501 | } |
| 1502 | |
| 1503 | |
| 1504 | // Fragment 2 encoded into 3 bits for 8 unique commands. |
| 1505 | switch ((Bits >> 21) & 7) { |
| 1506 | default: llvm_unreachable("Invalid command number."); |
| 1507 | case 0: |
| 1508 | // ADJCALLSTACKDOWN, CALLi, FCMPD, FCMPD_V9, FCMPQ, FCMPQ_V9, FCMPS, FCMP... |
| 1509 | printOperand(MI, opNum: 1, STI, OS&: O); |
| 1510 | break; |
| 1511 | case 1: |
| 1512 | // SET, SETSW, DES_IIP, DES_IP, FABSD, FABSQ, FABSS, FDTOI, FDTOQ, FDTOS,... |
| 1513 | printOperand(MI, opNum: 0, STI, OS&: O); |
| 1514 | break; |
| 1515 | case 2: |
| 1516 | // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC... |
| 1517 | printOperand(MI, opNum: 2, STI, OS&: O); |
| 1518 | break; |
| 1519 | case 3: |
| 1520 | // BCOND, BCONDA, BPICC, BPXCC, CPBCOND, CPBCONDA, FBCOND, FBCONDA, FBCON... |
| 1521 | printCTILabel(MI, Address, OpNum: 0, STI, O); |
| 1522 | return; |
| 1523 | break; |
| 1524 | case 4: |
| 1525 | // CASArr, CASXArr |
| 1526 | printASITag(MI, opNum: 4, STI, O); |
| 1527 | O << ", "; |
| 1528 | printOperand(MI, opNum: 2, STI, OS&: O); |
| 1529 | O << ", "; |
| 1530 | printOperand(MI, opNum: 0, STI, OS&: O); |
| 1531 | return; |
| 1532 | break; |
| 1533 | case 5: |
| 1534 | // LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDSHArr, LDSTUBArr, ... |
| 1535 | printASITag(MI, opNum: 3, STI, O); |
| 1536 | break; |
| 1537 | case 6: |
| 1538 | // PREFETCHAi, PREFETCHi, PREFETCHr |
| 1539 | printPrefetchTag(MI, opNum: 2, STI, O); |
| 1540 | return; |
| 1541 | break; |
| 1542 | case 7: |
| 1543 | // PREFETCHAr |
| 1544 | printASITag(MI, opNum: 2, STI, O); |
| 1545 | O << ", "; |
| 1546 | printPrefetchTag(MI, opNum: 3, STI, O); |
| 1547 | return; |
| 1548 | break; |
| 1549 | } |
| 1550 | |
| 1551 | |
| 1552 | // Fragment 3 encoded into 3 bits for 6 unique commands. |
| 1553 | switch ((Bits >> 24) & 7) { |
| 1554 | default: llvm_unreachable("Invalid command number."); |
| 1555 | case 0: |
| 1556 | // ADJCALLSTACKDOWN, SET, SETSW, CALLi, CALLrii, CALLrri, DES_IIP, DES_IP... |
| 1557 | return; |
| 1558 | break; |
| 1559 | case 1: |
| 1560 | // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC... |
| 1561 | O << ", "; |
| 1562 | break; |
| 1563 | case 2: |
| 1564 | // PWRPSRri, PWRPSRrr, WRPSRri, WRPSRrr |
| 1565 | O << ", %psr"; |
| 1566 | return; |
| 1567 | break; |
| 1568 | case 3: |
| 1569 | // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr |
| 1570 | O << " + "; |
| 1571 | printOperand(MI, opNum: 1, STI, OS&: O); |
| 1572 | return; |
| 1573 | break; |
| 1574 | case 4: |
| 1575 | // WRTBRri, WRTBRrr |
| 1576 | O << ", %tbr"; |
| 1577 | return; |
| 1578 | break; |
| 1579 | case 5: |
| 1580 | // WRWIMri, WRWIMrr |
| 1581 | O << ", %wim"; |
| 1582 | return; |
| 1583 | break; |
| 1584 | } |
| 1585 | |
| 1586 | |
| 1587 | // Fragment 4 encoded into 2 bits for 4 unique commands. |
| 1588 | switch ((Bits >> 27) & 3) { |
| 1589 | default: llvm_unreachable("Invalid command number."); |
| 1590 | case 0: |
| 1591 | // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC... |
| 1592 | printOperand(MI, opNum: 0, STI, OS&: O); |
| 1593 | break; |
| 1594 | case 1: |
| 1595 | // AES_DROUND01, AES_DROUND01_LAST, AES_DROUND23, AES_DROUND23_LAST, AES_... |
| 1596 | printOperand(MI, opNum: 3, STI, OS&: O); |
| 1597 | break; |
| 1598 | case 2: |
| 1599 | // BPFCC, BPFCCA, BPR, BPRA |
| 1600 | printCTILabel(MI, Address, OpNum: 0, STI, O); |
| 1601 | return; |
| 1602 | break; |
| 1603 | case 3: |
| 1604 | // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP... |
| 1605 | printOperand(MI, opNum: 2, STI, OS&: O); |
| 1606 | return; |
| 1607 | break; |
| 1608 | } |
| 1609 | |
| 1610 | |
| 1611 | // Fragment 5 encoded into 1 bits for 2 unique commands. |
| 1612 | if ((Bits >> 29) & 1) { |
| 1613 | // AES_DROUND01, AES_DROUND01_LAST, AES_DROUND23, AES_DROUND23_LAST, AES_... |
| 1614 | O << ", "; |
| 1615 | } else { |
| 1616 | // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC... |
| 1617 | return; |
| 1618 | } |
| 1619 | |
| 1620 | |
| 1621 | // Fragment 6 encoded into 2 bits for 3 unique commands. |
| 1622 | switch ((Bits >> 30) & 3) { |
| 1623 | default: llvm_unreachable("Invalid command number."); |
| 1624 | case 0: |
| 1625 | // AES_DROUND01, AES_DROUND01_LAST, AES_DROUND23, AES_DROUND23_LAST, AES_... |
| 1626 | printOperand(MI, opNum: 0, STI, OS&: O); |
| 1627 | return; |
| 1628 | break; |
| 1629 | case 1: |
| 1630 | // CWBCONDri, CWBCONDrr, CXBCONDri, CXBCONDrr |
| 1631 | printCTILabel(MI, Address, OpNum: 0, STI, O); |
| 1632 | return; |
| 1633 | break; |
| 1634 | case 2: |
| 1635 | // TLS_ADDrr |
| 1636 | printOperand(MI, opNum: 3, STI, OS&: O); |
| 1637 | return; |
| 1638 | break; |
| 1639 | } |
| 1640 | |
| 1641 | } |
| 1642 | |
| 1643 | |
| 1644 | /// getRegisterName - This method is automatically generated by tblgen |
| 1645 | /// from the register set description. This returns the assembler name |
| 1646 | /// for the specified register. |
| 1647 | const char *SparcInstPrinter:: |
| 1648 | getRegisterName(MCRegister Reg, unsigned AltIdx) { |
| 1649 | unsigned RegNo = Reg.id(); |
| 1650 | assert(RegNo && RegNo < 238 && "Invalid register number!"); |
| 1651 | |
| 1652 | |
| 1653 | #ifdef __GNUC__ |
| 1654 | #pragma GCC diagnostic push |
| 1655 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 1656 | #endif |
| 1657 | static const char AsmStrsNoRegAltName[] = { |
| 1658 | /* 0 */ "c10\000" |
| 1659 | /* 4 */ "f10\000" |
| 1660 | /* 8 */ "asr10\000" |
| 1661 | /* 14 */ "c20\000" |
| 1662 | /* 18 */ "f20\000" |
| 1663 | /* 22 */ "asr20\000" |
| 1664 | /* 28 */ "c30\000" |
| 1665 | /* 32 */ "f30\000" |
| 1666 | /* 36 */ "asr30\000" |
| 1667 | /* 42 */ "f40\000" |
| 1668 | /* 46 */ "f50\000" |
| 1669 | /* 50 */ "f60\000" |
| 1670 | /* 54 */ "fcc0\000" |
| 1671 | /* 59 */ "f0\000" |
| 1672 | /* 62 */ "g0\000" |
| 1673 | /* 65 */ "i0\000" |
| 1674 | /* 68 */ "l0\000" |
| 1675 | /* 71 */ "o0\000" |
| 1676 | /* 74 */ "c11\000" |
| 1677 | /* 78 */ "f11\000" |
| 1678 | /* 82 */ "asr11\000" |
| 1679 | /* 88 */ "c21\000" |
| 1680 | /* 92 */ "f21\000" |
| 1681 | /* 96 */ "asr21\000" |
| 1682 | /* 102 */ "c31\000" |
| 1683 | /* 106 */ "f31\000" |
| 1684 | /* 110 */ "asr31\000" |
| 1685 | /* 116 */ "fcc1\000" |
| 1686 | /* 121 */ "f1\000" |
| 1687 | /* 124 */ "g1\000" |
| 1688 | /* 127 */ "i1\000" |
| 1689 | /* 130 */ "l1\000" |
| 1690 | /* 133 */ "o1\000" |
| 1691 | /* 136 */ "asr1\000" |
| 1692 | /* 141 */ "c12\000" |
| 1693 | /* 145 */ "f12\000" |
| 1694 | /* 149 */ "asr12\000" |
| 1695 | /* 155 */ "c22\000" |
| 1696 | /* 159 */ "f22\000" |
| 1697 | /* 163 */ "asr22\000" |
| 1698 | /* 169 */ "f32\000" |
| 1699 | /* 173 */ "f42\000" |
| 1700 | /* 177 */ "f52\000" |
| 1701 | /* 181 */ "f62\000" |
| 1702 | /* 185 */ "fcc2\000" |
| 1703 | /* 190 */ "f2\000" |
| 1704 | /* 193 */ "g2\000" |
| 1705 | /* 196 */ "i2\000" |
| 1706 | /* 199 */ "l2\000" |
| 1707 | /* 202 */ "o2\000" |
| 1708 | /* 205 */ "asr2\000" |
| 1709 | /* 210 */ "c13\000" |
| 1710 | /* 214 */ "f13\000" |
| 1711 | /* 218 */ "asr13\000" |
| 1712 | /* 224 */ "c23\000" |
| 1713 | /* 228 */ "f23\000" |
| 1714 | /* 232 */ "asr23\000" |
| 1715 | /* 238 */ "fcc3\000" |
| 1716 | /* 243 */ "f3\000" |
| 1717 | /* 246 */ "g3\000" |
| 1718 | /* 249 */ "i3\000" |
| 1719 | /* 252 */ "l3\000" |
| 1720 | /* 255 */ "o3\000" |
| 1721 | /* 258 */ "asr3\000" |
| 1722 | /* 263 */ "c14\000" |
| 1723 | /* 267 */ "f14\000" |
| 1724 | /* 271 */ "asr14\000" |
| 1725 | /* 277 */ "c24\000" |
| 1726 | /* 281 */ "f24\000" |
| 1727 | /* 285 */ "asr24\000" |
| 1728 | /* 291 */ "f34\000" |
| 1729 | /* 295 */ "f44\000" |
| 1730 | /* 299 */ "f54\000" |
| 1731 | /* 303 */ "c4\000" |
| 1732 | /* 306 */ "f4\000" |
| 1733 | /* 309 */ "g4\000" |
| 1734 | /* 312 */ "i4\000" |
| 1735 | /* 315 */ "l4\000" |
| 1736 | /* 318 */ "o4\000" |
| 1737 | /* 321 */ "asr4\000" |
| 1738 | /* 326 */ "c15\000" |
| 1739 | /* 330 */ "f15\000" |
| 1740 | /* 334 */ "asr15\000" |
| 1741 | /* 340 */ "c25\000" |
| 1742 | /* 344 */ "f25\000" |
| 1743 | /* 348 */ "asr25\000" |
| 1744 | /* 354 */ "c5\000" |
| 1745 | /* 357 */ "f5\000" |
| 1746 | /* 360 */ "g5\000" |
| 1747 | /* 363 */ "i5\000" |
| 1748 | /* 366 */ "l5\000" |
| 1749 | /* 369 */ "o5\000" |
| 1750 | /* 372 */ "asr5\000" |
| 1751 | /* 377 */ "c16\000" |
| 1752 | /* 381 */ "f16\000" |
| 1753 | /* 385 */ "asr16\000" |
| 1754 | /* 391 */ "c26\000" |
| 1755 | /* 395 */ "f26\000" |
| 1756 | /* 399 */ "asr26\000" |
| 1757 | /* 405 */ "f36\000" |
| 1758 | /* 409 */ "f46\000" |
| 1759 | /* 413 */ "f56\000" |
| 1760 | /* 417 */ "c6\000" |
| 1761 | /* 420 */ "f6\000" |
| 1762 | /* 423 */ "g6\000" |
| 1763 | /* 426 */ "i6\000" |
| 1764 | /* 429 */ "l6\000" |
| 1765 | /* 432 */ "o6\000" |
| 1766 | /* 435 */ "asr6\000" |
| 1767 | /* 440 */ "c17\000" |
| 1768 | /* 444 */ "f17\000" |
| 1769 | /* 448 */ "asr17\000" |
| 1770 | /* 454 */ "c27\000" |
| 1771 | /* 458 */ "f27\000" |
| 1772 | /* 462 */ "asr27\000" |
| 1773 | /* 468 */ "c7\000" |
| 1774 | /* 471 */ "f7\000" |
| 1775 | /* 474 */ "g7\000" |
| 1776 | /* 477 */ "i7\000" |
| 1777 | /* 480 */ "l7\000" |
| 1778 | /* 483 */ "o7\000" |
| 1779 | /* 486 */ "asr7\000" |
| 1780 | /* 491 */ "c18\000" |
| 1781 | /* 495 */ "f18\000" |
| 1782 | /* 499 */ "asr18\000" |
| 1783 | /* 505 */ "c28\000" |
| 1784 | /* 509 */ "f28\000" |
| 1785 | /* 513 */ "asr28\000" |
| 1786 | /* 519 */ "f38\000" |
| 1787 | /* 523 */ "f48\000" |
| 1788 | /* 527 */ "f58\000" |
| 1789 | /* 531 */ "c8\000" |
| 1790 | /* 534 */ "f8\000" |
| 1791 | /* 537 */ "asr8\000" |
| 1792 | /* 542 */ "c19\000" |
| 1793 | /* 546 */ "f19\000" |
| 1794 | /* 550 */ "asr19\000" |
| 1795 | /* 556 */ "c29\000" |
| 1796 | /* 560 */ "f29\000" |
| 1797 | /* 564 */ "asr29\000" |
| 1798 | /* 570 */ "c9\000" |
| 1799 | /* 573 */ "f9\000" |
| 1800 | /* 576 */ "asr9\000" |
| 1801 | /* 581 */ "tba\000" |
| 1802 | /* 585 */ "icc\000" |
| 1803 | /* 589 */ "tnpc\000" |
| 1804 | /* 594 */ "tpc\000" |
| 1805 | /* 598 */ "canrestore\000" |
| 1806 | /* 609 */ "pstate\000" |
| 1807 | /* 616 */ "tstate\000" |
| 1808 | /* 623 */ "wstate\000" |
| 1809 | /* 630 */ "cansave\000" |
| 1810 | /* 638 */ "tick\000" |
| 1811 | /* 643 */ "gl\000" |
| 1812 | /* 646 */ "pil\000" |
| 1813 | /* 650 */ "tl\000" |
| 1814 | /* 653 */ "wim\000" |
| 1815 | /* 657 */ "cleanwin\000" |
| 1816 | /* 666 */ "otherwin\000" |
| 1817 | /* 675 */ "fp\000" |
| 1818 | /* 678 */ "sp\000" |
| 1819 | /* 681 */ "cwp\000" |
| 1820 | /* 685 */ "cq\000" |
| 1821 | /* 688 */ "fq\000" |
| 1822 | /* 691 */ "tbr\000" |
| 1823 | /* 695 */ "ver\000" |
| 1824 | /* 699 */ "csr\000" |
| 1825 | /* 703 */ "fsr\000" |
| 1826 | /* 707 */ "psr\000" |
| 1827 | /* 711 */ "tt\000" |
| 1828 | /* 714 */ "y\000" |
| 1829 | }; |
| 1830 | #ifdef __GNUC__ |
| 1831 | #pragma GCC diagnostic pop |
| 1832 | #endif |
| 1833 | |
| 1834 | static const uint16_t RegAsmOffsetNoRegAltName[] = { |
| 1835 | 598, 630, 657, 685, 699, 681, 688, 703, 643, 585, 666, 646, 707, 609, |
| 1836 | 581, 691, 638, 650, 589, 594, 616, 711, 695, 653, 623, 714, 136, 205, |
| 1837 | 258, 321, 372, 435, 486, 537, 576, 8, 82, 149, 218, 271, 334, 385, |
| 1838 | 448, 499, 550, 22, 96, 163, 232, 285, 348, 399, 462, 513, 564, 36, |
| 1839 | 110, 56, 118, 187, 240, 303, 354, 417, 468, 531, 570, 0, 74, 141, |
| 1840 | 210, 263, 326, 377, 440, 491, 542, 14, 88, 155, 224, 277, 340, 391, |
| 1841 | 454, 505, 556, 28, 102, 59, 190, 306, 420, 534, 4, 145, 267, 381, |
| 1842 | 495, 18, 159, 281, 395, 509, 32, 169, 291, 405, 519, 42, 173, 295, |
| 1843 | 409, 523, 46, 177, 299, 413, 527, 50, 181, 59, 121, 190, 243, 306, |
| 1844 | 357, 420, 471, 534, 573, 4, 78, 145, 214, 267, 330, 381, 444, 495, |
| 1845 | 546, 18, 92, 159, 228, 281, 344, 395, 458, 509, 560, 32, 106, 54, |
| 1846 | 116, 185, 238, 62, 124, 193, 246, 309, 360, 423, 474, 65, 127, 196, |
| 1847 | 249, 312, 363, 675, 477, 68, 130, 199, 252, 315, 366, 429, 480, 71, |
| 1848 | 133, 202, 255, 318, 369, 678, 483, 59, 306, 534, 145, 381, 18, 281, |
| 1849 | 509, 169, 405, 42, 295, 523, 177, 413, 50, 56, 187, 303, 417, 531, |
| 1850 | 0, 141, 263, 377, 491, 14, 155, 277, 391, 505, 28, 62, 193, 309, |
| 1851 | 423, 65, 196, 312, 426, 68, 199, 315, 429, 71, 202, 318, 432, |
| 1852 | }; |
| 1853 | |
| 1854 | |
| 1855 | #ifdef __GNUC__ |
| 1856 | #pragma GCC diagnostic push |
| 1857 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 1858 | #endif |
| 1859 | static const char AsmStrsRegNamesStateReg[] = { |
| 1860 | /* 0 */ "pc\000" |
| 1861 | /* 3 */ "asi\000" |
| 1862 | /* 7 */ "tick\000" |
| 1863 | /* 12 */ "ccr\000" |
| 1864 | /* 16 */ "fprs\000" |
| 1865 | }; |
| 1866 | #ifdef __GNUC__ |
| 1867 | #pragma GCC diagnostic pop |
| 1868 | #endif |
| 1869 | |
| 1870 | static const uint8_t RegAsmOffsetRegNamesStateReg[] = { |
| 1871 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
| 1872 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 12, |
| 1873 | 3, 7, 0, 16, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
| 1874 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
| 1875 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
| 1876 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
| 1877 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
| 1878 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
| 1879 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
| 1880 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
| 1881 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
| 1882 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
| 1883 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
| 1884 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
| 1885 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
| 1886 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
| 1887 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
| 1888 | }; |
| 1889 | |
| 1890 | switch(AltIdx) { |
| 1891 | default: llvm_unreachable("Invalid register alt name index!"); |
| 1892 | case SP::NoRegAltName: |
| 1893 | assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) && |
| 1894 | "Invalid alt name index for register!"); |
| 1895 | return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]; |
| 1896 | case SP::RegNamesStateReg: |
| 1897 | if (!*(AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1])) |
| 1898 | return getRegisterName(Reg: RegNo, AltIdx: SP::NoRegAltName); |
| 1899 | return AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1]; |
| 1900 | } |
| 1901 | } |
| 1902 | |
| 1903 | #ifdef PRINT_ALIAS_INSTR |
| 1904 | #undef PRINT_ALIAS_INSTR |
| 1905 | |
| 1906 | bool SparcInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS) { |
| 1907 | static const PatternsForOpcode OpToPatterns[] = { |
| 1908 | {.Opcode: SP::BCOND, .PatternStart: 0, .NumPatterns: 16 }, |
| 1909 | {.Opcode: SP::BCONDA, .PatternStart: 16, .NumPatterns: 16 }, |
| 1910 | {.Opcode: SP::BPFCCANT, .PatternStart: 32, .NumPatterns: 16 }, |
| 1911 | {.Opcode: SP::BPFCCNT, .PatternStart: 48, .NumPatterns: 16 }, |
| 1912 | {.Opcode: SP::BPICCANT, .PatternStart: 64, .NumPatterns: 32 }, |
| 1913 | {.Opcode: SP::BPICCNT, .PatternStart: 96, .NumPatterns: 32 }, |
| 1914 | {.Opcode: SP::BPRANT, .PatternStart: 128, .NumPatterns: 4 }, |
| 1915 | {.Opcode: SP::BPRNT, .PatternStart: 132, .NumPatterns: 4 }, |
| 1916 | {.Opcode: SP::CASArr, .PatternStart: 136, .NumPatterns: 2 }, |
| 1917 | {.Opcode: SP::CASXArr, .PatternStart: 138, .NumPatterns: 2 }, |
| 1918 | {.Opcode: SP::CWBCONDri, .PatternStart: 140, .NumPatterns: 14 }, |
| 1919 | {.Opcode: SP::CWBCONDrr, .PatternStart: 154, .NumPatterns: 14 }, |
| 1920 | {.Opcode: SP::CXBCONDri, .PatternStart: 168, .NumPatterns: 14 }, |
| 1921 | {.Opcode: SP::CXBCONDrr, .PatternStart: 182, .NumPatterns: 14 }, |
| 1922 | {.Opcode: SP::FMOVD_ICC, .PatternStart: 196, .NumPatterns: 32 }, |
| 1923 | {.Opcode: SP::FMOVQ_ICC, .PatternStart: 228, .NumPatterns: 32 }, |
| 1924 | {.Opcode: SP::FMOVRD, .PatternStart: 260, .NumPatterns: 4 }, |
| 1925 | {.Opcode: SP::FMOVRQ, .PatternStart: 264, .NumPatterns: 4 }, |
| 1926 | {.Opcode: SP::FMOVRS, .PatternStart: 268, .NumPatterns: 4 }, |
| 1927 | {.Opcode: SP::FMOVS_ICC, .PatternStart: 272, .NumPatterns: 32 }, |
| 1928 | {.Opcode: SP::MOVICCri, .PatternStart: 304, .NumPatterns: 32 }, |
| 1929 | {.Opcode: SP::MOVICCrr, .PatternStart: 336, .NumPatterns: 32 }, |
| 1930 | {.Opcode: SP::MOVRri, .PatternStart: 368, .NumPatterns: 4 }, |
| 1931 | {.Opcode: SP::MOVRrr, .PatternStart: 372, .NumPatterns: 4 }, |
| 1932 | {.Opcode: SP::ORCCrr, .PatternStart: 376, .NumPatterns: 1 }, |
| 1933 | {.Opcode: SP::ORri, .PatternStart: 377, .NumPatterns: 1 }, |
| 1934 | {.Opcode: SP::ORrr, .PatternStart: 378, .NumPatterns: 1 }, |
| 1935 | {.Opcode: SP::RESTORErr, .PatternStart: 379, .NumPatterns: 1 }, |
| 1936 | {.Opcode: SP::RET, .PatternStart: 380, .NumPatterns: 1 }, |
| 1937 | {.Opcode: SP::RETL, .PatternStart: 381, .NumPatterns: 1 }, |
| 1938 | {.Opcode: SP::SAVErr, .PatternStart: 382, .NumPatterns: 1 }, |
| 1939 | {.Opcode: SP::SUBCCri, .PatternStart: 383, .NumPatterns: 1 }, |
| 1940 | {.Opcode: SP::SUBCCrr, .PatternStart: 384, .NumPatterns: 1 }, |
| 1941 | {.Opcode: SP::TICCri, .PatternStart: 385, .NumPatterns: 64 }, |
| 1942 | {.Opcode: SP::TICCrr, .PatternStart: 449, .NumPatterns: 64 }, |
| 1943 | {.Opcode: SP::TRAPri, .PatternStart: 513, .NumPatterns: 32 }, |
| 1944 | {.Opcode: SP::TRAPrr, .PatternStart: 545, .NumPatterns: 32 }, |
| 1945 | {.Opcode: SP::TXCCri, .PatternStart: 577, .NumPatterns: 64 }, |
| 1946 | {.Opcode: SP::TXCCrr, .PatternStart: 641, .NumPatterns: 64 }, |
| 1947 | {.Opcode: SP::V9FCMPD, .PatternStart: 705, .NumPatterns: 1 }, |
| 1948 | {.Opcode: SP::V9FCMPED, .PatternStart: 706, .NumPatterns: 1 }, |
| 1949 | {.Opcode: SP::V9FCMPEQ, .PatternStart: 707, .NumPatterns: 1 }, |
| 1950 | {.Opcode: SP::V9FCMPES, .PatternStart: 708, .NumPatterns: 1 }, |
| 1951 | {.Opcode: SP::V9FCMPQ, .PatternStart: 709, .NumPatterns: 1 }, |
| 1952 | {.Opcode: SP::V9FCMPS, .PatternStart: 710, .NumPatterns: 1 }, |
| 1953 | {.Opcode: SP::V9FMOVD_FCC, .PatternStart: 711, .NumPatterns: 16 }, |
| 1954 | {.Opcode: SP::V9FMOVQ_FCC, .PatternStart: 727, .NumPatterns: 16 }, |
| 1955 | {.Opcode: SP::V9FMOVS_FCC, .PatternStart: 743, .NumPatterns: 16 }, |
| 1956 | {.Opcode: SP::V9MOVFCCri, .PatternStart: 759, .NumPatterns: 16 }, |
| 1957 | {.Opcode: SP::V9MOVFCCrr, .PatternStart: 775, .NumPatterns: 16 }, |
| 1958 | {.Opcode: SP::WRASRri, .PatternStart: 791, .NumPatterns: 1 }, |
| 1959 | {.Opcode: SP::WRASRrr, .PatternStart: 792, .NumPatterns: 1 }, |
| 1960 | }; |
| 1961 | |
| 1962 | static const AliasPattern Patterns[] = { |
| 1963 | // SP::BCOND - 0 |
| 1964 | {.AsmStrOffset: 0, .AliasCondStart: 0, .NumOperands: 2, .NumConds: 2 }, |
| 1965 | {.AsmStrOffset: 8, .AliasCondStart: 2, .NumOperands: 2, .NumConds: 2 }, |
| 1966 | {.AsmStrOffset: 16, .AliasCondStart: 4, .NumOperands: 2, .NumConds: 2 }, |
| 1967 | {.AsmStrOffset: 25, .AliasCondStart: 6, .NumOperands: 2, .NumConds: 2 }, |
| 1968 | {.AsmStrOffset: 33, .AliasCondStart: 8, .NumOperands: 2, .NumConds: 2 }, |
| 1969 | {.AsmStrOffset: 41, .AliasCondStart: 10, .NumOperands: 2, .NumConds: 2 }, |
| 1970 | {.AsmStrOffset: 50, .AliasCondStart: 12, .NumOperands: 2, .NumConds: 2 }, |
| 1971 | {.AsmStrOffset: 59, .AliasCondStart: 14, .NumOperands: 2, .NumConds: 2 }, |
| 1972 | {.AsmStrOffset: 67, .AliasCondStart: 16, .NumOperands: 2, .NumConds: 2 }, |
| 1973 | {.AsmStrOffset: 76, .AliasCondStart: 18, .NumOperands: 2, .NumConds: 2 }, |
| 1974 | {.AsmStrOffset: 86, .AliasCondStart: 20, .NumOperands: 2, .NumConds: 2 }, |
| 1975 | {.AsmStrOffset: 95, .AliasCondStart: 22, .NumOperands: 2, .NumConds: 2 }, |
| 1976 | {.AsmStrOffset: 104, .AliasCondStart: 24, .NumOperands: 2, .NumConds: 2 }, |
| 1977 | {.AsmStrOffset: 114, .AliasCondStart: 26, .NumOperands: 2, .NumConds: 2 }, |
| 1978 | {.AsmStrOffset: 124, .AliasCondStart: 28, .NumOperands: 2, .NumConds: 2 }, |
| 1979 | {.AsmStrOffset: 133, .AliasCondStart: 30, .NumOperands: 2, .NumConds: 2 }, |
| 1980 | // SP::BCONDA - 16 |
| 1981 | {.AsmStrOffset: 142, .AliasCondStart: 32, .NumOperands: 2, .NumConds: 2 }, |
| 1982 | {.AsmStrOffset: 152, .AliasCondStart: 34, .NumOperands: 2, .NumConds: 2 }, |
| 1983 | {.AsmStrOffset: 162, .AliasCondStart: 36, .NumOperands: 2, .NumConds: 2 }, |
| 1984 | {.AsmStrOffset: 173, .AliasCondStart: 38, .NumOperands: 2, .NumConds: 2 }, |
| 1985 | {.AsmStrOffset: 183, .AliasCondStart: 40, .NumOperands: 2, .NumConds: 2 }, |
| 1986 | {.AsmStrOffset: 193, .AliasCondStart: 42, .NumOperands: 2, .NumConds: 2 }, |
| 1987 | {.AsmStrOffset: 204, .AliasCondStart: 44, .NumOperands: 2, .NumConds: 2 }, |
| 1988 | {.AsmStrOffset: 215, .AliasCondStart: 46, .NumOperands: 2, .NumConds: 2 }, |
| 1989 | {.AsmStrOffset: 225, .AliasCondStart: 48, .NumOperands: 2, .NumConds: 2 }, |
| 1990 | {.AsmStrOffset: 236, .AliasCondStart: 50, .NumOperands: 2, .NumConds: 2 }, |
| 1991 | {.AsmStrOffset: 248, .AliasCondStart: 52, .NumOperands: 2, .NumConds: 2 }, |
| 1992 | {.AsmStrOffset: 259, .AliasCondStart: 54, .NumOperands: 2, .NumConds: 2 }, |
| 1993 | {.AsmStrOffset: 270, .AliasCondStart: 56, .NumOperands: 2, .NumConds: 2 }, |
| 1994 | {.AsmStrOffset: 282, .AliasCondStart: 58, .NumOperands: 2, .NumConds: 2 }, |
| 1995 | {.AsmStrOffset: 294, .AliasCondStart: 60, .NumOperands: 2, .NumConds: 2 }, |
| 1996 | {.AsmStrOffset: 305, .AliasCondStart: 62, .NumOperands: 2, .NumConds: 2 }, |
| 1997 | // SP::BPFCCANT - 32 |
| 1998 | {.AsmStrOffset: 316, .AliasCondStart: 64, .NumOperands: 3, .NumConds: 4 }, |
| 1999 | {.AsmStrOffset: 334, .AliasCondStart: 68, .NumOperands: 3, .NumConds: 4 }, |
| 2000 | {.AsmStrOffset: 352, .AliasCondStart: 72, .NumOperands: 3, .NumConds: 4 }, |
| 2001 | {.AsmStrOffset: 370, .AliasCondStart: 76, .NumOperands: 3, .NumConds: 4 }, |
| 2002 | {.AsmStrOffset: 388, .AliasCondStart: 80, .NumOperands: 3, .NumConds: 4 }, |
| 2003 | {.AsmStrOffset: 407, .AliasCondStart: 84, .NumOperands: 3, .NumConds: 4 }, |
| 2004 | {.AsmStrOffset: 425, .AliasCondStart: 88, .NumOperands: 3, .NumConds: 4 }, |
| 2005 | {.AsmStrOffset: 444, .AliasCondStart: 92, .NumOperands: 3, .NumConds: 4 }, |
| 2006 | {.AsmStrOffset: 463, .AliasCondStart: 96, .NumOperands: 3, .NumConds: 4 }, |
| 2007 | {.AsmStrOffset: 482, .AliasCondStart: 100, .NumOperands: 3, .NumConds: 4 }, |
| 2008 | {.AsmStrOffset: 500, .AliasCondStart: 104, .NumOperands: 3, .NumConds: 4 }, |
| 2009 | {.AsmStrOffset: 519, .AliasCondStart: 108, .NumOperands: 3, .NumConds: 4 }, |
| 2010 | {.AsmStrOffset: 538, .AliasCondStart: 112, .NumOperands: 3, .NumConds: 4 }, |
| 2011 | {.AsmStrOffset: 558, .AliasCondStart: 116, .NumOperands: 3, .NumConds: 4 }, |
| 2012 | {.AsmStrOffset: 577, .AliasCondStart: 120, .NumOperands: 3, .NumConds: 4 }, |
| 2013 | {.AsmStrOffset: 597, .AliasCondStart: 124, .NumOperands: 3, .NumConds: 4 }, |
| 2014 | // SP::BPFCCNT - 48 |
| 2015 | {.AsmStrOffset: 615, .AliasCondStart: 128, .NumOperands: 3, .NumConds: 4 }, |
| 2016 | {.AsmStrOffset: 631, .AliasCondStart: 132, .NumOperands: 3, .NumConds: 4 }, |
| 2017 | {.AsmStrOffset: 647, .AliasCondStart: 136, .NumOperands: 3, .NumConds: 4 }, |
| 2018 | {.AsmStrOffset: 663, .AliasCondStart: 140, .NumOperands: 3, .NumConds: 4 }, |
| 2019 | {.AsmStrOffset: 679, .AliasCondStart: 144, .NumOperands: 3, .NumConds: 4 }, |
| 2020 | {.AsmStrOffset: 696, .AliasCondStart: 148, .NumOperands: 3, .NumConds: 4 }, |
| 2021 | {.AsmStrOffset: 712, .AliasCondStart: 152, .NumOperands: 3, .NumConds: 4 }, |
| 2022 | {.AsmStrOffset: 729, .AliasCondStart: 156, .NumOperands: 3, .NumConds: 4 }, |
| 2023 | {.AsmStrOffset: 746, .AliasCondStart: 160, .NumOperands: 3, .NumConds: 4 }, |
| 2024 | {.AsmStrOffset: 763, .AliasCondStart: 164, .NumOperands: 3, .NumConds: 4 }, |
| 2025 | {.AsmStrOffset: 779, .AliasCondStart: 168, .NumOperands: 3, .NumConds: 4 }, |
| 2026 | {.AsmStrOffset: 796, .AliasCondStart: 172, .NumOperands: 3, .NumConds: 4 }, |
| 2027 | {.AsmStrOffset: 813, .AliasCondStart: 176, .NumOperands: 3, .NumConds: 4 }, |
| 2028 | {.AsmStrOffset: 831, .AliasCondStart: 180, .NumOperands: 3, .NumConds: 4 }, |
| 2029 | {.AsmStrOffset: 848, .AliasCondStart: 184, .NumOperands: 3, .NumConds: 4 }, |
| 2030 | {.AsmStrOffset: 866, .AliasCondStart: 188, .NumOperands: 3, .NumConds: 4 }, |
| 2031 | // SP::BPICCANT - 64 |
| 2032 | {.AsmStrOffset: 882, .AliasCondStart: 192, .NumOperands: 2, .NumConds: 3 }, |
| 2033 | {.AsmStrOffset: 901, .AliasCondStart: 195, .NumOperands: 2, .NumConds: 4 }, |
| 2034 | {.AsmStrOffset: 920, .AliasCondStart: 199, .NumOperands: 2, .NumConds: 3 }, |
| 2035 | {.AsmStrOffset: 939, .AliasCondStart: 202, .NumOperands: 2, .NumConds: 4 }, |
| 2036 | {.AsmStrOffset: 958, .AliasCondStart: 206, .NumOperands: 2, .NumConds: 3 }, |
| 2037 | {.AsmStrOffset: 978, .AliasCondStart: 209, .NumOperands: 2, .NumConds: 4 }, |
| 2038 | {.AsmStrOffset: 998, .AliasCondStart: 213, .NumOperands: 2, .NumConds: 3 }, |
| 2039 | {.AsmStrOffset: 1017, .AliasCondStart: 216, .NumOperands: 2, .NumConds: 4 }, |
| 2040 | {.AsmStrOffset: 1036, .AliasCondStart: 220, .NumOperands: 2, .NumConds: 3 }, |
| 2041 | {.AsmStrOffset: 1055, .AliasCondStart: 223, .NumOperands: 2, .NumConds: 4 }, |
| 2042 | {.AsmStrOffset: 1074, .AliasCondStart: 227, .NumOperands: 2, .NumConds: 3 }, |
| 2043 | {.AsmStrOffset: 1094, .AliasCondStart: 230, .NumOperands: 2, .NumConds: 4 }, |
| 2044 | {.AsmStrOffset: 1114, .AliasCondStart: 234, .NumOperands: 2, .NumConds: 3 }, |
| 2045 | {.AsmStrOffset: 1134, .AliasCondStart: 237, .NumOperands: 2, .NumConds: 4 }, |
| 2046 | {.AsmStrOffset: 1154, .AliasCondStart: 241, .NumOperands: 2, .NumConds: 3 }, |
| 2047 | {.AsmStrOffset: 1173, .AliasCondStart: 244, .NumOperands: 2, .NumConds: 4 }, |
| 2048 | {.AsmStrOffset: 1192, .AliasCondStart: 248, .NumOperands: 2, .NumConds: 3 }, |
| 2049 | {.AsmStrOffset: 1212, .AliasCondStart: 251, .NumOperands: 2, .NumConds: 4 }, |
| 2050 | {.AsmStrOffset: 1232, .AliasCondStart: 255, .NumOperands: 2, .NumConds: 3 }, |
| 2051 | {.AsmStrOffset: 1253, .AliasCondStart: 258, .NumOperands: 2, .NumConds: 4 }, |
| 2052 | {.AsmStrOffset: 1274, .AliasCondStart: 262, .NumOperands: 2, .NumConds: 3 }, |
| 2053 | {.AsmStrOffset: 1294, .AliasCondStart: 265, .NumOperands: 2, .NumConds: 4 }, |
| 2054 | {.AsmStrOffset: 1314, .AliasCondStart: 269, .NumOperands: 2, .NumConds: 3 }, |
| 2055 | {.AsmStrOffset: 1334, .AliasCondStart: 272, .NumOperands: 2, .NumConds: 4 }, |
| 2056 | {.AsmStrOffset: 1354, .AliasCondStart: 276, .NumOperands: 2, .NumConds: 3 }, |
| 2057 | {.AsmStrOffset: 1375, .AliasCondStart: 279, .NumOperands: 2, .NumConds: 4 }, |
| 2058 | {.AsmStrOffset: 1396, .AliasCondStart: 283, .NumOperands: 2, .NumConds: 3 }, |
| 2059 | {.AsmStrOffset: 1417, .AliasCondStart: 286, .NumOperands: 2, .NumConds: 4 }, |
| 2060 | {.AsmStrOffset: 1438, .AliasCondStart: 290, .NumOperands: 2, .NumConds: 3 }, |
| 2061 | {.AsmStrOffset: 1458, .AliasCondStart: 293, .NumOperands: 2, .NumConds: 4 }, |
| 2062 | {.AsmStrOffset: 1478, .AliasCondStart: 297, .NumOperands: 2, .NumConds: 3 }, |
| 2063 | {.AsmStrOffset: 1498, .AliasCondStart: 300, .NumOperands: 2, .NumConds: 4 }, |
| 2064 | // SP::BPICCNT - 96 |
| 2065 | {.AsmStrOffset: 1518, .AliasCondStart: 304, .NumOperands: 2, .NumConds: 3 }, |
| 2066 | {.AsmStrOffset: 1535, .AliasCondStart: 307, .NumOperands: 2, .NumConds: 4 }, |
| 2067 | {.AsmStrOffset: 1552, .AliasCondStart: 311, .NumOperands: 2, .NumConds: 3 }, |
| 2068 | {.AsmStrOffset: 1569, .AliasCondStart: 314, .NumOperands: 2, .NumConds: 4 }, |
| 2069 | {.AsmStrOffset: 1586, .AliasCondStart: 318, .NumOperands: 2, .NumConds: 3 }, |
| 2070 | {.AsmStrOffset: 1604, .AliasCondStart: 321, .NumOperands: 2, .NumConds: 4 }, |
| 2071 | {.AsmStrOffset: 1622, .AliasCondStart: 325, .NumOperands: 2, .NumConds: 3 }, |
| 2072 | {.AsmStrOffset: 1639, .AliasCondStart: 328, .NumOperands: 2, .NumConds: 4 }, |
| 2073 | {.AsmStrOffset: 1656, .AliasCondStart: 332, .NumOperands: 2, .NumConds: 3 }, |
| 2074 | {.AsmStrOffset: 1673, .AliasCondStart: 335, .NumOperands: 2, .NumConds: 4 }, |
| 2075 | {.AsmStrOffset: 1690, .AliasCondStart: 339, .NumOperands: 2, .NumConds: 3 }, |
| 2076 | {.AsmStrOffset: 1708, .AliasCondStart: 342, .NumOperands: 2, .NumConds: 4 }, |
| 2077 | {.AsmStrOffset: 1726, .AliasCondStart: 346, .NumOperands: 2, .NumConds: 3 }, |
| 2078 | {.AsmStrOffset: 1744, .AliasCondStart: 349, .NumOperands: 2, .NumConds: 4 }, |
| 2079 | {.AsmStrOffset: 1762, .AliasCondStart: 353, .NumOperands: 2, .NumConds: 3 }, |
| 2080 | {.AsmStrOffset: 1779, .AliasCondStart: 356, .NumOperands: 2, .NumConds: 4 }, |
| 2081 | {.AsmStrOffset: 1796, .AliasCondStart: 360, .NumOperands: 2, .NumConds: 3 }, |
| 2082 | {.AsmStrOffset: 1814, .AliasCondStart: 363, .NumOperands: 2, .NumConds: 4 }, |
| 2083 | {.AsmStrOffset: 1832, .AliasCondStart: 367, .NumOperands: 2, .NumConds: 3 }, |
| 2084 | {.AsmStrOffset: 1851, .AliasCondStart: 370, .NumOperands: 2, .NumConds: 4 }, |
| 2085 | {.AsmStrOffset: 1870, .AliasCondStart: 374, .NumOperands: 2, .NumConds: 3 }, |
| 2086 | {.AsmStrOffset: 1888, .AliasCondStart: 377, .NumOperands: 2, .NumConds: 4 }, |
| 2087 | {.AsmStrOffset: 1906, .AliasCondStart: 381, .NumOperands: 2, .NumConds: 3 }, |
| 2088 | {.AsmStrOffset: 1924, .AliasCondStart: 384, .NumOperands: 2, .NumConds: 4 }, |
| 2089 | {.AsmStrOffset: 1942, .AliasCondStart: 388, .NumOperands: 2, .NumConds: 3 }, |
| 2090 | {.AsmStrOffset: 1961, .AliasCondStart: 391, .NumOperands: 2, .NumConds: 4 }, |
| 2091 | {.AsmStrOffset: 1980, .AliasCondStart: 395, .NumOperands: 2, .NumConds: 3 }, |
| 2092 | {.AsmStrOffset: 1999, .AliasCondStart: 398, .NumOperands: 2, .NumConds: 4 }, |
| 2093 | {.AsmStrOffset: 2018, .AliasCondStart: 402, .NumOperands: 2, .NumConds: 3 }, |
| 2094 | {.AsmStrOffset: 2036, .AliasCondStart: 405, .NumOperands: 2, .NumConds: 4 }, |
| 2095 | {.AsmStrOffset: 2054, .AliasCondStart: 409, .NumOperands: 2, .NumConds: 3 }, |
| 2096 | {.AsmStrOffset: 2072, .AliasCondStart: 412, .NumOperands: 2, .NumConds: 4 }, |
| 2097 | // SP::BPRANT - 128 |
| 2098 | {.AsmStrOffset: 2090, .AliasCondStart: 416, .NumOperands: 3, .NumConds: 4 }, |
| 2099 | {.AsmStrOffset: 2110, .AliasCondStart: 420, .NumOperands: 3, .NumConds: 4 }, |
| 2100 | {.AsmStrOffset: 2129, .AliasCondStart: 424, .NumOperands: 3, .NumConds: 4 }, |
| 2101 | {.AsmStrOffset: 2148, .AliasCondStart: 428, .NumOperands: 3, .NumConds: 4 }, |
| 2102 | // SP::BPRNT - 132 |
| 2103 | {.AsmStrOffset: 2168, .AliasCondStart: 432, .NumOperands: 3, .NumConds: 4 }, |
| 2104 | {.AsmStrOffset: 2186, .AliasCondStart: 436, .NumOperands: 3, .NumConds: 4 }, |
| 2105 | {.AsmStrOffset: 2203, .AliasCondStart: 440, .NumOperands: 3, .NumConds: 4 }, |
| 2106 | {.AsmStrOffset: 2220, .AliasCondStart: 444, .NumOperands: 3, .NumConds: 4 }, |
| 2107 | // SP::CASArr - 136 |
| 2108 | {.AsmStrOffset: 2238, .AliasCondStart: 448, .NumOperands: 5, .NumConds: 6 }, |
| 2109 | {.AsmStrOffset: 2255, .AliasCondStart: 454, .NumOperands: 5, .NumConds: 6 }, |
| 2110 | // SP::CASXArr - 138 |
| 2111 | {.AsmStrOffset: 2273, .AliasCondStart: 460, .NumOperands: 5, .NumConds: 6 }, |
| 2112 | {.AsmStrOffset: 2291, .AliasCondStart: 466, .NumOperands: 5, .NumConds: 6 }, |
| 2113 | // SP::CWBCONDri - 140 |
| 2114 | {.AsmStrOffset: 2310, .AliasCondStart: 472, .NumOperands: 4, .NumConds: 4 }, |
| 2115 | {.AsmStrOffset: 2329, .AliasCondStart: 476, .NumOperands: 4, .NumConds: 4 }, |
| 2116 | {.AsmStrOffset: 2347, .AliasCondStart: 480, .NumOperands: 4, .NumConds: 4 }, |
| 2117 | {.AsmStrOffset: 2365, .AliasCondStart: 484, .NumOperands: 4, .NumConds: 4 }, |
| 2118 | {.AsmStrOffset: 2384, .AliasCondStart: 488, .NumOperands: 4, .NumConds: 4 }, |
| 2119 | {.AsmStrOffset: 2403, .AliasCondStart: 492, .NumOperands: 4, .NumConds: 4 }, |
| 2120 | {.AsmStrOffset: 2421, .AliasCondStart: 496, .NumOperands: 4, .NumConds: 4 }, |
| 2121 | {.AsmStrOffset: 2440, .AliasCondStart: 500, .NumOperands: 4, .NumConds: 4 }, |
| 2122 | {.AsmStrOffset: 2460, .AliasCondStart: 504, .NumOperands: 4, .NumConds: 4 }, |
| 2123 | {.AsmStrOffset: 2479, .AliasCondStart: 508, .NumOperands: 4, .NumConds: 4 }, |
| 2124 | {.AsmStrOffset: 2498, .AliasCondStart: 512, .NumOperands: 4, .NumConds: 4 }, |
| 2125 | {.AsmStrOffset: 2518, .AliasCondStart: 516, .NumOperands: 4, .NumConds: 4 }, |
| 2126 | {.AsmStrOffset: 2538, .AliasCondStart: 520, .NumOperands: 4, .NumConds: 4 }, |
| 2127 | {.AsmStrOffset: 2557, .AliasCondStart: 524, .NumOperands: 4, .NumConds: 4 }, |
| 2128 | // SP::CWBCONDrr - 154 |
| 2129 | {.AsmStrOffset: 2310, .AliasCondStart: 528, .NumOperands: 4, .NumConds: 5 }, |
| 2130 | {.AsmStrOffset: 2329, .AliasCondStart: 533, .NumOperands: 4, .NumConds: 5 }, |
| 2131 | {.AsmStrOffset: 2347, .AliasCondStart: 538, .NumOperands: 4, .NumConds: 5 }, |
| 2132 | {.AsmStrOffset: 2365, .AliasCondStart: 543, .NumOperands: 4, .NumConds: 5 }, |
| 2133 | {.AsmStrOffset: 2384, .AliasCondStart: 548, .NumOperands: 4, .NumConds: 5 }, |
| 2134 | {.AsmStrOffset: 2403, .AliasCondStart: 553, .NumOperands: 4, .NumConds: 5 }, |
| 2135 | {.AsmStrOffset: 2421, .AliasCondStart: 558, .NumOperands: 4, .NumConds: 5 }, |
| 2136 | {.AsmStrOffset: 2440, .AliasCondStart: 563, .NumOperands: 4, .NumConds: 5 }, |
| 2137 | {.AsmStrOffset: 2460, .AliasCondStart: 568, .NumOperands: 4, .NumConds: 5 }, |
| 2138 | {.AsmStrOffset: 2479, .AliasCondStart: 573, .NumOperands: 4, .NumConds: 5 }, |
| 2139 | {.AsmStrOffset: 2498, .AliasCondStart: 578, .NumOperands: 4, .NumConds: 5 }, |
| 2140 | {.AsmStrOffset: 2518, .AliasCondStart: 583, .NumOperands: 4, .NumConds: 5 }, |
| 2141 | {.AsmStrOffset: 2538, .AliasCondStart: 588, .NumOperands: 4, .NumConds: 5 }, |
| 2142 | {.AsmStrOffset: 2557, .AliasCondStart: 593, .NumOperands: 4, .NumConds: 5 }, |
| 2143 | // SP::CXBCONDri - 168 |
| 2144 | {.AsmStrOffset: 2576, .AliasCondStart: 598, .NumOperands: 4, .NumConds: 4 }, |
| 2145 | {.AsmStrOffset: 2595, .AliasCondStart: 602, .NumOperands: 4, .NumConds: 4 }, |
| 2146 | {.AsmStrOffset: 2613, .AliasCondStart: 606, .NumOperands: 4, .NumConds: 4 }, |
| 2147 | {.AsmStrOffset: 2631, .AliasCondStart: 610, .NumOperands: 4, .NumConds: 4 }, |
| 2148 | {.AsmStrOffset: 2650, .AliasCondStart: 614, .NumOperands: 4, .NumConds: 4 }, |
| 2149 | {.AsmStrOffset: 2669, .AliasCondStart: 618, .NumOperands: 4, .NumConds: 4 }, |
| 2150 | {.AsmStrOffset: 2687, .AliasCondStart: 622, .NumOperands: 4, .NumConds: 4 }, |
| 2151 | {.AsmStrOffset: 2706, .AliasCondStart: 626, .NumOperands: 4, .NumConds: 4 }, |
| 2152 | {.AsmStrOffset: 2726, .AliasCondStart: 630, .NumOperands: 4, .NumConds: 4 }, |
| 2153 | {.AsmStrOffset: 2745, .AliasCondStart: 634, .NumOperands: 4, .NumConds: 4 }, |
| 2154 | {.AsmStrOffset: 2764, .AliasCondStart: 638, .NumOperands: 4, .NumConds: 4 }, |
| 2155 | {.AsmStrOffset: 2784, .AliasCondStart: 642, .NumOperands: 4, .NumConds: 4 }, |
| 2156 | {.AsmStrOffset: 2804, .AliasCondStart: 646, .NumOperands: 4, .NumConds: 4 }, |
| 2157 | {.AsmStrOffset: 2823, .AliasCondStart: 650, .NumOperands: 4, .NumConds: 4 }, |
| 2158 | // SP::CXBCONDrr - 182 |
| 2159 | {.AsmStrOffset: 2576, .AliasCondStart: 654, .NumOperands: 4, .NumConds: 5 }, |
| 2160 | {.AsmStrOffset: 2595, .AliasCondStart: 659, .NumOperands: 4, .NumConds: 5 }, |
| 2161 | {.AsmStrOffset: 2613, .AliasCondStart: 664, .NumOperands: 4, .NumConds: 5 }, |
| 2162 | {.AsmStrOffset: 2631, .AliasCondStart: 669, .NumOperands: 4, .NumConds: 5 }, |
| 2163 | {.AsmStrOffset: 2650, .AliasCondStart: 674, .NumOperands: 4, .NumConds: 5 }, |
| 2164 | {.AsmStrOffset: 2669, .AliasCondStart: 679, .NumOperands: 4, .NumConds: 5 }, |
| 2165 | {.AsmStrOffset: 2687, .AliasCondStart: 684, .NumOperands: 4, .NumConds: 5 }, |
| 2166 | {.AsmStrOffset: 2706, .AliasCondStart: 689, .NumOperands: 4, .NumConds: 5 }, |
| 2167 | {.AsmStrOffset: 2726, .AliasCondStart: 694, .NumOperands: 4, .NumConds: 5 }, |
| 2168 | {.AsmStrOffset: 2745, .AliasCondStart: 699, .NumOperands: 4, .NumConds: 5 }, |
| 2169 | {.AsmStrOffset: 2764, .AliasCondStart: 704, .NumOperands: 4, .NumConds: 5 }, |
| 2170 | {.AsmStrOffset: 2784, .AliasCondStart: 709, .NumOperands: 4, .NumConds: 5 }, |
| 2171 | {.AsmStrOffset: 2804, .AliasCondStart: 714, .NumOperands: 4, .NumConds: 5 }, |
| 2172 | {.AsmStrOffset: 2823, .AliasCondStart: 719, .NumOperands: 4, .NumConds: 5 }, |
| 2173 | // SP::FMOVD_ICC - 196 |
| 2174 | {.AsmStrOffset: 2842, .AliasCondStart: 724, .NumOperands: 4, .NumConds: 5 }, |
| 2175 | {.AsmStrOffset: 2862, .AliasCondStart: 729, .NumOperands: 4, .NumConds: 6 }, |
| 2176 | {.AsmStrOffset: 2882, .AliasCondStart: 735, .NumOperands: 4, .NumConds: 5 }, |
| 2177 | {.AsmStrOffset: 2902, .AliasCondStart: 740, .NumOperands: 4, .NumConds: 6 }, |
| 2178 | {.AsmStrOffset: 2922, .AliasCondStart: 746, .NumOperands: 4, .NumConds: 5 }, |
| 2179 | {.AsmStrOffset: 2943, .AliasCondStart: 751, .NumOperands: 4, .NumConds: 6 }, |
| 2180 | {.AsmStrOffset: 2964, .AliasCondStart: 757, .NumOperands: 4, .NumConds: 5 }, |
| 2181 | {.AsmStrOffset: 2984, .AliasCondStart: 762, .NumOperands: 4, .NumConds: 6 }, |
| 2182 | {.AsmStrOffset: 3004, .AliasCondStart: 768, .NumOperands: 4, .NumConds: 5 }, |
| 2183 | {.AsmStrOffset: 3024, .AliasCondStart: 773, .NumOperands: 4, .NumConds: 6 }, |
| 2184 | {.AsmStrOffset: 3044, .AliasCondStart: 779, .NumOperands: 4, .NumConds: 5 }, |
| 2185 | {.AsmStrOffset: 3065, .AliasCondStart: 784, .NumOperands: 4, .NumConds: 6 }, |
| 2186 | {.AsmStrOffset: 3086, .AliasCondStart: 790, .NumOperands: 4, .NumConds: 5 }, |
| 2187 | {.AsmStrOffset: 3107, .AliasCondStart: 795, .NumOperands: 4, .NumConds: 6 }, |
| 2188 | {.AsmStrOffset: 3128, .AliasCondStart: 801, .NumOperands: 4, .NumConds: 5 }, |
| 2189 | {.AsmStrOffset: 3148, .AliasCondStart: 806, .NumOperands: 4, .NumConds: 6 }, |
| 2190 | {.AsmStrOffset: 3168, .AliasCondStart: 812, .NumOperands: 4, .NumConds: 5 }, |
| 2191 | {.AsmStrOffset: 3189, .AliasCondStart: 817, .NumOperands: 4, .NumConds: 6 }, |
| 2192 | {.AsmStrOffset: 3210, .AliasCondStart: 823, .NumOperands: 4, .NumConds: 5 }, |
| 2193 | {.AsmStrOffset: 3232, .AliasCondStart: 828, .NumOperands: 4, .NumConds: 6 }, |
| 2194 | {.AsmStrOffset: 3254, .AliasCondStart: 834, .NumOperands: 4, .NumConds: 5 }, |
| 2195 | {.AsmStrOffset: 3275, .AliasCondStart: 839, .NumOperands: 4, .NumConds: 6 }, |
| 2196 | {.AsmStrOffset: 3296, .AliasCondStart: 845, .NumOperands: 4, .NumConds: 5 }, |
| 2197 | {.AsmStrOffset: 3317, .AliasCondStart: 850, .NumOperands: 4, .NumConds: 6 }, |
| 2198 | {.AsmStrOffset: 3338, .AliasCondStart: 856, .NumOperands: 4, .NumConds: 5 }, |
| 2199 | {.AsmStrOffset: 3360, .AliasCondStart: 861, .NumOperands: 4, .NumConds: 6 }, |
| 2200 | {.AsmStrOffset: 3382, .AliasCondStart: 867, .NumOperands: 4, .NumConds: 5 }, |
| 2201 | {.AsmStrOffset: 3404, .AliasCondStart: 872, .NumOperands: 4, .NumConds: 6 }, |
| 2202 | {.AsmStrOffset: 3426, .AliasCondStart: 878, .NumOperands: 4, .NumConds: 5 }, |
| 2203 | {.AsmStrOffset: 3447, .AliasCondStart: 883, .NumOperands: 4, .NumConds: 6 }, |
| 2204 | {.AsmStrOffset: 3468, .AliasCondStart: 889, .NumOperands: 4, .NumConds: 5 }, |
| 2205 | {.AsmStrOffset: 3489, .AliasCondStart: 894, .NumOperands: 4, .NumConds: 6 }, |
| 2206 | // SP::FMOVQ_ICC - 228 |
| 2207 | {.AsmStrOffset: 3510, .AliasCondStart: 900, .NumOperands: 4, .NumConds: 5 }, |
| 2208 | {.AsmStrOffset: 3530, .AliasCondStart: 905, .NumOperands: 4, .NumConds: 6 }, |
| 2209 | {.AsmStrOffset: 3550, .AliasCondStart: 911, .NumOperands: 4, .NumConds: 5 }, |
| 2210 | {.AsmStrOffset: 3570, .AliasCondStart: 916, .NumOperands: 4, .NumConds: 6 }, |
| 2211 | {.AsmStrOffset: 3590, .AliasCondStart: 922, .NumOperands: 4, .NumConds: 5 }, |
| 2212 | {.AsmStrOffset: 3611, .AliasCondStart: 927, .NumOperands: 4, .NumConds: 6 }, |
| 2213 | {.AsmStrOffset: 3632, .AliasCondStart: 933, .NumOperands: 4, .NumConds: 5 }, |
| 2214 | {.AsmStrOffset: 3652, .AliasCondStart: 938, .NumOperands: 4, .NumConds: 6 }, |
| 2215 | {.AsmStrOffset: 3672, .AliasCondStart: 944, .NumOperands: 4, .NumConds: 5 }, |
| 2216 | {.AsmStrOffset: 3692, .AliasCondStart: 949, .NumOperands: 4, .NumConds: 6 }, |
| 2217 | {.AsmStrOffset: 3712, .AliasCondStart: 955, .NumOperands: 4, .NumConds: 5 }, |
| 2218 | {.AsmStrOffset: 3733, .AliasCondStart: 960, .NumOperands: 4, .NumConds: 6 }, |
| 2219 | {.AsmStrOffset: 3754, .AliasCondStart: 966, .NumOperands: 4, .NumConds: 5 }, |
| 2220 | {.AsmStrOffset: 3775, .AliasCondStart: 971, .NumOperands: 4, .NumConds: 6 }, |
| 2221 | {.AsmStrOffset: 3796, .AliasCondStart: 977, .NumOperands: 4, .NumConds: 5 }, |
| 2222 | {.AsmStrOffset: 3816, .AliasCondStart: 982, .NumOperands: 4, .NumConds: 6 }, |
| 2223 | {.AsmStrOffset: 3836, .AliasCondStart: 988, .NumOperands: 4, .NumConds: 5 }, |
| 2224 | {.AsmStrOffset: 3857, .AliasCondStart: 993, .NumOperands: 4, .NumConds: 6 }, |
| 2225 | {.AsmStrOffset: 3878, .AliasCondStart: 999, .NumOperands: 4, .NumConds: 5 }, |
| 2226 | {.AsmStrOffset: 3900, .AliasCondStart: 1004, .NumOperands: 4, .NumConds: 6 }, |
| 2227 | {.AsmStrOffset: 3922, .AliasCondStart: 1010, .NumOperands: 4, .NumConds: 5 }, |
| 2228 | {.AsmStrOffset: 3943, .AliasCondStart: 1015, .NumOperands: 4, .NumConds: 6 }, |
| 2229 | {.AsmStrOffset: 3964, .AliasCondStart: 1021, .NumOperands: 4, .NumConds: 5 }, |
| 2230 | {.AsmStrOffset: 3985, .AliasCondStart: 1026, .NumOperands: 4, .NumConds: 6 }, |
| 2231 | {.AsmStrOffset: 4006, .AliasCondStart: 1032, .NumOperands: 4, .NumConds: 5 }, |
| 2232 | {.AsmStrOffset: 4028, .AliasCondStart: 1037, .NumOperands: 4, .NumConds: 6 }, |
| 2233 | {.AsmStrOffset: 4050, .AliasCondStart: 1043, .NumOperands: 4, .NumConds: 5 }, |
| 2234 | {.AsmStrOffset: 4072, .AliasCondStart: 1048, .NumOperands: 4, .NumConds: 6 }, |
| 2235 | {.AsmStrOffset: 4094, .AliasCondStart: 1054, .NumOperands: 4, .NumConds: 5 }, |
| 2236 | {.AsmStrOffset: 4115, .AliasCondStart: 1059, .NumOperands: 4, .NumConds: 6 }, |
| 2237 | {.AsmStrOffset: 4136, .AliasCondStart: 1065, .NumOperands: 4, .NumConds: 5 }, |
| 2238 | {.AsmStrOffset: 4157, .AliasCondStart: 1070, .NumOperands: 4, .NumConds: 6 }, |
| 2239 | // SP::FMOVRD - 260 |
| 2240 | {.AsmStrOffset: 4178, .AliasCondStart: 1076, .NumOperands: 5, .NumConds: 6 }, |
| 2241 | {.AsmStrOffset: 4199, .AliasCondStart: 1082, .NumOperands: 5, .NumConds: 6 }, |
| 2242 | {.AsmStrOffset: 4219, .AliasCondStart: 1088, .NumOperands: 5, .NumConds: 6 }, |
| 2243 | {.AsmStrOffset: 4239, .AliasCondStart: 1094, .NumOperands: 5, .NumConds: 6 }, |
| 2244 | // SP::FMOVRQ - 264 |
| 2245 | {.AsmStrOffset: 4260, .AliasCondStart: 1100, .NumOperands: 5, .NumConds: 6 }, |
| 2246 | {.AsmStrOffset: 4281, .AliasCondStart: 1106, .NumOperands: 5, .NumConds: 6 }, |
| 2247 | {.AsmStrOffset: 4301, .AliasCondStart: 1112, .NumOperands: 5, .NumConds: 6 }, |
| 2248 | {.AsmStrOffset: 4321, .AliasCondStart: 1118, .NumOperands: 5, .NumConds: 6 }, |
| 2249 | // SP::FMOVRS - 268 |
| 2250 | {.AsmStrOffset: 4342, .AliasCondStart: 1124, .NumOperands: 5, .NumConds: 6 }, |
| 2251 | {.AsmStrOffset: 4363, .AliasCondStart: 1130, .NumOperands: 5, .NumConds: 6 }, |
| 2252 | {.AsmStrOffset: 4383, .AliasCondStart: 1136, .NumOperands: 5, .NumConds: 6 }, |
| 2253 | {.AsmStrOffset: 4403, .AliasCondStart: 1142, .NumOperands: 5, .NumConds: 6 }, |
| 2254 | // SP::FMOVS_ICC - 272 |
| 2255 | {.AsmStrOffset: 4424, .AliasCondStart: 1148, .NumOperands: 4, .NumConds: 5 }, |
| 2256 | {.AsmStrOffset: 4444, .AliasCondStart: 1153, .NumOperands: 4, .NumConds: 6 }, |
| 2257 | {.AsmStrOffset: 4464, .AliasCondStart: 1159, .NumOperands: 4, .NumConds: 5 }, |
| 2258 | {.AsmStrOffset: 4484, .AliasCondStart: 1164, .NumOperands: 4, .NumConds: 6 }, |
| 2259 | {.AsmStrOffset: 4504, .AliasCondStart: 1170, .NumOperands: 4, .NumConds: 5 }, |
| 2260 | {.AsmStrOffset: 4525, .AliasCondStart: 1175, .NumOperands: 4, .NumConds: 6 }, |
| 2261 | {.AsmStrOffset: 4546, .AliasCondStart: 1181, .NumOperands: 4, .NumConds: 5 }, |
| 2262 | {.AsmStrOffset: 4566, .AliasCondStart: 1186, .NumOperands: 4, .NumConds: 6 }, |
| 2263 | {.AsmStrOffset: 4586, .AliasCondStart: 1192, .NumOperands: 4, .NumConds: 5 }, |
| 2264 | {.AsmStrOffset: 4606, .AliasCondStart: 1197, .NumOperands: 4, .NumConds: 6 }, |
| 2265 | {.AsmStrOffset: 4626, .AliasCondStart: 1203, .NumOperands: 4, .NumConds: 5 }, |
| 2266 | {.AsmStrOffset: 4647, .AliasCondStart: 1208, .NumOperands: 4, .NumConds: 6 }, |
| 2267 | {.AsmStrOffset: 4668, .AliasCondStart: 1214, .NumOperands: 4, .NumConds: 5 }, |
| 2268 | {.AsmStrOffset: 4689, .AliasCondStart: 1219, .NumOperands: 4, .NumConds: 6 }, |
| 2269 | {.AsmStrOffset: 4710, .AliasCondStart: 1225, .NumOperands: 4, .NumConds: 5 }, |
| 2270 | {.AsmStrOffset: 4730, .AliasCondStart: 1230, .NumOperands: 4, .NumConds: 6 }, |
| 2271 | {.AsmStrOffset: 4750, .AliasCondStart: 1236, .NumOperands: 4, .NumConds: 5 }, |
| 2272 | {.AsmStrOffset: 4771, .AliasCondStart: 1241, .NumOperands: 4, .NumConds: 6 }, |
| 2273 | {.AsmStrOffset: 4792, .AliasCondStart: 1247, .NumOperands: 4, .NumConds: 5 }, |
| 2274 | {.AsmStrOffset: 4814, .AliasCondStart: 1252, .NumOperands: 4, .NumConds: 6 }, |
| 2275 | {.AsmStrOffset: 4836, .AliasCondStart: 1258, .NumOperands: 4, .NumConds: 5 }, |
| 2276 | {.AsmStrOffset: 4857, .AliasCondStart: 1263, .NumOperands: 4, .NumConds: 6 }, |
| 2277 | {.AsmStrOffset: 4878, .AliasCondStart: 1269, .NumOperands: 4, .NumConds: 5 }, |
| 2278 | {.AsmStrOffset: 4899, .AliasCondStart: 1274, .NumOperands: 4, .NumConds: 6 }, |
| 2279 | {.AsmStrOffset: 4920, .AliasCondStart: 1280, .NumOperands: 4, .NumConds: 5 }, |
| 2280 | {.AsmStrOffset: 4942, .AliasCondStart: 1285, .NumOperands: 4, .NumConds: 6 }, |
| 2281 | {.AsmStrOffset: 4964, .AliasCondStart: 1291, .NumOperands: 4, .NumConds: 5 }, |
| 2282 | {.AsmStrOffset: 4986, .AliasCondStart: 1296, .NumOperands: 4, .NumConds: 6 }, |
| 2283 | {.AsmStrOffset: 5008, .AliasCondStart: 1302, .NumOperands: 4, .NumConds: 5 }, |
| 2284 | {.AsmStrOffset: 5029, .AliasCondStart: 1307, .NumOperands: 4, .NumConds: 6 }, |
| 2285 | {.AsmStrOffset: 5050, .AliasCondStart: 1313, .NumOperands: 4, .NumConds: 5 }, |
| 2286 | {.AsmStrOffset: 5071, .AliasCondStart: 1318, .NumOperands: 4, .NumConds: 6 }, |
| 2287 | // SP::MOVICCri - 304 |
| 2288 | {.AsmStrOffset: 5092, .AliasCondStart: 1324, .NumOperands: 4, .NumConds: 5 }, |
| 2289 | {.AsmStrOffset: 5110, .AliasCondStart: 1329, .NumOperands: 4, .NumConds: 6 }, |
| 2290 | {.AsmStrOffset: 5128, .AliasCondStart: 1335, .NumOperands: 4, .NumConds: 5 }, |
| 2291 | {.AsmStrOffset: 5146, .AliasCondStart: 1340, .NumOperands: 4, .NumConds: 6 }, |
| 2292 | {.AsmStrOffset: 5164, .AliasCondStart: 1346, .NumOperands: 4, .NumConds: 5 }, |
| 2293 | {.AsmStrOffset: 5183, .AliasCondStart: 1351, .NumOperands: 4, .NumConds: 6 }, |
| 2294 | {.AsmStrOffset: 5202, .AliasCondStart: 1357, .NumOperands: 4, .NumConds: 5 }, |
| 2295 | {.AsmStrOffset: 5220, .AliasCondStart: 1362, .NumOperands: 4, .NumConds: 6 }, |
| 2296 | {.AsmStrOffset: 5238, .AliasCondStart: 1368, .NumOperands: 4, .NumConds: 5 }, |
| 2297 | {.AsmStrOffset: 5256, .AliasCondStart: 1373, .NumOperands: 4, .NumConds: 6 }, |
| 2298 | {.AsmStrOffset: 5274, .AliasCondStart: 1379, .NumOperands: 4, .NumConds: 5 }, |
| 2299 | {.AsmStrOffset: 5293, .AliasCondStart: 1384, .NumOperands: 4, .NumConds: 6 }, |
| 2300 | {.AsmStrOffset: 5312, .AliasCondStart: 1390, .NumOperands: 4, .NumConds: 5 }, |
| 2301 | {.AsmStrOffset: 5331, .AliasCondStart: 1395, .NumOperands: 4, .NumConds: 6 }, |
| 2302 | {.AsmStrOffset: 5350, .AliasCondStart: 1401, .NumOperands: 4, .NumConds: 5 }, |
| 2303 | {.AsmStrOffset: 5368, .AliasCondStart: 1406, .NumOperands: 4, .NumConds: 6 }, |
| 2304 | {.AsmStrOffset: 5386, .AliasCondStart: 1412, .NumOperands: 4, .NumConds: 5 }, |
| 2305 | {.AsmStrOffset: 5405, .AliasCondStart: 1417, .NumOperands: 4, .NumConds: 6 }, |
| 2306 | {.AsmStrOffset: 5424, .AliasCondStart: 1423, .NumOperands: 4, .NumConds: 5 }, |
| 2307 | {.AsmStrOffset: 5444, .AliasCondStart: 1428, .NumOperands: 4, .NumConds: 6 }, |
| 2308 | {.AsmStrOffset: 5464, .AliasCondStart: 1434, .NumOperands: 4, .NumConds: 5 }, |
| 2309 | {.AsmStrOffset: 5483, .AliasCondStart: 1439, .NumOperands: 4, .NumConds: 6 }, |
| 2310 | {.AsmStrOffset: 5502, .AliasCondStart: 1445, .NumOperands: 4, .NumConds: 5 }, |
| 2311 | {.AsmStrOffset: 5521, .AliasCondStart: 1450, .NumOperands: 4, .NumConds: 6 }, |
| 2312 | {.AsmStrOffset: 5540, .AliasCondStart: 1456, .NumOperands: 4, .NumConds: 5 }, |
| 2313 | {.AsmStrOffset: 5560, .AliasCondStart: 1461, .NumOperands: 4, .NumConds: 6 }, |
| 2314 | {.AsmStrOffset: 5580, .AliasCondStart: 1467, .NumOperands: 4, .NumConds: 5 }, |
| 2315 | {.AsmStrOffset: 5600, .AliasCondStart: 1472, .NumOperands: 4, .NumConds: 6 }, |
| 2316 | {.AsmStrOffset: 5620, .AliasCondStart: 1478, .NumOperands: 4, .NumConds: 5 }, |
| 2317 | {.AsmStrOffset: 5639, .AliasCondStart: 1483, .NumOperands: 4, .NumConds: 6 }, |
| 2318 | {.AsmStrOffset: 5658, .AliasCondStart: 1489, .NumOperands: 4, .NumConds: 5 }, |
| 2319 | {.AsmStrOffset: 5677, .AliasCondStart: 1494, .NumOperands: 4, .NumConds: 6 }, |
| 2320 | // SP::MOVICCrr - 336 |
| 2321 | {.AsmStrOffset: 5092, .AliasCondStart: 1500, .NumOperands: 4, .NumConds: 5 }, |
| 2322 | {.AsmStrOffset: 5110, .AliasCondStart: 1505, .NumOperands: 4, .NumConds: 6 }, |
| 2323 | {.AsmStrOffset: 5128, .AliasCondStart: 1511, .NumOperands: 4, .NumConds: 5 }, |
| 2324 | {.AsmStrOffset: 5146, .AliasCondStart: 1516, .NumOperands: 4, .NumConds: 6 }, |
| 2325 | {.AsmStrOffset: 5164, .AliasCondStart: 1522, .NumOperands: 4, .NumConds: 5 }, |
| 2326 | {.AsmStrOffset: 5183, .AliasCondStart: 1527, .NumOperands: 4, .NumConds: 6 }, |
| 2327 | {.AsmStrOffset: 5202, .AliasCondStart: 1533, .NumOperands: 4, .NumConds: 5 }, |
| 2328 | {.AsmStrOffset: 5220, .AliasCondStart: 1538, .NumOperands: 4, .NumConds: 6 }, |
| 2329 | {.AsmStrOffset: 5238, .AliasCondStart: 1544, .NumOperands: 4, .NumConds: 5 }, |
| 2330 | {.AsmStrOffset: 5256, .AliasCondStart: 1549, .NumOperands: 4, .NumConds: 6 }, |
| 2331 | {.AsmStrOffset: 5274, .AliasCondStart: 1555, .NumOperands: 4, .NumConds: 5 }, |
| 2332 | {.AsmStrOffset: 5293, .AliasCondStart: 1560, .NumOperands: 4, .NumConds: 6 }, |
| 2333 | {.AsmStrOffset: 5312, .AliasCondStart: 1566, .NumOperands: 4, .NumConds: 5 }, |
| 2334 | {.AsmStrOffset: 5331, .AliasCondStart: 1571, .NumOperands: 4, .NumConds: 6 }, |
| 2335 | {.AsmStrOffset: 5350, .AliasCondStart: 1577, .NumOperands: 4, .NumConds: 5 }, |
| 2336 | {.AsmStrOffset: 5368, .AliasCondStart: 1582, .NumOperands: 4, .NumConds: 6 }, |
| 2337 | {.AsmStrOffset: 5386, .AliasCondStart: 1588, .NumOperands: 4, .NumConds: 5 }, |
| 2338 | {.AsmStrOffset: 5405, .AliasCondStart: 1593, .NumOperands: 4, .NumConds: 6 }, |
| 2339 | {.AsmStrOffset: 5424, .AliasCondStart: 1599, .NumOperands: 4, .NumConds: 5 }, |
| 2340 | {.AsmStrOffset: 5444, .AliasCondStart: 1604, .NumOperands: 4, .NumConds: 6 }, |
| 2341 | {.AsmStrOffset: 5464, .AliasCondStart: 1610, .NumOperands: 4, .NumConds: 5 }, |
| 2342 | {.AsmStrOffset: 5483, .AliasCondStart: 1615, .NumOperands: 4, .NumConds: 6 }, |
| 2343 | {.AsmStrOffset: 5502, .AliasCondStart: 1621, .NumOperands: 4, .NumConds: 5 }, |
| 2344 | {.AsmStrOffset: 5521, .AliasCondStart: 1626, .NumOperands: 4, .NumConds: 6 }, |
| 2345 | {.AsmStrOffset: 5540, .AliasCondStart: 1632, .NumOperands: 4, .NumConds: 5 }, |
| 2346 | {.AsmStrOffset: 5560, .AliasCondStart: 1637, .NumOperands: 4, .NumConds: 6 }, |
| 2347 | {.AsmStrOffset: 5580, .AliasCondStart: 1643, .NumOperands: 4, .NumConds: 5 }, |
| 2348 | {.AsmStrOffset: 5600, .AliasCondStart: 1648, .NumOperands: 4, .NumConds: 6 }, |
| 2349 | {.AsmStrOffset: 5620, .AliasCondStart: 1654, .NumOperands: 4, .NumConds: 5 }, |
| 2350 | {.AsmStrOffset: 5639, .AliasCondStart: 1659, .NumOperands: 4, .NumConds: 6 }, |
| 2351 | {.AsmStrOffset: 5658, .AliasCondStart: 1665, .NumOperands: 4, .NumConds: 5 }, |
| 2352 | {.AsmStrOffset: 5677, .AliasCondStart: 1670, .NumOperands: 4, .NumConds: 6 }, |
| 2353 | // SP::MOVRri - 368 |
| 2354 | {.AsmStrOffset: 5696, .AliasCondStart: 1676, .NumOperands: 5, .NumConds: 6 }, |
| 2355 | {.AsmStrOffset: 5715, .AliasCondStart: 1682, .NumOperands: 5, .NumConds: 6 }, |
| 2356 | {.AsmStrOffset: 5733, .AliasCondStart: 1688, .NumOperands: 5, .NumConds: 6 }, |
| 2357 | {.AsmStrOffset: 5751, .AliasCondStart: 1694, .NumOperands: 5, .NumConds: 6 }, |
| 2358 | // SP::MOVRrr - 372 |
| 2359 | {.AsmStrOffset: 5696, .AliasCondStart: 1700, .NumOperands: 5, .NumConds: 6 }, |
| 2360 | {.AsmStrOffset: 5715, .AliasCondStart: 1706, .NumOperands: 5, .NumConds: 6 }, |
| 2361 | {.AsmStrOffset: 5733, .AliasCondStart: 1712, .NumOperands: 5, .NumConds: 6 }, |
| 2362 | {.AsmStrOffset: 5751, .AliasCondStart: 1718, .NumOperands: 5, .NumConds: 6 }, |
| 2363 | // SP::ORCCrr - 376 |
| 2364 | {.AsmStrOffset: 5770, .AliasCondStart: 1724, .NumOperands: 3, .NumConds: 3 }, |
| 2365 | // SP::ORri - 377 |
| 2366 | {.AsmStrOffset: 5777, .AliasCondStart: 1727, .NumOperands: 3, .NumConds: 2 }, |
| 2367 | // SP::ORrr - 378 |
| 2368 | {.AsmStrOffset: 5777, .AliasCondStart: 1729, .NumOperands: 3, .NumConds: 3 }, |
| 2369 | // SP::RESTORErr - 379 |
| 2370 | {.AsmStrOffset: 5788, .AliasCondStart: 1732, .NumOperands: 3, .NumConds: 3 }, |
| 2371 | // SP::RET - 380 |
| 2372 | {.AsmStrOffset: 5796, .AliasCondStart: 1735, .NumOperands: 1, .NumConds: 1 }, |
| 2373 | // SP::RETL - 381 |
| 2374 | {.AsmStrOffset: 5800, .AliasCondStart: 1736, .NumOperands: 1, .NumConds: 1 }, |
| 2375 | // SP::SAVErr - 382 |
| 2376 | {.AsmStrOffset: 5805, .AliasCondStart: 1737, .NumOperands: 3, .NumConds: 3 }, |
| 2377 | // SP::SUBCCri - 383 |
| 2378 | {.AsmStrOffset: 5810, .AliasCondStart: 1740, .NumOperands: 3, .NumConds: 2 }, |
| 2379 | // SP::SUBCCrr - 384 |
| 2380 | {.AsmStrOffset: 5810, .AliasCondStart: 1742, .NumOperands: 3, .NumConds: 3 }, |
| 2381 | // SP::TICCri - 385 |
| 2382 | {.AsmStrOffset: 5821, .AliasCondStart: 1745, .NumOperands: 3, .NumConds: 4 }, |
| 2383 | {.AsmStrOffset: 5833, .AliasCondStart: 1749, .NumOperands: 3, .NumConds: 5 }, |
| 2384 | {.AsmStrOffset: 5845, .AliasCondStart: 1754, .NumOperands: 3, .NumConds: 4 }, |
| 2385 | {.AsmStrOffset: 5862, .AliasCondStart: 1758, .NumOperands: 3, .NumConds: 5 }, |
| 2386 | {.AsmStrOffset: 5879, .AliasCondStart: 1763, .NumOperands: 3, .NumConds: 4 }, |
| 2387 | {.AsmStrOffset: 5891, .AliasCondStart: 1767, .NumOperands: 3, .NumConds: 5 }, |
| 2388 | {.AsmStrOffset: 5903, .AliasCondStart: 1772, .NumOperands: 3, .NumConds: 4 }, |
| 2389 | {.AsmStrOffset: 5920, .AliasCondStart: 1776, .NumOperands: 3, .NumConds: 5 }, |
| 2390 | {.AsmStrOffset: 5937, .AliasCondStart: 1781, .NumOperands: 3, .NumConds: 4 }, |
| 2391 | {.AsmStrOffset: 5950, .AliasCondStart: 1785, .NumOperands: 3, .NumConds: 5 }, |
| 2392 | {.AsmStrOffset: 5963, .AliasCondStart: 1790, .NumOperands: 3, .NumConds: 4 }, |
| 2393 | {.AsmStrOffset: 5981, .AliasCondStart: 1794, .NumOperands: 3, .NumConds: 5 }, |
| 2394 | {.AsmStrOffset: 5999, .AliasCondStart: 1799, .NumOperands: 3, .NumConds: 4 }, |
| 2395 | {.AsmStrOffset: 6011, .AliasCondStart: 1803, .NumOperands: 3, .NumConds: 5 }, |
| 2396 | {.AsmStrOffset: 6023, .AliasCondStart: 1808, .NumOperands: 3, .NumConds: 4 }, |
| 2397 | {.AsmStrOffset: 6040, .AliasCondStart: 1812, .NumOperands: 3, .NumConds: 5 }, |
| 2398 | {.AsmStrOffset: 6057, .AliasCondStart: 1817, .NumOperands: 3, .NumConds: 4 }, |
| 2399 | {.AsmStrOffset: 6069, .AliasCondStart: 1821, .NumOperands: 3, .NumConds: 5 }, |
| 2400 | {.AsmStrOffset: 6081, .AliasCondStart: 1826, .NumOperands: 3, .NumConds: 4 }, |
| 2401 | {.AsmStrOffset: 6098, .AliasCondStart: 1830, .NumOperands: 3, .NumConds: 5 }, |
| 2402 | {.AsmStrOffset: 6115, .AliasCondStart: 1835, .NumOperands: 3, .NumConds: 4 }, |
| 2403 | {.AsmStrOffset: 6128, .AliasCondStart: 1839, .NumOperands: 3, .NumConds: 5 }, |
| 2404 | {.AsmStrOffset: 6141, .AliasCondStart: 1844, .NumOperands: 3, .NumConds: 4 }, |
| 2405 | {.AsmStrOffset: 6159, .AliasCondStart: 1848, .NumOperands: 3, .NumConds: 5 }, |
| 2406 | {.AsmStrOffset: 6177, .AliasCondStart: 1853, .NumOperands: 3, .NumConds: 4 }, |
| 2407 | {.AsmStrOffset: 6190, .AliasCondStart: 1857, .NumOperands: 3, .NumConds: 5 }, |
| 2408 | {.AsmStrOffset: 6203, .AliasCondStart: 1862, .NumOperands: 3, .NumConds: 4 }, |
| 2409 | {.AsmStrOffset: 6221, .AliasCondStart: 1866, .NumOperands: 3, .NumConds: 5 }, |
| 2410 | {.AsmStrOffset: 6239, .AliasCondStart: 1871, .NumOperands: 3, .NumConds: 4 }, |
| 2411 | {.AsmStrOffset: 6251, .AliasCondStart: 1875, .NumOperands: 3, .NumConds: 5 }, |
| 2412 | {.AsmStrOffset: 6263, .AliasCondStart: 1880, .NumOperands: 3, .NumConds: 4 }, |
| 2413 | {.AsmStrOffset: 6280, .AliasCondStart: 1884, .NumOperands: 3, .NumConds: 5 }, |
| 2414 | {.AsmStrOffset: 6297, .AliasCondStart: 1889, .NumOperands: 3, .NumConds: 4 }, |
| 2415 | {.AsmStrOffset: 6310, .AliasCondStart: 1893, .NumOperands: 3, .NumConds: 5 }, |
| 2416 | {.AsmStrOffset: 6323, .AliasCondStart: 1898, .NumOperands: 3, .NumConds: 4 }, |
| 2417 | {.AsmStrOffset: 6341, .AliasCondStart: 1902, .NumOperands: 3, .NumConds: 5 }, |
| 2418 | {.AsmStrOffset: 6359, .AliasCondStart: 1907, .NumOperands: 3, .NumConds: 4 }, |
| 2419 | {.AsmStrOffset: 6373, .AliasCondStart: 1911, .NumOperands: 3, .NumConds: 5 }, |
| 2420 | {.AsmStrOffset: 6387, .AliasCondStart: 1916, .NumOperands: 3, .NumConds: 4 }, |
| 2421 | {.AsmStrOffset: 6406, .AliasCondStart: 1920, .NumOperands: 3, .NumConds: 5 }, |
| 2422 | {.AsmStrOffset: 6425, .AliasCondStart: 1925, .NumOperands: 3, .NumConds: 4 }, |
| 2423 | {.AsmStrOffset: 6438, .AliasCondStart: 1929, .NumOperands: 3, .NumConds: 5 }, |
| 2424 | {.AsmStrOffset: 6451, .AliasCondStart: 1934, .NumOperands: 3, .NumConds: 4 }, |
| 2425 | {.AsmStrOffset: 6469, .AliasCondStart: 1938, .NumOperands: 3, .NumConds: 5 }, |
| 2426 | {.AsmStrOffset: 6487, .AliasCondStart: 1943, .NumOperands: 3, .NumConds: 4 }, |
| 2427 | {.AsmStrOffset: 6500, .AliasCondStart: 1947, .NumOperands: 3, .NumConds: 5 }, |
| 2428 | {.AsmStrOffset: 6513, .AliasCondStart: 1952, .NumOperands: 3, .NumConds: 4 }, |
| 2429 | {.AsmStrOffset: 6531, .AliasCondStart: 1956, .NumOperands: 3, .NumConds: 5 }, |
| 2430 | {.AsmStrOffset: 6549, .AliasCondStart: 1961, .NumOperands: 3, .NumConds: 4 }, |
| 2431 | {.AsmStrOffset: 6563, .AliasCondStart: 1965, .NumOperands: 3, .NumConds: 5 }, |
| 2432 | {.AsmStrOffset: 6577, .AliasCondStart: 1970, .NumOperands: 3, .NumConds: 4 }, |
| 2433 | {.AsmStrOffset: 6596, .AliasCondStart: 1974, .NumOperands: 3, .NumConds: 5 }, |
| 2434 | {.AsmStrOffset: 6615, .AliasCondStart: 1979, .NumOperands: 3, .NumConds: 4 }, |
| 2435 | {.AsmStrOffset: 6629, .AliasCondStart: 1983, .NumOperands: 3, .NumConds: 5 }, |
| 2436 | {.AsmStrOffset: 6643, .AliasCondStart: 1988, .NumOperands: 3, .NumConds: 4 }, |
| 2437 | {.AsmStrOffset: 6662, .AliasCondStart: 1992, .NumOperands: 3, .NumConds: 5 }, |
| 2438 | {.AsmStrOffset: 6681, .AliasCondStart: 1997, .NumOperands: 3, .NumConds: 4 }, |
| 2439 | {.AsmStrOffset: 6694, .AliasCondStart: 2001, .NumOperands: 3, .NumConds: 5 }, |
| 2440 | {.AsmStrOffset: 6707, .AliasCondStart: 2006, .NumOperands: 3, .NumConds: 4 }, |
| 2441 | {.AsmStrOffset: 6725, .AliasCondStart: 2010, .NumOperands: 3, .NumConds: 5 }, |
| 2442 | {.AsmStrOffset: 6743, .AliasCondStart: 2015, .NumOperands: 3, .NumConds: 4 }, |
| 2443 | {.AsmStrOffset: 6756, .AliasCondStart: 2019, .NumOperands: 3, .NumConds: 5 }, |
| 2444 | {.AsmStrOffset: 6769, .AliasCondStart: 2024, .NumOperands: 3, .NumConds: 4 }, |
| 2445 | {.AsmStrOffset: 6787, .AliasCondStart: 2028, .NumOperands: 3, .NumConds: 5 }, |
| 2446 | // SP::TICCrr - 449 |
| 2447 | {.AsmStrOffset: 5821, .AliasCondStart: 2033, .NumOperands: 3, .NumConds: 4 }, |
| 2448 | {.AsmStrOffset: 5833, .AliasCondStart: 2037, .NumOperands: 3, .NumConds: 5 }, |
| 2449 | {.AsmStrOffset: 5845, .AliasCondStart: 2042, .NumOperands: 3, .NumConds: 4 }, |
| 2450 | {.AsmStrOffset: 5862, .AliasCondStart: 2046, .NumOperands: 3, .NumConds: 5 }, |
| 2451 | {.AsmStrOffset: 5879, .AliasCondStart: 2051, .NumOperands: 3, .NumConds: 4 }, |
| 2452 | {.AsmStrOffset: 5891, .AliasCondStart: 2055, .NumOperands: 3, .NumConds: 5 }, |
| 2453 | {.AsmStrOffset: 5903, .AliasCondStart: 2060, .NumOperands: 3, .NumConds: 4 }, |
| 2454 | {.AsmStrOffset: 5920, .AliasCondStart: 2064, .NumOperands: 3, .NumConds: 5 }, |
| 2455 | {.AsmStrOffset: 5937, .AliasCondStart: 2069, .NumOperands: 3, .NumConds: 4 }, |
| 2456 | {.AsmStrOffset: 5950, .AliasCondStart: 2073, .NumOperands: 3, .NumConds: 5 }, |
| 2457 | {.AsmStrOffset: 5963, .AliasCondStart: 2078, .NumOperands: 3, .NumConds: 4 }, |
| 2458 | {.AsmStrOffset: 5981, .AliasCondStart: 2082, .NumOperands: 3, .NumConds: 5 }, |
| 2459 | {.AsmStrOffset: 5999, .AliasCondStart: 2087, .NumOperands: 3, .NumConds: 4 }, |
| 2460 | {.AsmStrOffset: 6011, .AliasCondStart: 2091, .NumOperands: 3, .NumConds: 5 }, |
| 2461 | {.AsmStrOffset: 6023, .AliasCondStart: 2096, .NumOperands: 3, .NumConds: 4 }, |
| 2462 | {.AsmStrOffset: 6040, .AliasCondStart: 2100, .NumOperands: 3, .NumConds: 5 }, |
| 2463 | {.AsmStrOffset: 6057, .AliasCondStart: 2105, .NumOperands: 3, .NumConds: 4 }, |
| 2464 | {.AsmStrOffset: 6069, .AliasCondStart: 2109, .NumOperands: 3, .NumConds: 5 }, |
| 2465 | {.AsmStrOffset: 6081, .AliasCondStart: 2114, .NumOperands: 3, .NumConds: 4 }, |
| 2466 | {.AsmStrOffset: 6098, .AliasCondStart: 2118, .NumOperands: 3, .NumConds: 5 }, |
| 2467 | {.AsmStrOffset: 6115, .AliasCondStart: 2123, .NumOperands: 3, .NumConds: 4 }, |
| 2468 | {.AsmStrOffset: 6128, .AliasCondStart: 2127, .NumOperands: 3, .NumConds: 5 }, |
| 2469 | {.AsmStrOffset: 6141, .AliasCondStart: 2132, .NumOperands: 3, .NumConds: 4 }, |
| 2470 | {.AsmStrOffset: 6159, .AliasCondStart: 2136, .NumOperands: 3, .NumConds: 5 }, |
| 2471 | {.AsmStrOffset: 6177, .AliasCondStart: 2141, .NumOperands: 3, .NumConds: 4 }, |
| 2472 | {.AsmStrOffset: 6190, .AliasCondStart: 2145, .NumOperands: 3, .NumConds: 5 }, |
| 2473 | {.AsmStrOffset: 6203, .AliasCondStart: 2150, .NumOperands: 3, .NumConds: 4 }, |
| 2474 | {.AsmStrOffset: 6221, .AliasCondStart: 2154, .NumOperands: 3, .NumConds: 5 }, |
| 2475 | {.AsmStrOffset: 6239, .AliasCondStart: 2159, .NumOperands: 3, .NumConds: 4 }, |
| 2476 | {.AsmStrOffset: 6251, .AliasCondStart: 2163, .NumOperands: 3, .NumConds: 5 }, |
| 2477 | {.AsmStrOffset: 6263, .AliasCondStart: 2168, .NumOperands: 3, .NumConds: 4 }, |
| 2478 | {.AsmStrOffset: 6280, .AliasCondStart: 2172, .NumOperands: 3, .NumConds: 5 }, |
| 2479 | {.AsmStrOffset: 6297, .AliasCondStart: 2177, .NumOperands: 3, .NumConds: 4 }, |
| 2480 | {.AsmStrOffset: 6310, .AliasCondStart: 2181, .NumOperands: 3, .NumConds: 5 }, |
| 2481 | {.AsmStrOffset: 6323, .AliasCondStart: 2186, .NumOperands: 3, .NumConds: 4 }, |
| 2482 | {.AsmStrOffset: 6341, .AliasCondStart: 2190, .NumOperands: 3, .NumConds: 5 }, |
| 2483 | {.AsmStrOffset: 6359, .AliasCondStart: 2195, .NumOperands: 3, .NumConds: 4 }, |
| 2484 | {.AsmStrOffset: 6373, .AliasCondStart: 2199, .NumOperands: 3, .NumConds: 5 }, |
| 2485 | {.AsmStrOffset: 6387, .AliasCondStart: 2204, .NumOperands: 3, .NumConds: 4 }, |
| 2486 | {.AsmStrOffset: 6406, .AliasCondStart: 2208, .NumOperands: 3, .NumConds: 5 }, |
| 2487 | {.AsmStrOffset: 6425, .AliasCondStart: 2213, .NumOperands: 3, .NumConds: 4 }, |
| 2488 | {.AsmStrOffset: 6438, .AliasCondStart: 2217, .NumOperands: 3, .NumConds: 5 }, |
| 2489 | {.AsmStrOffset: 6451, .AliasCondStart: 2222, .NumOperands: 3, .NumConds: 4 }, |
| 2490 | {.AsmStrOffset: 6469, .AliasCondStart: 2226, .NumOperands: 3, .NumConds: 5 }, |
| 2491 | {.AsmStrOffset: 6487, .AliasCondStart: 2231, .NumOperands: 3, .NumConds: 4 }, |
| 2492 | {.AsmStrOffset: 6500, .AliasCondStart: 2235, .NumOperands: 3, .NumConds: 5 }, |
| 2493 | {.AsmStrOffset: 6513, .AliasCondStart: 2240, .NumOperands: 3, .NumConds: 4 }, |
| 2494 | {.AsmStrOffset: 6531, .AliasCondStart: 2244, .NumOperands: 3, .NumConds: 5 }, |
| 2495 | {.AsmStrOffset: 6549, .AliasCondStart: 2249, .NumOperands: 3, .NumConds: 4 }, |
| 2496 | {.AsmStrOffset: 6563, .AliasCondStart: 2253, .NumOperands: 3, .NumConds: 5 }, |
| 2497 | {.AsmStrOffset: 6577, .AliasCondStart: 2258, .NumOperands: 3, .NumConds: 4 }, |
| 2498 | {.AsmStrOffset: 6596, .AliasCondStart: 2262, .NumOperands: 3, .NumConds: 5 }, |
| 2499 | {.AsmStrOffset: 6615, .AliasCondStart: 2267, .NumOperands: 3, .NumConds: 4 }, |
| 2500 | {.AsmStrOffset: 6629, .AliasCondStart: 2271, .NumOperands: 3, .NumConds: 5 }, |
| 2501 | {.AsmStrOffset: 6643, .AliasCondStart: 2276, .NumOperands: 3, .NumConds: 4 }, |
| 2502 | {.AsmStrOffset: 6662, .AliasCondStart: 2280, .NumOperands: 3, .NumConds: 5 }, |
| 2503 | {.AsmStrOffset: 6681, .AliasCondStart: 2285, .NumOperands: 3, .NumConds: 4 }, |
| 2504 | {.AsmStrOffset: 6694, .AliasCondStart: 2289, .NumOperands: 3, .NumConds: 5 }, |
| 2505 | {.AsmStrOffset: 6707, .AliasCondStart: 2294, .NumOperands: 3, .NumConds: 4 }, |
| 2506 | {.AsmStrOffset: 6725, .AliasCondStart: 2298, .NumOperands: 3, .NumConds: 5 }, |
| 2507 | {.AsmStrOffset: 6743, .AliasCondStart: 2303, .NumOperands: 3, .NumConds: 4 }, |
| 2508 | {.AsmStrOffset: 6756, .AliasCondStart: 2307, .NumOperands: 3, .NumConds: 5 }, |
| 2509 | {.AsmStrOffset: 6769, .AliasCondStart: 2312, .NumOperands: 3, .NumConds: 4 }, |
| 2510 | {.AsmStrOffset: 6787, .AliasCondStart: 2316, .NumOperands: 3, .NumConds: 5 }, |
| 2511 | // SP::TRAPri - 513 |
| 2512 | {.AsmStrOffset: 6805, .AliasCondStart: 2321, .NumOperands: 3, .NumConds: 3 }, |
| 2513 | {.AsmStrOffset: 6811, .AliasCondStart: 2324, .NumOperands: 3, .NumConds: 3 }, |
| 2514 | {.AsmStrOffset: 6822, .AliasCondStart: 2327, .NumOperands: 3, .NumConds: 3 }, |
| 2515 | {.AsmStrOffset: 6828, .AliasCondStart: 2330, .NumOperands: 3, .NumConds: 3 }, |
| 2516 | {.AsmStrOffset: 6839, .AliasCondStart: 2333, .NumOperands: 3, .NumConds: 3 }, |
| 2517 | {.AsmStrOffset: 6846, .AliasCondStart: 2336, .NumOperands: 3, .NumConds: 3 }, |
| 2518 | {.AsmStrOffset: 6858, .AliasCondStart: 2339, .NumOperands: 3, .NumConds: 3 }, |
| 2519 | {.AsmStrOffset: 6864, .AliasCondStart: 2342, .NumOperands: 3, .NumConds: 3 }, |
| 2520 | {.AsmStrOffset: 6875, .AliasCondStart: 2345, .NumOperands: 3, .NumConds: 3 }, |
| 2521 | {.AsmStrOffset: 6881, .AliasCondStart: 2348, .NumOperands: 3, .NumConds: 3 }, |
| 2522 | {.AsmStrOffset: 6892, .AliasCondStart: 2351, .NumOperands: 3, .NumConds: 3 }, |
| 2523 | {.AsmStrOffset: 6899, .AliasCondStart: 2354, .NumOperands: 3, .NumConds: 3 }, |
| 2524 | {.AsmStrOffset: 6911, .AliasCondStart: 2357, .NumOperands: 3, .NumConds: 3 }, |
| 2525 | {.AsmStrOffset: 6918, .AliasCondStart: 2360, .NumOperands: 3, .NumConds: 3 }, |
| 2526 | {.AsmStrOffset: 6930, .AliasCondStart: 2363, .NumOperands: 3, .NumConds: 3 }, |
| 2527 | {.AsmStrOffset: 6936, .AliasCondStart: 2366, .NumOperands: 3, .NumConds: 3 }, |
| 2528 | {.AsmStrOffset: 6947, .AliasCondStart: 2369, .NumOperands: 3, .NumConds: 3 }, |
| 2529 | {.AsmStrOffset: 6954, .AliasCondStart: 2372, .NumOperands: 3, .NumConds: 3 }, |
| 2530 | {.AsmStrOffset: 6966, .AliasCondStart: 2375, .NumOperands: 3, .NumConds: 3 }, |
| 2531 | {.AsmStrOffset: 6974, .AliasCondStart: 2378, .NumOperands: 3, .NumConds: 3 }, |
| 2532 | {.AsmStrOffset: 6987, .AliasCondStart: 2381, .NumOperands: 3, .NumConds: 3 }, |
| 2533 | {.AsmStrOffset: 6994, .AliasCondStart: 2384, .NumOperands: 3, .NumConds: 3 }, |
| 2534 | {.AsmStrOffset: 7006, .AliasCondStart: 2387, .NumOperands: 3, .NumConds: 3 }, |
| 2535 | {.AsmStrOffset: 7013, .AliasCondStart: 2390, .NumOperands: 3, .NumConds: 3 }, |
| 2536 | {.AsmStrOffset: 7025, .AliasCondStart: 2393, .NumOperands: 3, .NumConds: 3 }, |
| 2537 | {.AsmStrOffset: 7033, .AliasCondStart: 2396, .NumOperands: 3, .NumConds: 3 }, |
| 2538 | {.AsmStrOffset: 7046, .AliasCondStart: 2399, .NumOperands: 3, .NumConds: 3 }, |
| 2539 | {.AsmStrOffset: 7054, .AliasCondStart: 2402, .NumOperands: 3, .NumConds: 3 }, |
| 2540 | {.AsmStrOffset: 7067, .AliasCondStart: 2405, .NumOperands: 3, .NumConds: 3 }, |
| 2541 | {.AsmStrOffset: 7074, .AliasCondStart: 2408, .NumOperands: 3, .NumConds: 3 }, |
| 2542 | {.AsmStrOffset: 7086, .AliasCondStart: 2411, .NumOperands: 3, .NumConds: 3 }, |
| 2543 | {.AsmStrOffset: 7093, .AliasCondStart: 2414, .NumOperands: 3, .NumConds: 3 }, |
| 2544 | // SP::TRAPrr - 545 |
| 2545 | {.AsmStrOffset: 6805, .AliasCondStart: 2417, .NumOperands: 3, .NumConds: 3 }, |
| 2546 | {.AsmStrOffset: 6811, .AliasCondStart: 2420, .NumOperands: 3, .NumConds: 3 }, |
| 2547 | {.AsmStrOffset: 6822, .AliasCondStart: 2423, .NumOperands: 3, .NumConds: 3 }, |
| 2548 | {.AsmStrOffset: 6828, .AliasCondStart: 2426, .NumOperands: 3, .NumConds: 3 }, |
| 2549 | {.AsmStrOffset: 6839, .AliasCondStart: 2429, .NumOperands: 3, .NumConds: 3 }, |
| 2550 | {.AsmStrOffset: 6846, .AliasCondStart: 2432, .NumOperands: 3, .NumConds: 3 }, |
| 2551 | {.AsmStrOffset: 6858, .AliasCondStart: 2435, .NumOperands: 3, .NumConds: 3 }, |
| 2552 | {.AsmStrOffset: 6864, .AliasCondStart: 2438, .NumOperands: 3, .NumConds: 3 }, |
| 2553 | {.AsmStrOffset: 6875, .AliasCondStart: 2441, .NumOperands: 3, .NumConds: 3 }, |
| 2554 | {.AsmStrOffset: 6881, .AliasCondStart: 2444, .NumOperands: 3, .NumConds: 3 }, |
| 2555 | {.AsmStrOffset: 6892, .AliasCondStart: 2447, .NumOperands: 3, .NumConds: 3 }, |
| 2556 | {.AsmStrOffset: 6899, .AliasCondStart: 2450, .NumOperands: 3, .NumConds: 3 }, |
| 2557 | {.AsmStrOffset: 6911, .AliasCondStart: 2453, .NumOperands: 3, .NumConds: 3 }, |
| 2558 | {.AsmStrOffset: 6918, .AliasCondStart: 2456, .NumOperands: 3, .NumConds: 3 }, |
| 2559 | {.AsmStrOffset: 6930, .AliasCondStart: 2459, .NumOperands: 3, .NumConds: 3 }, |
| 2560 | {.AsmStrOffset: 6936, .AliasCondStart: 2462, .NumOperands: 3, .NumConds: 3 }, |
| 2561 | {.AsmStrOffset: 6947, .AliasCondStart: 2465, .NumOperands: 3, .NumConds: 3 }, |
| 2562 | {.AsmStrOffset: 6954, .AliasCondStart: 2468, .NumOperands: 3, .NumConds: 3 }, |
| 2563 | {.AsmStrOffset: 6966, .AliasCondStart: 2471, .NumOperands: 3, .NumConds: 3 }, |
| 2564 | {.AsmStrOffset: 6974, .AliasCondStart: 2474, .NumOperands: 3, .NumConds: 3 }, |
| 2565 | {.AsmStrOffset: 6987, .AliasCondStart: 2477, .NumOperands: 3, .NumConds: 3 }, |
| 2566 | {.AsmStrOffset: 6994, .AliasCondStart: 2480, .NumOperands: 3, .NumConds: 3 }, |
| 2567 | {.AsmStrOffset: 7006, .AliasCondStart: 2483, .NumOperands: 3, .NumConds: 3 }, |
| 2568 | {.AsmStrOffset: 7013, .AliasCondStart: 2486, .NumOperands: 3, .NumConds: 3 }, |
| 2569 | {.AsmStrOffset: 7025, .AliasCondStart: 2489, .NumOperands: 3, .NumConds: 3 }, |
| 2570 | {.AsmStrOffset: 7033, .AliasCondStart: 2492, .NumOperands: 3, .NumConds: 3 }, |
| 2571 | {.AsmStrOffset: 7046, .AliasCondStart: 2495, .NumOperands: 3, .NumConds: 3 }, |
| 2572 | {.AsmStrOffset: 7054, .AliasCondStart: 2498, .NumOperands: 3, .NumConds: 3 }, |
| 2573 | {.AsmStrOffset: 7067, .AliasCondStart: 2501, .NumOperands: 3, .NumConds: 3 }, |
| 2574 | {.AsmStrOffset: 7074, .AliasCondStart: 2504, .NumOperands: 3, .NumConds: 3 }, |
| 2575 | {.AsmStrOffset: 7086, .AliasCondStart: 2507, .NumOperands: 3, .NumConds: 3 }, |
| 2576 | {.AsmStrOffset: 7093, .AliasCondStart: 2510, .NumOperands: 3, .NumConds: 3 }, |
| 2577 | // SP::TXCCri - 577 |
| 2578 | {.AsmStrOffset: 7105, .AliasCondStart: 2513, .NumOperands: 3, .NumConds: 4 }, |
| 2579 | {.AsmStrOffset: 5833, .AliasCondStart: 2517, .NumOperands: 3, .NumConds: 5 }, |
| 2580 | {.AsmStrOffset: 7117, .AliasCondStart: 2522, .NumOperands: 3, .NumConds: 4 }, |
| 2581 | {.AsmStrOffset: 5862, .AliasCondStart: 2526, .NumOperands: 3, .NumConds: 5 }, |
| 2582 | {.AsmStrOffset: 7134, .AliasCondStart: 2531, .NumOperands: 3, .NumConds: 4 }, |
| 2583 | {.AsmStrOffset: 5891, .AliasCondStart: 2535, .NumOperands: 3, .NumConds: 5 }, |
| 2584 | {.AsmStrOffset: 7146, .AliasCondStart: 2540, .NumOperands: 3, .NumConds: 4 }, |
| 2585 | {.AsmStrOffset: 5920, .AliasCondStart: 2544, .NumOperands: 3, .NumConds: 5 }, |
| 2586 | {.AsmStrOffset: 7163, .AliasCondStart: 2549, .NumOperands: 3, .NumConds: 4 }, |
| 2587 | {.AsmStrOffset: 5950, .AliasCondStart: 2553, .NumOperands: 3, .NumConds: 5 }, |
| 2588 | {.AsmStrOffset: 7176, .AliasCondStart: 2558, .NumOperands: 3, .NumConds: 4 }, |
| 2589 | {.AsmStrOffset: 5981, .AliasCondStart: 2562, .NumOperands: 3, .NumConds: 5 }, |
| 2590 | {.AsmStrOffset: 7194, .AliasCondStart: 2567, .NumOperands: 3, .NumConds: 4 }, |
| 2591 | {.AsmStrOffset: 6011, .AliasCondStart: 2571, .NumOperands: 3, .NumConds: 5 }, |
| 2592 | {.AsmStrOffset: 7206, .AliasCondStart: 2576, .NumOperands: 3, .NumConds: 4 }, |
| 2593 | {.AsmStrOffset: 6040, .AliasCondStart: 2580, .NumOperands: 3, .NumConds: 5 }, |
| 2594 | {.AsmStrOffset: 7223, .AliasCondStart: 2585, .NumOperands: 3, .NumConds: 4 }, |
| 2595 | {.AsmStrOffset: 6069, .AliasCondStart: 2589, .NumOperands: 3, .NumConds: 5 }, |
| 2596 | {.AsmStrOffset: 7235, .AliasCondStart: 2594, .NumOperands: 3, .NumConds: 4 }, |
| 2597 | {.AsmStrOffset: 6098, .AliasCondStart: 2598, .NumOperands: 3, .NumConds: 5 }, |
| 2598 | {.AsmStrOffset: 7252, .AliasCondStart: 2603, .NumOperands: 3, .NumConds: 4 }, |
| 2599 | {.AsmStrOffset: 6128, .AliasCondStart: 2607, .NumOperands: 3, .NumConds: 5 }, |
| 2600 | {.AsmStrOffset: 7265, .AliasCondStart: 2612, .NumOperands: 3, .NumConds: 4 }, |
| 2601 | {.AsmStrOffset: 6159, .AliasCondStart: 2616, .NumOperands: 3, .NumConds: 5 }, |
| 2602 | {.AsmStrOffset: 7283, .AliasCondStart: 2621, .NumOperands: 3, .NumConds: 4 }, |
| 2603 | {.AsmStrOffset: 6190, .AliasCondStart: 2625, .NumOperands: 3, .NumConds: 5 }, |
| 2604 | {.AsmStrOffset: 7296, .AliasCondStart: 2630, .NumOperands: 3, .NumConds: 4 }, |
| 2605 | {.AsmStrOffset: 6221, .AliasCondStart: 2634, .NumOperands: 3, .NumConds: 5 }, |
| 2606 | {.AsmStrOffset: 7314, .AliasCondStart: 2639, .NumOperands: 3, .NumConds: 4 }, |
| 2607 | {.AsmStrOffset: 6251, .AliasCondStart: 2643, .NumOperands: 3, .NumConds: 5 }, |
| 2608 | {.AsmStrOffset: 7326, .AliasCondStart: 2648, .NumOperands: 3, .NumConds: 4 }, |
| 2609 | {.AsmStrOffset: 6280, .AliasCondStart: 2652, .NumOperands: 3, .NumConds: 5 }, |
| 2610 | {.AsmStrOffset: 7343, .AliasCondStart: 2657, .NumOperands: 3, .NumConds: 4 }, |
| 2611 | {.AsmStrOffset: 6310, .AliasCondStart: 2661, .NumOperands: 3, .NumConds: 5 }, |
| 2612 | {.AsmStrOffset: 7356, .AliasCondStart: 2666, .NumOperands: 3, .NumConds: 4 }, |
| 2613 | {.AsmStrOffset: 6341, .AliasCondStart: 2670, .NumOperands: 3, .NumConds: 5 }, |
| 2614 | {.AsmStrOffset: 7374, .AliasCondStart: 2675, .NumOperands: 3, .NumConds: 4 }, |
| 2615 | {.AsmStrOffset: 6373, .AliasCondStart: 2679, .NumOperands: 3, .NumConds: 5 }, |
| 2616 | {.AsmStrOffset: 7388, .AliasCondStart: 2684, .NumOperands: 3, .NumConds: 4 }, |
| 2617 | {.AsmStrOffset: 6406, .AliasCondStart: 2688, .NumOperands: 3, .NumConds: 5 }, |
| 2618 | {.AsmStrOffset: 7407, .AliasCondStart: 2693, .NumOperands: 3, .NumConds: 4 }, |
| 2619 | {.AsmStrOffset: 6438, .AliasCondStart: 2697, .NumOperands: 3, .NumConds: 5 }, |
| 2620 | {.AsmStrOffset: 7420, .AliasCondStart: 2702, .NumOperands: 3, .NumConds: 4 }, |
| 2621 | {.AsmStrOffset: 6469, .AliasCondStart: 2706, .NumOperands: 3, .NumConds: 5 }, |
| 2622 | {.AsmStrOffset: 7438, .AliasCondStart: 2711, .NumOperands: 3, .NumConds: 4 }, |
| 2623 | {.AsmStrOffset: 6500, .AliasCondStart: 2715, .NumOperands: 3, .NumConds: 5 }, |
| 2624 | {.AsmStrOffset: 7451, .AliasCondStart: 2720, .NumOperands: 3, .NumConds: 4 }, |
| 2625 | {.AsmStrOffset: 6531, .AliasCondStart: 2724, .NumOperands: 3, .NumConds: 5 }, |
| 2626 | {.AsmStrOffset: 7469, .AliasCondStart: 2729, .NumOperands: 3, .NumConds: 4 }, |
| 2627 | {.AsmStrOffset: 6563, .AliasCondStart: 2733, .NumOperands: 3, .NumConds: 5 }, |
| 2628 | {.AsmStrOffset: 7483, .AliasCondStart: 2738, .NumOperands: 3, .NumConds: 4 }, |
| 2629 | {.AsmStrOffset: 6596, .AliasCondStart: 2742, .NumOperands: 3, .NumConds: 5 }, |
| 2630 | {.AsmStrOffset: 7502, .AliasCondStart: 2747, .NumOperands: 3, .NumConds: 4 }, |
| 2631 | {.AsmStrOffset: 6629, .AliasCondStart: 2751, .NumOperands: 3, .NumConds: 5 }, |
| 2632 | {.AsmStrOffset: 7516, .AliasCondStart: 2756, .NumOperands: 3, .NumConds: 4 }, |
| 2633 | {.AsmStrOffset: 6662, .AliasCondStart: 2760, .NumOperands: 3, .NumConds: 5 }, |
| 2634 | {.AsmStrOffset: 7535, .AliasCondStart: 2765, .NumOperands: 3, .NumConds: 4 }, |
| 2635 | {.AsmStrOffset: 6694, .AliasCondStart: 2769, .NumOperands: 3, .NumConds: 5 }, |
| 2636 | {.AsmStrOffset: 7548, .AliasCondStart: 2774, .NumOperands: 3, .NumConds: 4 }, |
| 2637 | {.AsmStrOffset: 6725, .AliasCondStart: 2778, .NumOperands: 3, .NumConds: 5 }, |
| 2638 | {.AsmStrOffset: 7566, .AliasCondStart: 2783, .NumOperands: 3, .NumConds: 4 }, |
| 2639 | {.AsmStrOffset: 6756, .AliasCondStart: 2787, .NumOperands: 3, .NumConds: 5 }, |
| 2640 | {.AsmStrOffset: 7579, .AliasCondStart: 2792, .NumOperands: 3, .NumConds: 4 }, |
| 2641 | {.AsmStrOffset: 6787, .AliasCondStart: 2796, .NumOperands: 3, .NumConds: 5 }, |
| 2642 | // SP::TXCCrr - 641 |
| 2643 | {.AsmStrOffset: 7105, .AliasCondStart: 2801, .NumOperands: 3, .NumConds: 4 }, |
| 2644 | {.AsmStrOffset: 5833, .AliasCondStart: 2805, .NumOperands: 3, .NumConds: 5 }, |
| 2645 | {.AsmStrOffset: 7117, .AliasCondStart: 2810, .NumOperands: 3, .NumConds: 4 }, |
| 2646 | {.AsmStrOffset: 5862, .AliasCondStart: 2814, .NumOperands: 3, .NumConds: 5 }, |
| 2647 | {.AsmStrOffset: 7134, .AliasCondStart: 2819, .NumOperands: 3, .NumConds: 4 }, |
| 2648 | {.AsmStrOffset: 5891, .AliasCondStart: 2823, .NumOperands: 3, .NumConds: 5 }, |
| 2649 | {.AsmStrOffset: 7146, .AliasCondStart: 2828, .NumOperands: 3, .NumConds: 4 }, |
| 2650 | {.AsmStrOffset: 5920, .AliasCondStart: 2832, .NumOperands: 3, .NumConds: 5 }, |
| 2651 | {.AsmStrOffset: 7163, .AliasCondStart: 2837, .NumOperands: 3, .NumConds: 4 }, |
| 2652 | {.AsmStrOffset: 5950, .AliasCondStart: 2841, .NumOperands: 3, .NumConds: 5 }, |
| 2653 | {.AsmStrOffset: 7176, .AliasCondStart: 2846, .NumOperands: 3, .NumConds: 4 }, |
| 2654 | {.AsmStrOffset: 5981, .AliasCondStart: 2850, .NumOperands: 3, .NumConds: 5 }, |
| 2655 | {.AsmStrOffset: 7194, .AliasCondStart: 2855, .NumOperands: 3, .NumConds: 4 }, |
| 2656 | {.AsmStrOffset: 6011, .AliasCondStart: 2859, .NumOperands: 3, .NumConds: 5 }, |
| 2657 | {.AsmStrOffset: 7206, .AliasCondStart: 2864, .NumOperands: 3, .NumConds: 4 }, |
| 2658 | {.AsmStrOffset: 6040, .AliasCondStart: 2868, .NumOperands: 3, .NumConds: 5 }, |
| 2659 | {.AsmStrOffset: 7223, .AliasCondStart: 2873, .NumOperands: 3, .NumConds: 4 }, |
| 2660 | {.AsmStrOffset: 6069, .AliasCondStart: 2877, .NumOperands: 3, .NumConds: 5 }, |
| 2661 | {.AsmStrOffset: 7235, .AliasCondStart: 2882, .NumOperands: 3, .NumConds: 4 }, |
| 2662 | {.AsmStrOffset: 6098, .AliasCondStart: 2886, .NumOperands: 3, .NumConds: 5 }, |
| 2663 | {.AsmStrOffset: 7252, .AliasCondStart: 2891, .NumOperands: 3, .NumConds: 4 }, |
| 2664 | {.AsmStrOffset: 6128, .AliasCondStart: 2895, .NumOperands: 3, .NumConds: 5 }, |
| 2665 | {.AsmStrOffset: 7265, .AliasCondStart: 2900, .NumOperands: 3, .NumConds: 4 }, |
| 2666 | {.AsmStrOffset: 6159, .AliasCondStart: 2904, .NumOperands: 3, .NumConds: 5 }, |
| 2667 | {.AsmStrOffset: 7283, .AliasCondStart: 2909, .NumOperands: 3, .NumConds: 4 }, |
| 2668 | {.AsmStrOffset: 6190, .AliasCondStart: 2913, .NumOperands: 3, .NumConds: 5 }, |
| 2669 | {.AsmStrOffset: 7296, .AliasCondStart: 2918, .NumOperands: 3, .NumConds: 4 }, |
| 2670 | {.AsmStrOffset: 6221, .AliasCondStart: 2922, .NumOperands: 3, .NumConds: 5 }, |
| 2671 | {.AsmStrOffset: 7314, .AliasCondStart: 2927, .NumOperands: 3, .NumConds: 4 }, |
| 2672 | {.AsmStrOffset: 6251, .AliasCondStart: 2931, .NumOperands: 3, .NumConds: 5 }, |
| 2673 | {.AsmStrOffset: 7326, .AliasCondStart: 2936, .NumOperands: 3, .NumConds: 4 }, |
| 2674 | {.AsmStrOffset: 6280, .AliasCondStart: 2940, .NumOperands: 3, .NumConds: 5 }, |
| 2675 | {.AsmStrOffset: 7343, .AliasCondStart: 2945, .NumOperands: 3, .NumConds: 4 }, |
| 2676 | {.AsmStrOffset: 6310, .AliasCondStart: 2949, .NumOperands: 3, .NumConds: 5 }, |
| 2677 | {.AsmStrOffset: 7356, .AliasCondStart: 2954, .NumOperands: 3, .NumConds: 4 }, |
| 2678 | {.AsmStrOffset: 6341, .AliasCondStart: 2958, .NumOperands: 3, .NumConds: 5 }, |
| 2679 | {.AsmStrOffset: 7374, .AliasCondStart: 2963, .NumOperands: 3, .NumConds: 4 }, |
| 2680 | {.AsmStrOffset: 6373, .AliasCondStart: 2967, .NumOperands: 3, .NumConds: 5 }, |
| 2681 | {.AsmStrOffset: 7388, .AliasCondStart: 2972, .NumOperands: 3, .NumConds: 4 }, |
| 2682 | {.AsmStrOffset: 6406, .AliasCondStart: 2976, .NumOperands: 3, .NumConds: 5 }, |
| 2683 | {.AsmStrOffset: 7407, .AliasCondStart: 2981, .NumOperands: 3, .NumConds: 4 }, |
| 2684 | {.AsmStrOffset: 6438, .AliasCondStart: 2985, .NumOperands: 3, .NumConds: 5 }, |
| 2685 | {.AsmStrOffset: 7420, .AliasCondStart: 2990, .NumOperands: 3, .NumConds: 4 }, |
| 2686 | {.AsmStrOffset: 6469, .AliasCondStart: 2994, .NumOperands: 3, .NumConds: 5 }, |
| 2687 | {.AsmStrOffset: 7438, .AliasCondStart: 2999, .NumOperands: 3, .NumConds: 4 }, |
| 2688 | {.AsmStrOffset: 6500, .AliasCondStart: 3003, .NumOperands: 3, .NumConds: 5 }, |
| 2689 | {.AsmStrOffset: 7451, .AliasCondStart: 3008, .NumOperands: 3, .NumConds: 4 }, |
| 2690 | {.AsmStrOffset: 6531, .AliasCondStart: 3012, .NumOperands: 3, .NumConds: 5 }, |
| 2691 | {.AsmStrOffset: 7469, .AliasCondStart: 3017, .NumOperands: 3, .NumConds: 4 }, |
| 2692 | {.AsmStrOffset: 6563, .AliasCondStart: 3021, .NumOperands: 3, .NumConds: 5 }, |
| 2693 | {.AsmStrOffset: 7483, .AliasCondStart: 3026, .NumOperands: 3, .NumConds: 4 }, |
| 2694 | {.AsmStrOffset: 6596, .AliasCondStart: 3030, .NumOperands: 3, .NumConds: 5 }, |
| 2695 | {.AsmStrOffset: 7502, .AliasCondStart: 3035, .NumOperands: 3, .NumConds: 4 }, |
| 2696 | {.AsmStrOffset: 6629, .AliasCondStart: 3039, .NumOperands: 3, .NumConds: 5 }, |
| 2697 | {.AsmStrOffset: 7516, .AliasCondStart: 3044, .NumOperands: 3, .NumConds: 4 }, |
| 2698 | {.AsmStrOffset: 6662, .AliasCondStart: 3048, .NumOperands: 3, .NumConds: 5 }, |
| 2699 | {.AsmStrOffset: 7535, .AliasCondStart: 3053, .NumOperands: 3, .NumConds: 4 }, |
| 2700 | {.AsmStrOffset: 6694, .AliasCondStart: 3057, .NumOperands: 3, .NumConds: 5 }, |
| 2701 | {.AsmStrOffset: 7548, .AliasCondStart: 3062, .NumOperands: 3, .NumConds: 4 }, |
| 2702 | {.AsmStrOffset: 6725, .AliasCondStart: 3066, .NumOperands: 3, .NumConds: 5 }, |
| 2703 | {.AsmStrOffset: 7566, .AliasCondStart: 3071, .NumOperands: 3, .NumConds: 4 }, |
| 2704 | {.AsmStrOffset: 6756, .AliasCondStart: 3075, .NumOperands: 3, .NumConds: 5 }, |
| 2705 | {.AsmStrOffset: 7579, .AliasCondStart: 3080, .NumOperands: 3, .NumConds: 4 }, |
| 2706 | {.AsmStrOffset: 6787, .AliasCondStart: 3084, .NumOperands: 3, .NumConds: 5 }, |
| 2707 | // SP::V9FCMPD - 705 |
| 2708 | {.AsmStrOffset: 7597, .AliasCondStart: 3089, .NumOperands: 3, .NumConds: 3 }, |
| 2709 | // SP::V9FCMPED - 706 |
| 2710 | {.AsmStrOffset: 7610, .AliasCondStart: 3092, .NumOperands: 3, .NumConds: 3 }, |
| 2711 | // SP::V9FCMPEQ - 707 |
| 2712 | {.AsmStrOffset: 7624, .AliasCondStart: 3095, .NumOperands: 3, .NumConds: 3 }, |
| 2713 | // SP::V9FCMPES - 708 |
| 2714 | {.AsmStrOffset: 7638, .AliasCondStart: 3098, .NumOperands: 3, .NumConds: 3 }, |
| 2715 | // SP::V9FCMPQ - 709 |
| 2716 | {.AsmStrOffset: 7652, .AliasCondStart: 3101, .NumOperands: 3, .NumConds: 3 }, |
| 2717 | // SP::V9FCMPS - 710 |
| 2718 | {.AsmStrOffset: 7665, .AliasCondStart: 3104, .NumOperands: 3, .NumConds: 3 }, |
| 2719 | // SP::V9FMOVD_FCC - 711 |
| 2720 | {.AsmStrOffset: 7678, .AliasCondStart: 3107, .NumOperands: 5, .NumConds: 6 }, |
| 2721 | {.AsmStrOffset: 7696, .AliasCondStart: 3113, .NumOperands: 5, .NumConds: 6 }, |
| 2722 | {.AsmStrOffset: 7714, .AliasCondStart: 3119, .NumOperands: 5, .NumConds: 6 }, |
| 2723 | {.AsmStrOffset: 7732, .AliasCondStart: 3125, .NumOperands: 5, .NumConds: 6 }, |
| 2724 | {.AsmStrOffset: 7750, .AliasCondStart: 3131, .NumOperands: 5, .NumConds: 6 }, |
| 2725 | {.AsmStrOffset: 7769, .AliasCondStart: 3137, .NumOperands: 5, .NumConds: 6 }, |
| 2726 | {.AsmStrOffset: 7787, .AliasCondStart: 3143, .NumOperands: 5, .NumConds: 6 }, |
| 2727 | {.AsmStrOffset: 7806, .AliasCondStart: 3149, .NumOperands: 5, .NumConds: 6 }, |
| 2728 | {.AsmStrOffset: 7825, .AliasCondStart: 3155, .NumOperands: 5, .NumConds: 6 }, |
| 2729 | {.AsmStrOffset: 7844, .AliasCondStart: 3161, .NumOperands: 5, .NumConds: 6 }, |
| 2730 | {.AsmStrOffset: 7862, .AliasCondStart: 3167, .NumOperands: 5, .NumConds: 6 }, |
| 2731 | {.AsmStrOffset: 7881, .AliasCondStart: 3173, .NumOperands: 5, .NumConds: 6 }, |
| 2732 | {.AsmStrOffset: 7900, .AliasCondStart: 3179, .NumOperands: 5, .NumConds: 6 }, |
| 2733 | {.AsmStrOffset: 7920, .AliasCondStart: 3185, .NumOperands: 5, .NumConds: 6 }, |
| 2734 | {.AsmStrOffset: 7939, .AliasCondStart: 3191, .NumOperands: 5, .NumConds: 6 }, |
| 2735 | {.AsmStrOffset: 7959, .AliasCondStart: 3197, .NumOperands: 5, .NumConds: 6 }, |
| 2736 | // SP::V9FMOVQ_FCC - 727 |
| 2737 | {.AsmStrOffset: 7977, .AliasCondStart: 3203, .NumOperands: 5, .NumConds: 6 }, |
| 2738 | {.AsmStrOffset: 7995, .AliasCondStart: 3209, .NumOperands: 5, .NumConds: 6 }, |
| 2739 | {.AsmStrOffset: 8013, .AliasCondStart: 3215, .NumOperands: 5, .NumConds: 6 }, |
| 2740 | {.AsmStrOffset: 8031, .AliasCondStart: 3221, .NumOperands: 5, .NumConds: 6 }, |
| 2741 | {.AsmStrOffset: 8049, .AliasCondStart: 3227, .NumOperands: 5, .NumConds: 6 }, |
| 2742 | {.AsmStrOffset: 8068, .AliasCondStart: 3233, .NumOperands: 5, .NumConds: 6 }, |
| 2743 | {.AsmStrOffset: 8086, .AliasCondStart: 3239, .NumOperands: 5, .NumConds: 6 }, |
| 2744 | {.AsmStrOffset: 8105, .AliasCondStart: 3245, .NumOperands: 5, .NumConds: 6 }, |
| 2745 | {.AsmStrOffset: 8124, .AliasCondStart: 3251, .NumOperands: 5, .NumConds: 6 }, |
| 2746 | {.AsmStrOffset: 8143, .AliasCondStart: 3257, .NumOperands: 5, .NumConds: 6 }, |
| 2747 | {.AsmStrOffset: 8161, .AliasCondStart: 3263, .NumOperands: 5, .NumConds: 6 }, |
| 2748 | {.AsmStrOffset: 8180, .AliasCondStart: 3269, .NumOperands: 5, .NumConds: 6 }, |
| 2749 | {.AsmStrOffset: 8199, .AliasCondStart: 3275, .NumOperands: 5, .NumConds: 6 }, |
| 2750 | {.AsmStrOffset: 8219, .AliasCondStart: 3281, .NumOperands: 5, .NumConds: 6 }, |
| 2751 | {.AsmStrOffset: 8238, .AliasCondStart: 3287, .NumOperands: 5, .NumConds: 6 }, |
| 2752 | {.AsmStrOffset: 8258, .AliasCondStart: 3293, .NumOperands: 5, .NumConds: 6 }, |
| 2753 | // SP::V9FMOVS_FCC - 743 |
| 2754 | {.AsmStrOffset: 8276, .AliasCondStart: 3299, .NumOperands: 5, .NumConds: 6 }, |
| 2755 | {.AsmStrOffset: 8294, .AliasCondStart: 3305, .NumOperands: 5, .NumConds: 6 }, |
| 2756 | {.AsmStrOffset: 8312, .AliasCondStart: 3311, .NumOperands: 5, .NumConds: 6 }, |
| 2757 | {.AsmStrOffset: 8330, .AliasCondStart: 3317, .NumOperands: 5, .NumConds: 6 }, |
| 2758 | {.AsmStrOffset: 8348, .AliasCondStart: 3323, .NumOperands: 5, .NumConds: 6 }, |
| 2759 | {.AsmStrOffset: 8367, .AliasCondStart: 3329, .NumOperands: 5, .NumConds: 6 }, |
| 2760 | {.AsmStrOffset: 8385, .AliasCondStart: 3335, .NumOperands: 5, .NumConds: 6 }, |
| 2761 | {.AsmStrOffset: 8404, .AliasCondStart: 3341, .NumOperands: 5, .NumConds: 6 }, |
| 2762 | {.AsmStrOffset: 8423, .AliasCondStart: 3347, .NumOperands: 5, .NumConds: 6 }, |
| 2763 | {.AsmStrOffset: 8442, .AliasCondStart: 3353, .NumOperands: 5, .NumConds: 6 }, |
| 2764 | {.AsmStrOffset: 8460, .AliasCondStart: 3359, .NumOperands: 5, .NumConds: 6 }, |
| 2765 | {.AsmStrOffset: 8479, .AliasCondStart: 3365, .NumOperands: 5, .NumConds: 6 }, |
| 2766 | {.AsmStrOffset: 8498, .AliasCondStart: 3371, .NumOperands: 5, .NumConds: 6 }, |
| 2767 | {.AsmStrOffset: 8518, .AliasCondStart: 3377, .NumOperands: 5, .NumConds: 6 }, |
| 2768 | {.AsmStrOffset: 8537, .AliasCondStart: 3383, .NumOperands: 5, .NumConds: 6 }, |
| 2769 | {.AsmStrOffset: 8557, .AliasCondStart: 3389, .NumOperands: 5, .NumConds: 6 }, |
| 2770 | // SP::V9MOVFCCri - 759 |
| 2771 | {.AsmStrOffset: 8575, .AliasCondStart: 3395, .NumOperands: 5, .NumConds: 6 }, |
| 2772 | {.AsmStrOffset: 8591, .AliasCondStart: 3401, .NumOperands: 5, .NumConds: 6 }, |
| 2773 | {.AsmStrOffset: 8607, .AliasCondStart: 3407, .NumOperands: 5, .NumConds: 6 }, |
| 2774 | {.AsmStrOffset: 8623, .AliasCondStart: 3413, .NumOperands: 5, .NumConds: 6 }, |
| 2775 | {.AsmStrOffset: 8639, .AliasCondStart: 3419, .NumOperands: 5, .NumConds: 6 }, |
| 2776 | {.AsmStrOffset: 8656, .AliasCondStart: 3425, .NumOperands: 5, .NumConds: 6 }, |
| 2777 | {.AsmStrOffset: 8672, .AliasCondStart: 3431, .NumOperands: 5, .NumConds: 6 }, |
| 2778 | {.AsmStrOffset: 8689, .AliasCondStart: 3437, .NumOperands: 5, .NumConds: 6 }, |
| 2779 | {.AsmStrOffset: 8706, .AliasCondStart: 3443, .NumOperands: 5, .NumConds: 6 }, |
| 2780 | {.AsmStrOffset: 8723, .AliasCondStart: 3449, .NumOperands: 5, .NumConds: 6 }, |
| 2781 | {.AsmStrOffset: 8739, .AliasCondStart: 3455, .NumOperands: 5, .NumConds: 6 }, |
| 2782 | {.AsmStrOffset: 8756, .AliasCondStart: 3461, .NumOperands: 5, .NumConds: 6 }, |
| 2783 | {.AsmStrOffset: 8773, .AliasCondStart: 3467, .NumOperands: 5, .NumConds: 6 }, |
| 2784 | {.AsmStrOffset: 8791, .AliasCondStart: 3473, .NumOperands: 5, .NumConds: 6 }, |
| 2785 | {.AsmStrOffset: 8808, .AliasCondStart: 3479, .NumOperands: 5, .NumConds: 6 }, |
| 2786 | {.AsmStrOffset: 8826, .AliasCondStart: 3485, .NumOperands: 5, .NumConds: 6 }, |
| 2787 | // SP::V9MOVFCCrr - 775 |
| 2788 | {.AsmStrOffset: 8575, .AliasCondStart: 3491, .NumOperands: 5, .NumConds: 6 }, |
| 2789 | {.AsmStrOffset: 8591, .AliasCondStart: 3497, .NumOperands: 5, .NumConds: 6 }, |
| 2790 | {.AsmStrOffset: 8607, .AliasCondStart: 3503, .NumOperands: 5, .NumConds: 6 }, |
| 2791 | {.AsmStrOffset: 8623, .AliasCondStart: 3509, .NumOperands: 5, .NumConds: 6 }, |
| 2792 | {.AsmStrOffset: 8639, .AliasCondStart: 3515, .NumOperands: 5, .NumConds: 6 }, |
| 2793 | {.AsmStrOffset: 8656, .AliasCondStart: 3521, .NumOperands: 5, .NumConds: 6 }, |
| 2794 | {.AsmStrOffset: 8672, .AliasCondStart: 3527, .NumOperands: 5, .NumConds: 6 }, |
| 2795 | {.AsmStrOffset: 8689, .AliasCondStart: 3533, .NumOperands: 5, .NumConds: 6 }, |
| 2796 | {.AsmStrOffset: 8706, .AliasCondStart: 3539, .NumOperands: 5, .NumConds: 6 }, |
| 2797 | {.AsmStrOffset: 8723, .AliasCondStart: 3545, .NumOperands: 5, .NumConds: 6 }, |
| 2798 | {.AsmStrOffset: 8739, .AliasCondStart: 3551, .NumOperands: 5, .NumConds: 6 }, |
| 2799 | {.AsmStrOffset: 8756, .AliasCondStart: 3557, .NumOperands: 5, .NumConds: 6 }, |
| 2800 | {.AsmStrOffset: 8773, .AliasCondStart: 3563, .NumOperands: 5, .NumConds: 6 }, |
| 2801 | {.AsmStrOffset: 8791, .AliasCondStart: 3569, .NumOperands: 5, .NumConds: 6 }, |
| 2802 | {.AsmStrOffset: 8808, .AliasCondStart: 3575, .NumOperands: 5, .NumConds: 6 }, |
| 2803 | {.AsmStrOffset: 8826, .AliasCondStart: 3581, .NumOperands: 5, .NumConds: 6 }, |
| 2804 | // SP::WRASRri - 791 |
| 2805 | {.AsmStrOffset: 8842, .AliasCondStart: 3587, .NumOperands: 3, .NumConds: 3 }, |
| 2806 | // SP::WRASRrr - 792 |
| 2807 | {.AsmStrOffset: 8842, .AliasCondStart: 3590, .NumOperands: 3, .NumConds: 4 }, |
| 2808 | }; |
| 2809 | |
| 2810 | static const AliasPatternCond Conds[] = { |
| 2811 | // (BCOND brtarget:$imm, 8) - 0 |
| 2812 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2813 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 2814 | // (BCOND brtarget:$imm, 0) - 2 |
| 2815 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2816 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 2817 | // (BCOND brtarget:$imm, 9) - 4 |
| 2818 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2819 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 2820 | // (BCOND brtarget:$imm, 1) - 6 |
| 2821 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2822 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 2823 | // (BCOND brtarget:$imm, 10) - 8 |
| 2824 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2825 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 2826 | // (BCOND brtarget:$imm, 2) - 10 |
| 2827 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2828 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 2829 | // (BCOND brtarget:$imm, 11) - 12 |
| 2830 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2831 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 2832 | // (BCOND brtarget:$imm, 3) - 14 |
| 2833 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2834 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 2835 | // (BCOND brtarget:$imm, 12) - 16 |
| 2836 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2837 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 2838 | // (BCOND brtarget:$imm, 4) - 18 |
| 2839 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2840 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 2841 | // (BCOND brtarget:$imm, 13) - 20 |
| 2842 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2843 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 2844 | // (BCOND brtarget:$imm, 5) - 22 |
| 2845 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2846 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 2847 | // (BCOND brtarget:$imm, 14) - 24 |
| 2848 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2849 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 2850 | // (BCOND brtarget:$imm, 6) - 26 |
| 2851 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2852 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 2853 | // (BCOND brtarget:$imm, 15) - 28 |
| 2854 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2855 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 2856 | // (BCOND brtarget:$imm, 7) - 30 |
| 2857 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2858 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 2859 | // (BCONDA brtarget:$imm, 8) - 32 |
| 2860 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2861 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 2862 | // (BCONDA brtarget:$imm, 0) - 34 |
| 2863 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2864 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 2865 | // (BCONDA brtarget:$imm, 9) - 36 |
| 2866 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2867 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 2868 | // (BCONDA brtarget:$imm, 1) - 38 |
| 2869 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2870 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 2871 | // (BCONDA brtarget:$imm, 10) - 40 |
| 2872 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2873 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 2874 | // (BCONDA brtarget:$imm, 2) - 42 |
| 2875 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2876 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 2877 | // (BCONDA brtarget:$imm, 11) - 44 |
| 2878 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2879 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 2880 | // (BCONDA brtarget:$imm, 3) - 46 |
| 2881 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2882 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 2883 | // (BCONDA brtarget:$imm, 12) - 48 |
| 2884 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2885 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 2886 | // (BCONDA brtarget:$imm, 4) - 50 |
| 2887 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2888 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 2889 | // (BCONDA brtarget:$imm, 13) - 52 |
| 2890 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2891 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 2892 | // (BCONDA brtarget:$imm, 5) - 54 |
| 2893 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2894 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 2895 | // (BCONDA brtarget:$imm, 14) - 56 |
| 2896 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2897 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 2898 | // (BCONDA brtarget:$imm, 6) - 58 |
| 2899 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2900 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 2901 | // (BCONDA brtarget:$imm, 15) - 60 |
| 2902 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2903 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 2904 | // (BCONDA brtarget:$imm, 7) - 62 |
| 2905 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2906 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 2907 | // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc) - 64 |
| 2908 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2909 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 2910 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 2911 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 2912 | // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc) - 68 |
| 2913 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2914 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 2915 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 2916 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 2917 | // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc) - 72 |
| 2918 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2919 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 2920 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 2921 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 2922 | // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc) - 76 |
| 2923 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2924 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 2925 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 2926 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 2927 | // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc) - 80 |
| 2928 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2929 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 2930 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 2931 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 2932 | // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc) - 84 |
| 2933 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2934 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 2935 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 2936 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 2937 | // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc) - 88 |
| 2938 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2939 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 2940 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 2941 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 2942 | // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc) - 92 |
| 2943 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2944 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 2945 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 2946 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 2947 | // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc) - 96 |
| 2948 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2949 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 2950 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 2951 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 2952 | // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc) - 100 |
| 2953 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2954 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 2955 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 2956 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 2957 | // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc) - 104 |
| 2958 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2959 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 2960 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 2961 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 2962 | // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc) - 108 |
| 2963 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2964 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 2965 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 2966 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 2967 | // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc) - 112 |
| 2968 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2969 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 2970 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 2971 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 2972 | // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc) - 116 |
| 2973 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2974 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 2975 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 2976 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 2977 | // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc) - 120 |
| 2978 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2979 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 2980 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 2981 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 2982 | // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc) - 124 |
| 2983 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2984 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 2985 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 2986 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 2987 | // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc) - 128 |
| 2988 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2989 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 2990 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 2991 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 2992 | // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc) - 132 |
| 2993 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2994 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 2995 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 2996 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 2997 | // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc) - 136 |
| 2998 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 2999 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 3000 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 3001 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3002 | // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc) - 140 |
| 3003 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3004 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 3005 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 3006 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3007 | // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc) - 144 |
| 3008 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3009 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 3010 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 3011 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3012 | // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc) - 148 |
| 3013 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3014 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 3015 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 3016 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3017 | // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc) - 152 |
| 3018 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3019 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 3020 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 3021 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3022 | // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc) - 156 |
| 3023 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3024 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 3025 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 3026 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3027 | // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc) - 160 |
| 3028 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3029 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 3030 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 3031 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3032 | // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc) - 164 |
| 3033 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3034 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 3035 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 3036 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3037 | // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc) - 168 |
| 3038 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3039 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 3040 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 3041 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3042 | // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc) - 172 |
| 3043 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3044 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 3045 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 3046 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3047 | // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc) - 176 |
| 3048 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3049 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 3050 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 3051 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3052 | // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc) - 180 |
| 3053 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3054 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 3055 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 3056 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3057 | // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc) - 184 |
| 3058 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3059 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 3060 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 3061 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3062 | // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc) - 188 |
| 3063 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3064 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 3065 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 3066 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3067 | // (BPICCANT brtarget:$imm, 8) - 192 |
| 3068 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3069 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 3070 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3071 | // (BPICCANT brtarget:$imm, 8) - 195 |
| 3072 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3073 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 3074 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3075 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3076 | // (BPICCANT brtarget:$imm, 0) - 199 |
| 3077 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3078 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 3079 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3080 | // (BPICCANT brtarget:$imm, 0) - 202 |
| 3081 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3082 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 3083 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3084 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3085 | // (BPICCANT brtarget:$imm, 9) - 206 |
| 3086 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3087 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 3088 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3089 | // (BPICCANT brtarget:$imm, 9) - 209 |
| 3090 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3091 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 3092 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3093 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3094 | // (BPICCANT brtarget:$imm, 1) - 213 |
| 3095 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3096 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 3097 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3098 | // (BPICCANT brtarget:$imm, 1) - 216 |
| 3099 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3100 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 3101 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3102 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3103 | // (BPICCANT brtarget:$imm, 10) - 220 |
| 3104 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3105 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 3106 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3107 | // (BPICCANT brtarget:$imm, 10) - 223 |
| 3108 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3109 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 3110 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3111 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3112 | // (BPICCANT brtarget:$imm, 2) - 227 |
| 3113 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3114 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 3115 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3116 | // (BPICCANT brtarget:$imm, 2) - 230 |
| 3117 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3118 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 3119 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3120 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3121 | // (BPICCANT brtarget:$imm, 11) - 234 |
| 3122 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3123 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 3124 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3125 | // (BPICCANT brtarget:$imm, 11) - 237 |
| 3126 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3127 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 3128 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3129 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3130 | // (BPICCANT brtarget:$imm, 3) - 241 |
| 3131 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3132 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 3133 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3134 | // (BPICCANT brtarget:$imm, 3) - 244 |
| 3135 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3136 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 3137 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3138 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3139 | // (BPICCANT brtarget:$imm, 12) - 248 |
| 3140 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3141 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 3142 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3143 | // (BPICCANT brtarget:$imm, 12) - 251 |
| 3144 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3145 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 3146 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3147 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3148 | // (BPICCANT brtarget:$imm, 4) - 255 |
| 3149 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3150 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 3151 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3152 | // (BPICCANT brtarget:$imm, 4) - 258 |
| 3153 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3154 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 3155 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3156 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3157 | // (BPICCANT brtarget:$imm, 13) - 262 |
| 3158 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3159 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 3160 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3161 | // (BPICCANT brtarget:$imm, 13) - 265 |
| 3162 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3163 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 3164 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3165 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3166 | // (BPICCANT brtarget:$imm, 5) - 269 |
| 3167 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3168 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 3169 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3170 | // (BPICCANT brtarget:$imm, 5) - 272 |
| 3171 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3172 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 3173 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3174 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3175 | // (BPICCANT brtarget:$imm, 14) - 276 |
| 3176 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3177 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 3178 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3179 | // (BPICCANT brtarget:$imm, 14) - 279 |
| 3180 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3181 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 3182 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3183 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3184 | // (BPICCANT brtarget:$imm, 6) - 283 |
| 3185 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3186 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 3187 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3188 | // (BPICCANT brtarget:$imm, 6) - 286 |
| 3189 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3190 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 3191 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3192 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3193 | // (BPICCANT brtarget:$imm, 15) - 290 |
| 3194 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3195 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 3196 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3197 | // (BPICCANT brtarget:$imm, 15) - 293 |
| 3198 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3199 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 3200 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3201 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3202 | // (BPICCANT brtarget:$imm, 7) - 297 |
| 3203 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3204 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 3205 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3206 | // (BPICCANT brtarget:$imm, 7) - 300 |
| 3207 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3208 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 3209 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3210 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3211 | // (BPICCNT brtarget:$imm, 8) - 304 |
| 3212 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3213 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 3214 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3215 | // (BPICCNT brtarget:$imm, 8) - 307 |
| 3216 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3217 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 3218 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3219 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3220 | // (BPICCNT brtarget:$imm, 0) - 311 |
| 3221 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3222 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 3223 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3224 | // (BPICCNT brtarget:$imm, 0) - 314 |
| 3225 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3226 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 3227 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3228 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3229 | // (BPICCNT brtarget:$imm, 9) - 318 |
| 3230 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3231 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 3232 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3233 | // (BPICCNT brtarget:$imm, 9) - 321 |
| 3234 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3235 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 3236 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3237 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3238 | // (BPICCNT brtarget:$imm, 1) - 325 |
| 3239 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3240 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 3241 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3242 | // (BPICCNT brtarget:$imm, 1) - 328 |
| 3243 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3244 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 3245 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3246 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3247 | // (BPICCNT brtarget:$imm, 10) - 332 |
| 3248 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3249 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 3250 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3251 | // (BPICCNT brtarget:$imm, 10) - 335 |
| 3252 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3253 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 3254 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3255 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3256 | // (BPICCNT brtarget:$imm, 2) - 339 |
| 3257 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3258 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 3259 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3260 | // (BPICCNT brtarget:$imm, 2) - 342 |
| 3261 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3262 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 3263 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3264 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3265 | // (BPICCNT brtarget:$imm, 11) - 346 |
| 3266 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3267 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 3268 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3269 | // (BPICCNT brtarget:$imm, 11) - 349 |
| 3270 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3271 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 3272 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3273 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3274 | // (BPICCNT brtarget:$imm, 3) - 353 |
| 3275 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3276 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 3277 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3278 | // (BPICCNT brtarget:$imm, 3) - 356 |
| 3279 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3280 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 3281 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3282 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3283 | // (BPICCNT brtarget:$imm, 12) - 360 |
| 3284 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3285 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 3286 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3287 | // (BPICCNT brtarget:$imm, 12) - 363 |
| 3288 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3289 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 3290 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3291 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3292 | // (BPICCNT brtarget:$imm, 4) - 367 |
| 3293 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3294 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 3295 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3296 | // (BPICCNT brtarget:$imm, 4) - 370 |
| 3297 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3298 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 3299 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3300 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3301 | // (BPICCNT brtarget:$imm, 13) - 374 |
| 3302 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3303 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 3304 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3305 | // (BPICCNT brtarget:$imm, 13) - 377 |
| 3306 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3307 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 3308 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3309 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3310 | // (BPICCNT brtarget:$imm, 5) - 381 |
| 3311 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3312 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 3313 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3314 | // (BPICCNT brtarget:$imm, 5) - 384 |
| 3315 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3316 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 3317 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3318 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3319 | // (BPICCNT brtarget:$imm, 14) - 388 |
| 3320 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3321 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 3322 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3323 | // (BPICCNT brtarget:$imm, 14) - 391 |
| 3324 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3325 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 3326 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3327 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3328 | // (BPICCNT brtarget:$imm, 6) - 395 |
| 3329 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3330 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 3331 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3332 | // (BPICCNT brtarget:$imm, 6) - 398 |
| 3333 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3334 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 3335 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3336 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3337 | // (BPICCNT brtarget:$imm, 15) - 402 |
| 3338 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3339 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 3340 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3341 | // (BPICCNT brtarget:$imm, 15) - 405 |
| 3342 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3343 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 3344 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3345 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3346 | // (BPICCNT brtarget:$imm, 7) - 409 |
| 3347 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3348 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 3349 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3350 | // (BPICCNT brtarget:$imm, 7) - 412 |
| 3351 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3352 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 3353 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3354 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3355 | // (BPRANT bprtarget16:$imm, 2, I64Regs:$rs1) - 416 |
| 3356 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3357 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 3358 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 3359 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 3360 | // (BPRANT bprtarget16:$imm, 3, I64Regs:$rs1) - 420 |
| 3361 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3362 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 3363 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 3364 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 3365 | // (BPRANT bprtarget16:$imm, 6, I64Regs:$rs1) - 424 |
| 3366 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3367 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 3368 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 3369 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 3370 | // (BPRANT bprtarget16:$imm, 7, I64Regs:$rs1) - 428 |
| 3371 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3372 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 3373 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 3374 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 3375 | // (BPRNT bprtarget16:$imm, 2, I64Regs:$rs1) - 432 |
| 3376 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3377 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 3378 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 3379 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 3380 | // (BPRNT bprtarget16:$imm, 3, I64Regs:$rs1) - 436 |
| 3381 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3382 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 3383 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 3384 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 3385 | // (BPRNT bprtarget16:$imm, 6, I64Regs:$rs1) - 440 |
| 3386 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3387 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 3388 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 3389 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 3390 | // (BPRNT bprtarget16:$imm, 7, I64Regs:$rs1) - 444 |
| 3391 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3392 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 3393 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 3394 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 3395 | // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 128) - 448 |
| 3396 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3397 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3398 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3399 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3400 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(128)}, |
| 3401 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3402 | // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 136) - 454 |
| 3403 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3404 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3405 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3406 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3407 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(136)}, |
| 3408 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3409 | // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 128) - 460 |
| 3410 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 3411 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 3412 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 3413 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3414 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(128)}, |
| 3415 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3416 | // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 136) - 466 |
| 3417 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 3418 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 3419 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 3420 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3421 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(136)}, |
| 3422 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3423 | // (CWBCONDri cbtarget:$imm, 9, IntRegs:$rs1, simm5Op:$simm5) - 472 |
| 3424 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3425 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 3426 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3427 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3428 | // (CWBCONDri cbtarget:$imm, 1, IntRegs:$rs1, simm5Op:$simm5) - 476 |
| 3429 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3430 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 3431 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3432 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3433 | // (CWBCONDri cbtarget:$imm, 10, IntRegs:$rs1, simm5Op:$simm5) - 480 |
| 3434 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3435 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 3436 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3437 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3438 | // (CWBCONDri cbtarget:$imm, 2, IntRegs:$rs1, simm5Op:$simm5) - 484 |
| 3439 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3440 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 3441 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3442 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3443 | // (CWBCONDri cbtarget:$imm, 11, IntRegs:$rs1, simm5Op:$simm5) - 488 |
| 3444 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3445 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 3446 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3447 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3448 | // (CWBCONDri cbtarget:$imm, 3, IntRegs:$rs1, simm5Op:$simm5) - 492 |
| 3449 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3450 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 3451 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3452 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3453 | // (CWBCONDri cbtarget:$imm, 12, IntRegs:$rs1, simm5Op:$simm5) - 496 |
| 3454 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3455 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 3456 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3457 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3458 | // (CWBCONDri cbtarget:$imm, 4, IntRegs:$rs1, simm5Op:$simm5) - 500 |
| 3459 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3460 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 3461 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3462 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3463 | // (CWBCONDri cbtarget:$imm, 13, IntRegs:$rs1, simm5Op:$simm5) - 504 |
| 3464 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3465 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 3466 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3467 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3468 | // (CWBCONDri cbtarget:$imm, 5, IntRegs:$rs1, simm5Op:$simm5) - 508 |
| 3469 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3470 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 3471 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3472 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3473 | // (CWBCONDri cbtarget:$imm, 14, IntRegs:$rs1, simm5Op:$simm5) - 512 |
| 3474 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3475 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 3476 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3477 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3478 | // (CWBCONDri cbtarget:$imm, 6, IntRegs:$rs1, simm5Op:$simm5) - 516 |
| 3479 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3480 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 3481 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3482 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3483 | // (CWBCONDri cbtarget:$imm, 15, IntRegs:$rs1, simm5Op:$simm5) - 520 |
| 3484 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3485 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 3486 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3487 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3488 | // (CWBCONDri cbtarget:$imm, 7, IntRegs:$rs1, simm5Op:$simm5) - 524 |
| 3489 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3490 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 3491 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3492 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3493 | // (CWBCONDrr cbtarget:$imm, 9, IntRegs:$rs1, IntRegs:$rs2) - 528 |
| 3494 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3495 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 3496 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3497 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3498 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3499 | // (CWBCONDrr cbtarget:$imm, 1, IntRegs:$rs1, IntRegs:$rs2) - 533 |
| 3500 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3501 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 3502 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3503 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3504 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3505 | // (CWBCONDrr cbtarget:$imm, 10, IntRegs:$rs1, IntRegs:$rs2) - 538 |
| 3506 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3507 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 3508 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3509 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3510 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3511 | // (CWBCONDrr cbtarget:$imm, 2, IntRegs:$rs1, IntRegs:$rs2) - 543 |
| 3512 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3513 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 3514 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3515 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3516 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3517 | // (CWBCONDrr cbtarget:$imm, 11, IntRegs:$rs1, IntRegs:$rs2) - 548 |
| 3518 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3519 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 3520 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3521 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3522 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3523 | // (CWBCONDrr cbtarget:$imm, 3, IntRegs:$rs1, IntRegs:$rs2) - 553 |
| 3524 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3525 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 3526 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3527 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3528 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3529 | // (CWBCONDrr cbtarget:$imm, 12, IntRegs:$rs1, IntRegs:$rs2) - 558 |
| 3530 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3531 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 3532 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3533 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3534 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3535 | // (CWBCONDrr cbtarget:$imm, 4, IntRegs:$rs1, IntRegs:$rs2) - 563 |
| 3536 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3537 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 3538 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3539 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3540 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3541 | // (CWBCONDrr cbtarget:$imm, 13, IntRegs:$rs1, IntRegs:$rs2) - 568 |
| 3542 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3543 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 3544 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3545 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3546 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3547 | // (CWBCONDrr cbtarget:$imm, 5, IntRegs:$rs1, IntRegs:$rs2) - 573 |
| 3548 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3549 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 3550 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3551 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3552 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3553 | // (CWBCONDrr cbtarget:$imm, 14, IntRegs:$rs1, IntRegs:$rs2) - 578 |
| 3554 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3555 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 3556 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3557 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3558 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3559 | // (CWBCONDrr cbtarget:$imm, 6, IntRegs:$rs1, IntRegs:$rs2) - 583 |
| 3560 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3561 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 3562 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3563 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3564 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3565 | // (CWBCONDrr cbtarget:$imm, 15, IntRegs:$rs1, IntRegs:$rs2) - 588 |
| 3566 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3567 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 3568 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3569 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3570 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3571 | // (CWBCONDrr cbtarget:$imm, 7, IntRegs:$rs1, IntRegs:$rs2) - 593 |
| 3572 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3573 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 3574 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3575 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3576 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3577 | // (CXBCONDri cbtarget:$imm, 9, IntRegs:$rs1, simm5Op:$simm5) - 598 |
| 3578 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3579 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 3580 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3581 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3582 | // (CXBCONDri cbtarget:$imm, 1, IntRegs:$rs1, simm5Op:$simm5) - 602 |
| 3583 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3584 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 3585 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3586 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3587 | // (CXBCONDri cbtarget:$imm, 10, IntRegs:$rs1, simm5Op:$simm5) - 606 |
| 3588 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3589 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 3590 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3591 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3592 | // (CXBCONDri cbtarget:$imm, 2, IntRegs:$rs1, simm5Op:$simm5) - 610 |
| 3593 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3594 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 3595 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3596 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3597 | // (CXBCONDri cbtarget:$imm, 11, IntRegs:$rs1, simm5Op:$simm5) - 614 |
| 3598 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3599 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 3600 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3601 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3602 | // (CXBCONDri cbtarget:$imm, 3, IntRegs:$rs1, simm5Op:$simm5) - 618 |
| 3603 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3604 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 3605 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3606 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3607 | // (CXBCONDri cbtarget:$imm, 12, IntRegs:$rs1, simm5Op:$simm5) - 622 |
| 3608 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3609 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 3610 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3611 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3612 | // (CXBCONDri cbtarget:$imm, 4, IntRegs:$rs1, simm5Op:$simm5) - 626 |
| 3613 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3614 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 3615 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3616 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3617 | // (CXBCONDri cbtarget:$imm, 13, IntRegs:$rs1, simm5Op:$simm5) - 630 |
| 3618 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3619 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 3620 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3621 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3622 | // (CXBCONDri cbtarget:$imm, 5, IntRegs:$rs1, simm5Op:$simm5) - 634 |
| 3623 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3624 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 3625 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3626 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3627 | // (CXBCONDri cbtarget:$imm, 14, IntRegs:$rs1, simm5Op:$simm5) - 638 |
| 3628 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3629 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 3630 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3631 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3632 | // (CXBCONDri cbtarget:$imm, 6, IntRegs:$rs1, simm5Op:$simm5) - 642 |
| 3633 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3634 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 3635 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3636 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3637 | // (CXBCONDri cbtarget:$imm, 15, IntRegs:$rs1, simm5Op:$simm5) - 646 |
| 3638 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3639 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 3640 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3641 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3642 | // (CXBCONDri cbtarget:$imm, 7, IntRegs:$rs1, simm5Op:$simm5) - 650 |
| 3643 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3644 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 3645 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3646 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3647 | // (CXBCONDrr cbtarget:$imm, 9, IntRegs:$rs1, IntRegs:$rs2) - 654 |
| 3648 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3649 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 3650 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3651 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3652 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3653 | // (CXBCONDrr cbtarget:$imm, 1, IntRegs:$rs1, IntRegs:$rs2) - 659 |
| 3654 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3655 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 3656 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3657 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3658 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3659 | // (CXBCONDrr cbtarget:$imm, 10, IntRegs:$rs1, IntRegs:$rs2) - 664 |
| 3660 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3661 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 3662 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3663 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3664 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3665 | // (CXBCONDrr cbtarget:$imm, 2, IntRegs:$rs1, IntRegs:$rs2) - 669 |
| 3666 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3667 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 3668 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3669 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3670 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3671 | // (CXBCONDrr cbtarget:$imm, 11, IntRegs:$rs1, IntRegs:$rs2) - 674 |
| 3672 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3673 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 3674 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3675 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3676 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3677 | // (CXBCONDrr cbtarget:$imm, 3, IntRegs:$rs1, IntRegs:$rs2) - 679 |
| 3678 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3679 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 3680 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3681 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3682 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3683 | // (CXBCONDrr cbtarget:$imm, 12, IntRegs:$rs1, IntRegs:$rs2) - 684 |
| 3684 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3685 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 3686 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3687 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3688 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3689 | // (CXBCONDrr cbtarget:$imm, 4, IntRegs:$rs1, IntRegs:$rs2) - 689 |
| 3690 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3691 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 3692 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3693 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3694 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3695 | // (CXBCONDrr cbtarget:$imm, 13, IntRegs:$rs1, IntRegs:$rs2) - 694 |
| 3696 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3697 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 3698 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3699 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3700 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3701 | // (CXBCONDrr cbtarget:$imm, 5, IntRegs:$rs1, IntRegs:$rs2) - 699 |
| 3702 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3703 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 3704 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3705 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3706 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3707 | // (CXBCONDrr cbtarget:$imm, 14, IntRegs:$rs1, IntRegs:$rs2) - 704 |
| 3708 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3709 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 3710 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3711 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3712 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3713 | // (CXBCONDrr cbtarget:$imm, 6, IntRegs:$rs1, IntRegs:$rs2) - 709 |
| 3714 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3715 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 3716 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3717 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3718 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3719 | // (CXBCONDrr cbtarget:$imm, 15, IntRegs:$rs1, IntRegs:$rs2) - 714 |
| 3720 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3721 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 3722 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3723 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3724 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3725 | // (CXBCONDrr cbtarget:$imm, 7, IntRegs:$rs1, IntRegs:$rs2) - 719 |
| 3726 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3727 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 3728 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3729 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 3730 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 3731 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8) - 724 |
| 3732 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3733 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3734 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3735 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 3736 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3737 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8) - 729 |
| 3738 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3739 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3740 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3741 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 3742 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3743 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3744 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0) - 735 |
| 3745 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3746 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3747 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3748 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 3749 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3750 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0) - 740 |
| 3751 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3752 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3753 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3754 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 3755 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3756 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3757 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9) - 746 |
| 3758 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3759 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3760 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3761 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 3762 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3763 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9) - 751 |
| 3764 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3765 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3766 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3767 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 3768 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3769 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3770 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1) - 757 |
| 3771 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3772 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3773 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3774 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 3775 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3776 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1) - 762 |
| 3777 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3778 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3779 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3780 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 3781 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3782 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3783 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10) - 768 |
| 3784 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3785 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3786 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3787 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 3788 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3789 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10) - 773 |
| 3790 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3791 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3792 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3793 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 3794 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3795 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3796 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2) - 779 |
| 3797 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3798 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3799 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3800 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 3801 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3802 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2) - 784 |
| 3803 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3804 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3805 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3806 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 3807 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3808 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3809 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11) - 790 |
| 3810 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3811 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3812 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3813 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 3814 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3815 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11) - 795 |
| 3816 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3817 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3818 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3819 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 3820 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3821 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3822 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3) - 801 |
| 3823 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3824 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3825 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3826 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 3827 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3828 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3) - 806 |
| 3829 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3830 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3831 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3832 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 3833 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3834 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3835 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12) - 812 |
| 3836 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3837 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3838 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3839 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 3840 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3841 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12) - 817 |
| 3842 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3843 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3844 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3845 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 3846 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3847 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3848 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4) - 823 |
| 3849 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3850 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3851 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3852 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 3853 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3854 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4) - 828 |
| 3855 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3856 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3857 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3858 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 3859 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3860 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3861 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13) - 834 |
| 3862 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3863 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3864 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3865 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 3866 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3867 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13) - 839 |
| 3868 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3869 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3870 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3871 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 3872 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3873 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3874 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5) - 845 |
| 3875 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3876 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3877 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3878 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 3879 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3880 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5) - 850 |
| 3881 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3882 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3883 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3884 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 3885 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3886 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3887 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14) - 856 |
| 3888 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3889 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3890 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3891 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 3892 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3893 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14) - 861 |
| 3894 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3895 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3896 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3897 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 3898 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3899 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3900 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6) - 867 |
| 3901 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3902 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3903 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3904 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 3905 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3906 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6) - 872 |
| 3907 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3908 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3909 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3910 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 3911 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3912 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3913 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15) - 878 |
| 3914 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3915 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3916 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3917 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 3918 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3919 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15) - 883 |
| 3920 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3921 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3922 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3923 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 3924 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3925 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3926 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7) - 889 |
| 3927 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3928 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3929 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3930 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 3931 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3932 | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7) - 894 |
| 3933 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3934 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 3935 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3936 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 3937 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3938 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3939 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8) - 900 |
| 3940 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 3941 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 3942 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3943 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 3944 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3945 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8) - 905 |
| 3946 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 3947 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 3948 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3949 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 3950 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3951 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3952 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0) - 911 |
| 3953 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 3954 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 3955 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3956 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 3957 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3958 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0) - 916 |
| 3959 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 3960 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 3961 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3962 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 3963 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3964 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3965 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9) - 922 |
| 3966 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 3967 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 3968 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3969 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 3970 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3971 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9) - 927 |
| 3972 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 3973 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 3974 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3975 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 3976 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3977 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3978 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1) - 933 |
| 3979 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 3980 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 3981 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3982 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 3983 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3984 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1) - 938 |
| 3985 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 3986 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 3987 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3988 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 3989 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3990 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 3991 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10) - 944 |
| 3992 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 3993 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 3994 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 3995 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 3996 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 3997 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10) - 949 |
| 3998 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 3999 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4000 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4001 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 4002 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4003 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4004 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2) - 955 |
| 4005 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4006 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4007 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4008 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 4009 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4010 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2) - 960 |
| 4011 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4012 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4013 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4014 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 4015 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4016 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4017 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11) - 966 |
| 4018 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4019 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4020 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4021 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 4022 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4023 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11) - 971 |
| 4024 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4025 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4026 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4027 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 4028 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4029 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4030 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3) - 977 |
| 4031 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4032 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4033 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4034 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 4035 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4036 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3) - 982 |
| 4037 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4038 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4039 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4040 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 4041 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4042 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4043 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12) - 988 |
| 4044 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4045 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4046 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4047 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 4048 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4049 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12) - 993 |
| 4050 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4051 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4052 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4053 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 4054 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4055 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4056 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4) - 999 |
| 4057 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4058 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4059 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4060 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 4061 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4062 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4) - 1004 |
| 4063 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4064 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4065 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4066 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 4067 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4068 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4069 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13) - 1010 |
| 4070 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4071 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4072 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4073 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 4074 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4075 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13) - 1015 |
| 4076 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4077 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4078 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4079 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 4080 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4081 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4082 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5) - 1021 |
| 4083 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4084 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4085 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4086 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 4087 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4088 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5) - 1026 |
| 4089 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4090 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4091 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4092 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 4093 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4094 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4095 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14) - 1032 |
| 4096 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4097 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4098 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4099 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 4100 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4101 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14) - 1037 |
| 4102 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4103 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4104 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4105 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 4106 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4107 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4108 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6) - 1043 |
| 4109 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4110 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4111 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4112 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 4113 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4114 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6) - 1048 |
| 4115 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4116 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4117 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4118 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 4119 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4120 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4121 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15) - 1054 |
| 4122 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4123 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4124 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4125 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 4126 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4127 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15) - 1059 |
| 4128 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4129 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4130 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4131 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 4132 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4133 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4134 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7) - 1065 |
| 4135 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4136 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4137 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4138 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 4139 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4140 | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7) - 1070 |
| 4141 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4142 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4143 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4144 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 4145 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4146 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4147 | // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 2) - 1076 |
| 4148 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 4149 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 4150 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 4151 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4152 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 4153 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 4154 | // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 3) - 1082 |
| 4155 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 4156 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 4157 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 4158 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4159 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 4160 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 4161 | // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 6) - 1088 |
| 4162 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 4163 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 4164 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 4165 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4166 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 4167 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 4168 | // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 7) - 1094 |
| 4169 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 4170 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 4171 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 4172 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4173 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 4174 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 4175 | // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 2) - 1100 |
| 4176 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4177 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 4178 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4179 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4180 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 4181 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 4182 | // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 3) - 1106 |
| 4183 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4184 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 4185 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4186 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4187 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 4188 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 4189 | // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 6) - 1112 |
| 4190 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4191 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 4192 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4193 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4194 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 4195 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 4196 | // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 7) - 1118 |
| 4197 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4198 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 4199 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 4200 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4201 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 4202 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 4203 | // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 2) - 1124 |
| 4204 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4205 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 4206 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4207 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4208 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 4209 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 4210 | // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 3) - 1130 |
| 4211 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4212 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 4213 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4214 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4215 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 4216 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 4217 | // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 6) - 1136 |
| 4218 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4219 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 4220 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4221 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4222 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 4223 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 4224 | // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 7) - 1142 |
| 4225 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4226 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 4227 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4228 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4229 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 4230 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 4231 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8) - 1148 |
| 4232 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4233 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4234 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4235 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 4236 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4237 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8) - 1153 |
| 4238 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4239 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4240 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4241 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 4242 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4243 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4244 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0) - 1159 |
| 4245 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4246 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4247 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4248 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 4249 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4250 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0) - 1164 |
| 4251 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4252 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4253 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4254 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 4255 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4256 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4257 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9) - 1170 |
| 4258 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4259 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4260 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4261 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 4262 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4263 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9) - 1175 |
| 4264 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4265 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4266 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4267 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 4268 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4269 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4270 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1) - 1181 |
| 4271 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4272 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4273 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4274 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 4275 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4276 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1) - 1186 |
| 4277 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4278 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4279 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4280 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 4281 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4282 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4283 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10) - 1192 |
| 4284 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4285 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4286 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4287 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 4288 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4289 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10) - 1197 |
| 4290 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4291 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4292 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4293 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 4294 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4295 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4296 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2) - 1203 |
| 4297 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4298 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4299 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4300 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 4301 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4302 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2) - 1208 |
| 4303 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4304 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4305 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4306 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 4307 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4308 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4309 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11) - 1214 |
| 4310 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4311 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4312 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4313 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 4314 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4315 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11) - 1219 |
| 4316 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4317 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4318 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4319 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 4320 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4321 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4322 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3) - 1225 |
| 4323 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4324 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4325 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4326 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 4327 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4328 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3) - 1230 |
| 4329 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4330 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4331 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4332 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 4333 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4334 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4335 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12) - 1236 |
| 4336 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4337 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4338 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4339 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 4340 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4341 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12) - 1241 |
| 4342 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4343 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4344 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4345 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 4346 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4347 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4348 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4) - 1247 |
| 4349 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4350 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4351 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4352 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 4353 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4354 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4) - 1252 |
| 4355 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4356 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4357 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4358 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 4359 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4360 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4361 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13) - 1258 |
| 4362 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4363 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4364 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4365 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 4366 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4367 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13) - 1263 |
| 4368 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4369 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4370 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4371 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 4372 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4373 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4374 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5) - 1269 |
| 4375 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4376 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4377 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4378 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 4379 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4380 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5) - 1274 |
| 4381 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4382 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4383 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4384 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 4385 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4386 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4387 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14) - 1280 |
| 4388 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4389 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4390 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4391 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 4392 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4393 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14) - 1285 |
| 4394 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4395 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4396 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4397 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 4398 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4399 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4400 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6) - 1291 |
| 4401 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4402 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4403 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4404 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 4405 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4406 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6) - 1296 |
| 4407 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4408 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4409 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4410 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 4411 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4412 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4413 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15) - 1302 |
| 4414 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4415 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4416 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4417 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 4418 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4419 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15) - 1307 |
| 4420 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4421 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4422 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4423 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 4424 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4425 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4426 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7) - 1313 |
| 4427 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4428 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4429 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4430 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 4431 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4432 | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7) - 1318 |
| 4433 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4434 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 4435 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4436 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 4437 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4438 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4439 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8) - 1324 |
| 4440 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4441 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4442 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4443 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 4444 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4445 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8) - 1329 |
| 4446 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4447 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4448 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4449 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 4450 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4451 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4452 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0) - 1335 |
| 4453 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4454 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4455 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4456 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 4457 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4458 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0) - 1340 |
| 4459 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4460 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4461 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4462 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 4463 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4464 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4465 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9) - 1346 |
| 4466 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4467 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4468 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4469 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 4470 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4471 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9) - 1351 |
| 4472 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4473 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4474 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4475 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 4476 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4477 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4478 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1) - 1357 |
| 4479 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4480 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4481 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4482 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 4483 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4484 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1) - 1362 |
| 4485 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4486 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4487 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4488 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 4489 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4490 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4491 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10) - 1368 |
| 4492 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4493 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4494 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4495 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 4496 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4497 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10) - 1373 |
| 4498 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4499 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4500 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4501 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 4502 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4503 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4504 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2) - 1379 |
| 4505 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4506 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4507 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4508 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 4509 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4510 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2) - 1384 |
| 4511 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4512 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4513 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4514 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 4515 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4516 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4517 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11) - 1390 |
| 4518 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4519 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4520 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4521 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 4522 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4523 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11) - 1395 |
| 4524 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4525 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4526 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4527 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 4528 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4529 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4530 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3) - 1401 |
| 4531 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4532 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4533 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4534 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 4535 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4536 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3) - 1406 |
| 4537 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4538 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4539 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4540 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 4541 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4542 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4543 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12) - 1412 |
| 4544 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4545 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4546 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4547 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 4548 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4549 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12) - 1417 |
| 4550 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4551 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4552 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4553 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 4554 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4555 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4556 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4) - 1423 |
| 4557 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4558 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4559 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4560 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 4561 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4562 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4) - 1428 |
| 4563 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4564 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4565 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4566 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 4567 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4568 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4569 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13) - 1434 |
| 4570 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4571 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4572 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4573 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 4574 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4575 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13) - 1439 |
| 4576 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4577 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4578 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4579 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 4580 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4581 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4582 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5) - 1445 |
| 4583 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4584 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4585 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4586 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 4587 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4588 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5) - 1450 |
| 4589 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4590 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4591 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4592 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 4593 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4594 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4595 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14) - 1456 |
| 4596 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4597 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4598 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4599 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 4600 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4601 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14) - 1461 |
| 4602 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4603 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4604 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4605 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 4606 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4607 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4608 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6) - 1467 |
| 4609 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4610 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4611 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4612 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 4613 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4614 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6) - 1472 |
| 4615 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4616 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4617 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4618 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 4619 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4620 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4621 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15) - 1478 |
| 4622 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4623 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4624 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4625 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 4626 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4627 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15) - 1483 |
| 4628 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4629 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4630 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4631 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 4632 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4633 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4634 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7) - 1489 |
| 4635 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4636 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4637 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4638 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 4639 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4640 | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7) - 1494 |
| 4641 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4642 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4643 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4644 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 4645 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4646 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4647 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1500 |
| 4648 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4649 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4650 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4651 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 4652 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4653 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1505 |
| 4654 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4655 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4656 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4657 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 4658 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4659 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4660 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1511 |
| 4661 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4662 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4663 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4664 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 4665 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4666 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1516 |
| 4667 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4668 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4669 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4670 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 4671 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4672 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4673 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1522 |
| 4674 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4675 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4676 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4677 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 4678 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4679 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1527 |
| 4680 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4681 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4682 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4683 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 4684 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4685 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4686 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1533 |
| 4687 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4688 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4689 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4690 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 4691 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4692 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1538 |
| 4693 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4694 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4695 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4696 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 4697 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4698 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4699 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1544 |
| 4700 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4701 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4702 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4703 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 4704 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4705 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1549 |
| 4706 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4707 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4708 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4709 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 4710 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4711 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4712 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1555 |
| 4713 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4714 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4715 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4716 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 4717 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4718 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1560 |
| 4719 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4720 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4721 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4722 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 4723 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4724 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4725 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1566 |
| 4726 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4727 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4728 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4729 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 4730 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4731 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1571 |
| 4732 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4733 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4734 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4735 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 4736 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4737 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4738 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1577 |
| 4739 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4740 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4741 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4742 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 4743 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4744 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1582 |
| 4745 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4746 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4747 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4748 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 4749 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4750 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4751 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1588 |
| 4752 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4753 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4754 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4755 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 4756 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4757 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1593 |
| 4758 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4759 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4760 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4761 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 4762 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4763 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4764 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1599 |
| 4765 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4766 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4767 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4768 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 4769 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4770 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1604 |
| 4771 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4772 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4773 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4774 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 4775 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4776 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4777 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1610 |
| 4778 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4779 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4780 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4781 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 4782 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4783 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1615 |
| 4784 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4785 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4786 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4787 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 4788 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4789 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4790 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1621 |
| 4791 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4792 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4793 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4794 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 4795 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4796 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1626 |
| 4797 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4798 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4799 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4800 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 4801 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4802 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4803 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1632 |
| 4804 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4805 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4806 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4807 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 4808 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4809 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1637 |
| 4810 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4811 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4812 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4813 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 4814 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4815 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4816 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1643 |
| 4817 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4818 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4819 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4820 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 4821 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4822 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1648 |
| 4823 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4824 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4825 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4826 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 4827 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4828 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4829 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1654 |
| 4830 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4831 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4832 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4833 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 4834 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4835 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1659 |
| 4836 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4837 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4838 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4839 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 4840 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4841 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4842 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1665 |
| 4843 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4844 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4845 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4846 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 4847 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4848 | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1670 |
| 4849 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4850 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4851 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4852 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 4853 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4854 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4855 | // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 2) - 1676 |
| 4856 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4857 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 4858 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4859 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4860 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 4861 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 4862 | // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 3) - 1682 |
| 4863 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4864 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 4865 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4866 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4867 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 4868 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 4869 | // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 6) - 1688 |
| 4870 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4871 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 4872 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4873 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4874 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 4875 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 4876 | // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 7) - 1694 |
| 4877 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4878 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 4879 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4880 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4881 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 4882 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 4883 | // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 2) - 1700 |
| 4884 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4885 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 4886 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4887 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4888 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 4889 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 4890 | // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 3) - 1706 |
| 4891 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4892 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 4893 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4894 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4895 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 4896 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 4897 | // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 6) - 1712 |
| 4898 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4899 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 4900 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4901 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4902 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 4903 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 4904 | // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 7) - 1718 |
| 4905 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4906 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID}, |
| 4907 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4908 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4909 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 4910 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 4911 | // (ORCCrr G0, IntRegs:$rs2, G0) - 1724 |
| 4912 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 4913 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4914 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 4915 | // (ORri IntRegs:$rd, G0, simm13Op:$simm13) - 1727 |
| 4916 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4917 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 4918 | // (ORrr IntRegs:$rd, G0, IntRegs:$rs2) - 1729 |
| 4919 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4920 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 4921 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4922 | // (RESTORErr G0, G0, G0) - 1732 |
| 4923 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 4924 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 4925 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 4926 | // (RET 8) - 1735 |
| 4927 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 4928 | // (RETL 8) - 1736 |
| 4929 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 4930 | // (SAVErr G0, G0, G0) - 1737 |
| 4931 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 4932 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 4933 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 4934 | // (SUBCCri G0, IntRegs:$rs1, simm13Op:$imm) - 1740 |
| 4935 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 4936 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4937 | // (SUBCCrr G0, IntRegs:$rs1, IntRegs:$rs2) - 1742 |
| 4938 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 4939 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4940 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4941 | // (TICCri G0, i32imm:$imm, 8) - 1745 |
| 4942 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 4943 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4944 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 4945 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4946 | // (TICCri G0, i32imm:$imm, 8) - 1749 |
| 4947 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 4948 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4949 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 4950 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4951 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4952 | // (TICCri IntRegs:$rs1, i32imm:$imm, 8) - 1754 |
| 4953 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4954 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4955 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 4956 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4957 | // (TICCri IntRegs:$rs1, i32imm:$imm, 8) - 1758 |
| 4958 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4959 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4960 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 4961 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4962 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4963 | // (TICCri G0, i32imm:$imm, 0) - 1763 |
| 4964 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 4965 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4966 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 4967 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4968 | // (TICCri G0, i32imm:$imm, 0) - 1767 |
| 4969 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 4970 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4971 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 4972 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4973 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4974 | // (TICCri IntRegs:$rs1, i32imm:$imm, 0) - 1772 |
| 4975 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4976 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4977 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 4978 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4979 | // (TICCri IntRegs:$rs1, i32imm:$imm, 0) - 1776 |
| 4980 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4981 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4982 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 4983 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4984 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4985 | // (TICCri G0, i32imm:$imm, 9) - 1781 |
| 4986 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 4987 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4988 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 4989 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4990 | // (TICCri G0, i32imm:$imm, 9) - 1785 |
| 4991 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 4992 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4993 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 4994 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 4995 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 4996 | // (TICCri IntRegs:$rs1, i32imm:$imm, 9) - 1790 |
| 4997 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 4998 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 4999 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 5000 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5001 | // (TICCri IntRegs:$rs1, i32imm:$imm, 9) - 1794 |
| 5002 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5003 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5004 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 5005 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5006 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5007 | // (TICCri G0, i32imm:$imm, 1) - 1799 |
| 5008 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5009 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5010 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 5011 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5012 | // (TICCri G0, i32imm:$imm, 1) - 1803 |
| 5013 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5014 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5015 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 5016 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5017 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5018 | // (TICCri IntRegs:$rs1, i32imm:$imm, 1) - 1808 |
| 5019 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5020 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5021 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 5022 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5023 | // (TICCri IntRegs:$rs1, i32imm:$imm, 1) - 1812 |
| 5024 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5025 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5026 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 5027 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5028 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5029 | // (TICCri G0, i32imm:$imm, 10) - 1817 |
| 5030 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5031 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5032 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 5033 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5034 | // (TICCri G0, i32imm:$imm, 10) - 1821 |
| 5035 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5036 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5037 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 5038 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5039 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5040 | // (TICCri IntRegs:$rs1, i32imm:$imm, 10) - 1826 |
| 5041 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5042 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5043 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 5044 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5045 | // (TICCri IntRegs:$rs1, i32imm:$imm, 10) - 1830 |
| 5046 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5047 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5048 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 5049 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5050 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5051 | // (TICCri G0, i32imm:$imm, 2) - 1835 |
| 5052 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5053 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5054 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 5055 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5056 | // (TICCri G0, i32imm:$imm, 2) - 1839 |
| 5057 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5058 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5059 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 5060 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5061 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5062 | // (TICCri IntRegs:$rs1, i32imm:$imm, 2) - 1844 |
| 5063 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5064 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5065 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 5066 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5067 | // (TICCri IntRegs:$rs1, i32imm:$imm, 2) - 1848 |
| 5068 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5069 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5070 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 5071 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5072 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5073 | // (TICCri G0, i32imm:$imm, 11) - 1853 |
| 5074 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5075 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5076 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 5077 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5078 | // (TICCri G0, i32imm:$imm, 11) - 1857 |
| 5079 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5080 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5081 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 5082 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5083 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5084 | // (TICCri IntRegs:$rs1, i32imm:$imm, 11) - 1862 |
| 5085 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5086 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5087 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 5088 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5089 | // (TICCri IntRegs:$rs1, i32imm:$imm, 11) - 1866 |
| 5090 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5091 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5092 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 5093 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5094 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5095 | // (TICCri G0, i32imm:$imm, 3) - 1871 |
| 5096 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5097 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5098 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 5099 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5100 | // (TICCri G0, i32imm:$imm, 3) - 1875 |
| 5101 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5102 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5103 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 5104 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5105 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5106 | // (TICCri IntRegs:$rs1, i32imm:$imm, 3) - 1880 |
| 5107 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5108 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5109 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 5110 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5111 | // (TICCri IntRegs:$rs1, i32imm:$imm, 3) - 1884 |
| 5112 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5113 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5114 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 5115 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5116 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5117 | // (TICCri G0, i32imm:$imm, 12) - 1889 |
| 5118 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5119 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5120 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 5121 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5122 | // (TICCri G0, i32imm:$imm, 12) - 1893 |
| 5123 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5124 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5125 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 5126 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5127 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5128 | // (TICCri IntRegs:$rs1, i32imm:$imm, 12) - 1898 |
| 5129 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5130 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5131 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 5132 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5133 | // (TICCri IntRegs:$rs1, i32imm:$imm, 12) - 1902 |
| 5134 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5135 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5136 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 5137 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5138 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5139 | // (TICCri G0, i32imm:$imm, 4) - 1907 |
| 5140 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5141 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5142 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 5143 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5144 | // (TICCri G0, i32imm:$imm, 4) - 1911 |
| 5145 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5146 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5147 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 5148 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5149 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5150 | // (TICCri IntRegs:$rs1, i32imm:$imm, 4) - 1916 |
| 5151 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5152 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5153 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 5154 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5155 | // (TICCri IntRegs:$rs1, i32imm:$imm, 4) - 1920 |
| 5156 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5157 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5158 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 5159 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5160 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5161 | // (TICCri G0, i32imm:$imm, 13) - 1925 |
| 5162 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5163 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5164 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 5165 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5166 | // (TICCri G0, i32imm:$imm, 13) - 1929 |
| 5167 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5168 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5169 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 5170 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5171 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5172 | // (TICCri IntRegs:$rs1, i32imm:$imm, 13) - 1934 |
| 5173 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5174 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5175 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 5176 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5177 | // (TICCri IntRegs:$rs1, i32imm:$imm, 13) - 1938 |
| 5178 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5179 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5180 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 5181 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5182 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5183 | // (TICCri G0, i32imm:$imm, 5) - 1943 |
| 5184 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5185 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5186 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 5187 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5188 | // (TICCri G0, i32imm:$imm, 5) - 1947 |
| 5189 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5190 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5191 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 5192 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5193 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5194 | // (TICCri IntRegs:$rs1, i32imm:$imm, 5) - 1952 |
| 5195 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5196 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5197 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 5198 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5199 | // (TICCri IntRegs:$rs1, i32imm:$imm, 5) - 1956 |
| 5200 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5201 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5202 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 5203 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5204 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5205 | // (TICCri G0, i32imm:$imm, 14) - 1961 |
| 5206 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5207 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5208 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 5209 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5210 | // (TICCri G0, i32imm:$imm, 14) - 1965 |
| 5211 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5212 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5213 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 5214 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5215 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5216 | // (TICCri IntRegs:$rs1, i32imm:$imm, 14) - 1970 |
| 5217 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5218 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5219 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 5220 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5221 | // (TICCri IntRegs:$rs1, i32imm:$imm, 14) - 1974 |
| 5222 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5223 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5224 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 5225 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5226 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5227 | // (TICCri G0, i32imm:$imm, 6) - 1979 |
| 5228 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5229 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5230 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 5231 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5232 | // (TICCri G0, i32imm:$imm, 6) - 1983 |
| 5233 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5234 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5235 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 5236 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5237 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5238 | // (TICCri IntRegs:$rs1, i32imm:$imm, 6) - 1988 |
| 5239 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5240 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5241 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 5242 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5243 | // (TICCri IntRegs:$rs1, i32imm:$imm, 6) - 1992 |
| 5244 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5245 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5246 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 5247 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5248 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5249 | // (TICCri G0, i32imm:$imm, 15) - 1997 |
| 5250 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5251 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5252 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 5253 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5254 | // (TICCri G0, i32imm:$imm, 15) - 2001 |
| 5255 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5256 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5257 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 5258 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5259 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5260 | // (TICCri IntRegs:$rs1, i32imm:$imm, 15) - 2006 |
| 5261 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5262 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5263 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 5264 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5265 | // (TICCri IntRegs:$rs1, i32imm:$imm, 15) - 2010 |
| 5266 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5267 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5268 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 5269 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5270 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5271 | // (TICCri G0, i32imm:$imm, 7) - 2015 |
| 5272 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5273 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5274 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 5275 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5276 | // (TICCri G0, i32imm:$imm, 7) - 2019 |
| 5277 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5278 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5279 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 5280 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5281 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5282 | // (TICCri IntRegs:$rs1, i32imm:$imm, 7) - 2024 |
| 5283 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5284 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5285 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 5286 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5287 | // (TICCri IntRegs:$rs1, i32imm:$imm, 7) - 2028 |
| 5288 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5289 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5290 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 5291 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5292 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5293 | // (TICCrr G0, IntRegs:$rs2, 8) - 2033 |
| 5294 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5295 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5296 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 5297 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5298 | // (TICCrr G0, IntRegs:$rs2, 8) - 2037 |
| 5299 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5300 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5301 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 5302 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5303 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5304 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2042 |
| 5305 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5306 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5307 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 5308 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5309 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2046 |
| 5310 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5311 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5312 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 5313 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5314 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5315 | // (TICCrr G0, IntRegs:$rs2, 0) - 2051 |
| 5316 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5317 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5318 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 5319 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5320 | // (TICCrr G0, IntRegs:$rs2, 0) - 2055 |
| 5321 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5322 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5323 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 5324 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5325 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5326 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2060 |
| 5327 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5328 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5329 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 5330 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5331 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2064 |
| 5332 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5333 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5334 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 5335 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5336 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5337 | // (TICCrr G0, IntRegs:$rs2, 9) - 2069 |
| 5338 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5339 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5340 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 5341 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5342 | // (TICCrr G0, IntRegs:$rs2, 9) - 2073 |
| 5343 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5344 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5345 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 5346 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5347 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5348 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2078 |
| 5349 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5350 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5351 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 5352 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5353 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2082 |
| 5354 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5355 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5356 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 5357 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5358 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5359 | // (TICCrr G0, IntRegs:$rs2, 1) - 2087 |
| 5360 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5361 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5362 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 5363 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5364 | // (TICCrr G0, IntRegs:$rs2, 1) - 2091 |
| 5365 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5366 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5367 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 5368 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5369 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5370 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2096 |
| 5371 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5372 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5373 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 5374 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5375 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2100 |
| 5376 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5377 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5378 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 5379 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5380 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5381 | // (TICCrr G0, IntRegs:$rs2, 10) - 2105 |
| 5382 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5383 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5384 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 5385 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5386 | // (TICCrr G0, IntRegs:$rs2, 10) - 2109 |
| 5387 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5388 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5389 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 5390 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5391 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5392 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2114 |
| 5393 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5394 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5395 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 5396 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5397 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2118 |
| 5398 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5399 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5400 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 5401 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5402 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5403 | // (TICCrr G0, IntRegs:$rs2, 2) - 2123 |
| 5404 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5405 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5406 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 5407 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5408 | // (TICCrr G0, IntRegs:$rs2, 2) - 2127 |
| 5409 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5410 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5411 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 5412 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5413 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5414 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2132 |
| 5415 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5416 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5417 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 5418 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5419 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2136 |
| 5420 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5421 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5422 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 5423 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5424 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5425 | // (TICCrr G0, IntRegs:$rs2, 11) - 2141 |
| 5426 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5427 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5428 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 5429 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5430 | // (TICCrr G0, IntRegs:$rs2, 11) - 2145 |
| 5431 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5432 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5433 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 5434 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5435 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5436 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2150 |
| 5437 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5438 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5439 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 5440 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5441 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2154 |
| 5442 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5443 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5444 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 5445 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5446 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5447 | // (TICCrr G0, IntRegs:$rs2, 3) - 2159 |
| 5448 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5449 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5450 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 5451 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5452 | // (TICCrr G0, IntRegs:$rs2, 3) - 2163 |
| 5453 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5454 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5455 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 5456 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5457 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5458 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2168 |
| 5459 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5460 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5461 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 5462 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5463 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2172 |
| 5464 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5465 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5466 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 5467 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5468 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5469 | // (TICCrr G0, IntRegs:$rs2, 12) - 2177 |
| 5470 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5471 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5472 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 5473 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5474 | // (TICCrr G0, IntRegs:$rs2, 12) - 2181 |
| 5475 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5476 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5477 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 5478 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5479 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5480 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2186 |
| 5481 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5482 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5483 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 5484 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5485 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2190 |
| 5486 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5487 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5488 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 5489 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5490 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5491 | // (TICCrr G0, IntRegs:$rs2, 4) - 2195 |
| 5492 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5493 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5494 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 5495 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5496 | // (TICCrr G0, IntRegs:$rs2, 4) - 2199 |
| 5497 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5498 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5499 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 5500 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5501 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5502 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2204 |
| 5503 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5504 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5505 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 5506 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5507 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2208 |
| 5508 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5509 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5510 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 5511 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5512 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5513 | // (TICCrr G0, IntRegs:$rs2, 13) - 2213 |
| 5514 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5515 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5516 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 5517 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5518 | // (TICCrr G0, IntRegs:$rs2, 13) - 2217 |
| 5519 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5520 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5521 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 5522 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5523 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5524 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2222 |
| 5525 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5526 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5527 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 5528 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5529 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2226 |
| 5530 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5531 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5532 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 5533 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5534 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5535 | // (TICCrr G0, IntRegs:$rs2, 5) - 2231 |
| 5536 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5537 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5538 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 5539 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5540 | // (TICCrr G0, IntRegs:$rs2, 5) - 2235 |
| 5541 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5542 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5543 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 5544 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5545 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5546 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 2240 |
| 5547 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5548 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5549 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 5550 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5551 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 2244 |
| 5552 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5553 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5554 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 5555 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5556 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5557 | // (TICCrr G0, IntRegs:$rs2, 14) - 2249 |
| 5558 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5559 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5560 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 5561 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5562 | // (TICCrr G0, IntRegs:$rs2, 14) - 2253 |
| 5563 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5564 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5565 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 5566 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5567 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5568 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 2258 |
| 5569 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5570 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5571 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 5572 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5573 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 2262 |
| 5574 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5575 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5576 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 5577 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5578 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5579 | // (TICCrr G0, IntRegs:$rs2, 6) - 2267 |
| 5580 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5581 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5582 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 5583 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5584 | // (TICCrr G0, IntRegs:$rs2, 6) - 2271 |
| 5585 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5586 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5587 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 5588 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5589 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5590 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 2276 |
| 5591 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5592 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5593 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 5594 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5595 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 2280 |
| 5596 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5597 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5598 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 5599 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5600 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5601 | // (TICCrr G0, IntRegs:$rs2, 15) - 2285 |
| 5602 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5603 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5604 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 5605 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5606 | // (TICCrr G0, IntRegs:$rs2, 15) - 2289 |
| 5607 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5608 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5609 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 5610 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5611 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5612 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 2294 |
| 5613 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5614 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5615 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 5616 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5617 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 2298 |
| 5618 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5619 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5620 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 5621 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5622 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5623 | // (TICCrr G0, IntRegs:$rs2, 7) - 2303 |
| 5624 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5625 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5626 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 5627 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5628 | // (TICCrr G0, IntRegs:$rs2, 7) - 2307 |
| 5629 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5630 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5631 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 5632 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5633 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5634 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 2312 |
| 5635 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5636 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5637 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 5638 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5639 | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 2316 |
| 5640 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5641 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5642 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 5643 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5644 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit}, |
| 5645 | // (TRAPri G0, i32imm:$imm, 8) - 2321 |
| 5646 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5647 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5648 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 5649 | // (TRAPri IntRegs:$rs1, i32imm:$imm, 8) - 2324 |
| 5650 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5651 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5652 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 5653 | // (TRAPri G0, i32imm:$imm, 0) - 2327 |
| 5654 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5655 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5656 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 5657 | // (TRAPri IntRegs:$rs1, i32imm:$imm, 0) - 2330 |
| 5658 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5659 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5660 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 5661 | // (TRAPri G0, i32imm:$imm, 9) - 2333 |
| 5662 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5663 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5664 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 5665 | // (TRAPri IntRegs:$rs1, i32imm:$imm, 9) - 2336 |
| 5666 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5667 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5668 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 5669 | // (TRAPri G0, i32imm:$imm, 1) - 2339 |
| 5670 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5671 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5672 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 5673 | // (TRAPri IntRegs:$rs1, i32imm:$imm, 1) - 2342 |
| 5674 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5675 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5676 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 5677 | // (TRAPri G0, i32imm:$imm, 10) - 2345 |
| 5678 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5679 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5680 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 5681 | // (TRAPri IntRegs:$rs1, i32imm:$imm, 10) - 2348 |
| 5682 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5683 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5684 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 5685 | // (TRAPri G0, i32imm:$imm, 2) - 2351 |
| 5686 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5687 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5688 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 5689 | // (TRAPri IntRegs:$rs1, i32imm:$imm, 2) - 2354 |
| 5690 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5691 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5692 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 5693 | // (TRAPri G0, i32imm:$imm, 11) - 2357 |
| 5694 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5695 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5696 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 5697 | // (TRAPri IntRegs:$rs1, i32imm:$imm, 11) - 2360 |
| 5698 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5699 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5700 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 5701 | // (TRAPri G0, i32imm:$imm, 3) - 2363 |
| 5702 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5703 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5704 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 5705 | // (TRAPri IntRegs:$rs1, i32imm:$imm, 3) - 2366 |
| 5706 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5707 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5708 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 5709 | // (TRAPri G0, i32imm:$imm, 12) - 2369 |
| 5710 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5711 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5712 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 5713 | // (TRAPri IntRegs:$rs1, i32imm:$imm, 12) - 2372 |
| 5714 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5715 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5716 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 5717 | // (TRAPri G0, i32imm:$imm, 4) - 2375 |
| 5718 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5719 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5720 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 5721 | // (TRAPri IntRegs:$rs1, i32imm:$imm, 4) - 2378 |
| 5722 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5723 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5724 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 5725 | // (TRAPri G0, i32imm:$imm, 13) - 2381 |
| 5726 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5727 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5728 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 5729 | // (TRAPri IntRegs:$rs1, i32imm:$imm, 13) - 2384 |
| 5730 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5731 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5732 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 5733 | // (TRAPri G0, i32imm:$imm, 5) - 2387 |
| 5734 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5735 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5736 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 5737 | // (TRAPri IntRegs:$rs1, i32imm:$imm, 5) - 2390 |
| 5738 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5739 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5740 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 5741 | // (TRAPri G0, i32imm:$imm, 14) - 2393 |
| 5742 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5743 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5744 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 5745 | // (TRAPri IntRegs:$rs1, i32imm:$imm, 14) - 2396 |
| 5746 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5747 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5748 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 5749 | // (TRAPri G0, i32imm:$imm, 6) - 2399 |
| 5750 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5751 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5752 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 5753 | // (TRAPri IntRegs:$rs1, i32imm:$imm, 6) - 2402 |
| 5754 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5755 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5756 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 5757 | // (TRAPri G0, i32imm:$imm, 15) - 2405 |
| 5758 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5759 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5760 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 5761 | // (TRAPri IntRegs:$rs1, i32imm:$imm, 15) - 2408 |
| 5762 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5763 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5764 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 5765 | // (TRAPri G0, i32imm:$imm, 7) - 2411 |
| 5766 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5767 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5768 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 5769 | // (TRAPri IntRegs:$rs1, i32imm:$imm, 7) - 2414 |
| 5770 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5771 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5772 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 5773 | // (TRAPrr G0, IntRegs:$rs1, 8) - 2417 |
| 5774 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5775 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5776 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 5777 | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2420 |
| 5778 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5779 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5780 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 5781 | // (TRAPrr G0, IntRegs:$rs1, 0) - 2423 |
| 5782 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5783 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5784 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 5785 | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2426 |
| 5786 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5787 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5788 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 5789 | // (TRAPrr G0, IntRegs:$rs1, 9) - 2429 |
| 5790 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5791 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5792 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 5793 | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2432 |
| 5794 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5795 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5796 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 5797 | // (TRAPrr G0, IntRegs:$rs1, 1) - 2435 |
| 5798 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5799 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5800 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 5801 | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2438 |
| 5802 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5803 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5804 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 5805 | // (TRAPrr G0, IntRegs:$rs1, 10) - 2441 |
| 5806 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5807 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5808 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 5809 | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2444 |
| 5810 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5811 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5812 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 5813 | // (TRAPrr G0, IntRegs:$rs1, 2) - 2447 |
| 5814 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5815 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5816 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 5817 | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2450 |
| 5818 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5819 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5820 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 5821 | // (TRAPrr G0, IntRegs:$rs1, 11) - 2453 |
| 5822 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5823 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5824 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 5825 | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2456 |
| 5826 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5827 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5828 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 5829 | // (TRAPrr G0, IntRegs:$rs1, 3) - 2459 |
| 5830 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5831 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5832 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 5833 | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2462 |
| 5834 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5835 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5836 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 5837 | // (TRAPrr G0, IntRegs:$rs1, 12) - 2465 |
| 5838 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5839 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5840 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 5841 | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2468 |
| 5842 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5843 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5844 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 5845 | // (TRAPrr G0, IntRegs:$rs1, 4) - 2471 |
| 5846 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5847 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5848 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 5849 | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2474 |
| 5850 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5851 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5852 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 5853 | // (TRAPrr G0, IntRegs:$rs1, 13) - 2477 |
| 5854 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5855 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5856 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 5857 | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2480 |
| 5858 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5859 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5860 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 5861 | // (TRAPrr G0, IntRegs:$rs1, 5) - 2483 |
| 5862 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5863 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5864 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 5865 | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 5) - 2486 |
| 5866 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5867 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5868 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 5869 | // (TRAPrr G0, IntRegs:$rs1, 14) - 2489 |
| 5870 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5871 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5872 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 5873 | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 14) - 2492 |
| 5874 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5875 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5876 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 5877 | // (TRAPrr G0, IntRegs:$rs1, 6) - 2495 |
| 5878 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5879 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5880 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 5881 | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 6) - 2498 |
| 5882 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5883 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5884 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 5885 | // (TRAPrr G0, IntRegs:$rs1, 15) - 2501 |
| 5886 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5887 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5888 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 5889 | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 15) - 2504 |
| 5890 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5891 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5892 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 5893 | // (TRAPrr G0, IntRegs:$rs1, 7) - 2507 |
| 5894 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5895 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5896 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 5897 | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 7) - 2510 |
| 5898 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5899 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5900 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 5901 | // (TXCCri G0, i32imm:$imm, 8) - 2513 |
| 5902 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5903 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5904 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 5905 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5906 | // (TXCCri G0, i32imm:$imm, 8) - 2517 |
| 5907 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5908 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5909 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 5910 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5911 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 5912 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 8) - 2522 |
| 5913 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5914 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5915 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 5916 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5917 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 8) - 2526 |
| 5918 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5919 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5920 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 5921 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5922 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 5923 | // (TXCCri G0, i32imm:$imm, 0) - 2531 |
| 5924 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5925 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5926 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 5927 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5928 | // (TXCCri G0, i32imm:$imm, 0) - 2535 |
| 5929 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5930 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5931 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 5932 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5933 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 5934 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 0) - 2540 |
| 5935 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5936 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5937 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 5938 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5939 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 0) - 2544 |
| 5940 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5941 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5942 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 5943 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5944 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 5945 | // (TXCCri G0, i32imm:$imm, 9) - 2549 |
| 5946 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5947 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5948 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 5949 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5950 | // (TXCCri G0, i32imm:$imm, 9) - 2553 |
| 5951 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5952 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5953 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 5954 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5955 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 5956 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 9) - 2558 |
| 5957 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5958 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5959 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 5960 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5961 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 9) - 2562 |
| 5962 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5963 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5964 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 5965 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5966 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 5967 | // (TXCCri G0, i32imm:$imm, 1) - 2567 |
| 5968 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5969 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5970 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 5971 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5972 | // (TXCCri G0, i32imm:$imm, 1) - 2571 |
| 5973 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5974 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5975 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 5976 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5977 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 5978 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 1) - 2576 |
| 5979 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5980 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5981 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 5982 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5983 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 1) - 2580 |
| 5984 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 5985 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5986 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 5987 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5988 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 5989 | // (TXCCri G0, i32imm:$imm, 10) - 2585 |
| 5990 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5991 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5992 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 5993 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5994 | // (TXCCri G0, i32imm:$imm, 10) - 2589 |
| 5995 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 5996 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 5997 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 5998 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 5999 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6000 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 10) - 2594 |
| 6001 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6002 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6003 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 6004 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6005 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 10) - 2598 |
| 6006 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6007 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6008 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 6009 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6010 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6011 | // (TXCCri G0, i32imm:$imm, 2) - 2603 |
| 6012 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6013 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6014 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 6015 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6016 | // (TXCCri G0, i32imm:$imm, 2) - 2607 |
| 6017 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6018 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6019 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 6020 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6021 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6022 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 2) - 2612 |
| 6023 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6024 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6025 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 6026 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6027 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 2) - 2616 |
| 6028 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6029 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6030 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 6031 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6032 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6033 | // (TXCCri G0, i32imm:$imm, 11) - 2621 |
| 6034 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6035 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6036 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 6037 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6038 | // (TXCCri G0, i32imm:$imm, 11) - 2625 |
| 6039 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6040 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6041 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 6042 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6043 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6044 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 11) - 2630 |
| 6045 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6046 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6047 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 6048 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6049 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 11) - 2634 |
| 6050 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6051 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6052 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 6053 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6054 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6055 | // (TXCCri G0, i32imm:$imm, 3) - 2639 |
| 6056 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6057 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6058 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 6059 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6060 | // (TXCCri G0, i32imm:$imm, 3) - 2643 |
| 6061 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6062 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6063 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 6064 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6065 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6066 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 3) - 2648 |
| 6067 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6068 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6069 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 6070 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6071 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 3) - 2652 |
| 6072 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6073 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6074 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 6075 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6076 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6077 | // (TXCCri G0, i32imm:$imm, 12) - 2657 |
| 6078 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6079 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6080 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 6081 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6082 | // (TXCCri G0, i32imm:$imm, 12) - 2661 |
| 6083 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6084 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6085 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 6086 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6087 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6088 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 12) - 2666 |
| 6089 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6090 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6091 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 6092 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6093 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 12) - 2670 |
| 6094 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6095 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6096 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 6097 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6098 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6099 | // (TXCCri G0, i32imm:$imm, 4) - 2675 |
| 6100 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6101 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6102 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 6103 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6104 | // (TXCCri G0, i32imm:$imm, 4) - 2679 |
| 6105 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6106 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6107 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 6108 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6109 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6110 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 4) - 2684 |
| 6111 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6112 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6113 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 6114 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6115 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 4) - 2688 |
| 6116 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6117 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6118 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 6119 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6120 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6121 | // (TXCCri G0, i32imm:$imm, 13) - 2693 |
| 6122 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6123 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6124 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 6125 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6126 | // (TXCCri G0, i32imm:$imm, 13) - 2697 |
| 6127 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6128 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6129 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 6130 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6131 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6132 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 13) - 2702 |
| 6133 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6134 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6135 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 6136 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6137 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 13) - 2706 |
| 6138 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6139 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6140 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 6141 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6142 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6143 | // (TXCCri G0, i32imm:$imm, 5) - 2711 |
| 6144 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6145 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6146 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 6147 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6148 | // (TXCCri G0, i32imm:$imm, 5) - 2715 |
| 6149 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6150 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6151 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 6152 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6153 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6154 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 5) - 2720 |
| 6155 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6156 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6157 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 6158 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6159 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 5) - 2724 |
| 6160 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6161 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6162 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 6163 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6164 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6165 | // (TXCCri G0, i32imm:$imm, 14) - 2729 |
| 6166 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6167 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6168 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 6169 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6170 | // (TXCCri G0, i32imm:$imm, 14) - 2733 |
| 6171 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6172 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6173 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 6174 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6175 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6176 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 14) - 2738 |
| 6177 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6178 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6179 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 6180 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6181 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 14) - 2742 |
| 6182 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6183 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6184 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 6185 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6186 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6187 | // (TXCCri G0, i32imm:$imm, 6) - 2747 |
| 6188 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6189 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6190 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 6191 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6192 | // (TXCCri G0, i32imm:$imm, 6) - 2751 |
| 6193 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6194 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6195 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 6196 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6197 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6198 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 6) - 2756 |
| 6199 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6200 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6201 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 6202 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6203 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 6) - 2760 |
| 6204 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6205 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6206 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 6207 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6208 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6209 | // (TXCCri G0, i32imm:$imm, 15) - 2765 |
| 6210 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6211 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6212 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 6213 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6214 | // (TXCCri G0, i32imm:$imm, 15) - 2769 |
| 6215 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6216 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6217 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 6218 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6219 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6220 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 15) - 2774 |
| 6221 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6222 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6223 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 6224 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6225 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 15) - 2778 |
| 6226 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6227 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6228 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 6229 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6230 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6231 | // (TXCCri G0, i32imm:$imm, 7) - 2783 |
| 6232 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6233 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6234 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 6235 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6236 | // (TXCCri G0, i32imm:$imm, 7) - 2787 |
| 6237 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6238 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6239 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 6240 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6241 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6242 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 7) - 2792 |
| 6243 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6244 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6245 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 6246 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6247 | // (TXCCri IntRegs:$rs1, i32imm:$imm, 7) - 2796 |
| 6248 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6249 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6250 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 6251 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6252 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6253 | // (TXCCrr G0, IntRegs:$rs2, 8) - 2801 |
| 6254 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6255 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6256 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 6257 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6258 | // (TXCCrr G0, IntRegs:$rs2, 8) - 2805 |
| 6259 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6260 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6261 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 6262 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6263 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6264 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2810 |
| 6265 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6266 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6267 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 6268 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6269 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2814 |
| 6270 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6271 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6272 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 6273 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6274 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6275 | // (TXCCrr G0, IntRegs:$rs2, 0) - 2819 |
| 6276 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6277 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6278 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 6279 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6280 | // (TXCCrr G0, IntRegs:$rs2, 0) - 2823 |
| 6281 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6282 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6283 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 6284 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6285 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6286 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2828 |
| 6287 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6288 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6289 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 6290 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6291 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2832 |
| 6292 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6293 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6294 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 6295 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6296 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6297 | // (TXCCrr G0, IntRegs:$rs2, 9) - 2837 |
| 6298 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6299 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6300 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 6301 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6302 | // (TXCCrr G0, IntRegs:$rs2, 9) - 2841 |
| 6303 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6304 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6305 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 6306 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6307 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6308 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2846 |
| 6309 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6310 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6311 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 6312 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6313 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2850 |
| 6314 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6315 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6316 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 6317 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6318 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6319 | // (TXCCrr G0, IntRegs:$rs2, 1) - 2855 |
| 6320 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6321 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6322 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 6323 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6324 | // (TXCCrr G0, IntRegs:$rs2, 1) - 2859 |
| 6325 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6326 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6327 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 6328 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6329 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6330 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2864 |
| 6331 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6332 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6333 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 6334 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6335 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2868 |
| 6336 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6337 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6338 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 6339 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6340 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6341 | // (TXCCrr G0, IntRegs:$rs2, 10) - 2873 |
| 6342 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6343 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6344 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 6345 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6346 | // (TXCCrr G0, IntRegs:$rs2, 10) - 2877 |
| 6347 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6348 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6349 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 6350 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6351 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6352 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2882 |
| 6353 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6354 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6355 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 6356 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6357 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2886 |
| 6358 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6359 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6360 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 6361 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6362 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6363 | // (TXCCrr G0, IntRegs:$rs2, 2) - 2891 |
| 6364 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6365 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6366 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 6367 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6368 | // (TXCCrr G0, IntRegs:$rs2, 2) - 2895 |
| 6369 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6370 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6371 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 6372 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6373 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6374 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2900 |
| 6375 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6376 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6377 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 6378 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6379 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2904 |
| 6380 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6381 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6382 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 6383 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6384 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6385 | // (TXCCrr G0, IntRegs:$rs2, 11) - 2909 |
| 6386 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6387 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6388 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 6389 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6390 | // (TXCCrr G0, IntRegs:$rs2, 11) - 2913 |
| 6391 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6392 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6393 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 6394 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6395 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6396 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2918 |
| 6397 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6398 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6399 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 6400 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6401 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2922 |
| 6402 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6403 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6404 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 6405 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6406 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6407 | // (TXCCrr G0, IntRegs:$rs2, 3) - 2927 |
| 6408 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6409 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6410 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 6411 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6412 | // (TXCCrr G0, IntRegs:$rs2, 3) - 2931 |
| 6413 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6414 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6415 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 6416 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6417 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6418 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2936 |
| 6419 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6420 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6421 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 6422 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6423 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2940 |
| 6424 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6425 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6426 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 6427 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6428 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6429 | // (TXCCrr G0, IntRegs:$rs2, 12) - 2945 |
| 6430 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6431 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6432 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 6433 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6434 | // (TXCCrr G0, IntRegs:$rs2, 12) - 2949 |
| 6435 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6436 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6437 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 6438 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6439 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6440 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2954 |
| 6441 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6442 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6443 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 6444 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6445 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2958 |
| 6446 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6447 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6448 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 6449 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6450 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6451 | // (TXCCrr G0, IntRegs:$rs2, 4) - 2963 |
| 6452 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6453 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6454 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 6455 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6456 | // (TXCCrr G0, IntRegs:$rs2, 4) - 2967 |
| 6457 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6458 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6459 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 6460 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6461 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6462 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2972 |
| 6463 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6464 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6465 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 6466 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6467 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2976 |
| 6468 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6469 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6470 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 6471 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6472 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6473 | // (TXCCrr G0, IntRegs:$rs2, 13) - 2981 |
| 6474 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6475 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6476 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 6477 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6478 | // (TXCCrr G0, IntRegs:$rs2, 13) - 2985 |
| 6479 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6480 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6481 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 6482 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6483 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6484 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2990 |
| 6485 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6486 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6487 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 6488 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6489 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2994 |
| 6490 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6491 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6492 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 6493 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6494 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6495 | // (TXCCrr G0, IntRegs:$rs2, 5) - 2999 |
| 6496 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6497 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6498 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 6499 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6500 | // (TXCCrr G0, IntRegs:$rs2, 5) - 3003 |
| 6501 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6502 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6503 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 6504 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6505 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6506 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 3008 |
| 6507 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6508 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6509 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 6510 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6511 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 3012 |
| 6512 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6513 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6514 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 6515 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6516 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6517 | // (TXCCrr G0, IntRegs:$rs2, 14) - 3017 |
| 6518 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6519 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6520 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 6521 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6522 | // (TXCCrr G0, IntRegs:$rs2, 14) - 3021 |
| 6523 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6524 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6525 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 6526 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6527 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6528 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 3026 |
| 6529 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6530 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6531 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 6532 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6533 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 3030 |
| 6534 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6535 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6536 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 6537 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6538 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6539 | // (TXCCrr G0, IntRegs:$rs2, 6) - 3035 |
| 6540 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6541 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6542 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 6543 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6544 | // (TXCCrr G0, IntRegs:$rs2, 6) - 3039 |
| 6545 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6546 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6547 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 6548 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6549 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6550 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 3044 |
| 6551 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6552 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6553 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 6554 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6555 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 3048 |
| 6556 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6557 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6558 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 6559 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6560 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6561 | // (TXCCrr G0, IntRegs:$rs2, 15) - 3053 |
| 6562 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6563 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6564 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 6565 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6566 | // (TXCCrr G0, IntRegs:$rs2, 15) - 3057 |
| 6567 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6568 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6569 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 6570 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6571 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6572 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 3062 |
| 6573 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6574 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6575 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 6576 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6577 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 3066 |
| 6578 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6579 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6580 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 6581 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6582 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6583 | // (TXCCrr G0, IntRegs:$rs2, 7) - 3071 |
| 6584 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6585 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6586 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 6587 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6588 | // (TXCCrr G0, IntRegs:$rs2, 7) - 3075 |
| 6589 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 6590 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6591 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 6592 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6593 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6594 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 3080 |
| 6595 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6596 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6597 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 6598 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6599 | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 3084 |
| 6600 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6601 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6602 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 6603 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6604 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit}, |
| 6605 | // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 3089 |
| 6606 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0}, |
| 6607 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6608 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6609 | // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 3092 |
| 6610 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0}, |
| 6611 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6612 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6613 | // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 3095 |
| 6614 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0}, |
| 6615 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6616 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6617 | // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2) - 3098 |
| 6618 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0}, |
| 6619 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6620 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6621 | // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 3101 |
| 6622 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0}, |
| 6623 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6624 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6625 | // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2) - 3104 |
| 6626 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0}, |
| 6627 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6628 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6629 | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8) - 3107 |
| 6630 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6631 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6632 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6633 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6634 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 6635 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6636 | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0) - 3113 |
| 6637 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6638 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6639 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6640 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6641 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 6642 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6643 | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7) - 3119 |
| 6644 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6645 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6646 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6647 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6648 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 6649 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6650 | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6) - 3125 |
| 6651 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6652 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6653 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6654 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6655 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 6656 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6657 | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5) - 3131 |
| 6658 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6659 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6660 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6661 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6662 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 6663 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6664 | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4) - 3137 |
| 6665 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6666 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6667 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6668 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6669 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 6670 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6671 | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3) - 3143 |
| 6672 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6673 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6674 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6675 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6676 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 6677 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6678 | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2) - 3149 |
| 6679 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6680 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6681 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6682 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6683 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 6684 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6685 | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1) - 3155 |
| 6686 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6687 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6688 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6689 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6690 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 6691 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6692 | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9) - 3161 |
| 6693 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6694 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6695 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6696 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6697 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 6698 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6699 | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10) - 3167 |
| 6700 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6701 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6702 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6703 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6704 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 6705 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6706 | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11) - 3173 |
| 6707 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6708 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6709 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6710 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6711 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 6712 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6713 | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12) - 3179 |
| 6714 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6715 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6716 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6717 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6718 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 6719 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6720 | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13) - 3185 |
| 6721 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6722 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6723 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6724 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6725 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 6726 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6727 | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14) - 3191 |
| 6728 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6729 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6730 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6731 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6732 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 6733 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6734 | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15) - 3197 |
| 6735 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6736 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6737 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID}, |
| 6738 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6739 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 6740 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6741 | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8) - 3203 |
| 6742 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6743 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6744 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6745 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6746 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 6747 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6748 | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0) - 3209 |
| 6749 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6750 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6751 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6752 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6753 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 6754 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6755 | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7) - 3215 |
| 6756 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6757 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6758 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6759 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6760 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 6761 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6762 | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6) - 3221 |
| 6763 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6764 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6765 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6766 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6767 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 6768 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6769 | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5) - 3227 |
| 6770 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6771 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6772 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6773 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6774 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 6775 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6776 | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4) - 3233 |
| 6777 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6778 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6779 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6780 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6781 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 6782 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6783 | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3) - 3239 |
| 6784 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6785 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6786 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6787 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6788 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 6789 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6790 | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2) - 3245 |
| 6791 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6792 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6793 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6794 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6795 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 6796 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6797 | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1) - 3251 |
| 6798 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6799 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6800 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6801 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6802 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 6803 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6804 | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9) - 3257 |
| 6805 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6806 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6807 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6808 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6809 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 6810 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6811 | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10) - 3263 |
| 6812 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6813 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6814 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6815 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6816 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 6817 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6818 | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11) - 3269 |
| 6819 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6820 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6821 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6822 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6823 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 6824 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6825 | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12) - 3275 |
| 6826 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6827 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6828 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6829 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6830 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 6831 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6832 | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13) - 3281 |
| 6833 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6834 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6835 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6836 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6837 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 6838 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6839 | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14) - 3287 |
| 6840 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6841 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6842 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6843 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6844 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 6845 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6846 | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15) - 3293 |
| 6847 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6848 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6849 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID}, |
| 6850 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6851 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 6852 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6853 | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8) - 3299 |
| 6854 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6855 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6856 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6857 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6858 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 6859 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6860 | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0) - 3305 |
| 6861 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6862 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6863 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6864 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6865 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 6866 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6867 | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7) - 3311 |
| 6868 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6869 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6870 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6871 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6872 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 6873 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6874 | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6) - 3317 |
| 6875 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6876 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6877 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6878 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6879 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 6880 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6881 | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5) - 3323 |
| 6882 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6883 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6884 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6885 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6886 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 6887 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6888 | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4) - 3329 |
| 6889 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6890 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6891 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6892 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6893 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 6894 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6895 | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3) - 3335 |
| 6896 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6897 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6898 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6899 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6900 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 6901 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6902 | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2) - 3341 |
| 6903 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6904 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6905 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6906 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6907 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 6908 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6909 | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1) - 3347 |
| 6910 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6911 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6912 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6913 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6914 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 6915 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6916 | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9) - 3353 |
| 6917 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6918 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6919 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6920 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6921 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 6922 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6923 | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10) - 3359 |
| 6924 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6925 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6926 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6927 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6928 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 6929 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6930 | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11) - 3365 |
| 6931 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6932 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6933 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6934 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6935 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 6936 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6937 | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12) - 3371 |
| 6938 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6939 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6940 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6941 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6942 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 6943 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6944 | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13) - 3377 |
| 6945 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6946 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6947 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6948 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6949 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 6950 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6951 | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14) - 3383 |
| 6952 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6953 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6954 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6955 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6956 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 6957 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6958 | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15) - 3389 |
| 6959 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6960 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6961 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID}, |
| 6962 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6963 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 6964 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6965 | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8) - 3395 |
| 6966 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6967 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6968 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6969 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6970 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 6971 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6972 | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0) - 3401 |
| 6973 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6974 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6975 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6976 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6977 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 6978 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6979 | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7) - 3407 |
| 6980 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6981 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6982 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6983 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6984 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 6985 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6986 | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6) - 3413 |
| 6987 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6988 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6989 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6990 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6991 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 6992 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 6993 | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5) - 3419 |
| 6994 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 6995 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 6996 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6997 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 6998 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 6999 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7000 | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4) - 3425 |
| 7001 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7002 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7003 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7004 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7005 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 7006 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7007 | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3) - 3431 |
| 7008 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7009 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7010 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7011 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7012 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 7013 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7014 | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2) - 3437 |
| 7015 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7016 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7017 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7018 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7019 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 7020 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7021 | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1) - 3443 |
| 7022 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7023 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7024 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7025 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7026 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 7027 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7028 | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9) - 3449 |
| 7029 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7030 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7031 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7032 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7033 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 7034 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7035 | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10) - 3455 |
| 7036 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7037 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7038 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7039 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7040 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 7041 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7042 | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11) - 3461 |
| 7043 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7044 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7045 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7046 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7047 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 7048 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7049 | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12) - 3467 |
| 7050 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7051 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7052 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7053 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7054 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 7055 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7056 | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13) - 3473 |
| 7057 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7058 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7059 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7060 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7061 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 7062 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7063 | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14) - 3479 |
| 7064 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7065 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7066 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7067 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7068 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 7069 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7070 | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15) - 3485 |
| 7071 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7072 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7073 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7074 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7075 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 7076 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7077 | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8) - 3491 |
| 7078 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7079 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7080 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7081 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7082 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)}, |
| 7083 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7084 | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0) - 3497 |
| 7085 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7086 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7087 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7088 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7089 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 7090 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7091 | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7) - 3503 |
| 7092 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7093 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7094 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7095 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7096 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 7097 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7098 | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6) - 3509 |
| 7099 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7100 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7101 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7102 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7103 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 7104 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7105 | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5) - 3515 |
| 7106 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7107 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7108 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7109 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7110 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 7111 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7112 | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4) - 3521 |
| 7113 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7114 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7115 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7116 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7117 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 7118 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7119 | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3) - 3527 |
| 7120 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7121 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7122 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7123 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7124 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 7125 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7126 | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2) - 3533 |
| 7127 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7128 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7129 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7130 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7131 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 7132 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7133 | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1) - 3539 |
| 7134 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7135 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7136 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7137 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7138 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 7139 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7140 | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9) - 3545 |
| 7141 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7142 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7143 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7144 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7145 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)}, |
| 7146 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7147 | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10) - 3551 |
| 7148 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7149 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7150 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7151 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7152 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)}, |
| 7153 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7154 | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11) - 3557 |
| 7155 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7156 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7157 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7158 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7159 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)}, |
| 7160 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7161 | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12) - 3563 |
| 7162 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7163 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7164 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7165 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7166 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 7167 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7168 | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13) - 3569 |
| 7169 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7170 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7171 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7172 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7173 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)}, |
| 7174 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7175 | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14) - 3575 |
| 7176 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7177 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7178 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7179 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7180 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)}, |
| 7181 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7182 | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15) - 3581 |
| 7183 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7184 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID}, |
| 7185 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7186 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 7187 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 7188 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9}, |
| 7189 | // (WRASRri ASR27, G0, simm13Op:$simm13) - 3587 |
| 7190 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::ASR27}, |
| 7191 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 7192 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 7193 | // (WRASRrr ASR27, G0, IntRegs:$rs2) - 3590 |
| 7194 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::ASR27}, |
| 7195 | {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0}, |
| 7196 | {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID}, |
| 7197 | {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011}, |
| 7198 | }; |
| 7199 | |
| 7200 | static const char AsmStrings[] = |
| 7201 | /* 0 */ "ba $\xFF\x01\x01\0" |
| 7202 | /* 8 */ "bn $\xFF\x01\x01\0" |
| 7203 | /* 16 */ "bne $\xFF\x01\x01\0" |
| 7204 | /* 25 */ "be $\xFF\x01\x01\0" |
| 7205 | /* 33 */ "bg $\xFF\x01\x01\0" |
| 7206 | /* 41 */ "ble $\xFF\x01\x01\0" |
| 7207 | /* 50 */ "bge $\xFF\x01\x01\0" |
| 7208 | /* 59 */ "bl $\xFF\x01\x01\0" |
| 7209 | /* 67 */ "bgu $\xFF\x01\x01\0" |
| 7210 | /* 76 */ "bleu $\xFF\x01\x01\0" |
| 7211 | /* 86 */ "bcc $\xFF\x01\x01\0" |
| 7212 | /* 95 */ "bcs $\xFF\x01\x01\0" |
| 7213 | /* 104 */ "bpos $\xFF\x01\x01\0" |
| 7214 | /* 114 */ "bneg $\xFF\x01\x01\0" |
| 7215 | /* 124 */ "bvc $\xFF\x01\x01\0" |
| 7216 | /* 133 */ "bvs $\xFF\x01\x01\0" |
| 7217 | /* 142 */ "ba,a $\xFF\x01\x01\0" |
| 7218 | /* 152 */ "bn,a $\xFF\x01\x01\0" |
| 7219 | /* 162 */ "bne,a $\xFF\x01\x01\0" |
| 7220 | /* 173 */ "be,a $\xFF\x01\x01\0" |
| 7221 | /* 183 */ "bg,a $\xFF\x01\x01\0" |
| 7222 | /* 193 */ "ble,a $\xFF\x01\x01\0" |
| 7223 | /* 204 */ "bge,a $\xFF\x01\x01\0" |
| 7224 | /* 215 */ "bl,a $\xFF\x01\x01\0" |
| 7225 | /* 225 */ "bgu,a $\xFF\x01\x01\0" |
| 7226 | /* 236 */ "bleu,a $\xFF\x01\x01\0" |
| 7227 | /* 248 */ "bcc,a $\xFF\x01\x01\0" |
| 7228 | /* 259 */ "bcs,a $\xFF\x01\x01\0" |
| 7229 | /* 270 */ "bpos,a $\xFF\x01\x01\0" |
| 7230 | /* 282 */ "bneg,a $\xFF\x01\x01\0" |
| 7231 | /* 294 */ "bvc,a $\xFF\x01\x01\0" |
| 7232 | /* 305 */ "bvs,a $\xFF\x01\x01\0" |
| 7233 | /* 316 */ "fba,a,pn $\x03, $\xFF\x01\x01\0" |
| 7234 | /* 334 */ "fbn,a,pn $\x03, $\xFF\x01\x01\0" |
| 7235 | /* 352 */ "fbu,a,pn $\x03, $\xFF\x01\x01\0" |
| 7236 | /* 370 */ "fbg,a,pn $\x03, $\xFF\x01\x01\0" |
| 7237 | /* 388 */ "fbug,a,pn $\x03, $\xFF\x01\x01\0" |
| 7238 | /* 407 */ "fbl,a,pn $\x03, $\xFF\x01\x01\0" |
| 7239 | /* 425 */ "fbul,a,pn $\x03, $\xFF\x01\x01\0" |
| 7240 | /* 444 */ "fblg,a,pn $\x03, $\xFF\x01\x01\0" |
| 7241 | /* 463 */ "fbne,a,pn $\x03, $\xFF\x01\x01\0" |
| 7242 | /* 482 */ "fbe,a,pn $\x03, $\xFF\x01\x01\0" |
| 7243 | /* 500 */ "fbue,a,pn $\x03, $\xFF\x01\x01\0" |
| 7244 | /* 519 */ "fbge,a,pn $\x03, $\xFF\x01\x01\0" |
| 7245 | /* 538 */ "fbuge,a,pn $\x03, $\xFF\x01\x01\0" |
| 7246 | /* 558 */ "fble,a,pn $\x03, $\xFF\x01\x01\0" |
| 7247 | /* 577 */ "fbule,a,pn $\x03, $\xFF\x01\x01\0" |
| 7248 | /* 597 */ "fbo,a,pn $\x03, $\xFF\x01\x01\0" |
| 7249 | /* 615 */ "fba,pn $\x03, $\xFF\x01\x01\0" |
| 7250 | /* 631 */ "fbn,pn $\x03, $\xFF\x01\x01\0" |
| 7251 | /* 647 */ "fbu,pn $\x03, $\xFF\x01\x01\0" |
| 7252 | /* 663 */ "fbg,pn $\x03, $\xFF\x01\x01\0" |
| 7253 | /* 679 */ "fbug,pn $\x03, $\xFF\x01\x01\0" |
| 7254 | /* 696 */ "fbl,pn $\x03, $\xFF\x01\x01\0" |
| 7255 | /* 712 */ "fbul,pn $\x03, $\xFF\x01\x01\0" |
| 7256 | /* 729 */ "fblg,pn $\x03, $\xFF\x01\x01\0" |
| 7257 | /* 746 */ "fbne,pn $\x03, $\xFF\x01\x01\0" |
| 7258 | /* 763 */ "fbe,pn $\x03, $\xFF\x01\x01\0" |
| 7259 | /* 779 */ "fbue,pn $\x03, $\xFF\x01\x01\0" |
| 7260 | /* 796 */ "fbge,pn $\x03, $\xFF\x01\x01\0" |
| 7261 | /* 813 */ "fbuge,pn $\x03, $\xFF\x01\x01\0" |
| 7262 | /* 831 */ "fble,pn $\x03, $\xFF\x01\x01\0" |
| 7263 | /* 848 */ "fbule,pn $\x03, $\xFF\x01\x01\0" |
| 7264 | /* 866 */ "fbo,pn $\x03, $\xFF\x01\x01\0" |
| 7265 | /* 882 */ "ba,a,pn %icc, $\xFF\x01\x01\0" |
| 7266 | /* 901 */ "ba,a,pn %ncc, $\xFF\x01\x01\0" |
| 7267 | /* 920 */ "bn,a,pn %icc, $\xFF\x01\x01\0" |
| 7268 | /* 939 */ "bn,a,pn %ncc, $\xFF\x01\x01\0" |
| 7269 | /* 958 */ "bne,a,pn %icc, $\xFF\x01\x01\0" |
| 7270 | /* 978 */ "bne,a,pn %ncc, $\xFF\x01\x01\0" |
| 7271 | /* 998 */ "be,a,pn %icc, $\xFF\x01\x01\0" |
| 7272 | /* 1017 */ "be,a,pn %ncc, $\xFF\x01\x01\0" |
| 7273 | /* 1036 */ "bg,a,pn %icc, $\xFF\x01\x01\0" |
| 7274 | /* 1055 */ "bg,a,pn %ncc, $\xFF\x01\x01\0" |
| 7275 | /* 1074 */ "ble,a,pn %icc, $\xFF\x01\x01\0" |
| 7276 | /* 1094 */ "ble,a,pn %ncc, $\xFF\x01\x01\0" |
| 7277 | /* 1114 */ "bge,a,pn %icc, $\xFF\x01\x01\0" |
| 7278 | /* 1134 */ "bge,a,pn %ncc, $\xFF\x01\x01\0" |
| 7279 | /* 1154 */ "bl,a,pn %icc, $\xFF\x01\x01\0" |
| 7280 | /* 1173 */ "bl,a,pn %ncc, $\xFF\x01\x01\0" |
| 7281 | /* 1192 */ "bgu,a,pn %icc, $\xFF\x01\x01\0" |
| 7282 | /* 1212 */ "bgu,a,pn %ncc, $\xFF\x01\x01\0" |
| 7283 | /* 1232 */ "bleu,a,pn %icc, $\xFF\x01\x01\0" |
| 7284 | /* 1253 */ "bleu,a,pn %ncc, $\xFF\x01\x01\0" |
| 7285 | /* 1274 */ "bcc,a,pn %icc, $\xFF\x01\x01\0" |
| 7286 | /* 1294 */ "bcc,a,pn %ncc, $\xFF\x01\x01\0" |
| 7287 | /* 1314 */ "bcs,a,pn %icc, $\xFF\x01\x01\0" |
| 7288 | /* 1334 */ "bcs,a,pn %ncc, $\xFF\x01\x01\0" |
| 7289 | /* 1354 */ "bpos,a,pn %icc, $\xFF\x01\x01\0" |
| 7290 | /* 1375 */ "bpos,a,pn %ncc, $\xFF\x01\x01\0" |
| 7291 | /* 1396 */ "bneg,a,pn %icc, $\xFF\x01\x01\0" |
| 7292 | /* 1417 */ "bneg,a,pn %ncc, $\xFF\x01\x01\0" |
| 7293 | /* 1438 */ "bvc,a,pn %icc, $\xFF\x01\x01\0" |
| 7294 | /* 1458 */ "bvc,a,pn %ncc, $\xFF\x01\x01\0" |
| 7295 | /* 1478 */ "bvs,a,pn %icc, $\xFF\x01\x01\0" |
| 7296 | /* 1498 */ "bvs,a,pn %ncc, $\xFF\x01\x01\0" |
| 7297 | /* 1518 */ "ba,pn %icc, $\xFF\x01\x01\0" |
| 7298 | /* 1535 */ "ba,pn %ncc, $\xFF\x01\x01\0" |
| 7299 | /* 1552 */ "bn,pn %icc, $\xFF\x01\x01\0" |
| 7300 | /* 1569 */ "bn,pn %ncc, $\xFF\x01\x01\0" |
| 7301 | /* 1586 */ "bne,pn %icc, $\xFF\x01\x01\0" |
| 7302 | /* 1604 */ "bne,pn %ncc, $\xFF\x01\x01\0" |
| 7303 | /* 1622 */ "be,pn %icc, $\xFF\x01\x01\0" |
| 7304 | /* 1639 */ "be,pn %ncc, $\xFF\x01\x01\0" |
| 7305 | /* 1656 */ "bg,pn %icc, $\xFF\x01\x01\0" |
| 7306 | /* 1673 */ "bg,pn %ncc, $\xFF\x01\x01\0" |
| 7307 | /* 1690 */ "ble,pn %icc, $\xFF\x01\x01\0" |
| 7308 | /* 1708 */ "ble,pn %ncc, $\xFF\x01\x01\0" |
| 7309 | /* 1726 */ "bge,pn %icc, $\xFF\x01\x01\0" |
| 7310 | /* 1744 */ "bge,pn %ncc, $\xFF\x01\x01\0" |
| 7311 | /* 1762 */ "bl,pn %icc, $\xFF\x01\x01\0" |
| 7312 | /* 1779 */ "bl,pn %ncc, $\xFF\x01\x01\0" |
| 7313 | /* 1796 */ "bgu,pn %icc, $\xFF\x01\x01\0" |
| 7314 | /* 1814 */ "bgu,pn %ncc, $\xFF\x01\x01\0" |
| 7315 | /* 1832 */ "bleu,pn %icc, $\xFF\x01\x01\0" |
| 7316 | /* 1851 */ "bleu,pn %ncc, $\xFF\x01\x01\0" |
| 7317 | /* 1870 */ "bcc,pn %icc, $\xFF\x01\x01\0" |
| 7318 | /* 1888 */ "bcc,pn %ncc, $\xFF\x01\x01\0" |
| 7319 | /* 1906 */ "bcs,pn %icc, $\xFF\x01\x01\0" |
| 7320 | /* 1924 */ "bcs,pn %ncc, $\xFF\x01\x01\0" |
| 7321 | /* 1942 */ "bpos,pn %icc, $\xFF\x01\x01\0" |
| 7322 | /* 1961 */ "bpos,pn %ncc, $\xFF\x01\x01\0" |
| 7323 | /* 1980 */ "bneg,pn %icc, $\xFF\x01\x01\0" |
| 7324 | /* 1999 */ "bneg,pn %ncc, $\xFF\x01\x01\0" |
| 7325 | /* 2018 */ "bvc,pn %icc, $\xFF\x01\x01\0" |
| 7326 | /* 2036 */ "bvc,pn %ncc, $\xFF\x01\x01\0" |
| 7327 | /* 2054 */ "bvs,pn %icc, $\xFF\x01\x01\0" |
| 7328 | /* 2072 */ "bvs,pn %ncc, $\xFF\x01\x01\0" |
| 7329 | /* 2090 */ "brlez,a,pn $\x03, $\xFF\x01\x01\0" |
| 7330 | /* 2110 */ "brlz,a,pn $\x03, $\xFF\x01\x01\0" |
| 7331 | /* 2129 */ "brgz,a,pn $\x03, $\xFF\x01\x01\0" |
| 7332 | /* 2148 */ "brgez,a,pn $\x03, $\xFF\x01\x01\0" |
| 7333 | /* 2168 */ "brlez,pn $\x03, $\xFF\x01\x01\0" |
| 7334 | /* 2186 */ "brlz,pn $\x03, $\xFF\x01\x01\0" |
| 7335 | /* 2203 */ "brgz,pn $\x03, $\xFF\x01\x01\0" |
| 7336 | /* 2220 */ "brgez,pn $\x03, $\xFF\x01\x01\0" |
| 7337 | /* 2238 */ "cas [$\x02], $\x03, $\x01\0" |
| 7338 | /* 2255 */ "casl [$\x02], $\x03, $\x01\0" |
| 7339 | /* 2273 */ "casx [$\x02], $\x03, $\x01\0" |
| 7340 | /* 2291 */ "casxl [$\x02], $\x03, $\x01\0" |
| 7341 | /* 2310 */ "cwbne $\x03, $\x04, $\xFF\x01\x01\0" |
| 7342 | /* 2329 */ "cwbe $\x03, $\x04, $\xFF\x01\x01\0" |
| 7343 | /* 2347 */ "cwbg $\x03, $\x04, $\xFF\x01\x01\0" |
| 7344 | /* 2365 */ "cwble $\x03, $\x04, $\xFF\x01\x01\0" |
| 7345 | /* 2384 */ "cwbge $\x03, $\x04, $\xFF\x01\x01\0" |
| 7346 | /* 2403 */ "cwbl $\x03, $\x04, $\xFF\x01\x01\0" |
| 7347 | /* 2421 */ "cwbgu $\x03, $\x04, $\xFF\x01\x01\0" |
| 7348 | /* 2440 */ "cwbleu $\x03, $\x04, $\xFF\x01\x01\0" |
| 7349 | /* 2460 */ "cwbcc $\x03, $\x04, $\xFF\x01\x01\0" |
| 7350 | /* 2479 */ "cwbcs $\x03, $\x04, $\xFF\x01\x01\0" |
| 7351 | /* 2498 */ "cwbpos $\x03, $\x04, $\xFF\x01\x01\0" |
| 7352 | /* 2518 */ "cwbneg $\x03, $\x04, $\xFF\x01\x01\0" |
| 7353 | /* 2538 */ "cwbvc $\x03, $\x04, $\xFF\x01\x01\0" |
| 7354 | /* 2557 */ "cwbvs $\x03, $\x04, $\xFF\x01\x01\0" |
| 7355 | /* 2576 */ "cxbne $\x03, $\x04, $\xFF\x01\x01\0" |
| 7356 | /* 2595 */ "cxbe $\x03, $\x04, $\xFF\x01\x01\0" |
| 7357 | /* 2613 */ "cxbg $\x03, $\x04, $\xFF\x01\x01\0" |
| 7358 | /* 2631 */ "cxble $\x03, $\x04, $\xFF\x01\x01\0" |
| 7359 | /* 2650 */ "cxbge $\x03, $\x04, $\xFF\x01\x01\0" |
| 7360 | /* 2669 */ "cxbl $\x03, $\x04, $\xFF\x01\x01\0" |
| 7361 | /* 2687 */ "cxbgu $\x03, $\x04, $\xFF\x01\x01\0" |
| 7362 | /* 2706 */ "cxbleu $\x03, $\x04, $\xFF\x01\x01\0" |
| 7363 | /* 2726 */ "cxbcc $\x03, $\x04, $\xFF\x01\x01\0" |
| 7364 | /* 2745 */ "cxbcs $\x03, $\x04, $\xFF\x01\x01\0" |
| 7365 | /* 2764 */ "cxbpos $\x03, $\x04, $\xFF\x01\x01\0" |
| 7366 | /* 2784 */ "cxbneg $\x03, $\x04, $\xFF\x01\x01\0" |
| 7367 | /* 2804 */ "cxbvc $\x03, $\x04, $\xFF\x01\x01\0" |
| 7368 | /* 2823 */ "cxbvs $\x03, $\x04, $\xFF\x01\x01\0" |
| 7369 | /* 2842 */ "fmovda %icc, $\x02, $\x01\0" |
| 7370 | /* 2862 */ "fmovda %ncc, $\x02, $\x01\0" |
| 7371 | /* 2882 */ "fmovdn %icc, $\x02, $\x01\0" |
| 7372 | /* 2902 */ "fmovdn %ncc, $\x02, $\x01\0" |
| 7373 | /* 2922 */ "fmovdne %icc, $\x02, $\x01\0" |
| 7374 | /* 2943 */ "fmovdne %ncc, $\x02, $\x01\0" |
| 7375 | /* 2964 */ "fmovde %icc, $\x02, $\x01\0" |
| 7376 | /* 2984 */ "fmovde %ncc, $\x02, $\x01\0" |
| 7377 | /* 3004 */ "fmovdg %icc, $\x02, $\x01\0" |
| 7378 | /* 3024 */ "fmovdg %ncc, $\x02, $\x01\0" |
| 7379 | /* 3044 */ "fmovdle %icc, $\x02, $\x01\0" |
| 7380 | /* 3065 */ "fmovdle %ncc, $\x02, $\x01\0" |
| 7381 | /* 3086 */ "fmovdge %icc, $\x02, $\x01\0" |
| 7382 | /* 3107 */ "fmovdge %ncc, $\x02, $\x01\0" |
| 7383 | /* 3128 */ "fmovdl %icc, $\x02, $\x01\0" |
| 7384 | /* 3148 */ "fmovdl %ncc, $\x02, $\x01\0" |
| 7385 | /* 3168 */ "fmovdgu %icc, $\x02, $\x01\0" |
| 7386 | /* 3189 */ "fmovdgu %ncc, $\x02, $\x01\0" |
| 7387 | /* 3210 */ "fmovdleu %icc, $\x02, $\x01\0" |
| 7388 | /* 3232 */ "fmovdleu %ncc, $\x02, $\x01\0" |
| 7389 | /* 3254 */ "fmovdcc %icc, $\x02, $\x01\0" |
| 7390 | /* 3275 */ "fmovdcc %ncc, $\x02, $\x01\0" |
| 7391 | /* 3296 */ "fmovdcs %icc, $\x02, $\x01\0" |
| 7392 | /* 3317 */ "fmovdcs %ncc, $\x02, $\x01\0" |
| 7393 | /* 3338 */ "fmovdpos %icc, $\x02, $\x01\0" |
| 7394 | /* 3360 */ "fmovdpos %ncc, $\x02, $\x01\0" |
| 7395 | /* 3382 */ "fmovdneg %icc, $\x02, $\x01\0" |
| 7396 | /* 3404 */ "fmovdneg %ncc, $\x02, $\x01\0" |
| 7397 | /* 3426 */ "fmovdvc %icc, $\x02, $\x01\0" |
| 7398 | /* 3447 */ "fmovdvc %ncc, $\x02, $\x01\0" |
| 7399 | /* 3468 */ "fmovdvs %icc, $\x02, $\x01\0" |
| 7400 | /* 3489 */ "fmovdvs %ncc, $\x02, $\x01\0" |
| 7401 | /* 3510 */ "fmovqa %icc, $\x02, $\x01\0" |
| 7402 | /* 3530 */ "fmovqa %ncc, $\x02, $\x01\0" |
| 7403 | /* 3550 */ "fmovqn %icc, $\x02, $\x01\0" |
| 7404 | /* 3570 */ "fmovqn %ncc, $\x02, $\x01\0" |
| 7405 | /* 3590 */ "fmovqne %icc, $\x02, $\x01\0" |
| 7406 | /* 3611 */ "fmovqne %ncc, $\x02, $\x01\0" |
| 7407 | /* 3632 */ "fmovqe %icc, $\x02, $\x01\0" |
| 7408 | /* 3652 */ "fmovqe %ncc, $\x02, $\x01\0" |
| 7409 | /* 3672 */ "fmovqg %icc, $\x02, $\x01\0" |
| 7410 | /* 3692 */ "fmovqg %ncc, $\x02, $\x01\0" |
| 7411 | /* 3712 */ "fmovqle %icc, $\x02, $\x01\0" |
| 7412 | /* 3733 */ "fmovqle %ncc, $\x02, $\x01\0" |
| 7413 | /* 3754 */ "fmovqge %icc, $\x02, $\x01\0" |
| 7414 | /* 3775 */ "fmovqge %ncc, $\x02, $\x01\0" |
| 7415 | /* 3796 */ "fmovql %icc, $\x02, $\x01\0" |
| 7416 | /* 3816 */ "fmovql %ncc, $\x02, $\x01\0" |
| 7417 | /* 3836 */ "fmovqgu %icc, $\x02, $\x01\0" |
| 7418 | /* 3857 */ "fmovqgu %ncc, $\x02, $\x01\0" |
| 7419 | /* 3878 */ "fmovqleu %icc, $\x02, $\x01\0" |
| 7420 | /* 3900 */ "fmovqleu %ncc, $\x02, $\x01\0" |
| 7421 | /* 3922 */ "fmovqcc %icc, $\x02, $\x01\0" |
| 7422 | /* 3943 */ "fmovqcc %ncc, $\x02, $\x01\0" |
| 7423 | /* 3964 */ "fmovqcs %icc, $\x02, $\x01\0" |
| 7424 | /* 3985 */ "fmovqcs %ncc, $\x02, $\x01\0" |
| 7425 | /* 4006 */ "fmovqpos %icc, $\x02, $\x01\0" |
| 7426 | /* 4028 */ "fmovqpos %ncc, $\x02, $\x01\0" |
| 7427 | /* 4050 */ "fmovqneg %icc, $\x02, $\x01\0" |
| 7428 | /* 4072 */ "fmovqneg %ncc, $\x02, $\x01\0" |
| 7429 | /* 4094 */ "fmovqvc %icc, $\x02, $\x01\0" |
| 7430 | /* 4115 */ "fmovqvc %ncc, $\x02, $\x01\0" |
| 7431 | /* 4136 */ "fmovqvs %icc, $\x02, $\x01\0" |
| 7432 | /* 4157 */ "fmovqvs %ncc, $\x02, $\x01\0" |
| 7433 | /* 4178 */ "fmovrdlez $\x02, $\x03, $\x01\0" |
| 7434 | /* 4199 */ "fmovrdlz $\x02, $\x03, $\x01\0" |
| 7435 | /* 4219 */ "fmovrdgz $\x02, $\x03, $\x01\0" |
| 7436 | /* 4239 */ "fmovrdgez $\x02, $\x03, $\x01\0" |
| 7437 | /* 4260 */ "fmovrqlez $\x02, $\x03, $\x01\0" |
| 7438 | /* 4281 */ "fmovrqlz $\x02, $\x03, $\x01\0" |
| 7439 | /* 4301 */ "fmovrqgz $\x02, $\x03, $\x01\0" |
| 7440 | /* 4321 */ "fmovrqgez $\x02, $\x03, $\x01\0" |
| 7441 | /* 4342 */ "fmovrslez $\x02, $\x03, $\x01\0" |
| 7442 | /* 4363 */ "fmovrslz $\x02, $\x03, $\x01\0" |
| 7443 | /* 4383 */ "fmovrsgz $\x02, $\x03, $\x01\0" |
| 7444 | /* 4403 */ "fmovrsgez $\x02, $\x03, $\x01\0" |
| 7445 | /* 4424 */ "fmovsa %icc, $\x02, $\x01\0" |
| 7446 | /* 4444 */ "fmovsa %ncc, $\x02, $\x01\0" |
| 7447 | /* 4464 */ "fmovsn %icc, $\x02, $\x01\0" |
| 7448 | /* 4484 */ "fmovsn %ncc, $\x02, $\x01\0" |
| 7449 | /* 4504 */ "fmovsne %icc, $\x02, $\x01\0" |
| 7450 | /* 4525 */ "fmovsne %ncc, $\x02, $\x01\0" |
| 7451 | /* 4546 */ "fmovse %icc, $\x02, $\x01\0" |
| 7452 | /* 4566 */ "fmovse %ncc, $\x02, $\x01\0" |
| 7453 | /* 4586 */ "fmovsg %icc, $\x02, $\x01\0" |
| 7454 | /* 4606 */ "fmovsg %ncc, $\x02, $\x01\0" |
| 7455 | /* 4626 */ "fmovsle %icc, $\x02, $\x01\0" |
| 7456 | /* 4647 */ "fmovsle %ncc, $\x02, $\x01\0" |
| 7457 | /* 4668 */ "fmovsge %icc, $\x02, $\x01\0" |
| 7458 | /* 4689 */ "fmovsge %ncc, $\x02, $\x01\0" |
| 7459 | /* 4710 */ "fmovsl %icc, $\x02, $\x01\0" |
| 7460 | /* 4730 */ "fmovsl %ncc, $\x02, $\x01\0" |
| 7461 | /* 4750 */ "fmovsgu %icc, $\x02, $\x01\0" |
| 7462 | /* 4771 */ "fmovsgu %ncc, $\x02, $\x01\0" |
| 7463 | /* 4792 */ "fmovsleu %icc, $\x02, $\x01\0" |
| 7464 | /* 4814 */ "fmovsleu %ncc, $\x02, $\x01\0" |
| 7465 | /* 4836 */ "fmovscc %icc, $\x02, $\x01\0" |
| 7466 | /* 4857 */ "fmovscc %ncc, $\x02, $\x01\0" |
| 7467 | /* 4878 */ "fmovscs %icc, $\x02, $\x01\0" |
| 7468 | /* 4899 */ "fmovscs %ncc, $\x02, $\x01\0" |
| 7469 | /* 4920 */ "fmovspos %icc, $\x02, $\x01\0" |
| 7470 | /* 4942 */ "fmovspos %ncc, $\x02, $\x01\0" |
| 7471 | /* 4964 */ "fmovsneg %icc, $\x02, $\x01\0" |
| 7472 | /* 4986 */ "fmovsneg %ncc, $\x02, $\x01\0" |
| 7473 | /* 5008 */ "fmovsvc %icc, $\x02, $\x01\0" |
| 7474 | /* 5029 */ "fmovsvc %ncc, $\x02, $\x01\0" |
| 7475 | /* 5050 */ "fmovsvs %icc, $\x02, $\x01\0" |
| 7476 | /* 5071 */ "fmovsvs %ncc, $\x02, $\x01\0" |
| 7477 | /* 5092 */ "mova %icc, $\x02, $\x01\0" |
| 7478 | /* 5110 */ "mova %ncc, $\x02, $\x01\0" |
| 7479 | /* 5128 */ "movn %icc, $\x02, $\x01\0" |
| 7480 | /* 5146 */ "movn %ncc, $\x02, $\x01\0" |
| 7481 | /* 5164 */ "movne %icc, $\x02, $\x01\0" |
| 7482 | /* 5183 */ "movne %ncc, $\x02, $\x01\0" |
| 7483 | /* 5202 */ "move %icc, $\x02, $\x01\0" |
| 7484 | /* 5220 */ "move %ncc, $\x02, $\x01\0" |
| 7485 | /* 5238 */ "movg %icc, $\x02, $\x01\0" |
| 7486 | /* 5256 */ "movg %ncc, $\x02, $\x01\0" |
| 7487 | /* 5274 */ "movle %icc, $\x02, $\x01\0" |
| 7488 | /* 5293 */ "movle %ncc, $\x02, $\x01\0" |
| 7489 | /* 5312 */ "movge %icc, $\x02, $\x01\0" |
| 7490 | /* 5331 */ "movge %ncc, $\x02, $\x01\0" |
| 7491 | /* 5350 */ "movl %icc, $\x02, $\x01\0" |
| 7492 | /* 5368 */ "movl %ncc, $\x02, $\x01\0" |
| 7493 | /* 5386 */ "movgu %icc, $\x02, $\x01\0" |
| 7494 | /* 5405 */ "movgu %ncc, $\x02, $\x01\0" |
| 7495 | /* 5424 */ "movleu %icc, $\x02, $\x01\0" |
| 7496 | /* 5444 */ "movleu %ncc, $\x02, $\x01\0" |
| 7497 | /* 5464 */ "movcc %icc, $\x02, $\x01\0" |
| 7498 | /* 5483 */ "movcc %ncc, $\x02, $\x01\0" |
| 7499 | /* 5502 */ "movcs %icc, $\x02, $\x01\0" |
| 7500 | /* 5521 */ "movcs %ncc, $\x02, $\x01\0" |
| 7501 | /* 5540 */ "movpos %icc, $\x02, $\x01\0" |
| 7502 | /* 5560 */ "movpos %ncc, $\x02, $\x01\0" |
| 7503 | /* 5580 */ "movneg %icc, $\x02, $\x01\0" |
| 7504 | /* 5600 */ "movneg %ncc, $\x02, $\x01\0" |
| 7505 | /* 5620 */ "movvc %icc, $\x02, $\x01\0" |
| 7506 | /* 5639 */ "movvc %ncc, $\x02, $\x01\0" |
| 7507 | /* 5658 */ "movvs %icc, $\x02, $\x01\0" |
| 7508 | /* 5677 */ "movvs %ncc, $\x02, $\x01\0" |
| 7509 | /* 5696 */ "movrlez $\x02, $\x03, $\x01\0" |
| 7510 | /* 5715 */ "movrlz $\x02, $\x03, $\x01\0" |
| 7511 | /* 5733 */ "movrgz $\x02, $\x03, $\x01\0" |
| 7512 | /* 5751 */ "movrgez $\x02, $\x03, $\x01\0" |
| 7513 | /* 5770 */ "tst $\x02\0" |
| 7514 | /* 5777 */ "mov $\x03, $\x01\0" |
| 7515 | /* 5788 */ "restore\0" |
| 7516 | /* 5796 */ "ret\0" |
| 7517 | /* 5800 */ "retl\0" |
| 7518 | /* 5805 */ "save\0" |
| 7519 | /* 5810 */ "cmp $\x02, $\x03\0" |
| 7520 | /* 5821 */ "ta %icc, $\x02\0" |
| 7521 | /* 5833 */ "ta %ncc, $\x02\0" |
| 7522 | /* 5845 */ "ta %icc, $\x01 + $\x02\0" |
| 7523 | /* 5862 */ "ta %ncc, $\x01 + $\x02\0" |
| 7524 | /* 5879 */ "tn %icc, $\x02\0" |
| 7525 | /* 5891 */ "tn %ncc, $\x02\0" |
| 7526 | /* 5903 */ "tn %icc, $\x01 + $\x02\0" |
| 7527 | /* 5920 */ "tn %ncc, $\x01 + $\x02\0" |
| 7528 | /* 5937 */ "tne %icc, $\x02\0" |
| 7529 | /* 5950 */ "tne %ncc, $\x02\0" |
| 7530 | /* 5963 */ "tne %icc, $\x01 + $\x02\0" |
| 7531 | /* 5981 */ "tne %ncc, $\x01 + $\x02\0" |
| 7532 | /* 5999 */ "te %icc, $\x02\0" |
| 7533 | /* 6011 */ "te %ncc, $\x02\0" |
| 7534 | /* 6023 */ "te %icc, $\x01 + $\x02\0" |
| 7535 | /* 6040 */ "te %ncc, $\x01 + $\x02\0" |
| 7536 | /* 6057 */ "tg %icc, $\x02\0" |
| 7537 | /* 6069 */ "tg %ncc, $\x02\0" |
| 7538 | /* 6081 */ "tg %icc, $\x01 + $\x02\0" |
| 7539 | /* 6098 */ "tg %ncc, $\x01 + $\x02\0" |
| 7540 | /* 6115 */ "tle %icc, $\x02\0" |
| 7541 | /* 6128 */ "tle %ncc, $\x02\0" |
| 7542 | /* 6141 */ "tle %icc, $\x01 + $\x02\0" |
| 7543 | /* 6159 */ "tle %ncc, $\x01 + $\x02\0" |
| 7544 | /* 6177 */ "tge %icc, $\x02\0" |
| 7545 | /* 6190 */ "tge %ncc, $\x02\0" |
| 7546 | /* 6203 */ "tge %icc, $\x01 + $\x02\0" |
| 7547 | /* 6221 */ "tge %ncc, $\x01 + $\x02\0" |
| 7548 | /* 6239 */ "tl %icc, $\x02\0" |
| 7549 | /* 6251 */ "tl %ncc, $\x02\0" |
| 7550 | /* 6263 */ "tl %icc, $\x01 + $\x02\0" |
| 7551 | /* 6280 */ "tl %ncc, $\x01 + $\x02\0" |
| 7552 | /* 6297 */ "tgu %icc, $\x02\0" |
| 7553 | /* 6310 */ "tgu %ncc, $\x02\0" |
| 7554 | /* 6323 */ "tgu %icc, $\x01 + $\x02\0" |
| 7555 | /* 6341 */ "tgu %ncc, $\x01 + $\x02\0" |
| 7556 | /* 6359 */ "tleu %icc, $\x02\0" |
| 7557 | /* 6373 */ "tleu %ncc, $\x02\0" |
| 7558 | /* 6387 */ "tleu %icc, $\x01 + $\x02\0" |
| 7559 | /* 6406 */ "tleu %ncc, $\x01 + $\x02\0" |
| 7560 | /* 6425 */ "tcc %icc, $\x02\0" |
| 7561 | /* 6438 */ "tcc %ncc, $\x02\0" |
| 7562 | /* 6451 */ "tcc %icc, $\x01 + $\x02\0" |
| 7563 | /* 6469 */ "tcc %ncc, $\x01 + $\x02\0" |
| 7564 | /* 6487 */ "tcs %icc, $\x02\0" |
| 7565 | /* 6500 */ "tcs %ncc, $\x02\0" |
| 7566 | /* 6513 */ "tcs %icc, $\x01 + $\x02\0" |
| 7567 | /* 6531 */ "tcs %ncc, $\x01 + $\x02\0" |
| 7568 | /* 6549 */ "tpos %icc, $\x02\0" |
| 7569 | /* 6563 */ "tpos %ncc, $\x02\0" |
| 7570 | /* 6577 */ "tpos %icc, $\x01 + $\x02\0" |
| 7571 | /* 6596 */ "tpos %ncc, $\x01 + $\x02\0" |
| 7572 | /* 6615 */ "tneg %icc, $\x02\0" |
| 7573 | /* 6629 */ "tneg %ncc, $\x02\0" |
| 7574 | /* 6643 */ "tneg %icc, $\x01 + $\x02\0" |
| 7575 | /* 6662 */ "tneg %ncc, $\x01 + $\x02\0" |
| 7576 | /* 6681 */ "tvc %icc, $\x02\0" |
| 7577 | /* 6694 */ "tvc %ncc, $\x02\0" |
| 7578 | /* 6707 */ "tvc %icc, $\x01 + $\x02\0" |
| 7579 | /* 6725 */ "tvc %ncc, $\x01 + $\x02\0" |
| 7580 | /* 6743 */ "tvs %icc, $\x02\0" |
| 7581 | /* 6756 */ "tvs %ncc, $\x02\0" |
| 7582 | /* 6769 */ "tvs %icc, $\x01 + $\x02\0" |
| 7583 | /* 6787 */ "tvs %ncc, $\x01 + $\x02\0" |
| 7584 | /* 6805 */ "ta $\x02\0" |
| 7585 | /* 6811 */ "ta $\x01 + $\x02\0" |
| 7586 | /* 6822 */ "tn $\x02\0" |
| 7587 | /* 6828 */ "tn $\x01 + $\x02\0" |
| 7588 | /* 6839 */ "tne $\x02\0" |
| 7589 | /* 6846 */ "tne $\x01 + $\x02\0" |
| 7590 | /* 6858 */ "te $\x02\0" |
| 7591 | /* 6864 */ "te $\x01 + $\x02\0" |
| 7592 | /* 6875 */ "tg $\x02\0" |
| 7593 | /* 6881 */ "tg $\x01 + $\x02\0" |
| 7594 | /* 6892 */ "tle $\x02\0" |
| 7595 | /* 6899 */ "tle $\x01 + $\x02\0" |
| 7596 | /* 6911 */ "tge $\x02\0" |
| 7597 | /* 6918 */ "tge $\x01 + $\x02\0" |
| 7598 | /* 6930 */ "tl $\x02\0" |
| 7599 | /* 6936 */ "tl $\x01 + $\x02\0" |
| 7600 | /* 6947 */ "tgu $\x02\0" |
| 7601 | /* 6954 */ "tgu $\x01 + $\x02\0" |
| 7602 | /* 6966 */ "tleu $\x02\0" |
| 7603 | /* 6974 */ "tleu $\x01 + $\x02\0" |
| 7604 | /* 6987 */ "tcc $\x02\0" |
| 7605 | /* 6994 */ "tcc $\x01 + $\x02\0" |
| 7606 | /* 7006 */ "tcs $\x02\0" |
| 7607 | /* 7013 */ "tcs $\x01 + $\x02\0" |
| 7608 | /* 7025 */ "tpos $\x02\0" |
| 7609 | /* 7033 */ "tpos $\x01 + $\x02\0" |
| 7610 | /* 7046 */ "tneg $\x02\0" |
| 7611 | /* 7054 */ "tneg $\x01 + $\x02\0" |
| 7612 | /* 7067 */ "tvc $\x02\0" |
| 7613 | /* 7074 */ "tvc $\x01 + $\x02\0" |
| 7614 | /* 7086 */ "tvs $\x02\0" |
| 7615 | /* 7093 */ "tvs $\x01 + $\x02\0" |
| 7616 | /* 7105 */ "ta %xcc, $\x02\0" |
| 7617 | /* 7117 */ "ta %xcc, $\x01 + $\x02\0" |
| 7618 | /* 7134 */ "tn %xcc, $\x02\0" |
| 7619 | /* 7146 */ "tn %xcc, $\x01 + $\x02\0" |
| 7620 | /* 7163 */ "tne %xcc, $\x02\0" |
| 7621 | /* 7176 */ "tne %xcc, $\x01 + $\x02\0" |
| 7622 | /* 7194 */ "te %xcc, $\x02\0" |
| 7623 | /* 7206 */ "te %xcc, $\x01 + $\x02\0" |
| 7624 | /* 7223 */ "tg %xcc, $\x02\0" |
| 7625 | /* 7235 */ "tg %xcc, $\x01 + $\x02\0" |
| 7626 | /* 7252 */ "tle %xcc, $\x02\0" |
| 7627 | /* 7265 */ "tle %xcc, $\x01 + $\x02\0" |
| 7628 | /* 7283 */ "tge %xcc, $\x02\0" |
| 7629 | /* 7296 */ "tge %xcc, $\x01 + $\x02\0" |
| 7630 | /* 7314 */ "tl %xcc, $\x02\0" |
| 7631 | /* 7326 */ "tl %xcc, $\x01 + $\x02\0" |
| 7632 | /* 7343 */ "tgu %xcc, $\x02\0" |
| 7633 | /* 7356 */ "tgu %xcc, $\x01 + $\x02\0" |
| 7634 | /* 7374 */ "tleu %xcc, $\x02\0" |
| 7635 | /* 7388 */ "tleu %xcc, $\x01 + $\x02\0" |
| 7636 | /* 7407 */ "tcc %xcc, $\x02\0" |
| 7637 | /* 7420 */ "tcc %xcc, $\x01 + $\x02\0" |
| 7638 | /* 7438 */ "tcs %xcc, $\x02\0" |
| 7639 | /* 7451 */ "tcs %xcc, $\x01 + $\x02\0" |
| 7640 | /* 7469 */ "tpos %xcc, $\x02\0" |
| 7641 | /* 7483 */ "tpos %xcc, $\x01 + $\x02\0" |
| 7642 | /* 7502 */ "tneg %xcc, $\x02\0" |
| 7643 | /* 7516 */ "tneg %xcc, $\x01 + $\x02\0" |
| 7644 | /* 7535 */ "tvc %xcc, $\x02\0" |
| 7645 | /* 7548 */ "tvc %xcc, $\x01 + $\x02\0" |
| 7646 | /* 7566 */ "tvs %xcc, $\x02\0" |
| 7647 | /* 7579 */ "tvs %xcc, $\x01 + $\x02\0" |
| 7648 | /* 7597 */ "fcmpd $\x02, $\x03\0" |
| 7649 | /* 7610 */ "fcmped $\x02, $\x03\0" |
| 7650 | /* 7624 */ "fcmpeq $\x02, $\x03\0" |
| 7651 | /* 7638 */ "fcmpes $\x02, $\x03\0" |
| 7652 | /* 7652 */ "fcmpq $\x02, $\x03\0" |
| 7653 | /* 7665 */ "fcmps $\x02, $\x03\0" |
| 7654 | /* 7678 */ "fmovda $\x02, $\x03, $\x01\0" |
| 7655 | /* 7696 */ "fmovdn $\x02, $\x03, $\x01\0" |
| 7656 | /* 7714 */ "fmovdu $\x02, $\x03, $\x01\0" |
| 7657 | /* 7732 */ "fmovdg $\x02, $\x03, $\x01\0" |
| 7658 | /* 7750 */ "fmovdug $\x02, $\x03, $\x01\0" |
| 7659 | /* 7769 */ "fmovdl $\x02, $\x03, $\x01\0" |
| 7660 | /* 7787 */ "fmovdul $\x02, $\x03, $\x01\0" |
| 7661 | /* 7806 */ "fmovdlg $\x02, $\x03, $\x01\0" |
| 7662 | /* 7825 */ "fmovdne $\x02, $\x03, $\x01\0" |
| 7663 | /* 7844 */ "fmovde $\x02, $\x03, $\x01\0" |
| 7664 | /* 7862 */ "fmovdue $\x02, $\x03, $\x01\0" |
| 7665 | /* 7881 */ "fmovdge $\x02, $\x03, $\x01\0" |
| 7666 | /* 7900 */ "fmovduge $\x02, $\x03, $\x01\0" |
| 7667 | /* 7920 */ "fmovdle $\x02, $\x03, $\x01\0" |
| 7668 | /* 7939 */ "fmovdule $\x02, $\x03, $\x01\0" |
| 7669 | /* 7959 */ "fmovdo $\x02, $\x03, $\x01\0" |
| 7670 | /* 7977 */ "fmovqa $\x02, $\x03, $\x01\0" |
| 7671 | /* 7995 */ "fmovqn $\x02, $\x03, $\x01\0" |
| 7672 | /* 8013 */ "fmovqu $\x02, $\x03, $\x01\0" |
| 7673 | /* 8031 */ "fmovqg $\x02, $\x03, $\x01\0" |
| 7674 | /* 8049 */ "fmovqug $\x02, $\x03, $\x01\0" |
| 7675 | /* 8068 */ "fmovql $\x02, $\x03, $\x01\0" |
| 7676 | /* 8086 */ "fmovqul $\x02, $\x03, $\x01\0" |
| 7677 | /* 8105 */ "fmovqlg $\x02, $\x03, $\x01\0" |
| 7678 | /* 8124 */ "fmovqne $\x02, $\x03, $\x01\0" |
| 7679 | /* 8143 */ "fmovqe $\x02, $\x03, $\x01\0" |
| 7680 | /* 8161 */ "fmovque $\x02, $\x03, $\x01\0" |
| 7681 | /* 8180 */ "fmovqge $\x02, $\x03, $\x01\0" |
| 7682 | /* 8199 */ "fmovquge $\x02, $\x03, $\x01\0" |
| 7683 | /* 8219 */ "fmovqle $\x02, $\x03, $\x01\0" |
| 7684 | /* 8238 */ "fmovqule $\x02, $\x03, $\x01\0" |
| 7685 | /* 8258 */ "fmovqo $\x02, $\x03, $\x01\0" |
| 7686 | /* 8276 */ "fmovsa $\x02, $\x03, $\x01\0" |
| 7687 | /* 8294 */ "fmovsn $\x02, $\x03, $\x01\0" |
| 7688 | /* 8312 */ "fmovsu $\x02, $\x03, $\x01\0" |
| 7689 | /* 8330 */ "fmovsg $\x02, $\x03, $\x01\0" |
| 7690 | /* 8348 */ "fmovsug $\x02, $\x03, $\x01\0" |
| 7691 | /* 8367 */ "fmovsl $\x02, $\x03, $\x01\0" |
| 7692 | /* 8385 */ "fmovsul $\x02, $\x03, $\x01\0" |
| 7693 | /* 8404 */ "fmovslg $\x02, $\x03, $\x01\0" |
| 7694 | /* 8423 */ "fmovsne $\x02, $\x03, $\x01\0" |
| 7695 | /* 8442 */ "fmovse $\x02, $\x03, $\x01\0" |
| 7696 | /* 8460 */ "fmovsue $\x02, $\x03, $\x01\0" |
| 7697 | /* 8479 */ "fmovsge $\x02, $\x03, $\x01\0" |
| 7698 | /* 8498 */ "fmovsuge $\x02, $\x03, $\x01\0" |
| 7699 | /* 8518 */ "fmovsle $\x02, $\x03, $\x01\0" |
| 7700 | /* 8537 */ "fmovsule $\x02, $\x03, $\x01\0" |
| 7701 | /* 8557 */ "fmovso $\x02, $\x03, $\x01\0" |
| 7702 | /* 8575 */ "mova $\x02, $\x03, $\x01\0" |
| 7703 | /* 8591 */ "movn $\x02, $\x03, $\x01\0" |
| 7704 | /* 8607 */ "movu $\x02, $\x03, $\x01\0" |
| 7705 | /* 8623 */ "movg $\x02, $\x03, $\x01\0" |
| 7706 | /* 8639 */ "movug $\x02, $\x03, $\x01\0" |
| 7707 | /* 8656 */ "movl $\x02, $\x03, $\x01\0" |
| 7708 | /* 8672 */ "movul $\x02, $\x03, $\x01\0" |
| 7709 | /* 8689 */ "movlg $\x02, $\x03, $\x01\0" |
| 7710 | /* 8706 */ "movne $\x02, $\x03, $\x01\0" |
| 7711 | /* 8723 */ "move $\x02, $\x03, $\x01\0" |
| 7712 | /* 8739 */ "movue $\x02, $\x03, $\x01\0" |
| 7713 | /* 8756 */ "movge $\x02, $\x03, $\x01\0" |
| 7714 | /* 8773 */ "movuge $\x02, $\x03, $\x01\0" |
| 7715 | /* 8791 */ "movle $\x02, $\x03, $\x01\0" |
| 7716 | /* 8808 */ "movule $\x02, $\x03, $\x01\0" |
| 7717 | /* 8826 */ "movo $\x02, $\x03, $\x01\0" |
| 7718 | /* 8842 */ "pause $\x03\0" |
| 7719 | ; |
| 7720 | |
| 7721 | #ifndef NDEBUG |
| 7722 | static struct SortCheck { |
| 7723 | SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) { |
| 7724 | assert(std::is_sorted( |
| 7725 | OpToPatterns.begin(), OpToPatterns.end(), |
| 7726 | [](const PatternsForOpcode &L, const PatternsForOpcode &R) { |
| 7727 | return L.Opcode < R.Opcode; |
| 7728 | }) && |
| 7729 | "tablegen failed to sort opcode patterns"); |
| 7730 | } |
| 7731 | } sortCheckVar(OpToPatterns); |
| 7732 | #endif |
| 7733 | |
| 7734 | AliasMatchingData M { |
| 7735 | .OpToPatterns: ArrayRef(OpToPatterns), |
| 7736 | .Patterns: ArrayRef(Patterns), |
| 7737 | .PatternConds: ArrayRef(Conds), |
| 7738 | .AsmStrings: StringRef(AsmStrings, std::size(AsmStrings)), |
| 7739 | .ValidateMCOperand: nullptr, |
| 7740 | }; |
| 7741 | const char *AsmString = matchAliasPatterns(MI, STI: &STI, M); |
| 7742 | if (!AsmString) return false; |
| 7743 | |
| 7744 | unsigned I = 0; |
| 7745 | while (AsmString[I] != ' ' && AsmString[I] != '\t' && |
| 7746 | AsmString[I] != '$' && AsmString[I] != '\0') |
| 7747 | ++I; |
| 7748 | OS << '\t' << StringRef(AsmString, I); |
| 7749 | if (AsmString[I] != '\0') { |
| 7750 | if (AsmString[I] == ' ' || AsmString[I] == '\t') { |
| 7751 | OS << '\t'; |
| 7752 | ++I; |
| 7753 | } |
| 7754 | do { |
| 7755 | if (AsmString[I] == '$') { |
| 7756 | ++I; |
| 7757 | if (AsmString[I] == (char)0xff) { |
| 7758 | ++I; |
| 7759 | int OpIdx = AsmString[I++] - 1; |
| 7760 | int PrintMethodIdx = AsmString[I++] - 1; |
| 7761 | printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, STI, O&: OS); |
| 7762 | } else |
| 7763 | printOperand(MI, opNum: unsigned(AsmString[I++]) - 1, STI, OS); |
| 7764 | } else { |
| 7765 | OS << AsmString[I++]; |
| 7766 | } |
| 7767 | } while (AsmString[I] != '\0'); |
| 7768 | } |
| 7769 | |
| 7770 | return true; |
| 7771 | } |
| 7772 | |
| 7773 | void SparcInstPrinter::printCustomAliasOperand( |
| 7774 | const MCInst *MI, uint64_t Address, unsigned OpIdx, |
| 7775 | unsigned PrintMethodIdx, |
| 7776 | const MCSubtargetInfo &STI, |
| 7777 | raw_ostream &OS) { |
| 7778 | switch (PrintMethodIdx) { |
| 7779 | default: |
| 7780 | llvm_unreachable("Unknown PrintMethod kind"); |
| 7781 | break; |
| 7782 | case 0: |
| 7783 | printCTILabel(MI, Address, OpNum: OpIdx, STI, O&: OS); |
| 7784 | break; |
| 7785 | } |
| 7786 | } |
| 7787 | |
| 7788 | #endif // PRINT_ALIAS_INSTR |
| 7789 |
Generated while processing llvm_projects/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
Generated on 2026-Apr-05 from project llvm_projects revision 36e495dd9
Powered by 
Code Browser 2.1
Generator usage only permitted with license.