1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Writer Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: Sparc.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10/// getMnemonic - This method is automatically generated by tablegen
11/// from the instruction set description.
12std::pair<const char *, uint64_t>
13SparcInstPrinter::getMnemonic(const MCInst &MI) const {
14
15#ifdef __GNUC__
16#pragma GCC diagnostic push
17#pragma GCC diagnostic ignored "-Woverlength-strings"
18#endif
19 static const char AsmStrs[] = {
20 /* 0 */ "fcmpd %fcc0, \000"
21 /* 14 */ "fcmpq %fcc0, \000"
22 /* 28 */ "fcmps %fcc0, \000"
23 /* 42 */ "rd %wim, \000"
24 /* 52 */ "rdpr %fq, \000"
25 /* 63 */ "rd %tbr, \000"
26 /* 73 */ "rd %psr, \000"
27 /* 83 */ "aes_kexpand0 \000"
28 /* 97 */ "aes_dround01 \000"
29 /* 111 */ "aes_eround01 \000"
30 /* 125 */ "fsrc1 \000"
31 /* 132 */ "aes_kexpand1 \000"
32 /* 146 */ "fandnot1 \000"
33 /* 156 */ "fnot1 \000"
34 /* 163 */ "fornot1 \000"
35 /* 172 */ "fsra32 \000"
36 /* 180 */ "fpsub32 \000"
37 /* 189 */ "fpadd32 \000"
38 /* 198 */ "edge32 \000"
39 /* 206 */ "fcmple32 \000"
40 /* 216 */ "fcmpne32 \000"
41 /* 226 */ "fpack32 \000"
42 /* 235 */ "cmask32 \000"
43 /* 244 */ "fsll32 \000"
44 /* 252 */ "fsrl32 \000"
45 /* 260 */ "fcmpeq32 \000"
46 /* 270 */ "fslas32 \000"
47 /* 279 */ "fcmpgt32 \000"
48 /* 289 */ "array32 \000"
49 /* 298 */ "fsrc2 \000"
50 /* 305 */ "aes_kexpand2 \000"
51 /* 319 */ "fandnot2 \000"
52 /* 329 */ "fnot2 \000"
53 /* 336 */ "fornot2 \000"
54 /* 345 */ "aes_dround23 \000"
55 /* 359 */ "aes_eround23 \000"
56 /* 373 */ "fpadd64 \000"
57 /* 382 */ "fsra16 \000"
58 /* 390 */ "fpsub16 \000"
59 /* 399 */ "fpadd16 \000"
60 /* 408 */ "edge16 \000"
61 /* 416 */ "fcmple16 \000"
62 /* 426 */ "fcmpne16 \000"
63 /* 436 */ "fpack16 \000"
64 /* 445 */ "cmask16 \000"
65 /* 454 */ "fsll16 \000"
66 /* 462 */ "fsrl16 \000"
67 /* 470 */ "fchksm16 \000"
68 /* 480 */ "fmean16 \000"
69 /* 489 */ "fcmpeq16 \000"
70 /* 499 */ "fslas16 \000"
71 /* 508 */ "fcmpgt16 \000"
72 /* 518 */ "fmul8x16 \000"
73 /* 528 */ "fmuld8ulx16 \000"
74 /* 541 */ "fmul8ulx16 \000"
75 /* 553 */ "fmuld8sux16 \000"
76 /* 566 */ "fmul8sux16 \000"
77 /* 578 */ "array16 \000"
78 /* 587 */ "edge8 \000"
79 /* 594 */ "cmask8 \000"
80 /* 602 */ "array8 \000"
81 /* 610 */ "!ADJCALLSTACKDOWN \000"
82 /* 629 */ "!ADJCALLSTACKUP \000"
83 /* 646 */ "stba \000"
84 /* 652 */ "stda \000"
85 /* 658 */ "stha \000"
86 /* 664 */ "stqa \000"
87 /* 670 */ "sra \000"
88 /* 675 */ "faligndata \000"
89 /* 687 */ "sta \000"
90 /* 692 */ "stxa \000"
91 /* 698 */ "stb \000"
92 /* 703 */ "sub \000"
93 /* 708 */ "crc32c \000"
94 /* 716 */ "smac \000"
95 /* 722 */ "umac \000"
96 /* 728 */ "tsubcc \000"
97 /* 736 */ "addxccc \000"
98 /* 745 */ "taddcc \000"
99 /* 753 */ "andcc \000"
100 /* 760 */ "smulcc \000"
101 /* 768 */ "umulcc \000"
102 /* 776 */ "andncc \000"
103 /* 784 */ "orncc \000"
104 /* 791 */ "xnorcc \000"
105 /* 799 */ "xorcc \000"
106 /* 806 */ "mulscc \000"
107 /* 814 */ "sdivcc \000"
108 /* 822 */ "udivcc \000"
109 /* 830 */ "subxcc \000"
110 /* 838 */ "addxcc \000"
111 /* 846 */ "popc \000"
112 /* 852 */ "addxc \000"
113 /* 859 */ "fsubd \000"
114 /* 866 */ "fhsubd \000"
115 /* 874 */ "fmsubd \000"
116 /* 882 */ "fnmsubd \000"
117 /* 891 */ "add \000"
118 /* 896 */ "faddd \000"
119 /* 903 */ "fhaddd \000"
120 /* 911 */ "fnhaddd \000"
121 /* 920 */ "fmaddd \000"
122 /* 928 */ "fnmaddd \000"
123 /* 937 */ "fnaddd \000"
124 /* 945 */ "fcmped \000"
125 /* 953 */ "fnegd \000"
126 /* 960 */ "fmuld \000"
127 /* 967 */ "fnmuld \000"
128 /* 975 */ "fsmuld \000"
129 /* 983 */ "fnsmuld \000"
130 /* 992 */ "fand \000"
131 /* 998 */ "fnand \000"
132 /* 1005 */ "fexpand \000"
133 /* 1014 */ "des_kexpand \000"
134 /* 1027 */ "des_round \000"
135 /* 1038 */ "fitod \000"
136 /* 1045 */ "fqtod \000"
137 /* 1052 */ "fstod \000"
138 /* 1059 */ "fxtod \000"
139 /* 1066 */ "movxtod \000"
140 /* 1075 */ "fcmpd \000"
141 /* 1082 */ "flcmpd \000"
142 /* 1090 */ "rd \000"
143 /* 1094 */ "fabsd \000"
144 /* 1101 */ "fsqrtd \000"
145 /* 1109 */ "std \000"
146 /* 1114 */ "fdivd \000"
147 /* 1121 */ "fmovd \000"
148 /* 1128 */ "fpmerge \000"
149 /* 1137 */ "bshuffle \000"
150 /* 1147 */ "fone \000"
151 /* 1153 */ "restore \000"
152 /* 1162 */ "save \000"
153 /* 1168 */ "camellia_f \000"
154 /* 1180 */ "flush \000"
155 /* 1187 */ "sth \000"
156 /* 1192 */ "sethi \000"
157 /* 1199 */ "fpmaddxhi \000"
158 /* 1210 */ "umulxhi \000"
159 /* 1219 */ "xmulxhi \000"
160 /* 1228 */ "camellia_fli \000"
161 /* 1242 */ "fdtoi \000"
162 /* 1249 */ "fqtoi \000"
163 /* 1256 */ "fstoi \000"
164 /* 1263 */ "bmask \000"
165 /* 1270 */ "edge32l \000"
166 /* 1279 */ "edge16l \000"
167 /* 1288 */ "edge8l \000"
168 /* 1296 */ "aes_dround01_l \000"
169 /* 1312 */ "aes_eround01_l \000"
170 /* 1328 */ "aes_dround23_l \000"
171 /* 1344 */ "aes_eround23_l \000"
172 /* 1360 */ "fmul8x16al \000"
173 /* 1372 */ "camellia_fl \000"
174 /* 1385 */ "call \000"
175 /* 1391 */ "sll \000"
176 /* 1396 */ "jmpl \000"
177 /* 1402 */ "alignaddrl \000"
178 /* 1414 */ "srl \000"
179 /* 1419 */ "mpmul \000"
180 /* 1426 */ "smul \000"
181 /* 1432 */ "montmul \000"
182 /* 1441 */ "umul \000"
183 /* 1447 */ "siam \000"
184 /* 1453 */ "edge32n \000"
185 /* 1462 */ "edge16n \000"
186 /* 1471 */ "edge8n \000"
187 /* 1479 */ "andn \000"
188 /* 1485 */ "edge32ln \000"
189 /* 1495 */ "edge16ln \000"
190 /* 1505 */ "edge8ln \000"
191 /* 1514 */ "orn \000"
192 /* 1519 */ "pdistn \000"
193 /* 1527 */ "fzero \000"
194 /* 1534 */ "des_ip \000"
195 /* 1542 */ "des_iip \000"
196 /* 1551 */ "unimp \000"
197 /* 1558 */ "jmp \000"
198 /* 1563 */ "fsubq \000"
199 /* 1570 */ "faddq \000"
200 /* 1577 */ "fcmpeq \000"
201 /* 1585 */ "fnegq \000"
202 /* 1592 */ "fdmulq \000"
203 /* 1600 */ "fmulq \000"
204 /* 1607 */ "fdtoq \000"
205 /* 1614 */ "fitoq \000"
206 /* 1621 */ "fstoq \000"
207 /* 1628 */ "fxtoq \000"
208 /* 1635 */ "fcmpq \000"
209 /* 1642 */ "fabsq \000"
210 /* 1649 */ "fsqrtq \000"
211 /* 1657 */ "stq \000"
212 /* 1662 */ "fdivq \000"
213 /* 1669 */ "fmovq \000"
214 /* 1676 */ "membar \000"
215 /* 1684 */ "alignaddr \000"
216 /* 1695 */ "sir \000"
217 /* 1700 */ "for \000"
218 /* 1705 */ "fnor \000"
219 /* 1711 */ "fxnor \000"
220 /* 1718 */ "fxor \000"
221 /* 1724 */ "rdpr \000"
222 /* 1730 */ "wrpr \000"
223 /* 1736 */ "montsqr \000"
224 /* 1745 */ "pwr \000"
225 /* 1750 */ "fsrc1s \000"
226 /* 1758 */ "fandnot1s \000"
227 /* 1769 */ "fnot1s \000"
228 /* 1777 */ "fornot1s \000"
229 /* 1787 */ "fpsub32s \000"
230 /* 1797 */ "fpadd32s \000"
231 /* 1807 */ "fsrc2s \000"
232 /* 1815 */ "fandnot2s \000"
233 /* 1826 */ "fnot2s \000"
234 /* 1834 */ "fornot2s \000"
235 /* 1844 */ "fpsub16s \000"
236 /* 1854 */ "fpadd16s \000"
237 /* 1864 */ "fsubs \000"
238 /* 1871 */ "fhsubs \000"
239 /* 1879 */ "fmsubs \000"
240 /* 1887 */ "fnmsubs \000"
241 /* 1896 */ "fadds \000"
242 /* 1903 */ "fhadds \000"
243 /* 1911 */ "fnhadds \000"
244 /* 1920 */ "fmadds \000"
245 /* 1928 */ "fnmadds \000"
246 /* 1937 */ "fnadds \000"
247 /* 1945 */ "fands \000"
248 /* 1952 */ "fnands \000"
249 /* 1960 */ "fones \000"
250 /* 1967 */ "fcmpes \000"
251 /* 1975 */ "fnegs \000"
252 /* 1982 */ "fmuls \000"
253 /* 1989 */ "fnmuls \000"
254 /* 1997 */ "fzeros \000"
255 /* 2005 */ "fdtos \000"
256 /* 2012 */ "fitos \000"
257 /* 2019 */ "fqtos \000"
258 /* 2026 */ "movwtos \000"
259 /* 2035 */ "fxtos \000"
260 /* 2042 */ "fcmps \000"
261 /* 2049 */ "flcmps \000"
262 /* 2057 */ "fors \000"
263 /* 2063 */ "fnors \000"
264 /* 2070 */ "fxnors \000"
265 /* 2078 */ "fxors \000"
266 /* 2085 */ "fabss \000"
267 /* 2092 */ "fsqrts \000"
268 /* 2100 */ "fdivs \000"
269 /* 2107 */ "fmovs \000"
270 /* 2114 */ "set \000"
271 /* 2119 */ "lzcnt \000"
272 /* 2126 */ "pdist \000"
273 /* 2133 */ "rett \000"
274 /* 2139 */ "fmul8x16au \000"
275 /* 2151 */ "sdiv \000"
276 /* 2157 */ "udiv \000"
277 /* 2163 */ "tsubcctv \000"
278 /* 2173 */ "taddcctv \000"
279 /* 2183 */ "movstosw \000"
280 /* 2193 */ "setsw \000"
281 /* 2200 */ "movstouw \000"
282 /* 2210 */ "srax \000"
283 /* 2216 */ "subx \000"
284 /* 2222 */ "fpmaddx \000"
285 /* 2231 */ "fpackfix \000"
286 /* 2241 */ "sllx \000"
287 /* 2247 */ "srlx \000"
288 /* 2253 */ "xmulx \000"
289 /* 2260 */ "fdtox \000"
290 /* 2267 */ "movdtox \000"
291 /* 2276 */ "fqtox \000"
292 /* 2283 */ "fstox \000"
293 /* 2290 */ "setx \000"
294 /* 2296 */ "stx \000"
295 /* 2301 */ "sdivx \000"
296 /* 2308 */ "udivx \000"
297 /* 2315 */ "; SELECT_CC_DFP_FCC PSEUDO!\000"
298 /* 2343 */ "; SELECT_CC_QFP_FCC PSEUDO!\000"
299 /* 2371 */ "; SELECT_CC_FP_FCC PSEUDO!\000"
300 /* 2398 */ "; SELECT_CC_Int_FCC PSEUDO!\000"
301 /* 2426 */ "; SELECT_CC_DFP_ICC PSEUDO!\000"
302 /* 2454 */ "; SELECT_CC_QFP_ICC PSEUDO!\000"
303 /* 2482 */ "; SELECT_CC_FP_ICC PSEUDO!\000"
304 /* 2509 */ "; SELECT_CC_Int_ICC PSEUDO!\000"
305 /* 2537 */ "; SELECT_CC_DFP_XCC PSEUDO!\000"
306 /* 2565 */ "; SELECT_CC_QFP_XCC PSEUDO!\000"
307 /* 2593 */ "; SELECT_CC_FP_XCC PSEUDO!\000"
308 /* 2620 */ "; SELECT_CC_Int_XCC PSEUDO!\000"
309 /* 2648 */ "jmp %i7+\000"
310 /* 2657 */ "jmp %o7+\000"
311 /* 2666 */ "# XRay Function Patchable RET.\000"
312 /* 2697 */ "# XRay Typed Event Log.\000"
313 /* 2721 */ "# XRay Custom Event Log.\000"
314 /* 2746 */ "# XRay Function Enter.\000"
315 /* 2769 */ "# XRay Tail Call Exit.\000"
316 /* 2792 */ "# XRay Function Exit.\000"
317 /* 2814 */ "flush %g0\000"
318 /* 2824 */ "ta 1\000"
319 /* 2829 */ "sha1\000"
320 /* 2834 */ "sha512\000"
321 /* 2841 */ "ta 3\000"
322 /* 2846 */ "ta 5\000"
323 /* 2851 */ "md5\000"
324 /* 2855 */ "sha256\000"
325 /* 2862 */ "LIFETIME_END\000"
326 /* 2875 */ "PSEUDO_PROBE\000"
327 /* 2888 */ "BUNDLE\000"
328 /* 2895 */ "FAKE_USE\000"
329 /* 2904 */ "DBG_VALUE\000"
330 /* 2914 */ "DBG_INSTR_REF\000"
331 /* 2928 */ "DBG_PHI\000"
332 /* 2936 */ "DBG_LABEL\000"
333 /* 2946 */ "!V8BAR\000"
334 /* 2953 */ "LIFETIME_START\000"
335 /* 2968 */ "DBG_VALUE_LIST\000"
336 /* 2983 */ "std %cq, [\000"
337 /* 2994 */ "std %fq, [\000"
338 /* 3005 */ "st %csr, [\000"
339 /* 3016 */ "st %fsr, [\000"
340 /* 3027 */ "stx %fsr, [\000"
341 /* 3039 */ "ldsba [\000"
342 /* 3047 */ "lduba [\000"
343 /* 3055 */ "ldstuba [\000"
344 /* 3065 */ "ldda [\000"
345 /* 3072 */ "lda [\000"
346 /* 3078 */ "prefetcha [\000"
347 /* 3090 */ "ldsha [\000"
348 /* 3098 */ "lduha [\000"
349 /* 3106 */ "swapa [\000"
350 /* 3114 */ "ldqa [\000"
351 /* 3121 */ "casa [\000"
352 /* 3128 */ "ldswa [\000"
353 /* 3136 */ "ldxa [\000"
354 /* 3143 */ "casxa [\000"
355 /* 3151 */ "ldsb [\000"
356 /* 3158 */ "ldub [\000"
357 /* 3165 */ "ldstub [\000"
358 /* 3174 */ "ldd [\000"
359 /* 3180 */ "ld [\000"
360 /* 3185 */ "prefetch [\000"
361 /* 3196 */ "ldsh [\000"
362 /* 3203 */ "lduh [\000"
363 /* 3210 */ "swap [\000"
364 /* 3217 */ "ldq [\000"
365 /* 3223 */ "ldsw [\000"
366 /* 3230 */ "ldx [\000"
367 /* 3236 */ "cb\000"
368 /* 3239 */ "fb\000"
369 /* 3242 */ "cwb\000"
370 /* 3246 */ "cxb\000"
371 /* 3250 */ "restored\000"
372 /* 3259 */ "saved\000"
373 /* 3265 */ "fmovrd\000"
374 /* 3272 */ "fmovd\000"
375 /* 3278 */ "done\000"
376 /* 3283 */ "# FEntry call\000"
377 /* 3297 */ "allclean\000"
378 /* 3306 */ "shutdown\000"
379 /* 3315 */ "nop\000"
380 /* 3319 */ "fmovrq\000"
381 /* 3326 */ "fmovq\000"
382 /* 3332 */ "stbar\000"
383 /* 3338 */ "br\000"
384 /* 3341 */ "movr\000"
385 /* 3346 */ "fmovrs\000"
386 /* 3353 */ "fmovs\000"
387 /* 3359 */ "t\000"
388 /* 3361 */ "mov\000"
389 /* 3365 */ "flushw\000"
390 /* 3372 */ "normalw\000"
391 /* 3380 */ "invalw\000"
392 /* 3387 */ "otherw\000"
393 /* 3394 */ "retry\000"
394};
395#ifdef __GNUC__
396#pragma GCC diagnostic pop
397#endif
398
399 static const uint32_t OpInfo0[] = {
400 0U, // PHI
401 0U, // INLINEASM
402 0U, // INLINEASM_BR
403 0U, // CFI_INSTRUCTION
404 0U, // EH_LABEL
405 0U, // GC_LABEL
406 0U, // ANNOTATION_LABEL
407 0U, // KILL
408 0U, // EXTRACT_SUBREG
409 0U, // INSERT_SUBREG
410 0U, // IMPLICIT_DEF
411 0U, // INIT_UNDEF
412 0U, // SUBREG_TO_REG
413 0U, // COPY_TO_REGCLASS
414 2905U, // DBG_VALUE
415 2969U, // DBG_VALUE_LIST
416 2915U, // DBG_INSTR_REF
417 2929U, // DBG_PHI
418 2937U, // DBG_LABEL
419 0U, // REG_SEQUENCE
420 0U, // COPY
421 0U, // COPY_LANEMASK
422 2889U, // BUNDLE
423 2954U, // LIFETIME_START
424 2863U, // LIFETIME_END
425 2876U, // PSEUDO_PROBE
426 0U, // ARITH_FENCE
427 0U, // STACKMAP
428 3284U, // FENTRY_CALL
429 0U, // PATCHPOINT
430 0U, // LOAD_STACK_GUARD
431 0U, // PREALLOCATED_SETUP
432 0U, // PREALLOCATED_ARG
433 0U, // STATEPOINT
434 0U, // LOCAL_ESCAPE
435 0U, // FAULTING_OP
436 0U, // PATCHABLE_OP
437 2747U, // PATCHABLE_FUNCTION_ENTER
438 2667U, // PATCHABLE_RET
439 2793U, // PATCHABLE_FUNCTION_EXIT
440 2770U, // PATCHABLE_TAIL_CALL
441 2722U, // PATCHABLE_EVENT_CALL
442 2698U, // PATCHABLE_TYPED_EVENT_CALL
443 0U, // ICALL_BRANCH_FUNNEL
444 2896U, // FAKE_USE
445 0U, // MEMBARRIER
446 0U, // JUMP_TABLE_DEBUG_INFO
447 0U, // RELOC_NONE
448 0U, // CONVERGENCECTRL_ENTRY
449 0U, // CONVERGENCECTRL_ANCHOR
450 0U, // CONVERGENCECTRL_LOOP
451 0U, // CONVERGENCECTRL_GLUE
452 0U, // G_ASSERT_SEXT
453 0U, // G_ASSERT_ZEXT
454 0U, // G_ASSERT_ALIGN
455 0U, // G_ADD
456 0U, // G_SUB
457 0U, // G_MUL
458 0U, // G_SDIV
459 0U, // G_UDIV
460 0U, // G_SREM
461 0U, // G_UREM
462 0U, // G_SDIVREM
463 0U, // G_UDIVREM
464 0U, // G_AND
465 0U, // G_OR
466 0U, // G_XOR
467 0U, // G_ABDS
468 0U, // G_ABDU
469 0U, // G_UAVGFLOOR
470 0U, // G_UAVGCEIL
471 0U, // G_SAVGFLOOR
472 0U, // G_SAVGCEIL
473 0U, // G_IMPLICIT_DEF
474 0U, // G_PHI
475 0U, // G_FRAME_INDEX
476 0U, // G_GLOBAL_VALUE
477 0U, // G_PTRAUTH_GLOBAL_VALUE
478 0U, // G_CONSTANT_POOL
479 0U, // G_EXTRACT
480 0U, // G_UNMERGE_VALUES
481 0U, // G_INSERT
482 0U, // G_MERGE_VALUES
483 0U, // G_BUILD_VECTOR
484 0U, // G_BUILD_VECTOR_TRUNC
485 0U, // G_CONCAT_VECTORS
486 0U, // G_PTRTOINT
487 0U, // G_INTTOPTR
488 0U, // G_BITCAST
489 0U, // G_FREEZE
490 0U, // G_CONSTANT_FOLD_BARRIER
491 0U, // G_INTRINSIC_FPTRUNC_ROUND
492 0U, // G_INTRINSIC_TRUNC
493 0U, // G_INTRINSIC_ROUND
494 0U, // G_INTRINSIC_LRINT
495 0U, // G_INTRINSIC_LLRINT
496 0U, // G_INTRINSIC_ROUNDEVEN
497 0U, // G_READCYCLECOUNTER
498 0U, // G_READSTEADYCOUNTER
499 0U, // G_LOAD
500 0U, // G_SEXTLOAD
501 0U, // G_ZEXTLOAD
502 0U, // G_INDEXED_LOAD
503 0U, // G_INDEXED_SEXTLOAD
504 0U, // G_INDEXED_ZEXTLOAD
505 0U, // G_STORE
506 0U, // G_INDEXED_STORE
507 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
508 0U, // G_ATOMIC_CMPXCHG
509 0U, // G_ATOMICRMW_XCHG
510 0U, // G_ATOMICRMW_ADD
511 0U, // G_ATOMICRMW_SUB
512 0U, // G_ATOMICRMW_AND
513 0U, // G_ATOMICRMW_NAND
514 0U, // G_ATOMICRMW_OR
515 0U, // G_ATOMICRMW_XOR
516 0U, // G_ATOMICRMW_MAX
517 0U, // G_ATOMICRMW_MIN
518 0U, // G_ATOMICRMW_UMAX
519 0U, // G_ATOMICRMW_UMIN
520 0U, // G_ATOMICRMW_FADD
521 0U, // G_ATOMICRMW_FSUB
522 0U, // G_ATOMICRMW_FMAX
523 0U, // G_ATOMICRMW_FMIN
524 0U, // G_ATOMICRMW_FMAXIMUM
525 0U, // G_ATOMICRMW_FMINIMUM
526 0U, // G_ATOMICRMW_UINC_WRAP
527 0U, // G_ATOMICRMW_UDEC_WRAP
528 0U, // G_ATOMICRMW_USUB_COND
529 0U, // G_ATOMICRMW_USUB_SAT
530 0U, // G_FENCE
531 0U, // G_PREFETCH
532 0U, // G_BRCOND
533 0U, // G_BRINDIRECT
534 0U, // G_INVOKE_REGION_START
535 0U, // G_INTRINSIC
536 0U, // G_INTRINSIC_W_SIDE_EFFECTS
537 0U, // G_INTRINSIC_CONVERGENT
538 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
539 0U, // G_ANYEXT
540 0U, // G_TRUNC
541 0U, // G_TRUNC_SSAT_S
542 0U, // G_TRUNC_SSAT_U
543 0U, // G_TRUNC_USAT_U
544 0U, // G_CONSTANT
545 0U, // G_FCONSTANT
546 0U, // G_VASTART
547 0U, // G_VAARG
548 0U, // G_SEXT
549 0U, // G_SEXT_INREG
550 0U, // G_ZEXT
551 0U, // G_SHL
552 0U, // G_LSHR
553 0U, // G_ASHR
554 0U, // G_FSHL
555 0U, // G_FSHR
556 0U, // G_ROTR
557 0U, // G_ROTL
558 0U, // G_ICMP
559 0U, // G_FCMP
560 0U, // G_SCMP
561 0U, // G_UCMP
562 0U, // G_SELECT
563 0U, // G_UADDO
564 0U, // G_UADDE
565 0U, // G_USUBO
566 0U, // G_USUBE
567 0U, // G_SADDO
568 0U, // G_SADDE
569 0U, // G_SSUBO
570 0U, // G_SSUBE
571 0U, // G_UMULO
572 0U, // G_SMULO
573 0U, // G_UMULH
574 0U, // G_SMULH
575 0U, // G_UADDSAT
576 0U, // G_SADDSAT
577 0U, // G_USUBSAT
578 0U, // G_SSUBSAT
579 0U, // G_USHLSAT
580 0U, // G_SSHLSAT
581 0U, // G_SMULFIX
582 0U, // G_UMULFIX
583 0U, // G_SMULFIXSAT
584 0U, // G_UMULFIXSAT
585 0U, // G_SDIVFIX
586 0U, // G_UDIVFIX
587 0U, // G_SDIVFIXSAT
588 0U, // G_UDIVFIXSAT
589 0U, // G_FADD
590 0U, // G_FSUB
591 0U, // G_FMUL
592 0U, // G_FMA
593 0U, // G_FMAD
594 0U, // G_FDIV
595 0U, // G_FREM
596 0U, // G_FMODF
597 0U, // G_FPOW
598 0U, // G_FPOWI
599 0U, // G_FEXP
600 0U, // G_FEXP2
601 0U, // G_FEXP10
602 0U, // G_FLOG
603 0U, // G_FLOG2
604 0U, // G_FLOG10
605 0U, // G_FLDEXP
606 0U, // G_FFREXP
607 0U, // G_FNEG
608 0U, // G_FPEXT
609 0U, // G_FPTRUNC
610 0U, // G_FPTOSI
611 0U, // G_FPTOUI
612 0U, // G_SITOFP
613 0U, // G_UITOFP
614 0U, // G_FPTOSI_SAT
615 0U, // G_FPTOUI_SAT
616 0U, // G_FABS
617 0U, // G_FCOPYSIGN
618 0U, // G_IS_FPCLASS
619 0U, // G_FCANONICALIZE
620 0U, // G_FMINNUM
621 0U, // G_FMAXNUM
622 0U, // G_FMINNUM_IEEE
623 0U, // G_FMAXNUM_IEEE
624 0U, // G_FMINIMUM
625 0U, // G_FMAXIMUM
626 0U, // G_FMINIMUMNUM
627 0U, // G_FMAXIMUMNUM
628 0U, // G_GET_FPENV
629 0U, // G_SET_FPENV
630 0U, // G_RESET_FPENV
631 0U, // G_GET_FPMODE
632 0U, // G_SET_FPMODE
633 0U, // G_RESET_FPMODE
634 0U, // G_GET_ROUNDING
635 0U, // G_SET_ROUNDING
636 0U, // G_PTR_ADD
637 0U, // G_PTRMASK
638 0U, // G_SMIN
639 0U, // G_SMAX
640 0U, // G_UMIN
641 0U, // G_UMAX
642 0U, // G_ABS
643 0U, // G_LROUND
644 0U, // G_LLROUND
645 0U, // G_BR
646 0U, // G_BRJT
647 0U, // G_VSCALE
648 0U, // G_INSERT_SUBVECTOR
649 0U, // G_EXTRACT_SUBVECTOR
650 0U, // G_INSERT_VECTOR_ELT
651 0U, // G_EXTRACT_VECTOR_ELT
652 0U, // G_SHUFFLE_VECTOR
653 0U, // G_SPLAT_VECTOR
654 0U, // G_STEP_VECTOR
655 0U, // G_VECTOR_COMPRESS
656 0U, // G_CTTZ
657 0U, // G_CTTZ_ZERO_UNDEF
658 0U, // G_CTLZ
659 0U, // G_CTLZ_ZERO_UNDEF
660 0U, // G_CTLS
661 0U, // G_CTPOP
662 0U, // G_BSWAP
663 0U, // G_BITREVERSE
664 0U, // G_FCEIL
665 0U, // G_FCOS
666 0U, // G_FSIN
667 0U, // G_FSINCOS
668 0U, // G_FTAN
669 0U, // G_FACOS
670 0U, // G_FASIN
671 0U, // G_FATAN
672 0U, // G_FATAN2
673 0U, // G_FCOSH
674 0U, // G_FSINH
675 0U, // G_FTANH
676 0U, // G_FSQRT
677 0U, // G_FFLOOR
678 0U, // G_FRINT
679 0U, // G_FNEARBYINT
680 0U, // G_ADDRSPACE_CAST
681 0U, // G_BLOCK_ADDR
682 0U, // G_JUMP_TABLE
683 0U, // G_DYN_STACKALLOC
684 0U, // G_STACKSAVE
685 0U, // G_STACKRESTORE
686 0U, // G_STRICT_FADD
687 0U, // G_STRICT_FSUB
688 0U, // G_STRICT_FMUL
689 0U, // G_STRICT_FDIV
690 0U, // G_STRICT_FREM
691 0U, // G_STRICT_FMA
692 0U, // G_STRICT_FSQRT
693 0U, // G_STRICT_FLDEXP
694 0U, // G_READ_REGISTER
695 0U, // G_WRITE_REGISTER
696 0U, // G_MEMCPY
697 0U, // G_MEMCPY_INLINE
698 0U, // G_MEMMOVE
699 0U, // G_MEMSET
700 0U, // G_BZERO
701 0U, // G_TRAP
702 0U, // G_DEBUGTRAP
703 0U, // G_UBSANTRAP
704 0U, // G_VECREDUCE_SEQ_FADD
705 0U, // G_VECREDUCE_SEQ_FMUL
706 0U, // G_VECREDUCE_FADD
707 0U, // G_VECREDUCE_FMUL
708 0U, // G_VECREDUCE_FMAX
709 0U, // G_VECREDUCE_FMIN
710 0U, // G_VECREDUCE_FMAXIMUM
711 0U, // G_VECREDUCE_FMINIMUM
712 0U, // G_VECREDUCE_ADD
713 0U, // G_VECREDUCE_MUL
714 0U, // G_VECREDUCE_AND
715 0U, // G_VECREDUCE_OR
716 0U, // G_VECREDUCE_XOR
717 0U, // G_VECREDUCE_SMAX
718 0U, // G_VECREDUCE_SMIN
719 0U, // G_VECREDUCE_UMAX
720 0U, // G_VECREDUCE_UMIN
721 0U, // G_SBFX
722 0U, // G_UBFX
723 4707U, // ADJCALLSTACKDOWN
724 70262U, // ADJCALLSTACKUP
725 8206U, // GETPCX
726 2316U, // SELECT_CC_DFP_FCC
727 2427U, // SELECT_CC_DFP_ICC
728 2538U, // SELECT_CC_DFP_XCC
729 2372U, // SELECT_CC_FP_FCC
730 2483U, // SELECT_CC_FP_ICC
731 2594U, // SELECT_CC_FP_XCC
732 2399U, // SELECT_CC_Int_FCC
733 2510U, // SELECT_CC_Int_ICC
734 2621U, // SELECT_CC_Int_XCC
735 2344U, // SELECT_CC_QFP_FCC
736 2455U, // SELECT_CC_QFP_ICC
737 2566U, // SELECT_CC_QFP_XCC
738 2111555U, // SET
739 2111634U, // SETSW
740 20986099U, // SETX
741 2947U, // V8BAR
742 20984555U, // ADDCCri
743 20984555U, // ADDCCrr
744 20986034U, // ADDCri
745 20986034U, // ADDCrr
746 20984647U, // ADDEri
747 20984647U, // ADDErr
748 20984661U, // ADDXC
749 20984545U, // ADDXCCC
750 20984700U, // ADDri
751 20984700U, // ADDrr
752 692072546U, // AES_DROUND01
753 692073745U, // AES_DROUND01_LAST
754 692072794U, // AES_DROUND23
755 692073777U, // AES_DROUND23_LAST
756 692072560U, // AES_EROUND01
757 692073761U, // AES_EROUND01_LAST
758 692072808U, // AES_EROUND23
759 692073793U, // AES_EROUND23_LAST
760 20983892U, // AES_KEXPAND0
761 692072581U, // AES_KEXPAND1
762 20984114U, // AES_KEXPAND2
763 20985493U, // ALIGNADDR
764 20985211U, // ALIGNADDRL
765 3298U, // ALLCLEAN
766 20984562U, // ANDCCri
767 20984562U, // ANDCCrr
768 20984585U, // ANDNCCri
769 20984585U, // ANDNCCrr
770 20985288U, // ANDNri
771 20985288U, // ANDNrr
772 20984802U, // ANDri
773 20984802U, // ANDrr
774 20984387U, // ARRAY16
775 20984098U, // ARRAY32
776 20984411U, // ARRAY8
777 82569U, // BA
778 6446246U, // BCOND
779 6511782U, // BCONDA
780 91671U, // BINDri
781 91671U, // BINDrr
782 20985072U, // BMASK
783 289561768U, // BPFCC
784 289627304U, // BPFCCA
785 285864U, // BPFCCANT
786 351400U, // BPFCCNT
787 6708390U, // BPICC
788 482470U, // BPICCA
789 548006U, // BPICCANT
790 613542U, // BPICCNT
791 289561867U, // BPR
792 289627403U, // BPRA
793 285963U, // BPRANT
794 351499U, // BPRNT
795 6970534U, // BPXCC
796 744614U, // BPXCCA
797 810150U, // BPXCCANT
798 875686U, // BPXCCNT
799 20984946U, // BSHUFFLE
800 83306U, // CALL
801 17770U, // CALLi
802 91498U, // CALLri
803 4220266U, // CALLrii
804 91498U, // CALLrr
805 4220266U, // CALLrri
806 692073617U, // CAMELLIA_F
807 20985181U, // CAMELLIA_FL
808 20985037U, // CAMELLIA_FLI
809 21904434U, // CASAri
810 9387058U, // CASArr
811 21904456U, // CASXAri
812 9387080U, // CASXArr
813 70078U, // CMASK16
814 69868U, // CMASK32
815 70227U, // CMASK8
816 6446245U, // CPBCOND
817 6511781U, // CPBCONDA
818 20984517U, // CRC32C
819 1765956779U, // CWBCONDri
820 1765956779U, // CWBCONDrr
821 1765956783U, // CXBCONDri
822 1765956783U, // CXBCONDrr
823 2110983U, // DES_IIP
824 2110975U, // DES_IP
825 20984823U, // DES_KEXPAND
826 692073476U, // DES_ROUND
827 3279U, // DONE
828 20984217U, // EDGE16
829 20985088U, // EDGE16L
830 20985304U, // EDGE16LN
831 20985271U, // EDGE16N
832 20984007U, // EDGE32
833 20985079U, // EDGE32L
834 20985294U, // EDGE32LN
835 20985262U, // EDGE32N
836 20984396U, // EDGE8
837 20985097U, // EDGE8L
838 20985314U, // EDGE8LN
839 20985280U, // EDGE8N
840 2110535U, // FABSD
841 2111083U, // FABSQ
842 2111526U, // FABSS
843 20984705U, // FADDD
844 20985379U, // FADDQ
845 20985705U, // FADDS
846 20984484U, // FALIGNADATA
847 20984801U, // FAND
848 20983955U, // FANDNOT1
849 20985567U, // FANDNOT1S
850 20984128U, // FANDNOT2
851 20985624U, // FANDNOT2S
852 20985754U, // FANDS
853 6446248U, // FBCOND
854 6511784U, // FBCONDA
855 1072296U, // FBCONDA_V9
856 7429288U, // FBCOND_V9
857 20984279U, // FCHKSM16
858 5172U, // FCMPD
859 4097U, // FCMPD_V9
860 20984298U, // FCMPEQ16
861 20984069U, // FCMPEQ32
862 20984317U, // FCMPGT16
863 20984088U, // FCMPGT32
864 20984225U, // FCMPLE16
865 20984015U, // FCMPLE32
866 20984235U, // FCMPNE16
867 20984025U, // FCMPNE32
868 5732U, // FCMPQ
869 4111U, // FCMPQ_V9
870 6139U, // FCMPS
871 4125U, // FCMPS_V9
872 20984923U, // FDIVD
873 20985471U, // FDIVQ
874 20985909U, // FDIVS
875 20985401U, // FDMULQ
876 2110683U, // FDTOI
877 2111048U, // FDTOQ
878 2111446U, // FDTOS
879 2111701U, // FDTOX
880 2110446U, // FEXPAND
881 20984712U, // FHADDD
882 20985712U, // FHADDS
883 20984675U, // FHSUBD
884 20985680U, // FHSUBS
885 2110479U, // FITOD
886 2111055U, // FITOQ
887 2111453U, // FITOS
888 419435579U, // FLCMPD
889 419436546U, // FLCMPS
890 2815U, // FLUSH
891 3366U, // FLUSHW
892 91293U, // FLUSHri
893 91293U, // FLUSHrr
894 692073369U, // FMADDD
895 692074369U, // FMADDS
896 20984289U, // FMEAN16
897 2110562U, // FMOVD
898 17923273U, // FMOVD_FCC
899 17202377U, // FMOVD_ICC
900 17464521U, // FMOVD_XCC
901 2111110U, // FMOVQ
902 17923327U, // FMOVQ_FCC
903 17202431U, // FMOVQ_ICC
904 17464575U, // FMOVQ_XCC
905 36034U, // FMOVRD
906 36088U, // FMOVRQ
907 36115U, // FMOVRS
908 2111548U, // FMOVS
909 17923354U, // FMOVS_FCC
910 17202458U, // FMOVS_ICC
911 17464602U, // FMOVS_XCC
912 692073323U, // FMSUBD
913 692074328U, // FMSUBS
914 20984375U, // FMUL8SUX16
915 20984350U, // FMUL8ULX16
916 20984327U, // FMUL8X16
917 20985169U, // FMUL8X16AL
918 20985948U, // FMUL8X16AU
919 20984769U, // FMULD
920 20984362U, // FMULD8SUX16
921 20984337U, // FMULD8ULX16
922 20985409U, // FMULQ
923 20985791U, // FMULS
924 20984746U, // FNADDD
925 20985746U, // FNADDS
926 20984807U, // FNAND
927 20985761U, // FNANDS
928 2110394U, // FNEGD
929 2111026U, // FNEGQ
930 2111416U, // FNEGS
931 20984720U, // FNHADDD
932 20985720U, // FNHADDS
933 692073377U, // FNMADDD
934 692074377U, // FNMADDS
935 692073331U, // FNMSUBD
936 692074336U, // FNMSUBS
937 20984776U, // FNMULD
938 20985798U, // FNMULS
939 20985514U, // FNOR
940 20985872U, // FNORS
941 2109597U, // FNOT1
942 2111210U, // FNOT1S
943 2109770U, // FNOT2
944 2111267U, // FNOT2S
945 20984792U, // FNSMULD
946 70780U, // FONE
947 71593U, // FONES
948 20985509U, // FOR
949 20983972U, // FORNOT1
950 20985586U, // FORNOT1S
951 20984145U, // FORNOT2
952 20985643U, // FORNOT2S
953 20985866U, // FORS
954 2109877U, // FPACK16
955 20984035U, // FPACK32
956 2111672U, // FPACKFIX
957 20984208U, // FPADD16
958 20985663U, // FPADD16S
959 20983998U, // FPADD32
960 20985606U, // FPADD32S
961 20984182U, // FPADD64
962 692074671U, // FPMADDX
963 692073648U, // FPMADDXHI
964 20984937U, // FPMERGE
965 20984199U, // FPSUB16
966 20985653U, // FPSUB16S
967 20983989U, // FPSUB32
968 20985596U, // FPSUB32S
969 2110486U, // FQTOD
970 2110690U, // FQTOI
971 2111460U, // FQTOS
972 2111717U, // FQTOX
973 20984308U, // FSLAS16
974 20984079U, // FSLAS32
975 20984263U, // FSLL16
976 20984053U, // FSLL32
977 20984784U, // FSMULD
978 2110542U, // FSQRTD
979 2111090U, // FSQRTQ
980 2111533U, // FSQRTS
981 20984191U, // FSRA16
982 20983981U, // FSRA32
983 2109566U, // FSRC1
984 2111191U, // FSRC1S
985 2109739U, // FSRC2
986 2111248U, // FSRC2S
987 20984271U, // FSRL16
988 20984061U, // FSRL32
989 2110493U, // FSTOD
990 2110697U, // FSTOI
991 2111062U, // FSTOQ
992 2111724U, // FSTOX
993 20984668U, // FSUBD
994 20985372U, // FSUBQ
995 20985673U, // FSUBS
996 20985520U, // FXNOR
997 20985879U, // FXNORS
998 20985527U, // FXOR
999 20985887U, // FXORS
1000 2110500U, // FXTOD
1001 2111069U, // FXTOQ
1002 2111476U, // FXTOS
1003 71160U, // FZERO
1004 71630U, // FZEROS
1005 154311839U, // GDOP_LDXrr
1006 154311789U, // GDOP_LDrr
1007 3381U, // INVALW
1008 2135413U, // JMPLri
1009 2135413U, // JMPLrr
1010 3054593U, // LDAri
1011 28285953U, // LDArr
1012 1272941U, // LDCSRri
1013 1272941U, // LDCSRrr
1014 3316845U, // LDCri
1015 3316845U, // LDCrr
1016 3054586U, // LDDAri
1017 28285946U, // LDDArr
1018 3316839U, // LDDCri
1019 3316839U, // LDDCrr
1020 3054586U, // LDDFAri
1021 28285946U, // LDDFArr
1022 3316839U, // LDDFri
1023 3316839U, // LDDFrr
1024 3316839U, // LDDri
1025 3316839U, // LDDrr
1026 3054593U, // LDFAri
1027 28285953U, // LDFArr
1028 1338477U, // LDFSRri
1029 1338477U, // LDFSRrr
1030 3316845U, // LDFri
1031 3316845U, // LDFrr
1032 3054635U, // LDQFAri
1033 28285995U, // LDQFArr
1034 3316882U, // LDQFri
1035 3316882U, // LDQFrr
1036 3054560U, // LDSBAri
1037 28285920U, // LDSBArr
1038 3316816U, // LDSBri
1039 3316816U, // LDSBrr
1040 3054611U, // LDSHAri
1041 28285971U, // LDSHArr
1042 3316861U, // LDSHri
1043 3316861U, // LDSHrr
1044 3054576U, // LDSTUBAri
1045 28285936U, // LDSTUBArr
1046 3316830U, // LDSTUBri
1047 3316830U, // LDSTUBrr
1048 3054649U, // LDSWAri
1049 28286009U, // LDSWArr
1050 3316888U, // LDSWri
1051 3316888U, // LDSWrr
1052 3054568U, // LDUBAri
1053 28285928U, // LDUBArr
1054 3316823U, // LDUBri
1055 3316823U, // LDUBrr
1056 3054619U, // LDUHAri
1057 28285979U, // LDUHArr
1058 3316868U, // LDUHri
1059 3316868U, // LDUHrr
1060 3054657U, // LDXAri
1061 28286017U, // LDXArr
1062 1338527U, // LDXFSRri
1063 1338527U, // LDXFSRrr
1064 3316895U, // LDXri
1065 3316895U, // LDXrr
1066 3316845U, // LDri
1067 3316845U, // LDrr
1068 2111560U, // LZCNT
1069 2852U, // MD5
1070 42637U, // MEMBARi
1071 71065U, // MONTMUL
1072 71369U, // MONTSQR
1073 2111708U, // MOVDTOX
1074 17923362U, // MOVFCCri
1075 17923362U, // MOVFCCrr
1076 17202466U, // MOVICCri
1077 17202466U, // MOVICCrr
1078 36110U, // MOVRri
1079 36110U, // MOVRrr
1080 2111624U, // MOVSTOSW
1081 2111641U, // MOVSTOUW
1082 2111467U, // MOVWTOS
1083 17464610U, // MOVXCCri
1084 17464610U, // MOVXCCrr
1085 2110507U, // MOVXTOD
1086 71052U, // MPMUL
1087 20984615U, // MULSCCri
1088 20984615U, // MULSCCrr
1089 20986063U, // MULXri
1090 20986063U, // MULXrr
1091 3316U, // NOP
1092 3373U, // NORMALW
1093 20984602U, // ORCCri
1094 20984602U, // ORCCrr
1095 20984593U, // ORNCCri
1096 20984593U, // ORNCCrr
1097 20985323U, // ORNri
1098 20985323U, // ORNrr
1099 20985510U, // ORri
1100 20985510U, // ORrr
1101 3388U, // OTHERW
1102 20985935U, // PDIST
1103 20985328U, // PDISTN
1104 2110287U, // POPCrr
1105 13528071U, // PREFETCHAi
1106 15690759U, // PREFETCHAr
1107 13790322U, // PREFETCHi
1108 13790322U, // PREFETCHr
1109 33560274U, // PWRPSRri
1110 33560274U, // PWRPSRrr
1111 2110531U, // RDASR
1112 69685U, // RDFQ
1113 2111165U, // RDPR
1114 69706U, // RDPSR
1115 69696U, // RDTBR
1116 69675U, // RDWIM
1117 3251U, // RESTORED
1118 20984962U, // RESTOREri
1119 20984962U, // RESTORErr
1120 72281U, // RET
1121 72290U, // RETL
1122 3395U, // RETRY
1123 92246U, // RETTri
1124 92246U, // RETTrr
1125 3260U, // SAVED
1126 20984971U, // SAVEri
1127 20984971U, // SAVErr
1128 20984623U, // SDIVCCri
1129 20984623U, // SDIVCCrr
1130 20986110U, // SDIVXri
1131 20986110U, // SDIVXrr
1132 20985960U, // SDIVri
1133 20985960U, // SDIVrr
1134 2110633U, // SETHIi
1135 2830U, // SHA1
1136 2856U, // SHA256
1137 2835U, // SHA512
1138 3307U, // SHUTDOWN
1139 71080U, // SIAM
1140 71328U, // SIR
1141 20986050U, // SLLXri
1142 20986050U, // SLLXrr
1143 20985200U, // SLLri
1144 20985200U, // SLLrr
1145 20984525U, // SMACri
1146 20984525U, // SMACrr
1147 20984569U, // SMULCCri
1148 20984569U, // SMULCCrr
1149 20985235U, // SMULri
1150 20985235U, // SMULrr
1151 20986019U, // SRAXri
1152 20986019U, // SRAXrr
1153 20984479U, // SRAri
1154 20984479U, // SRArr
1155 20986056U, // SRLXri
1156 20986056U, // SRLXrr
1157 20985223U, // SRLri
1158 20985223U, // SRLrr
1159 1422000U, // STAri
1160 11514544U, // STArr
1161 3333U, // STBAR
1162 1421959U, // STBAri
1163 11514503U, // STBArr
1164 1487547U, // STBri
1165 1487547U, // STBrr
1166 1469374U, // STCSRri
1167 1469374U, // STCSRrr
1168 1488978U, // STCri
1169 1488978U, // STCrr
1170 1421965U, // STDAri
1171 11514509U, // STDArr
1172 1469352U, // STDCQri
1173 1469352U, // STDCQrr
1174 1487958U, // STDCri
1175 1487958U, // STDCrr
1176 1421965U, // STDFAri
1177 11514509U, // STDFArr
1178 1469363U, // STDFQri
1179 1469363U, // STDFQrr
1180 1487958U, // STDFri
1181 1487958U, // STDFrr
1182 1487958U, // STDri
1183 1487958U, // STDrr
1184 1422000U, // STFAri
1185 11514544U, // STFArr
1186 1469385U, // STFSRri
1187 1469385U, // STFSRrr
1188 1488978U, // STFri
1189 1488978U, // STFrr
1190 1421971U, // STHAri
1191 11514515U, // STHArr
1192 1488036U, // STHri
1193 1488036U, // STHrr
1194 1421977U, // STQFAri
1195 11514521U, // STQFArr
1196 1488506U, // STQFri
1197 1488506U, // STQFrr
1198 1422005U, // STXAri
1199 11514549U, // STXArr
1200 1469396U, // STXFSRri
1201 1469396U, // STXFSRrr
1202 1489145U, // STXri
1203 1489145U, // STXrr
1204 1488978U, // STri
1205 1488978U, // STrr
1206 20984538U, // SUBCCri
1207 20984538U, // SUBCCrr
1208 20986025U, // SUBCri
1209 20986025U, // SUBCrr
1210 20984639U, // SUBEri
1211 20984639U, // SUBErr
1212 20984512U, // SUBri
1213 20984512U, // SUBrr
1214 3054627U, // SWAPAri
1215 28285987U, // SWAPArr
1216 3316875U, // SWAPri
1217 3316875U, // SWAPrr
1218 2825U, // TA1
1219 2842U, // TA3
1220 2847U, // TA5
1221 20985982U, // TADDCCTVri
1222 20985982U, // TADDCCTVrr
1223 20984554U, // TADDCCri
1224 20984554U, // TADDCCrr
1225 83306U, // TAIL_CALL
1226 91671U, // TAIL_CALLri
1227 52874528U, // TICCri
1228 52874528U, // TICCrr
1229 2705339260U, // TLS_ADDrr
1230 17770U, // TLS_CALL
1231 154311839U, // TLS_LDXrr
1232 154311789U, // TLS_LDrr
1233 52612384U, // TRAPri
1234 52612384U, // TRAPrr
1235 20985972U, // TSUBCCTVri
1236 20985972U, // TSUBCCTVrr
1237 20984537U, // TSUBCCri
1238 20984537U, // TSUBCCrr
1239 53136672U, // TXCCri
1240 53136672U, // TXCCrr
1241 20984631U, // UDIVCCri
1242 20984631U, // UDIVCCrr
1243 20986117U, // UDIVXri
1244 20986117U, // UDIVXrr
1245 20985966U, // UDIVri
1246 20985966U, // UDIVrr
1247 20984531U, // UMACri
1248 20984531U, // UMACrr
1249 20984577U, // UMULCCri
1250 20984577U, // UMULCCrr
1251 20985019U, // UMULXHI
1252 20985250U, // UMULri
1253 20985250U, // UMULrr
1254 71184U, // UNIMP
1255 419435572U, // V9FCMPD
1256 419435442U, // V9FCMPED
1257 419436074U, // V9FCMPEQ
1258 419436464U, // V9FCMPES
1259 419436132U, // V9FCMPQ
1260 419436539U, // V9FCMPS
1261 36041U, // V9FMOVD_FCC
1262 36095U, // V9FMOVQ_FCC
1263 36122U, // V9FMOVS_FCC
1264 36130U, // V9MOVFCCri
1265 36130U, // V9MOVFCCrr
1266 20985555U, // WRASRri
1267 20985555U, // WRASRrr
1268 20985539U, // WRPRri
1269 20985539U, // WRPRrr
1270 33560275U, // WRPSRri
1271 33560275U, // WRPSRrr
1272 67114707U, // WRTBRri
1273 67114707U, // WRTBRrr
1274 83891923U, // WRWIMri
1275 83891923U, // WRWIMrr
1276 20986062U, // XMULX
1277 20985028U, // XMULXHI
1278 20984600U, // XNORCCri
1279 20984600U, // XNORCCrr
1280 20985521U, // XNORri
1281 20985521U, // XNORrr
1282 20984608U, // XORCCri
1283 20984608U, // XORCCrr
1284 20985528U, // XORri
1285 20985528U, // XORrr
1286 };
1287
1288 // Emit the opcode for the instruction.
1289 uint32_t Bits = 0;
1290 Bits |= OpInfo0[MI.getOpcode()] << 0;
1291 if (Bits == 0)
1292 return {nullptr, Bits};
1293 return {AsmStrs+(Bits & 4095)-1, Bits};
1294
1295}
1296/// printInstruction - This method is automatically generated by tablegen
1297/// from the instruction set description.
1298LLVM_NO_PROFILE_INSTRUMENT_FUNCTION
1299void SparcInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) {
1300 O << "\t";
1301
1302 auto MnemonicInfo = getMnemonic(MI: *MI);
1303
1304 O << MnemonicInfo.first;
1305
1306 uint32_t Bits = MnemonicInfo.second;
1307 assert(Bits != 0 && "Cannot print this instruction.");
1308
1309 // Fragment 0 encoded into 4 bits for 13 unique commands.
1310 switch ((Bits >> 12) & 15) {
1311 default: llvm_unreachable("Invalid command number.");
1312 case 0:
1313 // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
1314 return;
1315 break;
1316 case 1:
1317 // ADJCALLSTACKDOWN, ADJCALLSTACKUP, CMASK16, CMASK32, CMASK8, FCMPD, FCM...
1318 printOperand(MI, opNum: 0, STI, OS&: O);
1319 break;
1320 case 2:
1321 // GETPCX
1322 printGetPCX(MI, OpNo: 0, STI, OS&: O);
1323 return;
1324 break;
1325 case 3:
1326 // SET, SETSW, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, AD...
1327 printOperand(MI, opNum: 1, STI, OS&: O);
1328 break;
1329 case 4:
1330 // BA, CALL, CALLi, TAIL_CALL, TLS_CALL
1331 printCTILabel(MI, Address, OpNum: 0, STI, O);
1332 break;
1333 case 5:
1334 // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
1335 printCCOperand(MI, opNum: 1, STI, OS&: O);
1336 break;
1337 case 6:
1338 // BINDri, BINDrr, CALLri, CALLrii, CALLrr, CALLrri, FLUSHri, FLUSHrr, LD...
1339 printMemOperand(MI, opNum: 0, STI, OS&: O);
1340 break;
1341 case 7:
1342 // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
1343 printCCOperand(MI, opNum: 3, STI, OS&: O);
1344 break;
1345 case 8:
1346 // FMOVRD, FMOVRQ, FMOVRS, MOVRri, MOVRrr, V9FMOVD_FCC, V9FMOVQ_FCC, V9FM...
1347 printCCOperand(MI, opNum: 4, STI, OS&: O);
1348 O << ' ';
1349 printOperand(MI, opNum: 1, STI, OS&: O);
1350 O << ", ";
1351 printOperand(MI, opNum: 2, STI, OS&: O);
1352 O << ", ";
1353 printOperand(MI, opNum: 0, STI, OS&: O);
1354 return;
1355 break;
1356 case 9:
1357 // GDOP_LDXrr, GDOP_LDrr, JMPLri, JMPLrr, LDAri, LDArr, LDCri, LDCrr, LDD...
1358 printMemOperand(MI, opNum: 1, STI, OS&: O);
1359 break;
1360 case 10:
1361 // MEMBARi
1362 printMembarTag(MI, opNum: 0, STI, O);
1363 return;
1364 break;
1365 case 11:
1366 // STAri, STArr, STBAri, STBArr, STBri, STBrr, STCri, STCrr, STDAri, STDA...
1367 printOperand(MI, opNum: 2, STI, OS&: O);
1368 O << ", [";
1369 printMemOperand(MI, opNum: 0, STI, OS&: O);
1370 break;
1371 case 12:
1372 // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr
1373 printCCOperand(MI, opNum: 2, STI, OS&: O);
1374 break;
1375 }
1376
1377
1378 // Fragment 1 encoded into 5 bits for 23 unique commands.
1379 switch ((Bits >> 16) & 31) {
1380 default: llvm_unreachable("Invalid command number.");
1381 case 0:
1382 // ADJCALLSTACKDOWN, SET, SETSW, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ...
1383 O << ", ";
1384 break;
1385 case 1:
1386 // ADJCALLSTACKUP, BA, BINDri, BINDrr, CALL, CALLri, CALLrr, CMASK16, CMA...
1387 return;
1388 break;
1389 case 2:
1390 // BCOND, BPFCC, BPR, CPBCOND, CWBCONDri, CWBCONDrr, CXBCONDri, CXBCONDrr...
1391 O << ' ';
1392 break;
1393 case 3:
1394 // BCONDA, BPFCCA, BPRA, CPBCONDA, FBCONDA
1395 O << ",a ";
1396 break;
1397 case 4:
1398 // BPFCCANT, BPRANT
1399 O << ",a,pn ";
1400 printOperand(MI, opNum: 2, STI, OS&: O);
1401 O << ", ";
1402 printCTILabel(MI, Address, OpNum: 0, STI, O);
1403 return;
1404 break;
1405 case 5:
1406 // BPFCCNT, BPRNT
1407 O << ",pn ";
1408 printOperand(MI, opNum: 2, STI, OS&: O);
1409 O << ", ";
1410 printCTILabel(MI, Address, OpNum: 0, STI, O);
1411 return;
1412 break;
1413 case 6:
1414 // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
1415 O << " %icc, ";
1416 break;
1417 case 7:
1418 // BPICCA
1419 O << ",a %icc, ";
1420 printCTILabel(MI, Address, OpNum: 0, STI, O);
1421 return;
1422 break;
1423 case 8:
1424 // BPICCANT
1425 O << ",a,pn %icc, ";
1426 printCTILabel(MI, Address, OpNum: 0, STI, O);
1427 return;
1428 break;
1429 case 9:
1430 // BPICCNT
1431 O << ",pn %icc, ";
1432 printCTILabel(MI, Address, OpNum: 0, STI, O);
1433 return;
1434 break;
1435 case 10:
1436 // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
1437 O << " %xcc, ";
1438 break;
1439 case 11:
1440 // BPXCCA
1441 O << ",a %xcc, ";
1442 printCTILabel(MI, Address, OpNum: 0, STI, O);
1443 return;
1444 break;
1445 case 12:
1446 // BPXCCANT
1447 O << ",a,pn %xcc, ";
1448 printCTILabel(MI, Address, OpNum: 0, STI, O);
1449 return;
1450 break;
1451 case 13:
1452 // BPXCCNT
1453 O << ",pn %xcc, ";
1454 printCTILabel(MI, Address, OpNum: 0, STI, O);
1455 return;
1456 break;
1457 case 14:
1458 // CASAri, CASXAri, LDAri, LDDAri, LDDFAri, LDFAri, LDQFAri, LDSBAri, LDS...
1459 O << "] %asi, ";
1460 break;
1461 case 15:
1462 // CASArr, CASXArr, LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDS...
1463 O << "] ";
1464 break;
1465 case 16:
1466 // FBCONDA_V9
1467 O << ",a %fcc0, ";
1468 printCTILabel(MI, Address, OpNum: 0, STI, O);
1469 return;
1470 break;
1471 case 17:
1472 // FBCOND_V9, FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1473 O << " %fcc0, ";
1474 break;
1475 case 18:
1476 // GDOP_LDXrr, GDOP_LDrr, LDCri, LDCrr, LDDCri, LDDCrr, LDDFri, LDDFrr, L...
1477 O << "], ";
1478 break;
1479 case 19:
1480 // LDCSRri, LDCSRrr
1481 O << "], %csr";
1482 return;
1483 break;
1484 case 20:
1485 // LDFSRri, LDFSRrr, LDXFSRri, LDXFSRrr
1486 O << "], %fsr";
1487 return;
1488 break;
1489 case 21:
1490 // STAri, STBAri, STDAri, STDFAri, STFAri, STHAri, STQFAri, STXAri
1491 O << "] %asi";
1492 return;
1493 break;
1494 case 22:
1495 // STBri, STBrr, STCSRri, STCSRrr, STCri, STCrr, STDCQri, STDCQrr, STDCri...
1496 O << ']';
1497 return;
1498 break;
1499 }
1500
1501
1502 // Fragment 2 encoded into 3 bits for 8 unique commands.
1503 switch ((Bits >> 21) & 7) {
1504 default: llvm_unreachable("Invalid command number.");
1505 case 0:
1506 // ADJCALLSTACKDOWN, CALLi, FCMPD, FCMPD_V9, FCMPQ, FCMPQ_V9, FCMPS, FCMP...
1507 printOperand(MI, opNum: 1, STI, OS&: O);
1508 break;
1509 case 1:
1510 // SET, SETSW, DES_IIP, DES_IP, FABSD, FABSQ, FABSS, FDTOI, FDTOQ, FDTOS,...
1511 printOperand(MI, opNum: 0, STI, OS&: O);
1512 break;
1513 case 2:
1514 // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1515 printOperand(MI, opNum: 2, STI, OS&: O);
1516 break;
1517 case 3:
1518 // BCOND, BCONDA, BPICC, BPXCC, CPBCOND, CPBCONDA, FBCOND, FBCONDA, FBCON...
1519 printCTILabel(MI, Address, OpNum: 0, STI, O);
1520 return;
1521 break;
1522 case 4:
1523 // CASArr, CASXArr
1524 printASITag(MI, opNum: 4, STI, O);
1525 O << ", ";
1526 printOperand(MI, opNum: 2, STI, OS&: O);
1527 O << ", ";
1528 printOperand(MI, opNum: 0, STI, OS&: O);
1529 return;
1530 break;
1531 case 5:
1532 // LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDSHArr, LDSTUBArr, ...
1533 printASITag(MI, opNum: 3, STI, O);
1534 break;
1535 case 6:
1536 // PREFETCHAi, PREFETCHi, PREFETCHr
1537 printPrefetchTag(MI, opNum: 2, STI, O);
1538 return;
1539 break;
1540 case 7:
1541 // PREFETCHAr
1542 printASITag(MI, opNum: 2, STI, O);
1543 O << ", ";
1544 printPrefetchTag(MI, opNum: 3, STI, O);
1545 return;
1546 break;
1547 }
1548
1549
1550 // Fragment 3 encoded into 3 bits for 6 unique commands.
1551 switch ((Bits >> 24) & 7) {
1552 default: llvm_unreachable("Invalid command number.");
1553 case 0:
1554 // ADJCALLSTACKDOWN, SET, SETSW, CALLi, CALLrii, CALLrri, DES_IIP, DES_IP...
1555 return;
1556 break;
1557 case 1:
1558 // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1559 O << ", ";
1560 break;
1561 case 2:
1562 // PWRPSRri, PWRPSRrr, WRPSRri, WRPSRrr
1563 O << ", %psr";
1564 return;
1565 break;
1566 case 3:
1567 // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr
1568 O << " + ";
1569 printOperand(MI, opNum: 1, STI, OS&: O);
1570 return;
1571 break;
1572 case 4:
1573 // WRTBRri, WRTBRrr
1574 O << ", %tbr";
1575 return;
1576 break;
1577 case 5:
1578 // WRWIMri, WRWIMrr
1579 O << ", %wim";
1580 return;
1581 break;
1582 }
1583
1584
1585 // Fragment 4 encoded into 2 bits for 4 unique commands.
1586 switch ((Bits >> 27) & 3) {
1587 default: llvm_unreachable("Invalid command number.");
1588 case 0:
1589 // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1590 printOperand(MI, opNum: 0, STI, OS&: O);
1591 break;
1592 case 1:
1593 // AES_DROUND01, AES_DROUND01_LAST, AES_DROUND23, AES_DROUND23_LAST, AES_...
1594 printOperand(MI, opNum: 3, STI, OS&: O);
1595 break;
1596 case 2:
1597 // BPFCC, BPFCCA, BPR, BPRA
1598 printCTILabel(MI, Address, OpNum: 0, STI, O);
1599 return;
1600 break;
1601 case 3:
1602 // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1603 printOperand(MI, opNum: 2, STI, OS&: O);
1604 return;
1605 break;
1606 }
1607
1608
1609 // Fragment 5 encoded into 1 bits for 2 unique commands.
1610 if ((Bits >> 29) & 1) {
1611 // AES_DROUND01, AES_DROUND01_LAST, AES_DROUND23, AES_DROUND23_LAST, AES_...
1612 O << ", ";
1613 } else {
1614 // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1615 return;
1616 }
1617
1618
1619 // Fragment 6 encoded into 2 bits for 3 unique commands.
1620 switch ((Bits >> 30) & 3) {
1621 default: llvm_unreachable("Invalid command number.");
1622 case 0:
1623 // AES_DROUND01, AES_DROUND01_LAST, AES_DROUND23, AES_DROUND23_LAST, AES_...
1624 printOperand(MI, opNum: 0, STI, OS&: O);
1625 return;
1626 break;
1627 case 1:
1628 // CWBCONDri, CWBCONDrr, CXBCONDri, CXBCONDrr
1629 printCTILabel(MI, Address, OpNum: 0, STI, O);
1630 return;
1631 break;
1632 case 2:
1633 // TLS_ADDrr
1634 printOperand(MI, opNum: 3, STI, OS&: O);
1635 return;
1636 break;
1637 }
1638
1639}
1640
1641
1642/// getRegisterName - This method is automatically generated by tblgen
1643/// from the register set description. This returns the assembler name
1644/// for the specified register.
1645const char *SparcInstPrinter::
1646getRegisterName(MCRegister Reg, unsigned AltIdx) {
1647 unsigned RegNo = Reg.id();
1648 assert(RegNo && RegNo < 238 && "Invalid register number!");
1649
1650
1651#ifdef __GNUC__
1652#pragma GCC diagnostic push
1653#pragma GCC diagnostic ignored "-Woverlength-strings"
1654#endif
1655 static const char AsmStrsNoRegAltName[] = {
1656 /* 0 */ "c10\000"
1657 /* 4 */ "f10\000"
1658 /* 8 */ "asr10\000"
1659 /* 14 */ "c20\000"
1660 /* 18 */ "f20\000"
1661 /* 22 */ "asr20\000"
1662 /* 28 */ "c30\000"
1663 /* 32 */ "f30\000"
1664 /* 36 */ "asr30\000"
1665 /* 42 */ "f40\000"
1666 /* 46 */ "f50\000"
1667 /* 50 */ "f60\000"
1668 /* 54 */ "fcc0\000"
1669 /* 59 */ "f0\000"
1670 /* 62 */ "g0\000"
1671 /* 65 */ "i0\000"
1672 /* 68 */ "l0\000"
1673 /* 71 */ "o0\000"
1674 /* 74 */ "c11\000"
1675 /* 78 */ "f11\000"
1676 /* 82 */ "asr11\000"
1677 /* 88 */ "c21\000"
1678 /* 92 */ "f21\000"
1679 /* 96 */ "asr21\000"
1680 /* 102 */ "c31\000"
1681 /* 106 */ "f31\000"
1682 /* 110 */ "asr31\000"
1683 /* 116 */ "fcc1\000"
1684 /* 121 */ "f1\000"
1685 /* 124 */ "g1\000"
1686 /* 127 */ "i1\000"
1687 /* 130 */ "l1\000"
1688 /* 133 */ "o1\000"
1689 /* 136 */ "asr1\000"
1690 /* 141 */ "c12\000"
1691 /* 145 */ "f12\000"
1692 /* 149 */ "asr12\000"
1693 /* 155 */ "c22\000"
1694 /* 159 */ "f22\000"
1695 /* 163 */ "asr22\000"
1696 /* 169 */ "f32\000"
1697 /* 173 */ "f42\000"
1698 /* 177 */ "f52\000"
1699 /* 181 */ "f62\000"
1700 /* 185 */ "fcc2\000"
1701 /* 190 */ "f2\000"
1702 /* 193 */ "g2\000"
1703 /* 196 */ "i2\000"
1704 /* 199 */ "l2\000"
1705 /* 202 */ "o2\000"
1706 /* 205 */ "asr2\000"
1707 /* 210 */ "c13\000"
1708 /* 214 */ "f13\000"
1709 /* 218 */ "asr13\000"
1710 /* 224 */ "c23\000"
1711 /* 228 */ "f23\000"
1712 /* 232 */ "asr23\000"
1713 /* 238 */ "fcc3\000"
1714 /* 243 */ "f3\000"
1715 /* 246 */ "g3\000"
1716 /* 249 */ "i3\000"
1717 /* 252 */ "l3\000"
1718 /* 255 */ "o3\000"
1719 /* 258 */ "asr3\000"
1720 /* 263 */ "c14\000"
1721 /* 267 */ "f14\000"
1722 /* 271 */ "asr14\000"
1723 /* 277 */ "c24\000"
1724 /* 281 */ "f24\000"
1725 /* 285 */ "asr24\000"
1726 /* 291 */ "f34\000"
1727 /* 295 */ "f44\000"
1728 /* 299 */ "f54\000"
1729 /* 303 */ "c4\000"
1730 /* 306 */ "f4\000"
1731 /* 309 */ "g4\000"
1732 /* 312 */ "i4\000"
1733 /* 315 */ "l4\000"
1734 /* 318 */ "o4\000"
1735 /* 321 */ "asr4\000"
1736 /* 326 */ "c15\000"
1737 /* 330 */ "f15\000"
1738 /* 334 */ "asr15\000"
1739 /* 340 */ "c25\000"
1740 /* 344 */ "f25\000"
1741 /* 348 */ "asr25\000"
1742 /* 354 */ "c5\000"
1743 /* 357 */ "f5\000"
1744 /* 360 */ "g5\000"
1745 /* 363 */ "i5\000"
1746 /* 366 */ "l5\000"
1747 /* 369 */ "o5\000"
1748 /* 372 */ "asr5\000"
1749 /* 377 */ "c16\000"
1750 /* 381 */ "f16\000"
1751 /* 385 */ "asr16\000"
1752 /* 391 */ "c26\000"
1753 /* 395 */ "f26\000"
1754 /* 399 */ "asr26\000"
1755 /* 405 */ "f36\000"
1756 /* 409 */ "f46\000"
1757 /* 413 */ "f56\000"
1758 /* 417 */ "c6\000"
1759 /* 420 */ "f6\000"
1760 /* 423 */ "g6\000"
1761 /* 426 */ "i6\000"
1762 /* 429 */ "l6\000"
1763 /* 432 */ "o6\000"
1764 /* 435 */ "asr6\000"
1765 /* 440 */ "c17\000"
1766 /* 444 */ "f17\000"
1767 /* 448 */ "asr17\000"
1768 /* 454 */ "c27\000"
1769 /* 458 */ "f27\000"
1770 /* 462 */ "asr27\000"
1771 /* 468 */ "c7\000"
1772 /* 471 */ "f7\000"
1773 /* 474 */ "g7\000"
1774 /* 477 */ "i7\000"
1775 /* 480 */ "l7\000"
1776 /* 483 */ "o7\000"
1777 /* 486 */ "asr7\000"
1778 /* 491 */ "c18\000"
1779 /* 495 */ "f18\000"
1780 /* 499 */ "asr18\000"
1781 /* 505 */ "c28\000"
1782 /* 509 */ "f28\000"
1783 /* 513 */ "asr28\000"
1784 /* 519 */ "f38\000"
1785 /* 523 */ "f48\000"
1786 /* 527 */ "f58\000"
1787 /* 531 */ "c8\000"
1788 /* 534 */ "f8\000"
1789 /* 537 */ "asr8\000"
1790 /* 542 */ "c19\000"
1791 /* 546 */ "f19\000"
1792 /* 550 */ "asr19\000"
1793 /* 556 */ "c29\000"
1794 /* 560 */ "f29\000"
1795 /* 564 */ "asr29\000"
1796 /* 570 */ "c9\000"
1797 /* 573 */ "f9\000"
1798 /* 576 */ "asr9\000"
1799 /* 581 */ "tba\000"
1800 /* 585 */ "icc\000"
1801 /* 589 */ "tnpc\000"
1802 /* 594 */ "tpc\000"
1803 /* 598 */ "canrestore\000"
1804 /* 609 */ "pstate\000"
1805 /* 616 */ "tstate\000"
1806 /* 623 */ "wstate\000"
1807 /* 630 */ "cansave\000"
1808 /* 638 */ "tick\000"
1809 /* 643 */ "gl\000"
1810 /* 646 */ "pil\000"
1811 /* 650 */ "tl\000"
1812 /* 653 */ "wim\000"
1813 /* 657 */ "cleanwin\000"
1814 /* 666 */ "otherwin\000"
1815 /* 675 */ "fp\000"
1816 /* 678 */ "sp\000"
1817 /* 681 */ "cwp\000"
1818 /* 685 */ "cq\000"
1819 /* 688 */ "fq\000"
1820 /* 691 */ "tbr\000"
1821 /* 695 */ "ver\000"
1822 /* 699 */ "csr\000"
1823 /* 703 */ "fsr\000"
1824 /* 707 */ "psr\000"
1825 /* 711 */ "tt\000"
1826 /* 714 */ "y\000"
1827};
1828#ifdef __GNUC__
1829#pragma GCC diagnostic pop
1830#endif
1831
1832 static const uint16_t RegAsmOffsetNoRegAltName[] = {
1833 598, 630, 657, 685, 699, 681, 688, 703, 643, 585, 666, 646, 707, 609,
1834 581, 691, 638, 650, 589, 594, 616, 711, 695, 653, 623, 714, 136, 205,
1835 258, 321, 372, 435, 486, 537, 576, 8, 82, 149, 218, 271, 334, 385,
1836 448, 499, 550, 22, 96, 163, 232, 285, 348, 399, 462, 513, 564, 36,
1837 110, 56, 118, 187, 240, 303, 354, 417, 468, 531, 570, 0, 74, 141,
1838 210, 263, 326, 377, 440, 491, 542, 14, 88, 155, 224, 277, 340, 391,
1839 454, 505, 556, 28, 102, 59, 190, 306, 420, 534, 4, 145, 267, 381,
1840 495, 18, 159, 281, 395, 509, 32, 169, 291, 405, 519, 42, 173, 295,
1841 409, 523, 46, 177, 299, 413, 527, 50, 181, 59, 121, 190, 243, 306,
1842 357, 420, 471, 534, 573, 4, 78, 145, 214, 267, 330, 381, 444, 495,
1843 546, 18, 92, 159, 228, 281, 344, 395, 458, 509, 560, 32, 106, 54,
1844 116, 185, 238, 62, 124, 193, 246, 309, 360, 423, 474, 65, 127, 196,
1845 249, 312, 363, 675, 477, 68, 130, 199, 252, 315, 366, 429, 480, 71,
1846 133, 202, 255, 318, 369, 678, 483, 59, 306, 534, 145, 381, 18, 281,
1847 509, 169, 405, 42, 295, 523, 177, 413, 50, 56, 187, 303, 417, 531,
1848 0, 141, 263, 377, 491, 14, 155, 277, 391, 505, 28, 62, 193, 309,
1849 423, 65, 196, 312, 426, 68, 199, 315, 429, 71, 202, 318, 432,
1850 };
1851
1852
1853#ifdef __GNUC__
1854#pragma GCC diagnostic push
1855#pragma GCC diagnostic ignored "-Woverlength-strings"
1856#endif
1857 static const char AsmStrsRegNamesStateReg[] = {
1858 /* 0 */ "pc\000"
1859 /* 3 */ "asi\000"
1860 /* 7 */ "tick\000"
1861 /* 12 */ "ccr\000"
1862 /* 16 */ "fprs\000"
1863};
1864#ifdef __GNUC__
1865#pragma GCC diagnostic pop
1866#endif
1867
1868 static const uint8_t RegAsmOffsetRegNamesStateReg[] = {
1869 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1870 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 12,
1871 3, 7, 0, 16, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1872 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1873 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1874 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1875 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1876 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1877 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1878 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1879 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1880 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1881 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1882 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1883 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1884 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1885 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1886 };
1887
1888 switch(AltIdx) {
1889 default: llvm_unreachable("Invalid register alt name index!");
1890 case SP::NoRegAltName:
1891 assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) &&
1892 "Invalid alt name index for register!");
1893 return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
1894 case SP::RegNamesStateReg:
1895 if (!*(AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1]))
1896 return getRegisterName(Reg: RegNo, AltIdx: SP::NoRegAltName);
1897 return AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1];
1898 }
1899}
1900
1901#ifdef PRINT_ALIAS_INSTR
1902#undef PRINT_ALIAS_INSTR
1903
1904bool SparcInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS) {
1905 static const PatternsForOpcode OpToPatterns[] = {
1906 {.Opcode: SP::BCOND, .PatternStart: 0, .NumPatterns: 16 },
1907 {.Opcode: SP::BCONDA, .PatternStart: 16, .NumPatterns: 16 },
1908 {.Opcode: SP::BPFCCANT, .PatternStart: 32, .NumPatterns: 16 },
1909 {.Opcode: SP::BPFCCNT, .PatternStart: 48, .NumPatterns: 16 },
1910 {.Opcode: SP::BPICCANT, .PatternStart: 64, .NumPatterns: 32 },
1911 {.Opcode: SP::BPICCNT, .PatternStart: 96, .NumPatterns: 32 },
1912 {.Opcode: SP::BPRANT, .PatternStart: 128, .NumPatterns: 4 },
1913 {.Opcode: SP::BPRNT, .PatternStart: 132, .NumPatterns: 4 },
1914 {.Opcode: SP::CASArr, .PatternStart: 136, .NumPatterns: 2 },
1915 {.Opcode: SP::CASXArr, .PatternStart: 138, .NumPatterns: 2 },
1916 {.Opcode: SP::CWBCONDri, .PatternStart: 140, .NumPatterns: 14 },
1917 {.Opcode: SP::CWBCONDrr, .PatternStart: 154, .NumPatterns: 14 },
1918 {.Opcode: SP::CXBCONDri, .PatternStart: 168, .NumPatterns: 14 },
1919 {.Opcode: SP::CXBCONDrr, .PatternStart: 182, .NumPatterns: 14 },
1920 {.Opcode: SP::FMOVD_ICC, .PatternStart: 196, .NumPatterns: 32 },
1921 {.Opcode: SP::FMOVQ_ICC, .PatternStart: 228, .NumPatterns: 32 },
1922 {.Opcode: SP::FMOVRD, .PatternStart: 260, .NumPatterns: 4 },
1923 {.Opcode: SP::FMOVRQ, .PatternStart: 264, .NumPatterns: 4 },
1924 {.Opcode: SP::FMOVRS, .PatternStart: 268, .NumPatterns: 4 },
1925 {.Opcode: SP::FMOVS_ICC, .PatternStart: 272, .NumPatterns: 32 },
1926 {.Opcode: SP::MOVICCri, .PatternStart: 304, .NumPatterns: 32 },
1927 {.Opcode: SP::MOVICCrr, .PatternStart: 336, .NumPatterns: 32 },
1928 {.Opcode: SP::MOVRri, .PatternStart: 368, .NumPatterns: 4 },
1929 {.Opcode: SP::MOVRrr, .PatternStart: 372, .NumPatterns: 4 },
1930 {.Opcode: SP::ORCCrr, .PatternStart: 376, .NumPatterns: 1 },
1931 {.Opcode: SP::ORri, .PatternStart: 377, .NumPatterns: 1 },
1932 {.Opcode: SP::ORrr, .PatternStart: 378, .NumPatterns: 1 },
1933 {.Opcode: SP::RESTORErr, .PatternStart: 379, .NumPatterns: 1 },
1934 {.Opcode: SP::RET, .PatternStart: 380, .NumPatterns: 1 },
1935 {.Opcode: SP::RETL, .PatternStart: 381, .NumPatterns: 1 },
1936 {.Opcode: SP::SAVErr, .PatternStart: 382, .NumPatterns: 1 },
1937 {.Opcode: SP::SUBCCri, .PatternStart: 383, .NumPatterns: 1 },
1938 {.Opcode: SP::SUBCCrr, .PatternStart: 384, .NumPatterns: 1 },
1939 {.Opcode: SP::TICCri, .PatternStart: 385, .NumPatterns: 64 },
1940 {.Opcode: SP::TICCrr, .PatternStart: 449, .NumPatterns: 64 },
1941 {.Opcode: SP::TRAPri, .PatternStart: 513, .NumPatterns: 32 },
1942 {.Opcode: SP::TRAPrr, .PatternStart: 545, .NumPatterns: 32 },
1943 {.Opcode: SP::TXCCri, .PatternStart: 577, .NumPatterns: 64 },
1944 {.Opcode: SP::TXCCrr, .PatternStart: 641, .NumPatterns: 64 },
1945 {.Opcode: SP::V9FCMPD, .PatternStart: 705, .NumPatterns: 1 },
1946 {.Opcode: SP::V9FCMPED, .PatternStart: 706, .NumPatterns: 1 },
1947 {.Opcode: SP::V9FCMPEQ, .PatternStart: 707, .NumPatterns: 1 },
1948 {.Opcode: SP::V9FCMPES, .PatternStart: 708, .NumPatterns: 1 },
1949 {.Opcode: SP::V9FCMPQ, .PatternStart: 709, .NumPatterns: 1 },
1950 {.Opcode: SP::V9FCMPS, .PatternStart: 710, .NumPatterns: 1 },
1951 {.Opcode: SP::V9FMOVD_FCC, .PatternStart: 711, .NumPatterns: 16 },
1952 {.Opcode: SP::V9FMOVQ_FCC, .PatternStart: 727, .NumPatterns: 16 },
1953 {.Opcode: SP::V9FMOVS_FCC, .PatternStart: 743, .NumPatterns: 16 },
1954 {.Opcode: SP::V9MOVFCCri, .PatternStart: 759, .NumPatterns: 16 },
1955 {.Opcode: SP::V9MOVFCCrr, .PatternStart: 775, .NumPatterns: 16 },
1956 {.Opcode: SP::WRASRri, .PatternStart: 791, .NumPatterns: 1 },
1957 {.Opcode: SP::WRASRrr, .PatternStart: 792, .NumPatterns: 1 },
1958 };
1959
1960 static const AliasPattern Patterns[] = {
1961 // SP::BCOND - 0
1962 {.AsmStrOffset: 0, .AliasCondStart: 0, .NumOperands: 2, .NumConds: 2 },
1963 {.AsmStrOffset: 8, .AliasCondStart: 2, .NumOperands: 2, .NumConds: 2 },
1964 {.AsmStrOffset: 16, .AliasCondStart: 4, .NumOperands: 2, .NumConds: 2 },
1965 {.AsmStrOffset: 25, .AliasCondStart: 6, .NumOperands: 2, .NumConds: 2 },
1966 {.AsmStrOffset: 33, .AliasCondStart: 8, .NumOperands: 2, .NumConds: 2 },
1967 {.AsmStrOffset: 41, .AliasCondStart: 10, .NumOperands: 2, .NumConds: 2 },
1968 {.AsmStrOffset: 50, .AliasCondStart: 12, .NumOperands: 2, .NumConds: 2 },
1969 {.AsmStrOffset: 59, .AliasCondStart: 14, .NumOperands: 2, .NumConds: 2 },
1970 {.AsmStrOffset: 67, .AliasCondStart: 16, .NumOperands: 2, .NumConds: 2 },
1971 {.AsmStrOffset: 76, .AliasCondStart: 18, .NumOperands: 2, .NumConds: 2 },
1972 {.AsmStrOffset: 86, .AliasCondStart: 20, .NumOperands: 2, .NumConds: 2 },
1973 {.AsmStrOffset: 95, .AliasCondStart: 22, .NumOperands: 2, .NumConds: 2 },
1974 {.AsmStrOffset: 104, .AliasCondStart: 24, .NumOperands: 2, .NumConds: 2 },
1975 {.AsmStrOffset: 114, .AliasCondStart: 26, .NumOperands: 2, .NumConds: 2 },
1976 {.AsmStrOffset: 124, .AliasCondStart: 28, .NumOperands: 2, .NumConds: 2 },
1977 {.AsmStrOffset: 133, .AliasCondStart: 30, .NumOperands: 2, .NumConds: 2 },
1978 // SP::BCONDA - 16
1979 {.AsmStrOffset: 142, .AliasCondStart: 32, .NumOperands: 2, .NumConds: 2 },
1980 {.AsmStrOffset: 152, .AliasCondStart: 34, .NumOperands: 2, .NumConds: 2 },
1981 {.AsmStrOffset: 162, .AliasCondStart: 36, .NumOperands: 2, .NumConds: 2 },
1982 {.AsmStrOffset: 173, .AliasCondStart: 38, .NumOperands: 2, .NumConds: 2 },
1983 {.AsmStrOffset: 183, .AliasCondStart: 40, .NumOperands: 2, .NumConds: 2 },
1984 {.AsmStrOffset: 193, .AliasCondStart: 42, .NumOperands: 2, .NumConds: 2 },
1985 {.AsmStrOffset: 204, .AliasCondStart: 44, .NumOperands: 2, .NumConds: 2 },
1986 {.AsmStrOffset: 215, .AliasCondStart: 46, .NumOperands: 2, .NumConds: 2 },
1987 {.AsmStrOffset: 225, .AliasCondStart: 48, .NumOperands: 2, .NumConds: 2 },
1988 {.AsmStrOffset: 236, .AliasCondStart: 50, .NumOperands: 2, .NumConds: 2 },
1989 {.AsmStrOffset: 248, .AliasCondStart: 52, .NumOperands: 2, .NumConds: 2 },
1990 {.AsmStrOffset: 259, .AliasCondStart: 54, .NumOperands: 2, .NumConds: 2 },
1991 {.AsmStrOffset: 270, .AliasCondStart: 56, .NumOperands: 2, .NumConds: 2 },
1992 {.AsmStrOffset: 282, .AliasCondStart: 58, .NumOperands: 2, .NumConds: 2 },
1993 {.AsmStrOffset: 294, .AliasCondStart: 60, .NumOperands: 2, .NumConds: 2 },
1994 {.AsmStrOffset: 305, .AliasCondStart: 62, .NumOperands: 2, .NumConds: 2 },
1995 // SP::BPFCCANT - 32
1996 {.AsmStrOffset: 316, .AliasCondStart: 64, .NumOperands: 3, .NumConds: 4 },
1997 {.AsmStrOffset: 334, .AliasCondStart: 68, .NumOperands: 3, .NumConds: 4 },
1998 {.AsmStrOffset: 352, .AliasCondStart: 72, .NumOperands: 3, .NumConds: 4 },
1999 {.AsmStrOffset: 370, .AliasCondStart: 76, .NumOperands: 3, .NumConds: 4 },
2000 {.AsmStrOffset: 388, .AliasCondStart: 80, .NumOperands: 3, .NumConds: 4 },
2001 {.AsmStrOffset: 407, .AliasCondStart: 84, .NumOperands: 3, .NumConds: 4 },
2002 {.AsmStrOffset: 425, .AliasCondStart: 88, .NumOperands: 3, .NumConds: 4 },
2003 {.AsmStrOffset: 444, .AliasCondStart: 92, .NumOperands: 3, .NumConds: 4 },
2004 {.AsmStrOffset: 463, .AliasCondStart: 96, .NumOperands: 3, .NumConds: 4 },
2005 {.AsmStrOffset: 482, .AliasCondStart: 100, .NumOperands: 3, .NumConds: 4 },
2006 {.AsmStrOffset: 500, .AliasCondStart: 104, .NumOperands: 3, .NumConds: 4 },
2007 {.AsmStrOffset: 519, .AliasCondStart: 108, .NumOperands: 3, .NumConds: 4 },
2008 {.AsmStrOffset: 538, .AliasCondStart: 112, .NumOperands: 3, .NumConds: 4 },
2009 {.AsmStrOffset: 558, .AliasCondStart: 116, .NumOperands: 3, .NumConds: 4 },
2010 {.AsmStrOffset: 577, .AliasCondStart: 120, .NumOperands: 3, .NumConds: 4 },
2011 {.AsmStrOffset: 597, .AliasCondStart: 124, .NumOperands: 3, .NumConds: 4 },
2012 // SP::BPFCCNT - 48
2013 {.AsmStrOffset: 615, .AliasCondStart: 128, .NumOperands: 3, .NumConds: 4 },
2014 {.AsmStrOffset: 631, .AliasCondStart: 132, .NumOperands: 3, .NumConds: 4 },
2015 {.AsmStrOffset: 647, .AliasCondStart: 136, .NumOperands: 3, .NumConds: 4 },
2016 {.AsmStrOffset: 663, .AliasCondStart: 140, .NumOperands: 3, .NumConds: 4 },
2017 {.AsmStrOffset: 679, .AliasCondStart: 144, .NumOperands: 3, .NumConds: 4 },
2018 {.AsmStrOffset: 696, .AliasCondStart: 148, .NumOperands: 3, .NumConds: 4 },
2019 {.AsmStrOffset: 712, .AliasCondStart: 152, .NumOperands: 3, .NumConds: 4 },
2020 {.AsmStrOffset: 729, .AliasCondStart: 156, .NumOperands: 3, .NumConds: 4 },
2021 {.AsmStrOffset: 746, .AliasCondStart: 160, .NumOperands: 3, .NumConds: 4 },
2022 {.AsmStrOffset: 763, .AliasCondStart: 164, .NumOperands: 3, .NumConds: 4 },
2023 {.AsmStrOffset: 779, .AliasCondStart: 168, .NumOperands: 3, .NumConds: 4 },
2024 {.AsmStrOffset: 796, .AliasCondStart: 172, .NumOperands: 3, .NumConds: 4 },
2025 {.AsmStrOffset: 813, .AliasCondStart: 176, .NumOperands: 3, .NumConds: 4 },
2026 {.AsmStrOffset: 831, .AliasCondStart: 180, .NumOperands: 3, .NumConds: 4 },
2027 {.AsmStrOffset: 848, .AliasCondStart: 184, .NumOperands: 3, .NumConds: 4 },
2028 {.AsmStrOffset: 866, .AliasCondStart: 188, .NumOperands: 3, .NumConds: 4 },
2029 // SP::BPICCANT - 64
2030 {.AsmStrOffset: 882, .AliasCondStart: 192, .NumOperands: 2, .NumConds: 3 },
2031 {.AsmStrOffset: 901, .AliasCondStart: 195, .NumOperands: 2, .NumConds: 4 },
2032 {.AsmStrOffset: 920, .AliasCondStart: 199, .NumOperands: 2, .NumConds: 3 },
2033 {.AsmStrOffset: 939, .AliasCondStart: 202, .NumOperands: 2, .NumConds: 4 },
2034 {.AsmStrOffset: 958, .AliasCondStart: 206, .NumOperands: 2, .NumConds: 3 },
2035 {.AsmStrOffset: 978, .AliasCondStart: 209, .NumOperands: 2, .NumConds: 4 },
2036 {.AsmStrOffset: 998, .AliasCondStart: 213, .NumOperands: 2, .NumConds: 3 },
2037 {.AsmStrOffset: 1017, .AliasCondStart: 216, .NumOperands: 2, .NumConds: 4 },
2038 {.AsmStrOffset: 1036, .AliasCondStart: 220, .NumOperands: 2, .NumConds: 3 },
2039 {.AsmStrOffset: 1055, .AliasCondStart: 223, .NumOperands: 2, .NumConds: 4 },
2040 {.AsmStrOffset: 1074, .AliasCondStart: 227, .NumOperands: 2, .NumConds: 3 },
2041 {.AsmStrOffset: 1094, .AliasCondStart: 230, .NumOperands: 2, .NumConds: 4 },
2042 {.AsmStrOffset: 1114, .AliasCondStart: 234, .NumOperands: 2, .NumConds: 3 },
2043 {.AsmStrOffset: 1134, .AliasCondStart: 237, .NumOperands: 2, .NumConds: 4 },
2044 {.AsmStrOffset: 1154, .AliasCondStart: 241, .NumOperands: 2, .NumConds: 3 },
2045 {.AsmStrOffset: 1173, .AliasCondStart: 244, .NumOperands: 2, .NumConds: 4 },
2046 {.AsmStrOffset: 1192, .AliasCondStart: 248, .NumOperands: 2, .NumConds: 3 },
2047 {.AsmStrOffset: 1212, .AliasCondStart: 251, .NumOperands: 2, .NumConds: 4 },
2048 {.AsmStrOffset: 1232, .AliasCondStart: 255, .NumOperands: 2, .NumConds: 3 },
2049 {.AsmStrOffset: 1253, .AliasCondStart: 258, .NumOperands: 2, .NumConds: 4 },
2050 {.AsmStrOffset: 1274, .AliasCondStart: 262, .NumOperands: 2, .NumConds: 3 },
2051 {.AsmStrOffset: 1294, .AliasCondStart: 265, .NumOperands: 2, .NumConds: 4 },
2052 {.AsmStrOffset: 1314, .AliasCondStart: 269, .NumOperands: 2, .NumConds: 3 },
2053 {.AsmStrOffset: 1334, .AliasCondStart: 272, .NumOperands: 2, .NumConds: 4 },
2054 {.AsmStrOffset: 1354, .AliasCondStart: 276, .NumOperands: 2, .NumConds: 3 },
2055 {.AsmStrOffset: 1375, .AliasCondStart: 279, .NumOperands: 2, .NumConds: 4 },
2056 {.AsmStrOffset: 1396, .AliasCondStart: 283, .NumOperands: 2, .NumConds: 3 },
2057 {.AsmStrOffset: 1417, .AliasCondStart: 286, .NumOperands: 2, .NumConds: 4 },
2058 {.AsmStrOffset: 1438, .AliasCondStart: 290, .NumOperands: 2, .NumConds: 3 },
2059 {.AsmStrOffset: 1458, .AliasCondStart: 293, .NumOperands: 2, .NumConds: 4 },
2060 {.AsmStrOffset: 1478, .AliasCondStart: 297, .NumOperands: 2, .NumConds: 3 },
2061 {.AsmStrOffset: 1498, .AliasCondStart: 300, .NumOperands: 2, .NumConds: 4 },
2062 // SP::BPICCNT - 96
2063 {.AsmStrOffset: 1518, .AliasCondStart: 304, .NumOperands: 2, .NumConds: 3 },
2064 {.AsmStrOffset: 1535, .AliasCondStart: 307, .NumOperands: 2, .NumConds: 4 },
2065 {.AsmStrOffset: 1552, .AliasCondStart: 311, .NumOperands: 2, .NumConds: 3 },
2066 {.AsmStrOffset: 1569, .AliasCondStart: 314, .NumOperands: 2, .NumConds: 4 },
2067 {.AsmStrOffset: 1586, .AliasCondStart: 318, .NumOperands: 2, .NumConds: 3 },
2068 {.AsmStrOffset: 1604, .AliasCondStart: 321, .NumOperands: 2, .NumConds: 4 },
2069 {.AsmStrOffset: 1622, .AliasCondStart: 325, .NumOperands: 2, .NumConds: 3 },
2070 {.AsmStrOffset: 1639, .AliasCondStart: 328, .NumOperands: 2, .NumConds: 4 },
2071 {.AsmStrOffset: 1656, .AliasCondStart: 332, .NumOperands: 2, .NumConds: 3 },
2072 {.AsmStrOffset: 1673, .AliasCondStart: 335, .NumOperands: 2, .NumConds: 4 },
2073 {.AsmStrOffset: 1690, .AliasCondStart: 339, .NumOperands: 2, .NumConds: 3 },
2074 {.AsmStrOffset: 1708, .AliasCondStart: 342, .NumOperands: 2, .NumConds: 4 },
2075 {.AsmStrOffset: 1726, .AliasCondStart: 346, .NumOperands: 2, .NumConds: 3 },
2076 {.AsmStrOffset: 1744, .AliasCondStart: 349, .NumOperands: 2, .NumConds: 4 },
2077 {.AsmStrOffset: 1762, .AliasCondStart: 353, .NumOperands: 2, .NumConds: 3 },
2078 {.AsmStrOffset: 1779, .AliasCondStart: 356, .NumOperands: 2, .NumConds: 4 },
2079 {.AsmStrOffset: 1796, .AliasCondStart: 360, .NumOperands: 2, .NumConds: 3 },
2080 {.AsmStrOffset: 1814, .AliasCondStart: 363, .NumOperands: 2, .NumConds: 4 },
2081 {.AsmStrOffset: 1832, .AliasCondStart: 367, .NumOperands: 2, .NumConds: 3 },
2082 {.AsmStrOffset: 1851, .AliasCondStart: 370, .NumOperands: 2, .NumConds: 4 },
2083 {.AsmStrOffset: 1870, .AliasCondStart: 374, .NumOperands: 2, .NumConds: 3 },
2084 {.AsmStrOffset: 1888, .AliasCondStart: 377, .NumOperands: 2, .NumConds: 4 },
2085 {.AsmStrOffset: 1906, .AliasCondStart: 381, .NumOperands: 2, .NumConds: 3 },
2086 {.AsmStrOffset: 1924, .AliasCondStart: 384, .NumOperands: 2, .NumConds: 4 },
2087 {.AsmStrOffset: 1942, .AliasCondStart: 388, .NumOperands: 2, .NumConds: 3 },
2088 {.AsmStrOffset: 1961, .AliasCondStart: 391, .NumOperands: 2, .NumConds: 4 },
2089 {.AsmStrOffset: 1980, .AliasCondStart: 395, .NumOperands: 2, .NumConds: 3 },
2090 {.AsmStrOffset: 1999, .AliasCondStart: 398, .NumOperands: 2, .NumConds: 4 },
2091 {.AsmStrOffset: 2018, .AliasCondStart: 402, .NumOperands: 2, .NumConds: 3 },
2092 {.AsmStrOffset: 2036, .AliasCondStart: 405, .NumOperands: 2, .NumConds: 4 },
2093 {.AsmStrOffset: 2054, .AliasCondStart: 409, .NumOperands: 2, .NumConds: 3 },
2094 {.AsmStrOffset: 2072, .AliasCondStart: 412, .NumOperands: 2, .NumConds: 4 },
2095 // SP::BPRANT - 128
2096 {.AsmStrOffset: 2090, .AliasCondStart: 416, .NumOperands: 3, .NumConds: 4 },
2097 {.AsmStrOffset: 2110, .AliasCondStart: 420, .NumOperands: 3, .NumConds: 4 },
2098 {.AsmStrOffset: 2129, .AliasCondStart: 424, .NumOperands: 3, .NumConds: 4 },
2099 {.AsmStrOffset: 2148, .AliasCondStart: 428, .NumOperands: 3, .NumConds: 4 },
2100 // SP::BPRNT - 132
2101 {.AsmStrOffset: 2168, .AliasCondStart: 432, .NumOperands: 3, .NumConds: 4 },
2102 {.AsmStrOffset: 2186, .AliasCondStart: 436, .NumOperands: 3, .NumConds: 4 },
2103 {.AsmStrOffset: 2203, .AliasCondStart: 440, .NumOperands: 3, .NumConds: 4 },
2104 {.AsmStrOffset: 2220, .AliasCondStart: 444, .NumOperands: 3, .NumConds: 4 },
2105 // SP::CASArr - 136
2106 {.AsmStrOffset: 2238, .AliasCondStart: 448, .NumOperands: 5, .NumConds: 6 },
2107 {.AsmStrOffset: 2255, .AliasCondStart: 454, .NumOperands: 5, .NumConds: 6 },
2108 // SP::CASXArr - 138
2109 {.AsmStrOffset: 2273, .AliasCondStart: 460, .NumOperands: 5, .NumConds: 6 },
2110 {.AsmStrOffset: 2291, .AliasCondStart: 466, .NumOperands: 5, .NumConds: 6 },
2111 // SP::CWBCONDri - 140
2112 {.AsmStrOffset: 2310, .AliasCondStart: 472, .NumOperands: 4, .NumConds: 4 },
2113 {.AsmStrOffset: 2329, .AliasCondStart: 476, .NumOperands: 4, .NumConds: 4 },
2114 {.AsmStrOffset: 2347, .AliasCondStart: 480, .NumOperands: 4, .NumConds: 4 },
2115 {.AsmStrOffset: 2365, .AliasCondStart: 484, .NumOperands: 4, .NumConds: 4 },
2116 {.AsmStrOffset: 2384, .AliasCondStart: 488, .NumOperands: 4, .NumConds: 4 },
2117 {.AsmStrOffset: 2403, .AliasCondStart: 492, .NumOperands: 4, .NumConds: 4 },
2118 {.AsmStrOffset: 2421, .AliasCondStart: 496, .NumOperands: 4, .NumConds: 4 },
2119 {.AsmStrOffset: 2440, .AliasCondStart: 500, .NumOperands: 4, .NumConds: 4 },
2120 {.AsmStrOffset: 2460, .AliasCondStart: 504, .NumOperands: 4, .NumConds: 4 },
2121 {.AsmStrOffset: 2479, .AliasCondStart: 508, .NumOperands: 4, .NumConds: 4 },
2122 {.AsmStrOffset: 2498, .AliasCondStart: 512, .NumOperands: 4, .NumConds: 4 },
2123 {.AsmStrOffset: 2518, .AliasCondStart: 516, .NumOperands: 4, .NumConds: 4 },
2124 {.AsmStrOffset: 2538, .AliasCondStart: 520, .NumOperands: 4, .NumConds: 4 },
2125 {.AsmStrOffset: 2557, .AliasCondStart: 524, .NumOperands: 4, .NumConds: 4 },
2126 // SP::CWBCONDrr - 154
2127 {.AsmStrOffset: 2310, .AliasCondStart: 528, .NumOperands: 4, .NumConds: 5 },
2128 {.AsmStrOffset: 2329, .AliasCondStart: 533, .NumOperands: 4, .NumConds: 5 },
2129 {.AsmStrOffset: 2347, .AliasCondStart: 538, .NumOperands: 4, .NumConds: 5 },
2130 {.AsmStrOffset: 2365, .AliasCondStart: 543, .NumOperands: 4, .NumConds: 5 },
2131 {.AsmStrOffset: 2384, .AliasCondStart: 548, .NumOperands: 4, .NumConds: 5 },
2132 {.AsmStrOffset: 2403, .AliasCondStart: 553, .NumOperands: 4, .NumConds: 5 },
2133 {.AsmStrOffset: 2421, .AliasCondStart: 558, .NumOperands: 4, .NumConds: 5 },
2134 {.AsmStrOffset: 2440, .AliasCondStart: 563, .NumOperands: 4, .NumConds: 5 },
2135 {.AsmStrOffset: 2460, .AliasCondStart: 568, .NumOperands: 4, .NumConds: 5 },
2136 {.AsmStrOffset: 2479, .AliasCondStart: 573, .NumOperands: 4, .NumConds: 5 },
2137 {.AsmStrOffset: 2498, .AliasCondStart: 578, .NumOperands: 4, .NumConds: 5 },
2138 {.AsmStrOffset: 2518, .AliasCondStart: 583, .NumOperands: 4, .NumConds: 5 },
2139 {.AsmStrOffset: 2538, .AliasCondStart: 588, .NumOperands: 4, .NumConds: 5 },
2140 {.AsmStrOffset: 2557, .AliasCondStart: 593, .NumOperands: 4, .NumConds: 5 },
2141 // SP::CXBCONDri - 168
2142 {.AsmStrOffset: 2576, .AliasCondStart: 598, .NumOperands: 4, .NumConds: 4 },
2143 {.AsmStrOffset: 2595, .AliasCondStart: 602, .NumOperands: 4, .NumConds: 4 },
2144 {.AsmStrOffset: 2613, .AliasCondStart: 606, .NumOperands: 4, .NumConds: 4 },
2145 {.AsmStrOffset: 2631, .AliasCondStart: 610, .NumOperands: 4, .NumConds: 4 },
2146 {.AsmStrOffset: 2650, .AliasCondStart: 614, .NumOperands: 4, .NumConds: 4 },
2147 {.AsmStrOffset: 2669, .AliasCondStart: 618, .NumOperands: 4, .NumConds: 4 },
2148 {.AsmStrOffset: 2687, .AliasCondStart: 622, .NumOperands: 4, .NumConds: 4 },
2149 {.AsmStrOffset: 2706, .AliasCondStart: 626, .NumOperands: 4, .NumConds: 4 },
2150 {.AsmStrOffset: 2726, .AliasCondStart: 630, .NumOperands: 4, .NumConds: 4 },
2151 {.AsmStrOffset: 2745, .AliasCondStart: 634, .NumOperands: 4, .NumConds: 4 },
2152 {.AsmStrOffset: 2764, .AliasCondStart: 638, .NumOperands: 4, .NumConds: 4 },
2153 {.AsmStrOffset: 2784, .AliasCondStart: 642, .NumOperands: 4, .NumConds: 4 },
2154 {.AsmStrOffset: 2804, .AliasCondStart: 646, .NumOperands: 4, .NumConds: 4 },
2155 {.AsmStrOffset: 2823, .AliasCondStart: 650, .NumOperands: 4, .NumConds: 4 },
2156 // SP::CXBCONDrr - 182
2157 {.AsmStrOffset: 2576, .AliasCondStart: 654, .NumOperands: 4, .NumConds: 5 },
2158 {.AsmStrOffset: 2595, .AliasCondStart: 659, .NumOperands: 4, .NumConds: 5 },
2159 {.AsmStrOffset: 2613, .AliasCondStart: 664, .NumOperands: 4, .NumConds: 5 },
2160 {.AsmStrOffset: 2631, .AliasCondStart: 669, .NumOperands: 4, .NumConds: 5 },
2161 {.AsmStrOffset: 2650, .AliasCondStart: 674, .NumOperands: 4, .NumConds: 5 },
2162 {.AsmStrOffset: 2669, .AliasCondStart: 679, .NumOperands: 4, .NumConds: 5 },
2163 {.AsmStrOffset: 2687, .AliasCondStart: 684, .NumOperands: 4, .NumConds: 5 },
2164 {.AsmStrOffset: 2706, .AliasCondStart: 689, .NumOperands: 4, .NumConds: 5 },
2165 {.AsmStrOffset: 2726, .AliasCondStart: 694, .NumOperands: 4, .NumConds: 5 },
2166 {.AsmStrOffset: 2745, .AliasCondStart: 699, .NumOperands: 4, .NumConds: 5 },
2167 {.AsmStrOffset: 2764, .AliasCondStart: 704, .NumOperands: 4, .NumConds: 5 },
2168 {.AsmStrOffset: 2784, .AliasCondStart: 709, .NumOperands: 4, .NumConds: 5 },
2169 {.AsmStrOffset: 2804, .AliasCondStart: 714, .NumOperands: 4, .NumConds: 5 },
2170 {.AsmStrOffset: 2823, .AliasCondStart: 719, .NumOperands: 4, .NumConds: 5 },
2171 // SP::FMOVD_ICC - 196
2172 {.AsmStrOffset: 2842, .AliasCondStart: 724, .NumOperands: 4, .NumConds: 5 },
2173 {.AsmStrOffset: 2862, .AliasCondStart: 729, .NumOperands: 4, .NumConds: 6 },
2174 {.AsmStrOffset: 2882, .AliasCondStart: 735, .NumOperands: 4, .NumConds: 5 },
2175 {.AsmStrOffset: 2902, .AliasCondStart: 740, .NumOperands: 4, .NumConds: 6 },
2176 {.AsmStrOffset: 2922, .AliasCondStart: 746, .NumOperands: 4, .NumConds: 5 },
2177 {.AsmStrOffset: 2943, .AliasCondStart: 751, .NumOperands: 4, .NumConds: 6 },
2178 {.AsmStrOffset: 2964, .AliasCondStart: 757, .NumOperands: 4, .NumConds: 5 },
2179 {.AsmStrOffset: 2984, .AliasCondStart: 762, .NumOperands: 4, .NumConds: 6 },
2180 {.AsmStrOffset: 3004, .AliasCondStart: 768, .NumOperands: 4, .NumConds: 5 },
2181 {.AsmStrOffset: 3024, .AliasCondStart: 773, .NumOperands: 4, .NumConds: 6 },
2182 {.AsmStrOffset: 3044, .AliasCondStart: 779, .NumOperands: 4, .NumConds: 5 },
2183 {.AsmStrOffset: 3065, .AliasCondStart: 784, .NumOperands: 4, .NumConds: 6 },
2184 {.AsmStrOffset: 3086, .AliasCondStart: 790, .NumOperands: 4, .NumConds: 5 },
2185 {.AsmStrOffset: 3107, .AliasCondStart: 795, .NumOperands: 4, .NumConds: 6 },
2186 {.AsmStrOffset: 3128, .AliasCondStart: 801, .NumOperands: 4, .NumConds: 5 },
2187 {.AsmStrOffset: 3148, .AliasCondStart: 806, .NumOperands: 4, .NumConds: 6 },
2188 {.AsmStrOffset: 3168, .AliasCondStart: 812, .NumOperands: 4, .NumConds: 5 },
2189 {.AsmStrOffset: 3189, .AliasCondStart: 817, .NumOperands: 4, .NumConds: 6 },
2190 {.AsmStrOffset: 3210, .AliasCondStart: 823, .NumOperands: 4, .NumConds: 5 },
2191 {.AsmStrOffset: 3232, .AliasCondStart: 828, .NumOperands: 4, .NumConds: 6 },
2192 {.AsmStrOffset: 3254, .AliasCondStart: 834, .NumOperands: 4, .NumConds: 5 },
2193 {.AsmStrOffset: 3275, .AliasCondStart: 839, .NumOperands: 4, .NumConds: 6 },
2194 {.AsmStrOffset: 3296, .AliasCondStart: 845, .NumOperands: 4, .NumConds: 5 },
2195 {.AsmStrOffset: 3317, .AliasCondStart: 850, .NumOperands: 4, .NumConds: 6 },
2196 {.AsmStrOffset: 3338, .AliasCondStart: 856, .NumOperands: 4, .NumConds: 5 },
2197 {.AsmStrOffset: 3360, .AliasCondStart: 861, .NumOperands: 4, .NumConds: 6 },
2198 {.AsmStrOffset: 3382, .AliasCondStart: 867, .NumOperands: 4, .NumConds: 5 },
2199 {.AsmStrOffset: 3404, .AliasCondStart: 872, .NumOperands: 4, .NumConds: 6 },
2200 {.AsmStrOffset: 3426, .AliasCondStart: 878, .NumOperands: 4, .NumConds: 5 },
2201 {.AsmStrOffset: 3447, .AliasCondStart: 883, .NumOperands: 4, .NumConds: 6 },
2202 {.AsmStrOffset: 3468, .AliasCondStart: 889, .NumOperands: 4, .NumConds: 5 },
2203 {.AsmStrOffset: 3489, .AliasCondStart: 894, .NumOperands: 4, .NumConds: 6 },
2204 // SP::FMOVQ_ICC - 228
2205 {.AsmStrOffset: 3510, .AliasCondStart: 900, .NumOperands: 4, .NumConds: 5 },
2206 {.AsmStrOffset: 3530, .AliasCondStart: 905, .NumOperands: 4, .NumConds: 6 },
2207 {.AsmStrOffset: 3550, .AliasCondStart: 911, .NumOperands: 4, .NumConds: 5 },
2208 {.AsmStrOffset: 3570, .AliasCondStart: 916, .NumOperands: 4, .NumConds: 6 },
2209 {.AsmStrOffset: 3590, .AliasCondStart: 922, .NumOperands: 4, .NumConds: 5 },
2210 {.AsmStrOffset: 3611, .AliasCondStart: 927, .NumOperands: 4, .NumConds: 6 },
2211 {.AsmStrOffset: 3632, .AliasCondStart: 933, .NumOperands: 4, .NumConds: 5 },
2212 {.AsmStrOffset: 3652, .AliasCondStart: 938, .NumOperands: 4, .NumConds: 6 },
2213 {.AsmStrOffset: 3672, .AliasCondStart: 944, .NumOperands: 4, .NumConds: 5 },
2214 {.AsmStrOffset: 3692, .AliasCondStart: 949, .NumOperands: 4, .NumConds: 6 },
2215 {.AsmStrOffset: 3712, .AliasCondStart: 955, .NumOperands: 4, .NumConds: 5 },
2216 {.AsmStrOffset: 3733, .AliasCondStart: 960, .NumOperands: 4, .NumConds: 6 },
2217 {.AsmStrOffset: 3754, .AliasCondStart: 966, .NumOperands: 4, .NumConds: 5 },
2218 {.AsmStrOffset: 3775, .AliasCondStart: 971, .NumOperands: 4, .NumConds: 6 },
2219 {.AsmStrOffset: 3796, .AliasCondStart: 977, .NumOperands: 4, .NumConds: 5 },
2220 {.AsmStrOffset: 3816, .AliasCondStart: 982, .NumOperands: 4, .NumConds: 6 },
2221 {.AsmStrOffset: 3836, .AliasCondStart: 988, .NumOperands: 4, .NumConds: 5 },
2222 {.AsmStrOffset: 3857, .AliasCondStart: 993, .NumOperands: 4, .NumConds: 6 },
2223 {.AsmStrOffset: 3878, .AliasCondStart: 999, .NumOperands: 4, .NumConds: 5 },
2224 {.AsmStrOffset: 3900, .AliasCondStart: 1004, .NumOperands: 4, .NumConds: 6 },
2225 {.AsmStrOffset: 3922, .AliasCondStart: 1010, .NumOperands: 4, .NumConds: 5 },
2226 {.AsmStrOffset: 3943, .AliasCondStart: 1015, .NumOperands: 4, .NumConds: 6 },
2227 {.AsmStrOffset: 3964, .AliasCondStart: 1021, .NumOperands: 4, .NumConds: 5 },
2228 {.AsmStrOffset: 3985, .AliasCondStart: 1026, .NumOperands: 4, .NumConds: 6 },
2229 {.AsmStrOffset: 4006, .AliasCondStart: 1032, .NumOperands: 4, .NumConds: 5 },
2230 {.AsmStrOffset: 4028, .AliasCondStart: 1037, .NumOperands: 4, .NumConds: 6 },
2231 {.AsmStrOffset: 4050, .AliasCondStart: 1043, .NumOperands: 4, .NumConds: 5 },
2232 {.AsmStrOffset: 4072, .AliasCondStart: 1048, .NumOperands: 4, .NumConds: 6 },
2233 {.AsmStrOffset: 4094, .AliasCondStart: 1054, .NumOperands: 4, .NumConds: 5 },
2234 {.AsmStrOffset: 4115, .AliasCondStart: 1059, .NumOperands: 4, .NumConds: 6 },
2235 {.AsmStrOffset: 4136, .AliasCondStart: 1065, .NumOperands: 4, .NumConds: 5 },
2236 {.AsmStrOffset: 4157, .AliasCondStart: 1070, .NumOperands: 4, .NumConds: 6 },
2237 // SP::FMOVRD - 260
2238 {.AsmStrOffset: 4178, .AliasCondStart: 1076, .NumOperands: 5, .NumConds: 6 },
2239 {.AsmStrOffset: 4199, .AliasCondStart: 1082, .NumOperands: 5, .NumConds: 6 },
2240 {.AsmStrOffset: 4219, .AliasCondStart: 1088, .NumOperands: 5, .NumConds: 6 },
2241 {.AsmStrOffset: 4239, .AliasCondStart: 1094, .NumOperands: 5, .NumConds: 6 },
2242 // SP::FMOVRQ - 264
2243 {.AsmStrOffset: 4260, .AliasCondStart: 1100, .NumOperands: 5, .NumConds: 6 },
2244 {.AsmStrOffset: 4281, .AliasCondStart: 1106, .NumOperands: 5, .NumConds: 6 },
2245 {.AsmStrOffset: 4301, .AliasCondStart: 1112, .NumOperands: 5, .NumConds: 6 },
2246 {.AsmStrOffset: 4321, .AliasCondStart: 1118, .NumOperands: 5, .NumConds: 6 },
2247 // SP::FMOVRS - 268
2248 {.AsmStrOffset: 4342, .AliasCondStart: 1124, .NumOperands: 5, .NumConds: 6 },
2249 {.AsmStrOffset: 4363, .AliasCondStart: 1130, .NumOperands: 5, .NumConds: 6 },
2250 {.AsmStrOffset: 4383, .AliasCondStart: 1136, .NumOperands: 5, .NumConds: 6 },
2251 {.AsmStrOffset: 4403, .AliasCondStart: 1142, .NumOperands: 5, .NumConds: 6 },
2252 // SP::FMOVS_ICC - 272
2253 {.AsmStrOffset: 4424, .AliasCondStart: 1148, .NumOperands: 4, .NumConds: 5 },
2254 {.AsmStrOffset: 4444, .AliasCondStart: 1153, .NumOperands: 4, .NumConds: 6 },
2255 {.AsmStrOffset: 4464, .AliasCondStart: 1159, .NumOperands: 4, .NumConds: 5 },
2256 {.AsmStrOffset: 4484, .AliasCondStart: 1164, .NumOperands: 4, .NumConds: 6 },
2257 {.AsmStrOffset: 4504, .AliasCondStart: 1170, .NumOperands: 4, .NumConds: 5 },
2258 {.AsmStrOffset: 4525, .AliasCondStart: 1175, .NumOperands: 4, .NumConds: 6 },
2259 {.AsmStrOffset: 4546, .AliasCondStart: 1181, .NumOperands: 4, .NumConds: 5 },
2260 {.AsmStrOffset: 4566, .AliasCondStart: 1186, .NumOperands: 4, .NumConds: 6 },
2261 {.AsmStrOffset: 4586, .AliasCondStart: 1192, .NumOperands: 4, .NumConds: 5 },
2262 {.AsmStrOffset: 4606, .AliasCondStart: 1197, .NumOperands: 4, .NumConds: 6 },
2263 {.AsmStrOffset: 4626, .AliasCondStart: 1203, .NumOperands: 4, .NumConds: 5 },
2264 {.AsmStrOffset: 4647, .AliasCondStart: 1208, .NumOperands: 4, .NumConds: 6 },
2265 {.AsmStrOffset: 4668, .AliasCondStart: 1214, .NumOperands: 4, .NumConds: 5 },
2266 {.AsmStrOffset: 4689, .AliasCondStart: 1219, .NumOperands: 4, .NumConds: 6 },
2267 {.AsmStrOffset: 4710, .AliasCondStart: 1225, .NumOperands: 4, .NumConds: 5 },
2268 {.AsmStrOffset: 4730, .AliasCondStart: 1230, .NumOperands: 4, .NumConds: 6 },
2269 {.AsmStrOffset: 4750, .AliasCondStart: 1236, .NumOperands: 4, .NumConds: 5 },
2270 {.AsmStrOffset: 4771, .AliasCondStart: 1241, .NumOperands: 4, .NumConds: 6 },
2271 {.AsmStrOffset: 4792, .AliasCondStart: 1247, .NumOperands: 4, .NumConds: 5 },
2272 {.AsmStrOffset: 4814, .AliasCondStart: 1252, .NumOperands: 4, .NumConds: 6 },
2273 {.AsmStrOffset: 4836, .AliasCondStart: 1258, .NumOperands: 4, .NumConds: 5 },
2274 {.AsmStrOffset: 4857, .AliasCondStart: 1263, .NumOperands: 4, .NumConds: 6 },
2275 {.AsmStrOffset: 4878, .AliasCondStart: 1269, .NumOperands: 4, .NumConds: 5 },
2276 {.AsmStrOffset: 4899, .AliasCondStart: 1274, .NumOperands: 4, .NumConds: 6 },
2277 {.AsmStrOffset: 4920, .AliasCondStart: 1280, .NumOperands: 4, .NumConds: 5 },
2278 {.AsmStrOffset: 4942, .AliasCondStart: 1285, .NumOperands: 4, .NumConds: 6 },
2279 {.AsmStrOffset: 4964, .AliasCondStart: 1291, .NumOperands: 4, .NumConds: 5 },
2280 {.AsmStrOffset: 4986, .AliasCondStart: 1296, .NumOperands: 4, .NumConds: 6 },
2281 {.AsmStrOffset: 5008, .AliasCondStart: 1302, .NumOperands: 4, .NumConds: 5 },
2282 {.AsmStrOffset: 5029, .AliasCondStart: 1307, .NumOperands: 4, .NumConds: 6 },
2283 {.AsmStrOffset: 5050, .AliasCondStart: 1313, .NumOperands: 4, .NumConds: 5 },
2284 {.AsmStrOffset: 5071, .AliasCondStart: 1318, .NumOperands: 4, .NumConds: 6 },
2285 // SP::MOVICCri - 304
2286 {.AsmStrOffset: 5092, .AliasCondStart: 1324, .NumOperands: 4, .NumConds: 5 },
2287 {.AsmStrOffset: 5110, .AliasCondStart: 1329, .NumOperands: 4, .NumConds: 6 },
2288 {.AsmStrOffset: 5128, .AliasCondStart: 1335, .NumOperands: 4, .NumConds: 5 },
2289 {.AsmStrOffset: 5146, .AliasCondStart: 1340, .NumOperands: 4, .NumConds: 6 },
2290 {.AsmStrOffset: 5164, .AliasCondStart: 1346, .NumOperands: 4, .NumConds: 5 },
2291 {.AsmStrOffset: 5183, .AliasCondStart: 1351, .NumOperands: 4, .NumConds: 6 },
2292 {.AsmStrOffset: 5202, .AliasCondStart: 1357, .NumOperands: 4, .NumConds: 5 },
2293 {.AsmStrOffset: 5220, .AliasCondStart: 1362, .NumOperands: 4, .NumConds: 6 },
2294 {.AsmStrOffset: 5238, .AliasCondStart: 1368, .NumOperands: 4, .NumConds: 5 },
2295 {.AsmStrOffset: 5256, .AliasCondStart: 1373, .NumOperands: 4, .NumConds: 6 },
2296 {.AsmStrOffset: 5274, .AliasCondStart: 1379, .NumOperands: 4, .NumConds: 5 },
2297 {.AsmStrOffset: 5293, .AliasCondStart: 1384, .NumOperands: 4, .NumConds: 6 },
2298 {.AsmStrOffset: 5312, .AliasCondStart: 1390, .NumOperands: 4, .NumConds: 5 },
2299 {.AsmStrOffset: 5331, .AliasCondStart: 1395, .NumOperands: 4, .NumConds: 6 },
2300 {.AsmStrOffset: 5350, .AliasCondStart: 1401, .NumOperands: 4, .NumConds: 5 },
2301 {.AsmStrOffset: 5368, .AliasCondStart: 1406, .NumOperands: 4, .NumConds: 6 },
2302 {.AsmStrOffset: 5386, .AliasCondStart: 1412, .NumOperands: 4, .NumConds: 5 },
2303 {.AsmStrOffset: 5405, .AliasCondStart: 1417, .NumOperands: 4, .NumConds: 6 },
2304 {.AsmStrOffset: 5424, .AliasCondStart: 1423, .NumOperands: 4, .NumConds: 5 },
2305 {.AsmStrOffset: 5444, .AliasCondStart: 1428, .NumOperands: 4, .NumConds: 6 },
2306 {.AsmStrOffset: 5464, .AliasCondStart: 1434, .NumOperands: 4, .NumConds: 5 },
2307 {.AsmStrOffset: 5483, .AliasCondStart: 1439, .NumOperands: 4, .NumConds: 6 },
2308 {.AsmStrOffset: 5502, .AliasCondStart: 1445, .NumOperands: 4, .NumConds: 5 },
2309 {.AsmStrOffset: 5521, .AliasCondStart: 1450, .NumOperands: 4, .NumConds: 6 },
2310 {.AsmStrOffset: 5540, .AliasCondStart: 1456, .NumOperands: 4, .NumConds: 5 },
2311 {.AsmStrOffset: 5560, .AliasCondStart: 1461, .NumOperands: 4, .NumConds: 6 },
2312 {.AsmStrOffset: 5580, .AliasCondStart: 1467, .NumOperands: 4, .NumConds: 5 },
2313 {.AsmStrOffset: 5600, .AliasCondStart: 1472, .NumOperands: 4, .NumConds: 6 },
2314 {.AsmStrOffset: 5620, .AliasCondStart: 1478, .NumOperands: 4, .NumConds: 5 },
2315 {.AsmStrOffset: 5639, .AliasCondStart: 1483, .NumOperands: 4, .NumConds: 6 },
2316 {.AsmStrOffset: 5658, .AliasCondStart: 1489, .NumOperands: 4, .NumConds: 5 },
2317 {.AsmStrOffset: 5677, .AliasCondStart: 1494, .NumOperands: 4, .NumConds: 6 },
2318 // SP::MOVICCrr - 336
2319 {.AsmStrOffset: 5092, .AliasCondStart: 1500, .NumOperands: 4, .NumConds: 5 },
2320 {.AsmStrOffset: 5110, .AliasCondStart: 1505, .NumOperands: 4, .NumConds: 6 },
2321 {.AsmStrOffset: 5128, .AliasCondStart: 1511, .NumOperands: 4, .NumConds: 5 },
2322 {.AsmStrOffset: 5146, .AliasCondStart: 1516, .NumOperands: 4, .NumConds: 6 },
2323 {.AsmStrOffset: 5164, .AliasCondStart: 1522, .NumOperands: 4, .NumConds: 5 },
2324 {.AsmStrOffset: 5183, .AliasCondStart: 1527, .NumOperands: 4, .NumConds: 6 },
2325 {.AsmStrOffset: 5202, .AliasCondStart: 1533, .NumOperands: 4, .NumConds: 5 },
2326 {.AsmStrOffset: 5220, .AliasCondStart: 1538, .NumOperands: 4, .NumConds: 6 },
2327 {.AsmStrOffset: 5238, .AliasCondStart: 1544, .NumOperands: 4, .NumConds: 5 },
2328 {.AsmStrOffset: 5256, .AliasCondStart: 1549, .NumOperands: 4, .NumConds: 6 },
2329 {.AsmStrOffset: 5274, .AliasCondStart: 1555, .NumOperands: 4, .NumConds: 5 },
2330 {.AsmStrOffset: 5293, .AliasCondStart: 1560, .NumOperands: 4, .NumConds: 6 },
2331 {.AsmStrOffset: 5312, .AliasCondStart: 1566, .NumOperands: 4, .NumConds: 5 },
2332 {.AsmStrOffset: 5331, .AliasCondStart: 1571, .NumOperands: 4, .NumConds: 6 },
2333 {.AsmStrOffset: 5350, .AliasCondStart: 1577, .NumOperands: 4, .NumConds: 5 },
2334 {.AsmStrOffset: 5368, .AliasCondStart: 1582, .NumOperands: 4, .NumConds: 6 },
2335 {.AsmStrOffset: 5386, .AliasCondStart: 1588, .NumOperands: 4, .NumConds: 5 },
2336 {.AsmStrOffset: 5405, .AliasCondStart: 1593, .NumOperands: 4, .NumConds: 6 },
2337 {.AsmStrOffset: 5424, .AliasCondStart: 1599, .NumOperands: 4, .NumConds: 5 },
2338 {.AsmStrOffset: 5444, .AliasCondStart: 1604, .NumOperands: 4, .NumConds: 6 },
2339 {.AsmStrOffset: 5464, .AliasCondStart: 1610, .NumOperands: 4, .NumConds: 5 },
2340 {.AsmStrOffset: 5483, .AliasCondStart: 1615, .NumOperands: 4, .NumConds: 6 },
2341 {.AsmStrOffset: 5502, .AliasCondStart: 1621, .NumOperands: 4, .NumConds: 5 },
2342 {.AsmStrOffset: 5521, .AliasCondStart: 1626, .NumOperands: 4, .NumConds: 6 },
2343 {.AsmStrOffset: 5540, .AliasCondStart: 1632, .NumOperands: 4, .NumConds: 5 },
2344 {.AsmStrOffset: 5560, .AliasCondStart: 1637, .NumOperands: 4, .NumConds: 6 },
2345 {.AsmStrOffset: 5580, .AliasCondStart: 1643, .NumOperands: 4, .NumConds: 5 },
2346 {.AsmStrOffset: 5600, .AliasCondStart: 1648, .NumOperands: 4, .NumConds: 6 },
2347 {.AsmStrOffset: 5620, .AliasCondStart: 1654, .NumOperands: 4, .NumConds: 5 },
2348 {.AsmStrOffset: 5639, .AliasCondStart: 1659, .NumOperands: 4, .NumConds: 6 },
2349 {.AsmStrOffset: 5658, .AliasCondStart: 1665, .NumOperands: 4, .NumConds: 5 },
2350 {.AsmStrOffset: 5677, .AliasCondStart: 1670, .NumOperands: 4, .NumConds: 6 },
2351 // SP::MOVRri - 368
2352 {.AsmStrOffset: 5696, .AliasCondStart: 1676, .NumOperands: 5, .NumConds: 6 },
2353 {.AsmStrOffset: 5715, .AliasCondStart: 1682, .NumOperands: 5, .NumConds: 6 },
2354 {.AsmStrOffset: 5733, .AliasCondStart: 1688, .NumOperands: 5, .NumConds: 6 },
2355 {.AsmStrOffset: 5751, .AliasCondStart: 1694, .NumOperands: 5, .NumConds: 6 },
2356 // SP::MOVRrr - 372
2357 {.AsmStrOffset: 5696, .AliasCondStart: 1700, .NumOperands: 5, .NumConds: 6 },
2358 {.AsmStrOffset: 5715, .AliasCondStart: 1706, .NumOperands: 5, .NumConds: 6 },
2359 {.AsmStrOffset: 5733, .AliasCondStart: 1712, .NumOperands: 5, .NumConds: 6 },
2360 {.AsmStrOffset: 5751, .AliasCondStart: 1718, .NumOperands: 5, .NumConds: 6 },
2361 // SP::ORCCrr - 376
2362 {.AsmStrOffset: 5770, .AliasCondStart: 1724, .NumOperands: 3, .NumConds: 3 },
2363 // SP::ORri - 377
2364 {.AsmStrOffset: 5777, .AliasCondStart: 1727, .NumOperands: 3, .NumConds: 2 },
2365 // SP::ORrr - 378
2366 {.AsmStrOffset: 5777, .AliasCondStart: 1729, .NumOperands: 3, .NumConds: 3 },
2367 // SP::RESTORErr - 379
2368 {.AsmStrOffset: 5788, .AliasCondStart: 1732, .NumOperands: 3, .NumConds: 3 },
2369 // SP::RET - 380
2370 {.AsmStrOffset: 5796, .AliasCondStart: 1735, .NumOperands: 1, .NumConds: 1 },
2371 // SP::RETL - 381
2372 {.AsmStrOffset: 5800, .AliasCondStart: 1736, .NumOperands: 1, .NumConds: 1 },
2373 // SP::SAVErr - 382
2374 {.AsmStrOffset: 5805, .AliasCondStart: 1737, .NumOperands: 3, .NumConds: 3 },
2375 // SP::SUBCCri - 383
2376 {.AsmStrOffset: 5810, .AliasCondStart: 1740, .NumOperands: 3, .NumConds: 2 },
2377 // SP::SUBCCrr - 384
2378 {.AsmStrOffset: 5810, .AliasCondStart: 1742, .NumOperands: 3, .NumConds: 3 },
2379 // SP::TICCri - 385
2380 {.AsmStrOffset: 5821, .AliasCondStart: 1745, .NumOperands: 3, .NumConds: 4 },
2381 {.AsmStrOffset: 5833, .AliasCondStart: 1749, .NumOperands: 3, .NumConds: 5 },
2382 {.AsmStrOffset: 5845, .AliasCondStart: 1754, .NumOperands: 3, .NumConds: 4 },
2383 {.AsmStrOffset: 5862, .AliasCondStart: 1758, .NumOperands: 3, .NumConds: 5 },
2384 {.AsmStrOffset: 5879, .AliasCondStart: 1763, .NumOperands: 3, .NumConds: 4 },
2385 {.AsmStrOffset: 5891, .AliasCondStart: 1767, .NumOperands: 3, .NumConds: 5 },
2386 {.AsmStrOffset: 5903, .AliasCondStart: 1772, .NumOperands: 3, .NumConds: 4 },
2387 {.AsmStrOffset: 5920, .AliasCondStart: 1776, .NumOperands: 3, .NumConds: 5 },
2388 {.AsmStrOffset: 5937, .AliasCondStart: 1781, .NumOperands: 3, .NumConds: 4 },
2389 {.AsmStrOffset: 5950, .AliasCondStart: 1785, .NumOperands: 3, .NumConds: 5 },
2390 {.AsmStrOffset: 5963, .AliasCondStart: 1790, .NumOperands: 3, .NumConds: 4 },
2391 {.AsmStrOffset: 5981, .AliasCondStart: 1794, .NumOperands: 3, .NumConds: 5 },
2392 {.AsmStrOffset: 5999, .AliasCondStart: 1799, .NumOperands: 3, .NumConds: 4 },
2393 {.AsmStrOffset: 6011, .AliasCondStart: 1803, .NumOperands: 3, .NumConds: 5 },
2394 {.AsmStrOffset: 6023, .AliasCondStart: 1808, .NumOperands: 3, .NumConds: 4 },
2395 {.AsmStrOffset: 6040, .AliasCondStart: 1812, .NumOperands: 3, .NumConds: 5 },
2396 {.AsmStrOffset: 6057, .AliasCondStart: 1817, .NumOperands: 3, .NumConds: 4 },
2397 {.AsmStrOffset: 6069, .AliasCondStart: 1821, .NumOperands: 3, .NumConds: 5 },
2398 {.AsmStrOffset: 6081, .AliasCondStart: 1826, .NumOperands: 3, .NumConds: 4 },
2399 {.AsmStrOffset: 6098, .AliasCondStart: 1830, .NumOperands: 3, .NumConds: 5 },
2400 {.AsmStrOffset: 6115, .AliasCondStart: 1835, .NumOperands: 3, .NumConds: 4 },
2401 {.AsmStrOffset: 6128, .AliasCondStart: 1839, .NumOperands: 3, .NumConds: 5 },
2402 {.AsmStrOffset: 6141, .AliasCondStart: 1844, .NumOperands: 3, .NumConds: 4 },
2403 {.AsmStrOffset: 6159, .AliasCondStart: 1848, .NumOperands: 3, .NumConds: 5 },
2404 {.AsmStrOffset: 6177, .AliasCondStart: 1853, .NumOperands: 3, .NumConds: 4 },
2405 {.AsmStrOffset: 6190, .AliasCondStart: 1857, .NumOperands: 3, .NumConds: 5 },
2406 {.AsmStrOffset: 6203, .AliasCondStart: 1862, .NumOperands: 3, .NumConds: 4 },
2407 {.AsmStrOffset: 6221, .AliasCondStart: 1866, .NumOperands: 3, .NumConds: 5 },
2408 {.AsmStrOffset: 6239, .AliasCondStart: 1871, .NumOperands: 3, .NumConds: 4 },
2409 {.AsmStrOffset: 6251, .AliasCondStart: 1875, .NumOperands: 3, .NumConds: 5 },
2410 {.AsmStrOffset: 6263, .AliasCondStart: 1880, .NumOperands: 3, .NumConds: 4 },
2411 {.AsmStrOffset: 6280, .AliasCondStart: 1884, .NumOperands: 3, .NumConds: 5 },
2412 {.AsmStrOffset: 6297, .AliasCondStart: 1889, .NumOperands: 3, .NumConds: 4 },
2413 {.AsmStrOffset: 6310, .AliasCondStart: 1893, .NumOperands: 3, .NumConds: 5 },
2414 {.AsmStrOffset: 6323, .AliasCondStart: 1898, .NumOperands: 3, .NumConds: 4 },
2415 {.AsmStrOffset: 6341, .AliasCondStart: 1902, .NumOperands: 3, .NumConds: 5 },
2416 {.AsmStrOffset: 6359, .AliasCondStart: 1907, .NumOperands: 3, .NumConds: 4 },
2417 {.AsmStrOffset: 6373, .AliasCondStart: 1911, .NumOperands: 3, .NumConds: 5 },
2418 {.AsmStrOffset: 6387, .AliasCondStart: 1916, .NumOperands: 3, .NumConds: 4 },
2419 {.AsmStrOffset: 6406, .AliasCondStart: 1920, .NumOperands: 3, .NumConds: 5 },
2420 {.AsmStrOffset: 6425, .AliasCondStart: 1925, .NumOperands: 3, .NumConds: 4 },
2421 {.AsmStrOffset: 6438, .AliasCondStart: 1929, .NumOperands: 3, .NumConds: 5 },
2422 {.AsmStrOffset: 6451, .AliasCondStart: 1934, .NumOperands: 3, .NumConds: 4 },
2423 {.AsmStrOffset: 6469, .AliasCondStart: 1938, .NumOperands: 3, .NumConds: 5 },
2424 {.AsmStrOffset: 6487, .AliasCondStart: 1943, .NumOperands: 3, .NumConds: 4 },
2425 {.AsmStrOffset: 6500, .AliasCondStart: 1947, .NumOperands: 3, .NumConds: 5 },
2426 {.AsmStrOffset: 6513, .AliasCondStart: 1952, .NumOperands: 3, .NumConds: 4 },
2427 {.AsmStrOffset: 6531, .AliasCondStart: 1956, .NumOperands: 3, .NumConds: 5 },
2428 {.AsmStrOffset: 6549, .AliasCondStart: 1961, .NumOperands: 3, .NumConds: 4 },
2429 {.AsmStrOffset: 6563, .AliasCondStart: 1965, .NumOperands: 3, .NumConds: 5 },
2430 {.AsmStrOffset: 6577, .AliasCondStart: 1970, .NumOperands: 3, .NumConds: 4 },
2431 {.AsmStrOffset: 6596, .AliasCondStart: 1974, .NumOperands: 3, .NumConds: 5 },
2432 {.AsmStrOffset: 6615, .AliasCondStart: 1979, .NumOperands: 3, .NumConds: 4 },
2433 {.AsmStrOffset: 6629, .AliasCondStart: 1983, .NumOperands: 3, .NumConds: 5 },
2434 {.AsmStrOffset: 6643, .AliasCondStart: 1988, .NumOperands: 3, .NumConds: 4 },
2435 {.AsmStrOffset: 6662, .AliasCondStart: 1992, .NumOperands: 3, .NumConds: 5 },
2436 {.AsmStrOffset: 6681, .AliasCondStart: 1997, .NumOperands: 3, .NumConds: 4 },
2437 {.AsmStrOffset: 6694, .AliasCondStart: 2001, .NumOperands: 3, .NumConds: 5 },
2438 {.AsmStrOffset: 6707, .AliasCondStart: 2006, .NumOperands: 3, .NumConds: 4 },
2439 {.AsmStrOffset: 6725, .AliasCondStart: 2010, .NumOperands: 3, .NumConds: 5 },
2440 {.AsmStrOffset: 6743, .AliasCondStart: 2015, .NumOperands: 3, .NumConds: 4 },
2441 {.AsmStrOffset: 6756, .AliasCondStart: 2019, .NumOperands: 3, .NumConds: 5 },
2442 {.AsmStrOffset: 6769, .AliasCondStart: 2024, .NumOperands: 3, .NumConds: 4 },
2443 {.AsmStrOffset: 6787, .AliasCondStart: 2028, .NumOperands: 3, .NumConds: 5 },
2444 // SP::TICCrr - 449
2445 {.AsmStrOffset: 5821, .AliasCondStart: 2033, .NumOperands: 3, .NumConds: 4 },
2446 {.AsmStrOffset: 5833, .AliasCondStart: 2037, .NumOperands: 3, .NumConds: 5 },
2447 {.AsmStrOffset: 5845, .AliasCondStart: 2042, .NumOperands: 3, .NumConds: 4 },
2448 {.AsmStrOffset: 5862, .AliasCondStart: 2046, .NumOperands: 3, .NumConds: 5 },
2449 {.AsmStrOffset: 5879, .AliasCondStart: 2051, .NumOperands: 3, .NumConds: 4 },
2450 {.AsmStrOffset: 5891, .AliasCondStart: 2055, .NumOperands: 3, .NumConds: 5 },
2451 {.AsmStrOffset: 5903, .AliasCondStart: 2060, .NumOperands: 3, .NumConds: 4 },
2452 {.AsmStrOffset: 5920, .AliasCondStart: 2064, .NumOperands: 3, .NumConds: 5 },
2453 {.AsmStrOffset: 5937, .AliasCondStart: 2069, .NumOperands: 3, .NumConds: 4 },
2454 {.AsmStrOffset: 5950, .AliasCondStart: 2073, .NumOperands: 3, .NumConds: 5 },
2455 {.AsmStrOffset: 5963, .AliasCondStart: 2078, .NumOperands: 3, .NumConds: 4 },
2456 {.AsmStrOffset: 5981, .AliasCondStart: 2082, .NumOperands: 3, .NumConds: 5 },
2457 {.AsmStrOffset: 5999, .AliasCondStart: 2087, .NumOperands: 3, .NumConds: 4 },
2458 {.AsmStrOffset: 6011, .AliasCondStart: 2091, .NumOperands: 3, .NumConds: 5 },
2459 {.AsmStrOffset: 6023, .AliasCondStart: 2096, .NumOperands: 3, .NumConds: 4 },
2460 {.AsmStrOffset: 6040, .AliasCondStart: 2100, .NumOperands: 3, .NumConds: 5 },
2461 {.AsmStrOffset: 6057, .AliasCondStart: 2105, .NumOperands: 3, .NumConds: 4 },
2462 {.AsmStrOffset: 6069, .AliasCondStart: 2109, .NumOperands: 3, .NumConds: 5 },
2463 {.AsmStrOffset: 6081, .AliasCondStart: 2114, .NumOperands: 3, .NumConds: 4 },
2464 {.AsmStrOffset: 6098, .AliasCondStart: 2118, .NumOperands: 3, .NumConds: 5 },
2465 {.AsmStrOffset: 6115, .AliasCondStart: 2123, .NumOperands: 3, .NumConds: 4 },
2466 {.AsmStrOffset: 6128, .AliasCondStart: 2127, .NumOperands: 3, .NumConds: 5 },
2467 {.AsmStrOffset: 6141, .AliasCondStart: 2132, .NumOperands: 3, .NumConds: 4 },
2468 {.AsmStrOffset: 6159, .AliasCondStart: 2136, .NumOperands: 3, .NumConds: 5 },
2469 {.AsmStrOffset: 6177, .AliasCondStart: 2141, .NumOperands: 3, .NumConds: 4 },
2470 {.AsmStrOffset: 6190, .AliasCondStart: 2145, .NumOperands: 3, .NumConds: 5 },
2471 {.AsmStrOffset: 6203, .AliasCondStart: 2150, .NumOperands: 3, .NumConds: 4 },
2472 {.AsmStrOffset: 6221, .AliasCondStart: 2154, .NumOperands: 3, .NumConds: 5 },
2473 {.AsmStrOffset: 6239, .AliasCondStart: 2159, .NumOperands: 3, .NumConds: 4 },
2474 {.AsmStrOffset: 6251, .AliasCondStart: 2163, .NumOperands: 3, .NumConds: 5 },
2475 {.AsmStrOffset: 6263, .AliasCondStart: 2168, .NumOperands: 3, .NumConds: 4 },
2476 {.AsmStrOffset: 6280, .AliasCondStart: 2172, .NumOperands: 3, .NumConds: 5 },
2477 {.AsmStrOffset: 6297, .AliasCondStart: 2177, .NumOperands: 3, .NumConds: 4 },
2478 {.AsmStrOffset: 6310, .AliasCondStart: 2181, .NumOperands: 3, .NumConds: 5 },
2479 {.AsmStrOffset: 6323, .AliasCondStart: 2186, .NumOperands: 3, .NumConds: 4 },
2480 {.AsmStrOffset: 6341, .AliasCondStart: 2190, .NumOperands: 3, .NumConds: 5 },
2481 {.AsmStrOffset: 6359, .AliasCondStart: 2195, .NumOperands: 3, .NumConds: 4 },
2482 {.AsmStrOffset: 6373, .AliasCondStart: 2199, .NumOperands: 3, .NumConds: 5 },
2483 {.AsmStrOffset: 6387, .AliasCondStart: 2204, .NumOperands: 3, .NumConds: 4 },
2484 {.AsmStrOffset: 6406, .AliasCondStart: 2208, .NumOperands: 3, .NumConds: 5 },
2485 {.AsmStrOffset: 6425, .AliasCondStart: 2213, .NumOperands: 3, .NumConds: 4 },
2486 {.AsmStrOffset: 6438, .AliasCondStart: 2217, .NumOperands: 3, .NumConds: 5 },
2487 {.AsmStrOffset: 6451, .AliasCondStart: 2222, .NumOperands: 3, .NumConds: 4 },
2488 {.AsmStrOffset: 6469, .AliasCondStart: 2226, .NumOperands: 3, .NumConds: 5 },
2489 {.AsmStrOffset: 6487, .AliasCondStart: 2231, .NumOperands: 3, .NumConds: 4 },
2490 {.AsmStrOffset: 6500, .AliasCondStart: 2235, .NumOperands: 3, .NumConds: 5 },
2491 {.AsmStrOffset: 6513, .AliasCondStart: 2240, .NumOperands: 3, .NumConds: 4 },
2492 {.AsmStrOffset: 6531, .AliasCondStart: 2244, .NumOperands: 3, .NumConds: 5 },
2493 {.AsmStrOffset: 6549, .AliasCondStart: 2249, .NumOperands: 3, .NumConds: 4 },
2494 {.AsmStrOffset: 6563, .AliasCondStart: 2253, .NumOperands: 3, .NumConds: 5 },
2495 {.AsmStrOffset: 6577, .AliasCondStart: 2258, .NumOperands: 3, .NumConds: 4 },
2496 {.AsmStrOffset: 6596, .AliasCondStart: 2262, .NumOperands: 3, .NumConds: 5 },
2497 {.AsmStrOffset: 6615, .AliasCondStart: 2267, .NumOperands: 3, .NumConds: 4 },
2498 {.AsmStrOffset: 6629, .AliasCondStart: 2271, .NumOperands: 3, .NumConds: 5 },
2499 {.AsmStrOffset: 6643, .AliasCondStart: 2276, .NumOperands: 3, .NumConds: 4 },
2500 {.AsmStrOffset: 6662, .AliasCondStart: 2280, .NumOperands: 3, .NumConds: 5 },
2501 {.AsmStrOffset: 6681, .AliasCondStart: 2285, .NumOperands: 3, .NumConds: 4 },
2502 {.AsmStrOffset: 6694, .AliasCondStart: 2289, .NumOperands: 3, .NumConds: 5 },
2503 {.AsmStrOffset: 6707, .AliasCondStart: 2294, .NumOperands: 3, .NumConds: 4 },
2504 {.AsmStrOffset: 6725, .AliasCondStart: 2298, .NumOperands: 3, .NumConds: 5 },
2505 {.AsmStrOffset: 6743, .AliasCondStart: 2303, .NumOperands: 3, .NumConds: 4 },
2506 {.AsmStrOffset: 6756, .AliasCondStart: 2307, .NumOperands: 3, .NumConds: 5 },
2507 {.AsmStrOffset: 6769, .AliasCondStart: 2312, .NumOperands: 3, .NumConds: 4 },
2508 {.AsmStrOffset: 6787, .AliasCondStart: 2316, .NumOperands: 3, .NumConds: 5 },
2509 // SP::TRAPri - 513
2510 {.AsmStrOffset: 6805, .AliasCondStart: 2321, .NumOperands: 3, .NumConds: 3 },
2511 {.AsmStrOffset: 6811, .AliasCondStart: 2324, .NumOperands: 3, .NumConds: 3 },
2512 {.AsmStrOffset: 6822, .AliasCondStart: 2327, .NumOperands: 3, .NumConds: 3 },
2513 {.AsmStrOffset: 6828, .AliasCondStart: 2330, .NumOperands: 3, .NumConds: 3 },
2514 {.AsmStrOffset: 6839, .AliasCondStart: 2333, .NumOperands: 3, .NumConds: 3 },
2515 {.AsmStrOffset: 6846, .AliasCondStart: 2336, .NumOperands: 3, .NumConds: 3 },
2516 {.AsmStrOffset: 6858, .AliasCondStart: 2339, .NumOperands: 3, .NumConds: 3 },
2517 {.AsmStrOffset: 6864, .AliasCondStart: 2342, .NumOperands: 3, .NumConds: 3 },
2518 {.AsmStrOffset: 6875, .AliasCondStart: 2345, .NumOperands: 3, .NumConds: 3 },
2519 {.AsmStrOffset: 6881, .AliasCondStart: 2348, .NumOperands: 3, .NumConds: 3 },
2520 {.AsmStrOffset: 6892, .AliasCondStart: 2351, .NumOperands: 3, .NumConds: 3 },
2521 {.AsmStrOffset: 6899, .AliasCondStart: 2354, .NumOperands: 3, .NumConds: 3 },
2522 {.AsmStrOffset: 6911, .AliasCondStart: 2357, .NumOperands: 3, .NumConds: 3 },
2523 {.AsmStrOffset: 6918, .AliasCondStart: 2360, .NumOperands: 3, .NumConds: 3 },
2524 {.AsmStrOffset: 6930, .AliasCondStart: 2363, .NumOperands: 3, .NumConds: 3 },
2525 {.AsmStrOffset: 6936, .AliasCondStart: 2366, .NumOperands: 3, .NumConds: 3 },
2526 {.AsmStrOffset: 6947, .AliasCondStart: 2369, .NumOperands: 3, .NumConds: 3 },
2527 {.AsmStrOffset: 6954, .AliasCondStart: 2372, .NumOperands: 3, .NumConds: 3 },
2528 {.AsmStrOffset: 6966, .AliasCondStart: 2375, .NumOperands: 3, .NumConds: 3 },
2529 {.AsmStrOffset: 6974, .AliasCondStart: 2378, .NumOperands: 3, .NumConds: 3 },
2530 {.AsmStrOffset: 6987, .AliasCondStart: 2381, .NumOperands: 3, .NumConds: 3 },
2531 {.AsmStrOffset: 6994, .AliasCondStart: 2384, .NumOperands: 3, .NumConds: 3 },
2532 {.AsmStrOffset: 7006, .AliasCondStart: 2387, .NumOperands: 3, .NumConds: 3 },
2533 {.AsmStrOffset: 7013, .AliasCondStart: 2390, .NumOperands: 3, .NumConds: 3 },
2534 {.AsmStrOffset: 7025, .AliasCondStart: 2393, .NumOperands: 3, .NumConds: 3 },
2535 {.AsmStrOffset: 7033, .AliasCondStart: 2396, .NumOperands: 3, .NumConds: 3 },
2536 {.AsmStrOffset: 7046, .AliasCondStart: 2399, .NumOperands: 3, .NumConds: 3 },
2537 {.AsmStrOffset: 7054, .AliasCondStart: 2402, .NumOperands: 3, .NumConds: 3 },
2538 {.AsmStrOffset: 7067, .AliasCondStart: 2405, .NumOperands: 3, .NumConds: 3 },
2539 {.AsmStrOffset: 7074, .AliasCondStart: 2408, .NumOperands: 3, .NumConds: 3 },
2540 {.AsmStrOffset: 7086, .AliasCondStart: 2411, .NumOperands: 3, .NumConds: 3 },
2541 {.AsmStrOffset: 7093, .AliasCondStart: 2414, .NumOperands: 3, .NumConds: 3 },
2542 // SP::TRAPrr - 545
2543 {.AsmStrOffset: 6805, .AliasCondStart: 2417, .NumOperands: 3, .NumConds: 3 },
2544 {.AsmStrOffset: 6811, .AliasCondStart: 2420, .NumOperands: 3, .NumConds: 3 },
2545 {.AsmStrOffset: 6822, .AliasCondStart: 2423, .NumOperands: 3, .NumConds: 3 },
2546 {.AsmStrOffset: 6828, .AliasCondStart: 2426, .NumOperands: 3, .NumConds: 3 },
2547 {.AsmStrOffset: 6839, .AliasCondStart: 2429, .NumOperands: 3, .NumConds: 3 },
2548 {.AsmStrOffset: 6846, .AliasCondStart: 2432, .NumOperands: 3, .NumConds: 3 },
2549 {.AsmStrOffset: 6858, .AliasCondStart: 2435, .NumOperands: 3, .NumConds: 3 },
2550 {.AsmStrOffset: 6864, .AliasCondStart: 2438, .NumOperands: 3, .NumConds: 3 },
2551 {.AsmStrOffset: 6875, .AliasCondStart: 2441, .NumOperands: 3, .NumConds: 3 },
2552 {.AsmStrOffset: 6881, .AliasCondStart: 2444, .NumOperands: 3, .NumConds: 3 },
2553 {.AsmStrOffset: 6892, .AliasCondStart: 2447, .NumOperands: 3, .NumConds: 3 },
2554 {.AsmStrOffset: 6899, .AliasCondStart: 2450, .NumOperands: 3, .NumConds: 3 },
2555 {.AsmStrOffset: 6911, .AliasCondStart: 2453, .NumOperands: 3, .NumConds: 3 },
2556 {.AsmStrOffset: 6918, .AliasCondStart: 2456, .NumOperands: 3, .NumConds: 3 },
2557 {.AsmStrOffset: 6930, .AliasCondStart: 2459, .NumOperands: 3, .NumConds: 3 },
2558 {.AsmStrOffset: 6936, .AliasCondStart: 2462, .NumOperands: 3, .NumConds: 3 },
2559 {.AsmStrOffset: 6947, .AliasCondStart: 2465, .NumOperands: 3, .NumConds: 3 },
2560 {.AsmStrOffset: 6954, .AliasCondStart: 2468, .NumOperands: 3, .NumConds: 3 },
2561 {.AsmStrOffset: 6966, .AliasCondStart: 2471, .NumOperands: 3, .NumConds: 3 },
2562 {.AsmStrOffset: 6974, .AliasCondStart: 2474, .NumOperands: 3, .NumConds: 3 },
2563 {.AsmStrOffset: 6987, .AliasCondStart: 2477, .NumOperands: 3, .NumConds: 3 },
2564 {.AsmStrOffset: 6994, .AliasCondStart: 2480, .NumOperands: 3, .NumConds: 3 },
2565 {.AsmStrOffset: 7006, .AliasCondStart: 2483, .NumOperands: 3, .NumConds: 3 },
2566 {.AsmStrOffset: 7013, .AliasCondStart: 2486, .NumOperands: 3, .NumConds: 3 },
2567 {.AsmStrOffset: 7025, .AliasCondStart: 2489, .NumOperands: 3, .NumConds: 3 },
2568 {.AsmStrOffset: 7033, .AliasCondStart: 2492, .NumOperands: 3, .NumConds: 3 },
2569 {.AsmStrOffset: 7046, .AliasCondStart: 2495, .NumOperands: 3, .NumConds: 3 },
2570 {.AsmStrOffset: 7054, .AliasCondStart: 2498, .NumOperands: 3, .NumConds: 3 },
2571 {.AsmStrOffset: 7067, .AliasCondStart: 2501, .NumOperands: 3, .NumConds: 3 },
2572 {.AsmStrOffset: 7074, .AliasCondStart: 2504, .NumOperands: 3, .NumConds: 3 },
2573 {.AsmStrOffset: 7086, .AliasCondStart: 2507, .NumOperands: 3, .NumConds: 3 },
2574 {.AsmStrOffset: 7093, .AliasCondStart: 2510, .NumOperands: 3, .NumConds: 3 },
2575 // SP::TXCCri - 577
2576 {.AsmStrOffset: 7105, .AliasCondStart: 2513, .NumOperands: 3, .NumConds: 4 },
2577 {.AsmStrOffset: 5833, .AliasCondStart: 2517, .NumOperands: 3, .NumConds: 5 },
2578 {.AsmStrOffset: 7117, .AliasCondStart: 2522, .NumOperands: 3, .NumConds: 4 },
2579 {.AsmStrOffset: 5862, .AliasCondStart: 2526, .NumOperands: 3, .NumConds: 5 },
2580 {.AsmStrOffset: 7134, .AliasCondStart: 2531, .NumOperands: 3, .NumConds: 4 },
2581 {.AsmStrOffset: 5891, .AliasCondStart: 2535, .NumOperands: 3, .NumConds: 5 },
2582 {.AsmStrOffset: 7146, .AliasCondStart: 2540, .NumOperands: 3, .NumConds: 4 },
2583 {.AsmStrOffset: 5920, .AliasCondStart: 2544, .NumOperands: 3, .NumConds: 5 },
2584 {.AsmStrOffset: 7163, .AliasCondStart: 2549, .NumOperands: 3, .NumConds: 4 },
2585 {.AsmStrOffset: 5950, .AliasCondStart: 2553, .NumOperands: 3, .NumConds: 5 },
2586 {.AsmStrOffset: 7176, .AliasCondStart: 2558, .NumOperands: 3, .NumConds: 4 },
2587 {.AsmStrOffset: 5981, .AliasCondStart: 2562, .NumOperands: 3, .NumConds: 5 },
2588 {.AsmStrOffset: 7194, .AliasCondStart: 2567, .NumOperands: 3, .NumConds: 4 },
2589 {.AsmStrOffset: 6011, .AliasCondStart: 2571, .NumOperands: 3, .NumConds: 5 },
2590 {.AsmStrOffset: 7206, .AliasCondStart: 2576, .NumOperands: 3, .NumConds: 4 },
2591 {.AsmStrOffset: 6040, .AliasCondStart: 2580, .NumOperands: 3, .NumConds: 5 },
2592 {.AsmStrOffset: 7223, .AliasCondStart: 2585, .NumOperands: 3, .NumConds: 4 },
2593 {.AsmStrOffset: 6069, .AliasCondStart: 2589, .NumOperands: 3, .NumConds: 5 },
2594 {.AsmStrOffset: 7235, .AliasCondStart: 2594, .NumOperands: 3, .NumConds: 4 },
2595 {.AsmStrOffset: 6098, .AliasCondStart: 2598, .NumOperands: 3, .NumConds: 5 },
2596 {.AsmStrOffset: 7252, .AliasCondStart: 2603, .NumOperands: 3, .NumConds: 4 },
2597 {.AsmStrOffset: 6128, .AliasCondStart: 2607, .NumOperands: 3, .NumConds: 5 },
2598 {.AsmStrOffset: 7265, .AliasCondStart: 2612, .NumOperands: 3, .NumConds: 4 },
2599 {.AsmStrOffset: 6159, .AliasCondStart: 2616, .NumOperands: 3, .NumConds: 5 },
2600 {.AsmStrOffset: 7283, .AliasCondStart: 2621, .NumOperands: 3, .NumConds: 4 },
2601 {.AsmStrOffset: 6190, .AliasCondStart: 2625, .NumOperands: 3, .NumConds: 5 },
2602 {.AsmStrOffset: 7296, .AliasCondStart: 2630, .NumOperands: 3, .NumConds: 4 },
2603 {.AsmStrOffset: 6221, .AliasCondStart: 2634, .NumOperands: 3, .NumConds: 5 },
2604 {.AsmStrOffset: 7314, .AliasCondStart: 2639, .NumOperands: 3, .NumConds: 4 },
2605 {.AsmStrOffset: 6251, .AliasCondStart: 2643, .NumOperands: 3, .NumConds: 5 },
2606 {.AsmStrOffset: 7326, .AliasCondStart: 2648, .NumOperands: 3, .NumConds: 4 },
2607 {.AsmStrOffset: 6280, .AliasCondStart: 2652, .NumOperands: 3, .NumConds: 5 },
2608 {.AsmStrOffset: 7343, .AliasCondStart: 2657, .NumOperands: 3, .NumConds: 4 },
2609 {.AsmStrOffset: 6310, .AliasCondStart: 2661, .NumOperands: 3, .NumConds: 5 },
2610 {.AsmStrOffset: 7356, .AliasCondStart: 2666, .NumOperands: 3, .NumConds: 4 },
2611 {.AsmStrOffset: 6341, .AliasCondStart: 2670, .NumOperands: 3, .NumConds: 5 },
2612 {.AsmStrOffset: 7374, .AliasCondStart: 2675, .NumOperands: 3, .NumConds: 4 },
2613 {.AsmStrOffset: 6373, .AliasCondStart: 2679, .NumOperands: 3, .NumConds: 5 },
2614 {.AsmStrOffset: 7388, .AliasCondStart: 2684, .NumOperands: 3, .NumConds: 4 },
2615 {.AsmStrOffset: 6406, .AliasCondStart: 2688, .NumOperands: 3, .NumConds: 5 },
2616 {.AsmStrOffset: 7407, .AliasCondStart: 2693, .NumOperands: 3, .NumConds: 4 },
2617 {.AsmStrOffset: 6438, .AliasCondStart: 2697, .NumOperands: 3, .NumConds: 5 },
2618 {.AsmStrOffset: 7420, .AliasCondStart: 2702, .NumOperands: 3, .NumConds: 4 },
2619 {.AsmStrOffset: 6469, .AliasCondStart: 2706, .NumOperands: 3, .NumConds: 5 },
2620 {.AsmStrOffset: 7438, .AliasCondStart: 2711, .NumOperands: 3, .NumConds: 4 },
2621 {.AsmStrOffset: 6500, .AliasCondStart: 2715, .NumOperands: 3, .NumConds: 5 },
2622 {.AsmStrOffset: 7451, .AliasCondStart: 2720, .NumOperands: 3, .NumConds: 4 },
2623 {.AsmStrOffset: 6531, .AliasCondStart: 2724, .NumOperands: 3, .NumConds: 5 },
2624 {.AsmStrOffset: 7469, .AliasCondStart: 2729, .NumOperands: 3, .NumConds: 4 },
2625 {.AsmStrOffset: 6563, .AliasCondStart: 2733, .NumOperands: 3, .NumConds: 5 },
2626 {.AsmStrOffset: 7483, .AliasCondStart: 2738, .NumOperands: 3, .NumConds: 4 },
2627 {.AsmStrOffset: 6596, .AliasCondStart: 2742, .NumOperands: 3, .NumConds: 5 },
2628 {.AsmStrOffset: 7502, .AliasCondStart: 2747, .NumOperands: 3, .NumConds: 4 },
2629 {.AsmStrOffset: 6629, .AliasCondStart: 2751, .NumOperands: 3, .NumConds: 5 },
2630 {.AsmStrOffset: 7516, .AliasCondStart: 2756, .NumOperands: 3, .NumConds: 4 },
2631 {.AsmStrOffset: 6662, .AliasCondStart: 2760, .NumOperands: 3, .NumConds: 5 },
2632 {.AsmStrOffset: 7535, .AliasCondStart: 2765, .NumOperands: 3, .NumConds: 4 },
2633 {.AsmStrOffset: 6694, .AliasCondStart: 2769, .NumOperands: 3, .NumConds: 5 },
2634 {.AsmStrOffset: 7548, .AliasCondStart: 2774, .NumOperands: 3, .NumConds: 4 },
2635 {.AsmStrOffset: 6725, .AliasCondStart: 2778, .NumOperands: 3, .NumConds: 5 },
2636 {.AsmStrOffset: 7566, .AliasCondStart: 2783, .NumOperands: 3, .NumConds: 4 },
2637 {.AsmStrOffset: 6756, .AliasCondStart: 2787, .NumOperands: 3, .NumConds: 5 },
2638 {.AsmStrOffset: 7579, .AliasCondStart: 2792, .NumOperands: 3, .NumConds: 4 },
2639 {.AsmStrOffset: 6787, .AliasCondStart: 2796, .NumOperands: 3, .NumConds: 5 },
2640 // SP::TXCCrr - 641
2641 {.AsmStrOffset: 7105, .AliasCondStart: 2801, .NumOperands: 3, .NumConds: 4 },
2642 {.AsmStrOffset: 5833, .AliasCondStart: 2805, .NumOperands: 3, .NumConds: 5 },
2643 {.AsmStrOffset: 7117, .AliasCondStart: 2810, .NumOperands: 3, .NumConds: 4 },
2644 {.AsmStrOffset: 5862, .AliasCondStart: 2814, .NumOperands: 3, .NumConds: 5 },
2645 {.AsmStrOffset: 7134, .AliasCondStart: 2819, .NumOperands: 3, .NumConds: 4 },
2646 {.AsmStrOffset: 5891, .AliasCondStart: 2823, .NumOperands: 3, .NumConds: 5 },
2647 {.AsmStrOffset: 7146, .AliasCondStart: 2828, .NumOperands: 3, .NumConds: 4 },
2648 {.AsmStrOffset: 5920, .AliasCondStart: 2832, .NumOperands: 3, .NumConds: 5 },
2649 {.AsmStrOffset: 7163, .AliasCondStart: 2837, .NumOperands: 3, .NumConds: 4 },
2650 {.AsmStrOffset: 5950, .AliasCondStart: 2841, .NumOperands: 3, .NumConds: 5 },
2651 {.AsmStrOffset: 7176, .AliasCondStart: 2846, .NumOperands: 3, .NumConds: 4 },
2652 {.AsmStrOffset: 5981, .AliasCondStart: 2850, .NumOperands: 3, .NumConds: 5 },
2653 {.AsmStrOffset: 7194, .AliasCondStart: 2855, .NumOperands: 3, .NumConds: 4 },
2654 {.AsmStrOffset: 6011, .AliasCondStart: 2859, .NumOperands: 3, .NumConds: 5 },
2655 {.AsmStrOffset: 7206, .AliasCondStart: 2864, .NumOperands: 3, .NumConds: 4 },
2656 {.AsmStrOffset: 6040, .AliasCondStart: 2868, .NumOperands: 3, .NumConds: 5 },
2657 {.AsmStrOffset: 7223, .AliasCondStart: 2873, .NumOperands: 3, .NumConds: 4 },
2658 {.AsmStrOffset: 6069, .AliasCondStart: 2877, .NumOperands: 3, .NumConds: 5 },
2659 {.AsmStrOffset: 7235, .AliasCondStart: 2882, .NumOperands: 3, .NumConds: 4 },
2660 {.AsmStrOffset: 6098, .AliasCondStart: 2886, .NumOperands: 3, .NumConds: 5 },
2661 {.AsmStrOffset: 7252, .AliasCondStart: 2891, .NumOperands: 3, .NumConds: 4 },
2662 {.AsmStrOffset: 6128, .AliasCondStart: 2895, .NumOperands: 3, .NumConds: 5 },
2663 {.AsmStrOffset: 7265, .AliasCondStart: 2900, .NumOperands: 3, .NumConds: 4 },
2664 {.AsmStrOffset: 6159, .AliasCondStart: 2904, .NumOperands: 3, .NumConds: 5 },
2665 {.AsmStrOffset: 7283, .AliasCondStart: 2909, .NumOperands: 3, .NumConds: 4 },
2666 {.AsmStrOffset: 6190, .AliasCondStart: 2913, .NumOperands: 3, .NumConds: 5 },
2667 {.AsmStrOffset: 7296, .AliasCondStart: 2918, .NumOperands: 3, .NumConds: 4 },
2668 {.AsmStrOffset: 6221, .AliasCondStart: 2922, .NumOperands: 3, .NumConds: 5 },
2669 {.AsmStrOffset: 7314, .AliasCondStart: 2927, .NumOperands: 3, .NumConds: 4 },
2670 {.AsmStrOffset: 6251, .AliasCondStart: 2931, .NumOperands: 3, .NumConds: 5 },
2671 {.AsmStrOffset: 7326, .AliasCondStart: 2936, .NumOperands: 3, .NumConds: 4 },
2672 {.AsmStrOffset: 6280, .AliasCondStart: 2940, .NumOperands: 3, .NumConds: 5 },
2673 {.AsmStrOffset: 7343, .AliasCondStart: 2945, .NumOperands: 3, .NumConds: 4 },
2674 {.AsmStrOffset: 6310, .AliasCondStart: 2949, .NumOperands: 3, .NumConds: 5 },
2675 {.AsmStrOffset: 7356, .AliasCondStart: 2954, .NumOperands: 3, .NumConds: 4 },
2676 {.AsmStrOffset: 6341, .AliasCondStart: 2958, .NumOperands: 3, .NumConds: 5 },
2677 {.AsmStrOffset: 7374, .AliasCondStart: 2963, .NumOperands: 3, .NumConds: 4 },
2678 {.AsmStrOffset: 6373, .AliasCondStart: 2967, .NumOperands: 3, .NumConds: 5 },
2679 {.AsmStrOffset: 7388, .AliasCondStart: 2972, .NumOperands: 3, .NumConds: 4 },
2680 {.AsmStrOffset: 6406, .AliasCondStart: 2976, .NumOperands: 3, .NumConds: 5 },
2681 {.AsmStrOffset: 7407, .AliasCondStart: 2981, .NumOperands: 3, .NumConds: 4 },
2682 {.AsmStrOffset: 6438, .AliasCondStart: 2985, .NumOperands: 3, .NumConds: 5 },
2683 {.AsmStrOffset: 7420, .AliasCondStart: 2990, .NumOperands: 3, .NumConds: 4 },
2684 {.AsmStrOffset: 6469, .AliasCondStart: 2994, .NumOperands: 3, .NumConds: 5 },
2685 {.AsmStrOffset: 7438, .AliasCondStart: 2999, .NumOperands: 3, .NumConds: 4 },
2686 {.AsmStrOffset: 6500, .AliasCondStart: 3003, .NumOperands: 3, .NumConds: 5 },
2687 {.AsmStrOffset: 7451, .AliasCondStart: 3008, .NumOperands: 3, .NumConds: 4 },
2688 {.AsmStrOffset: 6531, .AliasCondStart: 3012, .NumOperands: 3, .NumConds: 5 },
2689 {.AsmStrOffset: 7469, .AliasCondStart: 3017, .NumOperands: 3, .NumConds: 4 },
2690 {.AsmStrOffset: 6563, .AliasCondStart: 3021, .NumOperands: 3, .NumConds: 5 },
2691 {.AsmStrOffset: 7483, .AliasCondStart: 3026, .NumOperands: 3, .NumConds: 4 },
2692 {.AsmStrOffset: 6596, .AliasCondStart: 3030, .NumOperands: 3, .NumConds: 5 },
2693 {.AsmStrOffset: 7502, .AliasCondStart: 3035, .NumOperands: 3, .NumConds: 4 },
2694 {.AsmStrOffset: 6629, .AliasCondStart: 3039, .NumOperands: 3, .NumConds: 5 },
2695 {.AsmStrOffset: 7516, .AliasCondStart: 3044, .NumOperands: 3, .NumConds: 4 },
2696 {.AsmStrOffset: 6662, .AliasCondStart: 3048, .NumOperands: 3, .NumConds: 5 },
2697 {.AsmStrOffset: 7535, .AliasCondStart: 3053, .NumOperands: 3, .NumConds: 4 },
2698 {.AsmStrOffset: 6694, .AliasCondStart: 3057, .NumOperands: 3, .NumConds: 5 },
2699 {.AsmStrOffset: 7548, .AliasCondStart: 3062, .NumOperands: 3, .NumConds: 4 },
2700 {.AsmStrOffset: 6725, .AliasCondStart: 3066, .NumOperands: 3, .NumConds: 5 },
2701 {.AsmStrOffset: 7566, .AliasCondStart: 3071, .NumOperands: 3, .NumConds: 4 },
2702 {.AsmStrOffset: 6756, .AliasCondStart: 3075, .NumOperands: 3, .NumConds: 5 },
2703 {.AsmStrOffset: 7579, .AliasCondStart: 3080, .NumOperands: 3, .NumConds: 4 },
2704 {.AsmStrOffset: 6787, .AliasCondStart: 3084, .NumOperands: 3, .NumConds: 5 },
2705 // SP::V9FCMPD - 705
2706 {.AsmStrOffset: 7597, .AliasCondStart: 3089, .NumOperands: 3, .NumConds: 3 },
2707 // SP::V9FCMPED - 706
2708 {.AsmStrOffset: 7610, .AliasCondStart: 3092, .NumOperands: 3, .NumConds: 3 },
2709 // SP::V9FCMPEQ - 707
2710 {.AsmStrOffset: 7624, .AliasCondStart: 3095, .NumOperands: 3, .NumConds: 3 },
2711 // SP::V9FCMPES - 708
2712 {.AsmStrOffset: 7638, .AliasCondStart: 3098, .NumOperands: 3, .NumConds: 3 },
2713 // SP::V9FCMPQ - 709
2714 {.AsmStrOffset: 7652, .AliasCondStart: 3101, .NumOperands: 3, .NumConds: 3 },
2715 // SP::V9FCMPS - 710
2716 {.AsmStrOffset: 7665, .AliasCondStart: 3104, .NumOperands: 3, .NumConds: 3 },
2717 // SP::V9FMOVD_FCC - 711
2718 {.AsmStrOffset: 7678, .AliasCondStart: 3107, .NumOperands: 5, .NumConds: 6 },
2719 {.AsmStrOffset: 7696, .AliasCondStart: 3113, .NumOperands: 5, .NumConds: 6 },
2720 {.AsmStrOffset: 7714, .AliasCondStart: 3119, .NumOperands: 5, .NumConds: 6 },
2721 {.AsmStrOffset: 7732, .AliasCondStart: 3125, .NumOperands: 5, .NumConds: 6 },
2722 {.AsmStrOffset: 7750, .AliasCondStart: 3131, .NumOperands: 5, .NumConds: 6 },
2723 {.AsmStrOffset: 7769, .AliasCondStart: 3137, .NumOperands: 5, .NumConds: 6 },
2724 {.AsmStrOffset: 7787, .AliasCondStart: 3143, .NumOperands: 5, .NumConds: 6 },
2725 {.AsmStrOffset: 7806, .AliasCondStart: 3149, .NumOperands: 5, .NumConds: 6 },
2726 {.AsmStrOffset: 7825, .AliasCondStart: 3155, .NumOperands: 5, .NumConds: 6 },
2727 {.AsmStrOffset: 7844, .AliasCondStart: 3161, .NumOperands: 5, .NumConds: 6 },
2728 {.AsmStrOffset: 7862, .AliasCondStart: 3167, .NumOperands: 5, .NumConds: 6 },
2729 {.AsmStrOffset: 7881, .AliasCondStart: 3173, .NumOperands: 5, .NumConds: 6 },
2730 {.AsmStrOffset: 7900, .AliasCondStart: 3179, .NumOperands: 5, .NumConds: 6 },
2731 {.AsmStrOffset: 7920, .AliasCondStart: 3185, .NumOperands: 5, .NumConds: 6 },
2732 {.AsmStrOffset: 7939, .AliasCondStart: 3191, .NumOperands: 5, .NumConds: 6 },
2733 {.AsmStrOffset: 7959, .AliasCondStart: 3197, .NumOperands: 5, .NumConds: 6 },
2734 // SP::V9FMOVQ_FCC - 727
2735 {.AsmStrOffset: 7977, .AliasCondStart: 3203, .NumOperands: 5, .NumConds: 6 },
2736 {.AsmStrOffset: 7995, .AliasCondStart: 3209, .NumOperands: 5, .NumConds: 6 },
2737 {.AsmStrOffset: 8013, .AliasCondStart: 3215, .NumOperands: 5, .NumConds: 6 },
2738 {.AsmStrOffset: 8031, .AliasCondStart: 3221, .NumOperands: 5, .NumConds: 6 },
2739 {.AsmStrOffset: 8049, .AliasCondStart: 3227, .NumOperands: 5, .NumConds: 6 },
2740 {.AsmStrOffset: 8068, .AliasCondStart: 3233, .NumOperands: 5, .NumConds: 6 },
2741 {.AsmStrOffset: 8086, .AliasCondStart: 3239, .NumOperands: 5, .NumConds: 6 },
2742 {.AsmStrOffset: 8105, .AliasCondStart: 3245, .NumOperands: 5, .NumConds: 6 },
2743 {.AsmStrOffset: 8124, .AliasCondStart: 3251, .NumOperands: 5, .NumConds: 6 },
2744 {.AsmStrOffset: 8143, .AliasCondStart: 3257, .NumOperands: 5, .NumConds: 6 },
2745 {.AsmStrOffset: 8161, .AliasCondStart: 3263, .NumOperands: 5, .NumConds: 6 },
2746 {.AsmStrOffset: 8180, .AliasCondStart: 3269, .NumOperands: 5, .NumConds: 6 },
2747 {.AsmStrOffset: 8199, .AliasCondStart: 3275, .NumOperands: 5, .NumConds: 6 },
2748 {.AsmStrOffset: 8219, .AliasCondStart: 3281, .NumOperands: 5, .NumConds: 6 },
2749 {.AsmStrOffset: 8238, .AliasCondStart: 3287, .NumOperands: 5, .NumConds: 6 },
2750 {.AsmStrOffset: 8258, .AliasCondStart: 3293, .NumOperands: 5, .NumConds: 6 },
2751 // SP::V9FMOVS_FCC - 743
2752 {.AsmStrOffset: 8276, .AliasCondStart: 3299, .NumOperands: 5, .NumConds: 6 },
2753 {.AsmStrOffset: 8294, .AliasCondStart: 3305, .NumOperands: 5, .NumConds: 6 },
2754 {.AsmStrOffset: 8312, .AliasCondStart: 3311, .NumOperands: 5, .NumConds: 6 },
2755 {.AsmStrOffset: 8330, .AliasCondStart: 3317, .NumOperands: 5, .NumConds: 6 },
2756 {.AsmStrOffset: 8348, .AliasCondStart: 3323, .NumOperands: 5, .NumConds: 6 },
2757 {.AsmStrOffset: 8367, .AliasCondStart: 3329, .NumOperands: 5, .NumConds: 6 },
2758 {.AsmStrOffset: 8385, .AliasCondStart: 3335, .NumOperands: 5, .NumConds: 6 },
2759 {.AsmStrOffset: 8404, .AliasCondStart: 3341, .NumOperands: 5, .NumConds: 6 },
2760 {.AsmStrOffset: 8423, .AliasCondStart: 3347, .NumOperands: 5, .NumConds: 6 },
2761 {.AsmStrOffset: 8442, .AliasCondStart: 3353, .NumOperands: 5, .NumConds: 6 },
2762 {.AsmStrOffset: 8460, .AliasCondStart: 3359, .NumOperands: 5, .NumConds: 6 },
2763 {.AsmStrOffset: 8479, .AliasCondStart: 3365, .NumOperands: 5, .NumConds: 6 },
2764 {.AsmStrOffset: 8498, .AliasCondStart: 3371, .NumOperands: 5, .NumConds: 6 },
2765 {.AsmStrOffset: 8518, .AliasCondStart: 3377, .NumOperands: 5, .NumConds: 6 },
2766 {.AsmStrOffset: 8537, .AliasCondStart: 3383, .NumOperands: 5, .NumConds: 6 },
2767 {.AsmStrOffset: 8557, .AliasCondStart: 3389, .NumOperands: 5, .NumConds: 6 },
2768 // SP::V9MOVFCCri - 759
2769 {.AsmStrOffset: 8575, .AliasCondStart: 3395, .NumOperands: 5, .NumConds: 6 },
2770 {.AsmStrOffset: 8591, .AliasCondStart: 3401, .NumOperands: 5, .NumConds: 6 },
2771 {.AsmStrOffset: 8607, .AliasCondStart: 3407, .NumOperands: 5, .NumConds: 6 },
2772 {.AsmStrOffset: 8623, .AliasCondStart: 3413, .NumOperands: 5, .NumConds: 6 },
2773 {.AsmStrOffset: 8639, .AliasCondStart: 3419, .NumOperands: 5, .NumConds: 6 },
2774 {.AsmStrOffset: 8656, .AliasCondStart: 3425, .NumOperands: 5, .NumConds: 6 },
2775 {.AsmStrOffset: 8672, .AliasCondStart: 3431, .NumOperands: 5, .NumConds: 6 },
2776 {.AsmStrOffset: 8689, .AliasCondStart: 3437, .NumOperands: 5, .NumConds: 6 },
2777 {.AsmStrOffset: 8706, .AliasCondStart: 3443, .NumOperands: 5, .NumConds: 6 },
2778 {.AsmStrOffset: 8723, .AliasCondStart: 3449, .NumOperands: 5, .NumConds: 6 },
2779 {.AsmStrOffset: 8739, .AliasCondStart: 3455, .NumOperands: 5, .NumConds: 6 },
2780 {.AsmStrOffset: 8756, .AliasCondStart: 3461, .NumOperands: 5, .NumConds: 6 },
2781 {.AsmStrOffset: 8773, .AliasCondStart: 3467, .NumOperands: 5, .NumConds: 6 },
2782 {.AsmStrOffset: 8791, .AliasCondStart: 3473, .NumOperands: 5, .NumConds: 6 },
2783 {.AsmStrOffset: 8808, .AliasCondStart: 3479, .NumOperands: 5, .NumConds: 6 },
2784 {.AsmStrOffset: 8826, .AliasCondStart: 3485, .NumOperands: 5, .NumConds: 6 },
2785 // SP::V9MOVFCCrr - 775
2786 {.AsmStrOffset: 8575, .AliasCondStart: 3491, .NumOperands: 5, .NumConds: 6 },
2787 {.AsmStrOffset: 8591, .AliasCondStart: 3497, .NumOperands: 5, .NumConds: 6 },
2788 {.AsmStrOffset: 8607, .AliasCondStart: 3503, .NumOperands: 5, .NumConds: 6 },
2789 {.AsmStrOffset: 8623, .AliasCondStart: 3509, .NumOperands: 5, .NumConds: 6 },
2790 {.AsmStrOffset: 8639, .AliasCondStart: 3515, .NumOperands: 5, .NumConds: 6 },
2791 {.AsmStrOffset: 8656, .AliasCondStart: 3521, .NumOperands: 5, .NumConds: 6 },
2792 {.AsmStrOffset: 8672, .AliasCondStart: 3527, .NumOperands: 5, .NumConds: 6 },
2793 {.AsmStrOffset: 8689, .AliasCondStart: 3533, .NumOperands: 5, .NumConds: 6 },
2794 {.AsmStrOffset: 8706, .AliasCondStart: 3539, .NumOperands: 5, .NumConds: 6 },
2795 {.AsmStrOffset: 8723, .AliasCondStart: 3545, .NumOperands: 5, .NumConds: 6 },
2796 {.AsmStrOffset: 8739, .AliasCondStart: 3551, .NumOperands: 5, .NumConds: 6 },
2797 {.AsmStrOffset: 8756, .AliasCondStart: 3557, .NumOperands: 5, .NumConds: 6 },
2798 {.AsmStrOffset: 8773, .AliasCondStart: 3563, .NumOperands: 5, .NumConds: 6 },
2799 {.AsmStrOffset: 8791, .AliasCondStart: 3569, .NumOperands: 5, .NumConds: 6 },
2800 {.AsmStrOffset: 8808, .AliasCondStart: 3575, .NumOperands: 5, .NumConds: 6 },
2801 {.AsmStrOffset: 8826, .AliasCondStart: 3581, .NumOperands: 5, .NumConds: 6 },
2802 // SP::WRASRri - 791
2803 {.AsmStrOffset: 8842, .AliasCondStart: 3587, .NumOperands: 3, .NumConds: 3 },
2804 // SP::WRASRrr - 792
2805 {.AsmStrOffset: 8842, .AliasCondStart: 3590, .NumOperands: 3, .NumConds: 4 },
2806 };
2807
2808 static const AliasPatternCond Conds[] = {
2809 // (BCOND brtarget:$imm, 8) - 0
2810 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2811 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2812 // (BCOND brtarget:$imm, 0) - 2
2813 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2814 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2815 // (BCOND brtarget:$imm, 9) - 4
2816 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2817 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2818 // (BCOND brtarget:$imm, 1) - 6
2819 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2820 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2821 // (BCOND brtarget:$imm, 10) - 8
2822 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2823 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2824 // (BCOND brtarget:$imm, 2) - 10
2825 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2826 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2827 // (BCOND brtarget:$imm, 11) - 12
2828 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2829 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2830 // (BCOND brtarget:$imm, 3) - 14
2831 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2832 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2833 // (BCOND brtarget:$imm, 12) - 16
2834 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2835 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2836 // (BCOND brtarget:$imm, 4) - 18
2837 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2838 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2839 // (BCOND brtarget:$imm, 13) - 20
2840 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2841 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2842 // (BCOND brtarget:$imm, 5) - 22
2843 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2844 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2845 // (BCOND brtarget:$imm, 14) - 24
2846 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2847 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2848 // (BCOND brtarget:$imm, 6) - 26
2849 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2850 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2851 // (BCOND brtarget:$imm, 15) - 28
2852 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2853 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2854 // (BCOND brtarget:$imm, 7) - 30
2855 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2856 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2857 // (BCONDA brtarget:$imm, 8) - 32
2858 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2859 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2860 // (BCONDA brtarget:$imm, 0) - 34
2861 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2862 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2863 // (BCONDA brtarget:$imm, 9) - 36
2864 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2865 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2866 // (BCONDA brtarget:$imm, 1) - 38
2867 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2868 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2869 // (BCONDA brtarget:$imm, 10) - 40
2870 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2871 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2872 // (BCONDA brtarget:$imm, 2) - 42
2873 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2874 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2875 // (BCONDA brtarget:$imm, 11) - 44
2876 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2877 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2878 // (BCONDA brtarget:$imm, 3) - 46
2879 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2880 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2881 // (BCONDA brtarget:$imm, 12) - 48
2882 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2883 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2884 // (BCONDA brtarget:$imm, 4) - 50
2885 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2886 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2887 // (BCONDA brtarget:$imm, 13) - 52
2888 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2889 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2890 // (BCONDA brtarget:$imm, 5) - 54
2891 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2892 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2893 // (BCONDA brtarget:$imm, 14) - 56
2894 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2895 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2896 // (BCONDA brtarget:$imm, 6) - 58
2897 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2898 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2899 // (BCONDA brtarget:$imm, 15) - 60
2900 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2901 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2902 // (BCONDA brtarget:$imm, 7) - 62
2903 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2904 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2905 // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc) - 64
2906 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2907 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2908 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2909 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2910 // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc) - 68
2911 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2912 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2913 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2914 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2915 // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc) - 72
2916 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2917 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2918 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2919 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2920 // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc) - 76
2921 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2922 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2923 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2924 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2925 // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc) - 80
2926 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2927 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2928 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2929 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2930 // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc) - 84
2931 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2932 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2933 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2934 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2935 // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc) - 88
2936 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2937 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2938 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2939 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2940 // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc) - 92
2941 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2942 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2943 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2944 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2945 // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc) - 96
2946 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2947 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2948 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2949 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2950 // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc) - 100
2951 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2952 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2953 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2954 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2955 // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc) - 104
2956 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2957 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2958 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2959 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2960 // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc) - 108
2961 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2962 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2963 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2964 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2965 // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc) - 112
2966 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2967 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2968 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2969 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2970 // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc) - 116
2971 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2972 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2973 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2974 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2975 // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc) - 120
2976 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2977 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2978 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2979 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2980 // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc) - 124
2981 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2982 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2983 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2984 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2985 // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc) - 128
2986 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2987 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2988 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2989 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2990 // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc) - 132
2991 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2992 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2993 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2994 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2995 // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc) - 136
2996 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2997 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2998 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2999 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3000 // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc) - 140
3001 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3002 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3003 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3004 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3005 // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc) - 144
3006 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3007 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3008 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3009 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3010 // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc) - 148
3011 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3012 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3013 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3014 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3015 // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc) - 152
3016 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3017 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3018 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3019 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3020 // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc) - 156
3021 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3022 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3023 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3024 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3025 // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc) - 160
3026 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3027 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3028 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3029 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3030 // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc) - 164
3031 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3032 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3033 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3034 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3035 // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc) - 168
3036 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3037 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3038 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3039 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3040 // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc) - 172
3041 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3042 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3043 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3044 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3045 // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc) - 176
3046 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3047 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3048 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3049 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3050 // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc) - 180
3051 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3052 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3053 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3054 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3055 // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc) - 184
3056 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3057 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3058 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3059 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3060 // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc) - 188
3061 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3062 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3063 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3064 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3065 // (BPICCANT brtarget:$imm, 8) - 192
3066 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3067 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3068 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3069 // (BPICCANT brtarget:$imm, 8) - 195
3070 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3071 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3072 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3073 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3074 // (BPICCANT brtarget:$imm, 0) - 199
3075 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3076 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3077 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3078 // (BPICCANT brtarget:$imm, 0) - 202
3079 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3080 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3081 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3082 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3083 // (BPICCANT brtarget:$imm, 9) - 206
3084 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3085 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3086 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3087 // (BPICCANT brtarget:$imm, 9) - 209
3088 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3089 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3090 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3091 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3092 // (BPICCANT brtarget:$imm, 1) - 213
3093 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3094 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3095 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3096 // (BPICCANT brtarget:$imm, 1) - 216
3097 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3098 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3099 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3100 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3101 // (BPICCANT brtarget:$imm, 10) - 220
3102 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3103 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3104 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3105 // (BPICCANT brtarget:$imm, 10) - 223
3106 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3107 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3108 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3109 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3110 // (BPICCANT brtarget:$imm, 2) - 227
3111 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3112 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3113 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3114 // (BPICCANT brtarget:$imm, 2) - 230
3115 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3116 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3117 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3118 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3119 // (BPICCANT brtarget:$imm, 11) - 234
3120 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3121 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3122 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3123 // (BPICCANT brtarget:$imm, 11) - 237
3124 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3125 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3126 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3127 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3128 // (BPICCANT brtarget:$imm, 3) - 241
3129 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3130 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3131 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3132 // (BPICCANT brtarget:$imm, 3) - 244
3133 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3134 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3135 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3136 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3137 // (BPICCANT brtarget:$imm, 12) - 248
3138 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3139 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3140 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3141 // (BPICCANT brtarget:$imm, 12) - 251
3142 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3143 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3144 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3145 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3146 // (BPICCANT brtarget:$imm, 4) - 255
3147 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3148 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3149 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3150 // (BPICCANT brtarget:$imm, 4) - 258
3151 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3152 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3153 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3154 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3155 // (BPICCANT brtarget:$imm, 13) - 262
3156 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3157 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3158 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3159 // (BPICCANT brtarget:$imm, 13) - 265
3160 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3161 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3162 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3163 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3164 // (BPICCANT brtarget:$imm, 5) - 269
3165 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3166 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3167 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3168 // (BPICCANT brtarget:$imm, 5) - 272
3169 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3170 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3171 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3172 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3173 // (BPICCANT brtarget:$imm, 14) - 276
3174 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3175 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3176 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3177 // (BPICCANT brtarget:$imm, 14) - 279
3178 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3179 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3180 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3181 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3182 // (BPICCANT brtarget:$imm, 6) - 283
3183 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3184 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3185 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3186 // (BPICCANT brtarget:$imm, 6) - 286
3187 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3188 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3189 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3190 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3191 // (BPICCANT brtarget:$imm, 15) - 290
3192 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3193 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3194 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3195 // (BPICCANT brtarget:$imm, 15) - 293
3196 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3197 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3198 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3199 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3200 // (BPICCANT brtarget:$imm, 7) - 297
3201 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3202 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3203 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3204 // (BPICCANT brtarget:$imm, 7) - 300
3205 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3206 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3207 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3208 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3209 // (BPICCNT brtarget:$imm, 8) - 304
3210 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3211 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3212 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3213 // (BPICCNT brtarget:$imm, 8) - 307
3214 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3215 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3216 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3217 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3218 // (BPICCNT brtarget:$imm, 0) - 311
3219 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3220 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3221 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3222 // (BPICCNT brtarget:$imm, 0) - 314
3223 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3224 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3225 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3226 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3227 // (BPICCNT brtarget:$imm, 9) - 318
3228 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3229 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3230 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3231 // (BPICCNT brtarget:$imm, 9) - 321
3232 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3233 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3234 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3235 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3236 // (BPICCNT brtarget:$imm, 1) - 325
3237 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3238 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3239 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3240 // (BPICCNT brtarget:$imm, 1) - 328
3241 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3242 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3243 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3244 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3245 // (BPICCNT brtarget:$imm, 10) - 332
3246 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3247 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3248 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3249 // (BPICCNT brtarget:$imm, 10) - 335
3250 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3251 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3252 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3253 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3254 // (BPICCNT brtarget:$imm, 2) - 339
3255 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3256 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3257 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3258 // (BPICCNT brtarget:$imm, 2) - 342
3259 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3260 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3261 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3262 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3263 // (BPICCNT brtarget:$imm, 11) - 346
3264 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3265 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3266 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3267 // (BPICCNT brtarget:$imm, 11) - 349
3268 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3269 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3270 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3271 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3272 // (BPICCNT brtarget:$imm, 3) - 353
3273 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3274 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3275 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3276 // (BPICCNT brtarget:$imm, 3) - 356
3277 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3278 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3279 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3280 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3281 // (BPICCNT brtarget:$imm, 12) - 360
3282 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3283 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3284 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3285 // (BPICCNT brtarget:$imm, 12) - 363
3286 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3287 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3288 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3289 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3290 // (BPICCNT brtarget:$imm, 4) - 367
3291 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3292 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3293 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3294 // (BPICCNT brtarget:$imm, 4) - 370
3295 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3296 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3297 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3298 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3299 // (BPICCNT brtarget:$imm, 13) - 374
3300 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3301 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3302 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3303 // (BPICCNT brtarget:$imm, 13) - 377
3304 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3305 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3306 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3307 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3308 // (BPICCNT brtarget:$imm, 5) - 381
3309 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3310 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3311 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3312 // (BPICCNT brtarget:$imm, 5) - 384
3313 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3314 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3315 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3316 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3317 // (BPICCNT brtarget:$imm, 14) - 388
3318 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3319 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3320 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3321 // (BPICCNT brtarget:$imm, 14) - 391
3322 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3323 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3324 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3325 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3326 // (BPICCNT brtarget:$imm, 6) - 395
3327 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3328 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3329 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3330 // (BPICCNT brtarget:$imm, 6) - 398
3331 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3332 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3333 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3334 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3335 // (BPICCNT brtarget:$imm, 15) - 402
3336 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3337 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3338 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3339 // (BPICCNT brtarget:$imm, 15) - 405
3340 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3341 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3342 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3343 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3344 // (BPICCNT brtarget:$imm, 7) - 409
3345 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3346 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3347 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3348 // (BPICCNT brtarget:$imm, 7) - 412
3349 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3350 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3351 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3352 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3353 // (BPRANT bprtarget16:$imm, 2, I64Regs:$rs1) - 416
3354 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3355 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3356 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3357 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3358 // (BPRANT bprtarget16:$imm, 3, I64Regs:$rs1) - 420
3359 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3360 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3361 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3362 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3363 // (BPRANT bprtarget16:$imm, 6, I64Regs:$rs1) - 424
3364 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3365 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3366 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3367 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3368 // (BPRANT bprtarget16:$imm, 7, I64Regs:$rs1) - 428
3369 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3370 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3371 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3372 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3373 // (BPRNT bprtarget16:$imm, 2, I64Regs:$rs1) - 432
3374 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3375 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3376 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3377 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3378 // (BPRNT bprtarget16:$imm, 3, I64Regs:$rs1) - 436
3379 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3380 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3381 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3382 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3383 // (BPRNT bprtarget16:$imm, 6, I64Regs:$rs1) - 440
3384 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3385 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3386 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3387 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3388 // (BPRNT bprtarget16:$imm, 7, I64Regs:$rs1) - 444
3389 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3390 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3391 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3392 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3393 // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 128) - 448
3394 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3395 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3396 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3397 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3398 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(128)},
3399 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3400 // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 136) - 454
3401 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3402 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3403 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3404 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3405 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(136)},
3406 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3407 // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 128) - 460
3408 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3409 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3410 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3411 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3412 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(128)},
3413 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3414 // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 136) - 466
3415 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3416 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3417 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3418 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3419 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(136)},
3420 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3421 // (CWBCONDri cbtarget:$imm, 9, IntRegs:$rs1, simm5Op:$simm5) - 472
3422 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3423 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3424 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3425 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3426 // (CWBCONDri cbtarget:$imm, 1, IntRegs:$rs1, simm5Op:$simm5) - 476
3427 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3428 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3429 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3430 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3431 // (CWBCONDri cbtarget:$imm, 10, IntRegs:$rs1, simm5Op:$simm5) - 480
3432 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3433 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3434 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3435 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3436 // (CWBCONDri cbtarget:$imm, 2, IntRegs:$rs1, simm5Op:$simm5) - 484
3437 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3438 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3439 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3440 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3441 // (CWBCONDri cbtarget:$imm, 11, IntRegs:$rs1, simm5Op:$simm5) - 488
3442 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3443 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3444 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3445 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3446 // (CWBCONDri cbtarget:$imm, 3, IntRegs:$rs1, simm5Op:$simm5) - 492
3447 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3448 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3449 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3450 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3451 // (CWBCONDri cbtarget:$imm, 12, IntRegs:$rs1, simm5Op:$simm5) - 496
3452 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3453 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3454 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3455 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3456 // (CWBCONDri cbtarget:$imm, 4, IntRegs:$rs1, simm5Op:$simm5) - 500
3457 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3458 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3459 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3460 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3461 // (CWBCONDri cbtarget:$imm, 13, IntRegs:$rs1, simm5Op:$simm5) - 504
3462 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3463 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3464 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3465 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3466 // (CWBCONDri cbtarget:$imm, 5, IntRegs:$rs1, simm5Op:$simm5) - 508
3467 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3468 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3469 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3470 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3471 // (CWBCONDri cbtarget:$imm, 14, IntRegs:$rs1, simm5Op:$simm5) - 512
3472 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3473 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3474 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3475 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3476 // (CWBCONDri cbtarget:$imm, 6, IntRegs:$rs1, simm5Op:$simm5) - 516
3477 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3478 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3479 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3480 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3481 // (CWBCONDri cbtarget:$imm, 15, IntRegs:$rs1, simm5Op:$simm5) - 520
3482 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3483 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3484 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3485 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3486 // (CWBCONDri cbtarget:$imm, 7, IntRegs:$rs1, simm5Op:$simm5) - 524
3487 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3488 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3489 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3490 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3491 // (CWBCONDrr cbtarget:$imm, 9, IntRegs:$rs1, IntRegs:$rs2) - 528
3492 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3493 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3494 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3495 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3496 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3497 // (CWBCONDrr cbtarget:$imm, 1, IntRegs:$rs1, IntRegs:$rs2) - 533
3498 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3499 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3500 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3501 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3502 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3503 // (CWBCONDrr cbtarget:$imm, 10, IntRegs:$rs1, IntRegs:$rs2) - 538
3504 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3505 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3506 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3507 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3508 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3509 // (CWBCONDrr cbtarget:$imm, 2, IntRegs:$rs1, IntRegs:$rs2) - 543
3510 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3511 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3512 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3513 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3514 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3515 // (CWBCONDrr cbtarget:$imm, 11, IntRegs:$rs1, IntRegs:$rs2) - 548
3516 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3517 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3518 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3519 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3520 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3521 // (CWBCONDrr cbtarget:$imm, 3, IntRegs:$rs1, IntRegs:$rs2) - 553
3522 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3523 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3524 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3525 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3526 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3527 // (CWBCONDrr cbtarget:$imm, 12, IntRegs:$rs1, IntRegs:$rs2) - 558
3528 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3529 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3530 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3531 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3532 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3533 // (CWBCONDrr cbtarget:$imm, 4, IntRegs:$rs1, IntRegs:$rs2) - 563
3534 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3535 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3536 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3537 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3538 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3539 // (CWBCONDrr cbtarget:$imm, 13, IntRegs:$rs1, IntRegs:$rs2) - 568
3540 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3541 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3542 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3543 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3544 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3545 // (CWBCONDrr cbtarget:$imm, 5, IntRegs:$rs1, IntRegs:$rs2) - 573
3546 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3547 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3548 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3549 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3550 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3551 // (CWBCONDrr cbtarget:$imm, 14, IntRegs:$rs1, IntRegs:$rs2) - 578
3552 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3553 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3554 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3555 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3556 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3557 // (CWBCONDrr cbtarget:$imm, 6, IntRegs:$rs1, IntRegs:$rs2) - 583
3558 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3559 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3560 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3561 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3562 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3563 // (CWBCONDrr cbtarget:$imm, 15, IntRegs:$rs1, IntRegs:$rs2) - 588
3564 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3565 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3566 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3567 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3568 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3569 // (CWBCONDrr cbtarget:$imm, 7, IntRegs:$rs1, IntRegs:$rs2) - 593
3570 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3571 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3572 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3573 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3574 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3575 // (CXBCONDri cbtarget:$imm, 9, IntRegs:$rs1, simm5Op:$simm5) - 598
3576 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3577 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3578 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3579 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3580 // (CXBCONDri cbtarget:$imm, 1, IntRegs:$rs1, simm5Op:$simm5) - 602
3581 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3582 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3583 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3584 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3585 // (CXBCONDri cbtarget:$imm, 10, IntRegs:$rs1, simm5Op:$simm5) - 606
3586 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3587 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3588 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3589 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3590 // (CXBCONDri cbtarget:$imm, 2, IntRegs:$rs1, simm5Op:$simm5) - 610
3591 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3592 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3593 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3594 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3595 // (CXBCONDri cbtarget:$imm, 11, IntRegs:$rs1, simm5Op:$simm5) - 614
3596 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3597 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3598 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3599 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3600 // (CXBCONDri cbtarget:$imm, 3, IntRegs:$rs1, simm5Op:$simm5) - 618
3601 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3602 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3603 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3604 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3605 // (CXBCONDri cbtarget:$imm, 12, IntRegs:$rs1, simm5Op:$simm5) - 622
3606 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3607 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3608 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3609 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3610 // (CXBCONDri cbtarget:$imm, 4, IntRegs:$rs1, simm5Op:$simm5) - 626
3611 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3612 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3613 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3614 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3615 // (CXBCONDri cbtarget:$imm, 13, IntRegs:$rs1, simm5Op:$simm5) - 630
3616 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3617 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3618 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3619 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3620 // (CXBCONDri cbtarget:$imm, 5, IntRegs:$rs1, simm5Op:$simm5) - 634
3621 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3622 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3623 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3624 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3625 // (CXBCONDri cbtarget:$imm, 14, IntRegs:$rs1, simm5Op:$simm5) - 638
3626 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3627 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3628 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3629 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3630 // (CXBCONDri cbtarget:$imm, 6, IntRegs:$rs1, simm5Op:$simm5) - 642
3631 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3632 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3633 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3634 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3635 // (CXBCONDri cbtarget:$imm, 15, IntRegs:$rs1, simm5Op:$simm5) - 646
3636 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3637 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3638 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3639 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3640 // (CXBCONDri cbtarget:$imm, 7, IntRegs:$rs1, simm5Op:$simm5) - 650
3641 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3642 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3643 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3644 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3645 // (CXBCONDrr cbtarget:$imm, 9, IntRegs:$rs1, IntRegs:$rs2) - 654
3646 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3647 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3648 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3649 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3650 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3651 // (CXBCONDrr cbtarget:$imm, 1, IntRegs:$rs1, IntRegs:$rs2) - 659
3652 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3653 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3654 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3655 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3656 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3657 // (CXBCONDrr cbtarget:$imm, 10, IntRegs:$rs1, IntRegs:$rs2) - 664
3658 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3659 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3660 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3661 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3662 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3663 // (CXBCONDrr cbtarget:$imm, 2, IntRegs:$rs1, IntRegs:$rs2) - 669
3664 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3665 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3666 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3667 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3668 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3669 // (CXBCONDrr cbtarget:$imm, 11, IntRegs:$rs1, IntRegs:$rs2) - 674
3670 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3671 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3672 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3673 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3674 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3675 // (CXBCONDrr cbtarget:$imm, 3, IntRegs:$rs1, IntRegs:$rs2) - 679
3676 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3677 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3678 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3679 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3680 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3681 // (CXBCONDrr cbtarget:$imm, 12, IntRegs:$rs1, IntRegs:$rs2) - 684
3682 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3683 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3684 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3685 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3686 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3687 // (CXBCONDrr cbtarget:$imm, 4, IntRegs:$rs1, IntRegs:$rs2) - 689
3688 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3689 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3690 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3691 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3692 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3693 // (CXBCONDrr cbtarget:$imm, 13, IntRegs:$rs1, IntRegs:$rs2) - 694
3694 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3695 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3696 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3697 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3698 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3699 // (CXBCONDrr cbtarget:$imm, 5, IntRegs:$rs1, IntRegs:$rs2) - 699
3700 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3701 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3702 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3703 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3704 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3705 // (CXBCONDrr cbtarget:$imm, 14, IntRegs:$rs1, IntRegs:$rs2) - 704
3706 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3707 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3708 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3709 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3710 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3711 // (CXBCONDrr cbtarget:$imm, 6, IntRegs:$rs1, IntRegs:$rs2) - 709
3712 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3713 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3714 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3715 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3716 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3717 // (CXBCONDrr cbtarget:$imm, 15, IntRegs:$rs1, IntRegs:$rs2) - 714
3718 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3719 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3720 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3721 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3722 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3723 // (CXBCONDrr cbtarget:$imm, 7, IntRegs:$rs1, IntRegs:$rs2) - 719
3724 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3725 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3726 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3727 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3728 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3729 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8) - 724
3730 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3731 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3732 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3733 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3734 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3735 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8) - 729
3736 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3737 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3738 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3739 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3740 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3741 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3742 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0) - 735
3743 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3744 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3745 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3746 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3747 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3748 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0) - 740
3749 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3750 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3751 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3752 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3753 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3754 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3755 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9) - 746
3756 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3757 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3758 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3759 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3760 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3761 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9) - 751
3762 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3763 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3764 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3765 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3766 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3767 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3768 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1) - 757
3769 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3770 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3771 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3772 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3773 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3774 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1) - 762
3775 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3776 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3777 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3778 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3779 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3780 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3781 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10) - 768
3782 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3783 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3784 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3785 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3786 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3787 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10) - 773
3788 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3789 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3790 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3791 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3792 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3793 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3794 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2) - 779
3795 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3796 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3797 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3798 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3799 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3800 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2) - 784
3801 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3802 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3803 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3804 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3805 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3806 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3807 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11) - 790
3808 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3809 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3810 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3811 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3812 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3813 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11) - 795
3814 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3815 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3816 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3817 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3818 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3819 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3820 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3) - 801
3821 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3822 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3823 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3824 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3825 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3826 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3) - 806
3827 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3828 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3829 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3830 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3831 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3832 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3833 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12) - 812
3834 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3835 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3836 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3837 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3838 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3839 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12) - 817
3840 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3841 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3842 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3843 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3844 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3845 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3846 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4) - 823
3847 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3848 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3849 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3850 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3851 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3852 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4) - 828
3853 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3854 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3855 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3856 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3857 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3858 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3859 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13) - 834
3860 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3861 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3862 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3863 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3864 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3865 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13) - 839
3866 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3867 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3868 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3869 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3870 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3871 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3872 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5) - 845
3873 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3874 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3875 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3876 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3877 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3878 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5) - 850
3879 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3880 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3881 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3882 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3883 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3884 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3885 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14) - 856
3886 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3887 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3888 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3889 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3890 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3891 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14) - 861
3892 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3893 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3894 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3895 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3896 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3897 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3898 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6) - 867
3899 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3900 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3901 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3902 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3903 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3904 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6) - 872
3905 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3906 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3907 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3908 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3909 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3910 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3911 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15) - 878
3912 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3913 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3914 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3915 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3916 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3917 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15) - 883
3918 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3919 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3920 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3921 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3922 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3923 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3924 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7) - 889
3925 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3926 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3927 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3928 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3929 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3930 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7) - 894
3931 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3932 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3933 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3934 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3935 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3936 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3937 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8) - 900
3938 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3939 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3940 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3941 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3942 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3943 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8) - 905
3944 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3945 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3946 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3947 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3948 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3949 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3950 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0) - 911
3951 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3952 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3953 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3954 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3955 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3956 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0) - 916
3957 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3958 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3959 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3960 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3961 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3962 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3963 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9) - 922
3964 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3965 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3966 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3967 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3968 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3969 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9) - 927
3970 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3971 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3972 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3973 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3974 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3975 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3976 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1) - 933
3977 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3978 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3979 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3980 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3981 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3982 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1) - 938
3983 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3984 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3985 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3986 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3987 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3988 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3989 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10) - 944
3990 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3991 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3992 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3993 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3994 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3995 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10) - 949
3996 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3997 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3998 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3999 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4000 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4001 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4002 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2) - 955
4003 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4004 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4005 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4006 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4007 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4008 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2) - 960
4009 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4010 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4011 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4012 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4013 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4014 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4015 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11) - 966
4016 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4017 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4018 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4019 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4020 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4021 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11) - 971
4022 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4023 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4024 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4025 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4026 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4027 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4028 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3) - 977
4029 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4030 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4031 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4032 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4033 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4034 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3) - 982
4035 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4036 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4037 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4038 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4039 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4040 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4041 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12) - 988
4042 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4043 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4044 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4045 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4046 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4047 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12) - 993
4048 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4049 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4050 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4051 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4052 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4053 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4054 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4) - 999
4055 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4056 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4057 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4058 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4059 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4060 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4) - 1004
4061 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4062 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4063 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4064 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4065 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4066 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4067 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13) - 1010
4068 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4069 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4070 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4071 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4072 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4073 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13) - 1015
4074 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4075 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4076 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4077 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4078 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4079 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4080 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5) - 1021
4081 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4082 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4083 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4084 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4085 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4086 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5) - 1026
4087 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4088 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4089 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4090 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4091 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4092 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4093 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14) - 1032
4094 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4095 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4096 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4097 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4098 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4099 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14) - 1037
4100 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4101 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4102 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4103 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4104 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4105 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4106 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6) - 1043
4107 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4108 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4109 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4110 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4111 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4112 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6) - 1048
4113 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4114 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4115 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4116 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4117 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4118 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4119 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15) - 1054
4120 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4121 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4122 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4123 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4124 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4125 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15) - 1059
4126 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4127 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4128 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4129 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4130 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4131 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4132 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7) - 1065
4133 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4134 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4135 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4136 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4137 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4138 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7) - 1070
4139 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4140 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4141 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4142 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4143 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4144 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4145 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 2) - 1076
4146 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4147 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4148 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4149 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4150 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4151 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4152 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 3) - 1082
4153 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4154 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4155 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4156 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4157 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4158 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4159 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 6) - 1088
4160 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4161 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4162 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4163 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4164 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4165 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4166 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 7) - 1094
4167 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4168 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4169 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4170 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4171 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4172 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4173 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 2) - 1100
4174 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4175 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4176 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4177 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4178 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4179 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4180 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 3) - 1106
4181 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4182 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4183 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4184 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4185 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4186 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4187 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 6) - 1112
4188 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4189 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4190 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4191 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4192 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4193 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4194 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 7) - 1118
4195 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4196 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4197 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4198 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4199 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4200 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4201 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 2) - 1124
4202 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4203 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4204 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4205 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4206 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4207 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4208 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 3) - 1130
4209 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4210 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4211 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4212 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4213 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4214 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4215 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 6) - 1136
4216 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4217 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4218 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4219 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4220 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4221 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4222 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 7) - 1142
4223 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4224 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4225 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4226 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4227 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4228 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4229 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8) - 1148
4230 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4231 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4232 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4233 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4234 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4235 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8) - 1153
4236 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4237 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4238 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4239 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4240 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4241 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4242 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0) - 1159
4243 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4244 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4245 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4246 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4247 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4248 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0) - 1164
4249 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4250 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4251 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4252 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4253 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4254 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4255 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9) - 1170
4256 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4257 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4258 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4259 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4260 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4261 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9) - 1175
4262 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4263 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4264 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4265 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4266 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4267 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4268 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1) - 1181
4269 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4270 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4271 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4272 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4273 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4274 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1) - 1186
4275 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4276 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4277 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4278 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4279 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4280 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4281 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10) - 1192
4282 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4283 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4284 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4285 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4286 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4287 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10) - 1197
4288 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4289 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4290 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4291 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4292 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4293 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4294 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2) - 1203
4295 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4296 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4297 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4298 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4299 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4300 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2) - 1208
4301 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4302 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4303 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4304 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4305 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4306 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4307 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11) - 1214
4308 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4309 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4310 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4311 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4312 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4313 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11) - 1219
4314 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4315 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4316 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4317 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4318 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4319 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4320 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3) - 1225
4321 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4322 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4323 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4324 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4325 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4326 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3) - 1230
4327 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4328 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4329 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4330 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4331 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4332 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4333 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12) - 1236
4334 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4335 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4336 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4337 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4338 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4339 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12) - 1241
4340 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4341 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4342 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4343 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4344 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4345 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4346 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4) - 1247
4347 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4348 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4349 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4350 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4351 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4352 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4) - 1252
4353 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4354 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4355 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4356 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4357 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4358 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4359 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13) - 1258
4360 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4361 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4362 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4363 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4364 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4365 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13) - 1263
4366 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4367 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4368 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4369 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4370 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4371 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4372 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5) - 1269
4373 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4374 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4375 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4376 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4377 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4378 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5) - 1274
4379 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4380 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4381 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4382 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4383 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4384 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4385 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14) - 1280
4386 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4387 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4388 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4389 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4390 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4391 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14) - 1285
4392 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4393 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4394 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4395 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4396 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4397 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4398 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6) - 1291
4399 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4400 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4401 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4402 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4403 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4404 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6) - 1296
4405 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4406 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4407 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4408 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4409 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4410 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4411 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15) - 1302
4412 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4413 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4414 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4415 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4416 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4417 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15) - 1307
4418 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4419 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4420 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4421 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4422 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4423 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4424 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7) - 1313
4425 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4426 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4427 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4428 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4429 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4430 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7) - 1318
4431 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4432 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4433 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4434 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4435 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4436 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4437 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8) - 1324
4438 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4439 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4440 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4441 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4442 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4443 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8) - 1329
4444 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4445 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4446 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4447 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4448 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4449 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4450 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0) - 1335
4451 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4452 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4453 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4454 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4455 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4456 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0) - 1340
4457 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4458 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4459 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4460 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4461 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4462 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4463 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9) - 1346
4464 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4465 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4466 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4467 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4468 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4469 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9) - 1351
4470 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4471 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4472 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4473 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4474 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4475 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4476 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1) - 1357
4477 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4478 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4479 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4480 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4481 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4482 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1) - 1362
4483 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4484 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4485 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4486 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4487 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4488 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4489 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10) - 1368
4490 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4491 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4492 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4493 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4494 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4495 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10) - 1373
4496 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4497 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4498 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4499 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4500 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4501 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4502 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2) - 1379
4503 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4504 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4505 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4506 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4507 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4508 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2) - 1384
4509 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4510 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4511 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4512 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4513 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4514 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4515 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11) - 1390
4516 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4517 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4518 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4519 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4520 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4521 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11) - 1395
4522 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4523 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4524 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4525 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4526 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4527 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4528 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3) - 1401
4529 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4530 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4531 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4532 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4533 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4534 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3) - 1406
4535 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4536 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4537 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4538 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4539 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4540 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4541 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12) - 1412
4542 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4543 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4544 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4545 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4546 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4547 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12) - 1417
4548 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4549 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4550 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4551 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4552 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4553 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4554 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4) - 1423
4555 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4556 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4557 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4558 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4559 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4560 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4) - 1428
4561 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4562 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4563 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4564 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4565 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4566 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4567 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13) - 1434
4568 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4569 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4570 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4571 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4572 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4573 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13) - 1439
4574 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4575 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4576 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4577 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4578 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4579 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4580 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5) - 1445
4581 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4582 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4583 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4584 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4585 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4586 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5) - 1450
4587 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4588 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4589 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4590 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4591 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4592 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4593 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14) - 1456
4594 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4595 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4596 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4597 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4598 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4599 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14) - 1461
4600 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4601 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4602 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4603 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4604 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4605 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4606 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6) - 1467
4607 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4608 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4609 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4610 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4611 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4612 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6) - 1472
4613 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4614 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4615 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4616 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4617 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4618 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4619 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15) - 1478
4620 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4621 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4622 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4623 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4624 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4625 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15) - 1483
4626 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4627 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4628 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4629 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4630 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4631 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4632 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7) - 1489
4633 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4634 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4635 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4636 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4637 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4638 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7) - 1494
4639 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4640 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4641 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4642 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4643 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4644 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4645 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1500
4646 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4647 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4648 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4649 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4650 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4651 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1505
4652 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4653 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4654 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4655 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4656 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4657 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4658 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1511
4659 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4660 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4661 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4662 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4663 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4664 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1516
4665 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4666 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4667 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4668 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4669 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4670 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4671 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1522
4672 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4673 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4674 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4675 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4676 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4677 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1527
4678 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4679 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4680 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4681 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4682 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4683 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4684 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1533
4685 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4686 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4687 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4688 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4689 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4690 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1538
4691 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4692 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4693 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4694 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4695 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4696 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4697 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1544
4698 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4699 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4700 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4701 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4702 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4703 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1549
4704 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4705 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4706 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4707 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4708 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4709 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4710 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1555
4711 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4712 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4713 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4714 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4715 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4716 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1560
4717 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4718 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4719 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4720 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4721 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4722 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4723 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1566
4724 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4725 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4726 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4727 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4728 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4729 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1571
4730 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4731 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4732 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4733 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4734 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4735 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4736 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1577
4737 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4738 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4739 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4740 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4741 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4742 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1582
4743 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4744 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4745 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4746 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4747 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4748 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4749 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1588
4750 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4751 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4752 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4753 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4754 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4755 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1593
4756 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4757 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4758 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4759 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4760 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4761 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4762 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1599
4763 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4764 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4765 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4766 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4767 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4768 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1604
4769 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4770 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4771 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4772 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4773 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4774 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4775 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1610
4776 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4777 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4778 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4779 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4780 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4781 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1615
4782 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4783 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4784 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4785 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4786 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4787 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4788 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1621
4789 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4790 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4791 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4792 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4793 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4794 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1626
4795 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4796 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4797 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4798 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4799 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4800 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4801 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1632
4802 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4803 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4804 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4805 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4806 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4807 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1637
4808 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4809 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4810 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4811 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4812 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4813 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4814 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1643
4815 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4816 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4817 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4818 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4819 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4820 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1648
4821 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4822 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4823 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4824 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4825 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4826 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4827 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1654
4828 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4829 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4830 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4831 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4832 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4833 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1659
4834 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4835 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4836 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4837 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4838 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4839 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4840 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1665
4841 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4842 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4843 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4844 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4845 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4846 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1670
4847 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4848 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4849 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4850 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4851 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4852 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4853 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 2) - 1676
4854 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4855 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4856 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4857 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4858 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4859 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4860 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 3) - 1682
4861 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4862 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4863 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4864 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4865 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4866 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4867 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 6) - 1688
4868 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4869 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4870 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4871 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4872 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4873 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4874 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 7) - 1694
4875 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4876 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4877 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4878 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4879 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4880 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4881 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 2) - 1700
4882 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4883 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4884 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4885 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4886 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4887 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4888 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 3) - 1706
4889 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4890 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4891 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4892 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4893 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4894 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4895 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 6) - 1712
4896 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4897 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4898 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4899 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4900 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4901 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4902 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 7) - 1718
4903 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4904 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4905 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4906 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4907 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4908 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4909 // (ORCCrr G0, IntRegs:$rs2, G0) - 1724
4910 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4911 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4912 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4913 // (ORri IntRegs:$rd, G0, simm13Op:$simm13) - 1727
4914 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4915 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4916 // (ORrr IntRegs:$rd, G0, IntRegs:$rs2) - 1729
4917 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4918 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4919 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4920 // (RESTORErr G0, G0, G0) - 1732
4921 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4922 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4923 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4924 // (RET 8) - 1735
4925 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4926 // (RETL 8) - 1736
4927 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4928 // (SAVErr G0, G0, G0) - 1737
4929 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4930 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4931 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4932 // (SUBCCri G0, IntRegs:$rs1, simm13Op:$imm) - 1740
4933 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4934 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4935 // (SUBCCrr G0, IntRegs:$rs1, IntRegs:$rs2) - 1742
4936 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4937 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4938 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4939 // (TICCri G0, i32imm:$imm, 8) - 1745
4940 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4941 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4942 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4943 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4944 // (TICCri G0, i32imm:$imm, 8) - 1749
4945 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4946 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4947 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4948 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4949 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4950 // (TICCri IntRegs:$rs1, i32imm:$imm, 8) - 1754
4951 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4952 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4953 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4954 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4955 // (TICCri IntRegs:$rs1, i32imm:$imm, 8) - 1758
4956 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4957 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4958 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4959 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4960 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4961 // (TICCri G0, i32imm:$imm, 0) - 1763
4962 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4963 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4964 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4965 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4966 // (TICCri G0, i32imm:$imm, 0) - 1767
4967 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4968 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4969 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4970 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4971 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4972 // (TICCri IntRegs:$rs1, i32imm:$imm, 0) - 1772
4973 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4974 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4975 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4976 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4977 // (TICCri IntRegs:$rs1, i32imm:$imm, 0) - 1776
4978 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4979 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4980 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4981 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4982 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4983 // (TICCri G0, i32imm:$imm, 9) - 1781
4984 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4985 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4986 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4987 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4988 // (TICCri G0, i32imm:$imm, 9) - 1785
4989 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4990 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4991 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4992 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4993 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4994 // (TICCri IntRegs:$rs1, i32imm:$imm, 9) - 1790
4995 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4996 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4997 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4998 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4999 // (TICCri IntRegs:$rs1, i32imm:$imm, 9) - 1794
5000 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5001 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5002 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5003 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5004 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5005 // (TICCri G0, i32imm:$imm, 1) - 1799
5006 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5007 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5008 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5009 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5010 // (TICCri G0, i32imm:$imm, 1) - 1803
5011 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5012 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5013 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5014 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5015 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5016 // (TICCri IntRegs:$rs1, i32imm:$imm, 1) - 1808
5017 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5018 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5019 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5020 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5021 // (TICCri IntRegs:$rs1, i32imm:$imm, 1) - 1812
5022 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5023 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5024 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5025 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5026 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5027 // (TICCri G0, i32imm:$imm, 10) - 1817
5028 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5029 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5030 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5031 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5032 // (TICCri G0, i32imm:$imm, 10) - 1821
5033 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5034 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5035 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5036 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5037 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5038 // (TICCri IntRegs:$rs1, i32imm:$imm, 10) - 1826
5039 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5040 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5041 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5042 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5043 // (TICCri IntRegs:$rs1, i32imm:$imm, 10) - 1830
5044 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5045 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5046 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5047 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5048 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5049 // (TICCri G0, i32imm:$imm, 2) - 1835
5050 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5051 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5052 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5053 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5054 // (TICCri G0, i32imm:$imm, 2) - 1839
5055 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5056 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5057 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5058 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5059 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5060 // (TICCri IntRegs:$rs1, i32imm:$imm, 2) - 1844
5061 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5062 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5063 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5064 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5065 // (TICCri IntRegs:$rs1, i32imm:$imm, 2) - 1848
5066 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5067 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5068 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5069 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5070 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5071 // (TICCri G0, i32imm:$imm, 11) - 1853
5072 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5073 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5074 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5075 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5076 // (TICCri G0, i32imm:$imm, 11) - 1857
5077 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5078 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5079 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5080 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5081 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5082 // (TICCri IntRegs:$rs1, i32imm:$imm, 11) - 1862
5083 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5084 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5085 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5086 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5087 // (TICCri IntRegs:$rs1, i32imm:$imm, 11) - 1866
5088 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5089 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5090 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5091 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5092 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5093 // (TICCri G0, i32imm:$imm, 3) - 1871
5094 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5095 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5096 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5097 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5098 // (TICCri G0, i32imm:$imm, 3) - 1875
5099 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5100 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5101 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5102 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5103 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5104 // (TICCri IntRegs:$rs1, i32imm:$imm, 3) - 1880
5105 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5106 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5107 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5108 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5109 // (TICCri IntRegs:$rs1, i32imm:$imm, 3) - 1884
5110 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5111 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5112 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5113 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5114 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5115 // (TICCri G0, i32imm:$imm, 12) - 1889
5116 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5117 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5118 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5119 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5120 // (TICCri G0, i32imm:$imm, 12) - 1893
5121 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5122 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5123 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5124 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5125 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5126 // (TICCri IntRegs:$rs1, i32imm:$imm, 12) - 1898
5127 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5128 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5129 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5130 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5131 // (TICCri IntRegs:$rs1, i32imm:$imm, 12) - 1902
5132 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5133 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5134 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5135 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5136 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5137 // (TICCri G0, i32imm:$imm, 4) - 1907
5138 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5139 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5140 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5141 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5142 // (TICCri G0, i32imm:$imm, 4) - 1911
5143 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5144 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5145 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5146 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5147 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5148 // (TICCri IntRegs:$rs1, i32imm:$imm, 4) - 1916
5149 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5150 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5151 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5152 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5153 // (TICCri IntRegs:$rs1, i32imm:$imm, 4) - 1920
5154 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5155 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5156 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5157 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5158 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5159 // (TICCri G0, i32imm:$imm, 13) - 1925
5160 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5161 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5162 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5163 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5164 // (TICCri G0, i32imm:$imm, 13) - 1929
5165 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5166 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5167 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5168 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5169 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5170 // (TICCri IntRegs:$rs1, i32imm:$imm, 13) - 1934
5171 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5172 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5173 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5174 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5175 // (TICCri IntRegs:$rs1, i32imm:$imm, 13) - 1938
5176 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5177 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5178 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5179 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5180 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5181 // (TICCri G0, i32imm:$imm, 5) - 1943
5182 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5183 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5184 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5185 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5186 // (TICCri G0, i32imm:$imm, 5) - 1947
5187 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5188 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5189 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5190 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5191 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5192 // (TICCri IntRegs:$rs1, i32imm:$imm, 5) - 1952
5193 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5194 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5195 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5196 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5197 // (TICCri IntRegs:$rs1, i32imm:$imm, 5) - 1956
5198 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5199 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5200 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5201 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5202 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5203 // (TICCri G0, i32imm:$imm, 14) - 1961
5204 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5205 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5206 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5207 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5208 // (TICCri G0, i32imm:$imm, 14) - 1965
5209 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5210 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5211 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5212 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5213 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5214 // (TICCri IntRegs:$rs1, i32imm:$imm, 14) - 1970
5215 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5216 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5217 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5218 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5219 // (TICCri IntRegs:$rs1, i32imm:$imm, 14) - 1974
5220 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5221 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5222 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5223 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5224 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5225 // (TICCri G0, i32imm:$imm, 6) - 1979
5226 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5227 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5228 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5229 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5230 // (TICCri G0, i32imm:$imm, 6) - 1983
5231 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5232 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5233 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5234 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5235 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5236 // (TICCri IntRegs:$rs1, i32imm:$imm, 6) - 1988
5237 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5238 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5239 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5240 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5241 // (TICCri IntRegs:$rs1, i32imm:$imm, 6) - 1992
5242 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5243 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5244 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5245 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5246 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5247 // (TICCri G0, i32imm:$imm, 15) - 1997
5248 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5249 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5250 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5251 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5252 // (TICCri G0, i32imm:$imm, 15) - 2001
5253 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5254 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5255 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5256 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5257 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5258 // (TICCri IntRegs:$rs1, i32imm:$imm, 15) - 2006
5259 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5260 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5261 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5262 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5263 // (TICCri IntRegs:$rs1, i32imm:$imm, 15) - 2010
5264 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5265 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5266 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5267 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5268 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5269 // (TICCri G0, i32imm:$imm, 7) - 2015
5270 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5271 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5272 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5273 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5274 // (TICCri G0, i32imm:$imm, 7) - 2019
5275 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5276 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5277 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5278 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5279 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5280 // (TICCri IntRegs:$rs1, i32imm:$imm, 7) - 2024
5281 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5282 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5283 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5284 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5285 // (TICCri IntRegs:$rs1, i32imm:$imm, 7) - 2028
5286 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5287 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5288 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5289 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5290 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5291 // (TICCrr G0, IntRegs:$rs2, 8) - 2033
5292 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5293 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5294 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5295 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5296 // (TICCrr G0, IntRegs:$rs2, 8) - 2037
5297 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5298 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5299 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5300 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5301 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5302 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2042
5303 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5304 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5305 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5306 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5307 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2046
5308 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5309 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5310 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5311 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5312 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5313 // (TICCrr G0, IntRegs:$rs2, 0) - 2051
5314 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5315 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5316 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5317 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5318 // (TICCrr G0, IntRegs:$rs2, 0) - 2055
5319 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5320 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5321 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5322 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5323 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5324 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2060
5325 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5326 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5327 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5328 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5329 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2064
5330 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5331 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5332 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5333 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5334 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5335 // (TICCrr G0, IntRegs:$rs2, 9) - 2069
5336 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5337 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5338 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5339 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5340 // (TICCrr G0, IntRegs:$rs2, 9) - 2073
5341 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5342 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5343 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5344 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5345 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5346 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2078
5347 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5348 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5349 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5350 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5351 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2082
5352 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5353 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5354 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5355 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5356 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5357 // (TICCrr G0, IntRegs:$rs2, 1) - 2087
5358 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5359 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5360 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5361 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5362 // (TICCrr G0, IntRegs:$rs2, 1) - 2091
5363 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5364 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5365 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5366 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5367 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5368 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2096
5369 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5370 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5371 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5372 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5373 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2100
5374 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5375 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5376 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5377 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5378 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5379 // (TICCrr G0, IntRegs:$rs2, 10) - 2105
5380 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5381 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5382 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5383 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5384 // (TICCrr G0, IntRegs:$rs2, 10) - 2109
5385 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5386 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5387 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5388 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5389 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5390 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2114
5391 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5392 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5393 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5394 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5395 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2118
5396 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5397 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5398 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5399 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5400 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5401 // (TICCrr G0, IntRegs:$rs2, 2) - 2123
5402 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5403 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5404 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5405 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5406 // (TICCrr G0, IntRegs:$rs2, 2) - 2127
5407 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5408 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5409 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5410 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5411 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5412 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2132
5413 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5414 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5415 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5416 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5417 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2136
5418 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5419 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5420 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5421 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5422 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5423 // (TICCrr G0, IntRegs:$rs2, 11) - 2141
5424 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5425 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5426 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5427 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5428 // (TICCrr G0, IntRegs:$rs2, 11) - 2145
5429 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5430 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5431 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5432 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5433 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5434 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2150
5435 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5436 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5437 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5438 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5439 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2154
5440 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5441 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5442 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5443 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5444 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5445 // (TICCrr G0, IntRegs:$rs2, 3) - 2159
5446 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5447 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5448 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5449 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5450 // (TICCrr G0, IntRegs:$rs2, 3) - 2163
5451 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5452 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5453 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5454 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5455 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5456 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2168
5457 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5458 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5459 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5460 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5461 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2172
5462 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5463 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5464 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5465 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5466 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5467 // (TICCrr G0, IntRegs:$rs2, 12) - 2177
5468 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5469 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5470 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5471 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5472 // (TICCrr G0, IntRegs:$rs2, 12) - 2181
5473 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5474 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5475 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5476 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5477 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5478 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2186
5479 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5480 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5481 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5482 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5483 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2190
5484 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5485 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5486 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5487 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5488 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5489 // (TICCrr G0, IntRegs:$rs2, 4) - 2195
5490 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5491 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5492 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5493 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5494 // (TICCrr G0, IntRegs:$rs2, 4) - 2199
5495 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5496 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5497 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5498 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5499 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5500 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2204
5501 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5502 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5503 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5504 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5505 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2208
5506 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5507 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5508 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5509 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5510 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5511 // (TICCrr G0, IntRegs:$rs2, 13) - 2213
5512 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5513 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5514 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5515 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5516 // (TICCrr G0, IntRegs:$rs2, 13) - 2217
5517 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5518 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5519 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5520 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5521 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5522 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2222
5523 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5524 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5525 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5526 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5527 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2226
5528 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5529 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5530 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5531 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5532 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5533 // (TICCrr G0, IntRegs:$rs2, 5) - 2231
5534 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5535 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5536 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5537 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5538 // (TICCrr G0, IntRegs:$rs2, 5) - 2235
5539 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5540 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5541 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5542 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5543 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5544 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 2240
5545 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5546 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5547 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5548 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5549 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 2244
5550 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5551 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5552 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5553 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5554 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5555 // (TICCrr G0, IntRegs:$rs2, 14) - 2249
5556 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5557 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5558 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5559 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5560 // (TICCrr G0, IntRegs:$rs2, 14) - 2253
5561 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5562 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5563 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5564 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5565 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5566 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 2258
5567 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5568 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5569 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5570 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5571 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 2262
5572 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5573 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5574 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5575 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5576 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5577 // (TICCrr G0, IntRegs:$rs2, 6) - 2267
5578 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5579 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5580 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5581 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5582 // (TICCrr G0, IntRegs:$rs2, 6) - 2271
5583 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5584 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5585 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5586 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5587 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5588 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 2276
5589 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5590 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5591 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5592 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5593 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 2280
5594 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5595 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5596 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5597 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5598 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5599 // (TICCrr G0, IntRegs:$rs2, 15) - 2285
5600 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5601 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5602 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5603 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5604 // (TICCrr G0, IntRegs:$rs2, 15) - 2289
5605 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5606 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5607 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5608 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5609 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5610 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 2294
5611 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5612 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5613 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5614 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5615 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 2298
5616 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5617 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5618 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5619 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5620 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5621 // (TICCrr G0, IntRegs:$rs2, 7) - 2303
5622 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5623 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5624 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5625 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5626 // (TICCrr G0, IntRegs:$rs2, 7) - 2307
5627 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5628 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5629 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5630 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5631 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5632 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 2312
5633 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5634 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5635 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5636 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5637 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 2316
5638 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5639 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5640 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5641 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5642 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5643 // (TRAPri G0, i32imm:$imm, 8) - 2321
5644 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5645 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5646 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5647 // (TRAPri IntRegs:$rs1, i32imm:$imm, 8) - 2324
5648 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5649 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5650 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5651 // (TRAPri G0, i32imm:$imm, 0) - 2327
5652 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5653 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5654 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5655 // (TRAPri IntRegs:$rs1, i32imm:$imm, 0) - 2330
5656 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5657 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5658 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5659 // (TRAPri G0, i32imm:$imm, 9) - 2333
5660 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5661 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5662 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5663 // (TRAPri IntRegs:$rs1, i32imm:$imm, 9) - 2336
5664 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5665 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5666 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5667 // (TRAPri G0, i32imm:$imm, 1) - 2339
5668 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5669 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5670 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5671 // (TRAPri IntRegs:$rs1, i32imm:$imm, 1) - 2342
5672 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5673 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5674 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5675 // (TRAPri G0, i32imm:$imm, 10) - 2345
5676 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5677 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5678 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5679 // (TRAPri IntRegs:$rs1, i32imm:$imm, 10) - 2348
5680 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5681 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5682 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5683 // (TRAPri G0, i32imm:$imm, 2) - 2351
5684 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5685 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5686 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5687 // (TRAPri IntRegs:$rs1, i32imm:$imm, 2) - 2354
5688 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5689 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5690 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5691 // (TRAPri G0, i32imm:$imm, 11) - 2357
5692 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5693 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5694 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5695 // (TRAPri IntRegs:$rs1, i32imm:$imm, 11) - 2360
5696 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5697 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5698 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5699 // (TRAPri G0, i32imm:$imm, 3) - 2363
5700 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5701 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5702 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5703 // (TRAPri IntRegs:$rs1, i32imm:$imm, 3) - 2366
5704 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5705 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5706 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5707 // (TRAPri G0, i32imm:$imm, 12) - 2369
5708 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5709 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5710 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5711 // (TRAPri IntRegs:$rs1, i32imm:$imm, 12) - 2372
5712 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5713 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5714 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5715 // (TRAPri G0, i32imm:$imm, 4) - 2375
5716 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5717 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5718 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5719 // (TRAPri IntRegs:$rs1, i32imm:$imm, 4) - 2378
5720 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5721 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5722 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5723 // (TRAPri G0, i32imm:$imm, 13) - 2381
5724 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5725 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5726 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5727 // (TRAPri IntRegs:$rs1, i32imm:$imm, 13) - 2384
5728 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5729 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5730 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5731 // (TRAPri G0, i32imm:$imm, 5) - 2387
5732 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5733 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5734 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5735 // (TRAPri IntRegs:$rs1, i32imm:$imm, 5) - 2390
5736 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5737 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5738 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5739 // (TRAPri G0, i32imm:$imm, 14) - 2393
5740 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5741 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5742 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5743 // (TRAPri IntRegs:$rs1, i32imm:$imm, 14) - 2396
5744 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5745 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5746 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5747 // (TRAPri G0, i32imm:$imm, 6) - 2399
5748 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5749 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5750 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5751 // (TRAPri IntRegs:$rs1, i32imm:$imm, 6) - 2402
5752 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5753 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5754 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5755 // (TRAPri G0, i32imm:$imm, 15) - 2405
5756 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5757 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5758 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5759 // (TRAPri IntRegs:$rs1, i32imm:$imm, 15) - 2408
5760 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5761 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5762 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5763 // (TRAPri G0, i32imm:$imm, 7) - 2411
5764 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5765 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5766 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5767 // (TRAPri IntRegs:$rs1, i32imm:$imm, 7) - 2414
5768 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5769 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5770 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5771 // (TRAPrr G0, IntRegs:$rs1, 8) - 2417
5772 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5773 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5774 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5775 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2420
5776 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5777 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5778 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5779 // (TRAPrr G0, IntRegs:$rs1, 0) - 2423
5780 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5781 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5782 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5783 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2426
5784 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5785 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5786 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5787 // (TRAPrr G0, IntRegs:$rs1, 9) - 2429
5788 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5789 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5790 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5791 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2432
5792 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5793 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5794 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5795 // (TRAPrr G0, IntRegs:$rs1, 1) - 2435
5796 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5797 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5798 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5799 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2438
5800 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5801 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5802 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5803 // (TRAPrr G0, IntRegs:$rs1, 10) - 2441
5804 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5805 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5806 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5807 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2444
5808 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5809 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5810 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5811 // (TRAPrr G0, IntRegs:$rs1, 2) - 2447
5812 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5813 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5814 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5815 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2450
5816 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5817 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5818 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5819 // (TRAPrr G0, IntRegs:$rs1, 11) - 2453
5820 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5821 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5822 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5823 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2456
5824 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5825 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5826 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5827 // (TRAPrr G0, IntRegs:$rs1, 3) - 2459
5828 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5829 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5830 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5831 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2462
5832 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5833 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5834 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5835 // (TRAPrr G0, IntRegs:$rs1, 12) - 2465
5836 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5837 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5838 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5839 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2468
5840 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5841 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5842 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5843 // (TRAPrr G0, IntRegs:$rs1, 4) - 2471
5844 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5845 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5846 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5847 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2474
5848 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5849 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5850 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5851 // (TRAPrr G0, IntRegs:$rs1, 13) - 2477
5852 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5853 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5854 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5855 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2480
5856 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5857 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5858 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5859 // (TRAPrr G0, IntRegs:$rs1, 5) - 2483
5860 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5861 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5862 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5863 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 5) - 2486
5864 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5865 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5866 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5867 // (TRAPrr G0, IntRegs:$rs1, 14) - 2489
5868 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5869 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5870 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5871 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 14) - 2492
5872 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5873 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5874 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5875 // (TRAPrr G0, IntRegs:$rs1, 6) - 2495
5876 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5877 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5878 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5879 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 6) - 2498
5880 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5881 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5882 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5883 // (TRAPrr G0, IntRegs:$rs1, 15) - 2501
5884 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5885 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5886 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5887 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 15) - 2504
5888 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5889 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5890 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5891 // (TRAPrr G0, IntRegs:$rs1, 7) - 2507
5892 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5893 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5894 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5895 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 7) - 2510
5896 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5897 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5898 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5899 // (TXCCri G0, i32imm:$imm, 8) - 2513
5900 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5901 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5902 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5903 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5904 // (TXCCri G0, i32imm:$imm, 8) - 2517
5905 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5906 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5907 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5908 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5909 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5910 // (TXCCri IntRegs:$rs1, i32imm:$imm, 8) - 2522
5911 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5912 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5913 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5914 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5915 // (TXCCri IntRegs:$rs1, i32imm:$imm, 8) - 2526
5916 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5917 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5918 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5919 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5920 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5921 // (TXCCri G0, i32imm:$imm, 0) - 2531
5922 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5923 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5924 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5925 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5926 // (TXCCri G0, i32imm:$imm, 0) - 2535
5927 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5928 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5929 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5930 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5931 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5932 // (TXCCri IntRegs:$rs1, i32imm:$imm, 0) - 2540
5933 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5934 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5935 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5936 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5937 // (TXCCri IntRegs:$rs1, i32imm:$imm, 0) - 2544
5938 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5939 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5940 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5941 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5942 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5943 // (TXCCri G0, i32imm:$imm, 9) - 2549
5944 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5945 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5946 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5947 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5948 // (TXCCri G0, i32imm:$imm, 9) - 2553
5949 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5950 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5951 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5952 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5953 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5954 // (TXCCri IntRegs:$rs1, i32imm:$imm, 9) - 2558
5955 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5956 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5957 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5958 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5959 // (TXCCri IntRegs:$rs1, i32imm:$imm, 9) - 2562
5960 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5961 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5962 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5963 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5964 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5965 // (TXCCri G0, i32imm:$imm, 1) - 2567
5966 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5967 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5968 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5969 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5970 // (TXCCri G0, i32imm:$imm, 1) - 2571
5971 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5972 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5973 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5974 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5975 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5976 // (TXCCri IntRegs:$rs1, i32imm:$imm, 1) - 2576
5977 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5978 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5979 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5980 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5981 // (TXCCri IntRegs:$rs1, i32imm:$imm, 1) - 2580
5982 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5983 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5984 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5985 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5986 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5987 // (TXCCri G0, i32imm:$imm, 10) - 2585
5988 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5989 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5990 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5991 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5992 // (TXCCri G0, i32imm:$imm, 10) - 2589
5993 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5994 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5995 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5996 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5997 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5998 // (TXCCri IntRegs:$rs1, i32imm:$imm, 10) - 2594
5999 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6000 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6001 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6002 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6003 // (TXCCri IntRegs:$rs1, i32imm:$imm, 10) - 2598
6004 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6005 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6006 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6007 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6008 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6009 // (TXCCri G0, i32imm:$imm, 2) - 2603
6010 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6011 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6012 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6013 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6014 // (TXCCri G0, i32imm:$imm, 2) - 2607
6015 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6016 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6017 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6018 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6019 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6020 // (TXCCri IntRegs:$rs1, i32imm:$imm, 2) - 2612
6021 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6022 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6023 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6024 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6025 // (TXCCri IntRegs:$rs1, i32imm:$imm, 2) - 2616
6026 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6027 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6028 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6029 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6030 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6031 // (TXCCri G0, i32imm:$imm, 11) - 2621
6032 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6033 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6034 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6035 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6036 // (TXCCri G0, i32imm:$imm, 11) - 2625
6037 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6038 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6039 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6040 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6041 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6042 // (TXCCri IntRegs:$rs1, i32imm:$imm, 11) - 2630
6043 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6044 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6045 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6046 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6047 // (TXCCri IntRegs:$rs1, i32imm:$imm, 11) - 2634
6048 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6049 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6050 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6051 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6052 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6053 // (TXCCri G0, i32imm:$imm, 3) - 2639
6054 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6055 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6056 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6057 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6058 // (TXCCri G0, i32imm:$imm, 3) - 2643
6059 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6060 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6061 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6062 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6063 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6064 // (TXCCri IntRegs:$rs1, i32imm:$imm, 3) - 2648
6065 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6066 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6067 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6068 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6069 // (TXCCri IntRegs:$rs1, i32imm:$imm, 3) - 2652
6070 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6071 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6072 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6073 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6074 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6075 // (TXCCri G0, i32imm:$imm, 12) - 2657
6076 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6077 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6078 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6079 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6080 // (TXCCri G0, i32imm:$imm, 12) - 2661
6081 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6082 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6083 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6084 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6085 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6086 // (TXCCri IntRegs:$rs1, i32imm:$imm, 12) - 2666
6087 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6088 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6089 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6090 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6091 // (TXCCri IntRegs:$rs1, i32imm:$imm, 12) - 2670
6092 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6093 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6094 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6095 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6096 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6097 // (TXCCri G0, i32imm:$imm, 4) - 2675
6098 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6099 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6100 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6101 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6102 // (TXCCri G0, i32imm:$imm, 4) - 2679
6103 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6104 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6105 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6106 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6107 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6108 // (TXCCri IntRegs:$rs1, i32imm:$imm, 4) - 2684
6109 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6110 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6111 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6112 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6113 // (TXCCri IntRegs:$rs1, i32imm:$imm, 4) - 2688
6114 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6115 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6116 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6117 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6118 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6119 // (TXCCri G0, i32imm:$imm, 13) - 2693
6120 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6121 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6122 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6123 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6124 // (TXCCri G0, i32imm:$imm, 13) - 2697
6125 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6126 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6127 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6128 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6129 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6130 // (TXCCri IntRegs:$rs1, i32imm:$imm, 13) - 2702
6131 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6132 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6133 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6134 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6135 // (TXCCri IntRegs:$rs1, i32imm:$imm, 13) - 2706
6136 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6137 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6138 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6139 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6140 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6141 // (TXCCri G0, i32imm:$imm, 5) - 2711
6142 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6143 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6144 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6145 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6146 // (TXCCri G0, i32imm:$imm, 5) - 2715
6147 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6148 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6149 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6150 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6151 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6152 // (TXCCri IntRegs:$rs1, i32imm:$imm, 5) - 2720
6153 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6154 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6155 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6156 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6157 // (TXCCri IntRegs:$rs1, i32imm:$imm, 5) - 2724
6158 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6159 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6160 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6161 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6162 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6163 // (TXCCri G0, i32imm:$imm, 14) - 2729
6164 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6165 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6166 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6167 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6168 // (TXCCri G0, i32imm:$imm, 14) - 2733
6169 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6170 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6171 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6172 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6173 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6174 // (TXCCri IntRegs:$rs1, i32imm:$imm, 14) - 2738
6175 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6176 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6177 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6178 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6179 // (TXCCri IntRegs:$rs1, i32imm:$imm, 14) - 2742
6180 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6181 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6182 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6183 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6184 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6185 // (TXCCri G0, i32imm:$imm, 6) - 2747
6186 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6187 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6188 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6189 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6190 // (TXCCri G0, i32imm:$imm, 6) - 2751
6191 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6192 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6193 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6194 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6195 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6196 // (TXCCri IntRegs:$rs1, i32imm:$imm, 6) - 2756
6197 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6198 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6199 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6200 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6201 // (TXCCri IntRegs:$rs1, i32imm:$imm, 6) - 2760
6202 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6203 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6204 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6205 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6206 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6207 // (TXCCri G0, i32imm:$imm, 15) - 2765
6208 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6209 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6210 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6211 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6212 // (TXCCri G0, i32imm:$imm, 15) - 2769
6213 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6214 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6215 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6216 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6217 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6218 // (TXCCri IntRegs:$rs1, i32imm:$imm, 15) - 2774
6219 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6220 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6221 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6222 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6223 // (TXCCri IntRegs:$rs1, i32imm:$imm, 15) - 2778
6224 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6225 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6226 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6227 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6228 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6229 // (TXCCri G0, i32imm:$imm, 7) - 2783
6230 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6231 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6232 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6233 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6234 // (TXCCri G0, i32imm:$imm, 7) - 2787
6235 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6236 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6237 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6238 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6239 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6240 // (TXCCri IntRegs:$rs1, i32imm:$imm, 7) - 2792
6241 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6242 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6243 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6244 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6245 // (TXCCri IntRegs:$rs1, i32imm:$imm, 7) - 2796
6246 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6247 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6248 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6249 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6250 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6251 // (TXCCrr G0, IntRegs:$rs2, 8) - 2801
6252 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6253 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6254 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6255 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6256 // (TXCCrr G0, IntRegs:$rs2, 8) - 2805
6257 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6258 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6259 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6260 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6261 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6262 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2810
6263 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6264 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6265 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6266 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6267 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2814
6268 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6269 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6270 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6271 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6272 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6273 // (TXCCrr G0, IntRegs:$rs2, 0) - 2819
6274 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6275 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6276 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6277 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6278 // (TXCCrr G0, IntRegs:$rs2, 0) - 2823
6279 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6280 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6281 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6282 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6283 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6284 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2828
6285 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6286 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6287 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6288 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6289 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2832
6290 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6291 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6292 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6293 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6294 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6295 // (TXCCrr G0, IntRegs:$rs2, 9) - 2837
6296 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6297 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6298 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6299 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6300 // (TXCCrr G0, IntRegs:$rs2, 9) - 2841
6301 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6302 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6303 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6304 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6305 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6306 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2846
6307 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6308 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6309 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6310 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6311 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2850
6312 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6313 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6314 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6315 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6316 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6317 // (TXCCrr G0, IntRegs:$rs2, 1) - 2855
6318 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6319 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6320 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6321 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6322 // (TXCCrr G0, IntRegs:$rs2, 1) - 2859
6323 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6324 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6325 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6326 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6327 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6328 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2864
6329 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6330 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6331 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6332 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6333 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2868
6334 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6335 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6336 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6337 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6338 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6339 // (TXCCrr G0, IntRegs:$rs2, 10) - 2873
6340 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6341 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6342 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6343 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6344 // (TXCCrr G0, IntRegs:$rs2, 10) - 2877
6345 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6346 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6347 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6348 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6349 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6350 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2882
6351 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6352 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6353 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6354 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6355 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2886
6356 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6357 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6358 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6359 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6360 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6361 // (TXCCrr G0, IntRegs:$rs2, 2) - 2891
6362 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6363 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6364 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6365 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6366 // (TXCCrr G0, IntRegs:$rs2, 2) - 2895
6367 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6368 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6369 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6370 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6371 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6372 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2900
6373 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6374 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6375 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6376 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6377 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2904
6378 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6379 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6380 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6381 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6382 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6383 // (TXCCrr G0, IntRegs:$rs2, 11) - 2909
6384 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6385 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6386 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6387 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6388 // (TXCCrr G0, IntRegs:$rs2, 11) - 2913
6389 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6390 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6391 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6392 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6393 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6394 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2918
6395 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6396 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6397 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6398 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6399 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2922
6400 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6401 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6402 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6403 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6404 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6405 // (TXCCrr G0, IntRegs:$rs2, 3) - 2927
6406 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6407 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6408 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6409 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6410 // (TXCCrr G0, IntRegs:$rs2, 3) - 2931
6411 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6412 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6413 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6414 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6415 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6416 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2936
6417 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6418 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6419 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6420 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6421 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2940
6422 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6423 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6424 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6425 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6426 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6427 // (TXCCrr G0, IntRegs:$rs2, 12) - 2945
6428 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6429 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6430 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6431 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6432 // (TXCCrr G0, IntRegs:$rs2, 12) - 2949
6433 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6434 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6435 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6436 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6437 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6438 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2954
6439 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6440 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6441 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6442 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6443 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2958
6444 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6445 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6446 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6447 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6448 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6449 // (TXCCrr G0, IntRegs:$rs2, 4) - 2963
6450 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6451 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6452 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6453 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6454 // (TXCCrr G0, IntRegs:$rs2, 4) - 2967
6455 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6456 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6457 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6458 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6459 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6460 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2972
6461 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6462 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6463 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6464 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6465 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2976
6466 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6467 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6468 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6469 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6470 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6471 // (TXCCrr G0, IntRegs:$rs2, 13) - 2981
6472 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6473 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6474 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6475 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6476 // (TXCCrr G0, IntRegs:$rs2, 13) - 2985
6477 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6478 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6479 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6480 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6481 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6482 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2990
6483 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6484 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6485 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6486 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6487 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2994
6488 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6489 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6490 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6491 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6492 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6493 // (TXCCrr G0, IntRegs:$rs2, 5) - 2999
6494 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6495 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6496 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6497 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6498 // (TXCCrr G0, IntRegs:$rs2, 5) - 3003
6499 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6500 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6501 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6502 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6503 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6504 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 3008
6505 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6506 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6507 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6508 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6509 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 3012
6510 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6511 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6512 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6513 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6514 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6515 // (TXCCrr G0, IntRegs:$rs2, 14) - 3017
6516 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6517 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6518 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6519 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6520 // (TXCCrr G0, IntRegs:$rs2, 14) - 3021
6521 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6522 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6523 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6524 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6525 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6526 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 3026
6527 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6528 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6529 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6530 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6531 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 3030
6532 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6533 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6534 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6535 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6536 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6537 // (TXCCrr G0, IntRegs:$rs2, 6) - 3035
6538 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6539 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6540 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6541 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6542 // (TXCCrr G0, IntRegs:$rs2, 6) - 3039
6543 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6544 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6545 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6546 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6547 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6548 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 3044
6549 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6550 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6551 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6552 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6553 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 3048
6554 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6555 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6556 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6557 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6558 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6559 // (TXCCrr G0, IntRegs:$rs2, 15) - 3053
6560 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6561 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6562 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6563 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6564 // (TXCCrr G0, IntRegs:$rs2, 15) - 3057
6565 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6566 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6567 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6568 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6569 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6570 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 3062
6571 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6572 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6573 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6574 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6575 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 3066
6576 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6577 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6578 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6579 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6580 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6581 // (TXCCrr G0, IntRegs:$rs2, 7) - 3071
6582 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6583 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6584 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6585 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6586 // (TXCCrr G0, IntRegs:$rs2, 7) - 3075
6587 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6588 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6589 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6590 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6591 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6592 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 3080
6593 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6594 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6595 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6596 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6597 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 3084
6598 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6599 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6600 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6601 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6602 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6603 // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 3089
6604 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6605 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6606 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6607 // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 3092
6608 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6609 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6610 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6611 // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 3095
6612 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6613 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6614 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6615 // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2) - 3098
6616 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6617 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6618 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6619 // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 3101
6620 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6621 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6622 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6623 // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2) - 3104
6624 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6625 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6626 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6627 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8) - 3107
6628 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6629 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6630 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6631 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6632 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6633 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6634 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0) - 3113
6635 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6636 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6637 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6638 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6639 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6640 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6641 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7) - 3119
6642 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6643 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6644 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6645 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6646 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6647 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6648 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6) - 3125
6649 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6650 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6651 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6652 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6653 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6654 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6655 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5) - 3131
6656 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6657 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6658 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6659 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6660 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6661 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6662 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4) - 3137
6663 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6664 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6665 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6666 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6667 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6668 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6669 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3) - 3143
6670 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6671 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6672 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6673 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6674 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6675 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6676 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2) - 3149
6677 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6678 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6679 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6680 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6681 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6682 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6683 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1) - 3155
6684 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6685 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6686 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6687 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6688 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6689 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6690 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9) - 3161
6691 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6692 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6693 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6694 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6695 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6696 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6697 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10) - 3167
6698 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6699 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6700 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6701 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6702 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6703 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6704 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11) - 3173
6705 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6706 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6707 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6708 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6709 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6710 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6711 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12) - 3179
6712 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6713 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6714 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6715 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6716 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6717 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6718 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13) - 3185
6719 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6720 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6721 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6722 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6723 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6724 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6725 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14) - 3191
6726 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6727 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6728 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6729 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6730 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6731 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6732 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15) - 3197
6733 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6734 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6735 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6736 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6737 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6738 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6739 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8) - 3203
6740 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6741 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6742 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6743 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6744 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6745 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6746 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0) - 3209
6747 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6748 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6749 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6750 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6751 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6752 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6753 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7) - 3215
6754 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6755 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6756 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6757 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6758 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6759 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6760 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6) - 3221
6761 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6762 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6763 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6764 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6765 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6766 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6767 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5) - 3227
6768 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6769 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6770 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6771 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6772 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6773 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6774 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4) - 3233
6775 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6776 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6777 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6778 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6779 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6780 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6781 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3) - 3239
6782 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6783 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6784 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6785 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6786 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6787 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6788 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2) - 3245
6789 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6790 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6791 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6792 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6793 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6794 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6795 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1) - 3251
6796 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6797 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6798 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6799 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6800 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6801 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6802 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9) - 3257
6803 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6804 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6805 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6806 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6807 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6808 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6809 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10) - 3263
6810 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6811 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6812 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6813 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6814 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6815 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6816 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11) - 3269
6817 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6818 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6819 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6820 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6821 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6822 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6823 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12) - 3275
6824 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6825 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6826 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6827 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6828 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6829 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6830 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13) - 3281
6831 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6832 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6833 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6834 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6835 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6836 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6837 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14) - 3287
6838 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6839 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6840 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6841 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6842 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6843 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6844 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15) - 3293
6845 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6846 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6847 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6848 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6849 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6850 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6851 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8) - 3299
6852 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6853 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6854 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6855 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6856 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6857 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6858 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0) - 3305
6859 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6860 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6861 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6862 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6863 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6864 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6865 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7) - 3311
6866 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6867 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6868 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6869 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6870 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6871 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6872 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6) - 3317
6873 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6874 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6875 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6876 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6877 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6878 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6879 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5) - 3323
6880 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6881 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6882 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6883 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6884 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6885 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6886 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4) - 3329
6887 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6888 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6889 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6890 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6891 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6892 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6893 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3) - 3335
6894 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6895 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6896 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6897 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6898 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6899 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6900 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2) - 3341
6901 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6902 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6903 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6904 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6905 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6906 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6907 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1) - 3347
6908 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6909 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6910 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6911 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6912 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6913 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6914 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9) - 3353
6915 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6916 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6917 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6918 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6919 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6920 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6921 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10) - 3359
6922 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6923 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6924 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6925 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6926 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6927 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6928 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11) - 3365
6929 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6930 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6931 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6932 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6933 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6934 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6935 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12) - 3371
6936 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6937 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6938 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6939 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6940 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6941 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6942 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13) - 3377
6943 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6944 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6945 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6946 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6947 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6948 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6949 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14) - 3383
6950 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6951 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6952 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6953 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6954 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6955 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6956 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15) - 3389
6957 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6958 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6959 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6960 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6961 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6962 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6963 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8) - 3395
6964 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6965 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6966 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6967 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6968 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6969 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6970 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0) - 3401
6971 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6972 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6973 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6974 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6975 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6976 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6977 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7) - 3407
6978 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6979 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6980 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6981 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6982 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6983 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6984 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6) - 3413
6985 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6986 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6987 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6988 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6989 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6990 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6991 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5) - 3419
6992 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6993 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6994 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6995 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6996 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6997 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6998 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4) - 3425
6999 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7000 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7001 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7002 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7003 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
7004 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7005 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3) - 3431
7006 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7007 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7008 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7009 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7010 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
7011 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7012 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2) - 3437
7013 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7014 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7015 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7016 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7017 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
7018 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7019 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1) - 3443
7020 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7021 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7022 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7023 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7024 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
7025 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7026 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9) - 3449
7027 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7028 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7029 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7030 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7031 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
7032 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7033 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10) - 3455
7034 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7035 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7036 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7037 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7038 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
7039 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7040 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11) - 3461
7041 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7042 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7043 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7044 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7045 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
7046 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7047 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12) - 3467
7048 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7049 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7050 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7051 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7052 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
7053 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7054 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13) - 3473
7055 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7056 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7057 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7058 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7059 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
7060 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7061 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14) - 3479
7062 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7063 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7064 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7065 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7066 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
7067 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7068 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15) - 3485
7069 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7070 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7071 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7072 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7073 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
7074 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7075 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8) - 3491
7076 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7077 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7078 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7079 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7080 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
7081 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7082 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0) - 3497
7083 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7084 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7085 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7086 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7087 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
7088 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7089 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7) - 3503
7090 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7091 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7092 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7093 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7094 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
7095 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7096 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6) - 3509
7097 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7098 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7099 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7100 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7101 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
7102 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7103 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5) - 3515
7104 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7105 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7106 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7107 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7108 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
7109 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7110 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4) - 3521
7111 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7112 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7113 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7114 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7115 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
7116 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7117 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3) - 3527
7118 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7119 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7120 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7121 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7122 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
7123 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7124 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2) - 3533
7125 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7126 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7127 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7128 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7129 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
7130 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7131 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1) - 3539
7132 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7133 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7134 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7135 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7136 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
7137 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7138 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9) - 3545
7139 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7140 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7141 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7142 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7143 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
7144 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7145 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10) - 3551
7146 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7147 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7148 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7149 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7150 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
7151 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7152 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11) - 3557
7153 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7154 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7155 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7156 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7157 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
7158 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7159 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12) - 3563
7160 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7161 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7162 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7163 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7164 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
7165 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7166 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13) - 3569
7167 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7168 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7169 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7170 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7171 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
7172 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7173 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14) - 3575
7174 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7175 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7176 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7177 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7178 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
7179 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7180 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15) - 3581
7181 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7182 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7183 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7184 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7185 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
7186 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7187 // (WRASRri ASR27, G0, simm13Op:$simm13) - 3587
7188 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::ASR27},
7189 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
7190 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
7191 // (WRASRrr ASR27, G0, IntRegs:$rs2) - 3590
7192 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::ASR27},
7193 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
7194 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7195 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
7196 };
7197
7198 static const char AsmStrings[] =
7199 /* 0 */ "ba $\xFF\x01\x01\0"
7200 /* 8 */ "bn $\xFF\x01\x01\0"
7201 /* 16 */ "bne $\xFF\x01\x01\0"
7202 /* 25 */ "be $\xFF\x01\x01\0"
7203 /* 33 */ "bg $\xFF\x01\x01\0"
7204 /* 41 */ "ble $\xFF\x01\x01\0"
7205 /* 50 */ "bge $\xFF\x01\x01\0"
7206 /* 59 */ "bl $\xFF\x01\x01\0"
7207 /* 67 */ "bgu $\xFF\x01\x01\0"
7208 /* 76 */ "bleu $\xFF\x01\x01\0"
7209 /* 86 */ "bcc $\xFF\x01\x01\0"
7210 /* 95 */ "bcs $\xFF\x01\x01\0"
7211 /* 104 */ "bpos $\xFF\x01\x01\0"
7212 /* 114 */ "bneg $\xFF\x01\x01\0"
7213 /* 124 */ "bvc $\xFF\x01\x01\0"
7214 /* 133 */ "bvs $\xFF\x01\x01\0"
7215 /* 142 */ "ba,a $\xFF\x01\x01\0"
7216 /* 152 */ "bn,a $\xFF\x01\x01\0"
7217 /* 162 */ "bne,a $\xFF\x01\x01\0"
7218 /* 173 */ "be,a $\xFF\x01\x01\0"
7219 /* 183 */ "bg,a $\xFF\x01\x01\0"
7220 /* 193 */ "ble,a $\xFF\x01\x01\0"
7221 /* 204 */ "bge,a $\xFF\x01\x01\0"
7222 /* 215 */ "bl,a $\xFF\x01\x01\0"
7223 /* 225 */ "bgu,a $\xFF\x01\x01\0"
7224 /* 236 */ "bleu,a $\xFF\x01\x01\0"
7225 /* 248 */ "bcc,a $\xFF\x01\x01\0"
7226 /* 259 */ "bcs,a $\xFF\x01\x01\0"
7227 /* 270 */ "bpos,a $\xFF\x01\x01\0"
7228 /* 282 */ "bneg,a $\xFF\x01\x01\0"
7229 /* 294 */ "bvc,a $\xFF\x01\x01\0"
7230 /* 305 */ "bvs,a $\xFF\x01\x01\0"
7231 /* 316 */ "fba,a,pn $\x03, $\xFF\x01\x01\0"
7232 /* 334 */ "fbn,a,pn $\x03, $\xFF\x01\x01\0"
7233 /* 352 */ "fbu,a,pn $\x03, $\xFF\x01\x01\0"
7234 /* 370 */ "fbg,a,pn $\x03, $\xFF\x01\x01\0"
7235 /* 388 */ "fbug,a,pn $\x03, $\xFF\x01\x01\0"
7236 /* 407 */ "fbl,a,pn $\x03, $\xFF\x01\x01\0"
7237 /* 425 */ "fbul,a,pn $\x03, $\xFF\x01\x01\0"
7238 /* 444 */ "fblg,a,pn $\x03, $\xFF\x01\x01\0"
7239 /* 463 */ "fbne,a,pn $\x03, $\xFF\x01\x01\0"
7240 /* 482 */ "fbe,a,pn $\x03, $\xFF\x01\x01\0"
7241 /* 500 */ "fbue,a,pn $\x03, $\xFF\x01\x01\0"
7242 /* 519 */ "fbge,a,pn $\x03, $\xFF\x01\x01\0"
7243 /* 538 */ "fbuge,a,pn $\x03, $\xFF\x01\x01\0"
7244 /* 558 */ "fble,a,pn $\x03, $\xFF\x01\x01\0"
7245 /* 577 */ "fbule,a,pn $\x03, $\xFF\x01\x01\0"
7246 /* 597 */ "fbo,a,pn $\x03, $\xFF\x01\x01\0"
7247 /* 615 */ "fba,pn $\x03, $\xFF\x01\x01\0"
7248 /* 631 */ "fbn,pn $\x03, $\xFF\x01\x01\0"
7249 /* 647 */ "fbu,pn $\x03, $\xFF\x01\x01\0"
7250 /* 663 */ "fbg,pn $\x03, $\xFF\x01\x01\0"
7251 /* 679 */ "fbug,pn $\x03, $\xFF\x01\x01\0"
7252 /* 696 */ "fbl,pn $\x03, $\xFF\x01\x01\0"
7253 /* 712 */ "fbul,pn $\x03, $\xFF\x01\x01\0"
7254 /* 729 */ "fblg,pn $\x03, $\xFF\x01\x01\0"
7255 /* 746 */ "fbne,pn $\x03, $\xFF\x01\x01\0"
7256 /* 763 */ "fbe,pn $\x03, $\xFF\x01\x01\0"
7257 /* 779 */ "fbue,pn $\x03, $\xFF\x01\x01\0"
7258 /* 796 */ "fbge,pn $\x03, $\xFF\x01\x01\0"
7259 /* 813 */ "fbuge,pn $\x03, $\xFF\x01\x01\0"
7260 /* 831 */ "fble,pn $\x03, $\xFF\x01\x01\0"
7261 /* 848 */ "fbule,pn $\x03, $\xFF\x01\x01\0"
7262 /* 866 */ "fbo,pn $\x03, $\xFF\x01\x01\0"
7263 /* 882 */ "ba,a,pn %icc, $\xFF\x01\x01\0"
7264 /* 901 */ "ba,a,pn %ncc, $\xFF\x01\x01\0"
7265 /* 920 */ "bn,a,pn %icc, $\xFF\x01\x01\0"
7266 /* 939 */ "bn,a,pn %ncc, $\xFF\x01\x01\0"
7267 /* 958 */ "bne,a,pn %icc, $\xFF\x01\x01\0"
7268 /* 978 */ "bne,a,pn %ncc, $\xFF\x01\x01\0"
7269 /* 998 */ "be,a,pn %icc, $\xFF\x01\x01\0"
7270 /* 1017 */ "be,a,pn %ncc, $\xFF\x01\x01\0"
7271 /* 1036 */ "bg,a,pn %icc, $\xFF\x01\x01\0"
7272 /* 1055 */ "bg,a,pn %ncc, $\xFF\x01\x01\0"
7273 /* 1074 */ "ble,a,pn %icc, $\xFF\x01\x01\0"
7274 /* 1094 */ "ble,a,pn %ncc, $\xFF\x01\x01\0"
7275 /* 1114 */ "bge,a,pn %icc, $\xFF\x01\x01\0"
7276 /* 1134 */ "bge,a,pn %ncc, $\xFF\x01\x01\0"
7277 /* 1154 */ "bl,a,pn %icc, $\xFF\x01\x01\0"
7278 /* 1173 */ "bl,a,pn %ncc, $\xFF\x01\x01\0"
7279 /* 1192 */ "bgu,a,pn %icc, $\xFF\x01\x01\0"
7280 /* 1212 */ "bgu,a,pn %ncc, $\xFF\x01\x01\0"
7281 /* 1232 */ "bleu,a,pn %icc, $\xFF\x01\x01\0"
7282 /* 1253 */ "bleu,a,pn %ncc, $\xFF\x01\x01\0"
7283 /* 1274 */ "bcc,a,pn %icc, $\xFF\x01\x01\0"
7284 /* 1294 */ "bcc,a,pn %ncc, $\xFF\x01\x01\0"
7285 /* 1314 */ "bcs,a,pn %icc, $\xFF\x01\x01\0"
7286 /* 1334 */ "bcs,a,pn %ncc, $\xFF\x01\x01\0"
7287 /* 1354 */ "bpos,a,pn %icc, $\xFF\x01\x01\0"
7288 /* 1375 */ "bpos,a,pn %ncc, $\xFF\x01\x01\0"
7289 /* 1396 */ "bneg,a,pn %icc, $\xFF\x01\x01\0"
7290 /* 1417 */ "bneg,a,pn %ncc, $\xFF\x01\x01\0"
7291 /* 1438 */ "bvc,a,pn %icc, $\xFF\x01\x01\0"
7292 /* 1458 */ "bvc,a,pn %ncc, $\xFF\x01\x01\0"
7293 /* 1478 */ "bvs,a,pn %icc, $\xFF\x01\x01\0"
7294 /* 1498 */ "bvs,a,pn %ncc, $\xFF\x01\x01\0"
7295 /* 1518 */ "ba,pn %icc, $\xFF\x01\x01\0"
7296 /* 1535 */ "ba,pn %ncc, $\xFF\x01\x01\0"
7297 /* 1552 */ "bn,pn %icc, $\xFF\x01\x01\0"
7298 /* 1569 */ "bn,pn %ncc, $\xFF\x01\x01\0"
7299 /* 1586 */ "bne,pn %icc, $\xFF\x01\x01\0"
7300 /* 1604 */ "bne,pn %ncc, $\xFF\x01\x01\0"
7301 /* 1622 */ "be,pn %icc, $\xFF\x01\x01\0"
7302 /* 1639 */ "be,pn %ncc, $\xFF\x01\x01\0"
7303 /* 1656 */ "bg,pn %icc, $\xFF\x01\x01\0"
7304 /* 1673 */ "bg,pn %ncc, $\xFF\x01\x01\0"
7305 /* 1690 */ "ble,pn %icc, $\xFF\x01\x01\0"
7306 /* 1708 */ "ble,pn %ncc, $\xFF\x01\x01\0"
7307 /* 1726 */ "bge,pn %icc, $\xFF\x01\x01\0"
7308 /* 1744 */ "bge,pn %ncc, $\xFF\x01\x01\0"
7309 /* 1762 */ "bl,pn %icc, $\xFF\x01\x01\0"
7310 /* 1779 */ "bl,pn %ncc, $\xFF\x01\x01\0"
7311 /* 1796 */ "bgu,pn %icc, $\xFF\x01\x01\0"
7312 /* 1814 */ "bgu,pn %ncc, $\xFF\x01\x01\0"
7313 /* 1832 */ "bleu,pn %icc, $\xFF\x01\x01\0"
7314 /* 1851 */ "bleu,pn %ncc, $\xFF\x01\x01\0"
7315 /* 1870 */ "bcc,pn %icc, $\xFF\x01\x01\0"
7316 /* 1888 */ "bcc,pn %ncc, $\xFF\x01\x01\0"
7317 /* 1906 */ "bcs,pn %icc, $\xFF\x01\x01\0"
7318 /* 1924 */ "bcs,pn %ncc, $\xFF\x01\x01\0"
7319 /* 1942 */ "bpos,pn %icc, $\xFF\x01\x01\0"
7320 /* 1961 */ "bpos,pn %ncc, $\xFF\x01\x01\0"
7321 /* 1980 */ "bneg,pn %icc, $\xFF\x01\x01\0"
7322 /* 1999 */ "bneg,pn %ncc, $\xFF\x01\x01\0"
7323 /* 2018 */ "bvc,pn %icc, $\xFF\x01\x01\0"
7324 /* 2036 */ "bvc,pn %ncc, $\xFF\x01\x01\0"
7325 /* 2054 */ "bvs,pn %icc, $\xFF\x01\x01\0"
7326 /* 2072 */ "bvs,pn %ncc, $\xFF\x01\x01\0"
7327 /* 2090 */ "brlez,a,pn $\x03, $\xFF\x01\x01\0"
7328 /* 2110 */ "brlz,a,pn $\x03, $\xFF\x01\x01\0"
7329 /* 2129 */ "brgz,a,pn $\x03, $\xFF\x01\x01\0"
7330 /* 2148 */ "brgez,a,pn $\x03, $\xFF\x01\x01\0"
7331 /* 2168 */ "brlez,pn $\x03, $\xFF\x01\x01\0"
7332 /* 2186 */ "brlz,pn $\x03, $\xFF\x01\x01\0"
7333 /* 2203 */ "brgz,pn $\x03, $\xFF\x01\x01\0"
7334 /* 2220 */ "brgez,pn $\x03, $\xFF\x01\x01\0"
7335 /* 2238 */ "cas [$\x02], $\x03, $\x01\0"
7336 /* 2255 */ "casl [$\x02], $\x03, $\x01\0"
7337 /* 2273 */ "casx [$\x02], $\x03, $\x01\0"
7338 /* 2291 */ "casxl [$\x02], $\x03, $\x01\0"
7339 /* 2310 */ "cwbne $\x03, $\x04, $\xFF\x01\x01\0"
7340 /* 2329 */ "cwbe $\x03, $\x04, $\xFF\x01\x01\0"
7341 /* 2347 */ "cwbg $\x03, $\x04, $\xFF\x01\x01\0"
7342 /* 2365 */ "cwble $\x03, $\x04, $\xFF\x01\x01\0"
7343 /* 2384 */ "cwbge $\x03, $\x04, $\xFF\x01\x01\0"
7344 /* 2403 */ "cwbl $\x03, $\x04, $\xFF\x01\x01\0"
7345 /* 2421 */ "cwbgu $\x03, $\x04, $\xFF\x01\x01\0"
7346 /* 2440 */ "cwbleu $\x03, $\x04, $\xFF\x01\x01\0"
7347 /* 2460 */ "cwbcc $\x03, $\x04, $\xFF\x01\x01\0"
7348 /* 2479 */ "cwbcs $\x03, $\x04, $\xFF\x01\x01\0"
7349 /* 2498 */ "cwbpos $\x03, $\x04, $\xFF\x01\x01\0"
7350 /* 2518 */ "cwbneg $\x03, $\x04, $\xFF\x01\x01\0"
7351 /* 2538 */ "cwbvc $\x03, $\x04, $\xFF\x01\x01\0"
7352 /* 2557 */ "cwbvs $\x03, $\x04, $\xFF\x01\x01\0"
7353 /* 2576 */ "cxbne $\x03, $\x04, $\xFF\x01\x01\0"
7354 /* 2595 */ "cxbe $\x03, $\x04, $\xFF\x01\x01\0"
7355 /* 2613 */ "cxbg $\x03, $\x04, $\xFF\x01\x01\0"
7356 /* 2631 */ "cxble $\x03, $\x04, $\xFF\x01\x01\0"
7357 /* 2650 */ "cxbge $\x03, $\x04, $\xFF\x01\x01\0"
7358 /* 2669 */ "cxbl $\x03, $\x04, $\xFF\x01\x01\0"
7359 /* 2687 */ "cxbgu $\x03, $\x04, $\xFF\x01\x01\0"
7360 /* 2706 */ "cxbleu $\x03, $\x04, $\xFF\x01\x01\0"
7361 /* 2726 */ "cxbcc $\x03, $\x04, $\xFF\x01\x01\0"
7362 /* 2745 */ "cxbcs $\x03, $\x04, $\xFF\x01\x01\0"
7363 /* 2764 */ "cxbpos $\x03, $\x04, $\xFF\x01\x01\0"
7364 /* 2784 */ "cxbneg $\x03, $\x04, $\xFF\x01\x01\0"
7365 /* 2804 */ "cxbvc $\x03, $\x04, $\xFF\x01\x01\0"
7366 /* 2823 */ "cxbvs $\x03, $\x04, $\xFF\x01\x01\0"
7367 /* 2842 */ "fmovda %icc, $\x02, $\x01\0"
7368 /* 2862 */ "fmovda %ncc, $\x02, $\x01\0"
7369 /* 2882 */ "fmovdn %icc, $\x02, $\x01\0"
7370 /* 2902 */ "fmovdn %ncc, $\x02, $\x01\0"
7371 /* 2922 */ "fmovdne %icc, $\x02, $\x01\0"
7372 /* 2943 */ "fmovdne %ncc, $\x02, $\x01\0"
7373 /* 2964 */ "fmovde %icc, $\x02, $\x01\0"
7374 /* 2984 */ "fmovde %ncc, $\x02, $\x01\0"
7375 /* 3004 */ "fmovdg %icc, $\x02, $\x01\0"
7376 /* 3024 */ "fmovdg %ncc, $\x02, $\x01\0"
7377 /* 3044 */ "fmovdle %icc, $\x02, $\x01\0"
7378 /* 3065 */ "fmovdle %ncc, $\x02, $\x01\0"
7379 /* 3086 */ "fmovdge %icc, $\x02, $\x01\0"
7380 /* 3107 */ "fmovdge %ncc, $\x02, $\x01\0"
7381 /* 3128 */ "fmovdl %icc, $\x02, $\x01\0"
7382 /* 3148 */ "fmovdl %ncc, $\x02, $\x01\0"
7383 /* 3168 */ "fmovdgu %icc, $\x02, $\x01\0"
7384 /* 3189 */ "fmovdgu %ncc, $\x02, $\x01\0"
7385 /* 3210 */ "fmovdleu %icc, $\x02, $\x01\0"
7386 /* 3232 */ "fmovdleu %ncc, $\x02, $\x01\0"
7387 /* 3254 */ "fmovdcc %icc, $\x02, $\x01\0"
7388 /* 3275 */ "fmovdcc %ncc, $\x02, $\x01\0"
7389 /* 3296 */ "fmovdcs %icc, $\x02, $\x01\0"
7390 /* 3317 */ "fmovdcs %ncc, $\x02, $\x01\0"
7391 /* 3338 */ "fmovdpos %icc, $\x02, $\x01\0"
7392 /* 3360 */ "fmovdpos %ncc, $\x02, $\x01\0"
7393 /* 3382 */ "fmovdneg %icc, $\x02, $\x01\0"
7394 /* 3404 */ "fmovdneg %ncc, $\x02, $\x01\0"
7395 /* 3426 */ "fmovdvc %icc, $\x02, $\x01\0"
7396 /* 3447 */ "fmovdvc %ncc, $\x02, $\x01\0"
7397 /* 3468 */ "fmovdvs %icc, $\x02, $\x01\0"
7398 /* 3489 */ "fmovdvs %ncc, $\x02, $\x01\0"
7399 /* 3510 */ "fmovqa %icc, $\x02, $\x01\0"
7400 /* 3530 */ "fmovqa %ncc, $\x02, $\x01\0"
7401 /* 3550 */ "fmovqn %icc, $\x02, $\x01\0"
7402 /* 3570 */ "fmovqn %ncc, $\x02, $\x01\0"
7403 /* 3590 */ "fmovqne %icc, $\x02, $\x01\0"
7404 /* 3611 */ "fmovqne %ncc, $\x02, $\x01\0"
7405 /* 3632 */ "fmovqe %icc, $\x02, $\x01\0"
7406 /* 3652 */ "fmovqe %ncc, $\x02, $\x01\0"
7407 /* 3672 */ "fmovqg %icc, $\x02, $\x01\0"
7408 /* 3692 */ "fmovqg %ncc, $\x02, $\x01\0"
7409 /* 3712 */ "fmovqle %icc, $\x02, $\x01\0"
7410 /* 3733 */ "fmovqle %ncc, $\x02, $\x01\0"
7411 /* 3754 */ "fmovqge %icc, $\x02, $\x01\0"
7412 /* 3775 */ "fmovqge %ncc, $\x02, $\x01\0"
7413 /* 3796 */ "fmovql %icc, $\x02, $\x01\0"
7414 /* 3816 */ "fmovql %ncc, $\x02, $\x01\0"
7415 /* 3836 */ "fmovqgu %icc, $\x02, $\x01\0"
7416 /* 3857 */ "fmovqgu %ncc, $\x02, $\x01\0"
7417 /* 3878 */ "fmovqleu %icc, $\x02, $\x01\0"
7418 /* 3900 */ "fmovqleu %ncc, $\x02, $\x01\0"
7419 /* 3922 */ "fmovqcc %icc, $\x02, $\x01\0"
7420 /* 3943 */ "fmovqcc %ncc, $\x02, $\x01\0"
7421 /* 3964 */ "fmovqcs %icc, $\x02, $\x01\0"
7422 /* 3985 */ "fmovqcs %ncc, $\x02, $\x01\0"
7423 /* 4006 */ "fmovqpos %icc, $\x02, $\x01\0"
7424 /* 4028 */ "fmovqpos %ncc, $\x02, $\x01\0"
7425 /* 4050 */ "fmovqneg %icc, $\x02, $\x01\0"
7426 /* 4072 */ "fmovqneg %ncc, $\x02, $\x01\0"
7427 /* 4094 */ "fmovqvc %icc, $\x02, $\x01\0"
7428 /* 4115 */ "fmovqvc %ncc, $\x02, $\x01\0"
7429 /* 4136 */ "fmovqvs %icc, $\x02, $\x01\0"
7430 /* 4157 */ "fmovqvs %ncc, $\x02, $\x01\0"
7431 /* 4178 */ "fmovrdlez $\x02, $\x03, $\x01\0"
7432 /* 4199 */ "fmovrdlz $\x02, $\x03, $\x01\0"
7433 /* 4219 */ "fmovrdgz $\x02, $\x03, $\x01\0"
7434 /* 4239 */ "fmovrdgez $\x02, $\x03, $\x01\0"
7435 /* 4260 */ "fmovrqlez $\x02, $\x03, $\x01\0"
7436 /* 4281 */ "fmovrqlz $\x02, $\x03, $\x01\0"
7437 /* 4301 */ "fmovrqgz $\x02, $\x03, $\x01\0"
7438 /* 4321 */ "fmovrqgez $\x02, $\x03, $\x01\0"
7439 /* 4342 */ "fmovrslez $\x02, $\x03, $\x01\0"
7440 /* 4363 */ "fmovrslz $\x02, $\x03, $\x01\0"
7441 /* 4383 */ "fmovrsgz $\x02, $\x03, $\x01\0"
7442 /* 4403 */ "fmovrsgez $\x02, $\x03, $\x01\0"
7443 /* 4424 */ "fmovsa %icc, $\x02, $\x01\0"
7444 /* 4444 */ "fmovsa %ncc, $\x02, $\x01\0"
7445 /* 4464 */ "fmovsn %icc, $\x02, $\x01\0"
7446 /* 4484 */ "fmovsn %ncc, $\x02, $\x01\0"
7447 /* 4504 */ "fmovsne %icc, $\x02, $\x01\0"
7448 /* 4525 */ "fmovsne %ncc, $\x02, $\x01\0"
7449 /* 4546 */ "fmovse %icc, $\x02, $\x01\0"
7450 /* 4566 */ "fmovse %ncc, $\x02, $\x01\0"
7451 /* 4586 */ "fmovsg %icc, $\x02, $\x01\0"
7452 /* 4606 */ "fmovsg %ncc, $\x02, $\x01\0"
7453 /* 4626 */ "fmovsle %icc, $\x02, $\x01\0"
7454 /* 4647 */ "fmovsle %ncc, $\x02, $\x01\0"
7455 /* 4668 */ "fmovsge %icc, $\x02, $\x01\0"
7456 /* 4689 */ "fmovsge %ncc, $\x02, $\x01\0"
7457 /* 4710 */ "fmovsl %icc, $\x02, $\x01\0"
7458 /* 4730 */ "fmovsl %ncc, $\x02, $\x01\0"
7459 /* 4750 */ "fmovsgu %icc, $\x02, $\x01\0"
7460 /* 4771 */ "fmovsgu %ncc, $\x02, $\x01\0"
7461 /* 4792 */ "fmovsleu %icc, $\x02, $\x01\0"
7462 /* 4814 */ "fmovsleu %ncc, $\x02, $\x01\0"
7463 /* 4836 */ "fmovscc %icc, $\x02, $\x01\0"
7464 /* 4857 */ "fmovscc %ncc, $\x02, $\x01\0"
7465 /* 4878 */ "fmovscs %icc, $\x02, $\x01\0"
7466 /* 4899 */ "fmovscs %ncc, $\x02, $\x01\0"
7467 /* 4920 */ "fmovspos %icc, $\x02, $\x01\0"
7468 /* 4942 */ "fmovspos %ncc, $\x02, $\x01\0"
7469 /* 4964 */ "fmovsneg %icc, $\x02, $\x01\0"
7470 /* 4986 */ "fmovsneg %ncc, $\x02, $\x01\0"
7471 /* 5008 */ "fmovsvc %icc, $\x02, $\x01\0"
7472 /* 5029 */ "fmovsvc %ncc, $\x02, $\x01\0"
7473 /* 5050 */ "fmovsvs %icc, $\x02, $\x01\0"
7474 /* 5071 */ "fmovsvs %ncc, $\x02, $\x01\0"
7475 /* 5092 */ "mova %icc, $\x02, $\x01\0"
7476 /* 5110 */ "mova %ncc, $\x02, $\x01\0"
7477 /* 5128 */ "movn %icc, $\x02, $\x01\0"
7478 /* 5146 */ "movn %ncc, $\x02, $\x01\0"
7479 /* 5164 */ "movne %icc, $\x02, $\x01\0"
7480 /* 5183 */ "movne %ncc, $\x02, $\x01\0"
7481 /* 5202 */ "move %icc, $\x02, $\x01\0"
7482 /* 5220 */ "move %ncc, $\x02, $\x01\0"
7483 /* 5238 */ "movg %icc, $\x02, $\x01\0"
7484 /* 5256 */ "movg %ncc, $\x02, $\x01\0"
7485 /* 5274 */ "movle %icc, $\x02, $\x01\0"
7486 /* 5293 */ "movle %ncc, $\x02, $\x01\0"
7487 /* 5312 */ "movge %icc, $\x02, $\x01\0"
7488 /* 5331 */ "movge %ncc, $\x02, $\x01\0"
7489 /* 5350 */ "movl %icc, $\x02, $\x01\0"
7490 /* 5368 */ "movl %ncc, $\x02, $\x01\0"
7491 /* 5386 */ "movgu %icc, $\x02, $\x01\0"
7492 /* 5405 */ "movgu %ncc, $\x02, $\x01\0"
7493 /* 5424 */ "movleu %icc, $\x02, $\x01\0"
7494 /* 5444 */ "movleu %ncc, $\x02, $\x01\0"
7495 /* 5464 */ "movcc %icc, $\x02, $\x01\0"
7496 /* 5483 */ "movcc %ncc, $\x02, $\x01\0"
7497 /* 5502 */ "movcs %icc, $\x02, $\x01\0"
7498 /* 5521 */ "movcs %ncc, $\x02, $\x01\0"
7499 /* 5540 */ "movpos %icc, $\x02, $\x01\0"
7500 /* 5560 */ "movpos %ncc, $\x02, $\x01\0"
7501 /* 5580 */ "movneg %icc, $\x02, $\x01\0"
7502 /* 5600 */ "movneg %ncc, $\x02, $\x01\0"
7503 /* 5620 */ "movvc %icc, $\x02, $\x01\0"
7504 /* 5639 */ "movvc %ncc, $\x02, $\x01\0"
7505 /* 5658 */ "movvs %icc, $\x02, $\x01\0"
7506 /* 5677 */ "movvs %ncc, $\x02, $\x01\0"
7507 /* 5696 */ "movrlez $\x02, $\x03, $\x01\0"
7508 /* 5715 */ "movrlz $\x02, $\x03, $\x01\0"
7509 /* 5733 */ "movrgz $\x02, $\x03, $\x01\0"
7510 /* 5751 */ "movrgez $\x02, $\x03, $\x01\0"
7511 /* 5770 */ "tst $\x02\0"
7512 /* 5777 */ "mov $\x03, $\x01\0"
7513 /* 5788 */ "restore\0"
7514 /* 5796 */ "ret\0"
7515 /* 5800 */ "retl\0"
7516 /* 5805 */ "save\0"
7517 /* 5810 */ "cmp $\x02, $\x03\0"
7518 /* 5821 */ "ta %icc, $\x02\0"
7519 /* 5833 */ "ta %ncc, $\x02\0"
7520 /* 5845 */ "ta %icc, $\x01 + $\x02\0"
7521 /* 5862 */ "ta %ncc, $\x01 + $\x02\0"
7522 /* 5879 */ "tn %icc, $\x02\0"
7523 /* 5891 */ "tn %ncc, $\x02\0"
7524 /* 5903 */ "tn %icc, $\x01 + $\x02\0"
7525 /* 5920 */ "tn %ncc, $\x01 + $\x02\0"
7526 /* 5937 */ "tne %icc, $\x02\0"
7527 /* 5950 */ "tne %ncc, $\x02\0"
7528 /* 5963 */ "tne %icc, $\x01 + $\x02\0"
7529 /* 5981 */ "tne %ncc, $\x01 + $\x02\0"
7530 /* 5999 */ "te %icc, $\x02\0"
7531 /* 6011 */ "te %ncc, $\x02\0"
7532 /* 6023 */ "te %icc, $\x01 + $\x02\0"
7533 /* 6040 */ "te %ncc, $\x01 + $\x02\0"
7534 /* 6057 */ "tg %icc, $\x02\0"
7535 /* 6069 */ "tg %ncc, $\x02\0"
7536 /* 6081 */ "tg %icc, $\x01 + $\x02\0"
7537 /* 6098 */ "tg %ncc, $\x01 + $\x02\0"
7538 /* 6115 */ "tle %icc, $\x02\0"
7539 /* 6128 */ "tle %ncc, $\x02\0"
7540 /* 6141 */ "tle %icc, $\x01 + $\x02\0"
7541 /* 6159 */ "tle %ncc, $\x01 + $\x02\0"
7542 /* 6177 */ "tge %icc, $\x02\0"
7543 /* 6190 */ "tge %ncc, $\x02\0"
7544 /* 6203 */ "tge %icc, $\x01 + $\x02\0"
7545 /* 6221 */ "tge %ncc, $\x01 + $\x02\0"
7546 /* 6239 */ "tl %icc, $\x02\0"
7547 /* 6251 */ "tl %ncc, $\x02\0"
7548 /* 6263 */ "tl %icc, $\x01 + $\x02\0"
7549 /* 6280 */ "tl %ncc, $\x01 + $\x02\0"
7550 /* 6297 */ "tgu %icc, $\x02\0"
7551 /* 6310 */ "tgu %ncc, $\x02\0"
7552 /* 6323 */ "tgu %icc, $\x01 + $\x02\0"
7553 /* 6341 */ "tgu %ncc, $\x01 + $\x02\0"
7554 /* 6359 */ "tleu %icc, $\x02\0"
7555 /* 6373 */ "tleu %ncc, $\x02\0"
7556 /* 6387 */ "tleu %icc, $\x01 + $\x02\0"
7557 /* 6406 */ "tleu %ncc, $\x01 + $\x02\0"
7558 /* 6425 */ "tcc %icc, $\x02\0"
7559 /* 6438 */ "tcc %ncc, $\x02\0"
7560 /* 6451 */ "tcc %icc, $\x01 + $\x02\0"
7561 /* 6469 */ "tcc %ncc, $\x01 + $\x02\0"
7562 /* 6487 */ "tcs %icc, $\x02\0"
7563 /* 6500 */ "tcs %ncc, $\x02\0"
7564 /* 6513 */ "tcs %icc, $\x01 + $\x02\0"
7565 /* 6531 */ "tcs %ncc, $\x01 + $\x02\0"
7566 /* 6549 */ "tpos %icc, $\x02\0"
7567 /* 6563 */ "tpos %ncc, $\x02\0"
7568 /* 6577 */ "tpos %icc, $\x01 + $\x02\0"
7569 /* 6596 */ "tpos %ncc, $\x01 + $\x02\0"
7570 /* 6615 */ "tneg %icc, $\x02\0"
7571 /* 6629 */ "tneg %ncc, $\x02\0"
7572 /* 6643 */ "tneg %icc, $\x01 + $\x02\0"
7573 /* 6662 */ "tneg %ncc, $\x01 + $\x02\0"
7574 /* 6681 */ "tvc %icc, $\x02\0"
7575 /* 6694 */ "tvc %ncc, $\x02\0"
7576 /* 6707 */ "tvc %icc, $\x01 + $\x02\0"
7577 /* 6725 */ "tvc %ncc, $\x01 + $\x02\0"
7578 /* 6743 */ "tvs %icc, $\x02\0"
7579 /* 6756 */ "tvs %ncc, $\x02\0"
7580 /* 6769 */ "tvs %icc, $\x01 + $\x02\0"
7581 /* 6787 */ "tvs %ncc, $\x01 + $\x02\0"
7582 /* 6805 */ "ta $\x02\0"
7583 /* 6811 */ "ta $\x01 + $\x02\0"
7584 /* 6822 */ "tn $\x02\0"
7585 /* 6828 */ "tn $\x01 + $\x02\0"
7586 /* 6839 */ "tne $\x02\0"
7587 /* 6846 */ "tne $\x01 + $\x02\0"
7588 /* 6858 */ "te $\x02\0"
7589 /* 6864 */ "te $\x01 + $\x02\0"
7590 /* 6875 */ "tg $\x02\0"
7591 /* 6881 */ "tg $\x01 + $\x02\0"
7592 /* 6892 */ "tle $\x02\0"
7593 /* 6899 */ "tle $\x01 + $\x02\0"
7594 /* 6911 */ "tge $\x02\0"
7595 /* 6918 */ "tge $\x01 + $\x02\0"
7596 /* 6930 */ "tl $\x02\0"
7597 /* 6936 */ "tl $\x01 + $\x02\0"
7598 /* 6947 */ "tgu $\x02\0"
7599 /* 6954 */ "tgu $\x01 + $\x02\0"
7600 /* 6966 */ "tleu $\x02\0"
7601 /* 6974 */ "tleu $\x01 + $\x02\0"
7602 /* 6987 */ "tcc $\x02\0"
7603 /* 6994 */ "tcc $\x01 + $\x02\0"
7604 /* 7006 */ "tcs $\x02\0"
7605 /* 7013 */ "tcs $\x01 + $\x02\0"
7606 /* 7025 */ "tpos $\x02\0"
7607 /* 7033 */ "tpos $\x01 + $\x02\0"
7608 /* 7046 */ "tneg $\x02\0"
7609 /* 7054 */ "tneg $\x01 + $\x02\0"
7610 /* 7067 */ "tvc $\x02\0"
7611 /* 7074 */ "tvc $\x01 + $\x02\0"
7612 /* 7086 */ "tvs $\x02\0"
7613 /* 7093 */ "tvs $\x01 + $\x02\0"
7614 /* 7105 */ "ta %xcc, $\x02\0"
7615 /* 7117 */ "ta %xcc, $\x01 + $\x02\0"
7616 /* 7134 */ "tn %xcc, $\x02\0"
7617 /* 7146 */ "tn %xcc, $\x01 + $\x02\0"
7618 /* 7163 */ "tne %xcc, $\x02\0"
7619 /* 7176 */ "tne %xcc, $\x01 + $\x02\0"
7620 /* 7194 */ "te %xcc, $\x02\0"
7621 /* 7206 */ "te %xcc, $\x01 + $\x02\0"
7622 /* 7223 */ "tg %xcc, $\x02\0"
7623 /* 7235 */ "tg %xcc, $\x01 + $\x02\0"
7624 /* 7252 */ "tle %xcc, $\x02\0"
7625 /* 7265 */ "tle %xcc, $\x01 + $\x02\0"
7626 /* 7283 */ "tge %xcc, $\x02\0"
7627 /* 7296 */ "tge %xcc, $\x01 + $\x02\0"
7628 /* 7314 */ "tl %xcc, $\x02\0"
7629 /* 7326 */ "tl %xcc, $\x01 + $\x02\0"
7630 /* 7343 */ "tgu %xcc, $\x02\0"
7631 /* 7356 */ "tgu %xcc, $\x01 + $\x02\0"
7632 /* 7374 */ "tleu %xcc, $\x02\0"
7633 /* 7388 */ "tleu %xcc, $\x01 + $\x02\0"
7634 /* 7407 */ "tcc %xcc, $\x02\0"
7635 /* 7420 */ "tcc %xcc, $\x01 + $\x02\0"
7636 /* 7438 */ "tcs %xcc, $\x02\0"
7637 /* 7451 */ "tcs %xcc, $\x01 + $\x02\0"
7638 /* 7469 */ "tpos %xcc, $\x02\0"
7639 /* 7483 */ "tpos %xcc, $\x01 + $\x02\0"
7640 /* 7502 */ "tneg %xcc, $\x02\0"
7641 /* 7516 */ "tneg %xcc, $\x01 + $\x02\0"
7642 /* 7535 */ "tvc %xcc, $\x02\0"
7643 /* 7548 */ "tvc %xcc, $\x01 + $\x02\0"
7644 /* 7566 */ "tvs %xcc, $\x02\0"
7645 /* 7579 */ "tvs %xcc, $\x01 + $\x02\0"
7646 /* 7597 */ "fcmpd $\x02, $\x03\0"
7647 /* 7610 */ "fcmped $\x02, $\x03\0"
7648 /* 7624 */ "fcmpeq $\x02, $\x03\0"
7649 /* 7638 */ "fcmpes $\x02, $\x03\0"
7650 /* 7652 */ "fcmpq $\x02, $\x03\0"
7651 /* 7665 */ "fcmps $\x02, $\x03\0"
7652 /* 7678 */ "fmovda $\x02, $\x03, $\x01\0"
7653 /* 7696 */ "fmovdn $\x02, $\x03, $\x01\0"
7654 /* 7714 */ "fmovdu $\x02, $\x03, $\x01\0"
7655 /* 7732 */ "fmovdg $\x02, $\x03, $\x01\0"
7656 /* 7750 */ "fmovdug $\x02, $\x03, $\x01\0"
7657 /* 7769 */ "fmovdl $\x02, $\x03, $\x01\0"
7658 /* 7787 */ "fmovdul $\x02, $\x03, $\x01\0"
7659 /* 7806 */ "fmovdlg $\x02, $\x03, $\x01\0"
7660 /* 7825 */ "fmovdne $\x02, $\x03, $\x01\0"
7661 /* 7844 */ "fmovde $\x02, $\x03, $\x01\0"
7662 /* 7862 */ "fmovdue $\x02, $\x03, $\x01\0"
7663 /* 7881 */ "fmovdge $\x02, $\x03, $\x01\0"
7664 /* 7900 */ "fmovduge $\x02, $\x03, $\x01\0"
7665 /* 7920 */ "fmovdle $\x02, $\x03, $\x01\0"
7666 /* 7939 */ "fmovdule $\x02, $\x03, $\x01\0"
7667 /* 7959 */ "fmovdo $\x02, $\x03, $\x01\0"
7668 /* 7977 */ "fmovqa $\x02, $\x03, $\x01\0"
7669 /* 7995 */ "fmovqn $\x02, $\x03, $\x01\0"
7670 /* 8013 */ "fmovqu $\x02, $\x03, $\x01\0"
7671 /* 8031 */ "fmovqg $\x02, $\x03, $\x01\0"
7672 /* 8049 */ "fmovqug $\x02, $\x03, $\x01\0"
7673 /* 8068 */ "fmovql $\x02, $\x03, $\x01\0"
7674 /* 8086 */ "fmovqul $\x02, $\x03, $\x01\0"
7675 /* 8105 */ "fmovqlg $\x02, $\x03, $\x01\0"
7676 /* 8124 */ "fmovqne $\x02, $\x03, $\x01\0"
7677 /* 8143 */ "fmovqe $\x02, $\x03, $\x01\0"
7678 /* 8161 */ "fmovque $\x02, $\x03, $\x01\0"
7679 /* 8180 */ "fmovqge $\x02, $\x03, $\x01\0"
7680 /* 8199 */ "fmovquge $\x02, $\x03, $\x01\0"
7681 /* 8219 */ "fmovqle $\x02, $\x03, $\x01\0"
7682 /* 8238 */ "fmovqule $\x02, $\x03, $\x01\0"
7683 /* 8258 */ "fmovqo $\x02, $\x03, $\x01\0"
7684 /* 8276 */ "fmovsa $\x02, $\x03, $\x01\0"
7685 /* 8294 */ "fmovsn $\x02, $\x03, $\x01\0"
7686 /* 8312 */ "fmovsu $\x02, $\x03, $\x01\0"
7687 /* 8330 */ "fmovsg $\x02, $\x03, $\x01\0"
7688 /* 8348 */ "fmovsug $\x02, $\x03, $\x01\0"
7689 /* 8367 */ "fmovsl $\x02, $\x03, $\x01\0"
7690 /* 8385 */ "fmovsul $\x02, $\x03, $\x01\0"
7691 /* 8404 */ "fmovslg $\x02, $\x03, $\x01\0"
7692 /* 8423 */ "fmovsne $\x02, $\x03, $\x01\0"
7693 /* 8442 */ "fmovse $\x02, $\x03, $\x01\0"
7694 /* 8460 */ "fmovsue $\x02, $\x03, $\x01\0"
7695 /* 8479 */ "fmovsge $\x02, $\x03, $\x01\0"
7696 /* 8498 */ "fmovsuge $\x02, $\x03, $\x01\0"
7697 /* 8518 */ "fmovsle $\x02, $\x03, $\x01\0"
7698 /* 8537 */ "fmovsule $\x02, $\x03, $\x01\0"
7699 /* 8557 */ "fmovso $\x02, $\x03, $\x01\0"
7700 /* 8575 */ "mova $\x02, $\x03, $\x01\0"
7701 /* 8591 */ "movn $\x02, $\x03, $\x01\0"
7702 /* 8607 */ "movu $\x02, $\x03, $\x01\0"
7703 /* 8623 */ "movg $\x02, $\x03, $\x01\0"
7704 /* 8639 */ "movug $\x02, $\x03, $\x01\0"
7705 /* 8656 */ "movl $\x02, $\x03, $\x01\0"
7706 /* 8672 */ "movul $\x02, $\x03, $\x01\0"
7707 /* 8689 */ "movlg $\x02, $\x03, $\x01\0"
7708 /* 8706 */ "movne $\x02, $\x03, $\x01\0"
7709 /* 8723 */ "move $\x02, $\x03, $\x01\0"
7710 /* 8739 */ "movue $\x02, $\x03, $\x01\0"
7711 /* 8756 */ "movge $\x02, $\x03, $\x01\0"
7712 /* 8773 */ "movuge $\x02, $\x03, $\x01\0"
7713 /* 8791 */ "movle $\x02, $\x03, $\x01\0"
7714 /* 8808 */ "movule $\x02, $\x03, $\x01\0"
7715 /* 8826 */ "movo $\x02, $\x03, $\x01\0"
7716 /* 8842 */ "pause $\x03\0"
7717 ;
7718
7719#ifndef NDEBUG
7720 static struct SortCheck {
7721 SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
7722 assert(std::is_sorted(
7723 OpToPatterns.begin(), OpToPatterns.end(),
7724 [](const PatternsForOpcode &L, const PatternsForOpcode &R) {
7725 return L.Opcode < R.Opcode;
7726 }) &&
7727 "tablegen failed to sort opcode patterns");
7728 }
7729 } sortCheckVar(OpToPatterns);
7730#endif
7731
7732 AliasMatchingData M {
7733 .OpToPatterns: ArrayRef(OpToPatterns),
7734 .Patterns: ArrayRef(Patterns),
7735 .PatternConds: ArrayRef(Conds),
7736 .AsmStrings: StringRef(AsmStrings, std::size(AsmStrings)),
7737 .ValidateMCOperand: nullptr,
7738 };
7739 const char *AsmString = matchAliasPatterns(MI, STI: &STI, M);
7740 if (!AsmString) return false;
7741
7742 unsigned I = 0;
7743 while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
7744 AsmString[I] != '$' && AsmString[I] != '\0')
7745 ++I;
7746 OS << '\t' << StringRef(AsmString, I);
7747 if (AsmString[I] != '\0') {
7748 if (AsmString[I] == ' ' || AsmString[I] == '\t') {
7749 OS << '\t';
7750 ++I;
7751 }
7752 do {
7753 if (AsmString[I] == '$') {
7754 ++I;
7755 if (AsmString[I] == (char)0xff) {
7756 ++I;
7757 int OpIdx = AsmString[I++] - 1;
7758 int PrintMethodIdx = AsmString[I++] - 1;
7759 printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, STI, O&: OS);
7760 } else
7761 printOperand(MI, opNum: unsigned(AsmString[I++]) - 1, STI, OS);
7762 } else {
7763 OS << AsmString[I++];
7764 }
7765 } while (AsmString[I] != '\0');
7766 }
7767
7768 return true;
7769}
7770
7771void SparcInstPrinter::printCustomAliasOperand(
7772 const MCInst *MI, uint64_t Address, unsigned OpIdx,
7773 unsigned PrintMethodIdx,
7774 const MCSubtargetInfo &STI,
7775 raw_ostream &OS) {
7776 switch (PrintMethodIdx) {
7777 default:
7778 llvm_unreachable("Unknown PrintMethod kind");
7779 break;
7780 case 0:
7781 printCTILabel(MI, Address, OpNum: OpIdx, STI, O&: OS);
7782 break;
7783 }
7784}
7785
7786#endif // PRINT_ALIAS_INSTR
7787