1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Writer Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: Sparc.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10/// getMnemonic - This method is automatically generated by tablegen
11/// from the instruction set description.
12std::pair<const char *, uint64_t>
13SparcInstPrinter::getMnemonic(const MCInst &MI) const {
14
15#ifdef __GNUC__
16#pragma GCC diagnostic push
17#pragma GCC diagnostic ignored "-Woverlength-strings"
18#endif
19 static const char AsmStrs[] = {
20 /* 0 */ "fcmpd %fcc0, \000"
21 /* 14 */ "fcmpq %fcc0, \000"
22 /* 28 */ "fcmps %fcc0, \000"
23 /* 42 */ "rd %wim, \000"
24 /* 52 */ "rdpr %fq, \000"
25 /* 63 */ "rd %tbr, \000"
26 /* 73 */ "rd %psr, \000"
27 /* 83 */ "aes_kexpand0 \000"
28 /* 97 */ "aes_dround01 \000"
29 /* 111 */ "aes_eround01 \000"
30 /* 125 */ "fsrc1 \000"
31 /* 132 */ "aes_kexpand1 \000"
32 /* 146 */ "fandnot1 \000"
33 /* 156 */ "fnot1 \000"
34 /* 163 */ "fornot1 \000"
35 /* 172 */ "fsra32 \000"
36 /* 180 */ "fpsub32 \000"
37 /* 189 */ "fpadd32 \000"
38 /* 198 */ "edge32 \000"
39 /* 206 */ "fcmple32 \000"
40 /* 216 */ "fcmpne32 \000"
41 /* 226 */ "fpack32 \000"
42 /* 235 */ "cmask32 \000"
43 /* 244 */ "fsll32 \000"
44 /* 252 */ "fsrl32 \000"
45 /* 260 */ "fcmpeq32 \000"
46 /* 270 */ "fslas32 \000"
47 /* 279 */ "fcmpgt32 \000"
48 /* 289 */ "array32 \000"
49 /* 298 */ "fsrc2 \000"
50 /* 305 */ "aes_kexpand2 \000"
51 /* 319 */ "fandnot2 \000"
52 /* 329 */ "fnot2 \000"
53 /* 336 */ "fornot2 \000"
54 /* 345 */ "aes_dround23 \000"
55 /* 359 */ "aes_eround23 \000"
56 /* 373 */ "fpadd64 \000"
57 /* 382 */ "fsra16 \000"
58 /* 390 */ "fpsub16 \000"
59 /* 399 */ "fpadd16 \000"
60 /* 408 */ "edge16 \000"
61 /* 416 */ "fcmple16 \000"
62 /* 426 */ "fcmpne16 \000"
63 /* 436 */ "fpack16 \000"
64 /* 445 */ "cmask16 \000"
65 /* 454 */ "fsll16 \000"
66 /* 462 */ "fsrl16 \000"
67 /* 470 */ "fchksm16 \000"
68 /* 480 */ "fmean16 \000"
69 /* 489 */ "fcmpeq16 \000"
70 /* 499 */ "fslas16 \000"
71 /* 508 */ "fcmpgt16 \000"
72 /* 518 */ "fmul8x16 \000"
73 /* 528 */ "fmuld8ulx16 \000"
74 /* 541 */ "fmul8ulx16 \000"
75 /* 553 */ "fmuld8sux16 \000"
76 /* 566 */ "fmul8sux16 \000"
77 /* 578 */ "array16 \000"
78 /* 587 */ "edge8 \000"
79 /* 594 */ "cmask8 \000"
80 /* 602 */ "array8 \000"
81 /* 610 */ "!ADJCALLSTACKDOWN \000"
82 /* 629 */ "!ADJCALLSTACKUP \000"
83 /* 646 */ "stba \000"
84 /* 652 */ "stda \000"
85 /* 658 */ "stha \000"
86 /* 664 */ "stqa \000"
87 /* 670 */ "sra \000"
88 /* 675 */ "faligndata \000"
89 /* 687 */ "sta \000"
90 /* 692 */ "stxa \000"
91 /* 698 */ "stb \000"
92 /* 703 */ "sub \000"
93 /* 708 */ "crc32c \000"
94 /* 716 */ "smac \000"
95 /* 722 */ "umac \000"
96 /* 728 */ "tsubcc \000"
97 /* 736 */ "addxccc \000"
98 /* 745 */ "taddcc \000"
99 /* 753 */ "andcc \000"
100 /* 760 */ "smulcc \000"
101 /* 768 */ "umulcc \000"
102 /* 776 */ "andncc \000"
103 /* 784 */ "orncc \000"
104 /* 791 */ "xnorcc \000"
105 /* 799 */ "xorcc \000"
106 /* 806 */ "mulscc \000"
107 /* 814 */ "sdivcc \000"
108 /* 822 */ "udivcc \000"
109 /* 830 */ "subxcc \000"
110 /* 838 */ "addxcc \000"
111 /* 846 */ "popc \000"
112 /* 852 */ "addxc \000"
113 /* 859 */ "fsubd \000"
114 /* 866 */ "fhsubd \000"
115 /* 874 */ "fmsubd \000"
116 /* 882 */ "fnmsubd \000"
117 /* 891 */ "add \000"
118 /* 896 */ "faddd \000"
119 /* 903 */ "fhaddd \000"
120 /* 911 */ "fnhaddd \000"
121 /* 920 */ "fmaddd \000"
122 /* 928 */ "fnmaddd \000"
123 /* 937 */ "fnaddd \000"
124 /* 945 */ "fcmped \000"
125 /* 953 */ "fnegd \000"
126 /* 960 */ "fmuld \000"
127 /* 967 */ "fnmuld \000"
128 /* 975 */ "fsmuld \000"
129 /* 983 */ "fnsmuld \000"
130 /* 992 */ "fand \000"
131 /* 998 */ "fnand \000"
132 /* 1005 */ "fexpand \000"
133 /* 1014 */ "des_kexpand \000"
134 /* 1027 */ "des_round \000"
135 /* 1038 */ "fitod \000"
136 /* 1045 */ "fqtod \000"
137 /* 1052 */ "fstod \000"
138 /* 1059 */ "fxtod \000"
139 /* 1066 */ "movxtod \000"
140 /* 1075 */ "fcmpd \000"
141 /* 1082 */ "flcmpd \000"
142 /* 1090 */ "rd \000"
143 /* 1094 */ "fabsd \000"
144 /* 1101 */ "fsqrtd \000"
145 /* 1109 */ "std \000"
146 /* 1114 */ "fdivd \000"
147 /* 1121 */ "fmovd \000"
148 /* 1128 */ "fpmerge \000"
149 /* 1137 */ "bshuffle \000"
150 /* 1147 */ "fone \000"
151 /* 1153 */ "restore \000"
152 /* 1162 */ "save \000"
153 /* 1168 */ "camellia_f \000"
154 /* 1180 */ "flush \000"
155 /* 1187 */ "sth \000"
156 /* 1192 */ "sethi \000"
157 /* 1199 */ "fpmaddxhi \000"
158 /* 1210 */ "umulxhi \000"
159 /* 1219 */ "xmulxhi \000"
160 /* 1228 */ "camellia_fli \000"
161 /* 1242 */ "fdtoi \000"
162 /* 1249 */ "fqtoi \000"
163 /* 1256 */ "fstoi \000"
164 /* 1263 */ "bmask \000"
165 /* 1270 */ "edge32l \000"
166 /* 1279 */ "edge16l \000"
167 /* 1288 */ "edge8l \000"
168 /* 1296 */ "aes_dround01_l \000"
169 /* 1312 */ "aes_eround01_l \000"
170 /* 1328 */ "aes_dround23_l \000"
171 /* 1344 */ "aes_eround23_l \000"
172 /* 1360 */ "fmul8x16al \000"
173 /* 1372 */ "camellia_fl \000"
174 /* 1385 */ "call \000"
175 /* 1391 */ "sll \000"
176 /* 1396 */ "jmpl \000"
177 /* 1402 */ "alignaddrl \000"
178 /* 1414 */ "srl \000"
179 /* 1419 */ "mpmul \000"
180 /* 1426 */ "smul \000"
181 /* 1432 */ "montmul \000"
182 /* 1441 */ "umul \000"
183 /* 1447 */ "siam \000"
184 /* 1453 */ "edge32n \000"
185 /* 1462 */ "edge16n \000"
186 /* 1471 */ "edge8n \000"
187 /* 1479 */ "andn \000"
188 /* 1485 */ "edge32ln \000"
189 /* 1495 */ "edge16ln \000"
190 /* 1505 */ "edge8ln \000"
191 /* 1514 */ "orn \000"
192 /* 1519 */ "pdistn \000"
193 /* 1527 */ "fzero \000"
194 /* 1534 */ "des_ip \000"
195 /* 1542 */ "des_iip \000"
196 /* 1551 */ "unimp \000"
197 /* 1558 */ "jmp \000"
198 /* 1563 */ "fsubq \000"
199 /* 1570 */ "faddq \000"
200 /* 1577 */ "fcmpeq \000"
201 /* 1585 */ "fnegq \000"
202 /* 1592 */ "fdmulq \000"
203 /* 1600 */ "fmulq \000"
204 /* 1607 */ "fdtoq \000"
205 /* 1614 */ "fitoq \000"
206 /* 1621 */ "fstoq \000"
207 /* 1628 */ "fxtoq \000"
208 /* 1635 */ "fcmpq \000"
209 /* 1642 */ "fabsq \000"
210 /* 1649 */ "fsqrtq \000"
211 /* 1657 */ "stq \000"
212 /* 1662 */ "fdivq \000"
213 /* 1669 */ "fmovq \000"
214 /* 1676 */ "membar \000"
215 /* 1684 */ "alignaddr \000"
216 /* 1695 */ "sir \000"
217 /* 1700 */ "for \000"
218 /* 1705 */ "fnor \000"
219 /* 1711 */ "fxnor \000"
220 /* 1718 */ "fxor \000"
221 /* 1724 */ "rdpr \000"
222 /* 1730 */ "wrpr \000"
223 /* 1736 */ "montsqr \000"
224 /* 1745 */ "pwr \000"
225 /* 1750 */ "fsrc1s \000"
226 /* 1758 */ "fandnot1s \000"
227 /* 1769 */ "fnot1s \000"
228 /* 1777 */ "fornot1s \000"
229 /* 1787 */ "fpsub32s \000"
230 /* 1797 */ "fpadd32s \000"
231 /* 1807 */ "fsrc2s \000"
232 /* 1815 */ "fandnot2s \000"
233 /* 1826 */ "fnot2s \000"
234 /* 1834 */ "fornot2s \000"
235 /* 1844 */ "fpsub16s \000"
236 /* 1854 */ "fpadd16s \000"
237 /* 1864 */ "fsubs \000"
238 /* 1871 */ "fhsubs \000"
239 /* 1879 */ "fmsubs \000"
240 /* 1887 */ "fnmsubs \000"
241 /* 1896 */ "fadds \000"
242 /* 1903 */ "fhadds \000"
243 /* 1911 */ "fnhadds \000"
244 /* 1920 */ "fmadds \000"
245 /* 1928 */ "fnmadds \000"
246 /* 1937 */ "fnadds \000"
247 /* 1945 */ "fands \000"
248 /* 1952 */ "fnands \000"
249 /* 1960 */ "fones \000"
250 /* 1967 */ "fcmpes \000"
251 /* 1975 */ "fnegs \000"
252 /* 1982 */ "fmuls \000"
253 /* 1989 */ "fnmuls \000"
254 /* 1997 */ "fzeros \000"
255 /* 2005 */ "fdtos \000"
256 /* 2012 */ "fitos \000"
257 /* 2019 */ "fqtos \000"
258 /* 2026 */ "movwtos \000"
259 /* 2035 */ "fxtos \000"
260 /* 2042 */ "fcmps \000"
261 /* 2049 */ "flcmps \000"
262 /* 2057 */ "fors \000"
263 /* 2063 */ "fnors \000"
264 /* 2070 */ "fxnors \000"
265 /* 2078 */ "fxors \000"
266 /* 2085 */ "fabss \000"
267 /* 2092 */ "fsqrts \000"
268 /* 2100 */ "fdivs \000"
269 /* 2107 */ "fmovs \000"
270 /* 2114 */ "set \000"
271 /* 2119 */ "lzcnt \000"
272 /* 2126 */ "pdist \000"
273 /* 2133 */ "rett \000"
274 /* 2139 */ "fmul8x16au \000"
275 /* 2151 */ "sdiv \000"
276 /* 2157 */ "udiv \000"
277 /* 2163 */ "tsubcctv \000"
278 /* 2173 */ "taddcctv \000"
279 /* 2183 */ "movstosw \000"
280 /* 2193 */ "setsw \000"
281 /* 2200 */ "movstouw \000"
282 /* 2210 */ "srax \000"
283 /* 2216 */ "subx \000"
284 /* 2222 */ "fpmaddx \000"
285 /* 2231 */ "fpackfix \000"
286 /* 2241 */ "sllx \000"
287 /* 2247 */ "srlx \000"
288 /* 2253 */ "xmulx \000"
289 /* 2260 */ "fdtox \000"
290 /* 2267 */ "movdtox \000"
291 /* 2276 */ "fqtox \000"
292 /* 2283 */ "fstox \000"
293 /* 2290 */ "setx \000"
294 /* 2296 */ "stx \000"
295 /* 2301 */ "sdivx \000"
296 /* 2308 */ "udivx \000"
297 /* 2315 */ "; SELECT_CC_DFP_FCC PSEUDO!\000"
298 /* 2343 */ "; SELECT_CC_QFP_FCC PSEUDO!\000"
299 /* 2371 */ "; SELECT_CC_FP_FCC PSEUDO!\000"
300 /* 2398 */ "; SELECT_CC_Int_FCC PSEUDO!\000"
301 /* 2426 */ "; SELECT_CC_DFP_ICC PSEUDO!\000"
302 /* 2454 */ "; SELECT_CC_QFP_ICC PSEUDO!\000"
303 /* 2482 */ "; SELECT_CC_FP_ICC PSEUDO!\000"
304 /* 2509 */ "; SELECT_CC_Int_ICC PSEUDO!\000"
305 /* 2537 */ "; SELECT_CC_DFP_XCC PSEUDO!\000"
306 /* 2565 */ "; SELECT_CC_QFP_XCC PSEUDO!\000"
307 /* 2593 */ "; SELECT_CC_FP_XCC PSEUDO!\000"
308 /* 2620 */ "; SELECT_CC_Int_XCC PSEUDO!\000"
309 /* 2648 */ "jmp %i7+\000"
310 /* 2657 */ "jmp %o7+\000"
311 /* 2666 */ "# XRay Function Patchable RET.\000"
312 /* 2697 */ "# XRay Typed Event Log.\000"
313 /* 2721 */ "# XRay Custom Event Log.\000"
314 /* 2746 */ "# XRay Function Enter.\000"
315 /* 2769 */ "# XRay Tail Call Exit.\000"
316 /* 2792 */ "# XRay Function Exit.\000"
317 /* 2814 */ "flush %g0\000"
318 /* 2824 */ "ta 1\000"
319 /* 2829 */ "sha1\000"
320 /* 2834 */ "sha512\000"
321 /* 2841 */ "ta 3\000"
322 /* 2846 */ "ta 5\000"
323 /* 2851 */ "md5\000"
324 /* 2855 */ "sha256\000"
325 /* 2862 */ "LIFETIME_END\000"
326 /* 2875 */ "PSEUDO_PROBE\000"
327 /* 2888 */ "BUNDLE\000"
328 /* 2895 */ "FAKE_USE\000"
329 /* 2904 */ "DBG_VALUE\000"
330 /* 2914 */ "DBG_INSTR_REF\000"
331 /* 2928 */ "DBG_PHI\000"
332 /* 2936 */ "DBG_LABEL\000"
333 /* 2946 */ "!V8BAR\000"
334 /* 2953 */ "LIFETIME_START\000"
335 /* 2968 */ "DBG_VALUE_LIST\000"
336 /* 2983 */ "std %cq, [\000"
337 /* 2994 */ "std %fq, [\000"
338 /* 3005 */ "st %csr, [\000"
339 /* 3016 */ "st %fsr, [\000"
340 /* 3027 */ "stx %fsr, [\000"
341 /* 3039 */ "ldsba [\000"
342 /* 3047 */ "lduba [\000"
343 /* 3055 */ "ldstuba [\000"
344 /* 3065 */ "ldda [\000"
345 /* 3072 */ "lda [\000"
346 /* 3078 */ "prefetcha [\000"
347 /* 3090 */ "ldsha [\000"
348 /* 3098 */ "lduha [\000"
349 /* 3106 */ "swapa [\000"
350 /* 3114 */ "ldqa [\000"
351 /* 3121 */ "casa [\000"
352 /* 3128 */ "ldswa [\000"
353 /* 3136 */ "ldxa [\000"
354 /* 3143 */ "casxa [\000"
355 /* 3151 */ "ldsb [\000"
356 /* 3158 */ "ldub [\000"
357 /* 3165 */ "ldstub [\000"
358 /* 3174 */ "ldd [\000"
359 /* 3180 */ "ld [\000"
360 /* 3185 */ "prefetch [\000"
361 /* 3196 */ "ldsh [\000"
362 /* 3203 */ "lduh [\000"
363 /* 3210 */ "swap [\000"
364 /* 3217 */ "ldq [\000"
365 /* 3223 */ "ldsw [\000"
366 /* 3230 */ "ldx [\000"
367 /* 3236 */ "cb\000"
368 /* 3239 */ "fb\000"
369 /* 3242 */ "cwb\000"
370 /* 3246 */ "cxb\000"
371 /* 3250 */ "restored\000"
372 /* 3259 */ "saved\000"
373 /* 3265 */ "fmovrd\000"
374 /* 3272 */ "fmovd\000"
375 /* 3278 */ "done\000"
376 /* 3283 */ "# FEntry call\000"
377 /* 3297 */ "allclean\000"
378 /* 3306 */ "shutdown\000"
379 /* 3315 */ "nop\000"
380 /* 3319 */ "fmovrq\000"
381 /* 3326 */ "fmovq\000"
382 /* 3332 */ "stbar\000"
383 /* 3338 */ "br\000"
384 /* 3341 */ "movr\000"
385 /* 3346 */ "fmovrs\000"
386 /* 3353 */ "fmovs\000"
387 /* 3359 */ "t\000"
388 /* 3361 */ "mov\000"
389 /* 3365 */ "flushw\000"
390 /* 3372 */ "normalw\000"
391 /* 3380 */ "invalw\000"
392 /* 3387 */ "otherw\000"
393 /* 3394 */ "retry\000"
394};
395#ifdef __GNUC__
396#pragma GCC diagnostic pop
397#endif
398
399 static const uint32_t OpInfo0[] = {
400 0U, // PHI
401 0U, // INLINEASM
402 0U, // INLINEASM_BR
403 0U, // CFI_INSTRUCTION
404 0U, // EH_LABEL
405 0U, // GC_LABEL
406 0U, // ANNOTATION_LABEL
407 0U, // KILL
408 0U, // EXTRACT_SUBREG
409 0U, // INSERT_SUBREG
410 0U, // IMPLICIT_DEF
411 0U, // INIT_UNDEF
412 0U, // SUBREG_TO_REG
413 0U, // COPY_TO_REGCLASS
414 2905U, // DBG_VALUE
415 2969U, // DBG_VALUE_LIST
416 2915U, // DBG_INSTR_REF
417 2929U, // DBG_PHI
418 2937U, // DBG_LABEL
419 0U, // REG_SEQUENCE
420 0U, // COPY
421 0U, // COPY_LANEMASK
422 2889U, // BUNDLE
423 2954U, // LIFETIME_START
424 2863U, // LIFETIME_END
425 2876U, // PSEUDO_PROBE
426 0U, // ARITH_FENCE
427 0U, // STACKMAP
428 3284U, // FENTRY_CALL
429 0U, // PATCHPOINT
430 0U, // LOAD_STACK_GUARD
431 0U, // PREALLOCATED_SETUP
432 0U, // PREALLOCATED_ARG
433 0U, // STATEPOINT
434 0U, // LOCAL_ESCAPE
435 0U, // FAULTING_OP
436 0U, // PATCHABLE_OP
437 2747U, // PATCHABLE_FUNCTION_ENTER
438 2667U, // PATCHABLE_RET
439 2793U, // PATCHABLE_FUNCTION_EXIT
440 2770U, // PATCHABLE_TAIL_CALL
441 2722U, // PATCHABLE_EVENT_CALL
442 2698U, // PATCHABLE_TYPED_EVENT_CALL
443 0U, // ICALL_BRANCH_FUNNEL
444 2896U, // FAKE_USE
445 0U, // MEMBARRIER
446 0U, // JUMP_TABLE_DEBUG_INFO
447 0U, // RELOC_NONE
448 0U, // CONVERGENCECTRL_ENTRY
449 0U, // CONVERGENCECTRL_ANCHOR
450 0U, // CONVERGENCECTRL_LOOP
451 0U, // CONVERGENCECTRL_GLUE
452 0U, // G_ASSERT_SEXT
453 0U, // G_ASSERT_ZEXT
454 0U, // G_ASSERT_ALIGN
455 0U, // G_ADD
456 0U, // G_SUB
457 0U, // G_MUL
458 0U, // G_SDIV
459 0U, // G_UDIV
460 0U, // G_SREM
461 0U, // G_UREM
462 0U, // G_SDIVREM
463 0U, // G_UDIVREM
464 0U, // G_AND
465 0U, // G_OR
466 0U, // G_XOR
467 0U, // G_ABDS
468 0U, // G_ABDU
469 0U, // G_UAVGFLOOR
470 0U, // G_UAVGCEIL
471 0U, // G_SAVGFLOOR
472 0U, // G_SAVGCEIL
473 0U, // G_IMPLICIT_DEF
474 0U, // G_PHI
475 0U, // G_FRAME_INDEX
476 0U, // G_GLOBAL_VALUE
477 0U, // G_PTRAUTH_GLOBAL_VALUE
478 0U, // G_CONSTANT_POOL
479 0U, // G_EXTRACT
480 0U, // G_UNMERGE_VALUES
481 0U, // G_INSERT
482 0U, // G_MERGE_VALUES
483 0U, // G_BUILD_VECTOR
484 0U, // G_BUILD_VECTOR_TRUNC
485 0U, // G_CONCAT_VECTORS
486 0U, // G_PTRTOINT
487 0U, // G_INTTOPTR
488 0U, // G_BITCAST
489 0U, // G_FREEZE
490 0U, // G_CONSTANT_FOLD_BARRIER
491 0U, // G_INTRINSIC_FPTRUNC_ROUND
492 0U, // G_INTRINSIC_TRUNC
493 0U, // G_INTRINSIC_ROUND
494 0U, // G_INTRINSIC_LRINT
495 0U, // G_INTRINSIC_LLRINT
496 0U, // G_INTRINSIC_ROUNDEVEN
497 0U, // G_READCYCLECOUNTER
498 0U, // G_READSTEADYCOUNTER
499 0U, // G_LOAD
500 0U, // G_SEXTLOAD
501 0U, // G_ZEXTLOAD
502 0U, // G_FPEXTLOAD
503 0U, // G_INDEXED_LOAD
504 0U, // G_INDEXED_SEXTLOAD
505 0U, // G_INDEXED_ZEXTLOAD
506 0U, // G_STORE
507 0U, // G_FPTRUNCSTORE
508 0U, // G_INDEXED_STORE
509 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
510 0U, // G_ATOMIC_CMPXCHG
511 0U, // G_ATOMICRMW_XCHG
512 0U, // G_ATOMICRMW_ADD
513 0U, // G_ATOMICRMW_SUB
514 0U, // G_ATOMICRMW_AND
515 0U, // G_ATOMICRMW_NAND
516 0U, // G_ATOMICRMW_OR
517 0U, // G_ATOMICRMW_XOR
518 0U, // G_ATOMICRMW_MAX
519 0U, // G_ATOMICRMW_MIN
520 0U, // G_ATOMICRMW_UMAX
521 0U, // G_ATOMICRMW_UMIN
522 0U, // G_ATOMICRMW_FADD
523 0U, // G_ATOMICRMW_FSUB
524 0U, // G_ATOMICRMW_FMAX
525 0U, // G_ATOMICRMW_FMIN
526 0U, // G_ATOMICRMW_FMAXIMUM
527 0U, // G_ATOMICRMW_FMINIMUM
528 0U, // G_ATOMICRMW_FMAXIMUMNUM
529 0U, // G_ATOMICRMW_FMINIMUMNUM
530 0U, // G_ATOMICRMW_UINC_WRAP
531 0U, // G_ATOMICRMW_UDEC_WRAP
532 0U, // G_ATOMICRMW_USUB_COND
533 0U, // G_ATOMICRMW_USUB_SAT
534 0U, // G_FENCE
535 0U, // G_PREFETCH
536 0U, // G_BRCOND
537 0U, // G_BRINDIRECT
538 0U, // G_INVOKE_REGION_START
539 0U, // G_INTRINSIC
540 0U, // G_INTRINSIC_W_SIDE_EFFECTS
541 0U, // G_INTRINSIC_CONVERGENT
542 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
543 0U, // G_ANYEXT
544 0U, // G_TRUNC
545 0U, // G_TRUNC_SSAT_S
546 0U, // G_TRUNC_SSAT_U
547 0U, // G_TRUNC_USAT_U
548 0U, // G_CONSTANT
549 0U, // G_FCONSTANT
550 0U, // G_VASTART
551 0U, // G_VAARG
552 0U, // G_SEXT
553 0U, // G_SEXT_INREG
554 0U, // G_ZEXT
555 0U, // G_SHL
556 0U, // G_LSHR
557 0U, // G_ASHR
558 0U, // G_FSHL
559 0U, // G_FSHR
560 0U, // G_ROTR
561 0U, // G_ROTL
562 0U, // G_ICMP
563 0U, // G_FCMP
564 0U, // G_SCMP
565 0U, // G_UCMP
566 0U, // G_SELECT
567 0U, // G_UADDO
568 0U, // G_UADDE
569 0U, // G_USUBO
570 0U, // G_USUBE
571 0U, // G_SADDO
572 0U, // G_SADDE
573 0U, // G_SSUBO
574 0U, // G_SSUBE
575 0U, // G_UMULO
576 0U, // G_SMULO
577 0U, // G_UMULH
578 0U, // G_SMULH
579 0U, // G_UADDSAT
580 0U, // G_SADDSAT
581 0U, // G_USUBSAT
582 0U, // G_SSUBSAT
583 0U, // G_USHLSAT
584 0U, // G_SSHLSAT
585 0U, // G_SMULFIX
586 0U, // G_UMULFIX
587 0U, // G_SMULFIXSAT
588 0U, // G_UMULFIXSAT
589 0U, // G_SDIVFIX
590 0U, // G_UDIVFIX
591 0U, // G_SDIVFIXSAT
592 0U, // G_UDIVFIXSAT
593 0U, // G_FADD
594 0U, // G_FSUB
595 0U, // G_FMUL
596 0U, // G_FMA
597 0U, // G_FMAD
598 0U, // G_FDIV
599 0U, // G_FREM
600 0U, // G_FMODF
601 0U, // G_FPOW
602 0U, // G_FPOWI
603 0U, // G_FEXP
604 0U, // G_FEXP2
605 0U, // G_FEXP10
606 0U, // G_FLOG
607 0U, // G_FLOG2
608 0U, // G_FLOG10
609 0U, // G_FLDEXP
610 0U, // G_FFREXP
611 0U, // G_FNEG
612 0U, // G_FPEXT
613 0U, // G_FPTRUNC
614 0U, // G_FPTOSI
615 0U, // G_FPTOUI
616 0U, // G_SITOFP
617 0U, // G_UITOFP
618 0U, // G_FPTOSI_SAT
619 0U, // G_FPTOUI_SAT
620 0U, // G_FABS
621 0U, // G_FCOPYSIGN
622 0U, // G_IS_FPCLASS
623 0U, // G_FCANONICALIZE
624 0U, // G_FMINNUM
625 0U, // G_FMAXNUM
626 0U, // G_FMINNUM_IEEE
627 0U, // G_FMAXNUM_IEEE
628 0U, // G_FMINIMUM
629 0U, // G_FMAXIMUM
630 0U, // G_FMINIMUMNUM
631 0U, // G_FMAXIMUMNUM
632 0U, // G_GET_FPENV
633 0U, // G_SET_FPENV
634 0U, // G_RESET_FPENV
635 0U, // G_GET_FPMODE
636 0U, // G_SET_FPMODE
637 0U, // G_RESET_FPMODE
638 0U, // G_GET_ROUNDING
639 0U, // G_SET_ROUNDING
640 0U, // G_PTR_ADD
641 0U, // G_PTRMASK
642 0U, // G_SMIN
643 0U, // G_SMAX
644 0U, // G_UMIN
645 0U, // G_UMAX
646 0U, // G_ABS
647 0U, // G_LROUND
648 0U, // G_LLROUND
649 0U, // G_BR
650 0U, // G_BRJT
651 0U, // G_VSCALE
652 0U, // G_INSERT_SUBVECTOR
653 0U, // G_EXTRACT_SUBVECTOR
654 0U, // G_INSERT_VECTOR_ELT
655 0U, // G_EXTRACT_VECTOR_ELT
656 0U, // G_SHUFFLE_VECTOR
657 0U, // G_SPLAT_VECTOR
658 0U, // G_STEP_VECTOR
659 0U, // G_VECTOR_COMPRESS
660 0U, // G_CTTZ
661 0U, // G_CTTZ_ZERO_POISON
662 0U, // G_CTLZ
663 0U, // G_CTLZ_ZERO_POISON
664 0U, // G_CTLS
665 0U, // G_CTPOP
666 0U, // G_BSWAP
667 0U, // G_BITREVERSE
668 0U, // G_CLMUL
669 0U, // G_CLMULH
670 0U, // G_FCEIL
671 0U, // G_FCOS
672 0U, // G_FSIN
673 0U, // G_FSINCOS
674 0U, // G_FTAN
675 0U, // G_FACOS
676 0U, // G_FASIN
677 0U, // G_FATAN
678 0U, // G_FATAN2
679 0U, // G_FCOSH
680 0U, // G_FSINH
681 0U, // G_FTANH
682 0U, // G_FSQRT
683 0U, // G_FFLOOR
684 0U, // G_FRINT
685 0U, // G_FNEARBYINT
686 0U, // G_ADDRSPACE_CAST
687 0U, // G_BLOCK_ADDR
688 0U, // G_JUMP_TABLE
689 0U, // G_DYN_STACKALLOC
690 0U, // G_STACKSAVE
691 0U, // G_STACKRESTORE
692 0U, // G_STRICT_FADD
693 0U, // G_STRICT_FSUB
694 0U, // G_STRICT_FMUL
695 0U, // G_STRICT_FDIV
696 0U, // G_STRICT_FREM
697 0U, // G_STRICT_FMA
698 0U, // G_STRICT_FSQRT
699 0U, // G_STRICT_FLDEXP
700 0U, // G_STRICT_FCMP
701 0U, // G_STRICT_FCMPS
702 0U, // G_READ_REGISTER
703 0U, // G_WRITE_REGISTER
704 0U, // G_MEMCPY
705 0U, // G_MEMCPY_INLINE
706 0U, // G_MEMMOVE
707 0U, // G_MEMSET
708 0U, // G_BZERO
709 0U, // G_MEMSET_INLINE
710 0U, // G_TRAP
711 0U, // G_DEBUGTRAP
712 0U, // G_UBSANTRAP
713 0U, // G_VECREDUCE_SEQ_FADD
714 0U, // G_VECREDUCE_SEQ_FMUL
715 0U, // G_VECREDUCE_FADD
716 0U, // G_VECREDUCE_FMUL
717 0U, // G_VECREDUCE_FMAX
718 0U, // G_VECREDUCE_FMIN
719 0U, // G_VECREDUCE_FMAXIMUM
720 0U, // G_VECREDUCE_FMINIMUM
721 0U, // G_VECREDUCE_FMAXIMUMNUM
722 0U, // G_VECREDUCE_FMINIMUMNUM
723 0U, // G_VECREDUCE_ADD
724 0U, // G_VECREDUCE_MUL
725 0U, // G_VECREDUCE_AND
726 0U, // G_VECREDUCE_OR
727 0U, // G_VECREDUCE_XOR
728 0U, // G_VECREDUCE_SMAX
729 0U, // G_VECREDUCE_SMIN
730 0U, // G_VECREDUCE_UMAX
731 0U, // G_VECREDUCE_UMIN
732 0U, // G_SBFX
733 0U, // G_UBFX
734 4707U, // ADJCALLSTACKDOWN
735 70262U, // ADJCALLSTACKUP
736 8206U, // GETPCX
737 2316U, // SELECT_CC_DFP_FCC
738 2427U, // SELECT_CC_DFP_ICC
739 2538U, // SELECT_CC_DFP_XCC
740 2372U, // SELECT_CC_FP_FCC
741 2483U, // SELECT_CC_FP_ICC
742 2594U, // SELECT_CC_FP_XCC
743 2399U, // SELECT_CC_Int_FCC
744 2510U, // SELECT_CC_Int_ICC
745 2621U, // SELECT_CC_Int_XCC
746 2344U, // SELECT_CC_QFP_FCC
747 2455U, // SELECT_CC_QFP_ICC
748 2566U, // SELECT_CC_QFP_XCC
749 2111555U, // SET
750 2111634U, // SETSW
751 20986099U, // SETX
752 2947U, // V8BAR
753 20984555U, // ADDCCri
754 20984555U, // ADDCCrr
755 20986034U, // ADDCri
756 20986034U, // ADDCrr
757 20984647U, // ADDEri
758 20984647U, // ADDErr
759 20984661U, // ADDXC
760 20984545U, // ADDXCCC
761 20984700U, // ADDri
762 20984700U, // ADDrr
763 692072546U, // AES_DROUND01
764 692073745U, // AES_DROUND01_LAST
765 692072794U, // AES_DROUND23
766 692073777U, // AES_DROUND23_LAST
767 692072560U, // AES_EROUND01
768 692073761U, // AES_EROUND01_LAST
769 692072808U, // AES_EROUND23
770 692073793U, // AES_EROUND23_LAST
771 20983892U, // AES_KEXPAND0
772 692072581U, // AES_KEXPAND1
773 20984114U, // AES_KEXPAND2
774 20985493U, // ALIGNADDR
775 20985211U, // ALIGNADDRL
776 3298U, // ALLCLEAN
777 20984562U, // ANDCCri
778 20984562U, // ANDCCrr
779 20984585U, // ANDNCCri
780 20984585U, // ANDNCCrr
781 20985288U, // ANDNri
782 20985288U, // ANDNrr
783 20984802U, // ANDri
784 20984802U, // ANDrr
785 20984387U, // ARRAY16
786 20984098U, // ARRAY32
787 20984411U, // ARRAY8
788 82569U, // BA
789 6446246U, // BCOND
790 6511782U, // BCONDA
791 91671U, // BINDri
792 91671U, // BINDrr
793 20985072U, // BMASK
794 289561768U, // BPFCC
795 289627304U, // BPFCCA
796 285864U, // BPFCCANT
797 351400U, // BPFCCNT
798 6708390U, // BPICC
799 482470U, // BPICCA
800 548006U, // BPICCANT
801 613542U, // BPICCNT
802 289561867U, // BPR
803 289627403U, // BPRA
804 285963U, // BPRANT
805 351499U, // BPRNT
806 6970534U, // BPXCC
807 744614U, // BPXCCA
808 810150U, // BPXCCANT
809 875686U, // BPXCCNT
810 20984946U, // BSHUFFLE
811 83306U, // CALL
812 17770U, // CALLi
813 91498U, // CALLri
814 4220266U, // CALLrii
815 91498U, // CALLrr
816 4220266U, // CALLrri
817 692073617U, // CAMELLIA_F
818 20985181U, // CAMELLIA_FL
819 20985037U, // CAMELLIA_FLI
820 21904434U, // CASAri
821 9387058U, // CASArr
822 21904456U, // CASXAri
823 9387080U, // CASXArr
824 70078U, // CMASK16
825 69868U, // CMASK32
826 70227U, // CMASK8
827 6446245U, // CPBCOND
828 6511781U, // CPBCONDA
829 20984517U, // CRC32C
830 1765956779U, // CWBCONDri
831 1765956779U, // CWBCONDrr
832 1765956783U, // CXBCONDri
833 1765956783U, // CXBCONDrr
834 2110983U, // DES_IIP
835 2110975U, // DES_IP
836 20984823U, // DES_KEXPAND
837 692073476U, // DES_ROUND
838 3279U, // DONE
839 20984217U, // EDGE16
840 20985088U, // EDGE16L
841 20985304U, // EDGE16LN
842 20985271U, // EDGE16N
843 20984007U, // EDGE32
844 20985079U, // EDGE32L
845 20985294U, // EDGE32LN
846 20985262U, // EDGE32N
847 20984396U, // EDGE8
848 20985097U, // EDGE8L
849 20985314U, // EDGE8LN
850 20985280U, // EDGE8N
851 2110535U, // FABSD
852 2111083U, // FABSQ
853 2111526U, // FABSS
854 20984705U, // FADDD
855 20985379U, // FADDQ
856 20985705U, // FADDS
857 20984484U, // FALIGNADATA
858 20984801U, // FAND
859 20983955U, // FANDNOT1
860 20985567U, // FANDNOT1S
861 20984128U, // FANDNOT2
862 20985624U, // FANDNOT2S
863 20985754U, // FANDS
864 6446248U, // FBCOND
865 6511784U, // FBCONDA
866 1072296U, // FBCONDA_V9
867 7429288U, // FBCOND_V9
868 20984279U, // FCHKSM16
869 5172U, // FCMPD
870 4097U, // FCMPD_V9
871 20984298U, // FCMPEQ16
872 20984069U, // FCMPEQ32
873 20984317U, // FCMPGT16
874 20984088U, // FCMPGT32
875 20984225U, // FCMPLE16
876 20984015U, // FCMPLE32
877 20984235U, // FCMPNE16
878 20984025U, // FCMPNE32
879 5732U, // FCMPQ
880 4111U, // FCMPQ_V9
881 6139U, // FCMPS
882 4125U, // FCMPS_V9
883 20984923U, // FDIVD
884 20985471U, // FDIVQ
885 20985909U, // FDIVS
886 20985401U, // FDMULQ
887 2110683U, // FDTOI
888 2111048U, // FDTOQ
889 2111446U, // FDTOS
890 2111701U, // FDTOX
891 2110446U, // FEXPAND
892 20984712U, // FHADDD
893 20985712U, // FHADDS
894 20984675U, // FHSUBD
895 20985680U, // FHSUBS
896 2110479U, // FITOD
897 2111055U, // FITOQ
898 2111453U, // FITOS
899 419435579U, // FLCMPD
900 419436546U, // FLCMPS
901 2815U, // FLUSH
902 3366U, // FLUSHW
903 91293U, // FLUSHri
904 91293U, // FLUSHrr
905 692073369U, // FMADDD
906 692074369U, // FMADDS
907 20984289U, // FMEAN16
908 2110562U, // FMOVD
909 17923273U, // FMOVD_FCC
910 17202377U, // FMOVD_ICC
911 17464521U, // FMOVD_XCC
912 2111110U, // FMOVQ
913 17923327U, // FMOVQ_FCC
914 17202431U, // FMOVQ_ICC
915 17464575U, // FMOVQ_XCC
916 36034U, // FMOVRD
917 36088U, // FMOVRQ
918 36115U, // FMOVRS
919 2111548U, // FMOVS
920 17923354U, // FMOVS_FCC
921 17202458U, // FMOVS_ICC
922 17464602U, // FMOVS_XCC
923 692073323U, // FMSUBD
924 692074328U, // FMSUBS
925 20984375U, // FMUL8SUX16
926 20984350U, // FMUL8ULX16
927 20984327U, // FMUL8X16
928 20985169U, // FMUL8X16AL
929 20985948U, // FMUL8X16AU
930 20984769U, // FMULD
931 20984362U, // FMULD8SUX16
932 20984337U, // FMULD8ULX16
933 20985409U, // FMULQ
934 20985791U, // FMULS
935 20984746U, // FNADDD
936 20985746U, // FNADDS
937 20984807U, // FNAND
938 20985761U, // FNANDS
939 2110394U, // FNEGD
940 2111026U, // FNEGQ
941 2111416U, // FNEGS
942 20984720U, // FNHADDD
943 20985720U, // FNHADDS
944 692073377U, // FNMADDD
945 692074377U, // FNMADDS
946 692073331U, // FNMSUBD
947 692074336U, // FNMSUBS
948 20984776U, // FNMULD
949 20985798U, // FNMULS
950 20985514U, // FNOR
951 20985872U, // FNORS
952 2109597U, // FNOT1
953 2111210U, // FNOT1S
954 2109770U, // FNOT2
955 2111267U, // FNOT2S
956 20984792U, // FNSMULD
957 70780U, // FONE
958 71593U, // FONES
959 20985509U, // FOR
960 20983972U, // FORNOT1
961 20985586U, // FORNOT1S
962 20984145U, // FORNOT2
963 20985643U, // FORNOT2S
964 20985866U, // FORS
965 2109877U, // FPACK16
966 20984035U, // FPACK32
967 2111672U, // FPACKFIX
968 20984208U, // FPADD16
969 20985663U, // FPADD16S
970 20983998U, // FPADD32
971 20985606U, // FPADD32S
972 20984182U, // FPADD64
973 692074671U, // FPMADDX
974 692073648U, // FPMADDXHI
975 20984937U, // FPMERGE
976 20984199U, // FPSUB16
977 20985653U, // FPSUB16S
978 20983989U, // FPSUB32
979 20985596U, // FPSUB32S
980 2110486U, // FQTOD
981 2110690U, // FQTOI
982 2111460U, // FQTOS
983 2111717U, // FQTOX
984 20984308U, // FSLAS16
985 20984079U, // FSLAS32
986 20984263U, // FSLL16
987 20984053U, // FSLL32
988 20984784U, // FSMULD
989 2110542U, // FSQRTD
990 2111090U, // FSQRTQ
991 2111533U, // FSQRTS
992 20984191U, // FSRA16
993 20983981U, // FSRA32
994 2109566U, // FSRC1
995 2111191U, // FSRC1S
996 2109739U, // FSRC2
997 2111248U, // FSRC2S
998 20984271U, // FSRL16
999 20984061U, // FSRL32
1000 2110493U, // FSTOD
1001 2110697U, // FSTOI
1002 2111062U, // FSTOQ
1003 2111724U, // FSTOX
1004 20984668U, // FSUBD
1005 20985372U, // FSUBQ
1006 20985673U, // FSUBS
1007 20985520U, // FXNOR
1008 20985879U, // FXNORS
1009 20985527U, // FXOR
1010 20985887U, // FXORS
1011 2110500U, // FXTOD
1012 2111069U, // FXTOQ
1013 2111476U, // FXTOS
1014 71160U, // FZERO
1015 71630U, // FZEROS
1016 154311839U, // GDOP_LDXrr
1017 154311789U, // GDOP_LDrr
1018 3381U, // INVALW
1019 2135413U, // JMPLri
1020 2135413U, // JMPLrr
1021 3054593U, // LDAri
1022 28285953U, // LDArr
1023 1272941U, // LDCSRri
1024 1272941U, // LDCSRrr
1025 3316845U, // LDCri
1026 3316845U, // LDCrr
1027 3054586U, // LDDAri
1028 28285946U, // LDDArr
1029 3316839U, // LDDCri
1030 3316839U, // LDDCrr
1031 3054586U, // LDDFAri
1032 28285946U, // LDDFArr
1033 3316839U, // LDDFri
1034 3316839U, // LDDFrr
1035 3316839U, // LDDri
1036 3316839U, // LDDrr
1037 3054593U, // LDFAri
1038 28285953U, // LDFArr
1039 1338477U, // LDFSRri
1040 1338477U, // LDFSRrr
1041 3316845U, // LDFri
1042 3316845U, // LDFrr
1043 3054635U, // LDQFAri
1044 28285995U, // LDQFArr
1045 3316882U, // LDQFri
1046 3316882U, // LDQFrr
1047 3054560U, // LDSBAri
1048 28285920U, // LDSBArr
1049 3316816U, // LDSBri
1050 3316816U, // LDSBrr
1051 3054611U, // LDSHAri
1052 28285971U, // LDSHArr
1053 3316861U, // LDSHri
1054 3316861U, // LDSHrr
1055 3054576U, // LDSTUBAri
1056 28285936U, // LDSTUBArr
1057 3316830U, // LDSTUBri
1058 3316830U, // LDSTUBrr
1059 3054649U, // LDSWAri
1060 28286009U, // LDSWArr
1061 3316888U, // LDSWri
1062 3316888U, // LDSWrr
1063 3054568U, // LDUBAri
1064 28285928U, // LDUBArr
1065 3316823U, // LDUBri
1066 3316823U, // LDUBrr
1067 3054619U, // LDUHAri
1068 28285979U, // LDUHArr
1069 3316868U, // LDUHri
1070 3316868U, // LDUHrr
1071 3054657U, // LDXAri
1072 28286017U, // LDXArr
1073 1338527U, // LDXFSRri
1074 1338527U, // LDXFSRrr
1075 3316895U, // LDXri
1076 3316895U, // LDXrr
1077 3316845U, // LDri
1078 3316845U, // LDrr
1079 2111560U, // LZCNT
1080 2852U, // MD5
1081 42637U, // MEMBARi
1082 71065U, // MONTMUL
1083 71369U, // MONTSQR
1084 2111708U, // MOVDTOX
1085 17923362U, // MOVFCCri
1086 17923362U, // MOVFCCrr
1087 17202466U, // MOVICCri
1088 17202466U, // MOVICCrr
1089 36110U, // MOVRri
1090 36110U, // MOVRrr
1091 2111624U, // MOVSTOSW
1092 2111641U, // MOVSTOUW
1093 2111467U, // MOVWTOS
1094 17464610U, // MOVXCCri
1095 17464610U, // MOVXCCrr
1096 2110507U, // MOVXTOD
1097 71052U, // MPMUL
1098 20984615U, // MULSCCri
1099 20984615U, // MULSCCrr
1100 20986063U, // MULXri
1101 20986063U, // MULXrr
1102 3316U, // NOP
1103 3373U, // NORMALW
1104 20984602U, // ORCCri
1105 20984602U, // ORCCrr
1106 20984593U, // ORNCCri
1107 20984593U, // ORNCCrr
1108 20985323U, // ORNri
1109 20985323U, // ORNrr
1110 20985510U, // ORri
1111 20985510U, // ORrr
1112 3388U, // OTHERW
1113 20985935U, // PDIST
1114 20985328U, // PDISTN
1115 2110287U, // POPCrr
1116 13528071U, // PREFETCHAi
1117 15690759U, // PREFETCHAr
1118 13790322U, // PREFETCHi
1119 13790322U, // PREFETCHr
1120 33560274U, // PWRPSRri
1121 33560274U, // PWRPSRrr
1122 2110531U, // RDASR
1123 69685U, // RDFQ
1124 2111165U, // RDPR
1125 69706U, // RDPSR
1126 69696U, // RDTBR
1127 69675U, // RDWIM
1128 3251U, // RESTORED
1129 20984962U, // RESTOREri
1130 20984962U, // RESTORErr
1131 72281U, // RET
1132 72290U, // RETL
1133 3395U, // RETRY
1134 92246U, // RETTri
1135 92246U, // RETTrr
1136 3260U, // SAVED
1137 20984971U, // SAVEri
1138 20984971U, // SAVErr
1139 20984623U, // SDIVCCri
1140 20984623U, // SDIVCCrr
1141 20986110U, // SDIVXri
1142 20986110U, // SDIVXrr
1143 20985960U, // SDIVri
1144 20985960U, // SDIVrr
1145 2110633U, // SETHIi
1146 2830U, // SHA1
1147 2856U, // SHA256
1148 2835U, // SHA512
1149 3307U, // SHUTDOWN
1150 71080U, // SIAM
1151 71328U, // SIR
1152 20986050U, // SLLXri
1153 20986050U, // SLLXrr
1154 20985200U, // SLLri
1155 20985200U, // SLLrr
1156 20984525U, // SMACri
1157 20984525U, // SMACrr
1158 20984569U, // SMULCCri
1159 20984569U, // SMULCCrr
1160 20985235U, // SMULri
1161 20985235U, // SMULrr
1162 20986019U, // SRAXri
1163 20986019U, // SRAXrr
1164 20984479U, // SRAri
1165 20984479U, // SRArr
1166 20986056U, // SRLXri
1167 20986056U, // SRLXrr
1168 20985223U, // SRLri
1169 20985223U, // SRLrr
1170 1422000U, // STAri
1171 11514544U, // STArr
1172 3333U, // STBAR
1173 1421959U, // STBAri
1174 11514503U, // STBArr
1175 1487547U, // STBri
1176 1487547U, // STBrr
1177 1469374U, // STCSRri
1178 1469374U, // STCSRrr
1179 1488978U, // STCri
1180 1488978U, // STCrr
1181 1421965U, // STDAri
1182 11514509U, // STDArr
1183 1469352U, // STDCQri
1184 1469352U, // STDCQrr
1185 1487958U, // STDCri
1186 1487958U, // STDCrr
1187 1421965U, // STDFAri
1188 11514509U, // STDFArr
1189 1469363U, // STDFQri
1190 1469363U, // STDFQrr
1191 1487958U, // STDFri
1192 1487958U, // STDFrr
1193 1487958U, // STDri
1194 1487958U, // STDrr
1195 1422000U, // STFAri
1196 11514544U, // STFArr
1197 1469385U, // STFSRri
1198 1469385U, // STFSRrr
1199 1488978U, // STFri
1200 1488978U, // STFrr
1201 1421971U, // STHAri
1202 11514515U, // STHArr
1203 1488036U, // STHri
1204 1488036U, // STHrr
1205 1421977U, // STQFAri
1206 11514521U, // STQFArr
1207 1488506U, // STQFri
1208 1488506U, // STQFrr
1209 1422005U, // STXAri
1210 11514549U, // STXArr
1211 1469396U, // STXFSRri
1212 1469396U, // STXFSRrr
1213 1489145U, // STXri
1214 1489145U, // STXrr
1215 1488978U, // STri
1216 1488978U, // STrr
1217 20984538U, // SUBCCri
1218 20984538U, // SUBCCrr
1219 20986025U, // SUBCri
1220 20986025U, // SUBCrr
1221 20984639U, // SUBEri
1222 20984639U, // SUBErr
1223 20984512U, // SUBri
1224 20984512U, // SUBrr
1225 3054627U, // SWAPAri
1226 28285987U, // SWAPArr
1227 3316875U, // SWAPri
1228 3316875U, // SWAPrr
1229 2825U, // TA1
1230 2842U, // TA3
1231 2847U, // TA5
1232 20985982U, // TADDCCTVri
1233 20985982U, // TADDCCTVrr
1234 20984554U, // TADDCCri
1235 20984554U, // TADDCCrr
1236 83306U, // TAIL_CALL
1237 91671U, // TAIL_CALLri
1238 52874528U, // TICCri
1239 52874528U, // TICCrr
1240 2705339260U, // TLS_ADDrr
1241 17770U, // TLS_CALL
1242 154311839U, // TLS_LDXrr
1243 154311789U, // TLS_LDrr
1244 52612384U, // TRAPri
1245 52612384U, // TRAPrr
1246 20985972U, // TSUBCCTVri
1247 20985972U, // TSUBCCTVrr
1248 20984537U, // TSUBCCri
1249 20984537U, // TSUBCCrr
1250 53136672U, // TXCCri
1251 53136672U, // TXCCrr
1252 20984631U, // UDIVCCri
1253 20984631U, // UDIVCCrr
1254 20986117U, // UDIVXri
1255 20986117U, // UDIVXrr
1256 20985966U, // UDIVri
1257 20985966U, // UDIVrr
1258 20984531U, // UMACri
1259 20984531U, // UMACrr
1260 20984577U, // UMULCCri
1261 20984577U, // UMULCCrr
1262 20985019U, // UMULXHI
1263 20985250U, // UMULri
1264 20985250U, // UMULrr
1265 71184U, // UNIMP
1266 419435572U, // V9FCMPD
1267 419435442U, // V9FCMPED
1268 419436074U, // V9FCMPEQ
1269 419436464U, // V9FCMPES
1270 419436132U, // V9FCMPQ
1271 419436539U, // V9FCMPS
1272 36041U, // V9FMOVD_FCC
1273 36095U, // V9FMOVQ_FCC
1274 36122U, // V9FMOVS_FCC
1275 36130U, // V9MOVFCCri
1276 36130U, // V9MOVFCCrr
1277 20985555U, // WRASRri
1278 20985555U, // WRASRrr
1279 20985539U, // WRPRri
1280 20985539U, // WRPRrr
1281 33560275U, // WRPSRri
1282 33560275U, // WRPSRrr
1283 67114707U, // WRTBRri
1284 67114707U, // WRTBRrr
1285 83891923U, // WRWIMri
1286 83891923U, // WRWIMrr
1287 20986062U, // XMULX
1288 20985028U, // XMULXHI
1289 20984600U, // XNORCCri
1290 20984600U, // XNORCCrr
1291 20985521U, // XNORri
1292 20985521U, // XNORrr
1293 20984608U, // XORCCri
1294 20984608U, // XORCCrr
1295 20985528U, // XORri
1296 20985528U, // XORrr
1297 };
1298
1299 // Emit the opcode for the instruction.
1300 uint32_t Bits = 0;
1301 Bits |= OpInfo0[MI.getOpcode()] << 0;
1302 if (Bits == 0)
1303 return {nullptr, Bits};
1304 return {AsmStrs+(Bits & 4095)-1, Bits};
1305
1306}
1307/// printInstruction - This method is automatically generated by tablegen
1308/// from the instruction set description.
1309LLVM_NO_PROFILE_INSTRUMENT_FUNCTION
1310void SparcInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) {
1311 O << "\t";
1312
1313 auto MnemonicInfo = getMnemonic(MI: *MI);
1314
1315 O << MnemonicInfo.first;
1316
1317 uint32_t Bits = MnemonicInfo.second;
1318 assert(Bits != 0 && "Cannot print this instruction.");
1319
1320 // Fragment 0 encoded into 4 bits for 13 unique commands.
1321 switch ((Bits >> 12) & 15) {
1322 default: llvm_unreachable("Invalid command number.");
1323 case 0:
1324 // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
1325 return;
1326 break;
1327 case 1:
1328 // ADJCALLSTACKDOWN, ADJCALLSTACKUP, CMASK16, CMASK32, CMASK8, FCMPD, FCM...
1329 printOperand(MI, opNum: 0, STI, OS&: O);
1330 break;
1331 case 2:
1332 // GETPCX
1333 printGetPCX(MI, OpNo: 0, STI, OS&: O);
1334 return;
1335 break;
1336 case 3:
1337 // SET, SETSW, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, AD...
1338 printOperand(MI, opNum: 1, STI, OS&: O);
1339 break;
1340 case 4:
1341 // BA, CALL, CALLi, TAIL_CALL, TLS_CALL
1342 printCTILabel(MI, Address, OpNum: 0, STI, O);
1343 break;
1344 case 5:
1345 // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
1346 printCCOperand(MI, opNum: 1, STI, OS&: O);
1347 break;
1348 case 6:
1349 // BINDri, BINDrr, CALLri, CALLrii, CALLrr, CALLrri, FLUSHri, FLUSHrr, LD...
1350 printMemOperand(MI, opNum: 0, STI, OS&: O);
1351 break;
1352 case 7:
1353 // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
1354 printCCOperand(MI, opNum: 3, STI, OS&: O);
1355 break;
1356 case 8:
1357 // FMOVRD, FMOVRQ, FMOVRS, MOVRri, MOVRrr, V9FMOVD_FCC, V9FMOVQ_FCC, V9FM...
1358 printCCOperand(MI, opNum: 4, STI, OS&: O);
1359 O << ' ';
1360 printOperand(MI, opNum: 1, STI, OS&: O);
1361 O << ", ";
1362 printOperand(MI, opNum: 2, STI, OS&: O);
1363 O << ", ";
1364 printOperand(MI, opNum: 0, STI, OS&: O);
1365 return;
1366 break;
1367 case 9:
1368 // GDOP_LDXrr, GDOP_LDrr, JMPLri, JMPLrr, LDAri, LDArr, LDCri, LDCrr, LDD...
1369 printMemOperand(MI, opNum: 1, STI, OS&: O);
1370 break;
1371 case 10:
1372 // MEMBARi
1373 printMembarTag(MI, opNum: 0, STI, O);
1374 return;
1375 break;
1376 case 11:
1377 // STAri, STArr, STBAri, STBArr, STBri, STBrr, STCri, STCrr, STDAri, STDA...
1378 printOperand(MI, opNum: 2, STI, OS&: O);
1379 O << ", [";
1380 printMemOperand(MI, opNum: 0, STI, OS&: O);
1381 break;
1382 case 12:
1383 // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr
1384 printCCOperand(MI, opNum: 2, STI, OS&: O);
1385 break;
1386 }
1387
1388
1389 // Fragment 1 encoded into 5 bits for 23 unique commands.
1390 switch ((Bits >> 16) & 31) {
1391 default: llvm_unreachable("Invalid command number.");
1392 case 0:
1393 // ADJCALLSTACKDOWN, SET, SETSW, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ...
1394 O << ", ";
1395 break;
1396 case 1:
1397 // ADJCALLSTACKUP, BA, BINDri, BINDrr, CALL, CALLri, CALLrr, CMASK16, CMA...
1398 return;
1399 break;
1400 case 2:
1401 // BCOND, BPFCC, BPR, CPBCOND, CWBCONDri, CWBCONDrr, CXBCONDri, CXBCONDrr...
1402 O << ' ';
1403 break;
1404 case 3:
1405 // BCONDA, BPFCCA, BPRA, CPBCONDA, FBCONDA
1406 O << ",a ";
1407 break;
1408 case 4:
1409 // BPFCCANT, BPRANT
1410 O << ",a,pn ";
1411 printOperand(MI, opNum: 2, STI, OS&: O);
1412 O << ", ";
1413 printCTILabel(MI, Address, OpNum: 0, STI, O);
1414 return;
1415 break;
1416 case 5:
1417 // BPFCCNT, BPRNT
1418 O << ",pn ";
1419 printOperand(MI, opNum: 2, STI, OS&: O);
1420 O << ", ";
1421 printCTILabel(MI, Address, OpNum: 0, STI, O);
1422 return;
1423 break;
1424 case 6:
1425 // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
1426 O << " %icc, ";
1427 break;
1428 case 7:
1429 // BPICCA
1430 O << ",a %icc, ";
1431 printCTILabel(MI, Address, OpNum: 0, STI, O);
1432 return;
1433 break;
1434 case 8:
1435 // BPICCANT
1436 O << ",a,pn %icc, ";
1437 printCTILabel(MI, Address, OpNum: 0, STI, O);
1438 return;
1439 break;
1440 case 9:
1441 // BPICCNT
1442 O << ",pn %icc, ";
1443 printCTILabel(MI, Address, OpNum: 0, STI, O);
1444 return;
1445 break;
1446 case 10:
1447 // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
1448 O << " %xcc, ";
1449 break;
1450 case 11:
1451 // BPXCCA
1452 O << ",a %xcc, ";
1453 printCTILabel(MI, Address, OpNum: 0, STI, O);
1454 return;
1455 break;
1456 case 12:
1457 // BPXCCANT
1458 O << ",a,pn %xcc, ";
1459 printCTILabel(MI, Address, OpNum: 0, STI, O);
1460 return;
1461 break;
1462 case 13:
1463 // BPXCCNT
1464 O << ",pn %xcc, ";
1465 printCTILabel(MI, Address, OpNum: 0, STI, O);
1466 return;
1467 break;
1468 case 14:
1469 // CASAri, CASXAri, LDAri, LDDAri, LDDFAri, LDFAri, LDQFAri, LDSBAri, LDS...
1470 O << "] %asi, ";
1471 break;
1472 case 15:
1473 // CASArr, CASXArr, LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDS...
1474 O << "] ";
1475 break;
1476 case 16:
1477 // FBCONDA_V9
1478 O << ",a %fcc0, ";
1479 printCTILabel(MI, Address, OpNum: 0, STI, O);
1480 return;
1481 break;
1482 case 17:
1483 // FBCOND_V9, FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1484 O << " %fcc0, ";
1485 break;
1486 case 18:
1487 // GDOP_LDXrr, GDOP_LDrr, LDCri, LDCrr, LDDCri, LDDCrr, LDDFri, LDDFrr, L...
1488 O << "], ";
1489 break;
1490 case 19:
1491 // LDCSRri, LDCSRrr
1492 O << "], %csr";
1493 return;
1494 break;
1495 case 20:
1496 // LDFSRri, LDFSRrr, LDXFSRri, LDXFSRrr
1497 O << "], %fsr";
1498 return;
1499 break;
1500 case 21:
1501 // STAri, STBAri, STDAri, STDFAri, STFAri, STHAri, STQFAri, STXAri
1502 O << "] %asi";
1503 return;
1504 break;
1505 case 22:
1506 // STBri, STBrr, STCSRri, STCSRrr, STCri, STCrr, STDCQri, STDCQrr, STDCri...
1507 O << ']';
1508 return;
1509 break;
1510 }
1511
1512
1513 // Fragment 2 encoded into 3 bits for 8 unique commands.
1514 switch ((Bits >> 21) & 7) {
1515 default: llvm_unreachable("Invalid command number.");
1516 case 0:
1517 // ADJCALLSTACKDOWN, CALLi, FCMPD, FCMPD_V9, FCMPQ, FCMPQ_V9, FCMPS, FCMP...
1518 printOperand(MI, opNum: 1, STI, OS&: O);
1519 break;
1520 case 1:
1521 // SET, SETSW, DES_IIP, DES_IP, FABSD, FABSQ, FABSS, FDTOI, FDTOQ, FDTOS,...
1522 printOperand(MI, opNum: 0, STI, OS&: O);
1523 break;
1524 case 2:
1525 // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1526 printOperand(MI, opNum: 2, STI, OS&: O);
1527 break;
1528 case 3:
1529 // BCOND, BCONDA, BPICC, BPXCC, CPBCOND, CPBCONDA, FBCOND, FBCONDA, FBCON...
1530 printCTILabel(MI, Address, OpNum: 0, STI, O);
1531 return;
1532 break;
1533 case 4:
1534 // CASArr, CASXArr
1535 printASITag(MI, opNum: 4, STI, O);
1536 O << ", ";
1537 printOperand(MI, opNum: 2, STI, OS&: O);
1538 O << ", ";
1539 printOperand(MI, opNum: 0, STI, OS&: O);
1540 return;
1541 break;
1542 case 5:
1543 // LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDSHArr, LDSTUBArr, ...
1544 printASITag(MI, opNum: 3, STI, O);
1545 break;
1546 case 6:
1547 // PREFETCHAi, PREFETCHi, PREFETCHr
1548 printPrefetchTag(MI, opNum: 2, STI, O);
1549 return;
1550 break;
1551 case 7:
1552 // PREFETCHAr
1553 printASITag(MI, opNum: 2, STI, O);
1554 O << ", ";
1555 printPrefetchTag(MI, opNum: 3, STI, O);
1556 return;
1557 break;
1558 }
1559
1560
1561 // Fragment 3 encoded into 3 bits for 6 unique commands.
1562 switch ((Bits >> 24) & 7) {
1563 default: llvm_unreachable("Invalid command number.");
1564 case 0:
1565 // ADJCALLSTACKDOWN, SET, SETSW, CALLi, CALLrii, CALLrri, DES_IIP, DES_IP...
1566 return;
1567 break;
1568 case 1:
1569 // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1570 O << ", ";
1571 break;
1572 case 2:
1573 // PWRPSRri, PWRPSRrr, WRPSRri, WRPSRrr
1574 O << ", %psr";
1575 return;
1576 break;
1577 case 3:
1578 // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr
1579 O << " + ";
1580 printOperand(MI, opNum: 1, STI, OS&: O);
1581 return;
1582 break;
1583 case 4:
1584 // WRTBRri, WRTBRrr
1585 O << ", %tbr";
1586 return;
1587 break;
1588 case 5:
1589 // WRWIMri, WRWIMrr
1590 O << ", %wim";
1591 return;
1592 break;
1593 }
1594
1595
1596 // Fragment 4 encoded into 2 bits for 4 unique commands.
1597 switch ((Bits >> 27) & 3) {
1598 default: llvm_unreachable("Invalid command number.");
1599 case 0:
1600 // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1601 printOperand(MI, opNum: 0, STI, OS&: O);
1602 break;
1603 case 1:
1604 // AES_DROUND01, AES_DROUND01_LAST, AES_DROUND23, AES_DROUND23_LAST, AES_...
1605 printOperand(MI, opNum: 3, STI, OS&: O);
1606 break;
1607 case 2:
1608 // BPFCC, BPFCCA, BPR, BPRA
1609 printCTILabel(MI, Address, OpNum: 0, STI, O);
1610 return;
1611 break;
1612 case 3:
1613 // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1614 printOperand(MI, opNum: 2, STI, OS&: O);
1615 return;
1616 break;
1617 }
1618
1619
1620 // Fragment 5 encoded into 1 bits for 2 unique commands.
1621 if ((Bits >> 29) & 1) {
1622 // AES_DROUND01, AES_DROUND01_LAST, AES_DROUND23, AES_DROUND23_LAST, AES_...
1623 O << ", ";
1624 } else {
1625 // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1626 return;
1627 }
1628
1629
1630 // Fragment 6 encoded into 2 bits for 3 unique commands.
1631 switch ((Bits >> 30) & 3) {
1632 default: llvm_unreachable("Invalid command number.");
1633 case 0:
1634 // AES_DROUND01, AES_DROUND01_LAST, AES_DROUND23, AES_DROUND23_LAST, AES_...
1635 printOperand(MI, opNum: 0, STI, OS&: O);
1636 return;
1637 break;
1638 case 1:
1639 // CWBCONDri, CWBCONDrr, CXBCONDri, CXBCONDrr
1640 printCTILabel(MI, Address, OpNum: 0, STI, O);
1641 return;
1642 break;
1643 case 2:
1644 // TLS_ADDrr
1645 printOperand(MI, opNum: 3, STI, OS&: O);
1646 return;
1647 break;
1648 }
1649
1650}
1651
1652
1653/// getRegisterName - This method is automatically generated by tblgen
1654/// from the register set description. This returns the assembler name
1655/// for the specified register.
1656const char *SparcInstPrinter::
1657getRegisterName(MCRegister Reg, unsigned AltIdx) {
1658 unsigned RegNo = Reg.id();
1659 assert(RegNo && RegNo < 238 && "Invalid register number!");
1660
1661
1662#ifdef __GNUC__
1663#pragma GCC diagnostic push
1664#pragma GCC diagnostic ignored "-Woverlength-strings"
1665#endif
1666 static const char AsmStrsNoRegAltName[] = {
1667 /* 0 */ "c10\000"
1668 /* 4 */ "f10\000"
1669 /* 8 */ "asr10\000"
1670 /* 14 */ "c20\000"
1671 /* 18 */ "f20\000"
1672 /* 22 */ "asr20\000"
1673 /* 28 */ "c30\000"
1674 /* 32 */ "f30\000"
1675 /* 36 */ "asr30\000"
1676 /* 42 */ "f40\000"
1677 /* 46 */ "f50\000"
1678 /* 50 */ "f60\000"
1679 /* 54 */ "fcc0\000"
1680 /* 59 */ "f0\000"
1681 /* 62 */ "g0\000"
1682 /* 65 */ "i0\000"
1683 /* 68 */ "l0\000"
1684 /* 71 */ "o0\000"
1685 /* 74 */ "c11\000"
1686 /* 78 */ "f11\000"
1687 /* 82 */ "asr11\000"
1688 /* 88 */ "c21\000"
1689 /* 92 */ "f21\000"
1690 /* 96 */ "asr21\000"
1691 /* 102 */ "c31\000"
1692 /* 106 */ "f31\000"
1693 /* 110 */ "asr31\000"
1694 /* 116 */ "fcc1\000"
1695 /* 121 */ "f1\000"
1696 /* 124 */ "g1\000"
1697 /* 127 */ "i1\000"
1698 /* 130 */ "l1\000"
1699 /* 133 */ "o1\000"
1700 /* 136 */ "asr1\000"
1701 /* 141 */ "c12\000"
1702 /* 145 */ "f12\000"
1703 /* 149 */ "asr12\000"
1704 /* 155 */ "c22\000"
1705 /* 159 */ "f22\000"
1706 /* 163 */ "asr22\000"
1707 /* 169 */ "f32\000"
1708 /* 173 */ "f42\000"
1709 /* 177 */ "f52\000"
1710 /* 181 */ "f62\000"
1711 /* 185 */ "fcc2\000"
1712 /* 190 */ "f2\000"
1713 /* 193 */ "g2\000"
1714 /* 196 */ "i2\000"
1715 /* 199 */ "l2\000"
1716 /* 202 */ "o2\000"
1717 /* 205 */ "asr2\000"
1718 /* 210 */ "c13\000"
1719 /* 214 */ "f13\000"
1720 /* 218 */ "asr13\000"
1721 /* 224 */ "c23\000"
1722 /* 228 */ "f23\000"
1723 /* 232 */ "asr23\000"
1724 /* 238 */ "fcc3\000"
1725 /* 243 */ "f3\000"
1726 /* 246 */ "g3\000"
1727 /* 249 */ "i3\000"
1728 /* 252 */ "l3\000"
1729 /* 255 */ "o3\000"
1730 /* 258 */ "asr3\000"
1731 /* 263 */ "c14\000"
1732 /* 267 */ "f14\000"
1733 /* 271 */ "asr14\000"
1734 /* 277 */ "c24\000"
1735 /* 281 */ "f24\000"
1736 /* 285 */ "asr24\000"
1737 /* 291 */ "f34\000"
1738 /* 295 */ "f44\000"
1739 /* 299 */ "f54\000"
1740 /* 303 */ "c4\000"
1741 /* 306 */ "f4\000"
1742 /* 309 */ "g4\000"
1743 /* 312 */ "i4\000"
1744 /* 315 */ "l4\000"
1745 /* 318 */ "o4\000"
1746 /* 321 */ "asr4\000"
1747 /* 326 */ "c15\000"
1748 /* 330 */ "f15\000"
1749 /* 334 */ "asr15\000"
1750 /* 340 */ "c25\000"
1751 /* 344 */ "f25\000"
1752 /* 348 */ "asr25\000"
1753 /* 354 */ "c5\000"
1754 /* 357 */ "f5\000"
1755 /* 360 */ "g5\000"
1756 /* 363 */ "i5\000"
1757 /* 366 */ "l5\000"
1758 /* 369 */ "o5\000"
1759 /* 372 */ "asr5\000"
1760 /* 377 */ "c16\000"
1761 /* 381 */ "f16\000"
1762 /* 385 */ "asr16\000"
1763 /* 391 */ "c26\000"
1764 /* 395 */ "f26\000"
1765 /* 399 */ "asr26\000"
1766 /* 405 */ "f36\000"
1767 /* 409 */ "f46\000"
1768 /* 413 */ "f56\000"
1769 /* 417 */ "c6\000"
1770 /* 420 */ "f6\000"
1771 /* 423 */ "g6\000"
1772 /* 426 */ "i6\000"
1773 /* 429 */ "l6\000"
1774 /* 432 */ "o6\000"
1775 /* 435 */ "asr6\000"
1776 /* 440 */ "c17\000"
1777 /* 444 */ "f17\000"
1778 /* 448 */ "asr17\000"
1779 /* 454 */ "c27\000"
1780 /* 458 */ "f27\000"
1781 /* 462 */ "asr27\000"
1782 /* 468 */ "c7\000"
1783 /* 471 */ "f7\000"
1784 /* 474 */ "g7\000"
1785 /* 477 */ "i7\000"
1786 /* 480 */ "l7\000"
1787 /* 483 */ "o7\000"
1788 /* 486 */ "asr7\000"
1789 /* 491 */ "c18\000"
1790 /* 495 */ "f18\000"
1791 /* 499 */ "asr18\000"
1792 /* 505 */ "c28\000"
1793 /* 509 */ "f28\000"
1794 /* 513 */ "asr28\000"
1795 /* 519 */ "f38\000"
1796 /* 523 */ "f48\000"
1797 /* 527 */ "f58\000"
1798 /* 531 */ "c8\000"
1799 /* 534 */ "f8\000"
1800 /* 537 */ "asr8\000"
1801 /* 542 */ "c19\000"
1802 /* 546 */ "f19\000"
1803 /* 550 */ "asr19\000"
1804 /* 556 */ "c29\000"
1805 /* 560 */ "f29\000"
1806 /* 564 */ "asr29\000"
1807 /* 570 */ "c9\000"
1808 /* 573 */ "f9\000"
1809 /* 576 */ "asr9\000"
1810 /* 581 */ "tba\000"
1811 /* 585 */ "icc\000"
1812 /* 589 */ "tnpc\000"
1813 /* 594 */ "tpc\000"
1814 /* 598 */ "canrestore\000"
1815 /* 609 */ "pstate\000"
1816 /* 616 */ "tstate\000"
1817 /* 623 */ "wstate\000"
1818 /* 630 */ "cansave\000"
1819 /* 638 */ "tick\000"
1820 /* 643 */ "gl\000"
1821 /* 646 */ "pil\000"
1822 /* 650 */ "tl\000"
1823 /* 653 */ "wim\000"
1824 /* 657 */ "cleanwin\000"
1825 /* 666 */ "otherwin\000"
1826 /* 675 */ "fp\000"
1827 /* 678 */ "sp\000"
1828 /* 681 */ "cwp\000"
1829 /* 685 */ "cq\000"
1830 /* 688 */ "fq\000"
1831 /* 691 */ "tbr\000"
1832 /* 695 */ "ver\000"
1833 /* 699 */ "csr\000"
1834 /* 703 */ "fsr\000"
1835 /* 707 */ "psr\000"
1836 /* 711 */ "tt\000"
1837 /* 714 */ "y\000"
1838};
1839#ifdef __GNUC__
1840#pragma GCC diagnostic pop
1841#endif
1842
1843 static const uint16_t RegAsmOffsetNoRegAltName[] = {
1844 598, 630, 657, 685, 699, 681, 688, 703, 643, 585, 666, 646, 707, 609,
1845 581, 691, 638, 650, 589, 594, 616, 711, 695, 653, 623, 714, 136, 205,
1846 258, 321, 372, 435, 486, 537, 576, 8, 82, 149, 218, 271, 334, 385,
1847 448, 499, 550, 22, 96, 163, 232, 285, 348, 399, 462, 513, 564, 36,
1848 110, 56, 118, 187, 240, 303, 354, 417, 468, 531, 570, 0, 74, 141,
1849 210, 263, 326, 377, 440, 491, 542, 14, 88, 155, 224, 277, 340, 391,
1850 454, 505, 556, 28, 102, 59, 190, 306, 420, 534, 4, 145, 267, 381,
1851 495, 18, 159, 281, 395, 509, 32, 169, 291, 405, 519, 42, 173, 295,
1852 409, 523, 46, 177, 299, 413, 527, 50, 181, 59, 121, 190, 243, 306,
1853 357, 420, 471, 534, 573, 4, 78, 145, 214, 267, 330, 381, 444, 495,
1854 546, 18, 92, 159, 228, 281, 344, 395, 458, 509, 560, 32, 106, 54,
1855 116, 185, 238, 62, 124, 193, 246, 309, 360, 423, 474, 65, 127, 196,
1856 249, 312, 363, 675, 477, 68, 130, 199, 252, 315, 366, 429, 480, 71,
1857 133, 202, 255, 318, 369, 678, 483, 59, 306, 534, 145, 381, 18, 281,
1858 509, 169, 405, 42, 295, 523, 177, 413, 50, 56, 187, 303, 417, 531,
1859 0, 141, 263, 377, 491, 14, 155, 277, 391, 505, 28, 62, 193, 309,
1860 423, 65, 196, 312, 426, 68, 199, 315, 429, 71, 202, 318, 432,
1861 };
1862
1863
1864#ifdef __GNUC__
1865#pragma GCC diagnostic push
1866#pragma GCC diagnostic ignored "-Woverlength-strings"
1867#endif
1868 static const char AsmStrsRegNamesStateReg[] = {
1869 /* 0 */ "pc\000"
1870 /* 3 */ "asi\000"
1871 /* 7 */ "tick\000"
1872 /* 12 */ "ccr\000"
1873 /* 16 */ "fprs\000"
1874};
1875#ifdef __GNUC__
1876#pragma GCC diagnostic pop
1877#endif
1878
1879 static const uint8_t RegAsmOffsetRegNamesStateReg[] = {
1880 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1881 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 12,
1882 3, 7, 0, 16, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1883 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1884 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1885 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1886 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1887 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1888 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1889 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1890 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1891 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1892 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1893 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1894 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1895 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1896 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1897 };
1898
1899 switch(AltIdx) {
1900 default: llvm_unreachable("Invalid register alt name index!");
1901 case SP::NoRegAltName:
1902 assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) &&
1903 "Invalid alt name index for register!");
1904 return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
1905 case SP::RegNamesStateReg:
1906 if (!*(AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1]))
1907 return getRegisterName(Reg: RegNo, AltIdx: SP::NoRegAltName);
1908 return AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1];
1909 }
1910}
1911
1912#ifdef PRINT_ALIAS_INSTR
1913#undef PRINT_ALIAS_INSTR
1914
1915bool SparcInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS) {
1916 static const PatternsForOpcode OpToPatterns[] = {
1917 {.Opcode: SP::BCOND, .PatternStart: 0, .NumPatterns: 16 },
1918 {.Opcode: SP::BCONDA, .PatternStart: 16, .NumPatterns: 16 },
1919 {.Opcode: SP::BPFCCANT, .PatternStart: 32, .NumPatterns: 16 },
1920 {.Opcode: SP::BPFCCNT, .PatternStart: 48, .NumPatterns: 16 },
1921 {.Opcode: SP::BPICCANT, .PatternStart: 64, .NumPatterns: 32 },
1922 {.Opcode: SP::BPICCNT, .PatternStart: 96, .NumPatterns: 32 },
1923 {.Opcode: SP::BPRANT, .PatternStart: 128, .NumPatterns: 4 },
1924 {.Opcode: SP::BPRNT, .PatternStart: 132, .NumPatterns: 4 },
1925 {.Opcode: SP::CASArr, .PatternStart: 136, .NumPatterns: 2 },
1926 {.Opcode: SP::CASXArr, .PatternStart: 138, .NumPatterns: 2 },
1927 {.Opcode: SP::CWBCONDri, .PatternStart: 140, .NumPatterns: 14 },
1928 {.Opcode: SP::CWBCONDrr, .PatternStart: 154, .NumPatterns: 14 },
1929 {.Opcode: SP::CXBCONDri, .PatternStart: 168, .NumPatterns: 14 },
1930 {.Opcode: SP::CXBCONDrr, .PatternStart: 182, .NumPatterns: 14 },
1931 {.Opcode: SP::FMOVD_ICC, .PatternStart: 196, .NumPatterns: 32 },
1932 {.Opcode: SP::FMOVQ_ICC, .PatternStart: 228, .NumPatterns: 32 },
1933 {.Opcode: SP::FMOVRD, .PatternStart: 260, .NumPatterns: 4 },
1934 {.Opcode: SP::FMOVRQ, .PatternStart: 264, .NumPatterns: 4 },
1935 {.Opcode: SP::FMOVRS, .PatternStart: 268, .NumPatterns: 4 },
1936 {.Opcode: SP::FMOVS_ICC, .PatternStart: 272, .NumPatterns: 32 },
1937 {.Opcode: SP::MOVICCri, .PatternStart: 304, .NumPatterns: 32 },
1938 {.Opcode: SP::MOVICCrr, .PatternStart: 336, .NumPatterns: 32 },
1939 {.Opcode: SP::MOVRri, .PatternStart: 368, .NumPatterns: 4 },
1940 {.Opcode: SP::MOVRrr, .PatternStart: 372, .NumPatterns: 4 },
1941 {.Opcode: SP::ORCCrr, .PatternStart: 376, .NumPatterns: 1 },
1942 {.Opcode: SP::ORri, .PatternStart: 377, .NumPatterns: 1 },
1943 {.Opcode: SP::ORrr, .PatternStart: 378, .NumPatterns: 1 },
1944 {.Opcode: SP::RESTORErr, .PatternStart: 379, .NumPatterns: 1 },
1945 {.Opcode: SP::RET, .PatternStart: 380, .NumPatterns: 1 },
1946 {.Opcode: SP::RETL, .PatternStart: 381, .NumPatterns: 1 },
1947 {.Opcode: SP::SAVErr, .PatternStart: 382, .NumPatterns: 1 },
1948 {.Opcode: SP::SUBCCri, .PatternStart: 383, .NumPatterns: 1 },
1949 {.Opcode: SP::SUBCCrr, .PatternStart: 384, .NumPatterns: 1 },
1950 {.Opcode: SP::TICCri, .PatternStart: 385, .NumPatterns: 64 },
1951 {.Opcode: SP::TICCrr, .PatternStart: 449, .NumPatterns: 64 },
1952 {.Opcode: SP::TRAPri, .PatternStart: 513, .NumPatterns: 32 },
1953 {.Opcode: SP::TRAPrr, .PatternStart: 545, .NumPatterns: 32 },
1954 {.Opcode: SP::TXCCri, .PatternStart: 577, .NumPatterns: 64 },
1955 {.Opcode: SP::TXCCrr, .PatternStart: 641, .NumPatterns: 64 },
1956 {.Opcode: SP::V9FCMPD, .PatternStart: 705, .NumPatterns: 1 },
1957 {.Opcode: SP::V9FCMPED, .PatternStart: 706, .NumPatterns: 1 },
1958 {.Opcode: SP::V9FCMPEQ, .PatternStart: 707, .NumPatterns: 1 },
1959 {.Opcode: SP::V9FCMPES, .PatternStart: 708, .NumPatterns: 1 },
1960 {.Opcode: SP::V9FCMPQ, .PatternStart: 709, .NumPatterns: 1 },
1961 {.Opcode: SP::V9FCMPS, .PatternStart: 710, .NumPatterns: 1 },
1962 {.Opcode: SP::V9FMOVD_FCC, .PatternStart: 711, .NumPatterns: 16 },
1963 {.Opcode: SP::V9FMOVQ_FCC, .PatternStart: 727, .NumPatterns: 16 },
1964 {.Opcode: SP::V9FMOVS_FCC, .PatternStart: 743, .NumPatterns: 16 },
1965 {.Opcode: SP::V9MOVFCCri, .PatternStart: 759, .NumPatterns: 16 },
1966 {.Opcode: SP::V9MOVFCCrr, .PatternStart: 775, .NumPatterns: 16 },
1967 {.Opcode: SP::WRASRri, .PatternStart: 791, .NumPatterns: 1 },
1968 {.Opcode: SP::WRASRrr, .PatternStart: 792, .NumPatterns: 1 },
1969 };
1970
1971 static const AliasPattern Patterns[] = {
1972 // SP::BCOND - 0
1973 {.AsmStrOffset: 0, .AliasCondStart: 0, .NumOperands: 2, .NumConds: 2 },
1974 {.AsmStrOffset: 8, .AliasCondStart: 2, .NumOperands: 2, .NumConds: 2 },
1975 {.AsmStrOffset: 16, .AliasCondStart: 4, .NumOperands: 2, .NumConds: 2 },
1976 {.AsmStrOffset: 25, .AliasCondStart: 6, .NumOperands: 2, .NumConds: 2 },
1977 {.AsmStrOffset: 33, .AliasCondStart: 8, .NumOperands: 2, .NumConds: 2 },
1978 {.AsmStrOffset: 41, .AliasCondStart: 10, .NumOperands: 2, .NumConds: 2 },
1979 {.AsmStrOffset: 50, .AliasCondStart: 12, .NumOperands: 2, .NumConds: 2 },
1980 {.AsmStrOffset: 59, .AliasCondStart: 14, .NumOperands: 2, .NumConds: 2 },
1981 {.AsmStrOffset: 67, .AliasCondStart: 16, .NumOperands: 2, .NumConds: 2 },
1982 {.AsmStrOffset: 76, .AliasCondStart: 18, .NumOperands: 2, .NumConds: 2 },
1983 {.AsmStrOffset: 86, .AliasCondStart: 20, .NumOperands: 2, .NumConds: 2 },
1984 {.AsmStrOffset: 95, .AliasCondStart: 22, .NumOperands: 2, .NumConds: 2 },
1985 {.AsmStrOffset: 104, .AliasCondStart: 24, .NumOperands: 2, .NumConds: 2 },
1986 {.AsmStrOffset: 114, .AliasCondStart: 26, .NumOperands: 2, .NumConds: 2 },
1987 {.AsmStrOffset: 124, .AliasCondStart: 28, .NumOperands: 2, .NumConds: 2 },
1988 {.AsmStrOffset: 133, .AliasCondStart: 30, .NumOperands: 2, .NumConds: 2 },
1989 // SP::BCONDA - 16
1990 {.AsmStrOffset: 142, .AliasCondStart: 32, .NumOperands: 2, .NumConds: 2 },
1991 {.AsmStrOffset: 152, .AliasCondStart: 34, .NumOperands: 2, .NumConds: 2 },
1992 {.AsmStrOffset: 162, .AliasCondStart: 36, .NumOperands: 2, .NumConds: 2 },
1993 {.AsmStrOffset: 173, .AliasCondStart: 38, .NumOperands: 2, .NumConds: 2 },
1994 {.AsmStrOffset: 183, .AliasCondStart: 40, .NumOperands: 2, .NumConds: 2 },
1995 {.AsmStrOffset: 193, .AliasCondStart: 42, .NumOperands: 2, .NumConds: 2 },
1996 {.AsmStrOffset: 204, .AliasCondStart: 44, .NumOperands: 2, .NumConds: 2 },
1997 {.AsmStrOffset: 215, .AliasCondStart: 46, .NumOperands: 2, .NumConds: 2 },
1998 {.AsmStrOffset: 225, .AliasCondStart: 48, .NumOperands: 2, .NumConds: 2 },
1999 {.AsmStrOffset: 236, .AliasCondStart: 50, .NumOperands: 2, .NumConds: 2 },
2000 {.AsmStrOffset: 248, .AliasCondStart: 52, .NumOperands: 2, .NumConds: 2 },
2001 {.AsmStrOffset: 259, .AliasCondStart: 54, .NumOperands: 2, .NumConds: 2 },
2002 {.AsmStrOffset: 270, .AliasCondStart: 56, .NumOperands: 2, .NumConds: 2 },
2003 {.AsmStrOffset: 282, .AliasCondStart: 58, .NumOperands: 2, .NumConds: 2 },
2004 {.AsmStrOffset: 294, .AliasCondStart: 60, .NumOperands: 2, .NumConds: 2 },
2005 {.AsmStrOffset: 305, .AliasCondStart: 62, .NumOperands: 2, .NumConds: 2 },
2006 // SP::BPFCCANT - 32
2007 {.AsmStrOffset: 316, .AliasCondStart: 64, .NumOperands: 3, .NumConds: 4 },
2008 {.AsmStrOffset: 334, .AliasCondStart: 68, .NumOperands: 3, .NumConds: 4 },
2009 {.AsmStrOffset: 352, .AliasCondStart: 72, .NumOperands: 3, .NumConds: 4 },
2010 {.AsmStrOffset: 370, .AliasCondStart: 76, .NumOperands: 3, .NumConds: 4 },
2011 {.AsmStrOffset: 388, .AliasCondStart: 80, .NumOperands: 3, .NumConds: 4 },
2012 {.AsmStrOffset: 407, .AliasCondStart: 84, .NumOperands: 3, .NumConds: 4 },
2013 {.AsmStrOffset: 425, .AliasCondStart: 88, .NumOperands: 3, .NumConds: 4 },
2014 {.AsmStrOffset: 444, .AliasCondStart: 92, .NumOperands: 3, .NumConds: 4 },
2015 {.AsmStrOffset: 463, .AliasCondStart: 96, .NumOperands: 3, .NumConds: 4 },
2016 {.AsmStrOffset: 482, .AliasCondStart: 100, .NumOperands: 3, .NumConds: 4 },
2017 {.AsmStrOffset: 500, .AliasCondStart: 104, .NumOperands: 3, .NumConds: 4 },
2018 {.AsmStrOffset: 519, .AliasCondStart: 108, .NumOperands: 3, .NumConds: 4 },
2019 {.AsmStrOffset: 538, .AliasCondStart: 112, .NumOperands: 3, .NumConds: 4 },
2020 {.AsmStrOffset: 558, .AliasCondStart: 116, .NumOperands: 3, .NumConds: 4 },
2021 {.AsmStrOffset: 577, .AliasCondStart: 120, .NumOperands: 3, .NumConds: 4 },
2022 {.AsmStrOffset: 597, .AliasCondStart: 124, .NumOperands: 3, .NumConds: 4 },
2023 // SP::BPFCCNT - 48
2024 {.AsmStrOffset: 615, .AliasCondStart: 128, .NumOperands: 3, .NumConds: 4 },
2025 {.AsmStrOffset: 631, .AliasCondStart: 132, .NumOperands: 3, .NumConds: 4 },
2026 {.AsmStrOffset: 647, .AliasCondStart: 136, .NumOperands: 3, .NumConds: 4 },
2027 {.AsmStrOffset: 663, .AliasCondStart: 140, .NumOperands: 3, .NumConds: 4 },
2028 {.AsmStrOffset: 679, .AliasCondStart: 144, .NumOperands: 3, .NumConds: 4 },
2029 {.AsmStrOffset: 696, .AliasCondStart: 148, .NumOperands: 3, .NumConds: 4 },
2030 {.AsmStrOffset: 712, .AliasCondStart: 152, .NumOperands: 3, .NumConds: 4 },
2031 {.AsmStrOffset: 729, .AliasCondStart: 156, .NumOperands: 3, .NumConds: 4 },
2032 {.AsmStrOffset: 746, .AliasCondStart: 160, .NumOperands: 3, .NumConds: 4 },
2033 {.AsmStrOffset: 763, .AliasCondStart: 164, .NumOperands: 3, .NumConds: 4 },
2034 {.AsmStrOffset: 779, .AliasCondStart: 168, .NumOperands: 3, .NumConds: 4 },
2035 {.AsmStrOffset: 796, .AliasCondStart: 172, .NumOperands: 3, .NumConds: 4 },
2036 {.AsmStrOffset: 813, .AliasCondStart: 176, .NumOperands: 3, .NumConds: 4 },
2037 {.AsmStrOffset: 831, .AliasCondStart: 180, .NumOperands: 3, .NumConds: 4 },
2038 {.AsmStrOffset: 848, .AliasCondStart: 184, .NumOperands: 3, .NumConds: 4 },
2039 {.AsmStrOffset: 866, .AliasCondStart: 188, .NumOperands: 3, .NumConds: 4 },
2040 // SP::BPICCANT - 64
2041 {.AsmStrOffset: 882, .AliasCondStart: 192, .NumOperands: 2, .NumConds: 3 },
2042 {.AsmStrOffset: 901, .AliasCondStart: 195, .NumOperands: 2, .NumConds: 4 },
2043 {.AsmStrOffset: 920, .AliasCondStart: 199, .NumOperands: 2, .NumConds: 3 },
2044 {.AsmStrOffset: 939, .AliasCondStart: 202, .NumOperands: 2, .NumConds: 4 },
2045 {.AsmStrOffset: 958, .AliasCondStart: 206, .NumOperands: 2, .NumConds: 3 },
2046 {.AsmStrOffset: 978, .AliasCondStart: 209, .NumOperands: 2, .NumConds: 4 },
2047 {.AsmStrOffset: 998, .AliasCondStart: 213, .NumOperands: 2, .NumConds: 3 },
2048 {.AsmStrOffset: 1017, .AliasCondStart: 216, .NumOperands: 2, .NumConds: 4 },
2049 {.AsmStrOffset: 1036, .AliasCondStart: 220, .NumOperands: 2, .NumConds: 3 },
2050 {.AsmStrOffset: 1055, .AliasCondStart: 223, .NumOperands: 2, .NumConds: 4 },
2051 {.AsmStrOffset: 1074, .AliasCondStart: 227, .NumOperands: 2, .NumConds: 3 },
2052 {.AsmStrOffset: 1094, .AliasCondStart: 230, .NumOperands: 2, .NumConds: 4 },
2053 {.AsmStrOffset: 1114, .AliasCondStart: 234, .NumOperands: 2, .NumConds: 3 },
2054 {.AsmStrOffset: 1134, .AliasCondStart: 237, .NumOperands: 2, .NumConds: 4 },
2055 {.AsmStrOffset: 1154, .AliasCondStart: 241, .NumOperands: 2, .NumConds: 3 },
2056 {.AsmStrOffset: 1173, .AliasCondStart: 244, .NumOperands: 2, .NumConds: 4 },
2057 {.AsmStrOffset: 1192, .AliasCondStart: 248, .NumOperands: 2, .NumConds: 3 },
2058 {.AsmStrOffset: 1212, .AliasCondStart: 251, .NumOperands: 2, .NumConds: 4 },
2059 {.AsmStrOffset: 1232, .AliasCondStart: 255, .NumOperands: 2, .NumConds: 3 },
2060 {.AsmStrOffset: 1253, .AliasCondStart: 258, .NumOperands: 2, .NumConds: 4 },
2061 {.AsmStrOffset: 1274, .AliasCondStart: 262, .NumOperands: 2, .NumConds: 3 },
2062 {.AsmStrOffset: 1294, .AliasCondStart: 265, .NumOperands: 2, .NumConds: 4 },
2063 {.AsmStrOffset: 1314, .AliasCondStart: 269, .NumOperands: 2, .NumConds: 3 },
2064 {.AsmStrOffset: 1334, .AliasCondStart: 272, .NumOperands: 2, .NumConds: 4 },
2065 {.AsmStrOffset: 1354, .AliasCondStart: 276, .NumOperands: 2, .NumConds: 3 },
2066 {.AsmStrOffset: 1375, .AliasCondStart: 279, .NumOperands: 2, .NumConds: 4 },
2067 {.AsmStrOffset: 1396, .AliasCondStart: 283, .NumOperands: 2, .NumConds: 3 },
2068 {.AsmStrOffset: 1417, .AliasCondStart: 286, .NumOperands: 2, .NumConds: 4 },
2069 {.AsmStrOffset: 1438, .AliasCondStart: 290, .NumOperands: 2, .NumConds: 3 },
2070 {.AsmStrOffset: 1458, .AliasCondStart: 293, .NumOperands: 2, .NumConds: 4 },
2071 {.AsmStrOffset: 1478, .AliasCondStart: 297, .NumOperands: 2, .NumConds: 3 },
2072 {.AsmStrOffset: 1498, .AliasCondStart: 300, .NumOperands: 2, .NumConds: 4 },
2073 // SP::BPICCNT - 96
2074 {.AsmStrOffset: 1518, .AliasCondStart: 304, .NumOperands: 2, .NumConds: 3 },
2075 {.AsmStrOffset: 1535, .AliasCondStart: 307, .NumOperands: 2, .NumConds: 4 },
2076 {.AsmStrOffset: 1552, .AliasCondStart: 311, .NumOperands: 2, .NumConds: 3 },
2077 {.AsmStrOffset: 1569, .AliasCondStart: 314, .NumOperands: 2, .NumConds: 4 },
2078 {.AsmStrOffset: 1586, .AliasCondStart: 318, .NumOperands: 2, .NumConds: 3 },
2079 {.AsmStrOffset: 1604, .AliasCondStart: 321, .NumOperands: 2, .NumConds: 4 },
2080 {.AsmStrOffset: 1622, .AliasCondStart: 325, .NumOperands: 2, .NumConds: 3 },
2081 {.AsmStrOffset: 1639, .AliasCondStart: 328, .NumOperands: 2, .NumConds: 4 },
2082 {.AsmStrOffset: 1656, .AliasCondStart: 332, .NumOperands: 2, .NumConds: 3 },
2083 {.AsmStrOffset: 1673, .AliasCondStart: 335, .NumOperands: 2, .NumConds: 4 },
2084 {.AsmStrOffset: 1690, .AliasCondStart: 339, .NumOperands: 2, .NumConds: 3 },
2085 {.AsmStrOffset: 1708, .AliasCondStart: 342, .NumOperands: 2, .NumConds: 4 },
2086 {.AsmStrOffset: 1726, .AliasCondStart: 346, .NumOperands: 2, .NumConds: 3 },
2087 {.AsmStrOffset: 1744, .AliasCondStart: 349, .NumOperands: 2, .NumConds: 4 },
2088 {.AsmStrOffset: 1762, .AliasCondStart: 353, .NumOperands: 2, .NumConds: 3 },
2089 {.AsmStrOffset: 1779, .AliasCondStart: 356, .NumOperands: 2, .NumConds: 4 },
2090 {.AsmStrOffset: 1796, .AliasCondStart: 360, .NumOperands: 2, .NumConds: 3 },
2091 {.AsmStrOffset: 1814, .AliasCondStart: 363, .NumOperands: 2, .NumConds: 4 },
2092 {.AsmStrOffset: 1832, .AliasCondStart: 367, .NumOperands: 2, .NumConds: 3 },
2093 {.AsmStrOffset: 1851, .AliasCondStart: 370, .NumOperands: 2, .NumConds: 4 },
2094 {.AsmStrOffset: 1870, .AliasCondStart: 374, .NumOperands: 2, .NumConds: 3 },
2095 {.AsmStrOffset: 1888, .AliasCondStart: 377, .NumOperands: 2, .NumConds: 4 },
2096 {.AsmStrOffset: 1906, .AliasCondStart: 381, .NumOperands: 2, .NumConds: 3 },
2097 {.AsmStrOffset: 1924, .AliasCondStart: 384, .NumOperands: 2, .NumConds: 4 },
2098 {.AsmStrOffset: 1942, .AliasCondStart: 388, .NumOperands: 2, .NumConds: 3 },
2099 {.AsmStrOffset: 1961, .AliasCondStart: 391, .NumOperands: 2, .NumConds: 4 },
2100 {.AsmStrOffset: 1980, .AliasCondStart: 395, .NumOperands: 2, .NumConds: 3 },
2101 {.AsmStrOffset: 1999, .AliasCondStart: 398, .NumOperands: 2, .NumConds: 4 },
2102 {.AsmStrOffset: 2018, .AliasCondStart: 402, .NumOperands: 2, .NumConds: 3 },
2103 {.AsmStrOffset: 2036, .AliasCondStart: 405, .NumOperands: 2, .NumConds: 4 },
2104 {.AsmStrOffset: 2054, .AliasCondStart: 409, .NumOperands: 2, .NumConds: 3 },
2105 {.AsmStrOffset: 2072, .AliasCondStart: 412, .NumOperands: 2, .NumConds: 4 },
2106 // SP::BPRANT - 128
2107 {.AsmStrOffset: 2090, .AliasCondStart: 416, .NumOperands: 3, .NumConds: 4 },
2108 {.AsmStrOffset: 2110, .AliasCondStart: 420, .NumOperands: 3, .NumConds: 4 },
2109 {.AsmStrOffset: 2129, .AliasCondStart: 424, .NumOperands: 3, .NumConds: 4 },
2110 {.AsmStrOffset: 2148, .AliasCondStart: 428, .NumOperands: 3, .NumConds: 4 },
2111 // SP::BPRNT - 132
2112 {.AsmStrOffset: 2168, .AliasCondStart: 432, .NumOperands: 3, .NumConds: 4 },
2113 {.AsmStrOffset: 2186, .AliasCondStart: 436, .NumOperands: 3, .NumConds: 4 },
2114 {.AsmStrOffset: 2203, .AliasCondStart: 440, .NumOperands: 3, .NumConds: 4 },
2115 {.AsmStrOffset: 2220, .AliasCondStart: 444, .NumOperands: 3, .NumConds: 4 },
2116 // SP::CASArr - 136
2117 {.AsmStrOffset: 2238, .AliasCondStart: 448, .NumOperands: 5, .NumConds: 6 },
2118 {.AsmStrOffset: 2255, .AliasCondStart: 454, .NumOperands: 5, .NumConds: 6 },
2119 // SP::CASXArr - 138
2120 {.AsmStrOffset: 2273, .AliasCondStart: 460, .NumOperands: 5, .NumConds: 6 },
2121 {.AsmStrOffset: 2291, .AliasCondStart: 466, .NumOperands: 5, .NumConds: 6 },
2122 // SP::CWBCONDri - 140
2123 {.AsmStrOffset: 2310, .AliasCondStart: 472, .NumOperands: 4, .NumConds: 4 },
2124 {.AsmStrOffset: 2329, .AliasCondStart: 476, .NumOperands: 4, .NumConds: 4 },
2125 {.AsmStrOffset: 2347, .AliasCondStart: 480, .NumOperands: 4, .NumConds: 4 },
2126 {.AsmStrOffset: 2365, .AliasCondStart: 484, .NumOperands: 4, .NumConds: 4 },
2127 {.AsmStrOffset: 2384, .AliasCondStart: 488, .NumOperands: 4, .NumConds: 4 },
2128 {.AsmStrOffset: 2403, .AliasCondStart: 492, .NumOperands: 4, .NumConds: 4 },
2129 {.AsmStrOffset: 2421, .AliasCondStart: 496, .NumOperands: 4, .NumConds: 4 },
2130 {.AsmStrOffset: 2440, .AliasCondStart: 500, .NumOperands: 4, .NumConds: 4 },
2131 {.AsmStrOffset: 2460, .AliasCondStart: 504, .NumOperands: 4, .NumConds: 4 },
2132 {.AsmStrOffset: 2479, .AliasCondStart: 508, .NumOperands: 4, .NumConds: 4 },
2133 {.AsmStrOffset: 2498, .AliasCondStart: 512, .NumOperands: 4, .NumConds: 4 },
2134 {.AsmStrOffset: 2518, .AliasCondStart: 516, .NumOperands: 4, .NumConds: 4 },
2135 {.AsmStrOffset: 2538, .AliasCondStart: 520, .NumOperands: 4, .NumConds: 4 },
2136 {.AsmStrOffset: 2557, .AliasCondStart: 524, .NumOperands: 4, .NumConds: 4 },
2137 // SP::CWBCONDrr - 154
2138 {.AsmStrOffset: 2310, .AliasCondStart: 528, .NumOperands: 4, .NumConds: 5 },
2139 {.AsmStrOffset: 2329, .AliasCondStart: 533, .NumOperands: 4, .NumConds: 5 },
2140 {.AsmStrOffset: 2347, .AliasCondStart: 538, .NumOperands: 4, .NumConds: 5 },
2141 {.AsmStrOffset: 2365, .AliasCondStart: 543, .NumOperands: 4, .NumConds: 5 },
2142 {.AsmStrOffset: 2384, .AliasCondStart: 548, .NumOperands: 4, .NumConds: 5 },
2143 {.AsmStrOffset: 2403, .AliasCondStart: 553, .NumOperands: 4, .NumConds: 5 },
2144 {.AsmStrOffset: 2421, .AliasCondStart: 558, .NumOperands: 4, .NumConds: 5 },
2145 {.AsmStrOffset: 2440, .AliasCondStart: 563, .NumOperands: 4, .NumConds: 5 },
2146 {.AsmStrOffset: 2460, .AliasCondStart: 568, .NumOperands: 4, .NumConds: 5 },
2147 {.AsmStrOffset: 2479, .AliasCondStart: 573, .NumOperands: 4, .NumConds: 5 },
2148 {.AsmStrOffset: 2498, .AliasCondStart: 578, .NumOperands: 4, .NumConds: 5 },
2149 {.AsmStrOffset: 2518, .AliasCondStart: 583, .NumOperands: 4, .NumConds: 5 },
2150 {.AsmStrOffset: 2538, .AliasCondStart: 588, .NumOperands: 4, .NumConds: 5 },
2151 {.AsmStrOffset: 2557, .AliasCondStart: 593, .NumOperands: 4, .NumConds: 5 },
2152 // SP::CXBCONDri - 168
2153 {.AsmStrOffset: 2576, .AliasCondStart: 598, .NumOperands: 4, .NumConds: 4 },
2154 {.AsmStrOffset: 2595, .AliasCondStart: 602, .NumOperands: 4, .NumConds: 4 },
2155 {.AsmStrOffset: 2613, .AliasCondStart: 606, .NumOperands: 4, .NumConds: 4 },
2156 {.AsmStrOffset: 2631, .AliasCondStart: 610, .NumOperands: 4, .NumConds: 4 },
2157 {.AsmStrOffset: 2650, .AliasCondStart: 614, .NumOperands: 4, .NumConds: 4 },
2158 {.AsmStrOffset: 2669, .AliasCondStart: 618, .NumOperands: 4, .NumConds: 4 },
2159 {.AsmStrOffset: 2687, .AliasCondStart: 622, .NumOperands: 4, .NumConds: 4 },
2160 {.AsmStrOffset: 2706, .AliasCondStart: 626, .NumOperands: 4, .NumConds: 4 },
2161 {.AsmStrOffset: 2726, .AliasCondStart: 630, .NumOperands: 4, .NumConds: 4 },
2162 {.AsmStrOffset: 2745, .AliasCondStart: 634, .NumOperands: 4, .NumConds: 4 },
2163 {.AsmStrOffset: 2764, .AliasCondStart: 638, .NumOperands: 4, .NumConds: 4 },
2164 {.AsmStrOffset: 2784, .AliasCondStart: 642, .NumOperands: 4, .NumConds: 4 },
2165 {.AsmStrOffset: 2804, .AliasCondStart: 646, .NumOperands: 4, .NumConds: 4 },
2166 {.AsmStrOffset: 2823, .AliasCondStart: 650, .NumOperands: 4, .NumConds: 4 },
2167 // SP::CXBCONDrr - 182
2168 {.AsmStrOffset: 2576, .AliasCondStart: 654, .NumOperands: 4, .NumConds: 5 },
2169 {.AsmStrOffset: 2595, .AliasCondStart: 659, .NumOperands: 4, .NumConds: 5 },
2170 {.AsmStrOffset: 2613, .AliasCondStart: 664, .NumOperands: 4, .NumConds: 5 },
2171 {.AsmStrOffset: 2631, .AliasCondStart: 669, .NumOperands: 4, .NumConds: 5 },
2172 {.AsmStrOffset: 2650, .AliasCondStart: 674, .NumOperands: 4, .NumConds: 5 },
2173 {.AsmStrOffset: 2669, .AliasCondStart: 679, .NumOperands: 4, .NumConds: 5 },
2174 {.AsmStrOffset: 2687, .AliasCondStart: 684, .NumOperands: 4, .NumConds: 5 },
2175 {.AsmStrOffset: 2706, .AliasCondStart: 689, .NumOperands: 4, .NumConds: 5 },
2176 {.AsmStrOffset: 2726, .AliasCondStart: 694, .NumOperands: 4, .NumConds: 5 },
2177 {.AsmStrOffset: 2745, .AliasCondStart: 699, .NumOperands: 4, .NumConds: 5 },
2178 {.AsmStrOffset: 2764, .AliasCondStart: 704, .NumOperands: 4, .NumConds: 5 },
2179 {.AsmStrOffset: 2784, .AliasCondStart: 709, .NumOperands: 4, .NumConds: 5 },
2180 {.AsmStrOffset: 2804, .AliasCondStart: 714, .NumOperands: 4, .NumConds: 5 },
2181 {.AsmStrOffset: 2823, .AliasCondStart: 719, .NumOperands: 4, .NumConds: 5 },
2182 // SP::FMOVD_ICC - 196
2183 {.AsmStrOffset: 2842, .AliasCondStart: 724, .NumOperands: 4, .NumConds: 5 },
2184 {.AsmStrOffset: 2862, .AliasCondStart: 729, .NumOperands: 4, .NumConds: 6 },
2185 {.AsmStrOffset: 2882, .AliasCondStart: 735, .NumOperands: 4, .NumConds: 5 },
2186 {.AsmStrOffset: 2902, .AliasCondStart: 740, .NumOperands: 4, .NumConds: 6 },
2187 {.AsmStrOffset: 2922, .AliasCondStart: 746, .NumOperands: 4, .NumConds: 5 },
2188 {.AsmStrOffset: 2943, .AliasCondStart: 751, .NumOperands: 4, .NumConds: 6 },
2189 {.AsmStrOffset: 2964, .AliasCondStart: 757, .NumOperands: 4, .NumConds: 5 },
2190 {.AsmStrOffset: 2984, .AliasCondStart: 762, .NumOperands: 4, .NumConds: 6 },
2191 {.AsmStrOffset: 3004, .AliasCondStart: 768, .NumOperands: 4, .NumConds: 5 },
2192 {.AsmStrOffset: 3024, .AliasCondStart: 773, .NumOperands: 4, .NumConds: 6 },
2193 {.AsmStrOffset: 3044, .AliasCondStart: 779, .NumOperands: 4, .NumConds: 5 },
2194 {.AsmStrOffset: 3065, .AliasCondStart: 784, .NumOperands: 4, .NumConds: 6 },
2195 {.AsmStrOffset: 3086, .AliasCondStart: 790, .NumOperands: 4, .NumConds: 5 },
2196 {.AsmStrOffset: 3107, .AliasCondStart: 795, .NumOperands: 4, .NumConds: 6 },
2197 {.AsmStrOffset: 3128, .AliasCondStart: 801, .NumOperands: 4, .NumConds: 5 },
2198 {.AsmStrOffset: 3148, .AliasCondStart: 806, .NumOperands: 4, .NumConds: 6 },
2199 {.AsmStrOffset: 3168, .AliasCondStart: 812, .NumOperands: 4, .NumConds: 5 },
2200 {.AsmStrOffset: 3189, .AliasCondStart: 817, .NumOperands: 4, .NumConds: 6 },
2201 {.AsmStrOffset: 3210, .AliasCondStart: 823, .NumOperands: 4, .NumConds: 5 },
2202 {.AsmStrOffset: 3232, .AliasCondStart: 828, .NumOperands: 4, .NumConds: 6 },
2203 {.AsmStrOffset: 3254, .AliasCondStart: 834, .NumOperands: 4, .NumConds: 5 },
2204 {.AsmStrOffset: 3275, .AliasCondStart: 839, .NumOperands: 4, .NumConds: 6 },
2205 {.AsmStrOffset: 3296, .AliasCondStart: 845, .NumOperands: 4, .NumConds: 5 },
2206 {.AsmStrOffset: 3317, .AliasCondStart: 850, .NumOperands: 4, .NumConds: 6 },
2207 {.AsmStrOffset: 3338, .AliasCondStart: 856, .NumOperands: 4, .NumConds: 5 },
2208 {.AsmStrOffset: 3360, .AliasCondStart: 861, .NumOperands: 4, .NumConds: 6 },
2209 {.AsmStrOffset: 3382, .AliasCondStart: 867, .NumOperands: 4, .NumConds: 5 },
2210 {.AsmStrOffset: 3404, .AliasCondStart: 872, .NumOperands: 4, .NumConds: 6 },
2211 {.AsmStrOffset: 3426, .AliasCondStart: 878, .NumOperands: 4, .NumConds: 5 },
2212 {.AsmStrOffset: 3447, .AliasCondStart: 883, .NumOperands: 4, .NumConds: 6 },
2213 {.AsmStrOffset: 3468, .AliasCondStart: 889, .NumOperands: 4, .NumConds: 5 },
2214 {.AsmStrOffset: 3489, .AliasCondStart: 894, .NumOperands: 4, .NumConds: 6 },
2215 // SP::FMOVQ_ICC - 228
2216 {.AsmStrOffset: 3510, .AliasCondStart: 900, .NumOperands: 4, .NumConds: 5 },
2217 {.AsmStrOffset: 3530, .AliasCondStart: 905, .NumOperands: 4, .NumConds: 6 },
2218 {.AsmStrOffset: 3550, .AliasCondStart: 911, .NumOperands: 4, .NumConds: 5 },
2219 {.AsmStrOffset: 3570, .AliasCondStart: 916, .NumOperands: 4, .NumConds: 6 },
2220 {.AsmStrOffset: 3590, .AliasCondStart: 922, .NumOperands: 4, .NumConds: 5 },
2221 {.AsmStrOffset: 3611, .AliasCondStart: 927, .NumOperands: 4, .NumConds: 6 },
2222 {.AsmStrOffset: 3632, .AliasCondStart: 933, .NumOperands: 4, .NumConds: 5 },
2223 {.AsmStrOffset: 3652, .AliasCondStart: 938, .NumOperands: 4, .NumConds: 6 },
2224 {.AsmStrOffset: 3672, .AliasCondStart: 944, .NumOperands: 4, .NumConds: 5 },
2225 {.AsmStrOffset: 3692, .AliasCondStart: 949, .NumOperands: 4, .NumConds: 6 },
2226 {.AsmStrOffset: 3712, .AliasCondStart: 955, .NumOperands: 4, .NumConds: 5 },
2227 {.AsmStrOffset: 3733, .AliasCondStart: 960, .NumOperands: 4, .NumConds: 6 },
2228 {.AsmStrOffset: 3754, .AliasCondStart: 966, .NumOperands: 4, .NumConds: 5 },
2229 {.AsmStrOffset: 3775, .AliasCondStart: 971, .NumOperands: 4, .NumConds: 6 },
2230 {.AsmStrOffset: 3796, .AliasCondStart: 977, .NumOperands: 4, .NumConds: 5 },
2231 {.AsmStrOffset: 3816, .AliasCondStart: 982, .NumOperands: 4, .NumConds: 6 },
2232 {.AsmStrOffset: 3836, .AliasCondStart: 988, .NumOperands: 4, .NumConds: 5 },
2233 {.AsmStrOffset: 3857, .AliasCondStart: 993, .NumOperands: 4, .NumConds: 6 },
2234 {.AsmStrOffset: 3878, .AliasCondStart: 999, .NumOperands: 4, .NumConds: 5 },
2235 {.AsmStrOffset: 3900, .AliasCondStart: 1004, .NumOperands: 4, .NumConds: 6 },
2236 {.AsmStrOffset: 3922, .AliasCondStart: 1010, .NumOperands: 4, .NumConds: 5 },
2237 {.AsmStrOffset: 3943, .AliasCondStart: 1015, .NumOperands: 4, .NumConds: 6 },
2238 {.AsmStrOffset: 3964, .AliasCondStart: 1021, .NumOperands: 4, .NumConds: 5 },
2239 {.AsmStrOffset: 3985, .AliasCondStart: 1026, .NumOperands: 4, .NumConds: 6 },
2240 {.AsmStrOffset: 4006, .AliasCondStart: 1032, .NumOperands: 4, .NumConds: 5 },
2241 {.AsmStrOffset: 4028, .AliasCondStart: 1037, .NumOperands: 4, .NumConds: 6 },
2242 {.AsmStrOffset: 4050, .AliasCondStart: 1043, .NumOperands: 4, .NumConds: 5 },
2243 {.AsmStrOffset: 4072, .AliasCondStart: 1048, .NumOperands: 4, .NumConds: 6 },
2244 {.AsmStrOffset: 4094, .AliasCondStart: 1054, .NumOperands: 4, .NumConds: 5 },
2245 {.AsmStrOffset: 4115, .AliasCondStart: 1059, .NumOperands: 4, .NumConds: 6 },
2246 {.AsmStrOffset: 4136, .AliasCondStart: 1065, .NumOperands: 4, .NumConds: 5 },
2247 {.AsmStrOffset: 4157, .AliasCondStart: 1070, .NumOperands: 4, .NumConds: 6 },
2248 // SP::FMOVRD - 260
2249 {.AsmStrOffset: 4178, .AliasCondStart: 1076, .NumOperands: 5, .NumConds: 6 },
2250 {.AsmStrOffset: 4199, .AliasCondStart: 1082, .NumOperands: 5, .NumConds: 6 },
2251 {.AsmStrOffset: 4219, .AliasCondStart: 1088, .NumOperands: 5, .NumConds: 6 },
2252 {.AsmStrOffset: 4239, .AliasCondStart: 1094, .NumOperands: 5, .NumConds: 6 },
2253 // SP::FMOVRQ - 264
2254 {.AsmStrOffset: 4260, .AliasCondStart: 1100, .NumOperands: 5, .NumConds: 6 },
2255 {.AsmStrOffset: 4281, .AliasCondStart: 1106, .NumOperands: 5, .NumConds: 6 },
2256 {.AsmStrOffset: 4301, .AliasCondStart: 1112, .NumOperands: 5, .NumConds: 6 },
2257 {.AsmStrOffset: 4321, .AliasCondStart: 1118, .NumOperands: 5, .NumConds: 6 },
2258 // SP::FMOVRS - 268
2259 {.AsmStrOffset: 4342, .AliasCondStart: 1124, .NumOperands: 5, .NumConds: 6 },
2260 {.AsmStrOffset: 4363, .AliasCondStart: 1130, .NumOperands: 5, .NumConds: 6 },
2261 {.AsmStrOffset: 4383, .AliasCondStart: 1136, .NumOperands: 5, .NumConds: 6 },
2262 {.AsmStrOffset: 4403, .AliasCondStart: 1142, .NumOperands: 5, .NumConds: 6 },
2263 // SP::FMOVS_ICC - 272
2264 {.AsmStrOffset: 4424, .AliasCondStart: 1148, .NumOperands: 4, .NumConds: 5 },
2265 {.AsmStrOffset: 4444, .AliasCondStart: 1153, .NumOperands: 4, .NumConds: 6 },
2266 {.AsmStrOffset: 4464, .AliasCondStart: 1159, .NumOperands: 4, .NumConds: 5 },
2267 {.AsmStrOffset: 4484, .AliasCondStart: 1164, .NumOperands: 4, .NumConds: 6 },
2268 {.AsmStrOffset: 4504, .AliasCondStart: 1170, .NumOperands: 4, .NumConds: 5 },
2269 {.AsmStrOffset: 4525, .AliasCondStart: 1175, .NumOperands: 4, .NumConds: 6 },
2270 {.AsmStrOffset: 4546, .AliasCondStart: 1181, .NumOperands: 4, .NumConds: 5 },
2271 {.AsmStrOffset: 4566, .AliasCondStart: 1186, .NumOperands: 4, .NumConds: 6 },
2272 {.AsmStrOffset: 4586, .AliasCondStart: 1192, .NumOperands: 4, .NumConds: 5 },
2273 {.AsmStrOffset: 4606, .AliasCondStart: 1197, .NumOperands: 4, .NumConds: 6 },
2274 {.AsmStrOffset: 4626, .AliasCondStart: 1203, .NumOperands: 4, .NumConds: 5 },
2275 {.AsmStrOffset: 4647, .AliasCondStart: 1208, .NumOperands: 4, .NumConds: 6 },
2276 {.AsmStrOffset: 4668, .AliasCondStart: 1214, .NumOperands: 4, .NumConds: 5 },
2277 {.AsmStrOffset: 4689, .AliasCondStart: 1219, .NumOperands: 4, .NumConds: 6 },
2278 {.AsmStrOffset: 4710, .AliasCondStart: 1225, .NumOperands: 4, .NumConds: 5 },
2279 {.AsmStrOffset: 4730, .AliasCondStart: 1230, .NumOperands: 4, .NumConds: 6 },
2280 {.AsmStrOffset: 4750, .AliasCondStart: 1236, .NumOperands: 4, .NumConds: 5 },
2281 {.AsmStrOffset: 4771, .AliasCondStart: 1241, .NumOperands: 4, .NumConds: 6 },
2282 {.AsmStrOffset: 4792, .AliasCondStart: 1247, .NumOperands: 4, .NumConds: 5 },
2283 {.AsmStrOffset: 4814, .AliasCondStart: 1252, .NumOperands: 4, .NumConds: 6 },
2284 {.AsmStrOffset: 4836, .AliasCondStart: 1258, .NumOperands: 4, .NumConds: 5 },
2285 {.AsmStrOffset: 4857, .AliasCondStart: 1263, .NumOperands: 4, .NumConds: 6 },
2286 {.AsmStrOffset: 4878, .AliasCondStart: 1269, .NumOperands: 4, .NumConds: 5 },
2287 {.AsmStrOffset: 4899, .AliasCondStart: 1274, .NumOperands: 4, .NumConds: 6 },
2288 {.AsmStrOffset: 4920, .AliasCondStart: 1280, .NumOperands: 4, .NumConds: 5 },
2289 {.AsmStrOffset: 4942, .AliasCondStart: 1285, .NumOperands: 4, .NumConds: 6 },
2290 {.AsmStrOffset: 4964, .AliasCondStart: 1291, .NumOperands: 4, .NumConds: 5 },
2291 {.AsmStrOffset: 4986, .AliasCondStart: 1296, .NumOperands: 4, .NumConds: 6 },
2292 {.AsmStrOffset: 5008, .AliasCondStart: 1302, .NumOperands: 4, .NumConds: 5 },
2293 {.AsmStrOffset: 5029, .AliasCondStart: 1307, .NumOperands: 4, .NumConds: 6 },
2294 {.AsmStrOffset: 5050, .AliasCondStart: 1313, .NumOperands: 4, .NumConds: 5 },
2295 {.AsmStrOffset: 5071, .AliasCondStart: 1318, .NumOperands: 4, .NumConds: 6 },
2296 // SP::MOVICCri - 304
2297 {.AsmStrOffset: 5092, .AliasCondStart: 1324, .NumOperands: 4, .NumConds: 5 },
2298 {.AsmStrOffset: 5110, .AliasCondStart: 1329, .NumOperands: 4, .NumConds: 6 },
2299 {.AsmStrOffset: 5128, .AliasCondStart: 1335, .NumOperands: 4, .NumConds: 5 },
2300 {.AsmStrOffset: 5146, .AliasCondStart: 1340, .NumOperands: 4, .NumConds: 6 },
2301 {.AsmStrOffset: 5164, .AliasCondStart: 1346, .NumOperands: 4, .NumConds: 5 },
2302 {.AsmStrOffset: 5183, .AliasCondStart: 1351, .NumOperands: 4, .NumConds: 6 },
2303 {.AsmStrOffset: 5202, .AliasCondStart: 1357, .NumOperands: 4, .NumConds: 5 },
2304 {.AsmStrOffset: 5220, .AliasCondStart: 1362, .NumOperands: 4, .NumConds: 6 },
2305 {.AsmStrOffset: 5238, .AliasCondStart: 1368, .NumOperands: 4, .NumConds: 5 },
2306 {.AsmStrOffset: 5256, .AliasCondStart: 1373, .NumOperands: 4, .NumConds: 6 },
2307 {.AsmStrOffset: 5274, .AliasCondStart: 1379, .NumOperands: 4, .NumConds: 5 },
2308 {.AsmStrOffset: 5293, .AliasCondStart: 1384, .NumOperands: 4, .NumConds: 6 },
2309 {.AsmStrOffset: 5312, .AliasCondStart: 1390, .NumOperands: 4, .NumConds: 5 },
2310 {.AsmStrOffset: 5331, .AliasCondStart: 1395, .NumOperands: 4, .NumConds: 6 },
2311 {.AsmStrOffset: 5350, .AliasCondStart: 1401, .NumOperands: 4, .NumConds: 5 },
2312 {.AsmStrOffset: 5368, .AliasCondStart: 1406, .NumOperands: 4, .NumConds: 6 },
2313 {.AsmStrOffset: 5386, .AliasCondStart: 1412, .NumOperands: 4, .NumConds: 5 },
2314 {.AsmStrOffset: 5405, .AliasCondStart: 1417, .NumOperands: 4, .NumConds: 6 },
2315 {.AsmStrOffset: 5424, .AliasCondStart: 1423, .NumOperands: 4, .NumConds: 5 },
2316 {.AsmStrOffset: 5444, .AliasCondStart: 1428, .NumOperands: 4, .NumConds: 6 },
2317 {.AsmStrOffset: 5464, .AliasCondStart: 1434, .NumOperands: 4, .NumConds: 5 },
2318 {.AsmStrOffset: 5483, .AliasCondStart: 1439, .NumOperands: 4, .NumConds: 6 },
2319 {.AsmStrOffset: 5502, .AliasCondStart: 1445, .NumOperands: 4, .NumConds: 5 },
2320 {.AsmStrOffset: 5521, .AliasCondStart: 1450, .NumOperands: 4, .NumConds: 6 },
2321 {.AsmStrOffset: 5540, .AliasCondStart: 1456, .NumOperands: 4, .NumConds: 5 },
2322 {.AsmStrOffset: 5560, .AliasCondStart: 1461, .NumOperands: 4, .NumConds: 6 },
2323 {.AsmStrOffset: 5580, .AliasCondStart: 1467, .NumOperands: 4, .NumConds: 5 },
2324 {.AsmStrOffset: 5600, .AliasCondStart: 1472, .NumOperands: 4, .NumConds: 6 },
2325 {.AsmStrOffset: 5620, .AliasCondStart: 1478, .NumOperands: 4, .NumConds: 5 },
2326 {.AsmStrOffset: 5639, .AliasCondStart: 1483, .NumOperands: 4, .NumConds: 6 },
2327 {.AsmStrOffset: 5658, .AliasCondStart: 1489, .NumOperands: 4, .NumConds: 5 },
2328 {.AsmStrOffset: 5677, .AliasCondStart: 1494, .NumOperands: 4, .NumConds: 6 },
2329 // SP::MOVICCrr - 336
2330 {.AsmStrOffset: 5092, .AliasCondStart: 1500, .NumOperands: 4, .NumConds: 5 },
2331 {.AsmStrOffset: 5110, .AliasCondStart: 1505, .NumOperands: 4, .NumConds: 6 },
2332 {.AsmStrOffset: 5128, .AliasCondStart: 1511, .NumOperands: 4, .NumConds: 5 },
2333 {.AsmStrOffset: 5146, .AliasCondStart: 1516, .NumOperands: 4, .NumConds: 6 },
2334 {.AsmStrOffset: 5164, .AliasCondStart: 1522, .NumOperands: 4, .NumConds: 5 },
2335 {.AsmStrOffset: 5183, .AliasCondStart: 1527, .NumOperands: 4, .NumConds: 6 },
2336 {.AsmStrOffset: 5202, .AliasCondStart: 1533, .NumOperands: 4, .NumConds: 5 },
2337 {.AsmStrOffset: 5220, .AliasCondStart: 1538, .NumOperands: 4, .NumConds: 6 },
2338 {.AsmStrOffset: 5238, .AliasCondStart: 1544, .NumOperands: 4, .NumConds: 5 },
2339 {.AsmStrOffset: 5256, .AliasCondStart: 1549, .NumOperands: 4, .NumConds: 6 },
2340 {.AsmStrOffset: 5274, .AliasCondStart: 1555, .NumOperands: 4, .NumConds: 5 },
2341 {.AsmStrOffset: 5293, .AliasCondStart: 1560, .NumOperands: 4, .NumConds: 6 },
2342 {.AsmStrOffset: 5312, .AliasCondStart: 1566, .NumOperands: 4, .NumConds: 5 },
2343 {.AsmStrOffset: 5331, .AliasCondStart: 1571, .NumOperands: 4, .NumConds: 6 },
2344 {.AsmStrOffset: 5350, .AliasCondStart: 1577, .NumOperands: 4, .NumConds: 5 },
2345 {.AsmStrOffset: 5368, .AliasCondStart: 1582, .NumOperands: 4, .NumConds: 6 },
2346 {.AsmStrOffset: 5386, .AliasCondStart: 1588, .NumOperands: 4, .NumConds: 5 },
2347 {.AsmStrOffset: 5405, .AliasCondStart: 1593, .NumOperands: 4, .NumConds: 6 },
2348 {.AsmStrOffset: 5424, .AliasCondStart: 1599, .NumOperands: 4, .NumConds: 5 },
2349 {.AsmStrOffset: 5444, .AliasCondStart: 1604, .NumOperands: 4, .NumConds: 6 },
2350 {.AsmStrOffset: 5464, .AliasCondStart: 1610, .NumOperands: 4, .NumConds: 5 },
2351 {.AsmStrOffset: 5483, .AliasCondStart: 1615, .NumOperands: 4, .NumConds: 6 },
2352 {.AsmStrOffset: 5502, .AliasCondStart: 1621, .NumOperands: 4, .NumConds: 5 },
2353 {.AsmStrOffset: 5521, .AliasCondStart: 1626, .NumOperands: 4, .NumConds: 6 },
2354 {.AsmStrOffset: 5540, .AliasCondStart: 1632, .NumOperands: 4, .NumConds: 5 },
2355 {.AsmStrOffset: 5560, .AliasCondStart: 1637, .NumOperands: 4, .NumConds: 6 },
2356 {.AsmStrOffset: 5580, .AliasCondStart: 1643, .NumOperands: 4, .NumConds: 5 },
2357 {.AsmStrOffset: 5600, .AliasCondStart: 1648, .NumOperands: 4, .NumConds: 6 },
2358 {.AsmStrOffset: 5620, .AliasCondStart: 1654, .NumOperands: 4, .NumConds: 5 },
2359 {.AsmStrOffset: 5639, .AliasCondStart: 1659, .NumOperands: 4, .NumConds: 6 },
2360 {.AsmStrOffset: 5658, .AliasCondStart: 1665, .NumOperands: 4, .NumConds: 5 },
2361 {.AsmStrOffset: 5677, .AliasCondStart: 1670, .NumOperands: 4, .NumConds: 6 },
2362 // SP::MOVRri - 368
2363 {.AsmStrOffset: 5696, .AliasCondStart: 1676, .NumOperands: 5, .NumConds: 6 },
2364 {.AsmStrOffset: 5715, .AliasCondStart: 1682, .NumOperands: 5, .NumConds: 6 },
2365 {.AsmStrOffset: 5733, .AliasCondStart: 1688, .NumOperands: 5, .NumConds: 6 },
2366 {.AsmStrOffset: 5751, .AliasCondStart: 1694, .NumOperands: 5, .NumConds: 6 },
2367 // SP::MOVRrr - 372
2368 {.AsmStrOffset: 5696, .AliasCondStart: 1700, .NumOperands: 5, .NumConds: 6 },
2369 {.AsmStrOffset: 5715, .AliasCondStart: 1706, .NumOperands: 5, .NumConds: 6 },
2370 {.AsmStrOffset: 5733, .AliasCondStart: 1712, .NumOperands: 5, .NumConds: 6 },
2371 {.AsmStrOffset: 5751, .AliasCondStart: 1718, .NumOperands: 5, .NumConds: 6 },
2372 // SP::ORCCrr - 376
2373 {.AsmStrOffset: 5770, .AliasCondStart: 1724, .NumOperands: 3, .NumConds: 3 },
2374 // SP::ORri - 377
2375 {.AsmStrOffset: 5777, .AliasCondStart: 1727, .NumOperands: 3, .NumConds: 2 },
2376 // SP::ORrr - 378
2377 {.AsmStrOffset: 5777, .AliasCondStart: 1729, .NumOperands: 3, .NumConds: 3 },
2378 // SP::RESTORErr - 379
2379 {.AsmStrOffset: 5788, .AliasCondStart: 1732, .NumOperands: 3, .NumConds: 3 },
2380 // SP::RET - 380
2381 {.AsmStrOffset: 5796, .AliasCondStart: 1735, .NumOperands: 1, .NumConds: 1 },
2382 // SP::RETL - 381
2383 {.AsmStrOffset: 5800, .AliasCondStart: 1736, .NumOperands: 1, .NumConds: 1 },
2384 // SP::SAVErr - 382
2385 {.AsmStrOffset: 5805, .AliasCondStart: 1737, .NumOperands: 3, .NumConds: 3 },
2386 // SP::SUBCCri - 383
2387 {.AsmStrOffset: 5810, .AliasCondStart: 1740, .NumOperands: 3, .NumConds: 2 },
2388 // SP::SUBCCrr - 384
2389 {.AsmStrOffset: 5810, .AliasCondStart: 1742, .NumOperands: 3, .NumConds: 3 },
2390 // SP::TICCri - 385
2391 {.AsmStrOffset: 5821, .AliasCondStart: 1745, .NumOperands: 3, .NumConds: 4 },
2392 {.AsmStrOffset: 5833, .AliasCondStart: 1749, .NumOperands: 3, .NumConds: 5 },
2393 {.AsmStrOffset: 5845, .AliasCondStart: 1754, .NumOperands: 3, .NumConds: 4 },
2394 {.AsmStrOffset: 5862, .AliasCondStart: 1758, .NumOperands: 3, .NumConds: 5 },
2395 {.AsmStrOffset: 5879, .AliasCondStart: 1763, .NumOperands: 3, .NumConds: 4 },
2396 {.AsmStrOffset: 5891, .AliasCondStart: 1767, .NumOperands: 3, .NumConds: 5 },
2397 {.AsmStrOffset: 5903, .AliasCondStart: 1772, .NumOperands: 3, .NumConds: 4 },
2398 {.AsmStrOffset: 5920, .AliasCondStart: 1776, .NumOperands: 3, .NumConds: 5 },
2399 {.AsmStrOffset: 5937, .AliasCondStart: 1781, .NumOperands: 3, .NumConds: 4 },
2400 {.AsmStrOffset: 5950, .AliasCondStart: 1785, .NumOperands: 3, .NumConds: 5 },
2401 {.AsmStrOffset: 5963, .AliasCondStart: 1790, .NumOperands: 3, .NumConds: 4 },
2402 {.AsmStrOffset: 5981, .AliasCondStart: 1794, .NumOperands: 3, .NumConds: 5 },
2403 {.AsmStrOffset: 5999, .AliasCondStart: 1799, .NumOperands: 3, .NumConds: 4 },
2404 {.AsmStrOffset: 6011, .AliasCondStart: 1803, .NumOperands: 3, .NumConds: 5 },
2405 {.AsmStrOffset: 6023, .AliasCondStart: 1808, .NumOperands: 3, .NumConds: 4 },
2406 {.AsmStrOffset: 6040, .AliasCondStart: 1812, .NumOperands: 3, .NumConds: 5 },
2407 {.AsmStrOffset: 6057, .AliasCondStart: 1817, .NumOperands: 3, .NumConds: 4 },
2408 {.AsmStrOffset: 6069, .AliasCondStart: 1821, .NumOperands: 3, .NumConds: 5 },
2409 {.AsmStrOffset: 6081, .AliasCondStart: 1826, .NumOperands: 3, .NumConds: 4 },
2410 {.AsmStrOffset: 6098, .AliasCondStart: 1830, .NumOperands: 3, .NumConds: 5 },
2411 {.AsmStrOffset: 6115, .AliasCondStart: 1835, .NumOperands: 3, .NumConds: 4 },
2412 {.AsmStrOffset: 6128, .AliasCondStart: 1839, .NumOperands: 3, .NumConds: 5 },
2413 {.AsmStrOffset: 6141, .AliasCondStart: 1844, .NumOperands: 3, .NumConds: 4 },
2414 {.AsmStrOffset: 6159, .AliasCondStart: 1848, .NumOperands: 3, .NumConds: 5 },
2415 {.AsmStrOffset: 6177, .AliasCondStart: 1853, .NumOperands: 3, .NumConds: 4 },
2416 {.AsmStrOffset: 6190, .AliasCondStart: 1857, .NumOperands: 3, .NumConds: 5 },
2417 {.AsmStrOffset: 6203, .AliasCondStart: 1862, .NumOperands: 3, .NumConds: 4 },
2418 {.AsmStrOffset: 6221, .AliasCondStart: 1866, .NumOperands: 3, .NumConds: 5 },
2419 {.AsmStrOffset: 6239, .AliasCondStart: 1871, .NumOperands: 3, .NumConds: 4 },
2420 {.AsmStrOffset: 6251, .AliasCondStart: 1875, .NumOperands: 3, .NumConds: 5 },
2421 {.AsmStrOffset: 6263, .AliasCondStart: 1880, .NumOperands: 3, .NumConds: 4 },
2422 {.AsmStrOffset: 6280, .AliasCondStart: 1884, .NumOperands: 3, .NumConds: 5 },
2423 {.AsmStrOffset: 6297, .AliasCondStart: 1889, .NumOperands: 3, .NumConds: 4 },
2424 {.AsmStrOffset: 6310, .AliasCondStart: 1893, .NumOperands: 3, .NumConds: 5 },
2425 {.AsmStrOffset: 6323, .AliasCondStart: 1898, .NumOperands: 3, .NumConds: 4 },
2426 {.AsmStrOffset: 6341, .AliasCondStart: 1902, .NumOperands: 3, .NumConds: 5 },
2427 {.AsmStrOffset: 6359, .AliasCondStart: 1907, .NumOperands: 3, .NumConds: 4 },
2428 {.AsmStrOffset: 6373, .AliasCondStart: 1911, .NumOperands: 3, .NumConds: 5 },
2429 {.AsmStrOffset: 6387, .AliasCondStart: 1916, .NumOperands: 3, .NumConds: 4 },
2430 {.AsmStrOffset: 6406, .AliasCondStart: 1920, .NumOperands: 3, .NumConds: 5 },
2431 {.AsmStrOffset: 6425, .AliasCondStart: 1925, .NumOperands: 3, .NumConds: 4 },
2432 {.AsmStrOffset: 6438, .AliasCondStart: 1929, .NumOperands: 3, .NumConds: 5 },
2433 {.AsmStrOffset: 6451, .AliasCondStart: 1934, .NumOperands: 3, .NumConds: 4 },
2434 {.AsmStrOffset: 6469, .AliasCondStart: 1938, .NumOperands: 3, .NumConds: 5 },
2435 {.AsmStrOffset: 6487, .AliasCondStart: 1943, .NumOperands: 3, .NumConds: 4 },
2436 {.AsmStrOffset: 6500, .AliasCondStart: 1947, .NumOperands: 3, .NumConds: 5 },
2437 {.AsmStrOffset: 6513, .AliasCondStart: 1952, .NumOperands: 3, .NumConds: 4 },
2438 {.AsmStrOffset: 6531, .AliasCondStart: 1956, .NumOperands: 3, .NumConds: 5 },
2439 {.AsmStrOffset: 6549, .AliasCondStart: 1961, .NumOperands: 3, .NumConds: 4 },
2440 {.AsmStrOffset: 6563, .AliasCondStart: 1965, .NumOperands: 3, .NumConds: 5 },
2441 {.AsmStrOffset: 6577, .AliasCondStart: 1970, .NumOperands: 3, .NumConds: 4 },
2442 {.AsmStrOffset: 6596, .AliasCondStart: 1974, .NumOperands: 3, .NumConds: 5 },
2443 {.AsmStrOffset: 6615, .AliasCondStart: 1979, .NumOperands: 3, .NumConds: 4 },
2444 {.AsmStrOffset: 6629, .AliasCondStart: 1983, .NumOperands: 3, .NumConds: 5 },
2445 {.AsmStrOffset: 6643, .AliasCondStart: 1988, .NumOperands: 3, .NumConds: 4 },
2446 {.AsmStrOffset: 6662, .AliasCondStart: 1992, .NumOperands: 3, .NumConds: 5 },
2447 {.AsmStrOffset: 6681, .AliasCondStart: 1997, .NumOperands: 3, .NumConds: 4 },
2448 {.AsmStrOffset: 6694, .AliasCondStart: 2001, .NumOperands: 3, .NumConds: 5 },
2449 {.AsmStrOffset: 6707, .AliasCondStart: 2006, .NumOperands: 3, .NumConds: 4 },
2450 {.AsmStrOffset: 6725, .AliasCondStart: 2010, .NumOperands: 3, .NumConds: 5 },
2451 {.AsmStrOffset: 6743, .AliasCondStart: 2015, .NumOperands: 3, .NumConds: 4 },
2452 {.AsmStrOffset: 6756, .AliasCondStart: 2019, .NumOperands: 3, .NumConds: 5 },
2453 {.AsmStrOffset: 6769, .AliasCondStart: 2024, .NumOperands: 3, .NumConds: 4 },
2454 {.AsmStrOffset: 6787, .AliasCondStart: 2028, .NumOperands: 3, .NumConds: 5 },
2455 // SP::TICCrr - 449
2456 {.AsmStrOffset: 5821, .AliasCondStart: 2033, .NumOperands: 3, .NumConds: 4 },
2457 {.AsmStrOffset: 5833, .AliasCondStart: 2037, .NumOperands: 3, .NumConds: 5 },
2458 {.AsmStrOffset: 5845, .AliasCondStart: 2042, .NumOperands: 3, .NumConds: 4 },
2459 {.AsmStrOffset: 5862, .AliasCondStart: 2046, .NumOperands: 3, .NumConds: 5 },
2460 {.AsmStrOffset: 5879, .AliasCondStart: 2051, .NumOperands: 3, .NumConds: 4 },
2461 {.AsmStrOffset: 5891, .AliasCondStart: 2055, .NumOperands: 3, .NumConds: 5 },
2462 {.AsmStrOffset: 5903, .AliasCondStart: 2060, .NumOperands: 3, .NumConds: 4 },
2463 {.AsmStrOffset: 5920, .AliasCondStart: 2064, .NumOperands: 3, .NumConds: 5 },
2464 {.AsmStrOffset: 5937, .AliasCondStart: 2069, .NumOperands: 3, .NumConds: 4 },
2465 {.AsmStrOffset: 5950, .AliasCondStart: 2073, .NumOperands: 3, .NumConds: 5 },
2466 {.AsmStrOffset: 5963, .AliasCondStart: 2078, .NumOperands: 3, .NumConds: 4 },
2467 {.AsmStrOffset: 5981, .AliasCondStart: 2082, .NumOperands: 3, .NumConds: 5 },
2468 {.AsmStrOffset: 5999, .AliasCondStart: 2087, .NumOperands: 3, .NumConds: 4 },
2469 {.AsmStrOffset: 6011, .AliasCondStart: 2091, .NumOperands: 3, .NumConds: 5 },
2470 {.AsmStrOffset: 6023, .AliasCondStart: 2096, .NumOperands: 3, .NumConds: 4 },
2471 {.AsmStrOffset: 6040, .AliasCondStart: 2100, .NumOperands: 3, .NumConds: 5 },
2472 {.AsmStrOffset: 6057, .AliasCondStart: 2105, .NumOperands: 3, .NumConds: 4 },
2473 {.AsmStrOffset: 6069, .AliasCondStart: 2109, .NumOperands: 3, .NumConds: 5 },
2474 {.AsmStrOffset: 6081, .AliasCondStart: 2114, .NumOperands: 3, .NumConds: 4 },
2475 {.AsmStrOffset: 6098, .AliasCondStart: 2118, .NumOperands: 3, .NumConds: 5 },
2476 {.AsmStrOffset: 6115, .AliasCondStart: 2123, .NumOperands: 3, .NumConds: 4 },
2477 {.AsmStrOffset: 6128, .AliasCondStart: 2127, .NumOperands: 3, .NumConds: 5 },
2478 {.AsmStrOffset: 6141, .AliasCondStart: 2132, .NumOperands: 3, .NumConds: 4 },
2479 {.AsmStrOffset: 6159, .AliasCondStart: 2136, .NumOperands: 3, .NumConds: 5 },
2480 {.AsmStrOffset: 6177, .AliasCondStart: 2141, .NumOperands: 3, .NumConds: 4 },
2481 {.AsmStrOffset: 6190, .AliasCondStart: 2145, .NumOperands: 3, .NumConds: 5 },
2482 {.AsmStrOffset: 6203, .AliasCondStart: 2150, .NumOperands: 3, .NumConds: 4 },
2483 {.AsmStrOffset: 6221, .AliasCondStart: 2154, .NumOperands: 3, .NumConds: 5 },
2484 {.AsmStrOffset: 6239, .AliasCondStart: 2159, .NumOperands: 3, .NumConds: 4 },
2485 {.AsmStrOffset: 6251, .AliasCondStart: 2163, .NumOperands: 3, .NumConds: 5 },
2486 {.AsmStrOffset: 6263, .AliasCondStart: 2168, .NumOperands: 3, .NumConds: 4 },
2487 {.AsmStrOffset: 6280, .AliasCondStart: 2172, .NumOperands: 3, .NumConds: 5 },
2488 {.AsmStrOffset: 6297, .AliasCondStart: 2177, .NumOperands: 3, .NumConds: 4 },
2489 {.AsmStrOffset: 6310, .AliasCondStart: 2181, .NumOperands: 3, .NumConds: 5 },
2490 {.AsmStrOffset: 6323, .AliasCondStart: 2186, .NumOperands: 3, .NumConds: 4 },
2491 {.AsmStrOffset: 6341, .AliasCondStart: 2190, .NumOperands: 3, .NumConds: 5 },
2492 {.AsmStrOffset: 6359, .AliasCondStart: 2195, .NumOperands: 3, .NumConds: 4 },
2493 {.AsmStrOffset: 6373, .AliasCondStart: 2199, .NumOperands: 3, .NumConds: 5 },
2494 {.AsmStrOffset: 6387, .AliasCondStart: 2204, .NumOperands: 3, .NumConds: 4 },
2495 {.AsmStrOffset: 6406, .AliasCondStart: 2208, .NumOperands: 3, .NumConds: 5 },
2496 {.AsmStrOffset: 6425, .AliasCondStart: 2213, .NumOperands: 3, .NumConds: 4 },
2497 {.AsmStrOffset: 6438, .AliasCondStart: 2217, .NumOperands: 3, .NumConds: 5 },
2498 {.AsmStrOffset: 6451, .AliasCondStart: 2222, .NumOperands: 3, .NumConds: 4 },
2499 {.AsmStrOffset: 6469, .AliasCondStart: 2226, .NumOperands: 3, .NumConds: 5 },
2500 {.AsmStrOffset: 6487, .AliasCondStart: 2231, .NumOperands: 3, .NumConds: 4 },
2501 {.AsmStrOffset: 6500, .AliasCondStart: 2235, .NumOperands: 3, .NumConds: 5 },
2502 {.AsmStrOffset: 6513, .AliasCondStart: 2240, .NumOperands: 3, .NumConds: 4 },
2503 {.AsmStrOffset: 6531, .AliasCondStart: 2244, .NumOperands: 3, .NumConds: 5 },
2504 {.AsmStrOffset: 6549, .AliasCondStart: 2249, .NumOperands: 3, .NumConds: 4 },
2505 {.AsmStrOffset: 6563, .AliasCondStart: 2253, .NumOperands: 3, .NumConds: 5 },
2506 {.AsmStrOffset: 6577, .AliasCondStart: 2258, .NumOperands: 3, .NumConds: 4 },
2507 {.AsmStrOffset: 6596, .AliasCondStart: 2262, .NumOperands: 3, .NumConds: 5 },
2508 {.AsmStrOffset: 6615, .AliasCondStart: 2267, .NumOperands: 3, .NumConds: 4 },
2509 {.AsmStrOffset: 6629, .AliasCondStart: 2271, .NumOperands: 3, .NumConds: 5 },
2510 {.AsmStrOffset: 6643, .AliasCondStart: 2276, .NumOperands: 3, .NumConds: 4 },
2511 {.AsmStrOffset: 6662, .AliasCondStart: 2280, .NumOperands: 3, .NumConds: 5 },
2512 {.AsmStrOffset: 6681, .AliasCondStart: 2285, .NumOperands: 3, .NumConds: 4 },
2513 {.AsmStrOffset: 6694, .AliasCondStart: 2289, .NumOperands: 3, .NumConds: 5 },
2514 {.AsmStrOffset: 6707, .AliasCondStart: 2294, .NumOperands: 3, .NumConds: 4 },
2515 {.AsmStrOffset: 6725, .AliasCondStart: 2298, .NumOperands: 3, .NumConds: 5 },
2516 {.AsmStrOffset: 6743, .AliasCondStart: 2303, .NumOperands: 3, .NumConds: 4 },
2517 {.AsmStrOffset: 6756, .AliasCondStart: 2307, .NumOperands: 3, .NumConds: 5 },
2518 {.AsmStrOffset: 6769, .AliasCondStart: 2312, .NumOperands: 3, .NumConds: 4 },
2519 {.AsmStrOffset: 6787, .AliasCondStart: 2316, .NumOperands: 3, .NumConds: 5 },
2520 // SP::TRAPri - 513
2521 {.AsmStrOffset: 6805, .AliasCondStart: 2321, .NumOperands: 3, .NumConds: 3 },
2522 {.AsmStrOffset: 6811, .AliasCondStart: 2324, .NumOperands: 3, .NumConds: 3 },
2523 {.AsmStrOffset: 6822, .AliasCondStart: 2327, .NumOperands: 3, .NumConds: 3 },
2524 {.AsmStrOffset: 6828, .AliasCondStart: 2330, .NumOperands: 3, .NumConds: 3 },
2525 {.AsmStrOffset: 6839, .AliasCondStart: 2333, .NumOperands: 3, .NumConds: 3 },
2526 {.AsmStrOffset: 6846, .AliasCondStart: 2336, .NumOperands: 3, .NumConds: 3 },
2527 {.AsmStrOffset: 6858, .AliasCondStart: 2339, .NumOperands: 3, .NumConds: 3 },
2528 {.AsmStrOffset: 6864, .AliasCondStart: 2342, .NumOperands: 3, .NumConds: 3 },
2529 {.AsmStrOffset: 6875, .AliasCondStart: 2345, .NumOperands: 3, .NumConds: 3 },
2530 {.AsmStrOffset: 6881, .AliasCondStart: 2348, .NumOperands: 3, .NumConds: 3 },
2531 {.AsmStrOffset: 6892, .AliasCondStart: 2351, .NumOperands: 3, .NumConds: 3 },
2532 {.AsmStrOffset: 6899, .AliasCondStart: 2354, .NumOperands: 3, .NumConds: 3 },
2533 {.AsmStrOffset: 6911, .AliasCondStart: 2357, .NumOperands: 3, .NumConds: 3 },
2534 {.AsmStrOffset: 6918, .AliasCondStart: 2360, .NumOperands: 3, .NumConds: 3 },
2535 {.AsmStrOffset: 6930, .AliasCondStart: 2363, .NumOperands: 3, .NumConds: 3 },
2536 {.AsmStrOffset: 6936, .AliasCondStart: 2366, .NumOperands: 3, .NumConds: 3 },
2537 {.AsmStrOffset: 6947, .AliasCondStart: 2369, .NumOperands: 3, .NumConds: 3 },
2538 {.AsmStrOffset: 6954, .AliasCondStart: 2372, .NumOperands: 3, .NumConds: 3 },
2539 {.AsmStrOffset: 6966, .AliasCondStart: 2375, .NumOperands: 3, .NumConds: 3 },
2540 {.AsmStrOffset: 6974, .AliasCondStart: 2378, .NumOperands: 3, .NumConds: 3 },
2541 {.AsmStrOffset: 6987, .AliasCondStart: 2381, .NumOperands: 3, .NumConds: 3 },
2542 {.AsmStrOffset: 6994, .AliasCondStart: 2384, .NumOperands: 3, .NumConds: 3 },
2543 {.AsmStrOffset: 7006, .AliasCondStart: 2387, .NumOperands: 3, .NumConds: 3 },
2544 {.AsmStrOffset: 7013, .AliasCondStart: 2390, .NumOperands: 3, .NumConds: 3 },
2545 {.AsmStrOffset: 7025, .AliasCondStart: 2393, .NumOperands: 3, .NumConds: 3 },
2546 {.AsmStrOffset: 7033, .AliasCondStart: 2396, .NumOperands: 3, .NumConds: 3 },
2547 {.AsmStrOffset: 7046, .AliasCondStart: 2399, .NumOperands: 3, .NumConds: 3 },
2548 {.AsmStrOffset: 7054, .AliasCondStart: 2402, .NumOperands: 3, .NumConds: 3 },
2549 {.AsmStrOffset: 7067, .AliasCondStart: 2405, .NumOperands: 3, .NumConds: 3 },
2550 {.AsmStrOffset: 7074, .AliasCondStart: 2408, .NumOperands: 3, .NumConds: 3 },
2551 {.AsmStrOffset: 7086, .AliasCondStart: 2411, .NumOperands: 3, .NumConds: 3 },
2552 {.AsmStrOffset: 7093, .AliasCondStart: 2414, .NumOperands: 3, .NumConds: 3 },
2553 // SP::TRAPrr - 545
2554 {.AsmStrOffset: 6805, .AliasCondStart: 2417, .NumOperands: 3, .NumConds: 3 },
2555 {.AsmStrOffset: 6811, .AliasCondStart: 2420, .NumOperands: 3, .NumConds: 3 },
2556 {.AsmStrOffset: 6822, .AliasCondStart: 2423, .NumOperands: 3, .NumConds: 3 },
2557 {.AsmStrOffset: 6828, .AliasCondStart: 2426, .NumOperands: 3, .NumConds: 3 },
2558 {.AsmStrOffset: 6839, .AliasCondStart: 2429, .NumOperands: 3, .NumConds: 3 },
2559 {.AsmStrOffset: 6846, .AliasCondStart: 2432, .NumOperands: 3, .NumConds: 3 },
2560 {.AsmStrOffset: 6858, .AliasCondStart: 2435, .NumOperands: 3, .NumConds: 3 },
2561 {.AsmStrOffset: 6864, .AliasCondStart: 2438, .NumOperands: 3, .NumConds: 3 },
2562 {.AsmStrOffset: 6875, .AliasCondStart: 2441, .NumOperands: 3, .NumConds: 3 },
2563 {.AsmStrOffset: 6881, .AliasCondStart: 2444, .NumOperands: 3, .NumConds: 3 },
2564 {.AsmStrOffset: 6892, .AliasCondStart: 2447, .NumOperands: 3, .NumConds: 3 },
2565 {.AsmStrOffset: 6899, .AliasCondStart: 2450, .NumOperands: 3, .NumConds: 3 },
2566 {.AsmStrOffset: 6911, .AliasCondStart: 2453, .NumOperands: 3, .NumConds: 3 },
2567 {.AsmStrOffset: 6918, .AliasCondStart: 2456, .NumOperands: 3, .NumConds: 3 },
2568 {.AsmStrOffset: 6930, .AliasCondStart: 2459, .NumOperands: 3, .NumConds: 3 },
2569 {.AsmStrOffset: 6936, .AliasCondStart: 2462, .NumOperands: 3, .NumConds: 3 },
2570 {.AsmStrOffset: 6947, .AliasCondStart: 2465, .NumOperands: 3, .NumConds: 3 },
2571 {.AsmStrOffset: 6954, .AliasCondStart: 2468, .NumOperands: 3, .NumConds: 3 },
2572 {.AsmStrOffset: 6966, .AliasCondStart: 2471, .NumOperands: 3, .NumConds: 3 },
2573 {.AsmStrOffset: 6974, .AliasCondStart: 2474, .NumOperands: 3, .NumConds: 3 },
2574 {.AsmStrOffset: 6987, .AliasCondStart: 2477, .NumOperands: 3, .NumConds: 3 },
2575 {.AsmStrOffset: 6994, .AliasCondStart: 2480, .NumOperands: 3, .NumConds: 3 },
2576 {.AsmStrOffset: 7006, .AliasCondStart: 2483, .NumOperands: 3, .NumConds: 3 },
2577 {.AsmStrOffset: 7013, .AliasCondStart: 2486, .NumOperands: 3, .NumConds: 3 },
2578 {.AsmStrOffset: 7025, .AliasCondStart: 2489, .NumOperands: 3, .NumConds: 3 },
2579 {.AsmStrOffset: 7033, .AliasCondStart: 2492, .NumOperands: 3, .NumConds: 3 },
2580 {.AsmStrOffset: 7046, .AliasCondStart: 2495, .NumOperands: 3, .NumConds: 3 },
2581 {.AsmStrOffset: 7054, .AliasCondStart: 2498, .NumOperands: 3, .NumConds: 3 },
2582 {.AsmStrOffset: 7067, .AliasCondStart: 2501, .NumOperands: 3, .NumConds: 3 },
2583 {.AsmStrOffset: 7074, .AliasCondStart: 2504, .NumOperands: 3, .NumConds: 3 },
2584 {.AsmStrOffset: 7086, .AliasCondStart: 2507, .NumOperands: 3, .NumConds: 3 },
2585 {.AsmStrOffset: 7093, .AliasCondStart: 2510, .NumOperands: 3, .NumConds: 3 },
2586 // SP::TXCCri - 577
2587 {.AsmStrOffset: 7105, .AliasCondStart: 2513, .NumOperands: 3, .NumConds: 4 },
2588 {.AsmStrOffset: 5833, .AliasCondStart: 2517, .NumOperands: 3, .NumConds: 5 },
2589 {.AsmStrOffset: 7117, .AliasCondStart: 2522, .NumOperands: 3, .NumConds: 4 },
2590 {.AsmStrOffset: 5862, .AliasCondStart: 2526, .NumOperands: 3, .NumConds: 5 },
2591 {.AsmStrOffset: 7134, .AliasCondStart: 2531, .NumOperands: 3, .NumConds: 4 },
2592 {.AsmStrOffset: 5891, .AliasCondStart: 2535, .NumOperands: 3, .NumConds: 5 },
2593 {.AsmStrOffset: 7146, .AliasCondStart: 2540, .NumOperands: 3, .NumConds: 4 },
2594 {.AsmStrOffset: 5920, .AliasCondStart: 2544, .NumOperands: 3, .NumConds: 5 },
2595 {.AsmStrOffset: 7163, .AliasCondStart: 2549, .NumOperands: 3, .NumConds: 4 },
2596 {.AsmStrOffset: 5950, .AliasCondStart: 2553, .NumOperands: 3, .NumConds: 5 },
2597 {.AsmStrOffset: 7176, .AliasCondStart: 2558, .NumOperands: 3, .NumConds: 4 },
2598 {.AsmStrOffset: 5981, .AliasCondStart: 2562, .NumOperands: 3, .NumConds: 5 },
2599 {.AsmStrOffset: 7194, .AliasCondStart: 2567, .NumOperands: 3, .NumConds: 4 },
2600 {.AsmStrOffset: 6011, .AliasCondStart: 2571, .NumOperands: 3, .NumConds: 5 },
2601 {.AsmStrOffset: 7206, .AliasCondStart: 2576, .NumOperands: 3, .NumConds: 4 },
2602 {.AsmStrOffset: 6040, .AliasCondStart: 2580, .NumOperands: 3, .NumConds: 5 },
2603 {.AsmStrOffset: 7223, .AliasCondStart: 2585, .NumOperands: 3, .NumConds: 4 },
2604 {.AsmStrOffset: 6069, .AliasCondStart: 2589, .NumOperands: 3, .NumConds: 5 },
2605 {.AsmStrOffset: 7235, .AliasCondStart: 2594, .NumOperands: 3, .NumConds: 4 },
2606 {.AsmStrOffset: 6098, .AliasCondStart: 2598, .NumOperands: 3, .NumConds: 5 },
2607 {.AsmStrOffset: 7252, .AliasCondStart: 2603, .NumOperands: 3, .NumConds: 4 },
2608 {.AsmStrOffset: 6128, .AliasCondStart: 2607, .NumOperands: 3, .NumConds: 5 },
2609 {.AsmStrOffset: 7265, .AliasCondStart: 2612, .NumOperands: 3, .NumConds: 4 },
2610 {.AsmStrOffset: 6159, .AliasCondStart: 2616, .NumOperands: 3, .NumConds: 5 },
2611 {.AsmStrOffset: 7283, .AliasCondStart: 2621, .NumOperands: 3, .NumConds: 4 },
2612 {.AsmStrOffset: 6190, .AliasCondStart: 2625, .NumOperands: 3, .NumConds: 5 },
2613 {.AsmStrOffset: 7296, .AliasCondStart: 2630, .NumOperands: 3, .NumConds: 4 },
2614 {.AsmStrOffset: 6221, .AliasCondStart: 2634, .NumOperands: 3, .NumConds: 5 },
2615 {.AsmStrOffset: 7314, .AliasCondStart: 2639, .NumOperands: 3, .NumConds: 4 },
2616 {.AsmStrOffset: 6251, .AliasCondStart: 2643, .NumOperands: 3, .NumConds: 5 },
2617 {.AsmStrOffset: 7326, .AliasCondStart: 2648, .NumOperands: 3, .NumConds: 4 },
2618 {.AsmStrOffset: 6280, .AliasCondStart: 2652, .NumOperands: 3, .NumConds: 5 },
2619 {.AsmStrOffset: 7343, .AliasCondStart: 2657, .NumOperands: 3, .NumConds: 4 },
2620 {.AsmStrOffset: 6310, .AliasCondStart: 2661, .NumOperands: 3, .NumConds: 5 },
2621 {.AsmStrOffset: 7356, .AliasCondStart: 2666, .NumOperands: 3, .NumConds: 4 },
2622 {.AsmStrOffset: 6341, .AliasCondStart: 2670, .NumOperands: 3, .NumConds: 5 },
2623 {.AsmStrOffset: 7374, .AliasCondStart: 2675, .NumOperands: 3, .NumConds: 4 },
2624 {.AsmStrOffset: 6373, .AliasCondStart: 2679, .NumOperands: 3, .NumConds: 5 },
2625 {.AsmStrOffset: 7388, .AliasCondStart: 2684, .NumOperands: 3, .NumConds: 4 },
2626 {.AsmStrOffset: 6406, .AliasCondStart: 2688, .NumOperands: 3, .NumConds: 5 },
2627 {.AsmStrOffset: 7407, .AliasCondStart: 2693, .NumOperands: 3, .NumConds: 4 },
2628 {.AsmStrOffset: 6438, .AliasCondStart: 2697, .NumOperands: 3, .NumConds: 5 },
2629 {.AsmStrOffset: 7420, .AliasCondStart: 2702, .NumOperands: 3, .NumConds: 4 },
2630 {.AsmStrOffset: 6469, .AliasCondStart: 2706, .NumOperands: 3, .NumConds: 5 },
2631 {.AsmStrOffset: 7438, .AliasCondStart: 2711, .NumOperands: 3, .NumConds: 4 },
2632 {.AsmStrOffset: 6500, .AliasCondStart: 2715, .NumOperands: 3, .NumConds: 5 },
2633 {.AsmStrOffset: 7451, .AliasCondStart: 2720, .NumOperands: 3, .NumConds: 4 },
2634 {.AsmStrOffset: 6531, .AliasCondStart: 2724, .NumOperands: 3, .NumConds: 5 },
2635 {.AsmStrOffset: 7469, .AliasCondStart: 2729, .NumOperands: 3, .NumConds: 4 },
2636 {.AsmStrOffset: 6563, .AliasCondStart: 2733, .NumOperands: 3, .NumConds: 5 },
2637 {.AsmStrOffset: 7483, .AliasCondStart: 2738, .NumOperands: 3, .NumConds: 4 },
2638 {.AsmStrOffset: 6596, .AliasCondStart: 2742, .NumOperands: 3, .NumConds: 5 },
2639 {.AsmStrOffset: 7502, .AliasCondStart: 2747, .NumOperands: 3, .NumConds: 4 },
2640 {.AsmStrOffset: 6629, .AliasCondStart: 2751, .NumOperands: 3, .NumConds: 5 },
2641 {.AsmStrOffset: 7516, .AliasCondStart: 2756, .NumOperands: 3, .NumConds: 4 },
2642 {.AsmStrOffset: 6662, .AliasCondStart: 2760, .NumOperands: 3, .NumConds: 5 },
2643 {.AsmStrOffset: 7535, .AliasCondStart: 2765, .NumOperands: 3, .NumConds: 4 },
2644 {.AsmStrOffset: 6694, .AliasCondStart: 2769, .NumOperands: 3, .NumConds: 5 },
2645 {.AsmStrOffset: 7548, .AliasCondStart: 2774, .NumOperands: 3, .NumConds: 4 },
2646 {.AsmStrOffset: 6725, .AliasCondStart: 2778, .NumOperands: 3, .NumConds: 5 },
2647 {.AsmStrOffset: 7566, .AliasCondStart: 2783, .NumOperands: 3, .NumConds: 4 },
2648 {.AsmStrOffset: 6756, .AliasCondStart: 2787, .NumOperands: 3, .NumConds: 5 },
2649 {.AsmStrOffset: 7579, .AliasCondStart: 2792, .NumOperands: 3, .NumConds: 4 },
2650 {.AsmStrOffset: 6787, .AliasCondStart: 2796, .NumOperands: 3, .NumConds: 5 },
2651 // SP::TXCCrr - 641
2652 {.AsmStrOffset: 7105, .AliasCondStart: 2801, .NumOperands: 3, .NumConds: 4 },
2653 {.AsmStrOffset: 5833, .AliasCondStart: 2805, .NumOperands: 3, .NumConds: 5 },
2654 {.AsmStrOffset: 7117, .AliasCondStart: 2810, .NumOperands: 3, .NumConds: 4 },
2655 {.AsmStrOffset: 5862, .AliasCondStart: 2814, .NumOperands: 3, .NumConds: 5 },
2656 {.AsmStrOffset: 7134, .AliasCondStart: 2819, .NumOperands: 3, .NumConds: 4 },
2657 {.AsmStrOffset: 5891, .AliasCondStart: 2823, .NumOperands: 3, .NumConds: 5 },
2658 {.AsmStrOffset: 7146, .AliasCondStart: 2828, .NumOperands: 3, .NumConds: 4 },
2659 {.AsmStrOffset: 5920, .AliasCondStart: 2832, .NumOperands: 3, .NumConds: 5 },
2660 {.AsmStrOffset: 7163, .AliasCondStart: 2837, .NumOperands: 3, .NumConds: 4 },
2661 {.AsmStrOffset: 5950, .AliasCondStart: 2841, .NumOperands: 3, .NumConds: 5 },
2662 {.AsmStrOffset: 7176, .AliasCondStart: 2846, .NumOperands: 3, .NumConds: 4 },
2663 {.AsmStrOffset: 5981, .AliasCondStart: 2850, .NumOperands: 3, .NumConds: 5 },
2664 {.AsmStrOffset: 7194, .AliasCondStart: 2855, .NumOperands: 3, .NumConds: 4 },
2665 {.AsmStrOffset: 6011, .AliasCondStart: 2859, .NumOperands: 3, .NumConds: 5 },
2666 {.AsmStrOffset: 7206, .AliasCondStart: 2864, .NumOperands: 3, .NumConds: 4 },
2667 {.AsmStrOffset: 6040, .AliasCondStart: 2868, .NumOperands: 3, .NumConds: 5 },
2668 {.AsmStrOffset: 7223, .AliasCondStart: 2873, .NumOperands: 3, .NumConds: 4 },
2669 {.AsmStrOffset: 6069, .AliasCondStart: 2877, .NumOperands: 3, .NumConds: 5 },
2670 {.AsmStrOffset: 7235, .AliasCondStart: 2882, .NumOperands: 3, .NumConds: 4 },
2671 {.AsmStrOffset: 6098, .AliasCondStart: 2886, .NumOperands: 3, .NumConds: 5 },
2672 {.AsmStrOffset: 7252, .AliasCondStart: 2891, .NumOperands: 3, .NumConds: 4 },
2673 {.AsmStrOffset: 6128, .AliasCondStart: 2895, .NumOperands: 3, .NumConds: 5 },
2674 {.AsmStrOffset: 7265, .AliasCondStart: 2900, .NumOperands: 3, .NumConds: 4 },
2675 {.AsmStrOffset: 6159, .AliasCondStart: 2904, .NumOperands: 3, .NumConds: 5 },
2676 {.AsmStrOffset: 7283, .AliasCondStart: 2909, .NumOperands: 3, .NumConds: 4 },
2677 {.AsmStrOffset: 6190, .AliasCondStart: 2913, .NumOperands: 3, .NumConds: 5 },
2678 {.AsmStrOffset: 7296, .AliasCondStart: 2918, .NumOperands: 3, .NumConds: 4 },
2679 {.AsmStrOffset: 6221, .AliasCondStart: 2922, .NumOperands: 3, .NumConds: 5 },
2680 {.AsmStrOffset: 7314, .AliasCondStart: 2927, .NumOperands: 3, .NumConds: 4 },
2681 {.AsmStrOffset: 6251, .AliasCondStart: 2931, .NumOperands: 3, .NumConds: 5 },
2682 {.AsmStrOffset: 7326, .AliasCondStart: 2936, .NumOperands: 3, .NumConds: 4 },
2683 {.AsmStrOffset: 6280, .AliasCondStart: 2940, .NumOperands: 3, .NumConds: 5 },
2684 {.AsmStrOffset: 7343, .AliasCondStart: 2945, .NumOperands: 3, .NumConds: 4 },
2685 {.AsmStrOffset: 6310, .AliasCondStart: 2949, .NumOperands: 3, .NumConds: 5 },
2686 {.AsmStrOffset: 7356, .AliasCondStart: 2954, .NumOperands: 3, .NumConds: 4 },
2687 {.AsmStrOffset: 6341, .AliasCondStart: 2958, .NumOperands: 3, .NumConds: 5 },
2688 {.AsmStrOffset: 7374, .AliasCondStart: 2963, .NumOperands: 3, .NumConds: 4 },
2689 {.AsmStrOffset: 6373, .AliasCondStart: 2967, .NumOperands: 3, .NumConds: 5 },
2690 {.AsmStrOffset: 7388, .AliasCondStart: 2972, .NumOperands: 3, .NumConds: 4 },
2691 {.AsmStrOffset: 6406, .AliasCondStart: 2976, .NumOperands: 3, .NumConds: 5 },
2692 {.AsmStrOffset: 7407, .AliasCondStart: 2981, .NumOperands: 3, .NumConds: 4 },
2693 {.AsmStrOffset: 6438, .AliasCondStart: 2985, .NumOperands: 3, .NumConds: 5 },
2694 {.AsmStrOffset: 7420, .AliasCondStart: 2990, .NumOperands: 3, .NumConds: 4 },
2695 {.AsmStrOffset: 6469, .AliasCondStart: 2994, .NumOperands: 3, .NumConds: 5 },
2696 {.AsmStrOffset: 7438, .AliasCondStart: 2999, .NumOperands: 3, .NumConds: 4 },
2697 {.AsmStrOffset: 6500, .AliasCondStart: 3003, .NumOperands: 3, .NumConds: 5 },
2698 {.AsmStrOffset: 7451, .AliasCondStart: 3008, .NumOperands: 3, .NumConds: 4 },
2699 {.AsmStrOffset: 6531, .AliasCondStart: 3012, .NumOperands: 3, .NumConds: 5 },
2700 {.AsmStrOffset: 7469, .AliasCondStart: 3017, .NumOperands: 3, .NumConds: 4 },
2701 {.AsmStrOffset: 6563, .AliasCondStart: 3021, .NumOperands: 3, .NumConds: 5 },
2702 {.AsmStrOffset: 7483, .AliasCondStart: 3026, .NumOperands: 3, .NumConds: 4 },
2703 {.AsmStrOffset: 6596, .AliasCondStart: 3030, .NumOperands: 3, .NumConds: 5 },
2704 {.AsmStrOffset: 7502, .AliasCondStart: 3035, .NumOperands: 3, .NumConds: 4 },
2705 {.AsmStrOffset: 6629, .AliasCondStart: 3039, .NumOperands: 3, .NumConds: 5 },
2706 {.AsmStrOffset: 7516, .AliasCondStart: 3044, .NumOperands: 3, .NumConds: 4 },
2707 {.AsmStrOffset: 6662, .AliasCondStart: 3048, .NumOperands: 3, .NumConds: 5 },
2708 {.AsmStrOffset: 7535, .AliasCondStart: 3053, .NumOperands: 3, .NumConds: 4 },
2709 {.AsmStrOffset: 6694, .AliasCondStart: 3057, .NumOperands: 3, .NumConds: 5 },
2710 {.AsmStrOffset: 7548, .AliasCondStart: 3062, .NumOperands: 3, .NumConds: 4 },
2711 {.AsmStrOffset: 6725, .AliasCondStart: 3066, .NumOperands: 3, .NumConds: 5 },
2712 {.AsmStrOffset: 7566, .AliasCondStart: 3071, .NumOperands: 3, .NumConds: 4 },
2713 {.AsmStrOffset: 6756, .AliasCondStart: 3075, .NumOperands: 3, .NumConds: 5 },
2714 {.AsmStrOffset: 7579, .AliasCondStart: 3080, .NumOperands: 3, .NumConds: 4 },
2715 {.AsmStrOffset: 6787, .AliasCondStart: 3084, .NumOperands: 3, .NumConds: 5 },
2716 // SP::V9FCMPD - 705
2717 {.AsmStrOffset: 7597, .AliasCondStart: 3089, .NumOperands: 3, .NumConds: 3 },
2718 // SP::V9FCMPED - 706
2719 {.AsmStrOffset: 7610, .AliasCondStart: 3092, .NumOperands: 3, .NumConds: 3 },
2720 // SP::V9FCMPEQ - 707
2721 {.AsmStrOffset: 7624, .AliasCondStart: 3095, .NumOperands: 3, .NumConds: 3 },
2722 // SP::V9FCMPES - 708
2723 {.AsmStrOffset: 7638, .AliasCondStart: 3098, .NumOperands: 3, .NumConds: 3 },
2724 // SP::V9FCMPQ - 709
2725 {.AsmStrOffset: 7652, .AliasCondStart: 3101, .NumOperands: 3, .NumConds: 3 },
2726 // SP::V9FCMPS - 710
2727 {.AsmStrOffset: 7665, .AliasCondStart: 3104, .NumOperands: 3, .NumConds: 3 },
2728 // SP::V9FMOVD_FCC - 711
2729 {.AsmStrOffset: 7678, .AliasCondStart: 3107, .NumOperands: 5, .NumConds: 6 },
2730 {.AsmStrOffset: 7696, .AliasCondStart: 3113, .NumOperands: 5, .NumConds: 6 },
2731 {.AsmStrOffset: 7714, .AliasCondStart: 3119, .NumOperands: 5, .NumConds: 6 },
2732 {.AsmStrOffset: 7732, .AliasCondStart: 3125, .NumOperands: 5, .NumConds: 6 },
2733 {.AsmStrOffset: 7750, .AliasCondStart: 3131, .NumOperands: 5, .NumConds: 6 },
2734 {.AsmStrOffset: 7769, .AliasCondStart: 3137, .NumOperands: 5, .NumConds: 6 },
2735 {.AsmStrOffset: 7787, .AliasCondStart: 3143, .NumOperands: 5, .NumConds: 6 },
2736 {.AsmStrOffset: 7806, .AliasCondStart: 3149, .NumOperands: 5, .NumConds: 6 },
2737 {.AsmStrOffset: 7825, .AliasCondStart: 3155, .NumOperands: 5, .NumConds: 6 },
2738 {.AsmStrOffset: 7844, .AliasCondStart: 3161, .NumOperands: 5, .NumConds: 6 },
2739 {.AsmStrOffset: 7862, .AliasCondStart: 3167, .NumOperands: 5, .NumConds: 6 },
2740 {.AsmStrOffset: 7881, .AliasCondStart: 3173, .NumOperands: 5, .NumConds: 6 },
2741 {.AsmStrOffset: 7900, .AliasCondStart: 3179, .NumOperands: 5, .NumConds: 6 },
2742 {.AsmStrOffset: 7920, .AliasCondStart: 3185, .NumOperands: 5, .NumConds: 6 },
2743 {.AsmStrOffset: 7939, .AliasCondStart: 3191, .NumOperands: 5, .NumConds: 6 },
2744 {.AsmStrOffset: 7959, .AliasCondStart: 3197, .NumOperands: 5, .NumConds: 6 },
2745 // SP::V9FMOVQ_FCC - 727
2746 {.AsmStrOffset: 7977, .AliasCondStart: 3203, .NumOperands: 5, .NumConds: 6 },
2747 {.AsmStrOffset: 7995, .AliasCondStart: 3209, .NumOperands: 5, .NumConds: 6 },
2748 {.AsmStrOffset: 8013, .AliasCondStart: 3215, .NumOperands: 5, .NumConds: 6 },
2749 {.AsmStrOffset: 8031, .AliasCondStart: 3221, .NumOperands: 5, .NumConds: 6 },
2750 {.AsmStrOffset: 8049, .AliasCondStart: 3227, .NumOperands: 5, .NumConds: 6 },
2751 {.AsmStrOffset: 8068, .AliasCondStart: 3233, .NumOperands: 5, .NumConds: 6 },
2752 {.AsmStrOffset: 8086, .AliasCondStart: 3239, .NumOperands: 5, .NumConds: 6 },
2753 {.AsmStrOffset: 8105, .AliasCondStart: 3245, .NumOperands: 5, .NumConds: 6 },
2754 {.AsmStrOffset: 8124, .AliasCondStart: 3251, .NumOperands: 5, .NumConds: 6 },
2755 {.AsmStrOffset: 8143, .AliasCondStart: 3257, .NumOperands: 5, .NumConds: 6 },
2756 {.AsmStrOffset: 8161, .AliasCondStart: 3263, .NumOperands: 5, .NumConds: 6 },
2757 {.AsmStrOffset: 8180, .AliasCondStart: 3269, .NumOperands: 5, .NumConds: 6 },
2758 {.AsmStrOffset: 8199, .AliasCondStart: 3275, .NumOperands: 5, .NumConds: 6 },
2759 {.AsmStrOffset: 8219, .AliasCondStart: 3281, .NumOperands: 5, .NumConds: 6 },
2760 {.AsmStrOffset: 8238, .AliasCondStart: 3287, .NumOperands: 5, .NumConds: 6 },
2761 {.AsmStrOffset: 8258, .AliasCondStart: 3293, .NumOperands: 5, .NumConds: 6 },
2762 // SP::V9FMOVS_FCC - 743
2763 {.AsmStrOffset: 8276, .AliasCondStart: 3299, .NumOperands: 5, .NumConds: 6 },
2764 {.AsmStrOffset: 8294, .AliasCondStart: 3305, .NumOperands: 5, .NumConds: 6 },
2765 {.AsmStrOffset: 8312, .AliasCondStart: 3311, .NumOperands: 5, .NumConds: 6 },
2766 {.AsmStrOffset: 8330, .AliasCondStart: 3317, .NumOperands: 5, .NumConds: 6 },
2767 {.AsmStrOffset: 8348, .AliasCondStart: 3323, .NumOperands: 5, .NumConds: 6 },
2768 {.AsmStrOffset: 8367, .AliasCondStart: 3329, .NumOperands: 5, .NumConds: 6 },
2769 {.AsmStrOffset: 8385, .AliasCondStart: 3335, .NumOperands: 5, .NumConds: 6 },
2770 {.AsmStrOffset: 8404, .AliasCondStart: 3341, .NumOperands: 5, .NumConds: 6 },
2771 {.AsmStrOffset: 8423, .AliasCondStart: 3347, .NumOperands: 5, .NumConds: 6 },
2772 {.AsmStrOffset: 8442, .AliasCondStart: 3353, .NumOperands: 5, .NumConds: 6 },
2773 {.AsmStrOffset: 8460, .AliasCondStart: 3359, .NumOperands: 5, .NumConds: 6 },
2774 {.AsmStrOffset: 8479, .AliasCondStart: 3365, .NumOperands: 5, .NumConds: 6 },
2775 {.AsmStrOffset: 8498, .AliasCondStart: 3371, .NumOperands: 5, .NumConds: 6 },
2776 {.AsmStrOffset: 8518, .AliasCondStart: 3377, .NumOperands: 5, .NumConds: 6 },
2777 {.AsmStrOffset: 8537, .AliasCondStart: 3383, .NumOperands: 5, .NumConds: 6 },
2778 {.AsmStrOffset: 8557, .AliasCondStart: 3389, .NumOperands: 5, .NumConds: 6 },
2779 // SP::V9MOVFCCri - 759
2780 {.AsmStrOffset: 8575, .AliasCondStart: 3395, .NumOperands: 5, .NumConds: 6 },
2781 {.AsmStrOffset: 8591, .AliasCondStart: 3401, .NumOperands: 5, .NumConds: 6 },
2782 {.AsmStrOffset: 8607, .AliasCondStart: 3407, .NumOperands: 5, .NumConds: 6 },
2783 {.AsmStrOffset: 8623, .AliasCondStart: 3413, .NumOperands: 5, .NumConds: 6 },
2784 {.AsmStrOffset: 8639, .AliasCondStart: 3419, .NumOperands: 5, .NumConds: 6 },
2785 {.AsmStrOffset: 8656, .AliasCondStart: 3425, .NumOperands: 5, .NumConds: 6 },
2786 {.AsmStrOffset: 8672, .AliasCondStart: 3431, .NumOperands: 5, .NumConds: 6 },
2787 {.AsmStrOffset: 8689, .AliasCondStart: 3437, .NumOperands: 5, .NumConds: 6 },
2788 {.AsmStrOffset: 8706, .AliasCondStart: 3443, .NumOperands: 5, .NumConds: 6 },
2789 {.AsmStrOffset: 8723, .AliasCondStart: 3449, .NumOperands: 5, .NumConds: 6 },
2790 {.AsmStrOffset: 8739, .AliasCondStart: 3455, .NumOperands: 5, .NumConds: 6 },
2791 {.AsmStrOffset: 8756, .AliasCondStart: 3461, .NumOperands: 5, .NumConds: 6 },
2792 {.AsmStrOffset: 8773, .AliasCondStart: 3467, .NumOperands: 5, .NumConds: 6 },
2793 {.AsmStrOffset: 8791, .AliasCondStart: 3473, .NumOperands: 5, .NumConds: 6 },
2794 {.AsmStrOffset: 8808, .AliasCondStart: 3479, .NumOperands: 5, .NumConds: 6 },
2795 {.AsmStrOffset: 8826, .AliasCondStart: 3485, .NumOperands: 5, .NumConds: 6 },
2796 // SP::V9MOVFCCrr - 775
2797 {.AsmStrOffset: 8575, .AliasCondStart: 3491, .NumOperands: 5, .NumConds: 6 },
2798 {.AsmStrOffset: 8591, .AliasCondStart: 3497, .NumOperands: 5, .NumConds: 6 },
2799 {.AsmStrOffset: 8607, .AliasCondStart: 3503, .NumOperands: 5, .NumConds: 6 },
2800 {.AsmStrOffset: 8623, .AliasCondStart: 3509, .NumOperands: 5, .NumConds: 6 },
2801 {.AsmStrOffset: 8639, .AliasCondStart: 3515, .NumOperands: 5, .NumConds: 6 },
2802 {.AsmStrOffset: 8656, .AliasCondStart: 3521, .NumOperands: 5, .NumConds: 6 },
2803 {.AsmStrOffset: 8672, .AliasCondStart: 3527, .NumOperands: 5, .NumConds: 6 },
2804 {.AsmStrOffset: 8689, .AliasCondStart: 3533, .NumOperands: 5, .NumConds: 6 },
2805 {.AsmStrOffset: 8706, .AliasCondStart: 3539, .NumOperands: 5, .NumConds: 6 },
2806 {.AsmStrOffset: 8723, .AliasCondStart: 3545, .NumOperands: 5, .NumConds: 6 },
2807 {.AsmStrOffset: 8739, .AliasCondStart: 3551, .NumOperands: 5, .NumConds: 6 },
2808 {.AsmStrOffset: 8756, .AliasCondStart: 3557, .NumOperands: 5, .NumConds: 6 },
2809 {.AsmStrOffset: 8773, .AliasCondStart: 3563, .NumOperands: 5, .NumConds: 6 },
2810 {.AsmStrOffset: 8791, .AliasCondStart: 3569, .NumOperands: 5, .NumConds: 6 },
2811 {.AsmStrOffset: 8808, .AliasCondStart: 3575, .NumOperands: 5, .NumConds: 6 },
2812 {.AsmStrOffset: 8826, .AliasCondStart: 3581, .NumOperands: 5, .NumConds: 6 },
2813 // SP::WRASRri - 791
2814 {.AsmStrOffset: 8842, .AliasCondStart: 3587, .NumOperands: 3, .NumConds: 3 },
2815 // SP::WRASRrr - 792
2816 {.AsmStrOffset: 8842, .AliasCondStart: 3590, .NumOperands: 3, .NumConds: 4 },
2817 };
2818
2819 static const AliasPatternCond Conds[] = {
2820 // (BCOND brtarget:$imm, 8) - 0
2821 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2822 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2823 // (BCOND brtarget:$imm, 0) - 2
2824 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2825 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2826 // (BCOND brtarget:$imm, 9) - 4
2827 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2828 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2829 // (BCOND brtarget:$imm, 1) - 6
2830 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2831 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2832 // (BCOND brtarget:$imm, 10) - 8
2833 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2834 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2835 // (BCOND brtarget:$imm, 2) - 10
2836 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2837 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2838 // (BCOND brtarget:$imm, 11) - 12
2839 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2840 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2841 // (BCOND brtarget:$imm, 3) - 14
2842 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2843 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2844 // (BCOND brtarget:$imm, 12) - 16
2845 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2846 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2847 // (BCOND brtarget:$imm, 4) - 18
2848 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2849 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2850 // (BCOND brtarget:$imm, 13) - 20
2851 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2852 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2853 // (BCOND brtarget:$imm, 5) - 22
2854 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2855 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2856 // (BCOND brtarget:$imm, 14) - 24
2857 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2858 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2859 // (BCOND brtarget:$imm, 6) - 26
2860 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2861 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2862 // (BCOND brtarget:$imm, 15) - 28
2863 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2864 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2865 // (BCOND brtarget:$imm, 7) - 30
2866 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2867 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2868 // (BCONDA brtarget:$imm, 8) - 32
2869 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2870 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2871 // (BCONDA brtarget:$imm, 0) - 34
2872 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2873 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2874 // (BCONDA brtarget:$imm, 9) - 36
2875 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2876 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2877 // (BCONDA brtarget:$imm, 1) - 38
2878 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2879 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2880 // (BCONDA brtarget:$imm, 10) - 40
2881 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2882 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2883 // (BCONDA brtarget:$imm, 2) - 42
2884 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2885 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2886 // (BCONDA brtarget:$imm, 11) - 44
2887 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2888 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2889 // (BCONDA brtarget:$imm, 3) - 46
2890 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2891 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2892 // (BCONDA brtarget:$imm, 12) - 48
2893 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2894 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2895 // (BCONDA brtarget:$imm, 4) - 50
2896 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2897 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2898 // (BCONDA brtarget:$imm, 13) - 52
2899 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2900 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2901 // (BCONDA brtarget:$imm, 5) - 54
2902 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2903 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2904 // (BCONDA brtarget:$imm, 14) - 56
2905 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2906 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2907 // (BCONDA brtarget:$imm, 6) - 58
2908 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2909 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2910 // (BCONDA brtarget:$imm, 15) - 60
2911 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2912 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2913 // (BCONDA brtarget:$imm, 7) - 62
2914 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2915 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2916 // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc) - 64
2917 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2918 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2919 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2920 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2921 // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc) - 68
2922 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2923 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2924 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2925 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2926 // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc) - 72
2927 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2928 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2929 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2930 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2931 // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc) - 76
2932 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2933 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2934 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2935 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2936 // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc) - 80
2937 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2938 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2939 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2940 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2941 // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc) - 84
2942 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2943 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2944 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2945 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2946 // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc) - 88
2947 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2948 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2949 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2950 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2951 // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc) - 92
2952 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2953 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2954 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2955 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2956 // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc) - 96
2957 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2958 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2959 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2960 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2961 // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc) - 100
2962 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2963 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2964 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2965 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2966 // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc) - 104
2967 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2968 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2969 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2970 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2971 // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc) - 108
2972 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2973 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2974 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2975 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2976 // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc) - 112
2977 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2978 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2979 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2980 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2981 // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc) - 116
2982 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2983 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2984 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2985 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2986 // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc) - 120
2987 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2988 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2989 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2990 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2991 // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc) - 124
2992 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2993 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2994 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2995 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2996 // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc) - 128
2997 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2998 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2999 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3000 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3001 // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc) - 132
3002 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3003 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3004 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3005 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3006 // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc) - 136
3007 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3008 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3009 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3010 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3011 // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc) - 140
3012 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3013 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3014 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3015 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3016 // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc) - 144
3017 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3018 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3019 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3020 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3021 // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc) - 148
3022 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3023 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3024 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3025 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3026 // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc) - 152
3027 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3028 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3029 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3030 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3031 // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc) - 156
3032 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3033 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3034 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3035 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3036 // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc) - 160
3037 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3038 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3039 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3040 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3041 // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc) - 164
3042 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3043 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3044 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3045 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3046 // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc) - 168
3047 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3048 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3049 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3050 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3051 // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc) - 172
3052 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3053 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3054 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3055 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3056 // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc) - 176
3057 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3058 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3059 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3060 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3061 // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc) - 180
3062 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3063 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3064 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3065 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3066 // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc) - 184
3067 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3068 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3069 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3070 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3071 // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc) - 188
3072 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3073 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3074 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3075 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3076 // (BPICCANT brtarget:$imm, 8) - 192
3077 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3078 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3079 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3080 // (BPICCANT brtarget:$imm, 8) - 195
3081 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3082 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3083 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3084 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3085 // (BPICCANT brtarget:$imm, 0) - 199
3086 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3087 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3088 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3089 // (BPICCANT brtarget:$imm, 0) - 202
3090 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3091 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3092 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3093 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3094 // (BPICCANT brtarget:$imm, 9) - 206
3095 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3096 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3097 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3098 // (BPICCANT brtarget:$imm, 9) - 209
3099 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3100 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3101 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3102 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3103 // (BPICCANT brtarget:$imm, 1) - 213
3104 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3105 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3106 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3107 // (BPICCANT brtarget:$imm, 1) - 216
3108 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3109 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3110 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3111 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3112 // (BPICCANT brtarget:$imm, 10) - 220
3113 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3114 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3115 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3116 // (BPICCANT brtarget:$imm, 10) - 223
3117 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3118 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3119 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3120 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3121 // (BPICCANT brtarget:$imm, 2) - 227
3122 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3123 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3124 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3125 // (BPICCANT brtarget:$imm, 2) - 230
3126 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3127 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3128 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3129 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3130 // (BPICCANT brtarget:$imm, 11) - 234
3131 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3132 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3133 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3134 // (BPICCANT brtarget:$imm, 11) - 237
3135 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3136 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3137 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3138 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3139 // (BPICCANT brtarget:$imm, 3) - 241
3140 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3141 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3142 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3143 // (BPICCANT brtarget:$imm, 3) - 244
3144 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3145 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3146 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3147 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3148 // (BPICCANT brtarget:$imm, 12) - 248
3149 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3150 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3151 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3152 // (BPICCANT brtarget:$imm, 12) - 251
3153 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3154 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3155 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3156 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3157 // (BPICCANT brtarget:$imm, 4) - 255
3158 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3159 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3160 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3161 // (BPICCANT brtarget:$imm, 4) - 258
3162 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3163 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3164 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3165 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3166 // (BPICCANT brtarget:$imm, 13) - 262
3167 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3168 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3169 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3170 // (BPICCANT brtarget:$imm, 13) - 265
3171 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3172 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3173 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3174 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3175 // (BPICCANT brtarget:$imm, 5) - 269
3176 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3177 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3178 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3179 // (BPICCANT brtarget:$imm, 5) - 272
3180 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3181 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3182 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3183 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3184 // (BPICCANT brtarget:$imm, 14) - 276
3185 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3186 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3187 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3188 // (BPICCANT brtarget:$imm, 14) - 279
3189 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3190 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3191 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3192 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3193 // (BPICCANT brtarget:$imm, 6) - 283
3194 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3195 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3196 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3197 // (BPICCANT brtarget:$imm, 6) - 286
3198 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3199 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3200 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3201 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3202 // (BPICCANT brtarget:$imm, 15) - 290
3203 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3204 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3205 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3206 // (BPICCANT brtarget:$imm, 15) - 293
3207 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3208 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3209 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3210 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3211 // (BPICCANT brtarget:$imm, 7) - 297
3212 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3213 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3214 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3215 // (BPICCANT brtarget:$imm, 7) - 300
3216 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3217 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3218 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3219 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3220 // (BPICCNT brtarget:$imm, 8) - 304
3221 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3222 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3223 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3224 // (BPICCNT brtarget:$imm, 8) - 307
3225 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3226 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3227 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3228 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3229 // (BPICCNT brtarget:$imm, 0) - 311
3230 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3231 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3232 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3233 // (BPICCNT brtarget:$imm, 0) - 314
3234 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3235 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3236 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3237 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3238 // (BPICCNT brtarget:$imm, 9) - 318
3239 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3240 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3241 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3242 // (BPICCNT brtarget:$imm, 9) - 321
3243 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3244 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3245 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3246 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3247 // (BPICCNT brtarget:$imm, 1) - 325
3248 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3249 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3250 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3251 // (BPICCNT brtarget:$imm, 1) - 328
3252 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3253 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3254 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3255 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3256 // (BPICCNT brtarget:$imm, 10) - 332
3257 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3258 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3259 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3260 // (BPICCNT brtarget:$imm, 10) - 335
3261 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3262 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3263 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3264 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3265 // (BPICCNT brtarget:$imm, 2) - 339
3266 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3267 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3268 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3269 // (BPICCNT brtarget:$imm, 2) - 342
3270 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3271 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3272 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3273 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3274 // (BPICCNT brtarget:$imm, 11) - 346
3275 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3276 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3277 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3278 // (BPICCNT brtarget:$imm, 11) - 349
3279 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3280 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3281 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3282 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3283 // (BPICCNT brtarget:$imm, 3) - 353
3284 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3285 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3286 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3287 // (BPICCNT brtarget:$imm, 3) - 356
3288 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3289 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3290 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3291 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3292 // (BPICCNT brtarget:$imm, 12) - 360
3293 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3294 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3295 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3296 // (BPICCNT brtarget:$imm, 12) - 363
3297 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3298 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3299 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3300 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3301 // (BPICCNT brtarget:$imm, 4) - 367
3302 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3303 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3304 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3305 // (BPICCNT brtarget:$imm, 4) - 370
3306 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3307 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3308 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3309 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3310 // (BPICCNT brtarget:$imm, 13) - 374
3311 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3312 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3313 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3314 // (BPICCNT brtarget:$imm, 13) - 377
3315 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3316 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3317 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3318 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3319 // (BPICCNT brtarget:$imm, 5) - 381
3320 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3321 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3322 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3323 // (BPICCNT brtarget:$imm, 5) - 384
3324 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3325 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3326 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3327 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3328 // (BPICCNT brtarget:$imm, 14) - 388
3329 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3330 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3331 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3332 // (BPICCNT brtarget:$imm, 14) - 391
3333 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3334 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3335 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3336 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3337 // (BPICCNT brtarget:$imm, 6) - 395
3338 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3339 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3340 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3341 // (BPICCNT brtarget:$imm, 6) - 398
3342 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3343 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3344 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3345 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3346 // (BPICCNT brtarget:$imm, 15) - 402
3347 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3348 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3349 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3350 // (BPICCNT brtarget:$imm, 15) - 405
3351 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3352 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3353 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3354 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3355 // (BPICCNT brtarget:$imm, 7) - 409
3356 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3357 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3358 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3359 // (BPICCNT brtarget:$imm, 7) - 412
3360 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3361 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3362 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3363 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3364 // (BPRANT bprtarget16:$imm, 2, I64Regs:$rs1) - 416
3365 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3366 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3367 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3368 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3369 // (BPRANT bprtarget16:$imm, 3, I64Regs:$rs1) - 420
3370 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3371 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3372 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3373 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3374 // (BPRANT bprtarget16:$imm, 6, I64Regs:$rs1) - 424
3375 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3376 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3377 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3378 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3379 // (BPRANT bprtarget16:$imm, 7, I64Regs:$rs1) - 428
3380 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3381 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3382 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3383 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3384 // (BPRNT bprtarget16:$imm, 2, I64Regs:$rs1) - 432
3385 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3386 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3387 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3388 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3389 // (BPRNT bprtarget16:$imm, 3, I64Regs:$rs1) - 436
3390 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3391 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3392 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3393 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3394 // (BPRNT bprtarget16:$imm, 6, I64Regs:$rs1) - 440
3395 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3396 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3397 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3398 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3399 // (BPRNT bprtarget16:$imm, 7, I64Regs:$rs1) - 444
3400 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3401 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3402 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3403 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3404 // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 128) - 448
3405 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3406 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3407 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3408 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3409 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(128)},
3410 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3411 // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 136) - 454
3412 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3413 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3414 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3415 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3416 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(136)},
3417 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3418 // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 128) - 460
3419 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3420 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3421 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3422 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3423 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(128)},
3424 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3425 // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 136) - 466
3426 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3427 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3428 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3429 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3430 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(136)},
3431 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3432 // (CWBCONDri cbtarget:$imm, 9, IntRegs:$rs1, simm5Op:$simm5) - 472
3433 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3434 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3435 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3436 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3437 // (CWBCONDri cbtarget:$imm, 1, IntRegs:$rs1, simm5Op:$simm5) - 476
3438 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3439 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3440 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3441 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3442 // (CWBCONDri cbtarget:$imm, 10, IntRegs:$rs1, simm5Op:$simm5) - 480
3443 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3444 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3445 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3446 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3447 // (CWBCONDri cbtarget:$imm, 2, IntRegs:$rs1, simm5Op:$simm5) - 484
3448 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3449 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3450 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3451 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3452 // (CWBCONDri cbtarget:$imm, 11, IntRegs:$rs1, simm5Op:$simm5) - 488
3453 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3454 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3455 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3456 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3457 // (CWBCONDri cbtarget:$imm, 3, IntRegs:$rs1, simm5Op:$simm5) - 492
3458 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3459 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3460 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3461 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3462 // (CWBCONDri cbtarget:$imm, 12, IntRegs:$rs1, simm5Op:$simm5) - 496
3463 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3464 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3465 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3466 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3467 // (CWBCONDri cbtarget:$imm, 4, IntRegs:$rs1, simm5Op:$simm5) - 500
3468 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3469 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3470 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3471 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3472 // (CWBCONDri cbtarget:$imm, 13, IntRegs:$rs1, simm5Op:$simm5) - 504
3473 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3474 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3475 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3476 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3477 // (CWBCONDri cbtarget:$imm, 5, IntRegs:$rs1, simm5Op:$simm5) - 508
3478 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3479 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3480 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3481 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3482 // (CWBCONDri cbtarget:$imm, 14, IntRegs:$rs1, simm5Op:$simm5) - 512
3483 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3484 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3485 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3486 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3487 // (CWBCONDri cbtarget:$imm, 6, IntRegs:$rs1, simm5Op:$simm5) - 516
3488 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3489 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3490 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3491 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3492 // (CWBCONDri cbtarget:$imm, 15, IntRegs:$rs1, simm5Op:$simm5) - 520
3493 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3494 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3495 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3496 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3497 // (CWBCONDri cbtarget:$imm, 7, IntRegs:$rs1, simm5Op:$simm5) - 524
3498 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3499 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3500 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3501 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3502 // (CWBCONDrr cbtarget:$imm, 9, IntRegs:$rs1, IntRegs:$rs2) - 528
3503 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3504 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3505 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3506 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3507 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3508 // (CWBCONDrr cbtarget:$imm, 1, IntRegs:$rs1, IntRegs:$rs2) - 533
3509 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3510 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3511 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3512 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3513 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3514 // (CWBCONDrr cbtarget:$imm, 10, IntRegs:$rs1, IntRegs:$rs2) - 538
3515 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3516 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3517 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3518 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3519 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3520 // (CWBCONDrr cbtarget:$imm, 2, IntRegs:$rs1, IntRegs:$rs2) - 543
3521 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3522 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3523 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3524 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3525 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3526 // (CWBCONDrr cbtarget:$imm, 11, IntRegs:$rs1, IntRegs:$rs2) - 548
3527 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3528 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3529 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3530 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3531 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3532 // (CWBCONDrr cbtarget:$imm, 3, IntRegs:$rs1, IntRegs:$rs2) - 553
3533 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3534 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3535 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3536 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3537 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3538 // (CWBCONDrr cbtarget:$imm, 12, IntRegs:$rs1, IntRegs:$rs2) - 558
3539 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3540 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3541 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3542 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3543 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3544 // (CWBCONDrr cbtarget:$imm, 4, IntRegs:$rs1, IntRegs:$rs2) - 563
3545 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3546 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3547 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3548 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3549 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3550 // (CWBCONDrr cbtarget:$imm, 13, IntRegs:$rs1, IntRegs:$rs2) - 568
3551 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3552 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3553 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3554 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3555 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3556 // (CWBCONDrr cbtarget:$imm, 5, IntRegs:$rs1, IntRegs:$rs2) - 573
3557 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3558 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3559 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3560 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3561 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3562 // (CWBCONDrr cbtarget:$imm, 14, IntRegs:$rs1, IntRegs:$rs2) - 578
3563 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3564 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3565 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3566 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3567 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3568 // (CWBCONDrr cbtarget:$imm, 6, IntRegs:$rs1, IntRegs:$rs2) - 583
3569 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3570 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3571 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3572 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3573 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3574 // (CWBCONDrr cbtarget:$imm, 15, IntRegs:$rs1, IntRegs:$rs2) - 588
3575 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3576 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3577 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3578 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3579 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3580 // (CWBCONDrr cbtarget:$imm, 7, IntRegs:$rs1, IntRegs:$rs2) - 593
3581 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3582 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3583 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3584 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3585 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3586 // (CXBCONDri cbtarget:$imm, 9, IntRegs:$rs1, simm5Op:$simm5) - 598
3587 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3588 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3589 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3590 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3591 // (CXBCONDri cbtarget:$imm, 1, IntRegs:$rs1, simm5Op:$simm5) - 602
3592 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3593 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3594 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3595 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3596 // (CXBCONDri cbtarget:$imm, 10, IntRegs:$rs1, simm5Op:$simm5) - 606
3597 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3598 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3599 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3600 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3601 // (CXBCONDri cbtarget:$imm, 2, IntRegs:$rs1, simm5Op:$simm5) - 610
3602 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3603 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3604 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3605 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3606 // (CXBCONDri cbtarget:$imm, 11, IntRegs:$rs1, simm5Op:$simm5) - 614
3607 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3608 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3609 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3610 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3611 // (CXBCONDri cbtarget:$imm, 3, IntRegs:$rs1, simm5Op:$simm5) - 618
3612 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3613 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3614 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3615 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3616 // (CXBCONDri cbtarget:$imm, 12, IntRegs:$rs1, simm5Op:$simm5) - 622
3617 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3618 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3619 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3620 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3621 // (CXBCONDri cbtarget:$imm, 4, IntRegs:$rs1, simm5Op:$simm5) - 626
3622 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3623 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3624 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3625 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3626 // (CXBCONDri cbtarget:$imm, 13, IntRegs:$rs1, simm5Op:$simm5) - 630
3627 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3628 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3629 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3630 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3631 // (CXBCONDri cbtarget:$imm, 5, IntRegs:$rs1, simm5Op:$simm5) - 634
3632 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3633 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3634 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3635 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3636 // (CXBCONDri cbtarget:$imm, 14, IntRegs:$rs1, simm5Op:$simm5) - 638
3637 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3638 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3639 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3640 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3641 // (CXBCONDri cbtarget:$imm, 6, IntRegs:$rs1, simm5Op:$simm5) - 642
3642 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3643 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3644 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3645 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3646 // (CXBCONDri cbtarget:$imm, 15, IntRegs:$rs1, simm5Op:$simm5) - 646
3647 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3648 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3649 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3650 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3651 // (CXBCONDri cbtarget:$imm, 7, IntRegs:$rs1, simm5Op:$simm5) - 650
3652 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3653 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3654 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3655 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3656 // (CXBCONDrr cbtarget:$imm, 9, IntRegs:$rs1, IntRegs:$rs2) - 654
3657 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3658 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3659 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3660 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3661 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3662 // (CXBCONDrr cbtarget:$imm, 1, IntRegs:$rs1, IntRegs:$rs2) - 659
3663 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3664 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3665 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3666 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3667 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3668 // (CXBCONDrr cbtarget:$imm, 10, IntRegs:$rs1, IntRegs:$rs2) - 664
3669 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3670 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3671 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3672 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3673 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3674 // (CXBCONDrr cbtarget:$imm, 2, IntRegs:$rs1, IntRegs:$rs2) - 669
3675 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3676 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3677 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3678 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3679 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3680 // (CXBCONDrr cbtarget:$imm, 11, IntRegs:$rs1, IntRegs:$rs2) - 674
3681 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3682 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3683 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3684 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3685 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3686 // (CXBCONDrr cbtarget:$imm, 3, IntRegs:$rs1, IntRegs:$rs2) - 679
3687 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3688 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3689 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3690 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3691 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3692 // (CXBCONDrr cbtarget:$imm, 12, IntRegs:$rs1, IntRegs:$rs2) - 684
3693 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3694 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3695 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3696 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3697 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3698 // (CXBCONDrr cbtarget:$imm, 4, IntRegs:$rs1, IntRegs:$rs2) - 689
3699 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3700 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3701 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3702 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3703 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3704 // (CXBCONDrr cbtarget:$imm, 13, IntRegs:$rs1, IntRegs:$rs2) - 694
3705 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3706 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3707 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3708 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3709 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3710 // (CXBCONDrr cbtarget:$imm, 5, IntRegs:$rs1, IntRegs:$rs2) - 699
3711 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3712 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3713 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3714 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3715 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3716 // (CXBCONDrr cbtarget:$imm, 14, IntRegs:$rs1, IntRegs:$rs2) - 704
3717 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3718 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3719 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3720 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3721 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3722 // (CXBCONDrr cbtarget:$imm, 6, IntRegs:$rs1, IntRegs:$rs2) - 709
3723 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3724 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3725 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3726 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3727 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3728 // (CXBCONDrr cbtarget:$imm, 15, IntRegs:$rs1, IntRegs:$rs2) - 714
3729 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3730 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3731 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3732 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3733 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3734 // (CXBCONDrr cbtarget:$imm, 7, IntRegs:$rs1, IntRegs:$rs2) - 719
3735 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3736 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3737 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3738 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3739 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3740 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8) - 724
3741 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3742 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3743 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3744 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3745 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3746 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8) - 729
3747 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3748 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3749 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3750 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3751 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3752 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3753 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0) - 735
3754 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3755 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3756 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3757 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3758 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3759 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0) - 740
3760 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3761 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3762 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3763 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3764 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3765 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3766 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9) - 746
3767 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3768 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3769 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3770 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3771 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3772 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9) - 751
3773 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3774 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3775 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3776 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3777 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3778 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3779 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1) - 757
3780 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3781 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3782 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3783 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3784 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3785 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1) - 762
3786 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3787 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3788 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3789 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3790 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3791 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3792 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10) - 768
3793 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3794 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3795 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3796 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3797 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3798 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10) - 773
3799 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3800 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3801 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3802 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3803 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3804 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3805 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2) - 779
3806 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3807 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3808 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3809 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3810 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3811 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2) - 784
3812 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3813 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3814 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3815 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3816 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3817 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3818 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11) - 790
3819 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3820 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3821 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3822 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3823 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3824 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11) - 795
3825 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3826 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3827 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3828 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3829 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3830 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3831 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3) - 801
3832 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3833 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3834 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3835 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3836 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3837 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3) - 806
3838 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3839 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3840 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3841 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3842 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3843 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3844 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12) - 812
3845 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3846 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3847 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3848 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3849 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3850 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12) - 817
3851 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3852 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3853 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3854 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3855 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3856 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3857 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4) - 823
3858 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3859 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3860 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3861 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3862 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3863 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4) - 828
3864 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3865 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3866 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3867 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3868 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3869 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3870 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13) - 834
3871 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3872 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3873 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3874 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3875 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3876 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13) - 839
3877 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3878 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3879 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3880 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3881 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3882 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3883 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5) - 845
3884 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3885 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3886 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3887 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3888 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3889 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5) - 850
3890 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3891 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3892 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3893 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3894 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3895 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3896 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14) - 856
3897 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3898 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3899 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3900 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3901 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3902 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14) - 861
3903 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3904 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3905 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3906 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3907 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3908 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3909 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6) - 867
3910 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3911 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3912 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3913 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3914 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3915 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6) - 872
3916 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3917 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3918 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3919 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3920 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3921 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3922 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15) - 878
3923 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3924 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3925 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3926 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3927 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3928 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15) - 883
3929 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3930 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3931 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3932 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3933 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3934 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3935 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7) - 889
3936 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3937 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3938 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3939 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3940 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3941 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7) - 894
3942 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3943 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3944 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3945 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3946 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3947 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3948 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8) - 900
3949 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3950 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3951 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3952 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3953 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3954 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8) - 905
3955 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3956 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3957 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3958 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3959 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3960 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3961 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0) - 911
3962 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3963 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3964 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3965 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3966 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3967 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0) - 916
3968 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3969 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3970 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3971 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3972 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3973 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3974 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9) - 922
3975 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3976 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3977 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3978 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3979 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3980 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9) - 927
3981 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3982 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3983 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3984 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3985 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3986 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3987 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1) - 933
3988 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3989 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3990 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3991 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3992 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3993 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1) - 938
3994 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3995 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3996 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3997 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3998 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3999 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4000 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10) - 944
4001 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4002 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4003 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4004 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4005 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4006 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10) - 949
4007 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4008 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4009 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4010 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4011 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4012 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4013 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2) - 955
4014 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4015 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4016 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4017 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4018 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4019 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2) - 960
4020 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4021 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4022 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4023 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4024 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4025 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4026 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11) - 966
4027 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4028 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4029 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4030 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4031 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4032 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11) - 971
4033 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4034 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4035 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4036 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4037 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4038 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4039 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3) - 977
4040 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4041 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4042 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4043 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4044 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4045 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3) - 982
4046 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4047 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4048 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4049 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4050 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4051 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4052 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12) - 988
4053 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4054 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4055 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4056 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4057 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4058 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12) - 993
4059 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4060 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4061 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4062 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4063 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4064 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4065 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4) - 999
4066 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4067 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4068 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4069 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4070 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4071 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4) - 1004
4072 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4073 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4074 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4075 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4076 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4077 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4078 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13) - 1010
4079 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4080 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4081 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4082 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4083 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4084 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13) - 1015
4085 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4086 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4087 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4088 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4089 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4090 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4091 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5) - 1021
4092 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4093 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4094 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4095 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4096 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4097 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5) - 1026
4098 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4099 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4100 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4101 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4102 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4103 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4104 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14) - 1032
4105 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4106 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4107 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4108 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4109 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4110 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14) - 1037
4111 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4112 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4113 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4114 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4115 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4116 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4117 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6) - 1043
4118 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4119 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4120 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4121 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4122 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4123 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6) - 1048
4124 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4125 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4126 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4127 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4128 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4129 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4130 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15) - 1054
4131 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4132 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4133 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4134 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4135 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4136 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15) - 1059
4137 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4138 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4139 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4140 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4141 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4142 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4143 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7) - 1065
4144 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4145 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4146 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4147 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4148 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4149 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7) - 1070
4150 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4151 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4152 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4153 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4154 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4155 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4156 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 2) - 1076
4157 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4158 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4159 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4160 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4161 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4162 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4163 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 3) - 1082
4164 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4165 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4166 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4167 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4168 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4169 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4170 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 6) - 1088
4171 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4172 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4173 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4174 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4175 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4176 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4177 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 7) - 1094
4178 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4179 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4180 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4181 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4182 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4183 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4184 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 2) - 1100
4185 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4186 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4187 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4188 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4189 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4190 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4191 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 3) - 1106
4192 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4193 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4194 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4195 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4196 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4197 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4198 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 6) - 1112
4199 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4200 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4201 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4202 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4203 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4204 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4205 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 7) - 1118
4206 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4207 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4208 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4209 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4210 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4211 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4212 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 2) - 1124
4213 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4214 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4215 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4216 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4217 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4218 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4219 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 3) - 1130
4220 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4221 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4222 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4223 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4224 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4225 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4226 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 6) - 1136
4227 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4228 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4229 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4230 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4231 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4232 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4233 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 7) - 1142
4234 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4235 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4236 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4237 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4238 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4239 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4240 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8) - 1148
4241 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4242 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4243 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4244 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4245 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4246 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8) - 1153
4247 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4248 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4249 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4250 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4251 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4252 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4253 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0) - 1159
4254 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4255 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4256 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4257 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4258 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4259 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0) - 1164
4260 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4261 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4262 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4263 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4264 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4265 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4266 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9) - 1170
4267 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4268 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4269 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4270 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4271 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4272 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9) - 1175
4273 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4274 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4275 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4276 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4277 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4278 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4279 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1) - 1181
4280 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4281 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4282 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4283 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4284 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4285 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1) - 1186
4286 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4287 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4288 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4289 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4290 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4291 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4292 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10) - 1192
4293 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4294 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4295 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4296 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4297 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4298 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10) - 1197
4299 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4300 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4301 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4302 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4303 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4304 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4305 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2) - 1203
4306 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4307 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4308 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4309 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4310 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4311 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2) - 1208
4312 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4313 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4314 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4315 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4316 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4317 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4318 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11) - 1214
4319 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4320 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4321 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4322 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4323 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4324 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11) - 1219
4325 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4326 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4327 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4328 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4329 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4330 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4331 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3) - 1225
4332 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4333 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4334 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4335 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4336 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4337 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3) - 1230
4338 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4339 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4340 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4341 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4342 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4343 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4344 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12) - 1236
4345 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4346 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4347 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4348 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4349 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4350 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12) - 1241
4351 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4352 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4353 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4354 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4355 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4356 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4357 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4) - 1247
4358 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4359 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4360 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4361 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4362 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4363 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4) - 1252
4364 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4365 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4366 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4367 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4368 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4369 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4370 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13) - 1258
4371 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4372 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4373 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4374 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4375 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4376 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13) - 1263
4377 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4378 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4379 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4380 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4381 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4382 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4383 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5) - 1269
4384 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4385 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4386 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4387 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4388 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4389 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5) - 1274
4390 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4391 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4392 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4393 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4394 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4395 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4396 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14) - 1280
4397 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4398 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4399 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4400 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4401 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4402 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14) - 1285
4403 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4404 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4405 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4406 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4407 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4408 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4409 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6) - 1291
4410 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4411 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4412 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4413 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4414 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4415 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6) - 1296
4416 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4417 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4418 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4419 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4420 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4421 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4422 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15) - 1302
4423 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4424 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4425 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4426 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4427 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4428 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15) - 1307
4429 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4430 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4431 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4432 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4433 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4434 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4435 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7) - 1313
4436 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4437 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4438 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4439 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4440 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4441 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7) - 1318
4442 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4443 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4444 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4445 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4446 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4447 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4448 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8) - 1324
4449 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4450 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4451 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4452 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4453 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4454 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8) - 1329
4455 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4456 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4457 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4458 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4459 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4460 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4461 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0) - 1335
4462 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4463 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4464 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4465 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4466 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4467 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0) - 1340
4468 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4469 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4470 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4471 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4472 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4473 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4474 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9) - 1346
4475 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4476 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4477 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4478 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4479 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4480 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9) - 1351
4481 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4482 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4483 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4484 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4485 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4486 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4487 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1) - 1357
4488 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4489 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4490 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4491 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4492 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4493 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1) - 1362
4494 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4495 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4496 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4497 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4498 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4499 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4500 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10) - 1368
4501 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4502 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4503 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4504 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4505 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4506 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10) - 1373
4507 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4508 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4509 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4510 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4511 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4512 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4513 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2) - 1379
4514 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4515 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4516 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4517 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4518 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4519 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2) - 1384
4520 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4521 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4522 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4523 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4524 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4525 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4526 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11) - 1390
4527 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4528 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4529 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4530 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4531 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4532 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11) - 1395
4533 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4534 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4535 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4536 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4537 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4538 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4539 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3) - 1401
4540 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4541 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4542 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4543 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4544 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4545 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3) - 1406
4546 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4547 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4548 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4549 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4550 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4551 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4552 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12) - 1412
4553 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4554 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4555 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4556 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4557 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4558 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12) - 1417
4559 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4560 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4561 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4562 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4563 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4564 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4565 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4) - 1423
4566 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4567 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4568 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4569 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4570 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4571 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4) - 1428
4572 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4573 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4574 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4575 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4576 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4577 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4578 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13) - 1434
4579 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4580 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4581 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4582 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4583 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4584 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13) - 1439
4585 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4586 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4587 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4588 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4589 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4590 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4591 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5) - 1445
4592 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4593 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4594 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4595 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4596 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4597 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5) - 1450
4598 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4599 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4600 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4601 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4602 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4603 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4604 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14) - 1456
4605 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4606 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4607 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4608 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4609 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4610 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14) - 1461
4611 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4612 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4613 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4614 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4615 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4616 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4617 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6) - 1467
4618 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4619 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4620 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4621 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4622 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4623 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6) - 1472
4624 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4625 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4626 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4627 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4628 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4629 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4630 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15) - 1478
4631 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4632 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4633 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4634 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4635 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4636 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15) - 1483
4637 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4638 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4639 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4640 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4641 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4642 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4643 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7) - 1489
4644 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4645 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4646 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4647 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4648 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4649 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7) - 1494
4650 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4651 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4652 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4653 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4654 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4655 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4656 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1500
4657 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4658 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4659 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4660 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4661 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4662 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1505
4663 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4664 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4665 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4666 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4667 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4668 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4669 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1511
4670 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4671 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4672 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4673 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4674 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4675 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1516
4676 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4677 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4678 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4679 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4680 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4681 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4682 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1522
4683 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4684 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4685 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4686 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4687 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4688 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1527
4689 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4690 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4691 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4692 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4693 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4694 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4695 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1533
4696 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4697 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4698 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4699 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4700 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4701 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1538
4702 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4703 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4704 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4705 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4706 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4707 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4708 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1544
4709 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4710 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4711 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4712 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4713 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4714 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1549
4715 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4716 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4717 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4718 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4719 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4720 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4721 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1555
4722 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4723 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4724 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4725 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4726 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4727 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1560
4728 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4729 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4730 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4731 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4732 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4733 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4734 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1566
4735 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4736 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4737 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4738 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4739 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4740 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1571
4741 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4742 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4743 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4744 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4745 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4746 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4747 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1577
4748 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4749 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4750 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4751 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4752 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4753 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1582
4754 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4755 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4756 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4757 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4758 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4759 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4760 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1588
4761 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4762 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4763 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4764 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4765 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4766 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1593
4767 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4768 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4769 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4770 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4771 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4772 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4773 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1599
4774 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4775 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4776 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4777 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4778 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4779 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1604
4780 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4781 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4782 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4783 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4784 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4785 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4786 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1610
4787 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4788 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4789 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4790 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4791 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4792 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1615
4793 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4794 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4795 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4796 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4797 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4798 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4799 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1621
4800 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4801 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4802 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4803 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4804 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4805 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1626
4806 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4807 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4808 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4809 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4810 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4811 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4812 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1632
4813 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4814 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4815 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4816 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4817 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4818 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1637
4819 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4820 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4821 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4822 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4823 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4824 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4825 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1643
4826 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4827 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4828 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4829 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4830 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4831 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1648
4832 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4833 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4834 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4835 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4836 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4837 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4838 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1654
4839 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4840 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4841 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4842 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4843 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4844 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1659
4845 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4846 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4847 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4848 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4849 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4850 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4851 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1665
4852 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4853 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4854 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4855 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4856 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4857 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1670
4858 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4859 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4860 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4861 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4862 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4863 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4864 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 2) - 1676
4865 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4866 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4867 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4868 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4869 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4870 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4871 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 3) - 1682
4872 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4873 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4874 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4875 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4876 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4877 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4878 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 6) - 1688
4879 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4880 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4881 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4882 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4883 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4884 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4885 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 7) - 1694
4886 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4887 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4888 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4889 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4890 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4891 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4892 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 2) - 1700
4893 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4894 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4895 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4896 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4897 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4898 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4899 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 3) - 1706
4900 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4901 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4902 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4903 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4904 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4905 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4906 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 6) - 1712
4907 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4908 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4909 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4910 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4911 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4912 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4913 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 7) - 1718
4914 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4915 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4916 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4917 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4918 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4919 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4920 // (ORCCrr G0, IntRegs:$rs2, G0) - 1724
4921 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4922 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4923 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4924 // (ORri IntRegs:$rd, G0, simm13Op:$simm13) - 1727
4925 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4926 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4927 // (ORrr IntRegs:$rd, G0, IntRegs:$rs2) - 1729
4928 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4929 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4930 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4931 // (RESTORErr G0, G0, G0) - 1732
4932 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4933 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4934 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4935 // (RET 8) - 1735
4936 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4937 // (RETL 8) - 1736
4938 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4939 // (SAVErr G0, G0, G0) - 1737
4940 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4941 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4942 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4943 // (SUBCCri G0, IntRegs:$rs1, simm13Op:$imm) - 1740
4944 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4945 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4946 // (SUBCCrr G0, IntRegs:$rs1, IntRegs:$rs2) - 1742
4947 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4948 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4949 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4950 // (TICCri G0, i32imm:$imm, 8) - 1745
4951 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4952 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4953 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4954 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4955 // (TICCri G0, i32imm:$imm, 8) - 1749
4956 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4957 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4958 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4959 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4960 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4961 // (TICCri IntRegs:$rs1, i32imm:$imm, 8) - 1754
4962 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4963 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4964 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4965 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4966 // (TICCri IntRegs:$rs1, i32imm:$imm, 8) - 1758
4967 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4968 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4969 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4970 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4971 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4972 // (TICCri G0, i32imm:$imm, 0) - 1763
4973 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4974 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4975 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4976 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4977 // (TICCri G0, i32imm:$imm, 0) - 1767
4978 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4979 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4980 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4981 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4982 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4983 // (TICCri IntRegs:$rs1, i32imm:$imm, 0) - 1772
4984 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4985 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4986 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4987 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4988 // (TICCri IntRegs:$rs1, i32imm:$imm, 0) - 1776
4989 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4990 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4991 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4992 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4993 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4994 // (TICCri G0, i32imm:$imm, 9) - 1781
4995 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4996 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4997 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4998 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4999 // (TICCri G0, i32imm:$imm, 9) - 1785
5000 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5001 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5002 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5003 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5004 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5005 // (TICCri IntRegs:$rs1, i32imm:$imm, 9) - 1790
5006 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5007 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5008 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5009 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5010 // (TICCri IntRegs:$rs1, i32imm:$imm, 9) - 1794
5011 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5012 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5013 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5014 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5015 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5016 // (TICCri G0, i32imm:$imm, 1) - 1799
5017 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5018 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5019 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5020 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5021 // (TICCri G0, i32imm:$imm, 1) - 1803
5022 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5023 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5024 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5025 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5026 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5027 // (TICCri IntRegs:$rs1, i32imm:$imm, 1) - 1808
5028 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5029 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5030 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5031 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5032 // (TICCri IntRegs:$rs1, i32imm:$imm, 1) - 1812
5033 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5034 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5035 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5036 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5037 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5038 // (TICCri G0, i32imm:$imm, 10) - 1817
5039 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5040 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5041 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5042 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5043 // (TICCri G0, i32imm:$imm, 10) - 1821
5044 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5045 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5046 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5047 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5048 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5049 // (TICCri IntRegs:$rs1, i32imm:$imm, 10) - 1826
5050 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5051 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5052 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5053 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5054 // (TICCri IntRegs:$rs1, i32imm:$imm, 10) - 1830
5055 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5056 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5057 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5058 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5059 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5060 // (TICCri G0, i32imm:$imm, 2) - 1835
5061 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5062 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5063 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5064 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5065 // (TICCri G0, i32imm:$imm, 2) - 1839
5066 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5067 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5068 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5069 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5070 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5071 // (TICCri IntRegs:$rs1, i32imm:$imm, 2) - 1844
5072 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5073 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5074 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5075 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5076 // (TICCri IntRegs:$rs1, i32imm:$imm, 2) - 1848
5077 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5078 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5079 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5080 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5081 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5082 // (TICCri G0, i32imm:$imm, 11) - 1853
5083 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5084 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5085 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5086 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5087 // (TICCri G0, i32imm:$imm, 11) - 1857
5088 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5089 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5090 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5091 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5092 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5093 // (TICCri IntRegs:$rs1, i32imm:$imm, 11) - 1862
5094 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5095 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5096 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5097 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5098 // (TICCri IntRegs:$rs1, i32imm:$imm, 11) - 1866
5099 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5100 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5101 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5102 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5103 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5104 // (TICCri G0, i32imm:$imm, 3) - 1871
5105 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5106 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5107 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5108 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5109 // (TICCri G0, i32imm:$imm, 3) - 1875
5110 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5111 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5112 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5113 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5114 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5115 // (TICCri IntRegs:$rs1, i32imm:$imm, 3) - 1880
5116 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5117 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5118 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5119 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5120 // (TICCri IntRegs:$rs1, i32imm:$imm, 3) - 1884
5121 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5122 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5123 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5124 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5125 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5126 // (TICCri G0, i32imm:$imm, 12) - 1889
5127 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5128 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5129 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5130 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5131 // (TICCri G0, i32imm:$imm, 12) - 1893
5132 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5133 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5134 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5135 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5136 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5137 // (TICCri IntRegs:$rs1, i32imm:$imm, 12) - 1898
5138 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5139 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5140 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5141 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5142 // (TICCri IntRegs:$rs1, i32imm:$imm, 12) - 1902
5143 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5144 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5145 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5146 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5147 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5148 // (TICCri G0, i32imm:$imm, 4) - 1907
5149 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5150 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5151 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5152 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5153 // (TICCri G0, i32imm:$imm, 4) - 1911
5154 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5155 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5156 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5157 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5158 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5159 // (TICCri IntRegs:$rs1, i32imm:$imm, 4) - 1916
5160 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5161 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5162 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5163 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5164 // (TICCri IntRegs:$rs1, i32imm:$imm, 4) - 1920
5165 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5166 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5167 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5168 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5169 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5170 // (TICCri G0, i32imm:$imm, 13) - 1925
5171 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5172 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5173 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5174 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5175 // (TICCri G0, i32imm:$imm, 13) - 1929
5176 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5177 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5178 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5179 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5180 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5181 // (TICCri IntRegs:$rs1, i32imm:$imm, 13) - 1934
5182 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5183 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5184 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5185 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5186 // (TICCri IntRegs:$rs1, i32imm:$imm, 13) - 1938
5187 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5188 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5189 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5190 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5191 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5192 // (TICCri G0, i32imm:$imm, 5) - 1943
5193 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5194 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5195 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5196 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5197 // (TICCri G0, i32imm:$imm, 5) - 1947
5198 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5199 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5200 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5201 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5202 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5203 // (TICCri IntRegs:$rs1, i32imm:$imm, 5) - 1952
5204 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5205 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5206 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5207 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5208 // (TICCri IntRegs:$rs1, i32imm:$imm, 5) - 1956
5209 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5210 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5211 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5212 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5213 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5214 // (TICCri G0, i32imm:$imm, 14) - 1961
5215 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5216 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5217 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5218 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5219 // (TICCri G0, i32imm:$imm, 14) - 1965
5220 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5221 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5222 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5223 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5224 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5225 // (TICCri IntRegs:$rs1, i32imm:$imm, 14) - 1970
5226 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5227 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5228 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5229 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5230 // (TICCri IntRegs:$rs1, i32imm:$imm, 14) - 1974
5231 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5232 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5233 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5234 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5235 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5236 // (TICCri G0, i32imm:$imm, 6) - 1979
5237 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5238 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5239 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5240 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5241 // (TICCri G0, i32imm:$imm, 6) - 1983
5242 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5243 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5244 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5245 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5246 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5247 // (TICCri IntRegs:$rs1, i32imm:$imm, 6) - 1988
5248 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5249 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5250 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5251 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5252 // (TICCri IntRegs:$rs1, i32imm:$imm, 6) - 1992
5253 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5254 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5255 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5256 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5257 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5258 // (TICCri G0, i32imm:$imm, 15) - 1997
5259 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5260 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5261 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5262 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5263 // (TICCri G0, i32imm:$imm, 15) - 2001
5264 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5265 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5266 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5267 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5268 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5269 // (TICCri IntRegs:$rs1, i32imm:$imm, 15) - 2006
5270 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5271 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5272 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5273 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5274 // (TICCri IntRegs:$rs1, i32imm:$imm, 15) - 2010
5275 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5276 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5277 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5278 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5279 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5280 // (TICCri G0, i32imm:$imm, 7) - 2015
5281 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5282 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5283 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5284 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5285 // (TICCri G0, i32imm:$imm, 7) - 2019
5286 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5287 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5288 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5289 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5290 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5291 // (TICCri IntRegs:$rs1, i32imm:$imm, 7) - 2024
5292 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5293 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5294 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5295 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5296 // (TICCri IntRegs:$rs1, i32imm:$imm, 7) - 2028
5297 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5298 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5299 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5300 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5301 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5302 // (TICCrr G0, IntRegs:$rs2, 8) - 2033
5303 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5304 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5305 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5306 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5307 // (TICCrr G0, IntRegs:$rs2, 8) - 2037
5308 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5309 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5310 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5311 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5312 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5313 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2042
5314 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5315 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5316 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5317 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5318 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2046
5319 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5320 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5321 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5322 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5323 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5324 // (TICCrr G0, IntRegs:$rs2, 0) - 2051
5325 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5326 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5327 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5328 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5329 // (TICCrr G0, IntRegs:$rs2, 0) - 2055
5330 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5331 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5332 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5333 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5334 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5335 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2060
5336 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5337 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5338 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5339 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5340 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2064
5341 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5342 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5343 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5344 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5345 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5346 // (TICCrr G0, IntRegs:$rs2, 9) - 2069
5347 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5348 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5349 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5350 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5351 // (TICCrr G0, IntRegs:$rs2, 9) - 2073
5352 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5353 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5354 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5355 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5356 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5357 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2078
5358 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5359 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5360 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5361 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5362 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2082
5363 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5364 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5365 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5366 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5367 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5368 // (TICCrr G0, IntRegs:$rs2, 1) - 2087
5369 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5370 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5371 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5372 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5373 // (TICCrr G0, IntRegs:$rs2, 1) - 2091
5374 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5375 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5376 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5377 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5378 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5379 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2096
5380 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5381 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5382 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5383 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5384 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2100
5385 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5386 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5387 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5388 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5389 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5390 // (TICCrr G0, IntRegs:$rs2, 10) - 2105
5391 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5392 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5393 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5394 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5395 // (TICCrr G0, IntRegs:$rs2, 10) - 2109
5396 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5397 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5398 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5399 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5400 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5401 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2114
5402 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5403 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5404 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5405 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5406 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2118
5407 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5408 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5409 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5410 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5411 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5412 // (TICCrr G0, IntRegs:$rs2, 2) - 2123
5413 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5414 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5415 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5416 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5417 // (TICCrr G0, IntRegs:$rs2, 2) - 2127
5418 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5419 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5420 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5421 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5422 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5423 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2132
5424 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5425 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5426 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5427 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5428 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2136
5429 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5430 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5431 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5432 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5433 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5434 // (TICCrr G0, IntRegs:$rs2, 11) - 2141
5435 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5436 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5437 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5438 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5439 // (TICCrr G0, IntRegs:$rs2, 11) - 2145
5440 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5441 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5442 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5443 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5444 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5445 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2150
5446 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5447 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5448 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5449 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5450 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2154
5451 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5452 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5453 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5454 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5455 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5456 // (TICCrr G0, IntRegs:$rs2, 3) - 2159
5457 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5458 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5459 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5460 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5461 // (TICCrr G0, IntRegs:$rs2, 3) - 2163
5462 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5463 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5464 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5465 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5466 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5467 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2168
5468 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5469 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5470 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5471 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5472 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2172
5473 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5474 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5475 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5476 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5477 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5478 // (TICCrr G0, IntRegs:$rs2, 12) - 2177
5479 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5480 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5481 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5482 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5483 // (TICCrr G0, IntRegs:$rs2, 12) - 2181
5484 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5485 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5486 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5487 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5488 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5489 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2186
5490 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5491 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5492 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5493 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5494 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2190
5495 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5496 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5497 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5498 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5499 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5500 // (TICCrr G0, IntRegs:$rs2, 4) - 2195
5501 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5502 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5503 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5504 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5505 // (TICCrr G0, IntRegs:$rs2, 4) - 2199
5506 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5507 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5508 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5509 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5510 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5511 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2204
5512 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5513 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5514 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5515 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5516 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2208
5517 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5518 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5519 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5520 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5521 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5522 // (TICCrr G0, IntRegs:$rs2, 13) - 2213
5523 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5524 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5525 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5526 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5527 // (TICCrr G0, IntRegs:$rs2, 13) - 2217
5528 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5529 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5530 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5531 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5532 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5533 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2222
5534 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5535 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5536 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5537 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5538 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2226
5539 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5540 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5541 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5542 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5543 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5544 // (TICCrr G0, IntRegs:$rs2, 5) - 2231
5545 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5546 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5547 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5548 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5549 // (TICCrr G0, IntRegs:$rs2, 5) - 2235
5550 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5551 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5552 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5553 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5554 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5555 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 2240
5556 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5557 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5558 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5559 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5560 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 2244
5561 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5562 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5563 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5564 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5565 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5566 // (TICCrr G0, IntRegs:$rs2, 14) - 2249
5567 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5568 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5569 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5570 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5571 // (TICCrr G0, IntRegs:$rs2, 14) - 2253
5572 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5573 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5574 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5575 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5576 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5577 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 2258
5578 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5579 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5580 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5581 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5582 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 2262
5583 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5584 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5585 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5586 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5587 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5588 // (TICCrr G0, IntRegs:$rs2, 6) - 2267
5589 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5590 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5591 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5592 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5593 // (TICCrr G0, IntRegs:$rs2, 6) - 2271
5594 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5595 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5596 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5597 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5598 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5599 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 2276
5600 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5601 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5602 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5603 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5604 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 2280
5605 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5606 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5607 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5608 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5609 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5610 // (TICCrr G0, IntRegs:$rs2, 15) - 2285
5611 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5612 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5613 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5614 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5615 // (TICCrr G0, IntRegs:$rs2, 15) - 2289
5616 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5617 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5618 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5619 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5620 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5621 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 2294
5622 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5623 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5624 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5625 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5626 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 2298
5627 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5628 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5629 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5630 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5631 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5632 // (TICCrr G0, IntRegs:$rs2, 7) - 2303
5633 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5634 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5635 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5636 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5637 // (TICCrr G0, IntRegs:$rs2, 7) - 2307
5638 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5639 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5640 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5641 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5642 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5643 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 2312
5644 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5645 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5646 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5647 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5648 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 2316
5649 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5650 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5651 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5652 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5653 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5654 // (TRAPri G0, i32imm:$imm, 8) - 2321
5655 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5656 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5657 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5658 // (TRAPri IntRegs:$rs1, i32imm:$imm, 8) - 2324
5659 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5660 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5661 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5662 // (TRAPri G0, i32imm:$imm, 0) - 2327
5663 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5664 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5665 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5666 // (TRAPri IntRegs:$rs1, i32imm:$imm, 0) - 2330
5667 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5668 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5669 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5670 // (TRAPri G0, i32imm:$imm, 9) - 2333
5671 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5672 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5673 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5674 // (TRAPri IntRegs:$rs1, i32imm:$imm, 9) - 2336
5675 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5676 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5677 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5678 // (TRAPri G0, i32imm:$imm, 1) - 2339
5679 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5680 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5681 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5682 // (TRAPri IntRegs:$rs1, i32imm:$imm, 1) - 2342
5683 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5684 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5685 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5686 // (TRAPri G0, i32imm:$imm, 10) - 2345
5687 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5688 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5689 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5690 // (TRAPri IntRegs:$rs1, i32imm:$imm, 10) - 2348
5691 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5692 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5693 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5694 // (TRAPri G0, i32imm:$imm, 2) - 2351
5695 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5696 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5697 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5698 // (TRAPri IntRegs:$rs1, i32imm:$imm, 2) - 2354
5699 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5700 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5701 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5702 // (TRAPri G0, i32imm:$imm, 11) - 2357
5703 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5704 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5705 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5706 // (TRAPri IntRegs:$rs1, i32imm:$imm, 11) - 2360
5707 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5708 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5709 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5710 // (TRAPri G0, i32imm:$imm, 3) - 2363
5711 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5712 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5713 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5714 // (TRAPri IntRegs:$rs1, i32imm:$imm, 3) - 2366
5715 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5716 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5717 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5718 // (TRAPri G0, i32imm:$imm, 12) - 2369
5719 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5720 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5721 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5722 // (TRAPri IntRegs:$rs1, i32imm:$imm, 12) - 2372
5723 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5724 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5725 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5726 // (TRAPri G0, i32imm:$imm, 4) - 2375
5727 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5728 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5729 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5730 // (TRAPri IntRegs:$rs1, i32imm:$imm, 4) - 2378
5731 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5732 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5733 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5734 // (TRAPri G0, i32imm:$imm, 13) - 2381
5735 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5736 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5737 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5738 // (TRAPri IntRegs:$rs1, i32imm:$imm, 13) - 2384
5739 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5740 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5741 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5742 // (TRAPri G0, i32imm:$imm, 5) - 2387
5743 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5744 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5745 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5746 // (TRAPri IntRegs:$rs1, i32imm:$imm, 5) - 2390
5747 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5748 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5749 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5750 // (TRAPri G0, i32imm:$imm, 14) - 2393
5751 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5752 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5753 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5754 // (TRAPri IntRegs:$rs1, i32imm:$imm, 14) - 2396
5755 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5756 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5757 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5758 // (TRAPri G0, i32imm:$imm, 6) - 2399
5759 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5760 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5761 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5762 // (TRAPri IntRegs:$rs1, i32imm:$imm, 6) - 2402
5763 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5764 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5765 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5766 // (TRAPri G0, i32imm:$imm, 15) - 2405
5767 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5768 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5769 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5770 // (TRAPri IntRegs:$rs1, i32imm:$imm, 15) - 2408
5771 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5772 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5773 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5774 // (TRAPri G0, i32imm:$imm, 7) - 2411
5775 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5776 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5777 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5778 // (TRAPri IntRegs:$rs1, i32imm:$imm, 7) - 2414
5779 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5780 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5781 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5782 // (TRAPrr G0, IntRegs:$rs1, 8) - 2417
5783 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5784 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5785 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5786 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2420
5787 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5788 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5789 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5790 // (TRAPrr G0, IntRegs:$rs1, 0) - 2423
5791 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5792 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5793 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5794 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2426
5795 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5796 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5797 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5798 // (TRAPrr G0, IntRegs:$rs1, 9) - 2429
5799 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5800 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5801 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5802 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2432
5803 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5804 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5805 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5806 // (TRAPrr G0, IntRegs:$rs1, 1) - 2435
5807 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5808 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5809 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5810 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2438
5811 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5812 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5813 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5814 // (TRAPrr G0, IntRegs:$rs1, 10) - 2441
5815 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5816 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5817 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5818 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2444
5819 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5820 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5821 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5822 // (TRAPrr G0, IntRegs:$rs1, 2) - 2447
5823 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5824 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5825 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5826 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2450
5827 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5828 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5829 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5830 // (TRAPrr G0, IntRegs:$rs1, 11) - 2453
5831 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5832 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5833 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5834 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2456
5835 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5836 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5837 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5838 // (TRAPrr G0, IntRegs:$rs1, 3) - 2459
5839 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5840 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5841 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5842 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2462
5843 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5844 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5845 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5846 // (TRAPrr G0, IntRegs:$rs1, 12) - 2465
5847 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5848 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5849 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5850 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2468
5851 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5852 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5853 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5854 // (TRAPrr G0, IntRegs:$rs1, 4) - 2471
5855 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5856 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5857 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5858 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2474
5859 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5860 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5861 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5862 // (TRAPrr G0, IntRegs:$rs1, 13) - 2477
5863 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5864 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5865 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5866 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2480
5867 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5868 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5869 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5870 // (TRAPrr G0, IntRegs:$rs1, 5) - 2483
5871 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5872 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5873 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5874 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 5) - 2486
5875 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5876 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5877 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5878 // (TRAPrr G0, IntRegs:$rs1, 14) - 2489
5879 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5880 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5881 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5882 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 14) - 2492
5883 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5884 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5885 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5886 // (TRAPrr G0, IntRegs:$rs1, 6) - 2495
5887 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5888 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5889 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5890 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 6) - 2498
5891 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5892 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5893 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5894 // (TRAPrr G0, IntRegs:$rs1, 15) - 2501
5895 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5896 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5897 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5898 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 15) - 2504
5899 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5900 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5901 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5902 // (TRAPrr G0, IntRegs:$rs1, 7) - 2507
5903 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5904 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5905 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5906 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 7) - 2510
5907 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5908 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5909 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5910 // (TXCCri G0, i32imm:$imm, 8) - 2513
5911 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5912 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5913 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5914 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5915 // (TXCCri G0, i32imm:$imm, 8) - 2517
5916 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5917 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5918 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5919 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5920 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5921 // (TXCCri IntRegs:$rs1, i32imm:$imm, 8) - 2522
5922 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5923 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5924 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5925 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5926 // (TXCCri IntRegs:$rs1, i32imm:$imm, 8) - 2526
5927 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5928 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5929 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5930 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5931 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5932 // (TXCCri G0, i32imm:$imm, 0) - 2531
5933 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5934 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5935 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5936 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5937 // (TXCCri G0, i32imm:$imm, 0) - 2535
5938 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5939 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5940 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5941 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5942 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5943 // (TXCCri IntRegs:$rs1, i32imm:$imm, 0) - 2540
5944 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5945 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5946 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5947 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5948 // (TXCCri IntRegs:$rs1, i32imm:$imm, 0) - 2544
5949 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5950 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5951 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5952 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5953 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5954 // (TXCCri G0, i32imm:$imm, 9) - 2549
5955 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5956 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5957 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5958 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5959 // (TXCCri G0, i32imm:$imm, 9) - 2553
5960 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5961 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5962 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5963 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5964 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5965 // (TXCCri IntRegs:$rs1, i32imm:$imm, 9) - 2558
5966 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5967 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5968 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5969 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5970 // (TXCCri IntRegs:$rs1, i32imm:$imm, 9) - 2562
5971 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5972 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5973 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5974 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5975 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5976 // (TXCCri G0, i32imm:$imm, 1) - 2567
5977 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5978 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5979 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5980 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5981 // (TXCCri G0, i32imm:$imm, 1) - 2571
5982 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5983 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5984 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5985 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5986 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5987 // (TXCCri IntRegs:$rs1, i32imm:$imm, 1) - 2576
5988 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5989 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5990 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5991 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5992 // (TXCCri IntRegs:$rs1, i32imm:$imm, 1) - 2580
5993 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5994 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5995 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5996 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5997 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5998 // (TXCCri G0, i32imm:$imm, 10) - 2585
5999 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6000 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6001 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6002 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6003 // (TXCCri G0, i32imm:$imm, 10) - 2589
6004 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6005 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6006 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6007 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6008 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6009 // (TXCCri IntRegs:$rs1, i32imm:$imm, 10) - 2594
6010 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6011 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6012 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6013 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6014 // (TXCCri IntRegs:$rs1, i32imm:$imm, 10) - 2598
6015 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6016 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6017 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6018 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6019 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6020 // (TXCCri G0, i32imm:$imm, 2) - 2603
6021 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6022 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6023 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6024 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6025 // (TXCCri G0, i32imm:$imm, 2) - 2607
6026 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6027 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6028 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6029 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6030 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6031 // (TXCCri IntRegs:$rs1, i32imm:$imm, 2) - 2612
6032 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6033 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6034 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6035 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6036 // (TXCCri IntRegs:$rs1, i32imm:$imm, 2) - 2616
6037 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6038 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6039 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6040 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6041 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6042 // (TXCCri G0, i32imm:$imm, 11) - 2621
6043 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6044 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6045 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6046 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6047 // (TXCCri G0, i32imm:$imm, 11) - 2625
6048 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6049 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6050 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6051 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6052 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6053 // (TXCCri IntRegs:$rs1, i32imm:$imm, 11) - 2630
6054 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6055 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6056 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6057 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6058 // (TXCCri IntRegs:$rs1, i32imm:$imm, 11) - 2634
6059 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6060 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6061 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6062 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6063 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6064 // (TXCCri G0, i32imm:$imm, 3) - 2639
6065 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6066 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6067 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6068 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6069 // (TXCCri G0, i32imm:$imm, 3) - 2643
6070 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6071 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6072 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6073 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6074 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6075 // (TXCCri IntRegs:$rs1, i32imm:$imm, 3) - 2648
6076 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6077 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6078 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6079 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6080 // (TXCCri IntRegs:$rs1, i32imm:$imm, 3) - 2652
6081 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6082 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6083 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6084 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6085 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6086 // (TXCCri G0, i32imm:$imm, 12) - 2657
6087 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6088 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6089 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6090 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6091 // (TXCCri G0, i32imm:$imm, 12) - 2661
6092 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6093 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6094 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6095 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6096 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6097 // (TXCCri IntRegs:$rs1, i32imm:$imm, 12) - 2666
6098 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6099 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6100 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6101 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6102 // (TXCCri IntRegs:$rs1, i32imm:$imm, 12) - 2670
6103 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6104 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6105 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6106 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6107 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6108 // (TXCCri G0, i32imm:$imm, 4) - 2675
6109 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6110 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6111 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6112 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6113 // (TXCCri G0, i32imm:$imm, 4) - 2679
6114 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6115 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6116 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6117 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6118 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6119 // (TXCCri IntRegs:$rs1, i32imm:$imm, 4) - 2684
6120 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6121 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6122 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6123 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6124 // (TXCCri IntRegs:$rs1, i32imm:$imm, 4) - 2688
6125 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6126 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6127 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6128 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6129 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6130 // (TXCCri G0, i32imm:$imm, 13) - 2693
6131 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6132 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6133 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6134 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6135 // (TXCCri G0, i32imm:$imm, 13) - 2697
6136 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6137 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6138 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6139 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6140 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6141 // (TXCCri IntRegs:$rs1, i32imm:$imm, 13) - 2702
6142 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6143 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6144 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6145 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6146 // (TXCCri IntRegs:$rs1, i32imm:$imm, 13) - 2706
6147 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6148 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6149 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6150 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6151 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6152 // (TXCCri G0, i32imm:$imm, 5) - 2711
6153 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6154 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6155 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6156 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6157 // (TXCCri G0, i32imm:$imm, 5) - 2715
6158 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6159 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6160 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6161 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6162 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6163 // (TXCCri IntRegs:$rs1, i32imm:$imm, 5) - 2720
6164 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6165 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6166 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6167 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6168 // (TXCCri IntRegs:$rs1, i32imm:$imm, 5) - 2724
6169 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6170 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6171 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6172 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6173 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6174 // (TXCCri G0, i32imm:$imm, 14) - 2729
6175 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6176 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6177 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6178 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6179 // (TXCCri G0, i32imm:$imm, 14) - 2733
6180 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6181 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6182 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6183 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6184 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6185 // (TXCCri IntRegs:$rs1, i32imm:$imm, 14) - 2738
6186 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6187 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6188 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6189 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6190 // (TXCCri IntRegs:$rs1, i32imm:$imm, 14) - 2742
6191 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6192 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6193 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6194 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6195 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6196 // (TXCCri G0, i32imm:$imm, 6) - 2747
6197 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6198 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6199 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6200 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6201 // (TXCCri G0, i32imm:$imm, 6) - 2751
6202 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6203 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6204 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6205 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6206 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6207 // (TXCCri IntRegs:$rs1, i32imm:$imm, 6) - 2756
6208 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6209 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6210 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6211 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6212 // (TXCCri IntRegs:$rs1, i32imm:$imm, 6) - 2760
6213 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6214 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6215 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6216 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6217 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6218 // (TXCCri G0, i32imm:$imm, 15) - 2765
6219 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6220 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6221 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6222 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6223 // (TXCCri G0, i32imm:$imm, 15) - 2769
6224 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6225 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6226 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6227 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6228 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6229 // (TXCCri IntRegs:$rs1, i32imm:$imm, 15) - 2774
6230 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6231 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6232 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6233 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6234 // (TXCCri IntRegs:$rs1, i32imm:$imm, 15) - 2778
6235 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6236 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6237 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6238 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6239 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6240 // (TXCCri G0, i32imm:$imm, 7) - 2783
6241 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6242 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6243 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6244 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6245 // (TXCCri G0, i32imm:$imm, 7) - 2787
6246 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6247 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6248 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6249 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6250 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6251 // (TXCCri IntRegs:$rs1, i32imm:$imm, 7) - 2792
6252 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6253 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6254 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6255 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6256 // (TXCCri IntRegs:$rs1, i32imm:$imm, 7) - 2796
6257 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6258 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6259 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6260 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6261 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6262 // (TXCCrr G0, IntRegs:$rs2, 8) - 2801
6263 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6264 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6265 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6266 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6267 // (TXCCrr G0, IntRegs:$rs2, 8) - 2805
6268 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6269 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6270 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6271 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6272 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6273 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2810
6274 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6275 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6276 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6277 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6278 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2814
6279 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6280 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6281 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6282 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6283 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6284 // (TXCCrr G0, IntRegs:$rs2, 0) - 2819
6285 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6286 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6287 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6288 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6289 // (TXCCrr G0, IntRegs:$rs2, 0) - 2823
6290 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6291 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6292 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6293 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6294 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6295 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2828
6296 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6297 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6298 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6299 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6300 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2832
6301 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6302 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6303 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6304 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6305 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6306 // (TXCCrr G0, IntRegs:$rs2, 9) - 2837
6307 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6308 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6309 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6310 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6311 // (TXCCrr G0, IntRegs:$rs2, 9) - 2841
6312 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6313 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6314 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6315 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6316 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6317 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2846
6318 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6319 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6320 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6321 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6322 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2850
6323 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6324 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6325 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6326 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6327 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6328 // (TXCCrr G0, IntRegs:$rs2, 1) - 2855
6329 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6330 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6331 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6332 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6333 // (TXCCrr G0, IntRegs:$rs2, 1) - 2859
6334 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6335 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6336 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6337 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6338 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6339 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2864
6340 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6341 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6342 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6343 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6344 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2868
6345 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6346 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6347 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6348 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6349 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6350 // (TXCCrr G0, IntRegs:$rs2, 10) - 2873
6351 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6352 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6353 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6354 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6355 // (TXCCrr G0, IntRegs:$rs2, 10) - 2877
6356 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6357 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6358 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6359 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6360 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6361 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2882
6362 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6363 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6364 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6365 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6366 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2886
6367 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6368 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6369 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6370 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6371 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6372 // (TXCCrr G0, IntRegs:$rs2, 2) - 2891
6373 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6374 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6375 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6376 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6377 // (TXCCrr G0, IntRegs:$rs2, 2) - 2895
6378 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6379 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6380 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6381 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6382 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6383 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2900
6384 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6385 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6386 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6387 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6388 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2904
6389 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6390 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6391 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6392 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6393 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6394 // (TXCCrr G0, IntRegs:$rs2, 11) - 2909
6395 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6396 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6397 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6398 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6399 // (TXCCrr G0, IntRegs:$rs2, 11) - 2913
6400 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6401 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6402 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6403 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6404 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6405 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2918
6406 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6407 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6408 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6409 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6410 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2922
6411 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6412 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6413 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6414 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6415 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6416 // (TXCCrr G0, IntRegs:$rs2, 3) - 2927
6417 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6418 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6419 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6420 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6421 // (TXCCrr G0, IntRegs:$rs2, 3) - 2931
6422 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6423 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6424 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6425 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6426 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6427 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2936
6428 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6429 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6430 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6431 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6432 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2940
6433 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6434 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6435 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6436 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6437 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6438 // (TXCCrr G0, IntRegs:$rs2, 12) - 2945
6439 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6440 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6441 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6442 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6443 // (TXCCrr G0, IntRegs:$rs2, 12) - 2949
6444 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6445 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6446 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6447 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6448 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6449 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2954
6450 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6451 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6452 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6453 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6454 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2958
6455 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6456 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6457 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6458 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6459 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6460 // (TXCCrr G0, IntRegs:$rs2, 4) - 2963
6461 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6462 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6463 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6464 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6465 // (TXCCrr G0, IntRegs:$rs2, 4) - 2967
6466 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6467 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6468 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6469 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6470 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6471 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2972
6472 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6473 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6474 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6475 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6476 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2976
6477 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6478 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6479 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6480 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6481 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6482 // (TXCCrr G0, IntRegs:$rs2, 13) - 2981
6483 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6484 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6485 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6486 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6487 // (TXCCrr G0, IntRegs:$rs2, 13) - 2985
6488 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6489 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6490 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6491 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6492 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6493 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2990
6494 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6495 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6496 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6497 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6498 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2994
6499 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6500 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6501 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6502 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6503 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6504 // (TXCCrr G0, IntRegs:$rs2, 5) - 2999
6505 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6506 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6507 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6508 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6509 // (TXCCrr G0, IntRegs:$rs2, 5) - 3003
6510 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6511 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6512 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6513 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6514 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6515 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 3008
6516 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6517 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6518 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6519 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6520 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 3012
6521 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6522 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6523 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6524 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6525 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6526 // (TXCCrr G0, IntRegs:$rs2, 14) - 3017
6527 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6528 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6529 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6530 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6531 // (TXCCrr G0, IntRegs:$rs2, 14) - 3021
6532 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6533 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6534 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6535 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6536 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6537 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 3026
6538 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6539 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6540 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6541 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6542 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 3030
6543 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6544 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6545 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6546 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6547 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6548 // (TXCCrr G0, IntRegs:$rs2, 6) - 3035
6549 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6550 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6551 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6552 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6553 // (TXCCrr G0, IntRegs:$rs2, 6) - 3039
6554 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6555 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6556 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6557 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6558 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6559 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 3044
6560 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6561 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6562 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6563 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6564 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 3048
6565 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6566 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6567 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6568 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6569 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6570 // (TXCCrr G0, IntRegs:$rs2, 15) - 3053
6571 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6572 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6573 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6574 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6575 // (TXCCrr G0, IntRegs:$rs2, 15) - 3057
6576 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6577 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6578 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6579 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6580 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6581 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 3062
6582 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6583 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6584 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6585 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6586 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 3066
6587 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6588 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6589 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6590 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6591 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6592 // (TXCCrr G0, IntRegs:$rs2, 7) - 3071
6593 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6594 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6595 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6596 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6597 // (TXCCrr G0, IntRegs:$rs2, 7) - 3075
6598 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6599 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6600 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6601 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6602 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6603 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 3080
6604 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6605 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6606 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6607 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6608 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 3084
6609 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6610 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6611 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6612 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6613 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6614 // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 3089
6615 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6616 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6617 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6618 // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 3092
6619 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6620 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6621 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6622 // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 3095
6623 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6624 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6625 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6626 // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2) - 3098
6627 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6628 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6629 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6630 // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 3101
6631 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6632 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6633 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6634 // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2) - 3104
6635 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6636 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6637 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6638 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8) - 3107
6639 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6640 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6641 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6642 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6643 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6644 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6645 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0) - 3113
6646 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6647 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6648 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6649 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6650 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6651 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6652 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7) - 3119
6653 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6654 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6655 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6656 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6657 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6658 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6659 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6) - 3125
6660 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6661 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6662 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6663 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6664 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6665 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6666 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5) - 3131
6667 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6668 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6669 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6670 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6671 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6672 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6673 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4) - 3137
6674 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6675 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6676 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6677 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6678 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6679 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6680 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3) - 3143
6681 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6682 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6683 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6684 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6685 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6686 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6687 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2) - 3149
6688 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6689 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6690 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6691 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6692 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6693 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6694 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1) - 3155
6695 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6696 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6697 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6698 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6699 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6700 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6701 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9) - 3161
6702 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6703 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6704 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6705 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6706 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6707 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6708 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10) - 3167
6709 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6710 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6711 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6712 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6713 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6714 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6715 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11) - 3173
6716 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6717 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6718 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6719 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6720 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6721 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6722 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12) - 3179
6723 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6724 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6725 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6726 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6727 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6728 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6729 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13) - 3185
6730 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6731 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6732 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6733 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6734 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6735 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6736 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14) - 3191
6737 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6738 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6739 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6740 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6741 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6742 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6743 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15) - 3197
6744 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6745 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6746 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6747 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6748 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6749 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6750 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8) - 3203
6751 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6752 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6753 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6754 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6755 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6756 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6757 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0) - 3209
6758 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6759 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6760 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6761 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6762 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6763 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6764 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7) - 3215
6765 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6766 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6767 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6768 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6769 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6770 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6771 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6) - 3221
6772 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6773 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6774 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6775 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6776 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6777 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6778 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5) - 3227
6779 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6780 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6781 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6782 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6783 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6784 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6785 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4) - 3233
6786 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6787 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6788 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6789 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6790 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6791 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6792 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3) - 3239
6793 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6794 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6795 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6796 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6797 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6798 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6799 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2) - 3245
6800 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6801 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6802 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6803 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6804 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6805 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6806 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1) - 3251
6807 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6808 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6809 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6810 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6811 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6812 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6813 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9) - 3257
6814 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6815 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6816 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6817 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6818 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6819 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6820 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10) - 3263
6821 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6822 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6823 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6824 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6825 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6826 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6827 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11) - 3269
6828 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6829 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6830 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6831 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6832 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6833 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6834 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12) - 3275
6835 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6836 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6837 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6838 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6839 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6840 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6841 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13) - 3281
6842 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6843 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6844 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6845 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6846 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6847 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6848 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14) - 3287
6849 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6850 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6851 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6852 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6853 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6854 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6855 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15) - 3293
6856 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6857 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6858 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6859 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6860 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6861 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6862 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8) - 3299
6863 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6864 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6865 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6866 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6867 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6868 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6869 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0) - 3305
6870 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6871 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6872 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6873 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6874 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6875 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6876 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7) - 3311
6877 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6878 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6879 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6880 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6881 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6882 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6883 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6) - 3317
6884 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6885 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6886 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6887 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6888 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6889 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6890 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5) - 3323
6891 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6892 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6893 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6894 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6895 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6896 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6897 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4) - 3329
6898 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6899 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6900 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6901 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6902 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6903 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6904 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3) - 3335
6905 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6906 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6907 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6908 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6909 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6910 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6911 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2) - 3341
6912 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6913 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6914 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6915 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6916 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6917 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6918 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1) - 3347
6919 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6920 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6921 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6922 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6923 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6924 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6925 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9) - 3353
6926 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6927 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6928 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6929 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6930 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6931 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6932 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10) - 3359
6933 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6934 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6935 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6936 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6937 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6938 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6939 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11) - 3365
6940 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6941 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6942 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6943 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6944 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6945 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6946 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12) - 3371
6947 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6948 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6949 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6950 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6951 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6952 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6953 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13) - 3377
6954 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6955 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6956 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6957 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6958 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6959 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6960 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14) - 3383
6961 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6962 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6963 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6964 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6965 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6966 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6967 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15) - 3389
6968 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6969 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6970 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6971 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6972 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6973 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6974 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8) - 3395
6975 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6976 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6977 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6978 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6979 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6980 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6981 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0) - 3401
6982 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6983 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6984 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6985 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6986 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6987 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6988 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7) - 3407
6989 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6990 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6991 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6992 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6993 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6994 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6995 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6) - 3413
6996 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6997 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6998 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6999 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7000 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
7001 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7002 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5) - 3419
7003 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7004 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7005 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7006 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7007 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
7008 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7009 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4) - 3425
7010 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7011 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7012 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7013 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7014 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
7015 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7016 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3) - 3431
7017 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7018 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7019 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7020 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7021 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
7022 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7023 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2) - 3437
7024 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7025 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7026 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7027 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7028 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
7029 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7030 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1) - 3443
7031 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7032 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7033 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7034 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7035 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
7036 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7037 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9) - 3449
7038 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7039 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7040 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7041 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7042 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
7043 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7044 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10) - 3455
7045 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7046 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7047 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7048 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7049 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
7050 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7051 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11) - 3461
7052 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7053 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7054 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7055 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7056 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
7057 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7058 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12) - 3467
7059 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7060 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7061 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7062 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7063 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
7064 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7065 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13) - 3473
7066 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7067 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7068 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7069 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7070 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
7071 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7072 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14) - 3479
7073 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7074 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7075 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7076 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7077 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
7078 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7079 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15) - 3485
7080 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7081 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7082 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7083 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7084 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
7085 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7086 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8) - 3491
7087 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7088 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7089 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7090 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7091 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
7092 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7093 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0) - 3497
7094 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7095 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7096 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7097 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7098 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
7099 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7100 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7) - 3503
7101 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7102 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7103 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7104 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7105 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
7106 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7107 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6) - 3509
7108 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7109 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7110 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7111 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7112 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
7113 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7114 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5) - 3515
7115 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7116 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7117 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7118 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7119 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
7120 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7121 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4) - 3521
7122 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7123 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7124 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7125 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7126 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
7127 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7128 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3) - 3527
7129 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7130 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7131 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7132 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7133 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
7134 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7135 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2) - 3533
7136 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7137 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7138 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7139 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7140 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
7141 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7142 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1) - 3539
7143 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7144 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7145 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7146 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7147 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
7148 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7149 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9) - 3545
7150 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7151 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7152 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7153 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7154 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
7155 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7156 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10) - 3551
7157 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7158 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7159 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7160 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7161 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
7162 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7163 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11) - 3557
7164 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7165 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7166 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7167 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7168 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
7169 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7170 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12) - 3563
7171 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7172 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7173 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7174 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7175 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
7176 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7177 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13) - 3569
7178 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7179 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7180 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7181 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7182 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
7183 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7184 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14) - 3575
7185 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7186 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7187 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7188 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7189 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
7190 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7191 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15) - 3581
7192 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7193 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7194 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7195 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7196 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
7197 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7198 // (WRASRri ASR27, G0, simm13Op:$simm13) - 3587
7199 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::ASR27},
7200 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
7201 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
7202 // (WRASRrr ASR27, G0, IntRegs:$rs2) - 3590
7203 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::ASR27},
7204 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
7205 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7206 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
7207 };
7208
7209 static const char AsmStrings[] =
7210 /* 0 */ "ba $\xFF\x01\x01\0"
7211 /* 8 */ "bn $\xFF\x01\x01\0"
7212 /* 16 */ "bne $\xFF\x01\x01\0"
7213 /* 25 */ "be $\xFF\x01\x01\0"
7214 /* 33 */ "bg $\xFF\x01\x01\0"
7215 /* 41 */ "ble $\xFF\x01\x01\0"
7216 /* 50 */ "bge $\xFF\x01\x01\0"
7217 /* 59 */ "bl $\xFF\x01\x01\0"
7218 /* 67 */ "bgu $\xFF\x01\x01\0"
7219 /* 76 */ "bleu $\xFF\x01\x01\0"
7220 /* 86 */ "bcc $\xFF\x01\x01\0"
7221 /* 95 */ "bcs $\xFF\x01\x01\0"
7222 /* 104 */ "bpos $\xFF\x01\x01\0"
7223 /* 114 */ "bneg $\xFF\x01\x01\0"
7224 /* 124 */ "bvc $\xFF\x01\x01\0"
7225 /* 133 */ "bvs $\xFF\x01\x01\0"
7226 /* 142 */ "ba,a $\xFF\x01\x01\0"
7227 /* 152 */ "bn,a $\xFF\x01\x01\0"
7228 /* 162 */ "bne,a $\xFF\x01\x01\0"
7229 /* 173 */ "be,a $\xFF\x01\x01\0"
7230 /* 183 */ "bg,a $\xFF\x01\x01\0"
7231 /* 193 */ "ble,a $\xFF\x01\x01\0"
7232 /* 204 */ "bge,a $\xFF\x01\x01\0"
7233 /* 215 */ "bl,a $\xFF\x01\x01\0"
7234 /* 225 */ "bgu,a $\xFF\x01\x01\0"
7235 /* 236 */ "bleu,a $\xFF\x01\x01\0"
7236 /* 248 */ "bcc,a $\xFF\x01\x01\0"
7237 /* 259 */ "bcs,a $\xFF\x01\x01\0"
7238 /* 270 */ "bpos,a $\xFF\x01\x01\0"
7239 /* 282 */ "bneg,a $\xFF\x01\x01\0"
7240 /* 294 */ "bvc,a $\xFF\x01\x01\0"
7241 /* 305 */ "bvs,a $\xFF\x01\x01\0"
7242 /* 316 */ "fba,a,pn $\x03, $\xFF\x01\x01\0"
7243 /* 334 */ "fbn,a,pn $\x03, $\xFF\x01\x01\0"
7244 /* 352 */ "fbu,a,pn $\x03, $\xFF\x01\x01\0"
7245 /* 370 */ "fbg,a,pn $\x03, $\xFF\x01\x01\0"
7246 /* 388 */ "fbug,a,pn $\x03, $\xFF\x01\x01\0"
7247 /* 407 */ "fbl,a,pn $\x03, $\xFF\x01\x01\0"
7248 /* 425 */ "fbul,a,pn $\x03, $\xFF\x01\x01\0"
7249 /* 444 */ "fblg,a,pn $\x03, $\xFF\x01\x01\0"
7250 /* 463 */ "fbne,a,pn $\x03, $\xFF\x01\x01\0"
7251 /* 482 */ "fbe,a,pn $\x03, $\xFF\x01\x01\0"
7252 /* 500 */ "fbue,a,pn $\x03, $\xFF\x01\x01\0"
7253 /* 519 */ "fbge,a,pn $\x03, $\xFF\x01\x01\0"
7254 /* 538 */ "fbuge,a,pn $\x03, $\xFF\x01\x01\0"
7255 /* 558 */ "fble,a,pn $\x03, $\xFF\x01\x01\0"
7256 /* 577 */ "fbule,a,pn $\x03, $\xFF\x01\x01\0"
7257 /* 597 */ "fbo,a,pn $\x03, $\xFF\x01\x01\0"
7258 /* 615 */ "fba,pn $\x03, $\xFF\x01\x01\0"
7259 /* 631 */ "fbn,pn $\x03, $\xFF\x01\x01\0"
7260 /* 647 */ "fbu,pn $\x03, $\xFF\x01\x01\0"
7261 /* 663 */ "fbg,pn $\x03, $\xFF\x01\x01\0"
7262 /* 679 */ "fbug,pn $\x03, $\xFF\x01\x01\0"
7263 /* 696 */ "fbl,pn $\x03, $\xFF\x01\x01\0"
7264 /* 712 */ "fbul,pn $\x03, $\xFF\x01\x01\0"
7265 /* 729 */ "fblg,pn $\x03, $\xFF\x01\x01\0"
7266 /* 746 */ "fbne,pn $\x03, $\xFF\x01\x01\0"
7267 /* 763 */ "fbe,pn $\x03, $\xFF\x01\x01\0"
7268 /* 779 */ "fbue,pn $\x03, $\xFF\x01\x01\0"
7269 /* 796 */ "fbge,pn $\x03, $\xFF\x01\x01\0"
7270 /* 813 */ "fbuge,pn $\x03, $\xFF\x01\x01\0"
7271 /* 831 */ "fble,pn $\x03, $\xFF\x01\x01\0"
7272 /* 848 */ "fbule,pn $\x03, $\xFF\x01\x01\0"
7273 /* 866 */ "fbo,pn $\x03, $\xFF\x01\x01\0"
7274 /* 882 */ "ba,a,pn %icc, $\xFF\x01\x01\0"
7275 /* 901 */ "ba,a,pn %ncc, $\xFF\x01\x01\0"
7276 /* 920 */ "bn,a,pn %icc, $\xFF\x01\x01\0"
7277 /* 939 */ "bn,a,pn %ncc, $\xFF\x01\x01\0"
7278 /* 958 */ "bne,a,pn %icc, $\xFF\x01\x01\0"
7279 /* 978 */ "bne,a,pn %ncc, $\xFF\x01\x01\0"
7280 /* 998 */ "be,a,pn %icc, $\xFF\x01\x01\0"
7281 /* 1017 */ "be,a,pn %ncc, $\xFF\x01\x01\0"
7282 /* 1036 */ "bg,a,pn %icc, $\xFF\x01\x01\0"
7283 /* 1055 */ "bg,a,pn %ncc, $\xFF\x01\x01\0"
7284 /* 1074 */ "ble,a,pn %icc, $\xFF\x01\x01\0"
7285 /* 1094 */ "ble,a,pn %ncc, $\xFF\x01\x01\0"
7286 /* 1114 */ "bge,a,pn %icc, $\xFF\x01\x01\0"
7287 /* 1134 */ "bge,a,pn %ncc, $\xFF\x01\x01\0"
7288 /* 1154 */ "bl,a,pn %icc, $\xFF\x01\x01\0"
7289 /* 1173 */ "bl,a,pn %ncc, $\xFF\x01\x01\0"
7290 /* 1192 */ "bgu,a,pn %icc, $\xFF\x01\x01\0"
7291 /* 1212 */ "bgu,a,pn %ncc, $\xFF\x01\x01\0"
7292 /* 1232 */ "bleu,a,pn %icc, $\xFF\x01\x01\0"
7293 /* 1253 */ "bleu,a,pn %ncc, $\xFF\x01\x01\0"
7294 /* 1274 */ "bcc,a,pn %icc, $\xFF\x01\x01\0"
7295 /* 1294 */ "bcc,a,pn %ncc, $\xFF\x01\x01\0"
7296 /* 1314 */ "bcs,a,pn %icc, $\xFF\x01\x01\0"
7297 /* 1334 */ "bcs,a,pn %ncc, $\xFF\x01\x01\0"
7298 /* 1354 */ "bpos,a,pn %icc, $\xFF\x01\x01\0"
7299 /* 1375 */ "bpos,a,pn %ncc, $\xFF\x01\x01\0"
7300 /* 1396 */ "bneg,a,pn %icc, $\xFF\x01\x01\0"
7301 /* 1417 */ "bneg,a,pn %ncc, $\xFF\x01\x01\0"
7302 /* 1438 */ "bvc,a,pn %icc, $\xFF\x01\x01\0"
7303 /* 1458 */ "bvc,a,pn %ncc, $\xFF\x01\x01\0"
7304 /* 1478 */ "bvs,a,pn %icc, $\xFF\x01\x01\0"
7305 /* 1498 */ "bvs,a,pn %ncc, $\xFF\x01\x01\0"
7306 /* 1518 */ "ba,pn %icc, $\xFF\x01\x01\0"
7307 /* 1535 */ "ba,pn %ncc, $\xFF\x01\x01\0"
7308 /* 1552 */ "bn,pn %icc, $\xFF\x01\x01\0"
7309 /* 1569 */ "bn,pn %ncc, $\xFF\x01\x01\0"
7310 /* 1586 */ "bne,pn %icc, $\xFF\x01\x01\0"
7311 /* 1604 */ "bne,pn %ncc, $\xFF\x01\x01\0"
7312 /* 1622 */ "be,pn %icc, $\xFF\x01\x01\0"
7313 /* 1639 */ "be,pn %ncc, $\xFF\x01\x01\0"
7314 /* 1656 */ "bg,pn %icc, $\xFF\x01\x01\0"
7315 /* 1673 */ "bg,pn %ncc, $\xFF\x01\x01\0"
7316 /* 1690 */ "ble,pn %icc, $\xFF\x01\x01\0"
7317 /* 1708 */ "ble,pn %ncc, $\xFF\x01\x01\0"
7318 /* 1726 */ "bge,pn %icc, $\xFF\x01\x01\0"
7319 /* 1744 */ "bge,pn %ncc, $\xFF\x01\x01\0"
7320 /* 1762 */ "bl,pn %icc, $\xFF\x01\x01\0"
7321 /* 1779 */ "bl,pn %ncc, $\xFF\x01\x01\0"
7322 /* 1796 */ "bgu,pn %icc, $\xFF\x01\x01\0"
7323 /* 1814 */ "bgu,pn %ncc, $\xFF\x01\x01\0"
7324 /* 1832 */ "bleu,pn %icc, $\xFF\x01\x01\0"
7325 /* 1851 */ "bleu,pn %ncc, $\xFF\x01\x01\0"
7326 /* 1870 */ "bcc,pn %icc, $\xFF\x01\x01\0"
7327 /* 1888 */ "bcc,pn %ncc, $\xFF\x01\x01\0"
7328 /* 1906 */ "bcs,pn %icc, $\xFF\x01\x01\0"
7329 /* 1924 */ "bcs,pn %ncc, $\xFF\x01\x01\0"
7330 /* 1942 */ "bpos,pn %icc, $\xFF\x01\x01\0"
7331 /* 1961 */ "bpos,pn %ncc, $\xFF\x01\x01\0"
7332 /* 1980 */ "bneg,pn %icc, $\xFF\x01\x01\0"
7333 /* 1999 */ "bneg,pn %ncc, $\xFF\x01\x01\0"
7334 /* 2018 */ "bvc,pn %icc, $\xFF\x01\x01\0"
7335 /* 2036 */ "bvc,pn %ncc, $\xFF\x01\x01\0"
7336 /* 2054 */ "bvs,pn %icc, $\xFF\x01\x01\0"
7337 /* 2072 */ "bvs,pn %ncc, $\xFF\x01\x01\0"
7338 /* 2090 */ "brlez,a,pn $\x03, $\xFF\x01\x01\0"
7339 /* 2110 */ "brlz,a,pn $\x03, $\xFF\x01\x01\0"
7340 /* 2129 */ "brgz,a,pn $\x03, $\xFF\x01\x01\0"
7341 /* 2148 */ "brgez,a,pn $\x03, $\xFF\x01\x01\0"
7342 /* 2168 */ "brlez,pn $\x03, $\xFF\x01\x01\0"
7343 /* 2186 */ "brlz,pn $\x03, $\xFF\x01\x01\0"
7344 /* 2203 */ "brgz,pn $\x03, $\xFF\x01\x01\0"
7345 /* 2220 */ "brgez,pn $\x03, $\xFF\x01\x01\0"
7346 /* 2238 */ "cas [$\x02], $\x03, $\x01\0"
7347 /* 2255 */ "casl [$\x02], $\x03, $\x01\0"
7348 /* 2273 */ "casx [$\x02], $\x03, $\x01\0"
7349 /* 2291 */ "casxl [$\x02], $\x03, $\x01\0"
7350 /* 2310 */ "cwbne $\x03, $\x04, $\xFF\x01\x01\0"
7351 /* 2329 */ "cwbe $\x03, $\x04, $\xFF\x01\x01\0"
7352 /* 2347 */ "cwbg $\x03, $\x04, $\xFF\x01\x01\0"
7353 /* 2365 */ "cwble $\x03, $\x04, $\xFF\x01\x01\0"
7354 /* 2384 */ "cwbge $\x03, $\x04, $\xFF\x01\x01\0"
7355 /* 2403 */ "cwbl $\x03, $\x04, $\xFF\x01\x01\0"
7356 /* 2421 */ "cwbgu $\x03, $\x04, $\xFF\x01\x01\0"
7357 /* 2440 */ "cwbleu $\x03, $\x04, $\xFF\x01\x01\0"
7358 /* 2460 */ "cwbcc $\x03, $\x04, $\xFF\x01\x01\0"
7359 /* 2479 */ "cwbcs $\x03, $\x04, $\xFF\x01\x01\0"
7360 /* 2498 */ "cwbpos $\x03, $\x04, $\xFF\x01\x01\0"
7361 /* 2518 */ "cwbneg $\x03, $\x04, $\xFF\x01\x01\0"
7362 /* 2538 */ "cwbvc $\x03, $\x04, $\xFF\x01\x01\0"
7363 /* 2557 */ "cwbvs $\x03, $\x04, $\xFF\x01\x01\0"
7364 /* 2576 */ "cxbne $\x03, $\x04, $\xFF\x01\x01\0"
7365 /* 2595 */ "cxbe $\x03, $\x04, $\xFF\x01\x01\0"
7366 /* 2613 */ "cxbg $\x03, $\x04, $\xFF\x01\x01\0"
7367 /* 2631 */ "cxble $\x03, $\x04, $\xFF\x01\x01\0"
7368 /* 2650 */ "cxbge $\x03, $\x04, $\xFF\x01\x01\0"
7369 /* 2669 */ "cxbl $\x03, $\x04, $\xFF\x01\x01\0"
7370 /* 2687 */ "cxbgu $\x03, $\x04, $\xFF\x01\x01\0"
7371 /* 2706 */ "cxbleu $\x03, $\x04, $\xFF\x01\x01\0"
7372 /* 2726 */ "cxbcc $\x03, $\x04, $\xFF\x01\x01\0"
7373 /* 2745 */ "cxbcs $\x03, $\x04, $\xFF\x01\x01\0"
7374 /* 2764 */ "cxbpos $\x03, $\x04, $\xFF\x01\x01\0"
7375 /* 2784 */ "cxbneg $\x03, $\x04, $\xFF\x01\x01\0"
7376 /* 2804 */ "cxbvc $\x03, $\x04, $\xFF\x01\x01\0"
7377 /* 2823 */ "cxbvs $\x03, $\x04, $\xFF\x01\x01\0"
7378 /* 2842 */ "fmovda %icc, $\x02, $\x01\0"
7379 /* 2862 */ "fmovda %ncc, $\x02, $\x01\0"
7380 /* 2882 */ "fmovdn %icc, $\x02, $\x01\0"
7381 /* 2902 */ "fmovdn %ncc, $\x02, $\x01\0"
7382 /* 2922 */ "fmovdne %icc, $\x02, $\x01\0"
7383 /* 2943 */ "fmovdne %ncc, $\x02, $\x01\0"
7384 /* 2964 */ "fmovde %icc, $\x02, $\x01\0"
7385 /* 2984 */ "fmovde %ncc, $\x02, $\x01\0"
7386 /* 3004 */ "fmovdg %icc, $\x02, $\x01\0"
7387 /* 3024 */ "fmovdg %ncc, $\x02, $\x01\0"
7388 /* 3044 */ "fmovdle %icc, $\x02, $\x01\0"
7389 /* 3065 */ "fmovdle %ncc, $\x02, $\x01\0"
7390 /* 3086 */ "fmovdge %icc, $\x02, $\x01\0"
7391 /* 3107 */ "fmovdge %ncc, $\x02, $\x01\0"
7392 /* 3128 */ "fmovdl %icc, $\x02, $\x01\0"
7393 /* 3148 */ "fmovdl %ncc, $\x02, $\x01\0"
7394 /* 3168 */ "fmovdgu %icc, $\x02, $\x01\0"
7395 /* 3189 */ "fmovdgu %ncc, $\x02, $\x01\0"
7396 /* 3210 */ "fmovdleu %icc, $\x02, $\x01\0"
7397 /* 3232 */ "fmovdleu %ncc, $\x02, $\x01\0"
7398 /* 3254 */ "fmovdcc %icc, $\x02, $\x01\0"
7399 /* 3275 */ "fmovdcc %ncc, $\x02, $\x01\0"
7400 /* 3296 */ "fmovdcs %icc, $\x02, $\x01\0"
7401 /* 3317 */ "fmovdcs %ncc, $\x02, $\x01\0"
7402 /* 3338 */ "fmovdpos %icc, $\x02, $\x01\0"
7403 /* 3360 */ "fmovdpos %ncc, $\x02, $\x01\0"
7404 /* 3382 */ "fmovdneg %icc, $\x02, $\x01\0"
7405 /* 3404 */ "fmovdneg %ncc, $\x02, $\x01\0"
7406 /* 3426 */ "fmovdvc %icc, $\x02, $\x01\0"
7407 /* 3447 */ "fmovdvc %ncc, $\x02, $\x01\0"
7408 /* 3468 */ "fmovdvs %icc, $\x02, $\x01\0"
7409 /* 3489 */ "fmovdvs %ncc, $\x02, $\x01\0"
7410 /* 3510 */ "fmovqa %icc, $\x02, $\x01\0"
7411 /* 3530 */ "fmovqa %ncc, $\x02, $\x01\0"
7412 /* 3550 */ "fmovqn %icc, $\x02, $\x01\0"
7413 /* 3570 */ "fmovqn %ncc, $\x02, $\x01\0"
7414 /* 3590 */ "fmovqne %icc, $\x02, $\x01\0"
7415 /* 3611 */ "fmovqne %ncc, $\x02, $\x01\0"
7416 /* 3632 */ "fmovqe %icc, $\x02, $\x01\0"
7417 /* 3652 */ "fmovqe %ncc, $\x02, $\x01\0"
7418 /* 3672 */ "fmovqg %icc, $\x02, $\x01\0"
7419 /* 3692 */ "fmovqg %ncc, $\x02, $\x01\0"
7420 /* 3712 */ "fmovqle %icc, $\x02, $\x01\0"
7421 /* 3733 */ "fmovqle %ncc, $\x02, $\x01\0"
7422 /* 3754 */ "fmovqge %icc, $\x02, $\x01\0"
7423 /* 3775 */ "fmovqge %ncc, $\x02, $\x01\0"
7424 /* 3796 */ "fmovql %icc, $\x02, $\x01\0"
7425 /* 3816 */ "fmovql %ncc, $\x02, $\x01\0"
7426 /* 3836 */ "fmovqgu %icc, $\x02, $\x01\0"
7427 /* 3857 */ "fmovqgu %ncc, $\x02, $\x01\0"
7428 /* 3878 */ "fmovqleu %icc, $\x02, $\x01\0"
7429 /* 3900 */ "fmovqleu %ncc, $\x02, $\x01\0"
7430 /* 3922 */ "fmovqcc %icc, $\x02, $\x01\0"
7431 /* 3943 */ "fmovqcc %ncc, $\x02, $\x01\0"
7432 /* 3964 */ "fmovqcs %icc, $\x02, $\x01\0"
7433 /* 3985 */ "fmovqcs %ncc, $\x02, $\x01\0"
7434 /* 4006 */ "fmovqpos %icc, $\x02, $\x01\0"
7435 /* 4028 */ "fmovqpos %ncc, $\x02, $\x01\0"
7436 /* 4050 */ "fmovqneg %icc, $\x02, $\x01\0"
7437 /* 4072 */ "fmovqneg %ncc, $\x02, $\x01\0"
7438 /* 4094 */ "fmovqvc %icc, $\x02, $\x01\0"
7439 /* 4115 */ "fmovqvc %ncc, $\x02, $\x01\0"
7440 /* 4136 */ "fmovqvs %icc, $\x02, $\x01\0"
7441 /* 4157 */ "fmovqvs %ncc, $\x02, $\x01\0"
7442 /* 4178 */ "fmovrdlez $\x02, $\x03, $\x01\0"
7443 /* 4199 */ "fmovrdlz $\x02, $\x03, $\x01\0"
7444 /* 4219 */ "fmovrdgz $\x02, $\x03, $\x01\0"
7445 /* 4239 */ "fmovrdgez $\x02, $\x03, $\x01\0"
7446 /* 4260 */ "fmovrqlez $\x02, $\x03, $\x01\0"
7447 /* 4281 */ "fmovrqlz $\x02, $\x03, $\x01\0"
7448 /* 4301 */ "fmovrqgz $\x02, $\x03, $\x01\0"
7449 /* 4321 */ "fmovrqgez $\x02, $\x03, $\x01\0"
7450 /* 4342 */ "fmovrslez $\x02, $\x03, $\x01\0"
7451 /* 4363 */ "fmovrslz $\x02, $\x03, $\x01\0"
7452 /* 4383 */ "fmovrsgz $\x02, $\x03, $\x01\0"
7453 /* 4403 */ "fmovrsgez $\x02, $\x03, $\x01\0"
7454 /* 4424 */ "fmovsa %icc, $\x02, $\x01\0"
7455 /* 4444 */ "fmovsa %ncc, $\x02, $\x01\0"
7456 /* 4464 */ "fmovsn %icc, $\x02, $\x01\0"
7457 /* 4484 */ "fmovsn %ncc, $\x02, $\x01\0"
7458 /* 4504 */ "fmovsne %icc, $\x02, $\x01\0"
7459 /* 4525 */ "fmovsne %ncc, $\x02, $\x01\0"
7460 /* 4546 */ "fmovse %icc, $\x02, $\x01\0"
7461 /* 4566 */ "fmovse %ncc, $\x02, $\x01\0"
7462 /* 4586 */ "fmovsg %icc, $\x02, $\x01\0"
7463 /* 4606 */ "fmovsg %ncc, $\x02, $\x01\0"
7464 /* 4626 */ "fmovsle %icc, $\x02, $\x01\0"
7465 /* 4647 */ "fmovsle %ncc, $\x02, $\x01\0"
7466 /* 4668 */ "fmovsge %icc, $\x02, $\x01\0"
7467 /* 4689 */ "fmovsge %ncc, $\x02, $\x01\0"
7468 /* 4710 */ "fmovsl %icc, $\x02, $\x01\0"
7469 /* 4730 */ "fmovsl %ncc, $\x02, $\x01\0"
7470 /* 4750 */ "fmovsgu %icc, $\x02, $\x01\0"
7471 /* 4771 */ "fmovsgu %ncc, $\x02, $\x01\0"
7472 /* 4792 */ "fmovsleu %icc, $\x02, $\x01\0"
7473 /* 4814 */ "fmovsleu %ncc, $\x02, $\x01\0"
7474 /* 4836 */ "fmovscc %icc, $\x02, $\x01\0"
7475 /* 4857 */ "fmovscc %ncc, $\x02, $\x01\0"
7476 /* 4878 */ "fmovscs %icc, $\x02, $\x01\0"
7477 /* 4899 */ "fmovscs %ncc, $\x02, $\x01\0"
7478 /* 4920 */ "fmovspos %icc, $\x02, $\x01\0"
7479 /* 4942 */ "fmovspos %ncc, $\x02, $\x01\0"
7480 /* 4964 */ "fmovsneg %icc, $\x02, $\x01\0"
7481 /* 4986 */ "fmovsneg %ncc, $\x02, $\x01\0"
7482 /* 5008 */ "fmovsvc %icc, $\x02, $\x01\0"
7483 /* 5029 */ "fmovsvc %ncc, $\x02, $\x01\0"
7484 /* 5050 */ "fmovsvs %icc, $\x02, $\x01\0"
7485 /* 5071 */ "fmovsvs %ncc, $\x02, $\x01\0"
7486 /* 5092 */ "mova %icc, $\x02, $\x01\0"
7487 /* 5110 */ "mova %ncc, $\x02, $\x01\0"
7488 /* 5128 */ "movn %icc, $\x02, $\x01\0"
7489 /* 5146 */ "movn %ncc, $\x02, $\x01\0"
7490 /* 5164 */ "movne %icc, $\x02, $\x01\0"
7491 /* 5183 */ "movne %ncc, $\x02, $\x01\0"
7492 /* 5202 */ "move %icc, $\x02, $\x01\0"
7493 /* 5220 */ "move %ncc, $\x02, $\x01\0"
7494 /* 5238 */ "movg %icc, $\x02, $\x01\0"
7495 /* 5256 */ "movg %ncc, $\x02, $\x01\0"
7496 /* 5274 */ "movle %icc, $\x02, $\x01\0"
7497 /* 5293 */ "movle %ncc, $\x02, $\x01\0"
7498 /* 5312 */ "movge %icc, $\x02, $\x01\0"
7499 /* 5331 */ "movge %ncc, $\x02, $\x01\0"
7500 /* 5350 */ "movl %icc, $\x02, $\x01\0"
7501 /* 5368 */ "movl %ncc, $\x02, $\x01\0"
7502 /* 5386 */ "movgu %icc, $\x02, $\x01\0"
7503 /* 5405 */ "movgu %ncc, $\x02, $\x01\0"
7504 /* 5424 */ "movleu %icc, $\x02, $\x01\0"
7505 /* 5444 */ "movleu %ncc, $\x02, $\x01\0"
7506 /* 5464 */ "movcc %icc, $\x02, $\x01\0"
7507 /* 5483 */ "movcc %ncc, $\x02, $\x01\0"
7508 /* 5502 */ "movcs %icc, $\x02, $\x01\0"
7509 /* 5521 */ "movcs %ncc, $\x02, $\x01\0"
7510 /* 5540 */ "movpos %icc, $\x02, $\x01\0"
7511 /* 5560 */ "movpos %ncc, $\x02, $\x01\0"
7512 /* 5580 */ "movneg %icc, $\x02, $\x01\0"
7513 /* 5600 */ "movneg %ncc, $\x02, $\x01\0"
7514 /* 5620 */ "movvc %icc, $\x02, $\x01\0"
7515 /* 5639 */ "movvc %ncc, $\x02, $\x01\0"
7516 /* 5658 */ "movvs %icc, $\x02, $\x01\0"
7517 /* 5677 */ "movvs %ncc, $\x02, $\x01\0"
7518 /* 5696 */ "movrlez $\x02, $\x03, $\x01\0"
7519 /* 5715 */ "movrlz $\x02, $\x03, $\x01\0"
7520 /* 5733 */ "movrgz $\x02, $\x03, $\x01\0"
7521 /* 5751 */ "movrgez $\x02, $\x03, $\x01\0"
7522 /* 5770 */ "tst $\x02\0"
7523 /* 5777 */ "mov $\x03, $\x01\0"
7524 /* 5788 */ "restore\0"
7525 /* 5796 */ "ret\0"
7526 /* 5800 */ "retl\0"
7527 /* 5805 */ "save\0"
7528 /* 5810 */ "cmp $\x02, $\x03\0"
7529 /* 5821 */ "ta %icc, $\x02\0"
7530 /* 5833 */ "ta %ncc, $\x02\0"
7531 /* 5845 */ "ta %icc, $\x01 + $\x02\0"
7532 /* 5862 */ "ta %ncc, $\x01 + $\x02\0"
7533 /* 5879 */ "tn %icc, $\x02\0"
7534 /* 5891 */ "tn %ncc, $\x02\0"
7535 /* 5903 */ "tn %icc, $\x01 + $\x02\0"
7536 /* 5920 */ "tn %ncc, $\x01 + $\x02\0"
7537 /* 5937 */ "tne %icc, $\x02\0"
7538 /* 5950 */ "tne %ncc, $\x02\0"
7539 /* 5963 */ "tne %icc, $\x01 + $\x02\0"
7540 /* 5981 */ "tne %ncc, $\x01 + $\x02\0"
7541 /* 5999 */ "te %icc, $\x02\0"
7542 /* 6011 */ "te %ncc, $\x02\0"
7543 /* 6023 */ "te %icc, $\x01 + $\x02\0"
7544 /* 6040 */ "te %ncc, $\x01 + $\x02\0"
7545 /* 6057 */ "tg %icc, $\x02\0"
7546 /* 6069 */ "tg %ncc, $\x02\0"
7547 /* 6081 */ "tg %icc, $\x01 + $\x02\0"
7548 /* 6098 */ "tg %ncc, $\x01 + $\x02\0"
7549 /* 6115 */ "tle %icc, $\x02\0"
7550 /* 6128 */ "tle %ncc, $\x02\0"
7551 /* 6141 */ "tle %icc, $\x01 + $\x02\0"
7552 /* 6159 */ "tle %ncc, $\x01 + $\x02\0"
7553 /* 6177 */ "tge %icc, $\x02\0"
7554 /* 6190 */ "tge %ncc, $\x02\0"
7555 /* 6203 */ "tge %icc, $\x01 + $\x02\0"
7556 /* 6221 */ "tge %ncc, $\x01 + $\x02\0"
7557 /* 6239 */ "tl %icc, $\x02\0"
7558 /* 6251 */ "tl %ncc, $\x02\0"
7559 /* 6263 */ "tl %icc, $\x01 + $\x02\0"
7560 /* 6280 */ "tl %ncc, $\x01 + $\x02\0"
7561 /* 6297 */ "tgu %icc, $\x02\0"
7562 /* 6310 */ "tgu %ncc, $\x02\0"
7563 /* 6323 */ "tgu %icc, $\x01 + $\x02\0"
7564 /* 6341 */ "tgu %ncc, $\x01 + $\x02\0"
7565 /* 6359 */ "tleu %icc, $\x02\0"
7566 /* 6373 */ "tleu %ncc, $\x02\0"
7567 /* 6387 */ "tleu %icc, $\x01 + $\x02\0"
7568 /* 6406 */ "tleu %ncc, $\x01 + $\x02\0"
7569 /* 6425 */ "tcc %icc, $\x02\0"
7570 /* 6438 */ "tcc %ncc, $\x02\0"
7571 /* 6451 */ "tcc %icc, $\x01 + $\x02\0"
7572 /* 6469 */ "tcc %ncc, $\x01 + $\x02\0"
7573 /* 6487 */ "tcs %icc, $\x02\0"
7574 /* 6500 */ "tcs %ncc, $\x02\0"
7575 /* 6513 */ "tcs %icc, $\x01 + $\x02\0"
7576 /* 6531 */ "tcs %ncc, $\x01 + $\x02\0"
7577 /* 6549 */ "tpos %icc, $\x02\0"
7578 /* 6563 */ "tpos %ncc, $\x02\0"
7579 /* 6577 */ "tpos %icc, $\x01 + $\x02\0"
7580 /* 6596 */ "tpos %ncc, $\x01 + $\x02\0"
7581 /* 6615 */ "tneg %icc, $\x02\0"
7582 /* 6629 */ "tneg %ncc, $\x02\0"
7583 /* 6643 */ "tneg %icc, $\x01 + $\x02\0"
7584 /* 6662 */ "tneg %ncc, $\x01 + $\x02\0"
7585 /* 6681 */ "tvc %icc, $\x02\0"
7586 /* 6694 */ "tvc %ncc, $\x02\0"
7587 /* 6707 */ "tvc %icc, $\x01 + $\x02\0"
7588 /* 6725 */ "tvc %ncc, $\x01 + $\x02\0"
7589 /* 6743 */ "tvs %icc, $\x02\0"
7590 /* 6756 */ "tvs %ncc, $\x02\0"
7591 /* 6769 */ "tvs %icc, $\x01 + $\x02\0"
7592 /* 6787 */ "tvs %ncc, $\x01 + $\x02\0"
7593 /* 6805 */ "ta $\x02\0"
7594 /* 6811 */ "ta $\x01 + $\x02\0"
7595 /* 6822 */ "tn $\x02\0"
7596 /* 6828 */ "tn $\x01 + $\x02\0"
7597 /* 6839 */ "tne $\x02\0"
7598 /* 6846 */ "tne $\x01 + $\x02\0"
7599 /* 6858 */ "te $\x02\0"
7600 /* 6864 */ "te $\x01 + $\x02\0"
7601 /* 6875 */ "tg $\x02\0"
7602 /* 6881 */ "tg $\x01 + $\x02\0"
7603 /* 6892 */ "tle $\x02\0"
7604 /* 6899 */ "tle $\x01 + $\x02\0"
7605 /* 6911 */ "tge $\x02\0"
7606 /* 6918 */ "tge $\x01 + $\x02\0"
7607 /* 6930 */ "tl $\x02\0"
7608 /* 6936 */ "tl $\x01 + $\x02\0"
7609 /* 6947 */ "tgu $\x02\0"
7610 /* 6954 */ "tgu $\x01 + $\x02\0"
7611 /* 6966 */ "tleu $\x02\0"
7612 /* 6974 */ "tleu $\x01 + $\x02\0"
7613 /* 6987 */ "tcc $\x02\0"
7614 /* 6994 */ "tcc $\x01 + $\x02\0"
7615 /* 7006 */ "tcs $\x02\0"
7616 /* 7013 */ "tcs $\x01 + $\x02\0"
7617 /* 7025 */ "tpos $\x02\0"
7618 /* 7033 */ "tpos $\x01 + $\x02\0"
7619 /* 7046 */ "tneg $\x02\0"
7620 /* 7054 */ "tneg $\x01 + $\x02\0"
7621 /* 7067 */ "tvc $\x02\0"
7622 /* 7074 */ "tvc $\x01 + $\x02\0"
7623 /* 7086 */ "tvs $\x02\0"
7624 /* 7093 */ "tvs $\x01 + $\x02\0"
7625 /* 7105 */ "ta %xcc, $\x02\0"
7626 /* 7117 */ "ta %xcc, $\x01 + $\x02\0"
7627 /* 7134 */ "tn %xcc, $\x02\0"
7628 /* 7146 */ "tn %xcc, $\x01 + $\x02\0"
7629 /* 7163 */ "tne %xcc, $\x02\0"
7630 /* 7176 */ "tne %xcc, $\x01 + $\x02\0"
7631 /* 7194 */ "te %xcc, $\x02\0"
7632 /* 7206 */ "te %xcc, $\x01 + $\x02\0"
7633 /* 7223 */ "tg %xcc, $\x02\0"
7634 /* 7235 */ "tg %xcc, $\x01 + $\x02\0"
7635 /* 7252 */ "tle %xcc, $\x02\0"
7636 /* 7265 */ "tle %xcc, $\x01 + $\x02\0"
7637 /* 7283 */ "tge %xcc, $\x02\0"
7638 /* 7296 */ "tge %xcc, $\x01 + $\x02\0"
7639 /* 7314 */ "tl %xcc, $\x02\0"
7640 /* 7326 */ "tl %xcc, $\x01 + $\x02\0"
7641 /* 7343 */ "tgu %xcc, $\x02\0"
7642 /* 7356 */ "tgu %xcc, $\x01 + $\x02\0"
7643 /* 7374 */ "tleu %xcc, $\x02\0"
7644 /* 7388 */ "tleu %xcc, $\x01 + $\x02\0"
7645 /* 7407 */ "tcc %xcc, $\x02\0"
7646 /* 7420 */ "tcc %xcc, $\x01 + $\x02\0"
7647 /* 7438 */ "tcs %xcc, $\x02\0"
7648 /* 7451 */ "tcs %xcc, $\x01 + $\x02\0"
7649 /* 7469 */ "tpos %xcc, $\x02\0"
7650 /* 7483 */ "tpos %xcc, $\x01 + $\x02\0"
7651 /* 7502 */ "tneg %xcc, $\x02\0"
7652 /* 7516 */ "tneg %xcc, $\x01 + $\x02\0"
7653 /* 7535 */ "tvc %xcc, $\x02\0"
7654 /* 7548 */ "tvc %xcc, $\x01 + $\x02\0"
7655 /* 7566 */ "tvs %xcc, $\x02\0"
7656 /* 7579 */ "tvs %xcc, $\x01 + $\x02\0"
7657 /* 7597 */ "fcmpd $\x02, $\x03\0"
7658 /* 7610 */ "fcmped $\x02, $\x03\0"
7659 /* 7624 */ "fcmpeq $\x02, $\x03\0"
7660 /* 7638 */ "fcmpes $\x02, $\x03\0"
7661 /* 7652 */ "fcmpq $\x02, $\x03\0"
7662 /* 7665 */ "fcmps $\x02, $\x03\0"
7663 /* 7678 */ "fmovda $\x02, $\x03, $\x01\0"
7664 /* 7696 */ "fmovdn $\x02, $\x03, $\x01\0"
7665 /* 7714 */ "fmovdu $\x02, $\x03, $\x01\0"
7666 /* 7732 */ "fmovdg $\x02, $\x03, $\x01\0"
7667 /* 7750 */ "fmovdug $\x02, $\x03, $\x01\0"
7668 /* 7769 */ "fmovdl $\x02, $\x03, $\x01\0"
7669 /* 7787 */ "fmovdul $\x02, $\x03, $\x01\0"
7670 /* 7806 */ "fmovdlg $\x02, $\x03, $\x01\0"
7671 /* 7825 */ "fmovdne $\x02, $\x03, $\x01\0"
7672 /* 7844 */ "fmovde $\x02, $\x03, $\x01\0"
7673 /* 7862 */ "fmovdue $\x02, $\x03, $\x01\0"
7674 /* 7881 */ "fmovdge $\x02, $\x03, $\x01\0"
7675 /* 7900 */ "fmovduge $\x02, $\x03, $\x01\0"
7676 /* 7920 */ "fmovdle $\x02, $\x03, $\x01\0"
7677 /* 7939 */ "fmovdule $\x02, $\x03, $\x01\0"
7678 /* 7959 */ "fmovdo $\x02, $\x03, $\x01\0"
7679 /* 7977 */ "fmovqa $\x02, $\x03, $\x01\0"
7680 /* 7995 */ "fmovqn $\x02, $\x03, $\x01\0"
7681 /* 8013 */ "fmovqu $\x02, $\x03, $\x01\0"
7682 /* 8031 */ "fmovqg $\x02, $\x03, $\x01\0"
7683 /* 8049 */ "fmovqug $\x02, $\x03, $\x01\0"
7684 /* 8068 */ "fmovql $\x02, $\x03, $\x01\0"
7685 /* 8086 */ "fmovqul $\x02, $\x03, $\x01\0"
7686 /* 8105 */ "fmovqlg $\x02, $\x03, $\x01\0"
7687 /* 8124 */ "fmovqne $\x02, $\x03, $\x01\0"
7688 /* 8143 */ "fmovqe $\x02, $\x03, $\x01\0"
7689 /* 8161 */ "fmovque $\x02, $\x03, $\x01\0"
7690 /* 8180 */ "fmovqge $\x02, $\x03, $\x01\0"
7691 /* 8199 */ "fmovquge $\x02, $\x03, $\x01\0"
7692 /* 8219 */ "fmovqle $\x02, $\x03, $\x01\0"
7693 /* 8238 */ "fmovqule $\x02, $\x03, $\x01\0"
7694 /* 8258 */ "fmovqo $\x02, $\x03, $\x01\0"
7695 /* 8276 */ "fmovsa $\x02, $\x03, $\x01\0"
7696 /* 8294 */ "fmovsn $\x02, $\x03, $\x01\0"
7697 /* 8312 */ "fmovsu $\x02, $\x03, $\x01\0"
7698 /* 8330 */ "fmovsg $\x02, $\x03, $\x01\0"
7699 /* 8348 */ "fmovsug $\x02, $\x03, $\x01\0"
7700 /* 8367 */ "fmovsl $\x02, $\x03, $\x01\0"
7701 /* 8385 */ "fmovsul $\x02, $\x03, $\x01\0"
7702 /* 8404 */ "fmovslg $\x02, $\x03, $\x01\0"
7703 /* 8423 */ "fmovsne $\x02, $\x03, $\x01\0"
7704 /* 8442 */ "fmovse $\x02, $\x03, $\x01\0"
7705 /* 8460 */ "fmovsue $\x02, $\x03, $\x01\0"
7706 /* 8479 */ "fmovsge $\x02, $\x03, $\x01\0"
7707 /* 8498 */ "fmovsuge $\x02, $\x03, $\x01\0"
7708 /* 8518 */ "fmovsle $\x02, $\x03, $\x01\0"
7709 /* 8537 */ "fmovsule $\x02, $\x03, $\x01\0"
7710 /* 8557 */ "fmovso $\x02, $\x03, $\x01\0"
7711 /* 8575 */ "mova $\x02, $\x03, $\x01\0"
7712 /* 8591 */ "movn $\x02, $\x03, $\x01\0"
7713 /* 8607 */ "movu $\x02, $\x03, $\x01\0"
7714 /* 8623 */ "movg $\x02, $\x03, $\x01\0"
7715 /* 8639 */ "movug $\x02, $\x03, $\x01\0"
7716 /* 8656 */ "movl $\x02, $\x03, $\x01\0"
7717 /* 8672 */ "movul $\x02, $\x03, $\x01\0"
7718 /* 8689 */ "movlg $\x02, $\x03, $\x01\0"
7719 /* 8706 */ "movne $\x02, $\x03, $\x01\0"
7720 /* 8723 */ "move $\x02, $\x03, $\x01\0"
7721 /* 8739 */ "movue $\x02, $\x03, $\x01\0"
7722 /* 8756 */ "movge $\x02, $\x03, $\x01\0"
7723 /* 8773 */ "movuge $\x02, $\x03, $\x01\0"
7724 /* 8791 */ "movle $\x02, $\x03, $\x01\0"
7725 /* 8808 */ "movule $\x02, $\x03, $\x01\0"
7726 /* 8826 */ "movo $\x02, $\x03, $\x01\0"
7727 /* 8842 */ "pause $\x03\0"
7728 ;
7729
7730#ifndef NDEBUG
7731 static struct SortCheck {
7732 SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
7733 assert(std::is_sorted(
7734 OpToPatterns.begin(), OpToPatterns.end(),
7735 [](const PatternsForOpcode &L, const PatternsForOpcode &R) {
7736 return L.Opcode < R.Opcode;
7737 }) &&
7738 "tablegen failed to sort opcode patterns");
7739 }
7740 } sortCheckVar(OpToPatterns);
7741#endif
7742
7743 AliasMatchingData M {
7744 .OpToPatterns: ArrayRef(OpToPatterns),
7745 .Patterns: ArrayRef(Patterns),
7746 .PatternConds: ArrayRef(Conds),
7747 .AsmStrings: StringRef(AsmStrings, std::size(AsmStrings)),
7748 .ValidateMCOperand: nullptr,
7749 };
7750 const char *AsmString = matchAliasPatterns(MI, STI: &STI, M);
7751 if (!AsmString) return false;
7752
7753 unsigned I = 0;
7754 while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
7755 AsmString[I] != '$' && AsmString[I] != '\0')
7756 ++I;
7757 OS << '\t' << StringRef(AsmString, I);
7758 if (AsmString[I] != '\0') {
7759 if (AsmString[I] == ' ' || AsmString[I] == '\t') {
7760 OS << '\t';
7761 ++I;
7762 }
7763 do {
7764 if (AsmString[I] == '$') {
7765 ++I;
7766 if (AsmString[I] == (char)0xff) {
7767 ++I;
7768 int OpIdx = AsmString[I++] - 1;
7769 int PrintMethodIdx = AsmString[I++] - 1;
7770 printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, STI, O&: OS);
7771 } else
7772 printOperand(MI, opNum: unsigned(AsmString[I++]) - 1, STI, OS);
7773 } else {
7774 OS << AsmString[I++];
7775 }
7776 } while (AsmString[I] != '\0');
7777 }
7778
7779 return true;
7780}
7781
7782void SparcInstPrinter::printCustomAliasOperand(
7783 const MCInst *MI, uint64_t Address, unsigned OpIdx,
7784 unsigned PrintMethodIdx,
7785 const MCSubtargetInfo &STI,
7786 raw_ostream &OS) {
7787 switch (PrintMethodIdx) {
7788 default:
7789 llvm_unreachable("Unknown PrintMethod kind");
7790 break;
7791 case 0:
7792 printCTILabel(MI, Address, OpNum: OpIdx, STI, O&: OS);
7793 break;
7794 }
7795}
7796
7797#endif // PRINT_ALIAS_INSTR
7798