1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Writer Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: Sparc.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10/// getMnemonic - This method is automatically generated by tablegen
11/// from the instruction set description.
12std::pair<const char *, uint64_t>
13SparcInstPrinter::getMnemonic(const MCInst &MI) const {
14
15#ifdef __GNUC__
16#pragma GCC diagnostic push
17#pragma GCC diagnostic ignored "-Woverlength-strings"
18#endif
19 static const char AsmStrs[] = {
20 /* 0 */ "fcmpd %fcc0, \000"
21 /* 14 */ "fcmpq %fcc0, \000"
22 /* 28 */ "fcmps %fcc0, \000"
23 /* 42 */ "rd %wim, \000"
24 /* 52 */ "rdpr %fq, \000"
25 /* 63 */ "rd %tbr, \000"
26 /* 73 */ "rd %psr, \000"
27 /* 83 */ "aes_kexpand0 \000"
28 /* 97 */ "aes_dround01 \000"
29 /* 111 */ "aes_eround01 \000"
30 /* 125 */ "fsrc1 \000"
31 /* 132 */ "aes_kexpand1 \000"
32 /* 146 */ "fandnot1 \000"
33 /* 156 */ "fnot1 \000"
34 /* 163 */ "fornot1 \000"
35 /* 172 */ "fsra32 \000"
36 /* 180 */ "fpsub32 \000"
37 /* 189 */ "fpadd32 \000"
38 /* 198 */ "edge32 \000"
39 /* 206 */ "fcmple32 \000"
40 /* 216 */ "fcmpne32 \000"
41 /* 226 */ "fpack32 \000"
42 /* 235 */ "cmask32 \000"
43 /* 244 */ "fsll32 \000"
44 /* 252 */ "fsrl32 \000"
45 /* 260 */ "fcmpeq32 \000"
46 /* 270 */ "fslas32 \000"
47 /* 279 */ "fcmpgt32 \000"
48 /* 289 */ "array32 \000"
49 /* 298 */ "fsrc2 \000"
50 /* 305 */ "aes_kexpand2 \000"
51 /* 319 */ "fandnot2 \000"
52 /* 329 */ "fnot2 \000"
53 /* 336 */ "fornot2 \000"
54 /* 345 */ "aes_dround23 \000"
55 /* 359 */ "aes_eround23 \000"
56 /* 373 */ "fpadd64 \000"
57 /* 382 */ "fsra16 \000"
58 /* 390 */ "fpsub16 \000"
59 /* 399 */ "fpadd16 \000"
60 /* 408 */ "edge16 \000"
61 /* 416 */ "fcmple16 \000"
62 /* 426 */ "fcmpne16 \000"
63 /* 436 */ "fpack16 \000"
64 /* 445 */ "cmask16 \000"
65 /* 454 */ "fsll16 \000"
66 /* 462 */ "fsrl16 \000"
67 /* 470 */ "fchksm16 \000"
68 /* 480 */ "fmean16 \000"
69 /* 489 */ "fcmpeq16 \000"
70 /* 499 */ "fslas16 \000"
71 /* 508 */ "fcmpgt16 \000"
72 /* 518 */ "fmul8x16 \000"
73 /* 528 */ "fmuld8ulx16 \000"
74 /* 541 */ "fmul8ulx16 \000"
75 /* 553 */ "fmuld8sux16 \000"
76 /* 566 */ "fmul8sux16 \000"
77 /* 578 */ "array16 \000"
78 /* 587 */ "edge8 \000"
79 /* 594 */ "cmask8 \000"
80 /* 602 */ "array8 \000"
81 /* 610 */ "!ADJCALLSTACKDOWN \000"
82 /* 629 */ "!ADJCALLSTACKUP \000"
83 /* 646 */ "stba \000"
84 /* 652 */ "stda \000"
85 /* 658 */ "stha \000"
86 /* 664 */ "stqa \000"
87 /* 670 */ "sra \000"
88 /* 675 */ "faligndata \000"
89 /* 687 */ "sta \000"
90 /* 692 */ "stxa \000"
91 /* 698 */ "stb \000"
92 /* 703 */ "sub \000"
93 /* 708 */ "crc32c \000"
94 /* 716 */ "smac \000"
95 /* 722 */ "umac \000"
96 /* 728 */ "tsubcc \000"
97 /* 736 */ "addxccc \000"
98 /* 745 */ "taddcc \000"
99 /* 753 */ "andcc \000"
100 /* 760 */ "smulcc \000"
101 /* 768 */ "umulcc \000"
102 /* 776 */ "andncc \000"
103 /* 784 */ "orncc \000"
104 /* 791 */ "xnorcc \000"
105 /* 799 */ "xorcc \000"
106 /* 806 */ "mulscc \000"
107 /* 814 */ "sdivcc \000"
108 /* 822 */ "udivcc \000"
109 /* 830 */ "subxcc \000"
110 /* 838 */ "addxcc \000"
111 /* 846 */ "popc \000"
112 /* 852 */ "addxc \000"
113 /* 859 */ "fsubd \000"
114 /* 866 */ "fhsubd \000"
115 /* 874 */ "fmsubd \000"
116 /* 882 */ "fnmsubd \000"
117 /* 891 */ "add \000"
118 /* 896 */ "faddd \000"
119 /* 903 */ "fhaddd \000"
120 /* 911 */ "fnhaddd \000"
121 /* 920 */ "fmaddd \000"
122 /* 928 */ "fnmaddd \000"
123 /* 937 */ "fnaddd \000"
124 /* 945 */ "fcmped \000"
125 /* 953 */ "fnegd \000"
126 /* 960 */ "fmuld \000"
127 /* 967 */ "fnmuld \000"
128 /* 975 */ "fsmuld \000"
129 /* 983 */ "fnsmuld \000"
130 /* 992 */ "fand \000"
131 /* 998 */ "fnand \000"
132 /* 1005 */ "fexpand \000"
133 /* 1014 */ "des_kexpand \000"
134 /* 1027 */ "des_round \000"
135 /* 1038 */ "fitod \000"
136 /* 1045 */ "fqtod \000"
137 /* 1052 */ "fstod \000"
138 /* 1059 */ "fxtod \000"
139 /* 1066 */ "movxtod \000"
140 /* 1075 */ "fcmpd \000"
141 /* 1082 */ "flcmpd \000"
142 /* 1090 */ "rd \000"
143 /* 1094 */ "fabsd \000"
144 /* 1101 */ "fsqrtd \000"
145 /* 1109 */ "std \000"
146 /* 1114 */ "fdivd \000"
147 /* 1121 */ "fmovd \000"
148 /* 1128 */ "fpmerge \000"
149 /* 1137 */ "bshuffle \000"
150 /* 1147 */ "fone \000"
151 /* 1153 */ "restore \000"
152 /* 1162 */ "save \000"
153 /* 1168 */ "camellia_f \000"
154 /* 1180 */ "flush \000"
155 /* 1187 */ "sth \000"
156 /* 1192 */ "sethi \000"
157 /* 1199 */ "fpmaddxhi \000"
158 /* 1210 */ "umulxhi \000"
159 /* 1219 */ "xmulxhi \000"
160 /* 1228 */ "camellia_fli \000"
161 /* 1242 */ "fdtoi \000"
162 /* 1249 */ "fqtoi \000"
163 /* 1256 */ "fstoi \000"
164 /* 1263 */ "bmask \000"
165 /* 1270 */ "edge32l \000"
166 /* 1279 */ "edge16l \000"
167 /* 1288 */ "edge8l \000"
168 /* 1296 */ "aes_dround01_l \000"
169 /* 1312 */ "aes_eround01_l \000"
170 /* 1328 */ "aes_dround23_l \000"
171 /* 1344 */ "aes_eround23_l \000"
172 /* 1360 */ "fmul8x16al \000"
173 /* 1372 */ "camellia_fl \000"
174 /* 1385 */ "call \000"
175 /* 1391 */ "sll \000"
176 /* 1396 */ "jmpl \000"
177 /* 1402 */ "alignaddrl \000"
178 /* 1414 */ "srl \000"
179 /* 1419 */ "mpmul \000"
180 /* 1426 */ "smul \000"
181 /* 1432 */ "montmul \000"
182 /* 1441 */ "umul \000"
183 /* 1447 */ "siam \000"
184 /* 1453 */ "edge32n \000"
185 /* 1462 */ "edge16n \000"
186 /* 1471 */ "edge8n \000"
187 /* 1479 */ "andn \000"
188 /* 1485 */ "edge32ln \000"
189 /* 1495 */ "edge16ln \000"
190 /* 1505 */ "edge8ln \000"
191 /* 1514 */ "orn \000"
192 /* 1519 */ "pdistn \000"
193 /* 1527 */ "fzero \000"
194 /* 1534 */ "des_ip \000"
195 /* 1542 */ "des_iip \000"
196 /* 1551 */ "unimp \000"
197 /* 1558 */ "jmp \000"
198 /* 1563 */ "fsubq \000"
199 /* 1570 */ "faddq \000"
200 /* 1577 */ "fcmpeq \000"
201 /* 1585 */ "fnegq \000"
202 /* 1592 */ "fdmulq \000"
203 /* 1600 */ "fmulq \000"
204 /* 1607 */ "fdtoq \000"
205 /* 1614 */ "fitoq \000"
206 /* 1621 */ "fstoq \000"
207 /* 1628 */ "fxtoq \000"
208 /* 1635 */ "fcmpq \000"
209 /* 1642 */ "fabsq \000"
210 /* 1649 */ "fsqrtq \000"
211 /* 1657 */ "stq \000"
212 /* 1662 */ "fdivq \000"
213 /* 1669 */ "fmovq \000"
214 /* 1676 */ "membar \000"
215 /* 1684 */ "alignaddr \000"
216 /* 1695 */ "sir \000"
217 /* 1700 */ "for \000"
218 /* 1705 */ "fnor \000"
219 /* 1711 */ "fxnor \000"
220 /* 1718 */ "fxor \000"
221 /* 1724 */ "rdpr \000"
222 /* 1730 */ "wrpr \000"
223 /* 1736 */ "montsqr \000"
224 /* 1745 */ "pwr \000"
225 /* 1750 */ "fsrc1s \000"
226 /* 1758 */ "fandnot1s \000"
227 /* 1769 */ "fnot1s \000"
228 /* 1777 */ "fornot1s \000"
229 /* 1787 */ "fpsub32s \000"
230 /* 1797 */ "fpadd32s \000"
231 /* 1807 */ "fsrc2s \000"
232 /* 1815 */ "fandnot2s \000"
233 /* 1826 */ "fnot2s \000"
234 /* 1834 */ "fornot2s \000"
235 /* 1844 */ "fpsub16s \000"
236 /* 1854 */ "fpadd16s \000"
237 /* 1864 */ "fsubs \000"
238 /* 1871 */ "fhsubs \000"
239 /* 1879 */ "fmsubs \000"
240 /* 1887 */ "fnmsubs \000"
241 /* 1896 */ "fadds \000"
242 /* 1903 */ "fhadds \000"
243 /* 1911 */ "fnhadds \000"
244 /* 1920 */ "fmadds \000"
245 /* 1928 */ "fnmadds \000"
246 /* 1937 */ "fnadds \000"
247 /* 1945 */ "fands \000"
248 /* 1952 */ "fnands \000"
249 /* 1960 */ "fones \000"
250 /* 1967 */ "fcmpes \000"
251 /* 1975 */ "fnegs \000"
252 /* 1982 */ "fmuls \000"
253 /* 1989 */ "fnmuls \000"
254 /* 1997 */ "fzeros \000"
255 /* 2005 */ "fdtos \000"
256 /* 2012 */ "fitos \000"
257 /* 2019 */ "fqtos \000"
258 /* 2026 */ "movwtos \000"
259 /* 2035 */ "fxtos \000"
260 /* 2042 */ "fcmps \000"
261 /* 2049 */ "flcmps \000"
262 /* 2057 */ "fors \000"
263 /* 2063 */ "fnors \000"
264 /* 2070 */ "fxnors \000"
265 /* 2078 */ "fxors \000"
266 /* 2085 */ "fabss \000"
267 /* 2092 */ "fsqrts \000"
268 /* 2100 */ "fdivs \000"
269 /* 2107 */ "fmovs \000"
270 /* 2114 */ "set \000"
271 /* 2119 */ "lzcnt \000"
272 /* 2126 */ "pdist \000"
273 /* 2133 */ "rett \000"
274 /* 2139 */ "fmul8x16au \000"
275 /* 2151 */ "sdiv \000"
276 /* 2157 */ "udiv \000"
277 /* 2163 */ "tsubcctv \000"
278 /* 2173 */ "taddcctv \000"
279 /* 2183 */ "movstosw \000"
280 /* 2193 */ "setsw \000"
281 /* 2200 */ "movstouw \000"
282 /* 2210 */ "srax \000"
283 /* 2216 */ "subx \000"
284 /* 2222 */ "fpmaddx \000"
285 /* 2231 */ "fpackfix \000"
286 /* 2241 */ "sllx \000"
287 /* 2247 */ "srlx \000"
288 /* 2253 */ "xmulx \000"
289 /* 2260 */ "fdtox \000"
290 /* 2267 */ "movdtox \000"
291 /* 2276 */ "fqtox \000"
292 /* 2283 */ "fstox \000"
293 /* 2290 */ "setx \000"
294 /* 2296 */ "stx \000"
295 /* 2301 */ "sdivx \000"
296 /* 2308 */ "udivx \000"
297 /* 2315 */ "; SELECT_CC_DFP_FCC PSEUDO!\000"
298 /* 2343 */ "; SELECT_CC_QFP_FCC PSEUDO!\000"
299 /* 2371 */ "; SELECT_CC_FP_FCC PSEUDO!\000"
300 /* 2398 */ "; SELECT_CC_Int_FCC PSEUDO!\000"
301 /* 2426 */ "; SELECT_CC_DFP_ICC PSEUDO!\000"
302 /* 2454 */ "; SELECT_CC_QFP_ICC PSEUDO!\000"
303 /* 2482 */ "; SELECT_CC_FP_ICC PSEUDO!\000"
304 /* 2509 */ "; SELECT_CC_Int_ICC PSEUDO!\000"
305 /* 2537 */ "; SELECT_CC_DFP_XCC PSEUDO!\000"
306 /* 2565 */ "; SELECT_CC_QFP_XCC PSEUDO!\000"
307 /* 2593 */ "; SELECT_CC_FP_XCC PSEUDO!\000"
308 /* 2620 */ "; SELECT_CC_Int_XCC PSEUDO!\000"
309 /* 2648 */ "jmp %i7+\000"
310 /* 2657 */ "jmp %o7+\000"
311 /* 2666 */ "# XRay Function Patchable RET.\000"
312 /* 2697 */ "# XRay Typed Event Log.\000"
313 /* 2721 */ "# XRay Custom Event Log.\000"
314 /* 2746 */ "# XRay Function Enter.\000"
315 /* 2769 */ "# XRay Tail Call Exit.\000"
316 /* 2792 */ "# XRay Function Exit.\000"
317 /* 2814 */ "flush %g0\000"
318 /* 2824 */ "ta 1\000"
319 /* 2829 */ "sha1\000"
320 /* 2834 */ "sha512\000"
321 /* 2841 */ "ta 3\000"
322 /* 2846 */ "ta 5\000"
323 /* 2851 */ "md5\000"
324 /* 2855 */ "sha256\000"
325 /* 2862 */ "LIFETIME_END\000"
326 /* 2875 */ "PSEUDO_PROBE\000"
327 /* 2888 */ "BUNDLE\000"
328 /* 2895 */ "FAKE_USE\000"
329 /* 2904 */ "DBG_VALUE\000"
330 /* 2914 */ "DBG_INSTR_REF\000"
331 /* 2928 */ "DBG_PHI\000"
332 /* 2936 */ "DBG_LABEL\000"
333 /* 2946 */ "!V8BAR\000"
334 /* 2953 */ "LIFETIME_START\000"
335 /* 2968 */ "DBG_VALUE_LIST\000"
336 /* 2983 */ "std %cq, [\000"
337 /* 2994 */ "std %fq, [\000"
338 /* 3005 */ "st %csr, [\000"
339 /* 3016 */ "st %fsr, [\000"
340 /* 3027 */ "stx %fsr, [\000"
341 /* 3039 */ "ldsba [\000"
342 /* 3047 */ "lduba [\000"
343 /* 3055 */ "ldstuba [\000"
344 /* 3065 */ "ldda [\000"
345 /* 3072 */ "lda [\000"
346 /* 3078 */ "prefetcha [\000"
347 /* 3090 */ "ldsha [\000"
348 /* 3098 */ "lduha [\000"
349 /* 3106 */ "swapa [\000"
350 /* 3114 */ "ldqa [\000"
351 /* 3121 */ "casa [\000"
352 /* 3128 */ "ldswa [\000"
353 /* 3136 */ "ldxa [\000"
354 /* 3143 */ "casxa [\000"
355 /* 3151 */ "ldsb [\000"
356 /* 3158 */ "ldub [\000"
357 /* 3165 */ "ldstub [\000"
358 /* 3174 */ "ldd [\000"
359 /* 3180 */ "ld [\000"
360 /* 3185 */ "prefetch [\000"
361 /* 3196 */ "ldsh [\000"
362 /* 3203 */ "lduh [\000"
363 /* 3210 */ "swap [\000"
364 /* 3217 */ "ldq [\000"
365 /* 3223 */ "ldsw [\000"
366 /* 3230 */ "ldx [\000"
367 /* 3236 */ "cb\000"
368 /* 3239 */ "fb\000"
369 /* 3242 */ "cwb\000"
370 /* 3246 */ "cxb\000"
371 /* 3250 */ "restored\000"
372 /* 3259 */ "saved\000"
373 /* 3265 */ "fmovrd\000"
374 /* 3272 */ "fmovd\000"
375 /* 3278 */ "done\000"
376 /* 3283 */ "# FEntry call\000"
377 /* 3297 */ "allclean\000"
378 /* 3306 */ "shutdown\000"
379 /* 3315 */ "nop\000"
380 /* 3319 */ "fmovrq\000"
381 /* 3326 */ "fmovq\000"
382 /* 3332 */ "stbar\000"
383 /* 3338 */ "br\000"
384 /* 3341 */ "movr\000"
385 /* 3346 */ "fmovrs\000"
386 /* 3353 */ "fmovs\000"
387 /* 3359 */ "t\000"
388 /* 3361 */ "mov\000"
389 /* 3365 */ "flushw\000"
390 /* 3372 */ "normalw\000"
391 /* 3380 */ "invalw\000"
392 /* 3387 */ "otherw\000"
393 /* 3394 */ "retry\000"
394};
395#ifdef __GNUC__
396#pragma GCC diagnostic pop
397#endif
398
399 static const uint32_t OpInfo0[] = {
400 0U, // PHI
401 0U, // INLINEASM
402 0U, // INLINEASM_BR
403 0U, // CFI_INSTRUCTION
404 0U, // EH_LABEL
405 0U, // GC_LABEL
406 0U, // ANNOTATION_LABEL
407 0U, // KILL
408 0U, // EXTRACT_SUBREG
409 0U, // INSERT_SUBREG
410 0U, // IMPLICIT_DEF
411 0U, // INIT_UNDEF
412 0U, // SUBREG_TO_REG
413 0U, // COPY_TO_REGCLASS
414 2905U, // DBG_VALUE
415 2969U, // DBG_VALUE_LIST
416 2915U, // DBG_INSTR_REF
417 2929U, // DBG_PHI
418 2937U, // DBG_LABEL
419 0U, // REG_SEQUENCE
420 0U, // COPY
421 0U, // COPY_LANEMASK
422 2889U, // BUNDLE
423 2954U, // LIFETIME_START
424 2863U, // LIFETIME_END
425 2876U, // PSEUDO_PROBE
426 0U, // ARITH_FENCE
427 0U, // STACKMAP
428 3284U, // FENTRY_CALL
429 0U, // PATCHPOINT
430 0U, // LOAD_STACK_GUARD
431 0U, // PREALLOCATED_SETUP
432 0U, // PREALLOCATED_ARG
433 0U, // STATEPOINT
434 0U, // LOCAL_ESCAPE
435 0U, // FAULTING_OP
436 0U, // PATCHABLE_OP
437 2747U, // PATCHABLE_FUNCTION_ENTER
438 2667U, // PATCHABLE_RET
439 2793U, // PATCHABLE_FUNCTION_EXIT
440 2770U, // PATCHABLE_TAIL_CALL
441 2722U, // PATCHABLE_EVENT_CALL
442 2698U, // PATCHABLE_TYPED_EVENT_CALL
443 0U, // ICALL_BRANCH_FUNNEL
444 2896U, // FAKE_USE
445 0U, // MEMBARRIER
446 0U, // JUMP_TABLE_DEBUG_INFO
447 0U, // RELOC_NONE
448 0U, // CONVERGENCECTRL_ENTRY
449 0U, // CONVERGENCECTRL_ANCHOR
450 0U, // CONVERGENCECTRL_LOOP
451 0U, // CONVERGENCECTRL_GLUE
452 0U, // G_ASSERT_SEXT
453 0U, // G_ASSERT_ZEXT
454 0U, // G_ASSERT_ALIGN
455 0U, // G_ADD
456 0U, // G_SUB
457 0U, // G_MUL
458 0U, // G_SDIV
459 0U, // G_UDIV
460 0U, // G_SREM
461 0U, // G_UREM
462 0U, // G_SDIVREM
463 0U, // G_UDIVREM
464 0U, // G_AND
465 0U, // G_OR
466 0U, // G_XOR
467 0U, // G_ABDS
468 0U, // G_ABDU
469 0U, // G_UAVGFLOOR
470 0U, // G_UAVGCEIL
471 0U, // G_SAVGFLOOR
472 0U, // G_SAVGCEIL
473 0U, // G_IMPLICIT_DEF
474 0U, // G_PHI
475 0U, // G_FRAME_INDEX
476 0U, // G_GLOBAL_VALUE
477 0U, // G_PTRAUTH_GLOBAL_VALUE
478 0U, // G_CONSTANT_POOL
479 0U, // G_EXTRACT
480 0U, // G_UNMERGE_VALUES
481 0U, // G_INSERT
482 0U, // G_MERGE_VALUES
483 0U, // G_BUILD_VECTOR
484 0U, // G_BUILD_VECTOR_TRUNC
485 0U, // G_CONCAT_VECTORS
486 0U, // G_PTRTOINT
487 0U, // G_INTTOPTR
488 0U, // G_BITCAST
489 0U, // G_FREEZE
490 0U, // G_CONSTANT_FOLD_BARRIER
491 0U, // G_INTRINSIC_FPTRUNC_ROUND
492 0U, // G_INTRINSIC_TRUNC
493 0U, // G_INTRINSIC_ROUND
494 0U, // G_INTRINSIC_LRINT
495 0U, // G_INTRINSIC_LLRINT
496 0U, // G_INTRINSIC_ROUNDEVEN
497 0U, // G_READCYCLECOUNTER
498 0U, // G_READSTEADYCOUNTER
499 0U, // G_LOAD
500 0U, // G_SEXTLOAD
501 0U, // G_ZEXTLOAD
502 0U, // G_FPEXTLOAD
503 0U, // G_INDEXED_LOAD
504 0U, // G_INDEXED_SEXTLOAD
505 0U, // G_INDEXED_ZEXTLOAD
506 0U, // G_STORE
507 0U, // G_FPTRUNCSTORE
508 0U, // G_INDEXED_STORE
509 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
510 0U, // G_ATOMIC_CMPXCHG
511 0U, // G_ATOMICRMW_XCHG
512 0U, // G_ATOMICRMW_ADD
513 0U, // G_ATOMICRMW_SUB
514 0U, // G_ATOMICRMW_AND
515 0U, // G_ATOMICRMW_NAND
516 0U, // G_ATOMICRMW_OR
517 0U, // G_ATOMICRMW_XOR
518 0U, // G_ATOMICRMW_MAX
519 0U, // G_ATOMICRMW_MIN
520 0U, // G_ATOMICRMW_UMAX
521 0U, // G_ATOMICRMW_UMIN
522 0U, // G_ATOMICRMW_FADD
523 0U, // G_ATOMICRMW_FSUB
524 0U, // G_ATOMICRMW_FMAX
525 0U, // G_ATOMICRMW_FMIN
526 0U, // G_ATOMICRMW_FMAXIMUM
527 0U, // G_ATOMICRMW_FMINIMUM
528 0U, // G_ATOMICRMW_FMAXIMUMNUM
529 0U, // G_ATOMICRMW_FMINIMUMNUM
530 0U, // G_ATOMICRMW_UINC_WRAP
531 0U, // G_ATOMICRMW_UDEC_WRAP
532 0U, // G_ATOMICRMW_USUB_COND
533 0U, // G_ATOMICRMW_USUB_SAT
534 0U, // G_FENCE
535 0U, // G_PREFETCH
536 0U, // G_BRCOND
537 0U, // G_BRINDIRECT
538 0U, // G_INVOKE_REGION_START
539 0U, // G_INTRINSIC
540 0U, // G_INTRINSIC_W_SIDE_EFFECTS
541 0U, // G_INTRINSIC_CONVERGENT
542 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
543 0U, // G_ANYEXT
544 0U, // G_TRUNC
545 0U, // G_TRUNC_SSAT_S
546 0U, // G_TRUNC_SSAT_U
547 0U, // G_TRUNC_USAT_U
548 0U, // G_CONSTANT
549 0U, // G_FCONSTANT
550 0U, // G_VASTART
551 0U, // G_VAARG
552 0U, // G_SEXT
553 0U, // G_SEXT_INREG
554 0U, // G_ZEXT
555 0U, // G_SHL
556 0U, // G_LSHR
557 0U, // G_ASHR
558 0U, // G_FSHL
559 0U, // G_FSHR
560 0U, // G_ROTR
561 0U, // G_ROTL
562 0U, // G_ICMP
563 0U, // G_FCMP
564 0U, // G_SCMP
565 0U, // G_UCMP
566 0U, // G_SELECT
567 0U, // G_UADDO
568 0U, // G_UADDE
569 0U, // G_USUBO
570 0U, // G_USUBE
571 0U, // G_SADDO
572 0U, // G_SADDE
573 0U, // G_SSUBO
574 0U, // G_SSUBE
575 0U, // G_UMULO
576 0U, // G_SMULO
577 0U, // G_UMULH
578 0U, // G_SMULH
579 0U, // G_UADDSAT
580 0U, // G_SADDSAT
581 0U, // G_USUBSAT
582 0U, // G_SSUBSAT
583 0U, // G_USHLSAT
584 0U, // G_SSHLSAT
585 0U, // G_SMULFIX
586 0U, // G_UMULFIX
587 0U, // G_SMULFIXSAT
588 0U, // G_UMULFIXSAT
589 0U, // G_SDIVFIX
590 0U, // G_UDIVFIX
591 0U, // G_SDIVFIXSAT
592 0U, // G_UDIVFIXSAT
593 0U, // G_FADD
594 0U, // G_FSUB
595 0U, // G_FMUL
596 0U, // G_FMA
597 0U, // G_FMAD
598 0U, // G_FDIV
599 0U, // G_FREM
600 0U, // G_FMODF
601 0U, // G_FPOW
602 0U, // G_FPOWI
603 0U, // G_FEXP
604 0U, // G_FEXP2
605 0U, // G_FEXP10
606 0U, // G_FLOG
607 0U, // G_FLOG2
608 0U, // G_FLOG10
609 0U, // G_FLDEXP
610 0U, // G_FFREXP
611 0U, // G_FNEG
612 0U, // G_FPEXT
613 0U, // G_FPTRUNC
614 0U, // G_FPTOSI
615 0U, // G_FPTOUI
616 0U, // G_SITOFP
617 0U, // G_UITOFP
618 0U, // G_FPTOSI_SAT
619 0U, // G_FPTOUI_SAT
620 0U, // G_FABS
621 0U, // G_FCOPYSIGN
622 0U, // G_IS_FPCLASS
623 0U, // G_FCANONICALIZE
624 0U, // G_FMINNUM
625 0U, // G_FMAXNUM
626 0U, // G_FMINNUM_IEEE
627 0U, // G_FMAXNUM_IEEE
628 0U, // G_FMINIMUM
629 0U, // G_FMAXIMUM
630 0U, // G_FMINIMUMNUM
631 0U, // G_FMAXIMUMNUM
632 0U, // G_GET_FPENV
633 0U, // G_SET_FPENV
634 0U, // G_RESET_FPENV
635 0U, // G_GET_FPMODE
636 0U, // G_SET_FPMODE
637 0U, // G_RESET_FPMODE
638 0U, // G_GET_ROUNDING
639 0U, // G_SET_ROUNDING
640 0U, // G_PTR_ADD
641 0U, // G_PTRMASK
642 0U, // G_SMIN
643 0U, // G_SMAX
644 0U, // G_UMIN
645 0U, // G_UMAX
646 0U, // G_ABS
647 0U, // G_LROUND
648 0U, // G_LLROUND
649 0U, // G_BR
650 0U, // G_BRJT
651 0U, // G_VSCALE
652 0U, // G_INSERT_SUBVECTOR
653 0U, // G_EXTRACT_SUBVECTOR
654 0U, // G_INSERT_VECTOR_ELT
655 0U, // G_EXTRACT_VECTOR_ELT
656 0U, // G_SHUFFLE_VECTOR
657 0U, // G_SPLAT_VECTOR
658 0U, // G_STEP_VECTOR
659 0U, // G_VECTOR_COMPRESS
660 0U, // G_CTTZ
661 0U, // G_CTTZ_ZERO_POISON
662 0U, // G_CTLZ
663 0U, // G_CTLZ_ZERO_POISON
664 0U, // G_CTLS
665 0U, // G_CTPOP
666 0U, // G_BSWAP
667 0U, // G_BITREVERSE
668 0U, // G_CLMUL
669 0U, // G_FCEIL
670 0U, // G_FCOS
671 0U, // G_FSIN
672 0U, // G_FSINCOS
673 0U, // G_FTAN
674 0U, // G_FACOS
675 0U, // G_FASIN
676 0U, // G_FATAN
677 0U, // G_FATAN2
678 0U, // G_FCOSH
679 0U, // G_FSINH
680 0U, // G_FTANH
681 0U, // G_FSQRT
682 0U, // G_FFLOOR
683 0U, // G_FRINT
684 0U, // G_FNEARBYINT
685 0U, // G_ADDRSPACE_CAST
686 0U, // G_BLOCK_ADDR
687 0U, // G_JUMP_TABLE
688 0U, // G_DYN_STACKALLOC
689 0U, // G_STACKSAVE
690 0U, // G_STACKRESTORE
691 0U, // G_STRICT_FADD
692 0U, // G_STRICT_FSUB
693 0U, // G_STRICT_FMUL
694 0U, // G_STRICT_FDIV
695 0U, // G_STRICT_FREM
696 0U, // G_STRICT_FMA
697 0U, // G_STRICT_FSQRT
698 0U, // G_STRICT_FLDEXP
699 0U, // G_STRICT_FCMP
700 0U, // G_STRICT_FCMPS
701 0U, // G_READ_REGISTER
702 0U, // G_WRITE_REGISTER
703 0U, // G_MEMCPY
704 0U, // G_MEMCPY_INLINE
705 0U, // G_MEMMOVE
706 0U, // G_MEMSET
707 0U, // G_BZERO
708 0U, // G_MEMSET_INLINE
709 0U, // G_TRAP
710 0U, // G_DEBUGTRAP
711 0U, // G_UBSANTRAP
712 0U, // G_VECREDUCE_SEQ_FADD
713 0U, // G_VECREDUCE_SEQ_FMUL
714 0U, // G_VECREDUCE_FADD
715 0U, // G_VECREDUCE_FMUL
716 0U, // G_VECREDUCE_FMAX
717 0U, // G_VECREDUCE_FMIN
718 0U, // G_VECREDUCE_FMAXIMUM
719 0U, // G_VECREDUCE_FMINIMUM
720 0U, // G_VECREDUCE_FMAXIMUMNUM
721 0U, // G_VECREDUCE_FMINIMUMNUM
722 0U, // G_VECREDUCE_ADD
723 0U, // G_VECREDUCE_MUL
724 0U, // G_VECREDUCE_AND
725 0U, // G_VECREDUCE_OR
726 0U, // G_VECREDUCE_XOR
727 0U, // G_VECREDUCE_SMAX
728 0U, // G_VECREDUCE_SMIN
729 0U, // G_VECREDUCE_UMAX
730 0U, // G_VECREDUCE_UMIN
731 0U, // G_SBFX
732 0U, // G_UBFX
733 4707U, // ADJCALLSTACKDOWN
734 70262U, // ADJCALLSTACKUP
735 8206U, // GETPCX
736 2316U, // SELECT_CC_DFP_FCC
737 2427U, // SELECT_CC_DFP_ICC
738 2538U, // SELECT_CC_DFP_XCC
739 2372U, // SELECT_CC_FP_FCC
740 2483U, // SELECT_CC_FP_ICC
741 2594U, // SELECT_CC_FP_XCC
742 2399U, // SELECT_CC_Int_FCC
743 2510U, // SELECT_CC_Int_ICC
744 2621U, // SELECT_CC_Int_XCC
745 2344U, // SELECT_CC_QFP_FCC
746 2455U, // SELECT_CC_QFP_ICC
747 2566U, // SELECT_CC_QFP_XCC
748 2111555U, // SET
749 2111634U, // SETSW
750 20986099U, // SETX
751 2947U, // V8BAR
752 20984555U, // ADDCCri
753 20984555U, // ADDCCrr
754 20986034U, // ADDCri
755 20986034U, // ADDCrr
756 20984647U, // ADDEri
757 20984647U, // ADDErr
758 20984661U, // ADDXC
759 20984545U, // ADDXCCC
760 20984700U, // ADDri
761 20984700U, // ADDrr
762 692072546U, // AES_DROUND01
763 692073745U, // AES_DROUND01_LAST
764 692072794U, // AES_DROUND23
765 692073777U, // AES_DROUND23_LAST
766 692072560U, // AES_EROUND01
767 692073761U, // AES_EROUND01_LAST
768 692072808U, // AES_EROUND23
769 692073793U, // AES_EROUND23_LAST
770 20983892U, // AES_KEXPAND0
771 692072581U, // AES_KEXPAND1
772 20984114U, // AES_KEXPAND2
773 20985493U, // ALIGNADDR
774 20985211U, // ALIGNADDRL
775 3298U, // ALLCLEAN
776 20984562U, // ANDCCri
777 20984562U, // ANDCCrr
778 20984585U, // ANDNCCri
779 20984585U, // ANDNCCrr
780 20985288U, // ANDNri
781 20985288U, // ANDNrr
782 20984802U, // ANDri
783 20984802U, // ANDrr
784 20984387U, // ARRAY16
785 20984098U, // ARRAY32
786 20984411U, // ARRAY8
787 82569U, // BA
788 6446246U, // BCOND
789 6511782U, // BCONDA
790 91671U, // BINDri
791 91671U, // BINDrr
792 20985072U, // BMASK
793 289561768U, // BPFCC
794 289627304U, // BPFCCA
795 285864U, // BPFCCANT
796 351400U, // BPFCCNT
797 6708390U, // BPICC
798 482470U, // BPICCA
799 548006U, // BPICCANT
800 613542U, // BPICCNT
801 289561867U, // BPR
802 289627403U, // BPRA
803 285963U, // BPRANT
804 351499U, // BPRNT
805 6970534U, // BPXCC
806 744614U, // BPXCCA
807 810150U, // BPXCCANT
808 875686U, // BPXCCNT
809 20984946U, // BSHUFFLE
810 83306U, // CALL
811 17770U, // CALLi
812 91498U, // CALLri
813 4220266U, // CALLrii
814 91498U, // CALLrr
815 4220266U, // CALLrri
816 692073617U, // CAMELLIA_F
817 20985181U, // CAMELLIA_FL
818 20985037U, // CAMELLIA_FLI
819 21904434U, // CASAri
820 9387058U, // CASArr
821 21904456U, // CASXAri
822 9387080U, // CASXArr
823 70078U, // CMASK16
824 69868U, // CMASK32
825 70227U, // CMASK8
826 6446245U, // CPBCOND
827 6511781U, // CPBCONDA
828 20984517U, // CRC32C
829 1765956779U, // CWBCONDri
830 1765956779U, // CWBCONDrr
831 1765956783U, // CXBCONDri
832 1765956783U, // CXBCONDrr
833 2110983U, // DES_IIP
834 2110975U, // DES_IP
835 20984823U, // DES_KEXPAND
836 692073476U, // DES_ROUND
837 3279U, // DONE
838 20984217U, // EDGE16
839 20985088U, // EDGE16L
840 20985304U, // EDGE16LN
841 20985271U, // EDGE16N
842 20984007U, // EDGE32
843 20985079U, // EDGE32L
844 20985294U, // EDGE32LN
845 20985262U, // EDGE32N
846 20984396U, // EDGE8
847 20985097U, // EDGE8L
848 20985314U, // EDGE8LN
849 20985280U, // EDGE8N
850 2110535U, // FABSD
851 2111083U, // FABSQ
852 2111526U, // FABSS
853 20984705U, // FADDD
854 20985379U, // FADDQ
855 20985705U, // FADDS
856 20984484U, // FALIGNADATA
857 20984801U, // FAND
858 20983955U, // FANDNOT1
859 20985567U, // FANDNOT1S
860 20984128U, // FANDNOT2
861 20985624U, // FANDNOT2S
862 20985754U, // FANDS
863 6446248U, // FBCOND
864 6511784U, // FBCONDA
865 1072296U, // FBCONDA_V9
866 7429288U, // FBCOND_V9
867 20984279U, // FCHKSM16
868 5172U, // FCMPD
869 4097U, // FCMPD_V9
870 20984298U, // FCMPEQ16
871 20984069U, // FCMPEQ32
872 20984317U, // FCMPGT16
873 20984088U, // FCMPGT32
874 20984225U, // FCMPLE16
875 20984015U, // FCMPLE32
876 20984235U, // FCMPNE16
877 20984025U, // FCMPNE32
878 5732U, // FCMPQ
879 4111U, // FCMPQ_V9
880 6139U, // FCMPS
881 4125U, // FCMPS_V9
882 20984923U, // FDIVD
883 20985471U, // FDIVQ
884 20985909U, // FDIVS
885 20985401U, // FDMULQ
886 2110683U, // FDTOI
887 2111048U, // FDTOQ
888 2111446U, // FDTOS
889 2111701U, // FDTOX
890 2110446U, // FEXPAND
891 20984712U, // FHADDD
892 20985712U, // FHADDS
893 20984675U, // FHSUBD
894 20985680U, // FHSUBS
895 2110479U, // FITOD
896 2111055U, // FITOQ
897 2111453U, // FITOS
898 419435579U, // FLCMPD
899 419436546U, // FLCMPS
900 2815U, // FLUSH
901 3366U, // FLUSHW
902 91293U, // FLUSHri
903 91293U, // FLUSHrr
904 692073369U, // FMADDD
905 692074369U, // FMADDS
906 20984289U, // FMEAN16
907 2110562U, // FMOVD
908 17923273U, // FMOVD_FCC
909 17202377U, // FMOVD_ICC
910 17464521U, // FMOVD_XCC
911 2111110U, // FMOVQ
912 17923327U, // FMOVQ_FCC
913 17202431U, // FMOVQ_ICC
914 17464575U, // FMOVQ_XCC
915 36034U, // FMOVRD
916 36088U, // FMOVRQ
917 36115U, // FMOVRS
918 2111548U, // FMOVS
919 17923354U, // FMOVS_FCC
920 17202458U, // FMOVS_ICC
921 17464602U, // FMOVS_XCC
922 692073323U, // FMSUBD
923 692074328U, // FMSUBS
924 20984375U, // FMUL8SUX16
925 20984350U, // FMUL8ULX16
926 20984327U, // FMUL8X16
927 20985169U, // FMUL8X16AL
928 20985948U, // FMUL8X16AU
929 20984769U, // FMULD
930 20984362U, // FMULD8SUX16
931 20984337U, // FMULD8ULX16
932 20985409U, // FMULQ
933 20985791U, // FMULS
934 20984746U, // FNADDD
935 20985746U, // FNADDS
936 20984807U, // FNAND
937 20985761U, // FNANDS
938 2110394U, // FNEGD
939 2111026U, // FNEGQ
940 2111416U, // FNEGS
941 20984720U, // FNHADDD
942 20985720U, // FNHADDS
943 692073377U, // FNMADDD
944 692074377U, // FNMADDS
945 692073331U, // FNMSUBD
946 692074336U, // FNMSUBS
947 20984776U, // FNMULD
948 20985798U, // FNMULS
949 20985514U, // FNOR
950 20985872U, // FNORS
951 2109597U, // FNOT1
952 2111210U, // FNOT1S
953 2109770U, // FNOT2
954 2111267U, // FNOT2S
955 20984792U, // FNSMULD
956 70780U, // FONE
957 71593U, // FONES
958 20985509U, // FOR
959 20983972U, // FORNOT1
960 20985586U, // FORNOT1S
961 20984145U, // FORNOT2
962 20985643U, // FORNOT2S
963 20985866U, // FORS
964 2109877U, // FPACK16
965 20984035U, // FPACK32
966 2111672U, // FPACKFIX
967 20984208U, // FPADD16
968 20985663U, // FPADD16S
969 20983998U, // FPADD32
970 20985606U, // FPADD32S
971 20984182U, // FPADD64
972 692074671U, // FPMADDX
973 692073648U, // FPMADDXHI
974 20984937U, // FPMERGE
975 20984199U, // FPSUB16
976 20985653U, // FPSUB16S
977 20983989U, // FPSUB32
978 20985596U, // FPSUB32S
979 2110486U, // FQTOD
980 2110690U, // FQTOI
981 2111460U, // FQTOS
982 2111717U, // FQTOX
983 20984308U, // FSLAS16
984 20984079U, // FSLAS32
985 20984263U, // FSLL16
986 20984053U, // FSLL32
987 20984784U, // FSMULD
988 2110542U, // FSQRTD
989 2111090U, // FSQRTQ
990 2111533U, // FSQRTS
991 20984191U, // FSRA16
992 20983981U, // FSRA32
993 2109566U, // FSRC1
994 2111191U, // FSRC1S
995 2109739U, // FSRC2
996 2111248U, // FSRC2S
997 20984271U, // FSRL16
998 20984061U, // FSRL32
999 2110493U, // FSTOD
1000 2110697U, // FSTOI
1001 2111062U, // FSTOQ
1002 2111724U, // FSTOX
1003 20984668U, // FSUBD
1004 20985372U, // FSUBQ
1005 20985673U, // FSUBS
1006 20985520U, // FXNOR
1007 20985879U, // FXNORS
1008 20985527U, // FXOR
1009 20985887U, // FXORS
1010 2110500U, // FXTOD
1011 2111069U, // FXTOQ
1012 2111476U, // FXTOS
1013 71160U, // FZERO
1014 71630U, // FZEROS
1015 154311839U, // GDOP_LDXrr
1016 154311789U, // GDOP_LDrr
1017 3381U, // INVALW
1018 2135413U, // JMPLri
1019 2135413U, // JMPLrr
1020 3054593U, // LDAri
1021 28285953U, // LDArr
1022 1272941U, // LDCSRri
1023 1272941U, // LDCSRrr
1024 3316845U, // LDCri
1025 3316845U, // LDCrr
1026 3054586U, // LDDAri
1027 28285946U, // LDDArr
1028 3316839U, // LDDCri
1029 3316839U, // LDDCrr
1030 3054586U, // LDDFAri
1031 28285946U, // LDDFArr
1032 3316839U, // LDDFri
1033 3316839U, // LDDFrr
1034 3316839U, // LDDri
1035 3316839U, // LDDrr
1036 3054593U, // LDFAri
1037 28285953U, // LDFArr
1038 1338477U, // LDFSRri
1039 1338477U, // LDFSRrr
1040 3316845U, // LDFri
1041 3316845U, // LDFrr
1042 3054635U, // LDQFAri
1043 28285995U, // LDQFArr
1044 3316882U, // LDQFri
1045 3316882U, // LDQFrr
1046 3054560U, // LDSBAri
1047 28285920U, // LDSBArr
1048 3316816U, // LDSBri
1049 3316816U, // LDSBrr
1050 3054611U, // LDSHAri
1051 28285971U, // LDSHArr
1052 3316861U, // LDSHri
1053 3316861U, // LDSHrr
1054 3054576U, // LDSTUBAri
1055 28285936U, // LDSTUBArr
1056 3316830U, // LDSTUBri
1057 3316830U, // LDSTUBrr
1058 3054649U, // LDSWAri
1059 28286009U, // LDSWArr
1060 3316888U, // LDSWri
1061 3316888U, // LDSWrr
1062 3054568U, // LDUBAri
1063 28285928U, // LDUBArr
1064 3316823U, // LDUBri
1065 3316823U, // LDUBrr
1066 3054619U, // LDUHAri
1067 28285979U, // LDUHArr
1068 3316868U, // LDUHri
1069 3316868U, // LDUHrr
1070 3054657U, // LDXAri
1071 28286017U, // LDXArr
1072 1338527U, // LDXFSRri
1073 1338527U, // LDXFSRrr
1074 3316895U, // LDXri
1075 3316895U, // LDXrr
1076 3316845U, // LDri
1077 3316845U, // LDrr
1078 2111560U, // LZCNT
1079 2852U, // MD5
1080 42637U, // MEMBARi
1081 71065U, // MONTMUL
1082 71369U, // MONTSQR
1083 2111708U, // MOVDTOX
1084 17923362U, // MOVFCCri
1085 17923362U, // MOVFCCrr
1086 17202466U, // MOVICCri
1087 17202466U, // MOVICCrr
1088 36110U, // MOVRri
1089 36110U, // MOVRrr
1090 2111624U, // MOVSTOSW
1091 2111641U, // MOVSTOUW
1092 2111467U, // MOVWTOS
1093 17464610U, // MOVXCCri
1094 17464610U, // MOVXCCrr
1095 2110507U, // MOVXTOD
1096 71052U, // MPMUL
1097 20984615U, // MULSCCri
1098 20984615U, // MULSCCrr
1099 20986063U, // MULXri
1100 20986063U, // MULXrr
1101 3316U, // NOP
1102 3373U, // NORMALW
1103 20984602U, // ORCCri
1104 20984602U, // ORCCrr
1105 20984593U, // ORNCCri
1106 20984593U, // ORNCCrr
1107 20985323U, // ORNri
1108 20985323U, // ORNrr
1109 20985510U, // ORri
1110 20985510U, // ORrr
1111 3388U, // OTHERW
1112 20985935U, // PDIST
1113 20985328U, // PDISTN
1114 2110287U, // POPCrr
1115 13528071U, // PREFETCHAi
1116 15690759U, // PREFETCHAr
1117 13790322U, // PREFETCHi
1118 13790322U, // PREFETCHr
1119 33560274U, // PWRPSRri
1120 33560274U, // PWRPSRrr
1121 2110531U, // RDASR
1122 69685U, // RDFQ
1123 2111165U, // RDPR
1124 69706U, // RDPSR
1125 69696U, // RDTBR
1126 69675U, // RDWIM
1127 3251U, // RESTORED
1128 20984962U, // RESTOREri
1129 20984962U, // RESTORErr
1130 72281U, // RET
1131 72290U, // RETL
1132 3395U, // RETRY
1133 92246U, // RETTri
1134 92246U, // RETTrr
1135 3260U, // SAVED
1136 20984971U, // SAVEri
1137 20984971U, // SAVErr
1138 20984623U, // SDIVCCri
1139 20984623U, // SDIVCCrr
1140 20986110U, // SDIVXri
1141 20986110U, // SDIVXrr
1142 20985960U, // SDIVri
1143 20985960U, // SDIVrr
1144 2110633U, // SETHIi
1145 2830U, // SHA1
1146 2856U, // SHA256
1147 2835U, // SHA512
1148 3307U, // SHUTDOWN
1149 71080U, // SIAM
1150 71328U, // SIR
1151 20986050U, // SLLXri
1152 20986050U, // SLLXrr
1153 20985200U, // SLLri
1154 20985200U, // SLLrr
1155 20984525U, // SMACri
1156 20984525U, // SMACrr
1157 20984569U, // SMULCCri
1158 20984569U, // SMULCCrr
1159 20985235U, // SMULri
1160 20985235U, // SMULrr
1161 20986019U, // SRAXri
1162 20986019U, // SRAXrr
1163 20984479U, // SRAri
1164 20984479U, // SRArr
1165 20986056U, // SRLXri
1166 20986056U, // SRLXrr
1167 20985223U, // SRLri
1168 20985223U, // SRLrr
1169 1422000U, // STAri
1170 11514544U, // STArr
1171 3333U, // STBAR
1172 1421959U, // STBAri
1173 11514503U, // STBArr
1174 1487547U, // STBri
1175 1487547U, // STBrr
1176 1469374U, // STCSRri
1177 1469374U, // STCSRrr
1178 1488978U, // STCri
1179 1488978U, // STCrr
1180 1421965U, // STDAri
1181 11514509U, // STDArr
1182 1469352U, // STDCQri
1183 1469352U, // STDCQrr
1184 1487958U, // STDCri
1185 1487958U, // STDCrr
1186 1421965U, // STDFAri
1187 11514509U, // STDFArr
1188 1469363U, // STDFQri
1189 1469363U, // STDFQrr
1190 1487958U, // STDFri
1191 1487958U, // STDFrr
1192 1487958U, // STDri
1193 1487958U, // STDrr
1194 1422000U, // STFAri
1195 11514544U, // STFArr
1196 1469385U, // STFSRri
1197 1469385U, // STFSRrr
1198 1488978U, // STFri
1199 1488978U, // STFrr
1200 1421971U, // STHAri
1201 11514515U, // STHArr
1202 1488036U, // STHri
1203 1488036U, // STHrr
1204 1421977U, // STQFAri
1205 11514521U, // STQFArr
1206 1488506U, // STQFri
1207 1488506U, // STQFrr
1208 1422005U, // STXAri
1209 11514549U, // STXArr
1210 1469396U, // STXFSRri
1211 1469396U, // STXFSRrr
1212 1489145U, // STXri
1213 1489145U, // STXrr
1214 1488978U, // STri
1215 1488978U, // STrr
1216 20984538U, // SUBCCri
1217 20984538U, // SUBCCrr
1218 20986025U, // SUBCri
1219 20986025U, // SUBCrr
1220 20984639U, // SUBEri
1221 20984639U, // SUBErr
1222 20984512U, // SUBri
1223 20984512U, // SUBrr
1224 3054627U, // SWAPAri
1225 28285987U, // SWAPArr
1226 3316875U, // SWAPri
1227 3316875U, // SWAPrr
1228 2825U, // TA1
1229 2842U, // TA3
1230 2847U, // TA5
1231 20985982U, // TADDCCTVri
1232 20985982U, // TADDCCTVrr
1233 20984554U, // TADDCCri
1234 20984554U, // TADDCCrr
1235 83306U, // TAIL_CALL
1236 91671U, // TAIL_CALLri
1237 52874528U, // TICCri
1238 52874528U, // TICCrr
1239 2705339260U, // TLS_ADDrr
1240 17770U, // TLS_CALL
1241 154311839U, // TLS_LDXrr
1242 154311789U, // TLS_LDrr
1243 52612384U, // TRAPri
1244 52612384U, // TRAPrr
1245 20985972U, // TSUBCCTVri
1246 20985972U, // TSUBCCTVrr
1247 20984537U, // TSUBCCri
1248 20984537U, // TSUBCCrr
1249 53136672U, // TXCCri
1250 53136672U, // TXCCrr
1251 20984631U, // UDIVCCri
1252 20984631U, // UDIVCCrr
1253 20986117U, // UDIVXri
1254 20986117U, // UDIVXrr
1255 20985966U, // UDIVri
1256 20985966U, // UDIVrr
1257 20984531U, // UMACri
1258 20984531U, // UMACrr
1259 20984577U, // UMULCCri
1260 20984577U, // UMULCCrr
1261 20985019U, // UMULXHI
1262 20985250U, // UMULri
1263 20985250U, // UMULrr
1264 71184U, // UNIMP
1265 419435572U, // V9FCMPD
1266 419435442U, // V9FCMPED
1267 419436074U, // V9FCMPEQ
1268 419436464U, // V9FCMPES
1269 419436132U, // V9FCMPQ
1270 419436539U, // V9FCMPS
1271 36041U, // V9FMOVD_FCC
1272 36095U, // V9FMOVQ_FCC
1273 36122U, // V9FMOVS_FCC
1274 36130U, // V9MOVFCCri
1275 36130U, // V9MOVFCCrr
1276 20985555U, // WRASRri
1277 20985555U, // WRASRrr
1278 20985539U, // WRPRri
1279 20985539U, // WRPRrr
1280 33560275U, // WRPSRri
1281 33560275U, // WRPSRrr
1282 67114707U, // WRTBRri
1283 67114707U, // WRTBRrr
1284 83891923U, // WRWIMri
1285 83891923U, // WRWIMrr
1286 20986062U, // XMULX
1287 20985028U, // XMULXHI
1288 20984600U, // XNORCCri
1289 20984600U, // XNORCCrr
1290 20985521U, // XNORri
1291 20985521U, // XNORrr
1292 20984608U, // XORCCri
1293 20984608U, // XORCCrr
1294 20985528U, // XORri
1295 20985528U, // XORrr
1296 };
1297
1298 // Emit the opcode for the instruction.
1299 uint32_t Bits = 0;
1300 Bits |= OpInfo0[MI.getOpcode()] << 0;
1301 if (Bits == 0)
1302 return {nullptr, Bits};
1303 return {AsmStrs+(Bits & 4095)-1, Bits};
1304
1305}
1306/// printInstruction - This method is automatically generated by tablegen
1307/// from the instruction set description.
1308LLVM_NO_PROFILE_INSTRUMENT_FUNCTION
1309void SparcInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) {
1310 O << "\t";
1311
1312 auto MnemonicInfo = getMnemonic(MI: *MI);
1313
1314 O << MnemonicInfo.first;
1315
1316 uint32_t Bits = MnemonicInfo.second;
1317 assert(Bits != 0 && "Cannot print this instruction.");
1318
1319 // Fragment 0 encoded into 4 bits for 13 unique commands.
1320 switch ((Bits >> 12) & 15) {
1321 default: llvm_unreachable("Invalid command number.");
1322 case 0:
1323 // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
1324 return;
1325 break;
1326 case 1:
1327 // ADJCALLSTACKDOWN, ADJCALLSTACKUP, CMASK16, CMASK32, CMASK8, FCMPD, FCM...
1328 printOperand(MI, opNum: 0, STI, OS&: O);
1329 break;
1330 case 2:
1331 // GETPCX
1332 printGetPCX(MI, OpNo: 0, STI, OS&: O);
1333 return;
1334 break;
1335 case 3:
1336 // SET, SETSW, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, AD...
1337 printOperand(MI, opNum: 1, STI, OS&: O);
1338 break;
1339 case 4:
1340 // BA, CALL, CALLi, TAIL_CALL, TLS_CALL
1341 printCTILabel(MI, Address, OpNum: 0, STI, O);
1342 break;
1343 case 5:
1344 // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
1345 printCCOperand(MI, opNum: 1, STI, OS&: O);
1346 break;
1347 case 6:
1348 // BINDri, BINDrr, CALLri, CALLrii, CALLrr, CALLrri, FLUSHri, FLUSHrr, LD...
1349 printMemOperand(MI, opNum: 0, STI, OS&: O);
1350 break;
1351 case 7:
1352 // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
1353 printCCOperand(MI, opNum: 3, STI, OS&: O);
1354 break;
1355 case 8:
1356 // FMOVRD, FMOVRQ, FMOVRS, MOVRri, MOVRrr, V9FMOVD_FCC, V9FMOVQ_FCC, V9FM...
1357 printCCOperand(MI, opNum: 4, STI, OS&: O);
1358 O << ' ';
1359 printOperand(MI, opNum: 1, STI, OS&: O);
1360 O << ", ";
1361 printOperand(MI, opNum: 2, STI, OS&: O);
1362 O << ", ";
1363 printOperand(MI, opNum: 0, STI, OS&: O);
1364 return;
1365 break;
1366 case 9:
1367 // GDOP_LDXrr, GDOP_LDrr, JMPLri, JMPLrr, LDAri, LDArr, LDCri, LDCrr, LDD...
1368 printMemOperand(MI, opNum: 1, STI, OS&: O);
1369 break;
1370 case 10:
1371 // MEMBARi
1372 printMembarTag(MI, opNum: 0, STI, O);
1373 return;
1374 break;
1375 case 11:
1376 // STAri, STArr, STBAri, STBArr, STBri, STBrr, STCri, STCrr, STDAri, STDA...
1377 printOperand(MI, opNum: 2, STI, OS&: O);
1378 O << ", [";
1379 printMemOperand(MI, opNum: 0, STI, OS&: O);
1380 break;
1381 case 12:
1382 // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr
1383 printCCOperand(MI, opNum: 2, STI, OS&: O);
1384 break;
1385 }
1386
1387
1388 // Fragment 1 encoded into 5 bits for 23 unique commands.
1389 switch ((Bits >> 16) & 31) {
1390 default: llvm_unreachable("Invalid command number.");
1391 case 0:
1392 // ADJCALLSTACKDOWN, SET, SETSW, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ...
1393 O << ", ";
1394 break;
1395 case 1:
1396 // ADJCALLSTACKUP, BA, BINDri, BINDrr, CALL, CALLri, CALLrr, CMASK16, CMA...
1397 return;
1398 break;
1399 case 2:
1400 // BCOND, BPFCC, BPR, CPBCOND, CWBCONDri, CWBCONDrr, CXBCONDri, CXBCONDrr...
1401 O << ' ';
1402 break;
1403 case 3:
1404 // BCONDA, BPFCCA, BPRA, CPBCONDA, FBCONDA
1405 O << ",a ";
1406 break;
1407 case 4:
1408 // BPFCCANT, BPRANT
1409 O << ",a,pn ";
1410 printOperand(MI, opNum: 2, STI, OS&: O);
1411 O << ", ";
1412 printCTILabel(MI, Address, OpNum: 0, STI, O);
1413 return;
1414 break;
1415 case 5:
1416 // BPFCCNT, BPRNT
1417 O << ",pn ";
1418 printOperand(MI, opNum: 2, STI, OS&: O);
1419 O << ", ";
1420 printCTILabel(MI, Address, OpNum: 0, STI, O);
1421 return;
1422 break;
1423 case 6:
1424 // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
1425 O << " %icc, ";
1426 break;
1427 case 7:
1428 // BPICCA
1429 O << ",a %icc, ";
1430 printCTILabel(MI, Address, OpNum: 0, STI, O);
1431 return;
1432 break;
1433 case 8:
1434 // BPICCANT
1435 O << ",a,pn %icc, ";
1436 printCTILabel(MI, Address, OpNum: 0, STI, O);
1437 return;
1438 break;
1439 case 9:
1440 // BPICCNT
1441 O << ",pn %icc, ";
1442 printCTILabel(MI, Address, OpNum: 0, STI, O);
1443 return;
1444 break;
1445 case 10:
1446 // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
1447 O << " %xcc, ";
1448 break;
1449 case 11:
1450 // BPXCCA
1451 O << ",a %xcc, ";
1452 printCTILabel(MI, Address, OpNum: 0, STI, O);
1453 return;
1454 break;
1455 case 12:
1456 // BPXCCANT
1457 O << ",a,pn %xcc, ";
1458 printCTILabel(MI, Address, OpNum: 0, STI, O);
1459 return;
1460 break;
1461 case 13:
1462 // BPXCCNT
1463 O << ",pn %xcc, ";
1464 printCTILabel(MI, Address, OpNum: 0, STI, O);
1465 return;
1466 break;
1467 case 14:
1468 // CASAri, CASXAri, LDAri, LDDAri, LDDFAri, LDFAri, LDQFAri, LDSBAri, LDS...
1469 O << "] %asi, ";
1470 break;
1471 case 15:
1472 // CASArr, CASXArr, LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDS...
1473 O << "] ";
1474 break;
1475 case 16:
1476 // FBCONDA_V9
1477 O << ",a %fcc0, ";
1478 printCTILabel(MI, Address, OpNum: 0, STI, O);
1479 return;
1480 break;
1481 case 17:
1482 // FBCOND_V9, FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1483 O << " %fcc0, ";
1484 break;
1485 case 18:
1486 // GDOP_LDXrr, GDOP_LDrr, LDCri, LDCrr, LDDCri, LDDCrr, LDDFri, LDDFrr, L...
1487 O << "], ";
1488 break;
1489 case 19:
1490 // LDCSRri, LDCSRrr
1491 O << "], %csr";
1492 return;
1493 break;
1494 case 20:
1495 // LDFSRri, LDFSRrr, LDXFSRri, LDXFSRrr
1496 O << "], %fsr";
1497 return;
1498 break;
1499 case 21:
1500 // STAri, STBAri, STDAri, STDFAri, STFAri, STHAri, STQFAri, STXAri
1501 O << "] %asi";
1502 return;
1503 break;
1504 case 22:
1505 // STBri, STBrr, STCSRri, STCSRrr, STCri, STCrr, STDCQri, STDCQrr, STDCri...
1506 O << ']';
1507 return;
1508 break;
1509 }
1510
1511
1512 // Fragment 2 encoded into 3 bits for 8 unique commands.
1513 switch ((Bits >> 21) & 7) {
1514 default: llvm_unreachable("Invalid command number.");
1515 case 0:
1516 // ADJCALLSTACKDOWN, CALLi, FCMPD, FCMPD_V9, FCMPQ, FCMPQ_V9, FCMPS, FCMP...
1517 printOperand(MI, opNum: 1, STI, OS&: O);
1518 break;
1519 case 1:
1520 // SET, SETSW, DES_IIP, DES_IP, FABSD, FABSQ, FABSS, FDTOI, FDTOQ, FDTOS,...
1521 printOperand(MI, opNum: 0, STI, OS&: O);
1522 break;
1523 case 2:
1524 // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1525 printOperand(MI, opNum: 2, STI, OS&: O);
1526 break;
1527 case 3:
1528 // BCOND, BCONDA, BPICC, BPXCC, CPBCOND, CPBCONDA, FBCOND, FBCONDA, FBCON...
1529 printCTILabel(MI, Address, OpNum: 0, STI, O);
1530 return;
1531 break;
1532 case 4:
1533 // CASArr, CASXArr
1534 printASITag(MI, opNum: 4, STI, O);
1535 O << ", ";
1536 printOperand(MI, opNum: 2, STI, OS&: O);
1537 O << ", ";
1538 printOperand(MI, opNum: 0, STI, OS&: O);
1539 return;
1540 break;
1541 case 5:
1542 // LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDSHArr, LDSTUBArr, ...
1543 printASITag(MI, opNum: 3, STI, O);
1544 break;
1545 case 6:
1546 // PREFETCHAi, PREFETCHi, PREFETCHr
1547 printPrefetchTag(MI, opNum: 2, STI, O);
1548 return;
1549 break;
1550 case 7:
1551 // PREFETCHAr
1552 printASITag(MI, opNum: 2, STI, O);
1553 O << ", ";
1554 printPrefetchTag(MI, opNum: 3, STI, O);
1555 return;
1556 break;
1557 }
1558
1559
1560 // Fragment 3 encoded into 3 bits for 6 unique commands.
1561 switch ((Bits >> 24) & 7) {
1562 default: llvm_unreachable("Invalid command number.");
1563 case 0:
1564 // ADJCALLSTACKDOWN, SET, SETSW, CALLi, CALLrii, CALLrri, DES_IIP, DES_IP...
1565 return;
1566 break;
1567 case 1:
1568 // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1569 O << ", ";
1570 break;
1571 case 2:
1572 // PWRPSRri, PWRPSRrr, WRPSRri, WRPSRrr
1573 O << ", %psr";
1574 return;
1575 break;
1576 case 3:
1577 // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr
1578 O << " + ";
1579 printOperand(MI, opNum: 1, STI, OS&: O);
1580 return;
1581 break;
1582 case 4:
1583 // WRTBRri, WRTBRrr
1584 O << ", %tbr";
1585 return;
1586 break;
1587 case 5:
1588 // WRWIMri, WRWIMrr
1589 O << ", %wim";
1590 return;
1591 break;
1592 }
1593
1594
1595 // Fragment 4 encoded into 2 bits for 4 unique commands.
1596 switch ((Bits >> 27) & 3) {
1597 default: llvm_unreachable("Invalid command number.");
1598 case 0:
1599 // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1600 printOperand(MI, opNum: 0, STI, OS&: O);
1601 break;
1602 case 1:
1603 // AES_DROUND01, AES_DROUND01_LAST, AES_DROUND23, AES_DROUND23_LAST, AES_...
1604 printOperand(MI, opNum: 3, STI, OS&: O);
1605 break;
1606 case 2:
1607 // BPFCC, BPFCCA, BPR, BPRA
1608 printCTILabel(MI, Address, OpNum: 0, STI, O);
1609 return;
1610 break;
1611 case 3:
1612 // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1613 printOperand(MI, opNum: 2, STI, OS&: O);
1614 return;
1615 break;
1616 }
1617
1618
1619 // Fragment 5 encoded into 1 bits for 2 unique commands.
1620 if ((Bits >> 29) & 1) {
1621 // AES_DROUND01, AES_DROUND01_LAST, AES_DROUND23, AES_DROUND23_LAST, AES_...
1622 O << ", ";
1623 } else {
1624 // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1625 return;
1626 }
1627
1628
1629 // Fragment 6 encoded into 2 bits for 3 unique commands.
1630 switch ((Bits >> 30) & 3) {
1631 default: llvm_unreachable("Invalid command number.");
1632 case 0:
1633 // AES_DROUND01, AES_DROUND01_LAST, AES_DROUND23, AES_DROUND23_LAST, AES_...
1634 printOperand(MI, opNum: 0, STI, OS&: O);
1635 return;
1636 break;
1637 case 1:
1638 // CWBCONDri, CWBCONDrr, CXBCONDri, CXBCONDrr
1639 printCTILabel(MI, Address, OpNum: 0, STI, O);
1640 return;
1641 break;
1642 case 2:
1643 // TLS_ADDrr
1644 printOperand(MI, opNum: 3, STI, OS&: O);
1645 return;
1646 break;
1647 }
1648
1649}
1650
1651
1652/// getRegisterName - This method is automatically generated by tblgen
1653/// from the register set description. This returns the assembler name
1654/// for the specified register.
1655const char *SparcInstPrinter::
1656getRegisterName(MCRegister Reg, unsigned AltIdx) {
1657 unsigned RegNo = Reg.id();
1658 assert(RegNo && RegNo < 238 && "Invalid register number!");
1659
1660
1661#ifdef __GNUC__
1662#pragma GCC diagnostic push
1663#pragma GCC diagnostic ignored "-Woverlength-strings"
1664#endif
1665 static const char AsmStrsNoRegAltName[] = {
1666 /* 0 */ "c10\000"
1667 /* 4 */ "f10\000"
1668 /* 8 */ "asr10\000"
1669 /* 14 */ "c20\000"
1670 /* 18 */ "f20\000"
1671 /* 22 */ "asr20\000"
1672 /* 28 */ "c30\000"
1673 /* 32 */ "f30\000"
1674 /* 36 */ "asr30\000"
1675 /* 42 */ "f40\000"
1676 /* 46 */ "f50\000"
1677 /* 50 */ "f60\000"
1678 /* 54 */ "fcc0\000"
1679 /* 59 */ "f0\000"
1680 /* 62 */ "g0\000"
1681 /* 65 */ "i0\000"
1682 /* 68 */ "l0\000"
1683 /* 71 */ "o0\000"
1684 /* 74 */ "c11\000"
1685 /* 78 */ "f11\000"
1686 /* 82 */ "asr11\000"
1687 /* 88 */ "c21\000"
1688 /* 92 */ "f21\000"
1689 /* 96 */ "asr21\000"
1690 /* 102 */ "c31\000"
1691 /* 106 */ "f31\000"
1692 /* 110 */ "asr31\000"
1693 /* 116 */ "fcc1\000"
1694 /* 121 */ "f1\000"
1695 /* 124 */ "g1\000"
1696 /* 127 */ "i1\000"
1697 /* 130 */ "l1\000"
1698 /* 133 */ "o1\000"
1699 /* 136 */ "asr1\000"
1700 /* 141 */ "c12\000"
1701 /* 145 */ "f12\000"
1702 /* 149 */ "asr12\000"
1703 /* 155 */ "c22\000"
1704 /* 159 */ "f22\000"
1705 /* 163 */ "asr22\000"
1706 /* 169 */ "f32\000"
1707 /* 173 */ "f42\000"
1708 /* 177 */ "f52\000"
1709 /* 181 */ "f62\000"
1710 /* 185 */ "fcc2\000"
1711 /* 190 */ "f2\000"
1712 /* 193 */ "g2\000"
1713 /* 196 */ "i2\000"
1714 /* 199 */ "l2\000"
1715 /* 202 */ "o2\000"
1716 /* 205 */ "asr2\000"
1717 /* 210 */ "c13\000"
1718 /* 214 */ "f13\000"
1719 /* 218 */ "asr13\000"
1720 /* 224 */ "c23\000"
1721 /* 228 */ "f23\000"
1722 /* 232 */ "asr23\000"
1723 /* 238 */ "fcc3\000"
1724 /* 243 */ "f3\000"
1725 /* 246 */ "g3\000"
1726 /* 249 */ "i3\000"
1727 /* 252 */ "l3\000"
1728 /* 255 */ "o3\000"
1729 /* 258 */ "asr3\000"
1730 /* 263 */ "c14\000"
1731 /* 267 */ "f14\000"
1732 /* 271 */ "asr14\000"
1733 /* 277 */ "c24\000"
1734 /* 281 */ "f24\000"
1735 /* 285 */ "asr24\000"
1736 /* 291 */ "f34\000"
1737 /* 295 */ "f44\000"
1738 /* 299 */ "f54\000"
1739 /* 303 */ "c4\000"
1740 /* 306 */ "f4\000"
1741 /* 309 */ "g4\000"
1742 /* 312 */ "i4\000"
1743 /* 315 */ "l4\000"
1744 /* 318 */ "o4\000"
1745 /* 321 */ "asr4\000"
1746 /* 326 */ "c15\000"
1747 /* 330 */ "f15\000"
1748 /* 334 */ "asr15\000"
1749 /* 340 */ "c25\000"
1750 /* 344 */ "f25\000"
1751 /* 348 */ "asr25\000"
1752 /* 354 */ "c5\000"
1753 /* 357 */ "f5\000"
1754 /* 360 */ "g5\000"
1755 /* 363 */ "i5\000"
1756 /* 366 */ "l5\000"
1757 /* 369 */ "o5\000"
1758 /* 372 */ "asr5\000"
1759 /* 377 */ "c16\000"
1760 /* 381 */ "f16\000"
1761 /* 385 */ "asr16\000"
1762 /* 391 */ "c26\000"
1763 /* 395 */ "f26\000"
1764 /* 399 */ "asr26\000"
1765 /* 405 */ "f36\000"
1766 /* 409 */ "f46\000"
1767 /* 413 */ "f56\000"
1768 /* 417 */ "c6\000"
1769 /* 420 */ "f6\000"
1770 /* 423 */ "g6\000"
1771 /* 426 */ "i6\000"
1772 /* 429 */ "l6\000"
1773 /* 432 */ "o6\000"
1774 /* 435 */ "asr6\000"
1775 /* 440 */ "c17\000"
1776 /* 444 */ "f17\000"
1777 /* 448 */ "asr17\000"
1778 /* 454 */ "c27\000"
1779 /* 458 */ "f27\000"
1780 /* 462 */ "asr27\000"
1781 /* 468 */ "c7\000"
1782 /* 471 */ "f7\000"
1783 /* 474 */ "g7\000"
1784 /* 477 */ "i7\000"
1785 /* 480 */ "l7\000"
1786 /* 483 */ "o7\000"
1787 /* 486 */ "asr7\000"
1788 /* 491 */ "c18\000"
1789 /* 495 */ "f18\000"
1790 /* 499 */ "asr18\000"
1791 /* 505 */ "c28\000"
1792 /* 509 */ "f28\000"
1793 /* 513 */ "asr28\000"
1794 /* 519 */ "f38\000"
1795 /* 523 */ "f48\000"
1796 /* 527 */ "f58\000"
1797 /* 531 */ "c8\000"
1798 /* 534 */ "f8\000"
1799 /* 537 */ "asr8\000"
1800 /* 542 */ "c19\000"
1801 /* 546 */ "f19\000"
1802 /* 550 */ "asr19\000"
1803 /* 556 */ "c29\000"
1804 /* 560 */ "f29\000"
1805 /* 564 */ "asr29\000"
1806 /* 570 */ "c9\000"
1807 /* 573 */ "f9\000"
1808 /* 576 */ "asr9\000"
1809 /* 581 */ "tba\000"
1810 /* 585 */ "icc\000"
1811 /* 589 */ "tnpc\000"
1812 /* 594 */ "tpc\000"
1813 /* 598 */ "canrestore\000"
1814 /* 609 */ "pstate\000"
1815 /* 616 */ "tstate\000"
1816 /* 623 */ "wstate\000"
1817 /* 630 */ "cansave\000"
1818 /* 638 */ "tick\000"
1819 /* 643 */ "gl\000"
1820 /* 646 */ "pil\000"
1821 /* 650 */ "tl\000"
1822 /* 653 */ "wim\000"
1823 /* 657 */ "cleanwin\000"
1824 /* 666 */ "otherwin\000"
1825 /* 675 */ "fp\000"
1826 /* 678 */ "sp\000"
1827 /* 681 */ "cwp\000"
1828 /* 685 */ "cq\000"
1829 /* 688 */ "fq\000"
1830 /* 691 */ "tbr\000"
1831 /* 695 */ "ver\000"
1832 /* 699 */ "csr\000"
1833 /* 703 */ "fsr\000"
1834 /* 707 */ "psr\000"
1835 /* 711 */ "tt\000"
1836 /* 714 */ "y\000"
1837};
1838#ifdef __GNUC__
1839#pragma GCC diagnostic pop
1840#endif
1841
1842 static const uint16_t RegAsmOffsetNoRegAltName[] = {
1843 598, 630, 657, 685, 699, 681, 688, 703, 643, 585, 666, 646, 707, 609,
1844 581, 691, 638, 650, 589, 594, 616, 711, 695, 653, 623, 714, 136, 205,
1845 258, 321, 372, 435, 486, 537, 576, 8, 82, 149, 218, 271, 334, 385,
1846 448, 499, 550, 22, 96, 163, 232, 285, 348, 399, 462, 513, 564, 36,
1847 110, 56, 118, 187, 240, 303, 354, 417, 468, 531, 570, 0, 74, 141,
1848 210, 263, 326, 377, 440, 491, 542, 14, 88, 155, 224, 277, 340, 391,
1849 454, 505, 556, 28, 102, 59, 190, 306, 420, 534, 4, 145, 267, 381,
1850 495, 18, 159, 281, 395, 509, 32, 169, 291, 405, 519, 42, 173, 295,
1851 409, 523, 46, 177, 299, 413, 527, 50, 181, 59, 121, 190, 243, 306,
1852 357, 420, 471, 534, 573, 4, 78, 145, 214, 267, 330, 381, 444, 495,
1853 546, 18, 92, 159, 228, 281, 344, 395, 458, 509, 560, 32, 106, 54,
1854 116, 185, 238, 62, 124, 193, 246, 309, 360, 423, 474, 65, 127, 196,
1855 249, 312, 363, 675, 477, 68, 130, 199, 252, 315, 366, 429, 480, 71,
1856 133, 202, 255, 318, 369, 678, 483, 59, 306, 534, 145, 381, 18, 281,
1857 509, 169, 405, 42, 295, 523, 177, 413, 50, 56, 187, 303, 417, 531,
1858 0, 141, 263, 377, 491, 14, 155, 277, 391, 505, 28, 62, 193, 309,
1859 423, 65, 196, 312, 426, 68, 199, 315, 429, 71, 202, 318, 432,
1860 };
1861
1862
1863#ifdef __GNUC__
1864#pragma GCC diagnostic push
1865#pragma GCC diagnostic ignored "-Woverlength-strings"
1866#endif
1867 static const char AsmStrsRegNamesStateReg[] = {
1868 /* 0 */ "pc\000"
1869 /* 3 */ "asi\000"
1870 /* 7 */ "tick\000"
1871 /* 12 */ "ccr\000"
1872 /* 16 */ "fprs\000"
1873};
1874#ifdef __GNUC__
1875#pragma GCC diagnostic pop
1876#endif
1877
1878 static const uint8_t RegAsmOffsetRegNamesStateReg[] = {
1879 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1880 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 12,
1881 3, 7, 0, 16, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1882 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1883 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1884 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1885 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1886 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1887 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1888 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1889 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1890 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1891 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1892 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1893 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1894 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1895 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1896 };
1897
1898 switch(AltIdx) {
1899 default: llvm_unreachable("Invalid register alt name index!");
1900 case SP::NoRegAltName:
1901 assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) &&
1902 "Invalid alt name index for register!");
1903 return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
1904 case SP::RegNamesStateReg:
1905 if (!*(AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1]))
1906 return getRegisterName(Reg: RegNo, AltIdx: SP::NoRegAltName);
1907 return AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1];
1908 }
1909}
1910
1911#ifdef PRINT_ALIAS_INSTR
1912#undef PRINT_ALIAS_INSTR
1913
1914bool SparcInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS) {
1915 static const PatternsForOpcode OpToPatterns[] = {
1916 {.Opcode: SP::BCOND, .PatternStart: 0, .NumPatterns: 16 },
1917 {.Opcode: SP::BCONDA, .PatternStart: 16, .NumPatterns: 16 },
1918 {.Opcode: SP::BPFCCANT, .PatternStart: 32, .NumPatterns: 16 },
1919 {.Opcode: SP::BPFCCNT, .PatternStart: 48, .NumPatterns: 16 },
1920 {.Opcode: SP::BPICCANT, .PatternStart: 64, .NumPatterns: 32 },
1921 {.Opcode: SP::BPICCNT, .PatternStart: 96, .NumPatterns: 32 },
1922 {.Opcode: SP::BPRANT, .PatternStart: 128, .NumPatterns: 4 },
1923 {.Opcode: SP::BPRNT, .PatternStart: 132, .NumPatterns: 4 },
1924 {.Opcode: SP::CASArr, .PatternStart: 136, .NumPatterns: 2 },
1925 {.Opcode: SP::CASXArr, .PatternStart: 138, .NumPatterns: 2 },
1926 {.Opcode: SP::CWBCONDri, .PatternStart: 140, .NumPatterns: 14 },
1927 {.Opcode: SP::CWBCONDrr, .PatternStart: 154, .NumPatterns: 14 },
1928 {.Opcode: SP::CXBCONDri, .PatternStart: 168, .NumPatterns: 14 },
1929 {.Opcode: SP::CXBCONDrr, .PatternStart: 182, .NumPatterns: 14 },
1930 {.Opcode: SP::FMOVD_ICC, .PatternStart: 196, .NumPatterns: 32 },
1931 {.Opcode: SP::FMOVQ_ICC, .PatternStart: 228, .NumPatterns: 32 },
1932 {.Opcode: SP::FMOVRD, .PatternStart: 260, .NumPatterns: 4 },
1933 {.Opcode: SP::FMOVRQ, .PatternStart: 264, .NumPatterns: 4 },
1934 {.Opcode: SP::FMOVRS, .PatternStart: 268, .NumPatterns: 4 },
1935 {.Opcode: SP::FMOVS_ICC, .PatternStart: 272, .NumPatterns: 32 },
1936 {.Opcode: SP::MOVICCri, .PatternStart: 304, .NumPatterns: 32 },
1937 {.Opcode: SP::MOVICCrr, .PatternStart: 336, .NumPatterns: 32 },
1938 {.Opcode: SP::MOVRri, .PatternStart: 368, .NumPatterns: 4 },
1939 {.Opcode: SP::MOVRrr, .PatternStart: 372, .NumPatterns: 4 },
1940 {.Opcode: SP::ORCCrr, .PatternStart: 376, .NumPatterns: 1 },
1941 {.Opcode: SP::ORri, .PatternStart: 377, .NumPatterns: 1 },
1942 {.Opcode: SP::ORrr, .PatternStart: 378, .NumPatterns: 1 },
1943 {.Opcode: SP::RESTORErr, .PatternStart: 379, .NumPatterns: 1 },
1944 {.Opcode: SP::RET, .PatternStart: 380, .NumPatterns: 1 },
1945 {.Opcode: SP::RETL, .PatternStart: 381, .NumPatterns: 1 },
1946 {.Opcode: SP::SAVErr, .PatternStart: 382, .NumPatterns: 1 },
1947 {.Opcode: SP::SUBCCri, .PatternStart: 383, .NumPatterns: 1 },
1948 {.Opcode: SP::SUBCCrr, .PatternStart: 384, .NumPatterns: 1 },
1949 {.Opcode: SP::TICCri, .PatternStart: 385, .NumPatterns: 64 },
1950 {.Opcode: SP::TICCrr, .PatternStart: 449, .NumPatterns: 64 },
1951 {.Opcode: SP::TRAPri, .PatternStart: 513, .NumPatterns: 32 },
1952 {.Opcode: SP::TRAPrr, .PatternStart: 545, .NumPatterns: 32 },
1953 {.Opcode: SP::TXCCri, .PatternStart: 577, .NumPatterns: 64 },
1954 {.Opcode: SP::TXCCrr, .PatternStart: 641, .NumPatterns: 64 },
1955 {.Opcode: SP::V9FCMPD, .PatternStart: 705, .NumPatterns: 1 },
1956 {.Opcode: SP::V9FCMPED, .PatternStart: 706, .NumPatterns: 1 },
1957 {.Opcode: SP::V9FCMPEQ, .PatternStart: 707, .NumPatterns: 1 },
1958 {.Opcode: SP::V9FCMPES, .PatternStart: 708, .NumPatterns: 1 },
1959 {.Opcode: SP::V9FCMPQ, .PatternStart: 709, .NumPatterns: 1 },
1960 {.Opcode: SP::V9FCMPS, .PatternStart: 710, .NumPatterns: 1 },
1961 {.Opcode: SP::V9FMOVD_FCC, .PatternStart: 711, .NumPatterns: 16 },
1962 {.Opcode: SP::V9FMOVQ_FCC, .PatternStart: 727, .NumPatterns: 16 },
1963 {.Opcode: SP::V9FMOVS_FCC, .PatternStart: 743, .NumPatterns: 16 },
1964 {.Opcode: SP::V9MOVFCCri, .PatternStart: 759, .NumPatterns: 16 },
1965 {.Opcode: SP::V9MOVFCCrr, .PatternStart: 775, .NumPatterns: 16 },
1966 {.Opcode: SP::WRASRri, .PatternStart: 791, .NumPatterns: 1 },
1967 {.Opcode: SP::WRASRrr, .PatternStart: 792, .NumPatterns: 1 },
1968 };
1969
1970 static const AliasPattern Patterns[] = {
1971 // SP::BCOND - 0
1972 {.AsmStrOffset: 0, .AliasCondStart: 0, .NumOperands: 2, .NumConds: 2 },
1973 {.AsmStrOffset: 8, .AliasCondStart: 2, .NumOperands: 2, .NumConds: 2 },
1974 {.AsmStrOffset: 16, .AliasCondStart: 4, .NumOperands: 2, .NumConds: 2 },
1975 {.AsmStrOffset: 25, .AliasCondStart: 6, .NumOperands: 2, .NumConds: 2 },
1976 {.AsmStrOffset: 33, .AliasCondStart: 8, .NumOperands: 2, .NumConds: 2 },
1977 {.AsmStrOffset: 41, .AliasCondStart: 10, .NumOperands: 2, .NumConds: 2 },
1978 {.AsmStrOffset: 50, .AliasCondStart: 12, .NumOperands: 2, .NumConds: 2 },
1979 {.AsmStrOffset: 59, .AliasCondStart: 14, .NumOperands: 2, .NumConds: 2 },
1980 {.AsmStrOffset: 67, .AliasCondStart: 16, .NumOperands: 2, .NumConds: 2 },
1981 {.AsmStrOffset: 76, .AliasCondStart: 18, .NumOperands: 2, .NumConds: 2 },
1982 {.AsmStrOffset: 86, .AliasCondStart: 20, .NumOperands: 2, .NumConds: 2 },
1983 {.AsmStrOffset: 95, .AliasCondStart: 22, .NumOperands: 2, .NumConds: 2 },
1984 {.AsmStrOffset: 104, .AliasCondStart: 24, .NumOperands: 2, .NumConds: 2 },
1985 {.AsmStrOffset: 114, .AliasCondStart: 26, .NumOperands: 2, .NumConds: 2 },
1986 {.AsmStrOffset: 124, .AliasCondStart: 28, .NumOperands: 2, .NumConds: 2 },
1987 {.AsmStrOffset: 133, .AliasCondStart: 30, .NumOperands: 2, .NumConds: 2 },
1988 // SP::BCONDA - 16
1989 {.AsmStrOffset: 142, .AliasCondStart: 32, .NumOperands: 2, .NumConds: 2 },
1990 {.AsmStrOffset: 152, .AliasCondStart: 34, .NumOperands: 2, .NumConds: 2 },
1991 {.AsmStrOffset: 162, .AliasCondStart: 36, .NumOperands: 2, .NumConds: 2 },
1992 {.AsmStrOffset: 173, .AliasCondStart: 38, .NumOperands: 2, .NumConds: 2 },
1993 {.AsmStrOffset: 183, .AliasCondStart: 40, .NumOperands: 2, .NumConds: 2 },
1994 {.AsmStrOffset: 193, .AliasCondStart: 42, .NumOperands: 2, .NumConds: 2 },
1995 {.AsmStrOffset: 204, .AliasCondStart: 44, .NumOperands: 2, .NumConds: 2 },
1996 {.AsmStrOffset: 215, .AliasCondStart: 46, .NumOperands: 2, .NumConds: 2 },
1997 {.AsmStrOffset: 225, .AliasCondStart: 48, .NumOperands: 2, .NumConds: 2 },
1998 {.AsmStrOffset: 236, .AliasCondStart: 50, .NumOperands: 2, .NumConds: 2 },
1999 {.AsmStrOffset: 248, .AliasCondStart: 52, .NumOperands: 2, .NumConds: 2 },
2000 {.AsmStrOffset: 259, .AliasCondStart: 54, .NumOperands: 2, .NumConds: 2 },
2001 {.AsmStrOffset: 270, .AliasCondStart: 56, .NumOperands: 2, .NumConds: 2 },
2002 {.AsmStrOffset: 282, .AliasCondStart: 58, .NumOperands: 2, .NumConds: 2 },
2003 {.AsmStrOffset: 294, .AliasCondStart: 60, .NumOperands: 2, .NumConds: 2 },
2004 {.AsmStrOffset: 305, .AliasCondStart: 62, .NumOperands: 2, .NumConds: 2 },
2005 // SP::BPFCCANT - 32
2006 {.AsmStrOffset: 316, .AliasCondStart: 64, .NumOperands: 3, .NumConds: 4 },
2007 {.AsmStrOffset: 334, .AliasCondStart: 68, .NumOperands: 3, .NumConds: 4 },
2008 {.AsmStrOffset: 352, .AliasCondStart: 72, .NumOperands: 3, .NumConds: 4 },
2009 {.AsmStrOffset: 370, .AliasCondStart: 76, .NumOperands: 3, .NumConds: 4 },
2010 {.AsmStrOffset: 388, .AliasCondStart: 80, .NumOperands: 3, .NumConds: 4 },
2011 {.AsmStrOffset: 407, .AliasCondStart: 84, .NumOperands: 3, .NumConds: 4 },
2012 {.AsmStrOffset: 425, .AliasCondStart: 88, .NumOperands: 3, .NumConds: 4 },
2013 {.AsmStrOffset: 444, .AliasCondStart: 92, .NumOperands: 3, .NumConds: 4 },
2014 {.AsmStrOffset: 463, .AliasCondStart: 96, .NumOperands: 3, .NumConds: 4 },
2015 {.AsmStrOffset: 482, .AliasCondStart: 100, .NumOperands: 3, .NumConds: 4 },
2016 {.AsmStrOffset: 500, .AliasCondStart: 104, .NumOperands: 3, .NumConds: 4 },
2017 {.AsmStrOffset: 519, .AliasCondStart: 108, .NumOperands: 3, .NumConds: 4 },
2018 {.AsmStrOffset: 538, .AliasCondStart: 112, .NumOperands: 3, .NumConds: 4 },
2019 {.AsmStrOffset: 558, .AliasCondStart: 116, .NumOperands: 3, .NumConds: 4 },
2020 {.AsmStrOffset: 577, .AliasCondStart: 120, .NumOperands: 3, .NumConds: 4 },
2021 {.AsmStrOffset: 597, .AliasCondStart: 124, .NumOperands: 3, .NumConds: 4 },
2022 // SP::BPFCCNT - 48
2023 {.AsmStrOffset: 615, .AliasCondStart: 128, .NumOperands: 3, .NumConds: 4 },
2024 {.AsmStrOffset: 631, .AliasCondStart: 132, .NumOperands: 3, .NumConds: 4 },
2025 {.AsmStrOffset: 647, .AliasCondStart: 136, .NumOperands: 3, .NumConds: 4 },
2026 {.AsmStrOffset: 663, .AliasCondStart: 140, .NumOperands: 3, .NumConds: 4 },
2027 {.AsmStrOffset: 679, .AliasCondStart: 144, .NumOperands: 3, .NumConds: 4 },
2028 {.AsmStrOffset: 696, .AliasCondStart: 148, .NumOperands: 3, .NumConds: 4 },
2029 {.AsmStrOffset: 712, .AliasCondStart: 152, .NumOperands: 3, .NumConds: 4 },
2030 {.AsmStrOffset: 729, .AliasCondStart: 156, .NumOperands: 3, .NumConds: 4 },
2031 {.AsmStrOffset: 746, .AliasCondStart: 160, .NumOperands: 3, .NumConds: 4 },
2032 {.AsmStrOffset: 763, .AliasCondStart: 164, .NumOperands: 3, .NumConds: 4 },
2033 {.AsmStrOffset: 779, .AliasCondStart: 168, .NumOperands: 3, .NumConds: 4 },
2034 {.AsmStrOffset: 796, .AliasCondStart: 172, .NumOperands: 3, .NumConds: 4 },
2035 {.AsmStrOffset: 813, .AliasCondStart: 176, .NumOperands: 3, .NumConds: 4 },
2036 {.AsmStrOffset: 831, .AliasCondStart: 180, .NumOperands: 3, .NumConds: 4 },
2037 {.AsmStrOffset: 848, .AliasCondStart: 184, .NumOperands: 3, .NumConds: 4 },
2038 {.AsmStrOffset: 866, .AliasCondStart: 188, .NumOperands: 3, .NumConds: 4 },
2039 // SP::BPICCANT - 64
2040 {.AsmStrOffset: 882, .AliasCondStart: 192, .NumOperands: 2, .NumConds: 3 },
2041 {.AsmStrOffset: 901, .AliasCondStart: 195, .NumOperands: 2, .NumConds: 4 },
2042 {.AsmStrOffset: 920, .AliasCondStart: 199, .NumOperands: 2, .NumConds: 3 },
2043 {.AsmStrOffset: 939, .AliasCondStart: 202, .NumOperands: 2, .NumConds: 4 },
2044 {.AsmStrOffset: 958, .AliasCondStart: 206, .NumOperands: 2, .NumConds: 3 },
2045 {.AsmStrOffset: 978, .AliasCondStart: 209, .NumOperands: 2, .NumConds: 4 },
2046 {.AsmStrOffset: 998, .AliasCondStart: 213, .NumOperands: 2, .NumConds: 3 },
2047 {.AsmStrOffset: 1017, .AliasCondStart: 216, .NumOperands: 2, .NumConds: 4 },
2048 {.AsmStrOffset: 1036, .AliasCondStart: 220, .NumOperands: 2, .NumConds: 3 },
2049 {.AsmStrOffset: 1055, .AliasCondStart: 223, .NumOperands: 2, .NumConds: 4 },
2050 {.AsmStrOffset: 1074, .AliasCondStart: 227, .NumOperands: 2, .NumConds: 3 },
2051 {.AsmStrOffset: 1094, .AliasCondStart: 230, .NumOperands: 2, .NumConds: 4 },
2052 {.AsmStrOffset: 1114, .AliasCondStart: 234, .NumOperands: 2, .NumConds: 3 },
2053 {.AsmStrOffset: 1134, .AliasCondStart: 237, .NumOperands: 2, .NumConds: 4 },
2054 {.AsmStrOffset: 1154, .AliasCondStart: 241, .NumOperands: 2, .NumConds: 3 },
2055 {.AsmStrOffset: 1173, .AliasCondStart: 244, .NumOperands: 2, .NumConds: 4 },
2056 {.AsmStrOffset: 1192, .AliasCondStart: 248, .NumOperands: 2, .NumConds: 3 },
2057 {.AsmStrOffset: 1212, .AliasCondStart: 251, .NumOperands: 2, .NumConds: 4 },
2058 {.AsmStrOffset: 1232, .AliasCondStart: 255, .NumOperands: 2, .NumConds: 3 },
2059 {.AsmStrOffset: 1253, .AliasCondStart: 258, .NumOperands: 2, .NumConds: 4 },
2060 {.AsmStrOffset: 1274, .AliasCondStart: 262, .NumOperands: 2, .NumConds: 3 },
2061 {.AsmStrOffset: 1294, .AliasCondStart: 265, .NumOperands: 2, .NumConds: 4 },
2062 {.AsmStrOffset: 1314, .AliasCondStart: 269, .NumOperands: 2, .NumConds: 3 },
2063 {.AsmStrOffset: 1334, .AliasCondStart: 272, .NumOperands: 2, .NumConds: 4 },
2064 {.AsmStrOffset: 1354, .AliasCondStart: 276, .NumOperands: 2, .NumConds: 3 },
2065 {.AsmStrOffset: 1375, .AliasCondStart: 279, .NumOperands: 2, .NumConds: 4 },
2066 {.AsmStrOffset: 1396, .AliasCondStart: 283, .NumOperands: 2, .NumConds: 3 },
2067 {.AsmStrOffset: 1417, .AliasCondStart: 286, .NumOperands: 2, .NumConds: 4 },
2068 {.AsmStrOffset: 1438, .AliasCondStart: 290, .NumOperands: 2, .NumConds: 3 },
2069 {.AsmStrOffset: 1458, .AliasCondStart: 293, .NumOperands: 2, .NumConds: 4 },
2070 {.AsmStrOffset: 1478, .AliasCondStart: 297, .NumOperands: 2, .NumConds: 3 },
2071 {.AsmStrOffset: 1498, .AliasCondStart: 300, .NumOperands: 2, .NumConds: 4 },
2072 // SP::BPICCNT - 96
2073 {.AsmStrOffset: 1518, .AliasCondStart: 304, .NumOperands: 2, .NumConds: 3 },
2074 {.AsmStrOffset: 1535, .AliasCondStart: 307, .NumOperands: 2, .NumConds: 4 },
2075 {.AsmStrOffset: 1552, .AliasCondStart: 311, .NumOperands: 2, .NumConds: 3 },
2076 {.AsmStrOffset: 1569, .AliasCondStart: 314, .NumOperands: 2, .NumConds: 4 },
2077 {.AsmStrOffset: 1586, .AliasCondStart: 318, .NumOperands: 2, .NumConds: 3 },
2078 {.AsmStrOffset: 1604, .AliasCondStart: 321, .NumOperands: 2, .NumConds: 4 },
2079 {.AsmStrOffset: 1622, .AliasCondStart: 325, .NumOperands: 2, .NumConds: 3 },
2080 {.AsmStrOffset: 1639, .AliasCondStart: 328, .NumOperands: 2, .NumConds: 4 },
2081 {.AsmStrOffset: 1656, .AliasCondStart: 332, .NumOperands: 2, .NumConds: 3 },
2082 {.AsmStrOffset: 1673, .AliasCondStart: 335, .NumOperands: 2, .NumConds: 4 },
2083 {.AsmStrOffset: 1690, .AliasCondStart: 339, .NumOperands: 2, .NumConds: 3 },
2084 {.AsmStrOffset: 1708, .AliasCondStart: 342, .NumOperands: 2, .NumConds: 4 },
2085 {.AsmStrOffset: 1726, .AliasCondStart: 346, .NumOperands: 2, .NumConds: 3 },
2086 {.AsmStrOffset: 1744, .AliasCondStart: 349, .NumOperands: 2, .NumConds: 4 },
2087 {.AsmStrOffset: 1762, .AliasCondStart: 353, .NumOperands: 2, .NumConds: 3 },
2088 {.AsmStrOffset: 1779, .AliasCondStart: 356, .NumOperands: 2, .NumConds: 4 },
2089 {.AsmStrOffset: 1796, .AliasCondStart: 360, .NumOperands: 2, .NumConds: 3 },
2090 {.AsmStrOffset: 1814, .AliasCondStart: 363, .NumOperands: 2, .NumConds: 4 },
2091 {.AsmStrOffset: 1832, .AliasCondStart: 367, .NumOperands: 2, .NumConds: 3 },
2092 {.AsmStrOffset: 1851, .AliasCondStart: 370, .NumOperands: 2, .NumConds: 4 },
2093 {.AsmStrOffset: 1870, .AliasCondStart: 374, .NumOperands: 2, .NumConds: 3 },
2094 {.AsmStrOffset: 1888, .AliasCondStart: 377, .NumOperands: 2, .NumConds: 4 },
2095 {.AsmStrOffset: 1906, .AliasCondStart: 381, .NumOperands: 2, .NumConds: 3 },
2096 {.AsmStrOffset: 1924, .AliasCondStart: 384, .NumOperands: 2, .NumConds: 4 },
2097 {.AsmStrOffset: 1942, .AliasCondStart: 388, .NumOperands: 2, .NumConds: 3 },
2098 {.AsmStrOffset: 1961, .AliasCondStart: 391, .NumOperands: 2, .NumConds: 4 },
2099 {.AsmStrOffset: 1980, .AliasCondStart: 395, .NumOperands: 2, .NumConds: 3 },
2100 {.AsmStrOffset: 1999, .AliasCondStart: 398, .NumOperands: 2, .NumConds: 4 },
2101 {.AsmStrOffset: 2018, .AliasCondStart: 402, .NumOperands: 2, .NumConds: 3 },
2102 {.AsmStrOffset: 2036, .AliasCondStart: 405, .NumOperands: 2, .NumConds: 4 },
2103 {.AsmStrOffset: 2054, .AliasCondStart: 409, .NumOperands: 2, .NumConds: 3 },
2104 {.AsmStrOffset: 2072, .AliasCondStart: 412, .NumOperands: 2, .NumConds: 4 },
2105 // SP::BPRANT - 128
2106 {.AsmStrOffset: 2090, .AliasCondStart: 416, .NumOperands: 3, .NumConds: 4 },
2107 {.AsmStrOffset: 2110, .AliasCondStart: 420, .NumOperands: 3, .NumConds: 4 },
2108 {.AsmStrOffset: 2129, .AliasCondStart: 424, .NumOperands: 3, .NumConds: 4 },
2109 {.AsmStrOffset: 2148, .AliasCondStart: 428, .NumOperands: 3, .NumConds: 4 },
2110 // SP::BPRNT - 132
2111 {.AsmStrOffset: 2168, .AliasCondStart: 432, .NumOperands: 3, .NumConds: 4 },
2112 {.AsmStrOffset: 2186, .AliasCondStart: 436, .NumOperands: 3, .NumConds: 4 },
2113 {.AsmStrOffset: 2203, .AliasCondStart: 440, .NumOperands: 3, .NumConds: 4 },
2114 {.AsmStrOffset: 2220, .AliasCondStart: 444, .NumOperands: 3, .NumConds: 4 },
2115 // SP::CASArr - 136
2116 {.AsmStrOffset: 2238, .AliasCondStart: 448, .NumOperands: 5, .NumConds: 6 },
2117 {.AsmStrOffset: 2255, .AliasCondStart: 454, .NumOperands: 5, .NumConds: 6 },
2118 // SP::CASXArr - 138
2119 {.AsmStrOffset: 2273, .AliasCondStart: 460, .NumOperands: 5, .NumConds: 6 },
2120 {.AsmStrOffset: 2291, .AliasCondStart: 466, .NumOperands: 5, .NumConds: 6 },
2121 // SP::CWBCONDri - 140
2122 {.AsmStrOffset: 2310, .AliasCondStart: 472, .NumOperands: 4, .NumConds: 4 },
2123 {.AsmStrOffset: 2329, .AliasCondStart: 476, .NumOperands: 4, .NumConds: 4 },
2124 {.AsmStrOffset: 2347, .AliasCondStart: 480, .NumOperands: 4, .NumConds: 4 },
2125 {.AsmStrOffset: 2365, .AliasCondStart: 484, .NumOperands: 4, .NumConds: 4 },
2126 {.AsmStrOffset: 2384, .AliasCondStart: 488, .NumOperands: 4, .NumConds: 4 },
2127 {.AsmStrOffset: 2403, .AliasCondStart: 492, .NumOperands: 4, .NumConds: 4 },
2128 {.AsmStrOffset: 2421, .AliasCondStart: 496, .NumOperands: 4, .NumConds: 4 },
2129 {.AsmStrOffset: 2440, .AliasCondStart: 500, .NumOperands: 4, .NumConds: 4 },
2130 {.AsmStrOffset: 2460, .AliasCondStart: 504, .NumOperands: 4, .NumConds: 4 },
2131 {.AsmStrOffset: 2479, .AliasCondStart: 508, .NumOperands: 4, .NumConds: 4 },
2132 {.AsmStrOffset: 2498, .AliasCondStart: 512, .NumOperands: 4, .NumConds: 4 },
2133 {.AsmStrOffset: 2518, .AliasCondStart: 516, .NumOperands: 4, .NumConds: 4 },
2134 {.AsmStrOffset: 2538, .AliasCondStart: 520, .NumOperands: 4, .NumConds: 4 },
2135 {.AsmStrOffset: 2557, .AliasCondStart: 524, .NumOperands: 4, .NumConds: 4 },
2136 // SP::CWBCONDrr - 154
2137 {.AsmStrOffset: 2310, .AliasCondStart: 528, .NumOperands: 4, .NumConds: 5 },
2138 {.AsmStrOffset: 2329, .AliasCondStart: 533, .NumOperands: 4, .NumConds: 5 },
2139 {.AsmStrOffset: 2347, .AliasCondStart: 538, .NumOperands: 4, .NumConds: 5 },
2140 {.AsmStrOffset: 2365, .AliasCondStart: 543, .NumOperands: 4, .NumConds: 5 },
2141 {.AsmStrOffset: 2384, .AliasCondStart: 548, .NumOperands: 4, .NumConds: 5 },
2142 {.AsmStrOffset: 2403, .AliasCondStart: 553, .NumOperands: 4, .NumConds: 5 },
2143 {.AsmStrOffset: 2421, .AliasCondStart: 558, .NumOperands: 4, .NumConds: 5 },
2144 {.AsmStrOffset: 2440, .AliasCondStart: 563, .NumOperands: 4, .NumConds: 5 },
2145 {.AsmStrOffset: 2460, .AliasCondStart: 568, .NumOperands: 4, .NumConds: 5 },
2146 {.AsmStrOffset: 2479, .AliasCondStart: 573, .NumOperands: 4, .NumConds: 5 },
2147 {.AsmStrOffset: 2498, .AliasCondStart: 578, .NumOperands: 4, .NumConds: 5 },
2148 {.AsmStrOffset: 2518, .AliasCondStart: 583, .NumOperands: 4, .NumConds: 5 },
2149 {.AsmStrOffset: 2538, .AliasCondStart: 588, .NumOperands: 4, .NumConds: 5 },
2150 {.AsmStrOffset: 2557, .AliasCondStart: 593, .NumOperands: 4, .NumConds: 5 },
2151 // SP::CXBCONDri - 168
2152 {.AsmStrOffset: 2576, .AliasCondStart: 598, .NumOperands: 4, .NumConds: 4 },
2153 {.AsmStrOffset: 2595, .AliasCondStart: 602, .NumOperands: 4, .NumConds: 4 },
2154 {.AsmStrOffset: 2613, .AliasCondStart: 606, .NumOperands: 4, .NumConds: 4 },
2155 {.AsmStrOffset: 2631, .AliasCondStart: 610, .NumOperands: 4, .NumConds: 4 },
2156 {.AsmStrOffset: 2650, .AliasCondStart: 614, .NumOperands: 4, .NumConds: 4 },
2157 {.AsmStrOffset: 2669, .AliasCondStart: 618, .NumOperands: 4, .NumConds: 4 },
2158 {.AsmStrOffset: 2687, .AliasCondStart: 622, .NumOperands: 4, .NumConds: 4 },
2159 {.AsmStrOffset: 2706, .AliasCondStart: 626, .NumOperands: 4, .NumConds: 4 },
2160 {.AsmStrOffset: 2726, .AliasCondStart: 630, .NumOperands: 4, .NumConds: 4 },
2161 {.AsmStrOffset: 2745, .AliasCondStart: 634, .NumOperands: 4, .NumConds: 4 },
2162 {.AsmStrOffset: 2764, .AliasCondStart: 638, .NumOperands: 4, .NumConds: 4 },
2163 {.AsmStrOffset: 2784, .AliasCondStart: 642, .NumOperands: 4, .NumConds: 4 },
2164 {.AsmStrOffset: 2804, .AliasCondStart: 646, .NumOperands: 4, .NumConds: 4 },
2165 {.AsmStrOffset: 2823, .AliasCondStart: 650, .NumOperands: 4, .NumConds: 4 },
2166 // SP::CXBCONDrr - 182
2167 {.AsmStrOffset: 2576, .AliasCondStart: 654, .NumOperands: 4, .NumConds: 5 },
2168 {.AsmStrOffset: 2595, .AliasCondStart: 659, .NumOperands: 4, .NumConds: 5 },
2169 {.AsmStrOffset: 2613, .AliasCondStart: 664, .NumOperands: 4, .NumConds: 5 },
2170 {.AsmStrOffset: 2631, .AliasCondStart: 669, .NumOperands: 4, .NumConds: 5 },
2171 {.AsmStrOffset: 2650, .AliasCondStart: 674, .NumOperands: 4, .NumConds: 5 },
2172 {.AsmStrOffset: 2669, .AliasCondStart: 679, .NumOperands: 4, .NumConds: 5 },
2173 {.AsmStrOffset: 2687, .AliasCondStart: 684, .NumOperands: 4, .NumConds: 5 },
2174 {.AsmStrOffset: 2706, .AliasCondStart: 689, .NumOperands: 4, .NumConds: 5 },
2175 {.AsmStrOffset: 2726, .AliasCondStart: 694, .NumOperands: 4, .NumConds: 5 },
2176 {.AsmStrOffset: 2745, .AliasCondStart: 699, .NumOperands: 4, .NumConds: 5 },
2177 {.AsmStrOffset: 2764, .AliasCondStart: 704, .NumOperands: 4, .NumConds: 5 },
2178 {.AsmStrOffset: 2784, .AliasCondStart: 709, .NumOperands: 4, .NumConds: 5 },
2179 {.AsmStrOffset: 2804, .AliasCondStart: 714, .NumOperands: 4, .NumConds: 5 },
2180 {.AsmStrOffset: 2823, .AliasCondStart: 719, .NumOperands: 4, .NumConds: 5 },
2181 // SP::FMOVD_ICC - 196
2182 {.AsmStrOffset: 2842, .AliasCondStart: 724, .NumOperands: 4, .NumConds: 5 },
2183 {.AsmStrOffset: 2862, .AliasCondStart: 729, .NumOperands: 4, .NumConds: 6 },
2184 {.AsmStrOffset: 2882, .AliasCondStart: 735, .NumOperands: 4, .NumConds: 5 },
2185 {.AsmStrOffset: 2902, .AliasCondStart: 740, .NumOperands: 4, .NumConds: 6 },
2186 {.AsmStrOffset: 2922, .AliasCondStart: 746, .NumOperands: 4, .NumConds: 5 },
2187 {.AsmStrOffset: 2943, .AliasCondStart: 751, .NumOperands: 4, .NumConds: 6 },
2188 {.AsmStrOffset: 2964, .AliasCondStart: 757, .NumOperands: 4, .NumConds: 5 },
2189 {.AsmStrOffset: 2984, .AliasCondStart: 762, .NumOperands: 4, .NumConds: 6 },
2190 {.AsmStrOffset: 3004, .AliasCondStart: 768, .NumOperands: 4, .NumConds: 5 },
2191 {.AsmStrOffset: 3024, .AliasCondStart: 773, .NumOperands: 4, .NumConds: 6 },
2192 {.AsmStrOffset: 3044, .AliasCondStart: 779, .NumOperands: 4, .NumConds: 5 },
2193 {.AsmStrOffset: 3065, .AliasCondStart: 784, .NumOperands: 4, .NumConds: 6 },
2194 {.AsmStrOffset: 3086, .AliasCondStart: 790, .NumOperands: 4, .NumConds: 5 },
2195 {.AsmStrOffset: 3107, .AliasCondStart: 795, .NumOperands: 4, .NumConds: 6 },
2196 {.AsmStrOffset: 3128, .AliasCondStart: 801, .NumOperands: 4, .NumConds: 5 },
2197 {.AsmStrOffset: 3148, .AliasCondStart: 806, .NumOperands: 4, .NumConds: 6 },
2198 {.AsmStrOffset: 3168, .AliasCondStart: 812, .NumOperands: 4, .NumConds: 5 },
2199 {.AsmStrOffset: 3189, .AliasCondStart: 817, .NumOperands: 4, .NumConds: 6 },
2200 {.AsmStrOffset: 3210, .AliasCondStart: 823, .NumOperands: 4, .NumConds: 5 },
2201 {.AsmStrOffset: 3232, .AliasCondStart: 828, .NumOperands: 4, .NumConds: 6 },
2202 {.AsmStrOffset: 3254, .AliasCondStart: 834, .NumOperands: 4, .NumConds: 5 },
2203 {.AsmStrOffset: 3275, .AliasCondStart: 839, .NumOperands: 4, .NumConds: 6 },
2204 {.AsmStrOffset: 3296, .AliasCondStart: 845, .NumOperands: 4, .NumConds: 5 },
2205 {.AsmStrOffset: 3317, .AliasCondStart: 850, .NumOperands: 4, .NumConds: 6 },
2206 {.AsmStrOffset: 3338, .AliasCondStart: 856, .NumOperands: 4, .NumConds: 5 },
2207 {.AsmStrOffset: 3360, .AliasCondStart: 861, .NumOperands: 4, .NumConds: 6 },
2208 {.AsmStrOffset: 3382, .AliasCondStart: 867, .NumOperands: 4, .NumConds: 5 },
2209 {.AsmStrOffset: 3404, .AliasCondStart: 872, .NumOperands: 4, .NumConds: 6 },
2210 {.AsmStrOffset: 3426, .AliasCondStart: 878, .NumOperands: 4, .NumConds: 5 },
2211 {.AsmStrOffset: 3447, .AliasCondStart: 883, .NumOperands: 4, .NumConds: 6 },
2212 {.AsmStrOffset: 3468, .AliasCondStart: 889, .NumOperands: 4, .NumConds: 5 },
2213 {.AsmStrOffset: 3489, .AliasCondStart: 894, .NumOperands: 4, .NumConds: 6 },
2214 // SP::FMOVQ_ICC - 228
2215 {.AsmStrOffset: 3510, .AliasCondStart: 900, .NumOperands: 4, .NumConds: 5 },
2216 {.AsmStrOffset: 3530, .AliasCondStart: 905, .NumOperands: 4, .NumConds: 6 },
2217 {.AsmStrOffset: 3550, .AliasCondStart: 911, .NumOperands: 4, .NumConds: 5 },
2218 {.AsmStrOffset: 3570, .AliasCondStart: 916, .NumOperands: 4, .NumConds: 6 },
2219 {.AsmStrOffset: 3590, .AliasCondStart: 922, .NumOperands: 4, .NumConds: 5 },
2220 {.AsmStrOffset: 3611, .AliasCondStart: 927, .NumOperands: 4, .NumConds: 6 },
2221 {.AsmStrOffset: 3632, .AliasCondStart: 933, .NumOperands: 4, .NumConds: 5 },
2222 {.AsmStrOffset: 3652, .AliasCondStart: 938, .NumOperands: 4, .NumConds: 6 },
2223 {.AsmStrOffset: 3672, .AliasCondStart: 944, .NumOperands: 4, .NumConds: 5 },
2224 {.AsmStrOffset: 3692, .AliasCondStart: 949, .NumOperands: 4, .NumConds: 6 },
2225 {.AsmStrOffset: 3712, .AliasCondStart: 955, .NumOperands: 4, .NumConds: 5 },
2226 {.AsmStrOffset: 3733, .AliasCondStart: 960, .NumOperands: 4, .NumConds: 6 },
2227 {.AsmStrOffset: 3754, .AliasCondStart: 966, .NumOperands: 4, .NumConds: 5 },
2228 {.AsmStrOffset: 3775, .AliasCondStart: 971, .NumOperands: 4, .NumConds: 6 },
2229 {.AsmStrOffset: 3796, .AliasCondStart: 977, .NumOperands: 4, .NumConds: 5 },
2230 {.AsmStrOffset: 3816, .AliasCondStart: 982, .NumOperands: 4, .NumConds: 6 },
2231 {.AsmStrOffset: 3836, .AliasCondStart: 988, .NumOperands: 4, .NumConds: 5 },
2232 {.AsmStrOffset: 3857, .AliasCondStart: 993, .NumOperands: 4, .NumConds: 6 },
2233 {.AsmStrOffset: 3878, .AliasCondStart: 999, .NumOperands: 4, .NumConds: 5 },
2234 {.AsmStrOffset: 3900, .AliasCondStart: 1004, .NumOperands: 4, .NumConds: 6 },
2235 {.AsmStrOffset: 3922, .AliasCondStart: 1010, .NumOperands: 4, .NumConds: 5 },
2236 {.AsmStrOffset: 3943, .AliasCondStart: 1015, .NumOperands: 4, .NumConds: 6 },
2237 {.AsmStrOffset: 3964, .AliasCondStart: 1021, .NumOperands: 4, .NumConds: 5 },
2238 {.AsmStrOffset: 3985, .AliasCondStart: 1026, .NumOperands: 4, .NumConds: 6 },
2239 {.AsmStrOffset: 4006, .AliasCondStart: 1032, .NumOperands: 4, .NumConds: 5 },
2240 {.AsmStrOffset: 4028, .AliasCondStart: 1037, .NumOperands: 4, .NumConds: 6 },
2241 {.AsmStrOffset: 4050, .AliasCondStart: 1043, .NumOperands: 4, .NumConds: 5 },
2242 {.AsmStrOffset: 4072, .AliasCondStart: 1048, .NumOperands: 4, .NumConds: 6 },
2243 {.AsmStrOffset: 4094, .AliasCondStart: 1054, .NumOperands: 4, .NumConds: 5 },
2244 {.AsmStrOffset: 4115, .AliasCondStart: 1059, .NumOperands: 4, .NumConds: 6 },
2245 {.AsmStrOffset: 4136, .AliasCondStart: 1065, .NumOperands: 4, .NumConds: 5 },
2246 {.AsmStrOffset: 4157, .AliasCondStart: 1070, .NumOperands: 4, .NumConds: 6 },
2247 // SP::FMOVRD - 260
2248 {.AsmStrOffset: 4178, .AliasCondStart: 1076, .NumOperands: 5, .NumConds: 6 },
2249 {.AsmStrOffset: 4199, .AliasCondStart: 1082, .NumOperands: 5, .NumConds: 6 },
2250 {.AsmStrOffset: 4219, .AliasCondStart: 1088, .NumOperands: 5, .NumConds: 6 },
2251 {.AsmStrOffset: 4239, .AliasCondStart: 1094, .NumOperands: 5, .NumConds: 6 },
2252 // SP::FMOVRQ - 264
2253 {.AsmStrOffset: 4260, .AliasCondStart: 1100, .NumOperands: 5, .NumConds: 6 },
2254 {.AsmStrOffset: 4281, .AliasCondStart: 1106, .NumOperands: 5, .NumConds: 6 },
2255 {.AsmStrOffset: 4301, .AliasCondStart: 1112, .NumOperands: 5, .NumConds: 6 },
2256 {.AsmStrOffset: 4321, .AliasCondStart: 1118, .NumOperands: 5, .NumConds: 6 },
2257 // SP::FMOVRS - 268
2258 {.AsmStrOffset: 4342, .AliasCondStart: 1124, .NumOperands: 5, .NumConds: 6 },
2259 {.AsmStrOffset: 4363, .AliasCondStart: 1130, .NumOperands: 5, .NumConds: 6 },
2260 {.AsmStrOffset: 4383, .AliasCondStart: 1136, .NumOperands: 5, .NumConds: 6 },
2261 {.AsmStrOffset: 4403, .AliasCondStart: 1142, .NumOperands: 5, .NumConds: 6 },
2262 // SP::FMOVS_ICC - 272
2263 {.AsmStrOffset: 4424, .AliasCondStart: 1148, .NumOperands: 4, .NumConds: 5 },
2264 {.AsmStrOffset: 4444, .AliasCondStart: 1153, .NumOperands: 4, .NumConds: 6 },
2265 {.AsmStrOffset: 4464, .AliasCondStart: 1159, .NumOperands: 4, .NumConds: 5 },
2266 {.AsmStrOffset: 4484, .AliasCondStart: 1164, .NumOperands: 4, .NumConds: 6 },
2267 {.AsmStrOffset: 4504, .AliasCondStart: 1170, .NumOperands: 4, .NumConds: 5 },
2268 {.AsmStrOffset: 4525, .AliasCondStart: 1175, .NumOperands: 4, .NumConds: 6 },
2269 {.AsmStrOffset: 4546, .AliasCondStart: 1181, .NumOperands: 4, .NumConds: 5 },
2270 {.AsmStrOffset: 4566, .AliasCondStart: 1186, .NumOperands: 4, .NumConds: 6 },
2271 {.AsmStrOffset: 4586, .AliasCondStart: 1192, .NumOperands: 4, .NumConds: 5 },
2272 {.AsmStrOffset: 4606, .AliasCondStart: 1197, .NumOperands: 4, .NumConds: 6 },
2273 {.AsmStrOffset: 4626, .AliasCondStart: 1203, .NumOperands: 4, .NumConds: 5 },
2274 {.AsmStrOffset: 4647, .AliasCondStart: 1208, .NumOperands: 4, .NumConds: 6 },
2275 {.AsmStrOffset: 4668, .AliasCondStart: 1214, .NumOperands: 4, .NumConds: 5 },
2276 {.AsmStrOffset: 4689, .AliasCondStart: 1219, .NumOperands: 4, .NumConds: 6 },
2277 {.AsmStrOffset: 4710, .AliasCondStart: 1225, .NumOperands: 4, .NumConds: 5 },
2278 {.AsmStrOffset: 4730, .AliasCondStart: 1230, .NumOperands: 4, .NumConds: 6 },
2279 {.AsmStrOffset: 4750, .AliasCondStart: 1236, .NumOperands: 4, .NumConds: 5 },
2280 {.AsmStrOffset: 4771, .AliasCondStart: 1241, .NumOperands: 4, .NumConds: 6 },
2281 {.AsmStrOffset: 4792, .AliasCondStart: 1247, .NumOperands: 4, .NumConds: 5 },
2282 {.AsmStrOffset: 4814, .AliasCondStart: 1252, .NumOperands: 4, .NumConds: 6 },
2283 {.AsmStrOffset: 4836, .AliasCondStart: 1258, .NumOperands: 4, .NumConds: 5 },
2284 {.AsmStrOffset: 4857, .AliasCondStart: 1263, .NumOperands: 4, .NumConds: 6 },
2285 {.AsmStrOffset: 4878, .AliasCondStart: 1269, .NumOperands: 4, .NumConds: 5 },
2286 {.AsmStrOffset: 4899, .AliasCondStart: 1274, .NumOperands: 4, .NumConds: 6 },
2287 {.AsmStrOffset: 4920, .AliasCondStart: 1280, .NumOperands: 4, .NumConds: 5 },
2288 {.AsmStrOffset: 4942, .AliasCondStart: 1285, .NumOperands: 4, .NumConds: 6 },
2289 {.AsmStrOffset: 4964, .AliasCondStart: 1291, .NumOperands: 4, .NumConds: 5 },
2290 {.AsmStrOffset: 4986, .AliasCondStart: 1296, .NumOperands: 4, .NumConds: 6 },
2291 {.AsmStrOffset: 5008, .AliasCondStart: 1302, .NumOperands: 4, .NumConds: 5 },
2292 {.AsmStrOffset: 5029, .AliasCondStart: 1307, .NumOperands: 4, .NumConds: 6 },
2293 {.AsmStrOffset: 5050, .AliasCondStart: 1313, .NumOperands: 4, .NumConds: 5 },
2294 {.AsmStrOffset: 5071, .AliasCondStart: 1318, .NumOperands: 4, .NumConds: 6 },
2295 // SP::MOVICCri - 304
2296 {.AsmStrOffset: 5092, .AliasCondStart: 1324, .NumOperands: 4, .NumConds: 5 },
2297 {.AsmStrOffset: 5110, .AliasCondStart: 1329, .NumOperands: 4, .NumConds: 6 },
2298 {.AsmStrOffset: 5128, .AliasCondStart: 1335, .NumOperands: 4, .NumConds: 5 },
2299 {.AsmStrOffset: 5146, .AliasCondStart: 1340, .NumOperands: 4, .NumConds: 6 },
2300 {.AsmStrOffset: 5164, .AliasCondStart: 1346, .NumOperands: 4, .NumConds: 5 },
2301 {.AsmStrOffset: 5183, .AliasCondStart: 1351, .NumOperands: 4, .NumConds: 6 },
2302 {.AsmStrOffset: 5202, .AliasCondStart: 1357, .NumOperands: 4, .NumConds: 5 },
2303 {.AsmStrOffset: 5220, .AliasCondStart: 1362, .NumOperands: 4, .NumConds: 6 },
2304 {.AsmStrOffset: 5238, .AliasCondStart: 1368, .NumOperands: 4, .NumConds: 5 },
2305 {.AsmStrOffset: 5256, .AliasCondStart: 1373, .NumOperands: 4, .NumConds: 6 },
2306 {.AsmStrOffset: 5274, .AliasCondStart: 1379, .NumOperands: 4, .NumConds: 5 },
2307 {.AsmStrOffset: 5293, .AliasCondStart: 1384, .NumOperands: 4, .NumConds: 6 },
2308 {.AsmStrOffset: 5312, .AliasCondStart: 1390, .NumOperands: 4, .NumConds: 5 },
2309 {.AsmStrOffset: 5331, .AliasCondStart: 1395, .NumOperands: 4, .NumConds: 6 },
2310 {.AsmStrOffset: 5350, .AliasCondStart: 1401, .NumOperands: 4, .NumConds: 5 },
2311 {.AsmStrOffset: 5368, .AliasCondStart: 1406, .NumOperands: 4, .NumConds: 6 },
2312 {.AsmStrOffset: 5386, .AliasCondStart: 1412, .NumOperands: 4, .NumConds: 5 },
2313 {.AsmStrOffset: 5405, .AliasCondStart: 1417, .NumOperands: 4, .NumConds: 6 },
2314 {.AsmStrOffset: 5424, .AliasCondStart: 1423, .NumOperands: 4, .NumConds: 5 },
2315 {.AsmStrOffset: 5444, .AliasCondStart: 1428, .NumOperands: 4, .NumConds: 6 },
2316 {.AsmStrOffset: 5464, .AliasCondStart: 1434, .NumOperands: 4, .NumConds: 5 },
2317 {.AsmStrOffset: 5483, .AliasCondStart: 1439, .NumOperands: 4, .NumConds: 6 },
2318 {.AsmStrOffset: 5502, .AliasCondStart: 1445, .NumOperands: 4, .NumConds: 5 },
2319 {.AsmStrOffset: 5521, .AliasCondStart: 1450, .NumOperands: 4, .NumConds: 6 },
2320 {.AsmStrOffset: 5540, .AliasCondStart: 1456, .NumOperands: 4, .NumConds: 5 },
2321 {.AsmStrOffset: 5560, .AliasCondStart: 1461, .NumOperands: 4, .NumConds: 6 },
2322 {.AsmStrOffset: 5580, .AliasCondStart: 1467, .NumOperands: 4, .NumConds: 5 },
2323 {.AsmStrOffset: 5600, .AliasCondStart: 1472, .NumOperands: 4, .NumConds: 6 },
2324 {.AsmStrOffset: 5620, .AliasCondStart: 1478, .NumOperands: 4, .NumConds: 5 },
2325 {.AsmStrOffset: 5639, .AliasCondStart: 1483, .NumOperands: 4, .NumConds: 6 },
2326 {.AsmStrOffset: 5658, .AliasCondStart: 1489, .NumOperands: 4, .NumConds: 5 },
2327 {.AsmStrOffset: 5677, .AliasCondStart: 1494, .NumOperands: 4, .NumConds: 6 },
2328 // SP::MOVICCrr - 336
2329 {.AsmStrOffset: 5092, .AliasCondStart: 1500, .NumOperands: 4, .NumConds: 5 },
2330 {.AsmStrOffset: 5110, .AliasCondStart: 1505, .NumOperands: 4, .NumConds: 6 },
2331 {.AsmStrOffset: 5128, .AliasCondStart: 1511, .NumOperands: 4, .NumConds: 5 },
2332 {.AsmStrOffset: 5146, .AliasCondStart: 1516, .NumOperands: 4, .NumConds: 6 },
2333 {.AsmStrOffset: 5164, .AliasCondStart: 1522, .NumOperands: 4, .NumConds: 5 },
2334 {.AsmStrOffset: 5183, .AliasCondStart: 1527, .NumOperands: 4, .NumConds: 6 },
2335 {.AsmStrOffset: 5202, .AliasCondStart: 1533, .NumOperands: 4, .NumConds: 5 },
2336 {.AsmStrOffset: 5220, .AliasCondStart: 1538, .NumOperands: 4, .NumConds: 6 },
2337 {.AsmStrOffset: 5238, .AliasCondStart: 1544, .NumOperands: 4, .NumConds: 5 },
2338 {.AsmStrOffset: 5256, .AliasCondStart: 1549, .NumOperands: 4, .NumConds: 6 },
2339 {.AsmStrOffset: 5274, .AliasCondStart: 1555, .NumOperands: 4, .NumConds: 5 },
2340 {.AsmStrOffset: 5293, .AliasCondStart: 1560, .NumOperands: 4, .NumConds: 6 },
2341 {.AsmStrOffset: 5312, .AliasCondStart: 1566, .NumOperands: 4, .NumConds: 5 },
2342 {.AsmStrOffset: 5331, .AliasCondStart: 1571, .NumOperands: 4, .NumConds: 6 },
2343 {.AsmStrOffset: 5350, .AliasCondStart: 1577, .NumOperands: 4, .NumConds: 5 },
2344 {.AsmStrOffset: 5368, .AliasCondStart: 1582, .NumOperands: 4, .NumConds: 6 },
2345 {.AsmStrOffset: 5386, .AliasCondStart: 1588, .NumOperands: 4, .NumConds: 5 },
2346 {.AsmStrOffset: 5405, .AliasCondStart: 1593, .NumOperands: 4, .NumConds: 6 },
2347 {.AsmStrOffset: 5424, .AliasCondStart: 1599, .NumOperands: 4, .NumConds: 5 },
2348 {.AsmStrOffset: 5444, .AliasCondStart: 1604, .NumOperands: 4, .NumConds: 6 },
2349 {.AsmStrOffset: 5464, .AliasCondStart: 1610, .NumOperands: 4, .NumConds: 5 },
2350 {.AsmStrOffset: 5483, .AliasCondStart: 1615, .NumOperands: 4, .NumConds: 6 },
2351 {.AsmStrOffset: 5502, .AliasCondStart: 1621, .NumOperands: 4, .NumConds: 5 },
2352 {.AsmStrOffset: 5521, .AliasCondStart: 1626, .NumOperands: 4, .NumConds: 6 },
2353 {.AsmStrOffset: 5540, .AliasCondStart: 1632, .NumOperands: 4, .NumConds: 5 },
2354 {.AsmStrOffset: 5560, .AliasCondStart: 1637, .NumOperands: 4, .NumConds: 6 },
2355 {.AsmStrOffset: 5580, .AliasCondStart: 1643, .NumOperands: 4, .NumConds: 5 },
2356 {.AsmStrOffset: 5600, .AliasCondStart: 1648, .NumOperands: 4, .NumConds: 6 },
2357 {.AsmStrOffset: 5620, .AliasCondStart: 1654, .NumOperands: 4, .NumConds: 5 },
2358 {.AsmStrOffset: 5639, .AliasCondStart: 1659, .NumOperands: 4, .NumConds: 6 },
2359 {.AsmStrOffset: 5658, .AliasCondStart: 1665, .NumOperands: 4, .NumConds: 5 },
2360 {.AsmStrOffset: 5677, .AliasCondStart: 1670, .NumOperands: 4, .NumConds: 6 },
2361 // SP::MOVRri - 368
2362 {.AsmStrOffset: 5696, .AliasCondStart: 1676, .NumOperands: 5, .NumConds: 6 },
2363 {.AsmStrOffset: 5715, .AliasCondStart: 1682, .NumOperands: 5, .NumConds: 6 },
2364 {.AsmStrOffset: 5733, .AliasCondStart: 1688, .NumOperands: 5, .NumConds: 6 },
2365 {.AsmStrOffset: 5751, .AliasCondStart: 1694, .NumOperands: 5, .NumConds: 6 },
2366 // SP::MOVRrr - 372
2367 {.AsmStrOffset: 5696, .AliasCondStart: 1700, .NumOperands: 5, .NumConds: 6 },
2368 {.AsmStrOffset: 5715, .AliasCondStart: 1706, .NumOperands: 5, .NumConds: 6 },
2369 {.AsmStrOffset: 5733, .AliasCondStart: 1712, .NumOperands: 5, .NumConds: 6 },
2370 {.AsmStrOffset: 5751, .AliasCondStart: 1718, .NumOperands: 5, .NumConds: 6 },
2371 // SP::ORCCrr - 376
2372 {.AsmStrOffset: 5770, .AliasCondStart: 1724, .NumOperands: 3, .NumConds: 3 },
2373 // SP::ORri - 377
2374 {.AsmStrOffset: 5777, .AliasCondStart: 1727, .NumOperands: 3, .NumConds: 2 },
2375 // SP::ORrr - 378
2376 {.AsmStrOffset: 5777, .AliasCondStart: 1729, .NumOperands: 3, .NumConds: 3 },
2377 // SP::RESTORErr - 379
2378 {.AsmStrOffset: 5788, .AliasCondStart: 1732, .NumOperands: 3, .NumConds: 3 },
2379 // SP::RET - 380
2380 {.AsmStrOffset: 5796, .AliasCondStart: 1735, .NumOperands: 1, .NumConds: 1 },
2381 // SP::RETL - 381
2382 {.AsmStrOffset: 5800, .AliasCondStart: 1736, .NumOperands: 1, .NumConds: 1 },
2383 // SP::SAVErr - 382
2384 {.AsmStrOffset: 5805, .AliasCondStart: 1737, .NumOperands: 3, .NumConds: 3 },
2385 // SP::SUBCCri - 383
2386 {.AsmStrOffset: 5810, .AliasCondStart: 1740, .NumOperands: 3, .NumConds: 2 },
2387 // SP::SUBCCrr - 384
2388 {.AsmStrOffset: 5810, .AliasCondStart: 1742, .NumOperands: 3, .NumConds: 3 },
2389 // SP::TICCri - 385
2390 {.AsmStrOffset: 5821, .AliasCondStart: 1745, .NumOperands: 3, .NumConds: 4 },
2391 {.AsmStrOffset: 5833, .AliasCondStart: 1749, .NumOperands: 3, .NumConds: 5 },
2392 {.AsmStrOffset: 5845, .AliasCondStart: 1754, .NumOperands: 3, .NumConds: 4 },
2393 {.AsmStrOffset: 5862, .AliasCondStart: 1758, .NumOperands: 3, .NumConds: 5 },
2394 {.AsmStrOffset: 5879, .AliasCondStart: 1763, .NumOperands: 3, .NumConds: 4 },
2395 {.AsmStrOffset: 5891, .AliasCondStart: 1767, .NumOperands: 3, .NumConds: 5 },
2396 {.AsmStrOffset: 5903, .AliasCondStart: 1772, .NumOperands: 3, .NumConds: 4 },
2397 {.AsmStrOffset: 5920, .AliasCondStart: 1776, .NumOperands: 3, .NumConds: 5 },
2398 {.AsmStrOffset: 5937, .AliasCondStart: 1781, .NumOperands: 3, .NumConds: 4 },
2399 {.AsmStrOffset: 5950, .AliasCondStart: 1785, .NumOperands: 3, .NumConds: 5 },
2400 {.AsmStrOffset: 5963, .AliasCondStart: 1790, .NumOperands: 3, .NumConds: 4 },
2401 {.AsmStrOffset: 5981, .AliasCondStart: 1794, .NumOperands: 3, .NumConds: 5 },
2402 {.AsmStrOffset: 5999, .AliasCondStart: 1799, .NumOperands: 3, .NumConds: 4 },
2403 {.AsmStrOffset: 6011, .AliasCondStart: 1803, .NumOperands: 3, .NumConds: 5 },
2404 {.AsmStrOffset: 6023, .AliasCondStart: 1808, .NumOperands: 3, .NumConds: 4 },
2405 {.AsmStrOffset: 6040, .AliasCondStart: 1812, .NumOperands: 3, .NumConds: 5 },
2406 {.AsmStrOffset: 6057, .AliasCondStart: 1817, .NumOperands: 3, .NumConds: 4 },
2407 {.AsmStrOffset: 6069, .AliasCondStart: 1821, .NumOperands: 3, .NumConds: 5 },
2408 {.AsmStrOffset: 6081, .AliasCondStart: 1826, .NumOperands: 3, .NumConds: 4 },
2409 {.AsmStrOffset: 6098, .AliasCondStart: 1830, .NumOperands: 3, .NumConds: 5 },
2410 {.AsmStrOffset: 6115, .AliasCondStart: 1835, .NumOperands: 3, .NumConds: 4 },
2411 {.AsmStrOffset: 6128, .AliasCondStart: 1839, .NumOperands: 3, .NumConds: 5 },
2412 {.AsmStrOffset: 6141, .AliasCondStart: 1844, .NumOperands: 3, .NumConds: 4 },
2413 {.AsmStrOffset: 6159, .AliasCondStart: 1848, .NumOperands: 3, .NumConds: 5 },
2414 {.AsmStrOffset: 6177, .AliasCondStart: 1853, .NumOperands: 3, .NumConds: 4 },
2415 {.AsmStrOffset: 6190, .AliasCondStart: 1857, .NumOperands: 3, .NumConds: 5 },
2416 {.AsmStrOffset: 6203, .AliasCondStart: 1862, .NumOperands: 3, .NumConds: 4 },
2417 {.AsmStrOffset: 6221, .AliasCondStart: 1866, .NumOperands: 3, .NumConds: 5 },
2418 {.AsmStrOffset: 6239, .AliasCondStart: 1871, .NumOperands: 3, .NumConds: 4 },
2419 {.AsmStrOffset: 6251, .AliasCondStart: 1875, .NumOperands: 3, .NumConds: 5 },
2420 {.AsmStrOffset: 6263, .AliasCondStart: 1880, .NumOperands: 3, .NumConds: 4 },
2421 {.AsmStrOffset: 6280, .AliasCondStart: 1884, .NumOperands: 3, .NumConds: 5 },
2422 {.AsmStrOffset: 6297, .AliasCondStart: 1889, .NumOperands: 3, .NumConds: 4 },
2423 {.AsmStrOffset: 6310, .AliasCondStart: 1893, .NumOperands: 3, .NumConds: 5 },
2424 {.AsmStrOffset: 6323, .AliasCondStart: 1898, .NumOperands: 3, .NumConds: 4 },
2425 {.AsmStrOffset: 6341, .AliasCondStart: 1902, .NumOperands: 3, .NumConds: 5 },
2426 {.AsmStrOffset: 6359, .AliasCondStart: 1907, .NumOperands: 3, .NumConds: 4 },
2427 {.AsmStrOffset: 6373, .AliasCondStart: 1911, .NumOperands: 3, .NumConds: 5 },
2428 {.AsmStrOffset: 6387, .AliasCondStart: 1916, .NumOperands: 3, .NumConds: 4 },
2429 {.AsmStrOffset: 6406, .AliasCondStart: 1920, .NumOperands: 3, .NumConds: 5 },
2430 {.AsmStrOffset: 6425, .AliasCondStart: 1925, .NumOperands: 3, .NumConds: 4 },
2431 {.AsmStrOffset: 6438, .AliasCondStart: 1929, .NumOperands: 3, .NumConds: 5 },
2432 {.AsmStrOffset: 6451, .AliasCondStart: 1934, .NumOperands: 3, .NumConds: 4 },
2433 {.AsmStrOffset: 6469, .AliasCondStart: 1938, .NumOperands: 3, .NumConds: 5 },
2434 {.AsmStrOffset: 6487, .AliasCondStart: 1943, .NumOperands: 3, .NumConds: 4 },
2435 {.AsmStrOffset: 6500, .AliasCondStart: 1947, .NumOperands: 3, .NumConds: 5 },
2436 {.AsmStrOffset: 6513, .AliasCondStart: 1952, .NumOperands: 3, .NumConds: 4 },
2437 {.AsmStrOffset: 6531, .AliasCondStart: 1956, .NumOperands: 3, .NumConds: 5 },
2438 {.AsmStrOffset: 6549, .AliasCondStart: 1961, .NumOperands: 3, .NumConds: 4 },
2439 {.AsmStrOffset: 6563, .AliasCondStart: 1965, .NumOperands: 3, .NumConds: 5 },
2440 {.AsmStrOffset: 6577, .AliasCondStart: 1970, .NumOperands: 3, .NumConds: 4 },
2441 {.AsmStrOffset: 6596, .AliasCondStart: 1974, .NumOperands: 3, .NumConds: 5 },
2442 {.AsmStrOffset: 6615, .AliasCondStart: 1979, .NumOperands: 3, .NumConds: 4 },
2443 {.AsmStrOffset: 6629, .AliasCondStart: 1983, .NumOperands: 3, .NumConds: 5 },
2444 {.AsmStrOffset: 6643, .AliasCondStart: 1988, .NumOperands: 3, .NumConds: 4 },
2445 {.AsmStrOffset: 6662, .AliasCondStart: 1992, .NumOperands: 3, .NumConds: 5 },
2446 {.AsmStrOffset: 6681, .AliasCondStart: 1997, .NumOperands: 3, .NumConds: 4 },
2447 {.AsmStrOffset: 6694, .AliasCondStart: 2001, .NumOperands: 3, .NumConds: 5 },
2448 {.AsmStrOffset: 6707, .AliasCondStart: 2006, .NumOperands: 3, .NumConds: 4 },
2449 {.AsmStrOffset: 6725, .AliasCondStart: 2010, .NumOperands: 3, .NumConds: 5 },
2450 {.AsmStrOffset: 6743, .AliasCondStart: 2015, .NumOperands: 3, .NumConds: 4 },
2451 {.AsmStrOffset: 6756, .AliasCondStart: 2019, .NumOperands: 3, .NumConds: 5 },
2452 {.AsmStrOffset: 6769, .AliasCondStart: 2024, .NumOperands: 3, .NumConds: 4 },
2453 {.AsmStrOffset: 6787, .AliasCondStart: 2028, .NumOperands: 3, .NumConds: 5 },
2454 // SP::TICCrr - 449
2455 {.AsmStrOffset: 5821, .AliasCondStart: 2033, .NumOperands: 3, .NumConds: 4 },
2456 {.AsmStrOffset: 5833, .AliasCondStart: 2037, .NumOperands: 3, .NumConds: 5 },
2457 {.AsmStrOffset: 5845, .AliasCondStart: 2042, .NumOperands: 3, .NumConds: 4 },
2458 {.AsmStrOffset: 5862, .AliasCondStart: 2046, .NumOperands: 3, .NumConds: 5 },
2459 {.AsmStrOffset: 5879, .AliasCondStart: 2051, .NumOperands: 3, .NumConds: 4 },
2460 {.AsmStrOffset: 5891, .AliasCondStart: 2055, .NumOperands: 3, .NumConds: 5 },
2461 {.AsmStrOffset: 5903, .AliasCondStart: 2060, .NumOperands: 3, .NumConds: 4 },
2462 {.AsmStrOffset: 5920, .AliasCondStart: 2064, .NumOperands: 3, .NumConds: 5 },
2463 {.AsmStrOffset: 5937, .AliasCondStart: 2069, .NumOperands: 3, .NumConds: 4 },
2464 {.AsmStrOffset: 5950, .AliasCondStart: 2073, .NumOperands: 3, .NumConds: 5 },
2465 {.AsmStrOffset: 5963, .AliasCondStart: 2078, .NumOperands: 3, .NumConds: 4 },
2466 {.AsmStrOffset: 5981, .AliasCondStart: 2082, .NumOperands: 3, .NumConds: 5 },
2467 {.AsmStrOffset: 5999, .AliasCondStart: 2087, .NumOperands: 3, .NumConds: 4 },
2468 {.AsmStrOffset: 6011, .AliasCondStart: 2091, .NumOperands: 3, .NumConds: 5 },
2469 {.AsmStrOffset: 6023, .AliasCondStart: 2096, .NumOperands: 3, .NumConds: 4 },
2470 {.AsmStrOffset: 6040, .AliasCondStart: 2100, .NumOperands: 3, .NumConds: 5 },
2471 {.AsmStrOffset: 6057, .AliasCondStart: 2105, .NumOperands: 3, .NumConds: 4 },
2472 {.AsmStrOffset: 6069, .AliasCondStart: 2109, .NumOperands: 3, .NumConds: 5 },
2473 {.AsmStrOffset: 6081, .AliasCondStart: 2114, .NumOperands: 3, .NumConds: 4 },
2474 {.AsmStrOffset: 6098, .AliasCondStart: 2118, .NumOperands: 3, .NumConds: 5 },
2475 {.AsmStrOffset: 6115, .AliasCondStart: 2123, .NumOperands: 3, .NumConds: 4 },
2476 {.AsmStrOffset: 6128, .AliasCondStart: 2127, .NumOperands: 3, .NumConds: 5 },
2477 {.AsmStrOffset: 6141, .AliasCondStart: 2132, .NumOperands: 3, .NumConds: 4 },
2478 {.AsmStrOffset: 6159, .AliasCondStart: 2136, .NumOperands: 3, .NumConds: 5 },
2479 {.AsmStrOffset: 6177, .AliasCondStart: 2141, .NumOperands: 3, .NumConds: 4 },
2480 {.AsmStrOffset: 6190, .AliasCondStart: 2145, .NumOperands: 3, .NumConds: 5 },
2481 {.AsmStrOffset: 6203, .AliasCondStart: 2150, .NumOperands: 3, .NumConds: 4 },
2482 {.AsmStrOffset: 6221, .AliasCondStart: 2154, .NumOperands: 3, .NumConds: 5 },
2483 {.AsmStrOffset: 6239, .AliasCondStart: 2159, .NumOperands: 3, .NumConds: 4 },
2484 {.AsmStrOffset: 6251, .AliasCondStart: 2163, .NumOperands: 3, .NumConds: 5 },
2485 {.AsmStrOffset: 6263, .AliasCondStart: 2168, .NumOperands: 3, .NumConds: 4 },
2486 {.AsmStrOffset: 6280, .AliasCondStart: 2172, .NumOperands: 3, .NumConds: 5 },
2487 {.AsmStrOffset: 6297, .AliasCondStart: 2177, .NumOperands: 3, .NumConds: 4 },
2488 {.AsmStrOffset: 6310, .AliasCondStart: 2181, .NumOperands: 3, .NumConds: 5 },
2489 {.AsmStrOffset: 6323, .AliasCondStart: 2186, .NumOperands: 3, .NumConds: 4 },
2490 {.AsmStrOffset: 6341, .AliasCondStart: 2190, .NumOperands: 3, .NumConds: 5 },
2491 {.AsmStrOffset: 6359, .AliasCondStart: 2195, .NumOperands: 3, .NumConds: 4 },
2492 {.AsmStrOffset: 6373, .AliasCondStart: 2199, .NumOperands: 3, .NumConds: 5 },
2493 {.AsmStrOffset: 6387, .AliasCondStart: 2204, .NumOperands: 3, .NumConds: 4 },
2494 {.AsmStrOffset: 6406, .AliasCondStart: 2208, .NumOperands: 3, .NumConds: 5 },
2495 {.AsmStrOffset: 6425, .AliasCondStart: 2213, .NumOperands: 3, .NumConds: 4 },
2496 {.AsmStrOffset: 6438, .AliasCondStart: 2217, .NumOperands: 3, .NumConds: 5 },
2497 {.AsmStrOffset: 6451, .AliasCondStart: 2222, .NumOperands: 3, .NumConds: 4 },
2498 {.AsmStrOffset: 6469, .AliasCondStart: 2226, .NumOperands: 3, .NumConds: 5 },
2499 {.AsmStrOffset: 6487, .AliasCondStart: 2231, .NumOperands: 3, .NumConds: 4 },
2500 {.AsmStrOffset: 6500, .AliasCondStart: 2235, .NumOperands: 3, .NumConds: 5 },
2501 {.AsmStrOffset: 6513, .AliasCondStart: 2240, .NumOperands: 3, .NumConds: 4 },
2502 {.AsmStrOffset: 6531, .AliasCondStart: 2244, .NumOperands: 3, .NumConds: 5 },
2503 {.AsmStrOffset: 6549, .AliasCondStart: 2249, .NumOperands: 3, .NumConds: 4 },
2504 {.AsmStrOffset: 6563, .AliasCondStart: 2253, .NumOperands: 3, .NumConds: 5 },
2505 {.AsmStrOffset: 6577, .AliasCondStart: 2258, .NumOperands: 3, .NumConds: 4 },
2506 {.AsmStrOffset: 6596, .AliasCondStart: 2262, .NumOperands: 3, .NumConds: 5 },
2507 {.AsmStrOffset: 6615, .AliasCondStart: 2267, .NumOperands: 3, .NumConds: 4 },
2508 {.AsmStrOffset: 6629, .AliasCondStart: 2271, .NumOperands: 3, .NumConds: 5 },
2509 {.AsmStrOffset: 6643, .AliasCondStart: 2276, .NumOperands: 3, .NumConds: 4 },
2510 {.AsmStrOffset: 6662, .AliasCondStart: 2280, .NumOperands: 3, .NumConds: 5 },
2511 {.AsmStrOffset: 6681, .AliasCondStart: 2285, .NumOperands: 3, .NumConds: 4 },
2512 {.AsmStrOffset: 6694, .AliasCondStart: 2289, .NumOperands: 3, .NumConds: 5 },
2513 {.AsmStrOffset: 6707, .AliasCondStart: 2294, .NumOperands: 3, .NumConds: 4 },
2514 {.AsmStrOffset: 6725, .AliasCondStart: 2298, .NumOperands: 3, .NumConds: 5 },
2515 {.AsmStrOffset: 6743, .AliasCondStart: 2303, .NumOperands: 3, .NumConds: 4 },
2516 {.AsmStrOffset: 6756, .AliasCondStart: 2307, .NumOperands: 3, .NumConds: 5 },
2517 {.AsmStrOffset: 6769, .AliasCondStart: 2312, .NumOperands: 3, .NumConds: 4 },
2518 {.AsmStrOffset: 6787, .AliasCondStart: 2316, .NumOperands: 3, .NumConds: 5 },
2519 // SP::TRAPri - 513
2520 {.AsmStrOffset: 6805, .AliasCondStart: 2321, .NumOperands: 3, .NumConds: 3 },
2521 {.AsmStrOffset: 6811, .AliasCondStart: 2324, .NumOperands: 3, .NumConds: 3 },
2522 {.AsmStrOffset: 6822, .AliasCondStart: 2327, .NumOperands: 3, .NumConds: 3 },
2523 {.AsmStrOffset: 6828, .AliasCondStart: 2330, .NumOperands: 3, .NumConds: 3 },
2524 {.AsmStrOffset: 6839, .AliasCondStart: 2333, .NumOperands: 3, .NumConds: 3 },
2525 {.AsmStrOffset: 6846, .AliasCondStart: 2336, .NumOperands: 3, .NumConds: 3 },
2526 {.AsmStrOffset: 6858, .AliasCondStart: 2339, .NumOperands: 3, .NumConds: 3 },
2527 {.AsmStrOffset: 6864, .AliasCondStart: 2342, .NumOperands: 3, .NumConds: 3 },
2528 {.AsmStrOffset: 6875, .AliasCondStart: 2345, .NumOperands: 3, .NumConds: 3 },
2529 {.AsmStrOffset: 6881, .AliasCondStart: 2348, .NumOperands: 3, .NumConds: 3 },
2530 {.AsmStrOffset: 6892, .AliasCondStart: 2351, .NumOperands: 3, .NumConds: 3 },
2531 {.AsmStrOffset: 6899, .AliasCondStart: 2354, .NumOperands: 3, .NumConds: 3 },
2532 {.AsmStrOffset: 6911, .AliasCondStart: 2357, .NumOperands: 3, .NumConds: 3 },
2533 {.AsmStrOffset: 6918, .AliasCondStart: 2360, .NumOperands: 3, .NumConds: 3 },
2534 {.AsmStrOffset: 6930, .AliasCondStart: 2363, .NumOperands: 3, .NumConds: 3 },
2535 {.AsmStrOffset: 6936, .AliasCondStart: 2366, .NumOperands: 3, .NumConds: 3 },
2536 {.AsmStrOffset: 6947, .AliasCondStart: 2369, .NumOperands: 3, .NumConds: 3 },
2537 {.AsmStrOffset: 6954, .AliasCondStart: 2372, .NumOperands: 3, .NumConds: 3 },
2538 {.AsmStrOffset: 6966, .AliasCondStart: 2375, .NumOperands: 3, .NumConds: 3 },
2539 {.AsmStrOffset: 6974, .AliasCondStart: 2378, .NumOperands: 3, .NumConds: 3 },
2540 {.AsmStrOffset: 6987, .AliasCondStart: 2381, .NumOperands: 3, .NumConds: 3 },
2541 {.AsmStrOffset: 6994, .AliasCondStart: 2384, .NumOperands: 3, .NumConds: 3 },
2542 {.AsmStrOffset: 7006, .AliasCondStart: 2387, .NumOperands: 3, .NumConds: 3 },
2543 {.AsmStrOffset: 7013, .AliasCondStart: 2390, .NumOperands: 3, .NumConds: 3 },
2544 {.AsmStrOffset: 7025, .AliasCondStart: 2393, .NumOperands: 3, .NumConds: 3 },
2545 {.AsmStrOffset: 7033, .AliasCondStart: 2396, .NumOperands: 3, .NumConds: 3 },
2546 {.AsmStrOffset: 7046, .AliasCondStart: 2399, .NumOperands: 3, .NumConds: 3 },
2547 {.AsmStrOffset: 7054, .AliasCondStart: 2402, .NumOperands: 3, .NumConds: 3 },
2548 {.AsmStrOffset: 7067, .AliasCondStart: 2405, .NumOperands: 3, .NumConds: 3 },
2549 {.AsmStrOffset: 7074, .AliasCondStart: 2408, .NumOperands: 3, .NumConds: 3 },
2550 {.AsmStrOffset: 7086, .AliasCondStart: 2411, .NumOperands: 3, .NumConds: 3 },
2551 {.AsmStrOffset: 7093, .AliasCondStart: 2414, .NumOperands: 3, .NumConds: 3 },
2552 // SP::TRAPrr - 545
2553 {.AsmStrOffset: 6805, .AliasCondStart: 2417, .NumOperands: 3, .NumConds: 3 },
2554 {.AsmStrOffset: 6811, .AliasCondStart: 2420, .NumOperands: 3, .NumConds: 3 },
2555 {.AsmStrOffset: 6822, .AliasCondStart: 2423, .NumOperands: 3, .NumConds: 3 },
2556 {.AsmStrOffset: 6828, .AliasCondStart: 2426, .NumOperands: 3, .NumConds: 3 },
2557 {.AsmStrOffset: 6839, .AliasCondStart: 2429, .NumOperands: 3, .NumConds: 3 },
2558 {.AsmStrOffset: 6846, .AliasCondStart: 2432, .NumOperands: 3, .NumConds: 3 },
2559 {.AsmStrOffset: 6858, .AliasCondStart: 2435, .NumOperands: 3, .NumConds: 3 },
2560 {.AsmStrOffset: 6864, .AliasCondStart: 2438, .NumOperands: 3, .NumConds: 3 },
2561 {.AsmStrOffset: 6875, .AliasCondStart: 2441, .NumOperands: 3, .NumConds: 3 },
2562 {.AsmStrOffset: 6881, .AliasCondStart: 2444, .NumOperands: 3, .NumConds: 3 },
2563 {.AsmStrOffset: 6892, .AliasCondStart: 2447, .NumOperands: 3, .NumConds: 3 },
2564 {.AsmStrOffset: 6899, .AliasCondStart: 2450, .NumOperands: 3, .NumConds: 3 },
2565 {.AsmStrOffset: 6911, .AliasCondStart: 2453, .NumOperands: 3, .NumConds: 3 },
2566 {.AsmStrOffset: 6918, .AliasCondStart: 2456, .NumOperands: 3, .NumConds: 3 },
2567 {.AsmStrOffset: 6930, .AliasCondStart: 2459, .NumOperands: 3, .NumConds: 3 },
2568 {.AsmStrOffset: 6936, .AliasCondStart: 2462, .NumOperands: 3, .NumConds: 3 },
2569 {.AsmStrOffset: 6947, .AliasCondStart: 2465, .NumOperands: 3, .NumConds: 3 },
2570 {.AsmStrOffset: 6954, .AliasCondStart: 2468, .NumOperands: 3, .NumConds: 3 },
2571 {.AsmStrOffset: 6966, .AliasCondStart: 2471, .NumOperands: 3, .NumConds: 3 },
2572 {.AsmStrOffset: 6974, .AliasCondStart: 2474, .NumOperands: 3, .NumConds: 3 },
2573 {.AsmStrOffset: 6987, .AliasCondStart: 2477, .NumOperands: 3, .NumConds: 3 },
2574 {.AsmStrOffset: 6994, .AliasCondStart: 2480, .NumOperands: 3, .NumConds: 3 },
2575 {.AsmStrOffset: 7006, .AliasCondStart: 2483, .NumOperands: 3, .NumConds: 3 },
2576 {.AsmStrOffset: 7013, .AliasCondStart: 2486, .NumOperands: 3, .NumConds: 3 },
2577 {.AsmStrOffset: 7025, .AliasCondStart: 2489, .NumOperands: 3, .NumConds: 3 },
2578 {.AsmStrOffset: 7033, .AliasCondStart: 2492, .NumOperands: 3, .NumConds: 3 },
2579 {.AsmStrOffset: 7046, .AliasCondStart: 2495, .NumOperands: 3, .NumConds: 3 },
2580 {.AsmStrOffset: 7054, .AliasCondStart: 2498, .NumOperands: 3, .NumConds: 3 },
2581 {.AsmStrOffset: 7067, .AliasCondStart: 2501, .NumOperands: 3, .NumConds: 3 },
2582 {.AsmStrOffset: 7074, .AliasCondStart: 2504, .NumOperands: 3, .NumConds: 3 },
2583 {.AsmStrOffset: 7086, .AliasCondStart: 2507, .NumOperands: 3, .NumConds: 3 },
2584 {.AsmStrOffset: 7093, .AliasCondStart: 2510, .NumOperands: 3, .NumConds: 3 },
2585 // SP::TXCCri - 577
2586 {.AsmStrOffset: 7105, .AliasCondStart: 2513, .NumOperands: 3, .NumConds: 4 },
2587 {.AsmStrOffset: 5833, .AliasCondStart: 2517, .NumOperands: 3, .NumConds: 5 },
2588 {.AsmStrOffset: 7117, .AliasCondStart: 2522, .NumOperands: 3, .NumConds: 4 },
2589 {.AsmStrOffset: 5862, .AliasCondStart: 2526, .NumOperands: 3, .NumConds: 5 },
2590 {.AsmStrOffset: 7134, .AliasCondStart: 2531, .NumOperands: 3, .NumConds: 4 },
2591 {.AsmStrOffset: 5891, .AliasCondStart: 2535, .NumOperands: 3, .NumConds: 5 },
2592 {.AsmStrOffset: 7146, .AliasCondStart: 2540, .NumOperands: 3, .NumConds: 4 },
2593 {.AsmStrOffset: 5920, .AliasCondStart: 2544, .NumOperands: 3, .NumConds: 5 },
2594 {.AsmStrOffset: 7163, .AliasCondStart: 2549, .NumOperands: 3, .NumConds: 4 },
2595 {.AsmStrOffset: 5950, .AliasCondStart: 2553, .NumOperands: 3, .NumConds: 5 },
2596 {.AsmStrOffset: 7176, .AliasCondStart: 2558, .NumOperands: 3, .NumConds: 4 },
2597 {.AsmStrOffset: 5981, .AliasCondStart: 2562, .NumOperands: 3, .NumConds: 5 },
2598 {.AsmStrOffset: 7194, .AliasCondStart: 2567, .NumOperands: 3, .NumConds: 4 },
2599 {.AsmStrOffset: 6011, .AliasCondStart: 2571, .NumOperands: 3, .NumConds: 5 },
2600 {.AsmStrOffset: 7206, .AliasCondStart: 2576, .NumOperands: 3, .NumConds: 4 },
2601 {.AsmStrOffset: 6040, .AliasCondStart: 2580, .NumOperands: 3, .NumConds: 5 },
2602 {.AsmStrOffset: 7223, .AliasCondStart: 2585, .NumOperands: 3, .NumConds: 4 },
2603 {.AsmStrOffset: 6069, .AliasCondStart: 2589, .NumOperands: 3, .NumConds: 5 },
2604 {.AsmStrOffset: 7235, .AliasCondStart: 2594, .NumOperands: 3, .NumConds: 4 },
2605 {.AsmStrOffset: 6098, .AliasCondStart: 2598, .NumOperands: 3, .NumConds: 5 },
2606 {.AsmStrOffset: 7252, .AliasCondStart: 2603, .NumOperands: 3, .NumConds: 4 },
2607 {.AsmStrOffset: 6128, .AliasCondStart: 2607, .NumOperands: 3, .NumConds: 5 },
2608 {.AsmStrOffset: 7265, .AliasCondStart: 2612, .NumOperands: 3, .NumConds: 4 },
2609 {.AsmStrOffset: 6159, .AliasCondStart: 2616, .NumOperands: 3, .NumConds: 5 },
2610 {.AsmStrOffset: 7283, .AliasCondStart: 2621, .NumOperands: 3, .NumConds: 4 },
2611 {.AsmStrOffset: 6190, .AliasCondStart: 2625, .NumOperands: 3, .NumConds: 5 },
2612 {.AsmStrOffset: 7296, .AliasCondStart: 2630, .NumOperands: 3, .NumConds: 4 },
2613 {.AsmStrOffset: 6221, .AliasCondStart: 2634, .NumOperands: 3, .NumConds: 5 },
2614 {.AsmStrOffset: 7314, .AliasCondStart: 2639, .NumOperands: 3, .NumConds: 4 },
2615 {.AsmStrOffset: 6251, .AliasCondStart: 2643, .NumOperands: 3, .NumConds: 5 },
2616 {.AsmStrOffset: 7326, .AliasCondStart: 2648, .NumOperands: 3, .NumConds: 4 },
2617 {.AsmStrOffset: 6280, .AliasCondStart: 2652, .NumOperands: 3, .NumConds: 5 },
2618 {.AsmStrOffset: 7343, .AliasCondStart: 2657, .NumOperands: 3, .NumConds: 4 },
2619 {.AsmStrOffset: 6310, .AliasCondStart: 2661, .NumOperands: 3, .NumConds: 5 },
2620 {.AsmStrOffset: 7356, .AliasCondStart: 2666, .NumOperands: 3, .NumConds: 4 },
2621 {.AsmStrOffset: 6341, .AliasCondStart: 2670, .NumOperands: 3, .NumConds: 5 },
2622 {.AsmStrOffset: 7374, .AliasCondStart: 2675, .NumOperands: 3, .NumConds: 4 },
2623 {.AsmStrOffset: 6373, .AliasCondStart: 2679, .NumOperands: 3, .NumConds: 5 },
2624 {.AsmStrOffset: 7388, .AliasCondStart: 2684, .NumOperands: 3, .NumConds: 4 },
2625 {.AsmStrOffset: 6406, .AliasCondStart: 2688, .NumOperands: 3, .NumConds: 5 },
2626 {.AsmStrOffset: 7407, .AliasCondStart: 2693, .NumOperands: 3, .NumConds: 4 },
2627 {.AsmStrOffset: 6438, .AliasCondStart: 2697, .NumOperands: 3, .NumConds: 5 },
2628 {.AsmStrOffset: 7420, .AliasCondStart: 2702, .NumOperands: 3, .NumConds: 4 },
2629 {.AsmStrOffset: 6469, .AliasCondStart: 2706, .NumOperands: 3, .NumConds: 5 },
2630 {.AsmStrOffset: 7438, .AliasCondStart: 2711, .NumOperands: 3, .NumConds: 4 },
2631 {.AsmStrOffset: 6500, .AliasCondStart: 2715, .NumOperands: 3, .NumConds: 5 },
2632 {.AsmStrOffset: 7451, .AliasCondStart: 2720, .NumOperands: 3, .NumConds: 4 },
2633 {.AsmStrOffset: 6531, .AliasCondStart: 2724, .NumOperands: 3, .NumConds: 5 },
2634 {.AsmStrOffset: 7469, .AliasCondStart: 2729, .NumOperands: 3, .NumConds: 4 },
2635 {.AsmStrOffset: 6563, .AliasCondStart: 2733, .NumOperands: 3, .NumConds: 5 },
2636 {.AsmStrOffset: 7483, .AliasCondStart: 2738, .NumOperands: 3, .NumConds: 4 },
2637 {.AsmStrOffset: 6596, .AliasCondStart: 2742, .NumOperands: 3, .NumConds: 5 },
2638 {.AsmStrOffset: 7502, .AliasCondStart: 2747, .NumOperands: 3, .NumConds: 4 },
2639 {.AsmStrOffset: 6629, .AliasCondStart: 2751, .NumOperands: 3, .NumConds: 5 },
2640 {.AsmStrOffset: 7516, .AliasCondStart: 2756, .NumOperands: 3, .NumConds: 4 },
2641 {.AsmStrOffset: 6662, .AliasCondStart: 2760, .NumOperands: 3, .NumConds: 5 },
2642 {.AsmStrOffset: 7535, .AliasCondStart: 2765, .NumOperands: 3, .NumConds: 4 },
2643 {.AsmStrOffset: 6694, .AliasCondStart: 2769, .NumOperands: 3, .NumConds: 5 },
2644 {.AsmStrOffset: 7548, .AliasCondStart: 2774, .NumOperands: 3, .NumConds: 4 },
2645 {.AsmStrOffset: 6725, .AliasCondStart: 2778, .NumOperands: 3, .NumConds: 5 },
2646 {.AsmStrOffset: 7566, .AliasCondStart: 2783, .NumOperands: 3, .NumConds: 4 },
2647 {.AsmStrOffset: 6756, .AliasCondStart: 2787, .NumOperands: 3, .NumConds: 5 },
2648 {.AsmStrOffset: 7579, .AliasCondStart: 2792, .NumOperands: 3, .NumConds: 4 },
2649 {.AsmStrOffset: 6787, .AliasCondStart: 2796, .NumOperands: 3, .NumConds: 5 },
2650 // SP::TXCCrr - 641
2651 {.AsmStrOffset: 7105, .AliasCondStart: 2801, .NumOperands: 3, .NumConds: 4 },
2652 {.AsmStrOffset: 5833, .AliasCondStart: 2805, .NumOperands: 3, .NumConds: 5 },
2653 {.AsmStrOffset: 7117, .AliasCondStart: 2810, .NumOperands: 3, .NumConds: 4 },
2654 {.AsmStrOffset: 5862, .AliasCondStart: 2814, .NumOperands: 3, .NumConds: 5 },
2655 {.AsmStrOffset: 7134, .AliasCondStart: 2819, .NumOperands: 3, .NumConds: 4 },
2656 {.AsmStrOffset: 5891, .AliasCondStart: 2823, .NumOperands: 3, .NumConds: 5 },
2657 {.AsmStrOffset: 7146, .AliasCondStart: 2828, .NumOperands: 3, .NumConds: 4 },
2658 {.AsmStrOffset: 5920, .AliasCondStart: 2832, .NumOperands: 3, .NumConds: 5 },
2659 {.AsmStrOffset: 7163, .AliasCondStart: 2837, .NumOperands: 3, .NumConds: 4 },
2660 {.AsmStrOffset: 5950, .AliasCondStart: 2841, .NumOperands: 3, .NumConds: 5 },
2661 {.AsmStrOffset: 7176, .AliasCondStart: 2846, .NumOperands: 3, .NumConds: 4 },
2662 {.AsmStrOffset: 5981, .AliasCondStart: 2850, .NumOperands: 3, .NumConds: 5 },
2663 {.AsmStrOffset: 7194, .AliasCondStart: 2855, .NumOperands: 3, .NumConds: 4 },
2664 {.AsmStrOffset: 6011, .AliasCondStart: 2859, .NumOperands: 3, .NumConds: 5 },
2665 {.AsmStrOffset: 7206, .AliasCondStart: 2864, .NumOperands: 3, .NumConds: 4 },
2666 {.AsmStrOffset: 6040, .AliasCondStart: 2868, .NumOperands: 3, .NumConds: 5 },
2667 {.AsmStrOffset: 7223, .AliasCondStart: 2873, .NumOperands: 3, .NumConds: 4 },
2668 {.AsmStrOffset: 6069, .AliasCondStart: 2877, .NumOperands: 3, .NumConds: 5 },
2669 {.AsmStrOffset: 7235, .AliasCondStart: 2882, .NumOperands: 3, .NumConds: 4 },
2670 {.AsmStrOffset: 6098, .AliasCondStart: 2886, .NumOperands: 3, .NumConds: 5 },
2671 {.AsmStrOffset: 7252, .AliasCondStart: 2891, .NumOperands: 3, .NumConds: 4 },
2672 {.AsmStrOffset: 6128, .AliasCondStart: 2895, .NumOperands: 3, .NumConds: 5 },
2673 {.AsmStrOffset: 7265, .AliasCondStart: 2900, .NumOperands: 3, .NumConds: 4 },
2674 {.AsmStrOffset: 6159, .AliasCondStart: 2904, .NumOperands: 3, .NumConds: 5 },
2675 {.AsmStrOffset: 7283, .AliasCondStart: 2909, .NumOperands: 3, .NumConds: 4 },
2676 {.AsmStrOffset: 6190, .AliasCondStart: 2913, .NumOperands: 3, .NumConds: 5 },
2677 {.AsmStrOffset: 7296, .AliasCondStart: 2918, .NumOperands: 3, .NumConds: 4 },
2678 {.AsmStrOffset: 6221, .AliasCondStart: 2922, .NumOperands: 3, .NumConds: 5 },
2679 {.AsmStrOffset: 7314, .AliasCondStart: 2927, .NumOperands: 3, .NumConds: 4 },
2680 {.AsmStrOffset: 6251, .AliasCondStart: 2931, .NumOperands: 3, .NumConds: 5 },
2681 {.AsmStrOffset: 7326, .AliasCondStart: 2936, .NumOperands: 3, .NumConds: 4 },
2682 {.AsmStrOffset: 6280, .AliasCondStart: 2940, .NumOperands: 3, .NumConds: 5 },
2683 {.AsmStrOffset: 7343, .AliasCondStart: 2945, .NumOperands: 3, .NumConds: 4 },
2684 {.AsmStrOffset: 6310, .AliasCondStart: 2949, .NumOperands: 3, .NumConds: 5 },
2685 {.AsmStrOffset: 7356, .AliasCondStart: 2954, .NumOperands: 3, .NumConds: 4 },
2686 {.AsmStrOffset: 6341, .AliasCondStart: 2958, .NumOperands: 3, .NumConds: 5 },
2687 {.AsmStrOffset: 7374, .AliasCondStart: 2963, .NumOperands: 3, .NumConds: 4 },
2688 {.AsmStrOffset: 6373, .AliasCondStart: 2967, .NumOperands: 3, .NumConds: 5 },
2689 {.AsmStrOffset: 7388, .AliasCondStart: 2972, .NumOperands: 3, .NumConds: 4 },
2690 {.AsmStrOffset: 6406, .AliasCondStart: 2976, .NumOperands: 3, .NumConds: 5 },
2691 {.AsmStrOffset: 7407, .AliasCondStart: 2981, .NumOperands: 3, .NumConds: 4 },
2692 {.AsmStrOffset: 6438, .AliasCondStart: 2985, .NumOperands: 3, .NumConds: 5 },
2693 {.AsmStrOffset: 7420, .AliasCondStart: 2990, .NumOperands: 3, .NumConds: 4 },
2694 {.AsmStrOffset: 6469, .AliasCondStart: 2994, .NumOperands: 3, .NumConds: 5 },
2695 {.AsmStrOffset: 7438, .AliasCondStart: 2999, .NumOperands: 3, .NumConds: 4 },
2696 {.AsmStrOffset: 6500, .AliasCondStart: 3003, .NumOperands: 3, .NumConds: 5 },
2697 {.AsmStrOffset: 7451, .AliasCondStart: 3008, .NumOperands: 3, .NumConds: 4 },
2698 {.AsmStrOffset: 6531, .AliasCondStart: 3012, .NumOperands: 3, .NumConds: 5 },
2699 {.AsmStrOffset: 7469, .AliasCondStart: 3017, .NumOperands: 3, .NumConds: 4 },
2700 {.AsmStrOffset: 6563, .AliasCondStart: 3021, .NumOperands: 3, .NumConds: 5 },
2701 {.AsmStrOffset: 7483, .AliasCondStart: 3026, .NumOperands: 3, .NumConds: 4 },
2702 {.AsmStrOffset: 6596, .AliasCondStart: 3030, .NumOperands: 3, .NumConds: 5 },
2703 {.AsmStrOffset: 7502, .AliasCondStart: 3035, .NumOperands: 3, .NumConds: 4 },
2704 {.AsmStrOffset: 6629, .AliasCondStart: 3039, .NumOperands: 3, .NumConds: 5 },
2705 {.AsmStrOffset: 7516, .AliasCondStart: 3044, .NumOperands: 3, .NumConds: 4 },
2706 {.AsmStrOffset: 6662, .AliasCondStart: 3048, .NumOperands: 3, .NumConds: 5 },
2707 {.AsmStrOffset: 7535, .AliasCondStart: 3053, .NumOperands: 3, .NumConds: 4 },
2708 {.AsmStrOffset: 6694, .AliasCondStart: 3057, .NumOperands: 3, .NumConds: 5 },
2709 {.AsmStrOffset: 7548, .AliasCondStart: 3062, .NumOperands: 3, .NumConds: 4 },
2710 {.AsmStrOffset: 6725, .AliasCondStart: 3066, .NumOperands: 3, .NumConds: 5 },
2711 {.AsmStrOffset: 7566, .AliasCondStart: 3071, .NumOperands: 3, .NumConds: 4 },
2712 {.AsmStrOffset: 6756, .AliasCondStart: 3075, .NumOperands: 3, .NumConds: 5 },
2713 {.AsmStrOffset: 7579, .AliasCondStart: 3080, .NumOperands: 3, .NumConds: 4 },
2714 {.AsmStrOffset: 6787, .AliasCondStart: 3084, .NumOperands: 3, .NumConds: 5 },
2715 // SP::V9FCMPD - 705
2716 {.AsmStrOffset: 7597, .AliasCondStart: 3089, .NumOperands: 3, .NumConds: 3 },
2717 // SP::V9FCMPED - 706
2718 {.AsmStrOffset: 7610, .AliasCondStart: 3092, .NumOperands: 3, .NumConds: 3 },
2719 // SP::V9FCMPEQ - 707
2720 {.AsmStrOffset: 7624, .AliasCondStart: 3095, .NumOperands: 3, .NumConds: 3 },
2721 // SP::V9FCMPES - 708
2722 {.AsmStrOffset: 7638, .AliasCondStart: 3098, .NumOperands: 3, .NumConds: 3 },
2723 // SP::V9FCMPQ - 709
2724 {.AsmStrOffset: 7652, .AliasCondStart: 3101, .NumOperands: 3, .NumConds: 3 },
2725 // SP::V9FCMPS - 710
2726 {.AsmStrOffset: 7665, .AliasCondStart: 3104, .NumOperands: 3, .NumConds: 3 },
2727 // SP::V9FMOVD_FCC - 711
2728 {.AsmStrOffset: 7678, .AliasCondStart: 3107, .NumOperands: 5, .NumConds: 6 },
2729 {.AsmStrOffset: 7696, .AliasCondStart: 3113, .NumOperands: 5, .NumConds: 6 },
2730 {.AsmStrOffset: 7714, .AliasCondStart: 3119, .NumOperands: 5, .NumConds: 6 },
2731 {.AsmStrOffset: 7732, .AliasCondStart: 3125, .NumOperands: 5, .NumConds: 6 },
2732 {.AsmStrOffset: 7750, .AliasCondStart: 3131, .NumOperands: 5, .NumConds: 6 },
2733 {.AsmStrOffset: 7769, .AliasCondStart: 3137, .NumOperands: 5, .NumConds: 6 },
2734 {.AsmStrOffset: 7787, .AliasCondStart: 3143, .NumOperands: 5, .NumConds: 6 },
2735 {.AsmStrOffset: 7806, .AliasCondStart: 3149, .NumOperands: 5, .NumConds: 6 },
2736 {.AsmStrOffset: 7825, .AliasCondStart: 3155, .NumOperands: 5, .NumConds: 6 },
2737 {.AsmStrOffset: 7844, .AliasCondStart: 3161, .NumOperands: 5, .NumConds: 6 },
2738 {.AsmStrOffset: 7862, .AliasCondStart: 3167, .NumOperands: 5, .NumConds: 6 },
2739 {.AsmStrOffset: 7881, .AliasCondStart: 3173, .NumOperands: 5, .NumConds: 6 },
2740 {.AsmStrOffset: 7900, .AliasCondStart: 3179, .NumOperands: 5, .NumConds: 6 },
2741 {.AsmStrOffset: 7920, .AliasCondStart: 3185, .NumOperands: 5, .NumConds: 6 },
2742 {.AsmStrOffset: 7939, .AliasCondStart: 3191, .NumOperands: 5, .NumConds: 6 },
2743 {.AsmStrOffset: 7959, .AliasCondStart: 3197, .NumOperands: 5, .NumConds: 6 },
2744 // SP::V9FMOVQ_FCC - 727
2745 {.AsmStrOffset: 7977, .AliasCondStart: 3203, .NumOperands: 5, .NumConds: 6 },
2746 {.AsmStrOffset: 7995, .AliasCondStart: 3209, .NumOperands: 5, .NumConds: 6 },
2747 {.AsmStrOffset: 8013, .AliasCondStart: 3215, .NumOperands: 5, .NumConds: 6 },
2748 {.AsmStrOffset: 8031, .AliasCondStart: 3221, .NumOperands: 5, .NumConds: 6 },
2749 {.AsmStrOffset: 8049, .AliasCondStart: 3227, .NumOperands: 5, .NumConds: 6 },
2750 {.AsmStrOffset: 8068, .AliasCondStart: 3233, .NumOperands: 5, .NumConds: 6 },
2751 {.AsmStrOffset: 8086, .AliasCondStart: 3239, .NumOperands: 5, .NumConds: 6 },
2752 {.AsmStrOffset: 8105, .AliasCondStart: 3245, .NumOperands: 5, .NumConds: 6 },
2753 {.AsmStrOffset: 8124, .AliasCondStart: 3251, .NumOperands: 5, .NumConds: 6 },
2754 {.AsmStrOffset: 8143, .AliasCondStart: 3257, .NumOperands: 5, .NumConds: 6 },
2755 {.AsmStrOffset: 8161, .AliasCondStart: 3263, .NumOperands: 5, .NumConds: 6 },
2756 {.AsmStrOffset: 8180, .AliasCondStart: 3269, .NumOperands: 5, .NumConds: 6 },
2757 {.AsmStrOffset: 8199, .AliasCondStart: 3275, .NumOperands: 5, .NumConds: 6 },
2758 {.AsmStrOffset: 8219, .AliasCondStart: 3281, .NumOperands: 5, .NumConds: 6 },
2759 {.AsmStrOffset: 8238, .AliasCondStart: 3287, .NumOperands: 5, .NumConds: 6 },
2760 {.AsmStrOffset: 8258, .AliasCondStart: 3293, .NumOperands: 5, .NumConds: 6 },
2761 // SP::V9FMOVS_FCC - 743
2762 {.AsmStrOffset: 8276, .AliasCondStart: 3299, .NumOperands: 5, .NumConds: 6 },
2763 {.AsmStrOffset: 8294, .AliasCondStart: 3305, .NumOperands: 5, .NumConds: 6 },
2764 {.AsmStrOffset: 8312, .AliasCondStart: 3311, .NumOperands: 5, .NumConds: 6 },
2765 {.AsmStrOffset: 8330, .AliasCondStart: 3317, .NumOperands: 5, .NumConds: 6 },
2766 {.AsmStrOffset: 8348, .AliasCondStart: 3323, .NumOperands: 5, .NumConds: 6 },
2767 {.AsmStrOffset: 8367, .AliasCondStart: 3329, .NumOperands: 5, .NumConds: 6 },
2768 {.AsmStrOffset: 8385, .AliasCondStart: 3335, .NumOperands: 5, .NumConds: 6 },
2769 {.AsmStrOffset: 8404, .AliasCondStart: 3341, .NumOperands: 5, .NumConds: 6 },
2770 {.AsmStrOffset: 8423, .AliasCondStart: 3347, .NumOperands: 5, .NumConds: 6 },
2771 {.AsmStrOffset: 8442, .AliasCondStart: 3353, .NumOperands: 5, .NumConds: 6 },
2772 {.AsmStrOffset: 8460, .AliasCondStart: 3359, .NumOperands: 5, .NumConds: 6 },
2773 {.AsmStrOffset: 8479, .AliasCondStart: 3365, .NumOperands: 5, .NumConds: 6 },
2774 {.AsmStrOffset: 8498, .AliasCondStart: 3371, .NumOperands: 5, .NumConds: 6 },
2775 {.AsmStrOffset: 8518, .AliasCondStart: 3377, .NumOperands: 5, .NumConds: 6 },
2776 {.AsmStrOffset: 8537, .AliasCondStart: 3383, .NumOperands: 5, .NumConds: 6 },
2777 {.AsmStrOffset: 8557, .AliasCondStart: 3389, .NumOperands: 5, .NumConds: 6 },
2778 // SP::V9MOVFCCri - 759
2779 {.AsmStrOffset: 8575, .AliasCondStart: 3395, .NumOperands: 5, .NumConds: 6 },
2780 {.AsmStrOffset: 8591, .AliasCondStart: 3401, .NumOperands: 5, .NumConds: 6 },
2781 {.AsmStrOffset: 8607, .AliasCondStart: 3407, .NumOperands: 5, .NumConds: 6 },
2782 {.AsmStrOffset: 8623, .AliasCondStart: 3413, .NumOperands: 5, .NumConds: 6 },
2783 {.AsmStrOffset: 8639, .AliasCondStart: 3419, .NumOperands: 5, .NumConds: 6 },
2784 {.AsmStrOffset: 8656, .AliasCondStart: 3425, .NumOperands: 5, .NumConds: 6 },
2785 {.AsmStrOffset: 8672, .AliasCondStart: 3431, .NumOperands: 5, .NumConds: 6 },
2786 {.AsmStrOffset: 8689, .AliasCondStart: 3437, .NumOperands: 5, .NumConds: 6 },
2787 {.AsmStrOffset: 8706, .AliasCondStart: 3443, .NumOperands: 5, .NumConds: 6 },
2788 {.AsmStrOffset: 8723, .AliasCondStart: 3449, .NumOperands: 5, .NumConds: 6 },
2789 {.AsmStrOffset: 8739, .AliasCondStart: 3455, .NumOperands: 5, .NumConds: 6 },
2790 {.AsmStrOffset: 8756, .AliasCondStart: 3461, .NumOperands: 5, .NumConds: 6 },
2791 {.AsmStrOffset: 8773, .AliasCondStart: 3467, .NumOperands: 5, .NumConds: 6 },
2792 {.AsmStrOffset: 8791, .AliasCondStart: 3473, .NumOperands: 5, .NumConds: 6 },
2793 {.AsmStrOffset: 8808, .AliasCondStart: 3479, .NumOperands: 5, .NumConds: 6 },
2794 {.AsmStrOffset: 8826, .AliasCondStart: 3485, .NumOperands: 5, .NumConds: 6 },
2795 // SP::V9MOVFCCrr - 775
2796 {.AsmStrOffset: 8575, .AliasCondStart: 3491, .NumOperands: 5, .NumConds: 6 },
2797 {.AsmStrOffset: 8591, .AliasCondStart: 3497, .NumOperands: 5, .NumConds: 6 },
2798 {.AsmStrOffset: 8607, .AliasCondStart: 3503, .NumOperands: 5, .NumConds: 6 },
2799 {.AsmStrOffset: 8623, .AliasCondStart: 3509, .NumOperands: 5, .NumConds: 6 },
2800 {.AsmStrOffset: 8639, .AliasCondStart: 3515, .NumOperands: 5, .NumConds: 6 },
2801 {.AsmStrOffset: 8656, .AliasCondStart: 3521, .NumOperands: 5, .NumConds: 6 },
2802 {.AsmStrOffset: 8672, .AliasCondStart: 3527, .NumOperands: 5, .NumConds: 6 },
2803 {.AsmStrOffset: 8689, .AliasCondStart: 3533, .NumOperands: 5, .NumConds: 6 },
2804 {.AsmStrOffset: 8706, .AliasCondStart: 3539, .NumOperands: 5, .NumConds: 6 },
2805 {.AsmStrOffset: 8723, .AliasCondStart: 3545, .NumOperands: 5, .NumConds: 6 },
2806 {.AsmStrOffset: 8739, .AliasCondStart: 3551, .NumOperands: 5, .NumConds: 6 },
2807 {.AsmStrOffset: 8756, .AliasCondStart: 3557, .NumOperands: 5, .NumConds: 6 },
2808 {.AsmStrOffset: 8773, .AliasCondStart: 3563, .NumOperands: 5, .NumConds: 6 },
2809 {.AsmStrOffset: 8791, .AliasCondStart: 3569, .NumOperands: 5, .NumConds: 6 },
2810 {.AsmStrOffset: 8808, .AliasCondStart: 3575, .NumOperands: 5, .NumConds: 6 },
2811 {.AsmStrOffset: 8826, .AliasCondStart: 3581, .NumOperands: 5, .NumConds: 6 },
2812 // SP::WRASRri - 791
2813 {.AsmStrOffset: 8842, .AliasCondStart: 3587, .NumOperands: 3, .NumConds: 3 },
2814 // SP::WRASRrr - 792
2815 {.AsmStrOffset: 8842, .AliasCondStart: 3590, .NumOperands: 3, .NumConds: 4 },
2816 };
2817
2818 static const AliasPatternCond Conds[] = {
2819 // (BCOND brtarget:$imm, 8) - 0
2820 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2821 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2822 // (BCOND brtarget:$imm, 0) - 2
2823 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2824 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2825 // (BCOND brtarget:$imm, 9) - 4
2826 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2827 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2828 // (BCOND brtarget:$imm, 1) - 6
2829 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2830 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2831 // (BCOND brtarget:$imm, 10) - 8
2832 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2833 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2834 // (BCOND brtarget:$imm, 2) - 10
2835 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2836 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2837 // (BCOND brtarget:$imm, 11) - 12
2838 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2839 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2840 // (BCOND brtarget:$imm, 3) - 14
2841 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2842 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2843 // (BCOND brtarget:$imm, 12) - 16
2844 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2845 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2846 // (BCOND brtarget:$imm, 4) - 18
2847 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2848 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2849 // (BCOND brtarget:$imm, 13) - 20
2850 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2851 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2852 // (BCOND brtarget:$imm, 5) - 22
2853 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2854 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2855 // (BCOND brtarget:$imm, 14) - 24
2856 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2857 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2858 // (BCOND brtarget:$imm, 6) - 26
2859 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2860 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2861 // (BCOND brtarget:$imm, 15) - 28
2862 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2863 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2864 // (BCOND brtarget:$imm, 7) - 30
2865 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2866 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2867 // (BCONDA brtarget:$imm, 8) - 32
2868 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2869 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2870 // (BCONDA brtarget:$imm, 0) - 34
2871 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2872 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2873 // (BCONDA brtarget:$imm, 9) - 36
2874 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2875 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2876 // (BCONDA brtarget:$imm, 1) - 38
2877 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2878 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2879 // (BCONDA brtarget:$imm, 10) - 40
2880 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2881 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2882 // (BCONDA brtarget:$imm, 2) - 42
2883 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2884 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2885 // (BCONDA brtarget:$imm, 11) - 44
2886 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2887 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2888 // (BCONDA brtarget:$imm, 3) - 46
2889 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2890 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2891 // (BCONDA brtarget:$imm, 12) - 48
2892 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2893 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2894 // (BCONDA brtarget:$imm, 4) - 50
2895 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2896 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2897 // (BCONDA brtarget:$imm, 13) - 52
2898 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2899 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2900 // (BCONDA brtarget:$imm, 5) - 54
2901 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2902 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2903 // (BCONDA brtarget:$imm, 14) - 56
2904 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2905 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2906 // (BCONDA brtarget:$imm, 6) - 58
2907 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2908 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2909 // (BCONDA brtarget:$imm, 15) - 60
2910 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2911 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2912 // (BCONDA brtarget:$imm, 7) - 62
2913 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2914 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2915 // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc) - 64
2916 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2917 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2918 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2919 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2920 // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc) - 68
2921 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2922 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2923 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2924 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2925 // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc) - 72
2926 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2927 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2928 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2929 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2930 // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc) - 76
2931 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2932 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2933 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2934 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2935 // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc) - 80
2936 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2937 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2938 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2939 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2940 // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc) - 84
2941 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2942 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2943 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2944 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2945 // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc) - 88
2946 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2947 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2948 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2949 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2950 // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc) - 92
2951 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2952 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2953 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2954 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2955 // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc) - 96
2956 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2957 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2958 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2959 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2960 // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc) - 100
2961 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2962 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2963 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2964 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2965 // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc) - 104
2966 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2967 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2968 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2969 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2970 // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc) - 108
2971 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2972 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2973 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2974 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2975 // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc) - 112
2976 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2977 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2978 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2979 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2980 // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc) - 116
2981 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2982 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2983 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2984 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2985 // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc) - 120
2986 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2987 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2988 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2989 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2990 // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc) - 124
2991 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2992 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2993 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2994 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2995 // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc) - 128
2996 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2997 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2998 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2999 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3000 // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc) - 132
3001 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3002 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3003 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3004 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3005 // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc) - 136
3006 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3007 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3008 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3009 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3010 // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc) - 140
3011 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3012 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3013 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3014 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3015 // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc) - 144
3016 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3017 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3018 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3019 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3020 // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc) - 148
3021 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3022 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3023 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3024 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3025 // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc) - 152
3026 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3027 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3028 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3029 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3030 // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc) - 156
3031 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3032 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3033 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3034 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3035 // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc) - 160
3036 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3037 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3038 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3039 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3040 // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc) - 164
3041 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3042 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3043 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3044 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3045 // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc) - 168
3046 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3047 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3048 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3049 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3050 // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc) - 172
3051 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3052 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3053 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3054 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3055 // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc) - 176
3056 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3057 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3058 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3059 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3060 // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc) - 180
3061 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3062 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3063 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3064 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3065 // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc) - 184
3066 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3067 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3068 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3069 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3070 // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc) - 188
3071 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3072 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3073 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
3074 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3075 // (BPICCANT brtarget:$imm, 8) - 192
3076 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3077 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3078 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3079 // (BPICCANT brtarget:$imm, 8) - 195
3080 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3081 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3082 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3083 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3084 // (BPICCANT brtarget:$imm, 0) - 199
3085 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3086 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3087 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3088 // (BPICCANT brtarget:$imm, 0) - 202
3089 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3090 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3091 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3092 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3093 // (BPICCANT brtarget:$imm, 9) - 206
3094 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3095 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3096 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3097 // (BPICCANT brtarget:$imm, 9) - 209
3098 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3099 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3100 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3101 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3102 // (BPICCANT brtarget:$imm, 1) - 213
3103 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3104 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3105 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3106 // (BPICCANT brtarget:$imm, 1) - 216
3107 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3108 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3109 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3110 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3111 // (BPICCANT brtarget:$imm, 10) - 220
3112 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3113 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3114 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3115 // (BPICCANT brtarget:$imm, 10) - 223
3116 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3117 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3118 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3119 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3120 // (BPICCANT brtarget:$imm, 2) - 227
3121 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3122 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3123 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3124 // (BPICCANT brtarget:$imm, 2) - 230
3125 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3126 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3127 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3128 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3129 // (BPICCANT brtarget:$imm, 11) - 234
3130 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3131 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3132 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3133 // (BPICCANT brtarget:$imm, 11) - 237
3134 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3135 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3136 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3137 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3138 // (BPICCANT brtarget:$imm, 3) - 241
3139 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3140 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3141 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3142 // (BPICCANT brtarget:$imm, 3) - 244
3143 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3144 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3145 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3146 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3147 // (BPICCANT brtarget:$imm, 12) - 248
3148 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3149 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3150 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3151 // (BPICCANT brtarget:$imm, 12) - 251
3152 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3153 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3154 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3155 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3156 // (BPICCANT brtarget:$imm, 4) - 255
3157 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3158 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3159 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3160 // (BPICCANT brtarget:$imm, 4) - 258
3161 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3162 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3163 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3164 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3165 // (BPICCANT brtarget:$imm, 13) - 262
3166 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3167 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3168 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3169 // (BPICCANT brtarget:$imm, 13) - 265
3170 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3171 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3172 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3173 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3174 // (BPICCANT brtarget:$imm, 5) - 269
3175 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3176 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3177 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3178 // (BPICCANT brtarget:$imm, 5) - 272
3179 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3180 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3181 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3182 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3183 // (BPICCANT brtarget:$imm, 14) - 276
3184 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3185 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3186 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3187 // (BPICCANT brtarget:$imm, 14) - 279
3188 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3189 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3190 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3191 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3192 // (BPICCANT brtarget:$imm, 6) - 283
3193 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3194 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3195 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3196 // (BPICCANT brtarget:$imm, 6) - 286
3197 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3198 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3199 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3200 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3201 // (BPICCANT brtarget:$imm, 15) - 290
3202 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3203 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3204 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3205 // (BPICCANT brtarget:$imm, 15) - 293
3206 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3207 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3208 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3209 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3210 // (BPICCANT brtarget:$imm, 7) - 297
3211 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3212 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3213 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3214 // (BPICCANT brtarget:$imm, 7) - 300
3215 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3216 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3217 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3218 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3219 // (BPICCNT brtarget:$imm, 8) - 304
3220 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3221 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3222 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3223 // (BPICCNT brtarget:$imm, 8) - 307
3224 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3225 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3226 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3227 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3228 // (BPICCNT brtarget:$imm, 0) - 311
3229 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3230 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3231 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3232 // (BPICCNT brtarget:$imm, 0) - 314
3233 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3234 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3235 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3236 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3237 // (BPICCNT brtarget:$imm, 9) - 318
3238 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3239 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3240 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3241 // (BPICCNT brtarget:$imm, 9) - 321
3242 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3243 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3244 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3245 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3246 // (BPICCNT brtarget:$imm, 1) - 325
3247 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3248 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3249 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3250 // (BPICCNT brtarget:$imm, 1) - 328
3251 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3252 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3253 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3254 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3255 // (BPICCNT brtarget:$imm, 10) - 332
3256 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3257 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3258 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3259 // (BPICCNT brtarget:$imm, 10) - 335
3260 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3261 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3262 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3263 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3264 // (BPICCNT brtarget:$imm, 2) - 339
3265 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3266 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3267 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3268 // (BPICCNT brtarget:$imm, 2) - 342
3269 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3270 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3271 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3272 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3273 // (BPICCNT brtarget:$imm, 11) - 346
3274 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3275 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3276 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3277 // (BPICCNT brtarget:$imm, 11) - 349
3278 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3279 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3280 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3281 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3282 // (BPICCNT brtarget:$imm, 3) - 353
3283 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3284 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3285 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3286 // (BPICCNT brtarget:$imm, 3) - 356
3287 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3288 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3289 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3290 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3291 // (BPICCNT brtarget:$imm, 12) - 360
3292 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3293 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3294 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3295 // (BPICCNT brtarget:$imm, 12) - 363
3296 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3297 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3298 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3299 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3300 // (BPICCNT brtarget:$imm, 4) - 367
3301 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3302 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3303 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3304 // (BPICCNT brtarget:$imm, 4) - 370
3305 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3306 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3307 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3308 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3309 // (BPICCNT brtarget:$imm, 13) - 374
3310 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3311 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3312 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3313 // (BPICCNT brtarget:$imm, 13) - 377
3314 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3315 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3316 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3317 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3318 // (BPICCNT brtarget:$imm, 5) - 381
3319 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3320 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3321 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3322 // (BPICCNT brtarget:$imm, 5) - 384
3323 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3324 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3325 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3326 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3327 // (BPICCNT brtarget:$imm, 14) - 388
3328 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3329 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3330 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3331 // (BPICCNT brtarget:$imm, 14) - 391
3332 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3333 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3334 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3335 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3336 // (BPICCNT brtarget:$imm, 6) - 395
3337 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3338 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3339 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3340 // (BPICCNT brtarget:$imm, 6) - 398
3341 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3342 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3343 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3344 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3345 // (BPICCNT brtarget:$imm, 15) - 402
3346 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3347 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3348 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3349 // (BPICCNT brtarget:$imm, 15) - 405
3350 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3351 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3352 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3353 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3354 // (BPICCNT brtarget:$imm, 7) - 409
3355 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3356 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3357 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3358 // (BPICCNT brtarget:$imm, 7) - 412
3359 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3360 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3361 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3362 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3363 // (BPRANT bprtarget16:$imm, 2, I64Regs:$rs1) - 416
3364 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3365 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3366 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3367 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3368 // (BPRANT bprtarget16:$imm, 3, I64Regs:$rs1) - 420
3369 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3370 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3371 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3372 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3373 // (BPRANT bprtarget16:$imm, 6, I64Regs:$rs1) - 424
3374 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3375 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3376 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3377 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3378 // (BPRANT bprtarget16:$imm, 7, I64Regs:$rs1) - 428
3379 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3380 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3381 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3382 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3383 // (BPRNT bprtarget16:$imm, 2, I64Regs:$rs1) - 432
3384 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3385 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3386 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3387 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3388 // (BPRNT bprtarget16:$imm, 3, I64Regs:$rs1) - 436
3389 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3390 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3391 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3392 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3393 // (BPRNT bprtarget16:$imm, 6, I64Regs:$rs1) - 440
3394 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3395 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3396 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3397 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3398 // (BPRNT bprtarget16:$imm, 7, I64Regs:$rs1) - 444
3399 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3400 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3401 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3402 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
3403 // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 128) - 448
3404 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3405 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3406 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3407 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3408 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(128)},
3409 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3410 // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 136) - 454
3411 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3412 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3413 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3414 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3415 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(136)},
3416 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3417 // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 128) - 460
3418 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3419 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3420 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3421 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3422 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(128)},
3423 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3424 // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 136) - 466
3425 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3426 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3427 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3428 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3429 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(136)},
3430 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3431 // (CWBCONDri cbtarget:$imm, 9, IntRegs:$rs1, simm5Op:$simm5) - 472
3432 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3433 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3434 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3435 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3436 // (CWBCONDri cbtarget:$imm, 1, IntRegs:$rs1, simm5Op:$simm5) - 476
3437 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3438 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3439 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3440 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3441 // (CWBCONDri cbtarget:$imm, 10, IntRegs:$rs1, simm5Op:$simm5) - 480
3442 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3443 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3444 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3445 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3446 // (CWBCONDri cbtarget:$imm, 2, IntRegs:$rs1, simm5Op:$simm5) - 484
3447 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3448 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3449 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3450 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3451 // (CWBCONDri cbtarget:$imm, 11, IntRegs:$rs1, simm5Op:$simm5) - 488
3452 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3453 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3454 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3455 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3456 // (CWBCONDri cbtarget:$imm, 3, IntRegs:$rs1, simm5Op:$simm5) - 492
3457 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3458 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3459 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3460 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3461 // (CWBCONDri cbtarget:$imm, 12, IntRegs:$rs1, simm5Op:$simm5) - 496
3462 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3463 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3464 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3465 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3466 // (CWBCONDri cbtarget:$imm, 4, IntRegs:$rs1, simm5Op:$simm5) - 500
3467 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3468 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3469 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3470 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3471 // (CWBCONDri cbtarget:$imm, 13, IntRegs:$rs1, simm5Op:$simm5) - 504
3472 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3473 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3474 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3475 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3476 // (CWBCONDri cbtarget:$imm, 5, IntRegs:$rs1, simm5Op:$simm5) - 508
3477 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3478 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3479 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3480 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3481 // (CWBCONDri cbtarget:$imm, 14, IntRegs:$rs1, simm5Op:$simm5) - 512
3482 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3483 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3484 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3485 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3486 // (CWBCONDri cbtarget:$imm, 6, IntRegs:$rs1, simm5Op:$simm5) - 516
3487 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3488 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3489 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3490 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3491 // (CWBCONDri cbtarget:$imm, 15, IntRegs:$rs1, simm5Op:$simm5) - 520
3492 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3493 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3494 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3495 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3496 // (CWBCONDri cbtarget:$imm, 7, IntRegs:$rs1, simm5Op:$simm5) - 524
3497 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3498 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3499 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3500 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3501 // (CWBCONDrr cbtarget:$imm, 9, IntRegs:$rs1, IntRegs:$rs2) - 528
3502 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3503 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3504 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3505 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3506 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3507 // (CWBCONDrr cbtarget:$imm, 1, IntRegs:$rs1, IntRegs:$rs2) - 533
3508 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3509 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3510 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3511 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3512 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3513 // (CWBCONDrr cbtarget:$imm, 10, IntRegs:$rs1, IntRegs:$rs2) - 538
3514 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3515 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3516 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3517 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3518 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3519 // (CWBCONDrr cbtarget:$imm, 2, IntRegs:$rs1, IntRegs:$rs2) - 543
3520 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3521 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3522 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3523 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3524 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3525 // (CWBCONDrr cbtarget:$imm, 11, IntRegs:$rs1, IntRegs:$rs2) - 548
3526 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3527 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3528 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3529 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3530 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3531 // (CWBCONDrr cbtarget:$imm, 3, IntRegs:$rs1, IntRegs:$rs2) - 553
3532 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3533 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3534 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3535 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3536 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3537 // (CWBCONDrr cbtarget:$imm, 12, IntRegs:$rs1, IntRegs:$rs2) - 558
3538 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3539 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3540 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3541 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3542 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3543 // (CWBCONDrr cbtarget:$imm, 4, IntRegs:$rs1, IntRegs:$rs2) - 563
3544 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3545 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3546 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3547 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3548 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3549 // (CWBCONDrr cbtarget:$imm, 13, IntRegs:$rs1, IntRegs:$rs2) - 568
3550 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3551 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3552 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3553 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3554 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3555 // (CWBCONDrr cbtarget:$imm, 5, IntRegs:$rs1, IntRegs:$rs2) - 573
3556 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3557 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3558 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3559 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3560 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3561 // (CWBCONDrr cbtarget:$imm, 14, IntRegs:$rs1, IntRegs:$rs2) - 578
3562 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3563 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3564 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3565 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3566 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3567 // (CWBCONDrr cbtarget:$imm, 6, IntRegs:$rs1, IntRegs:$rs2) - 583
3568 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3569 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3570 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3571 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3572 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3573 // (CWBCONDrr cbtarget:$imm, 15, IntRegs:$rs1, IntRegs:$rs2) - 588
3574 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3575 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3576 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3577 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3578 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3579 // (CWBCONDrr cbtarget:$imm, 7, IntRegs:$rs1, IntRegs:$rs2) - 593
3580 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3581 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3582 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3583 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3584 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3585 // (CXBCONDri cbtarget:$imm, 9, IntRegs:$rs1, simm5Op:$simm5) - 598
3586 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3587 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3588 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3589 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3590 // (CXBCONDri cbtarget:$imm, 1, IntRegs:$rs1, simm5Op:$simm5) - 602
3591 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3592 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3593 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3594 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3595 // (CXBCONDri cbtarget:$imm, 10, IntRegs:$rs1, simm5Op:$simm5) - 606
3596 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3597 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3598 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3599 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3600 // (CXBCONDri cbtarget:$imm, 2, IntRegs:$rs1, simm5Op:$simm5) - 610
3601 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3602 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3603 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3604 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3605 // (CXBCONDri cbtarget:$imm, 11, IntRegs:$rs1, simm5Op:$simm5) - 614
3606 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3607 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3608 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3609 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3610 // (CXBCONDri cbtarget:$imm, 3, IntRegs:$rs1, simm5Op:$simm5) - 618
3611 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3612 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3613 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3614 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3615 // (CXBCONDri cbtarget:$imm, 12, IntRegs:$rs1, simm5Op:$simm5) - 622
3616 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3617 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3618 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3619 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3620 // (CXBCONDri cbtarget:$imm, 4, IntRegs:$rs1, simm5Op:$simm5) - 626
3621 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3622 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3623 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3624 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3625 // (CXBCONDri cbtarget:$imm, 13, IntRegs:$rs1, simm5Op:$simm5) - 630
3626 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3627 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3628 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3629 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3630 // (CXBCONDri cbtarget:$imm, 5, IntRegs:$rs1, simm5Op:$simm5) - 634
3631 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3632 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3633 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3634 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3635 // (CXBCONDri cbtarget:$imm, 14, IntRegs:$rs1, simm5Op:$simm5) - 638
3636 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3637 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3638 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3639 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3640 // (CXBCONDri cbtarget:$imm, 6, IntRegs:$rs1, simm5Op:$simm5) - 642
3641 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3642 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3643 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3644 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3645 // (CXBCONDri cbtarget:$imm, 15, IntRegs:$rs1, simm5Op:$simm5) - 646
3646 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3647 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3648 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3649 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3650 // (CXBCONDri cbtarget:$imm, 7, IntRegs:$rs1, simm5Op:$simm5) - 650
3651 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3652 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3653 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3654 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3655 // (CXBCONDrr cbtarget:$imm, 9, IntRegs:$rs1, IntRegs:$rs2) - 654
3656 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3657 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3658 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3659 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3660 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3661 // (CXBCONDrr cbtarget:$imm, 1, IntRegs:$rs1, IntRegs:$rs2) - 659
3662 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3663 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3664 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3665 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3666 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3667 // (CXBCONDrr cbtarget:$imm, 10, IntRegs:$rs1, IntRegs:$rs2) - 664
3668 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3669 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3670 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3671 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3672 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3673 // (CXBCONDrr cbtarget:$imm, 2, IntRegs:$rs1, IntRegs:$rs2) - 669
3674 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3675 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3676 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3677 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3678 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3679 // (CXBCONDrr cbtarget:$imm, 11, IntRegs:$rs1, IntRegs:$rs2) - 674
3680 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3681 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3682 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3683 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3684 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3685 // (CXBCONDrr cbtarget:$imm, 3, IntRegs:$rs1, IntRegs:$rs2) - 679
3686 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3687 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3688 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3689 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3690 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3691 // (CXBCONDrr cbtarget:$imm, 12, IntRegs:$rs1, IntRegs:$rs2) - 684
3692 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3693 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3694 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3695 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3696 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3697 // (CXBCONDrr cbtarget:$imm, 4, IntRegs:$rs1, IntRegs:$rs2) - 689
3698 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3699 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3700 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3701 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3702 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3703 // (CXBCONDrr cbtarget:$imm, 13, IntRegs:$rs1, IntRegs:$rs2) - 694
3704 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3705 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3706 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3707 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3708 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3709 // (CXBCONDrr cbtarget:$imm, 5, IntRegs:$rs1, IntRegs:$rs2) - 699
3710 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3711 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3712 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3713 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3714 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3715 // (CXBCONDrr cbtarget:$imm, 14, IntRegs:$rs1, IntRegs:$rs2) - 704
3716 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3717 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3718 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3719 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3720 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3721 // (CXBCONDrr cbtarget:$imm, 6, IntRegs:$rs1, IntRegs:$rs2) - 709
3722 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3723 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3724 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3725 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3726 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3727 // (CXBCONDrr cbtarget:$imm, 15, IntRegs:$rs1, IntRegs:$rs2) - 714
3728 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3729 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3730 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3731 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3732 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3733 // (CXBCONDrr cbtarget:$imm, 7, IntRegs:$rs1, IntRegs:$rs2) - 719
3734 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3735 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3736 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3737 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3738 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3739 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8) - 724
3740 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3741 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3742 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3743 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3744 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3745 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8) - 729
3746 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3747 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3748 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3749 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3750 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3751 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3752 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0) - 735
3753 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3754 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3755 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3756 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3757 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3758 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0) - 740
3759 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3760 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3761 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3762 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3763 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3764 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3765 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9) - 746
3766 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3767 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3768 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3769 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3770 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3771 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9) - 751
3772 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3773 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3774 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3775 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3776 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3777 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3778 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1) - 757
3779 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3780 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3781 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3782 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3783 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3784 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1) - 762
3785 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3786 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3787 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3788 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3789 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3790 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3791 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10) - 768
3792 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3793 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3794 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3795 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3796 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3797 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10) - 773
3798 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3799 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3800 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3801 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3802 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3803 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3804 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2) - 779
3805 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3806 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3807 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3808 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3809 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3810 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2) - 784
3811 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3812 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3813 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3814 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3815 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3816 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3817 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11) - 790
3818 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3819 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3820 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3821 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3822 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3823 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11) - 795
3824 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3825 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3826 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3827 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3828 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3829 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3830 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3) - 801
3831 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3832 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3833 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3834 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3835 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3836 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3) - 806
3837 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3838 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3839 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3840 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3841 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3842 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3843 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12) - 812
3844 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3845 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3846 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3847 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3848 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3849 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12) - 817
3850 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3851 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3852 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3853 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3854 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3855 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3856 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4) - 823
3857 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3858 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3859 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3860 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3861 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3862 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4) - 828
3863 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3864 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3865 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3866 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3867 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3868 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3869 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13) - 834
3870 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3871 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3872 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3873 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3874 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3875 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13) - 839
3876 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3877 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3878 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3879 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3880 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3881 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3882 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5) - 845
3883 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3884 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3885 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3886 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3887 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3888 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5) - 850
3889 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3890 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3891 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3892 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3893 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3894 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3895 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14) - 856
3896 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3897 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3898 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3899 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3900 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3901 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14) - 861
3902 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3903 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3904 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3905 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3906 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3907 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3908 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6) - 867
3909 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3910 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3911 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3912 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3913 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3914 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6) - 872
3915 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3916 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3917 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3918 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3919 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3920 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3921 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15) - 878
3922 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3923 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3924 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3925 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3926 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3927 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15) - 883
3928 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3929 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3930 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3931 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3932 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3933 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3934 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7) - 889
3935 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3936 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3937 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3938 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3939 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3940 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7) - 894
3941 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3942 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3943 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3944 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3945 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3946 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3947 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8) - 900
3948 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3949 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3950 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3951 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3952 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3953 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8) - 905
3954 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3955 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3956 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3957 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3958 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3959 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3960 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0) - 911
3961 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3962 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3963 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3964 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3965 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3966 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0) - 916
3967 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3968 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3969 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3970 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3971 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3972 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3973 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9) - 922
3974 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3975 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3976 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3977 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3978 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3979 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9) - 927
3980 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3981 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3982 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3983 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3984 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3985 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3986 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1) - 933
3987 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3988 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3989 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3990 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3991 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3992 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1) - 938
3993 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3994 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3995 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3996 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3997 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3998 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
3999 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10) - 944
4000 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4001 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4002 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4003 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4004 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4005 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10) - 949
4006 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4007 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4008 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4009 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4010 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4011 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4012 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2) - 955
4013 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4014 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4015 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4016 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4017 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4018 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2) - 960
4019 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4020 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4021 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4022 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4023 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4024 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4025 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11) - 966
4026 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4027 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4028 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4029 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4030 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4031 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11) - 971
4032 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4033 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4034 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4035 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4036 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4037 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4038 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3) - 977
4039 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4040 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4041 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4042 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4043 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4044 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3) - 982
4045 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4046 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4047 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4048 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4049 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4050 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4051 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12) - 988
4052 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4053 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4054 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4055 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4056 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4057 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12) - 993
4058 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4059 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4060 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4061 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4062 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4063 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4064 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4) - 999
4065 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4066 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4067 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4068 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4069 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4070 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4) - 1004
4071 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4072 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4073 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4074 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4075 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4076 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4077 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13) - 1010
4078 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4079 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4080 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4081 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4082 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4083 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13) - 1015
4084 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4085 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4086 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4087 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4088 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4089 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4090 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5) - 1021
4091 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4092 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4093 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4094 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4095 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4096 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5) - 1026
4097 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4098 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4099 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4100 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4101 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4102 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4103 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14) - 1032
4104 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4105 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4106 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4107 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4108 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4109 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14) - 1037
4110 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4111 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4112 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4113 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4114 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4115 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4116 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6) - 1043
4117 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4118 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4119 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4120 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4121 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4122 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6) - 1048
4123 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4124 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4125 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4126 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4127 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4128 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4129 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15) - 1054
4130 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4131 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4132 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4133 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4134 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4135 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15) - 1059
4136 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4137 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4138 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4139 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4140 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4141 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4142 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7) - 1065
4143 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4144 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4145 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4146 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4147 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4148 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7) - 1070
4149 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4150 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4151 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4152 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4153 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4154 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4155 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 2) - 1076
4156 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4157 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4158 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4159 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4160 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4161 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4162 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 3) - 1082
4163 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4164 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4165 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4166 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4167 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4168 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4169 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 6) - 1088
4170 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4171 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4172 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4173 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4174 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4175 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4176 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 7) - 1094
4177 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4178 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4179 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4180 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4181 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4182 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4183 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 2) - 1100
4184 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4185 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4186 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4187 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4188 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4189 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4190 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 3) - 1106
4191 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4192 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4193 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4194 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4195 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4196 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4197 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 6) - 1112
4198 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4199 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4200 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4201 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4202 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4203 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4204 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 7) - 1118
4205 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4206 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4207 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4208 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4209 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4210 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4211 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 2) - 1124
4212 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4213 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4214 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4215 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4216 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4217 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4218 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 3) - 1130
4219 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4220 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4221 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4222 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4223 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4224 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4225 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 6) - 1136
4226 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4227 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4228 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4229 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4230 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4231 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4232 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 7) - 1142
4233 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4234 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4235 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4236 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4237 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4238 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4239 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8) - 1148
4240 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4241 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4242 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4243 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4244 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4245 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8) - 1153
4246 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4247 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4248 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4249 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4250 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4251 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4252 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0) - 1159
4253 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4254 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4255 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4256 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4257 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4258 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0) - 1164
4259 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4260 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4261 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4262 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4263 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4264 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4265 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9) - 1170
4266 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4267 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4268 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4269 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4270 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4271 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9) - 1175
4272 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4273 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4274 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4275 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4276 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4277 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4278 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1) - 1181
4279 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4280 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4281 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4282 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4283 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4284 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1) - 1186
4285 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4286 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4287 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4288 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4289 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4290 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4291 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10) - 1192
4292 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4293 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4294 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4295 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4296 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4297 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10) - 1197
4298 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4299 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4300 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4301 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4302 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4303 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4304 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2) - 1203
4305 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4306 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4307 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4308 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4309 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4310 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2) - 1208
4311 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4312 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4313 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4314 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4315 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4316 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4317 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11) - 1214
4318 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4319 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4320 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4321 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4322 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4323 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11) - 1219
4324 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4325 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4326 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4327 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4328 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4329 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4330 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3) - 1225
4331 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4332 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4333 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4334 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4335 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4336 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3) - 1230
4337 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4338 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4339 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4340 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4341 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4342 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4343 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12) - 1236
4344 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4345 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4346 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4347 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4348 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4349 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12) - 1241
4350 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4351 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4352 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4353 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4354 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4355 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4356 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4) - 1247
4357 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4358 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4359 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4360 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4361 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4362 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4) - 1252
4363 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4364 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4365 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4366 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4367 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4368 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4369 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13) - 1258
4370 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4371 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4372 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4373 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4374 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4375 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13) - 1263
4376 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4377 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4378 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4379 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4380 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4381 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4382 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5) - 1269
4383 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4384 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4385 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4386 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4387 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4388 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5) - 1274
4389 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4390 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4391 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4392 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4393 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4394 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4395 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14) - 1280
4396 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4397 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4398 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4399 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4400 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4401 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14) - 1285
4402 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4403 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4404 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4405 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4406 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4407 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4408 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6) - 1291
4409 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4410 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4411 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4412 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4413 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4414 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6) - 1296
4415 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4416 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4417 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4418 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4419 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4420 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4421 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15) - 1302
4422 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4423 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4424 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4425 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4426 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4427 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15) - 1307
4428 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4429 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4430 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4431 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4432 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4433 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4434 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7) - 1313
4435 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4436 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4437 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4438 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4439 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4440 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7) - 1318
4441 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4442 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4443 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4444 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4445 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4446 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4447 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8) - 1324
4448 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4449 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4450 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4451 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4452 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4453 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8) - 1329
4454 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4455 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4456 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4457 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4458 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4459 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4460 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0) - 1335
4461 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4462 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4463 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4464 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4465 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4466 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0) - 1340
4467 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4468 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4469 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4470 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4471 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4472 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4473 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9) - 1346
4474 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4475 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4476 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4477 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4478 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4479 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9) - 1351
4480 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4481 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4482 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4483 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4484 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4485 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4486 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1) - 1357
4487 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4488 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4489 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4490 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4491 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4492 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1) - 1362
4493 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4494 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4495 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4496 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4497 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4498 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4499 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10) - 1368
4500 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4501 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4502 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4503 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4504 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4505 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10) - 1373
4506 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4507 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4508 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4509 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4510 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4511 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4512 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2) - 1379
4513 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4514 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4515 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4516 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4517 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4518 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2) - 1384
4519 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4520 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4521 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4522 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4523 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4524 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4525 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11) - 1390
4526 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4527 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4528 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4529 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4530 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4531 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11) - 1395
4532 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4533 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4534 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4535 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4536 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4537 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4538 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3) - 1401
4539 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4540 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4541 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4542 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4543 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4544 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3) - 1406
4545 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4546 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4547 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4548 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4549 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4550 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4551 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12) - 1412
4552 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4553 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4554 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4555 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4556 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4557 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12) - 1417
4558 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4559 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4560 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4561 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4562 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4563 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4564 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4) - 1423
4565 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4566 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4567 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4568 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4569 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4570 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4) - 1428
4571 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4572 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4573 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4574 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4575 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4576 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4577 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13) - 1434
4578 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4579 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4580 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4581 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4582 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4583 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13) - 1439
4584 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4585 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4586 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4587 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4588 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4589 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4590 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5) - 1445
4591 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4592 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4593 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4594 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4595 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4596 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5) - 1450
4597 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4598 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4599 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4600 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4601 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4602 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4603 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14) - 1456
4604 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4605 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4606 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4607 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4608 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4609 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14) - 1461
4610 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4611 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4612 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4613 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4614 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4615 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4616 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6) - 1467
4617 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4618 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4619 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4620 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4621 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4622 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6) - 1472
4623 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4624 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4625 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4626 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4627 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4628 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4629 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15) - 1478
4630 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4631 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4632 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4633 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4634 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4635 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15) - 1483
4636 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4637 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4638 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4639 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4640 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4641 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4642 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7) - 1489
4643 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4644 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4645 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4646 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4647 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4648 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7) - 1494
4649 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4650 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4651 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4652 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4653 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4654 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4655 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1500
4656 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4657 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4658 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4659 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4660 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4661 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1505
4662 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4663 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4664 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4665 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4666 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4667 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4668 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1511
4669 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4670 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4671 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4672 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4673 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4674 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1516
4675 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4676 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4677 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4678 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4679 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4680 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4681 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1522
4682 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4683 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4684 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4685 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4686 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4687 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1527
4688 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4689 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4690 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4691 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4692 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4693 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4694 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1533
4695 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4696 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4697 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4698 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4699 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4700 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1538
4701 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4702 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4703 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4704 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4705 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4706 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4707 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1544
4708 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4709 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4710 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4711 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4712 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4713 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1549
4714 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4715 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4716 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4717 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4718 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4719 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4720 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1555
4721 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4722 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4723 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4724 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4725 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4726 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1560
4727 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4728 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4729 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4730 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4731 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4732 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4733 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1566
4734 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4735 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4736 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4737 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4738 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4739 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1571
4740 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4741 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4742 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4743 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4744 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4745 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4746 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1577
4747 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4748 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4749 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4750 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4751 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4752 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1582
4753 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4754 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4755 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4756 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4757 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4758 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4759 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1588
4760 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4761 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4762 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4763 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4764 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4765 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1593
4766 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4767 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4768 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4769 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4770 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4771 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4772 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1599
4773 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4774 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4775 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4776 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4777 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4778 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1604
4779 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4780 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4781 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4782 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4783 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4784 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4785 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1610
4786 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4787 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4788 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4789 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4790 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4791 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1615
4792 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4793 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4794 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4795 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4796 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4797 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4798 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1621
4799 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4800 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4801 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4802 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4803 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4804 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1626
4805 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4806 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4807 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4808 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4809 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4810 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4811 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1632
4812 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4813 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4814 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4815 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4816 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4817 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1637
4818 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4819 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4820 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4821 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4822 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4823 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4824 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1643
4825 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4826 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4827 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4828 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4829 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4830 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1648
4831 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4832 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4833 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4834 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4835 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4836 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4837 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1654
4838 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4839 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4840 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4841 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4842 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4843 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1659
4844 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4845 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4846 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4847 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4848 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4849 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4850 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1665
4851 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4852 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4853 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4854 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4855 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4856 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1670
4857 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4858 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4859 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4860 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4861 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4862 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4863 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 2) - 1676
4864 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4865 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4866 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4867 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4868 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4869 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4870 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 3) - 1682
4871 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4872 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4873 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4874 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4875 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4876 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4877 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 6) - 1688
4878 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4879 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4880 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4881 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4882 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4883 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4884 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 7) - 1694
4885 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4886 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4887 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4888 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4889 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4890 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4891 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 2) - 1700
4892 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4893 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4894 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4895 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4896 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4897 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4898 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 3) - 1706
4899 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4900 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4901 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4902 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4903 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4904 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4905 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 6) - 1712
4906 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4907 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4908 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4909 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4910 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4911 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4912 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 7) - 1718
4913 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4914 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4915 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4916 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4917 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4918 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
4919 // (ORCCrr G0, IntRegs:$rs2, G0) - 1724
4920 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4921 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4922 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4923 // (ORri IntRegs:$rd, G0, simm13Op:$simm13) - 1727
4924 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4925 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4926 // (ORrr IntRegs:$rd, G0, IntRegs:$rs2) - 1729
4927 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4928 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4929 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4930 // (RESTORErr G0, G0, G0) - 1732
4931 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4932 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4933 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4934 // (RET 8) - 1735
4935 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4936 // (RETL 8) - 1736
4937 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4938 // (SAVErr G0, G0, G0) - 1737
4939 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4940 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4941 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4942 // (SUBCCri G0, IntRegs:$rs1, simm13Op:$imm) - 1740
4943 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4944 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4945 // (SUBCCrr G0, IntRegs:$rs1, IntRegs:$rs2) - 1742
4946 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4947 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4948 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4949 // (TICCri G0, i32imm:$imm, 8) - 1745
4950 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4951 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4952 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4953 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4954 // (TICCri G0, i32imm:$imm, 8) - 1749
4955 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4956 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4957 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4958 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4959 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4960 // (TICCri IntRegs:$rs1, i32imm:$imm, 8) - 1754
4961 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4962 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4963 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4964 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4965 // (TICCri IntRegs:$rs1, i32imm:$imm, 8) - 1758
4966 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4967 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4968 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4969 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4970 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4971 // (TICCri G0, i32imm:$imm, 0) - 1763
4972 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4973 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4974 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4975 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4976 // (TICCri G0, i32imm:$imm, 0) - 1767
4977 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4978 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4979 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4980 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4981 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4982 // (TICCri IntRegs:$rs1, i32imm:$imm, 0) - 1772
4983 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4984 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4985 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4986 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4987 // (TICCri IntRegs:$rs1, i32imm:$imm, 0) - 1776
4988 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4989 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4990 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4991 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4992 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
4993 // (TICCri G0, i32imm:$imm, 9) - 1781
4994 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4995 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4996 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4997 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4998 // (TICCri G0, i32imm:$imm, 9) - 1785
4999 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5000 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5001 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5002 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5003 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5004 // (TICCri IntRegs:$rs1, i32imm:$imm, 9) - 1790
5005 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5006 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5007 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5008 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5009 // (TICCri IntRegs:$rs1, i32imm:$imm, 9) - 1794
5010 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5011 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5012 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5013 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5014 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5015 // (TICCri G0, i32imm:$imm, 1) - 1799
5016 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5017 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5018 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5019 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5020 // (TICCri G0, i32imm:$imm, 1) - 1803
5021 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5022 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5023 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5024 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5025 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5026 // (TICCri IntRegs:$rs1, i32imm:$imm, 1) - 1808
5027 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5028 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5029 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5030 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5031 // (TICCri IntRegs:$rs1, i32imm:$imm, 1) - 1812
5032 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5033 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5034 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5035 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5036 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5037 // (TICCri G0, i32imm:$imm, 10) - 1817
5038 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5039 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5040 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5041 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5042 // (TICCri G0, i32imm:$imm, 10) - 1821
5043 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5044 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5045 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5046 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5047 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5048 // (TICCri IntRegs:$rs1, i32imm:$imm, 10) - 1826
5049 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5050 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5051 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5052 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5053 // (TICCri IntRegs:$rs1, i32imm:$imm, 10) - 1830
5054 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5055 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5056 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5057 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5058 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5059 // (TICCri G0, i32imm:$imm, 2) - 1835
5060 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5061 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5062 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5063 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5064 // (TICCri G0, i32imm:$imm, 2) - 1839
5065 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5066 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5067 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5068 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5069 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5070 // (TICCri IntRegs:$rs1, i32imm:$imm, 2) - 1844
5071 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5072 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5073 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5074 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5075 // (TICCri IntRegs:$rs1, i32imm:$imm, 2) - 1848
5076 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5077 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5078 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5079 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5080 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5081 // (TICCri G0, i32imm:$imm, 11) - 1853
5082 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5083 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5084 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5085 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5086 // (TICCri G0, i32imm:$imm, 11) - 1857
5087 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5088 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5089 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5090 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5091 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5092 // (TICCri IntRegs:$rs1, i32imm:$imm, 11) - 1862
5093 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5094 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5095 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5096 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5097 // (TICCri IntRegs:$rs1, i32imm:$imm, 11) - 1866
5098 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5099 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5100 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5101 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5102 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5103 // (TICCri G0, i32imm:$imm, 3) - 1871
5104 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5105 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5106 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5107 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5108 // (TICCri G0, i32imm:$imm, 3) - 1875
5109 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5110 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5111 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5112 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5113 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5114 // (TICCri IntRegs:$rs1, i32imm:$imm, 3) - 1880
5115 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5116 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5117 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5118 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5119 // (TICCri IntRegs:$rs1, i32imm:$imm, 3) - 1884
5120 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5121 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5122 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5123 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5124 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5125 // (TICCri G0, i32imm:$imm, 12) - 1889
5126 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5127 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5128 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5129 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5130 // (TICCri G0, i32imm:$imm, 12) - 1893
5131 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5132 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5133 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5134 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5135 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5136 // (TICCri IntRegs:$rs1, i32imm:$imm, 12) - 1898
5137 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5138 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5139 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5140 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5141 // (TICCri IntRegs:$rs1, i32imm:$imm, 12) - 1902
5142 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5143 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5144 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5145 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5146 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5147 // (TICCri G0, i32imm:$imm, 4) - 1907
5148 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5149 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5150 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5151 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5152 // (TICCri G0, i32imm:$imm, 4) - 1911
5153 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5154 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5155 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5156 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5157 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5158 // (TICCri IntRegs:$rs1, i32imm:$imm, 4) - 1916
5159 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5160 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5161 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5162 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5163 // (TICCri IntRegs:$rs1, i32imm:$imm, 4) - 1920
5164 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5165 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5166 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5167 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5168 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5169 // (TICCri G0, i32imm:$imm, 13) - 1925
5170 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5171 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5172 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5173 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5174 // (TICCri G0, i32imm:$imm, 13) - 1929
5175 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5176 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5177 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5178 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5179 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5180 // (TICCri IntRegs:$rs1, i32imm:$imm, 13) - 1934
5181 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5182 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5183 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5184 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5185 // (TICCri IntRegs:$rs1, i32imm:$imm, 13) - 1938
5186 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5187 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5188 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5189 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5190 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5191 // (TICCri G0, i32imm:$imm, 5) - 1943
5192 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5193 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5194 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5195 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5196 // (TICCri G0, i32imm:$imm, 5) - 1947
5197 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5198 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5199 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5200 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5201 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5202 // (TICCri IntRegs:$rs1, i32imm:$imm, 5) - 1952
5203 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5204 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5205 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5206 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5207 // (TICCri IntRegs:$rs1, i32imm:$imm, 5) - 1956
5208 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5209 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5210 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5211 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5212 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5213 // (TICCri G0, i32imm:$imm, 14) - 1961
5214 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5215 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5216 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5217 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5218 // (TICCri G0, i32imm:$imm, 14) - 1965
5219 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5220 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5221 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5222 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5223 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5224 // (TICCri IntRegs:$rs1, i32imm:$imm, 14) - 1970
5225 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5226 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5227 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5228 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5229 // (TICCri IntRegs:$rs1, i32imm:$imm, 14) - 1974
5230 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5231 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5232 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5233 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5234 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5235 // (TICCri G0, i32imm:$imm, 6) - 1979
5236 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5237 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5238 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5239 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5240 // (TICCri G0, i32imm:$imm, 6) - 1983
5241 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5242 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5243 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5244 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5245 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5246 // (TICCri IntRegs:$rs1, i32imm:$imm, 6) - 1988
5247 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5248 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5249 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5250 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5251 // (TICCri IntRegs:$rs1, i32imm:$imm, 6) - 1992
5252 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5253 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5254 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5255 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5256 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5257 // (TICCri G0, i32imm:$imm, 15) - 1997
5258 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5259 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5260 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5261 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5262 // (TICCri G0, i32imm:$imm, 15) - 2001
5263 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5264 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5265 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5266 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5267 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5268 // (TICCri IntRegs:$rs1, i32imm:$imm, 15) - 2006
5269 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5270 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5271 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5272 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5273 // (TICCri IntRegs:$rs1, i32imm:$imm, 15) - 2010
5274 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5275 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5276 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5277 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5278 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5279 // (TICCri G0, i32imm:$imm, 7) - 2015
5280 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5281 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5282 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5283 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5284 // (TICCri G0, i32imm:$imm, 7) - 2019
5285 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5286 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5287 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5288 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5289 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5290 // (TICCri IntRegs:$rs1, i32imm:$imm, 7) - 2024
5291 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5292 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5293 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5294 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5295 // (TICCri IntRegs:$rs1, i32imm:$imm, 7) - 2028
5296 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5297 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5298 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5299 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5300 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5301 // (TICCrr G0, IntRegs:$rs2, 8) - 2033
5302 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5303 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5304 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5305 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5306 // (TICCrr G0, IntRegs:$rs2, 8) - 2037
5307 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5308 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5309 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5310 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5311 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5312 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2042
5313 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5314 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5315 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5316 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5317 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2046
5318 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5319 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5320 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5321 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5322 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5323 // (TICCrr G0, IntRegs:$rs2, 0) - 2051
5324 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5325 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5326 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5327 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5328 // (TICCrr G0, IntRegs:$rs2, 0) - 2055
5329 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5330 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5331 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5332 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5333 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5334 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2060
5335 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5336 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5337 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5338 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5339 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2064
5340 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5341 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5342 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5343 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5344 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5345 // (TICCrr G0, IntRegs:$rs2, 9) - 2069
5346 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5347 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5348 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5349 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5350 // (TICCrr G0, IntRegs:$rs2, 9) - 2073
5351 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5352 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5353 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5354 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5355 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5356 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2078
5357 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5358 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5359 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5360 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5361 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2082
5362 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5363 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5364 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5365 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5366 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5367 // (TICCrr G0, IntRegs:$rs2, 1) - 2087
5368 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5369 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5370 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5371 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5372 // (TICCrr G0, IntRegs:$rs2, 1) - 2091
5373 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5374 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5375 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5376 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5377 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5378 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2096
5379 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5380 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5381 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5382 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5383 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2100
5384 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5385 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5386 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5387 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5388 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5389 // (TICCrr G0, IntRegs:$rs2, 10) - 2105
5390 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5391 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5392 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5393 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5394 // (TICCrr G0, IntRegs:$rs2, 10) - 2109
5395 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5396 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5397 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5398 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5399 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5400 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2114
5401 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5402 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5403 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5404 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5405 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2118
5406 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5407 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5408 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5409 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5410 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5411 // (TICCrr G0, IntRegs:$rs2, 2) - 2123
5412 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5413 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5414 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5415 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5416 // (TICCrr G0, IntRegs:$rs2, 2) - 2127
5417 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5418 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5419 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5420 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5421 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5422 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2132
5423 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5424 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5425 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5426 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5427 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2136
5428 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5429 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5430 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5431 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5432 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5433 // (TICCrr G0, IntRegs:$rs2, 11) - 2141
5434 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5435 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5436 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5437 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5438 // (TICCrr G0, IntRegs:$rs2, 11) - 2145
5439 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5440 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5441 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5442 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5443 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5444 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2150
5445 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5446 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5447 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5448 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5449 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2154
5450 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5451 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5452 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5453 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5454 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5455 // (TICCrr G0, IntRegs:$rs2, 3) - 2159
5456 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5457 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5458 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5459 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5460 // (TICCrr G0, IntRegs:$rs2, 3) - 2163
5461 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5462 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5463 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5464 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5465 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5466 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2168
5467 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5468 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5469 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5470 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5471 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2172
5472 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5473 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5474 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5475 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5476 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5477 // (TICCrr G0, IntRegs:$rs2, 12) - 2177
5478 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5479 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5480 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5481 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5482 // (TICCrr G0, IntRegs:$rs2, 12) - 2181
5483 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5484 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5485 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5486 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5487 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5488 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2186
5489 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5490 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5491 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5492 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5493 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2190
5494 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5495 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5496 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5497 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5498 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5499 // (TICCrr G0, IntRegs:$rs2, 4) - 2195
5500 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5501 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5502 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5503 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5504 // (TICCrr G0, IntRegs:$rs2, 4) - 2199
5505 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5506 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5507 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5508 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5509 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5510 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2204
5511 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5512 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5513 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5514 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5515 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2208
5516 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5517 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5518 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5519 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5520 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5521 // (TICCrr G0, IntRegs:$rs2, 13) - 2213
5522 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5523 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5524 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5525 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5526 // (TICCrr G0, IntRegs:$rs2, 13) - 2217
5527 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5528 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5529 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5530 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5531 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5532 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2222
5533 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5534 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5535 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5536 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5537 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2226
5538 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5539 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5540 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5541 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5542 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5543 // (TICCrr G0, IntRegs:$rs2, 5) - 2231
5544 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5545 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5546 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5547 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5548 // (TICCrr G0, IntRegs:$rs2, 5) - 2235
5549 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5550 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5551 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5552 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5553 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5554 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 2240
5555 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5556 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5557 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5558 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5559 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 2244
5560 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5561 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5562 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5563 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5564 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5565 // (TICCrr G0, IntRegs:$rs2, 14) - 2249
5566 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5567 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5568 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5569 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5570 // (TICCrr G0, IntRegs:$rs2, 14) - 2253
5571 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5572 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5573 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5574 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5575 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5576 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 2258
5577 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5578 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5579 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5580 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5581 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 2262
5582 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5583 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5584 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5585 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5586 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5587 // (TICCrr G0, IntRegs:$rs2, 6) - 2267
5588 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5589 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5590 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5591 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5592 // (TICCrr G0, IntRegs:$rs2, 6) - 2271
5593 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5594 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5595 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5596 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5597 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5598 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 2276
5599 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5600 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5601 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5602 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5603 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 2280
5604 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5605 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5606 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5607 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5608 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5609 // (TICCrr G0, IntRegs:$rs2, 15) - 2285
5610 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5611 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5612 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5613 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5614 // (TICCrr G0, IntRegs:$rs2, 15) - 2289
5615 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5616 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5617 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5618 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5619 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5620 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 2294
5621 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5622 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5623 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5624 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5625 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 2298
5626 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5627 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5628 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5629 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5630 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5631 // (TICCrr G0, IntRegs:$rs2, 7) - 2303
5632 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5633 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5634 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5635 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5636 // (TICCrr G0, IntRegs:$rs2, 7) - 2307
5637 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5638 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5639 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5640 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5641 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5642 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 2312
5643 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5644 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5645 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5646 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5647 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 2316
5648 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5649 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5650 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5651 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5652 {.Kind: AliasPatternCond::K_NegFeature, .Value: Sparc::Feature64Bit},
5653 // (TRAPri G0, i32imm:$imm, 8) - 2321
5654 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5655 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5656 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5657 // (TRAPri IntRegs:$rs1, i32imm:$imm, 8) - 2324
5658 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5659 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5660 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5661 // (TRAPri G0, i32imm:$imm, 0) - 2327
5662 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5663 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5664 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5665 // (TRAPri IntRegs:$rs1, i32imm:$imm, 0) - 2330
5666 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5667 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5668 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5669 // (TRAPri G0, i32imm:$imm, 9) - 2333
5670 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5671 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5672 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5673 // (TRAPri IntRegs:$rs1, i32imm:$imm, 9) - 2336
5674 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5675 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5676 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5677 // (TRAPri G0, i32imm:$imm, 1) - 2339
5678 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5679 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5680 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5681 // (TRAPri IntRegs:$rs1, i32imm:$imm, 1) - 2342
5682 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5683 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5684 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5685 // (TRAPri G0, i32imm:$imm, 10) - 2345
5686 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5687 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5688 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5689 // (TRAPri IntRegs:$rs1, i32imm:$imm, 10) - 2348
5690 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5691 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5692 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5693 // (TRAPri G0, i32imm:$imm, 2) - 2351
5694 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5695 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5696 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5697 // (TRAPri IntRegs:$rs1, i32imm:$imm, 2) - 2354
5698 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5699 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5700 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5701 // (TRAPri G0, i32imm:$imm, 11) - 2357
5702 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5703 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5704 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5705 // (TRAPri IntRegs:$rs1, i32imm:$imm, 11) - 2360
5706 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5707 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5708 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5709 // (TRAPri G0, i32imm:$imm, 3) - 2363
5710 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5711 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5712 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5713 // (TRAPri IntRegs:$rs1, i32imm:$imm, 3) - 2366
5714 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5715 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5716 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5717 // (TRAPri G0, i32imm:$imm, 12) - 2369
5718 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5719 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5720 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5721 // (TRAPri IntRegs:$rs1, i32imm:$imm, 12) - 2372
5722 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5723 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5724 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5725 // (TRAPri G0, i32imm:$imm, 4) - 2375
5726 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5727 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5728 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5729 // (TRAPri IntRegs:$rs1, i32imm:$imm, 4) - 2378
5730 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5731 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5732 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5733 // (TRAPri G0, i32imm:$imm, 13) - 2381
5734 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5735 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5736 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5737 // (TRAPri IntRegs:$rs1, i32imm:$imm, 13) - 2384
5738 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5739 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5740 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5741 // (TRAPri G0, i32imm:$imm, 5) - 2387
5742 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5743 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5744 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5745 // (TRAPri IntRegs:$rs1, i32imm:$imm, 5) - 2390
5746 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5747 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5748 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5749 // (TRAPri G0, i32imm:$imm, 14) - 2393
5750 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5751 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5752 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5753 // (TRAPri IntRegs:$rs1, i32imm:$imm, 14) - 2396
5754 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5755 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5756 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5757 // (TRAPri G0, i32imm:$imm, 6) - 2399
5758 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5759 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5760 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5761 // (TRAPri IntRegs:$rs1, i32imm:$imm, 6) - 2402
5762 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5763 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5764 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5765 // (TRAPri G0, i32imm:$imm, 15) - 2405
5766 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5767 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5768 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5769 // (TRAPri IntRegs:$rs1, i32imm:$imm, 15) - 2408
5770 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5771 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5772 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5773 // (TRAPri G0, i32imm:$imm, 7) - 2411
5774 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5775 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5776 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5777 // (TRAPri IntRegs:$rs1, i32imm:$imm, 7) - 2414
5778 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5779 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5780 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5781 // (TRAPrr G0, IntRegs:$rs1, 8) - 2417
5782 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5783 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5784 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5785 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2420
5786 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5787 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5788 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5789 // (TRAPrr G0, IntRegs:$rs1, 0) - 2423
5790 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5791 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5792 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5793 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2426
5794 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5795 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5796 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5797 // (TRAPrr G0, IntRegs:$rs1, 9) - 2429
5798 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5799 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5800 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5801 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2432
5802 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5803 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5804 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5805 // (TRAPrr G0, IntRegs:$rs1, 1) - 2435
5806 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5807 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5808 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5809 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2438
5810 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5811 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5812 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5813 // (TRAPrr G0, IntRegs:$rs1, 10) - 2441
5814 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5815 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5816 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5817 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2444
5818 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5819 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5820 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5821 // (TRAPrr G0, IntRegs:$rs1, 2) - 2447
5822 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5823 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5824 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5825 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2450
5826 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5827 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5828 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5829 // (TRAPrr G0, IntRegs:$rs1, 11) - 2453
5830 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5831 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5832 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5833 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2456
5834 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5835 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5836 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5837 // (TRAPrr G0, IntRegs:$rs1, 3) - 2459
5838 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5839 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5840 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5841 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2462
5842 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5843 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5844 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5845 // (TRAPrr G0, IntRegs:$rs1, 12) - 2465
5846 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5847 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5848 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5849 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2468
5850 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5851 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5852 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5853 // (TRAPrr G0, IntRegs:$rs1, 4) - 2471
5854 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5855 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5856 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5857 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2474
5858 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5859 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5860 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5861 // (TRAPrr G0, IntRegs:$rs1, 13) - 2477
5862 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5863 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5864 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5865 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2480
5866 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5867 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5868 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5869 // (TRAPrr G0, IntRegs:$rs1, 5) - 2483
5870 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5871 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5872 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5873 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 5) - 2486
5874 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5875 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5876 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5877 // (TRAPrr G0, IntRegs:$rs1, 14) - 2489
5878 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5879 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5880 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5881 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 14) - 2492
5882 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5883 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5884 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5885 // (TRAPrr G0, IntRegs:$rs1, 6) - 2495
5886 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5887 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5888 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5889 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 6) - 2498
5890 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5891 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5892 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5893 // (TRAPrr G0, IntRegs:$rs1, 15) - 2501
5894 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5895 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5896 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5897 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 15) - 2504
5898 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5899 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5900 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5901 // (TRAPrr G0, IntRegs:$rs1, 7) - 2507
5902 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5903 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5904 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5905 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 7) - 2510
5906 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5907 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5908 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5909 // (TXCCri G0, i32imm:$imm, 8) - 2513
5910 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5911 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5912 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5913 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5914 // (TXCCri G0, i32imm:$imm, 8) - 2517
5915 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5916 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5917 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5918 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5919 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5920 // (TXCCri IntRegs:$rs1, i32imm:$imm, 8) - 2522
5921 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5922 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5923 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5924 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5925 // (TXCCri IntRegs:$rs1, i32imm:$imm, 8) - 2526
5926 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5927 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5928 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5929 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5930 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5931 // (TXCCri G0, i32imm:$imm, 0) - 2531
5932 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5933 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5934 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5935 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5936 // (TXCCri G0, i32imm:$imm, 0) - 2535
5937 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5938 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5939 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5940 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5941 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5942 // (TXCCri IntRegs:$rs1, i32imm:$imm, 0) - 2540
5943 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5944 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5945 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5946 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5947 // (TXCCri IntRegs:$rs1, i32imm:$imm, 0) - 2544
5948 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5949 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5950 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5951 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5952 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5953 // (TXCCri G0, i32imm:$imm, 9) - 2549
5954 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5955 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5956 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5957 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5958 // (TXCCri G0, i32imm:$imm, 9) - 2553
5959 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5960 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5961 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5962 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5963 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5964 // (TXCCri IntRegs:$rs1, i32imm:$imm, 9) - 2558
5965 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5966 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5967 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5968 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5969 // (TXCCri IntRegs:$rs1, i32imm:$imm, 9) - 2562
5970 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5971 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5972 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5973 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5974 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5975 // (TXCCri G0, i32imm:$imm, 1) - 2567
5976 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5977 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5978 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5979 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5980 // (TXCCri G0, i32imm:$imm, 1) - 2571
5981 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5982 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5983 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5984 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5985 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5986 // (TXCCri IntRegs:$rs1, i32imm:$imm, 1) - 2576
5987 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5988 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5989 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5990 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5991 // (TXCCri IntRegs:$rs1, i32imm:$imm, 1) - 2580
5992 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5993 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5994 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5995 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5996 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
5997 // (TXCCri G0, i32imm:$imm, 10) - 2585
5998 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5999 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6000 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6001 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6002 // (TXCCri G0, i32imm:$imm, 10) - 2589
6003 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6004 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6005 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6006 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6007 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6008 // (TXCCri IntRegs:$rs1, i32imm:$imm, 10) - 2594
6009 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6010 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6011 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6012 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6013 // (TXCCri IntRegs:$rs1, i32imm:$imm, 10) - 2598
6014 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6015 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6016 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6017 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6018 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6019 // (TXCCri G0, i32imm:$imm, 2) - 2603
6020 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6021 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6022 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6023 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6024 // (TXCCri G0, i32imm:$imm, 2) - 2607
6025 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6026 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6027 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6028 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6029 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6030 // (TXCCri IntRegs:$rs1, i32imm:$imm, 2) - 2612
6031 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6032 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6033 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6034 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6035 // (TXCCri IntRegs:$rs1, i32imm:$imm, 2) - 2616
6036 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6037 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6038 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6039 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6040 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6041 // (TXCCri G0, i32imm:$imm, 11) - 2621
6042 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6043 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6044 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6045 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6046 // (TXCCri G0, i32imm:$imm, 11) - 2625
6047 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6048 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6049 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6050 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6051 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6052 // (TXCCri IntRegs:$rs1, i32imm:$imm, 11) - 2630
6053 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6054 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6055 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6056 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6057 // (TXCCri IntRegs:$rs1, i32imm:$imm, 11) - 2634
6058 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6059 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6060 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6061 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6062 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6063 // (TXCCri G0, i32imm:$imm, 3) - 2639
6064 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6065 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6066 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6067 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6068 // (TXCCri G0, i32imm:$imm, 3) - 2643
6069 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6070 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6071 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6072 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6073 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6074 // (TXCCri IntRegs:$rs1, i32imm:$imm, 3) - 2648
6075 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6076 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6077 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6078 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6079 // (TXCCri IntRegs:$rs1, i32imm:$imm, 3) - 2652
6080 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6081 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6082 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6083 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6084 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6085 // (TXCCri G0, i32imm:$imm, 12) - 2657
6086 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6087 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6088 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6089 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6090 // (TXCCri G0, i32imm:$imm, 12) - 2661
6091 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6092 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6093 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6094 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6095 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6096 // (TXCCri IntRegs:$rs1, i32imm:$imm, 12) - 2666
6097 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6098 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6099 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6100 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6101 // (TXCCri IntRegs:$rs1, i32imm:$imm, 12) - 2670
6102 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6103 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6104 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6105 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6106 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6107 // (TXCCri G0, i32imm:$imm, 4) - 2675
6108 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6109 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6110 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6111 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6112 // (TXCCri G0, i32imm:$imm, 4) - 2679
6113 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6114 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6115 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6116 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6117 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6118 // (TXCCri IntRegs:$rs1, i32imm:$imm, 4) - 2684
6119 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6120 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6121 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6122 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6123 // (TXCCri IntRegs:$rs1, i32imm:$imm, 4) - 2688
6124 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6125 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6126 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6127 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6128 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6129 // (TXCCri G0, i32imm:$imm, 13) - 2693
6130 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6131 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6132 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6133 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6134 // (TXCCri G0, i32imm:$imm, 13) - 2697
6135 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6136 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6137 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6138 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6139 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6140 // (TXCCri IntRegs:$rs1, i32imm:$imm, 13) - 2702
6141 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6142 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6143 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6144 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6145 // (TXCCri IntRegs:$rs1, i32imm:$imm, 13) - 2706
6146 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6147 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6148 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6149 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6150 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6151 // (TXCCri G0, i32imm:$imm, 5) - 2711
6152 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6153 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6154 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6155 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6156 // (TXCCri G0, i32imm:$imm, 5) - 2715
6157 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6158 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6159 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6160 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6161 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6162 // (TXCCri IntRegs:$rs1, i32imm:$imm, 5) - 2720
6163 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6164 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6165 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6166 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6167 // (TXCCri IntRegs:$rs1, i32imm:$imm, 5) - 2724
6168 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6169 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6170 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6171 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6172 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6173 // (TXCCri G0, i32imm:$imm, 14) - 2729
6174 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6175 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6176 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6177 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6178 // (TXCCri G0, i32imm:$imm, 14) - 2733
6179 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6180 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6181 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6182 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6183 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6184 // (TXCCri IntRegs:$rs1, i32imm:$imm, 14) - 2738
6185 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6186 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6187 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6188 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6189 // (TXCCri IntRegs:$rs1, i32imm:$imm, 14) - 2742
6190 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6191 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6192 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6193 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6194 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6195 // (TXCCri G0, i32imm:$imm, 6) - 2747
6196 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6197 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6198 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6199 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6200 // (TXCCri G0, i32imm:$imm, 6) - 2751
6201 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6202 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6203 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6204 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6205 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6206 // (TXCCri IntRegs:$rs1, i32imm:$imm, 6) - 2756
6207 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6208 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6209 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6210 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6211 // (TXCCri IntRegs:$rs1, i32imm:$imm, 6) - 2760
6212 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6213 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6214 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6215 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6216 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6217 // (TXCCri G0, i32imm:$imm, 15) - 2765
6218 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6219 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6220 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6221 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6222 // (TXCCri G0, i32imm:$imm, 15) - 2769
6223 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6224 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6225 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6226 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6227 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6228 // (TXCCri IntRegs:$rs1, i32imm:$imm, 15) - 2774
6229 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6230 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6231 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6232 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6233 // (TXCCri IntRegs:$rs1, i32imm:$imm, 15) - 2778
6234 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6235 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6236 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6237 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6238 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6239 // (TXCCri G0, i32imm:$imm, 7) - 2783
6240 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6241 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6242 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6243 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6244 // (TXCCri G0, i32imm:$imm, 7) - 2787
6245 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6246 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6247 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6248 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6249 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6250 // (TXCCri IntRegs:$rs1, i32imm:$imm, 7) - 2792
6251 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6252 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6253 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6254 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6255 // (TXCCri IntRegs:$rs1, i32imm:$imm, 7) - 2796
6256 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6257 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6258 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6259 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6260 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6261 // (TXCCrr G0, IntRegs:$rs2, 8) - 2801
6262 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6263 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6264 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6265 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6266 // (TXCCrr G0, IntRegs:$rs2, 8) - 2805
6267 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6268 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6269 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6270 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6271 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6272 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2810
6273 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6274 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6275 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6276 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6277 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2814
6278 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6279 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6280 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6281 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6282 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6283 // (TXCCrr G0, IntRegs:$rs2, 0) - 2819
6284 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6285 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6286 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6287 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6288 // (TXCCrr G0, IntRegs:$rs2, 0) - 2823
6289 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6290 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6291 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6292 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6293 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6294 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2828
6295 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6296 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6297 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6298 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6299 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2832
6300 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6301 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6302 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6303 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6304 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6305 // (TXCCrr G0, IntRegs:$rs2, 9) - 2837
6306 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6307 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6308 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6309 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6310 // (TXCCrr G0, IntRegs:$rs2, 9) - 2841
6311 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6312 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6313 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6314 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6315 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6316 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2846
6317 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6318 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6319 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6320 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6321 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2850
6322 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6323 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6324 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6325 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6326 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6327 // (TXCCrr G0, IntRegs:$rs2, 1) - 2855
6328 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6329 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6330 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6331 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6332 // (TXCCrr G0, IntRegs:$rs2, 1) - 2859
6333 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6334 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6335 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6336 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6337 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6338 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2864
6339 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6340 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6341 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6342 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6343 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2868
6344 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6345 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6346 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6347 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6348 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6349 // (TXCCrr G0, IntRegs:$rs2, 10) - 2873
6350 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6351 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6352 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6353 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6354 // (TXCCrr G0, IntRegs:$rs2, 10) - 2877
6355 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6356 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6357 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6358 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6359 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6360 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2882
6361 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6362 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6363 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6364 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6365 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2886
6366 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6367 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6368 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6369 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6370 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6371 // (TXCCrr G0, IntRegs:$rs2, 2) - 2891
6372 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6373 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6374 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6375 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6376 // (TXCCrr G0, IntRegs:$rs2, 2) - 2895
6377 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6378 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6379 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6380 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6381 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6382 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2900
6383 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6384 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6385 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6386 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6387 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2904
6388 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6389 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6390 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6391 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6392 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6393 // (TXCCrr G0, IntRegs:$rs2, 11) - 2909
6394 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6395 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6396 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6397 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6398 // (TXCCrr G0, IntRegs:$rs2, 11) - 2913
6399 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6400 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6401 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6402 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6403 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6404 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2918
6405 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6406 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6407 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6408 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6409 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2922
6410 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6411 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6412 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6413 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6414 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6415 // (TXCCrr G0, IntRegs:$rs2, 3) - 2927
6416 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6417 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6418 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6419 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6420 // (TXCCrr G0, IntRegs:$rs2, 3) - 2931
6421 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6422 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6423 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6424 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6425 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6426 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2936
6427 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6428 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6429 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6430 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6431 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2940
6432 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6433 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6434 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6435 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6436 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6437 // (TXCCrr G0, IntRegs:$rs2, 12) - 2945
6438 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6439 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6440 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6441 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6442 // (TXCCrr G0, IntRegs:$rs2, 12) - 2949
6443 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6444 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6445 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6446 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6447 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6448 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2954
6449 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6450 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6451 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6452 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6453 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2958
6454 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6455 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6456 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6457 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6458 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6459 // (TXCCrr G0, IntRegs:$rs2, 4) - 2963
6460 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6461 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6462 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6463 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6464 // (TXCCrr G0, IntRegs:$rs2, 4) - 2967
6465 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6466 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6467 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6468 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6469 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6470 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2972
6471 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6472 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6473 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6474 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6475 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2976
6476 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6477 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6478 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6479 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6480 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6481 // (TXCCrr G0, IntRegs:$rs2, 13) - 2981
6482 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6483 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6484 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6485 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6486 // (TXCCrr G0, IntRegs:$rs2, 13) - 2985
6487 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6488 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6489 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6490 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6491 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6492 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2990
6493 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6494 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6495 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6496 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6497 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2994
6498 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6499 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6500 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6501 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6502 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6503 // (TXCCrr G0, IntRegs:$rs2, 5) - 2999
6504 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6505 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6506 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6507 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6508 // (TXCCrr G0, IntRegs:$rs2, 5) - 3003
6509 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6510 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6511 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6512 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6513 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6514 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 3008
6515 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6516 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6517 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6518 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6519 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 3012
6520 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6521 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6522 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6523 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6524 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6525 // (TXCCrr G0, IntRegs:$rs2, 14) - 3017
6526 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6527 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6528 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6529 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6530 // (TXCCrr G0, IntRegs:$rs2, 14) - 3021
6531 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6532 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6533 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6534 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6535 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6536 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 3026
6537 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6538 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6539 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6540 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6541 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 3030
6542 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6543 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6544 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6545 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6546 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6547 // (TXCCrr G0, IntRegs:$rs2, 6) - 3035
6548 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6549 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6550 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6551 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6552 // (TXCCrr G0, IntRegs:$rs2, 6) - 3039
6553 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6554 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6555 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6556 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6557 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6558 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 3044
6559 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6560 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6561 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6562 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6563 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 3048
6564 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6565 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6566 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6567 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6568 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6569 // (TXCCrr G0, IntRegs:$rs2, 15) - 3053
6570 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6571 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6572 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6573 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6574 // (TXCCrr G0, IntRegs:$rs2, 15) - 3057
6575 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6576 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6577 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6578 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6579 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6580 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 3062
6581 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6582 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6583 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6584 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6585 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 3066
6586 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6587 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6588 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6589 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6590 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6591 // (TXCCrr G0, IntRegs:$rs2, 7) - 3071
6592 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6593 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6594 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6595 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6596 // (TXCCrr G0, IntRegs:$rs2, 7) - 3075
6597 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6598 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6599 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6600 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6601 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6602 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 3080
6603 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6604 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6605 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6606 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6607 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 3084
6608 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6609 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6610 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6611 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6612 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::Feature64Bit},
6613 // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 3089
6614 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6615 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6616 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6617 // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 3092
6618 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6619 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6620 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6621 // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 3095
6622 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6623 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6624 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6625 // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2) - 3098
6626 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6627 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6628 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6629 // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 3101
6630 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6631 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6632 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6633 // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2) - 3104
6634 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
6635 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6636 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6637 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8) - 3107
6638 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6639 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6640 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6641 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6642 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6643 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6644 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0) - 3113
6645 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6646 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6647 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6648 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6649 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6650 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6651 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7) - 3119
6652 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6653 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6654 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6655 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6656 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6657 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6658 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6) - 3125
6659 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6660 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6661 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6662 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6663 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6664 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6665 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5) - 3131
6666 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6667 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6668 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6669 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6670 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6671 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6672 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4) - 3137
6673 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6674 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6675 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6676 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6677 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6678 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6679 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3) - 3143
6680 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6681 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6682 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6683 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6684 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6685 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6686 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2) - 3149
6687 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6688 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6689 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6690 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6691 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6692 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6693 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1) - 3155
6694 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6695 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6696 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6697 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6698 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6699 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6700 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9) - 3161
6701 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6702 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6703 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6704 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6705 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6706 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6707 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10) - 3167
6708 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6709 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6710 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6711 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6712 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6713 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6714 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11) - 3173
6715 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6716 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6717 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6718 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6719 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6720 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6721 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12) - 3179
6722 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6723 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6724 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6725 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6726 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6727 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6728 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13) - 3185
6729 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6730 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6731 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6732 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6733 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6734 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6735 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14) - 3191
6736 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6737 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6738 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6739 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6740 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6741 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6742 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15) - 3197
6743 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6744 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6745 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
6746 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6747 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6748 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6749 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8) - 3203
6750 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6751 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6752 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6753 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6754 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6755 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6756 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0) - 3209
6757 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6758 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6759 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6760 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6761 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6762 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6763 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7) - 3215
6764 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6765 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6766 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6767 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6768 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6769 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6770 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6) - 3221
6771 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6772 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6773 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6774 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6775 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6776 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6777 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5) - 3227
6778 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6779 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6780 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6781 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6782 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6783 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6784 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4) - 3233
6785 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6786 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6787 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6788 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6789 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6790 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6791 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3) - 3239
6792 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6793 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6794 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6795 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6796 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6797 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6798 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2) - 3245
6799 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6800 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6801 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6802 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6803 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6804 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6805 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1) - 3251
6806 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6807 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6808 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6809 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6810 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6811 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6812 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9) - 3257
6813 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6814 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6815 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6816 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6817 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6818 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6819 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10) - 3263
6820 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6821 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6822 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6823 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6824 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6825 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6826 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11) - 3269
6827 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6828 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6829 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6830 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6831 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6832 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6833 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12) - 3275
6834 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6835 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6836 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6837 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6838 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6839 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6840 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13) - 3281
6841 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6842 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6843 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6844 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6845 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6846 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6847 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14) - 3287
6848 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6849 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6850 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6851 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6852 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6853 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6854 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15) - 3293
6855 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6856 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6857 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
6858 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6859 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6860 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6861 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8) - 3299
6862 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6863 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6864 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6865 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6866 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6867 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6868 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0) - 3305
6869 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6870 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6871 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6872 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6873 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6874 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6875 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7) - 3311
6876 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6877 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6878 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6879 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6880 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6881 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6882 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6) - 3317
6883 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6884 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6885 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6886 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6887 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6888 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6889 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5) - 3323
6890 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6891 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6892 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6893 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6894 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6895 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6896 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4) - 3329
6897 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6898 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6899 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6900 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6901 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6902 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6903 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3) - 3335
6904 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6905 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6906 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6907 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6908 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6909 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6910 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2) - 3341
6911 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6912 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6913 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6914 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6915 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6916 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6917 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1) - 3347
6918 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6919 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6920 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6921 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6922 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6923 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6924 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9) - 3353
6925 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6926 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6927 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6928 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6929 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6930 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6931 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10) - 3359
6932 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6933 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6934 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6935 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6936 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6937 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6938 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11) - 3365
6939 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6940 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6941 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6942 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6943 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6944 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6945 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12) - 3371
6946 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6947 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6948 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6949 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6950 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6951 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6952 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13) - 3377
6953 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6954 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6955 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6956 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6957 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6958 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6959 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14) - 3383
6960 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6961 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6962 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6963 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6964 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6965 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6966 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15) - 3389
6967 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6968 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6969 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
6970 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6971 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6972 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6973 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8) - 3395
6974 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6975 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6976 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6977 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6978 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6979 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6980 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0) - 3401
6981 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6982 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6983 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6984 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6985 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6986 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6987 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7) - 3407
6988 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6989 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6990 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6991 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6992 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6993 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6994 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6) - 3413
6995 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6996 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6997 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6998 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6999 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
7000 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7001 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5) - 3419
7002 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7003 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7004 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7005 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7006 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
7007 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7008 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4) - 3425
7009 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7010 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7011 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7012 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7013 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
7014 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7015 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3) - 3431
7016 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7017 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7018 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7019 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7020 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
7021 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7022 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2) - 3437
7023 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7024 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7025 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7026 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7027 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
7028 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7029 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1) - 3443
7030 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7031 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7032 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7033 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7034 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
7035 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7036 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9) - 3449
7037 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7038 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7039 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7040 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7041 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
7042 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7043 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10) - 3455
7044 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7045 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7046 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7047 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7048 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
7049 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7050 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11) - 3461
7051 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7052 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7053 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7054 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7055 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
7056 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7057 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12) - 3467
7058 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7059 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7060 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7061 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7062 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
7063 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7064 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13) - 3473
7065 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7066 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7067 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7068 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7069 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
7070 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7071 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14) - 3479
7072 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7073 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7074 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7075 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7076 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
7077 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7078 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15) - 3485
7079 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7080 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7081 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7082 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7083 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
7084 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7085 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8) - 3491
7086 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7087 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7088 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7089 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7090 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
7091 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7092 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0) - 3497
7093 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7094 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7095 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7096 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7097 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
7098 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7099 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7) - 3503
7100 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7101 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7102 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7103 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7104 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
7105 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7106 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6) - 3509
7107 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7108 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7109 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7110 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7111 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
7112 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7113 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5) - 3515
7114 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7115 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7116 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7117 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7118 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
7119 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7120 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4) - 3521
7121 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7122 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7123 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7124 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7125 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
7126 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7127 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3) - 3527
7128 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7129 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7130 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7131 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7132 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
7133 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7134 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2) - 3533
7135 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7136 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7137 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7138 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7139 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
7140 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7141 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1) - 3539
7142 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7143 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7144 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7145 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7146 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
7147 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7148 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9) - 3545
7149 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7150 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7151 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7152 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7153 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
7154 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7155 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10) - 3551
7156 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7157 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7158 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7159 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7160 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
7161 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7162 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11) - 3557
7163 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7164 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7165 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7166 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7167 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
7168 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7169 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12) - 3563
7170 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7171 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7172 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7173 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7174 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
7175 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7176 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13) - 3569
7177 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7178 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7179 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7180 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7181 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
7182 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7183 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14) - 3575
7184 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7185 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7186 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7187 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7188 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
7189 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7190 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15) - 3581
7191 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7192 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
7193 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7194 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
7195 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
7196 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
7197 // (WRASRri ASR27, G0, simm13Op:$simm13) - 3587
7198 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::ASR27},
7199 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
7200 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
7201 // (WRASRrr ASR27, G0, IntRegs:$rs2) - 3590
7202 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::ASR27},
7203 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
7204 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
7205 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
7206 };
7207
7208 static const char AsmStrings[] =
7209 /* 0 */ "ba $\xFF\x01\x01\0"
7210 /* 8 */ "bn $\xFF\x01\x01\0"
7211 /* 16 */ "bne $\xFF\x01\x01\0"
7212 /* 25 */ "be $\xFF\x01\x01\0"
7213 /* 33 */ "bg $\xFF\x01\x01\0"
7214 /* 41 */ "ble $\xFF\x01\x01\0"
7215 /* 50 */ "bge $\xFF\x01\x01\0"
7216 /* 59 */ "bl $\xFF\x01\x01\0"
7217 /* 67 */ "bgu $\xFF\x01\x01\0"
7218 /* 76 */ "bleu $\xFF\x01\x01\0"
7219 /* 86 */ "bcc $\xFF\x01\x01\0"
7220 /* 95 */ "bcs $\xFF\x01\x01\0"
7221 /* 104 */ "bpos $\xFF\x01\x01\0"
7222 /* 114 */ "bneg $\xFF\x01\x01\0"
7223 /* 124 */ "bvc $\xFF\x01\x01\0"
7224 /* 133 */ "bvs $\xFF\x01\x01\0"
7225 /* 142 */ "ba,a $\xFF\x01\x01\0"
7226 /* 152 */ "bn,a $\xFF\x01\x01\0"
7227 /* 162 */ "bne,a $\xFF\x01\x01\0"
7228 /* 173 */ "be,a $\xFF\x01\x01\0"
7229 /* 183 */ "bg,a $\xFF\x01\x01\0"
7230 /* 193 */ "ble,a $\xFF\x01\x01\0"
7231 /* 204 */ "bge,a $\xFF\x01\x01\0"
7232 /* 215 */ "bl,a $\xFF\x01\x01\0"
7233 /* 225 */ "bgu,a $\xFF\x01\x01\0"
7234 /* 236 */ "bleu,a $\xFF\x01\x01\0"
7235 /* 248 */ "bcc,a $\xFF\x01\x01\0"
7236 /* 259 */ "bcs,a $\xFF\x01\x01\0"
7237 /* 270 */ "bpos,a $\xFF\x01\x01\0"
7238 /* 282 */ "bneg,a $\xFF\x01\x01\0"
7239 /* 294 */ "bvc,a $\xFF\x01\x01\0"
7240 /* 305 */ "bvs,a $\xFF\x01\x01\0"
7241 /* 316 */ "fba,a,pn $\x03, $\xFF\x01\x01\0"
7242 /* 334 */ "fbn,a,pn $\x03, $\xFF\x01\x01\0"
7243 /* 352 */ "fbu,a,pn $\x03, $\xFF\x01\x01\0"
7244 /* 370 */ "fbg,a,pn $\x03, $\xFF\x01\x01\0"
7245 /* 388 */ "fbug,a,pn $\x03, $\xFF\x01\x01\0"
7246 /* 407 */ "fbl,a,pn $\x03, $\xFF\x01\x01\0"
7247 /* 425 */ "fbul,a,pn $\x03, $\xFF\x01\x01\0"
7248 /* 444 */ "fblg,a,pn $\x03, $\xFF\x01\x01\0"
7249 /* 463 */ "fbne,a,pn $\x03, $\xFF\x01\x01\0"
7250 /* 482 */ "fbe,a,pn $\x03, $\xFF\x01\x01\0"
7251 /* 500 */ "fbue,a,pn $\x03, $\xFF\x01\x01\0"
7252 /* 519 */ "fbge,a,pn $\x03, $\xFF\x01\x01\0"
7253 /* 538 */ "fbuge,a,pn $\x03, $\xFF\x01\x01\0"
7254 /* 558 */ "fble,a,pn $\x03, $\xFF\x01\x01\0"
7255 /* 577 */ "fbule,a,pn $\x03, $\xFF\x01\x01\0"
7256 /* 597 */ "fbo,a,pn $\x03, $\xFF\x01\x01\0"
7257 /* 615 */ "fba,pn $\x03, $\xFF\x01\x01\0"
7258 /* 631 */ "fbn,pn $\x03, $\xFF\x01\x01\0"
7259 /* 647 */ "fbu,pn $\x03, $\xFF\x01\x01\0"
7260 /* 663 */ "fbg,pn $\x03, $\xFF\x01\x01\0"
7261 /* 679 */ "fbug,pn $\x03, $\xFF\x01\x01\0"
7262 /* 696 */ "fbl,pn $\x03, $\xFF\x01\x01\0"
7263 /* 712 */ "fbul,pn $\x03, $\xFF\x01\x01\0"
7264 /* 729 */ "fblg,pn $\x03, $\xFF\x01\x01\0"
7265 /* 746 */ "fbne,pn $\x03, $\xFF\x01\x01\0"
7266 /* 763 */ "fbe,pn $\x03, $\xFF\x01\x01\0"
7267 /* 779 */ "fbue,pn $\x03, $\xFF\x01\x01\0"
7268 /* 796 */ "fbge,pn $\x03, $\xFF\x01\x01\0"
7269 /* 813 */ "fbuge,pn $\x03, $\xFF\x01\x01\0"
7270 /* 831 */ "fble,pn $\x03, $\xFF\x01\x01\0"
7271 /* 848 */ "fbule,pn $\x03, $\xFF\x01\x01\0"
7272 /* 866 */ "fbo,pn $\x03, $\xFF\x01\x01\0"
7273 /* 882 */ "ba,a,pn %icc, $\xFF\x01\x01\0"
7274 /* 901 */ "ba,a,pn %ncc, $\xFF\x01\x01\0"
7275 /* 920 */ "bn,a,pn %icc, $\xFF\x01\x01\0"
7276 /* 939 */ "bn,a,pn %ncc, $\xFF\x01\x01\0"
7277 /* 958 */ "bne,a,pn %icc, $\xFF\x01\x01\0"
7278 /* 978 */ "bne,a,pn %ncc, $\xFF\x01\x01\0"
7279 /* 998 */ "be,a,pn %icc, $\xFF\x01\x01\0"
7280 /* 1017 */ "be,a,pn %ncc, $\xFF\x01\x01\0"
7281 /* 1036 */ "bg,a,pn %icc, $\xFF\x01\x01\0"
7282 /* 1055 */ "bg,a,pn %ncc, $\xFF\x01\x01\0"
7283 /* 1074 */ "ble,a,pn %icc, $\xFF\x01\x01\0"
7284 /* 1094 */ "ble,a,pn %ncc, $\xFF\x01\x01\0"
7285 /* 1114 */ "bge,a,pn %icc, $\xFF\x01\x01\0"
7286 /* 1134 */ "bge,a,pn %ncc, $\xFF\x01\x01\0"
7287 /* 1154 */ "bl,a,pn %icc, $\xFF\x01\x01\0"
7288 /* 1173 */ "bl,a,pn %ncc, $\xFF\x01\x01\0"
7289 /* 1192 */ "bgu,a,pn %icc, $\xFF\x01\x01\0"
7290 /* 1212 */ "bgu,a,pn %ncc, $\xFF\x01\x01\0"
7291 /* 1232 */ "bleu,a,pn %icc, $\xFF\x01\x01\0"
7292 /* 1253 */ "bleu,a,pn %ncc, $\xFF\x01\x01\0"
7293 /* 1274 */ "bcc,a,pn %icc, $\xFF\x01\x01\0"
7294 /* 1294 */ "bcc,a,pn %ncc, $\xFF\x01\x01\0"
7295 /* 1314 */ "bcs,a,pn %icc, $\xFF\x01\x01\0"
7296 /* 1334 */ "bcs,a,pn %ncc, $\xFF\x01\x01\0"
7297 /* 1354 */ "bpos,a,pn %icc, $\xFF\x01\x01\0"
7298 /* 1375 */ "bpos,a,pn %ncc, $\xFF\x01\x01\0"
7299 /* 1396 */ "bneg,a,pn %icc, $\xFF\x01\x01\0"
7300 /* 1417 */ "bneg,a,pn %ncc, $\xFF\x01\x01\0"
7301 /* 1438 */ "bvc,a,pn %icc, $\xFF\x01\x01\0"
7302 /* 1458 */ "bvc,a,pn %ncc, $\xFF\x01\x01\0"
7303 /* 1478 */ "bvs,a,pn %icc, $\xFF\x01\x01\0"
7304 /* 1498 */ "bvs,a,pn %ncc, $\xFF\x01\x01\0"
7305 /* 1518 */ "ba,pn %icc, $\xFF\x01\x01\0"
7306 /* 1535 */ "ba,pn %ncc, $\xFF\x01\x01\0"
7307 /* 1552 */ "bn,pn %icc, $\xFF\x01\x01\0"
7308 /* 1569 */ "bn,pn %ncc, $\xFF\x01\x01\0"
7309 /* 1586 */ "bne,pn %icc, $\xFF\x01\x01\0"
7310 /* 1604 */ "bne,pn %ncc, $\xFF\x01\x01\0"
7311 /* 1622 */ "be,pn %icc, $\xFF\x01\x01\0"
7312 /* 1639 */ "be,pn %ncc, $\xFF\x01\x01\0"
7313 /* 1656 */ "bg,pn %icc, $\xFF\x01\x01\0"
7314 /* 1673 */ "bg,pn %ncc, $\xFF\x01\x01\0"
7315 /* 1690 */ "ble,pn %icc, $\xFF\x01\x01\0"
7316 /* 1708 */ "ble,pn %ncc, $\xFF\x01\x01\0"
7317 /* 1726 */ "bge,pn %icc, $\xFF\x01\x01\0"
7318 /* 1744 */ "bge,pn %ncc, $\xFF\x01\x01\0"
7319 /* 1762 */ "bl,pn %icc, $\xFF\x01\x01\0"
7320 /* 1779 */ "bl,pn %ncc, $\xFF\x01\x01\0"
7321 /* 1796 */ "bgu,pn %icc, $\xFF\x01\x01\0"
7322 /* 1814 */ "bgu,pn %ncc, $\xFF\x01\x01\0"
7323 /* 1832 */ "bleu,pn %icc, $\xFF\x01\x01\0"
7324 /* 1851 */ "bleu,pn %ncc, $\xFF\x01\x01\0"
7325 /* 1870 */ "bcc,pn %icc, $\xFF\x01\x01\0"
7326 /* 1888 */ "bcc,pn %ncc, $\xFF\x01\x01\0"
7327 /* 1906 */ "bcs,pn %icc, $\xFF\x01\x01\0"
7328 /* 1924 */ "bcs,pn %ncc, $\xFF\x01\x01\0"
7329 /* 1942 */ "bpos,pn %icc, $\xFF\x01\x01\0"
7330 /* 1961 */ "bpos,pn %ncc, $\xFF\x01\x01\0"
7331 /* 1980 */ "bneg,pn %icc, $\xFF\x01\x01\0"
7332 /* 1999 */ "bneg,pn %ncc, $\xFF\x01\x01\0"
7333 /* 2018 */ "bvc,pn %icc, $\xFF\x01\x01\0"
7334 /* 2036 */ "bvc,pn %ncc, $\xFF\x01\x01\0"
7335 /* 2054 */ "bvs,pn %icc, $\xFF\x01\x01\0"
7336 /* 2072 */ "bvs,pn %ncc, $\xFF\x01\x01\0"
7337 /* 2090 */ "brlez,a,pn $\x03, $\xFF\x01\x01\0"
7338 /* 2110 */ "brlz,a,pn $\x03, $\xFF\x01\x01\0"
7339 /* 2129 */ "brgz,a,pn $\x03, $\xFF\x01\x01\0"
7340 /* 2148 */ "brgez,a,pn $\x03, $\xFF\x01\x01\0"
7341 /* 2168 */ "brlez,pn $\x03, $\xFF\x01\x01\0"
7342 /* 2186 */ "brlz,pn $\x03, $\xFF\x01\x01\0"
7343 /* 2203 */ "brgz,pn $\x03, $\xFF\x01\x01\0"
7344 /* 2220 */ "brgez,pn $\x03, $\xFF\x01\x01\0"
7345 /* 2238 */ "cas [$\x02], $\x03, $\x01\0"
7346 /* 2255 */ "casl [$\x02], $\x03, $\x01\0"
7347 /* 2273 */ "casx [$\x02], $\x03, $\x01\0"
7348 /* 2291 */ "casxl [$\x02], $\x03, $\x01\0"
7349 /* 2310 */ "cwbne $\x03, $\x04, $\xFF\x01\x01\0"
7350 /* 2329 */ "cwbe $\x03, $\x04, $\xFF\x01\x01\0"
7351 /* 2347 */ "cwbg $\x03, $\x04, $\xFF\x01\x01\0"
7352 /* 2365 */ "cwble $\x03, $\x04, $\xFF\x01\x01\0"
7353 /* 2384 */ "cwbge $\x03, $\x04, $\xFF\x01\x01\0"
7354 /* 2403 */ "cwbl $\x03, $\x04, $\xFF\x01\x01\0"
7355 /* 2421 */ "cwbgu $\x03, $\x04, $\xFF\x01\x01\0"
7356 /* 2440 */ "cwbleu $\x03, $\x04, $\xFF\x01\x01\0"
7357 /* 2460 */ "cwbcc $\x03, $\x04, $\xFF\x01\x01\0"
7358 /* 2479 */ "cwbcs $\x03, $\x04, $\xFF\x01\x01\0"
7359 /* 2498 */ "cwbpos $\x03, $\x04, $\xFF\x01\x01\0"
7360 /* 2518 */ "cwbneg $\x03, $\x04, $\xFF\x01\x01\0"
7361 /* 2538 */ "cwbvc $\x03, $\x04, $\xFF\x01\x01\0"
7362 /* 2557 */ "cwbvs $\x03, $\x04, $\xFF\x01\x01\0"
7363 /* 2576 */ "cxbne $\x03, $\x04, $\xFF\x01\x01\0"
7364 /* 2595 */ "cxbe $\x03, $\x04, $\xFF\x01\x01\0"
7365 /* 2613 */ "cxbg $\x03, $\x04, $\xFF\x01\x01\0"
7366 /* 2631 */ "cxble $\x03, $\x04, $\xFF\x01\x01\0"
7367 /* 2650 */ "cxbge $\x03, $\x04, $\xFF\x01\x01\0"
7368 /* 2669 */ "cxbl $\x03, $\x04, $\xFF\x01\x01\0"
7369 /* 2687 */ "cxbgu $\x03, $\x04, $\xFF\x01\x01\0"
7370 /* 2706 */ "cxbleu $\x03, $\x04, $\xFF\x01\x01\0"
7371 /* 2726 */ "cxbcc $\x03, $\x04, $\xFF\x01\x01\0"
7372 /* 2745 */ "cxbcs $\x03, $\x04, $\xFF\x01\x01\0"
7373 /* 2764 */ "cxbpos $\x03, $\x04, $\xFF\x01\x01\0"
7374 /* 2784 */ "cxbneg $\x03, $\x04, $\xFF\x01\x01\0"
7375 /* 2804 */ "cxbvc $\x03, $\x04, $\xFF\x01\x01\0"
7376 /* 2823 */ "cxbvs $\x03, $\x04, $\xFF\x01\x01\0"
7377 /* 2842 */ "fmovda %icc, $\x02, $\x01\0"
7378 /* 2862 */ "fmovda %ncc, $\x02, $\x01\0"
7379 /* 2882 */ "fmovdn %icc, $\x02, $\x01\0"
7380 /* 2902 */ "fmovdn %ncc, $\x02, $\x01\0"
7381 /* 2922 */ "fmovdne %icc, $\x02, $\x01\0"
7382 /* 2943 */ "fmovdne %ncc, $\x02, $\x01\0"
7383 /* 2964 */ "fmovde %icc, $\x02, $\x01\0"
7384 /* 2984 */ "fmovde %ncc, $\x02, $\x01\0"
7385 /* 3004 */ "fmovdg %icc, $\x02, $\x01\0"
7386 /* 3024 */ "fmovdg %ncc, $\x02, $\x01\0"
7387 /* 3044 */ "fmovdle %icc, $\x02, $\x01\0"
7388 /* 3065 */ "fmovdle %ncc, $\x02, $\x01\0"
7389 /* 3086 */ "fmovdge %icc, $\x02, $\x01\0"
7390 /* 3107 */ "fmovdge %ncc, $\x02, $\x01\0"
7391 /* 3128 */ "fmovdl %icc, $\x02, $\x01\0"
7392 /* 3148 */ "fmovdl %ncc, $\x02, $\x01\0"
7393 /* 3168 */ "fmovdgu %icc, $\x02, $\x01\0"
7394 /* 3189 */ "fmovdgu %ncc, $\x02, $\x01\0"
7395 /* 3210 */ "fmovdleu %icc, $\x02, $\x01\0"
7396 /* 3232 */ "fmovdleu %ncc, $\x02, $\x01\0"
7397 /* 3254 */ "fmovdcc %icc, $\x02, $\x01\0"
7398 /* 3275 */ "fmovdcc %ncc, $\x02, $\x01\0"
7399 /* 3296 */ "fmovdcs %icc, $\x02, $\x01\0"
7400 /* 3317 */ "fmovdcs %ncc, $\x02, $\x01\0"
7401 /* 3338 */ "fmovdpos %icc, $\x02, $\x01\0"
7402 /* 3360 */ "fmovdpos %ncc, $\x02, $\x01\0"
7403 /* 3382 */ "fmovdneg %icc, $\x02, $\x01\0"
7404 /* 3404 */ "fmovdneg %ncc, $\x02, $\x01\0"
7405 /* 3426 */ "fmovdvc %icc, $\x02, $\x01\0"
7406 /* 3447 */ "fmovdvc %ncc, $\x02, $\x01\0"
7407 /* 3468 */ "fmovdvs %icc, $\x02, $\x01\0"
7408 /* 3489 */ "fmovdvs %ncc, $\x02, $\x01\0"
7409 /* 3510 */ "fmovqa %icc, $\x02, $\x01\0"
7410 /* 3530 */ "fmovqa %ncc, $\x02, $\x01\0"
7411 /* 3550 */ "fmovqn %icc, $\x02, $\x01\0"
7412 /* 3570 */ "fmovqn %ncc, $\x02, $\x01\0"
7413 /* 3590 */ "fmovqne %icc, $\x02, $\x01\0"
7414 /* 3611 */ "fmovqne %ncc, $\x02, $\x01\0"
7415 /* 3632 */ "fmovqe %icc, $\x02, $\x01\0"
7416 /* 3652 */ "fmovqe %ncc, $\x02, $\x01\0"
7417 /* 3672 */ "fmovqg %icc, $\x02, $\x01\0"
7418 /* 3692 */ "fmovqg %ncc, $\x02, $\x01\0"
7419 /* 3712 */ "fmovqle %icc, $\x02, $\x01\0"
7420 /* 3733 */ "fmovqle %ncc, $\x02, $\x01\0"
7421 /* 3754 */ "fmovqge %icc, $\x02, $\x01\0"
7422 /* 3775 */ "fmovqge %ncc, $\x02, $\x01\0"
7423 /* 3796 */ "fmovql %icc, $\x02, $\x01\0"
7424 /* 3816 */ "fmovql %ncc, $\x02, $\x01\0"
7425 /* 3836 */ "fmovqgu %icc, $\x02, $\x01\0"
7426 /* 3857 */ "fmovqgu %ncc, $\x02, $\x01\0"
7427 /* 3878 */ "fmovqleu %icc, $\x02, $\x01\0"
7428 /* 3900 */ "fmovqleu %ncc, $\x02, $\x01\0"
7429 /* 3922 */ "fmovqcc %icc, $\x02, $\x01\0"
7430 /* 3943 */ "fmovqcc %ncc, $\x02, $\x01\0"
7431 /* 3964 */ "fmovqcs %icc, $\x02, $\x01\0"
7432 /* 3985 */ "fmovqcs %ncc, $\x02, $\x01\0"
7433 /* 4006 */ "fmovqpos %icc, $\x02, $\x01\0"
7434 /* 4028 */ "fmovqpos %ncc, $\x02, $\x01\0"
7435 /* 4050 */ "fmovqneg %icc, $\x02, $\x01\0"
7436 /* 4072 */ "fmovqneg %ncc, $\x02, $\x01\0"
7437 /* 4094 */ "fmovqvc %icc, $\x02, $\x01\0"
7438 /* 4115 */ "fmovqvc %ncc, $\x02, $\x01\0"
7439 /* 4136 */ "fmovqvs %icc, $\x02, $\x01\0"
7440 /* 4157 */ "fmovqvs %ncc, $\x02, $\x01\0"
7441 /* 4178 */ "fmovrdlez $\x02, $\x03, $\x01\0"
7442 /* 4199 */ "fmovrdlz $\x02, $\x03, $\x01\0"
7443 /* 4219 */ "fmovrdgz $\x02, $\x03, $\x01\0"
7444 /* 4239 */ "fmovrdgez $\x02, $\x03, $\x01\0"
7445 /* 4260 */ "fmovrqlez $\x02, $\x03, $\x01\0"
7446 /* 4281 */ "fmovrqlz $\x02, $\x03, $\x01\0"
7447 /* 4301 */ "fmovrqgz $\x02, $\x03, $\x01\0"
7448 /* 4321 */ "fmovrqgez $\x02, $\x03, $\x01\0"
7449 /* 4342 */ "fmovrslez $\x02, $\x03, $\x01\0"
7450 /* 4363 */ "fmovrslz $\x02, $\x03, $\x01\0"
7451 /* 4383 */ "fmovrsgz $\x02, $\x03, $\x01\0"
7452 /* 4403 */ "fmovrsgez $\x02, $\x03, $\x01\0"
7453 /* 4424 */ "fmovsa %icc, $\x02, $\x01\0"
7454 /* 4444 */ "fmovsa %ncc, $\x02, $\x01\0"
7455 /* 4464 */ "fmovsn %icc, $\x02, $\x01\0"
7456 /* 4484 */ "fmovsn %ncc, $\x02, $\x01\0"
7457 /* 4504 */ "fmovsne %icc, $\x02, $\x01\0"
7458 /* 4525 */ "fmovsne %ncc, $\x02, $\x01\0"
7459 /* 4546 */ "fmovse %icc, $\x02, $\x01\0"
7460 /* 4566 */ "fmovse %ncc, $\x02, $\x01\0"
7461 /* 4586 */ "fmovsg %icc, $\x02, $\x01\0"
7462 /* 4606 */ "fmovsg %ncc, $\x02, $\x01\0"
7463 /* 4626 */ "fmovsle %icc, $\x02, $\x01\0"
7464 /* 4647 */ "fmovsle %ncc, $\x02, $\x01\0"
7465 /* 4668 */ "fmovsge %icc, $\x02, $\x01\0"
7466 /* 4689 */ "fmovsge %ncc, $\x02, $\x01\0"
7467 /* 4710 */ "fmovsl %icc, $\x02, $\x01\0"
7468 /* 4730 */ "fmovsl %ncc, $\x02, $\x01\0"
7469 /* 4750 */ "fmovsgu %icc, $\x02, $\x01\0"
7470 /* 4771 */ "fmovsgu %ncc, $\x02, $\x01\0"
7471 /* 4792 */ "fmovsleu %icc, $\x02, $\x01\0"
7472 /* 4814 */ "fmovsleu %ncc, $\x02, $\x01\0"
7473 /* 4836 */ "fmovscc %icc, $\x02, $\x01\0"
7474 /* 4857 */ "fmovscc %ncc, $\x02, $\x01\0"
7475 /* 4878 */ "fmovscs %icc, $\x02, $\x01\0"
7476 /* 4899 */ "fmovscs %ncc, $\x02, $\x01\0"
7477 /* 4920 */ "fmovspos %icc, $\x02, $\x01\0"
7478 /* 4942 */ "fmovspos %ncc, $\x02, $\x01\0"
7479 /* 4964 */ "fmovsneg %icc, $\x02, $\x01\0"
7480 /* 4986 */ "fmovsneg %ncc, $\x02, $\x01\0"
7481 /* 5008 */ "fmovsvc %icc, $\x02, $\x01\0"
7482 /* 5029 */ "fmovsvc %ncc, $\x02, $\x01\0"
7483 /* 5050 */ "fmovsvs %icc, $\x02, $\x01\0"
7484 /* 5071 */ "fmovsvs %ncc, $\x02, $\x01\0"
7485 /* 5092 */ "mova %icc, $\x02, $\x01\0"
7486 /* 5110 */ "mova %ncc, $\x02, $\x01\0"
7487 /* 5128 */ "movn %icc, $\x02, $\x01\0"
7488 /* 5146 */ "movn %ncc, $\x02, $\x01\0"
7489 /* 5164 */ "movne %icc, $\x02, $\x01\0"
7490 /* 5183 */ "movne %ncc, $\x02, $\x01\0"
7491 /* 5202 */ "move %icc, $\x02, $\x01\0"
7492 /* 5220 */ "move %ncc, $\x02, $\x01\0"
7493 /* 5238 */ "movg %icc, $\x02, $\x01\0"
7494 /* 5256 */ "movg %ncc, $\x02, $\x01\0"
7495 /* 5274 */ "movle %icc, $\x02, $\x01\0"
7496 /* 5293 */ "movle %ncc, $\x02, $\x01\0"
7497 /* 5312 */ "movge %icc, $\x02, $\x01\0"
7498 /* 5331 */ "movge %ncc, $\x02, $\x01\0"
7499 /* 5350 */ "movl %icc, $\x02, $\x01\0"
7500 /* 5368 */ "movl %ncc, $\x02, $\x01\0"
7501 /* 5386 */ "movgu %icc, $\x02, $\x01\0"
7502 /* 5405 */ "movgu %ncc, $\x02, $\x01\0"
7503 /* 5424 */ "movleu %icc, $\x02, $\x01\0"
7504 /* 5444 */ "movleu %ncc, $\x02, $\x01\0"
7505 /* 5464 */ "movcc %icc, $\x02, $\x01\0"
7506 /* 5483 */ "movcc %ncc, $\x02, $\x01\0"
7507 /* 5502 */ "movcs %icc, $\x02, $\x01\0"
7508 /* 5521 */ "movcs %ncc, $\x02, $\x01\0"
7509 /* 5540 */ "movpos %icc, $\x02, $\x01\0"
7510 /* 5560 */ "movpos %ncc, $\x02, $\x01\0"
7511 /* 5580 */ "movneg %icc, $\x02, $\x01\0"
7512 /* 5600 */ "movneg %ncc, $\x02, $\x01\0"
7513 /* 5620 */ "movvc %icc, $\x02, $\x01\0"
7514 /* 5639 */ "movvc %ncc, $\x02, $\x01\0"
7515 /* 5658 */ "movvs %icc, $\x02, $\x01\0"
7516 /* 5677 */ "movvs %ncc, $\x02, $\x01\0"
7517 /* 5696 */ "movrlez $\x02, $\x03, $\x01\0"
7518 /* 5715 */ "movrlz $\x02, $\x03, $\x01\0"
7519 /* 5733 */ "movrgz $\x02, $\x03, $\x01\0"
7520 /* 5751 */ "movrgez $\x02, $\x03, $\x01\0"
7521 /* 5770 */ "tst $\x02\0"
7522 /* 5777 */ "mov $\x03, $\x01\0"
7523 /* 5788 */ "restore\0"
7524 /* 5796 */ "ret\0"
7525 /* 5800 */ "retl\0"
7526 /* 5805 */ "save\0"
7527 /* 5810 */ "cmp $\x02, $\x03\0"
7528 /* 5821 */ "ta %icc, $\x02\0"
7529 /* 5833 */ "ta %ncc, $\x02\0"
7530 /* 5845 */ "ta %icc, $\x01 + $\x02\0"
7531 /* 5862 */ "ta %ncc, $\x01 + $\x02\0"
7532 /* 5879 */ "tn %icc, $\x02\0"
7533 /* 5891 */ "tn %ncc, $\x02\0"
7534 /* 5903 */ "tn %icc, $\x01 + $\x02\0"
7535 /* 5920 */ "tn %ncc, $\x01 + $\x02\0"
7536 /* 5937 */ "tne %icc, $\x02\0"
7537 /* 5950 */ "tne %ncc, $\x02\0"
7538 /* 5963 */ "tne %icc, $\x01 + $\x02\0"
7539 /* 5981 */ "tne %ncc, $\x01 + $\x02\0"
7540 /* 5999 */ "te %icc, $\x02\0"
7541 /* 6011 */ "te %ncc, $\x02\0"
7542 /* 6023 */ "te %icc, $\x01 + $\x02\0"
7543 /* 6040 */ "te %ncc, $\x01 + $\x02\0"
7544 /* 6057 */ "tg %icc, $\x02\0"
7545 /* 6069 */ "tg %ncc, $\x02\0"
7546 /* 6081 */ "tg %icc, $\x01 + $\x02\0"
7547 /* 6098 */ "tg %ncc, $\x01 + $\x02\0"
7548 /* 6115 */ "tle %icc, $\x02\0"
7549 /* 6128 */ "tle %ncc, $\x02\0"
7550 /* 6141 */ "tle %icc, $\x01 + $\x02\0"
7551 /* 6159 */ "tle %ncc, $\x01 + $\x02\0"
7552 /* 6177 */ "tge %icc, $\x02\0"
7553 /* 6190 */ "tge %ncc, $\x02\0"
7554 /* 6203 */ "tge %icc, $\x01 + $\x02\0"
7555 /* 6221 */ "tge %ncc, $\x01 + $\x02\0"
7556 /* 6239 */ "tl %icc, $\x02\0"
7557 /* 6251 */ "tl %ncc, $\x02\0"
7558 /* 6263 */ "tl %icc, $\x01 + $\x02\0"
7559 /* 6280 */ "tl %ncc, $\x01 + $\x02\0"
7560 /* 6297 */ "tgu %icc, $\x02\0"
7561 /* 6310 */ "tgu %ncc, $\x02\0"
7562 /* 6323 */ "tgu %icc, $\x01 + $\x02\0"
7563 /* 6341 */ "tgu %ncc, $\x01 + $\x02\0"
7564 /* 6359 */ "tleu %icc, $\x02\0"
7565 /* 6373 */ "tleu %ncc, $\x02\0"
7566 /* 6387 */ "tleu %icc, $\x01 + $\x02\0"
7567 /* 6406 */ "tleu %ncc, $\x01 + $\x02\0"
7568 /* 6425 */ "tcc %icc, $\x02\0"
7569 /* 6438 */ "tcc %ncc, $\x02\0"
7570 /* 6451 */ "tcc %icc, $\x01 + $\x02\0"
7571 /* 6469 */ "tcc %ncc, $\x01 + $\x02\0"
7572 /* 6487 */ "tcs %icc, $\x02\0"
7573 /* 6500 */ "tcs %ncc, $\x02\0"
7574 /* 6513 */ "tcs %icc, $\x01 + $\x02\0"
7575 /* 6531 */ "tcs %ncc, $\x01 + $\x02\0"
7576 /* 6549 */ "tpos %icc, $\x02\0"
7577 /* 6563 */ "tpos %ncc, $\x02\0"
7578 /* 6577 */ "tpos %icc, $\x01 + $\x02\0"
7579 /* 6596 */ "tpos %ncc, $\x01 + $\x02\0"
7580 /* 6615 */ "tneg %icc, $\x02\0"
7581 /* 6629 */ "tneg %ncc, $\x02\0"
7582 /* 6643 */ "tneg %icc, $\x01 + $\x02\0"
7583 /* 6662 */ "tneg %ncc, $\x01 + $\x02\0"
7584 /* 6681 */ "tvc %icc, $\x02\0"
7585 /* 6694 */ "tvc %ncc, $\x02\0"
7586 /* 6707 */ "tvc %icc, $\x01 + $\x02\0"
7587 /* 6725 */ "tvc %ncc, $\x01 + $\x02\0"
7588 /* 6743 */ "tvs %icc, $\x02\0"
7589 /* 6756 */ "tvs %ncc, $\x02\0"
7590 /* 6769 */ "tvs %icc, $\x01 + $\x02\0"
7591 /* 6787 */ "tvs %ncc, $\x01 + $\x02\0"
7592 /* 6805 */ "ta $\x02\0"
7593 /* 6811 */ "ta $\x01 + $\x02\0"
7594 /* 6822 */ "tn $\x02\0"
7595 /* 6828 */ "tn $\x01 + $\x02\0"
7596 /* 6839 */ "tne $\x02\0"
7597 /* 6846 */ "tne $\x01 + $\x02\0"
7598 /* 6858 */ "te $\x02\0"
7599 /* 6864 */ "te $\x01 + $\x02\0"
7600 /* 6875 */ "tg $\x02\0"
7601 /* 6881 */ "tg $\x01 + $\x02\0"
7602 /* 6892 */ "tle $\x02\0"
7603 /* 6899 */ "tle $\x01 + $\x02\0"
7604 /* 6911 */ "tge $\x02\0"
7605 /* 6918 */ "tge $\x01 + $\x02\0"
7606 /* 6930 */ "tl $\x02\0"
7607 /* 6936 */ "tl $\x01 + $\x02\0"
7608 /* 6947 */ "tgu $\x02\0"
7609 /* 6954 */ "tgu $\x01 + $\x02\0"
7610 /* 6966 */ "tleu $\x02\0"
7611 /* 6974 */ "tleu $\x01 + $\x02\0"
7612 /* 6987 */ "tcc $\x02\0"
7613 /* 6994 */ "tcc $\x01 + $\x02\0"
7614 /* 7006 */ "tcs $\x02\0"
7615 /* 7013 */ "tcs $\x01 + $\x02\0"
7616 /* 7025 */ "tpos $\x02\0"
7617 /* 7033 */ "tpos $\x01 + $\x02\0"
7618 /* 7046 */ "tneg $\x02\0"
7619 /* 7054 */ "tneg $\x01 + $\x02\0"
7620 /* 7067 */ "tvc $\x02\0"
7621 /* 7074 */ "tvc $\x01 + $\x02\0"
7622 /* 7086 */ "tvs $\x02\0"
7623 /* 7093 */ "tvs $\x01 + $\x02\0"
7624 /* 7105 */ "ta %xcc, $\x02\0"
7625 /* 7117 */ "ta %xcc, $\x01 + $\x02\0"
7626 /* 7134 */ "tn %xcc, $\x02\0"
7627 /* 7146 */ "tn %xcc, $\x01 + $\x02\0"
7628 /* 7163 */ "tne %xcc, $\x02\0"
7629 /* 7176 */ "tne %xcc, $\x01 + $\x02\0"
7630 /* 7194 */ "te %xcc, $\x02\0"
7631 /* 7206 */ "te %xcc, $\x01 + $\x02\0"
7632 /* 7223 */ "tg %xcc, $\x02\0"
7633 /* 7235 */ "tg %xcc, $\x01 + $\x02\0"
7634 /* 7252 */ "tle %xcc, $\x02\0"
7635 /* 7265 */ "tle %xcc, $\x01 + $\x02\0"
7636 /* 7283 */ "tge %xcc, $\x02\0"
7637 /* 7296 */ "tge %xcc, $\x01 + $\x02\0"
7638 /* 7314 */ "tl %xcc, $\x02\0"
7639 /* 7326 */ "tl %xcc, $\x01 + $\x02\0"
7640 /* 7343 */ "tgu %xcc, $\x02\0"
7641 /* 7356 */ "tgu %xcc, $\x01 + $\x02\0"
7642 /* 7374 */ "tleu %xcc, $\x02\0"
7643 /* 7388 */ "tleu %xcc, $\x01 + $\x02\0"
7644 /* 7407 */ "tcc %xcc, $\x02\0"
7645 /* 7420 */ "tcc %xcc, $\x01 + $\x02\0"
7646 /* 7438 */ "tcs %xcc, $\x02\0"
7647 /* 7451 */ "tcs %xcc, $\x01 + $\x02\0"
7648 /* 7469 */ "tpos %xcc, $\x02\0"
7649 /* 7483 */ "tpos %xcc, $\x01 + $\x02\0"
7650 /* 7502 */ "tneg %xcc, $\x02\0"
7651 /* 7516 */ "tneg %xcc, $\x01 + $\x02\0"
7652 /* 7535 */ "tvc %xcc, $\x02\0"
7653 /* 7548 */ "tvc %xcc, $\x01 + $\x02\0"
7654 /* 7566 */ "tvs %xcc, $\x02\0"
7655 /* 7579 */ "tvs %xcc, $\x01 + $\x02\0"
7656 /* 7597 */ "fcmpd $\x02, $\x03\0"
7657 /* 7610 */ "fcmped $\x02, $\x03\0"
7658 /* 7624 */ "fcmpeq $\x02, $\x03\0"
7659 /* 7638 */ "fcmpes $\x02, $\x03\0"
7660 /* 7652 */ "fcmpq $\x02, $\x03\0"
7661 /* 7665 */ "fcmps $\x02, $\x03\0"
7662 /* 7678 */ "fmovda $\x02, $\x03, $\x01\0"
7663 /* 7696 */ "fmovdn $\x02, $\x03, $\x01\0"
7664 /* 7714 */ "fmovdu $\x02, $\x03, $\x01\0"
7665 /* 7732 */ "fmovdg $\x02, $\x03, $\x01\0"
7666 /* 7750 */ "fmovdug $\x02, $\x03, $\x01\0"
7667 /* 7769 */ "fmovdl $\x02, $\x03, $\x01\0"
7668 /* 7787 */ "fmovdul $\x02, $\x03, $\x01\0"
7669 /* 7806 */ "fmovdlg $\x02, $\x03, $\x01\0"
7670 /* 7825 */ "fmovdne $\x02, $\x03, $\x01\0"
7671 /* 7844 */ "fmovde $\x02, $\x03, $\x01\0"
7672 /* 7862 */ "fmovdue $\x02, $\x03, $\x01\0"
7673 /* 7881 */ "fmovdge $\x02, $\x03, $\x01\0"
7674 /* 7900 */ "fmovduge $\x02, $\x03, $\x01\0"
7675 /* 7920 */ "fmovdle $\x02, $\x03, $\x01\0"
7676 /* 7939 */ "fmovdule $\x02, $\x03, $\x01\0"
7677 /* 7959 */ "fmovdo $\x02, $\x03, $\x01\0"
7678 /* 7977 */ "fmovqa $\x02, $\x03, $\x01\0"
7679 /* 7995 */ "fmovqn $\x02, $\x03, $\x01\0"
7680 /* 8013 */ "fmovqu $\x02, $\x03, $\x01\0"
7681 /* 8031 */ "fmovqg $\x02, $\x03, $\x01\0"
7682 /* 8049 */ "fmovqug $\x02, $\x03, $\x01\0"
7683 /* 8068 */ "fmovql $\x02, $\x03, $\x01\0"
7684 /* 8086 */ "fmovqul $\x02, $\x03, $\x01\0"
7685 /* 8105 */ "fmovqlg $\x02, $\x03, $\x01\0"
7686 /* 8124 */ "fmovqne $\x02, $\x03, $\x01\0"
7687 /* 8143 */ "fmovqe $\x02, $\x03, $\x01\0"
7688 /* 8161 */ "fmovque $\x02, $\x03, $\x01\0"
7689 /* 8180 */ "fmovqge $\x02, $\x03, $\x01\0"
7690 /* 8199 */ "fmovquge $\x02, $\x03, $\x01\0"
7691 /* 8219 */ "fmovqle $\x02, $\x03, $\x01\0"
7692 /* 8238 */ "fmovqule $\x02, $\x03, $\x01\0"
7693 /* 8258 */ "fmovqo $\x02, $\x03, $\x01\0"
7694 /* 8276 */ "fmovsa $\x02, $\x03, $\x01\0"
7695 /* 8294 */ "fmovsn $\x02, $\x03, $\x01\0"
7696 /* 8312 */ "fmovsu $\x02, $\x03, $\x01\0"
7697 /* 8330 */ "fmovsg $\x02, $\x03, $\x01\0"
7698 /* 8348 */ "fmovsug $\x02, $\x03, $\x01\0"
7699 /* 8367 */ "fmovsl $\x02, $\x03, $\x01\0"
7700 /* 8385 */ "fmovsul $\x02, $\x03, $\x01\0"
7701 /* 8404 */ "fmovslg $\x02, $\x03, $\x01\0"
7702 /* 8423 */ "fmovsne $\x02, $\x03, $\x01\0"
7703 /* 8442 */ "fmovse $\x02, $\x03, $\x01\0"
7704 /* 8460 */ "fmovsue $\x02, $\x03, $\x01\0"
7705 /* 8479 */ "fmovsge $\x02, $\x03, $\x01\0"
7706 /* 8498 */ "fmovsuge $\x02, $\x03, $\x01\0"
7707 /* 8518 */ "fmovsle $\x02, $\x03, $\x01\0"
7708 /* 8537 */ "fmovsule $\x02, $\x03, $\x01\0"
7709 /* 8557 */ "fmovso $\x02, $\x03, $\x01\0"
7710 /* 8575 */ "mova $\x02, $\x03, $\x01\0"
7711 /* 8591 */ "movn $\x02, $\x03, $\x01\0"
7712 /* 8607 */ "movu $\x02, $\x03, $\x01\0"
7713 /* 8623 */ "movg $\x02, $\x03, $\x01\0"
7714 /* 8639 */ "movug $\x02, $\x03, $\x01\0"
7715 /* 8656 */ "movl $\x02, $\x03, $\x01\0"
7716 /* 8672 */ "movul $\x02, $\x03, $\x01\0"
7717 /* 8689 */ "movlg $\x02, $\x03, $\x01\0"
7718 /* 8706 */ "movne $\x02, $\x03, $\x01\0"
7719 /* 8723 */ "move $\x02, $\x03, $\x01\0"
7720 /* 8739 */ "movue $\x02, $\x03, $\x01\0"
7721 /* 8756 */ "movge $\x02, $\x03, $\x01\0"
7722 /* 8773 */ "movuge $\x02, $\x03, $\x01\0"
7723 /* 8791 */ "movle $\x02, $\x03, $\x01\0"
7724 /* 8808 */ "movule $\x02, $\x03, $\x01\0"
7725 /* 8826 */ "movo $\x02, $\x03, $\x01\0"
7726 /* 8842 */ "pause $\x03\0"
7727 ;
7728
7729#ifndef NDEBUG
7730 static struct SortCheck {
7731 SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
7732 assert(std::is_sorted(
7733 OpToPatterns.begin(), OpToPatterns.end(),
7734 [](const PatternsForOpcode &L, const PatternsForOpcode &R) {
7735 return L.Opcode < R.Opcode;
7736 }) &&
7737 "tablegen failed to sort opcode patterns");
7738 }
7739 } sortCheckVar(OpToPatterns);
7740#endif
7741
7742 AliasMatchingData M {
7743 .OpToPatterns: ArrayRef(OpToPatterns),
7744 .Patterns: ArrayRef(Patterns),
7745 .PatternConds: ArrayRef(Conds),
7746 .AsmStrings: StringRef(AsmStrings, std::size(AsmStrings)),
7747 .ValidateMCOperand: nullptr,
7748 };
7749 const char *AsmString = matchAliasPatterns(MI, STI: &STI, M);
7750 if (!AsmString) return false;
7751
7752 unsigned I = 0;
7753 while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
7754 AsmString[I] != '$' && AsmString[I] != '\0')
7755 ++I;
7756 OS << '\t' << StringRef(AsmString, I);
7757 if (AsmString[I] != '\0') {
7758 if (AsmString[I] == ' ' || AsmString[I] == '\t') {
7759 OS << '\t';
7760 ++I;
7761 }
7762 do {
7763 if (AsmString[I] == '$') {
7764 ++I;
7765 if (AsmString[I] == (char)0xff) {
7766 ++I;
7767 int OpIdx = AsmString[I++] - 1;
7768 int PrintMethodIdx = AsmString[I++] - 1;
7769 printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, STI, O&: OS);
7770 } else
7771 printOperand(MI, opNum: unsigned(AsmString[I++]) - 1, STI, OS);
7772 } else {
7773 OS << AsmString[I++];
7774 }
7775 } while (AsmString[I] != '\0');
7776 }
7777
7778 return true;
7779}
7780
7781void SparcInstPrinter::printCustomAliasOperand(
7782 const MCInst *MI, uint64_t Address, unsigned OpIdx,
7783 unsigned PrintMethodIdx,
7784 const MCSubtargetInfo &STI,
7785 raw_ostream &OS) {
7786 switch (PrintMethodIdx) {
7787 default:
7788 llvm_unreachable("Unknown PrintMethod kind");
7789 break;
7790 case 0:
7791 printCTILabel(MI, Address, OpNum: OpIdx, STI, O&: OS);
7792 break;
7793 }
7794}
7795
7796#endif // PRINT_ALIAS_INSTR
7797