1//===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax -----==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This class prints an Sparc MCInst to a .s file.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SparcInstPrinter.h"
14#include "Sparc.h"
15#include "llvm/ADT/StringExtras.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCExpr.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCSubtargetInfo.h"
20#include "llvm/MC/MCSymbol.h"
21#include "llvm/Support/raw_ostream.h"
22using namespace llvm;
23
24#define DEBUG_TYPE "asm-printer"
25
26// The generated AsmMatcher SparcGenAsmWriter uses "Sparc" as the target
27// namespace. But SPARC backend uses "SP" as its namespace.
28namespace llvm {
29namespace Sparc {
30 using namespace SP;
31}
32}
33
34#define GET_INSTRUCTION_NAME
35#define PRINT_ALIAS_INSTR
36#include "SparcGenAsmWriter.inc"
37
38bool SparcInstPrinter::isV9(const MCSubtargetInfo &STI) const {
39 return (STI.hasFeature(Feature: Sparc::FeatureV9)) != 0;
40}
41
42void SparcInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) {
43 OS << '%' << getRegisterName(Reg);
44}
45
46void SparcInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg,
47 unsigned AltIdx) const {
48 OS << '%' << getRegisterName(Reg, AltIdx);
49}
50
51void SparcInstPrinter::printInst(const MCInst *MI, uint64_t Address,
52 StringRef Annot, const MCSubtargetInfo &STI,
53 raw_ostream &O) {
54 if (!printAliasInstr(MI, Address, STI, OS&: O) &&
55 !printSparcAliasInstr(MI, STI, OS&: O))
56 printInstruction(MI, Address, STI, O);
57 printAnnotation(OS&: O, Annot);
58}
59
60bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI,
61 const MCSubtargetInfo &STI,
62 raw_ostream &O) {
63 switch (MI->getOpcode()) {
64 default: return false;
65 case SP::JMPLrr:
66 case SP::JMPLri: {
67 if (MI->getNumOperands() != 3)
68 return false;
69 if (!MI->getOperand(i: 0).isReg())
70 return false;
71 switch (MI->getOperand(i: 0).getReg().id()) {
72 default: return false;
73 case SP::G0: // jmp $addr | ret | retl
74 if (MI->getOperand(i: 2).isImm() &&
75 MI->getOperand(i: 2).getImm() == 8) {
76 switch (MI->getOperand(i: 1).getReg().id()) {
77 default: break;
78 case SP::I7: O << "\tret"; return true;
79 case SP::O7: O << "\tretl"; return true;
80 }
81 }
82 O << "\tjmp "; printMemOperand(MI, opNum: 1, STI, OS&: O);
83 return true;
84 case SP::O7: // call $addr
85 O << "\tcall "; printMemOperand(MI, opNum: 1, STI, OS&: O);
86 return true;
87 }
88 }
89 case SP::V9FCMPS: case SP::V9FCMPD: case SP::V9FCMPQ:
90 case SP::V9FCMPES: case SP::V9FCMPED: case SP::V9FCMPEQ: {
91 if (isV9(STI)
92 || (MI->getNumOperands() != 3)
93 || (!MI->getOperand(i: 0).isReg())
94 || (MI->getOperand(i: 0).getReg() != SP::FCC0))
95 return false;
96 // if V8, skip printing %fcc0.
97 switch(MI->getOpcode()) {
98 default:
99 case SP::V9FCMPS: O << "\tfcmps "; break;
100 case SP::V9FCMPD: O << "\tfcmpd "; break;
101 case SP::V9FCMPQ: O << "\tfcmpq "; break;
102 case SP::V9FCMPES: O << "\tfcmpes "; break;
103 case SP::V9FCMPED: O << "\tfcmped "; break;
104 case SP::V9FCMPEQ: O << "\tfcmpeq "; break;
105 }
106 printOperand(MI, opNum: 1, STI, OS&: O);
107 O << ", ";
108 printOperand(MI, opNum: 2, STI, OS&: O);
109 return true;
110 }
111 }
112}
113
114void SparcInstPrinter::printOperand(const MCInst *MI, int opNum,
115 const MCSubtargetInfo &STI,
116 raw_ostream &O) {
117 const MCOperand &MO = MI->getOperand (i: opNum);
118
119 if (MO.isReg()) {
120 MCRegister Reg = MO.getReg();
121 if (isV9(STI))
122 printRegName(OS&: O, Reg, AltIdx: SP::RegNamesStateReg);
123 else
124 printRegName(OS&: O, Reg);
125 return ;
126 }
127
128 if (MO.isImm()) {
129 switch (MI->getOpcode()) {
130 default:
131 markup(OS&: O, M: Markup::Immediate) << formatImm(Value: int32_t(MO.getImm()));
132 return;
133
134 case SP::TICCri: // Fall through
135 case SP::TICCrr: // Fall through
136 case SP::TRAPri: // Fall through
137 case SP::TRAPrr: // Fall through
138 case SP::TXCCri: // Fall through
139 case SP::TXCCrr: // Fall through
140 // Only seven-bit values up to 127.
141 O << ((int) MO.getImm() & 0x7f);
142 return;
143 }
144 }
145
146 assert(MO.isExpr() && "Unknown operand kind in printOperand");
147 MAI.printExpr(O, *MO.getExpr());
148}
149
150void SparcInstPrinter::printMemOperand(const MCInst *MI, int opNum,
151 const MCSubtargetInfo &STI,
152 raw_ostream &O) {
153 const MCOperand &Op1 = MI->getOperand(i: opNum);
154 const MCOperand &Op2 = MI->getOperand(i: opNum + 1);
155
156 bool PrintedFirstOperand = false;
157 if (Op1.isReg() && Op1.getReg() != SP::G0) {
158 printOperand(MI, opNum, STI, O);
159 PrintedFirstOperand = true;
160 }
161
162 // Skip the second operand iff it adds nothing (literal 0 or %g0) and we've
163 // already printed the first one
164 const bool SkipSecondOperand =
165 PrintedFirstOperand && ((Op2.isReg() && Op2.getReg() == SP::G0) ||
166 (Op2.isImm() && Op2.getImm() == 0));
167
168 if (!SkipSecondOperand) {
169 if (PrintedFirstOperand)
170 O << '+';
171 printOperand(MI, opNum: opNum + 1, STI, O);
172 }
173}
174
175void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum,
176 const MCSubtargetInfo &STI,
177 raw_ostream &O) {
178 int CC = (int)MI->getOperand(i: opNum).getImm();
179 switch (MI->getOpcode()) {
180 default: break;
181 case SP::FBCOND:
182 case SP::FBCONDA:
183 case SP::FBCOND_V9:
184 case SP::FBCONDA_V9:
185 case SP::BPFCC:
186 case SP::BPFCCA:
187 case SP::BPFCCNT:
188 case SP::BPFCCANT:
189 case SP::MOVFCCrr: case SP::V9MOVFCCrr:
190 case SP::MOVFCCri: case SP::V9MOVFCCri:
191 case SP::FMOVS_FCC: case SP::V9FMOVS_FCC:
192 case SP::FMOVD_FCC: case SP::V9FMOVD_FCC:
193 case SP::FMOVQ_FCC: case SP::V9FMOVQ_FCC:
194 // Make sure CC is a fp conditional flag.
195 CC = (CC < SPCC::FCC_BEGIN) ? (CC + SPCC::FCC_BEGIN) : CC;
196 break;
197 case SP::CPBCOND:
198 case SP::CPBCONDA:
199 // Make sure CC is a cp conditional flag.
200 CC = (CC < SPCC::CPCC_BEGIN) ? (CC + SPCC::CPCC_BEGIN) : CC;
201 break;
202 case SP::BPR:
203 case SP::BPRA:
204 case SP::BPRNT:
205 case SP::BPRANT:
206 case SP::MOVRri:
207 case SP::MOVRrr:
208 case SP::FMOVRS:
209 case SP::FMOVRD:
210 case SP::FMOVRQ:
211 // Make sure CC is a register conditional flag.
212 CC = (CC < SPCC::REG_BEGIN) ? (CC + SPCC::REG_BEGIN) : CC;
213 break;
214 }
215 O << SPARCCondCodeToString(CC: (SPCC::CondCodes)CC);
216}
217
218bool SparcInstPrinter::printGetPCX(const MCInst *MI, unsigned opNum,
219 const MCSubtargetInfo &STI,
220 raw_ostream &O) {
221 llvm_unreachable("FIXME: Implement SparcInstPrinter::printGetPCX.");
222 return true;
223}
224
225void SparcInstPrinter::printMembarTag(const MCInst *MI, int opNum,
226 const MCSubtargetInfo &STI,
227 raw_ostream &O) {
228 static const char *const TagNames[] = {
229 "#LoadLoad", "#StoreLoad", "#LoadStore", "#StoreStore",
230 "#Lookaside", "#MemIssue", "#Sync"};
231
232 unsigned Imm = MI->getOperand(i: opNum).getImm();
233
234 if (Imm > 127) {
235 O << Imm;
236 return;
237 }
238
239 ListSeparator LS(" | ");
240 for (unsigned i = 0; i < std::size(TagNames); i++) {
241 if (Imm & (1 << i))
242 O << LS << TagNames[i];
243 }
244}
245
246void SparcInstPrinter::printASITag(const MCInst *MI, int opNum,
247 const MCSubtargetInfo &STI, raw_ostream &O) {
248 unsigned Imm = MI->getOperand(i: opNum).getImm();
249 auto ASITag = SparcASITag::lookupASITagByEncoding(Encoding: Imm);
250 if (isV9(STI) && ASITag)
251 O << '#' << ASITag->Name;
252 else
253 O << Imm;
254}
255
256void SparcInstPrinter::printPrefetchTag(const MCInst *MI, int opNum,
257 const MCSubtargetInfo &STI,
258 raw_ostream &O) {
259 unsigned Imm = MI->getOperand(i: opNum).getImm();
260 auto PrefetchTag = SparcPrefetchTag::lookupPrefetchTagByEncoding(Encoding: Imm);
261 if (PrefetchTag)
262 O << '#' << PrefetchTag->Name;
263 else
264 O << Imm;
265}
266
267void SparcInstPrinter::printCTILabel(const MCInst *MI, uint64_t Address,
268 unsigned OpNum, const MCSubtargetInfo &STI,
269 raw_ostream &O) {
270 const MCOperand &Op = MI->getOperand(i: OpNum);
271
272 // If the label has already been resolved to an immediate offset (say, when
273 // we're running the disassembler), just print the immediate.
274 if (Op.isImm()) {
275 int64_t Offset = Op.getImm();
276 if (PrintBranchImmAsAddress) {
277 uint64_t Target = Address + Offset;
278 if (STI.getTargetTriple().isSPARC32())
279 Target &= 0xffffffff;
280 O << formatHex(Value: Target);
281 } else {
282 O << ".";
283 if (Offset >= 0)
284 O << "+";
285 O << Offset;
286 }
287 return;
288 }
289
290 // Otherwise, just print the expression.
291 MAI.printExpr(O, *Op.getExpr());
292}
293