1//===---------- AArch64CollectLOH.cpp - AArch64 collect LOH pass --*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that collect the Linker Optimization Hint (LOH).
10// This pass should be run at the very end of the compilation flow, just before
11// assembly printer.
12// To be useful for the linker, the LOH must be printed into the assembly file.
13//
14// A LOH describes a sequence of instructions that may be optimized by the
15// linker.
16// This same sequence cannot be optimized by the compiler because some of
17// the information will be known at link time.
18// For instance, consider the following sequence:
19// L1: adrp xA, sym@PAGE
20// L2: add xB, xA, sym@PAGEOFF
21// L3: ldr xC, [xB, #imm]
22// This sequence can be turned into:
23// A literal load if sym@PAGE + sym@PAGEOFF + #imm - address(L3) is < 1MB:
24// L3: ldr xC, sym+#imm
25// It may also be turned into either the following more efficient
26// code sequences:
27// - If sym@PAGEOFF + #imm fits the encoding space of L3.
28// L1: adrp xA, sym@PAGE
29// L3: ldr xC, [xB, sym@PAGEOFF + #imm]
30// - If sym@PAGE + sym@PAGEOFF - address(L1) < 1MB:
31// L1: adr xA, sym
32// L3: ldr xC, [xB, #imm]
33//
34// To be valid a LOH must meet all the requirements needed by all the related
35// possible linker transformations.
36// For instance, using the running example, the constraints to emit
37// ".loh AdrpAddLdr" are:
38// - L1, L2, and L3 instructions are of the expected type, i.e.,
39// respectively ADRP, ADD (immediate), and LD.
40// - The result of L1 is used only by L2.
41// - The register argument (xA) used in the ADD instruction is defined
42// only by L1.
43// - The result of L2 is used only by L3.
44// - The base address (xB) in L3 is defined only L2.
45// - The ADRP in L1 and the ADD in L2 must reference the same symbol using
46// @PAGE/@PAGEOFF with no additional constants
47//
48// Currently supported LOHs are:
49// * So called non-ADRP-related:
50// - .loh AdrpAddLdr L1, L2, L3:
51// L1: adrp xA, sym@PAGE
52// L2: add xB, xA, sym@PAGEOFF
53// L3: ldr xC, [xB, #imm]
54// - .loh AdrpLdrGotLdr L1, L2, L3:
55// L1: adrp xA, sym@GOTPAGE
56// L2: ldr xB, [xA, sym@GOTPAGEOFF]
57// L3: ldr xC, [xB, #imm]
58// - .loh AdrpLdr L1, L3:
59// L1: adrp xA, sym@PAGE
60// L3: ldr xC, [xA, sym@PAGEOFF]
61// - .loh AdrpAddStr L1, L2, L3:
62// L1: adrp xA, sym@PAGE
63// L2: add xB, xA, sym@PAGEOFF
64// L3: str xC, [xB, #imm]
65// - .loh AdrpLdrGotStr L1, L2, L3:
66// L1: adrp xA, sym@GOTPAGE
67// L2: ldr xB, [xA, sym@GOTPAGEOFF]
68// L3: str xC, [xB, #imm]
69// - .loh AdrpAdd L1, L2:
70// L1: adrp xA, sym@PAGE
71// L2: add xB, xA, sym@PAGEOFF
72// For all these LOHs, L1, L2, L3 form a simple chain:
73// L1 result is used only by L2 and L2 result by L3.
74// L3 LOH-related argument is defined only by L2 and L2 LOH-related argument
75// by L1.
76// All these LOHs aim at using more efficient load/store patterns by folding
77// some instructions used to compute the address directly into the load/store.
78//
79// * So called ADRP-related:
80// - .loh AdrpAdrp L2, L1:
81// L2: ADRP xA, sym1@PAGE
82// L1: ADRP xA, sym2@PAGE
83// L2 dominates L1 and xA is not redefined between L2 and L1
84// This LOH aims at getting rid of redundant ADRP instructions.
85//
86// The overall design for emitting the LOHs is:
87// 1. AArch64CollectLOH (this pass) records the LOHs in the AArch64FunctionInfo.
88// 2. AArch64AsmPrinter reads the LOHs from AArch64FunctionInfo and it:
89// 1. Associates them a label.
90// 2. Emits them in a MCStreamer (EmitLOHDirective).
91// - The MCMachOStreamer records them into the MCAssembler.
92// - The MCAsmStreamer prints them.
93// - Other MCStreamers ignore them.
94// 3. Closes the MCStreamer:
95// - The MachObjectWriter gets them from the MCAssembler and writes
96// them in the object file.
97// - Other ObjectWriters ignore them.
98//===----------------------------------------------------------------------===//
99
100#include "AArch64.h"
101#include "AArch64MachineFunctionInfo.h"
102#include "llvm/ADT/SmallSet.h"
103#include "llvm/ADT/Statistic.h"
104#include "llvm/CodeGen/MachineBasicBlock.h"
105#include "llvm/CodeGen/MachineFunctionPass.h"
106#include "llvm/CodeGen/MachineInstr.h"
107#include "llvm/CodeGen/TargetRegisterInfo.h"
108#include "llvm/Support/Debug.h"
109#include "llvm/Support/ErrorHandling.h"
110#include "llvm/Support/raw_ostream.h"
111using namespace llvm;
112
113#define DEBUG_TYPE "aarch64-collect-loh"
114
115STATISTIC(NumADRPSimpleCandidate,
116 "Number of simplifiable ADRP dominate by another");
117STATISTIC(NumADDToSTR, "Number of simplifiable STR reachable by ADD");
118STATISTIC(NumLDRToSTR, "Number of simplifiable STR reachable by LDR");
119STATISTIC(NumADDToLDR, "Number of simplifiable LDR reachable by ADD");
120STATISTIC(NumLDRToLDR, "Number of simplifiable LDR reachable by LDR");
121STATISTIC(NumADRPToLDR, "Number of simplifiable LDR reachable by ADRP");
122STATISTIC(NumADRSimpleCandidate, "Number of simplifiable ADRP + ADD");
123
124#define AARCH64_COLLECT_LOH_NAME "AArch64 Collect Linker Optimization Hint (LOH)"
125
126static bool canAddBePartOfLOH(const MachineInstr &MI) {
127 // Check immediate to see if the immediate is an address.
128 switch (MI.getOperand(i: 2).getType()) {
129 default:
130 return false;
131 case MachineOperand::MO_GlobalAddress:
132 case MachineOperand::MO_JumpTableIndex:
133 case MachineOperand::MO_ConstantPoolIndex:
134 case MachineOperand::MO_BlockAddress:
135 return true;
136 }
137}
138
139/// Answer the following question: Can Def be one of the definition
140/// involved in a part of a LOH?
141static bool canDefBePartOfLOH(const MachineInstr &MI) {
142 // Accept ADRP, ADDLow and LOADGot.
143 switch (MI.getOpcode()) {
144 default:
145 return false;
146 case AArch64::ADRP:
147 return true;
148 case AArch64::ADDXri:
149 return canAddBePartOfLOH(MI);
150 case AArch64::LDRXui:
151 case AArch64::LDRWui:
152 // Check immediate to see if the immediate is an address.
153 switch (MI.getOperand(i: 2).getType()) {
154 default:
155 return false;
156 case MachineOperand::MO_GlobalAddress:
157 return MI.getOperand(i: 2).getTargetFlags() & AArch64II::MO_GOT;
158 }
159 }
160}
161
162/// Check whether the given instruction can the end of a LOH chain involving a
163/// store.
164static bool isCandidateStore(const MachineInstr &MI, const MachineOperand &MO) {
165 switch (MI.getOpcode()) {
166 default:
167 return false;
168 case AArch64::STRBBui:
169 case AArch64::STRHHui:
170 case AArch64::STRBui:
171 case AArch64::STRHui:
172 case AArch64::STRWui:
173 case AArch64::STRXui:
174 case AArch64::STRSui:
175 case AArch64::STRDui:
176 case AArch64::STRQui:
177 // We can only optimize the index operand.
178 // In case we have str xA, [xA, #imm], this is two different uses
179 // of xA and we cannot fold, otherwise the xA stored may be wrong,
180 // even if #imm == 0.
181 return MO.getOperandNo() == 1 &&
182 MI.getOperand(i: 0).getReg() != MI.getOperand(i: 1).getReg();
183 }
184}
185
186/// Check whether the given instruction can be the end of a LOH chain
187/// involving a load.
188static bool isCandidateLoad(const MachineInstr &MI) {
189 switch (MI.getOpcode()) {
190 default:
191 return false;
192 case AArch64::LDRSBWui:
193 case AArch64::LDRSBXui:
194 case AArch64::LDRSHWui:
195 case AArch64::LDRSHXui:
196 case AArch64::LDRSWui:
197 case AArch64::LDRBui:
198 case AArch64::LDRHui:
199 case AArch64::LDRWui:
200 case AArch64::LDRXui:
201 case AArch64::LDRSui:
202 case AArch64::LDRDui:
203 case AArch64::LDRQui:
204 return !(MI.getOperand(i: 2).getTargetFlags() & AArch64II::MO_GOT);
205 }
206}
207
208/// Check whether the given instruction can load a literal.
209static bool supportLoadFromLiteral(const MachineInstr &MI) {
210 switch (MI.getOpcode()) {
211 default:
212 return false;
213 case AArch64::LDRSWui:
214 case AArch64::LDRWui:
215 case AArch64::LDRXui:
216 case AArch64::LDRSui:
217 case AArch64::LDRDui:
218 case AArch64::LDRQui:
219 return true;
220 }
221}
222
223/// Returns \p true if there are no non-debug instructions between \p First and
224/// \p Second
225static bool areInstructionsConsecutive(const MachineInstr *First,
226 const MachineInstr *Second) {
227 auto It = First->getIterator();
228 auto EndIt = First->getParent()->instr_end();
229 if (It == EndIt)
230 return false;
231 return next_nodbg(It, End: EndIt) == Second->getIterator();
232}
233
234/// Number of GPR registers tracked by mapRegToGPRIndex()
235static const unsigned N_GPR_REGS = 31;
236/// Map register number to index from 0-30.
237static int mapRegToGPRIndex(MCRegister Reg) {
238 static_assert(AArch64::X28 - AArch64::X0 + 3 == N_GPR_REGS, "Number of GPRs");
239 static_assert(AArch64::W30 - AArch64::W0 + 1 == N_GPR_REGS, "Number of GPRs");
240 if (AArch64::X0 <= Reg && Reg <= AArch64::X28)
241 return Reg - AArch64::X0;
242 if (AArch64::W0 <= Reg && Reg <= AArch64::W30)
243 return Reg - AArch64::W0;
244 // TableGen gives "FP" and "LR" an index not adjacent to X28 so we have to
245 // handle them as special cases.
246 if (Reg == AArch64::FP)
247 return 29;
248 if (Reg == AArch64::LR)
249 return 30;
250 return -1;
251}
252
253/// State tracked per register.
254/// The main algorithm walks backwards over a basic block maintaining this
255/// datastructure for each tracked general purpose register.
256struct LOHInfo {
257 MCLOHType Type : 8; ///< "Best" type of LOH possible.
258 LLVM_PREFERRED_TYPE(bool)
259 unsigned IsCandidate : 1; ///< Possible LOH candidate.
260 LLVM_PREFERRED_TYPE(bool)
261 unsigned OneUser : 1; ///< Found exactly one user (yet).
262 LLVM_PREFERRED_TYPE(bool)
263 unsigned MultiUsers : 1; ///< Found multiple users.
264 const MachineInstr *MI0; ///< First instruction involved in the LOH.
265 const MachineInstr *MI1; ///< Second instruction involved in the LOH
266 /// (if any).
267 const MachineInstr *LastADRP; ///< Last ADRP in same register.
268};
269
270/// Update state \p Info given \p MI uses the tracked register.
271static void handleUse(const MachineInstr &MI, const MachineOperand &MO,
272 LOHInfo &Info) {
273 // We have multiple uses if we already found one before.
274 if (Info.MultiUsers || Info.OneUser) {
275 Info.IsCandidate = false;
276 Info.MultiUsers = true;
277 return;
278 }
279 Info.OneUser = true;
280
281 // Start new LOHInfo if applicable.
282 if (isCandidateLoad(MI)) {
283 Info.Type = MCLOH_AdrpLdr;
284 Info.IsCandidate = true;
285 Info.MI0 = &MI;
286 // Note that even this is AdrpLdr now, we can switch to a Ldr variant
287 // later.
288 } else if (isCandidateStore(MI, MO)) {
289 Info.Type = MCLOH_AdrpAddStr;
290 Info.IsCandidate = true;
291 Info.MI0 = &MI;
292 Info.MI1 = nullptr;
293 } else if (MI.getOpcode() == AArch64::ADDXri) {
294 Info.Type = MCLOH_AdrpAdd;
295 Info.IsCandidate = true;
296 Info.MI0 = &MI;
297 } else if ((MI.getOpcode() == AArch64::LDRXui ||
298 MI.getOpcode() == AArch64::LDRWui) &&
299 MI.getOperand(i: 2).getTargetFlags() & AArch64II::MO_GOT) {
300 Info.Type = MCLOH_AdrpLdrGot;
301 Info.IsCandidate = true;
302 Info.MI0 = &MI;
303 }
304}
305
306/// Update state \p Info given the tracked register is clobbered.
307static void handleClobber(LOHInfo &Info) {
308 Info.IsCandidate = false;
309 Info.OneUser = false;
310 Info.MultiUsers = false;
311 Info.LastADRP = nullptr;
312}
313
314/// Update state \p Info given that \p MI is possibly the middle instruction
315/// of an LOH involving 3 instructions.
316static bool handleMiddleInst(const MachineInstr &MI, LOHInfo &DefInfo,
317 LOHInfo &OpInfo) {
318 if (!DefInfo.IsCandidate || (&DefInfo != &OpInfo && OpInfo.OneUser))
319 return false;
320 // Copy LOHInfo for dest register to LOHInfo for source register.
321 if (&DefInfo != &OpInfo) {
322 OpInfo = DefInfo;
323 // Invalidate \p DefInfo because we track it in \p OpInfo now.
324 handleClobber(Info&: DefInfo);
325 } else
326 DefInfo.LastADRP = nullptr;
327
328 // Advance state machine.
329 assert(OpInfo.IsCandidate && "Expect valid state");
330 if (MI.getOpcode() == AArch64::ADDXri && canAddBePartOfLOH(MI)) {
331 if (OpInfo.Type == MCLOH_AdrpLdr) {
332 OpInfo.Type = MCLOH_AdrpAddLdr;
333 OpInfo.IsCandidate = true;
334 OpInfo.MI1 = &MI;
335 return true;
336 } else if (OpInfo.Type == MCLOH_AdrpAddStr && OpInfo.MI1 == nullptr) {
337 OpInfo.Type = MCLOH_AdrpAddStr;
338 OpInfo.IsCandidate = true;
339 OpInfo.MI1 = &MI;
340 return true;
341 }
342 } else {
343 assert((MI.getOpcode() == AArch64::LDRXui ||
344 MI.getOpcode() == AArch64::LDRWui) &&
345 "Expect LDRXui or LDRWui");
346 assert((MI.getOperand(2).getTargetFlags() & AArch64II::MO_GOT) &&
347 "Expected GOT relocation");
348 if (OpInfo.Type == MCLOH_AdrpAddStr && OpInfo.MI1 == nullptr) {
349 OpInfo.Type = MCLOH_AdrpLdrGotStr;
350 OpInfo.IsCandidate = true;
351 OpInfo.MI1 = &MI;
352 return true;
353 } else if (OpInfo.Type == MCLOH_AdrpLdr) {
354 OpInfo.Type = MCLOH_AdrpLdrGotLdr;
355 OpInfo.IsCandidate = true;
356 OpInfo.MI1 = &MI;
357 return true;
358 }
359 }
360 return false;
361}
362
363/// Update state when seeing and ADRP instruction.
364static void handleADRP(const MachineInstr &MI, AArch64FunctionInfo &AFI,
365 LOHInfo &Info, LOHInfo *LOHInfos) {
366 if (Info.LastADRP != nullptr) {
367 LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpAdrp:\n"
368 << '\t' << MI << '\t' << *Info.LastADRP);
369 AFI.addLOHDirective(Kind: MCLOH_AdrpAdrp, Args: {&MI, Info.LastADRP});
370 ++NumADRPSimpleCandidate;
371 }
372
373 // Produce LOH directive if possible.
374 if (Info.IsCandidate) {
375 switch (Info.Type) {
376 case MCLOH_AdrpAdd: {
377 // ADRPs and ADDs for this candidate may be split apart if using
378 // GlobalISel instead of pseudo-expanded. If that happens, the
379 // def register of the ADD may have a use in between. Adding an LOH in
380 // this case can cause the linker to rewrite the ADRP to write to that
381 // register, clobbering the use.
382 const MachineInstr *AddMI = Info.MI0;
383 int DefIdx = mapRegToGPRIndex(Reg: MI.getOperand(i: 0).getReg());
384 int OpIdx = mapRegToGPRIndex(Reg: AddMI->getOperand(i: 0).getReg());
385 LOHInfo DefInfo = LOHInfos[OpIdx];
386 if (DefIdx != OpIdx && (DefInfo.OneUser || DefInfo.MultiUsers))
387 break;
388 LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpAdd:\n"
389 << '\t' << MI << '\t' << *Info.MI0);
390 AFI.addLOHDirective(Kind: MCLOH_AdrpAdd, Args: {&MI, Info.MI0});
391 ++NumADRSimpleCandidate;
392 break;
393 }
394 case MCLOH_AdrpLdr:
395 if (supportLoadFromLiteral(MI: *Info.MI0)) {
396 LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpLdr:\n"
397 << '\t' << MI << '\t' << *Info.MI0);
398 AFI.addLOHDirective(Kind: MCLOH_AdrpLdr, Args: {&MI, Info.MI0});
399 ++NumADRPToLDR;
400 }
401 break;
402 case MCLOH_AdrpAddLdr:
403 // There is a possibility that the linker may try to rewrite:
404 // adrp x0, @sym@PAGE
405 // add x1, x0, @sym@PAGEOFF
406 // [x0 = some other def]
407 // ldr x2, [x1]
408 // ...into...
409 // adrp x0, @sym
410 // nop
411 // [x0 = some other def]
412 // ldr x2, [x0]
413 // ...if the offset to the symbol won't fit within a literal load.
414 // This causes the load to use the result of the adrp, which in this
415 // case has already been clobbered.
416 // FIXME: Implement proper liveness tracking for all registers. For now,
417 // don't emit the LOH if there are any instructions between the add and
418 // the ldr.
419 if (!areInstructionsConsecutive(First: Info.MI1, Second: Info.MI0))
420 break;
421 LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpAddLdr:\n"
422 << '\t' << MI << '\t' << *Info.MI1 << '\t'
423 << *Info.MI0);
424 AFI.addLOHDirective(Kind: MCLOH_AdrpAddLdr, Args: {&MI, Info.MI1, Info.MI0});
425 ++NumADDToLDR;
426 break;
427 case MCLOH_AdrpAddStr:
428 if (!Info.MI1)
429 break;
430 if (!areInstructionsConsecutive(First: Info.MI1, Second: Info.MI0))
431 break;
432 LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpAddStr:\n"
433 << '\t' << MI << '\t' << *Info.MI1 << '\t'
434 << *Info.MI0);
435 AFI.addLOHDirective(Kind: MCLOH_AdrpAddStr, Args: {&MI, Info.MI1, Info.MI0});
436 ++NumADDToSTR;
437 break;
438 case MCLOH_AdrpLdrGotLdr:
439 LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGotLdr:\n"
440 << '\t' << MI << '\t' << *Info.MI1 << '\t'
441 << *Info.MI0);
442 AFI.addLOHDirective(Kind: MCLOH_AdrpLdrGotLdr, Args: {&MI, Info.MI1, Info.MI0});
443 ++NumLDRToLDR;
444 break;
445 case MCLOH_AdrpLdrGotStr:
446 LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGotStr:\n"
447 << '\t' << MI << '\t' << *Info.MI1 << '\t'
448 << *Info.MI0);
449 AFI.addLOHDirective(Kind: MCLOH_AdrpLdrGotStr, Args: {&MI, Info.MI1, Info.MI0});
450 ++NumLDRToSTR;
451 break;
452 case MCLOH_AdrpLdrGot:
453 LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGot:\n"
454 << '\t' << MI << '\t' << *Info.MI0);
455 AFI.addLOHDirective(Kind: MCLOH_AdrpLdrGot, Args: {&MI, Info.MI0});
456 break;
457 case MCLOH_AdrpAdrp:
458 llvm_unreachable("MCLOH_AdrpAdrp not used in state machine");
459 }
460 }
461
462 handleClobber(Info);
463 Info.LastADRP = &MI;
464}
465
466static void handleRegMaskClobber(const uint32_t *RegMask, MCPhysReg Reg,
467 LOHInfo *LOHInfos) {
468 if (!MachineOperand::clobbersPhysReg(RegMask, PhysReg: Reg))
469 return;
470 int Idx = mapRegToGPRIndex(Reg);
471 if (Idx >= 0)
472 handleClobber(Info&: LOHInfos[Idx]);
473}
474
475static void handleNormalInst(const MachineInstr &MI, LOHInfo *LOHInfos) {
476 // Handle defs and regmasks.
477 for (const MachineOperand &MO : MI.operands()) {
478 if (MO.isRegMask()) {
479 const uint32_t *RegMask = MO.getRegMask();
480 for (MCPhysReg Reg : AArch64::GPR32RegClass)
481 handleRegMaskClobber(RegMask, Reg, LOHInfos);
482 for (MCPhysReg Reg : AArch64::GPR64RegClass)
483 handleRegMaskClobber(RegMask, Reg, LOHInfos);
484 continue;
485 }
486 if (!MO.isReg() || !MO.isDef())
487 continue;
488 int Idx = mapRegToGPRIndex(Reg: MO.getReg());
489 if (Idx < 0)
490 continue;
491 handleClobber(Info&: LOHInfos[Idx]);
492 }
493 // Handle uses.
494
495 SmallSet<int, 4> UsesSeen;
496 for (const MachineOperand &MO : MI.uses()) {
497 if (!MO.isReg() || !MO.readsReg())
498 continue;
499 int Idx = mapRegToGPRIndex(Reg: MO.getReg());
500 if (Idx < 0)
501 continue;
502
503 // Multiple uses of the same register within a single instruction don't
504 // count as MultiUser or block optimization. This is especially important on
505 // arm64_32, where any memory operation is likely to be an explicit use of
506 // xN and an implicit use of wN (the base address register).
507 if (UsesSeen.insert(V: Idx).second)
508 handleUse(MI, MO, Info&: LOHInfos[Idx]);
509 }
510}
511
512namespace {
513
514void runAArch64CollectLOH(MachineFunction &MF) {
515 LLVM_DEBUG(dbgs() << "********** AArch64 Collect LOH **********\n"
516 << "Looking in function " << MF.getName() << '\n');
517
518 LOHInfo LOHInfos[N_GPR_REGS];
519 AArch64FunctionInfo &AFI = *MF.getInfo<AArch64FunctionInfo>();
520 for (const MachineBasicBlock &MBB : MF) {
521 // Reset register tracking state.
522 memset(s: LOHInfos, c: 0, n: sizeof(LOHInfos));
523 // Live-out registers are used.
524 for (const MachineBasicBlock *Succ : MBB.successors()) {
525 for (const auto &LI : Succ->liveins()) {
526 int RegIdx = mapRegToGPRIndex(Reg: LI.PhysReg);
527 if (RegIdx >= 0)
528 LOHInfos[RegIdx].OneUser = true;
529 }
530 }
531
532 // Walk the basic block backwards and update the per register state machine
533 // in the process.
534 for (const MachineInstr &MI :
535 instructionsWithoutDebug(It: MBB.instr_rbegin(), End: MBB.instr_rend())) {
536 unsigned Opcode = MI.getOpcode();
537 switch (Opcode) {
538 case AArch64::ADDXri:
539 case AArch64::LDRXui:
540 case AArch64::LDRWui:
541 if (canDefBePartOfLOH(MI)) {
542 const MachineOperand &Def = MI.getOperand(i: 0);
543 const MachineOperand &Op = MI.getOperand(i: 1);
544 assert(Def.isReg() && Def.isDef() && "Expected reg def");
545 assert(Op.isReg() && Op.isUse() && "Expected reg use");
546 int DefIdx = mapRegToGPRIndex(Reg: Def.getReg());
547 int OpIdx = mapRegToGPRIndex(Reg: Op.getReg());
548 if (DefIdx >= 0 && OpIdx >= 0 &&
549 handleMiddleInst(MI, DefInfo&: LOHInfos[DefIdx], OpInfo&: LOHInfos[OpIdx]))
550 continue;
551 }
552 break;
553 case AArch64::ADRP:
554 const MachineOperand &Op0 = MI.getOperand(i: 0);
555 int Idx = mapRegToGPRIndex(Reg: Op0.getReg());
556 if (Idx >= 0) {
557 handleADRP(MI, AFI, Info&: LOHInfos[Idx], LOHInfos);
558 continue;
559 }
560 break;
561 }
562 handleNormalInst(MI, LOHInfos);
563 }
564 }
565}
566
567struct AArch64CollectLOHLegacy : public MachineFunctionPass {
568 static char ID;
569 AArch64CollectLOHLegacy() : MachineFunctionPass(ID) {}
570
571 bool runOnMachineFunction(MachineFunction &MF) override {
572 if (skipFunction(F: MF.getFunction()))
573 return false;
574 runAArch64CollectLOH(MF);
575
576 // Return "no change": The pass only collects information.
577 return false;
578 }
579
580 MachineFunctionProperties getRequiredProperties() const override {
581 return MachineFunctionProperties().setNoVRegs();
582 }
583
584 StringRef getPassName() const override { return AARCH64_COLLECT_LOH_NAME; }
585
586 void getAnalysisUsage(AnalysisUsage &AU) const override {
587 MachineFunctionPass::getAnalysisUsage(AU);
588 AU.setPreservesAll();
589 }
590};
591
592char AArch64CollectLOHLegacy::ID = 0;
593
594} // end anonymous namespace.
595
596INITIALIZE_PASS(AArch64CollectLOHLegacy, "aarch64-collect-loh",
597 AARCH64_COLLECT_LOH_NAME, false, false)
598
599PreservedAnalyses
600AArch64CollectLOHPass::run(MachineFunction &MF,
601 MachineFunctionAnalysisManager &MFAM) {
602 runAArch64CollectLOH(MF);
603
604 // This pass only collects information.
605 return PreservedAnalyses::all();
606}
607
608FunctionPass *llvm::createAArch64CollectLOHPass() {
609 return new AArch64CollectLOHLegacy();
610}
611