1//==-- AArch64DeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file When allowed by the instruction, replace a dead definition of a GPR
9/// with the zero register. This makes the code a bit friendlier towards the
10/// hardware's register renamer.
11//===----------------------------------------------------------------------===//
12
13#include "AArch64.h"
14#include "AArch64RegisterInfo.h"
15#include "AArch64Subtarget.h"
16#include "llvm/ADT/Statistic.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineFunctionPass.h"
19#include "llvm/CodeGen/MachineInstr.h"
20#include "llvm/CodeGen/MachineRegisterInfo.h"
21#include "llvm/CodeGen/TargetInstrInfo.h"
22#include "llvm/CodeGen/TargetSubtargetInfo.h"
23#include "llvm/Support/Debug.h"
24#include "llvm/Support/raw_ostream.h"
25using namespace llvm;
26
27#define DEBUG_TYPE "aarch64-dead-defs"
28
29STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
30
31#define AARCH64_DEAD_REG_DEF_NAME "AArch64 Dead register definitions"
32
33namespace {
34class AArch64DeadRegisterDefinitionsImpl {
35public:
36 bool run(MachineFunction &MF);
37
38private:
39 const TargetRegisterInfo *TRI;
40 const MachineRegisterInfo *MRI;
41 const TargetInstrInfo *TII;
42 bool Changed;
43 void processMachineBasicBlock(MachineBasicBlock &MBB);
44};
45
46class AArch64DeadRegisterDefinitionsLegacy : public MachineFunctionPass {
47public:
48 static char ID; // Pass identification, replacement for typeid.
49 AArch64DeadRegisterDefinitionsLegacy() : MachineFunctionPass(ID) {}
50
51 bool runOnMachineFunction(MachineFunction &F) override;
52
53 StringRef getPassName() const override { return AARCH64_DEAD_REG_DEF_NAME; }
54
55 void getAnalysisUsage(AnalysisUsage &AU) const override {
56 AU.setPreservesCFG();
57 MachineFunctionPass::getAnalysisUsage(AU);
58 }
59};
60char AArch64DeadRegisterDefinitionsLegacy::ID = 0;
61} // end anonymous namespace
62
63INITIALIZE_PASS(AArch64DeadRegisterDefinitionsLegacy, "aarch64-dead-defs",
64 AARCH64_DEAD_REG_DEF_NAME, false, false)
65
66static bool usesFrameIndex(const MachineInstr &MI) {
67 for (const MachineOperand &MO : MI.uses())
68 if (MO.isFI())
69 return true;
70 return false;
71}
72
73// Instructions that lose their 'read' operation for a subsequent fence acquire
74// (DMB LD) once the zero register is used.
75//
76// WARNING: The acquire variants of the instructions are also affected, but they
77// are split out into `atomicBarrierDroppedOnZero()` to support annotations on
78// assembly.
79static bool atomicReadDroppedOnZero(unsigned Opcode) {
80 switch (Opcode) {
81 case AArch64::LDADDB: case AArch64::LDADDH:
82 case AArch64::LDADDW: case AArch64::LDADDX:
83 case AArch64::LDADDLB: case AArch64::LDADDLH:
84 case AArch64::LDADDLW: case AArch64::LDADDLX:
85 case AArch64::LDCLRB: case AArch64::LDCLRH:
86 case AArch64::LDCLRW: case AArch64::LDCLRX:
87 case AArch64::LDCLRLB: case AArch64::LDCLRLH:
88 case AArch64::LDCLRLW: case AArch64::LDCLRLX:
89 case AArch64::LDEORB: case AArch64::LDEORH:
90 case AArch64::LDEORW: case AArch64::LDEORX:
91 case AArch64::LDEORLB: case AArch64::LDEORLH:
92 case AArch64::LDEORLW: case AArch64::LDEORLX:
93 case AArch64::LDSETB: case AArch64::LDSETH:
94 case AArch64::LDSETW: case AArch64::LDSETX:
95 case AArch64::LDSETLB: case AArch64::LDSETLH:
96 case AArch64::LDSETLW: case AArch64::LDSETLX:
97 case AArch64::LDSMAXB: case AArch64::LDSMAXH:
98 case AArch64::LDSMAXW: case AArch64::LDSMAXX:
99 case AArch64::LDSMAXLB: case AArch64::LDSMAXLH:
100 case AArch64::LDSMAXLW: case AArch64::LDSMAXLX:
101 case AArch64::LDSMINB: case AArch64::LDSMINH:
102 case AArch64::LDSMINW: case AArch64::LDSMINX:
103 case AArch64::LDSMINLB: case AArch64::LDSMINLH:
104 case AArch64::LDSMINLW: case AArch64::LDSMINLX:
105 case AArch64::LDUMAXB: case AArch64::LDUMAXH:
106 case AArch64::LDUMAXW: case AArch64::LDUMAXX:
107 case AArch64::LDUMAXLB: case AArch64::LDUMAXLH:
108 case AArch64::LDUMAXLW: case AArch64::LDUMAXLX:
109 case AArch64::LDUMINB: case AArch64::LDUMINH:
110 case AArch64::LDUMINW: case AArch64::LDUMINX:
111 case AArch64::LDUMINLB: case AArch64::LDUMINLH:
112 case AArch64::LDUMINLW: case AArch64::LDUMINLX:
113 case AArch64::SWPB: case AArch64::SWPH:
114 case AArch64::SWPW: case AArch64::SWPX:
115 case AArch64::SWPLB: case AArch64::SWPLH:
116 case AArch64::SWPLW: case AArch64::SWPLX:
117 return true;
118 }
119 return false;
120}
121
122void AArch64DeadRegisterDefinitionsImpl::processMachineBasicBlock(
123 MachineBasicBlock &MBB) {
124 for (MachineInstr &MI : MBB) {
125 if (usesFrameIndex(MI)) {
126 // We need to skip this instruction because while it appears to have a
127 // dead def it uses a frame index which might expand into a multi
128 // instruction sequence during EPI.
129 LLVM_DEBUG(dbgs() << " Ignoring, operand is frame index\n");
130 continue;
131 }
132 if (MI.definesRegister(Reg: AArch64::XZR, /*TRI=*/nullptr) ||
133 MI.definesRegister(Reg: AArch64::WZR, /*TRI=*/nullptr)) {
134 // It is not allowed to write to the same register (not even the zero
135 // register) twice in a single instruction.
136 LLVM_DEBUG(
137 dbgs()
138 << " Ignoring, XZR or WZR already used by the instruction\n");
139 continue;
140 }
141
142 if (atomicBarrierDroppedOnZero(Opcode: MI.getOpcode()) || atomicReadDroppedOnZero(Opcode: MI.getOpcode())) {
143 LLVM_DEBUG(dbgs() << " Ignoring, semantics change with xzr/wzr.\n");
144 continue;
145 }
146
147 const MCInstrDesc &Desc = MI.getDesc();
148 for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) {
149 MachineOperand &MO = MI.getOperand(i: I);
150 if (!MO.isReg() || !MO.isDef())
151 continue;
152 // We should not have any relevant physreg defs that are replacable by
153 // zero before register allocation. So we just check for dead vreg defs.
154 Register Reg = MO.getReg();
155 if (!Reg.isVirtual() || (!MO.isDead() && !MRI->use_nodbg_empty(RegNo: Reg)))
156 continue;
157 assert(!MO.isImplicit() && "Unexpected implicit def!");
158 LLVM_DEBUG(dbgs() << " Dead def operand #" << I << " in:\n ";
159 MI.print(dbgs()));
160 // Be careful not to change the register if it's a tied operand.
161 if (MI.isRegTiedToUseOperand(DefOpIdx: I)) {
162 LLVM_DEBUG(dbgs() << " Ignoring, def is tied operand.\n");
163 continue;
164 }
165 const TargetRegisterClass *RC = TII->getRegClass(MCID: Desc, OpNum: I);
166 unsigned NewReg;
167 if (RC == nullptr) {
168 LLVM_DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
169 continue;
170 } else if (RC->contains(Reg: AArch64::WZR))
171 NewReg = AArch64::WZR;
172 else if (RC->contains(Reg: AArch64::XZR))
173 NewReg = AArch64::XZR;
174 else {
175 LLVM_DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
176 continue;
177 }
178 LLVM_DEBUG(dbgs() << " Replacing with zero register. New:\n ");
179 MO.setReg(NewReg);
180 MO.setIsDead();
181 LLVM_DEBUG(MI.print(dbgs()));
182 ++NumDeadDefsReplaced;
183 Changed = true;
184 // Only replace one dead register, see check for zero register above.
185 break;
186 }
187 }
188}
189
190// Scan the function for instructions that have a dead definition of a
191// register. Replace that register with the zero register when possible.
192bool AArch64DeadRegisterDefinitionsImpl::run(MachineFunction &MF) {
193 TRI = MF.getSubtarget().getRegisterInfo();
194 TII = MF.getSubtarget().getInstrInfo();
195 MRI = &MF.getRegInfo();
196 LLVM_DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n");
197 Changed = false;
198 for (auto &MBB : MF)
199 processMachineBasicBlock(MBB);
200 return Changed;
201}
202
203bool AArch64DeadRegisterDefinitionsLegacy::runOnMachineFunction(
204 MachineFunction &MF) {
205 if (skipFunction(F: MF.getFunction()))
206 return false;
207 return AArch64DeadRegisterDefinitionsImpl().run(MF);
208}
209
210PreservedAnalyses
211AArch64DeadRegisterDefinitionsPass::run(MachineFunction &MF,
212 MachineFunctionAnalysisManager &MFAM) {
213 const bool Changed = AArch64DeadRegisterDefinitionsImpl().run(MF);
214 if (!Changed)
215 return PreservedAnalyses::all();
216 PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
217 PA.preserveSet<CFGAnalyses>();
218 return PA;
219}
220
221FunctionPass *llvm::createAArch64DeadRegisterDefinitions() {
222 return new AArch64DeadRegisterDefinitionsLegacy();
223}
224