1//===-- AArch64SelectionDAGInfo.cpp - AArch64 SelectionDAG Info -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the AArch64SelectionDAGInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64SelectionDAGInfo.h"
14#include "AArch64MachineFunctionInfo.h"
15
16#define GET_SDNODE_DESC
17#include "AArch64GenSDNodeInfo.inc"
18#undef GET_SDNODE_DESC
19
20using namespace llvm;
21
22#define DEBUG_TYPE "aarch64-selectiondag-info"
23
24AArch64SelectionDAGInfo::AArch64SelectionDAGInfo()
25 : SelectionDAGGenTargetInfo(AArch64GenSDNodeInfo) {}
26
27void AArch64SelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG,
28 const SDNode *N) const {
29 switch (N->getOpcode()) {
30 case AArch64ISD::WrapperLarge:
31 // operand #0 must have type i32, but has type i64
32 return;
33 }
34
35 SelectionDAGGenTargetInfo::verifyTargetNode(DAG, N);
36
37#ifndef NDEBUG
38 // Some additional checks not yet implemented by verifyTargetNode.
39 switch (N->getOpcode()) {
40 case AArch64ISD::CTTZ_ELTS:
41 case AArch64ISD::CTTZ_ELTS_ZERO_POISON:
42 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() &&
43 "Expected the general-predicate and mask to have matching types");
44 break;
45 case AArch64ISD::SUNPKLO:
46 case AArch64ISD::SUNPKHI:
47 case AArch64ISD::UUNPKLO:
48 case AArch64ISD::UUNPKHI: {
49 EVT VT = N->getValueType(0);
50 EVT OpVT = N->getOperand(0).getValueType();
51 assert(OpVT.isVector() && VT.isVector() && OpVT.isInteger() &&
52 VT.isInteger() && "Expected integer vectors!");
53 assert(OpVT.getSizeInBits() == VT.getSizeInBits() &&
54 "Expected vectors of equal size!");
55 assert(OpVT.getVectorElementCount() == VT.getVectorElementCount() * 2 &&
56 "Expected result vector with half the lanes of its input!");
57 break;
58 }
59 case AArch64ISD::TRN1:
60 case AArch64ISD::TRN2:
61 case AArch64ISD::UZP1:
62 case AArch64ISD::UZP2:
63 case AArch64ISD::ZIP1:
64 case AArch64ISD::ZIP2: {
65 EVT VT = N->getValueType(0);
66 EVT Op0VT = N->getOperand(0).getValueType();
67 EVT Op1VT = N->getOperand(1).getValueType();
68 assert(VT.isVector() && Op0VT.isVector() && Op1VT.isVector() &&
69 "Expected vectors!");
70 assert(VT == Op0VT && VT == Op1VT && "Expected matching vectors!");
71 break;
72 }
73 case AArch64ISD::RSHRNB_I: {
74 EVT VT = N->getValueType(0);
75 EVT Op0VT = N->getOperand(0).getValueType();
76 assert(VT.isVector() && VT.isInteger() &&
77 "Expected integer vector result type!");
78 assert(Op0VT.isVector() && Op0VT.isInteger() &&
79 "Expected first operand to be an integer vector!");
80 assert(VT.getSizeInBits() == Op0VT.getSizeInBits() &&
81 "Expected vectors of equal size!");
82 assert(VT.getVectorElementCount() == Op0VT.getVectorElementCount() * 2 &&
83 "Expected input vector with half the lanes of its result!");
84 assert(isa<ConstantSDNode>(N->getOperand(1)) &&
85 "Expected second operand to be a constant!");
86 break;
87 }
88 }
89#endif
90}
91
92SDValue AArch64SelectionDAGInfo::EmitMOPS(unsigned Opcode, SelectionDAG &DAG,
93 const SDLoc &DL, SDValue Chain,
94 SDValue Dst, SDValue SrcOrValue,
95 SDValue Size, Align DstAlign,
96 Align SrcAlign, bool isVolatile,
97 MachinePointerInfo DstPtrInfo,
98 MachinePointerInfo SrcPtrInfo) const {
99
100 // Get the constant size of the copy/set.
101 LocationSize MemSize = LocationSize::afterPointer();
102 if (auto *C = dyn_cast<ConstantSDNode>(Val&: Size))
103 MemSize = LocationSize::precise(Value: C->getZExtValue());
104
105 const bool IsSet = Opcode == AArch64::MOPSMemorySetPseudo ||
106 Opcode == AArch64::MOPSMemorySetTaggingPseudo;
107
108 MachineFunction &MF = DAG.getMachineFunction();
109
110 auto Vol =
111 isVolatile ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone;
112 auto DstFlags = MachineMemOperand::MOStore | Vol;
113 auto *DstOp =
114 MF.getMachineMemOperand(PtrInfo: DstPtrInfo, F: DstFlags, Size: MemSize, BaseAlignment: DstAlign);
115
116 if (IsSet) {
117 // Extend value to i64, if required.
118 if (SrcOrValue.getValueType() != MVT::i64)
119 SrcOrValue = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: MVT::i64, Operand: SrcOrValue);
120 SDValue Ops[] = {Dst, Size, SrcOrValue, Chain};
121 const EVT ResultTys[] = {MVT::i64, MVT::i64, MVT::Other};
122 MachineSDNode *Node = DAG.getMachineNode(Opcode, dl: DL, ResultTys, Ops);
123 DAG.setNodeMemRefs(N: Node, NewMemRefs: {DstOp});
124 return SDValue(Node, 2);
125 } else {
126 SDValue Ops[] = {Dst, SrcOrValue, Size, Chain};
127 const EVT ResultTys[] = {MVT::i64, MVT::i64, MVT::i64, MVT::Other};
128 MachineSDNode *Node = DAG.getMachineNode(Opcode, dl: DL, ResultTys, Ops);
129
130 auto SrcFlags = MachineMemOperand::MOLoad | Vol;
131 auto *SrcOp =
132 MF.getMachineMemOperand(PtrInfo: SrcPtrInfo, F: SrcFlags, Size: MemSize, BaseAlignment: SrcAlign);
133 DAG.setNodeMemRefs(N: Node, NewMemRefs: {DstOp, SrcOp});
134 return SDValue(Node, 3);
135 }
136}
137
138SDValue AArch64SelectionDAGInfo::EmitStreamingCompatibleMemLibCall(
139 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op0, SDValue Op1,
140 SDValue Size, RTLIB::Libcall LC) const {
141 const AArch64Subtarget &STI =
142 DAG.getMachineFunction().getSubtarget<AArch64Subtarget>();
143 const AArch64TargetLowering *TLI = STI.getTargetLowering();
144 TargetLowering::ArgListTy Args;
145 Args.emplace_back(args&: Op0, args: PointerType::getUnqual(C&: *DAG.getContext()));
146
147 bool UsesResult = false;
148 RTLIB::Libcall NewLC;
149 switch (LC) {
150 case RTLIB::MEMCPY: {
151 NewLC = RTLIB::SC_MEMCPY;
152 Args.emplace_back(args&: Op1, args: PointerType::getUnqual(C&: *DAG.getContext()));
153 break;
154 }
155 case RTLIB::MEMMOVE: {
156 NewLC = RTLIB::SC_MEMMOVE;
157 Args.emplace_back(args&: Op1, args: PointerType::getUnqual(C&: *DAG.getContext()));
158 break;
159 }
160 case RTLIB::MEMSET: {
161 NewLC = RTLIB::SC_MEMSET;
162 Args.emplace_back(args: DAG.getZExtOrTrunc(Op: Op1, DL, VT: MVT::i32),
163 args: Type::getInt32Ty(C&: *DAG.getContext()));
164 break;
165 }
166 case RTLIB::MEMCHR: {
167 UsesResult = true;
168 NewLC = RTLIB::SC_MEMCHR;
169 Args.emplace_back(args: DAG.getZExtOrTrunc(Op: Op1, DL, VT: MVT::i32),
170 args: Type::getInt32Ty(C&: *DAG.getContext()));
171 break;
172 }
173 default:
174 return SDValue();
175 }
176
177 RTLIB::LibcallImpl NewLCImpl = DAG.getLibcalls().getLibcallImpl(Call: NewLC);
178 if (NewLCImpl == RTLIB::Unsupported)
179 return SDValue();
180
181 EVT PointerVT = TLI->getPointerTy(DL: DAG.getDataLayout());
182 SDValue Symbol = DAG.getExternalSymbol(LCImpl: NewLCImpl, VT: PointerVT);
183 Args.emplace_back(args&: Size, args: DAG.getDataLayout().getIntPtrType(C&: *DAG.getContext()));
184
185 TargetLowering::CallLoweringInfo CLI(DAG);
186 PointerType *RetTy = PointerType::getUnqual(C&: *DAG.getContext());
187 CLI.setDebugLoc(DL).setChain(Chain).setLibCallee(
188 CC: DAG.getLibcalls().getLibcallImplCallingConv(Call: NewLCImpl), ResultType: RetTy, Target: Symbol,
189 ArgsList: std::move(Args));
190
191 auto [Result, ChainOut] = TLI->LowerCallTo(CLI);
192 return UsesResult ? DAG.getMergeValues(Ops: {Result, ChainOut}, dl: DL) : ChainOut;
193}
194
195SDValue AArch64SelectionDAGInfo::EmitTargetCodeForMemcpy(
196 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src,
197 SDValue Size, Align DstAlign, Align SrcAlign, bool isVolatile,
198 bool AlwaysInline, MachinePointerInfo DstPtrInfo,
199 MachinePointerInfo SrcPtrInfo) const {
200 const AArch64Subtarget &STI =
201 DAG.getMachineFunction().getSubtarget<AArch64Subtarget>();
202
203 if (STI.getCLOpts().use_mops && STI.hasMOPS())
204 return EmitMOPS(Opcode: AArch64::MOPSMemoryCopyPseudo, DAG, DL, Chain, Dst, SrcOrValue: Src,
205 Size, DstAlign, SrcAlign, isVolatile, DstPtrInfo,
206 SrcPtrInfo);
207
208 auto *AFI = DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
209 SMEAttrs Attrs = AFI->getSMEFnAttrs();
210 if (STI.getCLOpts().lower_to_sme_routines &&
211 !Attrs.hasNonStreamingInterfaceAndBody())
212 return EmitStreamingCompatibleMemLibCall(DAG, DL, Chain, Op0: Dst, Op1: Src, Size,
213 LC: RTLIB::MEMCPY);
214 return SDValue();
215}
216
217SDValue AArch64SelectionDAGInfo::EmitTargetCodeForMemset(
218 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
219 SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
220 MachinePointerInfo DstPtrInfo) const {
221 const AArch64Subtarget &STI =
222 DAG.getMachineFunction().getSubtarget<AArch64Subtarget>();
223
224 if (STI.getCLOpts().use_mops && STI.hasMOPS())
225 return EmitMOPS(Opcode: AArch64::MOPSMemorySetPseudo, DAG, DL: dl, Chain, Dst, SrcOrValue: Src,
226 Size, DstAlign: Alignment, SrcAlign: Alignment, isVolatile, DstPtrInfo,
227 SrcPtrInfo: MachinePointerInfo{});
228
229 auto *AFI = DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
230 SMEAttrs Attrs = AFI->getSMEFnAttrs();
231 if (STI.getCLOpts().lower_to_sme_routines &&
232 !Attrs.hasNonStreamingInterfaceAndBody())
233 return EmitStreamingCompatibleMemLibCall(DAG, DL: dl, Chain, Op0: Dst, Op1: Src, Size,
234 LC: RTLIB::MEMSET);
235 return SDValue();
236}
237
238SDValue AArch64SelectionDAGInfo::EmitTargetCodeForMemmove(
239 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
240 SDValue Size, Align DstAlign, Align SrcAlign, bool isVolatile,
241 MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
242 const AArch64Subtarget &STI =
243 DAG.getMachineFunction().getSubtarget<AArch64Subtarget>();
244
245 if (STI.getCLOpts().use_mops && STI.hasMOPS())
246 return EmitMOPS(Opcode: AArch64::MOPSMemoryMovePseudo, DAG, DL: dl, Chain, Dst, SrcOrValue: Src,
247 Size, DstAlign, SrcAlign, isVolatile, DstPtrInfo,
248 SrcPtrInfo);
249
250 auto *AFI = DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
251 SMEAttrs Attrs = AFI->getSMEFnAttrs();
252 if (STI.getCLOpts().lower_to_sme_routines &&
253 !Attrs.hasNonStreamingInterfaceAndBody())
254 return EmitStreamingCompatibleMemLibCall(DAG, DL: dl, Chain, Op0: Dst, Op1: Src, Size,
255 LC: RTLIB::MEMMOVE);
256 return SDValue();
257}
258
259std::pair<SDValue, SDValue> AArch64SelectionDAGInfo::EmitTargetCodeForMemchr(
260 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Src,
261 SDValue Char, SDValue Length, MachinePointerInfo SrcPtrInfo) const {
262 auto *AFI = DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
263 SMEAttrs Attrs = AFI->getSMEFnAttrs();
264 if (DAG.getSubtarget<AArch64Subtarget>().getCLOpts().lower_to_sme_routines &&
265 !Attrs.hasNonStreamingInterfaceAndBody()) {
266 SDValue Result = EmitStreamingCompatibleMemLibCall(
267 DAG, DL: dl, Chain, Op0: Src, Op1: Char, Size: Length, LC: RTLIB::MEMCHR);
268 return std::make_pair(x: Result.getValue(R: 0), y: Result.getValue(R: 1));
269 }
270 return std::make_pair(x: SDValue(), y: SDValue());
271}
272
273static const int kSetTagLoopThreshold = 176;
274
275static SDValue EmitUnrolledSetTag(SelectionDAG &DAG, const SDLoc &dl,
276 SDValue Chain, SDValue Ptr, uint64_t ObjSize,
277 const MachineMemOperand *BaseMemOperand,
278 bool ZeroData) {
279 MachineFunction &MF = DAG.getMachineFunction();
280 unsigned ObjSizeScaled = ObjSize / 16;
281
282 SDValue TagSrc = Ptr;
283 if (Ptr.getOpcode() == ISD::FrameIndex) {
284 int FI = cast<FrameIndexSDNode>(Val&: Ptr)->getIndex();
285 Ptr = DAG.getTargetFrameIndex(FI, VT: MVT::i64);
286 // A frame index operand may end up as [SP + offset] => it is fine to use SP
287 // register as the tag source.
288 TagSrc = DAG.getRegister(Reg: AArch64::SP, VT: MVT::i64);
289 }
290
291 const unsigned OpCode1 = ZeroData ? AArch64ISD::STZG : AArch64ISD::STG;
292 const unsigned OpCode2 = ZeroData ? AArch64ISD::STZ2G : AArch64ISD::ST2G;
293
294 SmallVector<SDValue, 8> OutChains;
295 unsigned OffsetScaled = 0;
296 while (OffsetScaled < ObjSizeScaled) {
297 if (ObjSizeScaled - OffsetScaled >= 2) {
298 SDValue AddrNode = DAG.getMemBasePlusOffset(
299 Base: Ptr, Offset: TypeSize::getFixed(ExactSize: OffsetScaled * 16), DL: dl);
300 SDValue St = DAG.getMemIntrinsicNode(
301 Opcode: OpCode2, dl, VTList: DAG.getVTList(VT: MVT::Other),
302 Ops: {Chain, TagSrc, AddrNode},
303 MemVT: MVT::v4i64,
304 MMO: MF.getMachineMemOperand(MMO: BaseMemOperand, Offset: OffsetScaled * 16, Size: 16 * 2));
305 OffsetScaled += 2;
306 OutChains.push_back(Elt: St);
307 continue;
308 }
309
310 if (ObjSizeScaled - OffsetScaled > 0) {
311 SDValue AddrNode = DAG.getMemBasePlusOffset(
312 Base: Ptr, Offset: TypeSize::getFixed(ExactSize: OffsetScaled * 16), DL: dl);
313 SDValue St = DAG.getMemIntrinsicNode(
314 Opcode: OpCode1, dl, VTList: DAG.getVTList(VT: MVT::Other),
315 Ops: {Chain, TagSrc, AddrNode},
316 MemVT: MVT::v2i64,
317 MMO: MF.getMachineMemOperand(MMO: BaseMemOperand, Offset: OffsetScaled * 16, Size: 16));
318 OffsetScaled += 1;
319 OutChains.push_back(Elt: St);
320 }
321 }
322
323 SDValue Res = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: OutChains);
324 return Res;
325}
326
327SDValue AArch64SelectionDAGInfo::EmitTargetCodeForSetTag(
328 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Addr,
329 SDValue Size, MachinePointerInfo DstPtrInfo, bool ZeroData) const {
330 uint64_t ObjSize = Size->getAsZExtVal();
331 assert(ObjSize % 16 == 0);
332
333 MachineFunction &MF = DAG.getMachineFunction();
334 MachineMemOperand *BaseMemOperand = MF.getMachineMemOperand(
335 PtrInfo: DstPtrInfo, F: MachineMemOperand::MOStore, Size: ObjSize, BaseAlignment: Align(16));
336
337 bool UseSetTagRangeLoop =
338 kSetTagLoopThreshold >= 0 && (int)ObjSize >= kSetTagLoopThreshold;
339 if (!UseSetTagRangeLoop)
340 return EmitUnrolledSetTag(DAG, dl, Chain, Ptr: Addr, ObjSize, BaseMemOperand,
341 ZeroData);
342
343 const EVT ResTys[] = {MVT::i64, MVT::i64, MVT::Other};
344
345 unsigned Opcode;
346 if (Addr.getOpcode() == ISD::FrameIndex) {
347 int FI = cast<FrameIndexSDNode>(Val&: Addr)->getIndex();
348 Addr = DAG.getTargetFrameIndex(FI, VT: MVT::i64);
349 Opcode = ZeroData ? AArch64::STZGloop : AArch64::STGloop;
350 } else {
351 Opcode = ZeroData ? AArch64::STZGloop_wback : AArch64::STGloop_wback;
352 }
353 SDValue Ops[] = {DAG.getTargetConstant(Val: ObjSize, DL: dl, VT: MVT::i64), Addr, Chain};
354 SDNode *St = DAG.getMachineNode(Opcode, dl, ResultTys: ResTys, Ops);
355
356 DAG.setNodeMemRefs(N: cast<MachineSDNode>(Val: St), NewMemRefs: {BaseMemOperand});
357 return SDValue(St, 2);
358}
359