1//===-- AArch64SelectionDAGInfo.cpp - AArch64 SelectionDAG Info -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the AArch64SelectionDAGInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64SelectionDAGInfo.h"
14#include "AArch64MachineFunctionInfo.h"
15
16#define GET_SDNODE_DESC
17#include "AArch64GenSDNodeInfo.inc"
18#undef GET_SDNODE_DESC
19
20using namespace llvm;
21
22#define DEBUG_TYPE "aarch64-selectiondag-info"
23
24static cl::opt<bool>
25 LowerToSMERoutines("aarch64-lower-to-sme-routines", cl::Hidden,
26 cl::desc("Enable AArch64 SME memory operations "
27 "to lower to librt functions"),
28 cl::init(Val: true));
29
30static cl::opt<bool> UseMOPS("aarch64-use-mops", cl::Hidden,
31 cl::desc("Enable AArch64 MOPS instructions "
32 "for memcpy/memset/memmove"),
33 cl::init(Val: true));
34
35AArch64SelectionDAGInfo::AArch64SelectionDAGInfo()
36 : SelectionDAGGenTargetInfo(AArch64GenSDNodeInfo) {}
37
38void AArch64SelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG,
39 const SDNode *N) const {
40 switch (N->getOpcode()) {
41 case AArch64ISD::WrapperLarge:
42 // operand #0 must have type i32, but has type i64
43 return;
44 }
45
46 SelectionDAGGenTargetInfo::verifyTargetNode(DAG, N);
47
48#ifndef NDEBUG
49 // Some additional checks not yet implemented by verifyTargetNode.
50 switch (N->getOpcode()) {
51 case AArch64ISD::CTTZ_ELTS:
52 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() &&
53 "Expected the general-predicate and mask to have matching types");
54 break;
55 case AArch64ISD::SUNPKLO:
56 case AArch64ISD::SUNPKHI:
57 case AArch64ISD::UUNPKLO:
58 case AArch64ISD::UUNPKHI: {
59 EVT VT = N->getValueType(0);
60 EVT OpVT = N->getOperand(0).getValueType();
61 assert(OpVT.isVector() && VT.isVector() && OpVT.isInteger() &&
62 VT.isInteger() && "Expected integer vectors!");
63 assert(OpVT.getSizeInBits() == VT.getSizeInBits() &&
64 "Expected vectors of equal size!");
65 assert(OpVT.getVectorElementCount() == VT.getVectorElementCount() * 2 &&
66 "Expected result vector with half the lanes of its input!");
67 break;
68 }
69 case AArch64ISD::TRN1:
70 case AArch64ISD::TRN2:
71 case AArch64ISD::UZP1:
72 case AArch64ISD::UZP2:
73 case AArch64ISD::ZIP1:
74 case AArch64ISD::ZIP2: {
75 EVT VT = N->getValueType(0);
76 EVT Op0VT = N->getOperand(0).getValueType();
77 EVT Op1VT = N->getOperand(1).getValueType();
78 assert(VT.isVector() && Op0VT.isVector() && Op1VT.isVector() &&
79 "Expected vectors!");
80 assert(VT == Op0VT && VT == Op1VT && "Expected matching vectors!");
81 break;
82 }
83 case AArch64ISD::RSHRNB_I: {
84 EVT VT = N->getValueType(0);
85 EVT Op0VT = N->getOperand(0).getValueType();
86 assert(VT.isVector() && VT.isInteger() &&
87 "Expected integer vector result type!");
88 assert(Op0VT.isVector() && Op0VT.isInteger() &&
89 "Expected first operand to be an integer vector!");
90 assert(VT.getSizeInBits() == Op0VT.getSizeInBits() &&
91 "Expected vectors of equal size!");
92 assert(VT.getVectorElementCount() == Op0VT.getVectorElementCount() * 2 &&
93 "Expected input vector with half the lanes of its result!");
94 assert(isa<ConstantSDNode>(N->getOperand(1)) &&
95 "Expected second operand to be a constant!");
96 break;
97 }
98 }
99#endif
100}
101
102SDValue AArch64SelectionDAGInfo::EmitMOPS(unsigned Opcode, SelectionDAG &DAG,
103 const SDLoc &DL, SDValue Chain,
104 SDValue Dst, SDValue SrcOrValue,
105 SDValue Size, Align DstAlign,
106 Align SrcAlign, bool isVolatile,
107 MachinePointerInfo DstPtrInfo,
108 MachinePointerInfo SrcPtrInfo) const {
109
110 // Get the constant size of the copy/set.
111 LocationSize MemSize = LocationSize::afterPointer();
112 if (auto *C = dyn_cast<ConstantSDNode>(Val&: Size))
113 MemSize = LocationSize::precise(Value: C->getZExtValue());
114
115 const bool IsSet = Opcode == AArch64::MOPSMemorySetPseudo ||
116 Opcode == AArch64::MOPSMemorySetTaggingPseudo;
117
118 MachineFunction &MF = DAG.getMachineFunction();
119
120 auto Vol =
121 isVolatile ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone;
122 auto DstFlags = MachineMemOperand::MOStore | Vol;
123 auto *DstOp =
124 MF.getMachineMemOperand(PtrInfo: DstPtrInfo, F: DstFlags, Size: MemSize, BaseAlignment: DstAlign);
125
126 if (IsSet) {
127 // Extend value to i64, if required.
128 if (SrcOrValue.getValueType() != MVT::i64)
129 SrcOrValue = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: MVT::i64, Operand: SrcOrValue);
130 SDValue Ops[] = {Dst, Size, SrcOrValue, Chain};
131 const EVT ResultTys[] = {MVT::i64, MVT::i64, MVT::Other};
132 MachineSDNode *Node = DAG.getMachineNode(Opcode, dl: DL, ResultTys, Ops);
133 DAG.setNodeMemRefs(N: Node, NewMemRefs: {DstOp});
134 return SDValue(Node, 2);
135 } else {
136 SDValue Ops[] = {Dst, SrcOrValue, Size, Chain};
137 const EVT ResultTys[] = {MVT::i64, MVT::i64, MVT::i64, MVT::Other};
138 MachineSDNode *Node = DAG.getMachineNode(Opcode, dl: DL, ResultTys, Ops);
139
140 auto SrcFlags = MachineMemOperand::MOLoad | Vol;
141 auto *SrcOp =
142 MF.getMachineMemOperand(PtrInfo: SrcPtrInfo, F: SrcFlags, Size: MemSize, BaseAlignment: SrcAlign);
143 DAG.setNodeMemRefs(N: Node, NewMemRefs: {DstOp, SrcOp});
144 return SDValue(Node, 3);
145 }
146}
147
148SDValue AArch64SelectionDAGInfo::EmitStreamingCompatibleMemLibCall(
149 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op0, SDValue Op1,
150 SDValue Size, RTLIB::Libcall LC) const {
151 const AArch64Subtarget &STI =
152 DAG.getMachineFunction().getSubtarget<AArch64Subtarget>();
153 const AArch64TargetLowering *TLI = STI.getTargetLowering();
154 TargetLowering::ArgListTy Args;
155 Args.emplace_back(args&: Op0, args: PointerType::getUnqual(C&: *DAG.getContext()));
156
157 bool UsesResult = false;
158 RTLIB::Libcall NewLC;
159 switch (LC) {
160 case RTLIB::MEMCPY: {
161 NewLC = RTLIB::SC_MEMCPY;
162 Args.emplace_back(args&: Op1, args: PointerType::getUnqual(C&: *DAG.getContext()));
163 break;
164 }
165 case RTLIB::MEMMOVE: {
166 NewLC = RTLIB::SC_MEMMOVE;
167 Args.emplace_back(args&: Op1, args: PointerType::getUnqual(C&: *DAG.getContext()));
168 break;
169 }
170 case RTLIB::MEMSET: {
171 NewLC = RTLIB::SC_MEMSET;
172 Args.emplace_back(args: DAG.getZExtOrTrunc(Op: Op1, DL, VT: MVT::i32),
173 args: Type::getInt32Ty(C&: *DAG.getContext()));
174 break;
175 }
176 case RTLIB::MEMCHR: {
177 UsesResult = true;
178 NewLC = RTLIB::SC_MEMCHR;
179 Args.emplace_back(args: DAG.getZExtOrTrunc(Op: Op1, DL, VT: MVT::i32),
180 args: Type::getInt32Ty(C&: *DAG.getContext()));
181 break;
182 }
183 default:
184 return SDValue();
185 }
186
187 RTLIB::LibcallImpl NewLCImpl = DAG.getLibcalls().getLibcallImpl(Call: NewLC);
188 if (NewLCImpl == RTLIB::Unsupported)
189 return SDValue();
190
191 EVT PointerVT = TLI->getPointerTy(DL: DAG.getDataLayout());
192 SDValue Symbol = DAG.getExternalSymbol(LCImpl: NewLCImpl, VT: PointerVT);
193 Args.emplace_back(args&: Size, args: DAG.getDataLayout().getIntPtrType(C&: *DAG.getContext()));
194
195 TargetLowering::CallLoweringInfo CLI(DAG);
196 PointerType *RetTy = PointerType::getUnqual(C&: *DAG.getContext());
197 CLI.setDebugLoc(DL).setChain(Chain).setLibCallee(
198 CC: DAG.getLibcalls().getLibcallImplCallingConv(Call: NewLCImpl), ResultType: RetTy, Target: Symbol,
199 ArgsList: std::move(Args));
200
201 auto [Result, ChainOut] = TLI->LowerCallTo(CLI);
202 return UsesResult ? DAG.getMergeValues(Ops: {Result, ChainOut}, dl: DL) : ChainOut;
203}
204
205SDValue AArch64SelectionDAGInfo::EmitTargetCodeForMemcpy(
206 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src,
207 SDValue Size, Align DstAlign, Align SrcAlign, bool isVolatile,
208 bool AlwaysInline, MachinePointerInfo DstPtrInfo,
209 MachinePointerInfo SrcPtrInfo) const {
210 const AArch64Subtarget &STI =
211 DAG.getMachineFunction().getSubtarget<AArch64Subtarget>();
212
213 if (UseMOPS && STI.hasMOPS())
214 return EmitMOPS(Opcode: AArch64::MOPSMemoryCopyPseudo, DAG, DL, Chain, Dst, SrcOrValue: Src,
215 Size, DstAlign, SrcAlign, isVolatile, DstPtrInfo,
216 SrcPtrInfo);
217
218 auto *AFI = DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
219 SMEAttrs Attrs = AFI->getSMEFnAttrs();
220 if (LowerToSMERoutines && !Attrs.hasNonStreamingInterfaceAndBody())
221 return EmitStreamingCompatibleMemLibCall(DAG, DL, Chain, Op0: Dst, Op1: Src, Size,
222 LC: RTLIB::MEMCPY);
223 return SDValue();
224}
225
226SDValue AArch64SelectionDAGInfo::EmitTargetCodeForMemset(
227 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
228 SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
229 MachinePointerInfo DstPtrInfo) const {
230 const AArch64Subtarget &STI =
231 DAG.getMachineFunction().getSubtarget<AArch64Subtarget>();
232
233 if (UseMOPS && STI.hasMOPS())
234 return EmitMOPS(Opcode: AArch64::MOPSMemorySetPseudo, DAG, DL: dl, Chain, Dst, SrcOrValue: Src,
235 Size, DstAlign: Alignment, SrcAlign: Alignment, isVolatile, DstPtrInfo,
236 SrcPtrInfo: MachinePointerInfo{});
237
238 auto *AFI = DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
239 SMEAttrs Attrs = AFI->getSMEFnAttrs();
240 if (LowerToSMERoutines && !Attrs.hasNonStreamingInterfaceAndBody())
241 return EmitStreamingCompatibleMemLibCall(DAG, DL: dl, Chain, Op0: Dst, Op1: Src, Size,
242 LC: RTLIB::MEMSET);
243 return SDValue();
244}
245
246SDValue AArch64SelectionDAGInfo::EmitTargetCodeForMemmove(
247 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
248 SDValue Size, Align DstAlign, Align SrcAlign, bool isVolatile,
249 MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
250 const AArch64Subtarget &STI =
251 DAG.getMachineFunction().getSubtarget<AArch64Subtarget>();
252
253 if (UseMOPS && STI.hasMOPS())
254 return EmitMOPS(Opcode: AArch64::MOPSMemoryMovePseudo, DAG, DL: dl, Chain, Dst, SrcOrValue: Src,
255 Size, DstAlign, SrcAlign, isVolatile, DstPtrInfo,
256 SrcPtrInfo);
257
258 auto *AFI = DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
259 SMEAttrs Attrs = AFI->getSMEFnAttrs();
260 if (LowerToSMERoutines && !Attrs.hasNonStreamingInterfaceAndBody())
261 return EmitStreamingCompatibleMemLibCall(DAG, DL: dl, Chain, Op0: Dst, Op1: Src, Size,
262 LC: RTLIB::MEMMOVE);
263 return SDValue();
264}
265
266std::pair<SDValue, SDValue> AArch64SelectionDAGInfo::EmitTargetCodeForMemchr(
267 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Src,
268 SDValue Char, SDValue Length, MachinePointerInfo SrcPtrInfo) const {
269 auto *AFI = DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
270 SMEAttrs Attrs = AFI->getSMEFnAttrs();
271 if (LowerToSMERoutines && !Attrs.hasNonStreamingInterfaceAndBody()) {
272 SDValue Result = EmitStreamingCompatibleMemLibCall(
273 DAG, DL: dl, Chain, Op0: Src, Op1: Char, Size: Length, LC: RTLIB::MEMCHR);
274 return std::make_pair(x: Result.getValue(R: 0), y: Result.getValue(R: 1));
275 }
276 return std::make_pair(x: SDValue(), y: SDValue());
277}
278
279static const int kSetTagLoopThreshold = 176;
280
281static SDValue EmitUnrolledSetTag(SelectionDAG &DAG, const SDLoc &dl,
282 SDValue Chain, SDValue Ptr, uint64_t ObjSize,
283 const MachineMemOperand *BaseMemOperand,
284 bool ZeroData) {
285 MachineFunction &MF = DAG.getMachineFunction();
286 unsigned ObjSizeScaled = ObjSize / 16;
287
288 SDValue TagSrc = Ptr;
289 if (Ptr.getOpcode() == ISD::FrameIndex) {
290 int FI = cast<FrameIndexSDNode>(Val&: Ptr)->getIndex();
291 Ptr = DAG.getTargetFrameIndex(FI, VT: MVT::i64);
292 // A frame index operand may end up as [SP + offset] => it is fine to use SP
293 // register as the tag source.
294 TagSrc = DAG.getRegister(Reg: AArch64::SP, VT: MVT::i64);
295 }
296
297 const unsigned OpCode1 = ZeroData ? AArch64ISD::STZG : AArch64ISD::STG;
298 const unsigned OpCode2 = ZeroData ? AArch64ISD::STZ2G : AArch64ISD::ST2G;
299
300 SmallVector<SDValue, 8> OutChains;
301 unsigned OffsetScaled = 0;
302 while (OffsetScaled < ObjSizeScaled) {
303 if (ObjSizeScaled - OffsetScaled >= 2) {
304 SDValue AddrNode = DAG.getMemBasePlusOffset(
305 Base: Ptr, Offset: TypeSize::getFixed(ExactSize: OffsetScaled * 16), DL: dl);
306 SDValue St = DAG.getMemIntrinsicNode(
307 Opcode: OpCode2, dl, VTList: DAG.getVTList(VT: MVT::Other),
308 Ops: {Chain, TagSrc, AddrNode},
309 MemVT: MVT::v4i64,
310 MMO: MF.getMachineMemOperand(MMO: BaseMemOperand, Offset: OffsetScaled * 16, Size: 16 * 2));
311 OffsetScaled += 2;
312 OutChains.push_back(Elt: St);
313 continue;
314 }
315
316 if (ObjSizeScaled - OffsetScaled > 0) {
317 SDValue AddrNode = DAG.getMemBasePlusOffset(
318 Base: Ptr, Offset: TypeSize::getFixed(ExactSize: OffsetScaled * 16), DL: dl);
319 SDValue St = DAG.getMemIntrinsicNode(
320 Opcode: OpCode1, dl, VTList: DAG.getVTList(VT: MVT::Other),
321 Ops: {Chain, TagSrc, AddrNode},
322 MemVT: MVT::v2i64,
323 MMO: MF.getMachineMemOperand(MMO: BaseMemOperand, Offset: OffsetScaled * 16, Size: 16));
324 OffsetScaled += 1;
325 OutChains.push_back(Elt: St);
326 }
327 }
328
329 SDValue Res = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: OutChains);
330 return Res;
331}
332
333SDValue AArch64SelectionDAGInfo::EmitTargetCodeForSetTag(
334 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Addr,
335 SDValue Size, MachinePointerInfo DstPtrInfo, bool ZeroData) const {
336 uint64_t ObjSize = Size->getAsZExtVal();
337 assert(ObjSize % 16 == 0);
338
339 MachineFunction &MF = DAG.getMachineFunction();
340 MachineMemOperand *BaseMemOperand = MF.getMachineMemOperand(
341 PtrInfo: DstPtrInfo, F: MachineMemOperand::MOStore, Size: ObjSize, BaseAlignment: Align(16));
342
343 bool UseSetTagRangeLoop =
344 kSetTagLoopThreshold >= 0 && (int)ObjSize >= kSetTagLoopThreshold;
345 if (!UseSetTagRangeLoop)
346 return EmitUnrolledSetTag(DAG, dl, Chain, Ptr: Addr, ObjSize, BaseMemOperand,
347 ZeroData);
348
349 const EVT ResTys[] = {MVT::i64, MVT::i64, MVT::Other};
350
351 unsigned Opcode;
352 if (Addr.getOpcode() == ISD::FrameIndex) {
353 int FI = cast<FrameIndexSDNode>(Val&: Addr)->getIndex();
354 Addr = DAG.getTargetFrameIndex(FI, VT: MVT::i64);
355 Opcode = ZeroData ? AArch64::STZGloop : AArch64::STGloop;
356 } else {
357 Opcode = ZeroData ? AArch64::STZGloop_wback : AArch64::STGloop_wback;
358 }
359 SDValue Ops[] = {DAG.getTargetConstant(Val: ObjSize, DL: dl, VT: MVT::i64), Addr, Chain};
360 SDNode *St = DAG.getMachineNode(Opcode, dl, ResultTys: ResTys, Ops);
361
362 DAG.setNodeMemRefs(N: cast<MachineSDNode>(Val: St), NewMemRefs: {BaseMemOperand});
363 return SDValue(St, 2);
364}
365