1//===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#include "AArch64TargetMachine.h"
13#include "AArch64.h"
14#include "AArch64AsmPrinter.h"
15#include "AArch64MachineFunctionInfo.h"
16#include "AArch64MachineScheduler.h"
17#include "AArch64MacroFusion.h"
18#include "AArch64Subtarget.h"
19#include "AArch64TargetObjectFile.h"
20#include "AArch64TargetTransformInfo.h"
21#include "MCTargetDesc/AArch64MCTargetDesc.h"
22#include "TargetInfo/AArch64TargetInfo.h"
23#include "llvm/ADT/StringExtras.h"
24#include "llvm/Analysis/TargetTransformInfo.h"
25#include "llvm/Analysis/ValueTracking.h"
26#include "llvm/CodeGen/CSEConfigBase.h"
27#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
28#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
29#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
30#include "llvm/CodeGen/GlobalISel/Legalizer.h"
31#include "llvm/CodeGen/GlobalISel/LoadStoreOpt.h"
32#include "llvm/CodeGen/GlobalISel/Localizer.h"
33#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
34#include "llvm/CodeGen/MIRParser/MIParser.h"
35#include "llvm/CodeGen/MachineScheduler.h"
36#include "llvm/CodeGen/Passes.h"
37#include "llvm/CodeGen/TargetInstrInfo.h"
38#include "llvm/CodeGen/TargetPassConfig.h"
39#include "llvm/IR/Attributes.h"
40#include "llvm/IR/Function.h"
41#include "llvm/InitializePasses.h"
42#include "llvm/MC/MCAsmInfo.h"
43#include "llvm/MC/MCTargetOptions.h"
44#include "llvm/MC/TargetRegistry.h"
45#include "llvm/Option/LibraryOptions.h"
46#include "llvm/Pass.h"
47#include "llvm/Passes/PassBuilder.h"
48#include "llvm/Support/CodeGen.h"
49#include "llvm/Support/CommandLine.h"
50#include "llvm/Support/Compiler.h"
51#include "llvm/Target/TargetLoweringObjectFile.h"
52#include "llvm/Target/TargetOptions.h"
53#include "llvm/TargetParser/Triple.h"
54#include "llvm/Transforms/CFGuard.h"
55#include "llvm/Transforms/Scalar.h"
56#include "llvm/Transforms/Utils/LowerIFunc.h"
57#include "llvm/Transforms/Vectorize/LoopIdiomVectorize.h"
58#include <memory>
59
60using namespace llvm;
61
62extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
63LLVMInitializeAArch64Target() {
64 // Register the target.
65 RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
66 RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
67 RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
68 RegisterTargetMachine<AArch64leTargetMachine> W(getTheARM64_32Target());
69 RegisterTargetMachine<AArch64leTargetMachine> V(getTheAArch64_32Target());
70 static opt::RegisterLibraryOptions<AArch64Options> O;
71 auto &PR = *PassRegistry::getPassRegistry();
72 initializeGlobalISel(PR);
73 initializeAArch64A53Fix835769LegacyPass(PR);
74 initializeAArch64A57FPLoadBalancingLegacyPass(PR);
75 initializeAArch64CodeLayoutOptPass(PR);
76 initializeAArch64AdvSIMDScalarLegacyPass(PR);
77 initializeAArch64AsmPrinterPass(PR);
78 initializeAArch64BranchTargetsLegacyPass(PR);
79 initializeAArch64CollectLOHLegacyPass(PR);
80 initializeAArch64CompressJumpTablesLegacyPass(PR);
81 initializeAArch64ConditionalComparesLegacyPass(PR);
82 initializeAArch64ConditionOptimizerLegacyPass(PR);
83 initializeAArch64DeadRegisterDefinitionsLegacyPass(PR);
84 initializeAArch64ExpandPseudoLegacyPass(PR);
85 initializeAArch64LoadStoreOptLegacyPass(PR);
86 initializeAArch64MIPeepholeOptLegacyPass(PR);
87 initializeAArch64PTrueCoalescingLegacyPass(PR);
88 initializeAArch64SIMDInstrOptLegacyPass(PR);
89 initializeAArch64O0PreLegalizerCombinerLegacyPass(PR);
90 initializeAArch64PredicateAsCounterLoopRewritesPass(PR);
91 initializeAArch64PreLegalizerCombinerLegacyPass(PR);
92 initializeAArch64PointerAuthLegacyPass(PR);
93 initializeAArch64PostCoalescerLegacyPass(PR);
94 initializeAArch64PostLegalizerCombinerLegacyPass(PR);
95 initializeAArch64PostSelectOptimizeLegacyPass(PR);
96 initializeAArch64PostLegalizerLoweringLegacyPass(PR);
97 initializeAArch64PromoteConstantPass(PR);
98 initializeAArch64RedundantCopyEliminationLegacyPass(PR);
99 initializeAArch64RedundantCondBranchLegacyPass(PR);
100 initializeAArch64StorePairSuppressPass(PR);
101 initializeFalkorHWPFFixPass(PR);
102 initializeFalkorMarkStridedAccessesLegacyPass(PR);
103 initializeLDTLSCleanupPass(PR);
104 initializeMachineKCFILegacyPass(PR);
105 initializeMachineSMEABIPass(PR);
106 initializeAArch64SRLTDefineSuperRegsLegacyPass(PR);
107 initializeSMEPeepholeOptPass(PR);
108 initializeAArch64SpeculationHardeningPass(PR);
109 initializeAArch64SLSHardeningLegacyPass(PR);
110 initializeAArch64StackTaggingPass(PR);
111 initializeAArch64StackTaggingPreRALegacyPass(PR);
112 initializeAArch64LowerHomogeneousPrologEpilogLegacyPass(PR);
113 initializeAArch64DAGToDAGISelLegacyPass(PR);
114 initializeAArch64CondBrTuningPass(PR);
115 initializeAArch64Arm64ECCallLoweringPass(PR);
116 initializeSVEShuffleOptsPass(PR);
117}
118
119bool AArch64TargetMachine::isGlobalISelOptNone() const {
120 const bool GlobalISelFlag =
121 getCGPassBuilderOption(TM: *this).EnableGlobalISelOption ==
122 cl::boolOrDefault::BOU_TRUE;
123
124 return getOptLevel() == CodeGenOptLevel::None ||
125 (static_cast<unsigned>(getOptLevel()) >
126 static_cast<unsigned>(CLOpts.enable_global_isel_at_O) &&
127 !GlobalISelFlag);
128}
129
130void AArch64TargetMachine::reset() {
131 SubtargetMap.clear();
132 LastSubtarget = nullptr;
133}
134
135//===----------------------------------------------------------------------===//
136// AArch64 Lowering public interface.
137//===----------------------------------------------------------------------===//
138static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
139 if (TT.isOSBinFormatMachO())
140 return std::make_unique<AArch64_MachoTargetObjectFile>();
141 if (TT.isOSBinFormatCOFF())
142 return std::make_unique<AArch64_COFFTargetObjectFile>();
143
144 return std::make_unique<AArch64_ELFTargetObjectFile>();
145}
146
147static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU) {
148 if (CPU.empty() && TT.isArm64e())
149 return "apple-a12";
150 return CPU;
151}
152
153static Reloc::Model getEffectiveRelocModel(const Triple &TT,
154 std::optional<Reloc::Model> RM) {
155 // AArch64 Darwin and Windows are always PIC.
156 if (TT.isOSDarwin() || TT.isOSWindows())
157 return Reloc::PIC_;
158 // On ELF platforms the default static relocation model has a smart enough
159 // linker to cope with referencing external symbols defined in a shared
160 // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
161 if (!RM || *RM == Reloc::DynamicNoPIC)
162 return Reloc::Static;
163 return *RM;
164}
165
166static CodeModel::Model
167getEffectiveAArch64CodeModel(const Triple &TT,
168 std::optional<CodeModel::Model> CM, bool JIT) {
169 if (CM) {
170 if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
171 *CM != CodeModel::Large) {
172 report_fatal_error(
173 reason: "Only small, tiny and large code models are allowed on AArch64");
174 } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF()) {
175 report_fatal_error(reason: "tiny code model is only supported on ELF");
176 }
177 return *CM;
178 }
179 // The default MCJIT memory managers make no guarantees about where they can
180 // find an executable page; JITed code needs to be able to refer to globals
181 // no matter how far away they are.
182 // We should set the CodeModel::Small for Windows ARM64 in JIT mode,
183 // since with large code model LLVM generating 4 MOV instructions, and
184 // Windows doesn't support relocating these long branch (4 MOVs).
185 if (JIT && !TT.isOSWindows())
186 return CodeModel::Large;
187 return CodeModel::Small;
188}
189
190/// Create an AArch64 architecture model.
191///
192AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
193 StringRef CPU, StringRef FS,
194 const TargetOptions &Options,
195 std::optional<Reloc::Model> RM,
196 std::optional<CodeModel::Model> CM,
197 CodeGenOptLevel OL, bool JIT,
198 bool LittleEndian)
199 : CodeGenTargetMachineImpl(T, TT, computeDefaultCPU(TT, CPU), FS, Options,
200 getEffectiveRelocModel(TT, RM),
201 getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
202 CLOpts(cl::LibraryOptionsContext::get<AArch64Options>(
203 C: Options.MCOptions.LibraryOptions)),
204 TLOF(createTLOF(TT: getTargetTriple())), isLittle(LittleEndian) {
205 initAsmInfo();
206
207 if (TT.isOSBinFormatMachO()) {
208 this->Options.TrapUnreachable = true;
209 this->Options.NoTrapAfterNoreturn = true;
210 }
211
212 if (this->Options.TLSSize == 0) // default
213 this->Options.TLSSize = 24;
214 if ((getCodeModel() == CodeModel::Small ||
215 getCodeModel() == CodeModel::Kernel) &&
216 this->Options.TLSSize > 32)
217 // for the small (and kernel) code model, the maximum TLS size is 4GiB
218 this->Options.TLSSize = 32;
219 else if (getCodeModel() == CodeModel::Tiny && this->Options.TLSSize > 24)
220 // for the tiny code model, the maximum TLS size is 1MiB (< 16MiB)
221 this->Options.TLSSize = 24;
222
223 const bool TargetSupportsGISel =
224 TT.getArch() != Triple::aarch64_32 &&
225 TT.getEnvironment() != Triple::GNUILP32 &&
226 !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO());
227
228 const bool GlobalISelFlag =
229 getCGPassBuilderOption(TM: *this).EnableGlobalISelOption ==
230 cl::boolOrDefault::BOU_TRUE;
231
232 // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
233 // MachO/CodeModel::Large, which GlobalISel does not support.
234 if (TargetSupportsGISel && CLOpts.enable_global_isel_at_O != -1 &&
235 (static_cast<int>(getOptLevel()) <= CLOpts.enable_global_isel_at_O ||
236 (!GlobalISelFlag && !Options.EnableGlobalISel))) {
237 setGlobalISel(true);
238 setGlobalISelAbort(GlobalISelAbortMode::Disable);
239 }
240
241 LLT::setUseExtended(true);
242
243 // AArch64 supports the MachineOutliner.
244 setMachineOutliner(true);
245
246 // AArch64 supports default outlining behaviour.
247 setSupportsDefaultOutlining(true);
248
249 // AArch64 supports the debug entry values.
250 setSupportsDebugEntryValues(true);
251
252 // AArch64 supports fixing up the DWARF unwind information.
253 // enableCFIFixup() checks per function for DWARF unwinding.
254 setCFIFixup(true);
255}
256
257unsigned AArch64TargetMachine::getEnableGlobalISelAtO() const {
258 return CLOpts.enable_global_isel_at_O;
259}
260
261AArch64TargetMachine::~AArch64TargetMachine() = default;
262
263const AArch64Subtarget *
264AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
265 // Constructing the subtarget key is not cheap, avoid rebuilding it for
266 // repeated queries with the same function attributes.
267 AttributeSet FnAttrs = F.getAttributes().getFnAttrs();
268 if (LastSubtarget && LastSubtargetAttrs == FnAttrs)
269 return LastSubtarget;
270
271 Attribute CPUAttr = F.getFnAttribute(Kind: "target-cpu");
272 Attribute TuneAttr = F.getFnAttribute(Kind: "tune-cpu");
273 Attribute FSAttr = F.getFnAttribute(Kind: "target-features");
274
275 StringRef CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString() : TargetCPU;
276 StringRef TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString() : CPU;
277 StringRef FS = FSAttr.isValid() ? FSAttr.getValueAsString() : TargetFS;
278 bool HasMinSize = F.hasMinSize();
279
280 bool IsStreaming = CLOpts.force_streaming ||
281 F.hasFnAttribute(Kind: "aarch64_pstate_sm_enabled") ||
282 F.hasFnAttribute(Kind: "aarch64_pstate_sm_body");
283 bool IsStreamingCompatible = CLOpts.force_streaming_compatible ||
284 F.hasFnAttribute(Kind: "aarch64_pstate_sm_compatible");
285
286 unsigned MinSVEVectorSize = 0;
287 unsigned MaxSVEVectorSize = 0;
288 if (F.hasFnAttribute(Kind: Attribute::VScaleRange)) {
289 ConstantRange CR = getVScaleRange(F: &F, BitWidth: 64);
290 MinSVEVectorSize = CR.getUnsignedMin().getZExtValue() * 128;
291 MaxSVEVectorSize = CR.getUnsignedMax().getZExtValue() * 128;
292 } else {
293 MinSVEVectorSize = CLOpts.sve_vector_bits_min;
294 MaxSVEVectorSize = CLOpts.sve_vector_bits_max;
295 }
296
297 assert(MinSVEVectorSize % 128 == 0 &&
298 "SVE requires vector length in multiples of 128!");
299 assert(MaxSVEVectorSize % 128 == 0 &&
300 "SVE requires vector length in multiples of 128!");
301 assert((MaxSVEVectorSize >= MinSVEVectorSize || MaxSVEVectorSize == 0) &&
302 "Minimum SVE vector size should not be larger than its maximum!");
303
304 // Sanitize user input in case of no asserts
305 if (MaxSVEVectorSize != 0) {
306 MinSVEVectorSize = std::min(a: MinSVEVectorSize, b: MaxSVEVectorSize);
307 MaxSVEVectorSize = std::max(a: MinSVEVectorSize, b: MaxSVEVectorSize);
308 }
309
310 SmallString<512> Key;
311 // This lookup is hot during repeated TTI queries, so build the key directly
312 // instead of formatting through raw_svector_ostream.
313 Key += "SVEMin";
314 Key += utostr(X: MinSVEVectorSize);
315 Key += "SVEMax";
316 Key += utostr(X: MaxSVEVectorSize);
317 Key += "IsStreaming=";
318 Key += utostr(X: IsStreaming);
319 Key += "IsStreamingCompatible=";
320 Key += utostr(X: IsStreamingCompatible);
321 Key += CPU;
322 Key += TuneCPU;
323 Key += FS;
324 Key += "HasMinSize=";
325 Key += utostr(X: HasMinSize);
326
327 auto &I = SubtargetMap[Key];
328 if (!I) {
329 I = std::make_unique<AArch64Subtarget>(
330 args: TargetTriple, args&: CPU, args&: TuneCPU, args&: FS, args: *this, args: isLittle, args&: MinSVEVectorSize,
331 args&: MaxSVEVectorSize, args&: IsStreaming, args&: IsStreamingCompatible, args&: HasMinSize,
332 args: CLOpts.srlt_mitigate_sr2r);
333 }
334
335 if (IsStreaming && !I->hasSME())
336 reportFatalUsageError(reason: "streaming SVE functions require SME");
337
338 LastSubtargetAttrs = FnAttrs;
339 LastSubtarget = I.get();
340 return LastSubtarget;
341}
342
343// Encourage placing FORM_TRANSPOSED_REG immediately before the instruction that
344// uses/consumes it. This ensures its def has a short live range, which means
345// we're more likely to allocate registers its operands first (which works best
346// for the hints in AArch64RegisterInfo::getRegAllocationHints).
347static bool scheduleFormTransposedTupleAdjacentToUsers(
348 const TargetInstrInfo &TII, const TargetSubtargetInfo &TSI,
349 const MachineInstr *FirstMI, const MachineInstr &SecondMI,
350 const SDep *Dep) {
351 if (isNonDataDep(Dep))
352 return false;
353 return !FirstMI ||
354 FirstMI->getOpcode() == AArch64::FORM_TRANSPOSED_REG_TUPLE_X2_PSEUDO ||
355 FirstMI->getOpcode() == AArch64::FORM_TRANSPOSED_REG_TUPLE_X4_PSEUDO;
356}
357
358ScheduleDAGInstrs *
359AArch64TargetMachine::createMachineScheduler(MachineSchedContext *C) const {
360 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
361 ScheduleDAGMILive *DAG = createSchedLive(C);
362 DAG->addMutation(Mutation: createLoadClusterDAGMutation(TII: DAG->TII));
363 DAG->addMutation(Mutation: createStoreClusterDAGMutation(TII: DAG->TII));
364 if (ST.hasFusion())
365 DAG->addMutation(Mutation: createAArch64MacroFusionDAGMutation());
366 if (ST.hasSME() && ST.isStreaming())
367 DAG->addMutation(Mutation: createMacroFusionDAGMutation(
368 Predicates: scheduleFormTransposedTupleAdjacentToUsers));
369 return DAG;
370}
371
372ScheduleDAGInstrs *
373AArch64TargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
374 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
375 ScheduleDAGMI *DAG = createSchedPostRA<AArch64PostRASchedStrategy>(C);
376 if (ST.hasFusion()) {
377 // Run the Macro Fusion after RA again since literals are expanded from
378 // pseudos then (v. addPreSched2()).
379 DAG->addMutation(Mutation: createAArch64MacroFusionDAGMutation());
380 return DAG;
381 }
382
383 return DAG;
384}
385
386size_t AArch64TargetMachine::clearLinkerOptimizationHints(
387 const SmallPtrSetImpl<MachineInstr *> &MIs) const {
388 if (MIs.empty())
389 return 0;
390 auto *MI = *MIs.begin();
391 auto *FuncInfo = MI->getMF()->getInfo<AArch64FunctionInfo>();
392 return FuncInfo->clearLinkerOptimizationHints(MIs);
393}
394
395void AArch64leTargetMachine::anchor() { }
396
397AArch64leTargetMachine::AArch64leTargetMachine(
398 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
399 const TargetOptions &Options, std::optional<Reloc::Model> RM,
400 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT)
401 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
402
403void AArch64beTargetMachine::anchor() { }
404
405AArch64beTargetMachine::AArch64beTargetMachine(
406 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
407 const TargetOptions &Options, std::optional<Reloc::Model> RM,
408 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT)
409 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
410
411namespace {
412
413/// AArch64 Code Generator Pass Configuration Options.
414class AArch64PassConfig : public TargetPassConfig {
415 const AArch64Options &CLOpts;
416
417public:
418 AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
419 : TargetPassConfig(TM, PM), CLOpts(TM.getCLOpts()) {
420 if (TM.getOptLevel() != CodeGenOptLevel::None)
421 substitutePass(StandardID: &PostRASchedulerID, TargetID: &PostMachineSchedulerID);
422 setEnableSinkAndFold(CLOpts.enable_sink_fold);
423 }
424
425 AArch64TargetMachine &getAArch64TargetMachine() const {
426 return getTM<AArch64TargetMachine>();
427 }
428
429 void addIRPasses() override;
430 bool addPreISel() override;
431 void addCodeGenPrepare() override;
432 bool addInstSelector() override;
433 bool addIRTranslator() override;
434 void addPreLegalizeMachineIR() override;
435 bool addLegalizeMachineIR() override;
436 void addPreRegBankSelect() override;
437 bool addRegBankSelect() override;
438 bool addGlobalInstructionSelect() override;
439 void addMachineSSAOptimization() override;
440 bool addILPOpts() override;
441 void addPreRegAlloc() override;
442 void addPostRewrite() override;
443 void addPostRegAlloc() override;
444 void addPreSched2() override;
445 void addPreEmitPass() override;
446 void addPostBBSections() override;
447 void addPreEmitPass2() override;
448 bool addRegAssignAndRewriteOptimized() override;
449
450 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
451};
452
453} // end anonymous namespace
454
455void AArch64TargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
456#define GET_PASS_REGISTRY "AArch64PassRegistry.def"
457#include "llvm/Passes/TargetPassRegistry.inc"
458
459 PB.registerLateLoopOptimizationsEPCallback(
460 C: [=](LoopPassManager &LPM, OptimizationLevel Level) {
461 if (Level != OptimizationLevel::O0)
462 LPM.addPass(Pass: LoopIdiomVectorizePass());
463 });
464 if (getTargetTriple().isOSWindows())
465 PB.registerPipelineEarlySimplificationEPCallback(
466 C: [](ModulePassManager &PM, OptimizationLevel, ThinOrFullLTOPhase) {
467 PM.addPass(Pass: LowerIFuncPass());
468 });
469}
470
471TargetTransformInfo
472AArch64TargetMachine::getTargetTransformInfo(const Function &F) const {
473 return TargetTransformInfo(std::make_unique<AArch64TTIImpl>(args: this, args: F));
474}
475
476TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
477 return new AArch64PassConfig(*this, PM);
478}
479
480std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
481 return getStandardCSEConfigForOpt(Level: TM->getOptLevel());
482}
483
484void AArch64PassConfig::addIRPasses() {
485 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
486 // ourselves.
487 addPass(P: createAtomicExpandLegacyPass());
488
489 if (getOptLevel() >= CodeGenOptLevel::Default &&
490 CLOpts.enable_subreg_liveness_tracking &&
491 CLOpts.enable_predicate_as_counter_loop_rewrites)
492 addPass(P: createAArch64PredicateAsCounterLoopRewritesPass());
493
494 // Cmpxchg instructions are often used with a subsequent comparison to
495 // determine whether it succeeded. We can exploit existing control-flow in
496 // ldrex/strex loops to simplify this, but it needs tidying up.
497 if (TM->getOptLevel() != CodeGenOptLevel::None &&
498 CLOpts.enable_atomic_cfg_tidy)
499 addPass(P: createCFGSimplificationPass(Options: SimplifyCFGOptions()
500 .forwardSwitchCondToPhi(B: true)
501 .convertSwitchRangeToICmp(B: true)
502 .convertSwitchToLookupTable(B: true)
503 .needCanonicalLoops(B: false)
504 .hoistCommonInsts(B: true)
505 .sinkCommonInsts(B: true)));
506
507 // Run LoopDataPrefetch
508 //
509 // Run this before LSR to remove the multiplies involved in computing the
510 // pointer values N iterations ahead.
511 if (TM->getOptLevel() != CodeGenOptLevel::None) {
512 if (CLOpts.enable_loop_data_prefetch)
513 addPass(P: createLoopDataPrefetchPass());
514 if (CLOpts.enable_falkor_hwpf_fix)
515 addPass(P: createFalkorMarkStridedAccessesPass());
516 }
517
518 if (CLOpts.enable_gep_opt) {
519 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
520 // and lower a GEP with multiple indices to either arithmetic operations or
521 // multiple GEPs with single index.
522 addPass(P: createSeparateConstOffsetFromGEPPass(LowerGEP: true));
523 // Call EarlyCSE pass to find and remove subexpressions in the lowered
524 // result.
525 addPass(P: createEarlyCSEPass());
526 // Do loop invariant code motion in case part of the lowered result is
527 // invariant.
528 addPass(P: createLICMPass());
529 }
530
531 TargetPassConfig::addIRPasses();
532
533 if (getOptLevel() == CodeGenOptLevel::Aggressive && CLOpts.select_opt)
534 addPass(P: createSelectOptimizePass());
535
536 addPass(P: createAArch64StackTaggingPass(
537 CLOpts, /*IsOptNone=*/TM->getOptLevel() == CodeGenOptLevel::None));
538
539 // Try to use tbl in place of other shuffling operations if doing so would
540 // reduce the total number of instructions. Shuffle masks for big endian may
541 // be different, so require a little endian target.
542 if (getOptLevel() >= CodeGenOptLevel::Default &&
543 CLOpts.enable_sve_shuffle_opts && TM->getTargetTriple().isLittleEndian())
544 addPass(P: createSVEShuffleOptsPass());
545
546 // Match complex arithmetic patterns
547 if (TM->getOptLevel() >= CodeGenOptLevel::Default)
548 addPass(P: createComplexDeinterleavingPass(TM));
549
550 // Match interleaved memory accesses to ldN/stN intrinsics.
551 if (TM->getOptLevel() != CodeGenOptLevel::None) {
552 addPass(P: createInterleavedLoadCombinePass());
553 addPass(P: createInterleavedAccessPass());
554 }
555
556 // Add Control Flow Guard checks.
557 if (TM->getTargetTriple().isOSWindows()) {
558 if (TM->getTargetTriple().isWindowsArm64EC())
559 addPass(P: createAArch64Arm64ECCallLoweringPass());
560 else
561 addPass(P: createCFGuardPass());
562 }
563
564 if (TM->Options.JMCInstrument)
565 addPass(P: createJMCInstrumenterPass());
566}
567
568// Pass Pipeline Configuration
569bool AArch64PassConfig::addPreISel() {
570 // Run promote constant before global merge, so that the promoted constants
571 // get a chance to be merged
572 if (TM->getOptLevel() != CodeGenOptLevel::None && CLOpts.enable_promote_const)
573 addPass(P: createAArch64PromoteConstantPass());
574 // FIXME: On AArch64, this depends on the type.
575 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
576 // and the offset has to be a multiple of the related size in bytes.
577 if (valueOr(X: CLOpts.enable_global_merge,
578 Default: TM->getOptLevel() != CodeGenOptLevel::None)) {
579 bool OnlyOptimizeForSize =
580 (TM->getOptLevel() < CodeGenOptLevel::Aggressive) &&
581 (CLOpts.enable_global_merge == BoolOrDefault::Default);
582
583 // Merging of extern globals is enabled by default on non-Mach-O as we
584 // expect it to be generally either beneficial or harmless. On Mach-O it
585 // is disabled as we emit the .subsections_via_symbols directive which
586 // means that merging extern globals is not safe.
587 bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
588 addPass(P: createGlobalMergePass(TM, MaximalOffset: 4095, OnlyOptimizeForSize,
589 MergeExternalByDefault));
590 }
591
592 return false;
593}
594
595void AArch64PassConfig::addCodeGenPrepare() {
596 if (getOptLevel() != CodeGenOptLevel::None)
597 addPass(P: createTypePromotionLegacyPass());
598 TargetPassConfig::addCodeGenPrepare();
599}
600
601bool AArch64PassConfig::addInstSelector() {
602 addPass(P: createAArch64ISelDag(TM&: getAArch64TargetMachine(), OptLevel: getOptLevel()));
603 return false;
604}
605
606bool AArch64PassConfig::addIRTranslator() {
607 addPass(P: new IRTranslatorLegacy(getOptLevel()));
608 return false;
609}
610
611void AArch64PassConfig::addPreLegalizeMachineIR() {
612 if (getAArch64TargetMachine().isGlobalISelOptNone()) {
613 addPass(P: createAArch64O0PreLegalizerCombiner());
614 } else {
615 addPass(P: createAArch64PreLegalizerCombiner());
616 addPass(P: new LocalizerLegacy());
617 if (CLOpts.enable_gisel_ldst_prelegal)
618 addPass(P: new LoadStoreOptLegacy());
619 }
620}
621
622bool AArch64PassConfig::addLegalizeMachineIR() {
623 addPass(P: new LegalizerLegacy());
624 return false;
625}
626
627void AArch64PassConfig::addPreRegBankSelect() {
628 const bool IsGlobalISelOptNone =
629 getAArch64TargetMachine().isGlobalISelOptNone();
630 if (!IsGlobalISelOptNone) {
631 addPass(P: createAArch64PostLegalizerCombinerLegacy(IsOptNone: IsGlobalISelOptNone));
632 if (CLOpts.enable_gisel_ldst_postlegal)
633 addPass(P: new LoadStoreOptLegacy());
634 }
635 addPass(P: createAArch64PostLegalizerLowering());
636}
637
638bool AArch64PassConfig::addRegBankSelect() {
639 addPass(P: new RegBankSelectLegacy());
640 return false;
641}
642
643bool AArch64PassConfig::addGlobalInstructionSelect() {
644 addPass(P: new InstructionSelectLegacy(getOptLevel()));
645 if (!getAArch64TargetMachine().isGlobalISelOptNone())
646 addPass(P: createAArch64PostSelectOptimize());
647
648 return false;
649}
650
651void AArch64PassConfig::addMachineSSAOptimization() {
652 // For ELF, cleanup any local-dynamic TLS accesses
653 // (i.e. combine as many references to _TLS_MODULE_BASE_ as possible.
654 if (TM->getTargetTriple().isOSBinFormatELF() &&
655 getOptLevel() != CodeGenOptLevel::None)
656 addPass(P: createAArch64CleanupLocalDynamicTLSPass());
657
658 if (TM->getOptLevel() != CodeGenOptLevel::None)
659 addPass(P: createMachineSMEABIPass(TM->getOptLevel()));
660
661 if (TM->getOptLevel() != CodeGenOptLevel::None &&
662 CLOpts.enable_aarch64_sme_peephole_opt)
663 addPass(P: createSMEPeepholeOptPass());
664
665 // Run default MachineSSAOptimization first.
666 TargetPassConfig::addMachineSSAOptimization();
667
668 if (TM->getOptLevel() != CodeGenOptLevel::None) {
669 addPass(P: createAArch64MIPeepholeOptLegacyPass());
670 addPass(P: createAArch64PTrueCoalescingLegacyPass());
671 }
672}
673
674bool AArch64PassConfig::addILPOpts() {
675 if (CLOpts.enable_condopt)
676 addPass(P: createAArch64ConditionOptimizerLegacyPass());
677 if (CLOpts.enable_ccmp)
678 addPass(P: createAArch64ConditionalCompares());
679 if (CLOpts.enable_mcr)
680 addPass(PassID: &MachineCombinerID);
681 if (CLOpts.enable_cond_br_tune)
682 addPass(P: createAArch64CondBrTuning());
683 if (CLOpts.enable_early_ifcvt)
684 addPass(PassID: &EarlyIfConverterLegacyID);
685 if (CLOpts.enable_stp_suppress)
686 addPass(P: createAArch64StorePairSuppressPass());
687 addPass(P: createAArch64SIMDInstrOptPass());
688 if (TM->getOptLevel() != CodeGenOptLevel::None)
689 addPass(P: createAArch64StackTaggingPreRALegacyPass());
690 return true;
691}
692
693void AArch64PassConfig::addPreRegAlloc() {
694 if (TM->getOptLevel() == CodeGenOptLevel::None)
695 addPass(P: createMachineSMEABIPass(CodeGenOptLevel::None));
696
697 // Change dead register definitions to refer to the zero register.
698 if (TM->getOptLevel() != CodeGenOptLevel::None && CLOpts.enable_dead_defs)
699 addPass(P: createAArch64DeadRegisterDefinitions());
700
701 // Use AdvSIMD scalar instructions whenever profitable.
702 if (TM->getOptLevel() != CodeGenOptLevel::None && CLOpts.enable_simd_scalar) {
703 addPass(P: createAArch64AdvSIMDScalar());
704 // The AdvSIMD pass may produce copies that can be rewritten to
705 // be register coalescer friendly.
706 addPass(PassID: &PeepholeOptimizerLegacyID);
707 }
708 if (TM->getOptLevel() != CodeGenOptLevel::None && CLOpts.enable_pipeliner)
709 addPass(PassID: &MachinePipelinerID);
710}
711
712void AArch64PassConfig::addPostRewrite() {
713 if (CLOpts.srlt_mitigate_sr2r)
714 addPass(P: createAArch64SRLTDefineSuperRegsLegacyPass());
715}
716
717void AArch64PassConfig::addPostRegAlloc() {
718 // Remove redundant copy instructions.
719 if (TM->getOptLevel() != CodeGenOptLevel::None && CLOpts.enable_copyelim)
720 addPass(P: createAArch64RedundantCopyEliminationPass());
721
722 if (TM->getOptLevel() != CodeGenOptLevel::None && usingDefaultRegAlloc())
723 // Improve performance for some FP/SIMD code for A57.
724 addPass(P: createAArch64A57FPLoadBalancingLegacyPass());
725}
726
727void AArch64PassConfig::addPreSched2() {
728 // Lower homogeneous frame instructions
729 if (CLOpts.homogeneous_prolog_epilog)
730 addPass(P: createAArch64LowerHomogeneousPrologEpilogPass());
731 // Expand some pseudo instructions to allow proper scheduling.
732 addPass(P: createAArch64ExpandPseudoLegacyPass());
733 // Use load/store pair instructions when possible.
734 if (TM->getOptLevel() != CodeGenOptLevel::None) {
735 if (CLOpts.enable_ldst_opt)
736 addPass(P: createAArch64LoadStoreOptLegacyPass());
737 }
738 // Emit KCFI checks for indirect calls.
739 addPass(P: createKCFIPass());
740
741 // The AArch64SpeculationHardeningPass destroys dominator tree and natural
742 // loop info, which is needed for the FalkorHWPFFixPass and also later on.
743 // Therefore, run the AArch64SpeculationHardeningPass before the
744 // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
745 // info.
746 addPass(P: createAArch64SpeculationHardeningPass());
747
748 if (TM->getOptLevel() != CodeGenOptLevel::None) {
749 if (CLOpts.enable_falkor_hwpf_fix)
750 addPass(P: createFalkorHWPFFixPass());
751 }
752}
753
754void AArch64PassConfig::addPreEmitPass() {
755 // Machine Block Placement might have created new opportunities when run
756 // at O3, where the Tail Duplication Threshold is set to 4 instructions.
757 // Run the load/store optimizer once more.
758 if (TM->getOptLevel() >= CodeGenOptLevel::Aggressive &&
759 CLOpts.enable_ldst_opt)
760 addPass(P: createAArch64LoadStoreOptLegacyPass());
761
762 if (TM->getOptLevel() >= CodeGenOptLevel::Aggressive &&
763 CLOpts.enable_copy_propagation)
764 addPass(P: createMachineCopyPropagationPass(UseCopyInstr: true));
765 if (TM->getOptLevel() != CodeGenOptLevel::None)
766 addPass(P: createAArch64RedundantCondBranchPass());
767
768 addPass(P: createAArch64A53Fix835769LegacyPass());
769
770 if (TM->getTargetTriple().isOSWindows()) {
771 // Identify valid longjmp targets for Windows Control Flow Guard.
772 addPass(P: createCFGuardLongjmpPass());
773 // Identify valid eh continuation targets for Windows EHCont Guard.
774 addPass(P: createEHContGuardTargetsLegacy());
775 }
776
777 if (TM->getOptLevel() != CodeGenOptLevel::None && CLOpts.enable_collect_loh &&
778 TM->getTargetTriple().isOSBinFormatMachO())
779 addPass(P: createAArch64CollectLOHPass());
780
781 // Apply code layout optimizations. Run late so detection reflects the
782 // final MI stream.
783 if (getOptLevel() != CodeGenOptLevel::None)
784 addPass(P: createAArch64CodeLayoutOptPass());
785}
786
787void AArch64PassConfig::addPostBBSections() {
788 addPass(P: createAArch64SLSHardeningLegacyPass());
789 addPass(P: createAArch64PointerAuthPass());
790 if (CLOpts.enable_branch_targets)
791 addPass(P: createAArch64BranchTargetsPass());
792 // Relax conditional branch instructions if they're otherwise out of
793 // range of their destination.
794 if (CLOpts.enable_branch_relax)
795 addPass(PassID: &BranchRelaxationPassID);
796
797 if (TM->getOptLevel() != CodeGenOptLevel::None &&
798 CLOpts.enable_compress_jump_tables)
799 addPass(P: createAArch64CompressJumpTablesPass());
800}
801
802void AArch64PassConfig::addPreEmitPass2() {
803 // Insert pseudo probe annotation for callsite profiling
804 addPass(P: createPseudoProbeInserter());
805
806 // SVE bundles move prefixes with destructive operations. BLR_RVMARKER pseudo
807 // instructions are lowered to bundles as well.
808 addPass(P: createUnpackMachineBundlesLegacy(Ftor: nullptr));
809}
810
811bool AArch64PassConfig::addRegAssignAndRewriteOptimized() {
812 addPass(P: createAArch64PostCoalescerPass());
813 return TargetPassConfig::addRegAssignAndRewriteOptimized();
814}
815
816MachineFunctionInfo *AArch64TargetMachine::createMachineFunctionInfo(
817 BumpPtrAllocator &Allocator, const Function &F,
818 const TargetSubtargetInfo *STI) const {
819 return AArch64FunctionInfo::create<AArch64FunctionInfo>(
820 Allocator, F, STI: static_cast<const AArch64Subtarget *>(STI));
821}
822
823yaml::MachineFunctionInfo *
824AArch64TargetMachine::createDefaultFuncInfoYAML() const {
825 return new yaml::AArch64FunctionInfo();
826}
827
828yaml::MachineFunctionInfo *
829AArch64TargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
830 const auto *MFI = MF.getInfo<AArch64FunctionInfo>();
831 return new yaml::AArch64FunctionInfo(*MFI);
832}
833
834bool AArch64TargetMachine::parseMachineFunctionInfo(
835 const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,
836 SMDiagnostic &Error, SMRange &SourceRange) const {
837 const auto &YamlMFI = static_cast<const yaml::AArch64FunctionInfo &>(MFI);
838 MachineFunction &MF = PFS.MF;
839 MF.getInfo<AArch64FunctionInfo>()->initializeBaseYamlFields(YamlMFI);
840 return false;
841}
842