1//===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#include "AArch64TargetMachine.h"
13#include "AArch64.h"
14#include "AArch64AsmPrinter.h"
15#include "AArch64MachineFunctionInfo.h"
16#include "AArch64MachineScheduler.h"
17#include "AArch64MacroFusion.h"
18#include "AArch64Subtarget.h"
19#include "AArch64TargetObjectFile.h"
20#include "AArch64TargetTransformInfo.h"
21#include "MCTargetDesc/AArch64MCTargetDesc.h"
22#include "TargetInfo/AArch64TargetInfo.h"
23#include "llvm/ADT/StringExtras.h"
24#include "llvm/Analysis/TargetTransformInfo.h"
25#include "llvm/Analysis/ValueTracking.h"
26#include "llvm/CodeGen/CSEConfigBase.h"
27#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
28#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
29#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
30#include "llvm/CodeGen/GlobalISel/Legalizer.h"
31#include "llvm/CodeGen/GlobalISel/LoadStoreOpt.h"
32#include "llvm/CodeGen/GlobalISel/Localizer.h"
33#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
34#include "llvm/CodeGen/MIRParser/MIParser.h"
35#include "llvm/CodeGen/MachineScheduler.h"
36#include "llvm/CodeGen/Passes.h"
37#include "llvm/CodeGen/TargetInstrInfo.h"
38#include "llvm/CodeGen/TargetPassConfig.h"
39#include "llvm/IR/Attributes.h"
40#include "llvm/IR/Function.h"
41#include "llvm/InitializePasses.h"
42#include "llvm/MC/MCAsmInfo.h"
43#include "llvm/MC/MCTargetOptions.h"
44#include "llvm/MC/TargetRegistry.h"
45#include "llvm/Option/LibraryOptions.h"
46#include "llvm/Pass.h"
47#include "llvm/Passes/PassBuilder.h"
48#include "llvm/Support/CodeGen.h"
49#include "llvm/Support/CommandLine.h"
50#include "llvm/Support/Compiler.h"
51#include "llvm/Target/TargetLoweringObjectFile.h"
52#include "llvm/Target/TargetOptions.h"
53#include "llvm/TargetParser/Triple.h"
54#include "llvm/Transforms/CFGuard.h"
55#include "llvm/Transforms/Scalar.h"
56#include "llvm/Transforms/Utils/LowerIFunc.h"
57#include "llvm/Transforms/Vectorize/LoopIdiomVectorize.h"
58#include <memory>
59
60using namespace llvm;
61
62extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
63LLVMInitializeAArch64Target() {
64 // Register the target.
65 RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
66 RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
67 RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
68 RegisterTargetMachine<AArch64leTargetMachine> W(getTheARM64_32Target());
69 RegisterTargetMachine<AArch64leTargetMachine> V(getTheAArch64_32Target());
70 static opt::RegisterLibraryOptions<AArch64Options> O;
71 auto &PR = *PassRegistry::getPassRegistry();
72 initializeGlobalISel(PR);
73 initializeAArch64A53Fix835769LegacyPass(PR);
74 initializeAArch64A57FPLoadBalancingLegacyPass(PR);
75 initializeAArch64CodeLayoutOptPass(PR);
76 initializeAArch64AdvSIMDScalarLegacyPass(PR);
77 initializeAArch64AsmPrinterPass(PR);
78 initializeAArch64BranchTargetsLegacyPass(PR);
79 initializeAArch64CollectLOHLegacyPass(PR);
80 initializeAArch64CompressJumpTablesLegacyPass(PR);
81 initializeAArch64ConditionalComparesLegacyPass(PR);
82 initializeAArch64ConditionOptimizerLegacyPass(PR);
83 initializeAArch64DeadRegisterDefinitionsLegacyPass(PR);
84 initializeAArch64ExpandPseudoLegacyPass(PR);
85 initializeAArch64LoadStoreOptLegacyPass(PR);
86 initializeAArch64MIPeepholeOptLegacyPass(PR);
87 initializeAArch64PTrueCoalescingLegacyPass(PR);
88 initializeAArch64SIMDInstrOptLegacyPass(PR);
89 initializeAArch64O0PreLegalizerCombinerLegacyPass(PR);
90 initializeAArch64PredicateAsCounterLoopRewritesPass(PR);
91 initializeAArch64PreLegalizerCombinerLegacyPass(PR);
92 initializeAArch64PointerAuthLegacyPass(PR);
93 initializeAArch64PostCoalescerLegacyPass(PR);
94 initializeAArch64PostLegalizerCombinerLegacyPass(PR);
95 initializeAArch64PostSelectOptimizeLegacyPass(PR);
96 initializeAArch64PostLegalizerLoweringLegacyPass(PR);
97 initializeAArch64PromoteConstantPass(PR);
98 initializeAArch64RedundantCopyEliminationLegacyPass(PR);
99 initializeAArch64RedundantCondBranchLegacyPass(PR);
100 initializeAArch64StorePairSuppressPass(PR);
101 initializeFalkorHWPFFixPass(PR);
102 initializeFalkorMarkStridedAccessesLegacyPass(PR);
103 initializeLDTLSCleanupPass(PR);
104 initializeMachineKCFILegacyPass(PR);
105 initializeMachineSMEABIPass(PR);
106 initializeAArch64SRLTDefineSuperRegsLegacyPass(PR);
107 initializeSMEPeepholeOptPass(PR);
108 initializeAArch64SpeculationHardeningPass(PR);
109 initializeAArch64SLSHardeningLegacyPass(PR);
110 initializeAArch64StackTaggingPass(PR);
111 initializeAArch64StackTaggingPreRALegacyPass(PR);
112 initializeAArch64LowerHomogeneousPrologEpilogLegacyPass(PR);
113 initializeAArch64DAGToDAGISelLegacyPass(PR);
114 initializeAArch64CondBrTuningPass(PR);
115 initializeAArch64Arm64ECCallLoweringPass(PR);
116 initializeSVEShuffleOptsPass(PR);
117}
118
119bool AArch64TargetMachine::isGlobalISelOptNone() const {
120 const bool GlobalISelFlag = getCGPassBuilderOption().EnableGlobalISelOption ==
121 cl::boolOrDefault::BOU_TRUE;
122
123 return getOptLevel() == CodeGenOptLevel::None ||
124 (static_cast<unsigned>(getOptLevel()) >
125 static_cast<unsigned>(CLOpts.enable_global_isel_at_O) &&
126 !GlobalISelFlag);
127}
128
129void AArch64TargetMachine::reset() {
130 SubtargetMap.clear();
131 LastSubtarget = nullptr;
132}
133
134//===----------------------------------------------------------------------===//
135// AArch64 Lowering public interface.
136//===----------------------------------------------------------------------===//
137static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
138 if (TT.isOSBinFormatMachO())
139 return std::make_unique<AArch64_MachoTargetObjectFile>();
140 if (TT.isOSBinFormatCOFF())
141 return std::make_unique<AArch64_COFFTargetObjectFile>();
142
143 return std::make_unique<AArch64_ELFTargetObjectFile>();
144}
145
146static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU) {
147 if (CPU.empty() && TT.isArm64e())
148 return "apple-a12";
149 return CPU;
150}
151
152static Reloc::Model getEffectiveRelocModel(const Triple &TT,
153 std::optional<Reloc::Model> RM) {
154 // AArch64 Darwin and Windows are always PIC.
155 if (TT.isOSDarwin() || TT.isOSWindows())
156 return Reloc::PIC_;
157 // On ELF platforms the default static relocation model has a smart enough
158 // linker to cope with referencing external symbols defined in a shared
159 // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
160 if (!RM || *RM == Reloc::DynamicNoPIC)
161 return Reloc::Static;
162 return *RM;
163}
164
165static CodeModel::Model
166getEffectiveAArch64CodeModel(const Triple &TT,
167 std::optional<CodeModel::Model> CM, bool JIT) {
168 if (CM) {
169 if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
170 *CM != CodeModel::Large) {
171 report_fatal_error(
172 reason: "Only small, tiny and large code models are allowed on AArch64");
173 } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF()) {
174 report_fatal_error(reason: "tiny code model is only supported on ELF");
175 }
176 return *CM;
177 }
178 // The default MCJIT memory managers make no guarantees about where they can
179 // find an executable page; JITed code needs to be able to refer to globals
180 // no matter how far away they are.
181 // We should set the CodeModel::Small for Windows ARM64 in JIT mode,
182 // since with large code model LLVM generating 4 MOV instructions, and
183 // Windows doesn't support relocating these long branch (4 MOVs).
184 if (JIT && !TT.isOSWindows())
185 return CodeModel::Large;
186 return CodeModel::Small;
187}
188
189/// Create an AArch64 architecture model.
190///
191AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
192 StringRef CPU, StringRef FS,
193 const TargetOptions &Options,
194 std::optional<Reloc::Model> RM,
195 std::optional<CodeModel::Model> CM,
196 CodeGenOptLevel OL, bool JIT,
197 bool LittleEndian)
198 : CodeGenTargetMachineImpl(T, TT, computeDefaultCPU(TT, CPU), FS, Options,
199 getEffectiveRelocModel(TT, RM),
200 getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
201 CLOpts(AArch64Options::Global), TLOF(createTLOF(TT: getTargetTriple())),
202 isLittle(LittleEndian) {
203 initAsmInfo();
204
205 if (TT.isOSBinFormatMachO()) {
206 this->Options.TrapUnreachable = true;
207 this->Options.NoTrapAfterNoreturn = true;
208 }
209
210 if (getMCAsmInfo().usesWindowsCFI()) {
211 // Unwinding can get confused if the last instruction in an
212 // exception-handling region (function, funclet, try block, etc.)
213 // is a call.
214 //
215 // FIXME: We could elide the trap if the next instruction would be in
216 // the same region anyway.
217 this->Options.TrapUnreachable = true;
218 }
219
220 if (this->Options.TLSSize == 0) // default
221 this->Options.TLSSize = 24;
222 if ((getCodeModel() == CodeModel::Small ||
223 getCodeModel() == CodeModel::Kernel) &&
224 this->Options.TLSSize > 32)
225 // for the small (and kernel) code model, the maximum TLS size is 4GiB
226 this->Options.TLSSize = 32;
227 else if (getCodeModel() == CodeModel::Tiny && this->Options.TLSSize > 24)
228 // for the tiny code model, the maximum TLS size is 1MiB (< 16MiB)
229 this->Options.TLSSize = 24;
230
231 const bool TargetSupportsGISel =
232 TT.getArch() != Triple::aarch64_32 &&
233 TT.getEnvironment() != Triple::GNUILP32 &&
234 !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO());
235
236 const bool GlobalISelFlag = getCGPassBuilderOption().EnableGlobalISelOption ==
237 cl::boolOrDefault::BOU_TRUE;
238
239 // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
240 // MachO/CodeModel::Large, which GlobalISel does not support.
241 if (TargetSupportsGISel && CLOpts.enable_global_isel_at_O != -1 &&
242 (static_cast<int>(getOptLevel()) <= CLOpts.enable_global_isel_at_O ||
243 (!GlobalISelFlag && !Options.EnableGlobalISel))) {
244 setGlobalISel(true);
245 setGlobalISelAbort(GlobalISelAbortMode::Disable);
246 }
247
248 LLT::setUseExtended(true);
249
250 // AArch64 supports the MachineOutliner.
251 setMachineOutliner(true);
252
253 // AArch64 supports default outlining behaviour.
254 setSupportsDefaultOutlining(true);
255
256 // AArch64 supports the debug entry values.
257 setSupportsDebugEntryValues(true);
258
259 // AArch64 supports fixing up the DWARF unwind information.
260 if (!getMCAsmInfo().usesWindowsCFI())
261 setCFIFixup(true);
262}
263
264unsigned AArch64TargetMachine::getEnableGlobalISelAtO() const {
265 return CLOpts.enable_global_isel_at_O;
266}
267
268AArch64TargetMachine::~AArch64TargetMachine() = default;
269
270const AArch64Subtarget *
271AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
272 // Constructing the subtarget key is not cheap, avoid rebuilding it for
273 // repeated queries with the same function attributes.
274 AttributeSet FnAttrs = F.getAttributes().getFnAttrs();
275 if (LastSubtarget && LastSubtargetAttrs == FnAttrs)
276 return LastSubtarget;
277
278 Attribute CPUAttr = F.getFnAttribute(Kind: "target-cpu");
279 Attribute TuneAttr = F.getFnAttribute(Kind: "tune-cpu");
280 Attribute FSAttr = F.getFnAttribute(Kind: "target-features");
281
282 StringRef CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString() : TargetCPU;
283 StringRef TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString() : CPU;
284 StringRef FS = FSAttr.isValid() ? FSAttr.getValueAsString() : TargetFS;
285 bool HasMinSize = F.hasMinSize();
286
287 bool IsStreaming = CLOpts.force_streaming ||
288 F.hasFnAttribute(Kind: "aarch64_pstate_sm_enabled") ||
289 F.hasFnAttribute(Kind: "aarch64_pstate_sm_body");
290 bool IsStreamingCompatible = CLOpts.force_streaming_compatible ||
291 F.hasFnAttribute(Kind: "aarch64_pstate_sm_compatible");
292
293 unsigned MinSVEVectorSize = 0;
294 unsigned MaxSVEVectorSize = 0;
295 if (F.hasFnAttribute(Kind: Attribute::VScaleRange)) {
296 ConstantRange CR = getVScaleRange(F: &F, BitWidth: 64);
297 MinSVEVectorSize = CR.getUnsignedMin().getZExtValue() * 128;
298 MaxSVEVectorSize = CR.getUnsignedMax().getZExtValue() * 128;
299 } else {
300 MinSVEVectorSize = CLOpts.sve_vector_bits_min;
301 MaxSVEVectorSize = CLOpts.sve_vector_bits_max;
302 }
303
304 assert(MinSVEVectorSize % 128 == 0 &&
305 "SVE requires vector length in multiples of 128!");
306 assert(MaxSVEVectorSize % 128 == 0 &&
307 "SVE requires vector length in multiples of 128!");
308 assert((MaxSVEVectorSize >= MinSVEVectorSize || MaxSVEVectorSize == 0) &&
309 "Minimum SVE vector size should not be larger than its maximum!");
310
311 // Sanitize user input in case of no asserts
312 if (MaxSVEVectorSize != 0) {
313 MinSVEVectorSize = std::min(a: MinSVEVectorSize, b: MaxSVEVectorSize);
314 MaxSVEVectorSize = std::max(a: MinSVEVectorSize, b: MaxSVEVectorSize);
315 }
316
317 SmallString<512> Key;
318 // This lookup is hot during repeated TTI queries, so build the key directly
319 // instead of formatting through raw_svector_ostream.
320 Key += "SVEMin";
321 Key += utostr(X: MinSVEVectorSize);
322 Key += "SVEMax";
323 Key += utostr(X: MaxSVEVectorSize);
324 Key += "IsStreaming=";
325 Key += utostr(X: IsStreaming);
326 Key += "IsStreamingCompatible=";
327 Key += utostr(X: IsStreamingCompatible);
328 Key += CPU;
329 Key += TuneCPU;
330 Key += FS;
331 Key += "HasMinSize=";
332 Key += utostr(X: HasMinSize);
333
334 auto &I = SubtargetMap[Key];
335 if (!I) {
336 I = std::make_unique<AArch64Subtarget>(
337 args: TargetTriple, args&: CPU, args&: TuneCPU, args&: FS, args: *this, args: isLittle, args&: MinSVEVectorSize,
338 args&: MaxSVEVectorSize, args&: IsStreaming, args&: IsStreamingCompatible, args&: HasMinSize,
339 args: CLOpts.srlt_mitigate_sr2r);
340 }
341
342 if (IsStreaming && !I->hasSME())
343 reportFatalUsageError(reason: "streaming SVE functions require SME");
344
345 LastSubtargetAttrs = FnAttrs;
346 LastSubtarget = I.get();
347 return LastSubtarget;
348}
349
350// Encourage placing FORM_TRANSPOSED_REG immediately before the instruction that
351// uses/consumes it. This ensures its def has a short live range, which means
352// we're more likely to allocate registers its operands first (which works best
353// for the hints in AArch64RegisterInfo::getRegAllocationHints).
354static bool scheduleFormTransposedTupleAdjacentToUsers(
355 const TargetInstrInfo &TII, const TargetSubtargetInfo &TSI,
356 const MachineInstr *FirstMI, const MachineInstr &SecondMI,
357 const SDep *Dep) {
358 if (isNonDataDep(Dep))
359 return false;
360 return !FirstMI ||
361 FirstMI->getOpcode() == AArch64::FORM_TRANSPOSED_REG_TUPLE_X2_PSEUDO ||
362 FirstMI->getOpcode() == AArch64::FORM_TRANSPOSED_REG_TUPLE_X4_PSEUDO;
363}
364
365ScheduleDAGInstrs *
366AArch64TargetMachine::createMachineScheduler(MachineSchedContext *C) const {
367 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
368 ScheduleDAGMILive *DAG = createSchedLive(C);
369 DAG->addMutation(Mutation: createLoadClusterDAGMutation(TII: DAG->TII));
370 DAG->addMutation(Mutation: createStoreClusterDAGMutation(TII: DAG->TII));
371 if (ST.hasFusion())
372 DAG->addMutation(Mutation: createAArch64MacroFusionDAGMutation());
373 if (ST.hasSME() && ST.isStreaming())
374 DAG->addMutation(Mutation: createMacroFusionDAGMutation(
375 Predicates: scheduleFormTransposedTupleAdjacentToUsers));
376 return DAG;
377}
378
379ScheduleDAGInstrs *
380AArch64TargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
381 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
382 ScheduleDAGMI *DAG = createSchedPostRA<AArch64PostRASchedStrategy>(C);
383 if (ST.hasFusion()) {
384 // Run the Macro Fusion after RA again since literals are expanded from
385 // pseudos then (v. addPreSched2()).
386 DAG->addMutation(Mutation: createAArch64MacroFusionDAGMutation());
387 return DAG;
388 }
389
390 return DAG;
391}
392
393size_t AArch64TargetMachine::clearLinkerOptimizationHints(
394 const SmallPtrSetImpl<MachineInstr *> &MIs) const {
395 if (MIs.empty())
396 return 0;
397 auto *MI = *MIs.begin();
398 auto *FuncInfo = MI->getMF()->getInfo<AArch64FunctionInfo>();
399 return FuncInfo->clearLinkerOptimizationHints(MIs);
400}
401
402void AArch64leTargetMachine::anchor() { }
403
404AArch64leTargetMachine::AArch64leTargetMachine(
405 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
406 const TargetOptions &Options, std::optional<Reloc::Model> RM,
407 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT)
408 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
409
410void AArch64beTargetMachine::anchor() { }
411
412AArch64beTargetMachine::AArch64beTargetMachine(
413 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
414 const TargetOptions &Options, std::optional<Reloc::Model> RM,
415 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT)
416 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
417
418namespace {
419
420/// AArch64 Code Generator Pass Configuration Options.
421class AArch64PassConfig : public TargetPassConfig {
422 const AArch64Options &CLOpts;
423
424public:
425 AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
426 : TargetPassConfig(TM, PM), CLOpts(TM.getCLOpts()) {
427 if (TM.getOptLevel() != CodeGenOptLevel::None)
428 substitutePass(StandardID: &PostRASchedulerID, TargetID: &PostMachineSchedulerID);
429 setEnableSinkAndFold(CLOpts.enable_sink_fold);
430 }
431
432 AArch64TargetMachine &getAArch64TargetMachine() const {
433 return getTM<AArch64TargetMachine>();
434 }
435
436 void addIRPasses() override;
437 bool addPreISel() override;
438 void addCodeGenPrepare() override;
439 bool addInstSelector() override;
440 bool addIRTranslator() override;
441 void addPreLegalizeMachineIR() override;
442 bool addLegalizeMachineIR() override;
443 void addPreRegBankSelect() override;
444 bool addRegBankSelect() override;
445 bool addGlobalInstructionSelect() override;
446 void addMachineSSAOptimization() override;
447 bool addILPOpts() override;
448 void addPreRegAlloc() override;
449 void addPostRewrite() override;
450 void addPostRegAlloc() override;
451 void addPreSched2() override;
452 void addPreEmitPass() override;
453 void addPostBBSections() override;
454 void addPreEmitPass2() override;
455 bool addRegAssignAndRewriteOptimized() override;
456
457 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
458};
459
460} // end anonymous namespace
461
462void AArch64TargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
463#define GET_PASS_REGISTRY "AArch64PassRegistry.def"
464#include "llvm/Passes/TargetPassRegistry.inc"
465
466 PB.registerLateLoopOptimizationsEPCallback(
467 C: [=](LoopPassManager &LPM, OptimizationLevel Level) {
468 if (Level != OptimizationLevel::O0)
469 LPM.addPass(Pass: LoopIdiomVectorizePass());
470 });
471 if (getTargetTriple().isOSWindows())
472 PB.registerPipelineEarlySimplificationEPCallback(
473 C: [](ModulePassManager &PM, OptimizationLevel, ThinOrFullLTOPhase) {
474 PM.addPass(Pass: LowerIFuncPass());
475 });
476}
477
478TargetTransformInfo
479AArch64TargetMachine::getTargetTransformInfo(const Function &F) const {
480 return TargetTransformInfo(std::make_unique<AArch64TTIImpl>(args: this, args: F));
481}
482
483TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
484 return new AArch64PassConfig(*this, PM);
485}
486
487std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
488 return getStandardCSEConfigForOpt(Level: TM->getOptLevel());
489}
490
491void AArch64PassConfig::addIRPasses() {
492 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
493 // ourselves.
494 addPass(P: createAtomicExpandLegacyPass());
495
496 if (getOptLevel() >= CodeGenOptLevel::Default &&
497 CLOpts.enable_predicate_as_counter_loop_rewrites)
498 addPass(P: createAArch64PredicateAsCounterLoopRewritesPass());
499
500 // Cmpxchg instructions are often used with a subsequent comparison to
501 // determine whether it succeeded. We can exploit existing control-flow in
502 // ldrex/strex loops to simplify this, but it needs tidying up.
503 if (TM->getOptLevel() != CodeGenOptLevel::None &&
504 CLOpts.enable_atomic_cfg_tidy)
505 addPass(P: createCFGSimplificationPass(Options: SimplifyCFGOptions()
506 .forwardSwitchCondToPhi(B: true)
507 .convertSwitchRangeToICmp(B: true)
508 .convertSwitchToLookupTable(B: true)
509 .needCanonicalLoops(B: false)
510 .hoistCommonInsts(B: true)
511 .sinkCommonInsts(B: true)));
512
513 // Run LoopDataPrefetch
514 //
515 // Run this before LSR to remove the multiplies involved in computing the
516 // pointer values N iterations ahead.
517 if (TM->getOptLevel() != CodeGenOptLevel::None) {
518 if (CLOpts.enable_loop_data_prefetch)
519 addPass(P: createLoopDataPrefetchPass());
520 if (CLOpts.enable_falkor_hwpf_fix)
521 addPass(P: createFalkorMarkStridedAccessesPass());
522 }
523
524 if (CLOpts.enable_gep_opt) {
525 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
526 // and lower a GEP with multiple indices to either arithmetic operations or
527 // multiple GEPs with single index.
528 addPass(P: createSeparateConstOffsetFromGEPPass(LowerGEP: true));
529 // Call EarlyCSE pass to find and remove subexpressions in the lowered
530 // result.
531 addPass(P: createEarlyCSEPass());
532 // Do loop invariant code motion in case part of the lowered result is
533 // invariant.
534 addPass(P: createLICMPass());
535 }
536
537 TargetPassConfig::addIRPasses();
538
539 if (getOptLevel() == CodeGenOptLevel::Aggressive && CLOpts.select_opt)
540 addPass(P: createSelectOptimizePass());
541
542 addPass(P: createAArch64StackTaggingPass(
543 /*IsOptNone=*/TM->getOptLevel() == CodeGenOptLevel::None));
544
545 // Try to use tbl in place of other shuffling operations if doing so would
546 // reduce the total number of instructions. Shuffle masks for big endian may
547 // be different, so require a little endian target.
548 if (getOptLevel() >= CodeGenOptLevel::Default &&
549 CLOpts.enable_sve_shuffle_opts && TM->getTargetTriple().isLittleEndian())
550 addPass(P: createSVEShuffleOptsPass());
551
552 // Match complex arithmetic patterns
553 if (TM->getOptLevel() >= CodeGenOptLevel::Default)
554 addPass(P: createComplexDeinterleavingPass(TM));
555
556 // Match interleaved memory accesses to ldN/stN intrinsics.
557 if (TM->getOptLevel() != CodeGenOptLevel::None) {
558 addPass(P: createInterleavedLoadCombinePass());
559 addPass(P: createInterleavedAccessPass());
560 }
561
562 // Add Control Flow Guard checks.
563 if (TM->getTargetTriple().isOSWindows()) {
564 if (TM->getTargetTriple().isWindowsArm64EC())
565 addPass(P: createAArch64Arm64ECCallLoweringPass());
566 else
567 addPass(P: createCFGuardPass());
568 }
569
570 if (TM->Options.JMCInstrument)
571 addPass(P: createJMCInstrumenterPass());
572}
573
574// Pass Pipeline Configuration
575bool AArch64PassConfig::addPreISel() {
576 // Run promote constant before global merge, so that the promoted constants
577 // get a chance to be merged
578 if (TM->getOptLevel() != CodeGenOptLevel::None && CLOpts.enable_promote_const)
579 addPass(P: createAArch64PromoteConstantPass());
580 // FIXME: On AArch64, this depends on the type.
581 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
582 // and the offset has to be a multiple of the related size in bytes.
583 if (valueOr(X: CLOpts.enable_global_merge,
584 Default: TM->getOptLevel() != CodeGenOptLevel::None)) {
585 bool OnlyOptimizeForSize =
586 (TM->getOptLevel() < CodeGenOptLevel::Aggressive) &&
587 (CLOpts.enable_global_merge == BoolOrDefault::Default);
588
589 // Merging of extern globals is enabled by default on non-Mach-O as we
590 // expect it to be generally either beneficial or harmless. On Mach-O it
591 // is disabled as we emit the .subsections_via_symbols directive which
592 // means that merging extern globals is not safe.
593 bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
594 addPass(P: createGlobalMergePass(TM, MaximalOffset: 4095, OnlyOptimizeForSize,
595 MergeExternalByDefault));
596 }
597
598 return false;
599}
600
601void AArch64PassConfig::addCodeGenPrepare() {
602 if (getOptLevel() != CodeGenOptLevel::None)
603 addPass(P: createTypePromotionLegacyPass());
604 TargetPassConfig::addCodeGenPrepare();
605}
606
607bool AArch64PassConfig::addInstSelector() {
608 addPass(P: createAArch64ISelDag(TM&: getAArch64TargetMachine(), OptLevel: getOptLevel()));
609 return false;
610}
611
612bool AArch64PassConfig::addIRTranslator() {
613 addPass(P: new IRTranslatorLegacy(getOptLevel()));
614 return false;
615}
616
617void AArch64PassConfig::addPreLegalizeMachineIR() {
618 if (getAArch64TargetMachine().isGlobalISelOptNone()) {
619 addPass(P: createAArch64O0PreLegalizerCombiner());
620 addPass(P: new LocalizerLegacy());
621 } else {
622 addPass(P: createAArch64PreLegalizerCombiner());
623 addPass(P: new LocalizerLegacy());
624 if (CLOpts.enable_gisel_ldst_prelegal)
625 addPass(P: new LoadStoreOptLegacy());
626 }
627}
628
629bool AArch64PassConfig::addLegalizeMachineIR() {
630 addPass(P: new LegalizerLegacy());
631 return false;
632}
633
634void AArch64PassConfig::addPreRegBankSelect() {
635 const bool IsGlobalISelOptNone =
636 getAArch64TargetMachine().isGlobalISelOptNone();
637 if (!IsGlobalISelOptNone) {
638 addPass(P: createAArch64PostLegalizerCombinerLegacy(IsOptNone: IsGlobalISelOptNone));
639 if (CLOpts.enable_gisel_ldst_postlegal)
640 addPass(P: new LoadStoreOptLegacy());
641 }
642 addPass(P: createAArch64PostLegalizerLowering());
643}
644
645bool AArch64PassConfig::addRegBankSelect() {
646 addPass(P: new RegBankSelectLegacy());
647 return false;
648}
649
650bool AArch64PassConfig::addGlobalInstructionSelect() {
651 addPass(P: new InstructionSelectLegacy(getOptLevel()));
652 if (!getAArch64TargetMachine().isGlobalISelOptNone())
653 addPass(P: createAArch64PostSelectOptimize());
654
655 return false;
656}
657
658void AArch64PassConfig::addMachineSSAOptimization() {
659 // For ELF, cleanup any local-dynamic TLS accesses
660 // (i.e. combine as many references to _TLS_MODULE_BASE_ as possible.
661 if (TM->getTargetTriple().isOSBinFormatELF() &&
662 getOptLevel() != CodeGenOptLevel::None)
663 addPass(P: createAArch64CleanupLocalDynamicTLSPass());
664
665 if (TM->getOptLevel() != CodeGenOptLevel::None)
666 addPass(P: createMachineSMEABIPass(TM->getOptLevel()));
667
668 if (TM->getOptLevel() != CodeGenOptLevel::None &&
669 CLOpts.enable_aarch64_sme_peephole_opt)
670 addPass(P: createSMEPeepholeOptPass());
671
672 // Run default MachineSSAOptimization first.
673 TargetPassConfig::addMachineSSAOptimization();
674
675 if (TM->getOptLevel() != CodeGenOptLevel::None) {
676 addPass(P: createAArch64MIPeepholeOptLegacyPass());
677 addPass(P: createAArch64PTrueCoalescingLegacyPass());
678 }
679}
680
681bool AArch64PassConfig::addILPOpts() {
682 if (CLOpts.enable_condopt)
683 addPass(P: createAArch64ConditionOptimizerLegacyPass());
684 if (CLOpts.enable_ccmp)
685 addPass(P: createAArch64ConditionalCompares());
686 if (CLOpts.enable_mcr)
687 addPass(PassID: &MachineCombinerID);
688 if (CLOpts.enable_cond_br_tune)
689 addPass(P: createAArch64CondBrTuning());
690 if (CLOpts.enable_early_ifcvt)
691 addPass(PassID: &EarlyIfConverterLegacyID);
692 if (CLOpts.enable_stp_suppress)
693 addPass(P: createAArch64StorePairSuppressPass());
694 addPass(P: createAArch64SIMDInstrOptPass());
695 if (TM->getOptLevel() != CodeGenOptLevel::None)
696 addPass(P: createAArch64StackTaggingPreRALegacyPass());
697 return true;
698}
699
700void AArch64PassConfig::addPreRegAlloc() {
701 if (TM->getOptLevel() == CodeGenOptLevel::None)
702 addPass(P: createMachineSMEABIPass(CodeGenOptLevel::None));
703
704 // Change dead register definitions to refer to the zero register.
705 if (TM->getOptLevel() != CodeGenOptLevel::None && CLOpts.enable_dead_defs)
706 addPass(P: createAArch64DeadRegisterDefinitions());
707
708 // Use AdvSIMD scalar instructions whenever profitable.
709 if (TM->getOptLevel() != CodeGenOptLevel::None && CLOpts.enable_simd_scalar) {
710 addPass(P: createAArch64AdvSIMDScalar());
711 // The AdvSIMD pass may produce copies that can be rewritten to
712 // be register coalescer friendly.
713 addPass(PassID: &PeepholeOptimizerLegacyID);
714 }
715 if (TM->getOptLevel() != CodeGenOptLevel::None && CLOpts.enable_pipeliner)
716 addPass(PassID: &MachinePipelinerID);
717}
718
719void AArch64PassConfig::addPostRewrite() {
720 if (CLOpts.srlt_mitigate_sr2r)
721 addPass(P: createAArch64SRLTDefineSuperRegsLegacyPass());
722}
723
724void AArch64PassConfig::addPostRegAlloc() {
725 // Remove redundant copy instructions.
726 if (TM->getOptLevel() != CodeGenOptLevel::None && CLOpts.enable_copyelim)
727 addPass(P: createAArch64RedundantCopyEliminationPass());
728
729 if (TM->getOptLevel() != CodeGenOptLevel::None && usingDefaultRegAlloc())
730 // Improve performance for some FP/SIMD code for A57.
731 addPass(P: createAArch64A57FPLoadBalancingLegacyPass());
732}
733
734void AArch64PassConfig::addPreSched2() {
735 // Lower homogeneous frame instructions
736 if (CLOpts.homogeneous_prolog_epilog)
737 addPass(P: createAArch64LowerHomogeneousPrologEpilogPass());
738 // Expand some pseudo instructions to allow proper scheduling.
739 addPass(P: createAArch64ExpandPseudoLegacyPass());
740 // Use load/store pair instructions when possible.
741 if (TM->getOptLevel() != CodeGenOptLevel::None) {
742 if (CLOpts.enable_ldst_opt)
743 addPass(P: createAArch64LoadStoreOptLegacyPass());
744 }
745 // Emit KCFI checks for indirect calls.
746 addPass(P: createKCFIPass());
747
748 // The AArch64SpeculationHardeningPass destroys dominator tree and natural
749 // loop info, which is needed for the FalkorHWPFFixPass and also later on.
750 // Therefore, run the AArch64SpeculationHardeningPass before the
751 // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
752 // info.
753 addPass(P: createAArch64SpeculationHardeningPass());
754
755 if (TM->getOptLevel() != CodeGenOptLevel::None) {
756 if (CLOpts.enable_falkor_hwpf_fix)
757 addPass(P: createFalkorHWPFFixPass());
758 }
759}
760
761void AArch64PassConfig::addPreEmitPass() {
762 // Machine Block Placement might have created new opportunities when run
763 // at O3, where the Tail Duplication Threshold is set to 4 instructions.
764 // Run the load/store optimizer once more.
765 if (TM->getOptLevel() >= CodeGenOptLevel::Aggressive &&
766 CLOpts.enable_ldst_opt)
767 addPass(P: createAArch64LoadStoreOptLegacyPass());
768
769 if (TM->getOptLevel() >= CodeGenOptLevel::Aggressive &&
770 CLOpts.enable_copy_propagation)
771 addPass(P: createMachineCopyPropagationPass(UseCopyInstr: true));
772 if (TM->getOptLevel() != CodeGenOptLevel::None)
773 addPass(P: createAArch64RedundantCondBranchPass());
774
775 addPass(P: createAArch64A53Fix835769LegacyPass());
776
777 if (TM->getTargetTriple().isOSWindows()) {
778 // Identify valid longjmp targets for Windows Control Flow Guard.
779 addPass(P: createCFGuardLongjmpPass());
780 // Identify valid eh continuation targets for Windows EHCont Guard.
781 addPass(P: createEHContGuardTargetsLegacy());
782 }
783
784 if (TM->getOptLevel() != CodeGenOptLevel::None && CLOpts.enable_collect_loh &&
785 TM->getTargetTriple().isOSBinFormatMachO())
786 addPass(P: createAArch64CollectLOHPass());
787
788 // Apply code layout optimizations. Run late so detection reflects the
789 // final MI stream.
790 if (getOptLevel() != CodeGenOptLevel::None)
791 addPass(P: createAArch64CodeLayoutOptPass());
792}
793
794void AArch64PassConfig::addPostBBSections() {
795 addPass(P: createAArch64SLSHardeningLegacyPass());
796 addPass(P: createAArch64PointerAuthPass());
797 if (CLOpts.enable_branch_targets)
798 addPass(P: createAArch64BranchTargetsPass());
799 // Relax conditional branch instructions if they're otherwise out of
800 // range of their destination.
801 if (CLOpts.enable_branch_relax)
802 addPass(PassID: &BranchRelaxationPassID);
803
804 if (TM->getOptLevel() != CodeGenOptLevel::None &&
805 CLOpts.enable_compress_jump_tables)
806 addPass(P: createAArch64CompressJumpTablesPass());
807}
808
809void AArch64PassConfig::addPreEmitPass2() {
810 // Insert pseudo probe annotation for callsite profiling
811 addPass(P: createPseudoProbeInserter());
812
813 // SVE bundles move prefixes with destructive operations. BLR_RVMARKER pseudo
814 // instructions are lowered to bundles as well.
815 addPass(P: createUnpackMachineBundlesLegacy(Ftor: nullptr));
816}
817
818bool AArch64PassConfig::addRegAssignAndRewriteOptimized() {
819 addPass(P: createAArch64PostCoalescerPass());
820 return TargetPassConfig::addRegAssignAndRewriteOptimized();
821}
822
823MachineFunctionInfo *AArch64TargetMachine::createMachineFunctionInfo(
824 BumpPtrAllocator &Allocator, const Function &F,
825 const TargetSubtargetInfo *STI) const {
826 return AArch64FunctionInfo::create<AArch64FunctionInfo>(
827 Allocator, F, STI: static_cast<const AArch64Subtarget *>(STI));
828}
829
830yaml::MachineFunctionInfo *
831AArch64TargetMachine::createDefaultFuncInfoYAML() const {
832 return new yaml::AArch64FunctionInfo();
833}
834
835yaml::MachineFunctionInfo *
836AArch64TargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
837 const auto *MFI = MF.getInfo<AArch64FunctionInfo>();
838 return new yaml::AArch64FunctionInfo(*MFI);
839}
840
841bool AArch64TargetMachine::parseMachineFunctionInfo(
842 const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,
843 SMDiagnostic &Error, SMRange &SourceRange) const {
844 const auto &YamlMFI = static_cast<const yaml::AArch64FunctionInfo &>(MFI);
845 MachineFunction &MF = PFS.MF;
846 MF.getInfo<AArch64FunctionInfo>()->initializeBaseYamlFields(YamlMFI);
847 return false;
848}
849