1//===- AArch64LegalizerInfo.cpp ----------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements the targeting of the Machinelegalizer class for
10/// AArch64.
11/// \todo This should be generated by TableGen.
12//===----------------------------------------------------------------------===//
13
14#include "AArch64LegalizerInfo.h"
15#include "AArch64Subtarget.h"
16#include "llvm/ADT/STLExtras.h"
17#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
18#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
19#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
20#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
21#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
22#include "llvm/CodeGen/GlobalISel/Utils.h"
23#include "llvm/CodeGen/MachineInstr.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/TargetOpcodes.h"
27#include "llvm/IR/DerivedTypes.h"
28#include "llvm/IR/Intrinsics.h"
29#include "llvm/IR/IntrinsicsAArch64.h"
30#include "llvm/IR/Type.h"
31#include "llvm/Support/MathExtras.h"
32#include <initializer_list>
33
34#define DEBUG_TYPE "aarch64-legalinfo"
35
36using namespace llvm;
37using namespace LegalizeActions;
38using namespace LegalizeMutations;
39using namespace LegalityPredicates;
40using namespace MIPatternMatch;
41
42AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
43 : ST(&ST) {
44 using namespace TargetOpcode;
45 const LLT p0 = LLT::pointer(AddressSpace: 0, SizeInBits: 64);
46 const LLT s8 = LLT::scalar(SizeInBits: 8);
47 const LLT s16 = LLT::scalar(SizeInBits: 16);
48 const LLT s32 = LLT::scalar(SizeInBits: 32);
49 const LLT s64 = LLT::scalar(SizeInBits: 64);
50 const LLT s128 = LLT::scalar(SizeInBits: 128);
51 const LLT v16s8 = LLT::fixed_vector(NumElements: 16, ScalarSizeInBits: 8);
52 const LLT v8s8 = LLT::fixed_vector(NumElements: 8, ScalarSizeInBits: 8);
53 const LLT v4s8 = LLT::fixed_vector(NumElements: 4, ScalarSizeInBits: 8);
54 const LLT v2s8 = LLT::fixed_vector(NumElements: 2, ScalarSizeInBits: 8);
55 const LLT v8s16 = LLT::fixed_vector(NumElements: 8, ScalarSizeInBits: 16);
56 const LLT v4s16 = LLT::fixed_vector(NumElements: 4, ScalarSizeInBits: 16);
57 const LLT v2s16 = LLT::fixed_vector(NumElements: 2, ScalarSizeInBits: 16);
58 const LLT v2s32 = LLT::fixed_vector(NumElements: 2, ScalarSizeInBits: 32);
59 const LLT v4s32 = LLT::fixed_vector(NumElements: 4, ScalarSizeInBits: 32);
60 const LLT v2s64 = LLT::fixed_vector(NumElements: 2, ScalarSizeInBits: 64);
61 const LLT v2p0 = LLT::fixed_vector(NumElements: 2, ScalarTy: p0);
62
63 const LLT nxv16s8 = LLT::scalable_vector(MinNumElements: 16, ScalarTy: s8);
64 const LLT nxv8s16 = LLT::scalable_vector(MinNumElements: 8, ScalarTy: s16);
65 const LLT nxv4s32 = LLT::scalable_vector(MinNumElements: 4, ScalarTy: s32);
66 const LLT nxv2s64 = LLT::scalable_vector(MinNumElements: 2, ScalarTy: s64);
67
68 const LLT bf16 = LLT::bfloat16();
69 const LLT v4bf16 = LLT::fixed_vector(NumElements: 4, ScalarTy: bf16);
70 const LLT v8bf16 = LLT::fixed_vector(NumElements: 8, ScalarTy: bf16);
71
72 const LLT f16 = LLT::float16();
73 const LLT v4f16 = LLT::fixed_vector(NumElements: 4, ScalarTy: f16);
74 const LLT v8f16 = LLT::fixed_vector(NumElements: 8, ScalarTy: f16);
75
76 const LLT f32 = LLT::float32();
77 const LLT v2f32 = LLT::fixed_vector(NumElements: 2, ScalarTy: f32);
78 const LLT v4f32 = LLT::fixed_vector(NumElements: 4, ScalarTy: f32);
79
80 const LLT f64 = LLT::float64();
81 const LLT v2f64 = LLT::fixed_vector(NumElements: 2, ScalarTy: f64);
82
83 const LLT f128 = LLT::float128();
84
85 const LLT i8 = LLT::integer(SizeInBits: 8);
86 const LLT v8i8 = LLT::fixed_vector(NumElements: 8, ScalarTy: i8);
87 const LLT v16i8 = LLT::fixed_vector(NumElements: 16, ScalarTy: i8);
88
89 const LLT i16 = LLT::integer(SizeInBits: 16);
90 const LLT v8i16 = LLT::fixed_vector(NumElements: 8, ScalarTy: i16);
91 const LLT v4i16 = LLT::fixed_vector(NumElements: 4, ScalarTy: i16);
92
93 const LLT i32 = LLT::integer(SizeInBits: 32);
94 const LLT v2i32 = LLT::fixed_vector(NumElements: 2, ScalarTy: i32);
95 const LLT v4i32 = LLT::fixed_vector(NumElements: 4, ScalarTy: i32);
96
97 const LLT i64 = LLT::integer(SizeInBits: 64);
98 const LLT v2i64 = LLT::fixed_vector(NumElements: 2, ScalarTy: i64);
99
100 const LLT i128 = LLT::integer(SizeInBits: 128);
101
102 const LLT nxv16i8 = LLT::scalable_vector(MinNumElements: 16, ScalarTy: i8);
103 const LLT nxv8i16 = LLT::scalable_vector(MinNumElements: 8, ScalarTy: i16);
104 const LLT nxv4i32 = LLT::scalable_vector(MinNumElements: 4, ScalarTy: i32);
105 const LLT nxv2i64 = LLT::scalable_vector(MinNumElements: 2, ScalarTy: i64);
106
107 std::initializer_list<LLT> PackedVectorAllTypeList = {/* Begin 128bit types */
108 v16s8, v8s16, v4s32,
109 v2s64, v2p0,
110 /* End 128bit types */
111 /* Begin 64bit types */
112 v8s8, v4s16, v2s32};
113 std::initializer_list<LLT> ScalarAndPtrTypesList = {s8, s16, s32, s64, p0};
114 SmallVector<LLT, 8> PackedVectorAllTypesVec(PackedVectorAllTypeList);
115 SmallVector<LLT, 8> ScalarAndPtrTypesVec(ScalarAndPtrTypesList);
116
117 const TargetMachine &TM = ST.getTargetLowering()->getTargetMachine();
118
119 // FIXME: support subtargets which have neon/fp-armv8 disabled.
120 if (!ST.hasNEON() || !ST.hasFPARMv8())
121 return;
122
123 // Some instructions only support s16 if the subtarget has full 16-bit FP
124 // support.
125 const bool HasFP16 = ST.hasFullFP16();
126 const bool HasCSSC = ST.hasCSSC();
127 const bool HasRCPC3 = ST.hasRCPC3();
128 const bool HasSVE = ST.hasSVE();
129
130 getActionDefinitionsBuilder(
131 Opcodes: {G_IMPLICIT_DEF, G_FREEZE, G_CONSTANT_FOLD_BARRIER})
132 .legalFor(Types: {p0, s8, s16, s32, s64, s128})
133 .legalFor(Types: {v2s8, v4s8, v8s8, v16s8, v2s16, v4s16, v8s16, v2s32, v4s32,
134 v2s64, v2p0})
135 .widenScalarToNextPow2(TypeIdx: 0)
136 .clampScalar(TypeIdx: 0, MinTy: s8, MaxTy: s64)
137 .moreElementsToNextPow2(TypeIdx: 0)
138 .widenVectorEltsToVectorMinSize(TypeIdx: 0, VectorSize: 64)
139 .clampNumElements(TypeIdx: 0, MinTy: v8s8, MaxTy: v16s8)
140 .clampNumElements(TypeIdx: 0, MinTy: v4s16, MaxTy: v8s16)
141 .clampNumElements(TypeIdx: 0, MinTy: v2s32, MaxTy: v4s32)
142 .clampMaxNumElements(TypeIdx: 0, EltTy: s64, MaxElements: 2)
143 .clampMaxNumElements(TypeIdx: 0, EltTy: p0, MaxElements: 2)
144 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 0, Size: 64), TypeIdx: 0);
145
146 getActionDefinitionsBuilder(Opcode: G_PHI)
147 .legalFor(Types: {p0, s16, s32, s64})
148 .legalFor(Types: PackedVectorAllTypeList)
149 .widenScalarToNextPow2(TypeIdx: 0)
150 .moreElementsToNextPow2(TypeIdx: 0)
151 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 0, Size: 64), TypeIdx: 0)
152 .clampScalar(TypeIdx: 0, MinTy: s16, MaxTy: s64)
153 .clampNumElements(TypeIdx: 0, MinTy: v8s8, MaxTy: v16s8)
154 .clampNumElements(TypeIdx: 0, MinTy: v4s16, MaxTy: v8s16)
155 .clampNumElements(TypeIdx: 0, MinTy: v2s32, MaxTy: v4s32)
156 .clampMaxNumElements(TypeIdx: 0, EltTy: s64, MaxElements: 2)
157 .clampMaxNumElements(TypeIdx: 0, EltTy: p0, MaxElements: 2)
158 .widenScalarOrEltToNextPow2OrMinSize(TypeIdx: 0, MinSize: 8);
159
160 getActionDefinitionsBuilder(Opcode: G_INSERT)
161 .legalIf(Predicate: all(P0: typeInSet(TypeIdx: 0, TypesInit: {s32, s64, p0}), P1: typeInSet(TypeIdx: 1, TypesInit: {s8, s16, s32}),
162 args: smallerThan(TypeIdx0: 1, TypeIdx1: 0)))
163 .widenScalarToNextPow2(TypeIdx: 0)
164 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s64)
165 .widenScalarToNextPow2(TypeIdx: 1)
166 .minScalar(TypeIdx: 1, Ty: s8)
167 .maxScalarIf(Predicate: typeInSet(TypeIdx: 0, TypesInit: {s32}), TypeIdx: 1, Ty: s16)
168 .maxScalarIf(Predicate: typeInSet(TypeIdx: 0, TypesInit: {s64, p0}), TypeIdx: 1, Ty: s32);
169
170 getActionDefinitionsBuilder(Opcode: G_EXTRACT)
171 .legalIf(Predicate: all(P0: typeInSet(TypeIdx: 0, TypesInit: {s16, s32, s64, p0}),
172 P1: typeInSet(TypeIdx: 1, TypesInit: {s32, s64, s128, p0}), args: smallerThan(TypeIdx0: 0, TypeIdx1: 1)))
173 .widenScalarToNextPow2(TypeIdx: 1)
174 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s128)
175 .widenScalarToNextPow2(TypeIdx: 0)
176 .minScalar(TypeIdx: 0, Ty: s16)
177 .maxScalarIf(Predicate: typeInSet(TypeIdx: 1, TypesInit: {s32}), TypeIdx: 0, Ty: s16)
178 .maxScalarIf(Predicate: typeInSet(TypeIdx: 1, TypesInit: {s64, p0}), TypeIdx: 0, Ty: s32)
179 .maxScalarIf(Predicate: typeInSet(TypeIdx: 1, TypesInit: {s128}), TypeIdx: 0, Ty: s64);
180
181 getActionDefinitionsBuilder(Opcodes: {G_ADD, G_SUB, G_AND, G_OR, G_XOR})
182 .legalFor(Types: {i32, i64, v8i8, v16i8, v4i16, v8i16, v2i32, v4i32, v2i64})
183 .legalFor(Pred: HasSVE, Types: {nxv16i8, nxv8i16, nxv4i32, nxv2i64})
184 .widenScalarToNextPow2(TypeIdx: 0)
185 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s64)
186 .clampMaxNumElements(TypeIdx: 0, EltTy: s8, MaxElements: 16)
187 .clampMaxNumElements(TypeIdx: 0, EltTy: s16, MaxElements: 8)
188 .clampNumElements(TypeIdx: 0, MinTy: v2s32, MaxTy: v4s32)
189 .clampNumElements(TypeIdx: 0, MinTy: v2s64, MaxTy: v2s64)
190 .minScalarOrEltIf(
191 Predicate: [=](const LegalityQuery &Query) {
192 return Query.Types[0].getNumElements() <= 2;
193 },
194 TypeIdx: 0, Ty: s32)
195 .minScalarOrEltIf(
196 Predicate: [=](const LegalityQuery &Query) {
197 return Query.Types[0].getNumElements() <= 4;
198 },
199 TypeIdx: 0, Ty: s16)
200 .minScalarOrEltIf(
201 Predicate: [=](const LegalityQuery &Query) {
202 return Query.Types[0].getNumElements() <= 16;
203 },
204 TypeIdx: 0, Ty: s8)
205 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 0, Size: 64), TypeIdx: 0)
206 .moreElementsToNextPow2(TypeIdx: 0);
207
208 getActionDefinitionsBuilder(Opcode: G_MUL)
209 .legalFor(Types: {i32, i64, v8i8, v16i8, v4i16, v8i16, v2i32, v4i32, v2i64})
210 .widenScalarToNextPow2(TypeIdx: 0)
211 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s64)
212 .clampMaxNumElements(TypeIdx: 0, EltTy: s8, MaxElements: 16)
213 .clampMaxNumElements(TypeIdx: 0, EltTy: s16, MaxElements: 8)
214 .clampNumElements(TypeIdx: 0, MinTy: v2s32, MaxTy: v4s32)
215 .clampNumElements(TypeIdx: 0, MinTy: v2s64, MaxTy: v2s64)
216 .minScalarOrEltIf(
217 Predicate: [=](const LegalityQuery &Query) {
218 return Query.Types[0].getNumElements() <= 2;
219 },
220 TypeIdx: 0, Ty: s32)
221 .minScalarOrEltIf(
222 Predicate: [=](const LegalityQuery &Query) {
223 return Query.Types[0].getNumElements() <= 4;
224 },
225 TypeIdx: 0, Ty: s16)
226 .minScalarOrEltIf(
227 Predicate: [=](const LegalityQuery &Query) {
228 return Query.Types[0].getNumElements() <= 16;
229 },
230 TypeIdx: 0, Ty: s8)
231 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 0, Size: 64), TypeIdx: 0)
232 .moreElementsToNextPow2(TypeIdx: 0);
233
234 getActionDefinitionsBuilder(Opcodes: {G_SHL, G_ASHR, G_LSHR})
235 .customIf(Predicate: [=](const LegalityQuery &Query) {
236 const auto &SrcTy = Query.Types[0];
237 const auto &AmtTy = Query.Types[1];
238 return !SrcTy.isVector() && SrcTy.getSizeInBits() == 32 &&
239 AmtTy.getSizeInBits() == 32;
240 })
241 .legalFor(Types: {
242 {i32, i32},
243 {i32, i64},
244 {i64, i64},
245 {v8i8, v8i8},
246 {v16i8, v16i8},
247 {v4i16, v4i16},
248 {v8i16, v8i16},
249 {v2i32, v2i32},
250 {v4i32, v4i32},
251 {v2i64, v2i64},
252 })
253 .widenScalarToNextPow2(TypeIdx: 1)
254 .widenScalarToNextPow2(TypeIdx: 0)
255 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s64)
256 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s64)
257 .clampNumElements(TypeIdx: 0, MinTy: v8s8, MaxTy: v16s8)
258 .clampNumElements(TypeIdx: 0, MinTy: v4s16, MaxTy: v8s16)
259 .clampNumElements(TypeIdx: 0, MinTy: v2s32, MaxTy: v4s32)
260 .clampNumElements(TypeIdx: 0, MinTy: v2s64, MaxTy: v2s64)
261 .moreElementsToNextPow2(TypeIdx: 0)
262 .minScalarSameAs(TypeIdx: 1, LargeTypeIdx: 0)
263 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 0, Size: 64), TypeIdx: 0)
264 .minScalarEltSameAsIf(Predicate: isVector(TypeIdx: 0), TypeIdx: 1, LargeTypeIdx: 0)
265 .maxScalarEltSameAsIf(Predicate: isVector(TypeIdx: 0), TypeIdx: 1, SmallTypeIdx: 0);
266
267 getActionDefinitionsBuilder(Opcode: G_PTR_ADD)
268 .legalFor(Types: {{p0, i64}, {v2p0, v2i64}})
269 .clampScalarOrElt(TypeIdx: 1, MinTy: s64, MaxTy: s64)
270 .clampNumElements(TypeIdx: 0, MinTy: v2p0, MaxTy: v2p0);
271
272 getActionDefinitionsBuilder(Opcode: G_PTRMASK).legalFor(Types: {{p0, s64}});
273
274 getActionDefinitionsBuilder(Opcodes: {G_SDIV, G_UDIV})
275 .legalFor(Types: {i32, i64})
276 .libcallFor(Types: {i128})
277 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s64)
278 .widenScalarToNextPow2(TypeIdx: 0)
279 .scalarize(TypeIdx: 0);
280
281 getActionDefinitionsBuilder(Opcodes: {G_SREM, G_UREM, G_SDIVREM, G_UDIVREM})
282 .lowerFor(Types: {i8, i16, i32, i64, v2i32, v4i32, v2i64})
283 .libcallFor(Types: {i128})
284 .widenScalarOrEltToNextPow2(TypeIdx: 0)
285 .minScalarOrElt(TypeIdx: 0, Ty: s32)
286 .clampNumElements(TypeIdx: 0, MinTy: v2s32, MaxTy: v4s32)
287 .clampNumElements(TypeIdx: 0, MinTy: v2s64, MaxTy: v2s64)
288 .scalarize(TypeIdx: 0);
289
290 getActionDefinitionsBuilder(Opcodes: {G_SMULO, G_UMULO})
291 .widenScalarToNextPow2(TypeIdx: 0, /*Min = */ MinSize: 32)
292 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s64)
293 .lower();
294
295 getActionDefinitionsBuilder(Opcodes: {G_SMULH, G_UMULH})
296 .legalFor(Types: {i64, v16i8, v8i16, v4i32})
297 .lower();
298
299 getActionDefinitionsBuilder(
300 Opcodes: {G_SMULFIX, G_UMULFIX, G_SMULFIXSAT, G_UMULFIXSAT})
301 .lower();
302
303 getActionDefinitionsBuilder(Opcodes: {G_SMIN, G_SMAX, G_UMIN, G_UMAX})
304 .legalFor(Types: {v8i8, v16i8, v4i16, v8i16, v2i32, v4i32})
305 .legalFor(Pred: HasCSSC, Types: {i32, i64})
306 .minScalar(Pred: HasCSSC, TypeIdx: 0, Ty: s32)
307 .clampNumElements(TypeIdx: 0, MinTy: v8s8, MaxTy: v16s8)
308 .clampNumElements(TypeIdx: 0, MinTy: v4s16, MaxTy: v8s16)
309 .clampNumElements(TypeIdx: 0, MinTy: v2s32, MaxTy: v4s32)
310 .lower();
311
312 // FIXME: Legal vector types are only legal with NEON.
313 getActionDefinitionsBuilder(Opcode: G_ABS)
314 .legalFor(Pred: HasCSSC, Types: {i32, i64})
315 .legalFor(Types: {v16i8, v8i16, v4i32, v2i64, v2p0, v8i8, v4i16, v2i32})
316 .customIf(Predicate: [=](const LegalityQuery &Q) {
317 // TODO: Fix suboptimal codegen for 128+ bit types.
318 LLT SrcTy = Q.Types[0];
319 return SrcTy.isScalar() && SrcTy.getSizeInBits() < 128;
320 })
321 .widenScalarIf(
322 Predicate: [=](const LegalityQuery &Query) { return Query.Types[0] == v4s8; },
323 Mutation: [=](const LegalityQuery &Query) { return std::make_pair(x: 0, y: v4i16); })
324 .widenScalarIf(
325 Predicate: [=](const LegalityQuery &Query) { return Query.Types[0] == v2s16; },
326 Mutation: [=](const LegalityQuery &Query) { return std::make_pair(x: 0, y: v2i32); })
327 .clampNumElements(TypeIdx: 0, MinTy: v8s8, MaxTy: v16s8)
328 .clampNumElements(TypeIdx: 0, MinTy: v4s16, MaxTy: v8s16)
329 .clampNumElements(TypeIdx: 0, MinTy: v2s32, MaxTy: v4s32)
330 .clampNumElements(TypeIdx: 0, MinTy: v2s64, MaxTy: v2s64)
331 .moreElementsToNextPow2(TypeIdx: 0)
332 .lower();
333
334 getActionDefinitionsBuilder(
335 Opcodes: {G_ABDS, G_ABDU, G_UAVGFLOOR, G_UAVGCEIL, G_SAVGFLOOR, G_SAVGCEIL})
336 .legalFor(Types: {v8i8, v16i8, v4i16, v8i16, v2i32, v4i32})
337 .lower();
338
339 getActionDefinitionsBuilder(
340 Opcodes: {G_SADDE, G_SSUBE, G_UADDE, G_USUBE, G_SADDO, G_SSUBO, G_UADDO, G_USUBO})
341 .legalFor(Types: {{i32, i32}, {i64, i32}})
342 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s64)
343 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s64)
344 .widenScalarToNextPow2(TypeIdx: 0)
345 .lower();
346
347 getActionDefinitionsBuilder(Opcodes: {G_FSHL, G_FSHR})
348 .customFor(Types: {{i32, i32}, {i32, i64}, {i64, i64}})
349 .lower();
350
351 getActionDefinitionsBuilder(Opcode: G_ROTR)
352 .legalFor(Types: {{i32, i64}, {i64, i64}})
353 .customIf(Predicate: [=](const LegalityQuery &Q) {
354 return Q.Types[0].isScalar() && Q.Types[1].getScalarSizeInBits() < 64;
355 })
356 .lower();
357 getActionDefinitionsBuilder(Opcode: G_ROTL).lower();
358
359 getActionDefinitionsBuilder(Opcodes: {G_SBFX, G_UBFX})
360 .customFor(Types: {{s32, s32}, {s64, s64}});
361
362 auto always = [=](const LegalityQuery &Q) { return true; };
363 getActionDefinitionsBuilder(Opcode: G_CTPOP)
364 .legalFor(Pred: HasCSSC, Types: {{i32, i32}, {i64, i64}})
365 .legalFor(Types: {{v8i8, v8i8}, {v16i8, v16i8}})
366 .customFor(Pred: !HasCSSC, Types: {{s32, s32}, {s64, s64}})
367 .customFor(Types: {{s128, s128},
368 {v4s16, v4s16},
369 {v8s16, v8s16},
370 {v2s32, v2s32},
371 {v4s32, v4s32},
372 {v2s64, v2s64}})
373 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s128)
374 .widenScalarToNextPow2(TypeIdx: 0)
375 .widenScalarOrEltToNextPow2OrMinSize(TypeIdx: 0, MinSize: 8)
376 .minScalarEltSameAsIf(Predicate: always, TypeIdx: 1, LargeTypeIdx: 0)
377 .maxScalarEltSameAsIf(Predicate: always, TypeIdx: 1, SmallTypeIdx: 0)
378 .clampNumElements(TypeIdx: 0, MinTy: v8s8, MaxTy: v16s8)
379 .clampNumElements(TypeIdx: 0, MinTy: v4s16, MaxTy: v8s16)
380 .clampNumElements(TypeIdx: 0, MinTy: v2s32, MaxTy: v4s32)
381 .clampNumElements(TypeIdx: 0, MinTy: v2s64, MaxTy: v2s64)
382 .moreElementsToNextPow2(TypeIdx: 0)
383 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 0, Size: 64), TypeIdx: 0);
384
385 getActionDefinitionsBuilder(Opcodes: {G_CTLZ, G_CTLS})
386 .legalFor(Types: {{i32, i32},
387 {i64, i64},
388 {v8i8, v8i8},
389 {v16i8, v16i8},
390 {v4i16, v4i16},
391 {v8i16, v8i16},
392 {v2i32, v2i32},
393 {v4i32, v4i32}})
394 .widenScalarToNextPow2(TypeIdx: 1, /*Min=*/MinSize: 32)
395 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s64)
396 .widenScalarOrEltToNextPow2OrMinSize(TypeIdx: 1, /*Min=*/MinSize: 8)
397 .clampNumElements(TypeIdx: 0, MinTy: v8s8, MaxTy: v16s8)
398 .clampNumElements(TypeIdx: 0, MinTy: v4s16, MaxTy: v8s16)
399 .clampNumElements(TypeIdx: 0, MinTy: v2s32, MaxTy: v4s32)
400 .moreElementsToNextPow2(TypeIdx: 0)
401 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 0, Size: 32), TypeIdx: 0)
402 .scalarSameSizeAs(TypeIdx: 0, SameSizeIdx: 1);
403
404 getActionDefinitionsBuilder(Opcode: G_INSERT_SUBVECTOR).lower();
405
406 getActionDefinitionsBuilder(Opcode: G_CTLZ_ZERO_POISON).lower();
407
408 getActionDefinitionsBuilder(Opcode: G_CTTZ)
409 .lowerIf(Predicate: isVector(TypeIdx: 0))
410 .widenScalarToNextPow2(TypeIdx: 1, /*Min=*/MinSize: 32)
411 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s64)
412 .scalarSameSizeAs(TypeIdx: 0, SameSizeIdx: 1)
413 .legalFor(Pred: HasCSSC, Types: {s32, s64})
414 .customFor(Pred: !HasCSSC, Types: {s32, s64});
415
416 getActionDefinitionsBuilder(Opcode: G_CTTZ_ZERO_POISON).lower();
417
418 getActionDefinitionsBuilder(Opcode: G_BITREVERSE)
419 .legalFor(Types: {i32, i64, v8i8, v16i8})
420 .widenScalarToNextPow2(TypeIdx: 0, /*Min = */ MinSize: 32)
421 .widenScalarOrEltToNextPow2OrMinSize(TypeIdx: 0, MinSize: 8)
422 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s64)
423 .clampNumElements(TypeIdx: 0, MinTy: v8s8, MaxTy: v16s8)
424 .clampNumElements(TypeIdx: 0, MinTy: v4s16, MaxTy: v8s16)
425 .clampNumElements(TypeIdx: 0, MinTy: v2s32, MaxTy: v4s32)
426 .clampNumElements(TypeIdx: 0, MinTy: v2s64, MaxTy: v2s64)
427 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 0, Size: 64), TypeIdx: 0)
428 .moreElementsToNextPow2(TypeIdx: 0)
429 .lower();
430
431 getActionDefinitionsBuilder(Opcode: G_CLMUL).legalFor(Types: {v8i8, v16i8});
432
433 getActionDefinitionsBuilder(Opcode: G_BSWAP)
434 .legalFor(Types: {i32, i64, v4i16, v8i16, v2i32, v4i32, v2i64})
435 .widenScalarOrEltToNextPow2(TypeIdx: 0, MinSize: 16)
436 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s64)
437 .clampNumElements(TypeIdx: 0, MinTy: v4s16, MaxTy: v8s16)
438 .clampNumElements(TypeIdx: 0, MinTy: v2s32, MaxTy: v4s32)
439 .clampNumElements(TypeIdx: 0, MinTy: v2s64, MaxTy: v2s64)
440 .moreElementsToNextPow2(TypeIdx: 0);
441
442 getActionDefinitionsBuilder(Opcodes: {G_UADDSAT, G_SADDSAT, G_USUBSAT, G_SSUBSAT})
443 .legalFor(Types: {v8i8, v16i8, v4i16, v8i16, v2i32, v4i32, v2i64})
444 .legalFor(Pred: HasSVE, Types: {nxv16i8, nxv8i16, nxv4i32, nxv2i64})
445 .clampNumElements(TypeIdx: 0, MinTy: v8s8, MaxTy: v16s8)
446 .clampNumElements(TypeIdx: 0, MinTy: v4s16, MaxTy: v8s16)
447 .clampNumElements(TypeIdx: 0, MinTy: v2s32, MaxTy: v4s32)
448 .clampMaxNumElements(TypeIdx: 0, EltTy: s64, MaxElements: 2)
449 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 0, Size: 64), TypeIdx: 0)
450 .moreElementsToNextPow2(TypeIdx: 0)
451 .lower();
452
453 getActionDefinitionsBuilder(
454 Opcodes: {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FMA, G_FSQRT, G_FMAXNUM, G_FMINNUM,
455 G_FMAXIMUM, G_FMINIMUM, G_FCEIL, G_FFLOOR, G_FRINT, G_FNEARBYINT,
456 G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND, G_INTRINSIC_ROUNDEVEN})
457 .legalFor(Types: {f32, f64, v2f32, v4f32, v2f64})
458 .legalFor(Pred: HasFP16, Types: {f16, v4f16, v8f16})
459 .libcallFor(Types: {f128})
460 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 0, Size: 64), TypeIdx: 0)
461 .widenScalarIf(
462 Predicate: [=](const LegalityQuery &Q) {
463 return (!HasFP16 && Q.Types[0].getScalarType().isFloat16()) ||
464 Q.Types[0].getScalarType().isBFloat16();
465 },
466 Mutation: changeElementTo(TypeIdx: 0, Ty: f32))
467 .clampNumElements(TypeIdx: 0, MinTy: v4s16, MaxTy: v8s16)
468 .clampNumElements(TypeIdx: 0, MinTy: v2s32, MaxTy: v4s32)
469 .clampNumElements(TypeIdx: 0, MinTy: v2s64, MaxTy: v2s64)
470 .moreElementsToNextPow2(TypeIdx: 0);
471
472 getActionDefinitionsBuilder(Opcodes: {G_FABS, G_FNEG})
473 .legalFor(Types: {f32, f64, v2f32, v4f32, v2f64})
474 .legalFor(Pred: HasFP16, Types: {f16, bf16, v4f16, v4bf16, v8f16, v8bf16})
475 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 0, Size: 64), TypeIdx: 0)
476 .lowerIf(Predicate: scalarOrEltWiderThan(TypeIdx: 0, Size: 64))
477 .clampNumElements(TypeIdx: 0, MinTy: v4s16, MaxTy: v8s16)
478 .clampNumElements(TypeIdx: 0, MinTy: v2s32, MaxTy: v4s32)
479 .clampNumElements(TypeIdx: 0, MinTy: v2s64, MaxTy: v2s64)
480 .moreElementsToNextPow2(TypeIdx: 0)
481 .lowerFor(Types: {f16, bf16, v4f16, v4bf16, v8f16, v8bf16});
482
483 getActionDefinitionsBuilder(Opcodes: {G_FREM, G_FCOS, G_FSIN, G_FPOW, G_FLOG, G_FLOG2,
484 G_FLOG10, G_FTAN, G_FEXP, G_FEXP2, G_FEXP10,
485 G_FACOS, G_FASIN, G_FATAN, G_FATAN2, G_FCOSH,
486 G_FSINH, G_FTANH, G_FMODF})
487 .libcallFor(Types: {f32, f64, f128})
488 .widenScalarFor(Types: {f16, bf16}, Mutation: changeElementTo(TypeIdx: 0, Ty: f32))
489 .scalarize(TypeIdx: 0);
490 getActionDefinitionsBuilder(Opcodes: {G_FPOWI, G_FLDEXP})
491 .libcallFor(Types: {{f32, i32}, {f64, i32}, {f128, i32}})
492 .widenScalarFor(Types: {f16, bf16}, Mutation: changeElementTo(TypeIdx: 0, Ty: f32))
493 .scalarize(TypeIdx: 0);
494
495 getActionDefinitionsBuilder(Opcodes: {G_LROUND, G_INTRINSIC_LRINT})
496 .legalFor(Types: {{i32, f32}, {i32, f64}, {i64, f32}, {i64, f64}})
497 .legalFor(Pred: HasFP16, Types: {{i32, f16}, {i64, f16}})
498 .minScalar(TypeIdx: 1, Ty: s32)
499 .libcallFor(Types: {{s64, s128}})
500 .lower();
501 getActionDefinitionsBuilder(Opcodes: {G_LLROUND, G_INTRINSIC_LLRINT})
502 .legalFor(Types: {{i64, f32}, {i64, f64}})
503 .legalFor(Pred: HasFP16, Types: {{i64, f16}})
504 .minScalar(TypeIdx: 0, Ty: s64)
505 .minScalar(TypeIdx: 1, Ty: s32)
506 .libcallFor(Types: {{s64, s128}})
507 .lower();
508
509 // TODO: Custom legalization for mismatched types.
510 getActionDefinitionsBuilder(Opcode: G_FCOPYSIGN)
511 .moreElementsIf(
512 Predicate: [](const LegalityQuery &Query) { return Query.Types[0].isScalar(); },
513 Mutation: [=](const LegalityQuery &Query) {
514 const LLT Ty = Query.Types[0];
515 return std::pair(0, LLT::fixed_vector(NumElements: Ty == s16 ? 4 : 2, ScalarTy: Ty));
516 })
517 .lower();
518
519 getActionDefinitionsBuilder(Opcode: G_FMAD).lower();
520
521 for (unsigned Op : {G_SEXTLOAD, G_ZEXTLOAD}) {
522 auto &Actions = getActionDefinitionsBuilder(Opcode: Op);
523
524 if (Op == G_SEXTLOAD)
525 Actions.lowerIf(Predicate: atomicOrderingAtLeastOrStrongerThan(MMOIdx: 0, Ordering: AtomicOrdering::Unordered));
526
527 // Atomics have zero extending behavior.
528 Actions
529 .legalForTypesWithMemDesc(TypesAndMemDesc: {{.Type0: s32, .Type1: p0, .MemTy: s8, .Align: 8},
530 {.Type0: s32, .Type1: p0, .MemTy: s16, .Align: 8},
531 {.Type0: s32, .Type1: p0, .MemTy: s32, .Align: 8},
532 {.Type0: s64, .Type1: p0, .MemTy: s8, .Align: 2},
533 {.Type0: s64, .Type1: p0, .MemTy: s16, .Align: 2},
534 {.Type0: s64, .Type1: p0, .MemTy: s32, .Align: 4},
535 {.Type0: s64, .Type1: p0, .MemTy: s64, .Align: 8},
536 {.Type0: p0, .Type1: p0, .MemTy: s64, .Align: 8},
537 {.Type0: v2s32, .Type1: p0, .MemTy: s64, .Align: 8}})
538 .widenScalarToNextPow2(TypeIdx: 0)
539 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s64)
540 // TODO: We could support sum-of-pow2's but the lowering code doesn't know
541 // how to do that yet.
542 .unsupportedIfMemSizeNotPow2()
543 // Lower anything left over into G_*EXT and G_LOAD
544 .lower();
545 }
546
547 auto IsPtrVecPred = [=](const LegalityQuery &Query) {
548 const LLT &ValTy = Query.Types[0];
549 return ValTy.isPointerVector() && ValTy.getAddressSpace() == 0;
550 };
551
552 getActionDefinitionsBuilder(Opcode: G_LOAD)
553 .customIf(Predicate: [=](const LegalityQuery &Query) {
554 return HasRCPC3 && Query.Types[0] == s128 &&
555 Query.MMODescrs[0].Ordering == AtomicOrdering::Acquire;
556 })
557 .customIf(Predicate: [=](const LegalityQuery &Query) {
558 return Query.Types[0] == s128 &&
559 Query.MMODescrs[0].Ordering != AtomicOrdering::NotAtomic;
560 })
561 .legalForTypesWithMemDesc(TypesAndMemDesc: {{.Type0: s8, .Type1: p0, .MemTy: s8, .Align: 8},
562 {.Type0: s16, .Type1: p0, .MemTy: s16, .Align: 8},
563 {.Type0: s32, .Type1: p0, .MemTy: s32, .Align: 8},
564 {.Type0: s64, .Type1: p0, .MemTy: s64, .Align: 8},
565 {.Type0: p0, .Type1: p0, .MemTy: s64, .Align: 8},
566 {.Type0: s128, .Type1: p0, .MemTy: s128, .Align: 8},
567 {.Type0: v8s8, .Type1: p0, .MemTy: s64, .Align: 8},
568 {.Type0: v16s8, .Type1: p0, .MemTy: s128, .Align: 8},
569 {.Type0: v4s16, .Type1: p0, .MemTy: s64, .Align: 8},
570 {.Type0: v8s16, .Type1: p0, .MemTy: s128, .Align: 8},
571 {.Type0: v2s32, .Type1: p0, .MemTy: s64, .Align: 8},
572 {.Type0: v4s32, .Type1: p0, .MemTy: s128, .Align: 8},
573 {.Type0: v2s64, .Type1: p0, .MemTy: s128, .Align: 8}})
574 // These extends are also legal
575 .legalForTypesWithMemDesc(
576 TypesAndMemDesc: {{.Type0: s32, .Type1: p0, .MemTy: s8, .Align: 8}, {.Type0: s32, .Type1: p0, .MemTy: s16, .Align: 8}, {.Type0: s64, .Type1: p0, .MemTy: s32, .Align: 8}})
577 .legalForTypesWithMemDesc(TypesAndMemDesc: {
578 // SVE vscale x 128 bit base sizes
579 {.Type0: nxv16s8, .Type1: p0, .MemTy: nxv16s8, .Align: 8},
580 {.Type0: nxv8s16, .Type1: p0, .MemTy: nxv8s16, .Align: 8},
581 {.Type0: nxv4s32, .Type1: p0, .MemTy: nxv4s32, .Align: 8},
582 {.Type0: nxv2s64, .Type1: p0, .MemTy: nxv2s64, .Align: 8},
583 })
584 .widenScalarToNextPow2(TypeIdx: 0, /* MinSize = */ 8)
585 .clampMaxNumElements(TypeIdx: 0, EltTy: s8, MaxElements: 16)
586 .clampMaxNumElements(TypeIdx: 0, EltTy: s16, MaxElements: 8)
587 .clampMaxNumElements(TypeIdx: 0, EltTy: s32, MaxElements: 4)
588 .clampMaxNumElements(TypeIdx: 0, EltTy: s64, MaxElements: 2)
589 .clampMaxNumElements(TypeIdx: 0, EltTy: p0, MaxElements: 2)
590 .lowerIfMemSizeNotByteSizePow2()
591 .clampScalar(TypeIdx: 0, MinTy: s8, MaxTy: s64)
592 .narrowScalarIf(
593 Predicate: [=](const LegalityQuery &Query) {
594 // Clamp extending load results to 32-bits.
595 return Query.Types[0].isScalar() &&
596 Query.Types[0] != Query.MMODescrs[0].MemoryTy &&
597 Query.Types[0].getSizeInBits() > 32;
598 },
599 Mutation: changeTo(TypeIdx: 0, Ty: i32))
600 // TODO: Use BITCAST for v2i8, v2i16 after G_TRUNC gets sorted out
601 .bitcastIf(Predicate: typeInSet(TypeIdx: 0, TypesInit: {v4s8}),
602 Mutation: [=](const LegalityQuery &Query) {
603 const LLT VecTy = Query.Types[0];
604 return std::pair(0, LLT::integer(SizeInBits: VecTy.getSizeInBits()));
605 })
606 .customIf(Predicate: IsPtrVecPred)
607 .scalarizeIf(Predicate: typeInSet(TypeIdx: 0, TypesInit: {v2s16, v2s8}), TypeIdx: 0)
608 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 0, Size: 64), TypeIdx: 0);
609
610 getActionDefinitionsBuilder(Opcode: G_STORE)
611 .customIf(Predicate: [=](const LegalityQuery &Query) {
612 return HasRCPC3 && Query.Types[0] == s128 &&
613 Query.MMODescrs[0].Ordering == AtomicOrdering::Release;
614 })
615 .customIf(Predicate: [=](const LegalityQuery &Query) {
616 return Query.Types[0] == s128 &&
617 Query.MMODescrs[0].Ordering != AtomicOrdering::NotAtomic;
618 })
619 .widenScalarIf(
620 Predicate: all(P0: scalarNarrowerThan(TypeIdx: 0, Size: 32),
621 P1: atomicOrderingAtLeastOrStrongerThan(MMOIdx: 0, Ordering: AtomicOrdering::Release)),
622 Mutation: changeElementSizeTo(TypeIdx: 0, NewTy: s32))
623 .legalForTypesWithMemDesc(
624 TypesAndMemDesc: {{.Type0: s8, .Type1: p0, .MemTy: s8, .Align: 8}, {.Type0: s16, .Type1: p0, .MemTy: s8, .Align: 8}, // truncstorei8 from s16
625 {.Type0: s32, .Type1: p0, .MemTy: s8, .Align: 8}, // truncstorei8 from s32
626 {.Type0: s64, .Type1: p0, .MemTy: s8, .Align: 8}, // truncstorei8 from s64
627 {.Type0: s16, .Type1: p0, .MemTy: s16, .Align: 8}, {.Type0: s32, .Type1: p0, .MemTy: s16, .Align: 8}, // truncstorei16 from s32
628 {.Type0: s64, .Type1: p0, .MemTy: s16, .Align: 8}, // truncstorei16 from s64
629 {.Type0: s32, .Type1: p0, .MemTy: s8, .Align: 8}, {.Type0: s32, .Type1: p0, .MemTy: s16, .Align: 8}, {.Type0: s32, .Type1: p0, .MemTy: s32, .Align: 8},
630 {.Type0: s64, .Type1: p0, .MemTy: s64, .Align: 8}, {.Type0: s64, .Type1: p0, .MemTy: s32, .Align: 8}, // truncstorei32 from s64
631 {.Type0: p0, .Type1: p0, .MemTy: s64, .Align: 8}, {.Type0: s128, .Type1: p0, .MemTy: s128, .Align: 8}, {.Type0: v16s8, .Type1: p0, .MemTy: s128, .Align: 8},
632 {.Type0: v8s8, .Type1: p0, .MemTy: s64, .Align: 8}, {.Type0: v4s16, .Type1: p0, .MemTy: s64, .Align: 8}, {.Type0: v8s16, .Type1: p0, .MemTy: s128, .Align: 8},
633 {.Type0: v2s32, .Type1: p0, .MemTy: s64, .Align: 8}, {.Type0: v4s32, .Type1: p0, .MemTy: s128, .Align: 8}, {.Type0: v2s64, .Type1: p0, .MemTy: s128, .Align: 8}})
634 .legalForTypesWithMemDesc(TypesAndMemDesc: {
635 // SVE vscale x 128 bit base sizes
636 // TODO: Add nxv2p0. Consider bitcastIf.
637 // See #92130
638 // https://github.com/llvm/llvm-project/pull/92130#discussion_r1616888461
639 {.Type0: nxv16s8, .Type1: p0, .MemTy: nxv16s8, .Align: 8},
640 {.Type0: nxv8s16, .Type1: p0, .MemTy: nxv8s16, .Align: 8},
641 {.Type0: nxv4s32, .Type1: p0, .MemTy: nxv4s32, .Align: 8},
642 {.Type0: nxv2s64, .Type1: p0, .MemTy: nxv2s64, .Align: 8},
643 })
644 .clampScalar(TypeIdx: 0, MinTy: s8, MaxTy: s64)
645 .minScalarOrElt(TypeIdx: 0, Ty: s8)
646 .lowerIf(Predicate: [=](const LegalityQuery &Query) {
647 return Query.Types[0].isScalar() &&
648 Query.Types[0] != Query.MMODescrs[0].MemoryTy;
649 })
650 // Maximum: sN * k = 128
651 .clampMaxNumElements(TypeIdx: 0, EltTy: s8, MaxElements: 16)
652 .clampMaxNumElements(TypeIdx: 0, EltTy: s16, MaxElements: 8)
653 .clampMaxNumElements(TypeIdx: 0, EltTy: s32, MaxElements: 4)
654 .clampMaxNumElements(TypeIdx: 0, EltTy: s64, MaxElements: 2)
655 .clampMaxNumElements(TypeIdx: 0, EltTy: p0, MaxElements: 2)
656 .lowerIfMemSizeNotPow2()
657 // TODO: Use BITCAST for v2i8, v2i16 after G_TRUNC gets sorted out
658 .bitcastIf(Predicate: all(P0: typeInSet(TypeIdx: 0, TypesInit: {v4s8}),
659 P1: LegalityPredicate([=](const LegalityQuery &Query) {
660 return Query.Types[0].getSizeInBits() ==
661 Query.MMODescrs[0].MemoryTy.getSizeInBits();
662 })),
663 Mutation: [=](const LegalityQuery &Query) {
664 const LLT VecTy = Query.Types[0];
665 return std::pair(0, LLT::integer(SizeInBits: VecTy.getSizeInBits()));
666 })
667 .customIf(Predicate: IsPtrVecPred)
668 .scalarizeIf(Predicate: typeInSet(TypeIdx: 0, TypesInit: {v2s16, v2s8}), TypeIdx: 0)
669 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 0, Size: 64), TypeIdx: 0)
670 .lower();
671
672 getActionDefinitionsBuilder(Opcode: G_INDEXED_STORE)
673 // Idx 0 == Ptr, Idx 1 == Val
674 // TODO: we can implement legalizations but as of now these are
675 // generated in a very specific way.
676 .legalForTypesWithMemDesc(TypesAndMemDesc: {
677 {.Type0: p0, .Type1: s8, .MemTy: s8, .Align: 8},
678 {.Type0: p0, .Type1: s16, .MemTy: s16, .Align: 8},
679 {.Type0: p0, .Type1: s32, .MemTy: s8, .Align: 8},
680 {.Type0: p0, .Type1: s32, .MemTy: s16, .Align: 8},
681 {.Type0: p0, .Type1: s32, .MemTy: s32, .Align: 8},
682 {.Type0: p0, .Type1: s64, .MemTy: s64, .Align: 8},
683 {.Type0: p0, .Type1: p0, .MemTy: p0, .Align: 8},
684 {.Type0: p0, .Type1: v8s8, .MemTy: v8s8, .Align: 8},
685 {.Type0: p0, .Type1: v16s8, .MemTy: v16s8, .Align: 8},
686 {.Type0: p0, .Type1: v4s16, .MemTy: v4s16, .Align: 8},
687 {.Type0: p0, .Type1: v8s16, .MemTy: v8s16, .Align: 8},
688 {.Type0: p0, .Type1: v2s32, .MemTy: v2s32, .Align: 8},
689 {.Type0: p0, .Type1: v4s32, .MemTy: v4s32, .Align: 8},
690 {.Type0: p0, .Type1: v2s64, .MemTy: v2s64, .Align: 8},
691 {.Type0: p0, .Type1: v2p0, .MemTy: v2p0, .Align: 8},
692 {.Type0: p0, .Type1: s128, .MemTy: s128, .Align: 8},
693 })
694 .unsupported();
695
696 auto IndexedLoadBasicPred = [=](const LegalityQuery &Query) {
697 LLT LdTy = Query.Types[0];
698 LLT PtrTy = Query.Types[1];
699 if (!llvm::is_contained(Range: PackedVectorAllTypesVec, Element: LdTy) &&
700 !llvm::is_contained(Range: ScalarAndPtrTypesVec, Element: LdTy) && LdTy != s128)
701 return false;
702 if (PtrTy != p0)
703 return false;
704 return true;
705 };
706 getActionDefinitionsBuilder(Opcode: G_INDEXED_LOAD)
707 .unsupportedIf(
708 Predicate: atomicOrderingAtLeastOrStrongerThan(MMOIdx: 0, Ordering: AtomicOrdering::Unordered))
709 .legalIf(Predicate: IndexedLoadBasicPred)
710 .unsupported();
711 getActionDefinitionsBuilder(Opcodes: {G_INDEXED_SEXTLOAD, G_INDEXED_ZEXTLOAD})
712 .unsupportedIf(
713 Predicate: atomicOrderingAtLeastOrStrongerThan(MMOIdx: 0, Ordering: AtomicOrdering::Unordered))
714 .legalIf(Predicate: all(P0: typeInSet(TypeIdx: 0, TypesInit: {s16, s32, s64}),
715 P1: LegalityPredicate([=](const LegalityQuery &Q) {
716 LLT LdTy = Q.Types[0];
717 LLT PtrTy = Q.Types[1];
718 LLT MemTy = Q.MMODescrs[0].MemoryTy;
719 if (PtrTy != p0)
720 return false;
721 if (LdTy == s16)
722 return MemTy == s8;
723 if (LdTy == s32)
724 return MemTy == s8 || MemTy == s16;
725 if (LdTy == s64)
726 return MemTy == s8 || MemTy == s16 || MemTy == s32;
727 return false;
728 })))
729 .unsupported();
730
731 // Constants
732 getActionDefinitionsBuilder(Opcode: G_CONSTANT)
733 .legalFor(Types: {p0, s8, s16, s32, s64})
734 .widenScalarToNextPow2(TypeIdx: 0)
735 .clampScalar(TypeIdx: 0, MinTy: s8, MaxTy: s64);
736 getActionDefinitionsBuilder(Opcode: G_FCONSTANT)
737 .legalFor(Types: {s16, s32, s64, s128});
738
739 // FIXME: fix moreElementsToNextPow2
740 getActionDefinitionsBuilder(Opcode: G_ICMP)
741 .legalFor(Types: {{i32, i32}, {i32, i64}, {i32, p0}})
742 .widenScalarOrEltToNextPow2(TypeIdx: 1)
743 .minScalarOrElt(TypeIdx: 1, Ty: s8)
744 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s64)
745 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32)
746 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 1, Size: 64), TypeIdx: 1)
747 .minScalarEltSameAsIf(
748 Predicate: [=](const LegalityQuery &Query) {
749 const LLT &Ty = Query.Types[0];
750 const LLT &SrcTy = Query.Types[1];
751 return Ty.isVector() && !SrcTy.isPointerVector() &&
752 Ty.getElementType() != SrcTy.getElementType();
753 },
754 TypeIdx: 0, LargeTypeIdx: 1)
755 .minScalarOrEltIf(
756 Predicate: [=](const LegalityQuery &Query) { return Query.Types[1] == v2s16; },
757 TypeIdx: 1, Ty: s32)
758 .minScalarOrEltIf(
759 Predicate: [=](const LegalityQuery &Query) {
760 return Query.Types[1].isPointerVector();
761 },
762 TypeIdx: 0, Ty: s64)
763 .moreElementsToNextPow2(TypeIdx: 1)
764 .clampNumElements(TypeIdx: 1, MinTy: v8s8, MaxTy: v16s8)
765 .clampNumElements(TypeIdx: 1, MinTy: v4s16, MaxTy: v8s16)
766 .clampNumElements(TypeIdx: 1, MinTy: v2s32, MaxTy: v4s32)
767 .clampNumElements(TypeIdx: 1, MinTy: v2s64, MaxTy: v2s64)
768 .clampNumElements(TypeIdx: 1, MinTy: v2p0, MaxTy: v2p0)
769 .customIf(Predicate: isVector(TypeIdx: 0));
770
771 getActionDefinitionsBuilder(Opcode: G_FCMP)
772 .legalFor(Types: {{i32, f32},
773 {i32, f64},
774 {v4i32, v4f32},
775 {v2i32, v2f32},
776 {v2i64, v2f64}})
777 .legalFor(Pred: HasFP16, Types: {{i32, f16}, {v4i16, v4f16}, {v8i16, v8f16}})
778 .widenScalarOrEltToNextPow2(TypeIdx: 1)
779 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32)
780 .widenScalarIf(
781 Predicate: [=](const LegalityQuery &Q) {
782 return (!HasFP16 && Q.Types[1].getScalarType().isFloat16()) ||
783 Q.Types[1].getScalarType().isBFloat16();
784 },
785 Mutation: changeElementTo(TypeIdx: 1, Ty: f32))
786 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 1, Size: 64), TypeIdx: 1)
787 .minScalarEltSameAsIf(
788 Predicate: [=](const LegalityQuery &Query) {
789 const LLT &Ty = Query.Types[0];
790 const LLT &SrcTy = Query.Types[1];
791 return Ty.isVector() && !SrcTy.isPointerVector() &&
792 Ty.getElementType() != SrcTy.getElementType();
793 },
794 TypeIdx: 0, LargeTypeIdx: 1)
795 .clampNumElements(TypeIdx: 1, MinTy: v4s16, MaxTy: v8s16)
796 .clampNumElements(TypeIdx: 1, MinTy: v2s32, MaxTy: v4s32)
797 .clampMaxNumElements(TypeIdx: 1, EltTy: s64, MaxElements: 2)
798 .moreElementsToNextPow2(TypeIdx: 1)
799 .libcallFor(Types: {{s32, s128}});
800
801 // Extensions
802 auto ExtLegalFunc = [=](const LegalityQuery &Query) {
803 unsigned DstSize = Query.Types[0].getSizeInBits();
804
805 // Handle legal vectors using legalFor
806 if (Query.Types[0].isVector())
807 return false;
808
809 if (DstSize < 8 || DstSize >= 128 || !isPowerOf2_32(Value: DstSize))
810 return false; // Extending to a scalar s128 needs narrowing.
811
812 const LLT &SrcTy = Query.Types[1];
813
814 // Make sure we fit in a register otherwise. Don't bother checking that
815 // the source type is below 128 bits. We shouldn't be allowing anything
816 // through which is wider than the destination in the first place.
817 unsigned SrcSize = SrcTy.getSizeInBits();
818 if (SrcSize < 8 || !isPowerOf2_32(Value: SrcSize))
819 return false;
820
821 return true;
822 };
823 getActionDefinitionsBuilder(Opcodes: {G_ZEXT, G_SEXT, G_ANYEXT})
824 .legalIf(Predicate: ExtLegalFunc)
825 .legalFor(Types: {{v8s16, v8s8}, {v4s32, v4s16}, {v2s64, v2s32}})
826 .clampScalar(TypeIdx: 0, MinTy: s64, MaxTy: s64) // Just for s128, others are handled above.
827 .moreElementsToNextPow2(TypeIdx: 0)
828 .clampMaxNumElements(TypeIdx: 1, EltTy: s8, MaxElements: 8)
829 .clampMaxNumElements(TypeIdx: 1, EltTy: s16, MaxElements: 4)
830 .clampMaxNumElements(TypeIdx: 1, EltTy: s32, MaxElements: 2)
831 // Tries to convert a large EXTEND into two smaller EXTENDs
832 .lowerIf(Predicate: [=](const LegalityQuery &Query) {
833 return (Query.Types[0].getScalarSizeInBits() >
834 Query.Types[1].getScalarSizeInBits() * 2) &&
835 Query.Types[0].isVector() &&
836 (Query.Types[1].getScalarSizeInBits() == 8 ||
837 Query.Types[1].getScalarSizeInBits() == 16);
838 })
839 .clampMinNumElements(TypeIdx: 1, EltTy: s8, MinElements: 8)
840 .clampMinNumElements(TypeIdx: 1, EltTy: s16, MinElements: 4)
841 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 0, Size: 64), TypeIdx: 0);
842
843 getActionDefinitionsBuilder(Opcode: G_TRUNC)
844 .legalFor(Types: {{v8s8, v8s16}, {v4s16, v4s32}, {v2s32, v2s64}})
845 .moreElementsToNextPow2(TypeIdx: 0)
846 .clampMaxNumElements(TypeIdx: 0, EltTy: s8, MaxElements: 8)
847 .clampMaxNumElements(TypeIdx: 0, EltTy: s16, MaxElements: 4)
848 .clampMaxNumElements(TypeIdx: 0, EltTy: s32, MaxElements: 2)
849 .minScalarOrEltIf(
850 Predicate: [=](const LegalityQuery &Query) { return Query.Types[0].isVector(); },
851 TypeIdx: 0, Ty: s8)
852 .lowerIf(Predicate: [=](const LegalityQuery &Query) {
853 LLT DstTy = Query.Types[0];
854 LLT SrcTy = Query.Types[1];
855 return DstTy.isVector() && SrcTy.getSizeInBits() > 128 &&
856 DstTy.getScalarSizeInBits() * 2 <= SrcTy.getScalarSizeInBits();
857 })
858 .clampMinNumElements(TypeIdx: 0, EltTy: s8, MinElements: 8)
859 .clampMinNumElements(TypeIdx: 0, EltTy: s16, MinElements: 4)
860 .alwaysLegal();
861
862 getActionDefinitionsBuilder(Opcodes: {G_TRUNC_SSAT_S, G_TRUNC_SSAT_U, G_TRUNC_USAT_U})
863 .legalFor(Types: {{v8i8, v8i16}, {v4i16, v4i32}, {v2i32, v2i64}})
864 .clampNumElements(TypeIdx: 0, MinTy: v8s8, MaxTy: v8s8)
865 .clampNumElements(TypeIdx: 0, MinTy: v4s16, MaxTy: v4s16)
866 .clampNumElements(TypeIdx: 0, MinTy: v2s32, MaxTy: v2s32)
867 .lower();
868
869 getActionDefinitionsBuilder(Opcode: G_SEXT_INREG)
870 .legalFor(Types: {i32, i64, v8i8, v16i8, v4i16, v8i16, v2i32, v4i32, v2i64})
871 .maxScalar(TypeIdx: 0, Ty: s64)
872 .clampNumElements(TypeIdx: 0, MinTy: v8s8, MaxTy: v16s8)
873 .clampNumElements(TypeIdx: 0, MinTy: v4s16, MaxTy: v8s16)
874 .clampNumElements(TypeIdx: 0, MinTy: v2s32, MaxTy: v4s32)
875 .clampMaxNumElements(TypeIdx: 0, EltTy: s64, MaxElements: 2)
876 .lower();
877
878 // FP conversions
879 getActionDefinitionsBuilder(Opcode: G_FPTRUNC)
880 .legalFor(
881 Types: {{f16, f32}, {f16, f64}, {f32, f64}, {v4f16, v4f32}, {v2f32, v2f64}})
882 .legalFor(Pred: ST.hasBF16(), Types: {{bf16, f32}, {v4bf16, v4f32}})
883 .libcallFor(Types: {{f16, f128}, {f32, f128}, {f64, f128}})
884 .moreElementsToNextPow2(TypeIdx: 1)
885 .customIf(Predicate: [](const LegalityQuery &Q) {
886 LLT DstTy = Q.Types[0];
887 LLT SrcTy = Q.Types[1];
888 return SrcTy.getScalarSizeInBits() == 64 &&
889 DstTy.getScalarSizeInBits() == 16;
890 })
891 .lowerFor(Types: {{bf16, f32}, {v4bf16, v4f32}})
892 // Clamp based on input
893 .clampNumElements(TypeIdx: 1, MinTy: v4s32, MaxTy: v4s32)
894 .clampNumElements(TypeIdx: 1, MinTy: v2s64, MaxTy: v2s64)
895 .scalarize(TypeIdx: 0);
896
897 getActionDefinitionsBuilder(Opcode: G_FPEXT)
898 .legalFor(Types: {{f32, f16},
899 {f64, f16},
900 {f32, bf16},
901 {f64, f32},
902 {v4f32, v4f16},
903 {v4f32, v4bf16},
904 {v2f64, v2f32}})
905 .libcallFor(Types: {{f128, f64}, {f128, f32}, {f128, f16}})
906 .moreElementsToNextPow2(TypeIdx: 0)
907 .widenScalarIf(
908 Predicate: [](const LegalityQuery &Q) {
909 LLT DstTy = Q.Types[0];
910 LLT SrcTy = Q.Types[1];
911 return SrcTy.isVector() && DstTy.isVector() &&
912 SrcTy.getScalarSizeInBits() == 16 &&
913 DstTy.getScalarSizeInBits() == 64;
914 },
915 Mutation: changeElementTo(TypeIdx: 1, Ty: f32))
916 .clampNumElements(TypeIdx: 0, MinTy: v4s32, MaxTy: v4s32)
917 .clampNumElements(TypeIdx: 0, MinTy: v2s64, MaxTy: v2s64)
918 .scalarize(TypeIdx: 0);
919
920 // Conversions
921 getActionDefinitionsBuilder(Opcodes: {G_FPTOSI, G_FPTOUI})
922 .legalFor(Types: {{i32, f32},
923 {i64, f32},
924 {i32, f64},
925 {i64, f64},
926 {v2i32, v2f32},
927 {v4i32, v4f32},
928 {v2i64, v2f64}})
929 .legalFor(Pred: HasFP16,
930 Types: {{i32, f16}, {i64, f16}, {v4i16, v4f16}, {v8i16, v8f16}})
931 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 0, Size: 64), TypeIdx: 0)
932 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 1, Size: 64), TypeIdx: 1)
933 // The range of a fp16 value fits into an i17, so we can lower the width
934 // to i64.
935 .narrowScalarIf(
936 Predicate: [=](const LegalityQuery &Query) {
937 return Query.Types[1] == f16 && Query.Types[0].getSizeInBits() > 64;
938 },
939 Mutation: changeTo(TypeIdx: 0, Ty: i64))
940 .moreElementsToNextPow2(TypeIdx: 0)
941 .widenScalarOrEltToNextPow2OrMinSize(TypeIdx: 0)
942 .minScalar(TypeIdx: 0, Ty: s32)
943 .widenScalarIf(
944 Predicate: [HasFP16](const LegalityQuery &Query) {
945 return (!HasFP16 && Query.Types[1].getScalarType().isFloat16()) ||
946 Query.Types[1].getScalarType().isBFloat16();
947 },
948 Mutation: changeElementTo(TypeIdx: 1, Ty: f32))
949 .widenScalarIf(
950 Predicate: [=](const LegalityQuery &Query) {
951 return Query.Types[0].getScalarSizeInBits() <= 64 &&
952 Query.Types[0].getScalarSizeInBits() >
953 Query.Types[1].getScalarSizeInBits();
954 },
955 Mutation: LegalizeMutations::changeElementSizeTo(TypeIdx: 1, FromTypeIdx: 0))
956 .widenScalarIf(
957 Predicate: [=](const LegalityQuery &Query) {
958 return Query.Types[1].getScalarSizeInBits() <= 64 &&
959 Query.Types[0].getScalarSizeInBits() <
960 Query.Types[1].getScalarSizeInBits();
961 },
962 Mutation: LegalizeMutations::changeElementSizeTo(TypeIdx: 0, FromTypeIdx: 1))
963 .clampNumElements(TypeIdx: 0, MinTy: v4s16, MaxTy: v8s16)
964 .clampNumElements(TypeIdx: 0, MinTy: v2s32, MaxTy: v4s32)
965 .clampMaxNumElements(TypeIdx: 0, EltTy: s64, MaxElements: 2)
966 .libcallFor(
967 Types: {{i32, f128}, {i64, f128}, {i128, f128}, {i128, f32}, {i128, f64}});
968
969 getActionDefinitionsBuilder(Opcodes: {G_FPTOSI_SAT, G_FPTOUI_SAT})
970 .legalFor(Types: {{i32, f32},
971 {i64, f32},
972 {i32, f64},
973 {i64, f64},
974 {v2i32, v2f32},
975 {v4i32, v4f32},
976 {v2i64, v2f64}})
977 .legalFor(
978 Pred: HasFP16,
979 Types: {{i16, f16}, {i32, f16}, {i64, f16}, {v4i16, v4f16}, {v8i16, v8f16}})
980 // Handle types larger than i64 by scalarizing/lowering.
981 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 0, Size: 64), TypeIdx: 0)
982 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 1, Size: 64), TypeIdx: 1)
983 // The range of a fp16 value fits into an i17, so we can lower the width
984 // to i64.
985 .narrowScalarIf(
986 Predicate: [=](const LegalityQuery &Query) {
987 return Query.Types[1] == f16 && Query.Types[0].getSizeInBits() > 64;
988 },
989 Mutation: changeTo(TypeIdx: 0, Ty: i64))
990 .lowerIf(Predicate: ::any(P0: scalarWiderThan(TypeIdx: 0, Size: 64), P1: scalarWiderThan(TypeIdx: 1, Size: 64)), Mutation: 0)
991 .moreElementsToNextPow2(TypeIdx: 0)
992 .widenScalarToNextPow2(TypeIdx: 0, /*MinSize=*/32)
993 .minScalar(TypeIdx: 0, Ty: s32)
994 .widenScalarIf(
995 Predicate: [HasFP16](const LegalityQuery &Query) {
996 return (!HasFP16 && Query.Types[1].getScalarType().isFloat16()) ||
997 Query.Types[1].getScalarType().isBFloat16();
998 },
999 Mutation: changeElementTo(TypeIdx: 1, Ty: f32))
1000 .widenScalarIf(
1001 Predicate: [=](const LegalityQuery &Query) {
1002 unsigned ITySize = Query.Types[0].getScalarSizeInBits();
1003 return (ITySize == 16 || ITySize == 32 || ITySize == 64) &&
1004 ITySize > Query.Types[1].getScalarSizeInBits();
1005 },
1006 Mutation: LegalizeMutations::changeElementSizeTo(TypeIdx: 1, FromTypeIdx: 0))
1007 .widenScalarIf(
1008 Predicate: [=](const LegalityQuery &Query) {
1009 unsigned FTySize = Query.Types[1].getScalarSizeInBits();
1010 return (FTySize == 16 || FTySize == 32 || FTySize == 64) &&
1011 Query.Types[0].getScalarSizeInBits() < FTySize;
1012 },
1013 Mutation: LegalizeMutations::changeElementSizeTo(TypeIdx: 0, FromTypeIdx: 1))
1014 .widenScalarOrEltToNextPow2(TypeIdx: 0)
1015 .clampNumElements(TypeIdx: 0, MinTy: v4s16, MaxTy: v8s16)
1016 .clampNumElements(TypeIdx: 0, MinTy: v2s32, MaxTy: v4s32)
1017 .clampMaxNumElements(TypeIdx: 0, EltTy: s64, MaxElements: 2);
1018
1019 getActionDefinitionsBuilder(Opcodes: {G_SITOFP, G_UITOFP})
1020 .legalFor(Types: {{f32, i32},
1021 {f64, i32},
1022 {f32, i64},
1023 {f64, i64},
1024 {v2f32, v2i32},
1025 {v4f32, v4i32},
1026 {v2f64, v2i64}})
1027 .legalFor(Pred: HasFP16,
1028 Types: {{f16, i32}, {f16, i64}, {v4f16, v4i16}, {v8f16, v8i16}})
1029 .unsupportedIf(Predicate: [&](const LegalityQuery &Query) {
1030 return Query.Types[0].getScalarType().isBFloat16();
1031 })
1032 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 1, Size: 64), TypeIdx: 1)
1033 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 0, Size: 64), TypeIdx: 0)
1034 .moreElementsToNextPow2(TypeIdx: 1)
1035 .widenScalarOrEltToNextPow2OrMinSize(TypeIdx: 1)
1036 .minScalar(TypeIdx: 1, Ty: f32)
1037 .lowerIf(Predicate: [](const LegalityQuery &Query) {
1038 return Query.Types[1].isVector() &&
1039 Query.Types[1].getScalarSizeInBits() == 64 &&
1040 Query.Types[0].getScalarSizeInBits() == 16;
1041 })
1042 .widenScalarOrEltToNextPow2OrMinSize(TypeIdx: 0, /*MinSize=*/HasFP16 ? 16 : 32)
1043 .scalarizeIf(
1044 // v2i64->v2f32 needs to scalarize to avoid double-rounding issues.
1045 Predicate: [](const LegalityQuery &Query) {
1046 return Query.Types[0].getScalarSizeInBits() == 32 &&
1047 Query.Types[1].getScalarSizeInBits() == 64;
1048 },
1049 TypeIdx: 0)
1050 .widenScalarIf(
1051 Predicate: [](const LegalityQuery &Query) {
1052 return Query.Types[1].getScalarSizeInBits() <= 64 &&
1053 Query.Types[0].getScalarSizeInBits() <
1054 Query.Types[1].getScalarSizeInBits();
1055 },
1056 Mutation: LegalizeMutations::changeElementSizeTo(TypeIdx: 0, FromTypeIdx: 1))
1057 .widenScalarIf(
1058 Predicate: [](const LegalityQuery &Query) {
1059 return Query.Types[0].getScalarSizeInBits() <= 64 &&
1060 Query.Types[0].getScalarSizeInBits() >
1061 Query.Types[1].getScalarSizeInBits();
1062 },
1063 Mutation: LegalizeMutations::changeElementSizeTo(TypeIdx: 1, FromTypeIdx: 0))
1064 .clampNumElements(TypeIdx: 0, MinTy: v4s16, MaxTy: v8s16)
1065 .clampNumElements(TypeIdx: 0, MinTy: v2s32, MaxTy: v4s32)
1066 .clampMaxNumElements(TypeIdx: 0, EltTy: s64, MaxElements: 2)
1067 .libcallFor(Types: {{f16, i128},
1068 {f32, i128},
1069 {f64, i128},
1070 {f128, i128},
1071 {f128, i32},
1072 {f128, i64}});
1073
1074 // Control-flow
1075 getActionDefinitionsBuilder(Opcode: G_BR).alwaysLegal();
1076 getActionDefinitionsBuilder(Opcode: G_BRCOND)
1077 .legalFor(Types: {s32})
1078 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
1079 getActionDefinitionsBuilder(Opcode: G_BRINDIRECT).legalFor(Types: {p0});
1080
1081 getActionDefinitionsBuilder(Opcode: G_SELECT)
1082 .legalFor(Types: {{s32, s32}, {s64, s32}, {p0, s32}})
1083 .widenScalarToNextPow2(TypeIdx: 0)
1084 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s64)
1085 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s32)
1086 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 0, Size: 64), TypeIdx: 0)
1087 .minScalarEltSameAsIf(Predicate: all(P0: isVector(TypeIdx: 0), P1: isVector(TypeIdx: 1)), TypeIdx: 1, LargeTypeIdx: 0)
1088 .lowerIf(Predicate: isVector(TypeIdx: 0));
1089
1090 // Pointer-handling
1091 getActionDefinitionsBuilder(Opcode: G_FRAME_INDEX).legalFor(Types: {p0});
1092
1093 if (TM.getCodeModel() == CodeModel::Small)
1094 getActionDefinitionsBuilder(Opcode: G_GLOBAL_VALUE).custom();
1095 else
1096 getActionDefinitionsBuilder(Opcode: G_GLOBAL_VALUE).legalFor(Types: {p0});
1097
1098 getActionDefinitionsBuilder(Opcode: G_PTRAUTH_GLOBAL_VALUE)
1099 .legalIf(Predicate: all(P0: typeIs(TypeIdx: 0, TypesInit: p0), P1: typeIs(TypeIdx: 1, TypesInit: p0)));
1100
1101 getActionDefinitionsBuilder(Opcode: G_PTRTOINT)
1102 .legalFor(Types: {{i64, p0}, {v2i64, v2p0}})
1103 .widenScalarToNextPow2(TypeIdx: 0, MinSize: 64)
1104 .clampScalar(TypeIdx: 0, MinTy: s64, MaxTy: s64)
1105 .clampMaxNumElements(TypeIdx: 0, EltTy: s64, MaxElements: 2);
1106
1107 getActionDefinitionsBuilder(Opcode: G_INTTOPTR)
1108 .unsupportedIf(Predicate: [&](const LegalityQuery &Query) {
1109 return Query.Types[0].getSizeInBits() != Query.Types[1].getSizeInBits();
1110 })
1111 .legalFor(Types: {{p0, i64}, {v2p0, v2i64}})
1112 .clampMaxNumElements(TypeIdx: 1, EltTy: s64, MaxElements: 2);
1113
1114 // Casts for 32 and 64-bit width type are just copies.
1115 // Same for 128-bit width type, except they are on the FPR bank.
1116 getActionDefinitionsBuilder(Opcode: G_BITCAST)
1117 .legalForCartesianProduct(Types: {s16})
1118 // Keeping 32-bit instructions legal to prevent regression in some tests
1119 .legalForCartesianProduct(Types: {s32, v2s16, v4s8})
1120 .legalForCartesianProduct(Types: {s64, v8s8, v4s16, v2s32})
1121 .legalForCartesianProduct(Types: {s128, v16s8, v8s16, v4s32, v2s64, v2p0})
1122 .customIf(Predicate: [=](const LegalityQuery &Query) {
1123 // Handle casts from i1 vectors to scalars.
1124 LLT DstTy = Query.Types[0];
1125 LLT SrcTy = Query.Types[1];
1126 return DstTy.isScalar() && SrcTy.isVector() &&
1127 SrcTy.getScalarSizeInBits() == 1;
1128 })
1129 .lowerIf(Predicate: [=](const LegalityQuery &Query) {
1130 return Query.Types[0].isVector() != Query.Types[1].isVector();
1131 })
1132 // moreElementsToNextPow2 cannot pad the source to match, so lower
1133 .lowerIf(Predicate: [=](const LegalityQuery &Query) {
1134 LLT DstTy = Query.Types[0];
1135 LLT SrcTy = Query.Types[1];
1136 if (!DstTy.isFixedVector() || !SrcTy.isFixedVector())
1137 return false;
1138 unsigned MoreElts = 1u << Log2_32_Ceil(Value: DstTy.getNumElements());
1139 return SrcTy.getNumElements() * MoreElts % DstTy.getNumElements() != 0;
1140 })
1141 .moreElementsToNextPow2(TypeIdx: 0)
1142 .clampNumElements(TypeIdx: 0, MinTy: v8s8, MaxTy: v16s8)
1143 .clampNumElements(TypeIdx: 0, MinTy: v4s16, MaxTy: v8s16)
1144 .clampNumElements(TypeIdx: 0, MinTy: v2s32, MaxTy: v4s32)
1145 .clampMaxNumElements(TypeIdx: 0, EltTy: s64, MaxElements: 2)
1146 .lower();
1147
1148 getActionDefinitionsBuilder(Opcode: G_VASTART).legalFor(Types: {p0});
1149
1150 // va_list must be a pointer, but most sized types are pretty easy to handle
1151 // as the destination.
1152 getActionDefinitionsBuilder(Opcode: G_VAARG)
1153 .customForCartesianProduct(Types0: {s8, s16, s32, s64, p0}, Types1: {p0})
1154 .clampScalar(TypeIdx: 0, MinTy: s8, MaxTy: s64)
1155 .widenScalarToNextPow2(TypeIdx: 0, /*Min*/ MinSize: 8);
1156
1157 getActionDefinitionsBuilder(Opcode: G_ATOMIC_CMPXCHG_WITH_SUCCESS)
1158 .lowerIf(
1159 Predicate: all(P0: typeInSet(TypeIdx: 0, TypesInit: {s8, s16, s32, s64, s128}), P1: typeIs(TypeIdx: 2, TypesInit: p0)));
1160
1161 bool UseOutlineAtomics = ST.outlineAtomics() && !ST.hasLSE();
1162
1163 getActionDefinitionsBuilder(Opcode: G_ATOMIC_CMPXCHG)
1164 .legalFor(Pred: !UseOutlineAtomics, Types: {{s32, p0}, {s64, p0}})
1165 .customFor(Pred: !UseOutlineAtomics, Types: {{s128, p0}})
1166 .libcallFor(Pred: UseOutlineAtomics,
1167 Types: {{s8, p0}, {s16, p0}, {s32, p0}, {s64, p0}, {s128, p0}})
1168 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s64);
1169
1170 getActionDefinitionsBuilder(Opcodes: {G_ATOMICRMW_XCHG, G_ATOMICRMW_ADD,
1171 G_ATOMICRMW_SUB, G_ATOMICRMW_AND, G_ATOMICRMW_OR,
1172 G_ATOMICRMW_XOR})
1173 .legalFor(Pred: !UseOutlineAtomics, Types: {{s32, p0}, {s64, p0}})
1174 .libcallFor(Pred: UseOutlineAtomics,
1175 Types: {{s8, p0}, {s16, p0}, {s32, p0}, {s64, p0}})
1176 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s64);
1177
1178 // Do not outline these atomics operations, as per comment in
1179 // AArch64ISelLowering.cpp's shouldExpandAtomicRMWInIR().
1180 getActionDefinitionsBuilder(
1181 Opcodes: {G_ATOMICRMW_MIN, G_ATOMICRMW_MAX, G_ATOMICRMW_UMIN, G_ATOMICRMW_UMAX})
1182 .legalIf(Predicate: all(P0: typeInSet(TypeIdx: 0, TypesInit: {s32, s64}), P1: typeIs(TypeIdx: 1, TypesInit: p0)))
1183 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s64);
1184
1185 getActionDefinitionsBuilder(Opcode: G_BLOCK_ADDR).legalFor(Types: {p0});
1186
1187 // Merge/Unmerge
1188 for (unsigned Op : {G_MERGE_VALUES, G_UNMERGE_VALUES}) {
1189 unsigned BigTyIdx = Op == G_MERGE_VALUES ? 0 : 1;
1190 unsigned LitTyIdx = Op == G_MERGE_VALUES ? 1 : 0;
1191 getActionDefinitionsBuilder(Opcode: Op)
1192 .widenScalarToNextPow2(TypeIdx: LitTyIdx, MinSize: 8)
1193 // Above s64 lowered shifts narrow back to a merge and never terminate
1194 .lowerIf(Predicate: [=](const LegalityQuery &Q) {
1195 const LLT BigTy = Q.Types[BigTyIdx];
1196 return BigTy.isScalar() && !isPowerOf2_32(Value: BigTy.getSizeInBits()) &&
1197 BigTy.getSizeInBits() < 64;
1198 })
1199 .widenScalarToNextPow2(TypeIdx: BigTyIdx, MinSize: 32)
1200 .clampScalar(TypeIdx: LitTyIdx, MinTy: s8, MaxTy: s64)
1201 .clampScalar(TypeIdx: BigTyIdx, MinTy: s32, MaxTy: s128)
1202 .legalIf(Predicate: [=](const LegalityQuery &Q) {
1203 switch (Q.Types[BigTyIdx].getSizeInBits()) {
1204 case 32:
1205 case 64:
1206 case 128:
1207 break;
1208 default:
1209 return false;
1210 }
1211 switch (Q.Types[LitTyIdx].getSizeInBits()) {
1212 case 8:
1213 case 16:
1214 case 32:
1215 case 64:
1216 return true;
1217 default:
1218 return false;
1219 }
1220 });
1221 }
1222
1223 // TODO : nxv4s16, nxv2s16, nxv2s32
1224 getActionDefinitionsBuilder(Opcode: G_EXTRACT_VECTOR_ELT)
1225 .legalFor(Pred: HasSVE, Types: {{s16, nxv16s8, s64},
1226 {s16, nxv8s16, s64},
1227 {s32, nxv4s32, s64},
1228 {s64, nxv2s64, s64}})
1229 .unsupportedIf(Predicate: [=](const LegalityQuery &Query) {
1230 const LLT &EltTy = Query.Types[1].getElementType();
1231 if (Query.Types[1].isScalableVector())
1232 return false;
1233 return Query.Types[0] != EltTy;
1234 })
1235 .minScalar(TypeIdx: 2, Ty: s64)
1236 .customIf(Predicate: [=](const LegalityQuery &Query) {
1237 const LLT &VecTy = Query.Types[1];
1238 return VecTy == v8s8 || VecTy == v16s8 || VecTy == v2s16 ||
1239 VecTy == v4s16 || VecTy == v8s16 || VecTy == v2s32 ||
1240 VecTy == v4s32 || VecTy == v2s64 || VecTy == v2p0;
1241 })
1242 .minScalarOrEltIf(
1243 Predicate: [=](const LegalityQuery &Query) {
1244 // We want to promote to <M x s1> to <M x s64> if that wouldn't
1245 // cause the total vec size to be > 128b.
1246 return Query.Types[1].isFixedVector() &&
1247 Query.Types[1].getNumElements() <= 2;
1248 },
1249 TypeIdx: 0, Ty: s64)
1250 .minScalarOrEltIf(
1251 Predicate: [=](const LegalityQuery &Query) {
1252 return Query.Types[1].isFixedVector() &&
1253 Query.Types[1].getNumElements() <= 4;
1254 },
1255 TypeIdx: 0, Ty: s32)
1256 .minScalarOrEltIf(
1257 Predicate: [=](const LegalityQuery &Query) {
1258 return Query.Types[1].isFixedVector() &&
1259 Query.Types[1].getNumElements() <= 8;
1260 },
1261 TypeIdx: 0, Ty: s16)
1262 .minScalarOrEltIf(
1263 Predicate: [=](const LegalityQuery &Query) {
1264 return Query.Types[1].isFixedVector() &&
1265 Query.Types[1].getNumElements() <= 16;
1266 },
1267 TypeIdx: 0, Ty: s8)
1268 .minScalarOrElt(TypeIdx: 0, Ty: s8) // Worst case, we need at least s8.
1269 .moreElementsToNextPow2(TypeIdx: 1)
1270 .clampMaxNumElements(TypeIdx: 1, EltTy: s64, MaxElements: 2)
1271 .clampMaxNumElements(TypeIdx: 1, EltTy: s32, MaxElements: 4)
1272 .clampMaxNumElements(TypeIdx: 1, EltTy: s16, MaxElements: 8)
1273 .clampMaxNumElements(TypeIdx: 1, EltTy: s8, MaxElements: 16)
1274 .clampMaxNumElements(TypeIdx: 1, EltTy: p0, MaxElements: 2)
1275 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 1, Size: 64), TypeIdx: 1);
1276
1277 getActionDefinitionsBuilder(Opcode: G_INSERT_VECTOR_ELT)
1278 .legalIf(
1279 Predicate: typeInSet(TypeIdx: 0, TypesInit: {v8s8, v16s8, v4s16, v8s16, v2s32, v4s32, v2s64, v2p0}))
1280 .legalFor(Pred: HasSVE, Types: {{nxv16s8, s32, s64},
1281 {nxv8s16, s32, s64},
1282 {nxv4s32, s32, s64},
1283 {nxv2s64, s64, s64}})
1284 .moreElementsToNextPow2(TypeIdx: 0)
1285 .widenVectorEltsToVectorMinSize(TypeIdx: 0, VectorSize: 64)
1286 .clampNumElements(TypeIdx: 0, MinTy: v8s8, MaxTy: v16s8)
1287 .clampNumElements(TypeIdx: 0, MinTy: v4s16, MaxTy: v8s16)
1288 .clampNumElements(TypeIdx: 0, MinTy: v2s32, MaxTy: v4s32)
1289 .clampMaxNumElements(TypeIdx: 0, EltTy: s64, MaxElements: 2)
1290 .clampMaxNumElements(TypeIdx: 0, EltTy: p0, MaxElements: 2)
1291 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 0, Size: 64), TypeIdx: 0);
1292
1293 getActionDefinitionsBuilder(Opcode: G_BUILD_VECTOR)
1294 .legalFor(Types: {{v8s8, s8},
1295 {v16s8, s8},
1296 {v4s16, s16},
1297 {v8s16, s16},
1298 {v2s32, s32},
1299 {v4s32, s32},
1300 {v2s64, s64},
1301 {v2p0, p0}})
1302 .clampNumElements(TypeIdx: 0, MinTy: v4s32, MaxTy: v4s32)
1303 .clampNumElements(TypeIdx: 0, MinTy: v2s64, MaxTy: v2s64)
1304 .minScalarOrElt(TypeIdx: 0, Ty: s8)
1305 .widenVectorEltsToVectorMinSize(TypeIdx: 0, VectorSize: 64)
1306 .widenScalarOrEltToNextPow2(TypeIdx: 0)
1307 .minScalarSameAs(TypeIdx: 1, LargeTypeIdx: 0);
1308
1309 getActionDefinitionsBuilder(Opcode: G_BUILD_VECTOR_TRUNC).lower();
1310
1311 getActionDefinitionsBuilder(Opcode: G_SHUFFLE_VECTOR)
1312 .legalIf(Predicate: [=](const LegalityQuery &Query) {
1313 const LLT &DstTy = Query.Types[0];
1314 const LLT &SrcTy = Query.Types[1];
1315 // For now just support the TBL2 variant which needs the source vectors
1316 // to be the same size as the dest.
1317 if (DstTy != SrcTy)
1318 return false;
1319 return llvm::is_contained(
1320 Set: {v8s8, v16s8, v4s16, v8s16, v2s32, v4s32, v2s64}, Element: DstTy);
1321 })
1322 .moreElementsIf(
1323 Predicate: [](const LegalityQuery &Query) {
1324 return Query.Types[0].getNumElements() >
1325 Query.Types[1].getNumElements();
1326 },
1327 Mutation: changeTo(TypeIdx: 1, FromTypeIdx: 0))
1328 .moreElementsToNextPow2(TypeIdx: 0)
1329 .moreElementsIf(
1330 Predicate: [](const LegalityQuery &Query) {
1331 return Query.Types[0].getNumElements() <
1332 Query.Types[1].getNumElements();
1333 },
1334 Mutation: changeTo(TypeIdx: 0, FromTypeIdx: 1))
1335 .widenScalarOrEltToNextPow2OrMinSize(TypeIdx: 0, MinSize: 8)
1336 .clampNumElements(TypeIdx: 0, MinTy: v8s8, MaxTy: v16s8)
1337 .clampNumElements(TypeIdx: 0, MinTy: v4s16, MaxTy: v8s16)
1338 .clampNumElements(TypeIdx: 0, MinTy: v4s32, MaxTy: v4s32)
1339 .clampNumElements(TypeIdx: 0, MinTy: v2s64, MaxTy: v2s64)
1340 .scalarizeIf(Predicate: scalarOrEltWiderThan(TypeIdx: 0, Size: 64), TypeIdx: 0)
1341 .bitcastIf(Predicate: isPointerVector(TypeIdx: 0), Mutation: [=](const LegalityQuery &Query) {
1342 // Bitcast pointers vector to i64.
1343 const LLT DstTy = Query.Types[0];
1344 return std::pair(
1345 0, LLT::vector(EC: DstTy.getElementCount(), ScalarTy: LLT::integer(SizeInBits: 64)));
1346 });
1347
1348 getActionDefinitionsBuilder(Opcode: G_CONCAT_VECTORS)
1349 .legalFor(Types: {{v16s8, v8s8}, {v8s16, v4s16}, {v4s32, v2s32}})
1350 .customIf(Predicate: [=](const LegalityQuery &Query) {
1351 return Query.Types[0].isFixedVector() &&
1352 Query.Types[0].getScalarSizeInBits() < 8;
1353 })
1354 .bitcastIf(
1355 Predicate: [=](const LegalityQuery &Query) {
1356 return Query.Types[0].isFixedVector() &&
1357 Query.Types[1].isFixedVector() &&
1358 Query.Types[0].getScalarSizeInBits() >= 8 &&
1359 isPowerOf2_64(Value: Query.Types[0].getScalarSizeInBits()) &&
1360 Query.Types[0].getSizeInBits() <= 128 &&
1361 Query.Types[1].getSizeInBits() <= 64;
1362 },
1363 Mutation: [=](const LegalityQuery &Query) {
1364 const LLT DstTy = Query.Types[0];
1365 const LLT SrcTy = Query.Types[1];
1366 return std::pair(
1367 0, DstTy.changeElementSize(NewEltSize: SrcTy.getSizeInBits())
1368 .changeElementCount(
1369 EC: DstTy.getElementCount().divideCoefficientBy(
1370 RHS: SrcTy.getNumElements())));
1371 });
1372
1373 getActionDefinitionsBuilder(Opcode: G_EXTRACT_SUBVECTOR)
1374 .legalFor(Types: {{v8s8, v16s8}, {v4s16, v8s16}, {v2s32, v4s32}})
1375 .widenScalarOrEltToNextPow2(TypeIdx: 0)
1376 .clampMaxNumElements(TypeIdx: 0, EltTy: s8, MaxElements: 16)
1377 .clampMaxNumElements(TypeIdx: 0, EltTy: s16, MaxElements: 8)
1378 .clampMaxNumElements(TypeIdx: 0, EltTy: s32, MaxElements: 4)
1379 .clampNumElements(TypeIdx: 1, MinTy: v8s8, MaxTy: v16s8)
1380 .clampNumElements(TypeIdx: 1, MinTy: v4s16, MaxTy: v8s16)
1381 .clampNumElements(TypeIdx: 1, MinTy: v2s32, MaxTy: v4s32)
1382 .lower()
1383 .immIdx(ImmIdx: 0); // Inform verifier imm idx 0 is handled.
1384
1385 // TODO: {nxv16s8, s8}, {nxv8s16, s16}
1386 getActionDefinitionsBuilder(Opcode: G_SPLAT_VECTOR)
1387 .legalFor(Pred: HasSVE, Types: {{nxv4s32, s32}, {nxv2s64, s64}});
1388
1389 getActionDefinitionsBuilder(Opcode: G_JUMP_TABLE).legalFor(Types: {p0});
1390
1391 getActionDefinitionsBuilder(Opcode: G_BRJT).legalFor(Types: {{p0, s64}});
1392
1393 getActionDefinitionsBuilder(Opcodes: {G_TRAP, G_DEBUGTRAP, G_UBSANTRAP}).alwaysLegal();
1394
1395 getActionDefinitionsBuilder(Opcode: G_DYN_STACKALLOC).custom();
1396
1397 getActionDefinitionsBuilder(Opcodes: {G_STACKSAVE, G_STACKRESTORE}).lower();
1398
1399 if (ST.hasMOPS()) {
1400 // G_BZERO is not supported. Currently it is only emitted by
1401 // PreLegalizerCombiner for G_MEMSET with zero constant.
1402 getActionDefinitionsBuilder(Opcode: G_BZERO).unsupported();
1403
1404 getActionDefinitionsBuilder(Opcode: G_MEMSET)
1405 .legalForCartesianProduct(Types0: {p0}, Types1: {s64}, Types2: {s64})
1406 .customForCartesianProduct(Types0: {p0}, Types1: {s8}, Types2: {s64})
1407 .immIdx(ImmIdx: 0); // Inform verifier imm idx 0 is handled.
1408
1409 getActionDefinitionsBuilder(Opcodes: {G_MEMCPY, G_MEMMOVE})
1410 .legalForCartesianProduct(Types0: {p0}, Types1: {p0}, Types2: {s64})
1411 .immIdx(ImmIdx: 0); // Inform verifier imm idx 0 is handled.
1412
1413 // G_MEMCPY_INLINE does not have a tailcall immediate
1414 getActionDefinitionsBuilder(Opcode: G_MEMCPY_INLINE)
1415 .legalForCartesianProduct(Types0: {p0}, Types1: {p0}, Types2: {s64});
1416
1417 getActionDefinitionsBuilder(Opcode: G_MEMSET_INLINE)
1418 .legalForCartesianProduct(Types0: {p0}, Types1: {s64}, Types2: {s64})
1419 .customForCartesianProduct(Types0: {p0}, Types1: {s8}, Types2: {s64});
1420 } else {
1421 getActionDefinitionsBuilder(Opcodes: {G_BZERO, G_MEMCPY, G_MEMMOVE, G_MEMSET})
1422 .libcall();
1423 }
1424
1425 // For fadd reductions we have pairwise operations available. We treat the
1426 // usual legal types as legal and handle the lowering to pairwise instructions
1427 // later.
1428 getActionDefinitionsBuilder(Opcode: G_VECREDUCE_FADD)
1429 .legalFor(Types: {{f32, v2f32}, {f32, v4f32}, {f64, v2f64}})
1430 .legalFor(Pred: HasFP16, Types: {{f16, v4f16}, {f16, v8f16}})
1431 .widenScalarIf(
1432 Predicate: [HasFP16](const LegalityQuery &Query) {
1433 return (!HasFP16 && Query.Types[0].getScalarType().isFloat16()) ||
1434 Query.Types[0].getScalarType().isBFloat16();
1435 },
1436 Mutation: changeElementTo(TypeIdx: 0, Ty: f32))
1437 .clampMaxNumElements(TypeIdx: 1, EltTy: s64, MaxElements: 2)
1438 .clampMaxNumElements(TypeIdx: 1, EltTy: s32, MaxElements: 4)
1439 .clampMaxNumElements(TypeIdx: 1, EltTy: s16, MaxElements: 8)
1440 .moreElementsToNextPow2(TypeIdx: 1)
1441 .scalarize(TypeIdx: 1)
1442 .lower();
1443
1444 // For fmul reductions we need to split up into individual operations. We
1445 // clamp to 128 bit vectors then to 64bit vectors to produce a cascade of
1446 // smaller types, followed by scalarizing what remains.
1447 getActionDefinitionsBuilder(Opcode: G_VECREDUCE_FMUL)
1448 .widenScalarIf(
1449 Predicate: [HasFP16](const LegalityQuery &Query) {
1450 return (!HasFP16 && Query.Types[0].getScalarType().isFloat16()) ||
1451 Query.Types[0].getScalarType().isBFloat16();
1452 },
1453 Mutation: changeElementTo(TypeIdx: 0, Ty: f32))
1454 .clampMaxNumElements(TypeIdx: 1, EltTy: s64, MaxElements: 2)
1455 .clampMaxNumElements(TypeIdx: 1, EltTy: s32, MaxElements: 4)
1456 .clampMaxNumElements(TypeIdx: 1, EltTy: s16, MaxElements: 8)
1457 .clampMaxNumElements(TypeIdx: 1, EltTy: s32, MaxElements: 2)
1458 .clampMaxNumElements(TypeIdx: 1, EltTy: s16, MaxElements: 4)
1459 .scalarize(TypeIdx: 1)
1460 .lower();
1461
1462 getActionDefinitionsBuilder(Opcodes: {G_VECREDUCE_SEQ_FADD, G_VECREDUCE_SEQ_FMUL})
1463 .scalarize(TypeIdx: 2)
1464 .lower();
1465
1466 getActionDefinitionsBuilder(Opcode: G_VECREDUCE_ADD)
1467 .legalFor(Types: {{i8, v8i8},
1468 {i8, v16i8},
1469 {i16, v4i16},
1470 {i16, v8i16},
1471 {i32, v2i32},
1472 {i32, v4i32},
1473 {i64, v2i64}})
1474 .moreElementsToNextPow2(TypeIdx: 1)
1475 .clampMaxNumElements(TypeIdx: 1, EltTy: s64, MaxElements: 2)
1476 .clampMaxNumElements(TypeIdx: 1, EltTy: s32, MaxElements: 4)
1477 .clampMaxNumElements(TypeIdx: 1, EltTy: s16, MaxElements: 8)
1478 .clampMaxNumElements(TypeIdx: 1, EltTy: s8, MaxElements: 16)
1479 .widenVectorEltsToVectorMinSize(TypeIdx: 1, VectorSize: 64)
1480 .scalarize(TypeIdx: 1);
1481
1482 getActionDefinitionsBuilder(Opcodes: {G_VECREDUCE_FMIN, G_VECREDUCE_FMAX,
1483 G_VECREDUCE_FMINIMUM, G_VECREDUCE_FMAXIMUM})
1484 .legalFor(Types: {{f32, v2f32}, {f32, v4f32}, {f64, v2f64}})
1485 .legalFor(Pred: HasFP16, Types: {{f16, v4f16}, {f16, v8f16}})
1486 .widenScalarIf(
1487 Predicate: [HasFP16](const LegalityQuery &Query) {
1488 return (!HasFP16 && Query.Types[0].getScalarType().isFloat16()) ||
1489 Query.Types[0].getScalarType().isBFloat16();
1490 },
1491 Mutation: changeElementTo(TypeIdx: 0, Ty: f32))
1492 .clampMaxNumElements(TypeIdx: 1, EltTy: s64, MaxElements: 2)
1493 .clampMaxNumElements(TypeIdx: 1, EltTy: s32, MaxElements: 4)
1494 .clampMaxNumElements(TypeIdx: 1, EltTy: s16, MaxElements: 8)
1495 .scalarize(TypeIdx: 1)
1496 .lower();
1497
1498 getActionDefinitionsBuilder(Opcode: G_VECREDUCE_MUL)
1499 .clampMaxNumElements(TypeIdx: 1, EltTy: s32, MaxElements: 2)
1500 .clampMaxNumElements(TypeIdx: 1, EltTy: s16, MaxElements: 4)
1501 .clampMaxNumElements(TypeIdx: 1, EltTy: s8, MaxElements: 8)
1502 .scalarize(TypeIdx: 1)
1503 .lower();
1504
1505 getActionDefinitionsBuilder(
1506 Opcodes: {G_VECREDUCE_SMIN, G_VECREDUCE_SMAX, G_VECREDUCE_UMIN, G_VECREDUCE_UMAX})
1507 .legalFor(Types: {{i8, v8i8},
1508 {i8, v16i8},
1509 {i16, v4i16},
1510 {i16, v8i16},
1511 {i32, v2i32},
1512 {i32, v4i32}})
1513 .moreElementsIf(
1514 Predicate: [=](const LegalityQuery &Query) {
1515 return Query.Types[1].isVector() &&
1516 Query.Types[1].getElementType() != s8 &&
1517 Query.Types[1].getNumElements() & 1;
1518 },
1519 Mutation: LegalizeMutations::moreElementsToNextPow2(TypeIdx: 1))
1520 .clampMaxNumElements(TypeIdx: 1, EltTy: s64, MaxElements: 2)
1521 .clampMaxNumElements(TypeIdx: 1, EltTy: s32, MaxElements: 4)
1522 .clampMaxNumElements(TypeIdx: 1, EltTy: s16, MaxElements: 8)
1523 .clampMaxNumElements(TypeIdx: 1, EltTy: s8, MaxElements: 16)
1524 .scalarize(TypeIdx: 1)
1525 .lower();
1526
1527 getActionDefinitionsBuilder(
1528 Opcodes: {G_VECREDUCE_OR, G_VECREDUCE_AND, G_VECREDUCE_XOR})
1529 // Try to break down into smaller vectors as long as they're at least 64
1530 // bits. This lets us use vector operations for some parts of the
1531 // reduction.
1532 .fewerElementsIf(
1533 Predicate: [=](const LegalityQuery &Q) {
1534 LLT SrcTy = Q.Types[1];
1535 if (SrcTy.isScalar())
1536 return false;
1537 if (!isPowerOf2_32(Value: SrcTy.getNumElements()))
1538 return false;
1539 // We can usually perform 64b vector operations.
1540 return SrcTy.getSizeInBits() > 64;
1541 },
1542 Mutation: [=](const LegalityQuery &Q) {
1543 LLT SrcTy = Q.Types[1];
1544 return std::make_pair(x: 1, y: SrcTy.divide(Factor: 2));
1545 })
1546 .scalarize(TypeIdx: 1)
1547 .lower();
1548
1549 // TODO: Update this to correct handling when adding AArch64/SVE support.
1550 getActionDefinitionsBuilder(Opcode: G_VECTOR_COMPRESS).lower();
1551
1552 // Access to floating-point environment.
1553 getActionDefinitionsBuilder(Opcodes: {G_GET_FPENV, G_SET_FPENV, G_RESET_FPENV,
1554 G_GET_FPMODE, G_SET_FPMODE, G_RESET_FPMODE})
1555 .libcall();
1556
1557 getActionDefinitionsBuilder(Opcodes: {G_GET_ROUNDING, G_SET_ROUNDING})
1558 .customFor(Types: {s32});
1559
1560 getActionDefinitionsBuilder(Opcode: G_IS_FPCLASS).lower();
1561
1562 getActionDefinitionsBuilder(Opcode: G_PREFETCH).custom();
1563
1564 getActionDefinitionsBuilder(Opcodes: {G_SCMP, G_UCMP}).lower();
1565
1566 getActionDefinitionsBuilder(Opcodes: {G_INTRINSIC, G_INTRINSIC_W_SIDE_EFFECTS})
1567 .alwaysLegal();
1568 getActionDefinitionsBuilder(Opcode: G_FENCE).alwaysLegal();
1569 getActionDefinitionsBuilder(Opcode: G_INVOKE_REGION_START).alwaysLegal();
1570
1571 verify(MII: *ST.getInstrInfo());
1572}
1573
1574bool AArch64LegalizerInfo::legalizeCustom(
1575 LegalizerHelper &Helper, MachineInstr &MI,
1576 LostDebugLocObserver &LocObserver) const {
1577 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
1578 MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
1579 GISelChangeObserver &Observer = Helper.Observer;
1580 switch (MI.getOpcode()) {
1581 default:
1582 // No idea what to do.
1583 return false;
1584 case TargetOpcode::G_VAARG:
1585 return legalizeVaArg(MI, MRI, MIRBuilder);
1586 case TargetOpcode::G_LOAD:
1587 case TargetOpcode::G_STORE:
1588 return legalizeLoadStore(MI, MRI, MIRBuilder, Observer);
1589 case TargetOpcode::G_SHL:
1590 case TargetOpcode::G_ASHR:
1591 case TargetOpcode::G_LSHR:
1592 return legalizeShlAshrLshr(MI, MRI, MIRBuilder, Observer);
1593 case TargetOpcode::G_GLOBAL_VALUE:
1594 return legalizeSmallCMGlobalValue(MI, MRI, MIRBuilder, Observer);
1595 case TargetOpcode::G_SBFX:
1596 case TargetOpcode::G_UBFX:
1597 return legalizeBitfieldExtract(MI, MRI, Helper);
1598 case TargetOpcode::G_FSHL:
1599 case TargetOpcode::G_FSHR:
1600 return legalizeFunnelShift(MI, MRI, MIRBuilder, Observer, Helper);
1601 case TargetOpcode::G_ROTR:
1602 return legalizeRotate(MI, MRI, Helper);
1603 case TargetOpcode::G_CTPOP:
1604 return legalizeCTPOP(MI, MRI, Helper);
1605 case TargetOpcode::G_ATOMIC_CMPXCHG:
1606 return legalizeAtomicCmpxchg128(MI, MRI, Helper);
1607 case TargetOpcode::G_CTTZ:
1608 return legalizeCTTZ(MI, Helper);
1609 case TargetOpcode::G_BZERO:
1610 case TargetOpcode::G_MEMCPY:
1611 case TargetOpcode::G_MEMMOVE:
1612 case TargetOpcode::G_MEMSET:
1613 case TargetOpcode::G_MEMSET_INLINE:
1614 return legalizeMemOps(MI, Helper);
1615 case TargetOpcode::G_EXTRACT_VECTOR_ELT:
1616 return legalizeExtractVectorElt(MI, MRI, Helper);
1617 case TargetOpcode::G_DYN_STACKALLOC:
1618 return legalizeDynStackAlloc(MI, Helper);
1619 case TargetOpcode::G_PREFETCH:
1620 return legalizePrefetch(MI, Helper);
1621 case TargetOpcode::G_ABS:
1622 return Helper.lowerAbsToCNeg(MI);
1623 case TargetOpcode::G_ICMP:
1624 return legalizeICMP(MI, MRI, MIRBuilder);
1625 case TargetOpcode::G_BITCAST:
1626 return legalizeBitcast(MI, Helper);
1627 case TargetOpcode::G_CONCAT_VECTORS:
1628 return legalizeConcatVectors(MI, MRI, MIRBuilder);
1629 case TargetOpcode::G_FPTRUNC:
1630 // In order to lower f16 to f64 properly, we need to use f32 as an
1631 // intermediary
1632 return legalizeFptrunc(MI, MIRBuilder, MRI);
1633 case TargetOpcode::G_GET_ROUNDING:
1634 return legalizeGetRounding(MI, MIRBuilder, MRI, Helper);
1635 case TargetOpcode::G_SET_ROUNDING:
1636 return legalizeSetRounding(MI, MIRBuilder, MRI, Helper);
1637 }
1638
1639 llvm_unreachable("expected switch to return");
1640}
1641
1642bool AArch64LegalizerInfo::legalizeBitcast(MachineInstr &MI,
1643 LegalizerHelper &Helper) const {
1644 assert(MI.getOpcode() == TargetOpcode::G_BITCAST && "Unexpected opcode");
1645 auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
1646 // We're trying to handle casts from i1 vectors to scalars but reloading from
1647 // stack.
1648 if (!DstTy.isScalar() || !SrcTy.isVector() ||
1649 SrcTy.getElementType() != LLT::scalar(SizeInBits: 1))
1650 return false;
1651
1652 Helper.createStackStoreLoad(Res: DstReg, Val: SrcReg);
1653 MI.eraseFromParent();
1654 return true;
1655}
1656
1657bool AArch64LegalizerInfo::legalizeFunnelShift(MachineInstr &MI,
1658 MachineRegisterInfo &MRI,
1659 MachineIRBuilder &MIRBuilder,
1660 GISelChangeObserver &Observer,
1661 LegalizerHelper &Helper) const {
1662 assert(MI.getOpcode() == TargetOpcode::G_FSHL ||
1663 MI.getOpcode() == TargetOpcode::G_FSHR);
1664
1665 // Keep as G_FSHR if shift amount is a G_CONSTANT, else use generic
1666 // lowering
1667 Register ShiftNo = MI.getOperand(i: 3).getReg();
1668 LLT ShiftTy = MRI.getType(Reg: ShiftNo);
1669 auto VRegAndVal = getIConstantVRegValWithLookThrough(VReg: ShiftNo, MRI);
1670
1671 // Adjust shift amount according to Opcode (FSHL/FSHR)
1672 // Convert FSHL to FSHR
1673 LLT OperationTy = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
1674 APInt BitWidth(ShiftTy.getSizeInBits(), OperationTy.getSizeInBits(), false);
1675
1676 // Lower non-constant shifts and leave zero shifts to the optimizer.
1677 if (!VRegAndVal || VRegAndVal->Value.urem(RHS: BitWidth) == 0)
1678 return (Helper.lowerFunnelShiftAsShifts(MI) ==
1679 LegalizerHelper::LegalizeResult::Legalized);
1680
1681 APInt Amount = VRegAndVal->Value.urem(RHS: BitWidth);
1682
1683 Amount = MI.getOpcode() == TargetOpcode::G_FSHL ? BitWidth - Amount : Amount;
1684
1685 // If the instruction is G_FSHR, has a 64-bit G_CONSTANT for shift amount
1686 // in the range of 0 <-> BitWidth, it is legal
1687 if (ShiftTy.getSizeInBits() == 64 && MI.getOpcode() == TargetOpcode::G_FSHR &&
1688 VRegAndVal->Value.ult(RHS: BitWidth))
1689 return true;
1690
1691 // Cast the ShiftNumber to a 64-bit type
1692 auto Cast64 = MIRBuilder.buildConstant(Res: LLT::integer(SizeInBits: 64), Val: Amount.zext(width: 64));
1693
1694 if (MI.getOpcode() == TargetOpcode::G_FSHR) {
1695 Observer.changingInstr(MI);
1696 MI.getOperand(i: 3).setReg(Cast64.getReg(Idx: 0));
1697 Observer.changedInstr(MI);
1698 }
1699 // If Opcode is FSHL, remove the FSHL instruction and create a FSHR
1700 // instruction
1701 else if (MI.getOpcode() == TargetOpcode::G_FSHL) {
1702 MIRBuilder.buildInstr(Opc: TargetOpcode::G_FSHR, DstOps: {MI.getOperand(i: 0).getReg()},
1703 SrcOps: {MI.getOperand(i: 1).getReg(), MI.getOperand(i: 2).getReg(),
1704 Cast64.getReg(Idx: 0)});
1705 MI.eraseFromParent();
1706 }
1707 return true;
1708}
1709
1710bool AArch64LegalizerInfo::legalizeICMP(MachineInstr &MI,
1711 MachineRegisterInfo &MRI,
1712 MachineIRBuilder &MIRBuilder) const {
1713 Register DstReg = MI.getOperand(i: 0).getReg();
1714 Register SrcReg1 = MI.getOperand(i: 2).getReg();
1715 Register SrcReg2 = MI.getOperand(i: 3).getReg();
1716 LLT DstTy = MRI.getType(Reg: DstReg);
1717 LLT SrcTy = MRI.getType(Reg: SrcReg1);
1718
1719 // Check the vector types are legal
1720 if (DstTy.getScalarSizeInBits() != SrcTy.getScalarSizeInBits() ||
1721 DstTy.getNumElements() != SrcTy.getNumElements() ||
1722 (DstTy.getSizeInBits() != 64 && DstTy.getSizeInBits() != 128))
1723 return false;
1724
1725 // Lowers G_ICMP NE => G_ICMP EQ to allow better pattern matching for
1726 // following passes
1727 CmpInst::Predicate Pred = (CmpInst::Predicate)MI.getOperand(i: 1).getPredicate();
1728 if (Pred != CmpInst::ICMP_NE)
1729 return true;
1730 Register CmpReg =
1731 MIRBuilder
1732 .buildICmp(Pred: CmpInst::ICMP_EQ, Res: MRI.getType(Reg: DstReg), Op0: SrcReg1, Op1: SrcReg2)
1733 .getReg(Idx: 0);
1734 MIRBuilder.buildNot(Dst: DstReg, Src0: CmpReg);
1735
1736 MI.eraseFromParent();
1737 return true;
1738}
1739
1740bool AArch64LegalizerInfo::legalizeRotate(MachineInstr &MI,
1741 MachineRegisterInfo &MRI,
1742 LegalizerHelper &Helper) const {
1743 // To allow for imported patterns to match, we ensure that the rotate amount
1744 // is 64b with an extension.
1745 Register AmtReg = MI.getOperand(i: 2).getReg();
1746 LLT AmtTy = MRI.getType(Reg: AmtReg);
1747 (void)AmtTy;
1748 assert(AmtTy.isScalar() && "Expected a scalar rotate");
1749 assert(AmtTy.getSizeInBits() < 64 && "Expected this rotate to be legal");
1750 auto NewAmt = Helper.MIRBuilder.buildZExt(Res: LLT::integer(SizeInBits: 64), Op: AmtReg);
1751 Helper.Observer.changingInstr(MI);
1752 MI.getOperand(i: 2).setReg(NewAmt.getReg(Idx: 0));
1753 Helper.Observer.changedInstr(MI);
1754 return true;
1755}
1756
1757bool AArch64LegalizerInfo::legalizeSmallCMGlobalValue(
1758 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder,
1759 GISelChangeObserver &Observer) const {
1760 assert(MI.getOpcode() == TargetOpcode::G_GLOBAL_VALUE);
1761 // We do this custom legalization to convert G_GLOBAL_VALUE into target ADRP +
1762 // G_ADD_LOW instructions.
1763 // By splitting this here, we can optimize accesses in the small code model by
1764 // folding in the G_ADD_LOW into the load/store offset.
1765 auto &GlobalOp = MI.getOperand(i: 1);
1766 // Don't modify an intrinsic call.
1767 if (GlobalOp.isSymbol())
1768 return true;
1769 const auto* GV = GlobalOp.getGlobal();
1770 if (GV->isThreadLocal())
1771 return true; // Don't want to modify TLS vars.
1772
1773 auto &TM = ST->getTargetLowering()->getTargetMachine();
1774 unsigned OpFlags = ST->ClassifyGlobalReference(GV, TM);
1775
1776 if (OpFlags & AArch64II::MO_GOT)
1777 return true;
1778
1779 auto Offset = GlobalOp.getOffset();
1780 Register DstReg = MI.getOperand(i: 0).getReg();
1781 auto ADRP = MIRBuilder.buildInstr(Opc: AArch64::ADRP, DstOps: {LLT::pointer(AddressSpace: 0, SizeInBits: 64)}, SrcOps: {})
1782 .addGlobalAddress(GV, Offset, TargetFlags: OpFlags | AArch64II::MO_PAGE);
1783 // Set the regclass on the dest reg too.
1784 MRI.setRegClass(Reg: ADRP.getReg(Idx: 0), RC: &AArch64::GPR64RegClass);
1785
1786 // MO_TAGGED on the page indicates a tagged address. Set the tag now. We do so
1787 // by creating a MOVK that sets bits 48-63 of the register to (global address
1788 // + 0x100000000 - PC) >> 48. The additional 0x100000000 offset here is to
1789 // prevent an incorrect tag being generated during relocation when the
1790 // global appears before the code section. Without the offset, a global at
1791 // `0x0f00'0000'0000'1000` (i.e. at `0x1000` with tag `0xf`) that's referenced
1792 // by code at `0x2000` would result in `0x0f00'0000'0000'1000 - 0x2000 =
1793 // 0x0eff'ffff'ffff'f000`, meaning the tag would be incorrectly set to `0xe`
1794 // instead of `0xf`.
1795 // This assumes that we're in the small code model so we can assume a binary
1796 // size of <= 4GB, which makes the untagged PC relative offset positive. The
1797 // binary must also be loaded into address range [0, 2^48). Both of these
1798 // properties need to be ensured at runtime when using tagged addresses.
1799 if (OpFlags & AArch64II::MO_TAGGED) {
1800 assert(!Offset &&
1801 "Should not have folded in an offset for a tagged global!");
1802 ADRP = MIRBuilder.buildInstr(Opc: AArch64::MOVKXi, DstOps: {LLT::pointer(AddressSpace: 0, SizeInBits: 64)}, SrcOps: {ADRP})
1803 .addGlobalAddress(GV, Offset: 0x100000000,
1804 TargetFlags: AArch64II::MO_PREL | AArch64II::MO_G3)
1805 .addImm(Val: 48);
1806 MRI.setRegClass(Reg: ADRP.getReg(Idx: 0), RC: &AArch64::GPR64RegClass);
1807 }
1808
1809 MIRBuilder.buildInstr(Opc: AArch64::G_ADD_LOW, DstOps: {DstReg}, SrcOps: {ADRP})
1810 .addGlobalAddress(GV, Offset,
1811 TargetFlags: OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
1812 MI.eraseFromParent();
1813 return true;
1814}
1815
1816bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
1817 MachineInstr &MI) const {
1818 MachineIRBuilder &MIB = Helper.MIRBuilder;
1819 MachineRegisterInfo &MRI = *MIB.getMRI();
1820
1821 auto LowerUnaryOp = [&MI, &MIB](unsigned Opcode) {
1822 MIB.buildInstr(Opc: Opcode, DstOps: {MI.getOperand(i: 0)}, SrcOps: {MI.getOperand(i: 2)});
1823 MI.eraseFromParent();
1824 return true;
1825 };
1826 auto LowerBinOp = [&MI, &MIB](unsigned Opcode) {
1827 MIB.buildInstr(Opc: Opcode, DstOps: {MI.getOperand(i: 0)},
1828 SrcOps: {MI.getOperand(i: 2), MI.getOperand(i: 3)});
1829 MI.eraseFromParent();
1830 return true;
1831 };
1832 auto LowerTriOp = [&MI, &MIB](unsigned Opcode) {
1833 MIB.buildInstr(Opc: Opcode, DstOps: {MI.getOperand(i: 0)},
1834 SrcOps: {MI.getOperand(i: 2), MI.getOperand(i: 3), MI.getOperand(i: 4)});
1835 MI.eraseFromParent();
1836 return true;
1837 };
1838
1839 Intrinsic::ID IntrinsicID = cast<GIntrinsic>(Val&: MI).getIntrinsicID();
1840 switch (IntrinsicID) {
1841 case Intrinsic::vacopy: {
1842 unsigned PtrSize = ST->isTargetILP32() ? 4 : 8;
1843 unsigned VaListSize =
1844 (ST->isTargetDarwin() || ST->isTargetWindows())
1845 ? PtrSize
1846 : ST->isTargetILP32() ? 20 : 32;
1847
1848 MachineFunction &MF = *MI.getMF();
1849 auto Val = MF.getRegInfo().createGenericVirtualRegister(
1850 Ty: LLT::integer(SizeInBits: VaListSize * 8));
1851 MIB.buildLoad(Res: Val, Addr: MI.getOperand(i: 2),
1852 MMO&: *MF.getMachineMemOperand(PtrInfo: MachinePointerInfo(),
1853 F: MachineMemOperand::MOLoad,
1854 Size: VaListSize, BaseAlignment: Align(PtrSize)));
1855 MIB.buildStore(Val, Addr: MI.getOperand(i: 1),
1856 MMO&: *MF.getMachineMemOperand(PtrInfo: MachinePointerInfo(),
1857 F: MachineMemOperand::MOStore,
1858 Size: VaListSize, BaseAlignment: Align(PtrSize)));
1859 MI.eraseFromParent();
1860 return true;
1861 }
1862 case Intrinsic::get_dynamic_area_offset: {
1863 MIB.buildConstant(Res: MI.getOperand(i: 0).getReg(), Val: 0);
1864 MI.eraseFromParent();
1865 return true;
1866 }
1867 case Intrinsic::aarch64_mops_memset_tag: {
1868 assert(MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS);
1869 // Anyext the value being set to 64 bit (only the bottom 8 bits are read by
1870 // the instruction).
1871 auto &Value = MI.getOperand(i: 3);
1872 Register ExtValueReg = MIB.buildAnyExt(Res: LLT::integer(SizeInBits: 64), Op: Value).getReg(Idx: 0);
1873 Value.setReg(ExtValueReg);
1874 return true;
1875 }
1876 case Intrinsic::aarch64_prefetch: {
1877 auto &AddrVal = MI.getOperand(i: 1);
1878
1879 int64_t IsWrite = MI.getOperand(i: 2).getImm();
1880 int64_t Target = MI.getOperand(i: 3).getImm();
1881 int64_t IsStream = MI.getOperand(i: 4).getImm();
1882 int64_t IsData = MI.getOperand(i: 5).getImm();
1883
1884 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1885 (!IsData << 3) | // IsDataCache bit
1886 (Target << 1) | // Cache level bits
1887 (unsigned)IsStream; // Stream bit
1888
1889 MIB.buildInstr(Opcode: AArch64::G_AARCH64_PREFETCH).addImm(Val: PrfOp).add(MO: AddrVal);
1890 MI.eraseFromParent();
1891 return true;
1892 }
1893 case Intrinsic::aarch64_range_prefetch: {
1894 auto &AddrVal = MI.getOperand(i: 1);
1895
1896 int64_t IsWrite = MI.getOperand(i: 2).getImm();
1897 int64_t IsStream = MI.getOperand(i: 3).getImm();
1898 unsigned PrfOp = (IsStream << 2) | IsWrite;
1899
1900 MIB.buildInstr(Opcode: AArch64::G_AARCH64_RANGE_PREFETCH)
1901 .addImm(Val: PrfOp)
1902 .add(MO: AddrVal)
1903 .addUse(RegNo: MI.getOperand(i: 4).getReg()); // Metadata
1904 MI.eraseFromParent();
1905 return true;
1906 }
1907 case Intrinsic::aarch64_prefetch_ir: {
1908 auto &AddrVal = MI.getOperand(i: 1);
1909 MIB.buildInstr(Opcode: AArch64::G_AARCH64_PREFETCH).addImm(Val: 24).add(MO: AddrVal);
1910 MI.eraseFromParent();
1911 return true;
1912 }
1913 case Intrinsic::aarch64_neon_uaddv:
1914 case Intrinsic::aarch64_neon_saddv:
1915 case Intrinsic::aarch64_neon_umaxv:
1916 case Intrinsic::aarch64_neon_smaxv:
1917 case Intrinsic::aarch64_neon_uminv:
1918 case Intrinsic::aarch64_neon_sminv: {
1919 bool IsSigned = IntrinsicID == Intrinsic::aarch64_neon_saddv ||
1920 IntrinsicID == Intrinsic::aarch64_neon_smaxv ||
1921 IntrinsicID == Intrinsic::aarch64_neon_sminv;
1922
1923 auto OldDst = MI.getOperand(i: 0).getReg();
1924 auto OldDstTy = MRI.getType(Reg: OldDst);
1925 LLT NewDstTy = MRI.getType(Reg: MI.getOperand(i: 2).getReg()).getElementType();
1926 if (OldDstTy == NewDstTy)
1927 return true;
1928
1929 auto NewDst = MRI.createGenericVirtualRegister(Ty: NewDstTy);
1930
1931 Helper.Observer.changingInstr(MI);
1932 MI.getOperand(i: 0).setReg(NewDst);
1933 Helper.Observer.changedInstr(MI);
1934
1935 MIB.setInsertPt(MBB&: MIB.getMBB(), II: ++MIB.getInsertPt());
1936 MIB.buildExtOrTrunc(ExtOpc: IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT,
1937 Res: OldDst, Op: NewDst);
1938
1939 return true;
1940 }
1941 case Intrinsic::aarch64_neon_uaddlp:
1942 case Intrinsic::aarch64_neon_saddlp: {
1943 unsigned Opc = IntrinsicID == Intrinsic::aarch64_neon_uaddlp
1944 ? AArch64::G_UADDLP
1945 : AArch64::G_SADDLP;
1946 MIB.buildInstr(Opc, DstOps: {MI.getOperand(i: 0)}, SrcOps: {MI.getOperand(i: 2)});
1947 MI.eraseFromParent();
1948
1949 return true;
1950 }
1951 case Intrinsic::aarch64_neon_uaddlv:
1952 case Intrinsic::aarch64_neon_saddlv: {
1953 unsigned Opc = IntrinsicID == Intrinsic::aarch64_neon_uaddlv
1954 ? AArch64::G_UADDLV
1955 : AArch64::G_SADDLV;
1956 Register DstReg = MI.getOperand(i: 0).getReg();
1957 Register SrcReg = MI.getOperand(i: 2).getReg();
1958 LLT DstTy = MRI.getType(Reg: DstReg);
1959
1960 LLT MidTy, ExtTy;
1961 if (DstTy.isScalar() && DstTy.getScalarSizeInBits() <= 32) {
1962 ExtTy = LLT::integer(SizeInBits: 32);
1963 MidTy = LLT::fixed_vector(NumElements: 4, ScalarTy: ExtTy);
1964 } else {
1965 ExtTy = LLT::integer(SizeInBits: 64);
1966 MidTy = LLT::fixed_vector(NumElements: 2, ScalarTy: ExtTy);
1967 }
1968
1969 Register MidReg =
1970 MIB.buildInstr(Opc, DstOps: {MidTy}, SrcOps: {SrcReg})->getOperand(i: 0).getReg();
1971 Register ZeroReg =
1972 MIB.buildConstant(Res: LLT::integer(SizeInBits: 64), Val: 0)->getOperand(i: 0).getReg();
1973 Register ExtReg = MIB.buildInstr(Opc: AArch64::G_EXTRACT_VECTOR_ELT, DstOps: {ExtTy},
1974 SrcOps: {MidReg, ZeroReg})
1975 .getReg(Idx: 0);
1976
1977 if (DstTy.getScalarSizeInBits() < 32)
1978 MIB.buildTrunc(Res: DstReg, Op: ExtReg);
1979 else
1980 MIB.buildCopy(Res: DstReg, Op: ExtReg);
1981
1982 MI.eraseFromParent();
1983
1984 return true;
1985 }
1986 case Intrinsic::aarch64_neon_fmax:
1987 return LowerBinOp(TargetOpcode::G_FMAXIMUM);
1988 case Intrinsic::aarch64_neon_fmin:
1989 return LowerBinOp(TargetOpcode::G_FMINIMUM);
1990 case Intrinsic::aarch64_neon_fmaxnm:
1991 return LowerBinOp(TargetOpcode::G_FMAXNUM);
1992 case Intrinsic::aarch64_neon_fminnm:
1993 return LowerBinOp(TargetOpcode::G_FMINNUM);
1994 case Intrinsic::aarch64_neon_pmul:
1995 return LowerBinOp(TargetOpcode::G_CLMUL);
1996 case Intrinsic::aarch64_neon_pmull:
1997 case Intrinsic::aarch64_neon_pmull64:
1998 return LowerBinOp(AArch64::G_PMULL);
1999 case Intrinsic::aarch64_neon_smull:
2000 return LowerBinOp(AArch64::G_SMULL);
2001 case Intrinsic::aarch64_neon_umull:
2002 return LowerBinOp(AArch64::G_UMULL);
2003 case Intrinsic::aarch64_neon_sabd:
2004 return LowerBinOp(TargetOpcode::G_ABDS);
2005 case Intrinsic::aarch64_neon_uabd:
2006 return LowerBinOp(TargetOpcode::G_ABDU);
2007 case Intrinsic::aarch64_neon_uhadd:
2008 return LowerBinOp(TargetOpcode::G_UAVGFLOOR);
2009 case Intrinsic::aarch64_neon_urhadd:
2010 return LowerBinOp(TargetOpcode::G_UAVGCEIL);
2011 case Intrinsic::aarch64_neon_shadd:
2012 return LowerBinOp(TargetOpcode::G_SAVGFLOOR);
2013 case Intrinsic::aarch64_neon_srhadd:
2014 return LowerBinOp(TargetOpcode::G_SAVGCEIL);
2015 case Intrinsic::aarch64_neon_sqshrn: {
2016 if (!MRI.getType(Reg: MI.getOperand(i: 0).getReg()).isVector())
2017 return true;
2018 // Create right shift instruction. Store the output register in Shr.
2019 auto Shr = MIB.buildInstr(Opc: AArch64::G_VASHR,
2020 DstOps: {MRI.getType(Reg: MI.getOperand(i: 2).getReg())},
2021 SrcOps: {MI.getOperand(i: 2), MI.getOperand(i: 3).getImm()});
2022 // Build the narrow intrinsic, taking in Shr.
2023 MIB.buildInstr(Opc: TargetOpcode::G_TRUNC_SSAT_S, DstOps: {MI.getOperand(i: 0)}, SrcOps: {Shr});
2024 MI.eraseFromParent();
2025 return true;
2026 }
2027 case Intrinsic::aarch64_neon_sqshrun: {
2028 if (!MRI.getType(Reg: MI.getOperand(i: 0).getReg()).isVector())
2029 return true;
2030 // Create right shift instruction. Store the output register in Shr.
2031 auto Shr = MIB.buildInstr(Opc: AArch64::G_VASHR,
2032 DstOps: {MRI.getType(Reg: MI.getOperand(i: 2).getReg())},
2033 SrcOps: {MI.getOperand(i: 2), MI.getOperand(i: 3).getImm()});
2034 // Build the narrow intrinsic, taking in Shr.
2035 MIB.buildInstr(Opc: TargetOpcode::G_TRUNC_SSAT_U, DstOps: {MI.getOperand(i: 0)}, SrcOps: {Shr});
2036 MI.eraseFromParent();
2037 return true;
2038 }
2039 case Intrinsic::aarch64_neon_sqrshrn: {
2040 if (!MRI.getType(Reg: MI.getOperand(i: 0).getReg()).isVector())
2041 return true;
2042 // Create right shift instruction. Store the output register in Shr.
2043 auto Shr = MIB.buildInstr(Opc: AArch64::G_SRSHR_I,
2044 DstOps: {MRI.getType(Reg: MI.getOperand(i: 2).getReg())},
2045 SrcOps: {MI.getOperand(i: 2), MI.getOperand(i: 3).getImm()});
2046 // Build the narrow intrinsic, taking in Shr.
2047 MIB.buildInstr(Opc: TargetOpcode::G_TRUNC_SSAT_S, DstOps: {MI.getOperand(i: 0)}, SrcOps: {Shr});
2048 MI.eraseFromParent();
2049 return true;
2050 }
2051 case Intrinsic::aarch64_neon_sqrshrun: {
2052 if (!MRI.getType(Reg: MI.getOperand(i: 0).getReg()).isVector())
2053 return true;
2054 // Create right shift instruction. Store the output register in Shr.
2055 auto Shr = MIB.buildInstr(Opc: AArch64::G_SRSHR_I,
2056 DstOps: {MRI.getType(Reg: MI.getOperand(i: 2).getReg())},
2057 SrcOps: {MI.getOperand(i: 2), MI.getOperand(i: 3).getImm()});
2058 // Build the narrow intrinsic, taking in Shr.
2059 MIB.buildInstr(Opc: TargetOpcode::G_TRUNC_SSAT_U, DstOps: {MI.getOperand(i: 0)}, SrcOps: {Shr});
2060 MI.eraseFromParent();
2061 return true;
2062 }
2063 case Intrinsic::aarch64_neon_uqrshrn: {
2064 if (!MRI.getType(Reg: MI.getOperand(i: 0).getReg()).isVector())
2065 return true;
2066 // Create right shift instruction. Store the output register in Shr.
2067 auto Shr = MIB.buildInstr(Opc: AArch64::G_URSHR_I,
2068 DstOps: {MRI.getType(Reg: MI.getOperand(i: 2).getReg())},
2069 SrcOps: {MI.getOperand(i: 2), MI.getOperand(i: 3).getImm()});
2070 // Build the narrow intrinsic, taking in Shr.
2071 MIB.buildInstr(Opc: TargetOpcode::G_TRUNC_USAT_U, DstOps: {MI.getOperand(i: 0)}, SrcOps: {Shr});
2072 MI.eraseFromParent();
2073 return true;
2074 }
2075 case Intrinsic::aarch64_neon_uqshrn: {
2076 if (!MRI.getType(Reg: MI.getOperand(i: 0).getReg()).isVector())
2077 return true;
2078 // Create right shift instruction. Store the output register in Shr.
2079 auto Shr = MIB.buildInstr(Opc: AArch64::G_VLSHR,
2080 DstOps: {MRI.getType(Reg: MI.getOperand(i: 2).getReg())},
2081 SrcOps: {MI.getOperand(i: 2), MI.getOperand(i: 3).getImm()});
2082 // Build the narrow intrinsic, taking in Shr.
2083 MIB.buildInstr(Opc: TargetOpcode::G_TRUNC_USAT_U, DstOps: {MI.getOperand(i: 0)}, SrcOps: {Shr});
2084 MI.eraseFromParent();
2085 return true;
2086 }
2087 case Intrinsic::aarch64_neon_sqshlu: {
2088 // Check if last operand is constant vector dup
2089 auto ShiftAmount =
2090 isConstantOrConstantSplatVector(Def: MI.getOperand(i: 3).getReg(), MRI);
2091 if (ShiftAmount) {
2092 // If so, create a new intrinsic with the correct shift amount
2093 MIB.buildInstr(Opc: AArch64::G_SQSHLU_I, DstOps: {MI.getOperand(i: 0)},
2094 SrcOps: {MI.getOperand(i: 2)})
2095 .addImm(Val: ShiftAmount->getSExtValue());
2096 MI.eraseFromParent();
2097 return true;
2098 }
2099 return false;
2100 }
2101 case Intrinsic::aarch64_neon_vsli: {
2102 MIB.buildInstr(
2103 Opc: AArch64::G_SLI, DstOps: {MI.getOperand(i: 0)},
2104 SrcOps: {MI.getOperand(i: 2), MI.getOperand(i: 3), MI.getOperand(i: 4).getImm()});
2105 MI.eraseFromParent();
2106 break;
2107 }
2108 case Intrinsic::aarch64_neon_vsri: {
2109 MIB.buildInstr(
2110 Opc: AArch64::G_SRI, DstOps: {MI.getOperand(i: 0)},
2111 SrcOps: {MI.getOperand(i: 2), MI.getOperand(i: 3), MI.getOperand(i: 4).getImm()});
2112 MI.eraseFromParent();
2113 break;
2114 }
2115 case Intrinsic::aarch64_neon_abs: {
2116 // Lower the intrinsic to G_ABS.
2117 MIB.buildInstr(Opc: TargetOpcode::G_ABS, DstOps: {MI.getOperand(i: 0)}, SrcOps: {MI.getOperand(i: 2)});
2118 MI.eraseFromParent();
2119 return true;
2120 }
2121 case Intrinsic::aarch64_neon_addhn:
2122 return LowerBinOp(AArch64::G_ADDHN);
2123 case Intrinsic::aarch64_neon_sqadd: {
2124 if (MRI.getType(Reg: MI.getOperand(i: 0).getReg()).isVector())
2125 return LowerBinOp(TargetOpcode::G_SADDSAT);
2126 break;
2127 }
2128 case Intrinsic::aarch64_neon_sqsub: {
2129 if (MRI.getType(Reg: MI.getOperand(i: 0).getReg()).isVector())
2130 return LowerBinOp(TargetOpcode::G_SSUBSAT);
2131 break;
2132 }
2133 case Intrinsic::aarch64_neon_uqadd: {
2134 if (MRI.getType(Reg: MI.getOperand(i: 0).getReg()).isVector())
2135 return LowerBinOp(TargetOpcode::G_UADDSAT);
2136 break;
2137 }
2138 case Intrinsic::aarch64_neon_uqsub: {
2139 if (MRI.getType(Reg: MI.getOperand(i: 0).getReg()).isVector())
2140 return LowerBinOp(TargetOpcode::G_USUBSAT);
2141 break;
2142 }
2143 case Intrinsic::aarch64_neon_udot:
2144 return LowerTriOp(AArch64::G_UDOT);
2145 case Intrinsic::aarch64_neon_sdot:
2146 return LowerTriOp(AArch64::G_SDOT);
2147 case Intrinsic::aarch64_neon_usdot:
2148 return LowerTriOp(AArch64::G_USDOT);
2149 case Intrinsic::aarch64_neon_sqxtn:
2150 return LowerUnaryOp(TargetOpcode::G_TRUNC_SSAT_S);
2151 case Intrinsic::aarch64_neon_sqxtun:
2152 return LowerUnaryOp(TargetOpcode::G_TRUNC_SSAT_U);
2153 case Intrinsic::aarch64_neon_uqxtn:
2154 return LowerUnaryOp(TargetOpcode::G_TRUNC_USAT_U);
2155 case Intrinsic::aarch64_neon_fcvtzu:
2156 return LowerUnaryOp(TargetOpcode::G_FPTOUI_SAT);
2157 case Intrinsic::aarch64_neon_fcvtzs:
2158 return LowerUnaryOp(TargetOpcode::G_FPTOSI_SAT);
2159 case Intrinsic::aarch64_neon_cls:
2160 return LowerUnaryOp(TargetOpcode::G_CTLS);
2161
2162 case Intrinsic::vector_reverse:
2163 // TODO: Add support for vector_reverse
2164 return false;
2165 }
2166
2167 return true;
2168}
2169
2170bool AArch64LegalizerInfo::legalizeShlAshrLshr(
2171 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder,
2172 GISelChangeObserver &Observer) const {
2173 assert(MI.getOpcode() == TargetOpcode::G_ASHR ||
2174 MI.getOpcode() == TargetOpcode::G_LSHR ||
2175 MI.getOpcode() == TargetOpcode::G_SHL);
2176 // If the shift amount is a G_CONSTANT, promote it to a 64 bit type so the
2177 // imported patterns can select it later. Either way, it will be legal.
2178 Register AmtReg = MI.getOperand(i: 2).getReg();
2179 LLT AmtRegEltTy = MRI.getType(Reg: AmtReg).getScalarType();
2180 auto VRegAndVal = getIConstantVRegValWithLookThrough(VReg: AmtReg, MRI);
2181 if (!VRegAndVal)
2182 return true;
2183 // Check the shift amount is in range for an immediate form.
2184 int64_t Amount = VRegAndVal->Value.getSExtValue();
2185 if (Amount > 31)
2186 return true; // This will have to remain a register variant.
2187 auto ExtCst =
2188 MIRBuilder.buildConstant(Res: AmtRegEltTy.changeElementSize(NewEltSize: 64), Val: Amount);
2189 Observer.changingInstr(MI);
2190 MI.getOperand(i: 2).setReg(ExtCst.getReg(Idx: 0));
2191 Observer.changedInstr(MI);
2192 return true;
2193}
2194
2195static void matchLDPSTPAddrMode(Register Root, Register &Base, int &Offset,
2196 MachineRegisterInfo &MRI) {
2197 Base = Root;
2198 Offset = 0;
2199
2200 Register NewBase;
2201 int64_t NewOffset;
2202 if (mi_match(R: Root, MRI, P: m_GPtrAdd(L: m_Reg(R&: NewBase), R: m_ICst(Cst&: NewOffset))) &&
2203 isShiftedInt<7, 3>(x: NewOffset)) {
2204 Base = NewBase;
2205 Offset = NewOffset;
2206 }
2207}
2208
2209// FIXME: This should be removed and replaced with the generic bitcast legalize
2210// action.
2211bool AArch64LegalizerInfo::legalizeLoadStore(
2212 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder,
2213 GISelChangeObserver &Observer) const {
2214 assert(MI.getOpcode() == TargetOpcode::G_STORE ||
2215 MI.getOpcode() == TargetOpcode::G_LOAD);
2216 // Here we just try to handle vector loads/stores where our value type might
2217 // have pointer elements, which the SelectionDAG importer can't handle. To
2218 // allow the existing patterns for s64 to fire for p0, we just try to bitcast
2219 // the value to use s64 types.
2220
2221 // Custom legalization requires the instruction, if not deleted, must be fully
2222 // legalized. In order to allow further legalization of the inst, we create
2223 // a new instruction and erase the existing one.
2224
2225 Register ValReg = MI.getOperand(i: 0).getReg();
2226 const LLT ValTy = MRI.getType(Reg: ValReg);
2227
2228 if (ValTy == LLT::scalar(SizeInBits: 128)) {
2229
2230 AtomicOrdering Ordering = (*MI.memoperands_begin())->getSuccessOrdering();
2231 bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD;
2232 bool IsLoadAcquire = IsLoad && Ordering == AtomicOrdering::Acquire;
2233 bool IsStoreRelease = !IsLoad && Ordering == AtomicOrdering::Release;
2234 bool IsRcpC3 =
2235 ST->hasLSE2() && ST->hasRCPC3() && (IsLoadAcquire || IsStoreRelease);
2236
2237 LLT s64 = LLT::integer(SizeInBits: 64);
2238
2239 unsigned Opcode;
2240 if (IsRcpC3) {
2241 Opcode = IsLoad ? AArch64::LDIAPPX : AArch64::STILPX;
2242 } else {
2243 // For LSE2, loads/stores should have been converted to monotonic and had
2244 // a fence inserted after them.
2245 assert(Ordering == AtomicOrdering::Monotonic ||
2246 Ordering == AtomicOrdering::Unordered);
2247 assert(ST->hasLSE2() && "ldp/stp not single copy atomic without +lse2");
2248
2249 Opcode = IsLoad ? AArch64::LDPXi : AArch64::STPXi;
2250 }
2251
2252 MachineInstrBuilder NewI;
2253 if (IsLoad) {
2254 NewI = MIRBuilder.buildInstr(Opc: Opcode, DstOps: {s64, s64}, SrcOps: {});
2255 MIRBuilder.buildMergeLikeInstr(
2256 Res: ValReg, Ops: {NewI->getOperand(i: 0), NewI->getOperand(i: 1)});
2257 } else {
2258 auto Split = MIRBuilder.buildUnmerge(Res: s64, Op: MI.getOperand(i: 0));
2259 NewI = MIRBuilder.buildInstr(
2260 Opc: Opcode, DstOps: {}, SrcOps: {Split->getOperand(i: 0), Split->getOperand(i: 1)});
2261 }
2262
2263 if (IsRcpC3) {
2264 NewI.addUse(RegNo: MI.getOperand(i: 1).getReg());
2265 } else {
2266 Register Base;
2267 int Offset;
2268 matchLDPSTPAddrMode(Root: MI.getOperand(i: 1).getReg(), Base, Offset, MRI);
2269 NewI.addUse(RegNo: Base);
2270 NewI.addImm(Val: Offset / 8);
2271 }
2272
2273 NewI.cloneMemRefs(OtherMI: MI);
2274 constrainSelectedInstRegOperands(I&: *NewI, TII: *ST->getInstrInfo(),
2275 TRI: *MRI.getTargetRegisterInfo(),
2276 RBI: *ST->getRegBankInfo());
2277 MI.eraseFromParent();
2278 return true;
2279 }
2280
2281 if (!ValTy.isPointerVector() ||
2282 ValTy.getElementType().getAddressSpace() != 0) {
2283 LLVM_DEBUG(dbgs() << "Tried to do custom legalization on wrong load/store");
2284 return false;
2285 }
2286
2287 unsigned PtrSize = ValTy.getElementType().getSizeInBits();
2288 const LLT NewTy = LLT::vector(EC: ValTy.getElementCount(), ScalarTy: LLT::integer(SizeInBits: PtrSize));
2289 auto &MMO = **MI.memoperands_begin();
2290 MMO.setType(NewTy);
2291
2292 if (MI.getOpcode() == TargetOpcode::G_STORE) {
2293 auto Bitcast = MIRBuilder.buildBitcast(Dst: NewTy, Src: ValReg);
2294 MIRBuilder.buildStore(Val: Bitcast.getReg(Idx: 0), Addr: MI.getOperand(i: 1), MMO);
2295 } else {
2296 auto NewLoad = MIRBuilder.buildLoad(Res: NewTy, Addr: MI.getOperand(i: 1), MMO);
2297 MIRBuilder.buildBitcast(Dst: ValReg, Src: NewLoad);
2298 }
2299 MI.eraseFromParent();
2300 return true;
2301}
2302
2303bool AArch64LegalizerInfo::legalizeVaArg(MachineInstr &MI,
2304 MachineRegisterInfo &MRI,
2305 MachineIRBuilder &MIRBuilder) const {
2306 MachineFunction &MF = MIRBuilder.getMF();
2307 Align Alignment(MI.getOperand(i: 2).getImm());
2308 Register Dst = MI.getOperand(i: 0).getReg();
2309 Register ListPtr = MI.getOperand(i: 1).getReg();
2310
2311 LLT PtrTy = MRI.getType(Reg: ListPtr);
2312 LLT IntPtrTy = LLT::integer(SizeInBits: PtrTy.getSizeInBits());
2313
2314 const unsigned PtrSize = PtrTy.getSizeInBits() / 8;
2315 const Align PtrAlign = Align(PtrSize);
2316 auto List = MIRBuilder.buildLoad(
2317 Res: PtrTy, Addr: ListPtr,
2318 MMO&: *MF.getMachineMemOperand(PtrInfo: MachinePointerInfo(), F: MachineMemOperand::MOLoad,
2319 MemTy: PtrTy, BaseAlignment: PtrAlign));
2320
2321 MachineInstrBuilder DstPtr;
2322 if (Alignment > PtrAlign) {
2323 // Realign the list to the actual required alignment.
2324 auto AlignMinus1 =
2325 MIRBuilder.buildConstant(Res: IntPtrTy, Val: Alignment.value() - 1);
2326 auto ListTmp = MIRBuilder.buildPtrAdd(Res: PtrTy, Op0: List, Op1: AlignMinus1.getReg(Idx: 0));
2327 DstPtr = MIRBuilder.buildMaskLowPtrBits(Res: PtrTy, Op0: ListTmp, NumBits: Log2(A: Alignment));
2328 } else
2329 DstPtr = List;
2330
2331 LLT ValTy = MRI.getType(Reg: Dst);
2332 uint64_t ValSize = ValTy.getSizeInBits() / 8;
2333 MIRBuilder.buildLoad(
2334 Res: Dst, Addr: DstPtr,
2335 MMO&: *MF.getMachineMemOperand(PtrInfo: MachinePointerInfo(), F: MachineMemOperand::MOLoad,
2336 MemTy: ValTy, BaseAlignment: std::max(a: Alignment, b: PtrAlign)));
2337
2338 auto Size = MIRBuilder.buildConstant(Res: IntPtrTy, Val: alignTo(Size: ValSize, A: PtrAlign));
2339
2340 auto NewList = MIRBuilder.buildPtrAdd(Res: PtrTy, Op0: DstPtr, Op1: Size.getReg(Idx: 0));
2341
2342 MIRBuilder.buildStore(Val: NewList, Addr: ListPtr,
2343 MMO&: *MF.getMachineMemOperand(PtrInfo: MachinePointerInfo(),
2344 F: MachineMemOperand::MOStore,
2345 MemTy: PtrTy, BaseAlignment: PtrAlign));
2346
2347 MI.eraseFromParent();
2348 return true;
2349}
2350
2351bool AArch64LegalizerInfo::legalizeBitfieldExtract(
2352 MachineInstr &MI, MachineRegisterInfo &MRI, LegalizerHelper &Helper) const {
2353 // Only legal if we can select immediate forms.
2354 // TODO: Lower this otherwise.
2355 return getIConstantVRegValWithLookThrough(VReg: MI.getOperand(i: 2).getReg(), MRI) &&
2356 getIConstantVRegValWithLookThrough(VReg: MI.getOperand(i: 3).getReg(), MRI);
2357}
2358
2359bool AArch64LegalizerInfo::legalizeCTPOP(MachineInstr &MI,
2360 MachineRegisterInfo &MRI,
2361 LegalizerHelper &Helper) const {
2362 // When there is no integer popcount instruction (FEAT_CSSC isn't available),
2363 // it can be more efficiently lowered to the following sequence that uses
2364 // AdvSIMD registers/instructions as long as the copies to/from the AdvSIMD
2365 // registers are cheap.
2366 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
2367 // CNT V0.8B, V0.8B // 8xbyte pop-counts
2368 // ADDV B0, V0.8B // sum 8xbyte pop-counts
2369 // UMOV X0, V0.B[0] // copy byte result back to integer reg
2370 //
2371 // For 128 bit vector popcounts, we lower to the following sequence:
2372 // cnt.16b v0, v0 // v8s16, v4s32, v2s64
2373 // uaddlp.8h v0, v0 // v8s16, v4s32, v2s64
2374 // uaddlp.4s v0, v0 // v4s32, v2s64
2375 // uaddlp.2d v0, v0 // v2s64
2376 //
2377 // For 64 bit vector popcounts, we lower to the following sequence:
2378 // cnt.8b v0, v0 // v4s16, v2s32
2379 // uaddlp.4h v0, v0 // v4s16, v2s32
2380 // uaddlp.2s v0, v0 // v2s32
2381
2382 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
2383 Register Dst = MI.getOperand(i: 0).getReg();
2384 Register Val = MI.getOperand(i: 1).getReg();
2385 LLT Ty = MRI.getType(Reg: Val);
2386
2387 LLT i64 = LLT::integer(SizeInBits: 64);
2388 LLT i32 = LLT::integer(SizeInBits: 32);
2389 LLT i16 = LLT::integer(SizeInBits: 16);
2390 LLT i8 = LLT::integer(SizeInBits: 8);
2391 unsigned Size = Ty.getSizeInBits();
2392
2393 assert(Ty == MRI.getType(Dst) &&
2394 "Expected src and dst to have the same type!");
2395
2396 if (ST->hasCSSC() && Ty.isScalar() && Size == 128) {
2397
2398 auto Split = MIRBuilder.buildUnmerge(Res: i64, Op: Val);
2399 auto CTPOP1 = MIRBuilder.buildCTPOP(Dst: i64, Src0: Split->getOperand(i: 0));
2400 auto CTPOP2 = MIRBuilder.buildCTPOP(Dst: i64, Src0: Split->getOperand(i: 1));
2401 auto Add = MIRBuilder.buildAdd(Dst: i64, Src0: CTPOP1, Src1: CTPOP2);
2402
2403 MIRBuilder.buildZExt(Res: Dst, Op: Add);
2404 MI.eraseFromParent();
2405 return true;
2406 }
2407
2408 if (!ST->hasNEON() ||
2409 MI.getMF()->getFunction().hasFnAttribute(Kind: Attribute::NoImplicitFloat)) {
2410 // Use generic lowering when custom lowering is not possible.
2411 return Ty.isScalar() && (Size == 32 || Size == 64) &&
2412 Helper.lowerBitCount(MI) ==
2413 LegalizerHelper::LegalizeResult::Legalized;
2414 }
2415
2416 // Pre-conditioning: widen Val up to the nearest vector type.
2417 // s32,s64,v4s16,v2s32 -> v8i8
2418 // v8s16,v4s32,v2s64 -> v16i8
2419 LLT VTy = Size == 128 ? LLT::fixed_vector(NumElements: 16, ScalarTy: i8) : LLT::fixed_vector(NumElements: 8, ScalarTy: i8);
2420 if (Ty.isScalar()) {
2421 assert((Size == 32 || Size == 64 || Size == 128) && "Expected only 32, 64, or 128 bit scalars!");
2422 if (Size == 32) {
2423 Val = MIRBuilder.buildZExt(Res: i64, Op: Val).getReg(Idx: 0);
2424 }
2425 }
2426 Val = MIRBuilder.buildBitcast(Dst: VTy, Src: Val).getReg(Idx: 0);
2427
2428 // Count bits in each byte-sized lane.
2429 auto CTPOP = MIRBuilder.buildCTPOP(Dst: VTy, Src0: Val);
2430
2431 // Sum across lanes.
2432 if (ST->hasDotProd() && Ty.isVector() && Ty.getNumElements() >= 2 &&
2433 Ty.getScalarSizeInBits() != 16) {
2434 LLT Dt = Ty == LLT::fixed_vector(NumElements: 2, ScalarTy: i64) ? LLT::fixed_vector(NumElements: 4, ScalarTy: i32) : Ty;
2435 auto Zeros = MIRBuilder.buildConstant(Res: Dt, Val: 0);
2436 auto Ones = MIRBuilder.buildConstant(Res: VTy, Val: 1);
2437 MachineInstrBuilder Sum;
2438
2439 if (Ty == LLT::fixed_vector(NumElements: 2, ScalarTy: i64)) {
2440 auto UDOT =
2441 MIRBuilder.buildInstr(Opc: AArch64::G_UDOT, DstOps: {Dt}, SrcOps: {Zeros, Ones, CTPOP});
2442 Sum = MIRBuilder.buildInstr(Opc: AArch64::G_UADDLP, DstOps: {Ty}, SrcOps: {UDOT});
2443 } else if (Ty == LLT::fixed_vector(NumElements: 4, ScalarTy: i32)) {
2444 Sum = MIRBuilder.buildInstr(Opc: AArch64::G_UDOT, DstOps: {Dt}, SrcOps: {Zeros, Ones, CTPOP});
2445 } else if (Ty == LLT::fixed_vector(NumElements: 2, ScalarTy: i32)) {
2446 Sum = MIRBuilder.buildInstr(Opc: AArch64::G_UDOT, DstOps: {Dt}, SrcOps: {Zeros, Ones, CTPOP});
2447 } else {
2448 llvm_unreachable("unexpected vector shape");
2449 }
2450
2451 Sum->getOperand(i: 0).setReg(Dst);
2452 MI.eraseFromParent();
2453 return true;
2454 }
2455
2456 Register HSum = CTPOP.getReg(Idx: 0);
2457 unsigned Opc;
2458 SmallVector<LLT> HAddTys;
2459 if (Ty.isScalar()) {
2460 Opc = Intrinsic::aarch64_neon_uaddlv;
2461 HAddTys.push_back(Elt: i32);
2462 } else if (Ty == LLT::fixed_vector(NumElements: 8, ScalarTy: i16)) {
2463 Opc = Intrinsic::aarch64_neon_uaddlp;
2464 HAddTys.push_back(Elt: LLT::fixed_vector(NumElements: 8, ScalarTy: i16));
2465 } else if (Ty == LLT::fixed_vector(NumElements: 4, ScalarTy: i32)) {
2466 Opc = Intrinsic::aarch64_neon_uaddlp;
2467 HAddTys.push_back(Elt: LLT::fixed_vector(NumElements: 8, ScalarTy: i16));
2468 HAddTys.push_back(Elt: LLT::fixed_vector(NumElements: 4, ScalarTy: i32));
2469 } else if (Ty == LLT::fixed_vector(NumElements: 2, ScalarTy: i64)) {
2470 Opc = Intrinsic::aarch64_neon_uaddlp;
2471 HAddTys.push_back(Elt: LLT::fixed_vector(NumElements: 8, ScalarTy: i16));
2472 HAddTys.push_back(Elt: LLT::fixed_vector(NumElements: 4, ScalarTy: i32));
2473 HAddTys.push_back(Elt: LLT::fixed_vector(NumElements: 2, ScalarTy: i64));
2474 } else if (Ty == LLT::fixed_vector(NumElements: 4, ScalarTy: i16)) {
2475 Opc = Intrinsic::aarch64_neon_uaddlp;
2476 HAddTys.push_back(Elt: LLT::fixed_vector(NumElements: 4, ScalarTy: i16));
2477 } else if (Ty == LLT::fixed_vector(NumElements: 2, ScalarTy: i32)) {
2478 Opc = Intrinsic::aarch64_neon_uaddlp;
2479 HAddTys.push_back(Elt: LLT::fixed_vector(NumElements: 4, ScalarTy: i16));
2480 HAddTys.push_back(Elt: LLT::fixed_vector(NumElements: 2, ScalarTy: i32));
2481 } else
2482 llvm_unreachable("unexpected vector shape");
2483 MachineInstrBuilder UADD;
2484 for (LLT HTy : HAddTys) {
2485 UADD = MIRBuilder.buildIntrinsic(ID: Opc, Res: {HTy}).addUse(RegNo: HSum);
2486 HSum = UADD.getReg(Idx: 0);
2487 }
2488
2489 // Post-conditioning.
2490 if (Ty.isScalar() && (Size == 64 || Size == 128))
2491 MIRBuilder.buildZExt(Res: Dst, Op: UADD);
2492 else
2493 UADD->getOperand(i: 0).setReg(Dst);
2494 MI.eraseFromParent();
2495 return true;
2496}
2497
2498bool AArch64LegalizerInfo::legalizeAtomicCmpxchg128(
2499 MachineInstr &MI, MachineRegisterInfo &MRI, LegalizerHelper &Helper) const {
2500 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
2501 LLT i64 = LLT::integer(SizeInBits: 64);
2502 auto Addr = MI.getOperand(i: 1).getReg();
2503 auto DesiredI = MIRBuilder.buildUnmerge(Res: {i64, i64}, Op: MI.getOperand(i: 2));
2504 auto NewI = MIRBuilder.buildUnmerge(Res: {i64, i64}, Op: MI.getOperand(i: 3));
2505 auto DstLo = MRI.createGenericVirtualRegister(Ty: i64);
2506 auto DstHi = MRI.createGenericVirtualRegister(Ty: i64);
2507
2508 MachineInstrBuilder CAS;
2509 if (ST->hasLSE()) {
2510 // We have 128-bit CASP instructions taking XSeqPair registers, which are
2511 // s128. We need the merge/unmerge to bracket the expansion and pair up with
2512 // the rest of the MIR so we must reassemble the extracted registers into a
2513 // 128-bit known-regclass one with code like this:
2514 //
2515 // %in1 = REG_SEQUENCE Lo, Hi ; One for each input
2516 // %out = CASP %in1, ...
2517 // %OldLo = G_EXTRACT %out, 0
2518 // %OldHi = G_EXTRACT %out, 64
2519 auto Ordering = (*MI.memoperands_begin())->getMergedOrdering();
2520 unsigned Opcode;
2521 switch (Ordering) {
2522 case AtomicOrdering::Acquire:
2523 Opcode = AArch64::CASPAX;
2524 break;
2525 case AtomicOrdering::Release:
2526 Opcode = AArch64::CASPLX;
2527 break;
2528 case AtomicOrdering::AcquireRelease:
2529 case AtomicOrdering::SequentiallyConsistent:
2530 Opcode = AArch64::CASPALX;
2531 break;
2532 default:
2533 Opcode = AArch64::CASPX;
2534 break;
2535 }
2536
2537 LLT s128 = LLT::integer(SizeInBits: 128);
2538 auto CASDst = MRI.createGenericVirtualRegister(Ty: s128);
2539 auto CASDesired = MRI.createGenericVirtualRegister(Ty: s128);
2540 auto CASNew = MRI.createGenericVirtualRegister(Ty: s128);
2541 MIRBuilder.buildInstr(Opc: TargetOpcode::REG_SEQUENCE, DstOps: {CASDesired}, SrcOps: {})
2542 .addUse(RegNo: DesiredI->getOperand(i: 0).getReg())
2543 .addImm(Val: AArch64::sube64)
2544 .addUse(RegNo: DesiredI->getOperand(i: 1).getReg())
2545 .addImm(Val: AArch64::subo64);
2546 MIRBuilder.buildInstr(Opc: TargetOpcode::REG_SEQUENCE, DstOps: {CASNew}, SrcOps: {})
2547 .addUse(RegNo: NewI->getOperand(i: 0).getReg())
2548 .addImm(Val: AArch64::sube64)
2549 .addUse(RegNo: NewI->getOperand(i: 1).getReg())
2550 .addImm(Val: AArch64::subo64);
2551
2552 CAS = MIRBuilder.buildInstr(Opc: Opcode, DstOps: {CASDst}, SrcOps: {CASDesired, CASNew, Addr});
2553
2554 MIRBuilder.buildExtract(Res: {DstLo}, Src: {CASDst}, Index: 0);
2555 MIRBuilder.buildExtract(Res: {DstHi}, Src: {CASDst}, Index: 64);
2556 } else {
2557 // The -O0 CMP_SWAP_128 is friendlier to generate code for because LDXP/STXP
2558 // can take arbitrary registers so it just has the normal GPR64 operands the
2559 // rest of AArch64 is expecting.
2560 auto Ordering = (*MI.memoperands_begin())->getMergedOrdering();
2561 unsigned Opcode;
2562 switch (Ordering) {
2563 case AtomicOrdering::Acquire:
2564 Opcode = AArch64::CMP_SWAP_128_ACQUIRE;
2565 break;
2566 case AtomicOrdering::Release:
2567 Opcode = AArch64::CMP_SWAP_128_RELEASE;
2568 break;
2569 case AtomicOrdering::AcquireRelease:
2570 case AtomicOrdering::SequentiallyConsistent:
2571 Opcode = AArch64::CMP_SWAP_128;
2572 break;
2573 default:
2574 Opcode = AArch64::CMP_SWAP_128_MONOTONIC;
2575 break;
2576 }
2577
2578 auto Scratch = MRI.createVirtualRegister(RegClass: &AArch64::GPR64RegClass);
2579 CAS = MIRBuilder.buildInstr(Opc: Opcode, DstOps: {DstLo, DstHi, Scratch},
2580 SrcOps: {Addr, DesiredI->getOperand(i: 0),
2581 DesiredI->getOperand(i: 1), NewI->getOperand(i: 0),
2582 NewI->getOperand(i: 1)});
2583 }
2584
2585 CAS.cloneMemRefs(OtherMI: MI);
2586 constrainSelectedInstRegOperands(I&: *CAS, TII: *ST->getInstrInfo(),
2587 TRI: *MRI.getTargetRegisterInfo(),
2588 RBI: *ST->getRegBankInfo());
2589
2590 MIRBuilder.buildMergeLikeInstr(Res: MI.getOperand(i: 0), Ops: {DstLo, DstHi});
2591 MI.eraseFromParent();
2592 return true;
2593}
2594
2595bool AArch64LegalizerInfo::legalizeCTTZ(MachineInstr &MI,
2596 LegalizerHelper &Helper) const {
2597 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
2598 MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
2599 LLT Ty = MRI.getType(Reg: MI.getOperand(i: 1).getReg());
2600 auto BitReverse = MIRBuilder.buildBitReverse(Dst: Ty, Src: MI.getOperand(i: 1));
2601 MIRBuilder.buildCTLZ(Dst: MI.getOperand(i: 0).getReg(), Src0: BitReverse);
2602 MI.eraseFromParent();
2603 return true;
2604}
2605
2606bool AArch64LegalizerInfo::legalizeMemOps(MachineInstr &MI,
2607 LegalizerHelper &Helper) const {
2608 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
2609
2610 // Tagged version MOPSMemorySetTagged is legalised in legalizeIntrinsic
2611 if (MI.getOpcode() == TargetOpcode::G_MEMSET ||
2612 MI.getOpcode() == TargetOpcode::G_MEMSET_INLINE) {
2613 // Anyext the value being set to 64 bit (only the bottom 8 bits are read by
2614 // the instruction).
2615 auto &Value = MI.getOperand(i: 1);
2616 Register ExtValueReg =
2617 MIRBuilder.buildAnyExt(Res: LLT::integer(SizeInBits: 64), Op: Value).getReg(Idx: 0);
2618 Value.setReg(ExtValueReg);
2619 return true;
2620 }
2621
2622 return false;
2623}
2624
2625bool AArch64LegalizerInfo::legalizeExtractVectorElt(
2626 MachineInstr &MI, MachineRegisterInfo &MRI, LegalizerHelper &Helper) const {
2627 const GExtractVectorElement *Element = cast<GExtractVectorElement>(Val: &MI);
2628 auto VRegAndVal =
2629 getIConstantVRegValWithLookThrough(VReg: Element->getIndexReg(), MRI);
2630 if (VRegAndVal)
2631 return true;
2632 LLT VecTy = MRI.getType(Reg: Element->getVectorReg());
2633 if (VecTy.isScalableVector())
2634 return true;
2635 return Helper.lowerExtractInsertVectorElt(MI) !=
2636 LegalizerHelper::LegalizeResult::UnableToLegalize;
2637}
2638
2639bool AArch64LegalizerInfo::legalizeDynStackAlloc(
2640 MachineInstr &MI, LegalizerHelper &Helper) const {
2641 MachineFunction &MF = *MI.getParent()->getParent();
2642 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
2643 MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
2644
2645 // If stack probing is not enabled for this function, use the default
2646 // lowering.
2647 if (!MF.getFunction().hasFnAttribute(Kind: "probe-stack") ||
2648 MF.getFunction().getFnAttribute(Kind: "probe-stack").getValueAsString() !=
2649 "inline-asm") {
2650 Helper.lowerDynStackAlloc(MI);
2651 return true;
2652 }
2653
2654 Register Dst = MI.getOperand(i: 0).getReg();
2655 Register AllocSize = MI.getOperand(i: 1).getReg();
2656 Align Alignment = assumeAligned(Value: MI.getOperand(i: 2).getImm());
2657
2658 assert(MRI.getType(Dst) == LLT::pointer(0, 64) &&
2659 "Unexpected type for dynamic alloca");
2660 assert(MRI.getType(AllocSize) == LLT::scalar(64) &&
2661 "Unexpected type for dynamic alloca");
2662
2663 LLT PtrTy = MRI.getType(Reg: Dst);
2664 Register SPReg =
2665 Helper.getTargetLowering().getStackPointerRegisterToSaveRestore();
2666 Register SPTmp =
2667 Helper.getDynStackAllocTargetPtr(SPReg, AllocSize, Alignment, PtrTy);
2668 auto NewMI =
2669 MIRBuilder.buildInstr(Opc: AArch64::PROBED_STACKALLOC_DYN, DstOps: {}, SrcOps: {SPTmp});
2670 MRI.setRegClass(Reg: NewMI.getReg(Idx: 0), RC: &AArch64::GPR64commonRegClass);
2671 MIRBuilder.setInsertPt(MBB&: *NewMI->getParent(), II: NewMI);
2672 MIRBuilder.buildCopy(Res: Dst, Op: SPTmp);
2673
2674 MI.eraseFromParent();
2675 return true;
2676}
2677
2678bool AArch64LegalizerInfo::legalizePrefetch(MachineInstr &MI,
2679 LegalizerHelper &Helper) const {
2680 MachineIRBuilder &MIB = Helper.MIRBuilder;
2681 auto &AddrVal = MI.getOperand(i: 0);
2682
2683 int64_t IsWrite = MI.getOperand(i: 1).getImm();
2684 int64_t Locality = MI.getOperand(i: 2).getImm();
2685 int64_t IsData = MI.getOperand(i: 3).getImm();
2686
2687 bool IsStream = Locality == 0;
2688 if (Locality != 0) {
2689 assert(Locality <= 3 && "Prefetch locality out-of-range");
2690 // The locality degree is the opposite of the cache speed.
2691 // Put the number the other way around.
2692 // The encoding starts at 0 for level 1
2693 Locality = 3 - Locality;
2694 }
2695
2696 unsigned PrfOp = (IsWrite << 4) | (!IsData << 3) | (Locality << 1) | IsStream;
2697
2698 MIB.buildInstr(Opcode: AArch64::G_AARCH64_PREFETCH).addImm(Val: PrfOp).add(MO: AddrVal);
2699 MI.eraseFromParent();
2700 return true;
2701}
2702
2703bool AArch64LegalizerInfo::legalizeConcatVectors(
2704 MachineInstr &MI, MachineRegisterInfo &MRI,
2705 MachineIRBuilder &MIRBuilder) const {
2706 // Widen sub-byte element vectors to byte-sized elements before concatenating.
2707 // This is analogous to SDAG's integer type promotion for sub-byte types.
2708 auto &Concat = cast<GConcatVectors>(Val&: MI);
2709 Register DstReg = Concat.getReg(Idx: 0);
2710 LLT DstTy = MRI.getType(Reg: DstReg);
2711 assert(DstTy.getScalarSizeInBits() < 8 && "Expected dst ty to be < 8b");
2712
2713 unsigned WideEltSize =
2714 std::max(a: 8u, b: (unsigned)PowerOf2Ceil(A: DstTy.getScalarSizeInBits()));
2715 LLT SrcTy = MRI.getType(Reg: Concat.getSourceReg(I: 0));
2716 LLT WideSrcTy = SrcTy.changeElementSize(NewEltSize: WideEltSize);
2717 LLT WideDstTy = DstTy.changeElementSize(NewEltSize: WideEltSize);
2718
2719 SmallVector<Register> WideSrcs;
2720 for (unsigned I = 0; I < Concat.getNumSources(); ++I) {
2721 auto Wide = MIRBuilder.buildAnyExt(Res: WideSrcTy, Op: Concat.getSourceReg(I));
2722 WideSrcs.push_back(Elt: Wide.getReg(Idx: 0));
2723 }
2724
2725 auto WideConcat = MIRBuilder.buildConcatVectors(Res: WideDstTy, Ops: WideSrcs);
2726 MIRBuilder.buildTrunc(Res: DstReg, Op: WideConcat);
2727 MI.eraseFromParent();
2728 return true;
2729}
2730
2731bool AArch64LegalizerInfo::legalizeFptrunc(MachineInstr &MI,
2732 MachineIRBuilder &MIRBuilder,
2733 MachineRegisterInfo &MRI) const {
2734 auto [Dst, DstTy, Src, SrcTy] = MI.getFirst2RegLLTs();
2735
2736 // This function legalizes f64 -> bf16 and f64 -> f16 truncations via f64 ->
2737 // f32 G_FPTRUNC_ODD and f32 -> [b]f16 G_FPTRUNC, which apparently avoids the
2738 // usual double-rounding issue that could be present from using twin
2739 // G_FPTRUNC.
2740
2741 if (DstTy.isBFloat16() && SrcTy.isFloat64()) {
2742 auto Mid = MIRBuilder.buildInstr(Opc: AArch64::G_FPTRUNC_ODD, DstOps: {LLT::float32()},
2743 SrcOps: {Src}, Flags: MI.getFlags());
2744 MIRBuilder.buildInstr(Opc: AArch64::G_FPTRUNC, DstOps: {Dst}, SrcOps: {Mid}, Flags: MI.getFlags());
2745 MI.eraseFromParent();
2746 return true;
2747 }
2748
2749 assert(SrcTy.isFixedVector() && isPowerOf2_32(SrcTy.getNumElements()) &&
2750 "Expected a power of 2 elements");
2751
2752 // We must mutate types here as FPTrunc may be used on a IEEE floating point
2753 // or a brainfloat.
2754 LLT v2s16 = DstTy.changeElementCount(NumElements: 2);
2755 LLT v4s16 = DstTy.changeElementCount(NumElements: 4);
2756 LLT v2s32 = SrcTy.changeElementCount(NumElements: 2).changeElementSize(NewEltSize: 32);
2757 LLT v4s32 = SrcTy.changeElementCount(NumElements: 4).changeElementSize(NewEltSize: 32);
2758 LLT v2s64 = SrcTy.changeElementCount(NumElements: 2);
2759
2760 SmallVector<Register> RegsToUnmergeTo;
2761 SmallVector<Register> TruncOddDstRegs;
2762 SmallVector<Register> RegsToMerge;
2763
2764 unsigned ElemCount = SrcTy.getNumElements();
2765
2766 // Find the biggest size chunks we can work with
2767 int StepSize = ElemCount % 4 ? 2 : 4;
2768
2769 // If we have a power of 2 greater than 2, we need to first unmerge into
2770 // enough pieces
2771 if (ElemCount <= 2)
2772 RegsToUnmergeTo.push_back(Elt: Src);
2773 else {
2774 for (unsigned i = 0; i < ElemCount / 2; ++i)
2775 RegsToUnmergeTo.push_back(Elt: MRI.createGenericVirtualRegister(Ty: v2s64));
2776
2777 MIRBuilder.buildUnmerge(Res: RegsToUnmergeTo, Op: Src);
2778 }
2779
2780 // Create all of the round-to-odd instructions and store them
2781 for (auto SrcReg : RegsToUnmergeTo) {
2782 Register Mid = MIRBuilder
2783 .buildInstr(Opc: AArch64::G_FPTRUNC_ODD, DstOps: {v2s32}, SrcOps: {SrcReg},
2784 Flags: MI.getFlags())
2785 .getReg(Idx: 0);
2786 TruncOddDstRegs.push_back(Elt: Mid);
2787 }
2788
2789 // Truncate 4s32 to 4s16 if we can to reduce instruction count, otherwise
2790 // truncate 2s32 to 2s16.
2791 unsigned Index = 0;
2792 for (unsigned LoopIter = 0; LoopIter < ElemCount / StepSize; ++LoopIter) {
2793 if (StepSize == 4) {
2794 Register ConcatDst =
2795 MIRBuilder
2796 .buildMergeLikeInstr(
2797 Res: {v4s32}, Ops: {TruncOddDstRegs[Index++], TruncOddDstRegs[Index++]})
2798 .getReg(Idx: 0);
2799
2800 RegsToMerge.push_back(
2801 Elt: MIRBuilder.buildFPTrunc(Res: v4s16, Op: ConcatDst, Flags: MI.getFlags()).getReg(Idx: 0));
2802 } else {
2803 RegsToMerge.push_back(
2804 Elt: MIRBuilder
2805 .buildFPTrunc(Res: v2s16, Op: TruncOddDstRegs[Index++], Flags: MI.getFlags())
2806 .getReg(Idx: 0));
2807 }
2808 }
2809
2810 // If there is only one register, replace the destination
2811 if (RegsToMerge.size() == 1) {
2812 MRI.replaceRegWith(FromReg: Dst, ToReg: RegsToMerge.pop_back_val());
2813 MI.eraseFromParent();
2814 return true;
2815 }
2816
2817 // Merge the rest of the instructions & replace the register
2818 Register Fin = MIRBuilder.buildMergeLikeInstr(Res: DstTy, Ops: RegsToMerge).getReg(Idx: 0);
2819 MRI.replaceRegWith(FromReg: Dst, ToReg: Fin);
2820 MI.eraseFromParent();
2821 return true;
2822}
2823
2824bool AArch64LegalizerInfo::legalizeGetRounding(MachineInstr &MI,
2825 MachineIRBuilder &MIRBuilder,
2826 MachineRegisterInfo &MRI,
2827 LegalizerHelper &Helper) const {
2828 const LLT I32 = LLT::integer(SizeInBits: 32);
2829 const LLT I64 = LLT::integer(SizeInBits: 64);
2830
2831 Register Dst = MI.getOperand(i: 0).getReg();
2832 Register FPCR64 = MRI.createGenericVirtualRegister(Ty: I64);
2833 MachineInstrBuilder GetFPCR =
2834 MIRBuilder.buildIntrinsic(ID: Intrinsic::aarch64_get_fpcr, Res: ArrayRef{FPCR64});
2835
2836 // AArch64 rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3,
2837 // 3->0, so we add one to the FPCR bits for the rounding mode.
2838 // Instead of shifting and then adding as `((FPCR >> 22) + 1) & 0b11` which
2839 // generates 3 instructions, we increment the rounding mode with
2840 // `(FPCR + (1 << 22))` and extract the bits. The shift and addition is done
2841 // in one instruction as `add .., .., #1024, lsl #12`, so overall we generate
2842 // one less instruction.
2843 auto FPCR32 = MIRBuilder.buildTrunc(Res: I32, Op: GetFPCR);
2844 auto One = MIRBuilder.buildConstant(Res: I32, Val: 1U << 22);
2845 auto Added = MIRBuilder.buildAdd(Dst: I32, Src0: FPCR32, Src1: One);
2846 auto LSB = MIRBuilder.buildConstant(Res: I32, Val: 22);
2847 auto Width = MIRBuilder.buildConstant(Res: I32, Val: 2);
2848 MIRBuilder.buildInstr(Opc: TargetOpcode::G_UBFX, DstOps: {Dst}, SrcOps: {Added, LSB, Width});
2849
2850 MI.eraseFromParent();
2851 return true;
2852}
2853
2854bool AArch64LegalizerInfo::legalizeSetRounding(MachineInstr &MI,
2855 MachineIRBuilder &MIRBuilder,
2856 MachineRegisterInfo &MRI,
2857 LegalizerHelper &Helper) const {
2858 const LLT I32 = LLT::integer(SizeInBits: 32);
2859 const LLT I64 = LLT::integer(SizeInBits: 64);
2860
2861 // AArch64 rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3,
2862 // 3->0, so calculate the new value of FPCR[23:22] as `((arg - 1) & 3) << 22`.
2863 Register RM = MI.getOperand(i: 0).getReg();
2864 auto One = MIRBuilder.buildConstant(Res: I32, Val: 1);
2865 auto Subtracted = MIRBuilder.buildSub(Dst: I32, Src0: RM, Src1: One);
2866 auto Mask = MIRBuilder.buildConstant(Res: I32, Val: 0b11);
2867 auto Masked = MIRBuilder.buildAnd(Dst: I32, Src0: Subtracted, Src1: Mask);
2868 auto ShiftAmount = MIRBuilder.buildConstant(Res: I32, Val: 22);
2869 auto Shifted = MIRBuilder.buildShl(Dst: I32, Src0: Masked, Src1: ShiftAmount);
2870
2871 // Get current value of FPCR.
2872 MachineInstrBuilder GetFPCR =
2873 MIRBuilder.buildIntrinsic(ID: Intrinsic::aarch64_get_fpcr, Res: {I64});
2874
2875 // (FPCR & ~Mask) | Shifted
2876 auto FPCRMask = MIRBuilder.buildConstant(Res: I64, Val: ~((int64_t)0b11 << 22));
2877 auto FPCRMasked = MIRBuilder.buildAnd(Dst: I64, Src0: GetFPCR, Src1: FPCRMask);
2878 auto ShiftedS64 = MIRBuilder.buildZExt(Res: I64, Op: Shifted);
2879 auto FPCRUpdated = MIRBuilder.buildOr(Dst: I64, Src0: FPCRMasked, Src1: ShiftedS64);
2880
2881 // Write new FPCR.
2882 MIRBuilder.buildIntrinsic(ID: Intrinsic::aarch64_set_fpcr, Res: ArrayRef<Register>())
2883 .addUse(RegNo: FPCRUpdated.getReg(Idx: 0));
2884
2885 MI.eraseFromParent();
2886
2887 return true;
2888}
2889