1//===-- AMDGPUPrepareAGPRAlloc.cpp ----------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Make simple transformations to relax register constraints for cases which can
10// allocate to AGPRs or VGPRs. Replace materialize of inline immediates into
11// AGPR or VGPR with a pseudo with an AV_* class register constraint. This
12// allows later passes to inflate the register class if necessary. The register
13// allocator does not know to replace instructions to relax constraints.
14//
15//===----------------------------------------------------------------------===//
16
17#include "AMDGPUPrepareAGPRAlloc.h"
18#include "AMDGPU.h"
19#include "GCNSubtarget.h"
20#include "SIMachineFunctionInfo.h"
21#include "SIRegisterInfo.h"
22#include "llvm/CodeGen/LiveIntervals.h"
23#include "llvm/CodeGen/MachineFunctionPass.h"
24#include "llvm/InitializePasses.h"
25
26using namespace llvm;
27
28#define DEBUG_TYPE "amdgpu-prepare-agpr-alloc"
29
30namespace {
31
32class AMDGPUPrepareAGPRAllocImpl {
33private:
34 const SIInstrInfo &TII;
35 MachineRegisterInfo &MRI;
36
37 bool isAV64Imm(const MachineOperand &MO) const;
38
39public:
40 AMDGPUPrepareAGPRAllocImpl(const GCNSubtarget &ST, MachineRegisterInfo &MRI)
41 : TII(*ST.getInstrInfo()), MRI(MRI) {}
42 bool run(MachineFunction &MF);
43};
44
45class AMDGPUPrepareAGPRAllocLegacy : public MachineFunctionPass {
46public:
47 static char ID;
48
49 AMDGPUPrepareAGPRAllocLegacy() : MachineFunctionPass(ID) {}
50
51 bool runOnMachineFunction(MachineFunction &MF) override;
52
53 StringRef getPassName() const override { return "AMDGPU Prepare AGPR Alloc"; }
54
55 void getAnalysisUsage(AnalysisUsage &AU) const override {
56 AU.setPreservesAll();
57 MachineFunctionPass::getAnalysisUsage(AU);
58 }
59};
60} // End anonymous namespace.
61
62INITIALIZE_PASS(AMDGPUPrepareAGPRAllocLegacy, DEBUG_TYPE,
63 "AMDGPU Prepare AGPR Alloc", false, false)
64
65char AMDGPUPrepareAGPRAllocLegacy::ID = 0;
66
67char &llvm::AMDGPUPrepareAGPRAllocLegacyID = AMDGPUPrepareAGPRAllocLegacy::ID;
68
69bool AMDGPUPrepareAGPRAllocLegacy::runOnMachineFunction(MachineFunction &MF) {
70 if (skipFunction(F: MF.getFunction()))
71 return false;
72
73 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
74 return AMDGPUPrepareAGPRAllocImpl(ST, MF.getRegInfo()).run(MF);
75}
76
77PreservedAnalyses
78AMDGPUPrepareAGPRAllocPass::run(MachineFunction &MF,
79 MachineFunctionAnalysisManager &MFAM) {
80 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
81 AMDGPUPrepareAGPRAllocImpl(ST, MF.getRegInfo()).run(MF);
82 return PreservedAnalyses::all();
83}
84
85bool AMDGPUPrepareAGPRAllocImpl::isAV64Imm(const MachineOperand &MO) const {
86 return MO.isImm() && TII.isLegalAV64PseudoImm(Imm: MO.getImm());
87}
88
89bool AMDGPUPrepareAGPRAllocImpl::run(MachineFunction &MF) {
90 if (MRI.isReserved(PhysReg: AMDGPU::AGPR0))
91 return false;
92
93 const MCInstrDesc &AVImmPseudo32 = TII.get(Opcode: AMDGPU::AV_MOV_B32_IMM_PSEUDO);
94 const MCInstrDesc &AVImmPseudo64 = TII.get(Opcode: AMDGPU::AV_MOV_B64_IMM_PSEUDO);
95
96 bool Changed = false;
97 for (MachineBasicBlock &MBB : MF) {
98 for (MachineInstr &MI : MBB) {
99 if ((MI.getOpcode() == AMDGPU::V_MOV_B32_e32 &&
100 TII.isInlineConstant(MI, OpIdx: 1)) ||
101 (MI.getOpcode() == AMDGPU::V_ACCVGPR_WRITE_B32_e64 &&
102 MI.getOperand(i: 1).isImm())) {
103 MI.setDesc(AVImmPseudo32);
104 Changed = true;
105 continue;
106 }
107
108 // TODO: If only half of the value is rewritable, is it worth splitting it
109 // up?
110 if ((MI.getOpcode() == AMDGPU::V_MOV_B64_e64 ||
111 MI.getOpcode() == AMDGPU::V_MOV_B64_PSEUDO) &&
112 isAV64Imm(MO: MI.getOperand(i: 1))) {
113 MI.setDesc(AVImmPseudo64);
114 Changed = true;
115 continue;
116 }
117 }
118 }
119
120 return Changed;
121}
122