1//===-- SIOptimizeExecMaskingPreRA.cpp ------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This pass performs exec mask handling peephole optimizations which needs
11/// to be done before register allocation to reduce register pressure.
12///
13//===----------------------------------------------------------------------===//
14
15#include "SIOptimizeExecMaskingPreRA.h"
16#include "AMDGPU.h"
17#include "AMDGPULaneMaskUtils.h"
18#include "GCNSubtarget.h"
19#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
20#include "llvm/CodeGen/LiveIntervals.h"
21#include "llvm/CodeGen/MachineFunctionPass.h"
22#include "llvm/InitializePasses.h"
23
24using namespace llvm;
25
26#define DEBUG_TYPE "si-optimize-exec-masking-pre-ra"
27
28namespace {
29
30class SIOptimizeExecMaskingPreRA {
31private:
32 const GCNSubtarget &ST;
33 const SIRegisterInfo *TRI;
34 const SIInstrInfo *TII;
35 MachineRegisterInfo *MRI;
36 LiveIntervals *LIS;
37 const AMDGPU::LaneMaskConstants &LMC;
38
39 MCRegister CondReg;
40 MCRegister ExecReg;
41
42 bool optimizeVcndVcmpPair(MachineBasicBlock &MBB);
43 bool optimizeElseBranch(MachineBasicBlock &MBB);
44
45public:
46 SIOptimizeExecMaskingPreRA(MachineFunction &MF, LiveIntervals *LIS)
47 : ST(MF.getSubtarget<GCNSubtarget>()), TRI(ST.getRegisterInfo()),
48 TII(ST.getInstrInfo()), MRI(&MF.getRegInfo()), LIS(LIS),
49 LMC(AMDGPU::LaneMaskConstants::get(ST)) {}
50 bool run(MachineFunction &MF);
51};
52
53class SIOptimizeExecMaskingPreRALegacy : public MachineFunctionPass {
54public:
55 static char ID;
56
57 SIOptimizeExecMaskingPreRALegacy() : MachineFunctionPass(ID) {}
58
59 bool runOnMachineFunction(MachineFunction &MF) override;
60
61 StringRef getPassName() const override {
62 return "SI optimize exec mask operations pre-RA";
63 }
64
65 void getAnalysisUsage(AnalysisUsage &AU) const override {
66 AU.addRequired<LiveIntervalsWrapperPass>();
67 AU.setPreservesAll();
68 MachineFunctionPass::getAnalysisUsage(AU);
69 }
70};
71
72} // End anonymous namespace.
73
74INITIALIZE_PASS_BEGIN(SIOptimizeExecMaskingPreRALegacy, DEBUG_TYPE,
75 "SI optimize exec mask operations pre-RA", false, false)
76INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
77INITIALIZE_PASS_END(SIOptimizeExecMaskingPreRALegacy, DEBUG_TYPE,
78 "SI optimize exec mask operations pre-RA", false, false)
79
80char SIOptimizeExecMaskingPreRALegacy::ID = 0;
81
82char &llvm::SIOptimizeExecMaskingPreRAID = SIOptimizeExecMaskingPreRALegacy::ID;
83
84FunctionPass *llvm::createSIOptimizeExecMaskingPreRAPass() {
85 return new SIOptimizeExecMaskingPreRALegacy();
86}
87
88// See if there is a def between \p AndIdx and \p SelIdx that needs to live
89// beyond \p AndIdx.
90static bool isDefBetween(const LiveRange &LR, SlotIndex AndIdx,
91 SlotIndex SelIdx) {
92 LiveQueryResult AndLRQ = LR.Query(Idx: AndIdx);
93 return (!AndLRQ.isKill() && AndLRQ.valueIn() != LR.Query(Idx: SelIdx).valueOut());
94}
95
96// FIXME: Why do we bother trying to handle physical registers here?
97static bool isDefBetween(const SIRegisterInfo &TRI,
98 LiveIntervals *LIS, Register Reg,
99 const MachineInstr &Sel, const MachineInstr &And) {
100 SlotIndex AndIdx = LIS->getInstructionIndex(Instr: And).getRegSlot();
101 SlotIndex SelIdx = LIS->getInstructionIndex(Instr: Sel).getRegSlot();
102
103 if (Reg.isVirtual())
104 return isDefBetween(LR: LIS->getInterval(Reg), AndIdx, SelIdx);
105
106 for (MCRegUnit Unit : TRI.regunits(Reg: Reg.asMCReg())) {
107 if (isDefBetween(LR: LIS->getRegUnit(Unit), AndIdx, SelIdx))
108 return true;
109 }
110
111 return false;
112}
113
114// Optimize sequence
115// %sel = V_CNDMASK_B32_e64 0, 1, %cc
116// %cmp = V_CMP_NE_U32 1, %sel
117// $vcc = S_AND_B64 $exec, %cmp
118// S_CBRANCH_VCC[N]Z
119// =>
120// $vcc = S_ANDN2_B64 $exec, %cc
121// S_CBRANCH_VCC[N]Z
122//
123// It is the negation pattern inserted by DAGCombiner::visitBRCOND() in the
124// rebuildSetCC(). We start with S_CBRANCH to avoid exhaustive search, but
125// only 3 first instructions are really needed. S_AND_B64 with exec is a
126// required part of the pattern since V_CNDMASK_B32 writes zeroes for inactive
127// lanes.
128//
129// Returns true on success.
130bool SIOptimizeExecMaskingPreRA::optimizeVcndVcmpPair(MachineBasicBlock &MBB) {
131 auto I = llvm::find_if(Range: MBB.terminators(), P: [](const MachineInstr &MI) {
132 unsigned Opc = MI.getOpcode();
133 return Opc == AMDGPU::S_CBRANCH_VCCZ ||
134 Opc == AMDGPU::S_CBRANCH_VCCNZ; });
135 if (I == MBB.terminators().end())
136 return false;
137
138 auto *And =
139 TRI->findReachingDef(Reg: CondReg, SubReg: AMDGPU::NoSubRegister, Use&: *I, MRI&: *MRI, LIS);
140 if (!And || And->getOpcode() != LMC.AndOpc || !And->getOperand(i: 1).isReg() ||
141 !And->getOperand(i: 2).isReg())
142 return false;
143
144 MachineOperand *AndCC = &And->getOperand(i: 1);
145 Register CmpReg = AndCC->getReg();
146 unsigned CmpSubReg = AndCC->getSubReg();
147 if (CmpReg == Register(ExecReg)) {
148 AndCC = &And->getOperand(i: 2);
149 CmpReg = AndCC->getReg();
150 CmpSubReg = AndCC->getSubReg();
151 } else if (And->getOperand(i: 2).getReg() != Register(ExecReg)) {
152 return false;
153 }
154
155 auto *Cmp = TRI->findReachingDef(Reg: CmpReg, SubReg: CmpSubReg, Use&: *And, MRI&: *MRI, LIS);
156 if (!Cmp || !(Cmp->getOpcode() == AMDGPU::V_CMP_NE_U32_e32 ||
157 Cmp->getOpcode() == AMDGPU::V_CMP_NE_U32_e64) ||
158 Cmp->getParent() != And->getParent())
159 return false;
160
161 MachineOperand *Op1 = TII->getNamedOperand(MI&: *Cmp, OperandName: AMDGPU::OpName::src0);
162 MachineOperand *Op2 = TII->getNamedOperand(MI&: *Cmp, OperandName: AMDGPU::OpName::src1);
163 if (Op1->isImm() && Op2->isReg())
164 std::swap(a&: Op1, b&: Op2);
165 if (!Op1->isReg() || !Op2->isImm() || Op2->getImm() != 1)
166 return false;
167
168 Register SelReg = Op1->getReg();
169 if (SelReg.isPhysical())
170 return false;
171
172 auto *Sel = TRI->findReachingDef(Reg: SelReg, SubReg: Op1->getSubReg(), Use&: *Cmp, MRI&: *MRI, LIS);
173 if (!Sel || Sel->getOpcode() != AMDGPU::V_CNDMASK_B32_e64)
174 return false;
175
176 if (TII->hasModifiersSet(MI: *Sel, OpName: AMDGPU::OpName::src0_modifiers) ||
177 TII->hasModifiersSet(MI: *Sel, OpName: AMDGPU::OpName::src1_modifiers))
178 return false;
179
180 Op1 = TII->getNamedOperand(MI&: *Sel, OperandName: AMDGPU::OpName::src0);
181 Op2 = TII->getNamedOperand(MI&: *Sel, OperandName: AMDGPU::OpName::src1);
182 MachineOperand *CC = TII->getNamedOperand(MI&: *Sel, OperandName: AMDGPU::OpName::src2);
183 if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() ||
184 Op1->getImm() != 0 || Op2->getImm() != 1)
185 return false;
186
187 Register CCReg = CC->getReg();
188
189 // If there was a def between the select and the and, we would need to move it
190 // to fold this.
191 if (isDefBetween(TRI: *TRI, LIS, Reg: CCReg, Sel: *Sel, And: *And))
192 return false;
193
194 // Cannot safely mirror live intervals with PHI nodes, so check for these
195 // before optimization.
196 SlotIndex SelIdx = LIS->getInstructionIndex(Instr: *Sel);
197 LiveInterval *SelLI = &LIS->getInterval(Reg: SelReg);
198 if (llvm::any_of(Range: SelLI->vnis(),
199 P: [](const VNInfo *VNI) {
200 return VNI->isPHIDef();
201 }))
202 return false;
203
204 // TODO: Guard against implicit def operands?
205 LLVM_DEBUG(dbgs() << "Folding sequence:\n\t" << *Sel << '\t' << *Cmp << '\t'
206 << *And);
207
208 MachineInstr *Andn2 =
209 BuildMI(BB&: MBB, I&: *And, MIMD: And->getDebugLoc(), MCID: TII->get(Opcode: LMC.AndN2Opc),
210 DestReg: And->getOperand(i: 0).getReg())
211 .addReg(RegNo: ExecReg)
212 .addReg(RegNo: CCReg, Flags: getUndefRegState(B: CC->isUndef()), SubReg: CC->getSubReg());
213 MachineOperand &AndSCC = And->getOperand(i: 3);
214 assert(AndSCC.getReg() == AMDGPU::SCC);
215 MachineOperand &Andn2SCC = Andn2->getOperand(i: 3);
216 assert(Andn2SCC.getReg() == AMDGPU::SCC);
217 Andn2SCC.setIsDead(AndSCC.isDead());
218
219 SlotIndex AndIdx = LIS->ReplaceMachineInstrInMaps(MI&: *And, NewMI&: *Andn2);
220 And->eraseFromParent();
221
222 LLVM_DEBUG(dbgs() << "=>\n\t" << *Andn2 << '\n');
223
224 // Update live intervals for CCReg before potentially removing CmpReg/SelReg,
225 // and their associated liveness information.
226 SlotIndex CmpIdx = LIS->getInstructionIndex(Instr: *Cmp);
227 if (CCReg.isVirtual()) {
228 LiveInterval &CCLI = LIS->getInterval(Reg: CCReg);
229 auto CCQ = CCLI.Query(Idx: SelIdx.getRegSlot());
230 if (CCQ.valueIn()) {
231 LIS->removeInterval(Reg: CCReg);
232 LIS->createAndComputeVirtRegInterval(Reg: CCReg);
233 }
234 } else
235 LIS->removeAllRegUnitsForPhysReg(Reg: CCReg);
236
237 // Try to remove compare. Cmp value should not used in between of cmp
238 // and s_and_b64 if VCC or just unused if any other register.
239 LiveInterval *CmpLI = CmpReg.isVirtual() ? &LIS->getInterval(Reg: CmpReg) : nullptr;
240 if ((CmpLI && CmpLI->Query(Idx: AndIdx.getRegSlot()).isKill()) ||
241 (CmpReg == Register(CondReg) &&
242 std::none_of(first: std::next(x: Cmp->getIterator()), last: Andn2->getIterator(),
243 pred: [&](const MachineInstr &MI) {
244 return MI.readsRegister(Reg: CondReg, TRI);
245 }))) {
246 LLVM_DEBUG(dbgs() << "Erasing: " << *Cmp << '\n');
247 if (CmpLI)
248 LIS->removeVRegDefAt(LI&: *CmpLI, Pos: CmpIdx.getRegSlot());
249 LIS->RemoveMachineInstrFromMaps(MI&: *Cmp);
250 Cmp->eraseFromParent();
251
252 // Try to remove v_cndmask_b32.
253 // Kill status must be checked before shrinking the live range.
254 bool IsKill = SelLI->Query(Idx: CmpIdx.getRegSlot()).isKill();
255 LIS->shrinkToUses(li: SelLI);
256 bool IsDead = SelLI->Query(Idx: SelIdx.getRegSlot()).isDeadDef();
257 if (MRI->use_nodbg_empty(RegNo: SelReg) && (IsKill || IsDead)) {
258 LLVM_DEBUG(dbgs() << "Erasing: " << *Sel << '\n');
259
260 LIS->removeVRegDefAt(LI&: *SelLI, Pos: SelIdx.getRegSlot());
261 LIS->RemoveMachineInstrFromMaps(MI&: *Sel);
262 bool ShrinkSel = Sel->getOperand(i: 0).readsReg();
263 Sel->eraseFromParent();
264 if (ShrinkSel) {
265 // The result of the V_CNDMASK was a subreg def which counted as a read
266 // from the other parts of the reg. Shrink their live ranges.
267 LIS->shrinkToUses(li: SelLI);
268 }
269 }
270 }
271
272 return true;
273}
274
275// Optimize sequence
276// %dst = S_OR_SAVEEXEC %src
277// ... instructions not modifying exec ...
278// %tmp = S_AND $exec, %dst
279// $exec = S_XOR_term $exec, %tmp
280// =>
281// %dst = S_OR_SAVEEXEC %src
282// ... instructions not modifying exec ...
283// $exec = S_XOR_term $exec, %dst
284//
285// Clean up potentially unnecessary code added for safety during
286// control flow lowering.
287//
288// Return whether any changes were made to MBB.
289bool SIOptimizeExecMaskingPreRA::optimizeElseBranch(MachineBasicBlock &MBB) {
290 if (MBB.empty())
291 return false;
292
293 // Check this is an else block.
294 auto First = MBB.begin();
295 MachineInstr &SaveExecMI = *First;
296 if (SaveExecMI.getOpcode() != LMC.OrSaveExecOpc)
297 return false;
298
299 auto I = llvm::find_if(Range: MBB.terminators(), P: [this](const MachineInstr &MI) {
300 return MI.getOpcode() == LMC.XorTermOpc;
301 });
302 if (I == MBB.terminators().end())
303 return false;
304
305 MachineInstr &XorTermMI = *I;
306 if (XorTermMI.getOperand(i: 1).getReg() != Register(ExecReg))
307 return false;
308
309 Register SavedExecReg = SaveExecMI.getOperand(i: 0).getReg();
310 Register DstReg = XorTermMI.getOperand(i: 2).getReg();
311
312 // Find potentially unnecessary S_AND
313 MachineInstr *AndExecMI = nullptr;
314 I--;
315 while (I != First && !AndExecMI) {
316 if (I->getOpcode() == LMC.AndOpc && I->getOperand(i: 0).getReg() == DstReg &&
317 I->getOperand(i: 1).getReg() == Register(ExecReg))
318 AndExecMI = &*I;
319 I--;
320 }
321 if (!AndExecMI)
322 return false;
323
324 // Check for exec modifying instructions.
325 // Note: exec defs do not create live ranges beyond the
326 // instruction so isDefBetween cannot be used.
327 // Instead just check that the def segments are adjacent.
328 SlotIndex StartIdx = LIS->getInstructionIndex(Instr: SaveExecMI);
329 SlotIndex EndIdx = LIS->getInstructionIndex(Instr: *AndExecMI);
330 for (MCRegUnit Unit : TRI->regunits(Reg: ExecReg)) {
331 LiveRange &RegUnit = LIS->getRegUnit(Unit);
332 if (RegUnit.find(Pos: StartIdx) != std::prev(x: RegUnit.find(Pos: EndIdx)))
333 return false;
334 }
335
336 // Remove unnecessary S_AND
337 LIS->removeInterval(Reg: SavedExecReg);
338 LIS->removeInterval(Reg: DstReg);
339
340 SaveExecMI.getOperand(i: 0).setReg(DstReg);
341
342 LIS->RemoveMachineInstrFromMaps(MI&: *AndExecMI);
343 AndExecMI->eraseFromParent();
344
345 LIS->createAndComputeVirtRegInterval(Reg: DstReg);
346
347 return true;
348}
349
350PreservedAnalyses
351SIOptimizeExecMaskingPreRAPass::run(MachineFunction &MF,
352 MachineFunctionAnalysisManager &MFAM) {
353 auto &LIS = MFAM.getResult<LiveIntervalsAnalysis>(IR&: MF);
354 SIOptimizeExecMaskingPreRA(MF, &LIS).run(MF);
355 return PreservedAnalyses::all();
356}
357
358bool SIOptimizeExecMaskingPreRALegacy::runOnMachineFunction(
359 MachineFunction &MF) {
360 if (skipFunction(F: MF.getFunction()))
361 return false;
362
363 auto *LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
364 return SIOptimizeExecMaskingPreRA(MF, LIS).run(MF);
365}
366
367bool SIOptimizeExecMaskingPreRA::run(MachineFunction &MF) {
368 CondReg = MCRegister::from(Val: LMC.VccReg);
369 ExecReg = MCRegister::from(Val: LMC.ExecReg);
370
371 DenseSet<Register> RecalcRegs({AMDGPU::EXEC_LO, AMDGPU::EXEC_HI});
372 bool Changed = false;
373
374 for (MachineBasicBlock &MBB : MF) {
375
376 if (optimizeElseBranch(MBB)) {
377 RecalcRegs.insert(V: AMDGPU::SCC);
378 Changed = true;
379 }
380
381 if (optimizeVcndVcmpPair(MBB)) {
382 RecalcRegs.insert(V: AMDGPU::VCC_LO);
383 RecalcRegs.insert(V: AMDGPU::VCC_HI);
384 RecalcRegs.insert(V: AMDGPU::SCC);
385 Changed = true;
386 }
387
388 // Try to remove unneeded instructions before s_endpgm.
389 if (MBB.succ_empty()) {
390 if (MBB.empty())
391 continue;
392
393 // Skip this if the endpgm has any implicit uses, otherwise we would need
394 // to be careful to update / remove them.
395 // S_ENDPGM always has a single imm operand that is not used other than to
396 // end up in the encoding
397 MachineInstr &Term = MBB.back();
398 if (Term.getOpcode() != AMDGPU::S_ENDPGM || Term.getNumOperands() != 1)
399 continue;
400
401 SmallVector<MachineBasicBlock*, 4> Blocks({&MBB});
402
403 while (!Blocks.empty()) {
404 auto *CurBB = Blocks.pop_back_val();
405 auto I = CurBB->rbegin(), E = CurBB->rend();
406 if (I != E) {
407 if (I->isUnconditionalBranch() || I->getOpcode() == AMDGPU::S_ENDPGM)
408 ++I;
409 else if (I->isBranch())
410 continue;
411 }
412
413 while (I != E) {
414 if (I->isDebugInstr()) {
415 I = std::next(x: I);
416 continue;
417 }
418
419 if (I->mayStore() || I->isBarrier() || I->isCall() ||
420 I->hasUnmodeledSideEffects() || I->hasOrderedMemoryRef())
421 break;
422
423 LLVM_DEBUG(dbgs()
424 << "Removing no effect instruction: " << *I << '\n');
425
426 for (auto &Op : I->operands()) {
427 if (Op.isReg())
428 RecalcRegs.insert(V: Op.getReg());
429 }
430
431 auto Next = std::next(x: I);
432 LIS->RemoveMachineInstrFromMaps(MI&: *I);
433 I->eraseFromParent();
434 I = Next;
435
436 Changed = true;
437 }
438
439 if (I != E)
440 continue;
441
442 // Try to ascend predecessors.
443 for (auto *Pred : CurBB->predecessors()) {
444 if (Pred->succ_size() == 1)
445 Blocks.push_back(Elt: Pred);
446 }
447 }
448 continue;
449 }
450
451 // If the only user of a logical operation is move to exec, fold it now
452 // to prevent forming of saveexec. I.e.:
453 //
454 // %0:sreg_64 = COPY $exec
455 // %1:sreg_64 = S_AND_B64 %0:sreg_64, %2:sreg_64
456 // =>
457 // %1 = S_AND_B64 $exec, %2:sreg_64
458 unsigned ScanThreshold = 10;
459 for (auto I = MBB.rbegin(), E = MBB.rend(); I != E
460 && ScanThreshold--; ++I) {
461 // Continue scanning if this is not a full exec copy
462 if (!(I->isFullCopy() && I->getOperand(i: 1).getReg() == Register(ExecReg)))
463 continue;
464
465 Register SavedExec = I->getOperand(i: 0).getReg();
466 if (SavedExec.isVirtual() && MRI->hasOneNonDBGUse(RegNo: SavedExec)) {
467 MachineInstr *SingleExecUser = &*MRI->use_instr_nodbg_begin(RegNo: SavedExec);
468 int Idx = SingleExecUser->findRegisterUseOperandIdx(Reg: SavedExec,
469 /*TRI=*/nullptr);
470 assert(Idx != -1);
471 if (SingleExecUser->getParent() == I->getParent() &&
472 !SingleExecUser->getOperand(i: Idx).isImplicit() &&
473 static_cast<unsigned>(Idx) <
474 SingleExecUser->getDesc().getNumOperands() &&
475 TII->isOperandLegal(MI: *SingleExecUser, OpIdx: Idx, MO: &I->getOperand(i: 1))) {
476 LLVM_DEBUG(dbgs() << "Redundant EXEC COPY: " << *I << '\n');
477 LIS->RemoveMachineInstrFromMaps(MI&: *I);
478 I->eraseFromParent();
479 MRI->replaceRegWith(FromReg: SavedExec, ToReg: ExecReg);
480 LIS->removeInterval(Reg: SavedExec);
481 Changed = true;
482 }
483 }
484 break;
485 }
486 }
487
488 if (Changed) {
489 for (auto Reg : RecalcRegs) {
490 if (Reg.isVirtual()) {
491 LIS->removeInterval(Reg);
492 if (!MRI->reg_empty(RegNo: Reg))
493 LIS->createAndComputeVirtRegInterval(Reg);
494 } else {
495 LIS->removeAllRegUnitsForPhysReg(Reg);
496 }
497 }
498 }
499
500 return Changed;
501}
502