1//===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#include "ARMTargetMachine.h"
13#include "ARM.h"
14#include "ARMLatencyMutations.h"
15#include "ARMMachineFunctionInfo.h"
16#include "ARMMacroFusion.h"
17#include "ARMSubtarget.h"
18#include "ARMTargetObjectFile.h"
19#include "ARMTargetTransformInfo.h"
20#include "MCTargetDesc/ARMMCTargetDesc.h"
21#include "TargetInfo/ARMTargetInfo.h"
22#include "llvm/ADT/StringRef.h"
23#include "llvm/Analysis/TargetTransformInfo.h"
24#include "llvm/CodeGen/ExecutionDomainFix.h"
25#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
26#include "llvm/CodeGen/GlobalISel/CallLowering.h"
27#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
28#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
29#include "llvm/CodeGen/GlobalISel/Legalizer.h"
30#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
31#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
32#include "llvm/CodeGen/MIRParser/MIParser.h"
33#include "llvm/CodeGen/MachineFunction.h"
34#include "llvm/CodeGen/MachineScheduler.h"
35#include "llvm/CodeGen/Passes.h"
36#include "llvm/CodeGen/TargetPassConfig.h"
37#include "llvm/IR/Attributes.h"
38#include "llvm/IR/CallingConv.h"
39#include "llvm/IR/DataLayout.h"
40#include "llvm/IR/DiagnosticInfo.h"
41#include "llvm/IR/Function.h"
42#include "llvm/IR/InstIterator.h"
43#include "llvm/IR/InstrTypes.h"
44#include "llvm/IR/Module.h"
45#include "llvm/MC/TargetRegistry.h"
46#include "llvm/Pass.h"
47#include "llvm/Passes/PassBuilder.h"
48#include "llvm/Support/CodeGen.h"
49#include "llvm/Support/CommandLine.h"
50#include "llvm/Support/Compiler.h"
51#include "llvm/Support/ErrorHandling.h"
52#include "llvm/Target/TargetLoweringObjectFile.h"
53#include "llvm/Target/TargetOptions.h"
54#include "llvm/TargetParser/ARMTargetParser.h"
55#include "llvm/TargetParser/Triple.h"
56#include "llvm/Transforms/CFGuard.h"
57#include "llvm/Transforms/IPO.h"
58#include "llvm/Transforms/Scalar.h"
59#include <cassert>
60#include <memory>
61#include <optional>
62#include <string>
63
64using namespace llvm;
65
66static cl::opt<bool>
67DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
68 cl::desc("Inhibit optimization of S->D register accesses on A15"),
69 cl::init(Val: false));
70
71static cl::opt<bool>
72EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
73 cl::desc("Run SimplifyCFG after expanding atomic operations"
74 " to make use of cmpxchg flow-based information"),
75 cl::init(Val: true));
76
77static cl::opt<bool>
78EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
79 cl::desc("Enable ARM load/store optimization pass"),
80 cl::init(Val: true));
81
82// FIXME: Unify control over GlobalMerge.
83static cl::opt<cl::boolOrDefault>
84EnableGlobalMerge("arm-global-merge", cl::Hidden,
85 cl::desc("Enable the global merge pass"));
86
87namespace llvm {
88 void initializeARMExecutionDomainFixPass(PassRegistry&);
89}
90
91extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget() {
92 // Register the target.
93 RegisterTargetMachine<ARMLETargetMachine> X(getTheARMLETarget());
94 RegisterTargetMachine<ARMLETargetMachine> A(getTheThumbLETarget());
95 RegisterTargetMachine<ARMBETargetMachine> Y(getTheARMBETarget());
96 RegisterTargetMachine<ARMBETargetMachine> B(getTheThumbBETarget());
97
98 PassRegistry &Registry = *PassRegistry::getPassRegistry();
99 initializeGlobalISel(Registry);
100 initializeARMAsmPrinterPass(Registry);
101 initializeARMLoadStoreOptLegacyPass(Registry);
102 initializeARMPreAllocLoadStoreOptLegacyPass(Registry);
103 initializeARMParallelDSPPass(Registry);
104 initializeARMBranchTargetsPass(Registry);
105 initializeARMConstantIslandsPass(Registry);
106 initializeARMExecutionDomainFixPass(Registry);
107 initializeARMExpandPseudoPass(Registry);
108 initializeThumb2SizeReducePass(Registry);
109 initializeMVEVPTBlockPass(Registry);
110 initializeMVETPAndVPTOptimisationsPass(Registry);
111 initializeMVETailPredicationPass(Registry);
112 initializeARMLowOverheadLoopsPass(Registry);
113 initializeARMBlockPlacementPass(Registry);
114 initializeMVEGatherScatterLoweringPass(Registry);
115 initializeARMSLSHardeningPass(Registry);
116 initializeMVELaneInterleavingPass(Registry);
117 initializeARMFixCortexA57AES1742098Pass(Registry);
118 initializeARMDAGToDAGISelLegacyPass(Registry);
119 initializeMachineKCFILegacyPass(Registry);
120}
121
122static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
123 if (TT.isOSBinFormatMachO())
124 return std::make_unique<TargetLoweringObjectFileMachO>();
125 if (TT.isOSWindows())
126 return std::make_unique<TargetLoweringObjectFileCOFF>();
127 return std::make_unique<ARMElfTargetObjectFile>();
128}
129
130static Reloc::Model getEffectiveRelocModel(const Triple &TT,
131 std::optional<Reloc::Model> RM) {
132 if (!RM)
133 // Default relocation model on Darwin is PIC.
134 return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
135
136 if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
137 assert(TT.isOSBinFormatELF() &&
138 "ROPI/RWPI currently only supported for ELF");
139
140 // DynamicNoPIC is only used on darwin.
141 if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
142 return Reloc::Static;
143
144 return *RM;
145}
146
147/// Create an ARM architecture model.
148///
149ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
150 StringRef CPU, StringRef FS,
151 const TargetOptions &Options,
152 std::optional<Reloc::Model> RM,
153 std::optional<CodeModel::Model> CM,
154 CodeGenOptLevel OL)
155 : CodeGenTargetMachineImpl(T, TT, CPU, FS, Options,
156 getEffectiveRelocModel(TT, RM),
157 getEffectiveCodeModel(CM, Default: CodeModel::Small), OL),
158 TLOF(createTLOF(TT: getTargetTriple())), isLittle(TT.isLittleEndian()) {
159
160 if (TT.isOSBinFormatMachO()) {
161 this->Options.TrapUnreachable = true;
162 this->Options.NoTrapAfterNoreturn = true;
163 }
164
165 // ARM supports the debug entry values.
166 setSupportsDebugEntryValues(true);
167
168 initAsmInfo();
169
170 // ARM supports the MachineOutliner.
171 setMachineOutliner(true);
172 setSupportsDefaultOutlining(true);
173}
174
175ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
176
177MachineFunctionInfo *ARMBaseTargetMachine::createMachineFunctionInfo(
178 BumpPtrAllocator &Allocator, const Function &F,
179 const TargetSubtargetInfo *STI) const {
180 const auto *ARMSTI = static_cast<const ARMSubtarget *>(STI);
181 if (!ARMSTI->hasFPRegs() || ARMSTI->isThumb1Only() ||
182 ARMSTI->useSoftFloat()) {
183 const StringRef FPRegsUnavailableMsg =
184 ", but floating-point registers are unavailable";
185 const ARMTargetLowering *TLI = ARMSTI->getTargetLowering();
186
187 if (TLI->getEffectiveCallingConv(CC: F.getCallingConv(), isVarArg: F.isVarArg()) ==
188 CallingConv::ARM_AAPCS_VFP) {
189 F.getContext().diagnose(DI: DiagnosticInfoUnsupported(
190 F, Twine("calling convention is hard-float") + FPRegsUnavailableMsg,
191 DiagnosticLocation(F.getSubprogram())));
192 } else {
193 for (const Instruction &I : instructions(F)) {
194 const auto *CB = dyn_cast<CallBase>(Val: &I);
195 if (!CB || CB->isInlineAsm() ||
196 (CB->getCalledFunction() && CB->getCalledFunction()->isIntrinsic()))
197 continue;
198 if (TLI->getEffectiveCallingConv(CC: CB->getCallingConv(),
199 isVarArg: CB->getFunctionType()->isVarArg()) ==
200 CallingConv::ARM_AAPCS_VFP) {
201 const Function *Callee = CB->getCalledFunction();
202 F.getContext().diagnose(DI: DiagnosticInfoUnsupported(
203 F,
204 (Callee ? Twine("'") + F.getName() + "' calls '" +
205 Callee->getName() + "', which"
206 : Twine("'") + F.getName() +
207 "' makes an indirect call that") +
208 " expects a hard-float calling convention" +
209 FPRegsUnavailableMsg,
210 CB->getDebugLoc()));
211 }
212 }
213 }
214 }
215 return ARMFunctionInfo::create<ARMFunctionInfo>(Allocator, F, STI: ARMSTI);
216}
217
218FloatABI::ABIType ARMBaseTargetMachine::getFloatABI(const Module &M) const {
219 // An explicit "float-abi" module flag always wins, even for AAPCS16.
220 if (auto *Val = dyn_cast_or_null<MDString>(Val: M.getModuleFlag(Key: "float-abi")))
221 return *FloatABI::parseABIType(S: Val->getString());
222 return M.getTargetTriple().getDefaultFloatABI(ABIName: getTargetABIName(M));
223}
224
225ARM::ARMABI ARMBaseTargetMachine::getEffectiveABI(const Module &M) const {
226 // Consistency of "target-abi" and -target-abi is validated elsewhere.
227 if (const auto *MD = cast_or_null<MDString>(Val: M.getModuleFlag(Key: "target-abi")))
228 return ARM::computeTargetABI(TT: TargetTriple, ABIName: MD->getString());
229 return ARM::computeTargetABI(TT: TargetTriple, ABIName: Options.MCOptions.getABIName());
230}
231
232const ARMSubtarget *
233ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
234 Attribute CPUAttr = F.getFnAttribute(Kind: "target-cpu");
235 Attribute FSAttr = F.getFnAttribute(Kind: "target-features");
236
237 std::string CPU =
238 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
239 std::string FS =
240 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
241
242 // FIXME: This is related to the code below to reset the target options,
243 // we need to know whether or not the soft float flag is set on the
244 // function before we can generate a subtarget. We also need to use
245 // it as a key for the subtarget since that can be the only difference
246 // between two functions.
247 bool SoftFloat = F.getFnAttribute(Kind: "use-soft-float").getValueAsBool();
248 // If the soft float attribute is set on the function turn on the soft float
249 // subtarget feature.
250 if (SoftFloat)
251 FS += FS.empty() ? "+soft-float" : ",+soft-float";
252
253 // Use the optminsize to identify the subtarget, but don't use it in the
254 // feature string.
255 std::string Key = CPU + FS;
256 if (F.hasMinSize())
257 Key += "+minsize";
258
259 DenormalMode DM = F.getDenormalFPEnv().DefaultMode;
260 if (DM != DenormalMode::getIEEE())
261 Key += "denormal-fp-math=" + DM.str();
262
263 FloatABI::ABIType FloatABI = getFloatABI(M: *F.getParent());
264 // It is legal to have FloatABI::Hard for targets with SIMD registers
265 // but no floating-point hardware (mve+nofp).
266 Key += FloatABI == FloatABI::Hard ? "+hard-float-abi" : "+soft-float-abi";
267
268 ARM::ARMABI ABI = getEffectiveABI(M: *F.getParent());
269 Key += "+abi=" + std::to_string(val: (int)ABI);
270
271 auto &I = SubtargetMap[Key];
272 if (!I) {
273 I = std::make_unique<ARMSubtarget>(args: TargetTriple, args&: CPU, args&: FS, args: *this, args: isLittle,
274 args&: FloatABI, args&: ABI, args: F.hasMinSize(), args&: DM);
275
276 if (!I->isThumb() && !I->hasARMOps())
277 F.getContext().emitError(ErrorStr: "Function '" + F.getName() + "' uses ARM "
278 "instructions, but the target does not support ARM mode execution.");
279 }
280
281 return I.get();
282}
283
284TargetTransformInfo
285ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) const {
286 return TargetTransformInfo(std::make_unique<ARMTTIImpl>(args: this, args: F));
287}
288
289ScheduleDAGInstrs *
290ARMBaseTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
291 ScheduleDAGMILive *DAG = createSchedLive(C);
292 // add DAG Mutations here.
293 const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
294 if (ST.hasFusion())
295 DAG->addMutation(Mutation: createARMMacroFusionDAGMutation());
296 return DAG;
297}
298
299ScheduleDAGInstrs *
300ARMBaseTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
301 ScheduleDAGMI *DAG = createSchedPostRA(C);
302 // add DAG Mutations here.
303 const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
304 if (ST.hasFusion())
305 DAG->addMutation(Mutation: createARMMacroFusionDAGMutation());
306 if (auto Mutation = createARMLatencyMutations(ST, AA: C->AA))
307 DAG->addMutation(Mutation: std::move(Mutation));
308 return DAG;
309}
310
311ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
312 StringRef CPU, StringRef FS,
313 const TargetOptions &Options,
314 std::optional<Reloc::Model> RM,
315 std::optional<CodeModel::Model> CM,
316 CodeGenOptLevel OL, bool JIT)
317 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
318
319ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
320 StringRef CPU, StringRef FS,
321 const TargetOptions &Options,
322 std::optional<Reloc::Model> RM,
323 std::optional<CodeModel::Model> CM,
324 CodeGenOptLevel OL, bool JIT)
325 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
326
327namespace {
328
329/// ARM Code Generator Pass Configuration Options.
330class ARMPassConfig : public TargetPassConfig {
331public:
332 ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
333 : TargetPassConfig(TM, PM) {}
334
335 ARMBaseTargetMachine &getARMTargetMachine() const {
336 return getTM<ARMBaseTargetMachine>();
337 }
338
339 void addIRPasses() override;
340 void addCodeGenPrepare() override;
341 bool addPreISel() override;
342 bool addInstSelector() override;
343 bool addIRTranslator() override;
344 bool addLegalizeMachineIR() override;
345 bool addRegBankSelect() override;
346 bool addGlobalInstructionSelect() override;
347 void addPreRegAlloc() override;
348 void addPreSched2() override;
349 void addPreEmitPass() override;
350 void addPreEmitPass2() override;
351
352 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
353};
354
355class ARMExecutionDomainFix : public ExecutionDomainFix {
356public:
357 static char ID;
358 ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
359 StringRef getPassName() const override {
360 return "ARM Execution Domain Fix";
361 }
362};
363char ARMExecutionDomainFix::ID;
364
365} // end anonymous namespace
366
367INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
368 "ARM Execution Domain Fix", false, false)
369INITIALIZE_PASS_DEPENDENCY(ReachingDefInfoWrapperPass)
370INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
371 "ARM Execution Domain Fix", false, false)
372
373void ARMBaseTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
374#define GET_PASS_REGISTRY "ARMPassRegistry.def"
375#include "llvm/Passes/TargetPassRegistry.inc"
376}
377
378TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
379 return new ARMPassConfig(*this, PM);
380}
381
382std::unique_ptr<CSEConfigBase> ARMPassConfig::getCSEConfig() const {
383 return getStandardCSEConfigForOpt(Level: TM->getOptLevel());
384}
385
386void ARMPassConfig::addIRPasses() {
387 addPass(P: createAtomicExpandLegacyPass());
388
389 // Cmpxchg instructions are often used with a subsequent comparison to
390 // determine whether it succeeded. We can exploit existing control-flow in
391 // ldrex/strex loops to simplify this, but it needs tidying up.
392 if (TM->getOptLevel() != CodeGenOptLevel::None && EnableAtomicTidy)
393 addPass(P: createCFGSimplificationPass(
394 Options: SimplifyCFGOptions().hoistCommonInsts(B: true).sinkCommonInsts(B: true),
395 Ftor: [this](const Function &F) {
396 const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
397 return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
398 }));
399
400 addPass(P: createMVEGatherScatterLoweringPass());
401 addPass(P: createMVELaneInterleavingPass());
402
403 TargetPassConfig::addIRPasses();
404
405 // Run the parallel DSP pass.
406 if (getOptLevel() == CodeGenOptLevel::Aggressive)
407 addPass(P: createARMParallelDSPPass());
408
409 // Match complex arithmetic patterns
410 if (TM->getOptLevel() >= CodeGenOptLevel::Default)
411 addPass(P: createComplexDeinterleavingPass(TM));
412
413 // Match interleaved memory accesses to ldN/stN intrinsics.
414 if (TM->getOptLevel() != CodeGenOptLevel::None)
415 addPass(P: createInterleavedAccessPass());
416
417 // Add Control Flow Guard checks.
418 if (TM->getTargetTriple().isOSWindows())
419 addPass(P: createCFGuardPass());
420
421 if (TM->Options.JMCInstrument)
422 addPass(P: createJMCInstrumenterPass());
423}
424
425void ARMPassConfig::addCodeGenPrepare() {
426 if (getOptLevel() != CodeGenOptLevel::None)
427 addPass(P: createTypePromotionLegacyPass());
428 TargetPassConfig::addCodeGenPrepare();
429}
430
431bool ARMPassConfig::addPreISel() {
432 if ((TM->getOptLevel() != CodeGenOptLevel::None &&
433 EnableGlobalMerge == cl::boolOrDefault::BOU_UNSET) ||
434 EnableGlobalMerge == cl::boolOrDefault::BOU_TRUE) {
435 // FIXME: This is using the thumb1 only constant value for
436 // maximal global offset for merging globals. We may want
437 // to look into using the old value for non-thumb1 code of
438 // 4095 based on the TargetMachine, but this starts to become
439 // tricky when doing code gen per function.
440 bool OnlyOptimizeForSize =
441 (TM->getOptLevel() < CodeGenOptLevel::Aggressive) &&
442 (EnableGlobalMerge == cl::boolOrDefault::BOU_UNSET);
443 // Merging of extern globals is enabled by default on non-Mach-O as we
444 // expect it to be generally either beneficial or harmless. On Mach-O it
445 // is disabled as we emit the .subsections_via_symbols directive which
446 // means that merging extern globals is not safe.
447 bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
448 addPass(P: createGlobalMergePass(TM, MaximalOffset: 127, OnlyOptimizeForSize,
449 MergeExternalByDefault));
450 }
451
452 if (TM->getOptLevel() != CodeGenOptLevel::None) {
453 addPass(P: createHardwareLoopsLegacyPass());
454 addPass(P: createMVETailPredicationPass());
455 // FIXME: IR passes can delete address-taken basic blocks, deleting
456 // corresponding blockaddresses. ARMConstantPoolConstant holds references to
457 // address-taken basic blocks which can be invalidated if the function
458 // containing the blockaddress has already been codegen'd and the basic
459 // block is removed. Work around this by forcing all IR passes to run before
460 // any ISel takes place. We should have a more principled way of handling
461 // this. See D99707 for more details.
462 addPass(P: createBarrierNoopPass());
463 }
464
465 return false;
466}
467
468bool ARMPassConfig::addInstSelector() {
469 addPass(P: createARMISelDag(TM&: getARMTargetMachine(), OptLevel: getOptLevel()));
470 return false;
471}
472
473bool ARMPassConfig::addIRTranslator() {
474 addPass(P: new IRTranslatorLegacy(getOptLevel()));
475 return false;
476}
477
478bool ARMPassConfig::addLegalizeMachineIR() {
479 addPass(P: new LegalizerLegacy());
480 return false;
481}
482
483bool ARMPassConfig::addRegBankSelect() {
484 addPass(P: new RegBankSelectLegacy());
485 return false;
486}
487
488bool ARMPassConfig::addGlobalInstructionSelect() {
489 addPass(P: new InstructionSelectLegacy(getOptLevel()));
490 return false;
491}
492
493void ARMPassConfig::addPreRegAlloc() {
494 if (getOptLevel() != CodeGenOptLevel::None) {
495 if (getOptLevel() == CodeGenOptLevel::Aggressive)
496 addPass(PassID: &MachinePipelinerID);
497
498 addPass(P: createMVETPAndVPTOptimisationsPass());
499
500 addPass(P: createMLxExpansionPass());
501
502 if (EnableARMLoadStoreOpt)
503 addPass(P: createARMLoadStoreOptLegacyPass(/* pre-register alloc */ PreAlloc: true));
504
505 if (!DisableA15SDOptimization)
506 addPass(P: createA15SDOptimizerPass());
507 }
508}
509
510void ARMPassConfig::addPreSched2() {
511 if (getOptLevel() != CodeGenOptLevel::None) {
512 if (EnableARMLoadStoreOpt)
513 addPass(P: createARMLoadStoreOptLegacyPass());
514
515 addPass(P: new ARMExecutionDomainFix());
516 addPass(P: createBreakFalseDepsLegacyPass());
517 }
518
519 // Expand some pseudo instructions into multiple instructions to allow
520 // proper scheduling.
521 addPass(P: createARMExpandPseudoPass());
522
523 // Emit KCFI checks for indirect calls.
524 addPass(P: createKCFIPass());
525
526 if (getOptLevel() != CodeGenOptLevel::None) {
527 // When optimising for size, always run the Thumb2SizeReduction pass before
528 // IfConversion. Otherwise, check whether IT blocks are restricted
529 // (e.g. in v8, IfConversion depends on Thumb instruction widths)
530 addPass(P: createThumb2SizeReductionPass(Ftor: [this](const Function &F) {
531 return this->TM->getSubtarget<ARMSubtarget>(F).hasMinSize() ||
532 this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
533 }));
534
535 addPass(P: createIfConverter(Ftor: [](const MachineFunction &MF) {
536 return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
537 }));
538 }
539 addPass(P: createThumb2ITBlockPass());
540
541 // Add both scheduling passes to give the subtarget an opportunity to pick
542 // between them.
543 if (getOptLevel() != CodeGenOptLevel::None) {
544 addPass(PassID: &PostMachineSchedulerID);
545 addPass(PassID: &PostRASchedulerID);
546 }
547
548 addPass(P: createMVEVPTBlockPass());
549 addPass(P: createARMIndirectThunks());
550 addPass(P: createARMSLSHardeningPass());
551}
552
553void ARMPassConfig::addPreEmitPass() {
554 addPass(P: createThumb2SizeReductionPass());
555
556 // Unpack bundles for:
557 // - Thumb2: Constant island pass requires unbundled instructions
558 // - KCFI: KCFI_CHECK pseudo instructions need to be unbundled for AsmPrinter
559 addPass(P: createUnpackMachineBundlesLegacy(Ftor: [](const MachineFunction &MF) {
560 return MF.getSubtarget<ARMSubtarget>().isThumb2() ||
561 MF.getFunction().getParent()->getModuleFlag(Key: "kcfi");
562 }));
563
564 // Don't optimize barriers or block placement at -O0.
565 if (getOptLevel() != CodeGenOptLevel::None) {
566 addPass(P: createARMBlockPlacementPass());
567 addPass(P: createARMOptimizeBarriersPass());
568 }
569}
570
571void ARMPassConfig::addPreEmitPass2() {
572
573 // Inserts fixup instructions before unsafe AES operations. Instructions may
574 // be inserted at the start of blocks and at within blocks so this pass has to
575 // come before those below.
576 addPass(P: createARMFixCortexA57AES1742098Pass());
577 // Inserts BTIs at the start of functions and indirectly-called basic blocks,
578 // so passes cannot add to the start of basic blocks once this has run.
579 addPass(P: createARMBranchTargetsPass());
580 // Inserts Constant Islands. Block sizes cannot be increased after this point,
581 // as this may push the branch ranges and load offsets of accessing constant
582 // pools out of range..
583 addPass(P: createARMConstantIslandPass());
584 // Finalises Low-Overhead Loops. This replaces pseudo instructions with real
585 // instructions, but the pseudos all have conservative sizes so that block
586 // sizes will only be decreased by this pass.
587 addPass(P: createARMLowOverheadLoopsPass());
588
589 if (TM->getTargetTriple().isOSWindows()) {
590 // Identify valid longjmp targets for Windows Control Flow Guard.
591 addPass(P: createCFGuardLongjmpPass());
592 // Identify valid eh continuation targets for Windows EHCont Guard.
593 addPass(P: createEHContGuardTargetsLegacy());
594 }
595}
596
597yaml::MachineFunctionInfo *
598ARMBaseTargetMachine::createDefaultFuncInfoYAML() const {
599 return new yaml::ARMFunctionInfo();
600}
601
602yaml::MachineFunctionInfo *
603ARMBaseTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
604 const auto *MFI = MF.getInfo<ARMFunctionInfo>();
605 return new yaml::ARMFunctionInfo(*MFI);
606}
607
608bool ARMBaseTargetMachine::parseMachineFunctionInfo(
609 const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,
610 SMDiagnostic &Error, SMRange &SourceRange) const {
611 const auto &YamlMFI = static_cast<const yaml::ARMFunctionInfo &>(MFI);
612 MachineFunction &MF = PFS.MF;
613 MF.getInfo<ARMFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
614 return false;
615}
616
617void ARMBaseTargetMachine::reset() { SubtargetMap.clear(); }
618