1//===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#include "ARMTargetMachine.h"
13#include "ARM.h"
14#include "ARMLatencyMutations.h"
15#include "ARMMachineFunctionInfo.h"
16#include "ARMMacroFusion.h"
17#include "ARMSubtarget.h"
18#include "ARMTargetObjectFile.h"
19#include "ARMTargetTransformInfo.h"
20#include "MCTargetDesc/ARMMCTargetDesc.h"
21#include "TargetInfo/ARMTargetInfo.h"
22#include "llvm/ADT/StringRef.h"
23#include "llvm/Analysis/TargetTransformInfo.h"
24#include "llvm/CodeGen/ExecutionDomainFix.h"
25#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
26#include "llvm/CodeGen/GlobalISel/CallLowering.h"
27#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
28#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
29#include "llvm/CodeGen/GlobalISel/Legalizer.h"
30#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
31#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
32#include "llvm/CodeGen/MIRParser/MIParser.h"
33#include "llvm/CodeGen/MachineFunction.h"
34#include "llvm/CodeGen/MachineScheduler.h"
35#include "llvm/CodeGen/Passes.h"
36#include "llvm/CodeGen/TargetPassConfig.h"
37#include "llvm/IR/Attributes.h"
38#include "llvm/IR/DataLayout.h"
39#include "llvm/IR/Function.h"
40#include "llvm/MC/TargetRegistry.h"
41#include "llvm/Pass.h"
42#include "llvm/Passes/PassBuilder.h"
43#include "llvm/Support/CodeGen.h"
44#include "llvm/Support/CommandLine.h"
45#include "llvm/Support/Compiler.h"
46#include "llvm/Support/ErrorHandling.h"
47#include "llvm/Target/TargetLoweringObjectFile.h"
48#include "llvm/Target/TargetOptions.h"
49#include "llvm/TargetParser/ARMTargetParser.h"
50#include "llvm/TargetParser/TargetParser.h"
51#include "llvm/TargetParser/Triple.h"
52#include "llvm/Transforms/CFGuard.h"
53#include "llvm/Transforms/IPO.h"
54#include "llvm/Transforms/Scalar.h"
55#include <cassert>
56#include <memory>
57#include <optional>
58#include <string>
59
60using namespace llvm;
61
62static cl::opt<bool>
63DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
64 cl::desc("Inhibit optimization of S->D register accesses on A15"),
65 cl::init(Val: false));
66
67static cl::opt<bool>
68EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
69 cl::desc("Run SimplifyCFG after expanding atomic operations"
70 " to make use of cmpxchg flow-based information"),
71 cl::init(Val: true));
72
73static cl::opt<bool>
74EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
75 cl::desc("Enable ARM load/store optimization pass"),
76 cl::init(Val: true));
77
78// FIXME: Unify control over GlobalMerge.
79static cl::opt<cl::boolOrDefault>
80EnableGlobalMerge("arm-global-merge", cl::Hidden,
81 cl::desc("Enable the global merge pass"));
82
83namespace llvm {
84 void initializeARMExecutionDomainFixPass(PassRegistry&);
85}
86
87extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget() {
88 // Register the target.
89 RegisterTargetMachine<ARMLETargetMachine> X(getTheARMLETarget());
90 RegisterTargetMachine<ARMLETargetMachine> A(getTheThumbLETarget());
91 RegisterTargetMachine<ARMBETargetMachine> Y(getTheARMBETarget());
92 RegisterTargetMachine<ARMBETargetMachine> B(getTheThumbBETarget());
93
94 PassRegistry &Registry = *PassRegistry::getPassRegistry();
95 initializeGlobalISel(Registry);
96 initializeARMAsmPrinterPass(Registry);
97 initializeARMLoadStoreOptLegacyPass(Registry);
98 initializeARMPreAllocLoadStoreOptLegacyPass(Registry);
99 initializeARMParallelDSPPass(Registry);
100 initializeARMBranchTargetsPass(Registry);
101 initializeARMConstantIslandsPass(Registry);
102 initializeARMExecutionDomainFixPass(Registry);
103 initializeARMExpandPseudoPass(Registry);
104 initializeThumb2SizeReducePass(Registry);
105 initializeMVEVPTBlockPass(Registry);
106 initializeMVETPAndVPTOptimisationsPass(Registry);
107 initializeMVETailPredicationPass(Registry);
108 initializeARMLowOverheadLoopsPass(Registry);
109 initializeARMBlockPlacementPass(Registry);
110 initializeMVEGatherScatterLoweringPass(Registry);
111 initializeARMSLSHardeningPass(Registry);
112 initializeMVELaneInterleavingPass(Registry);
113 initializeARMFixCortexA57AES1742098Pass(Registry);
114 initializeARMDAGToDAGISelLegacyPass(Registry);
115 initializeKCFIPass(Registry);
116}
117
118static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
119 if (TT.isOSBinFormatMachO())
120 return std::make_unique<TargetLoweringObjectFileMachO>();
121 if (TT.isOSWindows())
122 return std::make_unique<TargetLoweringObjectFileCOFF>();
123 return std::make_unique<ARMElfTargetObjectFile>();
124}
125
126static Reloc::Model getEffectiveRelocModel(const Triple &TT,
127 std::optional<Reloc::Model> RM) {
128 if (!RM)
129 // Default relocation model on Darwin is PIC.
130 return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
131
132 if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
133 assert(TT.isOSBinFormatELF() &&
134 "ROPI/RWPI currently only supported for ELF");
135
136 // DynamicNoPIC is only used on darwin.
137 if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
138 return Reloc::Static;
139
140 return *RM;
141}
142
143/// Create an ARM architecture model.
144///
145ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
146 StringRef CPU, StringRef FS,
147 const TargetOptions &Options,
148 std::optional<Reloc::Model> RM,
149 std::optional<CodeModel::Model> CM,
150 CodeGenOptLevel OL)
151 : CodeGenTargetMachineImpl(
152 T, TT.computeDataLayout(ABIName: Options.MCOptions.ABIName), TT, CPU, FS,
153 Options, getEffectiveRelocModel(TT, RM),
154 getEffectiveCodeModel(CM, Default: CodeModel::Small), OL),
155 TargetABI(ARM::computeTargetABI(TT, ABIName: Options.MCOptions.ABIName)),
156 TLOF(createTLOF(TT: getTargetTriple())), isLittle(TT.isLittleEndian()) {
157
158 // Default to triple-appropriate float ABI
159 if (Options.FloatABIType == FloatABI::Default) {
160 if (isTargetHardFloat())
161 this->Options.FloatABIType = FloatABI::Hard;
162 else
163 this->Options.FloatABIType = FloatABI::Soft;
164 }
165
166 // Default to triple-appropriate EABI
167 if (Options.EABIVersion == EABI::Default ||
168 Options.EABIVersion == EABI::Unknown) {
169 // musl is compatible with glibc with regard to EABI version
170 if ((TargetTriple.getEnvironment() == Triple::GNUEABI ||
171 TargetTriple.getEnvironment() == Triple::GNUEABIT64 ||
172 TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
173 TargetTriple.getEnvironment() == Triple::GNUEABIHFT64 ||
174 TargetTriple.getEnvironment() == Triple::MuslEABI ||
175 TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
176 TargetTriple.getEnvironment() == Triple::OpenHOS) &&
177 !(TargetTriple.isOSWindows() || TargetTriple.isOSDarwin()))
178 this->Options.EABIVersion = EABI::GNU;
179 else
180 this->Options.EABIVersion = EABI::EABI5;
181 }
182
183 if (TT.isOSBinFormatMachO()) {
184 this->Options.TrapUnreachable = true;
185 this->Options.NoTrapAfterNoreturn = true;
186 }
187
188 // ARM supports the debug entry values.
189 setSupportsDebugEntryValues(true);
190
191 initAsmInfo();
192
193 // ARM supports the MachineOutliner.
194 setMachineOutliner(true);
195 setSupportsDefaultOutlining(true);
196}
197
198ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
199
200MachineFunctionInfo *ARMBaseTargetMachine::createMachineFunctionInfo(
201 BumpPtrAllocator &Allocator, const Function &F,
202 const TargetSubtargetInfo *STI) const {
203 return ARMFunctionInfo::create<ARMFunctionInfo>(
204 Allocator, F, STI: static_cast<const ARMSubtarget *>(STI));
205}
206
207const ARMSubtarget *
208ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
209 Attribute CPUAttr = F.getFnAttribute(Kind: "target-cpu");
210 Attribute FSAttr = F.getFnAttribute(Kind: "target-features");
211
212 std::string CPU =
213 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
214 std::string FS =
215 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
216
217 // FIXME: This is related to the code below to reset the target options,
218 // we need to know whether or not the soft float flag is set on the
219 // function before we can generate a subtarget. We also need to use
220 // it as a key for the subtarget since that can be the only difference
221 // between two functions.
222 bool SoftFloat = F.getFnAttribute(Kind: "use-soft-float").getValueAsBool();
223 // If the soft float attribute is set on the function turn on the soft float
224 // subtarget feature.
225 if (SoftFloat)
226 FS += FS.empty() ? "+soft-float" : ",+soft-float";
227
228 // Use the optminsize to identify the subtarget, but don't use it in the
229 // feature string.
230 std::string Key = CPU + FS;
231 if (F.hasMinSize())
232 Key += "+minsize";
233
234 DenormalMode DM = F.getDenormalFPEnv().DefaultMode;
235 if (DM != DenormalMode::getIEEE())
236 Key += "denormal-fp-math=" + DM.str();
237
238 auto &I = SubtargetMap[Key];
239 if (!I) {
240 // This needs to be done before we create a new subtarget since any
241 // creation will depend on the TM and the code generation flags on the
242 // function that reside in TargetOptions.
243 resetTargetOptions(F);
244 I = std::make_unique<ARMSubtarget>(args: TargetTriple, args&: CPU, args&: FS, args: *this, args: isLittle,
245 args: F.hasMinSize(), args&: DM);
246
247 if (!I->isThumb() && !I->hasARMOps())
248 F.getContext().emitError(ErrorStr: "Function '" + F.getName() + "' uses ARM "
249 "instructions, but the target does not support ARM mode execution.");
250 }
251
252 return I.get();
253}
254
255TargetTransformInfo
256ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) const {
257 return TargetTransformInfo(std::make_unique<ARMTTIImpl>(args: this, args: F));
258}
259
260ScheduleDAGInstrs *
261ARMBaseTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
262 ScheduleDAGMILive *DAG = createSchedLive(C);
263 // add DAG Mutations here.
264 const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
265 if (ST.hasFusion())
266 DAG->addMutation(Mutation: createARMMacroFusionDAGMutation());
267 return DAG;
268}
269
270ScheduleDAGInstrs *
271ARMBaseTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
272 ScheduleDAGMI *DAG = createSchedPostRA(C);
273 // add DAG Mutations here.
274 const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
275 if (ST.hasFusion())
276 DAG->addMutation(Mutation: createARMMacroFusionDAGMutation());
277 if (auto Mutation = createARMLatencyMutations(ST, AA: C->AA))
278 DAG->addMutation(Mutation: std::move(Mutation));
279 return DAG;
280}
281
282ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
283 StringRef CPU, StringRef FS,
284 const TargetOptions &Options,
285 std::optional<Reloc::Model> RM,
286 std::optional<CodeModel::Model> CM,
287 CodeGenOptLevel OL, bool JIT)
288 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
289
290ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
291 StringRef CPU, StringRef FS,
292 const TargetOptions &Options,
293 std::optional<Reloc::Model> RM,
294 std::optional<CodeModel::Model> CM,
295 CodeGenOptLevel OL, bool JIT)
296 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
297
298namespace {
299
300/// ARM Code Generator Pass Configuration Options.
301class ARMPassConfig : public TargetPassConfig {
302public:
303 ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
304 : TargetPassConfig(TM, PM) {}
305
306 ARMBaseTargetMachine &getARMTargetMachine() const {
307 return getTM<ARMBaseTargetMachine>();
308 }
309
310 void addIRPasses() override;
311 void addCodeGenPrepare() override;
312 bool addPreISel() override;
313 bool addInstSelector() override;
314 bool addIRTranslator() override;
315 bool addLegalizeMachineIR() override;
316 bool addRegBankSelect() override;
317 bool addGlobalInstructionSelect() override;
318 void addPreRegAlloc() override;
319 void addPreSched2() override;
320 void addPreEmitPass() override;
321 void addPreEmitPass2() override;
322
323 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
324};
325
326class ARMExecutionDomainFix : public ExecutionDomainFix {
327public:
328 static char ID;
329 ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
330 StringRef getPassName() const override {
331 return "ARM Execution Domain Fix";
332 }
333};
334char ARMExecutionDomainFix::ID;
335
336} // end anonymous namespace
337
338INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
339 "ARM Execution Domain Fix", false, false)
340INITIALIZE_PASS_DEPENDENCY(ReachingDefInfoWrapperPass)
341INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
342 "ARM Execution Domain Fix", false, false)
343
344void ARMBaseTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
345#define GET_PASS_REGISTRY "ARMPassRegistry.def"
346#include "llvm/Passes/TargetPassRegistry.inc"
347}
348
349TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
350 return new ARMPassConfig(*this, PM);
351}
352
353std::unique_ptr<CSEConfigBase> ARMPassConfig::getCSEConfig() const {
354 return getStandardCSEConfigForOpt(Level: TM->getOptLevel());
355}
356
357void ARMPassConfig::addIRPasses() {
358 if (TM->Options.ThreadModel == ThreadModel::Single)
359 addPass(P: createLowerAtomicPass());
360 else
361 addPass(P: createAtomicExpandLegacyPass());
362
363 // Cmpxchg instructions are often used with a subsequent comparison to
364 // determine whether it succeeded. We can exploit existing control-flow in
365 // ldrex/strex loops to simplify this, but it needs tidying up.
366 if (TM->getOptLevel() != CodeGenOptLevel::None && EnableAtomicTidy)
367 addPass(P: createCFGSimplificationPass(
368 Options: SimplifyCFGOptions().hoistCommonInsts(B: true).sinkCommonInsts(B: true),
369 Ftor: [this](const Function &F) {
370 const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
371 return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
372 }));
373
374 addPass(P: createMVEGatherScatterLoweringPass());
375 addPass(P: createMVELaneInterleavingPass());
376
377 TargetPassConfig::addIRPasses();
378
379 // Run the parallel DSP pass.
380 if (getOptLevel() == CodeGenOptLevel::Aggressive)
381 addPass(P: createARMParallelDSPPass());
382
383 // Match complex arithmetic patterns
384 if (TM->getOptLevel() >= CodeGenOptLevel::Default)
385 addPass(P: createComplexDeinterleavingPass(TM));
386
387 // Match interleaved memory accesses to ldN/stN intrinsics.
388 if (TM->getOptLevel() != CodeGenOptLevel::None)
389 addPass(P: createInterleavedAccessPass());
390
391 // Add Control Flow Guard checks.
392 if (TM->getTargetTriple().isOSWindows())
393 addPass(P: createCFGuardCheckPass());
394
395 if (TM->Options.JMCInstrument)
396 addPass(P: createJMCInstrumenterPass());
397}
398
399void ARMPassConfig::addCodeGenPrepare() {
400 if (getOptLevel() != CodeGenOptLevel::None)
401 addPass(P: createTypePromotionLegacyPass());
402 TargetPassConfig::addCodeGenPrepare();
403}
404
405bool ARMPassConfig::addPreISel() {
406 if ((TM->getOptLevel() != CodeGenOptLevel::None &&
407 EnableGlobalMerge == cl::BOU_UNSET) ||
408 EnableGlobalMerge == cl::BOU_TRUE) {
409 // FIXME: This is using the thumb1 only constant value for
410 // maximal global offset for merging globals. We may want
411 // to look into using the old value for non-thumb1 code of
412 // 4095 based on the TargetMachine, but this starts to become
413 // tricky when doing code gen per function.
414 bool OnlyOptimizeForSize =
415 (TM->getOptLevel() < CodeGenOptLevel::Aggressive) &&
416 (EnableGlobalMerge == cl::BOU_UNSET);
417 // Merging of extern globals is enabled by default on non-Mach-O as we
418 // expect it to be generally either beneficial or harmless. On Mach-O it
419 // is disabled as we emit the .subsections_via_symbols directive which
420 // means that merging extern globals is not safe.
421 bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
422 addPass(P: createGlobalMergePass(TM, MaximalOffset: 127, OnlyOptimizeForSize,
423 MergeExternalByDefault));
424 }
425
426 if (TM->getOptLevel() != CodeGenOptLevel::None) {
427 addPass(P: createHardwareLoopsLegacyPass());
428 addPass(P: createMVETailPredicationPass());
429 // FIXME: IR passes can delete address-taken basic blocks, deleting
430 // corresponding blockaddresses. ARMConstantPoolConstant holds references to
431 // address-taken basic blocks which can be invalidated if the function
432 // containing the blockaddress has already been codegen'd and the basic
433 // block is removed. Work around this by forcing all IR passes to run before
434 // any ISel takes place. We should have a more principled way of handling
435 // this. See D99707 for more details.
436 addPass(P: createBarrierNoopPass());
437 }
438
439 return false;
440}
441
442bool ARMPassConfig::addInstSelector() {
443 addPass(P: createARMISelDag(TM&: getARMTargetMachine(), OptLevel: getOptLevel()));
444 return false;
445}
446
447bool ARMPassConfig::addIRTranslator() {
448 addPass(P: new IRTranslator(getOptLevel()));
449 return false;
450}
451
452bool ARMPassConfig::addLegalizeMachineIR() {
453 addPass(P: new Legalizer());
454 return false;
455}
456
457bool ARMPassConfig::addRegBankSelect() {
458 addPass(P: new RegBankSelect());
459 return false;
460}
461
462bool ARMPassConfig::addGlobalInstructionSelect() {
463 addPass(P: new InstructionSelect(getOptLevel()));
464 return false;
465}
466
467void ARMPassConfig::addPreRegAlloc() {
468 if (getOptLevel() != CodeGenOptLevel::None) {
469 if (getOptLevel() == CodeGenOptLevel::Aggressive)
470 addPass(PassID: &MachinePipelinerID);
471
472 addPass(P: createMVETPAndVPTOptimisationsPass());
473
474 addPass(P: createMLxExpansionPass());
475
476 if (EnableARMLoadStoreOpt)
477 addPass(P: createARMLoadStoreOptLegacyPass(/* pre-register alloc */ PreAlloc: true));
478
479 if (!DisableA15SDOptimization)
480 addPass(P: createA15SDOptimizerPass());
481 }
482}
483
484void ARMPassConfig::addPreSched2() {
485 if (getOptLevel() != CodeGenOptLevel::None) {
486 if (EnableARMLoadStoreOpt)
487 addPass(P: createARMLoadStoreOptLegacyPass());
488
489 addPass(P: new ARMExecutionDomainFix());
490 addPass(P: createBreakFalseDeps());
491 }
492
493 // Expand some pseudo instructions into multiple instructions to allow
494 // proper scheduling.
495 addPass(P: createARMExpandPseudoPass());
496
497 // Emit KCFI checks for indirect calls.
498 addPass(P: createKCFIPass());
499
500 if (getOptLevel() != CodeGenOptLevel::None) {
501 // When optimising for size, always run the Thumb2SizeReduction pass before
502 // IfConversion. Otherwise, check whether IT blocks are restricted
503 // (e.g. in v8, IfConversion depends on Thumb instruction widths)
504 addPass(P: createThumb2SizeReductionPass(Ftor: [this](const Function &F) {
505 return this->TM->getSubtarget<ARMSubtarget>(F).hasMinSize() ||
506 this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
507 }));
508
509 addPass(P: createIfConverter(Ftor: [](const MachineFunction &MF) {
510 return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
511 }));
512 }
513 addPass(P: createThumb2ITBlockPass());
514
515 // Add both scheduling passes to give the subtarget an opportunity to pick
516 // between them.
517 if (getOptLevel() != CodeGenOptLevel::None) {
518 addPass(PassID: &PostMachineSchedulerID);
519 addPass(PassID: &PostRASchedulerID);
520 }
521
522 addPass(P: createMVEVPTBlockPass());
523 addPass(P: createARMIndirectThunks());
524 addPass(P: createARMSLSHardeningPass());
525}
526
527void ARMPassConfig::addPreEmitPass() {
528 addPass(P: createThumb2SizeReductionPass());
529
530 // Unpack bundles for:
531 // - Thumb2: Constant island pass requires unbundled instructions
532 // - KCFI: KCFI_CHECK pseudo instructions need to be unbundled for AsmPrinter
533 addPass(P: createUnpackMachineBundlesLegacy(Ftor: [](const MachineFunction &MF) {
534 return MF.getSubtarget<ARMSubtarget>().isThumb2() ||
535 MF.getFunction().getParent()->getModuleFlag(Key: "kcfi");
536 }));
537
538 // Don't optimize barriers or block placement at -O0.
539 if (getOptLevel() != CodeGenOptLevel::None) {
540 addPass(P: createARMBlockPlacementPass());
541 addPass(P: createARMOptimizeBarriersPass());
542 }
543}
544
545void ARMPassConfig::addPreEmitPass2() {
546
547 // Inserts fixup instructions before unsafe AES operations. Instructions may
548 // be inserted at the start of blocks and at within blocks so this pass has to
549 // come before those below.
550 addPass(P: createARMFixCortexA57AES1742098Pass());
551 // Inserts BTIs at the start of functions and indirectly-called basic blocks,
552 // so passes cannot add to the start of basic blocks once this has run.
553 addPass(P: createARMBranchTargetsPass());
554 // Inserts Constant Islands. Block sizes cannot be increased after this point,
555 // as this may push the branch ranges and load offsets of accessing constant
556 // pools out of range..
557 addPass(P: createARMConstantIslandPass());
558 // Finalises Low-Overhead Loops. This replaces pseudo instructions with real
559 // instructions, but the pseudos all have conservative sizes so that block
560 // sizes will only be decreased by this pass.
561 addPass(P: createARMLowOverheadLoopsPass());
562
563 if (TM->getTargetTriple().isOSWindows()) {
564 // Identify valid longjmp targets for Windows Control Flow Guard.
565 addPass(P: createCFGuardLongjmpPass());
566 // Identify valid eh continuation targets for Windows EHCont Guard.
567 addPass(P: createEHContGuardTargetsPass());
568 }
569}
570
571yaml::MachineFunctionInfo *
572ARMBaseTargetMachine::createDefaultFuncInfoYAML() const {
573 return new yaml::ARMFunctionInfo();
574}
575
576yaml::MachineFunctionInfo *
577ARMBaseTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
578 const auto *MFI = MF.getInfo<ARMFunctionInfo>();
579 return new yaml::ARMFunctionInfo(*MFI);
580}
581
582bool ARMBaseTargetMachine::parseMachineFunctionInfo(
583 const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,
584 SMDiagnostic &Error, SMRange &SourceRange) const {
585 const auto &YamlMFI = static_cast<const yaml::ARMFunctionInfo &>(MFI);
586 MachineFunction &MF = PFS.MF;
587 MF.getInfo<ARMFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
588 return false;
589}
590
591void ARMBaseTargetMachine::reset() { SubtargetMap.clear(); }
592