1//===- HexagonBitTracker.cpp ----------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "HexagonBitTracker.h"
10#include "HexagonInstrInfo.h"
11#include "HexagonRegisterInfo.h"
12#include "HexagonSubtarget.h"
13#include "llvm/CodeGen/MachineFrameInfo.h"
14#include "llvm/CodeGen/MachineFunction.h"
15#include "llvm/CodeGen/MachineInstr.h"
16#include "llvm/CodeGen/MachineOperand.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/IR/Argument.h"
19#include "llvm/IR/Attributes.h"
20#include "llvm/IR/Function.h"
21#include "llvm/IR/Type.h"
22#include "llvm/Support/Compiler.h"
23#include "llvm/Support/Debug.h"
24#include "llvm/Support/ErrorHandling.h"
25
26using namespace llvm;
27
28using BT = BitTracker;
29
30HexagonEvaluator::HexagonEvaluator(const HexagonRegisterInfo &tri,
31 MachineRegisterInfo &mri,
32 const HexagonInstrInfo &tii,
33 MachineFunction &mf)
34 : MachineEvaluator(tri, mri), MF(mf), MFI(mf.getFrameInfo()), TII(tii) {
35 // Populate the VRX map (VR to extension-type).
36 // Go over all the formal parameters of the function. If a given parameter
37 // P is sign- or zero-extended, locate the virtual register holding that
38 // parameter and create an entry in the VRX map indicating the type of ex-
39 // tension (and the source type).
40 // This is a bit complicated to do accurately, since the memory layout in-
41 // formation is necessary to precisely determine whether an aggregate para-
42 // meter will be passed in a register or in memory. What is given in MRI
43 // is the association between the physical register that is live-in (i.e.
44 // holds an argument), and the virtual register that this value will be
45 // copied into. This, by itself, is not sufficient to map back the virtual
46 // register to a formal parameter from Function (since consecutive live-ins
47 // from MRI may not correspond to consecutive formal parameters from Func-
48 // tion). To avoid the complications with in-memory arguments, only consi-
49 // der the initial sequence of formal parameters that are known to be
50 // passed via registers.
51 unsigned InVirtReg, InPhysReg = 0;
52
53 for (const Argument &Arg : MF.getFunction().args()) {
54 Type *ATy = Arg.getType();
55 unsigned Width = 0;
56 if (ATy->isIntegerTy())
57 Width = ATy->getIntegerBitWidth();
58 else if (ATy->isPointerTy())
59 Width = 32;
60 // If pointer size is not set through target data, it will default to
61 // Module::AnyPointerSize.
62 if (Width == 0 || Width > 64)
63 break;
64 if (Arg.hasAttribute(Kind: Attribute::ByVal))
65 continue;
66 InPhysReg = getNextPhysReg(PReg: InPhysReg, Width);
67 if (!InPhysReg)
68 break;
69 InVirtReg = getVirtRegFor(PReg: InPhysReg);
70 if (!InVirtReg)
71 continue;
72 if (Arg.hasAttribute(Kind: Attribute::SExt))
73 VRX.insert(KV: std::make_pair(x&: InVirtReg, y: ExtType(ExtType::SExt, Width)));
74 else if (Arg.hasAttribute(Kind: Attribute::ZExt))
75 VRX.insert(KV: std::make_pair(x&: InVirtReg, y: ExtType(ExtType::ZExt, Width)));
76 }
77}
78
79BT::BitMask HexagonEvaluator::mask(Register Reg, unsigned Sub) const {
80 if (Sub == 0)
81 return MachineEvaluator::mask(Reg, Sub: 0);
82 const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
83 uint16_t RW = getRegBitWidth(RR: RegisterRef(Reg, Sub));
84 const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
85 bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, GenIdx: Hexagon::ps_sub_lo));
86 if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC: &RC) ||
87 Hexagon::HvxWRRegClass.hasSubClassEq(RC: &RC) ||
88 Hexagon::HvxVQRRegClass.hasSubClassEq(RC: &RC))
89 return IsSubLo ? BT::BitMask(0, RW - 1) : BT::BitMask(RW, 2 * RW - 1);
90#ifndef NDEBUG
91 dbgs() << printReg(Reg, &TRI, Sub) << " in reg class "
92 << TRI.getRegClassName(&RC) << '\n';
93#endif
94 llvm_unreachable("Unexpected register/subregister");
95}
96
97uint16_t HexagonEvaluator::getPhysRegBitWidth(MCRegister Reg) const {
98 using namespace Hexagon;
99 const auto &HST = MF.getSubtarget<HexagonSubtarget>();
100 if (HST.useHVXOps()) {
101 for (auto *RC :
102 {&HvxVRRegClass, &HvxWRRegClass, &HvxQRRegClass, &HvxVQRRegClass})
103 if (RC->contains(Reg))
104 return TRI.getRegSizeInBits(RC: *RC);
105 }
106 // Default treatment for other physical registers.
107 if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg))
108 return TRI.getRegSizeInBits(RC: *RC);
109
110 llvm_unreachable(
111 (Twine("Unhandled physical register") + TRI.getName(Reg)).str().c_str());
112}
113
114const TargetRegisterClass &HexagonEvaluator::composeWithSubRegIndex(
115 const TargetRegisterClass &RC, unsigned Idx) const {
116 if (Idx == 0)
117 return RC;
118
119#ifndef NDEBUG
120 const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
121 bool IsSubLo = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
122 bool IsSubHi = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi));
123 assert(IsSubLo != IsSubHi && "Must refer to either low or high subreg");
124#endif
125
126 if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC: &RC))
127 return Hexagon::IntRegsRegClass;
128 if (Hexagon::HvxWRRegClass.hasSubClassEq(RC: &RC))
129 return Hexagon::HvxVRRegClass;
130 if (Hexagon::HvxVQRRegClass.hasSubClassEq(RC: &RC))
131 return Hexagon::HvxWRRegClass;
132#ifndef NDEBUG
133 dbgs() << "Reg class id: " << RC.getID() << " idx: " << Idx << '\n';
134#endif
135 llvm_unreachable("Unimplemented combination of reg class/subreg idx");
136}
137
138namespace {
139
140class RegisterRefs {
141 std::vector<BT::RegisterRef> Vector;
142
143public:
144 RegisterRefs(const MachineInstr &MI) : Vector(MI.getNumOperands()) {
145 for (unsigned i = 0, n = Vector.size(); i < n; ++i) {
146 const MachineOperand &MO = MI.getOperand(i);
147 if (MO.isReg())
148 Vector[i] = BT::RegisterRef(MO);
149 // For indices that don't correspond to registers, the entry will
150 // remain constructed via the default constructor.
151 }
152 }
153
154 size_t size() const { return Vector.size(); }
155
156 const BT::RegisterRef &operator[](unsigned n) const {
157 // The main purpose of this operator is to assert with bad argument.
158 assert(n < Vector.size());
159 return Vector[n];
160 }
161};
162
163} // end anonymous namespace
164
165bool HexagonEvaluator::evaluate(const MachineInstr &MI,
166 const CellMapType &Inputs,
167 CellMapType &Outputs) const {
168 using namespace Hexagon;
169
170 unsigned NumDefs = 0;
171
172 // Basic correctness check: there should not be any defs with subregisters.
173 for (const MachineOperand &MO : MI.operands()) {
174 if (!MO.isReg() || !MO.isDef())
175 continue;
176 NumDefs++;
177 assert(MO.getSubReg() == 0);
178 }
179
180 if (NumDefs == 0)
181 return false;
182
183 unsigned Opc = MI.getOpcode();
184
185 if (MI.mayLoad()) {
186 switch (Opc) {
187 // These instructions may be marked as mayLoad, but they are generating
188 // immediate values, so skip them.
189 case CONST32:
190 case CONST64:
191 break;
192 default:
193 return evaluateLoad(MI, Inputs, Outputs);
194 }
195 }
196
197 // Check COPY instructions that copy formal parameters into virtual
198 // registers. Such parameters can be sign- or zero-extended at the
199 // call site, and we should take advantage of this knowledge. The MRI
200 // keeps a list of pairs of live-in physical and virtual registers,
201 // which provides information about which virtual registers will hold
202 // the argument values. The function will still contain instructions
203 // defining those virtual registers, and in practice those are COPY
204 // instructions from a physical to a virtual register. In such cases,
205 // applying the argument extension to the virtual register can be seen
206 // as simply mirroring the extension that had already been applied to
207 // the physical register at the call site. If the defining instruction
208 // was not a COPY, it would not be clear how to mirror that extension
209 // on the callee's side. For that reason, only check COPY instructions
210 // for potential extensions.
211 if (MI.isCopy()) {
212 if (evaluateFormalCopy(MI, Inputs, Outputs))
213 return true;
214 }
215
216 // Beyond this point, if any operand is a global, skip that instruction.
217 // The reason is that certain instructions that can take an immediate
218 // operand can also have a global symbol in that operand. To avoid
219 // checking what kind of operand a given instruction has individually
220 // for each instruction, do it here. Global symbols as operands gene-
221 // rally do not provide any useful information.
222 for (const MachineOperand &MO : MI.operands()) {
223 if (MO.isGlobal() || MO.isBlockAddress() || MO.isSymbol() || MO.isJTI() ||
224 MO.isCPI())
225 return false;
226 }
227
228 RegisterRefs Reg(MI);
229#define op(i) MI.getOperand(i)
230#define rc(i) RegisterCell::ref(getCell(Reg[i], Inputs))
231#define im(i) MI.getOperand(i).getImm()
232
233 // If the instruction has no register operands, skip it.
234 if (Reg.size() == 0)
235 return false;
236
237 // Record result for register in operand 0.
238 auto rr0 = [this,Reg] (const BT::RegisterCell &Val, CellMapType &Outputs)
239 -> bool {
240 putCell(RR: Reg[0], RC: Val, M&: Outputs);
241 return true;
242 };
243 // Get the cell corresponding to the N-th operand.
244 auto cop = [this, &Reg, &MI, &Inputs](unsigned N,
245 uint16_t W) -> BT::RegisterCell {
246 const MachineOperand &Op = MI.getOperand(i: N);
247 if (Op.isImm())
248 return eIMM(V: Op.getImm(), W);
249 if (!Op.isReg())
250 return RegisterCell::self(Reg: 0, Width: W);
251 assert(getRegBitWidth(Reg[N]) == W && "Register width mismatch");
252 return rc(N);
253 };
254 // Extract RW low bits of the cell.
255 auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
256 -> BT::RegisterCell {
257 assert(RW <= RC.width());
258 return eXTR(A1: RC, B: 0, E: RW);
259 };
260 // Extract RW high bits of the cell.
261 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW)
262 -> BT::RegisterCell {
263 uint16_t W = RC.width();
264 assert(RW <= W);
265 return eXTR(A1: RC, B: W-RW, E: W);
266 };
267 // Extract N-th halfword (counting from the least significant position).
268 auto half = [this] (const BT::RegisterCell &RC, unsigned N)
269 -> BT::RegisterCell {
270 assert(N*16+16 <= RC.width());
271 return eXTR(A1: RC, B: N*16, E: N*16+16);
272 };
273 // Shuffle bits (pick even/odd from cells and merge into result).
274 auto shuffle = [this] (const BT::RegisterCell &Rs, const BT::RegisterCell &Rt,
275 uint16_t BW, bool Odd) -> BT::RegisterCell {
276 uint16_t I = Odd, Ws = Rs.width();
277 assert(Ws == Rt.width());
278 RegisterCell RC = eXTR(A1: Rt, B: I*BW, E: I*BW+BW).cat(RC: eXTR(A1: Rs, B: I*BW, E: I*BW+BW));
279 I += 2;
280 while (I*BW < Ws) {
281 RC.cat(RC: eXTR(A1: Rt, B: I*BW, E: I*BW+BW)).cat(RC: eXTR(A1: Rs, B: I*BW, E: I*BW+BW));
282 I += 2;
283 }
284 return RC;
285 };
286
287 // The bitwidth of the 0th operand. In most (if not all) of the
288 // instructions below, the 0th operand is the defined register.
289 // Pre-compute the bitwidth here, because it is needed in many cases
290 // cases below.
291 uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(RR: Reg[0]) : 0;
292
293 // Register id of the 0th operand. It can be 0.
294 unsigned Reg0 = Reg[0].Reg;
295
296 switch (Opc) {
297 // Transfer immediate:
298
299 case A2_tfrsi:
300 case A2_tfrpi:
301 case CONST32:
302 case CONST64:
303 return rr0(eIMM(im(1), W: W0), Outputs);
304 case PS_false:
305 return rr0(RegisterCell(W0).fill(B: 0, E: W0, V: BT::BitValue::Zero), Outputs);
306 case PS_true:
307 return rr0(RegisterCell(W0).fill(B: 0, E: W0, V: BT::BitValue::One), Outputs);
308 case PS_fi: {
309 int FI = op(1).getIndex();
310 int Off = op(2).getImm();
311 unsigned A = MFI.getObjectAlign(ObjectIdx: FI).value() + std::abs(x: Off);
312 unsigned L = llvm::countr_zero(Val: A);
313 RegisterCell RC = RegisterCell::self(Reg: Reg[0].Reg, Width: W0);
314 RC.fill(B: 0, E: L, V: BT::BitValue::Zero);
315 return rr0(RC, Outputs);
316 }
317
318 // Transfer register:
319
320 case A2_tfr:
321 case A2_tfrp:
322 case C2_pxfer_map:
323 return rr0(rc(1), Outputs);
324 case C2_tfrpr: {
325 uint16_t RW = W0;
326 uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
327 assert(PW <= RW);
328 RegisterCell PC = eXTR(rc(1), B: 0, E: PW);
329 RegisterCell RC = RegisterCell(RW).insert(RC: PC, M: BT::BitMask(0, PW-1));
330 RC.fill(B: PW, E: RW, V: BT::BitValue::Zero);
331 return rr0(RC, Outputs);
332 }
333 case C2_tfrrp: {
334 uint16_t RW = W0;
335 uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
336 RegisterCell RC = RegisterCell::self(Reg: Reg[0].Reg, Width: RW);
337 RC.fill(B: PW, E: RW, V: BT::BitValue::Zero);
338 return rr0(eINS(A1: RC, A2: eXTR(rc(1), B: 0, E: PW), AtN: 0), Outputs);
339 }
340
341 // Arithmetic:
342
343 case A2_abs:
344 case A2_absp:
345 // TODO
346 break;
347
348 case A2_addsp: {
349 uint16_t W1 = getRegBitWidth(RR: Reg[1]);
350 assert(W0 == 64 && W1 == 32);
351 RegisterCell CW = RegisterCell(W0).insert(rc(1), M: BT::BitMask(0, W1-1));
352 RegisterCell RC = eADD(A1: eSXT(A1: CW, FromN: W1), rc(2));
353 return rr0(RC, Outputs);
354 }
355 case A2_add:
356 case A2_addp:
357 return rr0(eADD(rc(1), rc(2)), Outputs);
358 case A2_addi:
359 return rr0(eADD(rc(1), A2: eIMM(im(2), W: W0)), Outputs);
360 case S4_addi_asl_ri: {
361 RegisterCell RC = eADD(A1: eIMM(im(1), W: W0), A2: eASL(rc(2), im(3)));
362 return rr0(RC, Outputs);
363 }
364 case S4_addi_lsr_ri: {
365 RegisterCell RC = eADD(A1: eIMM(im(1), W: W0), A2: eLSR(rc(2), im(3)));
366 return rr0(RC, Outputs);
367 }
368 case S4_addaddi: {
369 RegisterCell RC = eADD(rc(1), A2: eADD(rc(2), A2: eIMM(im(3), W: W0)));
370 return rr0(RC, Outputs);
371 }
372 case M4_mpyri_addi: {
373 RegisterCell M = eMLS(rc(2), A2: eIMM(im(3), W: W0));
374 RegisterCell RC = eADD(A1: eIMM(im(1), W: W0), A2: lo(M, W0));
375 return rr0(RC, Outputs);
376 }
377 case M4_mpyrr_addi: {
378 RegisterCell M = eMLS(rc(2), rc(3));
379 RegisterCell RC = eADD(A1: eIMM(im(1), W: W0), A2: lo(M, W0));
380 return rr0(RC, Outputs);
381 }
382 case M4_mpyri_addr_u2: {
383 RegisterCell M = eMLS(A1: eIMM(im(2), W: W0), rc(3));
384 RegisterCell RC = eADD(rc(1), A2: lo(M, W0));
385 return rr0(RC, Outputs);
386 }
387 case M4_mpyri_addr: {
388 RegisterCell M = eMLS(rc(2), A2: eIMM(im(3), W: W0));
389 RegisterCell RC = eADD(rc(1), A2: lo(M, W0));
390 return rr0(RC, Outputs);
391 }
392 case M4_mpyrr_addr: {
393 RegisterCell M = eMLS(rc(2), rc(3));
394 RegisterCell RC = eADD(rc(1), A2: lo(M, W0));
395 return rr0(RC, Outputs);
396 }
397 case S4_subaddi: {
398 RegisterCell RC = eADD(rc(1), A2: eSUB(A1: eIMM(im(2), W: W0), rc(3)));
399 return rr0(RC, Outputs);
400 }
401 case M2_accii: {
402 RegisterCell RC = eADD(rc(1), A2: eADD(rc(2), A2: eIMM(im(3), W: W0)));
403 return rr0(RC, Outputs);
404 }
405 case M2_acci: {
406 RegisterCell RC = eADD(rc(1), A2: eADD(rc(2), rc(3)));
407 return rr0(RC, Outputs);
408 }
409 case M2_subacc: {
410 RegisterCell RC = eADD(rc(1), A2: eSUB(rc(2), rc(3)));
411 return rr0(RC, Outputs);
412 }
413 case S2_addasl_rrri: {
414 RegisterCell RC = eADD(rc(1), A2: eASL(rc(2), im(3)));
415 return rr0(RC, Outputs);
416 }
417 case C4_addipc: {
418 RegisterCell RPC = RegisterCell::self(Reg: Reg[0].Reg, Width: W0);
419 RPC.fill(B: 0, E: 2, V: BT::BitValue::Zero);
420 return rr0(eADD(A1: RPC, A2: eIMM(im(2), W: W0)), Outputs);
421 }
422 case A2_sub:
423 case A2_subp:
424 return rr0(eSUB(rc(1), rc(2)), Outputs);
425 case A2_subri:
426 return rr0(eSUB(A1: eIMM(im(1), W: W0), rc(2)), Outputs);
427 case S4_subi_asl_ri: {
428 RegisterCell RC = eSUB(A1: eIMM(im(1), W: W0), A2: eASL(rc(2), im(3)));
429 return rr0(RC, Outputs);
430 }
431 case S4_subi_lsr_ri: {
432 RegisterCell RC = eSUB(A1: eIMM(im(1), W: W0), A2: eLSR(rc(2), im(3)));
433 return rr0(RC, Outputs);
434 }
435 case M2_naccii: {
436 RegisterCell RC = eSUB(rc(1), A2: eADD(rc(2), A2: eIMM(im(3), W: W0)));
437 return rr0(RC, Outputs);
438 }
439 case M2_nacci: {
440 RegisterCell RC = eSUB(rc(1), A2: eADD(rc(2), rc(3)));
441 return rr0(RC, Outputs);
442 }
443 // 32-bit negation is done by "Rd = A2_subri 0, Rs"
444 case A2_negp:
445 return rr0(eSUB(A1: eIMM(V: 0, W: W0), rc(1)), Outputs);
446
447 case M2_mpy_up: {
448 RegisterCell M = eMLS(rc(1), rc(2));
449 return rr0(hi(M, W0), Outputs);
450 }
451 case M2_dpmpyss_s0:
452 return rr0(eMLS(rc(1), rc(2)), Outputs);
453 case M2_dpmpyss_acc_s0:
454 return rr0(eADD(rc(1), A2: eMLS(rc(2), rc(3))), Outputs);
455 case M2_dpmpyss_nac_s0:
456 return rr0(eSUB(rc(1), A2: eMLS(rc(2), rc(3))), Outputs);
457 case M2_mpyi: {
458 RegisterCell M = eMLS(rc(1), rc(2));
459 return rr0(lo(M, W0), Outputs);
460 }
461 case M2_macsip: {
462 RegisterCell M = eMLS(rc(2), A2: eIMM(im(3), W: W0));
463 RegisterCell RC = eADD(rc(1), A2: lo(M, W0));
464 return rr0(RC, Outputs);
465 }
466 case M2_macsin: {
467 RegisterCell M = eMLS(rc(2), A2: eIMM(im(3), W: W0));
468 RegisterCell RC = eSUB(rc(1), A2: lo(M, W0));
469 return rr0(RC, Outputs);
470 }
471 case M2_maci: {
472 RegisterCell M = eMLS(rc(2), rc(3));
473 RegisterCell RC = eADD(rc(1), A2: lo(M, W0));
474 return rr0(RC, Outputs);
475 }
476 case M2_mnaci: {
477 RegisterCell M = eMLS(rc(2), rc(3));
478 RegisterCell RC = eSUB(rc(1), A2: lo(M, W0));
479 return rr0(RC, Outputs);
480 }
481 case M2_mpysmi: {
482 RegisterCell M = eMLS(rc(1), A2: eIMM(im(2), W: W0));
483 return rr0(lo(M, 32), Outputs);
484 }
485 case M2_mpysin: {
486 RegisterCell M = eMLS(rc(1), A2: eIMM(V: -im(2), W: W0));
487 return rr0(lo(M, 32), Outputs);
488 }
489 case M2_mpysip: {
490 RegisterCell M = eMLS(rc(1), A2: eIMM(im(2), W: W0));
491 return rr0(lo(M, 32), Outputs);
492 }
493 case M2_mpyu_up: {
494 RegisterCell M = eMLU(rc(1), rc(2));
495 return rr0(hi(M, W0), Outputs);
496 }
497 case M2_dpmpyuu_s0:
498 return rr0(eMLU(rc(1), rc(2)), Outputs);
499 case M2_dpmpyuu_acc_s0:
500 return rr0(eADD(rc(1), A2: eMLU(rc(2), rc(3))), Outputs);
501 case M2_dpmpyuu_nac_s0:
502 return rr0(eSUB(rc(1), A2: eMLU(rc(2), rc(3))), Outputs);
503 //case M2_mpysu_up:
504
505 // Logical/bitwise:
506
507 case A2_andir:
508 return rr0(eAND(rc(1), A2: eIMM(im(2), W: W0)), Outputs);
509 case A2_and:
510 case A2_andp:
511 return rr0(eAND(rc(1), rc(2)), Outputs);
512 case A4_andn:
513 case A4_andnp:
514 return rr0(eAND(rc(1), A2: eNOT(rc(2))), Outputs);
515 case S4_andi_asl_ri: {
516 RegisterCell RC = eAND(A1: eIMM(im(1), W: W0), A2: eASL(rc(2), im(3)));
517 return rr0(RC, Outputs);
518 }
519 case S4_andi_lsr_ri: {
520 RegisterCell RC = eAND(A1: eIMM(im(1), W: W0), A2: eLSR(rc(2), im(3)));
521 return rr0(RC, Outputs);
522 }
523 case M4_and_and:
524 return rr0(eAND(rc(1), A2: eAND(rc(2), rc(3))), Outputs);
525 case M4_and_andn:
526 return rr0(eAND(rc(1), A2: eAND(rc(2), A2: eNOT(rc(3)))), Outputs);
527 case M4_and_or:
528 return rr0(eAND(rc(1), A2: eORL(rc(2), rc(3))), Outputs);
529 case M4_and_xor:
530 return rr0(eAND(rc(1), A2: eXOR(rc(2), rc(3))), Outputs);
531 case A2_orir:
532 return rr0(eORL(rc(1), A2: eIMM(im(2), W: W0)), Outputs);
533 case A2_or:
534 case A2_orp:
535 return rr0(eORL(rc(1), rc(2)), Outputs);
536 case A4_orn:
537 case A4_ornp:
538 return rr0(eORL(rc(1), A2: eNOT(rc(2))), Outputs);
539 case S4_ori_asl_ri: {
540 RegisterCell RC = eORL(A1: eIMM(im(1), W: W0), A2: eASL(rc(2), im(3)));
541 return rr0(RC, Outputs);
542 }
543 case S4_ori_lsr_ri: {
544 RegisterCell RC = eORL(A1: eIMM(im(1), W: W0), A2: eLSR(rc(2), im(3)));
545 return rr0(RC, Outputs);
546 }
547 case M4_or_and:
548 return rr0(eORL(rc(1), A2: eAND(rc(2), rc(3))), Outputs);
549 case M4_or_andn:
550 return rr0(eORL(rc(1), A2: eAND(rc(2), A2: eNOT(rc(3)))), Outputs);
551 case S4_or_andi:
552 case S4_or_andix: {
553 RegisterCell RC = eORL(rc(1), A2: eAND(rc(2), A2: eIMM(im(3), W: W0)));
554 return rr0(RC, Outputs);
555 }
556 case S4_or_ori: {
557 RegisterCell RC = eORL(rc(1), A2: eORL(rc(2), A2: eIMM(im(3), W: W0)));
558 return rr0(RC, Outputs);
559 }
560 case M4_or_or:
561 return rr0(eORL(rc(1), A2: eORL(rc(2), rc(3))), Outputs);
562 case M4_or_xor:
563 return rr0(eORL(rc(1), A2: eXOR(rc(2), rc(3))), Outputs);
564 case A2_xor:
565 case A2_xorp:
566 return rr0(eXOR(rc(1), rc(2)), Outputs);
567 case M4_xor_and:
568 return rr0(eXOR(rc(1), A2: eAND(rc(2), rc(3))), Outputs);
569 case M4_xor_andn:
570 return rr0(eXOR(rc(1), A2: eAND(rc(2), A2: eNOT(rc(3)))), Outputs);
571 case M4_xor_or:
572 return rr0(eXOR(rc(1), A2: eORL(rc(2), rc(3))), Outputs);
573 case M4_xor_xacc:
574 return rr0(eXOR(rc(1), A2: eXOR(rc(2), rc(3))), Outputs);
575 case A2_not:
576 case A2_notp:
577 return rr0(eNOT(rc(1)), Outputs);
578
579 case S2_asl_i_r:
580 case S2_asl_i_p:
581 return rr0(eASL(rc(1), im(2)), Outputs);
582 case A2_aslh:
583 return rr0(eASL(rc(1), Sh: 16), Outputs);
584 case S2_asl_i_r_acc:
585 case S2_asl_i_p_acc:
586 return rr0(eADD(rc(1), A2: eASL(rc(2), im(3))), Outputs);
587 case S2_asl_i_r_nac:
588 case S2_asl_i_p_nac:
589 return rr0(eSUB(rc(1), A2: eASL(rc(2), im(3))), Outputs);
590 case S2_asl_i_r_and:
591 case S2_asl_i_p_and:
592 return rr0(eAND(rc(1), A2: eASL(rc(2), im(3))), Outputs);
593 case S2_asl_i_r_or:
594 case S2_asl_i_p_or:
595 return rr0(eORL(rc(1), A2: eASL(rc(2), im(3))), Outputs);
596 case S2_asl_i_r_xacc:
597 case S2_asl_i_p_xacc:
598 return rr0(eXOR(rc(1), A2: eASL(rc(2), im(3))), Outputs);
599 case S2_asl_i_vh:
600 case S2_asl_i_vw:
601 // TODO
602 break;
603
604 case S2_asr_i_r:
605 case S2_asr_i_p:
606 return rr0(eASR(rc(1), im(2)), Outputs);
607 case A2_asrh:
608 return rr0(eASR(rc(1), Sh: 16), Outputs);
609 case S2_asr_i_r_acc:
610 case S2_asr_i_p_acc:
611 return rr0(eADD(rc(1), A2: eASR(rc(2), im(3))), Outputs);
612 case S2_asr_i_r_nac:
613 case S2_asr_i_p_nac:
614 return rr0(eSUB(rc(1), A2: eASR(rc(2), im(3))), Outputs);
615 case S2_asr_i_r_and:
616 case S2_asr_i_p_and:
617 return rr0(eAND(rc(1), A2: eASR(rc(2), im(3))), Outputs);
618 case S2_asr_i_r_or:
619 case S2_asr_i_p_or:
620 return rr0(eORL(rc(1), A2: eASR(rc(2), im(3))), Outputs);
621 case S2_asr_i_r_rnd: {
622 // The input is first sign-extended to 64 bits, then the output
623 // is truncated back to 32 bits.
624 assert(W0 == 32);
625 RegisterCell XC = eSXT(rc(1).cat(RC: eIMM(V: 0, W: W0)), FromN: W0);
626 RegisterCell RC = eASR(A1: eADD(A1: eASR(A1: XC, im(2)), A2: eIMM(V: 1, W: 2*W0)), Sh: 1);
627 return rr0(eXTR(A1: RC, B: 0, E: W0), Outputs);
628 }
629 case S2_asr_i_r_rnd_goodsyntax: {
630 int64_t S = im(2);
631 if (S == 0)
632 return rr0(rc(1), Outputs);
633 // Result: S2_asr_i_r_rnd Rs, u5-1
634 RegisterCell XC = eSXT(rc(1).cat(RC: eIMM(V: 0, W: W0)), FromN: W0);
635 RegisterCell RC = eLSR(A1: eADD(A1: eASR(A1: XC, Sh: S-1), A2: eIMM(V: 1, W: 2*W0)), Sh: 1);
636 return rr0(eXTR(A1: RC, B: 0, E: W0), Outputs);
637 }
638 case S2_asr_r_vh:
639 case S2_asr_i_vw:
640 case S2_asr_i_svw_trun:
641 // TODO
642 break;
643
644 case S2_lsr_i_r:
645 case S2_lsr_i_p:
646 return rr0(eLSR(rc(1), im(2)), Outputs);
647 case S2_lsr_i_r_acc:
648 case S2_lsr_i_p_acc:
649 return rr0(eADD(rc(1), A2: eLSR(rc(2), im(3))), Outputs);
650 case S2_lsr_i_r_nac:
651 case S2_lsr_i_p_nac:
652 return rr0(eSUB(rc(1), A2: eLSR(rc(2), im(3))), Outputs);
653 case S2_lsr_i_r_and:
654 case S2_lsr_i_p_and:
655 return rr0(eAND(rc(1), A2: eLSR(rc(2), im(3))), Outputs);
656 case S2_lsr_i_r_or:
657 case S2_lsr_i_p_or:
658 return rr0(eORL(rc(1), A2: eLSR(rc(2), im(3))), Outputs);
659 case S2_lsr_i_r_xacc:
660 case S2_lsr_i_p_xacc:
661 return rr0(eXOR(rc(1), A2: eLSR(rc(2), im(3))), Outputs);
662
663 case S2_clrbit_i: {
664 RegisterCell RC = rc(1);
665 RC[im(2)] = BT::BitValue::Zero;
666 return rr0(RC, Outputs);
667 }
668 case S2_setbit_i: {
669 RegisterCell RC = rc(1);
670 RC[im(2)] = BT::BitValue::One;
671 return rr0(RC, Outputs);
672 }
673 case S2_togglebit_i: {
674 RegisterCell RC = rc(1);
675 uint16_t BX = im(2);
676 RC[BX] = RC[BX].is(T: 0) ? BT::BitValue::One
677 : RC[BX].is(T: 1) ? BT::BitValue::Zero
678 : BT::BitValue::self();
679 return rr0(RC, Outputs);
680 }
681
682 case A4_bitspliti: {
683 uint16_t W1 = getRegBitWidth(RR: Reg[1]);
684 uint16_t BX = im(2);
685 // Res.uw[1] = Rs[bx+1:], Res.uw[0] = Rs[0:bx]
686 const BT::BitValue Zero = BT::BitValue::Zero;
687 RegisterCell RZ = RegisterCell(W0).fill(B: BX, E: W1, V: Zero)
688 .fill(B: W1+(W1-BX), E: W0, V: Zero);
689 RegisterCell BF1 = eXTR(rc(1), B: 0, E: BX), BF2 = eXTR(rc(1), B: BX, E: W1);
690 RegisterCell RC = eINS(A1: eINS(A1: RZ, A2: BF1, AtN: 0), A2: BF2, AtN: W1);
691 return rr0(RC, Outputs);
692 }
693 case S4_extract:
694 case S4_extractp:
695 case S2_extractu:
696 case S2_extractup: {
697 uint16_t Wd = im(2), Of = im(3);
698 assert(Wd <= W0);
699 if (Wd == 0)
700 return rr0(eIMM(V: 0, W: W0), Outputs);
701 // If the width extends beyond the register size, pad the register
702 // with 0 bits.
703 RegisterCell Pad = (Wd+Of > W0) ? rc(1).cat(RC: eIMM(V: 0, W: Wd+Of-W0)) : rc(1);
704 RegisterCell Ext = eXTR(A1: Pad, B: Of, E: Wd+Of);
705 // Ext is short, need to extend it with 0s or sign bit.
706 RegisterCell RC = RegisterCell(W0).insert(RC: Ext, M: BT::BitMask(0, Wd-1));
707 if (Opc == S2_extractu || Opc == S2_extractup)
708 return rr0(eZXT(A1: RC, FromN: Wd), Outputs);
709 return rr0(eSXT(A1: RC, FromN: Wd), Outputs);
710 }
711 case S2_insert:
712 case S2_insertp: {
713 uint16_t Wd = im(3), Of = im(4);
714 assert(Wd < W0 && Of < W0);
715 // If Wd+Of exceeds W0, the inserted bits are truncated.
716 if (Wd+Of > W0)
717 Wd = W0-Of;
718 if (Wd == 0)
719 return rr0(rc(1), Outputs);
720 return rr0(eINS(rc(1), A2: eXTR(rc(2), B: 0, E: Wd), AtN: Of), Outputs);
721 }
722
723 // Bit permutations:
724
725 case A2_combineii:
726 case A4_combineii:
727 case A4_combineir:
728 case A4_combineri:
729 case A2_combinew:
730 case V6_vcombine:
731 assert(W0 % 2 == 0);
732 return rr0(cop(2, W0/2).cat(RC: cop(1, W0/2)), Outputs);
733 case A2_combine_ll:
734 case A2_combine_lh:
735 case A2_combine_hl:
736 case A2_combine_hh: {
737 assert(W0 == 32);
738 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
739 // Low half in the output is 0 for _ll and _hl, 1 otherwise:
740 unsigned LoH = !(Opc == A2_combine_ll || Opc == A2_combine_hl);
741 // High half in the output is 0 for _ll and _lh, 1 otherwise:
742 unsigned HiH = !(Opc == A2_combine_ll || Opc == A2_combine_lh);
743 RegisterCell R1 = rc(1);
744 RegisterCell R2 = rc(2);
745 RegisterCell RC = half(R2, LoH).cat(RC: half(R1, HiH));
746 return rr0(RC, Outputs);
747 }
748 case S2_packhl: {
749 assert(W0 == 64);
750 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
751 RegisterCell R1 = rc(1);
752 RegisterCell R2 = rc(2);
753 RegisterCell RC = half(R2, 0).cat(RC: half(R1, 0)).cat(RC: half(R2, 1))
754 .cat(RC: half(R1, 1));
755 return rr0(RC, Outputs);
756 }
757 case S2_shuffeb: {
758 RegisterCell RC = shuffle(rc(1), rc(2), 8, false);
759 return rr0(RC, Outputs);
760 }
761 case S2_shuffeh: {
762 RegisterCell RC = shuffle(rc(1), rc(2), 16, false);
763 return rr0(RC, Outputs);
764 }
765 case S2_shuffob: {
766 RegisterCell RC = shuffle(rc(1), rc(2), 8, true);
767 return rr0(RC, Outputs);
768 }
769 case S2_shuffoh: {
770 RegisterCell RC = shuffle(rc(1), rc(2), 16, true);
771 return rr0(RC, Outputs);
772 }
773 case C2_mask: {
774 uint16_t WR = W0;
775 uint16_t WP = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
776 assert(WR == 64 && WP == 8);
777 RegisterCell R1 = rc(1);
778 RegisterCell RC(WR);
779 for (uint16_t i = 0; i < WP; ++i) {
780 const BT::BitValue &V = R1[i];
781 BT::BitValue F = (V.is(T: 0) || V.is(T: 1)) ? V : BT::BitValue::self();
782 RC.fill(B: i*8, E: i*8+8, V: F);
783 }
784 return rr0(RC, Outputs);
785 }
786
787 // Mux:
788
789 case C2_muxii:
790 case C2_muxir:
791 case C2_muxri:
792 case C2_mux: {
793 BT::BitValue PC0 = rc(1)[0];
794 RegisterCell R2 = cop(2, W0);
795 RegisterCell R3 = cop(3, W0);
796 if (PC0.is(T: 0) || PC0.is(T: 1))
797 return rr0(RegisterCell::ref(C: PC0 ? R2 : R3), Outputs);
798 R2.meet(RC: R3, SelfR: Reg[0].Reg);
799 return rr0(R2, Outputs);
800 }
801 case C2_vmux:
802 // TODO
803 break;
804
805 // Sign- and zero-extension:
806
807 case A2_sxtb:
808 return rr0(eSXT(rc(1), FromN: 8), Outputs);
809 case A2_sxth:
810 return rr0(eSXT(rc(1), FromN: 16), Outputs);
811 case A2_sxtw: {
812 uint16_t W1 = getRegBitWidth(RR: Reg[1]);
813 assert(W0 == 64 && W1 == 32);
814 RegisterCell RC = eSXT(rc(1).cat(RC: eIMM(V: 0, W: W1)), FromN: W1);
815 return rr0(RC, Outputs);
816 }
817 case A2_zxtb:
818 return rr0(eZXT(rc(1), FromN: 8), Outputs);
819 case A2_zxth:
820 return rr0(eZXT(rc(1), FromN: 16), Outputs);
821
822 // Saturations
823
824 case A2_satb:
825 return rr0(eSXT(A1: RegisterCell::self(Reg: 0, Width: W0).regify(R: Reg0), FromN: 8), Outputs);
826 case A2_sath:
827 return rr0(eSXT(A1: RegisterCell::self(Reg: 0, Width: W0).regify(R: Reg0), FromN: 16), Outputs);
828 case A2_satub:
829 return rr0(eZXT(A1: RegisterCell::self(Reg: 0, Width: W0).regify(R: Reg0), FromN: 8), Outputs);
830 case A2_satuh:
831 return rr0(eZXT(A1: RegisterCell::self(Reg: 0, Width: W0).regify(R: Reg0), FromN: 16), Outputs);
832
833 // Bit count:
834
835 case S2_cl0:
836 case S2_cl0p:
837 // Always produce a 32-bit result.
838 return rr0(eCLB(rc(1), B: false/*bit*/, W: 32), Outputs);
839 case S2_cl1:
840 case S2_cl1p:
841 return rr0(eCLB(rc(1), B: true/*bit*/, W: 32), Outputs);
842 case S2_clb:
843 case S2_clbp: {
844 uint16_t W1 = getRegBitWidth(RR: Reg[1]);
845 RegisterCell R1 = rc(1);
846 BT::BitValue TV = R1[W1-1];
847 if (TV.is(T: 0) || TV.is(T: 1))
848 return rr0(eCLB(A1: R1, B: TV, W: 32), Outputs);
849 break;
850 }
851 case S2_ct0:
852 case S2_ct0p:
853 return rr0(eCTB(rc(1), B: false/*bit*/, W: 32), Outputs);
854 case S2_ct1:
855 case S2_ct1p:
856 return rr0(eCTB(rc(1), B: true/*bit*/, W: 32), Outputs);
857 case S5_popcountp:
858 // TODO
859 break;
860
861 case C2_all8: {
862 RegisterCell P1 = rc(1);
863 bool Has0 = false, All1 = true;
864 for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
865 if (!P1[i].is(T: 1))
866 All1 = false;
867 if (!P1[i].is(T: 0))
868 continue;
869 Has0 = true;
870 break;
871 }
872 if (!Has0 && !All1)
873 break;
874 RegisterCell RC(W0);
875 RC.fill(B: 0, E: W0, V: (All1 ? BT::BitValue::One : BT::BitValue::Zero));
876 return rr0(RC, Outputs);
877 }
878 case C2_any8: {
879 RegisterCell P1 = rc(1);
880 bool Has1 = false, All0 = true;
881 for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
882 if (!P1[i].is(T: 0))
883 All0 = false;
884 if (!P1[i].is(T: 1))
885 continue;
886 Has1 = true;
887 break;
888 }
889 if (!Has1 && !All0)
890 break;
891 RegisterCell RC(W0);
892 RC.fill(B: 0, E: W0, V: (Has1 ? BT::BitValue::One : BT::BitValue::Zero));
893 return rr0(RC, Outputs);
894 }
895 case C2_and:
896 return rr0(eAND(rc(1), rc(2)), Outputs);
897 case C2_andn:
898 return rr0(eAND(rc(1), A2: eNOT(rc(2))), Outputs);
899 case C2_not:
900 return rr0(eNOT(rc(1)), Outputs);
901 case C2_or:
902 return rr0(eORL(rc(1), rc(2)), Outputs);
903 case C2_orn:
904 return rr0(eORL(rc(1), A2: eNOT(rc(2))), Outputs);
905 case C2_xor:
906 return rr0(eXOR(rc(1), rc(2)), Outputs);
907 case C4_and_and:
908 return rr0(eAND(rc(1), A2: eAND(rc(2), rc(3))), Outputs);
909 case C4_and_andn:
910 return rr0(eAND(rc(1), A2: eAND(rc(2), A2: eNOT(rc(3)))), Outputs);
911 case C4_and_or:
912 return rr0(eAND(rc(1), A2: eORL(rc(2), rc(3))), Outputs);
913 case C4_and_orn:
914 return rr0(eAND(rc(1), A2: eORL(rc(2), A2: eNOT(rc(3)))), Outputs);
915 case C4_or_and:
916 return rr0(eORL(rc(1), A2: eAND(rc(2), rc(3))), Outputs);
917 case C4_or_andn:
918 return rr0(eORL(rc(1), A2: eAND(rc(2), A2: eNOT(rc(3)))), Outputs);
919 case C4_or_or:
920 return rr0(eORL(rc(1), A2: eORL(rc(2), rc(3))), Outputs);
921 case C4_or_orn:
922 return rr0(eORL(rc(1), A2: eORL(rc(2), A2: eNOT(rc(3)))), Outputs);
923 case C2_bitsclr:
924 case C2_bitsclri:
925 case C2_bitsset:
926 case C4_nbitsclr:
927 case C4_nbitsclri:
928 case C4_nbitsset:
929 // TODO
930 break;
931 case S2_tstbit_i:
932 case S4_ntstbit_i: {
933 BT::BitValue V = rc(1)[im(2)];
934 if (V.is(T: 0) || V.is(T: 1)) {
935 // If instruction is S2_tstbit_i, test for 1, otherwise test for 0.
936 bool TV = (Opc == S2_tstbit_i);
937 BT::BitValue F = V.is(T: TV) ? BT::BitValue::One : BT::BitValue::Zero;
938 return rr0(RegisterCell(W0).fill(B: 0, E: W0, V: F), Outputs);
939 }
940 break;
941 }
942
943 default:
944 // For instructions that define a single predicate registers, store
945 // the low 8 bits of the register only.
946 if (unsigned DefR = getUniqueDefVReg(MI)) {
947 if (MRI.getRegClass(Reg: DefR) == &Hexagon::PredRegsRegClass) {
948 BT::RegisterRef PD(DefR, 0);
949 uint16_t RW = getRegBitWidth(RR: PD);
950 uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
951 RegisterCell RC = RegisterCell::self(Reg: DefR, Width: RW);
952 RC.fill(B: PW, E: RW, V: BT::BitValue::Zero);
953 putCell(RR: PD, RC, M&: Outputs);
954 return true;
955 }
956 }
957 return MachineEvaluator::evaluate(MI, Inputs, Outputs);
958 }
959 #undef im
960 #undef rc
961 #undef op
962 return false;
963}
964
965bool HexagonEvaluator::evaluate(const MachineInstr &BI,
966 const CellMapType &Inputs,
967 BranchTargetList &Targets,
968 bool &FallsThru) const {
969 // We need to evaluate one branch at a time. TII::analyzeBranch checks
970 // all the branches in a basic block at once, so we cannot use it.
971 unsigned Opc = BI.getOpcode();
972 bool SimpleBranch = false;
973 bool Negated = false;
974 switch (Opc) {
975 case Hexagon::J2_jumpf:
976 case Hexagon::J2_jumpfpt:
977 case Hexagon::J2_jumpfnew:
978 case Hexagon::J2_jumpfnewpt:
979 Negated = true;
980 [[fallthrough]];
981 case Hexagon::J2_jumpt:
982 case Hexagon::J2_jumptpt:
983 case Hexagon::J2_jumptnew:
984 case Hexagon::J2_jumptnewpt:
985 // Simple branch: if([!]Pn) jump ...
986 // i.e. Op0 = predicate, Op1 = branch target.
987 SimpleBranch = true;
988 break;
989 case Hexagon::J2_jump:
990 Targets.insert(X: BI.getOperand(i: 0).getMBB());
991 FallsThru = false;
992 return true;
993 default:
994 // If the branch is of unknown type, assume that all successors are
995 // executable.
996 return false;
997 }
998
999 if (!SimpleBranch)
1000 return false;
1001
1002 // BI is a conditional branch if we got here.
1003 RegisterRef PR = BI.getOperand(i: 0);
1004 RegisterCell PC = getCell(RR: PR, M: Inputs);
1005 const BT::BitValue &Test = PC[0];
1006
1007 // If the condition is neither true nor false, then it's unknown.
1008 if (!Test.is(T: 0) && !Test.is(T: 1))
1009 return false;
1010
1011 // "Test.is(!Negated)" means "branch condition is true".
1012 if (!Test.is(T: !Negated)) {
1013 // Condition known to be false.
1014 FallsThru = true;
1015 return true;
1016 }
1017
1018 Targets.insert(X: BI.getOperand(i: 1).getMBB());
1019 FallsThru = false;
1020 return true;
1021}
1022
1023unsigned HexagonEvaluator::getUniqueDefVReg(const MachineInstr &MI) const {
1024 unsigned DefReg = 0;
1025 for (const MachineOperand &Op : MI.operands()) {
1026 if (!Op.isReg() || !Op.isDef())
1027 continue;
1028 Register R = Op.getReg();
1029 if (!R.isVirtual())
1030 continue;
1031 if (DefReg != 0)
1032 return 0;
1033 DefReg = R;
1034 }
1035 return DefReg;
1036}
1037
1038bool HexagonEvaluator::evaluateLoad(const MachineInstr &MI,
1039 const CellMapType &Inputs,
1040 CellMapType &Outputs) const {
1041 using namespace Hexagon;
1042
1043 if (TII.isPredicated(MI))
1044 return false;
1045 assert(MI.mayLoad() && "A load that mayn't?");
1046 unsigned Opc = MI.getOpcode();
1047
1048 uint16_t BitNum;
1049 bool SignEx;
1050
1051 switch (Opc) {
1052 default:
1053 return false;
1054
1055#if 0
1056 // memb_fifo
1057 case L2_loadalignb_pbr:
1058 case L2_loadalignb_pcr:
1059 case L2_loadalignb_pi:
1060 // memh_fifo
1061 case L2_loadalignh_pbr:
1062 case L2_loadalignh_pcr:
1063 case L2_loadalignh_pi:
1064 // membh
1065 case L2_loadbsw2_pbr:
1066 case L2_loadbsw2_pci:
1067 case L2_loadbsw2_pcr:
1068 case L2_loadbsw2_pi:
1069 case L2_loadbsw4_pbr:
1070 case L2_loadbsw4_pci:
1071 case L2_loadbsw4_pcr:
1072 case L2_loadbsw4_pi:
1073 // memubh
1074 case L2_loadbzw2_pbr:
1075 case L2_loadbzw2_pci:
1076 case L2_loadbzw2_pcr:
1077 case L2_loadbzw2_pi:
1078 case L2_loadbzw4_pbr:
1079 case L2_loadbzw4_pci:
1080 case L2_loadbzw4_pcr:
1081 case L2_loadbzw4_pi:
1082#endif
1083
1084 case L2_loadrbgp:
1085 case L2_loadrb_io:
1086 case L2_loadrb_pbr:
1087 case L2_loadrb_pci:
1088 case L2_loadrb_pcr:
1089 case L2_loadrb_pi:
1090 case PS_loadrbabs:
1091 case L4_loadrb_ap:
1092 case L4_loadrb_rr:
1093 case L4_loadrb_ur:
1094 BitNum = 8;
1095 SignEx = true;
1096 break;
1097
1098 case L2_loadrubgp:
1099 case L2_loadrub_io:
1100 case L2_loadrub_pbr:
1101 case L2_loadrub_pci:
1102 case L2_loadrub_pcr:
1103 case L2_loadrub_pi:
1104 case PS_loadrubabs:
1105 case L4_loadrub_ap:
1106 case L4_loadrub_rr:
1107 case L4_loadrub_ur:
1108 BitNum = 8;
1109 SignEx = false;
1110 break;
1111
1112 case L2_loadrhgp:
1113 case L2_loadrh_io:
1114 case L2_loadrh_pbr:
1115 case L2_loadrh_pci:
1116 case L2_loadrh_pcr:
1117 case L2_loadrh_pi:
1118 case PS_loadrhabs:
1119 case L4_loadrh_ap:
1120 case L4_loadrh_rr:
1121 case L4_loadrh_ur:
1122 BitNum = 16;
1123 SignEx = true;
1124 break;
1125
1126 case L2_loadruhgp:
1127 case L2_loadruh_io:
1128 case L2_loadruh_pbr:
1129 case L2_loadruh_pci:
1130 case L2_loadruh_pcr:
1131 case L2_loadruh_pi:
1132 case L4_loadruh_rr:
1133 case PS_loadruhabs:
1134 case L4_loadruh_ap:
1135 case L4_loadruh_ur:
1136 BitNum = 16;
1137 SignEx = false;
1138 break;
1139
1140 case L2_loadrigp:
1141 case L2_loadri_io:
1142 case L2_loadri_pbr:
1143 case L2_loadri_pci:
1144 case L2_loadri_pcr:
1145 case L2_loadri_pi:
1146 case L2_loadw_locked:
1147 case PS_loadriabs:
1148 case L4_loadri_ap:
1149 case L4_loadri_rr:
1150 case L4_loadri_ur:
1151 case LDriw_pred:
1152 BitNum = 32;
1153 SignEx = true;
1154 break;
1155
1156 case L2_loadrdgp:
1157 case L2_loadrd_io:
1158 case L2_loadrd_pbr:
1159 case L2_loadrd_pci:
1160 case L2_loadrd_pcr:
1161 case L2_loadrd_pi:
1162 case L4_loadd_locked:
1163 case PS_loadrdabs:
1164 case L4_loadrd_ap:
1165 case L4_loadrd_rr:
1166 case L4_loadrd_ur:
1167 BitNum = 64;
1168 SignEx = true;
1169 break;
1170 }
1171
1172 const MachineOperand &MD = MI.getOperand(i: 0);
1173 assert(MD.isReg() && MD.isDef());
1174 RegisterRef RD = MD;
1175
1176 uint16_t W = getRegBitWidth(RR: RD);
1177 assert(W >= BitNum && BitNum > 0);
1178 RegisterCell Res(W);
1179
1180 for (uint16_t i = 0; i < BitNum; ++i)
1181 Res[i] = BT::BitValue::self(Self: BT::BitRef(RD.Reg, i));
1182
1183 if (SignEx) {
1184 const BT::BitValue &Sign = Res[BitNum-1];
1185 for (uint16_t i = BitNum; i < W; ++i)
1186 Res[i] = BT::BitValue::ref(V: Sign);
1187 } else {
1188 for (uint16_t i = BitNum; i < W; ++i)
1189 Res[i] = BT::BitValue::Zero;
1190 }
1191
1192 putCell(RR: RD, RC: Res, M&: Outputs);
1193 return true;
1194}
1195
1196bool HexagonEvaluator::evaluateFormalCopy(const MachineInstr &MI,
1197 const CellMapType &Inputs,
1198 CellMapType &Outputs) const {
1199 // If MI defines a formal parameter, but is not a copy (loads are handled
1200 // in evaluateLoad), then it's not clear what to do.
1201 assert(MI.isCopy());
1202
1203 RegisterRef RD = MI.getOperand(i: 0);
1204 RegisterRef RS = MI.getOperand(i: 1);
1205 assert(RD.Sub == 0);
1206 if (!RS.Reg.isPhysical())
1207 return false;
1208 RegExtMap::const_iterator F = VRX.find(Val: RD.Reg);
1209 if (F == VRX.end())
1210 return false;
1211
1212 uint16_t EW = F->second.Width;
1213 // Store RD's cell into the map. This will associate the cell with a virtual
1214 // register, and make zero-/sign-extends possible (otherwise we would be ex-
1215 // tending "self" bit values, which will have no effect, since "self" values
1216 // cannot be references to anything).
1217 putCell(RR: RD, RC: getCell(RR: RS, M: Inputs), M&: Outputs);
1218
1219 RegisterCell Res;
1220 // Read RD's cell from the outputs instead of RS's cell from the inputs:
1221 if (F->second.Type == ExtType::SExt)
1222 Res = eSXT(A1: getCell(RR: RD, M: Outputs), FromN: EW);
1223 else if (F->second.Type == ExtType::ZExt)
1224 Res = eZXT(A1: getCell(RR: RD, M: Outputs), FromN: EW);
1225
1226 putCell(RR: RD, RC: Res, M&: Outputs);
1227 return true;
1228}
1229
1230unsigned HexagonEvaluator::getNextPhysReg(unsigned PReg, unsigned Width) const {
1231 using namespace Hexagon;
1232
1233 bool Is64 = DoubleRegsRegClass.contains(Reg: PReg);
1234 assert(PReg == 0 || Is64 || IntRegsRegClass.contains(PReg));
1235
1236 static const unsigned Phys32[] = { R0, R1, R2, R3, R4, R5 };
1237 static const unsigned Phys64[] = { D0, D1, D2 };
1238 const unsigned Num32 = sizeof(Phys32)/sizeof(unsigned);
1239 const unsigned Num64 = sizeof(Phys64)/sizeof(unsigned);
1240
1241 // Return the first parameter register of the required width.
1242 if (PReg == 0)
1243 return (Width <= 32) ? Phys32[0] : Phys64[0];
1244
1245 // Set Idx32, Idx64 in such a way that Idx+1 would give the index of the
1246 // next register.
1247 unsigned Idx32 = 0, Idx64 = 0;
1248 if (!Is64) {
1249 while (Idx32 < Num32) {
1250 if (Phys32[Idx32] == PReg)
1251 break;
1252 Idx32++;
1253 }
1254 Idx64 = Idx32/2;
1255 } else {
1256 while (Idx64 < Num64) {
1257 if (Phys64[Idx64] == PReg)
1258 break;
1259 Idx64++;
1260 }
1261 Idx32 = Idx64*2+1;
1262 }
1263
1264 if (Width <= 32)
1265 return (Idx32+1 < Num32) ? Phys32[Idx32+1] : 0;
1266 return (Idx64+1 < Num64) ? Phys64[Idx64+1] : 0;
1267}
1268
1269unsigned HexagonEvaluator::getVirtRegFor(unsigned PReg) const {
1270 for (std::pair<MCRegister, Register> P : MRI.liveins())
1271 if (P.first == PReg)
1272 return P.second;
1273 return 0;
1274}
1275