1//===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implements the info about Hexagon target spec.
10//
11//===----------------------------------------------------------------------===//
12
13#include "HexagonTargetMachine.h"
14#include "Hexagon.h"
15#include "HexagonISelLowering.h"
16#include "HexagonLoopIdiomRecognition.h"
17#include "HexagonMachineFunctionInfo.h"
18#include "HexagonMachineScheduler.h"
19#include "HexagonTargetObjectFile.h"
20#include "HexagonTargetTransformInfo.h"
21#include "HexagonVectorLoopCarriedReuse.h"
22#include "TargetInfo/HexagonTargetInfo.h"
23#include "llvm/CodeGen/MIRParser/MIParser.h"
24#include "llvm/CodeGen/Passes.h"
25#include "llvm/CodeGen/TargetPassConfig.h"
26#include "llvm/CodeGen/VLIWMachineScheduler.h"
27#include "llvm/InitializePasses.h"
28#include "llvm/MC/TargetRegistry.h"
29#include "llvm/Passes/PassBuilder.h"
30#include "llvm/Support/CommandLine.h"
31#include "llvm/Support/Compiler.h"
32#include "llvm/Transforms/Scalar.h"
33#include <optional>
34
35using namespace llvm;
36
37static cl::opt<bool>
38 EnableCExtOpt("hexagon-cext", cl::Hidden, cl::init(Val: true),
39 cl::desc("Enable Hexagon constant-extender optimization"));
40
41static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::init(Val: true),
42 cl::desc("Enable RDF-based optimizations"));
43
44static cl::opt<bool> EnablePostRAHandleQFP(
45 "hexagon-handle-qfloat", cl::init(Val: true), cl::Hidden,
46 cl::desc("Fix up QFloat spills and reloads after register allocation"));
47
48cl::opt<unsigned> RDFFuncBlockLimit(
49 "rdf-bb-limit", cl::Hidden, cl::init(Val: 1000),
50 cl::desc("Basic block limit for a function for RDF optimizations"));
51
52static cl::opt<bool>
53 DisableHardwareLoops("disable-hexagon-hwloops", cl::Hidden,
54 cl::desc("Disable Hardware Loops for Hexagon target"));
55
56static cl::opt<bool> EnableMCR("hexagon-mcr", cl::Hidden, cl::init(Val: true),
57 cl::desc("Enable the machine combiner pass"));
58
59static cl::opt<bool>
60 DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden,
61 cl::desc("Disable Hexagon Addressing Mode Optimization"));
62
63static cl::opt<bool>
64 DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden,
65 cl::desc("Disable Hexagon CFG Optimization"));
66
67static cl::opt<bool>
68 DisableHCP("disable-hcp", cl::Hidden,
69 cl::desc("Disable Hexagon constant propagation"));
70
71static cl::opt<bool> DisableHexagonMask(
72 "disable-mask", cl::Hidden,
73 cl::desc("Disable Hexagon specific Mask generation pass"));
74
75static cl::opt<bool> DisableHexagonLiveVars(
76 "disable-hlv", cl::Hidden,
77 cl::desc("Disable Hexagon specific post-RA live-variable analysis"));
78static cl::opt<bool> DisableStoreWidening("disable-store-widen", cl::Hidden,
79 cl::init(Val: false),
80 cl::desc("Disable store widening"));
81
82static cl::opt<bool> DisableLoadWidening("disable-load-widen", cl::Hidden,
83 cl::desc("Disable load widening"));
84
85static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
86 cl::init(Val: true), cl::Hidden,
87 cl::desc("Early expansion of MUX"));
88
89static cl::opt<bool> EnableTfrCleanup("hexagon-tfr-cleanup", cl::init(Val: true),
90 cl::Hidden,
91 cl::desc("Cleanup of TFRs/COPYs"));
92
93static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(Val: true), cl::Hidden,
94 cl::desc("Enable early if-conversion"));
95
96static cl::opt<bool> EnableCopyHoist("hexagon-copy-hoist", cl::init(Val: true),
97 cl::Hidden,
98 cl::desc("Enable Hexagon copy hoisting"));
99
100static cl::opt<bool>
101 EnableGenInsert("hexagon-insert", cl::init(Val: true), cl::Hidden,
102 cl::desc("Generate \"insert\" instructions"));
103
104static cl::opt<bool>
105 EnableCommGEP("hexagon-commgep", cl::init(Val: true), cl::Hidden,
106 cl::desc("Enable commoning of GEP instructions"));
107
108static cl::opt<bool>
109 EnableGenExtract("hexagon-extract", cl::init(Val: true), cl::Hidden,
110 cl::desc("Generate \"extract\" instructions"));
111
112static cl::opt<bool> EnableGenMux(
113 "hexagon-mux", cl::init(Val: true), cl::Hidden,
114 cl::desc("Enable converting conditional transfers into MUX instructions"));
115
116static cl::opt<bool>
117 EnableGenPred("hexagon-gen-pred", cl::init(Val: true), cl::Hidden,
118 cl::desc("Enable conversion of arithmetic operations to "
119 "predicate instructions"));
120
121static cl::opt<bool>
122 EnableLoopPrefetch("hexagon-loop-prefetch", cl::Hidden,
123 cl::desc("Enable loop data prefetch on Hexagon"));
124
125static cl::opt<bool>
126 DisableHSDR("disable-hsdr", cl::init(Val: false), cl::Hidden,
127 cl::desc("Disable splitting double registers"));
128
129static cl::opt<bool>
130 EnableGenMemAbs("hexagon-mem-abs", cl::init(Val: true), cl::Hidden,
131 cl::desc("Generate absolute set instructions"));
132
133static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(Val: true),
134 cl::Hidden,
135 cl::desc("Bit simplification"));
136
137static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(Val: true),
138 cl::Hidden,
139 cl::desc("Loop rescheduling"));
140
141static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(Val: false), cl::Hidden,
142 cl::desc("Disable backend optimizations"));
143
144static cl::opt<bool>
145 EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden,
146 cl::desc("Enable Hexagon Vector print instr pass"));
147
148static cl::opt<bool>
149 EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::init(Val: true),
150 cl::desc("Enable vextract optimization"));
151
152static cl::opt<bool>
153 EnableVectorCombine("hexagon-vector-combine", cl::Hidden, cl::init(Val: true),
154 cl::desc("Enable HVX vector combining"));
155
156static cl::opt<bool> EnableInitialCFGCleanup(
157 "hexagon-initial-cfg-cleanup", cl::Hidden, cl::init(Val: true),
158 cl::desc("Simplify the CFG after atomic expansion pass"));
159
160static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
161 cl::init(Val: true),
162 cl::desc("Enable instsimplify"));
163
164cl::opt<QFloatMode> QFloatModeValue(
165 "hexagon-qfloat-mode", cl::desc("Specify the qfloat mode to operate on."),
166 cl::Hidden, cl::init(Val: QFloatMode::Legacy),
167 cl::values(
168 clEnumValN(QFloatMode::StrictIEEE, "strict-ieee",
169 "Enable code generation for qfloat strict IEEE-754 mode"),
170 clEnumValN(QFloatMode::IEEE, "ieee",
171 "Enable code generation for qfloat IEEE-754 mode"),
172 clEnumValN(QFloatMode::Lossy, "lossy",
173 "Enable code generation for qfloat lossy-subnormals mode"),
174 clEnumValN(QFloatMode::Legacy, "legacy",
175 "Enable code generation for qfloat legacy mode")));
176
177/// HexagonTargetMachineModule - Note that this is used on hosts that
178/// cannot link in a library unless there are references into the
179/// library. In particular, it seems that it is not possible to get
180/// things to work on Win32 without this. Though it is unused, do not
181/// remove it.
182extern "C" int HexagonTargetMachineModule;
183int HexagonTargetMachineModule = 0;
184
185static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
186 ScheduleDAGMILive *DAG = new VLIWMachineScheduler(
187 C, std::make_unique<HexagonConvergingVLIWScheduler>());
188 DAG->addMutation(Mutation: std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
189 DAG->addMutation(Mutation: std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
190 DAG->addMutation(Mutation: std::make_unique<HexagonSubtarget::CallMutation>());
191 DAG->addMutation(Mutation: createCopyConstrainDAGMutation(TII: DAG->TII, TRI: DAG->TRI));
192 return DAG;
193}
194
195static MachineSchedRegistry
196 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
197 createVLIWMachineSched);
198
199static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
200 return RM.value_or(u: Reloc::Static);
201}
202
203extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
204LLVMInitializeHexagonTarget() {
205 // Register the target.
206 RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
207
208 PassRegistry &PR = *PassRegistry::getPassRegistry();
209 initializeHexagonAsmPrinterPass(PR);
210 initializeHexagonBitSimplifyPass(PR);
211 initializeHexagonConstExtendersPass(PR);
212 initializeHexagonConstPropagationPass(PR);
213 initializeHexagonCopyToCombinePass(PR);
214 initializeHexagonEarlyIfConversionPass(PR);
215 initializeHexagonGenMemAbsolutePass(PR);
216 initializeHexagonGenMuxPass(PR);
217 initializeHexagonGlobalSchedulerPass(PR);
218 initializeHexagonLiveVariablesPass(PR);
219 initializeHexagonHardwareLoopsPass(PR);
220 initializeHexagonHVXSaveRemarkPass(PR);
221 initializeHexagonLoopIdiomRecognizeLegacyPassPass(PR);
222 initializeHexagonNewValueJumpPass(PR);
223 initializeHexagonOptAddrModePass(PR);
224 initializeHexagonPacketizerPass(PR);
225 initializeHexagonRDFOptPass(PR);
226 initializeHexagonSplitDoubleRegsPass(PR);
227 initializeHexagonVectorCombineLegacyPass(PR);
228 initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR);
229 initializeHexagonVExtractPass(PR);
230 initializeHexagonDAGToDAGISelLegacyPass(PR);
231 initializeHexagonLoopReschedulingPass(PR);
232 initializeHexagonBranchRelaxationPass(PR);
233 initializeHexagonCFGOptimizerPass(PR);
234 initializeHexagonCommonGEPPass(PR);
235 initializeHexagonCopyHoistingPass(PR);
236 initializeHexagonExpandCondsetsPass(PR);
237 initializeHexagonLoopAlignPass(PR);
238 initializeHexagonTfrCleanupPass(PR);
239 initializeHexagonFixupHwLoopsPass(PR);
240 initializeHexagonCallFrameInformationPass(PR);
241 initializeHexagonGenExtractPass(PR);
242 initializeHexagonGenInsertPass(PR);
243 initializeHexagonGenPredicatePass(PR);
244 initializeHexagonLoadWideningPass(PR);
245 initializeHexagonStoreWideningPass(PR);
246 initializeHexagonMaskPass(PR);
247 initializeHexagonOptimizeSZextendsPass(PR);
248 initializeHexagonPeepholePass(PR);
249 initializeHexagonSplitConst32AndConst64Pass(PR);
250 initializeHexagonVectorPrintPass(PR);
251 initializeHexagonQFPOptimizerPass(PR);
252 initializeHexagonXQFloatGeneratorPass(PR);
253 initializeHexagonPostRAHandleQFPPass(PR);
254 initializeMachineKCFILegacyPass(PR);
255}
256
257HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
258 StringRef CPU, StringRef FS,
259 const TargetOptions &Options,
260 std::optional<Reloc::Model> RM,
261 std::optional<CodeModel::Model> CM,
262 CodeGenOptLevel OL, bool JIT)
263 // Specify the vector alignment explicitly. For v512x1, the calculated
264 // alignment would be 512*alignment(i1), which is 512 bytes, instead of
265 // the required minimum of 64 bytes.
266 : CodeGenTargetMachineImpl(T, TT.computeDataLayout(), TT, CPU, FS, Options,
267 getEffectiveRelocModel(RM),
268 getEffectiveCodeModel(CM, Default: CodeModel::Small),
269 (HexagonNoOpt ? CodeGenOptLevel::None : OL)),
270 TLOF(std::make_unique<HexagonTargetObjectFile>()),
271 Subtarget(Triple(TT), CPU, FS, *this) {
272 initAsmInfo();
273}
274
275const HexagonSubtarget *
276HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
277 AttributeList FnAttrs = F.getAttributes();
278 Attribute CPUAttr = FnAttrs.getFnAttr(Kind: "target-cpu");
279 Attribute FSAttr = FnAttrs.getFnAttr(Kind: "target-features");
280
281 std::string CPU =
282 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
283 std::string FS =
284 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
285
286 auto &I = SubtargetMap[CPU + FS];
287 if (!I)
288 I = std::make_unique<HexagonSubtarget>(args: TargetTriple, args&: CPU, args&: FS, args: *this);
289 return I.get();
290}
291
292void HexagonTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
293#define GET_PASS_REGISTRY "HexagonPassRegistry.def"
294#include "llvm/Passes/TargetPassRegistry.inc"
295
296 PB.registerLateLoopOptimizationsEPCallback(
297 C: [=](LoopPassManager &LPM, OptimizationLevel Level) {
298 if (Level != OptimizationLevel::O0)
299 LPM.addPass(Pass: HexagonLoopIdiomRecognitionPass());
300 });
301 PB.registerLoopOptimizerEndEPCallback(
302 C: [=](LoopPassManager &LPM, OptimizationLevel Level) {
303 if (Level != OptimizationLevel::O0)
304 LPM.addPass(Pass: HexagonVectorLoopCarriedReusePass());
305 });
306}
307
308TargetTransformInfo
309HexagonTargetMachine::getTargetTransformInfo(const Function &F) const {
310 return TargetTransformInfo(std::make_unique<HexagonTTIImpl>(args: this, args: F));
311}
312
313MachineFunctionInfo *HexagonTargetMachine::createMachineFunctionInfo(
314 BumpPtrAllocator &Allocator, const Function &F,
315 const TargetSubtargetInfo *STI) const {
316 return HexagonMachineFunctionInfo::create<HexagonMachineFunctionInfo>(
317 Allocator, F, STI);
318}
319
320yaml::MachineFunctionInfo *
321HexagonTargetMachine::createDefaultFuncInfoYAML() const {
322 return new yaml::HexagonFunctionInfo();
323}
324
325yaml::MachineFunctionInfo *
326HexagonTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
327 const auto *MFI = MF.getInfo<HexagonMachineFunctionInfo>();
328 const auto &TRI = *MF.getSubtarget().getRegisterInfo();
329 return new yaml::HexagonFunctionInfo(*MFI, TRI);
330}
331
332bool HexagonTargetMachine::parseMachineFunctionInfo(
333 const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
334 SMDiagnostic &Error, SMRange &SourceRange) const {
335 const auto &YamlMFI = static_cast<const yaml::HexagonFunctionInfo &>(MFI_);
336 MachineFunction &MF = PFS.MF;
337 HexagonMachineFunctionInfo *MFI = MF.getInfo<HexagonMachineFunctionInfo>();
338
339 MFI->initializeBaseYamlFields(YamlMFI);
340
341 // Parse StackAlignBaseReg register name
342 if (!YamlMFI.StackAlignBaseReg.Value.empty()) {
343 Register Reg;
344 if (parseNamedRegisterReference(PFS, Reg, Src: YamlMFI.StackAlignBaseReg.Value,
345 Error)) {
346 SourceRange = YamlMFI.StackAlignBaseReg.SourceRange;
347 return true;
348 }
349 MFI->setStackAlignBaseReg(Reg);
350 }
351
352 return false;
353}
354
355HexagonTargetMachine::~HexagonTargetMachine() = default;
356
357ScheduleDAGInstrs *
358HexagonTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
359 return createVLIWMachineSched(C);
360}
361
362namespace {
363/// Hexagon Code Generator Pass Configuration Options.
364class HexagonPassConfig : public TargetPassConfig {
365public:
366 HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
367 : TargetPassConfig(TM, PM) {}
368
369 HexagonTargetMachine &getHexagonTargetMachine() const {
370 return getTM<HexagonTargetMachine>();
371 }
372
373 void addIRPasses() override;
374 bool addInstSelector() override;
375 bool addILPOpts() override;
376 void addPreRegAlloc() override;
377 void addPostRegAlloc() override;
378 void addPreSched2() override;
379 void addPreEmitPass() override;
380};
381} // namespace
382
383TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
384 return new HexagonPassConfig(*this, PM);
385}
386
387void HexagonPassConfig::addIRPasses() {
388 TargetPassConfig::addIRPasses();
389 bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
390
391 if (!NoOpt) {
392 if (EnableInstSimplify)
393 addPass(P: createInstSimplifyLegacyPass());
394 addPass(P: createDeadCodeEliminationPass());
395 }
396
397 addPass(P: createAtomicExpandLegacyPass());
398
399 if (!NoOpt) {
400 if (EnableInitialCFGCleanup)
401 addPass(P: createCFGSimplificationPass(Options: SimplifyCFGOptions()
402 .forwardSwitchCondToPhi(B: true)
403 .convertSwitchRangeToICmp(B: true)
404 .convertSwitchToLookupTable(B: true)
405 .needCanonicalLoops(B: false)
406 .hoistCommonInsts(B: true)
407 .sinkCommonInsts(B: true)));
408 if (EnableLoopPrefetch)
409 addPass(P: createLoopDataPrefetchPass());
410 if (EnableVectorCombine)
411 addPass(P: createHexagonVectorCombineLegacyPass());
412 if (EnableCommGEP)
413 addPass(P: createHexagonCommonGEP());
414 // Replace certain combinations of shifts and ands with extracts.
415 if (EnableGenExtract)
416 addPass(P: createHexagonGenExtract());
417 }
418}
419
420bool HexagonPassConfig::addInstSelector() {
421 HexagonTargetMachine &TM = getHexagonTargetMachine();
422 const HexagonSubtarget *HST = TM.getHexagonSubtarget();
423 bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
424
425 if (!NoOpt)
426 addPass(P: createHexagonOptimizeSZextends());
427
428 addPass(P: createHexagonISelDag(TM, OptLevel: getOptLevel()));
429 // Run the QFloat mode code generation pass only if v79 or greater.
430 // Do not run this pass, if legacy mode is passed on command line.
431 if (HST->useHVXV79Ops() && (QFloatModeValue != QFloatMode::Legacy))
432 addPass(P: createHexagonXQFloatGenerator());
433
434 if (!NoOpt) {
435 if (EnableVExtractOpt)
436 addPass(P: createHexagonVExtract());
437 // Create logical operations on predicate registers.
438 if (EnableGenPred)
439 addPass(P: createHexagonGenPredicate());
440 // Rotate loops to expose bit-simplification opportunities.
441 if (EnableLoopResched)
442 addPass(P: createHexagonLoopRescheduling());
443 // Split double registers.
444 if (!DisableHSDR)
445 addPass(P: createHexagonSplitDoubleRegs());
446 // Bit simplification.
447 if (EnableBitSimplify)
448 addPass(P: createHexagonBitSimplify());
449 addPass(P: createHexagonPeephole());
450 // Constant propagation.
451 if (!DisableHCP) {
452 addPass(P: createHexagonConstPropagationPass());
453 addPass(PassID: &UnreachableMachineBlockElimID);
454 }
455 if (EnableGenInsert)
456 addPass(P: createHexagonGenInsert());
457 if (EnableEarlyIf)
458 addPass(P: createHexagonEarlyIfConversion());
459 // For v75 or below, or if legacy mode is requested, run QFPOptizer pass
460 // to preserve backward compatibility.
461 if (!HST->useHVXV79Ops() || (QFloatModeValue == QFloatMode::Legacy))
462 addPass(P: createHexagonQFPOptimizer());
463 }
464
465 return false;
466}
467
468bool HexagonPassConfig::addILPOpts() {
469 if (EnableMCR)
470 addPass(PassID: &MachineCombinerID);
471
472 return true;
473}
474
475void HexagonPassConfig::addPreRegAlloc() {
476 if (getOptLevel() != CodeGenOptLevel::None) {
477 if (EnableCExtOpt)
478 addPass(P: createHexagonConstExtenders());
479 if (EnableExpandCondsets)
480 insertPass(TargetPassID: &RegisterCoalescerID, InsertedPassID: &HexagonExpandCondsetsID);
481 if (EnableCopyHoist)
482 insertPass(TargetPassID: &RegisterCoalescerID, InsertedPassID: &HexagonCopyHoistingID);
483 if (EnableTfrCleanup)
484 insertPass(TargetPassID: &VirtRegRewriterID, InsertedPassID: &HexagonTfrCleanupID);
485 if (!DisableStoreWidening)
486 addPass(P: createHexagonStoreWidening());
487 if (!DisableLoadWidening)
488 addPass(P: createHexagonLoadWidening());
489 if (EnableGenMemAbs)
490 addPass(P: createHexagonGenMemAbsolute());
491 if (!DisableHardwareLoops)
492 addPass(P: createHexagonHardwareLoops());
493 }
494 if (TM->getOptLevel() >= CodeGenOptLevel::Default)
495 addPass(PassID: &MachinePipelinerID);
496 addPass(P: createHexagonHVXSaveRemark());
497}
498
499void HexagonPassConfig::addPostRegAlloc() {
500 HexagonTargetMachine &HTM = getHexagonTargetMachine();
501 const HexagonSubtarget *HST = HTM.getHexagonSubtarget();
502 // Run PostRAQFP on v79 and above.
503 if (EnablePostRAHandleQFP && HST->useHVXV79Ops())
504 addPass(P: createHexagonPostRAHandleQFP());
505
506 if (getOptLevel() != CodeGenOptLevel::None) {
507 if (EnableRDFOpt)
508 addPass(P: createHexagonRDFOpt());
509 if (!DisableHexagonCFGOpt)
510 addPass(P: createHexagonCFGOptimizer());
511 if (!DisableAModeOpt)
512 addPass(P: createHexagonOptAddrMode());
513 }
514}
515
516void HexagonPassConfig::addPreSched2() {
517 bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
518 addPass(P: createHexagonCopyToCombine());
519 if (getOptLevel() != CodeGenOptLevel::None)
520 addPass(PassID: &IfConverterID);
521 addPass(P: createHexagonSplitConst32AndConst64());
522 if (!NoOpt && !DisableHexagonMask)
523 addPass(P: createHexagonMask());
524
525 if (!NoOpt && !DisableHexagonLiveVars) {
526 addPass(PassID: &HexagonLiveVariablesID);
527 }
528}
529
530void HexagonPassConfig::addPreEmitPass() {
531 bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
532
533 if (!NoOpt)
534 addPass(P: createHexagonNewValueJump());
535
536 addPass(P: createHexagonBranchRelaxation());
537
538 if (!NoOpt) {
539 if (!DisableHardwareLoops)
540 addPass(P: createHexagonFixupHwLoops());
541 // Generate MUX from pairs of conditional transfers.
542 if (EnableGenMux)
543 addPass(P: createHexagonGenMux());
544 if (!DisableHexagonLiveVars)
545 addPass(PassID: &HexagonLiveVariablesID);
546 }
547
548 // Emit KCFI checks for indirect calls. Must run before packetization so
549 // the check and call can be bundled together into a VLIW packet.
550 addPass(P: createKCFIPass());
551
552 // Packetization is mandatory: it handles gather/scatter at all opt levels.
553 addPass(P: createHexagonPacketizer(Minimal: NoOpt));
554
555 if (!NoOpt) {
556 // Global pull-up scheduler
557 addPass(P: createHexagonGlobalScheduler());
558
559 addPass(P: createHexagonLoopAlign());
560 }
561
562 if (EnableVectorPrint)
563 addPass(P: createHexagonVectorPrint());
564
565 // Add CFI instructions if necessary.
566 addPass(P: createHexagonCallFrameInformation());
567}
568