1//===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implements the info about Hexagon target spec.
10//
11//===----------------------------------------------------------------------===//
12
13#include "HexagonTargetMachine.h"
14#include "Hexagon.h"
15#include "HexagonISelLowering.h"
16#include "HexagonLoopIdiomRecognition.h"
17#include "HexagonMachineFunctionInfo.h"
18#include "HexagonMachineScheduler.h"
19#include "HexagonTargetObjectFile.h"
20#include "HexagonTargetTransformInfo.h"
21#include "HexagonVectorLoopCarriedReuse.h"
22#include "TargetInfo/HexagonTargetInfo.h"
23#include "llvm/CodeGen/MIRParser/MIParser.h"
24#include "llvm/CodeGen/Passes.h"
25#include "llvm/CodeGen/TargetPassConfig.h"
26#include "llvm/CodeGen/VLIWMachineScheduler.h"
27#include "llvm/InitializePasses.h"
28#include "llvm/MC/TargetRegistry.h"
29#include "llvm/Passes/PassBuilder.h"
30#include "llvm/Support/CommandLine.h"
31#include "llvm/Support/Compiler.h"
32#include "llvm/Transforms/Scalar.h"
33#include <optional>
34
35using namespace llvm;
36
37static cl::opt<bool>
38 EnableCExtOpt("hexagon-cext", cl::Hidden, cl::init(Val: true),
39 cl::desc("Enable Hexagon constant-extender optimization"));
40
41static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::init(Val: true),
42 cl::desc("Enable RDF-based optimizations"));
43
44static cl::opt<bool> EnablePostRAHandleQFP(
45 "hexagon-handle-qfloat", cl::init(Val: true), cl::Hidden,
46 cl::desc("Fix up QFloat spills and reloads after register allocation"));
47
48cl::opt<unsigned> RDFFuncBlockLimit(
49 "rdf-bb-limit", cl::Hidden, cl::init(Val: 1000),
50 cl::desc("Basic block limit for a function for RDF optimizations"));
51
52static cl::opt<bool>
53 DisableHardwareLoops("disable-hexagon-hwloops", cl::Hidden,
54 cl::desc("Disable Hardware Loops for Hexagon target"));
55
56static cl::opt<bool> EnableMCR("hexagon-mcr", cl::Hidden, cl::init(Val: true),
57 cl::desc("Enable the machine combiner pass"));
58
59static cl::opt<bool>
60 DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden,
61 cl::desc("Disable Hexagon Addressing Mode Optimization"));
62
63static cl::opt<bool>
64 DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden,
65 cl::desc("Disable Hexagon CFG Optimization"));
66
67static cl::opt<bool>
68 DisableHCP("disable-hcp", cl::Hidden,
69 cl::desc("Disable Hexagon constant propagation"));
70
71static cl::opt<bool> DisableHexagonMask(
72 "disable-mask", cl::Hidden,
73 cl::desc("Disable Hexagon specific Mask generation pass"));
74
75static cl::opt<bool> DisableHexagonLiveVars(
76 "disable-hlv", cl::Hidden,
77 cl::desc("Disable Hexagon specific post-RA live-variable analysis"));
78static cl::opt<bool> DisableStoreWidening("disable-store-widen", cl::Hidden,
79 cl::init(Val: false),
80 cl::desc("Disable store widening"));
81
82static cl::opt<bool> DisableLoadWidening("disable-load-widen", cl::Hidden,
83 cl::desc("Disable load widening"));
84
85static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
86 cl::init(Val: true), cl::Hidden,
87 cl::desc("Early expansion of MUX"));
88
89static cl::opt<bool> EnableTfrCleanup("hexagon-tfr-cleanup", cl::init(Val: true),
90 cl::Hidden,
91 cl::desc("Cleanup of TFRs/COPYs"));
92
93static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(Val: true), cl::Hidden,
94 cl::desc("Enable early if-conversion"));
95
96static cl::opt<bool> EnableCopyHoist("hexagon-copy-hoist", cl::init(Val: true),
97 cl::Hidden,
98 cl::desc("Enable Hexagon copy hoisting"));
99
100static cl::opt<bool>
101 EnableGenInsert("hexagon-insert", cl::init(Val: true), cl::Hidden,
102 cl::desc("Generate \"insert\" instructions"));
103
104static cl::opt<bool>
105 EnableCommGEP("hexagon-commgep", cl::init(Val: true), cl::Hidden,
106 cl::desc("Enable commoning of GEP instructions"));
107
108static cl::opt<bool>
109 EnableGenExtract("hexagon-extract", cl::init(Val: true), cl::Hidden,
110 cl::desc("Generate \"extract\" instructions"));
111
112static cl::opt<bool> EnableGenMux(
113 "hexagon-mux", cl::init(Val: true), cl::Hidden,
114 cl::desc("Enable converting conditional transfers into MUX instructions"));
115
116static cl::opt<bool>
117 EnableGenPred("hexagon-gen-pred", cl::init(Val: true), cl::Hidden,
118 cl::desc("Enable conversion of arithmetic operations to "
119 "predicate instructions"));
120
121static cl::opt<bool>
122 EnableLoopPrefetch("hexagon-loop-prefetch", cl::Hidden,
123 cl::desc("Enable loop data prefetch on Hexagon"));
124
125static cl::opt<bool>
126 DisableHSDR("disable-hsdr", cl::init(Val: false), cl::Hidden,
127 cl::desc("Disable splitting double registers"));
128
129static cl::opt<bool>
130 EnableGenMemAbs("hexagon-mem-abs", cl::init(Val: true), cl::Hidden,
131 cl::desc("Generate absolute set instructions"));
132
133static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(Val: true),
134 cl::Hidden,
135 cl::desc("Bit simplification"));
136
137static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(Val: true),
138 cl::Hidden,
139 cl::desc("Loop rescheduling"));
140
141static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(Val: false), cl::Hidden,
142 cl::desc("Disable backend optimizations"));
143
144static cl::opt<bool>
145 EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden,
146 cl::desc("Enable Hexagon Vector print instr pass"));
147
148static cl::opt<bool>
149 EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::init(Val: true),
150 cl::desc("Enable vextract optimization"));
151
152static cl::opt<bool>
153 EnableVectorCombine("hexagon-vector-combine", cl::Hidden, cl::init(Val: true),
154 cl::desc("Enable HVX vector combining"));
155
156static cl::opt<bool> EnableInitialCFGCleanup(
157 "hexagon-initial-cfg-cleanup", cl::Hidden, cl::init(Val: true),
158 cl::desc("Simplify the CFG after atomic expansion pass"));
159
160static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
161 cl::init(Val: true),
162 cl::desc("Enable instsimplify"));
163
164cl::opt<QFloatMode> QFloatModeValue(
165 "hexagon-qfloat-mode", cl::desc("Specify the qfloat mode to operate on."),
166 cl::Hidden, cl::init(Val: QFloatMode::Legacy),
167 cl::values(
168 clEnumValN(QFloatMode::StrictIEEE, "strict-ieee",
169 "Enable code generation for qfloat strict IEEE-754 mode"),
170 clEnumValN(QFloatMode::IEEE, "ieee",
171 "Enable code generation for qfloat IEEE-754 mode"),
172 clEnumValN(QFloatMode::Lossy, "lossy",
173 "Enable code generation for qfloat lossy-subnormals mode"),
174 clEnumValN(QFloatMode::Legacy, "legacy",
175 "Enable code generation for qfloat legacy mode")));
176
177/// HexagonTargetMachineModule - Note that this is used on hosts that
178/// cannot link in a library unless there are references into the
179/// library. In particular, it seems that it is not possible to get
180/// things to work on Win32 without this. Though it is unused, do not
181/// remove it.
182extern "C" int HexagonTargetMachineModule;
183int HexagonTargetMachineModule = 0;
184
185static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
186 ScheduleDAGMILive *DAG = new VLIWMachineScheduler(
187 C, std::make_unique<HexagonConvergingVLIWScheduler>());
188 DAG->addMutation(Mutation: std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
189 DAG->addMutation(Mutation: std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
190 DAG->addMutation(Mutation: std::make_unique<HexagonSubtarget::CallMutation>());
191 DAG->addMutation(Mutation: createCopyConstrainDAGMutation(TII: DAG->TII));
192 return DAG;
193}
194
195static MachineSchedRegistry
196 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
197 createVLIWMachineSched);
198
199static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
200 return RM.value_or(u: Reloc::Static);
201}
202
203extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
204LLVMInitializeHexagonTarget() {
205 // Register the target.
206 RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
207
208 PassRegistry &PR = *PassRegistry::getPassRegistry();
209 initializeHexagonAlignGlobalArraysPass(PR);
210 initializeHexagonAsmPrinterPass(PR);
211 initializeHexagonBitSimplifyPass(PR);
212 initializeHexagonConstExtendersPass(PR);
213 initializeHexagonConstPropagationPass(PR);
214 initializeHexagonCopyToCombinePass(PR);
215 initializeHexagonEarlyIfConversionPass(PR);
216 initializeHexagonGenMemAbsolutePass(PR);
217 initializeHexagonGenMuxPass(PR);
218 initializeHexagonGlobalSchedulerPass(PR);
219 initializeHexagonLiveVariablesPass(PR);
220 initializeHexagonHardwareLoopsPass(PR);
221 initializeHexagonHVXSaveRemarkPass(PR);
222 initializeHexagonLoopIdiomRecognizeLegacyPassPass(PR);
223 initializeHexagonNewValueJumpPass(PR);
224 initializeHexagonOptAddrModePass(PR);
225 initializeHexagonPacketizerPass(PR);
226 initializeHexagonRDFOptPass(PR);
227 initializeHexagonSplitDoubleRegsPass(PR);
228 initializeHexagonVectorCombineLegacyPass(PR);
229 initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR);
230 initializeHexagonVExtractPass(PR);
231 initializeHexagonDAGToDAGISelLegacyPass(PR);
232 initializeHexagonLoopReschedulingPass(PR);
233 initializeHexagonBranchRelaxationPass(PR);
234 initializeHexagonCFGOptimizerPass(PR);
235 initializeHexagonCommonGEPPass(PR);
236 initializeHexagonCopyHoistingPass(PR);
237 initializeHexagonExpandCondsetsPass(PR);
238 initializeHexagonLoopAlignPass(PR);
239 initializeHexagonTfrCleanupPass(PR);
240 initializeHexagonFixupHwLoopsPass(PR);
241 initializeHexagonCallFrameInformationPass(PR);
242 initializeHexagonGenExtractPass(PR);
243 initializeHexagonGenInsertPass(PR);
244 initializeHexagonGenPredicatePass(PR);
245 initializeHexagonLoadWideningPass(PR);
246 initializeHexagonStoreWideningPass(PR);
247 initializeHexagonMaskPass(PR);
248 initializeHexagonOptimizeSZextendsPass(PR);
249 initializeHexagonPeepholePass(PR);
250 initializeHexagonSplitConst32AndConst64Pass(PR);
251 initializeHexagonVectorPrintPass(PR);
252 initializeHexagonQFPOptimizerPass(PR);
253 initializeHexagonXQFloatGeneratorPass(PR);
254 initializeHexagonPostRAHandleQFPPass(PR);
255 initializeMachineKCFILegacyPass(PR);
256}
257
258HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
259 StringRef CPU, StringRef FS,
260 const TargetOptions &Options,
261 std::optional<Reloc::Model> RM,
262 std::optional<CodeModel::Model> CM,
263 CodeGenOptLevel OL, bool JIT)
264 : CodeGenTargetMachineImpl(T, TT, CPU, FS, Options,
265 getEffectiveRelocModel(RM),
266 getEffectiveCodeModel(CM, Default: CodeModel::Small),
267 (HexagonNoOpt ? CodeGenOptLevel::None : OL)),
268 TLOF(std::make_unique<HexagonTargetObjectFile>()),
269 Subtarget(Triple(TT), CPU, FS, *this) {
270 initAsmInfo();
271}
272
273const HexagonSubtarget *
274HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
275 AttributeList FnAttrs = F.getAttributes();
276 Attribute CPUAttr = FnAttrs.getFnAttr(Kind: "target-cpu");
277 Attribute FSAttr = FnAttrs.getFnAttr(Kind: "target-features");
278
279 std::string CPU =
280 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
281 std::string FS =
282 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
283
284 auto &I = SubtargetMap[CPU + FS];
285 if (!I)
286 I = std::make_unique<HexagonSubtarget>(args: TargetTriple, args&: CPU, args&: FS, args: *this);
287 return I.get();
288}
289
290void HexagonTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
291#define GET_PASS_REGISTRY "HexagonPassRegistry.def"
292#include "llvm/Passes/TargetPassRegistry.inc"
293
294 PB.registerLateLoopOptimizationsEPCallback(
295 C: [=](LoopPassManager &LPM, OptimizationLevel Level) {
296 if (Level != OptimizationLevel::O0)
297 LPM.addPass(Pass: HexagonLoopIdiomRecognitionPass());
298 });
299 PB.registerLoopOptimizerEndEPCallback(
300 C: [=](LoopPassManager &LPM, OptimizationLevel Level) {
301 if (Level != OptimizationLevel::O0)
302 LPM.addPass(Pass: HexagonVectorLoopCarriedReusePass());
303 });
304}
305
306TargetTransformInfo
307HexagonTargetMachine::getTargetTransformInfo(const Function &F) const {
308 return TargetTransformInfo(std::make_unique<HexagonTTIImpl>(args: this, args: F));
309}
310
311MachineFunctionInfo *HexagonTargetMachine::createMachineFunctionInfo(
312 BumpPtrAllocator &Allocator, const Function &F,
313 const TargetSubtargetInfo *STI) const {
314 return HexagonMachineFunctionInfo::create<HexagonMachineFunctionInfo>(
315 Allocator, F, STI);
316}
317
318yaml::MachineFunctionInfo *
319HexagonTargetMachine::createDefaultFuncInfoYAML() const {
320 return new yaml::HexagonFunctionInfo();
321}
322
323yaml::MachineFunctionInfo *
324HexagonTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
325 const auto *MFI = MF.getInfo<HexagonMachineFunctionInfo>();
326 const auto &TRI = *MF.getSubtarget().getRegisterInfo();
327 return new yaml::HexagonFunctionInfo(*MFI, TRI);
328}
329
330bool HexagonTargetMachine::parseMachineFunctionInfo(
331 const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
332 SMDiagnostic &Error, SMRange &SourceRange) const {
333 const auto &YamlMFI = static_cast<const yaml::HexagonFunctionInfo &>(MFI_);
334 MachineFunction &MF = PFS.MF;
335 HexagonMachineFunctionInfo *MFI = MF.getInfo<HexagonMachineFunctionInfo>();
336
337 MFI->initializeBaseYamlFields(YamlMFI);
338
339 // Parse StackAlignBaseReg register name
340 if (!YamlMFI.StackAlignBaseReg.Value.empty()) {
341 Register Reg;
342 if (parseNamedRegisterReference(PFS, Reg, Src: YamlMFI.StackAlignBaseReg.Value,
343 Error)) {
344 SourceRange = YamlMFI.StackAlignBaseReg.SourceRange;
345 return true;
346 }
347 MFI->setStackAlignBaseReg(Reg);
348 }
349
350 return false;
351}
352
353HexagonTargetMachine::~HexagonTargetMachine() = default;
354
355ScheduleDAGInstrs *
356HexagonTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
357 return createVLIWMachineSched(C);
358}
359
360namespace {
361/// Hexagon Code Generator Pass Configuration Options.
362class HexagonPassConfig : public TargetPassConfig {
363public:
364 HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
365 : TargetPassConfig(TM, PM) {}
366
367 HexagonTargetMachine &getHexagonTargetMachine() const {
368 return getTM<HexagonTargetMachine>();
369 }
370
371 void addIRPasses() override;
372 bool addInstSelector() override;
373 bool addILPOpts() override;
374 void addPreRegAlloc() override;
375 void addPostRegAlloc() override;
376 void addPreSched2() override;
377 void addPreEmitPass() override;
378};
379} // namespace
380
381TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
382 return new HexagonPassConfig(*this, PM);
383}
384
385void HexagonPassConfig::addIRPasses() {
386 TargetPassConfig::addIRPasses();
387 bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
388
389 if (!NoOpt) {
390 // Raise the alignment of global integer arrays to 8 bytes. At -O1/-O2,
391 // reduce .rodata size by keeping byte/half-word arrays at their natural
392 // alignment; apply full 8-byte alignment at -O3.
393 addPass(P: createHexagonAlignGlobalArrays(ReduceRodataSize: getOptLevel() !=
394 CodeGenOptLevel::Aggressive));
395 if (EnableInstSimplify)
396 addPass(P: createInstSimplifyLegacyPass());
397 addPass(P: createDeadCodeEliminationPass());
398 }
399
400 addPass(P: createAtomicExpandLegacyPass());
401
402 if (!NoOpt) {
403 if (EnableInitialCFGCleanup)
404 addPass(P: createCFGSimplificationPass(Options: SimplifyCFGOptions()
405 .forwardSwitchCondToPhi(B: true)
406 .convertSwitchRangeToICmp(B: true)
407 .convertSwitchToLookupTable(B: true)
408 .needCanonicalLoops(B: false)
409 .hoistCommonInsts(B: true)
410 .sinkCommonInsts(B: true)));
411 if (EnableLoopPrefetch)
412 addPass(P: createLoopDataPrefetchPass());
413 if (EnableVectorCombine)
414 addPass(P: createHexagonVectorCombineLegacyPass());
415 if (EnableCommGEP)
416 addPass(P: createHexagonCommonGEP());
417 // Replace certain combinations of shifts and ands with extracts.
418 if (EnableGenExtract)
419 addPass(P: createHexagonGenExtract());
420 }
421}
422
423bool HexagonPassConfig::addInstSelector() {
424 HexagonTargetMachine &TM = getHexagonTargetMachine();
425 const HexagonSubtarget *HST = TM.getHexagonSubtarget();
426 bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
427
428 if (!NoOpt)
429 addPass(P: createHexagonOptimizeSZextends());
430
431 addPass(P: createHexagonISelDag(TM, OptLevel: getOptLevel()));
432 // Run the QFloat mode code generation pass only if v79 or greater.
433 // Do not run this pass, if legacy mode is passed on command line.
434 if (HST->useHVXV79Ops() && (QFloatModeValue != QFloatMode::Legacy))
435 addPass(P: createHexagonXQFloatGenerator());
436
437 if (!NoOpt) {
438 if (EnableVExtractOpt)
439 addPass(P: createHexagonVExtract());
440 // Create logical operations on predicate registers.
441 if (EnableGenPred)
442 addPass(P: createHexagonGenPredicate());
443 // Rotate loops to expose bit-simplification opportunities.
444 if (EnableLoopResched)
445 addPass(P: createHexagonLoopRescheduling());
446 // Split double registers.
447 if (!DisableHSDR)
448 addPass(P: createHexagonSplitDoubleRegs());
449 // Bit simplification.
450 if (EnableBitSimplify)
451 addPass(P: createHexagonBitSimplify());
452 addPass(P: createHexagonPeephole());
453 // Constant propagation.
454 if (!DisableHCP) {
455 addPass(P: createHexagonConstPropagationPass());
456 addPass(PassID: &UnreachableMachineBlockElimID);
457 }
458 if (EnableGenInsert)
459 addPass(P: createHexagonGenInsert());
460 if (EnableEarlyIf)
461 addPass(P: createHexagonEarlyIfConversion());
462 // For v75 or below, or if legacy mode is requested, run QFPOptizer pass
463 // to preserve backward compatibility.
464 if (!HST->useHVXV79Ops() || (QFloatModeValue == QFloatMode::Legacy))
465 addPass(P: createHexagonQFPOptimizer());
466 }
467
468 return false;
469}
470
471bool HexagonPassConfig::addILPOpts() {
472 if (EnableMCR)
473 addPass(PassID: &MachineCombinerID);
474
475 return true;
476}
477
478void HexagonPassConfig::addPreRegAlloc() {
479 if (getOptLevel() != CodeGenOptLevel::None) {
480 if (EnableCExtOpt)
481 addPass(P: createHexagonConstExtenders());
482 if (EnableExpandCondsets)
483 insertPass(TargetPassID: &RegisterCoalescerID, InsertedPassID: &HexagonExpandCondsetsID);
484 if (EnableCopyHoist)
485 insertPass(TargetPassID: &RegisterCoalescerID, InsertedPassID: &HexagonCopyHoistingID);
486 if (EnableTfrCleanup)
487 insertPass(TargetPassID: &VirtRegRewriterID, InsertedPassID: &HexagonTfrCleanupID);
488 if (!DisableStoreWidening)
489 addPass(P: createHexagonStoreWidening());
490 if (!DisableLoadWidening)
491 addPass(P: createHexagonLoadWidening());
492 if (EnableGenMemAbs)
493 addPass(P: createHexagonGenMemAbsolute());
494 if (!DisableHardwareLoops)
495 addPass(P: createHexagonHardwareLoops());
496 }
497 if (TM->getOptLevel() >= CodeGenOptLevel::Default)
498 addPass(PassID: &MachinePipelinerID);
499 addPass(P: createHexagonHVXSaveRemark());
500}
501
502void HexagonPassConfig::addPostRegAlloc() {
503 HexagonTargetMachine &HTM = getHexagonTargetMachine();
504 const HexagonSubtarget *HST = HTM.getHexagonSubtarget();
505 // Run PostRAQFP on v79 and above.
506 if (EnablePostRAHandleQFP && HST->useHVXV79Ops())
507 addPass(P: createHexagonPostRAHandleQFP());
508
509 if (getOptLevel() != CodeGenOptLevel::None) {
510 if (EnableRDFOpt)
511 addPass(P: createHexagonRDFOpt());
512 if (!DisableHexagonCFGOpt)
513 addPass(P: createHexagonCFGOptimizer());
514 if (!DisableAModeOpt)
515 addPass(P: createHexagonOptAddrMode());
516 }
517}
518
519void HexagonPassConfig::addPreSched2() {
520 bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
521 addPass(P: createHexagonCopyToCombine());
522 if (getOptLevel() != CodeGenOptLevel::None)
523 addPass(PassID: &IfConverterID);
524 addPass(P: createHexagonSplitConst32AndConst64());
525 if (!NoOpt && !DisableHexagonMask)
526 addPass(P: createHexagonMask());
527
528 if (!NoOpt && !DisableHexagonLiveVars) {
529 addPass(PassID: &HexagonLiveVariablesID);
530 }
531}
532
533void HexagonPassConfig::addPreEmitPass() {
534 bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
535
536 if (!NoOpt)
537 addPass(P: createHexagonNewValueJump());
538
539 addPass(P: createHexagonBranchRelaxation());
540
541 if (!NoOpt) {
542 if (!DisableHardwareLoops)
543 addPass(P: createHexagonFixupHwLoops());
544 // Generate MUX from pairs of conditional transfers.
545 if (EnableGenMux)
546 addPass(P: createHexagonGenMux());
547 if (!DisableHexagonLiveVars)
548 addPass(PassID: &HexagonLiveVariablesID);
549 }
550
551 // Emit KCFI checks for indirect calls. Must run before packetization so
552 // the check and call can be bundled together into a VLIW packet.
553 addPass(P: createKCFIPass());
554
555 // Packetization is mandatory: it handles gather/scatter at all opt levels.
556 addPass(P: createHexagonPacketizer(Minimal: NoOpt));
557
558 if (!NoOpt) {
559 // Global pull-up scheduler
560 addPass(P: createHexagonGlobalScheduler());
561
562 addPass(P: createHexagonLoopAlign());
563 }
564
565 if (EnableVectorPrint)
566 addPass(P: createHexagonVectorPrint());
567
568 // Add CFI instructions if necessary.
569 addPass(P: createHexagonCallFrameInformation());
570}
571