1//===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implements the info about Hexagon target spec.
10//
11//===----------------------------------------------------------------------===//
12
13#include "HexagonTargetMachine.h"
14#include "Hexagon.h"
15#include "HexagonISelLowering.h"
16#include "HexagonLoopIdiomRecognition.h"
17#include "HexagonMachineFunctionInfo.h"
18#include "HexagonMachineScheduler.h"
19#include "HexagonTargetObjectFile.h"
20#include "HexagonTargetTransformInfo.h"
21#include "HexagonVectorLoopCarriedReuse.h"
22#include "TargetInfo/HexagonTargetInfo.h"
23#include "llvm/CodeGen/Passes.h"
24#include "llvm/CodeGen/TargetPassConfig.h"
25#include "llvm/CodeGen/VLIWMachineScheduler.h"
26#include "llvm/MC/TargetRegistry.h"
27#include "llvm/Passes/PassBuilder.h"
28#include "llvm/Support/CommandLine.h"
29#include "llvm/Support/Compiler.h"
30#include "llvm/Transforms/Scalar.h"
31#include <optional>
32
33using namespace llvm;
34
35static cl::opt<bool>
36 EnableCExtOpt("hexagon-cext", cl::Hidden, cl::init(Val: true),
37 cl::desc("Enable Hexagon constant-extender optimization"));
38
39static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::init(Val: true),
40 cl::desc("Enable RDF-based optimizations"));
41
42cl::opt<unsigned> RDFFuncBlockLimit(
43 "rdf-bb-limit", cl::Hidden, cl::init(Val: 1000),
44 cl::desc("Basic block limit for a function for RDF optimizations"));
45
46static cl::opt<bool>
47 DisableHardwareLoops("disable-hexagon-hwloops", cl::Hidden,
48 cl::desc("Disable Hardware Loops for Hexagon target"));
49
50static cl::opt<bool> EnableMCR("hexagon-mcr", cl::Hidden, cl::init(Val: true),
51 cl::desc("Enable the machine combiner pass"));
52
53static cl::opt<bool>
54 DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden,
55 cl::desc("Disable Hexagon Addressing Mode Optimization"));
56
57static cl::opt<bool>
58 DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden,
59 cl::desc("Disable Hexagon CFG Optimization"));
60
61static cl::opt<bool>
62 DisableHCP("disable-hcp", cl::Hidden,
63 cl::desc("Disable Hexagon constant propagation"));
64
65static cl::opt<bool> DisableHexagonMask(
66 "disable-mask", cl::Hidden,
67 cl::desc("Disable Hexagon specific Mask generation pass"));
68
69static cl::opt<bool> DisableStoreWidening("disable-store-widen", cl::Hidden,
70 cl::init(Val: false),
71 cl::desc("Disable store widening"));
72
73static cl::opt<bool> DisableLoadWidening("disable-load-widen", cl::Hidden,
74 cl::desc("Disable load widening"));
75
76static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
77 cl::init(Val: true), cl::Hidden,
78 cl::desc("Early expansion of MUX"));
79
80static cl::opt<bool> EnableTfrCleanup("hexagon-tfr-cleanup", cl::init(Val: true),
81 cl::Hidden,
82 cl::desc("Cleanup of TFRs/COPYs"));
83
84static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(Val: true), cl::Hidden,
85 cl::desc("Enable early if-conversion"));
86
87static cl::opt<bool> EnableCopyHoist("hexagon-copy-hoist", cl::init(Val: true),
88 cl::Hidden, cl::ZeroOrMore,
89 cl::desc("Enable Hexagon copy hoisting"));
90
91static cl::opt<bool>
92 EnableGenInsert("hexagon-insert", cl::init(Val: true), cl::Hidden,
93 cl::desc("Generate \"insert\" instructions"));
94
95static cl::opt<bool>
96 EnableCommGEP("hexagon-commgep", cl::init(Val: true), cl::Hidden,
97 cl::desc("Enable commoning of GEP instructions"));
98
99static cl::opt<bool>
100 EnableGenExtract("hexagon-extract", cl::init(Val: true), cl::Hidden,
101 cl::desc("Generate \"extract\" instructions"));
102
103static cl::opt<bool> EnableGenMux(
104 "hexagon-mux", cl::init(Val: true), cl::Hidden,
105 cl::desc("Enable converting conditional transfers into MUX instructions"));
106
107static cl::opt<bool>
108 EnableGenPred("hexagon-gen-pred", cl::init(Val: true), cl::Hidden,
109 cl::desc("Enable conversion of arithmetic operations to "
110 "predicate instructions"));
111
112static cl::opt<bool>
113 EnableLoopPrefetch("hexagon-loop-prefetch", cl::Hidden,
114 cl::desc("Enable loop data prefetch on Hexagon"));
115
116static cl::opt<bool>
117 DisableHSDR("disable-hsdr", cl::init(Val: false), cl::Hidden,
118 cl::desc("Disable splitting double registers"));
119
120static cl::opt<bool>
121 EnableGenMemAbs("hexagon-mem-abs", cl::init(Val: true), cl::Hidden,
122 cl::desc("Generate absolute set instructions"));
123
124static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(Val: true),
125 cl::Hidden,
126 cl::desc("Bit simplification"));
127
128static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(Val: true),
129 cl::Hidden,
130 cl::desc("Loop rescheduling"));
131
132static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(Val: false), cl::Hidden,
133 cl::desc("Disable backend optimizations"));
134
135static cl::opt<bool>
136 EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden,
137 cl::desc("Enable Hexagon Vector print instr pass"));
138
139static cl::opt<bool>
140 EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::init(Val: true),
141 cl::desc("Enable vextract optimization"));
142
143static cl::opt<bool>
144 EnableVectorCombine("hexagon-vector-combine", cl::Hidden, cl::init(Val: true),
145 cl::desc("Enable HVX vector combining"));
146
147static cl::opt<bool> EnableInitialCFGCleanup(
148 "hexagon-initial-cfg-cleanup", cl::Hidden, cl::init(Val: true),
149 cl::desc("Simplify the CFG after atomic expansion pass"));
150
151static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
152 cl::init(Val: true),
153 cl::desc("Enable instsimplify"));
154
155/// HexagonTargetMachineModule - Note that this is used on hosts that
156/// cannot link in a library unless there are references into the
157/// library. In particular, it seems that it is not possible to get
158/// things to work on Win32 without this. Though it is unused, do not
159/// remove it.
160extern "C" int HexagonTargetMachineModule;
161int HexagonTargetMachineModule = 0;
162
163static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
164 ScheduleDAGMILive *DAG = new VLIWMachineScheduler(
165 C, std::make_unique<HexagonConvergingVLIWScheduler>());
166 DAG->addMutation(Mutation: std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
167 DAG->addMutation(Mutation: std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
168 DAG->addMutation(Mutation: std::make_unique<HexagonSubtarget::CallMutation>());
169 DAG->addMutation(Mutation: createCopyConstrainDAGMutation(TII: DAG->TII, TRI: DAG->TRI));
170 return DAG;
171}
172
173static MachineSchedRegistry
174 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
175 createVLIWMachineSched);
176
177static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
178 return RM.value_or(u: Reloc::Static);
179}
180
181extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
182LLVMInitializeHexagonTarget() {
183 // Register the target.
184 RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
185
186 PassRegistry &PR = *PassRegistry::getPassRegistry();
187 initializeHexagonAsmPrinterPass(PR);
188 initializeHexagonBitSimplifyPass(PR);
189 initializeHexagonConstExtendersPass(PR);
190 initializeHexagonConstPropagationPass(PR);
191 initializeHexagonCopyToCombinePass(PR);
192 initializeHexagonEarlyIfConversionPass(PR);
193 initializeHexagonGenMemAbsolutePass(PR);
194 initializeHexagonGenMuxPass(PR);
195 initializeHexagonHardwareLoopsPass(PR);
196 initializeHexagonLoopIdiomRecognizeLegacyPassPass(PR);
197 initializeHexagonNewValueJumpPass(PR);
198 initializeHexagonOptAddrModePass(PR);
199 initializeHexagonPacketizerPass(PR);
200 initializeHexagonRDFOptPass(PR);
201 initializeHexagonSplitDoubleRegsPass(PR);
202 initializeHexagonVectorCombineLegacyPass(PR);
203 initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR);
204 initializeHexagonVExtractPass(PR);
205 initializeHexagonDAGToDAGISelLegacyPass(PR);
206 initializeHexagonLoopReschedulingPass(PR);
207 initializeHexagonBranchRelaxationPass(PR);
208 initializeHexagonCFGOptimizerPass(PR);
209 initializeHexagonCommonGEPPass(PR);
210 initializeHexagonCopyHoistingPass(PR);
211 initializeHexagonExpandCondsetsPass(PR);
212 initializeHexagonLoopAlignPass(PR);
213 initializeHexagonTfrCleanupPass(PR);
214 initializeHexagonFixupHwLoopsPass(PR);
215 initializeHexagonCallFrameInformationPass(PR);
216 initializeHexagonGenExtractPass(PR);
217 initializeHexagonGenInsertPass(PR);
218 initializeHexagonGenPredicatePass(PR);
219 initializeHexagonLoadWideningPass(PR);
220 initializeHexagonStoreWideningPass(PR);
221 initializeHexagonMaskPass(PR);
222 initializeHexagonOptimizeSZextendsPass(PR);
223 initializeHexagonPeepholePass(PR);
224 initializeHexagonSplitConst32AndConst64Pass(PR);
225 initializeHexagonVectorPrintPass(PR);
226 initializeHexagonQFPOptimizerPass(PR);
227}
228
229HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
230 StringRef CPU, StringRef FS,
231 const TargetOptions &Options,
232 std::optional<Reloc::Model> RM,
233 std::optional<CodeModel::Model> CM,
234 CodeGenOptLevel OL, bool JIT)
235 // Specify the vector alignment explicitly. For v512x1, the calculated
236 // alignment would be 512*alignment(i1), which is 512 bytes, instead of
237 // the required minimum of 64 bytes.
238 : CodeGenTargetMachineImpl(T, TT.computeDataLayout(), TT, CPU, FS, Options,
239 getEffectiveRelocModel(RM),
240 getEffectiveCodeModel(CM, Default: CodeModel::Small),
241 (HexagonNoOpt ? CodeGenOptLevel::None : OL)),
242 TLOF(std::make_unique<HexagonTargetObjectFile>()),
243 Subtarget(Triple(TT), CPU, FS, *this) {
244 initAsmInfo();
245}
246
247const HexagonSubtarget *
248HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
249 AttributeList FnAttrs = F.getAttributes();
250 Attribute CPUAttr = FnAttrs.getFnAttr(Kind: "target-cpu");
251 Attribute FSAttr = FnAttrs.getFnAttr(Kind: "target-features");
252
253 std::string CPU =
254 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
255 std::string FS =
256 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
257
258 auto &I = SubtargetMap[CPU + FS];
259 if (!I) {
260 // This needs to be done before we create a new subtarget since any
261 // creation will depend on the TM and the code generation flags on the
262 // function that reside in TargetOptions.
263 resetTargetOptions(F);
264 I = std::make_unique<HexagonSubtarget>(args: TargetTriple, args&: CPU, args&: FS, args: *this);
265 }
266 return I.get();
267}
268
269void HexagonTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
270#define GET_PASS_REGISTRY "HexagonPassRegistry.def"
271#include "llvm/Passes/TargetPassRegistry.inc"
272
273 PB.registerLateLoopOptimizationsEPCallback(
274 C: [=](LoopPassManager &LPM, OptimizationLevel Level) {
275 if (Level.getSpeedupLevel() > 0)
276 LPM.addPass(Pass: HexagonLoopIdiomRecognitionPass());
277 });
278 PB.registerLoopOptimizerEndEPCallback(
279 C: [=](LoopPassManager &LPM, OptimizationLevel Level) {
280 if (Level.getSpeedupLevel() > 0)
281 LPM.addPass(Pass: HexagonVectorLoopCarriedReusePass());
282 });
283}
284
285TargetTransformInfo
286HexagonTargetMachine::getTargetTransformInfo(const Function &F) const {
287 return TargetTransformInfo(std::make_unique<HexagonTTIImpl>(args: this, args: F));
288}
289
290MachineFunctionInfo *HexagonTargetMachine::createMachineFunctionInfo(
291 BumpPtrAllocator &Allocator, const Function &F,
292 const TargetSubtargetInfo *STI) const {
293 return HexagonMachineFunctionInfo::create<HexagonMachineFunctionInfo>(
294 Allocator, F, STI);
295}
296
297HexagonTargetMachine::~HexagonTargetMachine() = default;
298
299ScheduleDAGInstrs *
300HexagonTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
301 return createVLIWMachineSched(C);
302}
303
304namespace {
305/// Hexagon Code Generator Pass Configuration Options.
306class HexagonPassConfig : public TargetPassConfig {
307public:
308 HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
309 : TargetPassConfig(TM, PM) {}
310
311 HexagonTargetMachine &getHexagonTargetMachine() const {
312 return getTM<HexagonTargetMachine>();
313 }
314
315 void addIRPasses() override;
316 bool addInstSelector() override;
317 bool addILPOpts() override;
318 void addPreRegAlloc() override;
319 void addPostRegAlloc() override;
320 void addPreSched2() override;
321 void addPreEmitPass() override;
322};
323} // namespace
324
325TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
326 return new HexagonPassConfig(*this, PM);
327}
328
329void HexagonPassConfig::addIRPasses() {
330 TargetPassConfig::addIRPasses();
331 bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
332
333 if (!NoOpt) {
334 if (EnableInstSimplify)
335 addPass(P: createInstSimplifyLegacyPass());
336 addPass(P: createDeadCodeEliminationPass());
337 }
338
339 addPass(P: createAtomicExpandLegacyPass());
340
341 if (!NoOpt) {
342 if (EnableInitialCFGCleanup)
343 addPass(P: createCFGSimplificationPass(Options: SimplifyCFGOptions()
344 .forwardSwitchCondToPhi(B: true)
345 .convertSwitchRangeToICmp(B: true)
346 .convertSwitchToLookupTable(B: true)
347 .needCanonicalLoops(B: false)
348 .hoistCommonInsts(B: true)
349 .sinkCommonInsts(B: true)));
350 if (EnableLoopPrefetch)
351 addPass(P: createLoopDataPrefetchPass());
352 if (EnableVectorCombine)
353 addPass(P: createHexagonVectorCombineLegacyPass());
354 if (EnableCommGEP)
355 addPass(P: createHexagonCommonGEP());
356 // Replace certain combinations of shifts and ands with extracts.
357 if (EnableGenExtract)
358 addPass(P: createHexagonGenExtract());
359 }
360}
361
362bool HexagonPassConfig::addInstSelector() {
363 HexagonTargetMachine &TM = getHexagonTargetMachine();
364 bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
365
366 if (!NoOpt)
367 addPass(P: createHexagonOptimizeSZextends());
368
369 addPass(P: createHexagonISelDag(TM, OptLevel: getOptLevel()));
370
371 if (!NoOpt) {
372 if (EnableVExtractOpt)
373 addPass(P: createHexagonVExtract());
374 // Create logical operations on predicate registers.
375 if (EnableGenPred)
376 addPass(P: createHexagonGenPredicate());
377 // Rotate loops to expose bit-simplification opportunities.
378 if (EnableLoopResched)
379 addPass(P: createHexagonLoopRescheduling());
380 // Split double registers.
381 if (!DisableHSDR)
382 addPass(P: createHexagonSplitDoubleRegs());
383 // Bit simplification.
384 if (EnableBitSimplify)
385 addPass(P: createHexagonBitSimplify());
386 addPass(P: createHexagonPeephole());
387 // Constant propagation.
388 if (!DisableHCP) {
389 addPass(P: createHexagonConstPropagationPass());
390 addPass(PassID: &UnreachableMachineBlockElimID);
391 }
392 if (EnableGenInsert)
393 addPass(P: createHexagonGenInsert());
394 if (EnableEarlyIf)
395 addPass(P: createHexagonEarlyIfConversion());
396 addPass(P: createHexagonQFPOptimizer());
397 }
398
399 return false;
400}
401
402bool HexagonPassConfig::addILPOpts() {
403 if (EnableMCR)
404 addPass(PassID: &MachineCombinerID);
405
406 return true;
407}
408
409void HexagonPassConfig::addPreRegAlloc() {
410 if (getOptLevel() != CodeGenOptLevel::None) {
411 if (EnableCExtOpt)
412 addPass(P: createHexagonConstExtenders());
413 if (EnableExpandCondsets)
414 insertPass(TargetPassID: &RegisterCoalescerID, InsertedPassID: &HexagonExpandCondsetsID);
415 if (EnableCopyHoist)
416 insertPass(TargetPassID: &RegisterCoalescerID, InsertedPassID: &HexagonCopyHoistingID);
417 if (EnableTfrCleanup)
418 insertPass(TargetPassID: &VirtRegRewriterID, InsertedPassID: &HexagonTfrCleanupID);
419 if (!DisableStoreWidening)
420 addPass(P: createHexagonStoreWidening());
421 if (!DisableLoadWidening)
422 addPass(P: createHexagonLoadWidening());
423 if (EnableGenMemAbs)
424 addPass(P: createHexagonGenMemAbsolute());
425 if (!DisableHardwareLoops)
426 addPass(P: createHexagonHardwareLoops());
427 }
428 if (TM->getOptLevel() >= CodeGenOptLevel::Default)
429 addPass(PassID: &MachinePipelinerID);
430}
431
432void HexagonPassConfig::addPostRegAlloc() {
433 if (getOptLevel() != CodeGenOptLevel::None) {
434 if (EnableRDFOpt)
435 addPass(P: createHexagonRDFOpt());
436 if (!DisableHexagonCFGOpt)
437 addPass(P: createHexagonCFGOptimizer());
438 if (!DisableAModeOpt)
439 addPass(P: createHexagonOptAddrMode());
440 }
441}
442
443void HexagonPassConfig::addPreSched2() {
444 bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
445 addPass(P: createHexagonCopyToCombine());
446 if (getOptLevel() != CodeGenOptLevel::None)
447 addPass(PassID: &IfConverterID);
448 addPass(P: createHexagonSplitConst32AndConst64());
449 if (!NoOpt && !DisableHexagonMask)
450 addPass(P: createHexagonMask());
451}
452
453void HexagonPassConfig::addPreEmitPass() {
454 bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
455
456 if (!NoOpt)
457 addPass(P: createHexagonNewValueJump());
458
459 addPass(P: createHexagonBranchRelaxation());
460
461 if (!NoOpt) {
462 if (!DisableHardwareLoops)
463 addPass(P: createHexagonFixupHwLoops());
464 // Generate MUX from pairs of conditional transfers.
465 if (EnableGenMux)
466 addPass(P: createHexagonGenMux());
467 }
468
469 // Packetization is mandatory: it handles gather/scatter at all opt levels.
470 addPass(P: createHexagonPacketizer(Minimal: NoOpt));
471
472 if (!NoOpt)
473 addPass(P: createHexagonLoopAlign());
474
475 if (EnableVectorPrint)
476 addPass(P: createHexagonVectorPrint());
477
478 // Add CFI instructions if necessary.
479 addPass(P: createHexagonCallFrameInformation());
480}
481