1//===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implements the info about Hexagon target spec.
10//
11//===----------------------------------------------------------------------===//
12
13#include "HexagonTargetMachine.h"
14#include "Hexagon.h"
15#include "HexagonISelLowering.h"
16#include "HexagonLoopIdiomRecognition.h"
17#include "HexagonMachineFunctionInfo.h"
18#include "HexagonMachineScheduler.h"
19#include "HexagonTargetObjectFile.h"
20#include "HexagonTargetTransformInfo.h"
21#include "HexagonVectorLoopCarriedReuse.h"
22#include "TargetInfo/HexagonTargetInfo.h"
23#include "llvm/CodeGen/MIRParser/MIParser.h"
24#include "llvm/CodeGen/Passes.h"
25#include "llvm/CodeGen/TargetPassConfig.h"
26#include "llvm/CodeGen/VLIWMachineScheduler.h"
27#include "llvm/InitializePasses.h"
28#include "llvm/MC/TargetRegistry.h"
29#include "llvm/Passes/PassBuilder.h"
30#include "llvm/Support/CommandLine.h"
31#include "llvm/Support/Compiler.h"
32#include "llvm/Transforms/Scalar.h"
33#include <optional>
34
35using namespace llvm;
36
37static cl::opt<bool>
38 EnableCExtOpt("hexagon-cext", cl::Hidden, cl::init(Val: true),
39 cl::desc("Enable Hexagon constant-extender optimization"));
40
41static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::init(Val: true),
42 cl::desc("Enable RDF-based optimizations"));
43
44static cl::opt<bool> EnablePostRAHandleQFP(
45 "hexagon-handle-qfloat", cl::init(Val: true), cl::Hidden,
46 cl::desc("Fix up QFloat spills and reloads after register allocation"));
47
48cl::opt<unsigned> RDFFuncBlockLimit(
49 "rdf-bb-limit", cl::Hidden, cl::init(Val: 1000),
50 cl::desc("Basic block limit for a function for RDF optimizations"));
51
52static cl::opt<bool>
53 DisableHardwareLoops("disable-hexagon-hwloops", cl::Hidden,
54 cl::desc("Disable Hardware Loops for Hexagon target"));
55
56static cl::opt<bool> EnableMCR("hexagon-mcr", cl::Hidden, cl::init(Val: true),
57 cl::desc("Enable the machine combiner pass"));
58
59static cl::opt<bool>
60 DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden,
61 cl::desc("Disable Hexagon Addressing Mode Optimization"));
62
63static cl::opt<bool>
64 DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden,
65 cl::desc("Disable Hexagon CFG Optimization"));
66
67static cl::opt<bool>
68 DisableHCP("disable-hcp", cl::Hidden,
69 cl::desc("Disable Hexagon constant propagation"));
70
71static cl::opt<bool> DisableHexagonMask(
72 "disable-mask", cl::Hidden,
73 cl::desc("Disable Hexagon specific Mask generation pass"));
74
75static cl::opt<bool> DisableHexagonLiveVars(
76 "disable-hlv", cl::Hidden,
77 cl::desc("Disable Hexagon specific post-RA live-variable analysis"));
78static cl::opt<bool> DisableStoreWidening("disable-store-widen", cl::Hidden,
79 cl::init(Val: false),
80 cl::desc("Disable store widening"));
81
82static cl::opt<bool> DisableLoadWidening("disable-load-widen", cl::Hidden,
83 cl::desc("Disable load widening"));
84
85static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
86 cl::init(Val: true), cl::Hidden,
87 cl::desc("Early expansion of MUX"));
88
89static cl::opt<bool> EnableTfrCleanup("hexagon-tfr-cleanup", cl::init(Val: true),
90 cl::Hidden,
91 cl::desc("Cleanup of TFRs/COPYs"));
92
93static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(Val: true), cl::Hidden,
94 cl::desc("Enable early if-conversion"));
95
96static cl::opt<bool> EnableCopyHoist("hexagon-copy-hoist", cl::init(Val: true),
97 cl::Hidden,
98 cl::desc("Enable Hexagon copy hoisting"));
99
100static cl::opt<bool>
101 EnableGenInsert("hexagon-insert", cl::init(Val: true), cl::Hidden,
102 cl::desc("Generate \"insert\" instructions"));
103
104static cl::opt<bool>
105 EnableCommGEP("hexagon-commgep", cl::init(Val: true), cl::Hidden,
106 cl::desc("Enable commoning of GEP instructions"));
107
108static cl::opt<bool>
109 EnableGenExtract("hexagon-extract", cl::init(Val: true), cl::Hidden,
110 cl::desc("Generate \"extract\" instructions"));
111
112static cl::opt<bool> EnableGenMux(
113 "hexagon-mux", cl::init(Val: true), cl::Hidden,
114 cl::desc("Enable converting conditional transfers into MUX instructions"));
115
116static cl::opt<bool>
117 EnableGenPred("hexagon-gen-pred", cl::init(Val: true), cl::Hidden,
118 cl::desc("Enable conversion of arithmetic operations to "
119 "predicate instructions"));
120
121static cl::opt<bool>
122 EnableLoopPrefetch("hexagon-loop-prefetch", cl::Hidden,
123 cl::desc("Enable loop data prefetch on Hexagon"));
124
125static cl::opt<bool>
126 DisableHSDR("disable-hsdr", cl::init(Val: false), cl::Hidden,
127 cl::desc("Disable splitting double registers"));
128
129static cl::opt<bool>
130 EnableGenMemAbs("hexagon-mem-abs", cl::init(Val: true), cl::Hidden,
131 cl::desc("Generate absolute set instructions"));
132
133static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(Val: true),
134 cl::Hidden,
135 cl::desc("Bit simplification"));
136
137static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(Val: true),
138 cl::Hidden,
139 cl::desc("Loop rescheduling"));
140
141static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(Val: false), cl::Hidden,
142 cl::desc("Disable backend optimizations"));
143
144static cl::opt<bool>
145 EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden,
146 cl::desc("Enable Hexagon Vector print instr pass"));
147
148static cl::opt<bool>
149 EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::init(Val: true),
150 cl::desc("Enable vextract optimization"));
151
152static cl::opt<bool>
153 EnableVectorCombine("hexagon-vector-combine", cl::Hidden, cl::init(Val: true),
154 cl::desc("Enable HVX vector combining"));
155
156static cl::opt<bool> EnableInitialCFGCleanup(
157 "hexagon-initial-cfg-cleanup", cl::Hidden, cl::init(Val: true),
158 cl::desc("Simplify the CFG after atomic expansion pass"));
159
160static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
161 cl::init(Val: true),
162 cl::desc("Enable instsimplify"));
163
164cl::opt<QFloatMode> QFloatModeValue(
165 "hexagon-qfloat-mode", cl::desc("Specify the qfloat mode to operate on."),
166 cl::Hidden, cl::init(Val: QFloatMode::Legacy),
167 cl::values(
168 clEnumValN(QFloatMode::StrictIEEE, "strict-ieee",
169 "Enable code generation for qfloat strict IEEE-754 mode"),
170 clEnumValN(QFloatMode::IEEE, "ieee",
171 "Enable code generation for qfloat IEEE-754 mode"),
172 clEnumValN(QFloatMode::Lossy, "lossy",
173 "Enable code generation for qfloat lossy-subnormals mode"),
174 clEnumValN(QFloatMode::Legacy, "legacy",
175 "Enable code generation for qfloat legacy mode")));
176
177/// HexagonTargetMachineModule - Note that this is used on hosts that
178/// cannot link in a library unless there are references into the
179/// library. In particular, it seems that it is not possible to get
180/// things to work on Win32 without this. Though it is unused, do not
181/// remove it.
182extern "C" int HexagonTargetMachineModule;
183int HexagonTargetMachineModule = 0;
184
185static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
186 ScheduleDAGMILive *DAG = new VLIWMachineScheduler(
187 C, std::make_unique<HexagonConvergingVLIWScheduler>());
188 DAG->addMutation(Mutation: std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
189 DAG->addMutation(Mutation: std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
190 DAG->addMutation(Mutation: std::make_unique<HexagonSubtarget::CallMutation>());
191 DAG->addMutation(Mutation: createCopyConstrainDAGMutation(TII: DAG->TII, TRI: DAG->TRI));
192 return DAG;
193}
194
195static MachineSchedRegistry
196 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
197 createVLIWMachineSched);
198
199static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
200 return RM.value_or(u: Reloc::Static);
201}
202
203extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
204LLVMInitializeHexagonTarget() {
205 // Register the target.
206 RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
207
208 PassRegistry &PR = *PassRegistry::getPassRegistry();
209 initializeHexagonAlignGlobalArraysPass(PR);
210 initializeHexagonAsmPrinterPass(PR);
211 initializeHexagonBitSimplifyPass(PR);
212 initializeHexagonConstExtendersPass(PR);
213 initializeHexagonConstPropagationPass(PR);
214 initializeHexagonCopyToCombinePass(PR);
215 initializeHexagonEarlyIfConversionPass(PR);
216 initializeHexagonGenMemAbsolutePass(PR);
217 initializeHexagonGenMuxPass(PR);
218 initializeHexagonGlobalSchedulerPass(PR);
219 initializeHexagonLiveVariablesPass(PR);
220 initializeHexagonHardwareLoopsPass(PR);
221 initializeHexagonHVXSaveRemarkPass(PR);
222 initializeHexagonLoopIdiomRecognizeLegacyPassPass(PR);
223 initializeHexagonNewValueJumpPass(PR);
224 initializeHexagonOptAddrModePass(PR);
225 initializeHexagonPacketizerPass(PR);
226 initializeHexagonRDFOptPass(PR);
227 initializeHexagonSplitDoubleRegsPass(PR);
228 initializeHexagonVectorCombineLegacyPass(PR);
229 initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR);
230 initializeHexagonVExtractPass(PR);
231 initializeHexagonDAGToDAGISelLegacyPass(PR);
232 initializeHexagonLoopReschedulingPass(PR);
233 initializeHexagonBranchRelaxationPass(PR);
234 initializeHexagonCFGOptimizerPass(PR);
235 initializeHexagonCommonGEPPass(PR);
236 initializeHexagonCopyHoistingPass(PR);
237 initializeHexagonExpandCondsetsPass(PR);
238 initializeHexagonLoopAlignPass(PR);
239 initializeHexagonTfrCleanupPass(PR);
240 initializeHexagonFixupHwLoopsPass(PR);
241 initializeHexagonCallFrameInformationPass(PR);
242 initializeHexagonGenExtractPass(PR);
243 initializeHexagonGenInsertPass(PR);
244 initializeHexagonGenPredicatePass(PR);
245 initializeHexagonLoadWideningPass(PR);
246 initializeHexagonStoreWideningPass(PR);
247 initializeHexagonMaskPass(PR);
248 initializeHexagonOptimizeSZextendsPass(PR);
249 initializeHexagonPeepholePass(PR);
250 initializeHexagonSplitConst32AndConst64Pass(PR);
251 initializeHexagonVectorPrintPass(PR);
252 initializeHexagonQFPOptimizerPass(PR);
253 initializeHexagonXQFloatGeneratorPass(PR);
254 initializeHexagonPostRAHandleQFPPass(PR);
255 initializeMachineKCFILegacyPass(PR);
256}
257
258HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
259 StringRef CPU, StringRef FS,
260 const TargetOptions &Options,
261 std::optional<Reloc::Model> RM,
262 std::optional<CodeModel::Model> CM,
263 CodeGenOptLevel OL, bool JIT)
264 // Specify the vector alignment explicitly. For v512x1, the calculated
265 // alignment would be 512*alignment(i1), which is 512 bytes, instead of
266 // the required minimum of 64 bytes.
267 : CodeGenTargetMachineImpl(T, TT.computeDataLayout(), TT, CPU, FS, Options,
268 getEffectiveRelocModel(RM),
269 getEffectiveCodeModel(CM, Default: CodeModel::Small),
270 (HexagonNoOpt ? CodeGenOptLevel::None : OL)),
271 TLOF(std::make_unique<HexagonTargetObjectFile>()),
272 Subtarget(Triple(TT), CPU, FS, *this) {
273 initAsmInfo();
274}
275
276const HexagonSubtarget *
277HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
278 AttributeList FnAttrs = F.getAttributes();
279 Attribute CPUAttr = FnAttrs.getFnAttr(Kind: "target-cpu");
280 Attribute FSAttr = FnAttrs.getFnAttr(Kind: "target-features");
281
282 std::string CPU =
283 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
284 std::string FS =
285 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
286
287 auto &I = SubtargetMap[CPU + FS];
288 if (!I)
289 I = std::make_unique<HexagonSubtarget>(args: TargetTriple, args&: CPU, args&: FS, args: *this);
290 return I.get();
291}
292
293void HexagonTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
294#define GET_PASS_REGISTRY "HexagonPassRegistry.def"
295#include "llvm/Passes/TargetPassRegistry.inc"
296
297 PB.registerLateLoopOptimizationsEPCallback(
298 C: [=](LoopPassManager &LPM, OptimizationLevel Level) {
299 if (Level != OptimizationLevel::O0)
300 LPM.addPass(Pass: HexagonLoopIdiomRecognitionPass());
301 });
302 PB.registerLoopOptimizerEndEPCallback(
303 C: [=](LoopPassManager &LPM, OptimizationLevel Level) {
304 if (Level != OptimizationLevel::O0)
305 LPM.addPass(Pass: HexagonVectorLoopCarriedReusePass());
306 });
307}
308
309TargetTransformInfo
310HexagonTargetMachine::getTargetTransformInfo(const Function &F) const {
311 return TargetTransformInfo(std::make_unique<HexagonTTIImpl>(args: this, args: F));
312}
313
314MachineFunctionInfo *HexagonTargetMachine::createMachineFunctionInfo(
315 BumpPtrAllocator &Allocator, const Function &F,
316 const TargetSubtargetInfo *STI) const {
317 return HexagonMachineFunctionInfo::create<HexagonMachineFunctionInfo>(
318 Allocator, F, STI);
319}
320
321yaml::MachineFunctionInfo *
322HexagonTargetMachine::createDefaultFuncInfoYAML() const {
323 return new yaml::HexagonFunctionInfo();
324}
325
326yaml::MachineFunctionInfo *
327HexagonTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
328 const auto *MFI = MF.getInfo<HexagonMachineFunctionInfo>();
329 const auto &TRI = *MF.getSubtarget().getRegisterInfo();
330 return new yaml::HexagonFunctionInfo(*MFI, TRI);
331}
332
333bool HexagonTargetMachine::parseMachineFunctionInfo(
334 const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
335 SMDiagnostic &Error, SMRange &SourceRange) const {
336 const auto &YamlMFI = static_cast<const yaml::HexagonFunctionInfo &>(MFI_);
337 MachineFunction &MF = PFS.MF;
338 HexagonMachineFunctionInfo *MFI = MF.getInfo<HexagonMachineFunctionInfo>();
339
340 MFI->initializeBaseYamlFields(YamlMFI);
341
342 // Parse StackAlignBaseReg register name
343 if (!YamlMFI.StackAlignBaseReg.Value.empty()) {
344 Register Reg;
345 if (parseNamedRegisterReference(PFS, Reg, Src: YamlMFI.StackAlignBaseReg.Value,
346 Error)) {
347 SourceRange = YamlMFI.StackAlignBaseReg.SourceRange;
348 return true;
349 }
350 MFI->setStackAlignBaseReg(Reg);
351 }
352
353 return false;
354}
355
356HexagonTargetMachine::~HexagonTargetMachine() = default;
357
358ScheduleDAGInstrs *
359HexagonTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
360 return createVLIWMachineSched(C);
361}
362
363namespace {
364/// Hexagon Code Generator Pass Configuration Options.
365class HexagonPassConfig : public TargetPassConfig {
366public:
367 HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
368 : TargetPassConfig(TM, PM) {}
369
370 HexagonTargetMachine &getHexagonTargetMachine() const {
371 return getTM<HexagonTargetMachine>();
372 }
373
374 void addIRPasses() override;
375 bool addInstSelector() override;
376 bool addILPOpts() override;
377 void addPreRegAlloc() override;
378 void addPostRegAlloc() override;
379 void addPreSched2() override;
380 void addPreEmitPass() override;
381};
382} // namespace
383
384TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
385 return new HexagonPassConfig(*this, PM);
386}
387
388void HexagonPassConfig::addIRPasses() {
389 TargetPassConfig::addIRPasses();
390 bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
391
392 if (!NoOpt) {
393 // Raise the alignment of global integer arrays to 8 bytes. At -O1/-O2,
394 // reduce .rodata size by keeping byte/half-word arrays at their natural
395 // alignment; apply full 8-byte alignment at -O3.
396 addPass(P: createHexagonAlignGlobalArrays(ReduceRodataSize: getOptLevel() !=
397 CodeGenOptLevel::Aggressive));
398 if (EnableInstSimplify)
399 addPass(P: createInstSimplifyLegacyPass());
400 addPass(P: createDeadCodeEliminationPass());
401 }
402
403 addPass(P: createAtomicExpandLegacyPass());
404
405 if (!NoOpt) {
406 if (EnableInitialCFGCleanup)
407 addPass(P: createCFGSimplificationPass(Options: SimplifyCFGOptions()
408 .forwardSwitchCondToPhi(B: true)
409 .convertSwitchRangeToICmp(B: true)
410 .convertSwitchToLookupTable(B: true)
411 .needCanonicalLoops(B: false)
412 .hoistCommonInsts(B: true)
413 .sinkCommonInsts(B: true)));
414 if (EnableLoopPrefetch)
415 addPass(P: createLoopDataPrefetchPass());
416 if (EnableVectorCombine)
417 addPass(P: createHexagonVectorCombineLegacyPass());
418 if (EnableCommGEP)
419 addPass(P: createHexagonCommonGEP());
420 // Replace certain combinations of shifts and ands with extracts.
421 if (EnableGenExtract)
422 addPass(P: createHexagonGenExtract());
423 }
424}
425
426bool HexagonPassConfig::addInstSelector() {
427 HexagonTargetMachine &TM = getHexagonTargetMachine();
428 const HexagonSubtarget *HST = TM.getHexagonSubtarget();
429 bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
430
431 if (!NoOpt)
432 addPass(P: createHexagonOptimizeSZextends());
433
434 addPass(P: createHexagonISelDag(TM, OptLevel: getOptLevel()));
435 // Run the QFloat mode code generation pass only if v79 or greater.
436 // Do not run this pass, if legacy mode is passed on command line.
437 if (HST->useHVXV79Ops() && (QFloatModeValue != QFloatMode::Legacy))
438 addPass(P: createHexagonXQFloatGenerator());
439
440 if (!NoOpt) {
441 if (EnableVExtractOpt)
442 addPass(P: createHexagonVExtract());
443 // Create logical operations on predicate registers.
444 if (EnableGenPred)
445 addPass(P: createHexagonGenPredicate());
446 // Rotate loops to expose bit-simplification opportunities.
447 if (EnableLoopResched)
448 addPass(P: createHexagonLoopRescheduling());
449 // Split double registers.
450 if (!DisableHSDR)
451 addPass(P: createHexagonSplitDoubleRegs());
452 // Bit simplification.
453 if (EnableBitSimplify)
454 addPass(P: createHexagonBitSimplify());
455 addPass(P: createHexagonPeephole());
456 // Constant propagation.
457 if (!DisableHCP) {
458 addPass(P: createHexagonConstPropagationPass());
459 addPass(PassID: &UnreachableMachineBlockElimID);
460 }
461 if (EnableGenInsert)
462 addPass(P: createHexagonGenInsert());
463 if (EnableEarlyIf)
464 addPass(P: createHexagonEarlyIfConversion());
465 // For v75 or below, or if legacy mode is requested, run QFPOptizer pass
466 // to preserve backward compatibility.
467 if (!HST->useHVXV79Ops() || (QFloatModeValue == QFloatMode::Legacy))
468 addPass(P: createHexagonQFPOptimizer());
469 }
470
471 return false;
472}
473
474bool HexagonPassConfig::addILPOpts() {
475 if (EnableMCR)
476 addPass(PassID: &MachineCombinerID);
477
478 return true;
479}
480
481void HexagonPassConfig::addPreRegAlloc() {
482 if (getOptLevel() != CodeGenOptLevel::None) {
483 if (EnableCExtOpt)
484 addPass(P: createHexagonConstExtenders());
485 if (EnableExpandCondsets)
486 insertPass(TargetPassID: &RegisterCoalescerID, InsertedPassID: &HexagonExpandCondsetsID);
487 if (EnableCopyHoist)
488 insertPass(TargetPassID: &RegisterCoalescerID, InsertedPassID: &HexagonCopyHoistingID);
489 if (EnableTfrCleanup)
490 insertPass(TargetPassID: &VirtRegRewriterID, InsertedPassID: &HexagonTfrCleanupID);
491 if (!DisableStoreWidening)
492 addPass(P: createHexagonStoreWidening());
493 if (!DisableLoadWidening)
494 addPass(P: createHexagonLoadWidening());
495 if (EnableGenMemAbs)
496 addPass(P: createHexagonGenMemAbsolute());
497 if (!DisableHardwareLoops)
498 addPass(P: createHexagonHardwareLoops());
499 }
500 if (TM->getOptLevel() >= CodeGenOptLevel::Default)
501 addPass(PassID: &MachinePipelinerID);
502 addPass(P: createHexagonHVXSaveRemark());
503}
504
505void HexagonPassConfig::addPostRegAlloc() {
506 HexagonTargetMachine &HTM = getHexagonTargetMachine();
507 const HexagonSubtarget *HST = HTM.getHexagonSubtarget();
508 // Run PostRAQFP on v79 and above.
509 if (EnablePostRAHandleQFP && HST->useHVXV79Ops())
510 addPass(P: createHexagonPostRAHandleQFP());
511
512 if (getOptLevel() != CodeGenOptLevel::None) {
513 if (EnableRDFOpt)
514 addPass(P: createHexagonRDFOpt());
515 if (!DisableHexagonCFGOpt)
516 addPass(P: createHexagonCFGOptimizer());
517 if (!DisableAModeOpt)
518 addPass(P: createHexagonOptAddrMode());
519 }
520}
521
522void HexagonPassConfig::addPreSched2() {
523 bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
524 addPass(P: createHexagonCopyToCombine());
525 if (getOptLevel() != CodeGenOptLevel::None)
526 addPass(PassID: &IfConverterID);
527 addPass(P: createHexagonSplitConst32AndConst64());
528 if (!NoOpt && !DisableHexagonMask)
529 addPass(P: createHexagonMask());
530
531 if (!NoOpt && !DisableHexagonLiveVars) {
532 addPass(PassID: &HexagonLiveVariablesID);
533 }
534}
535
536void HexagonPassConfig::addPreEmitPass() {
537 bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
538
539 if (!NoOpt)
540 addPass(P: createHexagonNewValueJump());
541
542 addPass(P: createHexagonBranchRelaxation());
543
544 if (!NoOpt) {
545 if (!DisableHardwareLoops)
546 addPass(P: createHexagonFixupHwLoops());
547 // Generate MUX from pairs of conditional transfers.
548 if (EnableGenMux)
549 addPass(P: createHexagonGenMux());
550 if (!DisableHexagonLiveVars)
551 addPass(PassID: &HexagonLiveVariablesID);
552 }
553
554 // Emit KCFI checks for indirect calls. Must run before packetization so
555 // the check and call can be bundled together into a VLIW packet.
556 addPass(P: createKCFIPass());
557
558 // Packetization is mandatory: it handles gather/scatter at all opt levels.
559 addPass(P: createHexagonPacketizer(Minimal: NoOpt));
560
561 if (!NoOpt) {
562 // Global pull-up scheduler
563 addPass(P: createHexagonGlobalScheduler());
564
565 addPass(P: createHexagonLoopAlign());
566 }
567
568 if (EnableVectorPrint)
569 addPass(P: createHexagonVectorPrint());
570
571 // Add CFI instructions if necessary.
572 addPass(P: createHexagonCallFrameInformation());
573}
574