1//===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides Mips specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MipsMCTargetDesc.h"
14#include "MipsAsmBackend.h"
15#include "MipsBaseInfo.h"
16#include "MipsELFStreamer.h"
17#include "MipsInstPrinter.h"
18#include "MipsMCAsmInfo.h"
19#include "MipsMCOptions.h"
20#include "MipsTargetStreamer.h"
21#include "TargetInfo/MipsTargetInfo.h"
22#include "llvm/DebugInfo/CodeView/CodeView.h"
23#include "llvm/MC/MCCodeEmitter.h"
24#include "llvm/MC/MCELFStreamer.h"
25#include "llvm/MC/MCInstrAnalysis.h"
26#include "llvm/MC/MCInstrInfo.h"
27#include "llvm/MC/MCObjectWriter.h"
28#include "llvm/MC/MCRegisterInfo.h"
29#include "llvm/MC/MCSubtargetInfo.h"
30#include "llvm/MC/MCSymbol.h"
31#include "llvm/MC/TargetRegistry.h"
32#include "llvm/Option/LibraryOptions.h"
33#include "llvm/Support/Compiler.h"
34#include "llvm/Support/ErrorHandling.h"
35#include "llvm/Support/FormattedStream.h"
36#include "llvm/TargetParser/Triple.h"
37
38using namespace llvm;
39
40#define GET_INSTRINFO_MC_DESC
41#define ENABLE_INSTR_PREDICATE_VERIFIER
42#include "MipsGenInstrInfo.inc"
43
44#define GET_SUBTARGETINFO_MC_DESC
45#include "MipsGenSubtargetInfo.inc"
46
47#define GET_REGINFO_MC_DESC
48#include "MipsGenRegisterInfo.inc"
49
50#define GET_REGISTER_MATCHER
51#include "MipsGenAsmMatcher.inc"
52
53#define OPTIONS_STRUCT_DEFS
54#include "MipsMCOptions.inc"
55
56MCRegister MIPS_MC::matchRegisterName(StringRef Name, const MCRegisterInfo &MRI,
57 unsigned RegClassID, unsigned AltIdx) {
58 MCRegister Reg = MatchRegisterAltName(Name, AltIdx);
59 if (!Reg)
60 Reg = MatchRegisterName(Name);
61 if (!Reg)
62 return MCRegister();
63
64 const MCRegisterClass &RC = MRI.getRegClass(i: RegClassID);
65 // GPR32 and GPR64 share names; select the requested width.
66 if (!RC.contains(Reg)) {
67 if (RegClassID == Mips::GPR32RegClassID &&
68 MRI.getRegClass(i: Mips::GPR64RegClassID).contains(Reg))
69 Reg = MRI.getSubReg(Reg, Idx: Mips::sub_32);
70 else if (RegClassID == Mips::GPR64RegClassID &&
71 MRI.getRegClass(i: Mips::GPR32RegClassID).contains(Reg))
72 Reg = MRI.getMatchingSuperReg(Reg, SubIdx: Mips::sub_32, RC: &RC);
73 }
74 return RC.contains(Reg) ? Reg : MCRegister();
75}
76
77int MIPS_MC::getCPURegisterIndex(StringRef Name, const MCRegisterInfo &MRI,
78 unsigned AltIdx, bool *IsDeprecated) {
79 if (IsDeprecated)
80 *IsDeprecated = false;
81
82 if (MCRegister Reg =
83 matchRegisterName(Name, MRI, RegClassID: Mips::GPR32RegClassID, AltIdx))
84 return MRI.getEncodingValue(Reg);
85
86 static const struct {
87 StringLiteral Name;
88 MCPhysReg Reg;
89 // NoRegAltName applies to all ABIs.
90 unsigned AltIdx;
91 } Aliases[] = {
92 {.Name: "AT", .Reg: Mips::R1, .AltIdx: Mips::NoRegAltName},
93 {.Name: "s8", .Reg: Mips::FP, .AltIdx: Mips::NoRegAltName},
94 {.Name: "kt0", .Reg: Mips::R26, .AltIdx: Mips::NABIRegAltName},
95 {.Name: "kt1", .Reg: Mips::R27, .AltIdx: Mips::NABIRegAltName},
96 };
97 for (const auto &Alias : Aliases)
98 if (Name == Alias.Name &&
99 (Alias.AltIdx == Mips::NoRegAltName || Alias.AltIdx == AltIdx))
100 return MRI.getEncodingValue(Reg: Alias.Reg);
101
102 // GNU also accepts t4-t7 for NABI's t0-t3.
103 if (AltIdx == Mips::NABIRegAltName) {
104 static const struct {
105 StringLiteral Name;
106 MCPhysReg Reg;
107 } Deprecated[] = {
108 {.Name: "t4", .Reg: Mips::R12},
109 {.Name: "t5", .Reg: Mips::R13},
110 {.Name: "t6", .Reg: Mips::R14},
111 {.Name: "t7", .Reg: Mips::R15},
112 };
113 for (const auto &Alias : Deprecated) {
114 if (Name == Alias.Name) {
115 if (IsDeprecated)
116 *IsDeprecated = true;
117 return MRI.getEncodingValue(Reg: Alias.Reg);
118 }
119 }
120 }
121 return -1;
122}
123
124void MIPS_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
125 // Mapping from CodeView to MC register id.
126 static const struct {
127 codeview::RegisterId CVReg;
128 MCPhysReg Reg;
129 } RegMap[] = {
130 {.CVReg: codeview::RegisterId::MIPS_ZERO, .Reg: Mips::R0},
131 {.CVReg: codeview::RegisterId::MIPS_AT, .Reg: Mips::R1},
132 {.CVReg: codeview::RegisterId::MIPS_V0, .Reg: Mips::R2},
133 {.CVReg: codeview::RegisterId::MIPS_V1, .Reg: Mips::R3},
134 {.CVReg: codeview::RegisterId::MIPS_A0, .Reg: Mips::R4},
135 {.CVReg: codeview::RegisterId::MIPS_A1, .Reg: Mips::R5},
136 {.CVReg: codeview::RegisterId::MIPS_A2, .Reg: Mips::R6},
137 {.CVReg: codeview::RegisterId::MIPS_A3, .Reg: Mips::R7},
138 {.CVReg: codeview::RegisterId::MIPS_T0, .Reg: Mips::R8},
139 {.CVReg: codeview::RegisterId::MIPS_T1, .Reg: Mips::R9},
140 {.CVReg: codeview::RegisterId::MIPS_T2, .Reg: Mips::R10},
141 {.CVReg: codeview::RegisterId::MIPS_T3, .Reg: Mips::R11},
142 {.CVReg: codeview::RegisterId::MIPS_T4, .Reg: Mips::R12},
143 {.CVReg: codeview::RegisterId::MIPS_T5, .Reg: Mips::R13},
144 {.CVReg: codeview::RegisterId::MIPS_T6, .Reg: Mips::R14},
145 {.CVReg: codeview::RegisterId::MIPS_T7, .Reg: Mips::R15},
146 {.CVReg: codeview::RegisterId::MIPS_S0, .Reg: Mips::R16},
147 {.CVReg: codeview::RegisterId::MIPS_S1, .Reg: Mips::R17},
148 {.CVReg: codeview::RegisterId::MIPS_S2, .Reg: Mips::R18},
149 {.CVReg: codeview::RegisterId::MIPS_S3, .Reg: Mips::R19},
150 {.CVReg: codeview::RegisterId::MIPS_S4, .Reg: Mips::R20},
151 {.CVReg: codeview::RegisterId::MIPS_S5, .Reg: Mips::R21},
152 {.CVReg: codeview::RegisterId::MIPS_S6, .Reg: Mips::R22},
153 {.CVReg: codeview::RegisterId::MIPS_S7, .Reg: Mips::R23},
154 {.CVReg: codeview::RegisterId::MIPS_T8, .Reg: Mips::R24},
155 {.CVReg: codeview::RegisterId::MIPS_T9, .Reg: Mips::R25},
156 {.CVReg: codeview::RegisterId::MIPS_K0, .Reg: Mips::R26},
157 {.CVReg: codeview::RegisterId::MIPS_K1, .Reg: Mips::R27},
158 {.CVReg: codeview::RegisterId::MIPS_GP, .Reg: Mips::GP},
159 {.CVReg: codeview::RegisterId::MIPS_SP, .Reg: Mips::SP},
160 {.CVReg: codeview::RegisterId::MIPS_S8, .Reg: Mips::FP},
161 {.CVReg: codeview::RegisterId::MIPS_RA, .Reg: Mips::RA},
162 {.CVReg: codeview::RegisterId::MIPS_LO, .Reg: Mips::HI0},
163 {.CVReg: codeview::RegisterId::MIPS_HI, .Reg: Mips::LO0},
164 {.CVReg: codeview::RegisterId::MIPS_Fir, .Reg: Mips::FCR0},
165 {.CVReg: codeview::RegisterId::MIPS_Psr, .Reg: Mips::COP012}, // CP0.Status
166 {.CVReg: codeview::RegisterId::MIPS_F0, .Reg: Mips::F0},
167 {.CVReg: codeview::RegisterId::MIPS_F1, .Reg: Mips::F1},
168 {.CVReg: codeview::RegisterId::MIPS_F2, .Reg: Mips::F2},
169 {.CVReg: codeview::RegisterId::MIPS_F3, .Reg: Mips::F3},
170 {.CVReg: codeview::RegisterId::MIPS_F4, .Reg: Mips::F4},
171 {.CVReg: codeview::RegisterId::MIPS_F5, .Reg: Mips::F5},
172 {.CVReg: codeview::RegisterId::MIPS_F6, .Reg: Mips::F6},
173 {.CVReg: codeview::RegisterId::MIPS_F7, .Reg: Mips::F7},
174 {.CVReg: codeview::RegisterId::MIPS_F8, .Reg: Mips::F8},
175 {.CVReg: codeview::RegisterId::MIPS_F9, .Reg: Mips::F9},
176 {.CVReg: codeview::RegisterId::MIPS_F10, .Reg: Mips::F10},
177 {.CVReg: codeview::RegisterId::MIPS_F11, .Reg: Mips::F11},
178 {.CVReg: codeview::RegisterId::MIPS_F12, .Reg: Mips::F12},
179 {.CVReg: codeview::RegisterId::MIPS_F13, .Reg: Mips::F13},
180 {.CVReg: codeview::RegisterId::MIPS_F14, .Reg: Mips::F14},
181 {.CVReg: codeview::RegisterId::MIPS_F15, .Reg: Mips::F15},
182 {.CVReg: codeview::RegisterId::MIPS_F16, .Reg: Mips::F16},
183 {.CVReg: codeview::RegisterId::MIPS_F17, .Reg: Mips::F17},
184 {.CVReg: codeview::RegisterId::MIPS_F18, .Reg: Mips::F18},
185 {.CVReg: codeview::RegisterId::MIPS_F19, .Reg: Mips::F19},
186 {.CVReg: codeview::RegisterId::MIPS_F20, .Reg: Mips::F20},
187 {.CVReg: codeview::RegisterId::MIPS_F21, .Reg: Mips::F21},
188 {.CVReg: codeview::RegisterId::MIPS_F22, .Reg: Mips::F22},
189 {.CVReg: codeview::RegisterId::MIPS_F23, .Reg: Mips::F23},
190 {.CVReg: codeview::RegisterId::MIPS_F24, .Reg: Mips::F24},
191 {.CVReg: codeview::RegisterId::MIPS_F25, .Reg: Mips::F25},
192 {.CVReg: codeview::RegisterId::MIPS_F26, .Reg: Mips::F26},
193 {.CVReg: codeview::RegisterId::MIPS_F27, .Reg: Mips::F27},
194 {.CVReg: codeview::RegisterId::MIPS_F28, .Reg: Mips::F28},
195 {.CVReg: codeview::RegisterId::MIPS_F29, .Reg: Mips::F29},
196 {.CVReg: codeview::RegisterId::MIPS_F30, .Reg: Mips::F30},
197 {.CVReg: codeview::RegisterId::MIPS_F31, .Reg: Mips::F31},
198 {.CVReg: codeview::RegisterId::MIPS_Fsr, .Reg: Mips::FCR31},
199 };
200 for (const auto &I : RegMap)
201 MRI->mapLLVMRegToCVReg(LLVMReg: I.Reg, CVReg: static_cast<int>(I.CVReg));
202}
203
204namespace {
205class MipsWinCOFFTargetStreamer : public MipsTargetStreamer {
206public:
207 MipsWinCOFFTargetStreamer(MCStreamer &S) : MipsTargetStreamer(S) {}
208};
209} // end namespace
210
211/// Select the Mips CPU for the given triple and cpu name.
212StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) {
213 if (CPU.empty() || CPU == "generic") {
214 if (TT.getSubArch() == llvm::Triple::MipsSubArch_r6) {
215 if (TT.isMIPS32())
216 CPU = "mips32r6";
217 else
218 CPU = "mips64r6";
219 } else {
220 if (TT.isMIPS32())
221 CPU = "mips32";
222 else
223 CPU = "mips64";
224 }
225 }
226 return CPU;
227}
228
229static MCInstrInfo *createMipsMCInstrInfo() {
230 MCInstrInfo *X = new MCInstrInfo();
231 InitMipsMCInstrInfo(II: X);
232 return X;
233}
234
235static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
236 MCRegisterInfo *X = new MCRegisterInfo();
237 InitMipsMCRegisterInfo(RI: X, RA: Mips::RA);
238 return X;
239}
240
241static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
242 StringRef CPU, StringRef FS) {
243 CPU = MIPS_MC::selectMipsCPU(TT, CPU);
244 return createMipsMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
245}
246
247static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
248 const Triple &TT,
249 const MCTargetOptions &Options) {
250 MCAsmInfo *MAI;
251
252 if (TT.isOSBinFormatCOFF())
253 MAI = new MipsCOFFMCAsmInfo(Options);
254 else
255 MAI = new MipsELFMCAsmInfo(TT, Options);
256
257 unsigned SP = MRI.getDwarfRegNum(Reg: Mips::SP, isEH: true);
258 MCCFIInstruction Inst = MCCFIInstruction::createDefCfaRegister(L: nullptr, Register: SP);
259 MAI->addInitialFrameState(Inst);
260
261 return MAI;
262}
263
264static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
265 unsigned SyntaxVariant,
266 const MCAsmInfo &MAI,
267 const MCInstrInfo &MII,
268 const MCRegisterInfo &MRI) {
269 return new MipsInstPrinter(MAI, MII, MRI);
270}
271
272static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
273 std::unique_ptr<MCAsmBackend> &&MAB,
274 std::unique_ptr<MCObjectWriter> &&OW,
275 std::unique_ptr<MCCodeEmitter> &&Emitter) {
276 MCStreamer *S;
277 S = createMipsELFStreamer(Context, MAB: std::move(MAB), OW: std::move(OW),
278 Emitter: std::move(Emitter));
279 return S;
280}
281
282static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S,
283 formatted_raw_ostream &OS,
284 MCInstPrinter *InstPrint) {
285 return new MipsTargetAsmStreamer(S, OS);
286}
287
288static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) {
289 return new MipsTargetStreamer(S);
290}
291
292static MCTargetStreamer *
293createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
294 if (STI.getTargetTriple().isOSBinFormatCOFF())
295 return new MipsWinCOFFTargetStreamer(S);
296 return new MipsTargetELFStreamer(S, STI);
297}
298
299namespace {
300
301class MipsMCInstrAnalysis : public MCInstrAnalysis {
302public:
303 MipsMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
304
305 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
306 uint64_t &Target) const override {
307 unsigned NumOps = Inst.getNumOperands();
308 // Register-list transfers have more MC operands than descriptor entries.
309 if (NumOps == 0 || NumOps > Info->get(Opcode: Inst.getOpcode()).getNumOperands())
310 return false;
311 switch (Info->get(Opcode: Inst.getOpcode()).operands()[NumOps - 1].OperandType) {
312 case MCOI::OPERAND_UNKNOWN:
313 case MCOI::OPERAND_IMMEDIATE: {
314 // j, jal, jalx, jals
315 // Absolute branch within the current 256 MB-aligned region
316 uint64_t Region = Addr & ~uint64_t(0xfffffff);
317 Target = Region + Inst.getOperand(i: NumOps - 1).getImm();
318 return true;
319 }
320 case MCOI::OPERAND_PCREL:
321 // b, beq ...
322 Target = Addr + Inst.getOperand(i: NumOps - 1).getImm();
323 return true;
324 default:
325 return false;
326 }
327 }
328};
329}
330
331static MCInstrAnalysis *createMipsMCInstrAnalysis(const MCInstrInfo *Info) {
332 return new MipsMCInstrAnalysis(Info);
333}
334
335extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTargetMC() {
336 static opt::RegisterLibraryOptions<MipsMCOptions> O;
337 for (Target *T : {&getTheMipsTarget(), &getTheMipselTarget(),
338 &getTheMips64Target(), &getTheMips64elTarget()}) {
339 // Register the MC asm info.
340 RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
341
342 // Register the MC instruction info.
343 TargetRegistry::RegisterMCInstrInfo(T&: *T, Fn: createMipsMCInstrInfo);
344
345 // Register the MC register info.
346 TargetRegistry::RegisterMCRegInfo(T&: *T, Fn: createMipsMCRegisterInfo);
347
348 // Register the elf streamer.
349 TargetRegistry::RegisterELFStreamer(T&: *T, Fn: createMCStreamer);
350
351 // Register the asm target streamer.
352 TargetRegistry::RegisterAsmTargetStreamer(T&: *T, Fn: createMipsAsmTargetStreamer);
353
354 TargetRegistry::RegisterNullTargetStreamer(T&: *T,
355 Fn: createMipsNullTargetStreamer);
356
357 TargetRegistry::RegisterCOFFStreamer(T&: *T, Fn: createMipsWinCOFFStreamer);
358
359 // Register the MC subtarget info.
360 TargetRegistry::RegisterMCSubtargetInfo(T&: *T, Fn: createMipsMCSubtargetInfo);
361
362 // Register the MC instruction analyzer.
363 TargetRegistry::RegisterMCInstrAnalysis(T&: *T, Fn: createMipsMCInstrAnalysis);
364
365 // Register the MCInstPrinter.
366 TargetRegistry::RegisterMCInstPrinter(T&: *T, Fn: createMipsMCInstPrinter);
367
368 TargetRegistry::RegisterObjectTargetStreamer(
369 T&: *T, Fn: createMipsObjectTargetStreamer);
370
371 // Register the asm backend.
372 TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createMipsAsmBackend);
373 }
374
375 // Register the MC Code Emitter
376 for (Target *T : {&getTheMipsTarget(), &getTheMips64Target()})
377 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createMipsMCCodeEmitterEB);
378
379 for (Target *T : {&getTheMipselTarget(), &getTheMips64elTarget()})
380 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createMipsMCCodeEmitterEL);
381}
382