1//===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides Mips specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MipsMCTargetDesc.h"
14#include "MipsAsmBackend.h"
15#include "MipsBaseInfo.h"
16#include "MipsELFStreamer.h"
17#include "MipsInstPrinter.h"
18#include "MipsMCAsmInfo.h"
19#include "MipsTargetStreamer.h"
20#include "TargetInfo/MipsTargetInfo.h"
21#include "llvm/DebugInfo/CodeView/CodeView.h"
22#include "llvm/MC/MCCodeEmitter.h"
23#include "llvm/MC/MCELFStreamer.h"
24#include "llvm/MC/MCInstrAnalysis.h"
25#include "llvm/MC/MCInstrInfo.h"
26#include "llvm/MC/MCObjectWriter.h"
27#include "llvm/MC/MCRegisterInfo.h"
28#include "llvm/MC/MCSubtargetInfo.h"
29#include "llvm/MC/MCSymbol.h"
30#include "llvm/MC/TargetRegistry.h"
31#include "llvm/Support/Compiler.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/FormattedStream.h"
34#include "llvm/TargetParser/Triple.h"
35
36using namespace llvm;
37
38#define GET_INSTRINFO_MC_DESC
39#define ENABLE_INSTR_PREDICATE_VERIFIER
40#include "MipsGenInstrInfo.inc"
41
42#define GET_SUBTARGETINFO_MC_DESC
43#include "MipsGenSubtargetInfo.inc"
44
45#define GET_REGINFO_MC_DESC
46#include "MipsGenRegisterInfo.inc"
47
48#define GET_REGISTER_MATCHER
49#include "MipsGenAsmMatcher.inc"
50
51MCRegister MIPS_MC::matchRegisterName(StringRef Name, const MCRegisterInfo &MRI,
52 unsigned RegClassID, unsigned AltIdx) {
53 MCRegister Reg = MatchRegisterAltName(Name, AltIdx);
54 if (!Reg)
55 Reg = MatchRegisterName(Name);
56 if (!Reg)
57 return MCRegister();
58
59 const MCRegisterClass &RC = MRI.getRegClass(i: RegClassID);
60 // GPR32 and GPR64 share names; select the requested width.
61 if (!RC.contains(Reg)) {
62 if (RegClassID == Mips::GPR32RegClassID &&
63 MRI.getRegClass(i: Mips::GPR64RegClassID).contains(Reg))
64 Reg = MRI.getSubReg(Reg, Idx: Mips::sub_32);
65 else if (RegClassID == Mips::GPR64RegClassID &&
66 MRI.getRegClass(i: Mips::GPR32RegClassID).contains(Reg))
67 Reg = MRI.getMatchingSuperReg(Reg, SubIdx: Mips::sub_32, RC: &RC);
68 }
69 return RC.contains(Reg) ? Reg : MCRegister();
70}
71
72int MIPS_MC::getCPURegisterIndex(StringRef Name, const MCRegisterInfo &MRI,
73 unsigned AltIdx, bool *IsDeprecated) {
74 if (IsDeprecated)
75 *IsDeprecated = false;
76
77 if (MCRegister Reg =
78 matchRegisterName(Name, MRI, RegClassID: Mips::GPR32RegClassID, AltIdx))
79 return MRI.getEncodingValue(Reg);
80
81 static const struct {
82 StringLiteral Name;
83 MCPhysReg Reg;
84 // NoRegAltName applies to all ABIs.
85 unsigned AltIdx;
86 } Aliases[] = {
87 {.Name: "AT", .Reg: Mips::AT, .AltIdx: Mips::NoRegAltName},
88 {.Name: "s8", .Reg: Mips::FP, .AltIdx: Mips::NoRegAltName},
89 {.Name: "kt0", .Reg: Mips::K0, .AltIdx: Mips::NABIRegAltName},
90 {.Name: "kt1", .Reg: Mips::K1, .AltIdx: Mips::NABIRegAltName},
91 };
92 for (const auto &Alias : Aliases)
93 if (Name == Alias.Name &&
94 (Alias.AltIdx == Mips::NoRegAltName || Alias.AltIdx == AltIdx))
95 return MRI.getEncodingValue(Reg: Alias.Reg);
96
97 // GNU also accepts t4-t7 for NABI's t0-t3.
98 if (AltIdx == Mips::NABIRegAltName) {
99 static const struct {
100 StringLiteral Name;
101 MCPhysReg Reg;
102 } Deprecated[] = {
103 {.Name: "t4", .Reg: Mips::T4},
104 {.Name: "t5", .Reg: Mips::T5},
105 {.Name: "t6", .Reg: Mips::T6},
106 {.Name: "t7", .Reg: Mips::T7},
107 };
108 for (const auto &Alias : Deprecated) {
109 if (Name == Alias.Name) {
110 if (IsDeprecated)
111 *IsDeprecated = true;
112 return MRI.getEncodingValue(Reg: Alias.Reg);
113 }
114 }
115 }
116 return -1;
117}
118
119void MIPS_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
120 // Mapping from CodeView to MC register id.
121 static const struct {
122 codeview::RegisterId CVReg;
123 MCPhysReg Reg;
124 } RegMap[] = {
125 {.CVReg: codeview::RegisterId::MIPS_ZERO, .Reg: Mips::ZERO},
126 {.CVReg: codeview::RegisterId::MIPS_AT, .Reg: Mips::AT},
127 {.CVReg: codeview::RegisterId::MIPS_V0, .Reg: Mips::V0},
128 {.CVReg: codeview::RegisterId::MIPS_V1, .Reg: Mips::V1},
129 {.CVReg: codeview::RegisterId::MIPS_A0, .Reg: Mips::A0},
130 {.CVReg: codeview::RegisterId::MIPS_A1, .Reg: Mips::A1},
131 {.CVReg: codeview::RegisterId::MIPS_A2, .Reg: Mips::A2},
132 {.CVReg: codeview::RegisterId::MIPS_A3, .Reg: Mips::A3},
133 {.CVReg: codeview::RegisterId::MIPS_T0, .Reg: Mips::T0},
134 {.CVReg: codeview::RegisterId::MIPS_T1, .Reg: Mips::T1},
135 {.CVReg: codeview::RegisterId::MIPS_T2, .Reg: Mips::T2},
136 {.CVReg: codeview::RegisterId::MIPS_T3, .Reg: Mips::T3},
137 {.CVReg: codeview::RegisterId::MIPS_T4, .Reg: Mips::T4},
138 {.CVReg: codeview::RegisterId::MIPS_T5, .Reg: Mips::T5},
139 {.CVReg: codeview::RegisterId::MIPS_T6, .Reg: Mips::T6},
140 {.CVReg: codeview::RegisterId::MIPS_T7, .Reg: Mips::T7},
141 {.CVReg: codeview::RegisterId::MIPS_S0, .Reg: Mips::S0},
142 {.CVReg: codeview::RegisterId::MIPS_S1, .Reg: Mips::S1},
143 {.CVReg: codeview::RegisterId::MIPS_S2, .Reg: Mips::S2},
144 {.CVReg: codeview::RegisterId::MIPS_S3, .Reg: Mips::S3},
145 {.CVReg: codeview::RegisterId::MIPS_S4, .Reg: Mips::S4},
146 {.CVReg: codeview::RegisterId::MIPS_S5, .Reg: Mips::S5},
147 {.CVReg: codeview::RegisterId::MIPS_S6, .Reg: Mips::S6},
148 {.CVReg: codeview::RegisterId::MIPS_S7, .Reg: Mips::S7},
149 {.CVReg: codeview::RegisterId::MIPS_T8, .Reg: Mips::T8},
150 {.CVReg: codeview::RegisterId::MIPS_T9, .Reg: Mips::T9},
151 {.CVReg: codeview::RegisterId::MIPS_K0, .Reg: Mips::K0},
152 {.CVReg: codeview::RegisterId::MIPS_K1, .Reg: Mips::K1},
153 {.CVReg: codeview::RegisterId::MIPS_GP, .Reg: Mips::GP},
154 {.CVReg: codeview::RegisterId::MIPS_SP, .Reg: Mips::SP},
155 {.CVReg: codeview::RegisterId::MIPS_S8, .Reg: Mips::FP},
156 {.CVReg: codeview::RegisterId::MIPS_RA, .Reg: Mips::RA},
157 {.CVReg: codeview::RegisterId::MIPS_LO, .Reg: Mips::HI0},
158 {.CVReg: codeview::RegisterId::MIPS_HI, .Reg: Mips::LO0},
159 {.CVReg: codeview::RegisterId::MIPS_Fir, .Reg: Mips::FCR0},
160 {.CVReg: codeview::RegisterId::MIPS_Psr, .Reg: Mips::COP012}, // CP0.Status
161 {.CVReg: codeview::RegisterId::MIPS_F0, .Reg: Mips::F0},
162 {.CVReg: codeview::RegisterId::MIPS_F1, .Reg: Mips::F1},
163 {.CVReg: codeview::RegisterId::MIPS_F2, .Reg: Mips::F2},
164 {.CVReg: codeview::RegisterId::MIPS_F3, .Reg: Mips::F3},
165 {.CVReg: codeview::RegisterId::MIPS_F4, .Reg: Mips::F4},
166 {.CVReg: codeview::RegisterId::MIPS_F5, .Reg: Mips::F5},
167 {.CVReg: codeview::RegisterId::MIPS_F6, .Reg: Mips::F6},
168 {.CVReg: codeview::RegisterId::MIPS_F7, .Reg: Mips::F7},
169 {.CVReg: codeview::RegisterId::MIPS_F8, .Reg: Mips::F8},
170 {.CVReg: codeview::RegisterId::MIPS_F9, .Reg: Mips::F9},
171 {.CVReg: codeview::RegisterId::MIPS_F10, .Reg: Mips::F10},
172 {.CVReg: codeview::RegisterId::MIPS_F11, .Reg: Mips::F11},
173 {.CVReg: codeview::RegisterId::MIPS_F12, .Reg: Mips::F12},
174 {.CVReg: codeview::RegisterId::MIPS_F13, .Reg: Mips::F13},
175 {.CVReg: codeview::RegisterId::MIPS_F14, .Reg: Mips::F14},
176 {.CVReg: codeview::RegisterId::MIPS_F15, .Reg: Mips::F15},
177 {.CVReg: codeview::RegisterId::MIPS_F16, .Reg: Mips::F16},
178 {.CVReg: codeview::RegisterId::MIPS_F17, .Reg: Mips::F17},
179 {.CVReg: codeview::RegisterId::MIPS_F18, .Reg: Mips::F18},
180 {.CVReg: codeview::RegisterId::MIPS_F19, .Reg: Mips::F19},
181 {.CVReg: codeview::RegisterId::MIPS_F20, .Reg: Mips::F20},
182 {.CVReg: codeview::RegisterId::MIPS_F21, .Reg: Mips::F21},
183 {.CVReg: codeview::RegisterId::MIPS_F22, .Reg: Mips::F22},
184 {.CVReg: codeview::RegisterId::MIPS_F23, .Reg: Mips::F23},
185 {.CVReg: codeview::RegisterId::MIPS_F24, .Reg: Mips::F24},
186 {.CVReg: codeview::RegisterId::MIPS_F25, .Reg: Mips::F25},
187 {.CVReg: codeview::RegisterId::MIPS_F26, .Reg: Mips::F26},
188 {.CVReg: codeview::RegisterId::MIPS_F27, .Reg: Mips::F27},
189 {.CVReg: codeview::RegisterId::MIPS_F28, .Reg: Mips::F28},
190 {.CVReg: codeview::RegisterId::MIPS_F29, .Reg: Mips::F29},
191 {.CVReg: codeview::RegisterId::MIPS_F30, .Reg: Mips::F30},
192 {.CVReg: codeview::RegisterId::MIPS_F31, .Reg: Mips::F31},
193 {.CVReg: codeview::RegisterId::MIPS_Fsr, .Reg: Mips::FCR31},
194 };
195 for (const auto &I : RegMap)
196 MRI->mapLLVMRegToCVReg(LLVMReg: I.Reg, CVReg: static_cast<int>(I.CVReg));
197}
198
199namespace {
200class MipsWinCOFFTargetStreamer : public MipsTargetStreamer {
201public:
202 MipsWinCOFFTargetStreamer(MCStreamer &S) : MipsTargetStreamer(S) {}
203};
204} // end namespace
205
206/// Select the Mips CPU for the given triple and cpu name.
207StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) {
208 if (CPU.empty() || CPU == "generic") {
209 if (TT.getSubArch() == llvm::Triple::MipsSubArch_r6) {
210 if (TT.isMIPS32())
211 CPU = "mips32r6";
212 else
213 CPU = "mips64r6";
214 } else {
215 if (TT.isMIPS32())
216 CPU = "mips32";
217 else
218 CPU = "mips64";
219 }
220 }
221 return CPU;
222}
223
224static MCInstrInfo *createMipsMCInstrInfo() {
225 MCInstrInfo *X = new MCInstrInfo();
226 InitMipsMCInstrInfo(II: X);
227 return X;
228}
229
230static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
231 MCRegisterInfo *X = new MCRegisterInfo();
232 InitMipsMCRegisterInfo(RI: X, RA: Mips::RA);
233 return X;
234}
235
236static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
237 StringRef CPU, StringRef FS) {
238 CPU = MIPS_MC::selectMipsCPU(TT, CPU);
239 return createMipsMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
240}
241
242static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
243 const Triple &TT,
244 const MCTargetOptions &Options) {
245 MCAsmInfo *MAI;
246
247 if (TT.isOSBinFormatCOFF())
248 MAI = new MipsCOFFMCAsmInfo(Options);
249 else
250 MAI = new MipsELFMCAsmInfo(TT, Options);
251
252 unsigned SP = MRI.getDwarfRegNum(Reg: Mips::SP, isEH: true);
253 MCCFIInstruction Inst = MCCFIInstruction::createDefCfaRegister(L: nullptr, Register: SP);
254 MAI->addInitialFrameState(Inst);
255
256 return MAI;
257}
258
259static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
260 unsigned SyntaxVariant,
261 const MCAsmInfo &MAI,
262 const MCInstrInfo &MII,
263 const MCRegisterInfo &MRI) {
264 return new MipsInstPrinter(MAI, MII, MRI);
265}
266
267static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
268 std::unique_ptr<MCAsmBackend> &&MAB,
269 std::unique_ptr<MCObjectWriter> &&OW,
270 std::unique_ptr<MCCodeEmitter> &&Emitter) {
271 MCStreamer *S;
272 S = createMipsELFStreamer(Context, MAB: std::move(MAB), OW: std::move(OW),
273 Emitter: std::move(Emitter));
274 return S;
275}
276
277static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S,
278 formatted_raw_ostream &OS,
279 MCInstPrinter *InstPrint) {
280 return new MipsTargetAsmStreamer(S, OS);
281}
282
283static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) {
284 return new MipsTargetStreamer(S);
285}
286
287static MCTargetStreamer *
288createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
289 if (STI.getTargetTriple().isOSBinFormatCOFF())
290 return new MipsWinCOFFTargetStreamer(S);
291 return new MipsTargetELFStreamer(S, STI);
292}
293
294namespace {
295
296class MipsMCInstrAnalysis : public MCInstrAnalysis {
297public:
298 MipsMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
299
300 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
301 uint64_t &Target) const override {
302 unsigned NumOps = Inst.getNumOperands();
303 if (NumOps == 0)
304 return false;
305 switch (Info->get(Opcode: Inst.getOpcode()).operands()[NumOps - 1].OperandType) {
306 case MCOI::OPERAND_UNKNOWN:
307 case MCOI::OPERAND_IMMEDIATE: {
308 // j, jal, jalx, jals
309 // Absolute branch within the current 256 MB-aligned region
310 uint64_t Region = Addr & ~uint64_t(0xfffffff);
311 Target = Region + Inst.getOperand(i: NumOps - 1).getImm();
312 return true;
313 }
314 case MCOI::OPERAND_PCREL:
315 // b, beq ...
316 Target = Addr + Inst.getOperand(i: NumOps - 1).getImm();
317 return true;
318 default:
319 return false;
320 }
321 }
322};
323}
324
325static MCInstrAnalysis *createMipsMCInstrAnalysis(const MCInstrInfo *Info) {
326 return new MipsMCInstrAnalysis(Info);
327}
328
329extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTargetMC() {
330 for (Target *T : {&getTheMipsTarget(), &getTheMipselTarget(),
331 &getTheMips64Target(), &getTheMips64elTarget()}) {
332 // Register the MC asm info.
333 RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
334
335 // Register the MC instruction info.
336 TargetRegistry::RegisterMCInstrInfo(T&: *T, Fn: createMipsMCInstrInfo);
337
338 // Register the MC register info.
339 TargetRegistry::RegisterMCRegInfo(T&: *T, Fn: createMipsMCRegisterInfo);
340
341 // Register the elf streamer.
342 TargetRegistry::RegisterELFStreamer(T&: *T, Fn: createMCStreamer);
343
344 // Register the asm target streamer.
345 TargetRegistry::RegisterAsmTargetStreamer(T&: *T, Fn: createMipsAsmTargetStreamer);
346
347 TargetRegistry::RegisterNullTargetStreamer(T&: *T,
348 Fn: createMipsNullTargetStreamer);
349
350 TargetRegistry::RegisterCOFFStreamer(T&: *T, Fn: createMipsWinCOFFStreamer);
351
352 // Register the MC subtarget info.
353 TargetRegistry::RegisterMCSubtargetInfo(T&: *T, Fn: createMipsMCSubtargetInfo);
354
355 // Register the MC instruction analyzer.
356 TargetRegistry::RegisterMCInstrAnalysis(T&: *T, Fn: createMipsMCInstrAnalysis);
357
358 // Register the MCInstPrinter.
359 TargetRegistry::RegisterMCInstPrinter(T&: *T, Fn: createMipsMCInstPrinter);
360
361 TargetRegistry::RegisterObjectTargetStreamer(
362 T&: *T, Fn: createMipsObjectTargetStreamer);
363
364 // Register the asm backend.
365 TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createMipsAsmBackend);
366 }
367
368 // Register the MC Code Emitter
369 for (Target *T : {&getTheMipsTarget(), &getTheMips64Target()})
370 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createMipsMCCodeEmitterEB);
371
372 for (Target *T : {&getTheMipselTarget(), &getTheMips64elTarget()})
373 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createMipsMCCodeEmitterEL);
374}
375