1//===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides Mips specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MipsMCTargetDesc.h"
14#include "MipsAsmBackend.h"
15#include "MipsBaseInfo.h"
16#include "MipsELFStreamer.h"
17#include "MipsInstPrinter.h"
18#include "MipsMCAsmInfo.h"
19#include "MipsTargetStreamer.h"
20#include "TargetInfo/MipsTargetInfo.h"
21#include "llvm/DebugInfo/CodeView/CodeView.h"
22#include "llvm/MC/MCCodeEmitter.h"
23#include "llvm/MC/MCELFStreamer.h"
24#include "llvm/MC/MCInstrAnalysis.h"
25#include "llvm/MC/MCInstrInfo.h"
26#include "llvm/MC/MCObjectWriter.h"
27#include "llvm/MC/MCRegisterInfo.h"
28#include "llvm/MC/MCSubtargetInfo.h"
29#include "llvm/MC/MCSymbol.h"
30#include "llvm/MC/TargetRegistry.h"
31#include "llvm/Support/Compiler.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/FormattedStream.h"
34#include "llvm/TargetParser/Triple.h"
35
36using namespace llvm;
37
38#define GET_INSTRINFO_MC_DESC
39#define ENABLE_INSTR_PREDICATE_VERIFIER
40#include "MipsGenInstrInfo.inc"
41
42#define GET_SUBTARGETINFO_MC_DESC
43#include "MipsGenSubtargetInfo.inc"
44
45#define GET_REGINFO_MC_DESC
46#include "MipsGenRegisterInfo.inc"
47
48void MIPS_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
49 // Mapping from CodeView to MC register id.
50 static const struct {
51 codeview::RegisterId CVReg;
52 MCPhysReg Reg;
53 } RegMap[] = {
54 {.CVReg: codeview::RegisterId::MIPS_ZERO, .Reg: Mips::ZERO},
55 {.CVReg: codeview::RegisterId::MIPS_AT, .Reg: Mips::AT},
56 {.CVReg: codeview::RegisterId::MIPS_V0, .Reg: Mips::V0},
57 {.CVReg: codeview::RegisterId::MIPS_V1, .Reg: Mips::V1},
58 {.CVReg: codeview::RegisterId::MIPS_A0, .Reg: Mips::A0},
59 {.CVReg: codeview::RegisterId::MIPS_A1, .Reg: Mips::A1},
60 {.CVReg: codeview::RegisterId::MIPS_A2, .Reg: Mips::A2},
61 {.CVReg: codeview::RegisterId::MIPS_A3, .Reg: Mips::A3},
62 {.CVReg: codeview::RegisterId::MIPS_T0, .Reg: Mips::T0},
63 {.CVReg: codeview::RegisterId::MIPS_T1, .Reg: Mips::T1},
64 {.CVReg: codeview::RegisterId::MIPS_T2, .Reg: Mips::T2},
65 {.CVReg: codeview::RegisterId::MIPS_T3, .Reg: Mips::T3},
66 {.CVReg: codeview::RegisterId::MIPS_T4, .Reg: Mips::T4},
67 {.CVReg: codeview::RegisterId::MIPS_T5, .Reg: Mips::T5},
68 {.CVReg: codeview::RegisterId::MIPS_T6, .Reg: Mips::T6},
69 {.CVReg: codeview::RegisterId::MIPS_T7, .Reg: Mips::T7},
70 {.CVReg: codeview::RegisterId::MIPS_S0, .Reg: Mips::S0},
71 {.CVReg: codeview::RegisterId::MIPS_S1, .Reg: Mips::S1},
72 {.CVReg: codeview::RegisterId::MIPS_S2, .Reg: Mips::S2},
73 {.CVReg: codeview::RegisterId::MIPS_S3, .Reg: Mips::S3},
74 {.CVReg: codeview::RegisterId::MIPS_S4, .Reg: Mips::S4},
75 {.CVReg: codeview::RegisterId::MIPS_S5, .Reg: Mips::S5},
76 {.CVReg: codeview::RegisterId::MIPS_S6, .Reg: Mips::S6},
77 {.CVReg: codeview::RegisterId::MIPS_S7, .Reg: Mips::S7},
78 {.CVReg: codeview::RegisterId::MIPS_T8, .Reg: Mips::T8},
79 {.CVReg: codeview::RegisterId::MIPS_T9, .Reg: Mips::T9},
80 {.CVReg: codeview::RegisterId::MIPS_K0, .Reg: Mips::K0},
81 {.CVReg: codeview::RegisterId::MIPS_K1, .Reg: Mips::K1},
82 {.CVReg: codeview::RegisterId::MIPS_GP, .Reg: Mips::GP},
83 {.CVReg: codeview::RegisterId::MIPS_SP, .Reg: Mips::SP},
84 {.CVReg: codeview::RegisterId::MIPS_S8, .Reg: Mips::FP},
85 {.CVReg: codeview::RegisterId::MIPS_RA, .Reg: Mips::RA},
86 {.CVReg: codeview::RegisterId::MIPS_LO, .Reg: Mips::HI0},
87 {.CVReg: codeview::RegisterId::MIPS_HI, .Reg: Mips::LO0},
88 {.CVReg: codeview::RegisterId::MIPS_Fir, .Reg: Mips::FCR0},
89 {.CVReg: codeview::RegisterId::MIPS_Psr, .Reg: Mips::COP012}, // CP0.Status
90 {.CVReg: codeview::RegisterId::MIPS_F0, .Reg: Mips::F0},
91 {.CVReg: codeview::RegisterId::MIPS_F1, .Reg: Mips::F1},
92 {.CVReg: codeview::RegisterId::MIPS_F2, .Reg: Mips::F2},
93 {.CVReg: codeview::RegisterId::MIPS_F3, .Reg: Mips::F3},
94 {.CVReg: codeview::RegisterId::MIPS_F4, .Reg: Mips::F4},
95 {.CVReg: codeview::RegisterId::MIPS_F5, .Reg: Mips::F5},
96 {.CVReg: codeview::RegisterId::MIPS_F6, .Reg: Mips::F6},
97 {.CVReg: codeview::RegisterId::MIPS_F7, .Reg: Mips::F7},
98 {.CVReg: codeview::RegisterId::MIPS_F8, .Reg: Mips::F8},
99 {.CVReg: codeview::RegisterId::MIPS_F9, .Reg: Mips::F9},
100 {.CVReg: codeview::RegisterId::MIPS_F10, .Reg: Mips::F10},
101 {.CVReg: codeview::RegisterId::MIPS_F11, .Reg: Mips::F11},
102 {.CVReg: codeview::RegisterId::MIPS_F12, .Reg: Mips::F12},
103 {.CVReg: codeview::RegisterId::MIPS_F13, .Reg: Mips::F13},
104 {.CVReg: codeview::RegisterId::MIPS_F14, .Reg: Mips::F14},
105 {.CVReg: codeview::RegisterId::MIPS_F15, .Reg: Mips::F15},
106 {.CVReg: codeview::RegisterId::MIPS_F16, .Reg: Mips::F16},
107 {.CVReg: codeview::RegisterId::MIPS_F17, .Reg: Mips::F17},
108 {.CVReg: codeview::RegisterId::MIPS_F18, .Reg: Mips::F18},
109 {.CVReg: codeview::RegisterId::MIPS_F19, .Reg: Mips::F19},
110 {.CVReg: codeview::RegisterId::MIPS_F20, .Reg: Mips::F20},
111 {.CVReg: codeview::RegisterId::MIPS_F21, .Reg: Mips::F21},
112 {.CVReg: codeview::RegisterId::MIPS_F22, .Reg: Mips::F22},
113 {.CVReg: codeview::RegisterId::MIPS_F23, .Reg: Mips::F23},
114 {.CVReg: codeview::RegisterId::MIPS_F24, .Reg: Mips::F24},
115 {.CVReg: codeview::RegisterId::MIPS_F25, .Reg: Mips::F25},
116 {.CVReg: codeview::RegisterId::MIPS_F26, .Reg: Mips::F26},
117 {.CVReg: codeview::RegisterId::MIPS_F27, .Reg: Mips::F27},
118 {.CVReg: codeview::RegisterId::MIPS_F28, .Reg: Mips::F28},
119 {.CVReg: codeview::RegisterId::MIPS_F29, .Reg: Mips::F29},
120 {.CVReg: codeview::RegisterId::MIPS_F30, .Reg: Mips::F30},
121 {.CVReg: codeview::RegisterId::MIPS_F31, .Reg: Mips::F31},
122 {.CVReg: codeview::RegisterId::MIPS_Fsr, .Reg: Mips::FCR31},
123 };
124 for (const auto &I : RegMap)
125 MRI->mapLLVMRegToCVReg(LLVMReg: I.Reg, CVReg: static_cast<int>(I.CVReg));
126}
127
128namespace {
129class MipsWinCOFFTargetStreamer : public MipsTargetStreamer {
130public:
131 MipsWinCOFFTargetStreamer(MCStreamer &S) : MipsTargetStreamer(S) {}
132};
133} // end namespace
134
135/// Select the Mips CPU for the given triple and cpu name.
136StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) {
137 if (CPU.empty() || CPU == "generic") {
138 if (TT.getSubArch() == llvm::Triple::MipsSubArch_r6) {
139 if (TT.isMIPS32())
140 CPU = "mips32r6";
141 else
142 CPU = "mips64r6";
143 } else {
144 if (TT.isMIPS32())
145 CPU = "mips32";
146 else
147 CPU = "mips64";
148 }
149 }
150 return CPU;
151}
152
153static MCInstrInfo *createMipsMCInstrInfo() {
154 MCInstrInfo *X = new MCInstrInfo();
155 InitMipsMCInstrInfo(II: X);
156 return X;
157}
158
159static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
160 MCRegisterInfo *X = new MCRegisterInfo();
161 InitMipsMCRegisterInfo(RI: X, RA: Mips::RA);
162 return X;
163}
164
165static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
166 StringRef CPU, StringRef FS) {
167 CPU = MIPS_MC::selectMipsCPU(TT, CPU);
168 return createMipsMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
169}
170
171static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
172 const Triple &TT,
173 const MCTargetOptions &Options) {
174 MCAsmInfo *MAI;
175
176 if (TT.isOSBinFormatCOFF())
177 MAI = new MipsCOFFMCAsmInfo();
178 else
179 MAI = new MipsELFMCAsmInfo(TT, Options);
180
181 unsigned SP = MRI.getDwarfRegNum(Reg: Mips::SP, isEH: true);
182 MCCFIInstruction Inst = MCCFIInstruction::createDefCfaRegister(L: nullptr, Register: SP);
183 MAI->addInitialFrameState(Inst);
184
185 return MAI;
186}
187
188static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
189 unsigned SyntaxVariant,
190 const MCAsmInfo &MAI,
191 const MCInstrInfo &MII,
192 const MCRegisterInfo &MRI) {
193 return new MipsInstPrinter(MAI, MII, MRI);
194}
195
196static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
197 std::unique_ptr<MCAsmBackend> &&MAB,
198 std::unique_ptr<MCObjectWriter> &&OW,
199 std::unique_ptr<MCCodeEmitter> &&Emitter) {
200 MCStreamer *S;
201 S = createMipsELFStreamer(Context, MAB: std::move(MAB), OW: std::move(OW),
202 Emitter: std::move(Emitter));
203 return S;
204}
205
206static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S,
207 formatted_raw_ostream &OS,
208 MCInstPrinter *InstPrint) {
209 return new MipsTargetAsmStreamer(S, OS);
210}
211
212static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) {
213 return new MipsTargetStreamer(S);
214}
215
216static MCTargetStreamer *
217createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
218 if (STI.getTargetTriple().isOSBinFormatCOFF())
219 return new MipsWinCOFFTargetStreamer(S);
220 return new MipsTargetELFStreamer(S, STI);
221}
222
223namespace {
224
225class MipsMCInstrAnalysis : public MCInstrAnalysis {
226public:
227 MipsMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
228
229 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
230 uint64_t &Target) const override {
231 unsigned NumOps = Inst.getNumOperands();
232 if (NumOps == 0)
233 return false;
234 switch (Info->get(Opcode: Inst.getOpcode()).operands()[NumOps - 1].OperandType) {
235 case MCOI::OPERAND_UNKNOWN:
236 case MCOI::OPERAND_IMMEDIATE: {
237 // j, jal, jalx, jals
238 // Absolute branch within the current 256 MB-aligned region
239 uint64_t Region = Addr & ~uint64_t(0xfffffff);
240 Target = Region + Inst.getOperand(i: NumOps - 1).getImm();
241 return true;
242 }
243 case MCOI::OPERAND_PCREL:
244 // b, beq ...
245 Target = Addr + Inst.getOperand(i: NumOps - 1).getImm();
246 return true;
247 default:
248 return false;
249 }
250 }
251};
252}
253
254static MCInstrAnalysis *createMipsMCInstrAnalysis(const MCInstrInfo *Info) {
255 return new MipsMCInstrAnalysis(Info);
256}
257
258extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTargetMC() {
259 for (Target *T : {&getTheMipsTarget(), &getTheMipselTarget(),
260 &getTheMips64Target(), &getTheMips64elTarget()}) {
261 // Register the MC asm info.
262 RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
263
264 // Register the MC instruction info.
265 TargetRegistry::RegisterMCInstrInfo(T&: *T, Fn: createMipsMCInstrInfo);
266
267 // Register the MC register info.
268 TargetRegistry::RegisterMCRegInfo(T&: *T, Fn: createMipsMCRegisterInfo);
269
270 // Register the elf streamer.
271 TargetRegistry::RegisterELFStreamer(T&: *T, Fn: createMCStreamer);
272
273 // Register the asm target streamer.
274 TargetRegistry::RegisterAsmTargetStreamer(T&: *T, Fn: createMipsAsmTargetStreamer);
275
276 TargetRegistry::RegisterNullTargetStreamer(T&: *T,
277 Fn: createMipsNullTargetStreamer);
278
279 TargetRegistry::RegisterCOFFStreamer(T&: *T, Fn: createMipsWinCOFFStreamer);
280
281 // Register the MC subtarget info.
282 TargetRegistry::RegisterMCSubtargetInfo(T&: *T, Fn: createMipsMCSubtargetInfo);
283
284 // Register the MC instruction analyzer.
285 TargetRegistry::RegisterMCInstrAnalysis(T&: *T, Fn: createMipsMCInstrAnalysis);
286
287 // Register the MCInstPrinter.
288 TargetRegistry::RegisterMCInstPrinter(T&: *T, Fn: createMipsMCInstPrinter);
289
290 TargetRegistry::RegisterObjectTargetStreamer(
291 T&: *T, Fn: createMipsObjectTargetStreamer);
292
293 // Register the asm backend.
294 TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createMipsAsmBackend);
295 }
296
297 // Register the MC Code Emitter
298 for (Target *T : {&getTheMipsTarget(), &getTheMips64Target()})
299 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createMipsMCCodeEmitterEB);
300
301 for (Target *T : {&getTheMipselTarget(), &getTheMips64elTarget()})
302 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createMipsMCCodeEmitterEL);
303}
304