1//===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines an instruction selector for the MIPS target.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MipsISelDAGToDAG.h"
14#include "Mips.h"
15#include "MipsMachineFunction.h"
16#include "llvm/CodeGen/MachineConstantPool.h"
17#include "llvm/CodeGen/MachineFrameInfo.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/SelectionDAG.h"
20#include "llvm/CodeGen/SelectionDAGNodes.h"
21#include "llvm/CodeGen/StackProtector.h"
22#include "llvm/IR/Instructions.h"
23#include "llvm/IR/Type.h"
24#include "llvm/Support/Debug.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/KnownBits.h"
27#include "llvm/Support/raw_ostream.h"
28using namespace llvm;
29
30#define DEBUG_TYPE "mips-isel"
31#define PASS_NAME "MIPS DAG->DAG Pattern Instruction Selection"
32
33//===----------------------------------------------------------------------===//
34// Instruction Selector Implementation
35//===----------------------------------------------------------------------===//
36
37//===----------------------------------------------------------------------===//
38// MipsDAGToDAGISel - MIPS specific code to select MIPS machine
39// instructions for SelectionDAG operations.
40//===----------------------------------------------------------------------===//
41
42void MipsDAGToDAGISelLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
43 // There are multiple MipsDAGToDAGISel instances added to the pass pipeline.
44 // We need to preserve StackProtector for the next one.
45 AU.addPreserved<StackProtector>();
46 SelectionDAGISelLegacy::getAnalysisUsage(AU);
47}
48
49bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
50 Subtarget = &MF.getSubtarget<MipsSubtarget>();
51 bool Ret = SelectionDAGISel::runOnMachineFunction(mf&: MF);
52
53 processFunctionAfterISel(MF);
54
55 return Ret;
56}
57
58/// getGlobalBaseReg - Output the instructions required to put the
59/// GOT address into a register.
60SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
61 Register GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg(MF&: *MF);
62 return CurDAG->getRegister(Reg: GlobalBaseReg, VT: getTargetLowering()->getPointerTy(
63 DL: CurDAG->getDataLayout()))
64 .getNode();
65}
66
67/// ComplexPattern used on MipsInstrInfo
68/// Used on Mips Load/Store instructions
69bool MipsDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
70 SDValue &Offset) const {
71 llvm_unreachable("Unimplemented function.");
72 return false;
73}
74
75bool MipsDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
76 SDValue &Offset) const {
77 llvm_unreachable("Unimplemented function.");
78 return false;
79}
80
81bool MipsDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
82 SDValue &Offset) const {
83 llvm_unreachable("Unimplemented function.");
84 return false;
85}
86
87bool MipsDAGToDAGISel::selectIntAddr11MM(SDValue Addr, SDValue &Base,
88 SDValue &Offset) const {
89 llvm_unreachable("Unimplemented function.");
90 return false;
91}
92
93bool MipsDAGToDAGISel::selectIntAddr12MM(SDValue Addr, SDValue &Base,
94 SDValue &Offset) const {
95 llvm_unreachable("Unimplemented function.");
96 return false;
97}
98
99bool MipsDAGToDAGISel::selectIntAddr16MM(SDValue Addr, SDValue &Base,
100 SDValue &Offset) const {
101 llvm_unreachable("Unimplemented function.");
102 return false;
103}
104
105bool MipsDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
106 SDValue &Offset) const {
107 llvm_unreachable("Unimplemented function.");
108 return false;
109}
110
111bool MipsDAGToDAGISel::selectIntAddrSImm10(SDValue Addr, SDValue &Base,
112 SDValue &Offset) const {
113 llvm_unreachable("Unimplemented function.");
114 return false;
115}
116
117bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base,
118 SDValue &Offset) const {
119 llvm_unreachable("Unimplemented function.");
120 return false;
121}
122
123bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base,
124 SDValue &Offset) const {
125 llvm_unreachable("Unimplemented function.");
126 return false;
127}
128
129bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base,
130 SDValue &Offset) const {
131 llvm_unreachable("Unimplemented function.");
132 return false;
133}
134
135bool MipsDAGToDAGISel::selectAddr16(SDValue Addr, SDValue &Base,
136 SDValue &Offset) {
137 llvm_unreachable("Unimplemented function.");
138 return false;
139}
140
141bool MipsDAGToDAGISel::selectAddr16SP(SDValue Addr, SDValue &Base,
142 SDValue &Offset) {
143 llvm_unreachable("Unimplemented function.");
144 return false;
145}
146
147bool MipsDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm,
148 unsigned MinSizeInBits) const {
149 llvm_unreachable("Unimplemented function.");
150 return false;
151}
152
153bool MipsDAGToDAGISel::selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
154 unsigned ImmBitSize) const {
155 llvm_unreachable("Unimplemented function.");
156}
157
158bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
159 llvm_unreachable("Unimplemented function.");
160 return false;
161}
162
163bool MipsDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const {
164 llvm_unreachable("Unimplemented function.");
165 return false;
166}
167
168bool MipsDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
169 llvm_unreachable("Unimplemented function.");
170 return false;
171}
172
173bool MipsDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
174 llvm_unreachable("Unimplemented function.");
175 return false;
176}
177
178bool MipsDAGToDAGISel::selectVSplatImmEq1(SDValue N) const {
179 llvm_unreachable("Unimplemented function.");
180}
181
182/// Convert vector addition with vector subtraction if that allows to encode
183/// constant as an immediate and thus avoid extra 'ldi' instruction.
184/// add X, <-1, -1...> --> sub X, <1, 1...>
185bool MipsDAGToDAGISel::selectVecAddAsVecSubIfProfitable(SDNode *Node) {
186 assert(Node->getOpcode() == ISD::ADD && "Should only get 'add' here.");
187
188 EVT VT = Node->getValueType(ResNo: 0);
189 assert(VT.isVector() && "Should only be called for vectors.");
190
191 SDValue X = Node->getOperand(Num: 0);
192 SDValue C = Node->getOperand(Num: 1);
193
194 auto *BVN = dyn_cast<BuildVectorSDNode>(Val&: C);
195 if (!BVN)
196 return false;
197
198 APInt SplatValue, SplatUndef;
199 unsigned SplatBitSize;
200 bool HasAnyUndefs;
201
202 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
203 MinSplatBits: 8, isBigEndian: !Subtarget->isLittle()))
204 return false;
205
206 auto IsInlineConstant = [](const APInt &Imm) { return Imm.isIntN(N: 5); };
207
208 if (IsInlineConstant(SplatValue))
209 return false; // Can already be encoded as an immediate.
210
211 APInt NegSplatValue = 0 - SplatValue;
212 if (!IsInlineConstant(NegSplatValue))
213 return false; // Even if we negate it it won't help.
214
215 SDLoc DL(Node);
216
217 SDValue NegC = CurDAG->FoldConstantArithmetic(
218 Opcode: ISD::SUB, DL, VT, Ops: {CurDAG->getConstant(Val: 0, DL, VT), C});
219 assert(NegC && "Constant-folding failed!");
220 SDValue NewNode = CurDAG->getNode(Opcode: ISD::SUB, DL, VT, N1: X, N2: NegC);
221
222 ReplaceNode(F: Node, T: NewNode.getNode());
223 SelectCode(N: NewNode.getNode());
224 return true;
225}
226
227void MipsDAGToDAGISel::PreprocessISelDAG() {
228 // The generic DAG combiner folds
229 //
230 // select C, (add $gp, %gp_rel(A)), (add $gp, %gp_rel(B))
231 //
232 // into
233 //
234 // add $gp, (select C, %gp_rel(A), %gp_rel(B)).
235 //
236 // A GP-relative relocation is only selectable as an operand of the add.
237 // Restore the original form before instruction selection so the relocation
238 // is never selected on its own.
239 bool MadeChange = false;
240 for (SDNode &Node : llvm::make_early_inc_range(Range: CurDAG->allnodes())) {
241 if (Node.getOpcode() != ISD::ADD)
242 continue;
243
244 SDValue Base = Node.getOperand(Num: 0);
245 SDValue Sel = Node.getOperand(Num: 1);
246 if (Base.getOpcode() == ISD::SELECT)
247 std::swap(a&: Base, b&: Sel);
248
249 const auto *BaseReg = dyn_cast<RegisterSDNode>(Val&: Base);
250 if (!BaseReg ||
251 (BaseReg->getReg() != Mips::GP && BaseReg->getReg() != Mips::GP_64) ||
252 Sel.getOpcode() != ISD::SELECT)
253 continue;
254
255 SDValue TrueValue = Sel.getOperand(i: 1);
256 SDValue FalseValue = Sel.getOperand(i: 2);
257 if (TrueValue.getOpcode() != MipsISD::GPRel &&
258 FalseValue.getOpcode() != MipsISD::GPRel)
259 continue;
260
261 SDLoc DL(&Node);
262 EVT VT = Node.getValueType(ResNo: 0);
263 SDNodeFlags Flags = Node.getFlags();
264 TrueValue = CurDAG->getNode(Opcode: ISD::ADD, DL, VT, N1: Base, N2: TrueValue, Flags);
265 FalseValue = CurDAG->getNode(Opcode: ISD::ADD, DL, VT, N1: Base, N2: FalseValue, Flags);
266 SDValue NewSel =
267 CurDAG->getSelect(DL, VT, Cond: Sel.getOperand(i: 0), LHS: TrueValue, RHS: FalseValue);
268 CurDAG->ReplaceAllUsesOfValueWith(From: SDValue(&Node, 0), To: NewSel);
269 MadeChange = true;
270 }
271
272 if (MadeChange)
273 CurDAG->RemoveDeadNodes();
274}
275
276/// Select instructions not customized! Used for
277/// expanded, promoted and normal instructions
278void MipsDAGToDAGISel::Select(SDNode *Node) {
279 unsigned Opcode = Node->getOpcode();
280
281 // If we have a custom node, we already have selected!
282 if (Node->isMachineOpcode()) {
283 LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
284 Node->setNodeId(-1);
285 return;
286 }
287
288 // See if subclasses can handle this node.
289 if (trySelect(Node))
290 return;
291
292 switch(Opcode) {
293 default: break;
294
295 case ISD::ADD:
296 if (Node->getSimpleValueType(ResNo: 0).isVector() &&
297 selectVecAddAsVecSubIfProfitable(Node))
298 return;
299 break;
300
301 // Get target GOT address.
302 case ISD::GLOBAL_OFFSET_TABLE:
303 ReplaceNode(F: Node, T: getGlobalBaseReg());
304 return;
305
306#ifndef NDEBUG
307 case ISD::LOAD:
308 case ISD::STORE:
309 assert((Subtarget->systemSupportsUnalignedAccess() ||
310 cast<MemSDNode>(Node)->getAlign() >=
311 cast<MemSDNode>(Node)->getMemoryVT().getStoreSize()) &&
312 "Unexpected unaligned loads/stores.");
313 break;
314#endif
315 }
316
317 // Select the default instruction
318 SelectCode(N: Node);
319}
320
321bool MipsDAGToDAGISel::SelectInlineAsmMemoryOperand(
322 const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
323 std::vector<SDValue> &OutOps) {
324 // All memory constraints can at least accept raw pointers.
325 switch(ConstraintID) {
326 default:
327 llvm_unreachable("Unexpected asm memory constraint");
328 case InlineAsm::ConstraintCode::m:
329 case InlineAsm::ConstraintCode::R:
330 case InlineAsm::ConstraintCode::ZC:
331 OutOps.push_back(x: Op);
332 return false;
333 }
334 return true;
335}
336
337bool MipsDAGToDAGISel::isUnneededShiftMask(SDNode *N,
338 unsigned ShAmtBits) const {
339 assert(N->getOpcode() == ISD::AND && "Unexpected opcode");
340
341 const APInt &RHS = N->getConstantOperandAPInt(Num: 1);
342 if (RHS.countr_one() >= ShAmtBits) {
343 LLVM_DEBUG(
344 dbgs()
345 << DEBUG_TYPE
346 << " Need optimize 'and & shl/srl/sra' and operand value bits is "
347 << RHS.countr_one() << "\n");
348 return true;
349 }
350
351 KnownBits Known = CurDAG->computeKnownBits(Op: N->getOperand(Num: 0));
352 return (Known.Zero | RHS).countr_one() >= ShAmtBits;
353}
354
355char MipsDAGToDAGISelLegacy::ID = 0;
356
357MipsDAGToDAGISelLegacy::MipsDAGToDAGISelLegacy(
358 std::unique_ptr<SelectionDAGISel> S)
359 : SelectionDAGISelLegacy(ID, std::move(S)) {}
360
361INITIALIZE_PASS(MipsDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
362